2014-05-15 19:16:29 +00:00
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[DEVICE]
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Family = M4A5;
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PartType = M4A5-128/64;
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Package = 100TQFP;
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PartNumber = M4A5-128/64-10VC;
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Speed = -10;
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Operating_condition = COM;
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EN_Segment = NO;
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Pin_MC_1to1 = NO;
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Voltage = 5.0;
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[REVISION]
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RCS = "$Revision: 1.2 $";
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Parent = m4a5.lci;
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SDS_file = m4a5.sds;
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Design = 68030_tk.tt4;
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Rev = 0.01;
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DATE = 5/15/14;
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2014-05-15 20:19:03 +00:00
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TIME = 22:17:31;
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2014-05-15 19:16:29 +00:00
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Type = TT2;
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Pre_Fit_Time = 1;
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Source_Format = Pure_VHDL;
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[IGNORE ASSIGNMENTS]
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Pin_Assignments = NO;
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Pin_Keep_Block = NO;
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Pin_Keep_Segment = NO;
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Group_Assignments = NO;
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Macrocell_Assignments = NO;
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Macrocell_Keep_Block = NO;
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Macrocell_Keep_Segment = NO;
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Pin_Reservation = NO;
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Timing_Constraints = NO;
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Block_Reservation = NO;
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Segment_Reservation = NO;
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Ignore_Source_Location = NO;
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Ignore_Source_Optimization = NO;
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Ignore_Source_Timing = NO;
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[CLEAR ASSIGNMENTS]
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Pin_Assignments = NO;
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Pin_Keep_Block = NO;
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Pin_Keep_Segment = NO;
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Group_Assignments = NO;
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Macrocell_Assignments = NO;
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Macrocell_Keep_Block = NO;
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Macrocell_Keep_Segment = NO;
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Pin_Reservation = NO;
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Timing_Constraints = NO;
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Block_Reservation = NO;
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Segment_Reservation = NO;
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Ignore_Source_Location = NO;
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Ignore_Source_Optimization = NO;
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Ignore_Source_Timing = NO;
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[BACKANNOTATE NETLIST]
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Netlist = VHDL;
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Delay_File = SDF;
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Generic_VCC = ;
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Generic_GND = ;
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[BACKANNOTATE ASSIGNMENTS]
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Pin_Assignment = NO;
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Pin_Block = NO;
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Pin_Macrocell_Block = NO;
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Routing = NO;
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[GLOBAL PROJECT OPTIMIZATION]
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Balanced_Partitioning = YES;
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Spread_Placement = YES;
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Max_Pin_Percent = 100;
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Max_Macrocell_Percent = 100;
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Max_Inter_Seg_Percent = 100;
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Max_Seg_In_Percent = 100;
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Max_Blk_In_Percent = 100;
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[FITTER REPORT FORMAT]
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Fitter_Options = YES;
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Pinout_Diagram = NO;
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Pinout_Listing = YES;
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Detailed_Block_Segment_Summary = YES;
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Input_Signal_List = YES;
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Output_Signal_List = YES;
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Bidir_Signal_List = YES;
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Node_Signal_List = YES;
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Signal_Fanout_List = YES;
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Block_Segment_Fanin_List = YES;
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Prefit_Eqn = YES;
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Postfit_Eqn = YES;
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Page_Break = YES;
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[OPTIMIZATION OPTIONS]
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Logic_Reduction = YES;
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Max_PTerm_Split = 16;
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Max_PTerm_Collapse = 16;
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XOR_Synthesis = YES;
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Node_Collapse = Yes;
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DT_Synthesis = Yes;
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[FITTER GLOBAL OPTIONS]
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Run_Time = 0;
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Set_Reset_Dont_Care = NO;
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In_Reg_Optimize = YES;
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Clock_Optimize = NO;
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Conf_Unused_IOs = OUT_LOW;
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[POWER]
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Powerlevel = Low, High;
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Default = High;
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Type = GLB;
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[HARDWARE DEVICE OPTIONS]
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Zero_Hold_Time = Yes;
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Signature_Word = 0;
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Pull_up = Yes;
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Out_Slew_Rate = FAST, SLOW, 0;
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Device_max_fanin = 33;
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Device_max_pterms = 20;
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Usercode_Format = Hex;
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[LOCATION ASSIGNMENT]
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Layer = OFF
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DSACK_1_ = BIDIR,81,7,-;
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DTACK = OUTPUT,30,3,-;
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CLK_EXP = OUTPUT,10,1,-;
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2014-05-15 20:19:03 +00:00
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LDS_000 = OUTPUT,31,3,-;
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2014-05-15 19:16:29 +00:00
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UDS_000 = OUTPUT,32,3,-;
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E = OUTPUT,66,6,-;
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BG_000 = OUTPUT,29,3,-;
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BGACK_030 = OUTPUT,83,7,-;
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FPU_CS = OUTPUT,78,7,-;
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2014-05-15 20:19:03 +00:00
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VMA = OUTPUT,35,3,-;
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2014-05-15 19:16:29 +00:00
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AS_000 = OUTPUT,33,3,-;
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IPL_030_2_ = OUTPUT,9,1,-;
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IPL_030_0_ = OUTPUT,8,1,-;
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IPL_030_1_ = OUTPUT,7,1,-;
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AVEC = OUTPUT,92,0,-;
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DSACK_0_ = OUTPUT,80,7,-;
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CLK_DIV_OUT = OUTPUT,65,6,-;
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AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-;
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CIIN = OUTPUT,47,4,-;
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BERR = OUTPUT,41,4,-;
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AMIGA_BUS_ENABLE = OUTPUT,34,3,-;
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AVEC_EXP = OUTPUT,22,2,-;
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AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-;
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RESET = OUTPUT,3,1,-;
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2014-05-15 20:19:03 +00:00
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inst_CLK_000_D = NODE,*,7,-;
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SM_AMIGA_3_ = NODE,*,6,-;
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cpu_est_1_ = NODE,*,6,-;
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RN_E = NODE,-1,6,-;
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SM_AMIGA_1_ = NODE,*,6,-;
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cpu_est_2_ = NODE,*,6,-;
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cpu_est_0_ = NODE,*,6,-;
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2014-05-15 19:16:29 +00:00
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RN_FPU_CS = NODE,-1,7,-;
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SM_AMIGA_4_ = NODE,*,3,-;
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2014-05-15 20:19:03 +00:00
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inst_VPA_D = NODE,*,0,-;
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2014-05-15 19:16:29 +00:00
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inst_AS_030_000_SYNC = NODE,*,7,-;
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2014-05-15 20:19:03 +00:00
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SM_AMIGA_0_ = NODE,*,6,-;
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2014-05-15 19:16:29 +00:00
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SM_AMIGA_2_ = NODE,*,6,-;
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SM_AMIGA_6_ = NODE,*,3,-;
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2014-05-15 20:19:03 +00:00
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RN_VMA = NODE,-1,3,-;
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2014-05-15 19:16:29 +00:00
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RN_BGACK_030 = NODE,-1,7,-;
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RN_AS_000 = NODE,-1,3,-;
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SM_AMIGA_5_ = NODE,*,3,-;
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SM_AMIGA_7_ = NODE,*,6,-;
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inst_CLK_OUT_PRE = NODE,*,6,-;
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2014-05-15 20:19:03 +00:00
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inst_VPA_SYNC = NODE,*,5,-;
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inst_DTACK_SYNC = NODE,*,0,-;
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2014-05-15 19:16:29 +00:00
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inst_RISING_CLK_AMIGA = NODE,*,7,-;
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2014-05-15 20:19:03 +00:00
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inst_CLK_000_DD = NODE,*,7,-;
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RN_LDS_000 = NODE,-1,3,-;
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2014-05-15 19:16:29 +00:00
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RN_UDS_000 = NODE,-1,3,-;
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RN_BG_000 = NODE,-1,3,-;
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RN_IPL_030_0_ = NODE,-1,1,-;
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RN_IPL_030_1_ = NODE,-1,1,-;
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2014-05-15 20:19:03 +00:00
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RN_DSACK_1_ = NODE,-1,7,-;
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2014-05-15 19:16:29 +00:00
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RN_IPL_030_2_ = NODE,-1,1,-;
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2014-05-15 20:19:03 +00:00
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SM_AMIGA_D_2_ = NODE,*,1,-;
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2014-05-15 19:16:29 +00:00
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SM_AMIGA_D_1_ = NODE,*,1,-;
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SM_AMIGA_D_0_ = NODE,*,1,-;
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CLK_CNT_0_ = NODE,*,6,-;
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2014-05-15 20:19:03 +00:00
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cpu_est_d_2_ = NODE,*,6,-;
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cpu_est_d_1_ = NODE,*,6,-;
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cpu_est_d_3_ = NODE,*,6,-;
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cpu_est_d_0_ = NODE,*,6,-;
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2014-05-15 19:16:29 +00:00
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CLK_OSZI = INPUT,61,-,-;
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