68030tk/Logic/synlog/bus68030_fpga_mapper.srr

Synopsys CPLD Technology Mapper, Version maplat, Build 621R, Built Mar 19 2013
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
Product Version G-2012.09LC-SP1 
@N: MF248 |Running in 64-bit mode.
Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
original code -> new code
   000 -> 00000001
   001 -> 00000010
   010 -> 00000100
   011 -> 00001000
   100 -> 00010000
   101 -> 00100000
   110 -> 01000000
   111 -> 10000000
Encoding state machine cpu_est[0:10] (view:work.BUS68030(behavioral))
original code -> new code
   0000 -> 0000
   0010 -> 0010
   0011 -> 0011
   0100 -> 0100
   0101 -> 0101
   0110 -> 0110
   0111 -> 0111
   1010 -> 1010
   1011 -> 1011
   1100 -> 1100
   1111 -> 1111
---------------------------------------
Resource Usage Report

Simple gate primitives:
DFFRH           44 uses
DFFSH           26 uses
DFF             1 use
BI_DIR          13 uses
IBUF            30 uses
OBUF            16 uses
BUFTH           1 use
AND2            203 uses
INV             161 uses
OR2             21 uses
XOR2            2 uses


@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
G-2012.09LC-SP1 
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Fri Jul 18 14:05:28 2014

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