@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:61:132:75|Pruning bit 12 of CLK_000_N_SYNC(12 downto 0) -- not in use ...
@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:36:102:38|Pruning bits 12 to 10 of CLK_000_P_SYNC(12 downto 0) -- not in use ...
@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:35:136:37|Feedback mux created for signal CLK_030_H -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":137:32:137:34|Trying to extract state machine for register SM_AMIGA