diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index f72124c..8a2bafb 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -126,11 +126,7 @@ signal CLK_OUT_PRE_D: STD_LOGIC := '1'; signal CLK_OUT_INT: STD_LOGIC := '1'; signal CLK_OUT_EXP_INT: STD_LOGIC := '1'; signal CLK_030_H: STD_LOGIC := '1'; -signal CLK_000_D0: STD_LOGIC := '1'; -signal CLK_000_D1: STD_LOGIC := '1'; -signal CLK_000_D2: STD_LOGIC := '1'; -signal CLK_000_D3: STD_LOGIC := '1'; -signal CLK_000_D4: STD_LOGIC := '1'; +signal CLK_000_D: STD_LOGIC_VECTOR ( 7 downto 0 ) := "00000000"; signal CLK_000_P_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000"; signal CLK_000_N_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000"; signal CLK_000_PE: STD_LOGIC := '0'; @@ -169,28 +165,26 @@ begin CLK_OUT_INT <= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool! CLK_OUT_EXP_INT <= CLK_OUT_PRE_50; --delayed Clocks and signals for edge detection - CLK_000_D0 <= CLK_000; - CLK_000_D1 <= CLK_000_D0; - CLK_000_D2 <= CLK_000_D1; - CLK_000_D3 <= CLK_000_D2; - CLK_000_D4 <= CLK_000_D3; + CLK_000_D(0) <= CLK_000; + CLK_000_D(7 downto 1) <= CLK_000_D(6 downto 0); --shift registers for edge detection CLK_000_P_SYNC( 12 downto 1 ) <= CLK_000_P_SYNC( 11 downto 0 ); - CLK_000_P_SYNC(0) <= CLK_000_D0 AND NOT CLK_000_D1; + CLK_000_P_SYNC(0) <= CLK_000_D(0) AND NOT CLK_000_D(1); CLK_000_N_SYNC( 12 downto 1 ) <= CLK_000_N_SYNC( 11 downto 0 ); - CLK_000_N_SYNC(0) <= NOT CLK_000_D0 AND CLK_000_D1; + CLK_000_N_SYNC(0) <= NOT CLK_000_D(0) AND CLK_000_D(1); -- values are determined empiracally for 7.09 MHz Clock -- since the clock is not symmetrically these values differ! CLK_000_PE <= CLK_000_P_SYNC(9); CLK_000_NE <= CLK_000_N_SYNC(11); + --CLK_000_PE <= CLK_000_D(0) AND NOT CLK_000_D(1) AND NOT CLK_000_D(2); + --CLK_000_NE <= NOT CLK_000_D(0) AND CLK_000_D(1) AND CLK_000_D(2); CLK_000_NE_D0 <= CLK_000_NE; -- e-clock is changed on the FALLING edge! if(CLK_000_NE_D0 = '1' ) then - --if(CLK_000_D0='0' AND CLK_000_D1='1') then case (cpu_est) is when E1 => cpu_est <= E2 ; when E2 => cpu_est <= E3 ; @@ -279,7 +273,6 @@ begin elsif ( BGACK_000='1' AND CLK_000_PE='1' AND AS_000 = '1' --the amiga AS can be still active while bgack is deasserted, so wait for this signal too! - --AND CLK_000_D0='1' and CLK_000_D1='0' ) then -- BGACK_000 is high here! BGACK_030_INT_PRE<= '1'; BGACK_030_INT <= BGACK_030_INT_PRE; --hold this signal high until 7m clock goes low @@ -293,8 +286,7 @@ begin BG_000 <= '1'; elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P) and nEXP_SPACE_D0 = '1' and AS_030_D0='1' - and CLK_000_D0='1' - --and CLK_000_D0='1' AND CLK_000_D1='0' + and CLK_000_D(0)='1' ) then --bus granted no local access and no AS_030 running! BG_000 <= '0'; end if; @@ -302,7 +294,6 @@ begin --interrupt buffering to avoid ghost interrupts --if(CLK_000_NE='1')then - --if(CLK_000_D0='0' and CLK_000_D1='1')then IPL_D0<=IPL; if(IPL = IPL_D0)then IPL_030<=IPL; @@ -332,7 +323,6 @@ begin -- VMA generation if(CLK_000_NE='1' AND VPA_D='0' AND cpu_est = E4)then --assert - --if(CLK_000_D0='0' AND CLK_000_D1='1' AND VPA_D='0' AND cpu_est = E4)then --assert VMA_INT <= '0'; elsif(CLK_000_PE='1' AND cpu_est=E1)then --deassert VMA_INT <= '1'; @@ -362,14 +352,13 @@ begin case (SM_AMIGA) is when IDLE_P => --68000:S0 wait for a falling edge RW_000_INT <= '1'; - AMIGA_BUS_ENABLE_INT <= CLK_000_D1; - if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE_D0 ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle! + AMIGA_BUS_ENABLE_INT <= CLK_000_D(1); + if( CLK_000_D(0)='0' and CLK_000_D(1)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE_D0 ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle! SM_AMIGA<=IDLE_N; --go to s1 end if; when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga if(CLK_000_PE='1')then --go to s2 - --if(CLK_000_D0='1')then --go to s2 SM_AMIGA <= AS_SET_P; --as for amiga set! end if; when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here @@ -379,13 +368,11 @@ begin DS_000_ENABLE <= '1'; end if; if(CLK_000_NE='1')then --go to s3 - --if(CLK_000_D0='0')then --go to s3 SM_AMIGA<=AS_SET_N; end if; when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write if(CLK_000_PE='1')then --go to s4 - --if(CLK_000_D0='1')then --go to s4 -- set DS-Enable without respect to rw: this simplifies the life for the syntesizer DS_000_ENABLE <= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late SM_AMIGA <= SAMPLE_DTACK_P; @@ -393,7 +380,6 @@ begin when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA DS_000_ENABLE <= '1'; if( CLK_000_NE_D0='1' and --falling edge - --if( CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge ((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle (VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle )then --go to s5 @@ -402,7 +388,6 @@ begin when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock DS_000_ENABLE <= '1'; if(CLK_000_PE = '1')then --go to s6 - --if(CLK_000_D0='1')then --go to s6 SM_AMIGA<=DATA_FETCH_P; end if; when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus! @@ -411,17 +396,11 @@ begin (CLK_000_N_SYNC(10)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge DSACK1_INT <='0'; end if; - --if( CLK_000_D3 ='1' AND CLK_000_D4 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge - -- DSACK1_INT <='0'; - --end if; if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge - --if( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge - --DSACK1_INT <='0'; SM_AMIGA<=END_CYCLE_N; end if; when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock if(CLK_000_PE='1')then --go to s0 - --if(CLK_000_D0='1')then --go to s0 SM_AMIGA<=IDLE_P; RW_000_INT <= '1'; --AMIGA_BUS_ENABLE_INT <= '1'; @@ -462,7 +441,7 @@ begin if(BGACK_030_INT='0' and AS_000='0')then -- an 68000-memory cycle is three positive edges long! - if(CLK_000_P_SYNC(10)='1')then + if(CLK_000_PE='1')then CYCLE_DMA <= CYCLE_DMA+1; end if; else @@ -609,4 +588,4 @@ begin '0' when DSACK1_INT ='0' else '1'; -end Behavioral; \ No newline at end of file +end Behavioral; diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index 8d21363..46c9ad9 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -351770,3 +351770,3522 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 01/27/16 21:56:36 ########### + +########## Tcl recorder starts at 08/17/16 16:31:07 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 16:31:07 ########### + + +########## Tcl recorder starts at 08/17/16 16:31:10 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 16:31:10 ########### + + +########## Tcl recorder starts at 08/17/16 17:00:46 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:00:46 ########### + + +########## Tcl recorder starts at 08/17/16 17:00:51 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:00:51 ########### + + +########## Tcl recorder starts at 08/17/16 17:03:06 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:03:06 ########### + + +########## Tcl recorder starts at 08/17/16 17:03:09 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:03:09 ########### + + +########## Tcl recorder starts at 08/17/16 17:04:22 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:04:22 ########### + + +########## Tcl recorder starts at 08/17/16 17:05:21 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:05:21 ########### + + +########## Tcl recorder starts at 08/17/16 17:05:34 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:05:34 ########### + + +########## Tcl recorder starts at 08/17/16 17:06:12 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:06:12 ########### + + +########## Tcl recorder starts at 08/17/16 17:06:15 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:06:15 ########### + + +########## Tcl recorder starts at 08/17/16 17:10:03 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:10:03 ########### + + +########## Tcl recorder starts at 08/17/16 17:11:11 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:11:11 ########### + + +########## Tcl recorder starts at 08/17/16 17:11:16 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:11:16 ########### + + +########## Tcl recorder starts at 08/17/16 17:16:18 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:16:18 ########### + + +########## Tcl recorder starts at 08/17/16 17:16:23 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:16:23 ########### + + +########## Tcl recorder starts at 08/17/16 17:17:27 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:17:27 ########### + + +########## Tcl recorder starts at 08/17/16 17:17:48 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:17:48 ########### + + +########## Tcl recorder starts at 08/17/16 17:18:58 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:18:58 ########### + + +########## Tcl recorder starts at 08/17/16 17:19:03 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:19:03 ########### + + +########## Tcl recorder starts at 08/17/16 17:20:44 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:20:44 ########### + + +########## Tcl recorder starts at 08/17/16 17:20:50 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:20:50 ########### + + +########## Tcl recorder starts at 08/17/16 17:21:52 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:21:52 ########### + + +########## Tcl recorder starts at 08/17/16 17:21:53 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:21:53 ########### + + +########## Tcl recorder starts at 08/17/16 17:36:05 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:36:05 ########### + + +########## Tcl recorder starts at 08/17/16 17:36:07 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:36:07 ########### + + +########## Tcl recorder starts at 08/17/16 17:36:29 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:36:29 ########### + + +########## Tcl recorder starts at 08/17/16 17:36:30 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:36:30 ########### + + +########## Tcl recorder starts at 08/17/16 17:36:59 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:36:59 ########### + + +########## Tcl recorder starts at 08/17/16 17:37:02 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:37:02 ########### + + +########## Tcl recorder starts at 08/17/16 17:40:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:40:08 ########### + + +########## Tcl recorder starts at 08/17/16 17:40:09 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:40:09 ########### + + +########## Tcl recorder starts at 08/17/16 17:41:11 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:41:11 ########### + + +########## Tcl recorder starts at 08/17/16 17:41:15 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:41:15 ########### + + +########## Tcl recorder starts at 08/17/16 17:42:36 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:42:36 ########### + + +########## Tcl recorder starts at 08/17/16 17:42:42 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:42:42 ########### + + +########## Tcl recorder starts at 08/17/16 17:44:01 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:44:01 ########### + + +########## Tcl recorder starts at 08/17/16 17:44:07 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:44:07 ########### + + +########## Tcl recorder starts at 08/17/16 17:45:28 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:45:29 ########### + + +########## Tcl recorder starts at 08/17/16 17:45:34 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/17/16 17:45:34 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index 3f7dea8..3c31eee 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,5 +1,5 @@ -#$ TOOL ispLEVER Classic 1.8.00.04.29.14 -#$ DATE Wed Jan 27 21:56:48 2016 +#$ TOOL ispLEVER Classic 2.0.00.17.20.15 +#$ DATE Wed Aug 17 17:45:46 2016 #$ MODULE 68030_tk #$ PINS 75 A_8_ A_7_ SIZE_1_ A_6_ A_5_ A_31_ A_4_ A_3_ IPL_030_2_ A_2_ IPL_030_1_ IPL_2_ \ # IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 \ @@ -37,17 +37,17 @@ # lds_000_int_0_un0_n inst_CLK_OUT_PRE_D sm_amiga_i_3__n N_350_i rw_000_dma_0_un3_n \ # inst_DTACK_D0 cpu_est_i_0__n N_188_0 rw_000_dma_0_un1_n inst_RESET_OUT \ # cpu_est_i_3__n N_187_i rw_000_dma_0_un0_n inst_CLK_OUT_PRE_50 cpu_est_i_2__n \ -# N_185_i a_15__n inst_CLK_000_D1 cpu_est_i_1__n N_182_i inst_CLK_000_D0 VPA_D_i \ -# N_181_i a_14__n inst_CLK_000_PE CLK_000_NE_i CLK_OUT_PRE_D_i CLK_000_P_SYNC_9_ \ +# N_185_i a_15__n CLK_000_D_1_ cpu_est_i_1__n N_182_i CLK_000_D_0_ VPA_D_i N_181_i \ +# a_14__n inst_CLK_000_PE CLK_000_NE_i CLK_OUT_PRE_D_i CLK_000_P_SYNC_9_ \ # sm_amiga_i_1__n N_175_0 a_13__n inst_CLK_000_NE rst_dly_i_2__n N_168_i \ # CLK_000_N_SYNC_11_ CLK_030_i AS_030_000_SYNC_i a_12__n IPL_D0_0_ rst_dly_i_0__n \ -# N_158_i IPL_D0_1_ rst_dly_i_1__n CLK_000_D0_i a_11__n IPL_D0_2_ CLK_000_D1_i N_148_i \ -# inst_CLK_000_NE_D0 DTACK_D0_i N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i \ -# SM_AMIGA_0_ CLK_030_H_i N_144_0 a_9__n inst_AMIGA_BUS_ENABLE_DMA_HIGH \ +# N_158_i IPL_D0_1_ rst_dly_i_1__n clk_000_d_i_0__n a_11__n IPL_D0_2_ clk_000_d_i_1__n \ +# N_148_i inst_CLK_000_NE_D0 DTACK_D0_i N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i \ +# N_344_i SM_AMIGA_0_ CLK_030_H_i N_144_0 a_9__n inst_AMIGA_BUS_ENABLE_DMA_HIGH \ # sm_amiga_i_6__n N_138_0 inst_DSACK1_INTreg sm_amiga_i_2__n a_8__n AS_000_i N_342_i \ # pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n SM_AMIGA_4_ A1_i N_124_0 \ # inst_DS_000_ENABLE a_i_31__n N_341_i a_6__n RST_DLY_0_ a_i_29__n N_119_0 RST_DLY_1_ \ -# a_i_30__n N_340_i a_5__n RST_DLY_2_ a_i_27__n N_361_i pos_clk_un8_bg_030_n a_i_28__n \ +# a_i_30__n N_340_i a_5__n RST_DLY_2_ a_i_27__n N_361_i pos_clk_un9_bg_030_n a_i_28__n \ # cpu_est_2_0_2__n a_4__n CLK_000_P_SYNC_0_ a_i_25__n N_338_i CLK_000_P_SYNC_1_ \ # a_i_26__n N_339_i a_3__n CLK_000_P_SYNC_2_ N_213_i cpu_est_2_0_1__n \ # CLK_000_P_SYNC_3_ N_214_i N_332_i a_2__n CLK_000_P_SYNC_4_ N_215_i N_336_i \ @@ -69,7 +69,7 @@ # N_17_i N_42_0 a_c_23__n N_19_i N_40_0 SM_AMIGA_i_7_ a_c_24__n N_20_i N_123 N_39_0 \ # cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i G_134 \ # N_37_0 G_135 a_c_27__n N_25_i G_136 N_34_0 N_217 a_c_28__n N_26_i N_33_0 N_61 a_c_29__n \ -# BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un8_bg_030_0_n N_80 \ +# BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 \ # N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \ # pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c N_351_2 N_124 N_168_i_1 N_138 \ # nEXP_SPACE_c N_192_0_1 N_144 N_192_0_2 N_158 BERR_c N_137_i_1 N_168 N_137_i_2 N_175 \ @@ -94,7 +94,7 @@ # as_030_000_sync_0_un3_n N_347 N_272_i as_030_000_sync_0_un1_n N_350 N_271_i \ # as_030_000_sync_0_un0_n N_351 N_279_0 ds_000_enable_0_un3_n N_353 N_280_0 \ # ds_000_enable_0_un1_n N_361 N_281_0 ds_000_enable_0_un0_n \ -# pos_clk_un24_bgack_030_int_i_i_a4_i_x2 N_298_i as_000_int_0_un3_n \ +# pos_clk_un23_bgack_030_int_i_i_a4_i_x2 N_298_i as_000_int_0_un3_n \ # pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_size_dma_6_0_0__n as_000_int_0_un1_n \ # cpu_est_0_0_x2_0_ N_299_i as_000_int_0_un0_n pos_clk_CYCLE_DMA_5_1_i_x2 \ # pos_clk_size_dma_6_0_1__n dsack1_int_0_un3_n un22_berr_1 un1_as_000_i \ @@ -164,14 +164,14 @@ sm_amiga_i_3__n.BLIF N_350_i.BLIF rw_000_dma_0_un3_n.BLIF inst_DTACK_D0.BLIF \ cpu_est_i_0__n.BLIF N_188_0.BLIF rw_000_dma_0_un1_n.BLIF inst_RESET_OUT.BLIF \ cpu_est_i_3__n.BLIF N_187_i.BLIF rw_000_dma_0_un0_n.BLIF \ inst_CLK_OUT_PRE_50.BLIF cpu_est_i_2__n.BLIF N_185_i.BLIF a_15__n.BLIF \ -inst_CLK_000_D1.BLIF cpu_est_i_1__n.BLIF N_182_i.BLIF inst_CLK_000_D0.BLIF \ +CLK_000_D_1_.BLIF cpu_est_i_1__n.BLIF N_182_i.BLIF CLK_000_D_0_.BLIF \ VPA_D_i.BLIF N_181_i.BLIF a_14__n.BLIF inst_CLK_000_PE.BLIF CLK_000_NE_i.BLIF \ CLK_OUT_PRE_D_i.BLIF CLK_000_P_SYNC_9_.BLIF sm_amiga_i_1__n.BLIF N_175_0.BLIF \ a_13__n.BLIF inst_CLK_000_NE.BLIF rst_dly_i_2__n.BLIF N_168_i.BLIF \ CLK_000_N_SYNC_11_.BLIF CLK_030_i.BLIF AS_030_000_SYNC_i.BLIF a_12__n.BLIF \ IPL_D0_0_.BLIF rst_dly_i_0__n.BLIF N_158_i.BLIF IPL_D0_1_.BLIF \ -rst_dly_i_1__n.BLIF CLK_000_D0_i.BLIF a_11__n.BLIF IPL_D0_2_.BLIF \ -CLK_000_D1_i.BLIF N_148_i.BLIF inst_CLK_000_NE_D0.BLIF DTACK_D0_i.BLIF \ +rst_dly_i_1__n.BLIF clk_000_d_i_0__n.BLIF a_11__n.BLIF IPL_D0_2_.BLIF \ +clk_000_d_i_1__n.BLIF N_148_i.BLIF inst_CLK_000_NE_D0.BLIF DTACK_D0_i.BLIF \ N_345_i.BLIF a_10__n.BLIF pos_clk_un6_bg_030_n.BLIF RW_000_i.BLIF N_344_i.BLIF \ SM_AMIGA_0_.BLIF CLK_030_H_i.BLIF N_144_0.BLIF a_9__n.BLIF \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF sm_amiga_i_6__n.BLIF N_138_0.BLIF \ @@ -180,7 +180,7 @@ N_342_i.BLIF pos_clk_ipl_n.BLIF sm_amiga_i_0__n.BLIF N_343_i.BLIF a_7__n.BLIF \ SM_AMIGA_4_.BLIF A1_i.BLIF N_124_0.BLIF inst_DS_000_ENABLE.BLIF a_i_31__n.BLIF \ N_341_i.BLIF a_6__n.BLIF RST_DLY_0_.BLIF a_i_29__n.BLIF N_119_0.BLIF \ RST_DLY_1_.BLIF a_i_30__n.BLIF N_340_i.BLIF a_5__n.BLIF RST_DLY_2_.BLIF \ -a_i_27__n.BLIF N_361_i.BLIF pos_clk_un8_bg_030_n.BLIF a_i_28__n.BLIF \ +a_i_27__n.BLIF N_361_i.BLIF pos_clk_un9_bg_030_n.BLIF a_i_28__n.BLIF \ cpu_est_2_0_2__n.BLIF a_4__n.BLIF CLK_000_P_SYNC_0_.BLIF a_i_25__n.BLIF \ N_338_i.BLIF CLK_000_P_SYNC_1_.BLIF a_i_26__n.BLIF N_339_i.BLIF a_3__n.BLIF \ CLK_000_P_SYNC_2_.BLIF N_213_i.BLIF cpu_est_2_0_1__n.BLIF \ @@ -216,7 +216,7 @@ cpu_est_2_1__n.BLIF a_c_25__n.BLIF N_21_i.BLIF cpu_est_2_2__n.BLIF N_38_0.BLIF \ N_209.BLIF a_c_26__n.BLIF N_22_i.BLIF G_134.BLIF N_37_0.BLIF G_135.BLIF \ a_c_27__n.BLIF N_25_i.BLIF G_136.BLIF N_34_0.BLIF N_217.BLIF a_c_28__n.BLIF \ N_26_i.BLIF N_33_0.BLIF N_61.BLIF a_c_29__n.BLIF BG_030_c_i.BLIF N_127.BLIF \ -pos_clk_un6_bg_030_i_n.BLIF a_c_30__n.BLIF pos_clk_un8_bg_030_0_n.BLIF \ +pos_clk_un6_bg_030_i_n.BLIF a_c_30__n.BLIF pos_clk_un9_bg_030_0_n.BLIF \ N_80.BLIF N_289_0_1.BLIF a_c_31__n.BLIF un1_SM_AMIGA_5_i_1.BLIF N_90.BLIF \ un1_SM_AMIGA_5_i_2.BLIF N_96.BLIF A0_c.BLIF pos_clk_un8_sm_amiga_i_1_n.BLIF \ N_99.BLIF N_351_1.BLIF N_119.BLIF A1_c.BLIF N_351_2.BLIF N_124.BLIF \ @@ -259,7 +259,7 @@ as_030_000_sync_0_un1_n.BLIF N_350.BLIF N_271_i.BLIF \ as_030_000_sync_0_un0_n.BLIF N_351.BLIF N_279_0.BLIF \ ds_000_enable_0_un3_n.BLIF N_353.BLIF N_280_0.BLIF ds_000_enable_0_un1_n.BLIF \ N_361.BLIF N_281_0.BLIF ds_000_enable_0_un0_n.BLIF \ -pos_clk_un24_bgack_030_int_i_i_a4_i_x2.BLIF N_298_i.BLIF \ +pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_298_i.BLIF \ as_000_int_0_un3_n.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF \ pos_clk_size_dma_6_0_0__n.BLIF as_000_int_0_un1_n.BLIF cpu_est_0_0_x2_0_.BLIF \ N_299_i.BLIF as_000_int_0_un0_n.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF \ @@ -286,18 +286,17 @@ UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_5_.D SM_AMIGA_5_.C \ -SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D \ -SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \ -IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \ -IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D \ -IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C \ -SM_AMIGA_6_.D SM_AMIGA_6_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C \ -CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D \ -CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \ -CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \ -cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \ -cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ +SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D \ +SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D \ +IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ +IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ +IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_5_.D SM_AMIGA_5_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \ +CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ +CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ +SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \ +cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C \ CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D \ CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \ CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D \ @@ -306,33 +305,34 @@ CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D \ CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C \ CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \ CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \ -CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D \ -RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \ +CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \ +CLK_000_N_SYNC_9_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ +CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \ +CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \ CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C \ CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D \ -CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_DMA.D \ -inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ -inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \ -inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C \ -inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C \ -inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ -BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ +CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_INT.D \ +inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \ +inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \ +inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ +inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D \ +inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ +BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \ inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \ inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \ -inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D \ -inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ +inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C \ +inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D \ +inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ -inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C \ -inst_CLK_000_NE.D inst_CLK_000_NE.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 \ -LDS_000 A0 BERR RW SIZE_0_ N_280 N_210_0 cpu_est_0_1__un0_n N_279 N_289_0 \ -cpu_est_0_2__un3_n N_271 N_218_0 cpu_est_0_2__un1_n N_272 cpu_est_0_2__un0_n \ -N_276 N_242_i cpu_est_0_3__un3_n DS_000_ENABLE_1_sqmuxa_1 N_246_i \ -cpu_est_0_3__un1_n N_4 N_240_i cpu_est_0_3__un0_n vcc_n_n N_5 N_241_i \ +inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C \ +inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 RW_000 \ +UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_280 N_210_0 cpu_est_0_1__un0_n N_279 \ +N_289_0 cpu_est_0_2__un3_n N_271 N_218_0 cpu_est_0_2__un1_n N_272 \ +cpu_est_0_2__un0_n N_276 N_242_i cpu_est_0_3__un3_n DS_000_ENABLE_1_sqmuxa_1 \ +N_246_i cpu_est_0_3__un1_n N_4 N_240_i cpu_est_0_3__un0_n vcc_n_n N_5 N_241_i \ ipl_030_0_0__un3_n N_7 ipl_030_0_0__un1_n gnd_n_n N_10 N_266_i \ ipl_030_0_0__un0_n un1_amiga_bus_enable_low N_18 N_267_i ipl_030_0_1__un3_n \ un3_size N_24 N_254_i ipl_030_0_1__un1_n un4_size N_6 N_317_i \ @@ -358,20 +358,20 @@ N_188_0 rw_000_dma_0_un1_n cpu_est_i_3__n N_187_i rw_000_dma_0_un0_n \ cpu_est_i_2__n N_185_i a_15__n cpu_est_i_1__n N_182_i VPA_D_i N_181_i a_14__n \ CLK_000_NE_i CLK_OUT_PRE_D_i sm_amiga_i_1__n N_175_0 a_13__n rst_dly_i_2__n \ N_168_i CLK_030_i AS_030_000_SYNC_i a_12__n rst_dly_i_0__n N_158_i \ -rst_dly_i_1__n CLK_000_D0_i a_11__n CLK_000_D1_i N_148_i DTACK_D0_i N_345_i \ -a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i CLK_030_H_i N_144_0 a_9__n \ -sm_amiga_i_6__n N_138_0 sm_amiga_i_2__n a_8__n AS_000_i N_342_i pos_clk_ipl_n \ -sm_amiga_i_0__n N_343_i a_7__n A1_i N_124_0 a_i_31__n N_341_i a_6__n a_i_29__n \ -N_119_0 a_i_30__n N_340_i a_5__n a_i_27__n N_361_i pos_clk_un8_bg_030_n \ -a_i_28__n cpu_est_2_0_2__n a_4__n a_i_25__n N_338_i a_i_26__n N_339_i a_3__n \ -N_213_i cpu_est_2_0_1__n N_214_i N_332_i a_2__n N_215_i N_336_i \ -pos_clk_un7_clk_000_pe_0_n N_275_i N_99_0 un6_ds_030_i N_331_i DS_000_DMA_i \ -N_96_0 un4_as_000_i N_330_i AS_000_INT_i N_90_0 un4_lds_000_i N_328_i \ -un4_uds_000_i AS_030_c N_80_0 N_325_i AS_000_c N_326_i N_258_0 RW_000_c \ -N_217_i N_321_i N_322_i UDS_000_c N_320_i pos_clk_un7_clk_000_pe_n LDS_000_c \ -un5_ciin_i pos_clk_a0_dma_3_n size_c_0__n N_61_0 N_310_i size_c_1__n N_305_i \ -N_307_i N_3 N_303_i N_8 N_304_i N_283_0 N_301_i N_300_i N_123_0 N_17 N_278_i \ -N_19 N_297_i N_20 AMIGA_BUS_DATA_DIR_c_0 N_21 N_277_i N_22 N_25 N_26 \ +rst_dly_i_1__n clk_000_d_i_0__n a_11__n clk_000_d_i_1__n N_148_i DTACK_D0_i \ +N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i CLK_030_H_i N_144_0 \ +a_9__n sm_amiga_i_6__n N_138_0 sm_amiga_i_2__n a_8__n AS_000_i N_342_i \ +pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n A1_i N_124_0 a_i_31__n N_341_i \ +a_6__n a_i_29__n N_119_0 a_i_30__n N_340_i a_5__n a_i_27__n N_361_i \ +pos_clk_un9_bg_030_n a_i_28__n cpu_est_2_0_2__n a_4__n a_i_25__n N_338_i \ +a_i_26__n N_339_i a_3__n N_213_i cpu_est_2_0_1__n N_214_i N_332_i a_2__n \ +N_215_i N_336_i pos_clk_un7_clk_000_pe_0_n N_275_i N_99_0 un6_ds_030_i N_331_i \ +DS_000_DMA_i N_96_0 un4_as_000_i N_330_i AS_000_INT_i N_90_0 un4_lds_000_i \ +N_328_i un4_uds_000_i AS_030_c N_80_0 N_325_i AS_000_c N_326_i N_258_0 \ +RW_000_c N_217_i N_321_i N_322_i UDS_000_c N_320_i pos_clk_un7_clk_000_pe_n \ +LDS_000_c un5_ciin_i pos_clk_a0_dma_3_n size_c_0__n N_61_0 N_310_i size_c_1__n \ +N_305_i N_307_i N_3 N_303_i N_8 N_304_i N_283_0 N_301_i N_300_i N_123_0 N_17 \ +N_278_i N_19 N_297_i N_20 AMIGA_BUS_DATA_DIR_c_0 N_21 N_277_i N_22 N_25 N_26 \ pos_clk_un8_sm_amiga_i_n N_27 A0_c_i N_28 size_c_i_1__n N_29 N_29_i N_32_0 \ N_28_i N_31_0 N_27_i N_30_0 ipl_c_i_2__n N_53_0 ipl_c_i_1__n N_52_0 a_c_16__n \ ipl_c_i_0__n N_51_0 a_c_17__n DTACK_c_i N_56_0 a_c_18__n VPA_c_i N_55_0 \ @@ -379,7 +379,7 @@ a_c_19__n nEXP_SPACE_c_i N_54_0 a_c_20__n N_3_i N_49_0 a_c_21__n N_8_i N_45_0 \ a_c_22__n N_17_i N_42_0 a_c_23__n N_19_i N_40_0 a_c_24__n N_20_i N_123 N_39_0 \ cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i \ N_37_0 a_c_27__n N_25_i N_34_0 N_217 a_c_28__n N_26_i N_33_0 N_61 a_c_29__n \ -BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un8_bg_030_0_n N_80 \ +BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 \ N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \ pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c N_351_2 N_124 N_168_i_1 \ N_138 nEXP_SPACE_c N_192_0_1 N_144 N_192_0_2 N_158 BERR_c N_137_i_1 N_168 \ @@ -423,10 +423,8 @@ pos_clk_size_dma_6_0__n N_207_0 sm_amiga_srsts_i_0_m2_5__un0_n N_298 N_354_i \ cpu_est_0_1__un3_n N_281 N_208_0 cpu_est_0_1__un1_n AS_030.OE AS_000.OE \ RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE \ DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_134 G_135 G_136 \ -pos_clk_un24_bgack_030_int_i_i_a4_i_x2 pos_clk_CYCLE_DMA_5_0_i_x2 \ +pos_clk_un23_bgack_030_int_i_i_a4_i_x2 pos_clk_CYCLE_DMA_5_0_i_x2 \ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 -.names N_141_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D -11 1 .names N_139_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D 11 1 .names N_137_i_1.BLIF N_137_i_2.BLIF SM_AMIGA_3_.D @@ -453,6 +451,8 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 11 1 .names N_258_0.BLIF SM_AMIGA_6_.D 0 1 +.names N_141_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D +11 1 .names N_282_i_1.BLIF N_210_0.BLIF CYCLE_DMA_0_.D 11 1 .names N_134_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF CYCLE_DMA_1_.D @@ -476,14 +476,10 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 11 1 .names N_259_i_1.BLIF N_259_i_2.BLIF RST_DLY_2_.D 11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF CLK_000_P_SYNC_0_.D 11 1 .names N_261_i_1.BLIF N_322_i.BLIF RST_DLY_0_.D 11 1 -.names N_45_0.BLIF inst_AS_000_DMA.D -0 1 -.names N_46_0.BLIF inst_AS_030_000_SYNC.D -0 1 .names N_47_0.BLIF inst_AS_000_INT.D 0 1 .names N_48_0.BLIF inst_DSACK1_INTreg.D @@ -524,6 +520,10 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 0 1 .names N_43_0.BLIF inst_BGACK_030_INTreg.D 0 1 +.names N_45_0.BLIF inst_AS_000_DMA.D +0 1 +.names N_46_0.BLIF inst_AS_030_000_SYNC.D +0 1 .names N_210_0.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D @@ -726,13 +726,13 @@ amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n 0 1 .names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_212_0 11 1 -.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n 0 1 .names inst_CLK_000_PE.BLIF CLK_000_PE_i 0 1 .names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_211_0 11 1 -.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n 11 1 .names a_c_16__n.BLIF a_i_16__n 0 1 @@ -846,17 +846,17 @@ amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n 11 1 .names RST_DLY_1_.BLIF rst_dly_i_1__n 0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n 0 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n 0 1 -.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_148_i +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_148_i 11 1 .names inst_DTACK_D0.BLIF DTACK_D0_i 0 1 .names N_345.BLIF N_345_i 0 1 -.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n +.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n 11 1 .names RW_000_c.BLIF RW_000_i 0 1 @@ -902,7 +902,7 @@ amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n 0 1 .names N_361.BLIF N_361_i 0 1 -.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n 0 1 .names a_c_28__n.BLIF a_i_28__n 0 1 @@ -1140,7 +1140,7 @@ pos_clk_un8_sm_amiga_i_n 11 1 .names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n 0 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n 11 1 .names N_80_0.BLIF N_80 0 1 @@ -1174,7 +1174,7 @@ pos_clk_un8_sm_amiga_i_n 11 1 .names N_144_0.BLIF N_144 0 1 -.names pos_clk_un24_bgack_030_int_i_i_a4_i_x2.BLIF N_345_i.BLIF N_192_0_2 +.names pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_345_i.BLIF N_192_0_2 11 1 .names N_158_i.BLIF N_158 0 1 @@ -1663,7 +1663,7 @@ sm_amiga_srsts_i_0_m2_5__un0_n 11 0 00 0 .names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ -pos_clk_un24_bgack_030_int_i_i_a4_i_x2 +pos_clk_un23_bgack_030_int_i_i_a4_i_x2 01 1 10 1 11 0 @@ -1740,9 +1740,6 @@ pos_clk_un24_bgack_030_int_i_i_a4_i_x2 .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -1782,10 +1779,7 @@ pos_clk_un24_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 0 0 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 0 0 .names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D @@ -1911,12 +1905,30 @@ pos_clk_un24_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C 1 1 0 0 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF RST_DLY_1_.C 1 1 0 0 .names CLK_OSZI_c.BLIF RST_DLY_2_.C 1 1 0 0 +.names CLK_000.BLIF CLK_000_D_0_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C +1 1 +0 0 +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_1_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C 1 1 0 0 @@ -1947,12 +1959,6 @@ pos_clk_un24_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF RST_DLY_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_AS_000_INT.C 1 1 0 0 @@ -2013,18 +2019,15 @@ pos_clk_un24_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C -1 1 -0 0 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C -1 1 -0 0 .names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D 1 1 0 0 @@ -2043,12 +2046,6 @@ pos_clk_un24_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 0 0 -.names CLK_000.BLIF inst_CLK_000_D0.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C -1 1 -0 0 .names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D 1 1 0 0 @@ -2061,6 +2058,9 @@ pos_clk_un24_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF inst_CLK_000_NE.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +1 1 +0 0 .names un3_size.BLIF SIZE_1_ 1 1 0 0 diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index 8b3764b..a115e41 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,5 +1,5 @@ -#$ TOOL ispLEVER Classic 1.8.00.04.29.14 -#$ DATE Wed Jan 27 21:56:48 2016 +#$ TOOL ispLEVER Classic 2.0.00.17.20.15 +#$ DATE Wed Aug 17 17:45:46 2016 #$ MODULE 68030_tk #$ PINS 61 SIZE_1_ A_31_ IPL_030_2_ IPL_030_1_ IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ \ # AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 nEXP_SPACE BERR BG_030 BG_000 \ @@ -12,7 +12,7 @@ # inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D \ # inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ \ # inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 \ -# inst_RESET_OUT inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE \ +# inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE \ # CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ \ # inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg \ # SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ \ @@ -37,8 +37,8 @@ inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \ inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF inst_VPA_D.BLIF inst_UDS_000_INT.BLIF \ inst_LDS_000_INT.BLIF inst_CLK_OUT_PRE_D.BLIF inst_DTACK_D0.BLIF \ -inst_RESET_OUT.BLIF inst_CLK_OUT_PRE_50.BLIF inst_CLK_000_D1.BLIF \ -inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF CLK_000_P_SYNC_9_.BLIF \ +inst_RESET_OUT.BLIF inst_CLK_OUT_PRE_50.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF inst_CLK_000_PE.BLIF CLK_000_P_SYNC_9_.BLIF \ inst_CLK_000_NE.BLIF CLK_000_N_SYNC_11_.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF \ IPL_D0_2_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_DSACK1_INTreg.BLIF SM_AMIGA_4_.BLIF \ @@ -58,63 +58,52 @@ RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_5_.D SM_AMIGA_5_.C \ -SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C \ -SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D \ -IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ -IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ -IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ -CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \ -CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D \ -CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C \ -SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D \ -cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C \ -CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ -CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \ -CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \ -CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C \ -CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D \ -CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C \ -CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D \ -CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C \ -CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D \ -CLK_000_N_SYNC_8_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ +SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \ +IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \ +IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \ +SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \ +SM_AMIGA_5_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D \ +CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \ +CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \ +cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \ +cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C \ +CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D \ +CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \ +CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D \ +CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C \ +CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D \ +CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C \ +CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \ +CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \ +CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \ +CLK_000_N_SYNC_9_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ +CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \ CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \ CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C \ CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D \ -CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_DMA.D \ +CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_INT.D \ +inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \ +inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \ +inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ +inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C \ +inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ +inst_VMA_INTreg.D inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ +inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ +inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ +inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \ inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ -inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \ -inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C \ -inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.D \ -inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ -BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ -inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \ -inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \ -inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \ -inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D \ -inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ -inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ -inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C \ -inst_CLK_000_NE.D inst_CLK_000_NE.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 \ -LDS_000 A0 BERR RW SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE \ -LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE \ -RESET.OE CIIN.OE inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 \ -SM_AMIGA_3_.D.X2 -.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \ -SM_AMIGA_6_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D -101-1- 1 -11-0-1 1 -11--11 1 ----10- 0 --00--- 0 --0--0- 0 --1---0 0 -0----- 0 +inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.D \ +inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \ +CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_PE.D inst_CLK_000_PE.C \ +inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D \ +inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 LDS_000 A0 BERR RW \ +SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ +SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE \ +inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 .names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \ SM_AMIGA_4_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D 1-0-11 1 @@ -281,8 +270,8 @@ SM_AMIGA_i_7_.D 0------------------- 0 -------------1-----0 0 .names RST.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \ -inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF \ -SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D 11010--0- 1 1----01-1 1 1-----10- 1 @@ -294,6 +283,16 @@ SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D ------01- 0 0-------- 0 -------10 0 +.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \ +SM_AMIGA_6_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D +101-1- 1 +11-0-1 1 +11--11 1 +---10- 0 +-00--- 0 +-0--0- 0 +-1---0 0 +0----- 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF \ inst_CLK_000_PE.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D 10100 1 @@ -379,7 +378,7 @@ RST_DLY_2_.BLIF RST_DLY_2_.D ---00 0 --0-0 0 -0--0 0 -.names inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF CLK_000_P_SYNC_0_.D +.names CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_P_SYNC_0_.D 01 1 1- 0 -0 0 @@ -392,43 +391,6 @@ RST_DLY_2_.BLIF RST_DLY_0_.D -00-- 0 -11-0 0 0---- 0 -.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ -CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ -LDS_000.PIN.BLIF inst_AS_000_DMA.D -----00--- 1 -----11--- 1 -0--1----- 1 -------1-- 1 ---1------ 1 --0------- 1 --------11 1 --1001000- 0 -110-1000- 0 --1000100- 0 -110-0100- 0 --100100-0 0 -110-100-0 0 --100010-0 0 -110-010-0 0 -.names FC_1_.BLIF RST.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \ -FC_0_.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_030_D0.BLIF \ -inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \ -SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D -1-00101---1--- 1 -----------1-1- 1 -----------10-- 1 ----------01--- 1 --------0--1--- 1 ---------1----- 1 --0------------ 1 --------------0 1 --1----0101-101 0 --1---1-101-101 0 --1--0--101-101 0 --1-1---101-101 0 --11----101-101 0 -01-----101-101 0 --1------0-0--1 0 .names RST.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF \ BERR.PIN.BLIF inst_AS_000_INT.D -10-- 1 @@ -533,7 +495,7 @@ SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D --1-1------ 0 0---------- 0 .names BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF \ -inst_CLK_000_D0.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D +CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D ----01 1 ---0-1 1 --0--1 1 @@ -625,6 +587,43 @@ AS_000.PIN.BLIF inst_BGACK_030_INTreg.D -100- 0 -10-0 0 01--- 0 +.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ +CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ +LDS_000.PIN.BLIF inst_AS_000_DMA.D +----00--- 1 +----11--- 1 +0--1----- 1 +------1-- 1 +--1------ 1 +-0------- 1 +-------11 1 +-1001000- 0 +110-1000- 0 +-1000100- 0 +110-0100- 0 +-100100-0 0 +110-100-0 0 +-100010-0 0 +110-010-0 0 +.names FC_1_.BLIF RST.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \ +FC_0_.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_030_D0.BLIF \ +inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \ +SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D +1-00101---1--- 1 +----------1-1- 1 +----------10-- 1 +---------01--- 1 +-------0--1--- 1 +--------1----- 1 +-0------------ 1 +-------------0 1 +-1----0101-101 0 +-1---1-101-101 0 +-1--0--101-101 0 +-1-1---101-101 0 +-11----101-101 0 +01-----101-101 0 +-1------0-0--1 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D 0- 1 -1 1 @@ -633,7 +632,7 @@ AS_000.PIN.BLIF inst_BGACK_030_INTreg.D 0 1 1 0 .names SM_AMIGA_5_.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \ -inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF \ SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF N_317_i -1010------ 1 ---------1- 1 @@ -738,9 +737,6 @@ inst_AS_030_D0.BLIF CIIN .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 -.names CLK_OSZI.BLIF SM_AMIGA_5_.C -1 1 -0 0 .names CLK_OSZI.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -780,10 +776,7 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF SM_AMIGA_6_.C 1 1 0 0 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C +.names CLK_OSZI.BLIF SM_AMIGA_5_.C 1 1 0 0 .names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D @@ -857,7 +850,7 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF CLK_000_P_SYNC_9_.C 1 1 0 0 -.names inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF CLK_000_N_SYNC_0_.D +.names CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_N_SYNC_0_.D 10 1 0- 0 -1 0 @@ -912,12 +905,30 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C 1 1 0 0 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C +1 1 +0 0 .names CLK_OSZI.BLIF RST_DLY_1_.C 1 1 0 0 .names CLK_OSZI.BLIF RST_DLY_2_.C 1 1 0 0 +.names CLK_000.BLIF CLK_000_D_0_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_0_.C +1 1 +0 0 +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_1_.C +1 1 +0 0 .names CLK_OSZI.BLIF CLK_000_P_SYNC_0_.C 1 1 0 0 @@ -948,12 +959,6 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF RST_DLY_0_.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_AS_000_DMA.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 .names CLK_OSZI.BLIF inst_AS_000_INT.C 1 1 0 0 @@ -1014,18 +1019,15 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 +.names CLK_OSZI.BLIF inst_AS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 .names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C -1 1 -0 0 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D -1 1 -0 0 -.names CLK_OSZI.BLIF inst_CLK_000_D1.C -1 1 -0 0 .names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D 1 1 0 0 @@ -1044,12 +1046,6 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF CLK_OUT_INTreg.C 1 1 0 0 -.names CLK_000.BLIF inst_CLK_000_D0.D -1 1 -0 0 -.names CLK_OSZI.BLIF inst_CLK_000_D0.C -1 1 -0 0 .names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D 1 1 0 0 @@ -1062,6 +1058,9 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF inst_CLK_000_NE.C 1 1 0 0 +.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C +1 1 +0 0 .names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_1_ 01 1 1- 0 diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index 2a73743..0f15e10 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File -// ispLEVER Classic 1.8.00.04.29.14 +// ispLEVER Classic 2.0.00.17.20.15 -// Design '68030_tk' created Wed Jan 27 21:56:48 2016 +// Design '68030_tk' created Wed Aug 17 17:45:46 2016 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index bd5657e..c40f95f 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -1,8 +1,8 @@ - ispLEVER Classic 1.8.00.04.29.14 Linked Equations File -Copyright(C), 1992-2014, Lattice Semiconductor Corp. + ispLEVER Classic 2.0.00.17.20.15 Linked Equations File +Copyright(C), 1992-2015, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Wed Jan 27 21:56:48 2016 +Design bus68030 created Wed Aug 17 17:45:46 2016 P-Terms Fan-in Fan-out Type Name (attributes) @@ -111,10 +111,10 @@ Design bus68030 created Wed Jan 27 21:56:48 2016 1 1 1 Node inst_RESET_OUT.C 1 1 1 Node inst_CLK_OUT_PRE_50.D 1 1 1 Node inst_CLK_OUT_PRE_50.C - 1 1 1 Node inst_CLK_000_D1.D - 1 1 1 Node inst_CLK_000_D1.C - 1 1 1 Node inst_CLK_000_D0.D - 1 1 1 Node inst_CLK_000_D0.C + 1 1 1 Node CLK_000_D_1_.D + 1 1 1 Node CLK_000_D_1_.C + 1 1 1 Node CLK_000_D_0_.D + 1 1 1 Node CLK_000_D_0_.C 1 1 1 Node inst_CLK_000_PE.D 1 1 1 Node inst_CLK_000_PE.C 1 1 1 Node CLK_000_P_SYNC_9_.D @@ -324,7 +324,7 @@ A0.D = (!RST A0.C = (CLK_OSZI); !BG_000.D = (!BG_030 & RST & !BG_000.Q - # !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_CLK_000_D0.Q); + # !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & CLK_000_D_0_.Q); BG_000.C = (CLK_OSZI); @@ -362,8 +362,8 @@ RW.C = (CLK_OSZI); !N_317_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q); + # !SM_AMIGA_5_.Q & !CLK_000_D_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & CLK_000_D_0_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q); cpu_est_2_.D = (cpu_est_2_.Q & !cpu_est_0_.Q # cpu_est_2_.Q & !cpu_est_1_.Q @@ -504,13 +504,13 @@ inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_50.C = (CLK_OSZI); -inst_CLK_000_D1.D = (inst_CLK_000_D0.Q); +CLK_000_D_1_.D = (CLK_000_D_0_.Q); -inst_CLK_000_D1.C = (CLK_OSZI); +CLK_000_D_1_.C = (CLK_OSZI); -inst_CLK_000_D0.D = (CLK_000); +CLK_000_D_0_.D = (CLK_000); -inst_CLK_000_D0.C = (CLK_OSZI); +CLK_000_D_0_.C = (CLK_OSZI); inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q); @@ -586,7 +586,7 @@ RST_DLY_2_.D = (RST & RST_DLY_2_.Q RST_DLY_2_.C = (CLK_OSZI); -CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q); +CLK_000_P_SYNC_0_.D = (!CLK_000_D_1_.Q & CLK_000_D_0_.Q); CLK_000_P_SYNC_0_.C = (CLK_OSZI); @@ -622,7 +622,7 @@ CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q); CLK_000_P_SYNC_8_.C = (CLK_OSZI); -CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q); +CLK_000_N_SYNC_0_.D = (CLK_000_D_1_.Q & !CLK_000_D_0_.Q); CLK_000_N_SYNC_0_.C = (CLK_OSZI); @@ -668,7 +668,7 @@ CLK_000_N_SYNC_10_.C = (CLK_OSZI); SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q # RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN - # RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & !SM_AMIGA_i_7_.Q); + # RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_6_.C = (CLK_OSZI); diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index 7ca0563..3dd1e3a 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -36,6 +36,8 @@ DATA LOCATION BG_030:C_*_21 // INP DATA LOCATION CIIN:E_12_47 // OUT DATA LOCATION CIIN_0:E_5 // NOD DATA LOCATION CLK_000:*_*_11 // INP +DATA LOCATION CLK_000_D_0_:B_9 // NOD +DATA LOCATION CLK_000_D_1_:E_8 // NOD DATA LOCATION CLK_000_N_SYNC_0_:E_9 // NOD DATA LOCATION CLK_000_N_SYNC_10_:H_2 // NOD DATA LOCATION CLK_000_N_SYNC_11_:H_6 // NOD @@ -126,8 +128,6 @@ DATA LOCATION inst_AS_000_INT:C_1 // NOD DATA LOCATION inst_AS_030_000_SYNC:C_4 // NOD DATA LOCATION inst_AS_030_D0:H_3 // NOD DATA LOCATION inst_BGACK_030_INT_D:H_13 // NOD -DATA LOCATION inst_CLK_000_D0:B_9 // NOD -DATA LOCATION inst_CLK_000_D1:E_8 // NOD DATA LOCATION inst_CLK_000_NE:G_2 // NOD DATA LOCATION inst_CLK_000_NE_D0:D_10 // NOD DATA LOCATION inst_CLK_000_PE:G_5 // NOD @@ -371,10 +371,10 @@ DATA PW_LEVEL inst_RESET_OUT:1 DATA SLEW inst_RESET_OUT:1 DATA PW_LEVEL inst_CLK_OUT_PRE_50:1 DATA SLEW inst_CLK_OUT_PRE_50:1 -DATA PW_LEVEL inst_CLK_000_D1:1 -DATA SLEW inst_CLK_000_D1:1 -DATA PW_LEVEL inst_CLK_000_D0:1 -DATA SLEW inst_CLK_000_D0:1 +DATA PW_LEVEL CLK_000_D_1_:1 +DATA SLEW CLK_000_D_1_:1 +DATA PW_LEVEL CLK_000_D_0_:1 +DATA SLEW CLK_000_D_0_:1 DATA PW_LEVEL inst_CLK_000_PE:1 DATA SLEW inst_CLK_000_PE:1 DATA PW_LEVEL CLK_000_P_SYNC_9_:1 diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index 8b23778..f7c6278 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -5,7 +5,7 @@ GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA inst_LDS_000_INT GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ RN_IPL_030_2_ CLK_EXP inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AMIGA_BUS_ENABLE_DMA_HIGH - CYCLE_DMA_0_ inst_DTACK_D0 IPL_D0_2_ inst_CLK_000_D0 CLK_000_P_SYNC_1_ + CYCLE_DMA_0_ inst_DTACK_D0 IPL_D0_2_ CLK_000_D_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_7_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ RESET GROUP MACH_SEG_C inst_AS_030_000_SYNC inst_DS_000_ENABLE CYCLE_DMA_1_ inst_AS_000_INT @@ -15,7 +15,7 @@ GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 inst_RESET_OUT RST_DLY_0_ CLK_000_N_SYNC_5_ inst_CLK_000_NE_D0 LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH AMIGA_ADDR_ENABLE GROUP MACH_SEG_E CLK_000_P_SYNC_0_ CLK_000_N_SYNC_0_ CLK_000_P_SYNC_3_ - inst_CLK_000_D1 CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 + CLK_000_D_1_ CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ SM_AMIGA_6_ SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_4_ SM_AMIGA_5_ cpu_est_3_ inst_VPA_D CLK_000_N_SYNC_7_ inst_CLK_OUT_PRE_50 N_317_i diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index 5a35daf..fd30cdc 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -910;6<5r } [ \ No newline at end of file +755;017}nxñA.c \ No newline at end of file diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed new file mode 100644 index 0000000..ef3d250 --- /dev/null +++ b/Logic/68030_tk.jed @@ -0,0 +1,1114 @@ +|--------------------------------------------| +|- ispLEVER Fitter Report File -| +|- Version 2.0.00.17.20.15 -| +|- (c)Copyright, Lattice Semiconductor 2002 -| +|--------------------------------------------| + + +TITLE: +AUTHOR: +PATTERN: +COMPANY: +REVISION: +DATE: Wed Aug 17 17:45:51 2016 + +ABEL mach447a + * +QP100* +QF54096* +G0*F0* +NOTE Part Number : M4A5-128/64-10VC * +NOTE Handling of Preplacements No Change * +NOTE Use placement data from 68030_tk.vct * +NOTE Global clocks routable as PT clocks? N * +NOTE 22V10/MACH1XX/2XX S/R Compatibility? Y * +NOTE SET/RESET treated as DONT_CARE? N * +NOTE Reduce Unforced Global Clocks? N * +NOTE Iterate between partitioning and place/route? Y * +NOTE Balanced partitioning? Y * +NOTE Reduce Routes Per Placement? N * +NOTE Spread Placement? Y * +NOTE Run Time Upper Bound in 15 minutes 0 * +NOTE Zero Hold Time For Input Registers? Y * +NOTE Table of pin names and numbers* +NOTE PINS SIZE_1_:79 A_31_:4 IPL_2_:68 IPL_1_:56 FC_1_:58* +NOTE PINS IPL_0_:67 AS_030:82 FC_0_:57 AS_000:42 DS_030:98* +NOTE PINS UDS_000:32 LDS_000:31 A1:60 nEXP_SPACE:14 BERR:41* +NOTE PINS BG_030:21 BGACK_000:28 CLK_030:64 CLK_000:11 CLK_OSZI:61* +NOTE PINS CLK_DIV_OUT:65 FPU_CS:78 FPU_SENSE:91 DTACK:30* +NOTE PINS AVEC:92 E:66 VPA:36 RST:86 RESET:3 AMIGA_ADDR_ENABLE:33* +NOTE PINS SIZE_0_:70 AMIGA_BUS_DATA_DIR:48 A_30_:5 AMIGA_BUS_ENABLE_LOW:20* +NOTE PINS A_29_:6 AMIGA_BUS_ENABLE_HIGH:34 A_28_:15 CIIN:47* +NOTE PINS A_27_:16 A_26_:17 A_25_:18 A_24_:19 A_23_:85 A_22_:84* +NOTE PINS A_21_:94 A_20_:93 A_19_:97 A_18_:95 A_17_:59 A_16_:96* +NOTE PINS IPL_030_2_:9 IPL_030_1_:7 IPL_030_0_:8 RW_000:80* +NOTE PINS A0:69 BG_000:29 BGACK_030:83 CLK_EXP:10 DSACK1:81* +NOTE PINS VMA:35 RW:71 * +NOTE Table of node names and numbers* +NOTE NODES RN_SIZE_1_:287 RN_AS_030:281 RN_AS_000:203 RN_UDS_000:185 * +NOTE NODES RN_LDS_000:191 RN_BERR:197 RN_SIZE_0_:263 RN_IPL_030_2_:131 * +NOTE NODES RN_IPL_030_1_:143 RN_IPL_030_0_:137 RN_RW_000:269 * +NOTE NODES RN_A0:257 RN_BG_000:175 RN_BGACK_030:275 RN_DSACK1:283 * +NOTE NODES RN_VMA:173 RN_RW:245 N_317_i:242 cpu_est_2_:193 * +NOTE NODES cpu_est_3_:239 cpu_est_0_:182 cpu_est_1_:176 * +NOTE NODES inst_AS_000_INT:151 SM_AMIGA_5_:233 inst_AMIGA_BUS_ENABLE_DMA_LOW:128 * +NOTE NODES inst_AS_030_D0:274 inst_nEXP_SPACE_D0reg:113 * +NOTE NODES inst_AS_030_000_SYNC:155 inst_BGACK_030_INT_D:289 * +NOTE NODES inst_AS_000_DMA:103 inst_DS_000_DMA:121 CYCLE_DMA_0_:133 * +NOTE NODES CYCLE_DMA_1_:167 SIZE_DMA_0_:265 SIZE_DMA_1_:259 * +NOTE NODES inst_VPA_D:224 inst_UDS_000_INT:115 inst_LDS_000_INT:109 * +NOTE NODES inst_CLK_OUT_PRE_D:119 inst_DTACK_D0:148 inst_RESET_OUT:187 * +NOTE NODES inst_CLK_OUT_PRE_50:241 CLK_000_D_1_:209 CLK_000_D_0_:139 * +NOTE NODES inst_CLK_000_PE:253 CLK_000_P_SYNC_9_:268 inst_CLK_000_NE:248 * +NOTE NODES CLK_000_N_SYNC_11_:278 IPL_D0_0_:262 IPL_D0_1_:196 * +NOTE NODES IPL_D0_2_:142 inst_CLK_000_NE_D0:188 SM_AMIGA_0_:223 * +NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_HIGH:145 SM_AMIGA_4_:235 * +NOTE NODES inst_DS_000_ENABLE:161 RST_DLY_0_:178 RST_DLY_1_:194 * +NOTE NODES RST_DLY_2_:184 CLK_000_P_SYNC_0_:200 CLK_000_P_SYNC_1_:136 * +NOTE NODES CLK_000_P_SYNC_2_:256 CLK_000_P_SYNC_3_:217 CLK_000_P_SYNC_4_:250 * +NOTE NODES CLK_000_P_SYNC_5_:266 CLK_000_P_SYNC_6_:106 CLK_000_P_SYNC_7_:130 * +NOTE NODES CLK_000_P_SYNC_8_:260 CLK_000_N_SYNC_0_:211 CLK_000_N_SYNC_1_:122 * +NOTE NODES CLK_000_N_SYNC_2_:146 CLK_000_N_SYNC_3_:140 CLK_000_N_SYNC_4_:134 * +NOTE NODES CLK_000_N_SYNC_5_:190 CLK_000_N_SYNC_6_:254 CLK_000_N_SYNC_7_:226 * +NOTE NODES CLK_000_N_SYNC_8_:116 CLK_000_N_SYNC_9_:110 CLK_000_N_SYNC_10_:272 * +NOTE NODES SM_AMIGA_6_:227 inst_CLK_030_H:104 SM_AMIGA_1_:229 * +NOTE NODES SM_AMIGA_3_:230 SM_AMIGA_2_:236 SM_AMIGA_i_7_:221 * +NOTE NODES CIIN_0:205 * +NOTE BLOCK 0 * +L000000 + 111111110111111111111110111111101111111110111111111111111111111111 + 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11111011111111* +E1 +1 +01111100 +1 +01110010 +1 +00000000 +1 +01000011 +1 +01011001 +1 +00000000 +1 +10001110 +1 +10000010 +1 +* +C2728* +U00000000000000000000000000000000* +ECEB diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index 9ba962b..4f33ac0 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; -DATE = 1/27/16; -TIME = 21:56:53; +DATE = 8/17/16; +TIME = 17:45:51; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -162,8 +162,8 @@ inst_CLK_OUT_PRE_D = node,-,-,A,12; inst_DTACK_D0 = node,-,-,B,15; inst_RESET_OUT = node,-,-,D,9; inst_CLK_OUT_PRE_50 = node,-,-,F,13; -inst_CLK_000_D1 = node,-,-,E,8; -inst_CLK_000_D0 = node,-,-,B,9; +CLK_000_D_1_ = node,-,-,E,8; +CLK_000_D_0_ = node,-,-,B,9; inst_CLK_000_PE = node,-,-,G,5; CLK_000_P_SYNC_9_ = node,-,-,G,15; inst_CLK_000_NE = node,-,-,G,2; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index 2489793..9dbe4bb 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -2164,6 +2164,1965 @@ 324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21 321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A0 5 366 6 2 0 1 68 -1 3 0 21 + 70 RW 5 371 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21 + 80 DSACK1 5 369 7 0 80 -1 4 0 21 + 82 BGACK_030 5 368 7 0 82 -1 3 0 21 + 34 VMA 5 370 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 367 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 368 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 301 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21 + 355 SM_AMIGA_6_ 3 -1 5 4 0 1 2 5 -1 -1 3 0 21 + 299 SM_AMIGA_5_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 + 320 inst_CLK_000_PE 3 -1 4 4 2 3 5 7 -1 -1 1 0 21 + 319 inst_CLK_000_D0 3 -1 4 4 2 3 4 5 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 4 0 1 5 6 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 2 3 3 5 7 -1 -1 15 0 21 + 295 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 310 SIZE_DMA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 + 296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 294 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 326 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 2 0 21 + 322 inst_CLK_000_NE 3 -1 4 3 2 3 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 5 3 1 6 7 -1 -1 1 0 21 + 305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 303 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21 + 329 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 370 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 357 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21 + 328 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 327 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 297 cpu_est_0_ 3 -1 2 2 2 3 -1 -1 2 0 21 + 321 inst_CLK_000_NE_D0 3 -1 5 2 2 3 -1 -1 1 0 21 + 318 inst_CLK_000_D1 3 -1 5 2 2 5 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 358 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 359 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21 + 331 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 366 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 330 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 371 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 332 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 307 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_7_ 3 -1 3 1 6 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_6_ 3 -1 5 1 3 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_5_ 3 -1 6 1 5 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_3_ 3 -1 3 1 1 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_1_ 3 -1 6 1 6 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_9_ 3 -1 2 1 6 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_8_ 3 -1 5 1 2 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_7_ 3 -1 2 1 5 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_6_ 3 -1 1 1 2 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_5_ 3 -1 0 1 1 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_3_ 3 -1 2 1 0 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_2_ 3 -1 6 1 2 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_10_ 3 -1 6 1 0 -1 -1 1 0 21 + 325 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 324 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 5 1 5 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21 + 293 N_336_i 3 -1 2 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 59 A1 1 -1 -1 2 0 1 59 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 10 CLK_000 1 -1 -1 1 4 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +129 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 352 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 31 UDS_000 5 -1 3 3 0 2 6 31 -1 1 0 21 + 68 A0 5 353 6 2 5 6 68 -1 3 0 21 + 70 RW 5 358 6 2 1 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 2 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21 + 8 IPL_030_2_ 5 351 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 360 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 359 1 0 6 -1 10 0 21 + 80 DSACK1 5 356 7 0 80 -1 4 0 21 + 82 BGACK_030 5 355 7 0 82 -1 3 0 21 + 34 VMA 5 357 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 354 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 355 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 315 inst_RESET_OUT 3 -1 6 6 0 1 3 4 6 7 -1 -1 2 0 21 + 318 inst_CLK_000_PE 3 -1 5 6 0 1 2 3 5 7 -1 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 6 6 0 3 4 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 6 0 1 3 4 5 7 -1 -1 1 0 21 + 348 SM_AMIGA_i_7_ 3 -1 5 5 0 1 3 5 7 -1 -1 15 0 21 + 320 inst_CLK_000_NE 3 -1 5 4 1 3 5 6 -1 -1 1 0 21 + 317 inst_CLK_000_D0 3 -1 5 4 1 3 5 6 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 4 0 2 3 6 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 343 SM_AMIGA_6_ 3 -1 5 3 1 5 6 -1 -1 3 0 21 + 327 SM_AMIGA_4_ 3 -1 5 3 1 2 5 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 298 SM_AMIGA_5_ 3 -1 1 3 1 5 7 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 5 3 1 5 7 -1 -1 2 0 21 + 319 inst_CLK_000_NE_D0 3 -1 1 3 2 3 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 2 3 2 3 5 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21 + 346 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21 + 328 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21 + 347 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 357 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 345 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21 + 311 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21 + 324 inst_CLK_000_D1 3 -1 6 2 1 5 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 3 2 2 5 -1 -1 1 0 21 + 360 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 359 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 351 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 344 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 356 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 4 0 21 + 353 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 352 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 358 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 354 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 350 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 326 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 349 N_350 3 -1 3 1 5 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_7_ 3 -1 2 1 2 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_6_ 3 -1 3 1 2 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_5_ 3 -1 0 1 3 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_3_ 3 -1 4 1 0 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_2_ 3 -1 5 1 4 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 59 A1 1 -1 -1 2 2 3 59 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 5 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +123 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 346 7 2 4 6 79 -1 3 0 21 + 68 A0 5 347 6 2 1 2 68 -1 3 0 21 + 70 RW 5 352 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 31 UDS_000 5 -1 3 1 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 1 6 30 -1 1 0 21 + 8 IPL_030_2_ 5 345 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 354 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 353 1 0 6 -1 10 0 21 + 80 DSACK1 5 350 7 0 80 -1 4 0 21 + 82 BGACK_030 5 349 7 0 82 -1 3 0 21 + 34 VMA 5 351 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 348 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 349 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 318 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 1 6 0 3 4 5 6 7 -1 -1 1 0 21 + 320 inst_CLK_000_PE 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 5 0 3 4 5 7 -1 -1 1 0 21 + 341 SM_AMIGA_i_7_ 3 -1 5 4 0 3 5 7 -1 -1 14 0 21 + 296 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 338 SM_AMIGA_1_ 3 -1 2 3 2 5 7 -1 -1 3 0 21 + 336 SM_AMIGA_6_ 3 -1 5 3 1 2 5 -1 -1 3 0 21 + 298 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 295 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 293 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 342 inst_CLK_000_NE 3 -1 5 3 2 3 5 -1 -1 1 0 21 + 321 inst_CLK_000_NE_D0 3 -1 5 3 2 3 5 -1 -1 1 0 21 + 314 inst_CLK_000_D0 3 -1 5 3 3 5 6 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21 + 305 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 + 304 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21 + 339 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21 + 329 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 340 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 351 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 328 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 2 0 6 -1 -1 3 0 21 + 327 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 326 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 294 cpu_est_0_ 3 -1 2 2 2 3 -1 -1 2 0 21 + 325 inst_CLK_000_D1 3 -1 6 2 4 5 -1 -1 1 0 21 + 315 inst_CLK_000_D5 3 -1 4 2 4 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 2 0 6 -1 -1 1 0 21 + 354 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 353 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 345 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 337 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21 + 350 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 332 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 347 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 346 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 331 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 352 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 348 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 344 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 343 N_192 3 -1 2 1 5 -1 -1 2 0 21 + 333 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 335 inst_CLK_000_D4 3 -1 7 1 4 -1 -1 1 0 21 + 334 inst_CLK_000_D3 3 -1 1 1 7 -1 -1 1 0 21 + 330 inst_CLK_000_D2 3 -1 4 1 1 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 319 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21 + 317 inst_DTACK_D0 3 -1 1 1 2 -1 -1 1 0 21 + 316 inst_CLK_000_D6 3 -1 4 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 + 63 CLK_030 1 -1 -1 2 6 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 0 59 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 1 13 -1 + 10 CLK_000 1 -1 -1 1 5 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +129 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 352 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 31 UDS_000 5 -1 3 3 0 2 6 31 -1 1 0 21 + 68 A0 5 353 6 2 5 6 68 -1 3 0 21 + 70 RW 5 358 6 2 1 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 2 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21 + 8 IPL_030_2_ 5 351 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 360 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 359 1 0 6 -1 10 0 21 + 80 DSACK1 5 356 7 0 80 -1 4 0 21 + 82 BGACK_030 5 355 7 0 82 -1 3 0 21 + 34 VMA 5 357 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 354 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 355 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 315 inst_RESET_OUT 3 -1 6 6 0 1 3 4 6 7 -1 -1 2 0 21 + 318 inst_CLK_000_PE 3 -1 5 6 0 1 2 3 5 7 -1 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 6 6 0 3 4 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 6 0 1 3 4 5 7 -1 -1 1 0 21 + 348 SM_AMIGA_i_7_ 3 -1 5 5 0 1 3 5 7 -1 -1 15 0 21 + 320 inst_CLK_000_NE 3 -1 5 4 1 3 5 6 -1 -1 1 0 21 + 317 inst_CLK_000_D0 3 -1 5 4 1 3 5 6 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 4 0 2 3 6 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 343 SM_AMIGA_6_ 3 -1 5 3 1 5 6 -1 -1 3 0 21 + 327 SM_AMIGA_4_ 3 -1 5 3 1 2 5 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 298 SM_AMIGA_5_ 3 -1 1 3 1 5 7 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 5 3 1 5 7 -1 -1 2 0 21 + 319 inst_CLK_000_NE_D0 3 -1 1 3 2 3 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 2 3 2 3 5 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21 + 346 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21 + 328 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21 + 347 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 357 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 345 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21 + 311 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21 + 324 inst_CLK_000_D1 3 -1 6 2 1 5 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 3 2 2 5 -1 -1 1 0 21 + 360 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 359 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 351 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 344 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 356 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 4 0 21 + 353 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 352 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 358 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 354 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 350 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 326 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 349 N_350 3 -1 3 1 5 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_7_ 3 -1 2 1 2 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_6_ 3 -1 3 1 2 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_5_ 3 -1 0 1 3 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_3_ 3 -1 4 1 0 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_2_ 3 -1 5 1 4 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 59 A1 1 -1 -1 2 2 3 59 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 5 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 + 79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21 + 40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21 + 70 RW 5 371 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 366 6 1 0 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21 + 80 DSACK1 5 369 7 0 80 -1 4 0 21 + 82 BGACK_030 5 368 7 0 82 -1 3 0 21 + 34 VMA 5 370 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 367 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21 + 299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21 + 319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21 + 318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 + 364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21 + 366 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 371 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21 + 326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 + 79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21 + 40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21 + 70 RW 5 371 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 366 6 1 0 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21 + 80 DSACK1 5 369 7 0 80 -1 4 0 21 + 82 BGACK_030 5 368 7 0 82 -1 3 0 21 + 34 VMA 5 370 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 367 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21 + 299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21 + 319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21 + 318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 + 364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21 + 366 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 371 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21 + 326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +141 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 363 7 3 0 4 6 79 -1 3 0 21 + 68 A0 5 364 6 2 5 6 68 -1 3 0 21 + 70 RW 5 371 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 368 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 367 1 0 6 -1 10 0 21 + 80 DSACK1 5 369 7 0 80 -1 4 0 21 + 32 AMIGA_ADDR_ENABLE 5 372 3 0 32 -1 4 0 21 + 82 BGACK_030 5 366 7 0 82 -1 3 0 21 + 34 VMA 5 370 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 365 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 366 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 0 6 0 2 3 4 6 7 -1 -1 1 0 21 + 322 inst_CLK_000_NE 3 -1 6 5 1 2 3 5 6 -1 -1 1 0 21 + 320 inst_CLK_000_PE 3 -1 1 5 1 2 3 5 7 -1 -1 1 0 21 + 301 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21 + 328 SM_AMIGA_6_ 3 -1 2 4 2 3 5 6 -1 -1 3 0 21 + 299 SM_AMIGA_5_ 3 -1 2 4 0 2 5 7 -1 -1 3 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 3 2 3 7 -1 -1 14 0 21 + 293 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 357 SM_AMIGA_1_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 329 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 319 inst_CLK_000_D0 3 -1 0 3 2 3 4 -1 -1 1 0 21 + 318 inst_CLK_000_D1 3 -1 4 3 2 3 4 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 3 2 3 6 -1 -1 1 0 21 + 305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 358 SM_AMIGA_3_ 3 -1 5 2 2 5 -1 -1 5 0 21 + 332 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 359 SM_AMIGA_2_ 3 -1 5 2 2 5 -1 -1 4 0 21 + 334 RST_DLY_1_ 3 -1 6 2 1 6 -1 -1 4 0 21 + 370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 333 RST_DLY_0_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 331 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 CYCLE_DMA_1_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 335 RST_DLY_2_ 3 -1 6 2 1 6 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 307 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 3 2 2 3 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 354 CLK_000_N_SYNC_9_ 3 -1 5 2 3 7 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 7 2 3 5 -1 -1 1 0 21 + 368 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 367 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 303 inst_AS_030_000_SYNC 3 -1 2 1 2 -1 -1 7 0 21 + 372 RN_AMIGA_ADDR_ENABLE 3 32 3 1 3 32 -1 4 0 21 + 369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 298 N_257_i 3 -1 2 1 5 -1 -1 4 0 21 + 364 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 363 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 371 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 365 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21 + 355 CLK_000_N_SYNC_10_ 3 -1 3 1 7 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_8_ 3 -1 0 1 5 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_7_ 3 -1 6 1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_6_ 3 -1 6 1 6 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_8_ 3 -1 4 1 1 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_7_ 3 -1 1 1 4 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_6_ 3 -1 6 1 1 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_5_ 3 -1 5 1 6 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_4_ 3 -1 5 1 5 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_3_ 3 -1 1 1 5 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_1_ 3 -1 0 1 0 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21 + 327 inst_CLK_000_NE_D0 3 -1 3 1 5 -1 -1 1 0 21 + 326 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 324 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_9_ 3 -1 1 1 1 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 5 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 59 A1 1 -1 -1 1 3 59 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 29 DTACK 1 -1 -1 1 5 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 10 CLK_000 1 -1 -1 1 0 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 + 79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21 + 40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21 + 70 RW 5 371 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 366 6 1 0 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21 + 80 DSACK1 5 369 7 0 80 -1 4 0 21 + 82 BGACK_030 5 368 7 0 82 -1 3 0 21 + 34 VMA 5 370 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 367 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21 + 299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21 + 319 inst_CLK_000_D0 3 -1 1 3 3 4 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21 + 318 inst_CLK_000_D1 3 -1 4 2 4 5 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 + 364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21 + 366 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 371 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21 + 326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 + 79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21 + 40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21 + 70 RW 5 371 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 366 6 1 0 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21 + 80 DSACK1 5 369 7 0 80 -1 4 0 21 + 82 BGACK_030 5 368 7 0 82 -1 3 0 21 + 34 VMA 5 370 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 367 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21 + 299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21 + 319 CLK_000_D_0_ 3 -1 1 3 3 4 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 4 2 4 5 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 + 364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21 + 366 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 371 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21 + 326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +129 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 352 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 31 UDS_000 5 -1 3 3 0 2 6 31 -1 1 0 21 + 68 A0 5 353 6 2 5 6 68 -1 3 0 21 + 70 RW 5 358 6 2 1 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 2 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21 + 8 IPL_030_2_ 5 351 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 360 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 359 1 0 6 -1 10 0 21 + 80 DSACK1 5 356 7 0 80 -1 4 0 21 + 82 BGACK_030 5 355 7 0 82 -1 3 0 21 + 34 VMA 5 357 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 354 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 355 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 315 inst_RESET_OUT 3 -1 6 6 0 1 3 4 6 7 -1 -1 2 0 21 + 318 inst_CLK_000_PE 3 -1 5 6 0 1 2 3 5 7 -1 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 6 6 0 3 4 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 6 0 1 3 4 5 7 -1 -1 1 0 21 + 348 SM_AMIGA_i_7_ 3 -1 5 5 0 1 3 5 7 -1 -1 15 0 21 + 320 inst_CLK_000_NE 3 -1 5 4 1 3 5 6 -1 -1 1 0 21 + 317 CLK_000_D_0_ 3 -1 5 4 1 3 5 6 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 4 0 2 3 6 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 343 SM_AMIGA_6_ 3 -1 5 3 1 5 6 -1 -1 3 0 21 + 327 SM_AMIGA_4_ 3 -1 5 3 1 2 5 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 298 SM_AMIGA_5_ 3 -1 1 3 1 5 7 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 5 3 1 5 7 -1 -1 2 0 21 + 319 inst_CLK_000_NE_D0 3 -1 1 3 2 3 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 2 3 2 3 5 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21 + 346 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21 + 328 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21 + 347 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 357 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 345 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21 + 311 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21 + 324 CLK_000_D_1_ 3 -1 6 2 1 5 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 3 2 2 5 -1 -1 1 0 21 + 360 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 359 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 351 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 344 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 356 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 330 RST_DLY_1_ 3 -1 6 1 6 -1 -1 4 0 21 + 353 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 352 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 329 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 358 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 354 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 350 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 331 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 326 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 349 N_350 3 -1 3 1 5 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_7_ 3 -1 2 1 2 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_6_ 3 -1 3 1 2 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_5_ 3 -1 0 1 3 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_3_ 3 -1 4 1 0 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_2_ 3 -1 5 1 4 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 59 A1 1 -1 -1 2 2 3 59 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 5 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +127 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 350 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A0 5 351 6 2 1 6 68 -1 3 0 21 + 70 RW 5 356 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 349 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 358 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 357 1 0 6 -1 10 0 21 + 80 DSACK1 5 354 7 0 80 -1 4 0 21 + 82 BGACK_030 5 353 7 0 82 -1 3 0 21 + 34 VMA 5 355 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 352 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 353 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 347 SM_AMIGA_i_7_ 3 -1 2 5 0 2 3 5 7 -1 -1 14 0 21 + 301 inst_AS_030_D0 3 -1 7 5 0 3 4 5 7 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 1 4 1 2 3 6 -1 -1 4 0 21 + 342 SM_AMIGA_6_ 3 -1 2 4 0 1 2 6 -1 -1 3 0 21 + 299 SM_AMIGA_5_ 3 -1 0 4 0 2 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 1 4 1 2 3 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 2 4 1 2 3 6 -1 -1 3 0 21 + 322 inst_CLK_000_NE 3 -1 1 4 0 2 3 6 -1 -1 1 0 21 + 321 inst_CLK_000_NE_D0 3 -1 6 4 1 2 3 5 -1 -1 1 0 21 + 320 inst_CLK_000_PE 3 -1 4 4 0 2 3 7 -1 -1 1 0 21 + 319 CLK_000_D_0_ 3 -1 1 4 1 2 3 4 -1 -1 1 0 21 + 326 SM_AMIGA_0_ 3 -1 2 3 0 2 7 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 3 1 2 3 -1 -1 2 0 21 + 318 CLK_000_D_1_ 3 -1 4 3 1 2 4 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 303 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21 + 329 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21 + 355 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 344 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21 + 328 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 327 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 311 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21 + 358 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 357 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 343 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 345 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 354 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 346 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21 + 331 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 293 N_317_i 3 -1 2 1 2 -1 -1 4 0 21 + 351 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 350 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 330 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 356 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 348 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 332 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 307 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 341 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_9_ 3 -1 5 1 7 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_8_ 3 -1 0 1 5 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_6_ 3 -1 5 1 5 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_5_ 3 -1 6 1 5 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_4_ 3 -1 5 1 6 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_3_ 3 -1 1 1 5 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 325 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 324 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 5 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 5 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +127 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 350 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 356 6 2 1 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 351 6 1 3 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 8 IPL_030_2_ 5 349 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 358 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 357 1 0 6 -1 10 0 21 + 80 DSACK1 5 354 7 0 80 -1 4 0 21 + 82 BGACK_030 5 353 7 0 82 -1 3 0 21 + 34 VMA 5 355 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 352 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 353 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 315 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 319 inst_CLK_000_PE 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 6 6 0 3 4 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 4 6 1 3 4 5 6 7 -1 -1 1 0 21 + 321 inst_CLK_000_NE 3 -1 5 5 1 2 3 5 6 -1 -1 1 0 21 + 347 SM_AMIGA_i_7_ 3 -1 5 4 1 3 5 7 -1 -1 14 0 21 + 342 SM_AMIGA_6_ 3 -1 5 4 1 3 5 6 -1 -1 3 0 21 + 298 SM_AMIGA_5_ 3 -1 6 4 1 5 6 7 -1 -1 3 0 21 + 293 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 327 SM_AMIGA_4_ 3 -1 1 3 1 2 5 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 325 SM_AMIGA_0_ 3 -1 5 3 1 5 7 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 7 3 1 6 7 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 4 3 0 5 6 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 345 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21 + 328 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21 + 346 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 355 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 344 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 326 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21 + 320 inst_CLK_000_NE_D0 3 -1 5 2 2 5 -1 -1 1 0 21 + 318 CLK_000_D_0_ 3 -1 0 2 3 5 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21 + 358 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 357 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 343 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 302 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21 + 354 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 331 RST_DLY_1_ 3 -1 2 1 2 -1 -1 4 0 21 + 351 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 350 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 329 RST_DLY_0_ 3 -1 2 1 2 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 3 1 3 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 356 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 348 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 332 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21 + 330 N_182_i 3 -1 2 1 5 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 341 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_8_ 3 -1 1 1 0 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_7_ 3 -1 5 1 1 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_6_ 3 -1 2 1 5 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_5_ 3 -1 2 1 2 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_4_ 3 -1 6 1 2 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_3_ 3 -1 1 1 6 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 4 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 317 CLK_000_D_1_ 3 -1 5 1 5 -1 -1 1 0 21 + 316 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 4 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 4 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A1 1 -1 -1 1 0 59 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 4 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 0 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +130 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 6 0 1 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 353 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 31 UDS_000 5 -1 3 3 0 2 6 31 -1 1 0 21 + 70 RW 5 359 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 2 30 -1 1 0 21 + 68 A0 5 354 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 352 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 361 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 360 1 0 6 -1 10 0 21 + 80 DSACK1 5 357 7 0 80 -1 4 0 21 + 82 BGACK_030 5 356 7 0 82 -1 3 0 21 + 34 VMA 5 358 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 355 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 356 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 315 inst_RESET_OUT 3 -1 6 6 0 1 3 4 6 7 -1 -1 2 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 2 6 0 3 4 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 4 6 0 1 3 4 6 7 -1 -1 1 0 21 + 350 SM_AMIGA_i_7_ 3 -1 5 5 0 3 5 6 7 -1 -1 14 0 21 + 322 inst_CLK_000_NE 3 -1 5 5 0 3 5 6 7 -1 -1 1 0 21 + 320 inst_CLK_000_PE 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21 + 298 SM_AMIGA_5_ 3 -1 0 4 0 1 5 7 -1 -1 3 0 21 + 318 CLK_000_D_0_ 3 -1 6 4 0 2 3 5 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 344 SM_AMIGA_6_ 3 -1 5 3 0 1 5 -1 -1 3 0 21 + 328 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 293 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 326 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 2 0 21 + 321 inst_CLK_000_NE_D0 3 -1 7 3 2 3 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 3 2 5 6 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 6 2 5 6 -1 -1 7 0 21 + 347 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21 + 329 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21 + 349 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 358 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 346 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 327 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21 + 317 CLK_000_D_1_ 3 -1 2 2 0 5 -1 -1 1 0 21 + 316 inst_CLK_OUT_PRE_50 3 -1 3 2 0 3 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21 + 361 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 360 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 352 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 345 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 357 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 331 RST_DLY_1_ 3 -1 6 1 6 -1 -1 4 0 21 + 354 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 353 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 330 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 359 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 355 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 351 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 348 N_187_i 3 -1 2 1 5 -1 -1 2 0 21 + 332 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 343 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_9_ 3 -1 1 1 7 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_8_ 3 -1 1 1 1 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_7_ 3 -1 5 1 1 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_6_ 3 -1 5 1 5 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_5_ 3 -1 2 1 5 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_4_ 3 -1 6 1 2 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_3_ 3 -1 3 1 6 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_2_ 3 -1 5 1 3 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 325 IPL_D0_2_ 3 -1 4 1 1 -1 -1 1 0 21 + 324 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 + 323 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 319 CLK_000_D_2_ 3 -1 5 1 5 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 4 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 6 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 6 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 6 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 6 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 6 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 6 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 4 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 59 A1 1 -1 -1 2 2 5 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 4 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 2 13 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 + 79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21 + 40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21 + 70 RW 5 371 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 366 6 1 0 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21 + 80 DSACK1 5 369 7 0 80 -1 4 0 21 + 82 BGACK_030 5 368 7 0 82 -1 3 0 21 + 34 VMA 5 370 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 367 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 320 inst_CLK_000_PE 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21 + 299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 328 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21 + 319 CLK_000_D_0_ 3 -1 1 3 3 4 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 331 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 330 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 329 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 327 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 322 inst_CLK_000_NE 3 -1 6 2 3 5 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 4 2 4 5 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 + 364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 333 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21 + 366 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 332 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 371 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 334 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 354 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_3_ 3 -1 4 1 6 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_1_ 3 -1 1 1 6 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21 + 326 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 325 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 324 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 323 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21 315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 60 CLK_OSZI 9 -1 0 60 -1 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index 53b1c72..0782a97 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -1,6 +1,6 @@ |--------------------------------------------| |- ispLEVER Fitter Report File -| -|- Version 1.8.00.04.29.14 -| +|- Version 2.0.00.17.20.15 -| |- (c)Copyright, Lattice Semiconductor 2002 -| |--------------------------------------------| @@ -8,7 +8,7 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Wed Jan 27 21:56:53 2016 +; DATE Wed Aug 17 17:45:51 2016 Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287 @@ -114,8 +114,8 @@ Node 119 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 Node 148 inst_DTACK_D0 Reg ; S6=1 S9=1 Node 187 inst_RESET_OUT Reg ; S6=1 S9=1 Node 241 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 -Node 209 inst_CLK_000_D1 Reg ; S6=1 S9=1 -Node 139 inst_CLK_000_D0 Reg ; S6=1 S9=1 +Node 209 CLK_000_D_1_ Reg ; S6=1 S9=1 +Node 139 CLK_000_D_0_ Reg ; S6=1 S9=1 Node 253 inst_CLK_000_PE Reg ; S6=1 S9=1 Node 268 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1 Node 248 inst_CLK_000_NE Reg ; S6=1 S9=1 diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index 411ade1..ddce524 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -1,14 +1,14 @@ |--------------------------------------------| |- ispLEVER Fitter Report File -| -|- Version 1.8.00.04.29.14 -| +|- Version 2.0.00.17.20.15 -| |- (c)Copyright, Lattice Semiconductor 2002 -| |--------------------------------------------| -Start: Wed Jan 27 21:56:53 2016 -End : Wed Jan 27 21:56:53 2016 $$$ Elapsed time: 00:00:00 +Start: Wed Aug 17 17:45:51 2016 +End : Wed Aug 17 17:45:51 2016 $$$ Elapsed time: 00:00:00 =========================================================================== -Part [C:/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] +Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] * Place/Route options (keycode = 540674) = Spread Placement: ON @@ -93,115 +93,115 @@ ___|__|__|____|____________________________________________________________ 31| 4|OUT| 47|=> ....|....| CIIN 32| 4|NOD| . |=> ....|4...| CIIN_0 33| +|INP| 11|=> .1..|....| CLK_000 - 34| 4|NOD| . |=> 0...|....| CLK_000_N_SYNC_0_ - 35| 7|NOD| . |=> ....|...7| CLK_000_N_SYNC_10_ - 36| 7|NOD| . |=> ....|..6.| CLK_000_N_SYNC_11_ - 37| 0|NOD| . |=> .1..|....| CLK_000_N_SYNC_1_ - 38| 1|NOD| . |=> .1..|....| CLK_000_N_SYNC_2_ - 39| 1|NOD| . |=> .1..|....| CLK_000_N_SYNC_3_ - 40| 1|NOD| . |=> ...3|....| CLK_000_N_SYNC_4_ - 41| 3|NOD| . |=> ....|..6.| CLK_000_N_SYNC_5_ - 42| 6|NOD| . |=> ....|.5..| CLK_000_N_SYNC_6_ - 43| 5|NOD| . |=> 0...|....| CLK_000_N_SYNC_7_ - 44| 0|NOD| . |=> 0...|....| CLK_000_N_SYNC_8_ - 45| 0|NOD| . |=> ....|...7| CLK_000_N_SYNC_9_ - 46| 4|NOD| . |=> .1..|....| CLK_000_P_SYNC_0_ - 47| 1|NOD| . |=> ....|..6.| CLK_000_P_SYNC_1_ - 48| 6|NOD| . |=> ....|4...| CLK_000_P_SYNC_2_ - 49| 4|NOD| . |=> ....|..6.| CLK_000_P_SYNC_3_ - 50| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_4_ - 51| 6|NOD| . |=> 0...|....| CLK_000_P_SYNC_5_ - 52| 0|NOD| . |=> .1..|....| CLK_000_P_SYNC_6_ - 53| 1|NOD| . |=> ....|..6.| CLK_000_P_SYNC_7_ - 54| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_8_ - 55| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_9_ - 56| +|INP| 64|=> 0...|...7| CLK_030 - 57| 6|OUT| 65|=> ....|....| CLK_DIV_OUT - 58| 1|OUT| 10|=> ....|....| CLK_EXP - 59| +|Cin| 61|=> ....|....| CLK_OSZI - 60| 1|NOD| . |=> 012.|....| CYCLE_DMA_0_ - 61| 2|NOD| . |=> 0.2.|....| CYCLE_DMA_1_ - 62| 7| IO| 81|=> ....|....| DSACK1 + 34| 1|NOD| . |=> ...3|45..| CLK_000_D_0_ + 35| 4|NOD| . |=> ....|45..| CLK_000_D_1_ + 36| 4|NOD| . |=> 0...|....| CLK_000_N_SYNC_0_ + 37| 7|NOD| . |=> ....|...7| CLK_000_N_SYNC_10_ + 38| 7|NOD| . |=> ....|..6.| CLK_000_N_SYNC_11_ + 39| 0|NOD| . |=> .1..|....| CLK_000_N_SYNC_1_ + 40| 1|NOD| . |=> .1..|....| CLK_000_N_SYNC_2_ + 41| 1|NOD| . |=> .1..|....| CLK_000_N_SYNC_3_ + 42| 1|NOD| . |=> ...3|....| CLK_000_N_SYNC_4_ + 43| 3|NOD| . |=> ....|..6.| CLK_000_N_SYNC_5_ + 44| 6|NOD| . |=> ....|.5..| CLK_000_N_SYNC_6_ + 45| 5|NOD| . |=> 0...|....| CLK_000_N_SYNC_7_ + 46| 0|NOD| . |=> 0...|....| CLK_000_N_SYNC_8_ + 47| 0|NOD| . |=> ....|...7| CLK_000_N_SYNC_9_ + 48| 4|NOD| . |=> .1..|....| CLK_000_P_SYNC_0_ + 49| 1|NOD| . |=> ....|..6.| CLK_000_P_SYNC_1_ + 50| 6|NOD| . |=> ....|4...| CLK_000_P_SYNC_2_ + 51| 4|NOD| . |=> ....|..6.| CLK_000_P_SYNC_3_ + 52| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_4_ + 53| 6|NOD| . |=> 0...|....| CLK_000_P_SYNC_5_ + 54| 0|NOD| . |=> .1..|....| CLK_000_P_SYNC_6_ + 55| 1|NOD| . |=> ....|..6.| CLK_000_P_SYNC_7_ + 56| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_8_ + 57| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_9_ + 58| +|INP| 64|=> 0...|...7| CLK_030 + 59| 6|OUT| 65|=> ....|....| CLK_DIV_OUT + 60| 1|OUT| 10|=> ....|....| CLK_EXP + 61| +|Cin| 61|=> ....|....| CLK_OSZI + 62| 1|NOD| . |=> 012.|....| CYCLE_DMA_0_ + 63| 2|NOD| . |=> 0.2.|....| CYCLE_DMA_1_ + 64| 7| IO| 81|=> ....|....| DSACK1 |=> Paired w/: RN_DSACK1 - 63| 0|OUT| 98|=> ....|....| DS_030 - 64| 3|INP| 30|=> .1..|....| DTACK - 65| 6|OUT| 66|=> ....|....| E - 66| 5|INP| 57|=> ..2.|4..7| FC_0_ - 67| 5|INP| 58|=> ..2.|4..7| FC_1_ - 68| 7|OUT| 78|=> ....|....| FPU_CS - 69| 0|INP| 91|=> ....|4..7| FPU_SENSE - 70| 1| IO| 8|=> ....|....| IPL_030_0_ + 65| 0|OUT| 98|=> ....|....| DS_030 + 66| 3|INP| 30|=> .1..|....| DTACK + 67| 6|OUT| 66|=> ....|....| E + 68| 5|INP| 57|=> ..2.|4..7| FC_0_ + 69| 5|INP| 58|=> ..2.|4..7| FC_1_ + 70| 7|OUT| 78|=> ....|....| FPU_CS + 71| 0|INP| 91|=> ....|4..7| FPU_SENSE + 72| 1| IO| 8|=> ....|....| IPL_030_0_ |=> Paired w/: RN_IPL_030_0_ - 71| 1| IO| 7|=> ....|....| IPL_030_1_ + 73| 1| IO| 7|=> ....|....| IPL_030_1_ |=> Paired w/: RN_IPL_030_1_ - 72| 1| IO| 9|=> ....|....| IPL_030_2_ + 74| 1| IO| 9|=> ....|....| IPL_030_2_ |=> Paired w/: RN_IPL_030_2_ - 73| 6|INP| 67|=> .1..|..6.| IPL_0_ - 74| 5|INP| 56|=> .1.3|....| IPL_1_ - 75| 6|INP| 68|=> .1..|....| IPL_2_ - 76| 6|NOD| . |=> .1..|....| IPL_D0_0_ - 77| 3|NOD| . |=> .1..|....| IPL_D0_1_ - 78| 1|NOD| . |=> .1..|....| IPL_D0_2_ - 79| 3| IO| 31|=> 0...|..6.| LDS_000 - 80| 5|NOD| . |=> ....|.5..| N_317_i - 81| 1|OUT| 3|=> ....|....| RESET - 82| 6|NOD| . |=> ....|..6.| RN_A0 + 75| 6|INP| 67|=> .1..|..6.| IPL_0_ + 76| 5|INP| 56|=> .1.3|....| IPL_1_ + 77| 6|INP| 68|=> .1..|....| IPL_2_ + 78| 6|NOD| . |=> .1..|....| IPL_D0_0_ + 79| 3|NOD| . |=> .1..|....| IPL_D0_1_ + 80| 1|NOD| . |=> .1..|....| IPL_D0_2_ + 81| 3| IO| 31|=> 0...|..6.| LDS_000 + 82| 5|NOD| . |=> ....|.5..| N_317_i + 83| 1|OUT| 3|=> ....|....| RESET + 84| 6|NOD| . |=> ....|..6.| RN_A0 |=> Paired w/: A0 - 83| 7|NOD| . |=> 0123|4.67| RN_BGACK_030 + 85| 7|NOD| . |=> 0123|4.67| RN_BGACK_030 |=> Paired w/: BGACK_030 - 84| 3|NOD| . |=> ...3|....| RN_BG_000 + 86| 3|NOD| . |=> ...3|....| RN_BG_000 |=> Paired w/: BG_000 - 85| 7|NOD| . |=> ....|...7| RN_DSACK1 + 87| 7|NOD| . |=> ....|...7| RN_DSACK1 |=> Paired w/: DSACK1 - 86| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + 88| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ |=> Paired w/: IPL_030_0_ - 87| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + 89| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ |=> Paired w/: IPL_030_1_ - 88| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + 90| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ |=> Paired w/: IPL_030_2_ - 89| 6|NOD| . |=> ....|..6.| RN_RW + 91| 6|NOD| . |=> ....|..6.| RN_RW |=> Paired w/: RW - 90| 7|NOD| . |=> ....|...7| RN_RW_000 + 92| 7|NOD| . |=> ....|...7| RN_RW_000 |=> Paired w/: RW_000 - 91| 3|NOD| . |=> ...3|.5..| RN_VMA + 93| 3|NOD| . |=> ...3|.5..| RN_VMA |=> Paired w/: VMA - 92| +|INP| 86|=> 0123|.567| RST - 93| 3|NOD| . |=> ...3|....| RST_DLY_0_ - 94| 3|NOD| . |=> ...3|....| RST_DLY_1_ - 95| 3|NOD| . |=> ...3|....| RST_DLY_2_ - 96| 6| IO| 71|=> ..2.|...7| RW + 94| +|INP| 86|=> 0123|.567| RST + 95| 3|NOD| . |=> ...3|....| RST_DLY_0_ + 96| 3|NOD| . |=> ...3|....| RST_DLY_1_ + 97| 3|NOD| . |=> ...3|....| RST_DLY_2_ + 98| 6| IO| 71|=> ..2.|...7| RW |=> Paired w/: RN_RW - 97| 7| IO| 80|=> 0...|4.6.| RW_000 + 99| 7| IO| 80|=> 0...|4.6.| RW_000 |=> Paired w/: RN_RW_000 - 98| 6| IO| 70|=> 0...|....| SIZE_0_ - 99| 7| IO| 79|=> 0...|....| SIZE_1_ - 100| 6|NOD| . |=> ....|..67| SIZE_DMA_0_ - 101| 6|NOD| . |=> ....|..67| SIZE_DMA_1_ - 102| 5|NOD| . |=> ..2.|.5.7| SM_AMIGA_0_ - 103| 5|NOD| . |=> ....|.5.7| SM_AMIGA_1_ - 104| 5|NOD| . |=> ....|.5..| SM_AMIGA_2_ - 105| 5|NOD| . |=> ....|.5..| SM_AMIGA_3_ - 106| 5|NOD| . |=> ..2.|.5..| SM_AMIGA_4_ - 107| 5|NOD| . |=> ..2.|.5.7| SM_AMIGA_5_ - 108| 5|NOD| . |=> 0.2.|.5..| SM_AMIGA_6_ - 109| 5|NOD| . |=> ..23|.5.7| SM_AMIGA_i_7_ - 110| 3| IO| 32|=> 0...|..6.| UDS_000 - 111| 3| IO| 35|=> ....|....| VMA + 100| 6| IO| 70|=> 0...|....| SIZE_0_ + 101| 7| IO| 79|=> 0...|....| SIZE_1_ + 102| 6|NOD| . |=> ....|..67| SIZE_DMA_0_ + 103| 6|NOD| . |=> ....|..67| SIZE_DMA_1_ + 104| 5|NOD| . |=> ..2.|.5.7| SM_AMIGA_0_ + 105| 5|NOD| . |=> ....|.5.7| SM_AMIGA_1_ + 106| 5|NOD| . |=> ....|.5..| SM_AMIGA_2_ + 107| 5|NOD| . |=> ....|.5..| SM_AMIGA_3_ + 108| 5|NOD| . |=> ..2.|.5..| SM_AMIGA_4_ + 109| 5|NOD| . |=> ..2.|.5.7| SM_AMIGA_5_ + 110| 5|NOD| . |=> 0.2.|.5..| SM_AMIGA_6_ + 111| 5|NOD| . |=> ..23|.5.7| SM_AMIGA_i_7_ + 112| 3| IO| 32|=> 0...|..6.| UDS_000 + 113| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 112| +|INP| 36|=> ....|.5..| VPA - 113| 3|NOD| . |=> ...3|.5..| cpu_est_0_ - 114| 3|NOD| . |=> ...3|.56.| cpu_est_1_ - 115| 3|NOD| . |=> ...3|.56.| cpu_est_2_ - 116| 5|NOD| . |=> ...3|.56.| cpu_est_3_ - 117| 1|NOD| . |=> .1.3|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH - 118| 1|NOD| . |=> .12.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW - 119| 0|NOD| . |=> 0...|...7| inst_AS_000_DMA - 120| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT - 121| 2|NOD| . |=> ..2.|.5..| inst_AS_030_000_SYNC - 122| 7|NOD| . |=> ..23|4..7| inst_AS_030_D0 - 123| 7|NOD| . |=> .12.|..6.| inst_BGACK_030_INT_D - 124| 1|NOD| . |=> ...3|45..| inst_CLK_000_D0 - 125| 4|NOD| . |=> ....|45..| inst_CLK_000_D1 + 114| +|INP| 36|=> ....|.5..| VPA + 115| 3|NOD| . |=> ...3|.5..| cpu_est_0_ + 116| 3|NOD| . |=> ...3|.56.| cpu_est_1_ + 117| 3|NOD| . |=> ...3|.56.| cpu_est_2_ + 118| 5|NOD| . |=> ...3|.56.| cpu_est_3_ + 119| 1|NOD| . |=> .1.3|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH + 120| 1|NOD| . |=> .12.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW + 121| 0|NOD| . |=> 0...|...7| inst_AS_000_DMA + 122| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT + 123| 2|NOD| . |=> ..2.|.5..| inst_AS_030_000_SYNC + 124| 7|NOD| . |=> ..23|4..7| inst_AS_030_D0 + 125| 7|NOD| . |=> .12.|..6.| inst_BGACK_030_INT_D 126| 6|NOD| . |=> ...3|.5..| inst_CLK_000_NE 127| 3|NOD| . |=> ...3|.5..| inst_CLK_000_NE_D0 128| 6|NOD| . |=> .123|.5.7| inst_CLK_000_PE @@ -219,7 +219,7 @@ ___|__|__|____|____________________________________________________________ 140| +|INP| 14|=> 0...|....| nEXP_SPACE --------------------------------------------------------------------------- =========================================================================== - < C:/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments > + < E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a Device Pin Assignments > =========================================================================== +- Device Pin No | Pin Type +- Signal Fixed (*) @@ -549,7 +549,7 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 6|CLK_000_N_SYNC_4_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7|CLK_000_P_SYNC_1_|NOD| | S | 1 | 4 to [ 5]| 1 XOR to [ 7] for 1 PT sig 8| IPL_030_0_| IO| | S |10 | 4 to [ 8]| 1 XOR to [ 8] as logic PT - 9|inst_CLK_000_D0|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig + 9| CLK_000_D_0_|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig 10|CLK_000_N_SYNC_3_|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [10] for 1 PT sig 11| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig 12| IPL_030_1_| IO| | S |10 | 4 to [12]| 1 XOR to [12] as logic PT @@ -576,7 +576,7 @@ _|_________________|__|__|___|_____|_______________________________________ 6|CLK_000_N_SYNC_4_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) 7|CLK_000_P_SYNC_1_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) 8| IPL_030_0_| IO| | S |10 |=> can support up to [ 13] logic PT(s) - 9|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 9| CLK_000_D_0_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) 10|CLK_000_N_SYNC_3_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) 11| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) 12| IPL_030_1_| IO| | S |10 |=> can support up to [ 18] logic PT(s) @@ -601,7 +601,7 @@ _|_________________|__|_____|____________________|________________________ 6|CLK_000_N_SYNC_4_|NOD| | => | 0 1 2 3 | 10 9 8 7 7|CLK_000_P_SYNC_1_|NOD| | => | 0 1 2 3 | 10 9 8 7 8| IPL_030_0_| IO| | => | 1 ( 2) 3 4 | 9 ( 8) 7 6 - 9|inst_CLK_000_D0|NOD| | => | 1 2 3 4 | 9 8 7 6 + 9| CLK_000_D_0_|NOD| | => | 1 2 3 4 | 9 8 7 6 10|CLK_000_N_SYNC_3_|NOD| | => | 2 3 4 5 | 8 7 6 5 11| IPL_D0_2_|NOD| | => | 2 3 4 5 | 8 7 6 5 12| IPL_030_1_| IO| | => |( 3) 4 5 6 |( 7) 6 5 4 @@ -680,7 +680,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 6|INP A_29_|*|*] [RegIn 4 |138| -| | ] [MCell 8 |137|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] - [MCell 9 |139|NOD inst_CLK_000_D0| |*] + [MCell 9 |139|NOD CLK_000_D_0_| |*] 5 [IOpin 5 | 5|INP A_30_|*|*] [RegIn 5 |141| -| | ] @@ -1119,7 +1119,7 @@ Mux02| Mcel 3 1 ( 175)| RN_BG_000 Mux03| Mcel 3 2 ( 176)| cpu_est_1_ Mux04| IOPin 2 6 ( 21)| BG_030 Mux05| Mcel 5 0 ( 221)| SM_AMIGA_i_7_ -Mux06| Mcel 1 9 ( 139)| inst_CLK_000_D0 +Mux06| Mcel 1 9 ( 139)| CLK_000_D_0_ Mux07| Mcel 2 8 ( 161)| inst_DS_000_ENABLE Mux08| Mcel 3 7 ( 184)| RST_DLY_2_ Mux09| Mcel 3 3 ( 178)| RST_DLY_0_ @@ -1165,7 +1165,7 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 5| CIIN_0|NOD| | S | 2 | 4 to [ 5]| 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8|inst_CLK_000_D1|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 8| CLK_000_D_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig 9|CLK_000_N_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free @@ -1192,7 +1192,7 @@ _|_________________|__|__|___|_____|_______________________________________ 5| CIIN_0|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) 6| | ? | | S | |=> can support up to [ 14] logic PT(s) 7| | ? | | S | |=> can support up to [ 18] logic PT(s) - 8|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 8| CLK_000_D_1_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) 9|CLK_000_N_SYNC_0_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) 10| | ? | | S | |=> can support up to [ 18] logic PT(s) 11| | ? | | S | |=> can support up to [ 18] logic PT(s) @@ -1217,7 +1217,7 @@ _|_________________|__|_____|____________________|________________________ 5| CIIN_0|NOD| | => | 7 0 1 2 | 48 41 42 43 6| | | | => | 0 1 2 3 | 41 42 43 44 7| | | | => | 0 1 2 3 | 41 42 43 44 - 8|inst_CLK_000_D1|NOD| | => | 1 2 3 4 | 42 43 44 45 + 8| CLK_000_D_1_|NOD| | => | 1 2 3 4 | 42 43 44 45 9|CLK_000_N_SYNC_0_|NOD| | => | 1 2 3 4 | 42 43 44 45 10| | | | => | 2 3 4 5 | 43 44 45 46 11| | | | => | 2 3 4 5 | 43 44 45 46 @@ -1293,7 +1293,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 45| -| | ] [RegIn 4 |210| -| | ] - [MCell 8 |209|NOD inst_CLK_000_D1| |*] + [MCell 8 |209|NOD CLK_000_D_1_| |*] [MCell 9 |211|NOD CLK_000_N_SYNC_0_| |*] 5 [IOpin 5 | 46| -| | ] @@ -1323,7 +1323,7 @@ Mux02| IOPin 4 1 ( 42)| AS_000 Mux03| IOPin 2 3 ( 18)| A_25_ Mux04| IOPin 3 7 ( 28)| BGACK_000 Mux05| IOPin 2 4 ( 19)| A_24_ -Mux06| Mcel 1 9 ( 139)| inst_CLK_000_D0 +Mux06| Mcel 1 9 ( 139)| CLK_000_D_0_ Mux07| IOPin 2 0 ( 15)| A_28_ Mux08| Mcel 6 7 ( 256)| CLK_000_P_SYNC_2_ Mux09| IOPin 7 1 ( 84)| A_22_ @@ -1333,7 +1333,7 @@ Mux12| IOPin 0 6 ( 97)| A_19_ Mux13| IOPin 1 4 ( 6)| A_29_ Mux14| Mcel 4 5 ( 205)| CIIN_0 Mux15| IOPin 0 3 ( 94)| A_21_ -Mux16| Mcel 4 8 ( 209)| inst_CLK_000_D1 +Mux16| Mcel 4 8 ( 209)| CLK_000_D_1_ Mux17| IOPin 2 2 ( 17)| A_26_ Mux18| IOPin 7 0 ( 85)| A_23_ Mux19| IOPin 1 5 ( 5)| A_30_ @@ -1529,7 +1529,7 @@ Mux04| Mcel 6 2 ( 248)| inst_CLK_000_NE Mux05| Mcel 6 6 ( 254)| CLK_000_N_SYNC_6_ Mux06| Mcel 5 13 ( 241)| inst_CLK_OUT_PRE_50 Mux07| ... | ... -Mux08| Mcel 4 8 ( 209)| inst_CLK_000_D1 +Mux08| Mcel 4 8 ( 209)| CLK_000_D_1_ Mux09| Mcel 5 2 ( 224)| inst_VPA_D Mux10| Mcel 5 4 ( 227)| SM_AMIGA_6_ Mux11| Mcel 5 6 ( 230)| SM_AMIGA_3_ @@ -1552,7 +1552,7 @@ Mux27| ... | ... Mux28| ... | ... Mux29| Mcel 2 4 ( 155)| inst_AS_030_000_SYNC Mux30| Mcel 3 6 ( 182)| cpu_est_0_ -Mux31| Mcel 1 9 ( 139)| inst_CLK_000_D0 +Mux31| Mcel 1 9 ( 139)| CLK_000_D_0_ Mux32| Mcel 5 8 ( 233)| SM_AMIGA_5_ --------------------------------------------------------------------------- =========================================================================== diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index 6ee7b7d..d9cdde2 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -1,6 +1,6 @@ |--------------------------------------------| |- ispLEVER Fitter Report File -| -|- Version 1.8.00.04.29.14 -| +|- Version 2.0.00.17.20.15 -| |- (c)Copyright, Lattice Semiconductor 2002 -| |--------------------------------------------| @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic -Project Fitted on : Wed Jan 27 21:56:53 2016 +Project Fitted on : Wed Aug 17 17:45:51 2016 Device : M4A5-128/64 Package : 100TQFP @@ -394,6 +394,8 @@ Buried_Signal_List #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- E5 E 2 COM ----E--- Low Slow CIIN_0 + B9 B 1 DFF * * ---DEF-- Low Slow CLK_000_D_0_ + E8 E 1 DFF * * ----EF-- Low Slow CLK_000_D_1_ E9 E 1 DFF * * A------- Low Slow CLK_000_N_SYNC_0_ H2 H 1 DFF * * -------H Low Slow CLK_000_N_SYNC_10_ H6 H 1 DFF * * ------G- Low Slow CLK_000_N_SYNC_11_ @@ -456,8 +458,6 @@ Buried_Signal_List C4 C 7 DFF * * --C--F-- Low Slow inst_AS_030_000_SYNC H3 H 1 DFF * * --CDE--H Low Slow inst_AS_030_D0 H13 H 1 DFF * * -BC---G- Low Slow inst_BGACK_030_INT_D - B9 B 1 DFF * * ---DEF-- Low Slow inst_CLK_000_D0 - E8 E 1 DFF * * ----EF-- Low Slow inst_CLK_000_D1 G2 G 1 DFF * * ---D-F-- Low Slow inst_CLK_000_NE D10 D 1 DFF * * ---D-F-- Low Slow inst_CLK_000_NE_D0 G5 G 1 DFF * * -BCD-F-H Low Slow inst_CLK_000_PE @@ -515,7 +515,7 @@ Signal Source : Fanout List BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H} CLK_030{. }: DSACK1{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} : inst_CLK_030_H{ A} - CLK_000{. }:inst_CLK_000_D0{ B} + CLK_000{. }: CLK_000_D_0_{ B} FPU_SENSE{ B}: BERR{ E} FPU_CS{ H} DTACK{ E}: inst_DTACK_D0{ B} VPA{. }: inst_VPA_D{ F} @@ -621,9 +621,9 @@ inst_RESET_OUT{ E}: AS_030{ H} AS_000{ E} DS_030{ A} : RW_000{ H} A0{ G} RW{ G} : inst_RESET_OUT{ D} inst_CLK_OUT_PRE_50{ G}:inst_CLK_OUT_PRE_D{ A}inst_CLK_OUT_PRE_50{ F} -inst_CLK_000_D1{ F}: N_317_i{ F}CLK_000_P_SYNC_0_{ E}CLK_000_N_SYNC_0_{ E} +CLK_000_D_1_{ F}: N_317_i{ F}CLK_000_P_SYNC_0_{ E}CLK_000_N_SYNC_0_{ E} : SM_AMIGA_6_{ F} -inst_CLK_000_D0{ C}: BG_000{ D} N_317_i{ F}inst_CLK_000_D1{ E} +CLK_000_D_0_{ C}: BG_000{ D} N_317_i{ F} CLK_000_D_1_{ E} :CLK_000_P_SYNC_0_{ E}CLK_000_N_SYNC_0_{ E} SM_AMIGA_6_{ F} inst_CLK_000_PE{ H}: RW_000{ H} BGACK_030{ H} VMA{ D} : SM_AMIGA_5_{ F} CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ C} @@ -736,7 +736,7 @@ Equations : | * | S | BS | BR | CLK_EXP | | | | | RESET | * | S | BS | BR | CYCLE_DMA_0_ -| * | S | BS | BR | inst_CLK_000_D0 +| * | S | BS | BR | CLK_000_D_0_ | * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH | * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW | * | S | BS | BR | RN_IPL_030_0_ @@ -814,7 +814,7 @@ Equations : | | | | | BERR | | | | | AMIGA_BUS_DATA_DIR | | | | | CIIN -| * | S | BS | BR | inst_CLK_000_D1 +| * | S | BS | BR | CLK_000_D_1_ | | | | | CIIN_0 | * | S | BS | BR | CLK_000_N_SYNC_0_ | * | S | BS | BR | CLK_000_P_SYNC_3_ @@ -993,7 +993,7 @@ mx D2 RN_BG_000 mcell D1 mx D19inst_UDS_000_INT mcell A9 mx D3 cpu_est_1_ mcell D2 mx D20inst_CLK_000_NE_D0 mcell D10 mx D4 BG_030 pin 21 mx D21 RST pin 86 mx D5 SM_AMIGA_i_7_ mcell F0 mx D22 inst_CLK_000_PE mcell G5 -mx D6 inst_CLK_000_D0 mcell B9 mx D23 inst_CLK_000_NE mcell G2 +mx D6 CLK_000_D_0_ mcell B9 mx D23 inst_CLK_000_NE mcell G2 mx D7inst_DS_000_ENABLE mcell C8 mx D24 ... ... mx D8 RST_DLY_2_ mcell D7 mx D25 ... ... mx D9 RST_DLY_0_ mcell D3 mx D26 RN_VMA mcell D0 @@ -1017,7 +1017,7 @@ mx E2 AS_000 pin 42 mx E19 A_30_ pin 5 mx E3 A_25_ pin 18 mx E20 FC_1_ pin 58 mx E4 BGACK_000 pin 28 mx E21 A_27_ pin 16 mx E5 A_24_ pin 19 mx E22 inst_AS_000_INT mcell C1 -mx E6 inst_CLK_000_D0 mcell B9 mx E23 ... ... +mx E6 CLK_000_D_0_ mcell B9 mx E23 ... ... mx E7 A_28_ pin 15 mx E24 FC_0_ pin 57 mx E8CLK_000_P_SYNC_2_ mcell G7 mx E25 inst_RESET_OUT mcell D9 mx E9 A_22_ pin 84 mx E26 A_16_ pin 96 @@ -1027,7 +1027,7 @@ mx E12 A_19_ pin 97 mx E29 A_20_ pin 93 mx E13 A_29_ pin 6 mx E30inst_nEXP_SPACE_D0reg mcell A8 mx E14 CIIN_0 mcell E5 mx E31 A_18_ pin 95 mx E15 A_21_ pin 94 mx E32 AS_030 pin 82 -mx E16 inst_CLK_000_D1 mcell E8 +mx E16 CLK_000_D_1_ mcell E8 ---------------------------------------------------------------------------- @@ -1043,13 +1043,13 @@ mx F4 inst_CLK_000_NE mcell G2 mx F21 cpu_est_2_ mcell D13 mx F5CLK_000_N_SYNC_6_ mcell G6 mx F22 inst_CLK_000_PE mcell G5 mx F6inst_CLK_OUT_PRE_50 mcell F13 mx F23 ... ... mx F7 ... ... mx F24 N_317_i mcell F14 -mx F8 inst_CLK_000_D1 mcell E8 mx F25 SM_AMIGA_i_7_ mcell F0 +mx F8 CLK_000_D_1_ mcell E8 mx F25 SM_AMIGA_i_7_ mcell F0 mx F9 inst_VPA_D mcell F2 mx F26 RN_VMA mcell D0 mx F10 SM_AMIGA_6_ mcell F4 mx F27 ... ... mx F11 SM_AMIGA_3_ mcell F6 mx F28 ... ... mx F12 ... ... mx F29inst_AS_030_000_SYNC mcell C4 mx F13 VPA pin 36 mx F30 cpu_est_0_ mcell D6 -mx F14 SM_AMIGA_1_ mcell F5 mx F31 inst_CLK_000_D0 mcell B9 +mx F14 SM_AMIGA_1_ mcell F5 mx F31 CLK_000_D_0_ mcell B9 mx F15 SM_AMIGA_0_ mcell F1 mx F32 SM_AMIGA_5_ mcell F8 mx F16 cpu_est_1_ mcell D2 ---------------------------------------------------------------------------- @@ -1218,10 +1218,10 @@ PostFit_Equations 1 1 1 Node inst_RESET_OUT.C 1 1 1 Node inst_CLK_OUT_PRE_50.D 1 1 1 Node inst_CLK_OUT_PRE_50.C - 1 1 1 Node inst_CLK_000_D1.D - 1 1 1 Node inst_CLK_000_D1.C - 1 1 1 Node inst_CLK_000_D0.D - 1 1 1 Node inst_CLK_000_D0.C + 1 1 1 Node CLK_000_D_1_.D + 1 1 1 Node CLK_000_D_1_.C + 1 1 1 Node CLK_000_D_0_.D + 1 1 1 Node CLK_000_D_0_.C 1 1 1 Node inst_CLK_000_PE.D 1 1 1 Node inst_CLK_000_PE.C 1 1 1 Node CLK_000_P_SYNC_9_.D @@ -1431,7 +1431,7 @@ A0.D = (!RST A0.C = (CLK_OSZI); !BG_000.D = (!BG_030 & RST & !BG_000.Q - # !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_CLK_000_D0.Q); + # !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & CLK_000_D_0_.Q); BG_000.C = (CLK_OSZI); @@ -1469,8 +1469,8 @@ RW.C = (CLK_OSZI); !N_317_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q); + # !SM_AMIGA_5_.Q & !CLK_000_D_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & CLK_000_D_0_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q); cpu_est_2_.D = (cpu_est_2_.Q & !cpu_est_0_.Q # cpu_est_2_.Q & !cpu_est_1_.Q @@ -1611,13 +1611,13 @@ inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_50.C = (CLK_OSZI); -inst_CLK_000_D1.D = (inst_CLK_000_D0.Q); +CLK_000_D_1_.D = (CLK_000_D_0_.Q); -inst_CLK_000_D1.C = (CLK_OSZI); +CLK_000_D_1_.C = (CLK_OSZI); -inst_CLK_000_D0.D = (CLK_000); +CLK_000_D_0_.D = (CLK_000); -inst_CLK_000_D0.C = (CLK_OSZI); +CLK_000_D_0_.C = (CLK_OSZI); inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q); @@ -1693,7 +1693,7 @@ RST_DLY_2_.D = (RST & RST_DLY_2_.Q RST_DLY_2_.C = (CLK_OSZI); -CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q); +CLK_000_P_SYNC_0_.D = (!CLK_000_D_1_.Q & CLK_000_D_0_.Q); CLK_000_P_SYNC_0_.C = (CLK_OSZI); @@ -1729,7 +1729,7 @@ CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q); CLK_000_P_SYNC_8_.C = (CLK_OSZI); -CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q); +CLK_000_N_SYNC_0_.D = (CLK_000_D_1_.Q & !CLK_000_D_0_.Q); CLK_000_N_SYNC_0_.C = (CLK_OSZI); @@ -1775,7 +1775,7 @@ CLK_000_N_SYNC_10_.C = (CLK_OSZI); SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q # RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN - # RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & !SM_AMIGA_i_7_.Q); + # RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_6_.C = (CLK_OSZI); diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index a71d207..3123d42 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -50,8 +50,8 @@ inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2 SIZE_DMA_1_ 1 1 1 1 .. .. 2 2 inst_UDS_000_INT 1 1 1 1 .. .. 2 2 inst_LDS_000_INT 1 1 1 1 .. .. 2 2 - inst_CLK_000_D1 .. .. .. .. .. .. 1 2 - inst_CLK_000_D0 1 1 .. .. .. .. 1 2 + CLK_000_D_1_ .. .. .. .. .. .. 1 2 + CLK_000_D_0_ 1 1 .. .. .. .. 1 2 SM_AMIGA_0_ 1 1 .. .. .. .. 1 2 SM_AMIGA_4_ 1 1 .. .. .. .. 1 2 inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2 diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index 198e000..006ff1c 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,13 +1,13 @@ -#$ TOOL ispLEVER Classic 1.8.00.04.29.14 -#$ DATE Wed Jan 27 21:56:48 2016 +#$ TOOL ispLEVER Classic 2.0.00.17.20.15 +#$ DATE Wed Aug 17 17:45:46 2016 #$ MODULE 68030_tk #$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW -#$ NODES 68 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ +#$ NODES 68 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ .type fr .i 120 .o 190 -.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN -.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C RST_DLY_0_.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C A0.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_000_D0.C inst_CLK_000_PE.C inst_CLK_000_NE.C SIZE_1_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D inst_CLK_000_D1.D inst_CLK_000_D0.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D +.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN +.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C RST_DLY_0_.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C A0.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_000_PE.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D .p 554 ------------------------------------------------------------------------------------------------------------------------ ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -1---------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index 7cdffd1..8a26ce8 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,13 +1,13 @@ -#$ TOOL ispLEVER Classic 1.8.00.04.29.14 -#$ DATE Wed Jan 27 21:56:48 2016 +#$ TOOL ispLEVER Classic 2.0.00.17.20.15 +#$ DATE Wed Aug 17 17:45:46 2016 #$ MODULE 68030_tk #$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW -#$ NODES 68 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ +#$ NODES 68 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ .type fr .i 120 .o 190 -.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN -.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C RST_DLY_0_.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C A0.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_000_D0.C inst_CLK_000_PE.C inst_CLK_000_NE.C SIZE_1_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D inst_CLK_000_D1.D inst_CLK_000_D0.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D +.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN +.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C RST_DLY_0_.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C A0.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_000_PE.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D .p 554 ------------------------------------------------------------------------------------------------------------------------ ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -1---------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index 62db5d8..46beba7 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,5 +1,5 @@ -#$ TOOL ispLEVER Classic 1.8.00.04.29.14 -#$ DATE Wed Jan 27 21:56:48 2016 +#$ TOOL ispLEVER Classic 2.0.00.17.20.15 +#$ DATE Wed Aug 17 17:45:46 2016 #$ MODULE BUS68030 #$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI @@ -13,17 +13,16 @@ inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT - inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE - CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ - IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH - SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ - CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ - CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ - CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ - CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ - CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ - SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ - CIIN_0 + inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_ + inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ + inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ + inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ + CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ + CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ + CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ + CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ + CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ + inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0 .type f .i 121 .o 191 @@ -36,7 +35,7 @@ inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q - inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q + CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q @@ -68,10 +67,10 @@ inst_UDS_000_INT.D% inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D% inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C - inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D0.D inst_CLK_000_D0.C - inst_CLK_000_PE.D inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C - inst_CLK_000_NE.D inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C - IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C + CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_000_PE.D + inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D + inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C IPL_D0_0_.D% + IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_4_.D SM_AMIGA_4_.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C RST_DLY_0_.D diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index 392ef7e..e6d1891 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,5 +1,5 @@ -#$ TOOL ispLEVER Classic 1.8.00.04.29.14 -#$ DATE Wed Jan 27 21:56:48 2016 +#$ TOOL ispLEVER Classic 2.0.00.17.20.15 +#$ DATE Wed Aug 17 17:45:46 2016 #$ MODULE BUS68030 #$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI @@ -13,17 +13,16 @@ inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT - inst_CLK_OUT_PRE_50 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE - CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ - IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH - SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ - CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ - CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ - CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ - CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ - CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ - SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ - CIIN_0 + inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_ + inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ + inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ + inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ + CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ + CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ + CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ + CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ + CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ + inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0 .type f .i 121 .o 191 @@ -36,7 +35,7 @@ inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q - inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q + CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q @@ -68,10 +67,10 @@ inst_UDS_000_INT.D- inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C - inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D0.D inst_CLK_000_D0.C - inst_CLK_000_PE.D inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C - inst_CLK_000_NE.D inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C - IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C + CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_000_PE.D + inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D + inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C IPL_D0_0_.D- + IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_4_.D SM_AMIGA_4_.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C RST_DLY_0_.D diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index 7dd1faf..c964397 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 1/27/16; -TIME = 21:56:53; +DATE = 8/17/16; +TIME = 17:45:51; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -178,7 +178,7 @@ cpu_est_1_ = NODE,*,3,-; cpu_est_3_ = NODE,*,5,-; SM_AMIGA_0_ = NODE,*,5,-; CYCLE_DMA_0_ = NODE,*,1,-; -inst_CLK_000_D0 = NODE,*,1,-; +CLK_000_D_0_ = NODE,*,1,-; inst_CLK_OUT_PRE_D = NODE,*,0,-; inst_BGACK_030_INT_D = NODE,*,7,-; inst_AS_000_DMA = NODE,*,0,-; @@ -198,7 +198,7 @@ inst_AS_000_INT = NODE,*,2,-; cpu_est_0_ = NODE,*,3,-; inst_CLK_000_NE_D0 = NODE,*,3,-; inst_CLK_000_NE = NODE,*,6,-; -inst_CLK_000_D1 = NODE,*,4,-; +CLK_000_D_1_ = NODE,*,4,-; inst_CLK_OUT_PRE_50 = NODE,*,5,-; inst_VPA_D = NODE,*,5,-; RN_IPL_030_0_ = NODE,-1,1,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index 5d689f2..9525a33 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 1/27/16; -TIME = 21:56:53; +DATE = 8/17/16; +TIME = 17:45:51; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -222,8 +222,8 @@ inst_CLK_OUT_PRE_D = NODE,12, A,-; inst_DTACK_D0 = NODE,15, B,-; inst_RESET_OUT = NODE,9, D,-; inst_CLK_OUT_PRE_50 = NODE,13, F,-; -inst_CLK_000_D1 = NODE,8, E,-; -inst_CLK_000_D0 = NODE,9, B,-; +CLK_000_D_1_ = NODE,8, E,-; +CLK_000_D_0_ = NODE,9, B,-; inst_CLK_000_PE = NODE,5, G,-; CLK_000_P_SYNC_9_ = NODE,15, G,-; inst_CLK_000_NE = NODE,2, G,-; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index 4c24b29..6389c2e 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -1,8 +1,8 @@ Signal Name Cross Reference File -ispLEVER Classic 1.8.00.04.29.14 +ispLEVER Classic 2.0.00.17.20.15 -Design '68030_tk' created Wed Jan 27 21:56:48 2016 +Design '68030_tk' created Wed Aug 17 17:45:46 2016 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index bc705a2..79f04b4 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,4 +1,4 @@ -#$ DATE Wed Jan 27 21:56:48 2016 +#$ DATE Wed Aug 17 17:45:46 2016 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 #$ PINS 75 A_8_ A_7_ SIZE_1_ A_6_ A_5_ A_31_ A_4_ A_3_ IPL_030_2_ A_2_ IPL_030_1_ IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_15_ A_14_ A_13_ A_12_ A_11_ A_10_ A_9_ @@ -18,14 +18,14 @@ # SIZE_DMA_0_ sm_amiga_i_4__n N_197_i as_000_dma_0_un1_n SIZE_DMA_1_ FPU_SENSE_i N_196_i as_000_dma_0_un0_n inst_VPA_D AS_030_i \ # N_193_i lds_000_int_0_un3_n inst_UDS_000_INT AS_030_D0_i N_192_0 lds_000_int_0_un1_n inst_LDS_000_INT a_i_24__n clk_000_n_sync_i_10__n lds_000_int_0_un0_n \ # inst_CLK_OUT_PRE_D sm_amiga_i_3__n N_350_i rw_000_dma_0_un3_n inst_DTACK_D0 cpu_est_i_0__n N_188_0 rw_000_dma_0_un1_n inst_RESET_OUT cpu_est_i_3__n \ -# N_187_i rw_000_dma_0_un0_n inst_CLK_OUT_PRE_50 cpu_est_i_2__n N_185_i a_15__n inst_CLK_000_D1 cpu_est_i_1__n N_182_i inst_CLK_000_D0 \ +# N_187_i rw_000_dma_0_un0_n inst_CLK_OUT_PRE_50 cpu_est_i_2__n N_185_i a_15__n CLK_000_D_1_ cpu_est_i_1__n N_182_i CLK_000_D_0_ \ # VPA_D_i N_181_i a_14__n inst_CLK_000_PE CLK_000_NE_i CLK_OUT_PRE_D_i CLK_000_P_SYNC_9_ sm_amiga_i_1__n N_175_0 a_13__n \ # inst_CLK_000_NE rst_dly_i_2__n N_168_i CLK_000_N_SYNC_11_ CLK_030_i AS_030_000_SYNC_i a_12__n IPL_D0_0_ rst_dly_i_0__n N_158_i \ -# IPL_D0_1_ rst_dly_i_1__n CLK_000_D0_i a_11__n IPL_D0_2_ CLK_000_D1_i N_148_i inst_CLK_000_NE_D0 DTACK_D0_i N_345_i \ +# IPL_D0_1_ rst_dly_i_1__n clk_000_d_i_0__n a_11__n IPL_D0_2_ clk_000_d_i_1__n N_148_i inst_CLK_000_NE_D0 DTACK_D0_i N_345_i \ # a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i SM_AMIGA_0_ CLK_030_H_i N_144_0 a_9__n inst_AMIGA_BUS_ENABLE_DMA_HIGH sm_amiga_i_6__n \ # N_138_0 inst_DSACK1_INTreg sm_amiga_i_2__n a_8__n AS_000_i N_342_i pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n \ # SM_AMIGA_4_ A1_i N_124_0 inst_DS_000_ENABLE a_i_31__n N_341_i a_6__n RST_DLY_0_ a_i_29__n N_119_0 \ -# RST_DLY_1_ a_i_30__n N_340_i a_5__n RST_DLY_2_ a_i_27__n N_361_i pos_clk_un8_bg_030_n a_i_28__n cpu_est_2_0_2__n \ +# RST_DLY_1_ a_i_30__n N_340_i a_5__n RST_DLY_2_ a_i_27__n N_361_i pos_clk_un9_bg_030_n a_i_28__n cpu_est_2_0_2__n \ # a_4__n CLK_000_P_SYNC_0_ a_i_25__n N_338_i CLK_000_P_SYNC_1_ a_i_26__n N_339_i a_3__n CLK_000_P_SYNC_2_ N_213_i \ # cpu_est_2_0_1__n CLK_000_P_SYNC_3_ N_214_i N_332_i a_2__n CLK_000_P_SYNC_4_ N_215_i N_336_i CLK_000_P_SYNC_5_ pos_clk_un7_clk_000_pe_0_n \ # CLK_000_P_SYNC_6_ N_275_i N_99_0 CLK_000_P_SYNC_7_ un6_ds_030_i N_331_i CLK_000_P_SYNC_8_ DS_000_DMA_i N_96_0 CLK_000_N_SYNC_0_ \ @@ -42,7 +42,7 @@ # a_c_22__n N_17_i N_42_0 a_c_23__n N_19_i N_40_0 SM_AMIGA_i_7_ a_c_24__n N_20_i N_123 \ # N_39_0 cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i G_134 \ # N_37_0 G_135 a_c_27__n N_25_i G_136 N_34_0 N_217 a_c_28__n N_26_i N_33_0 \ -# N_61 a_c_29__n BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un8_bg_030_0_n N_80 N_289_0_1 a_c_31__n \ +# N_61 a_c_29__n BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 N_289_0_1 a_c_31__n \ # un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c \ # N_351_2 N_124 N_168_i_1 N_138 nEXP_SPACE_c N_192_0_1 N_144 N_192_0_2 N_158 BERR_c \ # N_137_i_1 N_168 N_137_i_2 N_175 BG_030_c N_145_i_1 N_182 N_145_i_2 N_185 BG_000DFFreg \ @@ -63,7 +63,7 @@ # rw_000_int_0_un1_n N_341 N_46_0 rw_000_int_0_un0_n N_342 N_5_i bgack_030_int_0_un3_n N_343 N_47_0 bgack_030_int_0_un1_n \ # N_344 N_4_i bgack_030_int_0_un0_n N_345 N_48_0 as_030_000_sync_0_un3_n N_347 N_272_i as_030_000_sync_0_un1_n N_350 \ # N_271_i as_030_000_sync_0_un0_n N_351 N_279_0 ds_000_enable_0_un3_n N_353 N_280_0 ds_000_enable_0_un1_n N_361 N_281_0 \ -# ds_000_enable_0_un0_n pos_clk_un24_bgack_030_int_i_i_a4_i_x2 N_298_i as_000_int_0_un3_n pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_size_dma_6_0_0__n as_000_int_0_un1_n cpu_est_0_0_x2_0_ N_299_i as_000_int_0_un0_n \ +# ds_000_enable_0_un0_n pos_clk_un23_bgack_030_int_i_i_a4_i_x2 N_298_i as_000_int_0_un3_n pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_size_dma_6_0_0__n as_000_int_0_un1_n cpu_est_0_0_x2_0_ N_299_i as_000_int_0_un0_n \ # pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk_size_dma_6_0_1__n dsack1_int_0_un3_n un22_berr_1 un1_as_000_i dsack1_int_0_un1_n N_375 N_358_i dsack1_int_0_un0_n N_218 \ # pos_clk_un6_bgack_000_0_n size_dma_0_1__un3_n N_156 N_284_i size_dma_0_1__un1_n N_289 N_285_i size_dma_0_1__un0_n N_354 N_286_0 \ # size_dma_0_0__un3_n N_205 N_88_0 size_dma_0_0__un1_n un1_SM_AMIGA_5 pos_clk_un3_as_030_d0_i_n size_dma_0_0__un0_n DS_000_ENABLE_1_sqmuxa N_156_i sm_amiga_srsts_i_0_m2_1__un3_n \ @@ -95,15 +95,15 @@ SIZE_DMA_1_.BLIF FPU_SENSE_i.BLIF N_196_i.BLIF as_000_dma_0_un0_n.BLIF inst_VPA_D.BLIF AS_030_i.BLIF N_193_i.BLIF lds_000_int_0_un3_n.BLIF inst_UDS_000_INT.BLIF \ AS_030_D0_i.BLIF N_192_0.BLIF lds_000_int_0_un1_n.BLIF inst_LDS_000_INT.BLIF a_i_24__n.BLIF clk_000_n_sync_i_10__n.BLIF lds_000_int_0_un0_n.BLIF inst_CLK_OUT_PRE_D.BLIF sm_amiga_i_3__n.BLIF \ N_350_i.BLIF rw_000_dma_0_un3_n.BLIF inst_DTACK_D0.BLIF cpu_est_i_0__n.BLIF N_188_0.BLIF rw_000_dma_0_un1_n.BLIF inst_RESET_OUT.BLIF cpu_est_i_3__n.BLIF N_187_i.BLIF \ - rw_000_dma_0_un0_n.BLIF inst_CLK_OUT_PRE_50.BLIF cpu_est_i_2__n.BLIF N_185_i.BLIF a_15__n.BLIF inst_CLK_000_D1.BLIF cpu_est_i_1__n.BLIF N_182_i.BLIF inst_CLK_000_D0.BLIF \ + rw_000_dma_0_un0_n.BLIF inst_CLK_OUT_PRE_50.BLIF cpu_est_i_2__n.BLIF N_185_i.BLIF a_15__n.BLIF CLK_000_D_1_.BLIF cpu_est_i_1__n.BLIF N_182_i.BLIF CLK_000_D_0_.BLIF \ VPA_D_i.BLIF N_181_i.BLIF a_14__n.BLIF inst_CLK_000_PE.BLIF CLK_000_NE_i.BLIF CLK_OUT_PRE_D_i.BLIF CLK_000_P_SYNC_9_.BLIF sm_amiga_i_1__n.BLIF N_175_0.BLIF \ a_13__n.BLIF inst_CLK_000_NE.BLIF rst_dly_i_2__n.BLIF N_168_i.BLIF CLK_000_N_SYNC_11_.BLIF CLK_030_i.BLIF AS_030_000_SYNC_i.BLIF a_12__n.BLIF IPL_D0_0_.BLIF \ - rst_dly_i_0__n.BLIF N_158_i.BLIF IPL_D0_1_.BLIF rst_dly_i_1__n.BLIF CLK_000_D0_i.BLIF a_11__n.BLIF IPL_D0_2_.BLIF CLK_000_D1_i.BLIF N_148_i.BLIF \ + rst_dly_i_0__n.BLIF N_158_i.BLIF IPL_D0_1_.BLIF rst_dly_i_1__n.BLIF clk_000_d_i_0__n.BLIF a_11__n.BLIF IPL_D0_2_.BLIF clk_000_d_i_1__n.BLIF N_148_i.BLIF \ inst_CLK_000_NE_D0.BLIF DTACK_D0_i.BLIF N_345_i.BLIF a_10__n.BLIF pos_clk_un6_bg_030_n.BLIF RW_000_i.BLIF N_344_i.BLIF SM_AMIGA_0_.BLIF CLK_030_H_i.BLIF \ N_144_0.BLIF a_9__n.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF sm_amiga_i_6__n.BLIF N_138_0.BLIF inst_DSACK1_INTreg.BLIF sm_amiga_i_2__n.BLIF a_8__n.BLIF AS_000_i.BLIF \ N_342_i.BLIF pos_clk_ipl_n.BLIF sm_amiga_i_0__n.BLIF N_343_i.BLIF a_7__n.BLIF SM_AMIGA_4_.BLIF A1_i.BLIF N_124_0.BLIF inst_DS_000_ENABLE.BLIF \ a_i_31__n.BLIF N_341_i.BLIF a_6__n.BLIF RST_DLY_0_.BLIF a_i_29__n.BLIF N_119_0.BLIF RST_DLY_1_.BLIF a_i_30__n.BLIF N_340_i.BLIF \ - a_5__n.BLIF RST_DLY_2_.BLIF a_i_27__n.BLIF N_361_i.BLIF pos_clk_un8_bg_030_n.BLIF a_i_28__n.BLIF cpu_est_2_0_2__n.BLIF a_4__n.BLIF CLK_000_P_SYNC_0_.BLIF \ + a_5__n.BLIF RST_DLY_2_.BLIF a_i_27__n.BLIF N_361_i.BLIF pos_clk_un9_bg_030_n.BLIF a_i_28__n.BLIF cpu_est_2_0_2__n.BLIF a_4__n.BLIF CLK_000_P_SYNC_0_.BLIF \ a_i_25__n.BLIF N_338_i.BLIF CLK_000_P_SYNC_1_.BLIF a_i_26__n.BLIF N_339_i.BLIF a_3__n.BLIF CLK_000_P_SYNC_2_.BLIF N_213_i.BLIF cpu_est_2_0_1__n.BLIF \ CLK_000_P_SYNC_3_.BLIF N_214_i.BLIF N_332_i.BLIF a_2__n.BLIF CLK_000_P_SYNC_4_.BLIF N_215_i.BLIF N_336_i.BLIF CLK_000_P_SYNC_5_.BLIF pos_clk_un7_clk_000_pe_0_n.BLIF \ CLK_000_P_SYNC_6_.BLIF N_275_i.BLIF N_99_0.BLIF CLK_000_P_SYNC_7_.BLIF un6_ds_030_i.BLIF N_331_i.BLIF CLK_000_P_SYNC_8_.BLIF DS_000_DMA_i.BLIF N_96_0.BLIF \ @@ -122,7 +122,7 @@ a_c_24__n.BLIF N_20_i.BLIF N_123.BLIF N_39_0.BLIF cpu_est_2_1__n.BLIF a_c_25__n.BLIF N_21_i.BLIF cpu_est_2_2__n.BLIF N_38_0.BLIF \ N_209.BLIF a_c_26__n.BLIF N_22_i.BLIF G_134.BLIF N_37_0.BLIF G_135.BLIF a_c_27__n.BLIF N_25_i.BLIF G_136.BLIF \ N_34_0.BLIF N_217.BLIF a_c_28__n.BLIF N_26_i.BLIF N_33_0.BLIF N_61.BLIF a_c_29__n.BLIF BG_030_c_i.BLIF N_127.BLIF \ - pos_clk_un6_bg_030_i_n.BLIF a_c_30__n.BLIF pos_clk_un8_bg_030_0_n.BLIF N_80.BLIF N_289_0_1.BLIF a_c_31__n.BLIF un1_SM_AMIGA_5_i_1.BLIF N_90.BLIF un1_SM_AMIGA_5_i_2.BLIF \ + pos_clk_un6_bg_030_i_n.BLIF a_c_30__n.BLIF pos_clk_un9_bg_030_0_n.BLIF N_80.BLIF N_289_0_1.BLIF a_c_31__n.BLIF un1_SM_AMIGA_5_i_1.BLIF N_90.BLIF un1_SM_AMIGA_5_i_2.BLIF \ N_96.BLIF A0_c.BLIF pos_clk_un8_sm_amiga_i_1_n.BLIF N_99.BLIF N_351_1.BLIF N_119.BLIF A1_c.BLIF N_351_2.BLIF N_124.BLIF \ N_168_i_1.BLIF N_138.BLIF nEXP_SPACE_c.BLIF N_192_0_1.BLIF N_144.BLIF N_192_0_2.BLIF N_158.BLIF BERR_c.BLIF N_137_i_1.BLIF \ N_168.BLIF N_137_i_2.BLIF N_175.BLIF BG_030_c.BLIF N_145_i_1.BLIF N_182.BLIF N_145_i_2.BLIF N_185.BLIF BG_000DFFreg.BLIF \ @@ -145,7 +145,7 @@ N_342.BLIF N_5_i.BLIF bgack_030_int_0_un3_n.BLIF N_343.BLIF N_47_0.BLIF bgack_030_int_0_un1_n.BLIF N_344.BLIF N_4_i.BLIF bgack_030_int_0_un0_n.BLIF \ N_345.BLIF N_48_0.BLIF as_030_000_sync_0_un3_n.BLIF N_347.BLIF N_272_i.BLIF as_030_000_sync_0_un1_n.BLIF N_350.BLIF N_271_i.BLIF as_030_000_sync_0_un0_n.BLIF \ N_351.BLIF N_279_0.BLIF ds_000_enable_0_un3_n.BLIF N_353.BLIF N_280_0.BLIF ds_000_enable_0_un1_n.BLIF N_361.BLIF N_281_0.BLIF ds_000_enable_0_un0_n.BLIF \ - pos_clk_un24_bgack_030_int_i_i_a4_i_x2.BLIF N_298_i.BLIF as_000_int_0_un3_n.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF pos_clk_size_dma_6_0_0__n.BLIF as_000_int_0_un1_n.BLIF cpu_est_0_0_x2_0_.BLIF N_299_i.BLIF as_000_int_0_un0_n.BLIF \ + pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_298_i.BLIF as_000_int_0_un3_n.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF pos_clk_size_dma_6_0_0__n.BLIF as_000_int_0_un1_n.BLIF cpu_est_0_0_x2_0_.BLIF N_299_i.BLIF as_000_int_0_un0_n.BLIF \ pos_clk_CYCLE_DMA_5_1_i_x2.BLIF pos_clk_size_dma_6_0_1__n.BLIF dsack1_int_0_un3_n.BLIF un22_berr_1.BLIF un1_as_000_i.BLIF dsack1_int_0_un1_n.BLIF N_375.BLIF N_358_i.BLIF dsack1_int_0_un0_n.BLIF \ N_218.BLIF pos_clk_un6_bgack_000_0_n.BLIF size_dma_0_1__un3_n.BLIF N_156.BLIF N_284_i.BLIF size_dma_0_1__un1_n.BLIF N_289.BLIF N_285_i.BLIF size_dma_0_1__un0_n.BLIF \ N_354.BLIF N_286_0.BLIF size_dma_0_0__un3_n.BLIF N_205.BLIF N_88_0.BLIF size_dma_0_0__un1_n.BLIF un1_SM_AMIGA_5.BLIF pos_clk_un3_as_030_d0_i_n.BLIF size_dma_0_0__un0_n.BLIF \ @@ -155,22 +155,22 @@ N_298.BLIF N_354_i.BLIF cpu_est_0_1__un3_n.BLIF N_281.BLIF N_208_0.BLIF cpu_est_0_1__un1_n.BLIF AS_030.PIN AS_000.PIN RW_000.PIN \ UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E VMA \ - RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D \ - SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \ - IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D \ - SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ - CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \ - cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \ - CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D \ - CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C RST_DLY_1_.D RST_DLY_1_.C \ - RST_DLY_2_.D RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D \ - CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ + RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D \ + SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \ + IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D \ + SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C \ + SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D \ + cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C \ + CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D \ + CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C RST_DLY_1_.D RST_DLY_1_.C \ + RST_DLY_2_.D RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \ + CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D \ inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ inst_VMA_INTreg.D inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D \ - inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ - inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C pos_clk_CYCLE_DMA_5_0_i_x2.X1 \ - pos_clk_CYCLE_DMA_5_0_i_x2.X2 cpu_est_0_0_x2_0_.X1 cpu_est_0_0_x2_0_.X2 pos_clk_CYCLE_DMA_5_1_i_x2.X1 pos_clk_CYCLE_DMA_5_1_i_x2.X2 pos_clk_un24_bgack_030_int_i_i_a4_i_x2.X1 pos_clk_un24_bgack_030_int_i_i_a4_i_x2.X2 G_134.X1 G_134.X2 G_135.X1 G_135.X2 \ + inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ + inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C pos_clk_CYCLE_DMA_5_0_i_x2.X1 \ + pos_clk_CYCLE_DMA_5_0_i_x2.X2 cpu_est_0_0_x2_0_.X1 cpu_est_0_0_x2_0_.X2 pos_clk_CYCLE_DMA_5_1_i_x2.X1 pos_clk_CYCLE_DMA_5_1_i_x2.X2 pos_clk_un23_bgack_030_int_i_i_a4_i_x2.X1 pos_clk_un23_bgack_030_int_i_i_a4_i_x2.X2 G_134.X1 G_134.X2 G_135.X1 G_135.X2 \ G_136.X1 G_136.X2 SIZE_1_ AS_030 AS_000 RW_000 UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_280 N_210_0 cpu_est_0_1__un0_n N_279 N_289_0 cpu_est_0_2__un3_n N_271 N_218_0 cpu_est_0_2__un1_n \ N_272 cpu_est_0_2__un0_n N_276 N_242_i cpu_est_0_3__un3_n DS_000_ENABLE_1_sqmuxa_1 N_246_i cpu_est_0_3__un1_n N_4 N_240_i cpu_est_0_3__un0_n \ vcc_n_n N_5 N_241_i ipl_030_0_0__un3_n N_7 ipl_030_0_0__un1_n gnd_n_n N_10 N_266_i ipl_030_0_0__un0_n un1_amiga_bus_enable_low \ @@ -185,10 +185,10 @@ AS_030_i N_193_i lds_000_int_0_un3_n AS_030_D0_i N_192_0 lds_000_int_0_un1_n a_i_24__n clk_000_n_sync_i_10__n lds_000_int_0_un0_n sm_amiga_i_3__n N_350_i \ rw_000_dma_0_un3_n cpu_est_i_0__n N_188_0 rw_000_dma_0_un1_n cpu_est_i_3__n N_187_i rw_000_dma_0_un0_n cpu_est_i_2__n N_185_i a_15__n cpu_est_i_1__n \ N_182_i VPA_D_i N_181_i a_14__n CLK_000_NE_i CLK_OUT_PRE_D_i sm_amiga_i_1__n N_175_0 a_13__n rst_dly_i_2__n N_168_i \ - CLK_030_i AS_030_000_SYNC_i a_12__n rst_dly_i_0__n N_158_i rst_dly_i_1__n CLK_000_D0_i a_11__n CLK_000_D1_i N_148_i DTACK_D0_i \ + CLK_030_i AS_030_000_SYNC_i a_12__n rst_dly_i_0__n N_158_i rst_dly_i_1__n clk_000_d_i_0__n a_11__n clk_000_d_i_1__n N_148_i DTACK_D0_i \ N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i CLK_030_H_i N_144_0 a_9__n sm_amiga_i_6__n N_138_0 sm_amiga_i_2__n \ a_8__n AS_000_i N_342_i pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n A1_i N_124_0 a_i_31__n N_341_i \ - a_6__n a_i_29__n N_119_0 a_i_30__n N_340_i a_5__n a_i_27__n N_361_i pos_clk_un8_bg_030_n a_i_28__n cpu_est_2_0_2__n \ + a_6__n a_i_29__n N_119_0 a_i_30__n N_340_i a_5__n a_i_27__n N_361_i pos_clk_un9_bg_030_n a_i_28__n cpu_est_2_0_2__n \ a_4__n a_i_25__n N_338_i a_i_26__n N_339_i a_3__n N_213_i cpu_est_2_0_1__n N_214_i N_332_i a_2__n \ N_215_i N_336_i pos_clk_un7_clk_000_pe_0_n N_275_i N_99_0 un6_ds_030_i N_331_i DS_000_DMA_i N_96_0 un4_as_000_i N_330_i \ AS_000_INT_i N_90_0 un4_lds_000_i N_328_i un4_uds_000_i AS_030_c N_80_0 N_325_i AS_000_c N_326_i N_258_0 \ @@ -201,7 +201,7 @@ a_c_21__n N_8_i N_45_0 a_c_22__n N_17_i N_42_0 a_c_23__n N_19_i N_40_0 a_c_24__n N_20_i \ N_123 N_39_0 cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i N_37_0 \ a_c_27__n N_25_i N_34_0 N_217 a_c_28__n N_26_i N_33_0 N_61 a_c_29__n BG_030_c_i N_127 \ - pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un8_bg_030_0_n N_80 N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \ + pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \ pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c N_351_2 N_124 N_168_i_1 N_138 nEXP_SPACE_c N_192_0_1 \ N_144 N_192_0_2 N_158 BERR_c N_137_i_1 N_168 N_137_i_2 N_175 BG_030_c N_145_i_1 N_182 \ N_145_i_2 N_185 N_145_i_3 N_187 N_260_i_1 N_188 N_260_i_2 N_192 BGACK_000_c N_259_i_1 N_193 \ @@ -307,16 +307,16 @@ 11 1 .names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un4_uds_000 11 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C -1 1 .names AS_030_D0_i.BLIF a_c_20__n.BLIF un5_ciin_1 11 1 .names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 .names un4_uds_000.BLIF un4_uds_000_i 0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C +1 1 .names a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2 11 1 .names SIZE_DMA_1_.BLIF size_dma_i_1__n @@ -335,14 +335,14 @@ 0 1 .names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C -1 1 .names a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5 11 1 .names a_c_18__n.BLIF a_i_18__n 0 1 .names un4_as_000.BLIF un4_as_000_i 0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C +1 1 .names a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6 11 1 .names N_286.BLIF size_dma_0_1__un3_n @@ -361,8 +361,6 @@ 11 1 .names un6_ds_030.BLIF un6_ds_030_i 0 1 -.names CLK_OSZI_c.BLIF RST_DLY_0_.C -1 1 .names un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9 11 1 .names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D @@ -370,6 +368,8 @@ -1 1 .names N_96.BLIF ds_000_dma_0_un3_n 0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C +1 1 .names un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10 11 1 .names N_286.BLIF size_dma_0_0__un3_n @@ -389,8 +389,6 @@ .names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 .names N_260_i_1.BLIF N_260_i_2.BLIF RST_DLY_1_.D 11 1 .names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D @@ -398,6 +396,8 @@ -1 1 .names N_99.BLIF as_000_dma_0_un3_n 0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C +1 1 .names N_240_i.BLIF N_241_i.BLIF N_259_i_1 11 1 .names N_4_i.BLIF RST_c.BLIF N_48_0 @@ -417,14 +417,14 @@ .names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_8 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 .names inst_CLK_000_NE.BLIF N_361.BLIF N_336_1 11 1 .names N_10_i.BLIF RST_c.BLIF N_43_0 11 1 .names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n 0 1 +.names CLK_OSZI_c.BLIF RST_DLY_0_.C +1 1 .names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_336_2 11 1 .names N_18_i.BLIF RST_c.BLIF N_41_0 @@ -444,14 +444,14 @@ .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_17 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C -1 1 .names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_332_2 11 1 .names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D 11 1 .names N_193.BLIF rw_000_dma_0_un3_n 0 1 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 .names N_332_1.BLIF N_332_2.BLIF N_332_3 11 1 .names N_276.BLIF N_276_i @@ -471,14 +471,14 @@ .names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C -1 1 .names N_196_i.BLIF N_197_i.BLIF N_317_2 11 1 .names CLK_000_PE_i.BLIF SM_AMIGA_4_.BLIF N_349 11 1 .names vcc_n_n 1 +.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C +1 1 .names N_317_1.BLIF N_317_2.BLIF N_317_3 11 1 .names N_218.BLIF sm_amiga_i_5__n.BLIF N_305 @@ -496,14 +496,14 @@ 11 1 .names A_14_.BLIF a_14__n 1 1 -.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C -1 1 .names AS_030_000_SYNC_i.BLIF N_148_i.BLIF N_168_i_1 11 1 .names BGACK_030_INT_i.BLIF N_205.BLIF N_298 11 1 .names A_13_.BLIF a_13__n 1 1 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 .names N_168_i_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_168_i 11 1 .names A1_c.BLIF BGACK_030_INT_i.BLIF N_276 @@ -516,20 +516,20 @@ 11 1 .names A_11_.BLIF a_11__n 1 1 -.names pos_clk_un24_bgack_030_int_i_i_a4_i_x2.BLIF N_345_i.BLIF N_192_0_2 +.names pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_345_i.BLIF N_192_0_2 11 1 .names N_375.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_272 11 1 .names A_10_.BLIF a_10__n 1 1 -.names CLK_OSZI_c.BLIF inst_AS_030_D0.C -1 1 .names N_192_0_1.BLIF N_192_0_2.BLIF N_192_0 11 1 .names N_289.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_271 11 1 .names A_9_.BLIF a_9__n 1 1 +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +1 1 .names N_323_i.BLIF N_324_i.BLIF N_137_i_1 11 1 .names RW_c.BLIF RW_i @@ -548,14 +548,14 @@ 0 1 .names A_6_.BLIF a_6__n 1 1 -.names CLK_OSZI_c.BLIF inst_nEXP_SPACE_D0reg.C -1 1 .names N_208_0.BLIF N_312_i.BLIF N_145_i_1 11 1 .names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size 11 1 .names A_5_.BLIF a_5__n 1 1 +.names CLK_OSZI_c.BLIF inst_nEXP_SPACE_D0reg.C +1 1 .names N_313_i.BLIF N_316_i.BLIF N_145_i_2 11 1 .names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n @@ -574,12 +574,12 @@ 11 1 .names A_2_.BLIF a_2__n 1 1 -.names CLK_OSZI_c.BLIF inst_VPA_D.C -1 1 .names N_242_i.BLIF N_254_i.BLIF N_260_i_1 11 1 .names N_222_i.BLIF inst_RESET_OUT.BLIF N_285_i 11 1 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 .names N_25.BLIF N_25_i 0 1 .names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_284_i @@ -592,12 +592,12 @@ 0 1 .names inst_RESET_OUT.BLIF RESET_OUT_i 0 1 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C -1 1 .names N_33_0.BLIF BG_000DFFreg.D 0 1 .names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i 11 1 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 .names BG_030_c.BLIF BG_030_c_i 0 1 .names N_299_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n @@ -606,16 +606,16 @@ 0 1 .names N_298_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n 11 1 -.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n 0 1 .names N_236_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_281_0 11 1 -.names CLK_OSZI_c.BLIF inst_CLK_030_H.C -1 1 .names N_193_i.BLIF sm_amiga_i_i_7__n.BLIF N_289_0_1 11 1 .names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_280_0 11 1 +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +1 1 .names N_289_0_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_289_0 11 1 .names N_271_i.BLIF N_272_i.BLIF N_279_0 @@ -628,12 +628,12 @@ 11 1 .names AS_000_c.BLIF inst_CLK_000_PE.BLIF N_358 11 1 -.names CLK_OSZI_c.BLIF inst_RESET_OUT.C -1 1 .names un1_SM_AMIGA_5_i_1.BLIF un1_SM_AMIGA_5_i_2.BLIF un1_SM_AMIGA_5_i 11 1 .names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 11 1 +.names CLK_OSZI_c.BLIF inst_RESET_OUT.C +1 1 .names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un8_sm_amiga_i_1_n 11 1 .names FPU_SENSE_c.BLIF FPU_SENSE_i @@ -646,12 +646,12 @@ 11 1 .names BERR_c.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n 11 1 -.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C -1 1 .names N_54_0.BLIF inst_nEXP_SPACE_D0reg.D 0 1 .names inst_CLK_000_PE.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n 11 1 +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 .names N_3.BLIF N_3_i 0 1 .names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_229 @@ -665,12 +665,12 @@ 0 1 .names N_156_i.BLIF SM_AMIGA_4_.BLIF N_218_0 11 1 -.names CLK_OSZI_c.BLIF BG_000DFFreg.C -1 1 .names N_45_0.BLIF inst_AS_000_DMA.D 0 1 .names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i 0 1 +.names CLK_OSZI_c.BLIF BG_000DFFreg.C +1 1 .names N_17.BLIF N_17_i 0 1 .names BGACK_030_INT_i.BLIF RST_c.BLIF N_210_0 @@ -683,12 +683,12 @@ 0 1 .names N_156.BLIF sm_amiga_i_3__n.BLIF N_207_0 11 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C -1 1 .names N_40_0.BLIF inst_RW_000_DMA.D 0 1 .names N_156.BLIF SM_AMIGA_i_7_.BLIF N_206_0 11 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 .names N_20.BLIF N_20_i 0 1 .names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_205_i @@ -701,12 +701,12 @@ 0 1 .names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_194_i 11 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 .names N_38_0.BLIF inst_UDS_000_INT.D 0 1 .names BERR_c.BLIF CLK_000_PE_i.BLIF N_156_i 11 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 .names N_22.BLIF N_22_i 0 1 .names BERR_c.BLIF BERR_i @@ -719,12 +719,12 @@ 0 1 .names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n 0 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 .names N_31_0.BLIF IPL_030DFF_1_reg.D 0 1 .names sm_amiga_i_i_7__n.BLIF inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un1_n 11 1 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 .names N_27.BLIF N_27_i 0 1 .names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n @@ -736,13 +736,13 @@ -1 1 .names ipl_c_2__n.BLIF ipl_c_i_2__n 0 1 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C -1 1 .names N_53_0.BLIF IPL_D0_2_.D 0 1 .names SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_m2_5__un3_n 0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +1 1 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C 1 1 .names ipl_c_1__n.BLIF ipl_c_i_1__n 0 1 @@ -757,11 +757,11 @@ .names sm_amiga_srsts_i_0_m2_5__un1_n.BLIF sm_amiga_srsts_i_0_m2_5__un0_n.BLIF N_230 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_A0_DMA.C -1 1 .names N_51_0.BLIF IPL_D0_0_.D 0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C 1 1 .names DTACK_c.BLIF DTACK_c_i 0 1 @@ -773,13 +773,13 @@ 0 1 .names cpu_est_2_.BLIF cpu_est_i_2__n 0 1 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C -1 1 .names N_55_0.BLIF inst_VPA_D.D 0 1 .names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C 1 1 .names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i 0 1 @@ -793,13 +793,13 @@ 0 1 .names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 .names N_304.BLIF N_304_i 0 1 .names inst_AS_030_D0.BLIF AS_030_D0_i 0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C 1 1 .names N_283_0.BLIF SM_AMIGA_2_.D 0 1 @@ -813,13 +813,13 @@ 0 1 .names clk_000_n_sync_i_10__n.BLIF N_350_i.BLIF N_188_0 11 1 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 .names N_123_0.BLIF N_123 0 1 .names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_193_i 11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C 1 1 .names N_278.BLIF N_278_i 0 1 @@ -833,13 +833,13 @@ 0 1 .names N_351_i.BLIF N_353_i.BLIF N_201_i 11 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 .names N_277.BLIF N_277_i 0 1 .names N_196_i.BLIF sm_amiga_i_6__n.BLIF N_204_0 11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C +1 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 .names A0_c.BLIF A0_c_i 0 1 @@ -853,13 +853,13 @@ 0 1 .names inst_CLK_000_NE_D0.BLIF N_201.BLIF N_290_0 11 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C -1 1 .names N_32_0.BLIF IPL_030DFF_2_reg.D 0 1 .names inst_CLK_000_NE.BLIF N_187_i.BLIF N_216_0 11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C +.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C +1 1 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C 1 1 .names N_330.BLIF N_330_i 0 1 @@ -873,13 +873,13 @@ 0 1 .names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_219_0 11 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C -1 1 .names N_80_0.BLIF N_80 0 1 .names inst_CLK_000_PE.BLIF SM_AMIGA_4_.BLIF N_220_0 11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C +.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +1 1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C 1 1 .names N_325.BLIF N_325_i 0 1 @@ -889,25 +889,23 @@ 0 1 .names AS_000_DMA_i.BLIF AS_000_i.BLIF N_138_0 11 1 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D -1 1 .names N_258_0.BLIF SM_AMIGA_6_.D 0 1 .names N_217_i.BLIF N_217 0 1 .names N_344_i.BLIF RST_c.BLIF N_144_0 11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +.names CLK_OSZI_c.BLIF IPL_D0_0_.C 1 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 .names N_321.BLIF N_321_i 0 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n 0 1 .names N_322.BLIF N_322_i 0 1 -.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_148_i +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_148_i 11 1 .names N_320.BLIF N_320_i 0 1 @@ -919,7 +917,7 @@ 0 1 .names RST_DLY_1_.BLIF rst_dly_i_1__n 0 1 -.names CLK_OSZI_c.BLIF IPL_D0_0_.C +.names CLK_OSZI_c.BLIF IPL_D0_1_.C 1 1 .names N_61_0.BLIF N_61 0 1 @@ -939,7 +937,7 @@ 0 1 .names cpu_est_3_.BLIF cpu_est_i_2__n.BLIF N_181_i 11 1 -.names CLK_OSZI_c.BLIF IPL_D0_1_.C +.names CLK_OSZI_c.BLIF IPL_D0_2_.C 1 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D 1 1 @@ -961,7 +959,7 @@ 0 1 .names N_158_i.BLIF RST_DLY_2_.BLIF N_187_i 11 1 -.names CLK_OSZI_c.BLIF IPL_D0_2_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C 1 1 .names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n 0 1 @@ -983,7 +981,7 @@ 0 1 .names nEXP_SPACE_D0_i.BLIF un5_ciin_i.BLIF N_61_0 11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 .names N_332.BLIF N_332_i 0 1 @@ -997,13 +995,13 @@ 0 1 .names N_325_i.BLIF N_326_i.BLIF N_258_0 11 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C +.names CLK_OSZI_c.BLIF inst_CLK_000_PE.C 1 1 .names N_99_0.BLIF N_99 0 1 .names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_80_0 11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 .names N_331.BLIF N_331_i 0 1 @@ -1017,18 +1015,20 @@ 0 1 .names N_332_i.BLIF N_336_i.BLIF pos_clk_un7_clk_000_pe_0_n 11 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_PE.C +.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +1 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C 1 1 .names N_185_i.BLIF N_185 0 1 .names N_338_i.BLIF N_339_i.BLIF cpu_est_2_0_1__n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C -1 1 .names N_182_i.BLIF N_182 0 1 .names N_340_i.BLIF N_361_i.BLIF cpu_est_2_0_2__n 11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C +1 1 .names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i 0 1 .names N_182.BLIF N_341_i.BLIF N_119_0 @@ -1037,27 +1037,27 @@ 0 1 .names N_342_i.BLIF N_343_i.BLIF N_124_0 11 1 -.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D -1 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C 1 1 .names N_168_i.BLIF N_168 0 1 .names RW_000_c.BLIF RW_000_i 0 1 +.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D +1 1 .names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i 0 1 .names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_330 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C -1 1 .names N_158_i.BLIF N_158 0 1 .names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_331 11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C +1 1 .names inst_CLK_000_PE.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.X1 1 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n 0 1 .names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_338 11 1 @@ -1065,8 +1065,6 @@ 0 1 .names N_185.BLIF cpu_est_2_.BLIF N_340 11 1 -.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D -1 1 .names CYCLE_DMA_0_.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.X2 1 1 .names N_344.BLIF N_344_i @@ -1077,7 +1075,7 @@ 0 1 .names N_181_i.BLIF cpu_est_i_1__n.BLIF N_342 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C 1 1 .names N_138_0.BLIF N_138 0 1 @@ -1103,7 +1101,7 @@ 0 1 .names CLK_000_N_SYNC_9_.BLIF N_175.BLIF N_350 11 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C 1 1 .names A_18_.BLIF a_c_18__n 1 1 @@ -1131,7 +1129,7 @@ 0 1 .names N_185_i.BLIF cpu_est_i_2__n.BLIF N_361 11 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C 1 1 .names N_209.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X2 1 1 @@ -1153,7 +1151,7 @@ 0 1 .names AS_000_c.BLIF AS_000_i 0 1 -.names CYCLE_DMA_0_.BLIF pos_clk_un24_bgack_030_int_i_i_a4_i_x2.X1 +.names CYCLE_DMA_0_.BLIF pos_clk_un23_bgack_030_int_i_i_a4_i_x2.X1 1 1 .names A_25_.BLIF a_c_25__n 1 1 @@ -1161,7 +1159,7 @@ 0 1 .names SM_AMIGA_2_.BLIF sm_amiga_i_2__n 0 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C 1 1 .names A_26_.BLIF a_c_26__n 1 1 @@ -1169,7 +1167,7 @@ 0 1 .names N_212.BLIF sm_amiga_i_2__n.BLIF N_301 11 1 -.names CYCLE_DMA_1_.BLIF pos_clk_un24_bgack_030_int_i_i_a4_i_x2.X2 +.names CYCLE_DMA_1_.BLIF pos_clk_un23_bgack_030_int_i_i_a4_i_x2.X2 1 1 .names A_27_.BLIF a_c_27__n 1 1 @@ -1189,7 +1187,7 @@ 0 1 .names N_211.BLIF sm_amiga_i_6__n.BLIF N_310 11 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +.names CLK_OSZI_c.BLIF cpu_est_0_.C 1 1 .names IPL_D0_0_.BLIF G_134.X1 1 1 @@ -1217,7 +1215,7 @@ 0 1 .names N_127.BLIF rst_dly_i_0__n.BLIF N_322 11 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C +.names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 .names nEXP_SPACE.BLIF nEXP_SPACE_c 1 1 @@ -1245,7 +1243,7 @@ 0 1 .names a_c_31__n.BLIF a_i_31__n 0 1 -.names CLK_OSZI_c.BLIF cpu_est_1_.C +.names CLK_OSZI_c.BLIF cpu_est_2_.C 1 1 .names inst_BGACK_030_INTreg.BLIF BGACK_030 1 1 @@ -1261,13 +1259,13 @@ 1 1 .names N_347.BLIF N_347_i 0 1 -.names CLK_000.BLIF inst_CLK_000_D0.D +.names CLK_000.BLIF CLK_000_D_0_.D 1 1 .names N_323.BLIF N_323_i 0 1 .names N_188.BLIF SM_AMIGA_1_.BLIF N_236 11 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C +.names CLK_OSZI_c.BLIF cpu_est_3_.C 1 1 .names ipl_c_2__n.BLIF G_136.X2 1 1 @@ -1289,7 +1287,7 @@ 0 1 .names N_127.BLIF rst_dly_i_2__n.BLIF N_246 11 1 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +.names cpu_est_0_0_x2_0_.BLIF cpu_est_0_.D 1 1 .names un21_fpu_cs_i.BLIF FPU_CS 1 1 @@ -1297,9 +1295,9 @@ 0 1 .names N_144.BLIF N_158_i.BLIF N_254 11 1 -.names CLK_OSZI_c.BLIF cpu_est_3_.C +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C 1 1 -.names cpu_est_0_0_x2_0_.BLIF cpu_est_0_.D +.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D 1 1 .names FPU_SENSE.BLIF FPU_SENSE_c 1 1 @@ -1307,15 +1305,15 @@ 0 1 .names N_127.BLIF rst_dly_i_1__n.BLIF N_267 11 1 -.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D 1 1 .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 .names N_156_i.BLIF N_156 0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF CLK_000_P_SYNC_0_.D 11 1 -.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D 1 1 .names IPL_030DFF_1_reg.BLIF IPL_030_1_ 1 1 @@ -1323,7 +1321,7 @@ 0 1 .names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n 11 1 -.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D +.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D 1 1 .names IPL_030DFF_2_reg.BLIF IPL_030_2_ 1 1 @@ -1331,9 +1329,9 @@ 0 1 .names A1_c.BLIF A1_i 0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C 1 1 -.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D +.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D 1 1 .names IPL_0_.BLIF ipl_c_0__n 1 1 @@ -1341,7 +1339,7 @@ 0 1 .names A1_i.BLIF BGACK_030_INT_i.BLIF N_275 11 1 -.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D +.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D 1 1 .names IPL_1_.BLIF ipl_c_1__n 1 1 @@ -1349,85 +1347,85 @@ 0 1 .names SM_AMIGA_0_.BLIF sm_amiga_i_0__n 0 1 -.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D +.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D 1 1 .names IPL_2_.BLIF ipl_c_2__n 1 1 .names N_205_i.BLIF N_205 0 1 -.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_209 -11 1 -.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D +0 1 +.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D 1 1 .names N_206_0.BLIF N_206 0 1 -.names G_134.BLIF N_213_i -0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C +.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_209 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C 1 1 -.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D +.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D 1 1 .names DTACK.BLIF DTACK_c 1 1 .names N_207_0.BLIF N_207 0 1 -.names G_135.BLIF N_214_i +.names G_134.BLIF N_213_i 0 1 -.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D +.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D 1 1 .names vcc_n_n.BLIF AVEC 1 1 .names N_354.BLIF N_354_i 0 1 -.names G_136.BLIF N_215_i +.names G_135.BLIF N_214_i 0 1 -.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D +.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D 1 1 .names N_124.BLIF E 1 1 .names N_210_0.BLIF inst_BGACK_030_INT_D.D 0 1 -.names a_c_25__n.BLIF a_i_25__n +.names G_136.BLIF N_215_i 0 1 -.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D +.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D 1 1 .names VPA.BLIF VPA_c 1 1 .names N_289_0.BLIF N_289 0 1 -.names a_c_26__n.BLIF a_i_26__n +.names a_c_25__n.BLIF a_i_25__n 0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C 1 1 -.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D +.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D 1 1 .names inst_VMA_INTreg.BLIF VMA 1 1 .names N_218_0.BLIF N_218 0 1 -.names a_c_27__n.BLIF a_i_27__n +.names a_c_26__n.BLIF a_i_26__n 0 1 -.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D 1 1 .names RST.BLIF RST_c 1 1 .names N_242.BLIF N_242_i 0 1 -.names a_c_28__n.BLIF a_i_28__n +.names a_c_27__n.BLIF a_i_27__n 0 1 .names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D 1 1 .names N_246.BLIF N_246_i 0 1 -.names a_c_29__n.BLIF a_i_29__n +.names a_c_28__n.BLIF a_i_28__n 0 1 .names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D 1 1 .names N_240.BLIF N_240_i 0 1 -.names a_c_30__n.BLIF a_i_30__n +.names a_c_29__n.BLIF a_i_29__n 0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C 1 1 .names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D 1 1 @@ -1435,7 +1433,7 @@ 1 1 .names N_48_0.BLIF inst_DSACK1_INTreg.D 0 1 -.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D +.names a_c_30__n.BLIF a_i_30__n 0 1 .names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D 1 1 @@ -1453,6 +1451,8 @@ 0 1 .names RST_c.BLIF VPA_c_i.BLIF N_55_0 11 1 +.names N_148_i.BLIF CLK_000_N_SYNC_0_.D +1 1 .names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D 1 1 .names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR @@ -1461,14 +1461,14 @@ 0 1 .names DTACK_c_i.BLIF RST_c.BLIF N_56_0 11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C -1 1 .names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW 1 1 .names N_280_0.BLIF N_280 0 1 .names ipl_c_i_0__n.BLIF RST_c.BLIF N_51_0 11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C +1 1 .names N_227.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 .names N_281_0.BLIF N_281 @@ -1479,8 +1479,6 @@ 0 1 .names ipl_c_i_2__n.BLIF RST_c.BLIF N_53_0 11 1 -.names N_148_i.BLIF CLK_000_N_SYNC_0_.D -1 1 .names N_303_1.BLIF SM_AMIGA_2_.BLIF N_303 11 1 .names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n @@ -1493,7 +1491,7 @@ 0 1 .names N_28_i.BLIF RST_c.BLIF N_31_0 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C 1 1 .names N_297_1.BLIF RW_000_c.BLIF N_297 11 1 @@ -1519,7 +1517,7 @@ 0 1 .names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C 1 1 .names N_240_1.BLIF rst_dly_i_2__n.BLIF N_240 11 1 @@ -1546,7 +1544,7 @@ 0 1 .names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C 1 1 .names N_339_1.BLIF cpu_est_i_3__n.BLIF N_339 11 1 @@ -1561,7 +1559,7 @@ 0 1 .names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n 0 1 -.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n +.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n 11 1 .names N_10.BLIF N_10_i 0 1 @@ -1573,7 +1571,7 @@ 0 1 .names cpu_est_3_.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C 1 1 .names N_326_1.BLIF sm_amiga_i_i_7__n.BLIF N_326 11 1 @@ -1600,7 +1598,7 @@ 0 1 .names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C 1 1 .names N_324_1.BLIF sm_amiga_i_4__n.BLIF N_324 11 1 @@ -1627,7 +1625,7 @@ 0 1 .names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C 1 1 .names N_313_1.BLIF CLK_000_PE_i.BLIF N_313 11 1 @@ -1654,7 +1652,7 @@ 11 1 .names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C 1 1 .names N_261_i_1.BLIF N_322_i.BLIF RST_DLY_0_.D 11 1 @@ -1682,7 +1680,7 @@ 11 1 .names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C 1 1 .names N_139_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D 11 1 @@ -1710,7 +1708,7 @@ 11 1 .names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C 1 1 .names N_123_0_1.BLIF SM_AMIGA_i_7_.BLIF N_123_0 11 1 @@ -1786,15 +1784,15 @@ 11 1 .names SM_AMIGA_5_.BLIF sm_amiga_i_5__n 0 1 -.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n 0 1 .names a_c_17__n.BLIF a_i_16__n.BLIF N_375_2 11 1 .names N_280.BLIF as_000_int_0_un3_n 0 1 -.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C 1 1 .names a_i_18__n.BLIF a_i_19__n.BLIF N_375_3 11 1 @@ -1816,20 +1814,22 @@ -1 1 .names N_26_i.BLIF RST_c.BLIF N_33_0 11 1 +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D +1 1 .names AS_000_i.BLIF N_210_0.BLIF N_134_i_1 11 1 .names N_236.BLIF N_236_i 0 1 .names N_25_i.BLIF RST_c.BLIF N_34_0 11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C -1 1 .names N_134_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF CYCLE_DMA_1_.D 11 1 .names N_281.BLIF dsack1_int_0_un3_n 0 1 .names N_22_i.BLIF RST_c.BLIF N_37_0 11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_1_.C +1 1 .names N_192_0.BLIF N_331_i.BLIF N_96_0_1 11 1 .names N_236_i.BLIF N_281.BLIF dsack1_int_0_un1_n @@ -1849,14 +1849,14 @@ -1 1 .names N_19_i.BLIF RST_c.BLIF N_40_0 11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C -1 1 .names N_317_3.BLIF sm_amiga_i_3__n.BLIF N_317 11 1 .names inst_LDS_000_INT.BLIF LDS_000_INT_i 0 1 .names N_17_i.BLIF RST_c.BLIF N_42_0 11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C +1 1 .names inst_CLK_000_NE_D0.BLIF N_201.BLIF N_304_1 11 1 .names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un4_lds_000 diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index 5013208..7477b47 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,5 +1,5 @@ -#$ TOOL ispLEVER Classic 1.8.00.04.29.14 -#$ DATE Wed Jan 27 21:56:48 2016 +#$ TOOL ispLEVER Classic 2.0.00.17.20.15 +#$ DATE Wed Aug 17 17:45:46 2016 #$ MODULE bus68030 #$ PINS 75 A_8_ A_7_ SIZE_1_ A_6_ A_5_ A_31_ A_4_ A_3_ IPL_030_2_ A_2_ IPL_030_1_ IPL_2_ \ # IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 \ @@ -37,17 +37,17 @@ # lds_000_int_0_un0_n inst_CLK_OUT_PRE_D sm_amiga_i_3__n N_350_i rw_000_dma_0_un3_n \ # inst_DTACK_D0 cpu_est_i_0__n N_188_0 rw_000_dma_0_un1_n inst_RESET_OUT \ # cpu_est_i_3__n N_187_i rw_000_dma_0_un0_n inst_CLK_OUT_PRE_50 cpu_est_i_2__n \ -# N_185_i a_15__n inst_CLK_000_D1 cpu_est_i_1__n N_182_i inst_CLK_000_D0 VPA_D_i \ -# N_181_i a_14__n inst_CLK_000_PE CLK_000_NE_i CLK_OUT_PRE_D_i CLK_000_P_SYNC_9_ \ +# N_185_i a_15__n CLK_000_D_1_ cpu_est_i_1__n N_182_i CLK_000_D_0_ VPA_D_i N_181_i \ +# a_14__n inst_CLK_000_PE CLK_000_NE_i CLK_OUT_PRE_D_i CLK_000_P_SYNC_9_ \ # sm_amiga_i_1__n N_175_0 a_13__n inst_CLK_000_NE rst_dly_i_2__n N_168_i \ # CLK_000_N_SYNC_11_ CLK_030_i AS_030_000_SYNC_i a_12__n IPL_D0_0_ rst_dly_i_0__n \ -# N_158_i IPL_D0_1_ rst_dly_i_1__n CLK_000_D0_i a_11__n IPL_D0_2_ CLK_000_D1_i N_148_i \ -# inst_CLK_000_NE_D0 DTACK_D0_i N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i \ -# SM_AMIGA_0_ CLK_030_H_i N_144_0 a_9__n inst_AMIGA_BUS_ENABLE_DMA_HIGH \ +# N_158_i IPL_D0_1_ rst_dly_i_1__n clk_000_d_i_0__n a_11__n IPL_D0_2_ clk_000_d_i_1__n \ +# N_148_i inst_CLK_000_NE_D0 DTACK_D0_i N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i \ +# N_344_i SM_AMIGA_0_ CLK_030_H_i N_144_0 a_9__n inst_AMIGA_BUS_ENABLE_DMA_HIGH \ # sm_amiga_i_6__n N_138_0 inst_DSACK1_INTreg sm_amiga_i_2__n a_8__n AS_000_i N_342_i \ # pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n SM_AMIGA_4_ A1_i N_124_0 \ # inst_DS_000_ENABLE a_i_31__n N_341_i a_6__n RST_DLY_0_ a_i_29__n N_119_0 RST_DLY_1_ \ -# a_i_30__n N_340_i a_5__n RST_DLY_2_ a_i_27__n N_361_i pos_clk_un8_bg_030_n a_i_28__n \ +# a_i_30__n N_340_i a_5__n RST_DLY_2_ a_i_27__n N_361_i pos_clk_un9_bg_030_n a_i_28__n \ # cpu_est_2_0_2__n a_4__n CLK_000_P_SYNC_0_ a_i_25__n N_338_i CLK_000_P_SYNC_1_ \ # a_i_26__n N_339_i a_3__n CLK_000_P_SYNC_2_ N_213_i cpu_est_2_0_1__n \ # CLK_000_P_SYNC_3_ N_214_i N_332_i a_2__n CLK_000_P_SYNC_4_ N_215_i N_336_i \ @@ -69,7 +69,7 @@ # N_17_i N_42_0 a_c_23__n N_19_i N_40_0 SM_AMIGA_i_7_ a_c_24__n N_20_i N_123 N_39_0 \ # cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i G_134 \ # N_37_0 G_135 a_c_27__n N_25_i G_136 N_34_0 N_217 a_c_28__n N_26_i N_33_0 N_61 a_c_29__n \ -# BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un8_bg_030_0_n N_80 \ +# BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 \ # N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \ # pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c N_351_2 N_124 N_168_i_1 N_138 \ # nEXP_SPACE_c N_192_0_1 N_144 N_192_0_2 N_158 BERR_c N_137_i_1 N_168 N_137_i_2 N_175 \ @@ -94,7 +94,7 @@ # as_030_000_sync_0_un3_n N_347 N_272_i as_030_000_sync_0_un1_n N_350 N_271_i \ # as_030_000_sync_0_un0_n N_351 N_279_0 ds_000_enable_0_un3_n N_353 N_280_0 \ # ds_000_enable_0_un1_n N_361 N_281_0 ds_000_enable_0_un0_n \ -# pos_clk_un24_bgack_030_int_i_i_a4_i_x2 N_298_i as_000_int_0_un3_n \ +# pos_clk_un23_bgack_030_int_i_i_a4_i_x2 N_298_i as_000_int_0_un3_n \ # pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_size_dma_6_0_0__n as_000_int_0_un1_n \ # cpu_est_0_0_x2_0_ N_299_i as_000_int_0_un0_n pos_clk_CYCLE_DMA_5_1_i_x2 \ # pos_clk_size_dma_6_0_1__n dsack1_int_0_un3_n un22_berr_1 un1_as_000_i \ @@ -164,14 +164,14 @@ sm_amiga_i_3__n.BLIF N_350_i.BLIF rw_000_dma_0_un3_n.BLIF inst_DTACK_D0.BLIF \ cpu_est_i_0__n.BLIF N_188_0.BLIF rw_000_dma_0_un1_n.BLIF inst_RESET_OUT.BLIF \ cpu_est_i_3__n.BLIF N_187_i.BLIF rw_000_dma_0_un0_n.BLIF \ inst_CLK_OUT_PRE_50.BLIF cpu_est_i_2__n.BLIF N_185_i.BLIF a_15__n.BLIF \ -inst_CLK_000_D1.BLIF cpu_est_i_1__n.BLIF N_182_i.BLIF inst_CLK_000_D0.BLIF \ +CLK_000_D_1_.BLIF cpu_est_i_1__n.BLIF N_182_i.BLIF CLK_000_D_0_.BLIF \ VPA_D_i.BLIF N_181_i.BLIF a_14__n.BLIF inst_CLK_000_PE.BLIF CLK_000_NE_i.BLIF \ CLK_OUT_PRE_D_i.BLIF CLK_000_P_SYNC_9_.BLIF sm_amiga_i_1__n.BLIF N_175_0.BLIF \ a_13__n.BLIF inst_CLK_000_NE.BLIF rst_dly_i_2__n.BLIF N_168_i.BLIF \ CLK_000_N_SYNC_11_.BLIF CLK_030_i.BLIF AS_030_000_SYNC_i.BLIF a_12__n.BLIF \ IPL_D0_0_.BLIF rst_dly_i_0__n.BLIF N_158_i.BLIF IPL_D0_1_.BLIF \ -rst_dly_i_1__n.BLIF CLK_000_D0_i.BLIF a_11__n.BLIF IPL_D0_2_.BLIF \ -CLK_000_D1_i.BLIF N_148_i.BLIF inst_CLK_000_NE_D0.BLIF DTACK_D0_i.BLIF \ +rst_dly_i_1__n.BLIF clk_000_d_i_0__n.BLIF a_11__n.BLIF IPL_D0_2_.BLIF \ +clk_000_d_i_1__n.BLIF N_148_i.BLIF inst_CLK_000_NE_D0.BLIF DTACK_D0_i.BLIF \ N_345_i.BLIF a_10__n.BLIF pos_clk_un6_bg_030_n.BLIF RW_000_i.BLIF N_344_i.BLIF \ SM_AMIGA_0_.BLIF CLK_030_H_i.BLIF N_144_0.BLIF a_9__n.BLIF \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF sm_amiga_i_6__n.BLIF N_138_0.BLIF \ @@ -180,7 +180,7 @@ N_342_i.BLIF pos_clk_ipl_n.BLIF sm_amiga_i_0__n.BLIF N_343_i.BLIF a_7__n.BLIF \ SM_AMIGA_4_.BLIF A1_i.BLIF N_124_0.BLIF inst_DS_000_ENABLE.BLIF a_i_31__n.BLIF \ N_341_i.BLIF a_6__n.BLIF RST_DLY_0_.BLIF a_i_29__n.BLIF N_119_0.BLIF \ RST_DLY_1_.BLIF a_i_30__n.BLIF N_340_i.BLIF a_5__n.BLIF RST_DLY_2_.BLIF \ -a_i_27__n.BLIF N_361_i.BLIF pos_clk_un8_bg_030_n.BLIF a_i_28__n.BLIF \ +a_i_27__n.BLIF N_361_i.BLIF pos_clk_un9_bg_030_n.BLIF a_i_28__n.BLIF \ cpu_est_2_0_2__n.BLIF a_4__n.BLIF CLK_000_P_SYNC_0_.BLIF a_i_25__n.BLIF \ N_338_i.BLIF CLK_000_P_SYNC_1_.BLIF a_i_26__n.BLIF N_339_i.BLIF a_3__n.BLIF \ CLK_000_P_SYNC_2_.BLIF N_213_i.BLIF cpu_est_2_0_1__n.BLIF \ @@ -216,7 +216,7 @@ cpu_est_2_1__n.BLIF a_c_25__n.BLIF N_21_i.BLIF cpu_est_2_2__n.BLIF N_38_0.BLIF \ N_209.BLIF a_c_26__n.BLIF N_22_i.BLIF G_134.BLIF N_37_0.BLIF G_135.BLIF \ a_c_27__n.BLIF N_25_i.BLIF G_136.BLIF N_34_0.BLIF N_217.BLIF a_c_28__n.BLIF \ N_26_i.BLIF N_33_0.BLIF N_61.BLIF a_c_29__n.BLIF BG_030_c_i.BLIF N_127.BLIF \ -pos_clk_un6_bg_030_i_n.BLIF a_c_30__n.BLIF pos_clk_un8_bg_030_0_n.BLIF \ +pos_clk_un6_bg_030_i_n.BLIF a_c_30__n.BLIF pos_clk_un9_bg_030_0_n.BLIF \ N_80.BLIF N_289_0_1.BLIF a_c_31__n.BLIF un1_SM_AMIGA_5_i_1.BLIF N_90.BLIF \ un1_SM_AMIGA_5_i_2.BLIF N_96.BLIF A0_c.BLIF pos_clk_un8_sm_amiga_i_1_n.BLIF \ N_99.BLIF N_351_1.BLIF N_119.BLIF A1_c.BLIF N_351_2.BLIF N_124.BLIF \ @@ -259,7 +259,7 @@ as_030_000_sync_0_un1_n.BLIF N_350.BLIF N_271_i.BLIF \ as_030_000_sync_0_un0_n.BLIF N_351.BLIF N_279_0.BLIF \ ds_000_enable_0_un3_n.BLIF N_353.BLIF N_280_0.BLIF ds_000_enable_0_un1_n.BLIF \ N_361.BLIF N_281_0.BLIF ds_000_enable_0_un0_n.BLIF \ -pos_clk_un24_bgack_030_int_i_i_a4_i_x2.BLIF N_298_i.BLIF \ +pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_298_i.BLIF \ as_000_int_0_un3_n.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF \ pos_clk_size_dma_6_0_0__n.BLIF as_000_int_0_un1_n.BLIF cpu_est_0_0_x2_0_.BLIF \ N_299_i.BLIF as_000_int_0_un0_n.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF \ @@ -286,18 +286,17 @@ UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_5_.D SM_AMIGA_5_.C \ -SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D \ -SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \ -IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \ -IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D \ -IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C \ -SM_AMIGA_6_.D SM_AMIGA_6_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C \ -CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D \ -CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \ -CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \ -cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \ -cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ +SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D \ +SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D \ +IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ +IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ +IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_5_.D SM_AMIGA_5_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \ +CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ +CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ +SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \ +cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C \ CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D \ CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \ CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D \ @@ -306,33 +305,34 @@ CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D \ CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C \ CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \ CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \ -CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D \ -RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \ +CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \ +CLK_000_N_SYNC_9_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ +CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \ +CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \ CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C \ CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D \ -CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_DMA.D \ -inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ -inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \ -inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C \ -inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C \ -inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ -BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ +CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_INT.D \ +inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \ +inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \ +inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ +inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D \ +inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ +BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \ inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \ inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \ -inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_000_D1.D \ -inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ +inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C \ +inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D \ +inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ -inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C \ -inst_CLK_000_NE.D inst_CLK_000_NE.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 \ -LDS_000 A0 BERR RW SIZE_0_ N_280 N_210_0 cpu_est_0_1__un0_n N_279 N_289_0 \ -cpu_est_0_2__un3_n N_271 N_218_0 cpu_est_0_2__un1_n N_272 cpu_est_0_2__un0_n \ -N_276 N_242_i cpu_est_0_3__un3_n DS_000_ENABLE_1_sqmuxa_1 N_246_i \ -cpu_est_0_3__un1_n N_4 N_240_i cpu_est_0_3__un0_n vcc_n_n N_5 N_241_i \ +inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C \ +inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 RW_000 \ +UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_280 N_210_0 cpu_est_0_1__un0_n N_279 \ +N_289_0 cpu_est_0_2__un3_n N_271 N_218_0 cpu_est_0_2__un1_n N_272 \ +cpu_est_0_2__un0_n N_276 N_242_i cpu_est_0_3__un3_n DS_000_ENABLE_1_sqmuxa_1 \ +N_246_i cpu_est_0_3__un1_n N_4 N_240_i cpu_est_0_3__un0_n vcc_n_n N_5 N_241_i \ ipl_030_0_0__un3_n N_7 ipl_030_0_0__un1_n gnd_n_n N_10 N_266_i \ ipl_030_0_0__un0_n un1_amiga_bus_enable_low N_18 N_267_i ipl_030_0_1__un3_n \ un3_size N_24 N_254_i ipl_030_0_1__un1_n un4_size N_6 N_317_i \ @@ -358,20 +358,20 @@ N_188_0 rw_000_dma_0_un1_n cpu_est_i_3__n N_187_i rw_000_dma_0_un0_n \ cpu_est_i_2__n N_185_i a_15__n cpu_est_i_1__n N_182_i VPA_D_i N_181_i a_14__n \ CLK_000_NE_i CLK_OUT_PRE_D_i sm_amiga_i_1__n N_175_0 a_13__n rst_dly_i_2__n \ N_168_i CLK_030_i AS_030_000_SYNC_i a_12__n rst_dly_i_0__n N_158_i \ -rst_dly_i_1__n CLK_000_D0_i a_11__n CLK_000_D1_i N_148_i DTACK_D0_i N_345_i \ -a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i CLK_030_H_i N_144_0 a_9__n \ -sm_amiga_i_6__n N_138_0 sm_amiga_i_2__n a_8__n AS_000_i N_342_i pos_clk_ipl_n \ -sm_amiga_i_0__n N_343_i a_7__n A1_i N_124_0 a_i_31__n N_341_i a_6__n a_i_29__n \ -N_119_0 a_i_30__n N_340_i a_5__n a_i_27__n N_361_i pos_clk_un8_bg_030_n \ -a_i_28__n cpu_est_2_0_2__n a_4__n a_i_25__n N_338_i a_i_26__n N_339_i a_3__n \ -N_213_i cpu_est_2_0_1__n N_214_i N_332_i a_2__n N_215_i N_336_i \ -pos_clk_un7_clk_000_pe_0_n N_275_i N_99_0 un6_ds_030_i N_331_i DS_000_DMA_i \ -N_96_0 un4_as_000_i N_330_i AS_000_INT_i N_90_0 un4_lds_000_i N_328_i \ -un4_uds_000_i AS_030_c N_80_0 N_325_i AS_000_c N_326_i N_258_0 RW_000_c \ -N_217_i N_321_i N_322_i UDS_000_c N_320_i pos_clk_un7_clk_000_pe_n LDS_000_c \ -un5_ciin_i pos_clk_a0_dma_3_n size_c_0__n N_61_0 N_310_i size_c_1__n N_305_i \ -N_307_i N_3 N_303_i N_8 N_304_i N_283_0 N_301_i N_300_i N_123_0 N_17 N_278_i \ -N_19 N_297_i N_20 AMIGA_BUS_DATA_DIR_c_0 N_21 N_277_i N_22 N_25 N_26 \ +rst_dly_i_1__n clk_000_d_i_0__n a_11__n clk_000_d_i_1__n N_148_i DTACK_D0_i \ +N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i CLK_030_H_i N_144_0 \ +a_9__n sm_amiga_i_6__n N_138_0 sm_amiga_i_2__n a_8__n AS_000_i N_342_i \ +pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n A1_i N_124_0 a_i_31__n N_341_i \ +a_6__n a_i_29__n N_119_0 a_i_30__n N_340_i a_5__n a_i_27__n N_361_i \ +pos_clk_un9_bg_030_n a_i_28__n cpu_est_2_0_2__n a_4__n a_i_25__n N_338_i \ +a_i_26__n N_339_i a_3__n N_213_i cpu_est_2_0_1__n N_214_i N_332_i a_2__n \ +N_215_i N_336_i pos_clk_un7_clk_000_pe_0_n N_275_i N_99_0 un6_ds_030_i N_331_i \ +DS_000_DMA_i N_96_0 un4_as_000_i N_330_i AS_000_INT_i N_90_0 un4_lds_000_i \ +N_328_i un4_uds_000_i AS_030_c N_80_0 N_325_i AS_000_c N_326_i N_258_0 \ +RW_000_c N_217_i N_321_i N_322_i UDS_000_c N_320_i pos_clk_un7_clk_000_pe_n \ +LDS_000_c un5_ciin_i pos_clk_a0_dma_3_n size_c_0__n N_61_0 N_310_i size_c_1__n \ +N_305_i N_307_i N_3 N_303_i N_8 N_304_i N_283_0 N_301_i N_300_i N_123_0 N_17 \ +N_278_i N_19 N_297_i N_20 AMIGA_BUS_DATA_DIR_c_0 N_21 N_277_i N_22 N_25 N_26 \ pos_clk_un8_sm_amiga_i_n N_27 A0_c_i N_28 size_c_i_1__n N_29 N_29_i N_32_0 \ N_28_i N_31_0 N_27_i N_30_0 ipl_c_i_2__n N_53_0 ipl_c_i_1__n N_52_0 a_c_16__n \ ipl_c_i_0__n N_51_0 a_c_17__n DTACK_c_i N_56_0 a_c_18__n VPA_c_i N_55_0 \ @@ -379,7 +379,7 @@ a_c_19__n nEXP_SPACE_c_i N_54_0 a_c_20__n N_3_i N_49_0 a_c_21__n N_8_i N_45_0 \ a_c_22__n N_17_i N_42_0 a_c_23__n N_19_i N_40_0 a_c_24__n N_20_i N_123 N_39_0 \ cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i \ N_37_0 a_c_27__n N_25_i N_34_0 N_217 a_c_28__n N_26_i N_33_0 N_61 a_c_29__n \ -BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un8_bg_030_0_n N_80 \ +BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 \ N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \ pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c N_351_2 N_124 N_168_i_1 \ N_138 nEXP_SPACE_c N_192_0_1 N_144 N_192_0_2 N_158 BERR_c N_137_i_1 N_168 \ @@ -423,10 +423,8 @@ pos_clk_size_dma_6_0__n N_207_0 sm_amiga_srsts_i_0_m2_5__un0_n N_298 N_354_i \ cpu_est_0_1__un3_n N_281 N_208_0 cpu_est_0_1__un1_n AS_030.OE AS_000.OE \ RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE \ DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_134 G_135 G_136 \ -pos_clk_un24_bgack_030_int_i_i_a4_i_x2 pos_clk_CYCLE_DMA_5_0_i_x2 \ +pos_clk_un23_bgack_030_int_i_i_a4_i_x2 pos_clk_CYCLE_DMA_5_0_i_x2 \ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 -.names N_141_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D -11 1 .names N_139_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D 11 1 .names N_137_i_1.BLIF N_137_i_2.BLIF SM_AMIGA_3_.D @@ -453,6 +451,8 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 11 1 .names N_258_0.BLIF SM_AMIGA_6_.D 0 1 +.names N_141_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D +11 1 .names N_282_i_1.BLIF N_210_0.BLIF CYCLE_DMA_0_.D 11 1 .names N_134_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF CYCLE_DMA_1_.D @@ -476,14 +476,10 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 11 1 .names N_259_i_1.BLIF N_259_i_2.BLIF RST_DLY_2_.D 11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF CLK_000_P_SYNC_0_.D 11 1 .names N_261_i_1.BLIF N_322_i.BLIF RST_DLY_0_.D 11 1 -.names N_45_0.BLIF inst_AS_000_DMA.D -0 1 -.names N_46_0.BLIF inst_AS_030_000_SYNC.D -0 1 .names N_47_0.BLIF inst_AS_000_INT.D 0 1 .names N_48_0.BLIF inst_DSACK1_INTreg.D @@ -524,6 +520,10 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 0 1 .names N_43_0.BLIF inst_BGACK_030_INTreg.D 0 1 +.names N_45_0.BLIF inst_AS_000_DMA.D +0 1 +.names N_46_0.BLIF inst_AS_030_000_SYNC.D +0 1 .names N_210_0.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D @@ -726,13 +726,13 @@ amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n 0 1 .names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_212_0 11 1 -.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n 0 1 .names inst_CLK_000_PE.BLIF CLK_000_PE_i 0 1 .names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_211_0 11 1 -.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n 11 1 .names a_c_16__n.BLIF a_i_16__n 0 1 @@ -846,17 +846,17 @@ amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n 11 1 .names RST_DLY_1_.BLIF rst_dly_i_1__n 0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n 0 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n 0 1 -.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_148_i +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_148_i 11 1 .names inst_DTACK_D0.BLIF DTACK_D0_i 0 1 .names N_345.BLIF N_345_i 0 1 -.names pos_clk_un6_bg_030_1_n.BLIF inst_CLK_000_D0.BLIF pos_clk_un6_bg_030_n +.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n 11 1 .names RW_000_c.BLIF RW_000_i 0 1 @@ -902,7 +902,7 @@ amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n 0 1 .names N_361.BLIF N_361_i 0 1 -.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n 0 1 .names a_c_28__n.BLIF a_i_28__n 0 1 @@ -1140,7 +1140,7 @@ pos_clk_un8_sm_amiga_i_n 11 1 .names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n 0 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un8_bg_030_0_n +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n 11 1 .names N_80_0.BLIF N_80 0 1 @@ -1174,7 +1174,7 @@ pos_clk_un8_sm_amiga_i_n 11 1 .names N_144_0.BLIF N_144 0 1 -.names pos_clk_un24_bgack_030_int_i_i_a4_i_x2.BLIF N_345_i.BLIF N_192_0_2 +.names pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_345_i.BLIF N_192_0_2 11 1 .names N_158_i.BLIF N_158 0 1 @@ -1704,9 +1704,6 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -1746,10 +1743,7 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 0 0 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 0 0 .names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D @@ -1875,12 +1869,30 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C 1 1 0 0 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF RST_DLY_1_.C 1 1 0 0 .names CLK_OSZI_c.BLIF RST_DLY_2_.C 1 1 0 0 +.names CLK_000.BLIF CLK_000_D_0_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C +1 1 +0 0 +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_1_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C 1 1 0 0 @@ -1911,12 +1923,6 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF RST_DLY_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_AS_000_INT.C 1 1 0 0 @@ -1977,18 +1983,15 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C -1 1 -0 0 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C -1 1 -0 0 .names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D 1 1 0 0 @@ -2007,12 +2010,6 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 0 0 -.names CLK_000.BLIF inst_CLK_000_D0.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C -1 1 -0 0 .names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D 1 1 0 0 @@ -2025,6 +2022,9 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF inst_CLK_000_NE.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +1 1 +0 0 .names un3_size.BLIF SIZE_1_ 1 1 0 0 @@ -2278,7 +2278,7 @@ sm_amiga_srsts_i_0_m2_5__un0_n 11 0 00 0 .names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ -pos_clk_un24_bgack_030_int_i_i_a4_i_x2 +pos_clk_un23_bgack_030_int_i_i_a4_i_x2 01 1 10 1 11 0 diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index 82345e5..2fa153c 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2016 1 27 21 56 45) + (timeStamp 2016 8 17 17 45 43) (author "Synopsys, Inc.") (program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R")) ) @@ -140,8 +140,6 @@ (port CIIN (direction OUTPUT)) ) (contents - (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -168,7 +166,7 @@ ) (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -218,10 +216,16 @@ ) (instance (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename RST_DLY_1 "RST_DLY[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename RST_DLY_2 "RST_DLY[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance (rename CLK_000_D_0 "CLK_000_D[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_D_1 "CLK_000_D[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_P_SYNC_1 "CLK_000_P_SYNC[1]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -234,10 +238,6 @@ ) (instance (rename RST_DLY_0 "RST_DLY[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance AS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AS_030_000_SYNC (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance AS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance DSACK1_INT (viewRef prim (cellRef DFF (libraryRef mach))) @@ -278,24 +278,24 @@ ) (instance BGACK_030_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance AS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_030_000_SYNC (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance BGACK_030_INT_D (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance CLK_OUT_PRE_50 (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance CLK_000_D1 (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance CLK_000_NE_D0 (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance CLK_OUT_PRE_D (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance CLK_OUT_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance CLK_000_D0 (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance CLK_000_PE (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance CLK_000_NE (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance CLK_OUT_PRE_50 (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance AS_030 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) (instance AS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) (instance RW_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) @@ -459,9 +459,9 @@ (instance (rename SM_AMIGA_srsts_i_i_a2_2 "SM_AMIGA_srsts_i_i_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_nss_i_i_0_o2_1_0_0 "SM_AMIGA_nss_i_i_0_o2_1_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_nss_i_i_0_o2_0 "SM_AMIGA_nss_i_i_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un24_bgack_030_int_i_i_a4_i_o3_1 "pos_clk.un24_bgack_030_int_i_i_a4_i_o3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un24_bgack_030_int_i_i_a4_i_o3_2 "pos_clk.un24_bgack_030_int_i_i_a4_i_o3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un24_bgack_030_int_i_i_a4_i_o3 "pos_clk.un24_bgack_030_int_i_i_a4_i_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_o3_1 "pos_clk.un23_bgack_030_int_i_i_a4_i_o3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_o3_2 "pos_clk.un23_bgack_030_int_i_i_a4_i_o3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_o3 "pos_clk.un23_bgack_030_int_i_i_a4_i_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_0_0_1_3 "SM_AMIGA_srsts_i_0_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_0_0_2_3 "SM_AMIGA_srsts_i_0_0_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_0_0_3 "SM_AMIGA_srsts_i_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -476,7 +476,7 @@ (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un8_bg_030_i "pos_clk.un8_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un9_bg_030_i "pos_clk.un9_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_un37_as_030_d0_i_o2_1 "pos_clk.un37_as_030_d0_i_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un37_as_030_d0_i_o2 "pos_clk.un37_as_030_d0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_SM_AMIGA_5_0_o3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -568,7 +568,7 @@ (instance (rename SM_AMIGA_nss_i_i_0_o2_i_0 "SM_AMIGA_nss_i_i_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance RST_DLY_e2_i_0_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_345_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_344_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance RST_DLY_e2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -586,7 +586,7 @@ (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_nss_i_i_0_o2_0_i_0 "SM_AMIGA_nss_i_i_0_o2_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_un5_bgack_030_int_d_i_0_a4_i_o3_i "pos_clk.un5_bgack_030_int_d_i_0_a4_i_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un24_bgack_030_int_i_i_a4_i_o3_i "pos_clk.un24_bgack_030_int_i_i_a4_i_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_o3_i "pos_clk.un23_bgack_030_int_i_i_a4_i_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename CLK_000_N_SYNC_i_10 "CLK_000_N_SYNC_i[10]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_350_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DSACK1_INT_0_sqmuxa_i_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -792,9 +792,9 @@ (instance (rename SM_AMIGA_srsts_i_0_0_o2_3 "SM_AMIGA_srsts_i_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance CLK_030_H_2_0_a2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un6_as_030_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un24_bgack_030_int_i_i_a4_i_x2 "pos_clk.un24_bgack_030_int_i_i_a4_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_x2 "pos_clk.un23_bgack_030_int_i_i_a4_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) (instance RST_DLY_e2_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0 "pos_clk.CLK_000_N_SYNC_2_0_a4_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename RST_DLY_i_0 "RST_DLY_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename RST_DLY_i_1 "RST_DLY_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -829,7 +829,7 @@ (instance (rename cpu_est_2_i_0_i_a3_3 "cpu_est_2_i_0_i_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un5_e_i_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance RST_DLY_e2_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un24_bgack_030_int_i_i_a4_i_a2 "pos_clk.un24_bgack_030_int_i_i_a4_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_a2 "pos_clk.un23_bgack_030_int_i_i_a4_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_0_0_a2_3 "SM_AMIGA_srsts_i_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DSACK1_INT_0_sqmuxa_i_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance RST_DLYlde_i_a4_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -866,6 +866,7 @@ (instance A1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a3 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance G_129 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance N_213_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_214_i (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -876,7 +877,6 @@ (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance nEXP_SPACE_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -940,7 +940,7 @@ (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un8_bg_030 "pos_clk.un8_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un4_uds_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un4_lds_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -1114,12 +1114,12 @@ (net (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (joined (portRef Q (instanceRef CYCLE_DMA_0)) (portRef I1 (instanceRef G_129)) - (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_x2)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_x2)) (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2)) )) (net (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (joined (portRef Q (instanceRef CYCLE_DMA_1)) - (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_x2)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_x2)) (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) )) (net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined @@ -1170,17 +1170,17 @@ (portRef I0 (instanceRef CLK_OUT_PRE_50_i)) (portRef D (instanceRef CLK_OUT_PRE_D)) )) - (net CLK_000_D1 (joined - (portRef Q (instanceRef CLK_000_D1)) - (portRef I1 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0)) - (portRef I0 (instanceRef CLK_000_D1_i)) + (net (rename CLK_000_D_1 "CLK_000_D[1]") (joined + (portRef Q (instanceRef CLK_000_D_1)) + (portRef I0 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0)) + (portRef I0 (instanceRef CLK_000_D_i_1)) )) - (net CLK_000_D0 (joined - (portRef Q (instanceRef CLK_000_D0)) + (net (rename CLK_000_D_0 "CLK_000_D[0]") (joined + (portRef Q (instanceRef CLK_000_D_0)) (portRef I0 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a3_0)) - (portRef I0 (instanceRef CLK_000_D0_i)) + (portRef I0 (instanceRef CLK_000_D_i_0)) (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_0_a3)) - (portRef D (instanceRef CLK_000_D1)) + (portRef D (instanceRef CLK_000_D_1)) )) (net CLK_000_PE (joined (portRef Q (instanceRef CLK_000_PE)) @@ -1298,8 +1298,8 @@ (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2)) (portRef I0 (instanceRef RST_DLY_i_2)) )) - (net (rename pos_clk_un8_bg_030 "pos_clk.un8_bg_030") (joined - (portRef O (instanceRef pos_clk_un8_bg_030_i)) + (net (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (joined + (portRef O (instanceRef pos_clk_un9_bg_030_i)) (portRef I1 (instanceRef BG_000_0_m)) (portRef I0 (instanceRef BG_000_0_r)) )) @@ -1738,7 +1738,7 @@ (portRef I0 (instanceRef DSACK1_INT_0_sqmuxa_i_i_a3)) )) (net N_192 (joined - (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_i)) + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_i)) (portRef I0 (instanceRef AS_000_DMA_0_m)) )) (net N_193 (joined @@ -1987,7 +1987,7 @@ (portRef I0 (instanceRef N_344_i)) )) (net N_345 (joined - (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_a2)) + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_a2)) (portRef I0 (instanceRef N_345_i)) )) (net N_347 (joined @@ -2013,8 +2013,8 @@ (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0_1)) )) (net N_140_i (joined - (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_x2)) - (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_2)) + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_x2)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_2)) )) (net N_228_i (joined (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2)) @@ -2189,7 +2189,7 @@ (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a3_0)) (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a3_1)) (portRef I1 (instanceRef un1_amiga_bus_enable_low)) - (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_1)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_1)) )) (net AMIGA_BUS_ENABLE_DMA_LOW_i (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) @@ -2376,8 +2376,8 @@ (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_1)) (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_0)) )) - (net CLK_000_D1_i (joined - (portRef O (instanceRef CLK_000_D1_i)) + (net (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (joined + (portRef O (instanceRef CLK_000_D_i_1)) (portRef I1 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a3_0)) )) (net DTACK_D0_i (joined @@ -2410,7 +2410,7 @@ (portRef O (instanceRef I_199)) (portRef I0 (instanceRef un6_ds_030)) (portRef I1 (instanceRef un6_as_030_i_0)) - (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_1)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_1)) (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0_1)) @@ -2529,7 +2529,7 @@ (net UDS_000_c (joined (portRef O (instanceRef UDS_000)) (portRef I1 (instanceRef pos_clk_A0_DMA_3_0_a3)) - (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_a2)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_a2)) (portRef I0 (instanceRef UDS_000_c_i)) )) (net UDS_000 (joined @@ -2538,7 +2538,7 @@ )) (net LDS_000_c (joined (portRef O (instanceRef LDS_000)) - (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_a2)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_a2)) (portRef I0 (instanceRef LDS_000_c_i)) )) (net LDS_000 (joined @@ -2869,7 +2869,7 @@ )) (net CLK_000_c (joined (portRef O (instanceRef CLK_000)) - (portRef D (instanceRef CLK_000_D0)) + (portRef D (instanceRef CLK_000_D_0)) )) (net CLK_000 (joined (portRef CLK_000) @@ -2887,8 +2887,8 @@ (portRef CLK (instanceRef BGACK_030_INT)) (portRef CLK (instanceRef BGACK_030_INT_D)) (portRef CLK (instanceRef BG_000DFF)) - (portRef CLK (instanceRef CLK_000_D0)) - (portRef CLK (instanceRef CLK_000_D1)) + (portRef CLK (instanceRef CLK_000_D_0)) + (portRef CLK (instanceRef CLK_000_D_1)) (portRef CLK (instanceRef CLK_000_NE)) (portRef CLK (instanceRef CLK_000_NE_D0)) (portRef CLK (instanceRef CLK_000_N_SYNC_0)) @@ -3519,10 +3519,10 @@ (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_o2_1)) )) (net N_192_0 (joined - (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3)) + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3)) (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i)) (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i)) - (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_i)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_i)) (portRef I0 (instanceRef CLK_030_H_2_0_a2_i_1)) (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_1)) )) @@ -3583,9 +3583,9 @@ (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2)) (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_0_i)) )) - (net CLK_000_D0_i (joined - (portRef O (instanceRef CLK_000_D0_i)) - (portRef I0 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0)) + (net (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (joined + (portRef O (instanceRef CLK_000_D_i_0)) + (portRef I1 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0)) )) (net N_148_i (joined (portRef O (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0)) @@ -3594,7 +3594,7 @@ )) (net N_345_i (joined (portRef O (instanceRef N_345_i)) - (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_2)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_2)) )) (net N_344_i (joined (portRef O (instanceRef N_344_i)) @@ -3977,15 +3977,15 @@ )) (net BG_030_c_i (joined (portRef O (instanceRef BG_030_c_i)) - (portRef I0 (instanceRef pos_clk_un8_bg_030)) + (portRef I0 (instanceRef pos_clk_un9_bg_030)) )) (net (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (joined (portRef O (instanceRef pos_clk_un6_bg_030_i)) - (portRef I1 (instanceRef pos_clk_un8_bg_030)) + (portRef I1 (instanceRef pos_clk_un9_bg_030)) )) - (net (rename pos_clk_un8_bg_030_0 "pos_clk.un8_bg_030_0") (joined - (portRef O (instanceRef pos_clk_un8_bg_030)) - (portRef I0 (instanceRef pos_clk_un8_bg_030_i)) + (net (rename pos_clk_un9_bg_030_0 "pos_clk.un9_bg_030_0") (joined + (portRef O (instanceRef pos_clk_un9_bg_030)) + (portRef I0 (instanceRef pos_clk_un9_bg_030_i)) )) (net N_289_0_1 (joined (portRef O (instanceRef pos_clk_un37_as_030_d0_i_o2_1)) @@ -4016,12 +4016,12 @@ (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o2_0)) )) (net N_192_0_1 (joined - (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_1)) - (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3)) + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_1)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3)) )) (net N_192_0_2 (joined - (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3_2)) - (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_i_a4_i_o3)) + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_2)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3)) )) (net N_137_i_1 (joined (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) diff --git a/Logic/BUS68030.fse b/Logic/BUS68030.fse index f43bb72..b89de70 100644 --- a/Logic/BUS68030.fse +++ b/Logic/BUS68030.fse @@ -1,20 +1,20 @@ -fsm_encoding {7138371381} onehot +fsm_encoding {7134371341} onehot -fsm_state_encoding {7138371381} idle_p {00000000} +fsm_state_encoding {7134371341} idle_p {00000000} -fsm_state_encoding {7138371381} idle_n {00000011} +fsm_state_encoding {7134371341} idle_n {00000011} -fsm_state_encoding {7138371381} as_set_p {00000101} +fsm_state_encoding {7134371341} as_set_p {00000101} -fsm_state_encoding {7138371381} as_set_n {00001001} +fsm_state_encoding {7134371341} as_set_n {00001001} -fsm_state_encoding {7138371381} sample_dtack_p {00010001} +fsm_state_encoding {7134371341} sample_dtack_p {00010001} -fsm_state_encoding {7138371381} data_fetch_n {00100001} +fsm_state_encoding {7134371341} data_fetch_n {00100001} -fsm_state_encoding {7138371381} data_fetch_p {01000001} +fsm_state_encoding {7134371341} data_fetch_p {01000001} -fsm_state_encoding {7138371381} end_cycle_n {10000001} +fsm_state_encoding {7134371341} end_cycle_n {10000001} -fsm_registers {7138371381} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]} +fsm_registers {7134371341} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]} diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index 2c08c14..d8c8daa 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj -#-- Written on Wed Jan 27 21:56:36 2016 +#-- Written on Wed Aug 17 17:45:34 2016 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index efef759..36e5e5d 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -1,29 +1,29 @@ %%% protect protected_file -f "c:\isplever\synpbase\lib\vhd\std.vhd"; #file 0 +f "e:\isplever_classic2_0\synpbase\lib\vhd\std.vhd"; #file 0 af .is_vhdl 1; af .child_list "-1"; af .parent_list "-1"; -f "c:\isplever\synpbase\lib\vhd\snps_haps_pkg.vhd"; #file 1 +f "e:\isplever_classic2_0\synpbase\lib\vhd\snps_haps_pkg.vhd"; #file 1 af .is_vhdl 1; af .child_list "-1"; af .parent_list "-1"; -f "c:\isplever\synpbase\lib\vhd\std1164.vhd"; #file 2 +f "e:\isplever_classic2_0\synpbase\lib\vhd\std1164.vhd"; #file 2 af .is_vhdl 1; af .child_list "-1"; af .parent_list "-1"; -f "c:\isplever\synpbase\lib\vhd\numeric.vhd"; #file 3 +f "e:\isplever_classic2_0\synpbase\lib\vhd\numeric.vhd"; #file 3 af .is_vhdl 1; af .child_list "-1"; af .parent_list "-1"; -f "c:\isplever\synpbase\lib\vhd\umr_capim.vhd"; #file 4 +f "e:\isplever_classic2_0\synpbase\lib\vhd\umr_capim.vhd"; #file 4 af .is_vhdl 1; af .child_list "-1"; af .parent_list "-1"; -f "c:\isplever\synpbase\lib\vhd\arith.vhd"; #file 5 +f "e:\isplever_classic2_0\synpbase\lib\vhd\arith.vhd"; #file 5 af .is_vhdl 1; af .child_list "-1"; af .parent_list "-1"; -f "c:\isplever\synpbase\lib\vhd\unsigned.vhd"; #file 6 +f "e:\isplever_classic2_0\synpbase\lib\vhd\unsigned.vhd"; #file 6 af .is_vhdl 1; af .child_list "-1"; af .parent_list "-1"; @@ -181,13 +181,13 @@ B;bjRf:VjRNCD#RDVN#tCRh ftell; @E@MR@4(:d::(44d:cIRRFRs Anz1UjjdRELCNFPHs;ND -RNP3MDHCRMF6 -j;N3PRHE#P84DR;P +RNP3MDHCRMFc +n;N3PRHE#P84DR;P NR#3H_8PED;R4 RNP3ONsEDVHC;R( RNP38lFkVDCHRDC(N; P#R3$VM_lRNb"sIF "R\B\:\ks#C#l\\NC0x\F\8OCklM\0#\0oHE\kL\jnUd j0\F\Do\HO\jnUdnj-Ujjj-#Lk38PE\M"\"N; -POR3DMCNk#b_0.Cb_l0HC3RjjUcn(;6j +POR3DMCNk#b_0.Cb_l0HC3Rjj.d46;jj RNP3CODNbMk_C#0b04_HRlCj43j66n.jN; POR3F0M#N_M0sRCo"qAtBji_dQj_hua_)4 R"N; P#R30Dl0H0#0HRlCjj3jjjjj;P @@ -202,8 +202,8 @@ PVR3D_FIDbFF#s_LFM CR j;}N; P$R#M#_HlCHG8MDNo;R4 RNP3M#$_#lV_FoskHb_8;Rj -RNP3M#$_lMkOsEN#nRUn -c;N3PR#_$MD HMC8sHRq"{q gqU-(7.A U-7c77.-g.(d-gAww(U(6A}w4"N; +RNP3M#$_lMkOsEN#nRU. +U;N3PR#_$MD HMC8sHRn"{c(dU7-7UdqBq-.cwqn-Uq(4-w4AUc(4nn}dU"N; POR38#L_NRPC{P NRM#$_VsCCMsCOOC_D FORN{ P$R1#l0CRN{ @@ -709,7 +709,7 @@ RoM)jW_j7j_vjq_3jkM;M NRN3#PMC_CV0_D#No46R.nb; Rj@@:44::.4:+:4j0CskR:fjjsR0k0CRsRkCe;BB @bR@4j::44::4.+jN:VDR#Cfjj:RDVN#VCRNCD#R7th;R -b@:@(4:dUd4(:ddU:gj+4:_1vqtvQq:rj(f9RjR:jo#EF0vR1_Qqvtjqr:R(9h4_(,(h_._,h(hd,_,(ch6_(,(h_n_,h(h(,_;(U +b@:@(4:dcd4(:ddc:gj+4:_1vqtvQq:rj(f9RjR:jo#EF0vR1_Qqvtjqr:R(9h4_(,(h_._,h(hd,_,(ch6_(,(h_n_,h(h(,_;(U Robm9rj;b NRM#$_sbF0NVDon#Rco; brRm4 @@ -727,7 +727,7 @@ NRM#$_sbF0NVDon#Rco; brRm( 9;N#bR$bM_FVs0D#NoR;nc RNH3Ds0CF_0R -4;N#HR$VM_#Hl_8(R"4ddU(U4d4 +4;N#HR$VM_#Hl_8(R"4ddc(c4d4 ";N3HRs_0DFosHMCNlRv"1_Qqvt;q" RNH3lV#_FVslR#0"_1vqtvQq"Rd;H NR#3VlF_0#"0R1qv_vqQtR;U" @@ -735,12 +735,12 @@ RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j RNH3lV#_HFsolMNC1R"vv_qQ"tq;H NR#3Vl0_#Ns0CC4oR;H NR03#N_0ClbNbHRMo"RRRjjjjj4jjRR->jjjjjjjj\RMRRjjjj4jjj>R-Rjjjj4jj4R\MRjRjj4jjj-jR>jRjj4jjjM4\RjRRj4jjjRjj-j>Rj4jjj\j4MRRRj4jjjjjjRR->j4jjj4jj\RMRR4jjjjjjj>R-R4jjjjjj4R\MR4Rjjjjjj-jR>4RjjjjjjM4\R4RRjjjjjRjj-4>Rjjjjj\j4M -";s@R@(d:4U(:d:U4d:+dg41j:vv_qQrtqj9:(R:fjjNRlO7ERwbwRsRHl1qv_vqQtr -69S1T=vv_qQrtq6S9 -7_=h4_c4HB +";s@R@(d:4c(:d:c4d:+dg41j:vv_qQrtqj9:(R:fjjNRlO7ERwbwRsRHl1qv_vqQtr +c9S1T=vv_qQrtqcS9 +7_=h4_dgHB SpBi=pmi_1_ZQON; HsR30_DC04FR;H -NRM#$_lV#_RH8"d(4U4d(d"U4;H +NRM#$_lV#_RH8"d(4c4d(d"c4;H NR03sDs_FHNoMl"CR1qv_vqQt"N; HVR3#Vl_s#Fl01R"vv_qQRtqd ";N3HRV_#l00F#Rv"1_QqvtUqR"N; @@ -748,12 +748,12 @@ HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjj HVR3#Fl_sMHoNRlC"_1vqtvQq ";N3HRV_#l#00NCosCR 4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R -s@:@(4:dUd4(:ddU:gj+4:_1vqtvQq:rj(f9RjR:jlENORw7wRHbslvR1_Qqvtcqr9T -S=_1vqtvQq9rc -=S7hd_4g +s@:@(4:dcd4(:ddc:gj+4:_1vqtvQq:rj(f9RjR:jlENORw7wRHbslvR1_Qqvtdqr9T +S=_1vqtvQq9rd +=S7hd_4( _HSiBp=iBp_Zm1Q;_O RNH3Ds0CF_0R -4;N#HR$VM_#Hl_8(R"4ddU(U4d4 +4;N#HR$VM_#Hl_8(R"4ddc(c4d4 ";N3HRs_0DFosHMCNlRv"1_Qqvt;q" RNH3lV#_FVslR#0"_1vqtvQq"Rd;H NR#3VlF_0#"0R1qv_vqQtR;U" @@ -761,38 +761,12 @@ RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j RNH3lV#_HFsolMNC1R"vv_qQ"tq;H NR#3Vl0_#Ns0CC4oR;H NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9 -';s@R@(d:4U(:d:U4d:+dg41j:vv_qQrtqj9:(R:fjjNRlO7ERwbwRsRHl1qv_vqQtr -d9S1T=vv_qQrtqdS9 -7_=h4_d(HB -SpBi=pmi_1_ZQON; -HsR30_DC04FR;H -NRM#$_lV#_RH8"d(4U4d(d"U4;H -NR03sDs_FHNoMl"CR1qv_vqQt"N; -HVR3#Vl_s#Fl01R"vv_qQRtqd -";N3HRV_#l00F#Rv"1_QqvtUqR"N; -HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N; -HVR3#Fl_sMHoNRlC"_1vqtvQq -";N3HRV_#l#00NCosCR -4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R -s@:@(4:dUd4(:ddU:gj+4:_1vqtvQq:rj(f9RjR:jlENORw7wRHbslvR1_Qqvt.qr9T -S=_1vqtvQq9r. -=S7hU_.dB -SpBi=pmi_1_ZQON; -HsR30_DC04FR;H -NRM#$_lV#_RH8"d(4U4d(d"U4;H -NR03sDs_FHNoMl"CR1qv_vqQt"N; -HVR3#Vl_s#Fl01R"vv_qQRtqd -";N3HRV_#l00F#Rv"1_QqvtUqR"N; -HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N; -HVR3#Fl_sMHoNRlC"_1vqtvQq -";N3HRV_#l#00NCosCR -4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R -s@:@(4:dUd4(:ddU:gj+4:_1vqtvQq:rj(f9RjR:jlENORw7wRHbslvR1_Qqvt4qr9T -S=_1vqtvQq9r4 -=S7hd_4d -_HSiBp=iBp_Zm1Q;_O +';s@R@(d:4c(:d:c4d:+dg41j:vv_qQrtqj9:(R:fjjNRlO7ERwbwRsRHl1qv_vqQtr +.9S1T=vv_qQrtq.S9 +7_=h. +UdSiBp=iBp_Zm1Q;_O RNH3Ds0CF_0R -4;N#HR$VM_#Hl_8(R"4ddU(U4d4 +4;N#HR$VM_#Hl_8(R"4ddc(c4d4 ";N3HRs_0DFosHMCNlRv"1_Qqvt;q" RNH3lV#_FVslR#0"_1vqtvQq"Rd;H NR#3VlF_0#"0R1qv_vqQtR;U" @@ -800,12 +774,12 @@ RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j RNH3lV#_HFsolMNC1R"vv_qQ"tq;H NR#3Vl0_#Ns0CC4oR;H NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9 -';s@R@(d:4U(:d:U4d:+dg41j:vv_qQrtqj9:(R:fjjNRlO7ERwbwRsRHl1qv_vqQtr -j9S1T=vv_qQrtqjS9 -7_=h4_d4HB +';s@R@(d:4c(:d:c4d:+dg41j:vv_qQrtqj9:(R:fjjNRlO7ERwbwRsRHl1qv_vqQtr +49S1T=vv_qQrtq4S9 +7_=h4_ddHB SpBi=pmi_1_ZQON; HsR30_DC04FR;H -NRM#$_lV#_RH8"d(4U4d(d"U4;H +NRM#$_lV#_RH8"d(4c4d(d"c4;H NR03sDs_FHNoMl"CR1qv_vqQt"N; HVR3#Vl_s#Fl01R"vv_qQRtqd ";N3HRV_#l00F#Rv"1_QqvtUqR"N; @@ -813,66 +787,92 @@ HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjj HVR3#Fl_sMHoNRlC"_1vqtvQq ";N3HRV_#l#00NCosCR 4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R -s@:@(4:dUd4(:ddU:gj+4:pQu_jjdrj.:9jRf:ljRNROE7RwwblsHRpQu_jjd7rwwjS9 -Tu=Qpd_jjr_OjS9 -7_=hdSj -B=piB_pimQ1Z_ -O;N3HRs_0DFosHMCNlRu"Qpd_jj -";N3HRksMVNHO_MG8CR -j;s@R@(d:4U(:d:U4d:+dg4Qj:ujp_d.jr:Rj9fjj:ROlNEwR7wsRbHQlRujp_dwj7w9r4 -=STQ_upj_djO9r4 -=S7h4_d +s@:@(4:dcd4(:ddc:gj+4:_1vqtvQq:rj(f9RjR:jlENORw7wRHbslvR1_Qqvtjqr9T +S=_1vqtvQq9rj +=S7hd_44 +_HSiBp=iBp_Zm1Q;_O +RNH3Ds0CF_0R +4;N#HR$VM_#Hl_8(R"4ddc(c4d4 +";N3HRs_0DFosHMCNlRv"1_Qqvt;q" +RNH3lV#_FVslR#0"_1vqtvQq"Rd;H +NR#3VlF_0#"0R1qv_vqQtR;U" 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@@ -3327,9 +3330,9 @@ Qhj=_(4. 4SQ=a)1_Y7p_4Hr9s; R:fjjNRlOqERhR7.blsHR#bF_ OD\p3Bij_jj__u1BYh_j.__rNdjS9 mF=b#D_O B\3pji_juj__h1YBr_.jS9 -QBj=pji_j7j_jQ -S4p=Bij_jj4_7_ -H;sjRf:ljRNROEq.h7RHbslFRb#D_O q\3jv_7q__djd_N +QBj=pji_j7j_r +j9S=Q4B_pij_jj7r_H4 +9;sjRf:ljRNROEq.h7RHbslFRb#D_O q\3jv_7q__djd_N =Smb_F#O\D 3_qj7_vqdQ Sjt=Aq_Bij_djQ_haHQ S47=z1j_jj;_O @@ -3343,41 +3346,41 @@ QA4=tiqB_jjd_aQh_ H;sjRf:ljRNROEQRheblsHR_1vqtvQqr_HjS9 mv=1_QqvtHq_r j9S=Qj1qv_vqQtr;j9 -fsRjR:jlENOR7qh.sRbHtlR_g4. -=Smhj_.gQ -Sjp=Bij_jj _u -4SQ=BBYp7 _vjqr9s; -R:fjjNRlOQERhbeRsRHlh4_.d -_HShm=_d.4_SH -Qhj=_d.4;R -sfjj:ROlNEhRQesRbHhlR_c.4_SH -m_=h._4cHQ -Sj_=h.;4c -fsRjR:jlENOReQhRHbsl_Rh._46Hm -S=.h_4H6_ +fsRjR:jlENOReQhRHbslpRBiz_ma)_u j_6_SH +mp=Biz_ma)_u j_6_SH +QBj=pmi_zua_)6 _js; +R:fjjNRlOqERhR7.blsHR4t_.Sg +m_=h. +jgS=QjB_pij_jjuS +QB4=Y Bp_q7vr;j9 +fsRjR:jlENOReQhRHbsl_Rh._4dHm +S=.h_4Hd_ jSQ=.h_4 -6;sjRf:ljRNROEQRheblsHRHq_r9.6 -=Smqr_H. -69S=Qjqr_O.;69 -fsRjR:jlENOReQhRHbsl_RqHnr.9m -S=Hq_r9.n -jSQ=Oq_r9.n;R -sfjj:ROlNEhRQesRbHqlR_.Hr(S9 -m_=qH(r.9Q -Sj_=qO(r.9s; +d;sjRf:ljRNROEQRheblsHR.h_4Hc_ +=Smh4_.c +_HS=Qjh4_.cs; +R:fjjNRlOQERhbeRsRHlh4_.6 +_HShm=_6.4_SH +Qhj=_6.4;R +sfjj:ROlNEhRQesRbHqlR_.Hr6S9 +m_=qH6r.9Q +Sj_=qO6r.9s; R:fjjNRlOQERhbeRsRHlqr_H. -U9Sqm=_.HrUS9 -Qqj=_.OrU -9;sjRf:ljRNROEQRheblsHRHq_r9.g +n9Sqm=_.HrnS9 +Qqj=_.Orn +9;sjRf:ljRNROEQRheblsHRHq_r9.( =Smqr_H. -g9S=Qjqr_O.;g9 -fsRjR:jlENOReQhRHbsl_RqHjrd9m -S=Hq_r9dj -jSQ=Oq_r9dj;R -sfjj:ROlNEhRQesRbHBlRpmi_zua_)6 _j -_HSBm=pmi_zua_)6 _j -_HS=QjB_pim_zau_) 6 -j;sjRf:ljRNROEq.h7RHbsl RMX1u_u qB__7jjm +(9S=Qjqr_O.;(9 +fsRjR:jlENOReQhRHbsl_RqHUr.9m +S=Hq_r9.U +jSQ=Oq_r9.U;R +sfjj:ROlNEhRQesRbHqlR_.HrgS9 +m_=qHgr.9Q +Sj_=qOgr.9s; +R:fjjNRlOQERhbeRsRHlqr_Hd +j9Sqm=_dHrjS9 +Qqj=_dOrj +9;sjRf:ljRNROEq.h7RHbsl RMX1u_u qB__7jjm S=6h_c _jS=Qj)_1aOQ S4 =MX1u_u qB_HO_;R @@ -3568,11 +3571,11 @@ fsRjR:jlENOR.m)RHbslvRqQ_tqA_z1 Ahqp7 _v]q_Q_t]j M4S=Q4qtvQqz_A1h_ q Ap_q7v_t]Q]3_jk;Mj fsRjR:jlENOReQhRHbsltRA_jjj_sj3 =SmAjt_jjj_3dkM -jSQ=#bF_ OD\M3kUo_L_jjd;R +jSQ=#bF_ OD\M3kgo_L_jjd;R sfjj:ROlNEhRq7b.RsRHlAjt_jjj_3Sl mt=A_jjj_kj3MS4 QAj=td_jj -_OS=Q4b_F#O\D 3UkM__Loj;dj +_OS=Q4b_F#O\D 3gkM__Loj;dj fsRjR:jlENOR7qh.sRbHAlRtj_jj3_jMm S=_Atj_jjjM3kjQ Sjt=A_jjj_SO @@ -3617,8 +3620,8 @@ fsRjR:jlENOR7qh.sRbH7lR1j_jjv_7q _4Shm=__cgjQ Sj_=hd _HS=Q4)_1aOs; -R:fjjNRlOqERhR7.blsHR#bF_ OD\M3kUo_L_jjd -=Smb_F#O\D 3UkM__Loj_djjQ +R:fjjNRlOqERhR7.blsHR#bF_ OD\M3kgo_L_jjd +=Smb_F#O\D 3gkM__Loj_djjQ Sjt=A_jjd_HO_ 4SQ=#bF_ OD\M3kno_L_jjd_ H;sjRf:ljRNROEQRheblsHRckM_#k8_jjj_SH diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index 7989e8f..32ef490 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -1,18 +1,18 @@ #Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014 -#install: C:\ispLever\synpbase +#install: E:\ispLEVER_Classic2_0\synpbase #OS: Windows 7 6.2 #Hostname: DEEPTHOUGHT #Implementation: logic $ Start of Compile -#Wed Jan 27 21:56:43 2016 +#Wed Aug 17 17:45:41 2016 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 @N|Running in 64-bit mode Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, or distribution of this software is strictly prohibited. -@N: CD720 :"C:\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns +@N: CD720 :"E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030. File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling VHDL syntax check successful! @@ -22,18 +22,16 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - @N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000 @W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register DS_030_D0_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register AMIGA_BUS_ENABLE_INT_4 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D4_2 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D3_2 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D2_2 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register DS_030_D0_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register AMIGA_BUS_ENABLE_INT_5 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2 -@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... -@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... -@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ... -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":151:2:151:3|Pruning register CLK_030_D0_2 +@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:61:130:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... +@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:55:129:64|Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... +@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:38:127:40|Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ... +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ... +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -44,14 +42,14 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register cpu_est @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused @END At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Jan 27 21:56:44 2016 +# Wed Aug 17 17:45:41 2016 ###########################################################] Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 @@ -61,7 +59,7 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Jan 27 21:56:45 2016 +# Wed Aug 17 17:45:43 2016 ###########################################################] Map & Optimize Report @@ -70,7 +68,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2014.03LC @N: MF248 |Running in 64-bit mode. -@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0] +@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0] Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral)) original code -> new code 000 -> 00000000 @@ -81,7 +79,6 @@ original code -> new code 101 -> 00100001 110 -> 01000001 111 -> 10000001 -@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Removing instance CLK_000_P_SYNC[10], because it is equivalent to instance CLK_000_PE --------------------------------------- Resource Usage Report @@ -104,6 +101,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Jan 27 21:56:45 2016 +# Wed Aug 17 17:45:43 2016 ###########################################################] diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs index d3521d9..08f3a2c 100644 Binary files a/Logic/BUS68030.srs and b/Logic/BUS68030.srs differ diff --git a/Logic/Programming.xcf b/Logic/Programming.xcf index a4e741a..89bbd7c 100644 --- a/Logic/Programming.xcf +++ b/Logic/Programming.xcf @@ -18,8 +18,8 @@ 1 0 - C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk-50.jed - 01/27/16 21:56:53 + C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed + 08/17/16 17:45:51 0x2728 Erase,Program,Verify