diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index 9d5d2ee..af49e13 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -409,8 +409,13 @@ begin --A0_DMA <= '0'; --A1 is set by the amiga side --here we determine the upper or lower half of the databus - AMIGA_BUS_ENABLE_DMA_HIGH <= A(1); - AMIGA_BUS_ENABLE_DMA_LOW <= not A(1); + if(AHIGH=x"00" and A_DECODE(23 downto 19) = "11101") then --evil hack: E8-EF is assumed to be only 16 bit wide! + AMIGA_BUS_ENABLE_DMA_HIGH <= '0'; + AMIGA_BUS_ENABLE_DMA_LOW <= '1'; + else + AMIGA_BUS_ENABLE_DMA_HIGH <= A(1); + AMIGA_BUS_ENABLE_DMA_LOW <= not A(1); + end if; else RW_000_DMA <= '1'; diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index eda62da..ac165b5 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -433654,3 +433654,186 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 12/30/17 00:43:20 ########### + +########## Tcl recorder starts at 01/11/18 20:16:09 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/11/18 20:16:09 ########### + + +########## Tcl recorder starts at 01/11/18 20:16:10 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 01/11/18 20:16:10 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index 0e86964..94c7f16 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,94 +1,94 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Sat Dec 30 00:43:37 2017 +#$ DATE Thu Jan 11 20:16:29 2018 #$ MODULE 68030_tk -#$ PINS 75 AHIGH_27_ AHIGH_26_ SIZE_1_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ \ -# A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ \ -# IPL_030_2_ A_DECODE_16_ A_DECODE_15_ IPL_2_ A_DECODE_14_ A_DECODE_13_ FC_1_ \ -# A_DECODE_12_ AS_030 A_DECODE_11_ AS_000 A_DECODE_10_ RW_000 A_DECODE_9_ DS_030 \ -# A_DECODE_8_ UDS_000 A_DECODE_7_ LDS_000 A_DECODE_6_ nEXP_SPACE A_DECODE_5_ BERR \ -# A_DECODE_4_ BG_030 A_DECODE_3_ BG_000 A_DECODE_2_ BGACK_030 A_0_ BGACK_000 IPL_030_1_ \ -# CLK_030 IPL_030_0_ CLK_000 IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ FPU_CS \ -# FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR \ -# AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ \ -# AHIGH_28_ -#$ NODES 508 N_23_0 UDS_000_c N_19_i N_22_0 LDS_000_c N_18_i N_21_0 size_c_0__n \ -# ipl_c_i_2__n N_43_0 size_c_1__n ipl_c_i_1__n inst_BGACK_030_INTreg N_42_0 vcc_n_n \ -# ahigh_c_24__n ipl_c_i_0__n un5_e N_41_0 gnd_n_n ahigh_c_25__n DTACK_c_i \ -# un1_amiga_bus_enable_low N_45_0 un3_as_030 ahigh_c_26__n VPA_c_i un1_UDS_000_INT \ -# N_44_0 un1_LDS_000_INT ahigh_c_27__n N_13_i un1_DS_000_ENABLE_0_sqmuxa N_27_0 \ -# un10_ciin ahigh_c_28__n LDS_000_INT_i un21_fpu_cs un1_LDS_000_INT_0 un21_berr \ -# ahigh_c_29__n UDS_000_INT_i un2_ds_030 un1_UDS_000_INT_0 cpu_est_0_ ahigh_c_30__n \ -# N_96_0_1 cpu_est_1_ N_96_0_2 cpu_est_2_ ahigh_c_31__n N_282_0_1 cpu_est_3_ N_282_0_2 \ -# inst_AMIGA_BUS_ENABLE_DMA_HIGH N_282_0_3 inst_AMIGA_BUS_ENABLE_DMA_LOW N_282_0_4 \ -# inst_AS_030_D0 pos_clk_un10_sm_amiga_i_1_n inst_AS_030_D1 un10_ciin_1 \ -# inst_AS_030_000_SYNC un10_ciin_2 inst_AS_000_DMA un10_ciin_3 inst_DS_000_DMA \ -# un10_ciin_4 inst_VMA_INTreg un10_ciin_5 inst_VPA_D un10_ciin_6 CLK_000_D_3_ \ -# un10_ciin_7 inst_DTACK_D0 un10_ciin_8 inst_AMIGA_DS un10_ciin_9 CLK_000_D_1_ \ -# un10_ciin_10 CLK_000_D_0_ un10_ciin_11 inst_CLK_OUT_PRE_50 N_201_1 \ -# inst_CLK_OUT_PRE_D N_201_2 IPL_D0_0_ N_131_i_1 IPL_D0_1_ N_134_0_1 IPL_D0_2_ \ -# N_113_i_1 CLK_000_D_2_ N_113_i_2 CLK_000_D_4_ N_144_1 pos_clk_ipl_n N_144_2 \ -# SIZE_DMA_0_ N_143_1 SIZE_DMA_1_ N_143_2 inst_A0_DMA N_163_1 inst_RW_000_DMA N_163_2 \ -# inst_UDS_000_INT N_163_3 inst_DS_000_ENABLE un21_fpu_cs_1 inst_LDS_000_INT \ -# a_decode_c_16__n un21_berr_1_0 inst_BGACK_030_INT_D pos_clk_cycle_dma_5_1_1__n \ -# SM_AMIGA_6_ a_decode_c_17__n N_199_1 inst_RW_000_INT AS_000_DMA_1_sqmuxa_1 \ -# SM_AMIGA_4_ a_decode_c_18__n N_140_1 SM_AMIGA_1_ N_66_i_1 SM_AMIGA_0_ \ -# a_decode_c_19__n N_66_i_2 CYCLE_DMA_0_ N_205_i_1 CYCLE_DMA_1_ a_decode_c_20__n \ -# N_205_i_2 inst_DSACK1_INT N_180_1 inst_AS_000_INT a_decode_c_21__n N_180_2 \ -# pos_clk_un9_clk_000_pe_n N_59_i_1 SM_AMIGA_5_ a_decode_c_22__n N_127_i_1 \ -# SM_AMIGA_3_ N_123_i_1 SM_AMIGA_2_ a_decode_c_23__n N_121_i_1 N_119_i_1 N_6 a_c_0__n \ -# N_117_i_1 N_115_i_1 a_c_1__n N_111_i_1 N_165_1 N_13 nEXP_SPACE_c N_162_1 N_148_1 N_18 \ -# BERR_c pos_clk_ipl_1_n N_19 ds_000_dma_0_un3_n N_20 BG_030_c ds_000_dma_0_un1_n \ -# ds_000_dma_0_un0_n BG_000DFFreg as_000_dma_0_un3_n as_000_dma_0_un1_n \ -# as_000_dma_0_un0_n BGACK_000_c uds_000_int_0_un3_n uds_000_int_0_un1_n \ -# uds_000_int_0_un0_n bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n CLK_OSZI_c \ -# lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n CLK_OUT_INTreg \ -# as_030_d1_0_un3_n as_030_d1_0_un1_n as_030_d1_0_un0_n FPU_SENSE_c \ -# rw_000_int_0_un3_n rw_000_int_0_un1_n IPL_030DFF_0_reg rw_000_int_0_un0_n \ -# as_030_000_sync_0_un3_n IPL_030DFF_1_reg as_030_000_sync_0_un1_n SM_AMIGA_i_7_ \ -# as_030_000_sync_0_un0_n IPL_030DFF_2_reg bgack_030_int_0_un3_n \ -# bgack_030_int_0_un1_n cpu_est_2_1__n ipl_c_0__n bgack_030_int_0_un0_n \ -# cpu_est_2_2__n cpu_est_0_1__un3_n cpu_est_2_3__n ipl_c_1__n cpu_est_0_1__un1_n \ -# G_105 cpu_est_0_1__un0_n G_106 ipl_c_2__n cpu_est_0_2__un3_n G_107 \ -# cpu_est_0_2__un1_n N_60 cpu_est_0_2__un0_n N_63 DTACK_c cpu_est_0_3__un3_n N_126 \ -# cpu_est_0_3__un1_n N_150 cpu_est_0_3__un0_n N_151 ipl_030_0_0__un3_n N_219 VPA_c \ -# ipl_030_0_0__un1_n N_175 ipl_030_0_0__un0_n ipl_030_0_1__un3_n N_59 RST_c \ -# ipl_030_0_1__un1_n N_68 ipl_030_0_1__un0_n N_72 ipl_030_0_2__un3_n N_80 \ -# ipl_030_0_2__un1_n N_93 RW_c ipl_030_0_2__un0_n N_98 ds_000_enable_0_un3_n N_107 \ -# fc_c_0__n ds_000_enable_0_un1_n N_128 ds_000_enable_0_un0_n N_131 fc_c_1__n \ -# vma_int_0_un3_n N_134 vma_int_0_un1_n N_135 vma_int_0_un0_n N_141 \ -# AMIGA_BUS_DATA_DIR_c a_decode_15__n N_142 N_143 a_decode_14__n N_144 N_145 \ -# a_decode_13__n N_146 N_205_i N_147 N_140_i a_decode_12__n N_148 AMIGA_DS_i N_149 \ -# a_decode_11__n N_154 N_199_i N_155 N_198_i a_decode_10__n N_162 N_180_i N_165 N_262_i \ -# a_decode_9__n N_259 AMIGA_BUS_DATA_DIR_c_0 N_260 pos_clk_un2_i_n a_decode_8__n N_181 \ -# N_3_i N_182 N_32_0 a_decode_7__n N_183 N_4_i N_184 N_31_0 a_decode_6__n N_185 N_220_i \ -# N_186 BG_030_c_i a_decode_5__n N_266 pos_clk_un9_bg_030_0_n N_267 N_17_i \ -# a_decode_4__n N_268 N_24_0 N_190 N_16_i a_decode_3__n N_191 N_25_0 N_201 N_15_i \ -# a_decode_2__n N_202 N_26_0 N_203 N_12_i N_208 N_28_0 N_163 N_11_i N_282 N_29_0 \ -# un21_berr_1 N_5_i N_132 N_30_0 N_96 a_c_i_0__n N_129 size_c_i_1__n \ -# un1_SM_AMIGA_0_sqmuxa_1 pos_clk_un10_sm_amiga_i_n N_169 un1_dsack1_i N_170 N_69_i \ -# N_167 N_163_i N_168 N_244_0 pos_clk_rw_000_int_5_n N_164_i pos_clk_un6_bgack_000_n \ -# N_165_i N_274 un11_amiga_bus_enable_high_i N_164 un10_ciin_i N_244 N_60_0 N_5 N_274_i \ -# N_11 pos_clk_un6_bgack_000_0_n N_12 RW_c_i N_15 pos_clk_rw_000_int_5_0_n N_16 N_168_i \ -# N_17 N_167_i pos_clk_un9_bg_030_n G_91 N_170_i N_3 N_169_i N_205 AS_000_DMA_1_sqmuxa \ -# N_38_0 N_4 un1_SM_AMIGA_0_sqmuxa_1_0 N_199 N_282_0 pos_clk_un2_n clk_000_d_i_3__n \ -# N_140 N_96_0 N_262 N_129_i N_198 N_268_i N_180 N_246_i un1_amiga_bus_enable_low_i \ -# N_132_0 un21_fpu_cs_i AS_000_i N_142_i BGACK_030_INT_i N_141_i nEXP_SPACE_i N_135_0 \ -# cycle_dma_i_0__n N_134_0 RW_000_i N_131_i CLK_EXP_i LDS_000_c_i cycle_dma_i_1__n \ -# UDS_000_c_i DS_000_DMA_i N_128_i AS_000_DMA_i N_107_i a_i_1__n N_203_i \ -# AMIGA_BUS_ENABLE_DMA_LOW_i un1_DS_000_ENABLE_0_sqmuxa_0 a_decode_i_19__n N_201_i \ -# a_decode_i_18__n N_202_i a_decode_i_16__n VMA_INT_i AMIGA_BUS_ENABLE_DMA_HIGH_i \ -# N_98_i sm_amiga_i_0__n N_93_i sm_amiga_i_5__n N_82_i sm_amiga_i_6__n N_80_i \ -# sm_amiga_i_i_7__n N_72_i AS_030_i N_68_i AS_000_INT_i N_59_i DSACK1_INT_i N_190_i \ -# sm_amiga_i_1__n N_191_i FPU_SENSE_i AS_030_D1_i N_267_i cpu_est_i_0__n \ -# cpu_est_i_3__n N_266_i VPA_D_i sm_amiga_i_3__n N_186_i sm_amiga_i_4__n \ -# cpu_est_i_1__n N_185_i clk_000_d_i_0__n clk_000_d_i_1__n N_183_i AS_030_D0_i N_184_i \ -# cpu_est_i_2__n DTACK_D0_i N_182_i sm_amiga_i_2__n AS_030_000_SYNC_i N_181_i \ -# ahigh_i_30__n ahigh_i_31__n N_260_i ahigh_i_28__n pos_clk_size_dma_6_0_1__n \ -# ahigh_i_29__n N_259_i ahigh_i_26__n pos_clk_size_dma_6_0_0__n ahigh_i_27__n N_63_0 \ -# ahigh_i_24__n N_155_i ahigh_i_25__n N_162_i N_187_i un5_e_0 N_188_i N_154_i N_189_i \ -# cpu_est_2_0_3__n N_149_i N_208_i cpu_est_2_0_2__n N_147_i un2_ds_030_i N_148_i \ -# N_219_i cpu_est_2_0_1__n N_175_i N_146_i un3_as_030_i N_36_0 AS_030_c N_145_i N_35_0 \ -# AS_000_c N_143_i N_144_i RW_000_c pos_clk_un9_clk_000_pe_0_n N_20_i +#$ PINS 75 SIZE_1_ SIZE_0_ AHIGH_30_ AHIGH_31_ AHIGH_29_ AHIGH_28_ A_DECODE_23_ \ +# AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ IPL_030_2_ A_DECODE_22_ A_DECODE_21_ IPL_2_ \ +# A_DECODE_20_ A_DECODE_19_ FC_1_ A_DECODE_18_ AS_030 A_DECODE_17_ AS_000 A_DECODE_16_ \ +# RW_000 A_DECODE_15_ DS_030 A_DECODE_14_ UDS_000 A_DECODE_13_ LDS_000 A_DECODE_12_ \ +# nEXP_SPACE A_DECODE_11_ BERR A_DECODE_10_ BG_030 A_DECODE_9_ BG_000 A_DECODE_8_ \ +# BGACK_030 A_DECODE_7_ BGACK_000 A_DECODE_6_ CLK_030 A_DECODE_5_ CLK_000 A_DECODE_4_ \ +# CLK_OSZI A_DECODE_3_ CLK_DIV_OUT A_DECODE_2_ CLK_EXP A_0_ FPU_CS IPL_030_1_ FPU_SENSE \ +# IPL_030_0_ DSACK1 IPL_1_ DTACK IPL_0_ AVEC FC_0_ E A_1_ VPA VMA RST RESET RW \ +# AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH \ +# CIIN +#$ NODES 514 N_157_i UDS_000_c cpu_est_2_0_3__n N_156_i LDS_000_c N_229_i \ +# cpu_est_2_0_2__n size_c_0__n N_126_i N_150_i size_c_1__n pos_clk_un9_clk_000_pe_0_n \ +# inst_BGACK_030_INTreg N_20_i vcc_n_n ahigh_c_24__n N_23_0 un5_e N_19_i gnd_n_n \ +# ahigh_c_25__n N_22_0 un1_amiga_bus_enable_low N_18_i un3_as_030 ahigh_c_26__n N_21_0 \ +# un1_UDS_000_INT ipl_c_i_2__n un1_LDS_000_INT ahigh_c_27__n N_43_0 \ +# un1_DS_000_ENABLE_0_sqmuxa ipl_c_i_1__n un21_fpu_cs ahigh_c_28__n N_42_0 un21_berr \ +# ipl_c_i_0__n un8_ciin ahigh_c_29__n N_41_0 un2_ds_030 N_13_i cpu_est_0_ ahigh_c_30__n \ +# N_27_0 cpu_est_1_ LDS_000_INT_i cpu_est_2_ ahigh_c_31__n un1_LDS_000_INT_0 \ +# cpu_est_3_ UDS_000_INT_i inst_AMIGA_BUS_ENABLE_DMA_HIGH un1_UDS_000_INT_0 \ +# inst_AMIGA_BUS_ENABLE_DMA_LOW N_104_0_1 inst_AS_030_D0 N_104_0_2 inst_AS_030_D1 \ +# N_100_0_1 inst_AS_030_000_SYNC N_100_0_2 inst_AS_000_DMA N_113_i_1 inst_DS_000_DMA \ +# N_113_i_2 inst_VMA_INTreg N_107_0_1 inst_VPA_D N_99_i_1 CLK_000_D_3_ \ +# pos_clk_un10_sm_amiga_i_1_n inst_DTACK_D0 N_202_1 inst_AMIGA_DS N_202_2 \ +# CLK_000_D_1_ N_228_1 CLK_000_D_0_ N_228_2 inst_CLK_OUT_PRE_50 N_228_3 \ +# inst_CLK_OUT_PRE_D N_228_4 IPL_D0_0_ N_228_5 IPL_D0_1_ N_150_1 IPL_D0_2_ N_150_2 \ +# CLK_000_D_2_ N_126_1 CLK_000_D_4_ N_126_2 pos_clk_ipl_n un8_ciin_1 SIZE_DMA_0_ \ +# un8_ciin_2 SIZE_DMA_1_ N_201_1_1 inst_A0_DMA N_201_1_2 inst_RW_000_DMA N_201_1_3 \ +# inst_UDS_000_INT N_201_1_4 inst_DS_000_ENABLE N_201_1_5 inst_LDS_000_INT \ +# a_decode_c_16__n N_201_1_6 inst_BGACK_030_INT_D N_201_1_7 SM_AMIGA_6_ \ +# a_decode_c_17__n N_201_1_8 inst_RW_000_INT N_201_1_0 SM_AMIGA_4_ a_decode_c_18__n \ +# N_201_2 SM_AMIGA_1_ pos_clk_cycle_dma_5_1_1__n SM_AMIGA_0_ a_decode_c_19__n N_176_1 \ +# CYCLE_DMA_0_ AS_000_DMA_1_sqmuxa_1 CYCLE_DMA_1_ a_decode_c_20__n N_198_1 \ +# inst_DSACK1_INT N_72_i_1 inst_AS_000_INT a_decode_c_21__n N_72_i_2 \ +# pos_clk_un9_clk_000_pe_n N_206_i_1 SM_AMIGA_5_ a_decode_c_22__n N_206_i_2 \ +# SM_AMIGA_3_ N_186_1 SM_AMIGA_2_ a_decode_c_23__n N_186_2 N_74_i_1 N_6 a_c_0__n \ +# N_121_i_1 N_117_i_1 a_c_1__n N_115_i_1 N_127_i_1 N_13 nEXP_SPACE_c N_123_i_1 N_119_i_1 \ +# N_18 BERR_c N_111_i_1 N_19 un21_berr_1 N_20 BG_030_c un21_fpu_cs_1 N_172_1 BG_000DFFreg \ +# N_161_1 N_153_1 pos_clk_ipl_1_n BGACK_000_c ds_000_dma_0_un3_n ds_000_dma_0_un1_n \ +# ds_000_dma_0_un0_n as_000_dma_0_un3_n as_000_dma_0_un1_n as_000_dma_0_un0_n \ +# CLK_OSZI_c uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n \ +# CLK_OUT_INTreg bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n FPU_SENSE_c \ +# lds_000_int_0_un3_n lds_000_int_0_un1_n IPL_030DFF_0_reg lds_000_int_0_un0_n \ +# rw_000_int_0_un3_n IPL_030DFF_1_reg rw_000_int_0_un1_n rw_000_int_0_un0_n \ +# SM_AMIGA_i_7_ IPL_030DFF_2_reg bgack_030_int_0_un3_n bgack_030_int_0_un1_n \ +# ipl_c_0__n bgack_030_int_0_un0_n cpu_est_2_2__n as_030_000_sync_0_un3_n \ +# cpu_est_2_3__n ipl_c_1__n as_030_000_sync_0_un1_n G_105 as_030_000_sync_0_un0_n \ +# G_106 ipl_c_2__n cpu_est_0_1__un3_n G_107 cpu_est_0_1__un1_n cpu_est_0_1__un0_n \ +# N_205 DTACK_c cpu_est_0_2__un3_n N_74 cpu_est_0_2__un1_n N_78 cpu_est_0_2__un0_n N_79 \ +# cpu_est_0_3__un3_n N_80 VPA_c cpu_est_0_3__un1_n N_83 cpu_est_0_3__un0_n N_84 \ +# ipl_030_0_0__un3_n N_89 RST_c ipl_030_0_0__un1_n N_95 ipl_030_0_0__un0_n N_96 \ +# ipl_030_0_1__un3_n N_97 ipl_030_0_1__un1_n N_105 RW_c ipl_030_0_1__un0_n N_126 \ +# ipl_030_0_2__un3_n N_150 fc_c_0__n ipl_030_0_2__un1_n N_153 ipl_030_0_2__un0_n N_156 \ +# fc_c_1__n ds_000_enable_0_un3_n N_157 ds_000_enable_0_un1_n N_158 \ +# ds_000_enable_0_un0_n N_159 AMIGA_BUS_DATA_DIR_c vma_int_0_un3_n N_160 \ +# vma_int_0_un1_n N_161 vma_int_0_un0_n N_172 as_030_d1_0_un3_n N_177 \ +# as_030_d1_0_un1_n N_178 N_181_i as_030_d1_0_un0_n N_179 N_37_0 a_decode_15__n N_180 \ +# N_182 N_176_i a_decode_14__n N_183 N_175_i N_184 N_72_i a_decode_13__n N_212 N_198_i \ +# N_213 AMIGA_DS_i a_decode_12__n N_214 N_186_i N_190 N_185_i a_decode_11__n N_191 \ +# AMIGA_BUS_DATA_DIR_c_0 N_194 pos_clk_un2_i_n a_decode_10__n N_195 N_3_i N_196 N_32_0 \ +# a_decode_9__n N_197 N_4_i N_202 N_31_0 a_decode_8__n N_220 N_39_1_i N_224 N_34_0 \ +# a_decode_7__n N_225 BG_030_c_i N_228 pos_clk_un9_bg_030_0_n a_decode_6__n N_229 \ +# N_17_i N_201_1 N_24_0 a_decode_5__n N_104 N_16_i N_100 N_25_0 a_decode_4__n N_171 N_15_i \ +# N_204 N_26_0 a_decode_3__n N_164 N_12_i N_162 N_28_0 a_decode_2__n N_163 N_5_i \ +# cpu_est_2_1__n N_30_0 N_152 a_c_i_0__n N_11 size_c_i_1__n N_201 \ +# pos_clk_un10_sm_amiga_i_n N_193 N_231_i N_192 pos_clk_un6_bgack_000_0_n N_107 N_40_0 \ +# N_99 un1_SM_AMIGA_0_sqmuxa_1_0 N_219 RW_c_i N_81 pos_clk_rw_000_int_5_0_n \ +# pos_clk_rw_000_int_5_n N_201_i un1_SM_AMIGA_0_sqmuxa_1 N_81_i \ +# pos_clk_un6_bgack_000_n N_219_i N_231 N_202_i N_5 N_191_i N_12 N_98_i N_15 N_99_i N_16 \ +# N_107_0 N_17 N_192_i pos_clk_un9_bg_030_n N_193_i N_3 N_72 N_11_i AS_000_DMA_1_sqmuxa \ +# N_29_0 N_4 VPA_c_i G_91 N_44_0 N_176 DTACK_c_i pos_clk_un2_n N_45_0 N_175 N_152_i N_185 \ +# N_153_i N_198 cpu_est_2_0_1__n N_186 N_163_i N_181 N_162_i un1_amiga_bus_enable_low_i \ +# un21_fpu_cs_i N_203_i AS_000_i un1_dsack1_i BGACK_030_INT_i N_164_i nEXP_SPACE_i \ +# N_228_i RW_000_i N_204_0 cycle_dma_i_0__n N_171_i CLK_EXP_i N_172_i cycle_dma_i_1__n \ +# un11_amiga_bus_enable_high_i DS_000_DMA_i N_85_0 AS_000_DMA_i clk_000_d_i_3__n \ +# ahigh_i_25__n N_100_0 ahigh_i_24__n AS_030_D1_i ahigh_i_27__n N_104_0 ahigh_i_26__n \ +# N_105_0 ahigh_i_29__n N_97_i ahigh_i_28__n LDS_000_c_i ahigh_i_31__n UDS_000_c_i \ +# ahigh_i_30__n N_96_i sm_amiga_i_2__n N_95_i sm_amiga_i_1__n N_220_i DTACK_D0_i \ +# un1_DS_000_ENABLE_0_sqmuxa_0 sm_amiga_i_i_7__n VMA_INT_i sm_amiga_i_3__n N_89_i \ +# a_decode_i_20__n N_84_i AMIGA_BUS_ENABLE_DMA_LOW_i N_83_i cpu_est_i_0__n N_82_i \ +# AS_030_i N_80_i AMIGA_BUS_ENABLE_DMA_HIGH_i N_79_i sm_amiga_i_6__n N_78_0 \ +# AS_030_D0_i N_74_i cpu_est_i_3__n N_197_i VPA_D_i sm_amiga_i_5__n N_195_i \ +# sm_amiga_i_4__n N_196_i cpu_est_i_1__n clk_000_d_i_0__n N_194_i clk_000_d_i_1__n \ +# cpu_est_i_2__n N_190_i DSACK1_INT_i AS_000_INT_i N_214_i a_decode_i_16__n \ +# a_decode_i_19__n N_184_i a_decode_i_18__n pos_clk_size_dma_6_0_1__n FPU_SENSE_i \ +# N_183_i AS_030_000_SYNC_i pos_clk_size_dma_6_0_0__n sm_amiga_i_0__n N_182_i N_187_i \ +# N_38_0 N_188_i N_179_i N_189_i N_180_i N_177_i N_178_i un2_ds_030_i N_225_i un8_ciin_i \ +# N_224_i N_205_0 un3_as_030_i N_160_i AS_030_c N_161_i un5_e_0 AS_000_c N_159_i RW_000_c \ +# N_158_i .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF DTACK.BLIF VPA.BLIF \ @@ -101,238 +101,249 @@ A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF A_1_.BLIF \ SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF \ LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF \ AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF \ -A_0_.BLIF N_23_0.BLIF UDS_000_c.BLIF N_19_i.BLIF N_22_0.BLIF LDS_000_c.BLIF \ -N_18_i.BLIF N_21_0.BLIF size_c_0__n.BLIF ipl_c_i_2__n.BLIF N_43_0.BLIF \ -size_c_1__n.BLIF ipl_c_i_1__n.BLIF inst_BGACK_030_INTreg.BLIF N_42_0.BLIF \ -vcc_n_n.BLIF ahigh_c_24__n.BLIF ipl_c_i_0__n.BLIF un5_e.BLIF N_41_0.BLIF \ -gnd_n_n.BLIF ahigh_c_25__n.BLIF DTACK_c_i.BLIF un1_amiga_bus_enable_low.BLIF \ -N_45_0.BLIF un3_as_030.BLIF ahigh_c_26__n.BLIF VPA_c_i.BLIF \ -un1_UDS_000_INT.BLIF N_44_0.BLIF un1_LDS_000_INT.BLIF ahigh_c_27__n.BLIF \ -N_13_i.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF N_27_0.BLIF un10_ciin.BLIF \ -ahigh_c_28__n.BLIF LDS_000_INT_i.BLIF un21_fpu_cs.BLIF un1_LDS_000_INT_0.BLIF \ -un21_berr.BLIF ahigh_c_29__n.BLIF UDS_000_INT_i.BLIF un2_ds_030.BLIF \ -un1_UDS_000_INT_0.BLIF cpu_est_0_.BLIF ahigh_c_30__n.BLIF N_96_0_1.BLIF \ -cpu_est_1_.BLIF N_96_0_2.BLIF cpu_est_2_.BLIF ahigh_c_31__n.BLIF \ -N_282_0_1.BLIF cpu_est_3_.BLIF N_282_0_2.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_282_0_3.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_282_0_4.BLIF inst_AS_030_D0.BLIF \ -pos_clk_un10_sm_amiga_i_1_n.BLIF inst_AS_030_D1.BLIF un10_ciin_1.BLIF \ -inst_AS_030_000_SYNC.BLIF un10_ciin_2.BLIF inst_AS_000_DMA.BLIF \ -un10_ciin_3.BLIF inst_DS_000_DMA.BLIF un10_ciin_4.BLIF inst_VMA_INTreg.BLIF \ -un10_ciin_5.BLIF inst_VPA_D.BLIF un10_ciin_6.BLIF CLK_000_D_3_.BLIF \ -un10_ciin_7.BLIF inst_DTACK_D0.BLIF un10_ciin_8.BLIF inst_AMIGA_DS.BLIF \ -un10_ciin_9.BLIF CLK_000_D_1_.BLIF un10_ciin_10.BLIF CLK_000_D_0_.BLIF \ -un10_ciin_11.BLIF inst_CLK_OUT_PRE_50.BLIF N_201_1.BLIF \ -inst_CLK_OUT_PRE_D.BLIF N_201_2.BLIF IPL_D0_0_.BLIF N_131_i_1.BLIF \ -IPL_D0_1_.BLIF N_134_0_1.BLIF IPL_D0_2_.BLIF N_113_i_1.BLIF CLK_000_D_2_.BLIF \ -N_113_i_2.BLIF CLK_000_D_4_.BLIF N_144_1.BLIF pos_clk_ipl_n.BLIF N_144_2.BLIF \ -SIZE_DMA_0_.BLIF N_143_1.BLIF SIZE_DMA_1_.BLIF N_143_2.BLIF inst_A0_DMA.BLIF \ -N_163_1.BLIF inst_RW_000_DMA.BLIF N_163_2.BLIF inst_UDS_000_INT.BLIF \ -N_163_3.BLIF inst_DS_000_ENABLE.BLIF un21_fpu_cs_1.BLIF inst_LDS_000_INT.BLIF \ -a_decode_c_16__n.BLIF un21_berr_1_0.BLIF inst_BGACK_030_INT_D.BLIF \ -pos_clk_cycle_dma_5_1_1__n.BLIF SM_AMIGA_6_.BLIF a_decode_c_17__n.BLIF \ -N_199_1.BLIF inst_RW_000_INT.BLIF AS_000_DMA_1_sqmuxa_1.BLIF SM_AMIGA_4_.BLIF \ -a_decode_c_18__n.BLIF N_140_1.BLIF SM_AMIGA_1_.BLIF N_66_i_1.BLIF \ -SM_AMIGA_0_.BLIF a_decode_c_19__n.BLIF N_66_i_2.BLIF CYCLE_DMA_0_.BLIF \ -N_205_i_1.BLIF CYCLE_DMA_1_.BLIF a_decode_c_20__n.BLIF N_205_i_2.BLIF \ -inst_DSACK1_INT.BLIF N_180_1.BLIF inst_AS_000_INT.BLIF a_decode_c_21__n.BLIF \ -N_180_2.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_59_i_1.BLIF SM_AMIGA_5_.BLIF \ -a_decode_c_22__n.BLIF N_127_i_1.BLIF SM_AMIGA_3_.BLIF N_123_i_1.BLIF \ -SM_AMIGA_2_.BLIF a_decode_c_23__n.BLIF N_121_i_1.BLIF N_119_i_1.BLIF N_6.BLIF \ -a_c_0__n.BLIF N_117_i_1.BLIF N_115_i_1.BLIF a_c_1__n.BLIF N_111_i_1.BLIF \ -N_165_1.BLIF N_13.BLIF nEXP_SPACE_c.BLIF N_162_1.BLIF N_148_1.BLIF N_18.BLIF \ -BERR_c.BLIF pos_clk_ipl_1_n.BLIF N_19.BLIF ds_000_dma_0_un3_n.BLIF N_20.BLIF \ -BG_030_c.BLIF ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF \ -BG_000DFFreg.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un1_n.BLIF \ -as_000_dma_0_un0_n.BLIF BGACK_000_c.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF bg_000_0_un3_n.BLIF \ -bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF CLK_OSZI_c.BLIF \ -lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF \ -CLK_OUT_INTreg.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un1_n.BLIF \ -as_030_d1_0_un0_n.BLIF FPU_SENSE_c.BLIF rw_000_int_0_un3_n.BLIF \ -rw_000_int_0_un1_n.BLIF IPL_030DFF_0_reg.BLIF rw_000_int_0_un0_n.BLIF \ -as_030_000_sync_0_un3_n.BLIF IPL_030DFF_1_reg.BLIF \ -as_030_000_sync_0_un1_n.BLIF SM_AMIGA_i_7_.BLIF as_030_000_sync_0_un0_n.BLIF \ -IPL_030DFF_2_reg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un1_n.BLIF \ -cpu_est_2_1__n.BLIF ipl_c_0__n.BLIF bgack_030_int_0_un0_n.BLIF \ -cpu_est_2_2__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_2_3__n.BLIF \ -ipl_c_1__n.BLIF cpu_est_0_1__un1_n.BLIF G_105.BLIF cpu_est_0_1__un0_n.BLIF \ -G_106.BLIF ipl_c_2__n.BLIF cpu_est_0_2__un3_n.BLIF G_107.BLIF \ -cpu_est_0_2__un1_n.BLIF N_60.BLIF cpu_est_0_2__un0_n.BLIF N_63.BLIF \ -DTACK_c.BLIF cpu_est_0_3__un3_n.BLIF N_126.BLIF cpu_est_0_3__un1_n.BLIF \ -N_150.BLIF cpu_est_0_3__un0_n.BLIF N_151.BLIF ipl_030_0_0__un3_n.BLIF \ -N_219.BLIF VPA_c.BLIF ipl_030_0_0__un1_n.BLIF N_175.BLIF \ -ipl_030_0_0__un0_n.BLIF ipl_030_0_1__un3_n.BLIF N_59.BLIF RST_c.BLIF \ -ipl_030_0_1__un1_n.BLIF N_68.BLIF ipl_030_0_1__un0_n.BLIF N_72.BLIF \ -ipl_030_0_2__un3_n.BLIF N_80.BLIF ipl_030_0_2__un1_n.BLIF N_93.BLIF RW_c.BLIF \ -ipl_030_0_2__un0_n.BLIF N_98.BLIF ds_000_enable_0_un3_n.BLIF N_107.BLIF \ -fc_c_0__n.BLIF ds_000_enable_0_un1_n.BLIF N_128.BLIF \ -ds_000_enable_0_un0_n.BLIF N_131.BLIF fc_c_1__n.BLIF vma_int_0_un3_n.BLIF \ -N_134.BLIF vma_int_0_un1_n.BLIF N_135.BLIF vma_int_0_un0_n.BLIF N_141.BLIF \ -AMIGA_BUS_DATA_DIR_c.BLIF a_decode_15__n.BLIF N_142.BLIF N_143.BLIF \ -a_decode_14__n.BLIF N_144.BLIF N_145.BLIF a_decode_13__n.BLIF N_146.BLIF \ -N_205_i.BLIF N_147.BLIF N_140_i.BLIF a_decode_12__n.BLIF N_148.BLIF \ -AMIGA_DS_i.BLIF N_149.BLIF a_decode_11__n.BLIF N_154.BLIF N_199_i.BLIF \ -N_155.BLIF N_198_i.BLIF a_decode_10__n.BLIF N_162.BLIF N_180_i.BLIF N_165.BLIF \ -N_262_i.BLIF a_decode_9__n.BLIF N_259.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF \ -N_260.BLIF pos_clk_un2_i_n.BLIF a_decode_8__n.BLIF N_181.BLIF N_3_i.BLIF \ -N_182.BLIF N_32_0.BLIF a_decode_7__n.BLIF N_183.BLIF N_4_i.BLIF N_184.BLIF \ -N_31_0.BLIF a_decode_6__n.BLIF N_185.BLIF N_220_i.BLIF N_186.BLIF \ -BG_030_c_i.BLIF a_decode_5__n.BLIF N_266.BLIF pos_clk_un9_bg_030_0_n.BLIF \ -N_267.BLIF N_17_i.BLIF a_decode_4__n.BLIF N_268.BLIF N_24_0.BLIF N_190.BLIF \ -N_16_i.BLIF a_decode_3__n.BLIF N_191.BLIF N_25_0.BLIF N_201.BLIF N_15_i.BLIF \ -a_decode_2__n.BLIF N_202.BLIF N_26_0.BLIF N_203.BLIF N_12_i.BLIF N_208.BLIF \ -N_28_0.BLIF N_163.BLIF N_11_i.BLIF N_282.BLIF N_29_0.BLIF un21_berr_1.BLIF \ -N_5_i.BLIF N_132.BLIF N_30_0.BLIF N_96.BLIF a_c_i_0__n.BLIF N_129.BLIF \ -size_c_i_1__n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF pos_clk_un10_sm_amiga_i_n.BLIF \ -N_169.BLIF un1_dsack1_i.BLIF N_170.BLIF N_69_i.BLIF N_167.BLIF N_163_i.BLIF \ -N_168.BLIF N_244_0.BLIF pos_clk_rw_000_int_5_n.BLIF N_164_i.BLIF \ -pos_clk_un6_bgack_000_n.BLIF N_165_i.BLIF N_274.BLIF \ -un11_amiga_bus_enable_high_i.BLIF N_164.BLIF un10_ciin_i.BLIF N_244.BLIF \ -N_60_0.BLIF N_5.BLIF N_274_i.BLIF N_11.BLIF pos_clk_un6_bgack_000_0_n.BLIF \ -N_12.BLIF RW_c_i.BLIF N_15.BLIF pos_clk_rw_000_int_5_0_n.BLIF N_16.BLIF \ -N_168_i.BLIF N_17.BLIF N_167_i.BLIF pos_clk_un9_bg_030_n.BLIF G_91.BLIF \ -N_170_i.BLIF N_3.BLIF N_169_i.BLIF N_205.BLIF AS_000_DMA_1_sqmuxa.BLIF \ -N_38_0.BLIF N_4.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF N_199.BLIF N_282_0.BLIF \ -pos_clk_un2_n.BLIF clk_000_d_i_3__n.BLIF N_140.BLIF N_96_0.BLIF N_262.BLIF \ -N_129_i.BLIF N_198.BLIF N_268_i.BLIF N_180.BLIF N_246_i.BLIF \ -un1_amiga_bus_enable_low_i.BLIF N_132_0.BLIF un21_fpu_cs_i.BLIF AS_000_i.BLIF \ -N_142_i.BLIF BGACK_030_INT_i.BLIF N_141_i.BLIF nEXP_SPACE_i.BLIF N_135_0.BLIF \ -cycle_dma_i_0__n.BLIF N_134_0.BLIF RW_000_i.BLIF N_131_i.BLIF CLK_EXP_i.BLIF \ -LDS_000_c_i.BLIF cycle_dma_i_1__n.BLIF UDS_000_c_i.BLIF DS_000_DMA_i.BLIF \ -N_128_i.BLIF AS_000_DMA_i.BLIF N_107_i.BLIF a_i_1__n.BLIF N_203_i.BLIF \ -AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF \ -a_decode_i_19__n.BLIF N_201_i.BLIF a_decode_i_18__n.BLIF N_202_i.BLIF \ -a_decode_i_16__n.BLIF VMA_INT_i.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \ -N_98_i.BLIF sm_amiga_i_0__n.BLIF N_93_i.BLIF sm_amiga_i_5__n.BLIF N_82_i.BLIF \ -sm_amiga_i_6__n.BLIF N_80_i.BLIF sm_amiga_i_i_7__n.BLIF N_72_i.BLIF \ -AS_030_i.BLIF N_68_i.BLIF AS_000_INT_i.BLIF N_59_i.BLIF DSACK1_INT_i.BLIF \ -N_190_i.BLIF sm_amiga_i_1__n.BLIF N_191_i.BLIF FPU_SENSE_i.BLIF \ -AS_030_D1_i.BLIF N_267_i.BLIF cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF \ -N_266_i.BLIF VPA_D_i.BLIF sm_amiga_i_3__n.BLIF N_186_i.BLIF \ -sm_amiga_i_4__n.BLIF cpu_est_i_1__n.BLIF N_185_i.BLIF clk_000_d_i_0__n.BLIF \ -clk_000_d_i_1__n.BLIF N_183_i.BLIF AS_030_D0_i.BLIF N_184_i.BLIF \ -cpu_est_i_2__n.BLIF DTACK_D0_i.BLIF N_182_i.BLIF sm_amiga_i_2__n.BLIF \ -AS_030_000_SYNC_i.BLIF N_181_i.BLIF ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF \ -N_260_i.BLIF ahigh_i_28__n.BLIF pos_clk_size_dma_6_0_1__n.BLIF \ -ahigh_i_29__n.BLIF N_259_i.BLIF ahigh_i_26__n.BLIF \ -pos_clk_size_dma_6_0_0__n.BLIF ahigh_i_27__n.BLIF N_63_0.BLIF \ -ahigh_i_24__n.BLIF N_155_i.BLIF ahigh_i_25__n.BLIF N_162_i.BLIF N_187_i.BLIF \ -un5_e_0.BLIF N_188_i.BLIF N_154_i.BLIF N_189_i.BLIF cpu_est_2_0_3__n.BLIF \ -N_149_i.BLIF N_208_i.BLIF cpu_est_2_0_2__n.BLIF N_147_i.BLIF un2_ds_030_i.BLIF \ -N_148_i.BLIF N_219_i.BLIF cpu_est_2_0_1__n.BLIF N_175_i.BLIF N_146_i.BLIF \ -un3_as_030_i.BLIF N_36_0.BLIF AS_030_c.BLIF N_145_i.BLIF N_35_0.BLIF \ -AS_000_c.BLIF N_143_i.BLIF N_144_i.BLIF RW_000_c.BLIF \ -pos_clk_un9_clk_000_pe_0_n.BLIF N_20_i.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ -RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ -SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \ -AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \ -AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF +A_0_.BLIF N_157_i.BLIF UDS_000_c.BLIF cpu_est_2_0_3__n.BLIF N_156_i.BLIF \ +LDS_000_c.BLIF N_229_i.BLIF cpu_est_2_0_2__n.BLIF size_c_0__n.BLIF \ +N_126_i.BLIF N_150_i.BLIF size_c_1__n.BLIF pos_clk_un9_clk_000_pe_0_n.BLIF \ +inst_BGACK_030_INTreg.BLIF N_20_i.BLIF vcc_n_n.BLIF ahigh_c_24__n.BLIF \ +N_23_0.BLIF un5_e.BLIF N_19_i.BLIF gnd_n_n.BLIF ahigh_c_25__n.BLIF N_22_0.BLIF \ +un1_amiga_bus_enable_low.BLIF N_18_i.BLIF un3_as_030.BLIF ahigh_c_26__n.BLIF \ +N_21_0.BLIF un1_UDS_000_INT.BLIF ipl_c_i_2__n.BLIF un1_LDS_000_INT.BLIF \ +ahigh_c_27__n.BLIF N_43_0.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF \ +ipl_c_i_1__n.BLIF un21_fpu_cs.BLIF ahigh_c_28__n.BLIF N_42_0.BLIF \ +un21_berr.BLIF ipl_c_i_0__n.BLIF un8_ciin.BLIF ahigh_c_29__n.BLIF N_41_0.BLIF \ +un2_ds_030.BLIF N_13_i.BLIF cpu_est_0_.BLIF ahigh_c_30__n.BLIF N_27_0.BLIF \ +cpu_est_1_.BLIF LDS_000_INT_i.BLIF cpu_est_2_.BLIF ahigh_c_31__n.BLIF \ +un1_LDS_000_INT_0.BLIF cpu_est_3_.BLIF UDS_000_INT_i.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF un1_UDS_000_INT_0.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_104_0_1.BLIF inst_AS_030_D0.BLIF \ +N_104_0_2.BLIF inst_AS_030_D1.BLIF N_100_0_1.BLIF inst_AS_030_000_SYNC.BLIF \ +N_100_0_2.BLIF inst_AS_000_DMA.BLIF N_113_i_1.BLIF inst_DS_000_DMA.BLIF \ +N_113_i_2.BLIF inst_VMA_INTreg.BLIF N_107_0_1.BLIF inst_VPA_D.BLIF \ +N_99_i_1.BLIF CLK_000_D_3_.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF \ +inst_DTACK_D0.BLIF N_202_1.BLIF inst_AMIGA_DS.BLIF N_202_2.BLIF \ +CLK_000_D_1_.BLIF N_228_1.BLIF CLK_000_D_0_.BLIF N_228_2.BLIF \ +inst_CLK_OUT_PRE_50.BLIF N_228_3.BLIF inst_CLK_OUT_PRE_D.BLIF N_228_4.BLIF \ +IPL_D0_0_.BLIF N_228_5.BLIF IPL_D0_1_.BLIF N_150_1.BLIF IPL_D0_2_.BLIF \ +N_150_2.BLIF CLK_000_D_2_.BLIF N_126_1.BLIF CLK_000_D_4_.BLIF N_126_2.BLIF \ +pos_clk_ipl_n.BLIF un8_ciin_1.BLIF SIZE_DMA_0_.BLIF un8_ciin_2.BLIF \ +SIZE_DMA_1_.BLIF N_201_1_1.BLIF inst_A0_DMA.BLIF N_201_1_2.BLIF \ +inst_RW_000_DMA.BLIF N_201_1_3.BLIF inst_UDS_000_INT.BLIF N_201_1_4.BLIF \ +inst_DS_000_ENABLE.BLIF N_201_1_5.BLIF inst_LDS_000_INT.BLIF \ +a_decode_c_16__n.BLIF N_201_1_6.BLIF inst_BGACK_030_INT_D.BLIF N_201_1_7.BLIF \ +SM_AMIGA_6_.BLIF a_decode_c_17__n.BLIF N_201_1_8.BLIF inst_RW_000_INT.BLIF \ +N_201_1_0.BLIF SM_AMIGA_4_.BLIF a_decode_c_18__n.BLIF N_201_2.BLIF \ +SM_AMIGA_1_.BLIF pos_clk_cycle_dma_5_1_1__n.BLIF SM_AMIGA_0_.BLIF \ +a_decode_c_19__n.BLIF N_176_1.BLIF CYCLE_DMA_0_.BLIF \ +AS_000_DMA_1_sqmuxa_1.BLIF CYCLE_DMA_1_.BLIF a_decode_c_20__n.BLIF \ +N_198_1.BLIF inst_DSACK1_INT.BLIF N_72_i_1.BLIF inst_AS_000_INT.BLIF \ +a_decode_c_21__n.BLIF N_72_i_2.BLIF pos_clk_un9_clk_000_pe_n.BLIF \ +N_206_i_1.BLIF SM_AMIGA_5_.BLIF a_decode_c_22__n.BLIF N_206_i_2.BLIF \ +SM_AMIGA_3_.BLIF N_186_1.BLIF SM_AMIGA_2_.BLIF a_decode_c_23__n.BLIF \ +N_186_2.BLIF N_74_i_1.BLIF N_6.BLIF a_c_0__n.BLIF N_121_i_1.BLIF \ +N_117_i_1.BLIF a_c_1__n.BLIF N_115_i_1.BLIF N_127_i_1.BLIF N_13.BLIF \ +nEXP_SPACE_c.BLIF N_123_i_1.BLIF N_119_i_1.BLIF N_18.BLIF BERR_c.BLIF \ +N_111_i_1.BLIF N_19.BLIF un21_berr_1.BLIF N_20.BLIF BG_030_c.BLIF \ +un21_fpu_cs_1.BLIF N_172_1.BLIF BG_000DFFreg.BLIF N_161_1.BLIF N_153_1.BLIF \ +pos_clk_ipl_1_n.BLIF BGACK_000_c.BLIF ds_000_dma_0_un3_n.BLIF \ +ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF as_000_dma_0_un3_n.BLIF \ +as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF CLK_OSZI_c.BLIF \ +uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF \ +CLK_OUT_INTreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF \ +bg_000_0_un0_n.BLIF FPU_SENSE_c.BLIF lds_000_int_0_un3_n.BLIF \ +lds_000_int_0_un1_n.BLIF IPL_030DFF_0_reg.BLIF lds_000_int_0_un0_n.BLIF \ +rw_000_int_0_un3_n.BLIF IPL_030DFF_1_reg.BLIF rw_000_int_0_un1_n.BLIF \ +rw_000_int_0_un0_n.BLIF SM_AMIGA_i_7_.BLIF IPL_030DFF_2_reg.BLIF \ +bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un1_n.BLIF ipl_c_0__n.BLIF \ +bgack_030_int_0_un0_n.BLIF cpu_est_2_2__n.BLIF as_030_000_sync_0_un3_n.BLIF \ +cpu_est_2_3__n.BLIF ipl_c_1__n.BLIF as_030_000_sync_0_un1_n.BLIF G_105.BLIF \ +as_030_000_sync_0_un0_n.BLIF G_106.BLIF ipl_c_2__n.BLIF \ +cpu_est_0_1__un3_n.BLIF G_107.BLIF cpu_est_0_1__un1_n.BLIF \ +cpu_est_0_1__un0_n.BLIF N_205.BLIF DTACK_c.BLIF cpu_est_0_2__un3_n.BLIF \ +N_74.BLIF cpu_est_0_2__un1_n.BLIF N_78.BLIF cpu_est_0_2__un0_n.BLIF N_79.BLIF \ +cpu_est_0_3__un3_n.BLIF N_80.BLIF VPA_c.BLIF cpu_est_0_3__un1_n.BLIF N_83.BLIF \ +cpu_est_0_3__un0_n.BLIF N_84.BLIF ipl_030_0_0__un3_n.BLIF N_89.BLIF RST_c.BLIF \ +ipl_030_0_0__un1_n.BLIF N_95.BLIF ipl_030_0_0__un0_n.BLIF N_96.BLIF \ +ipl_030_0_1__un3_n.BLIF N_97.BLIF ipl_030_0_1__un1_n.BLIF N_105.BLIF RW_c.BLIF \ +ipl_030_0_1__un0_n.BLIF N_126.BLIF ipl_030_0_2__un3_n.BLIF N_150.BLIF \ +fc_c_0__n.BLIF ipl_030_0_2__un1_n.BLIF N_153.BLIF ipl_030_0_2__un0_n.BLIF \ +N_156.BLIF fc_c_1__n.BLIF ds_000_enable_0_un3_n.BLIF N_157.BLIF \ +ds_000_enable_0_un1_n.BLIF N_158.BLIF ds_000_enable_0_un0_n.BLIF N_159.BLIF \ +AMIGA_BUS_DATA_DIR_c.BLIF vma_int_0_un3_n.BLIF N_160.BLIF vma_int_0_un1_n.BLIF \ +N_161.BLIF vma_int_0_un0_n.BLIF N_172.BLIF as_030_d1_0_un3_n.BLIF N_177.BLIF \ +as_030_d1_0_un1_n.BLIF N_178.BLIF N_181_i.BLIF as_030_d1_0_un0_n.BLIF \ +N_179.BLIF N_37_0.BLIF a_decode_15__n.BLIF N_180.BLIF N_182.BLIF N_176_i.BLIF \ +a_decode_14__n.BLIF N_183.BLIF N_175_i.BLIF N_184.BLIF N_72_i.BLIF \ +a_decode_13__n.BLIF N_212.BLIF N_198_i.BLIF N_213.BLIF AMIGA_DS_i.BLIF \ +a_decode_12__n.BLIF N_214.BLIF N_186_i.BLIF N_190.BLIF N_185_i.BLIF \ +a_decode_11__n.BLIF N_191.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_194.BLIF \ +pos_clk_un2_i_n.BLIF a_decode_10__n.BLIF N_195.BLIF N_3_i.BLIF N_196.BLIF \ +N_32_0.BLIF a_decode_9__n.BLIF N_197.BLIF N_4_i.BLIF N_202.BLIF N_31_0.BLIF \ +a_decode_8__n.BLIF N_220.BLIF N_39_1_i.BLIF N_224.BLIF N_34_0.BLIF \ +a_decode_7__n.BLIF N_225.BLIF BG_030_c_i.BLIF N_228.BLIF \ +pos_clk_un9_bg_030_0_n.BLIF a_decode_6__n.BLIF N_229.BLIF N_17_i.BLIF \ +N_201_1.BLIF N_24_0.BLIF a_decode_5__n.BLIF N_104.BLIF N_16_i.BLIF N_100.BLIF \ +N_25_0.BLIF a_decode_4__n.BLIF N_171.BLIF N_15_i.BLIF N_204.BLIF N_26_0.BLIF \ +a_decode_3__n.BLIF N_164.BLIF N_12_i.BLIF N_162.BLIF N_28_0.BLIF \ +a_decode_2__n.BLIF N_163.BLIF N_5_i.BLIF cpu_est_2_1__n.BLIF N_30_0.BLIF \ +N_152.BLIF a_c_i_0__n.BLIF N_11.BLIF size_c_i_1__n.BLIF N_201.BLIF \ +pos_clk_un10_sm_amiga_i_n.BLIF N_193.BLIF N_231_i.BLIF N_192.BLIF \ +pos_clk_un6_bgack_000_0_n.BLIF N_107.BLIF N_40_0.BLIF N_99.BLIF \ +un1_SM_AMIGA_0_sqmuxa_1_0.BLIF N_219.BLIF RW_c_i.BLIF N_81.BLIF \ +pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n.BLIF N_201_i.BLIF \ +un1_SM_AMIGA_0_sqmuxa_1.BLIF N_81_i.BLIF pos_clk_un6_bgack_000_n.BLIF \ +N_219_i.BLIF N_231.BLIF N_202_i.BLIF N_5.BLIF N_191_i.BLIF N_12.BLIF \ +N_98_i.BLIF N_15.BLIF N_99_i.BLIF N_16.BLIF N_107_0.BLIF N_17.BLIF \ +N_192_i.BLIF pos_clk_un9_bg_030_n.BLIF N_193_i.BLIF N_3.BLIF N_72.BLIF \ +N_11_i.BLIF AS_000_DMA_1_sqmuxa.BLIF N_29_0.BLIF N_4.BLIF VPA_c_i.BLIF \ +G_91.BLIF N_44_0.BLIF N_176.BLIF DTACK_c_i.BLIF pos_clk_un2_n.BLIF N_45_0.BLIF \ +N_175.BLIF N_152_i.BLIF N_185.BLIF N_153_i.BLIF N_198.BLIF \ +cpu_est_2_0_1__n.BLIF N_186.BLIF N_163_i.BLIF N_181.BLIF N_162_i.BLIF \ +un1_amiga_bus_enable_low_i.BLIF un21_fpu_cs_i.BLIF N_203_i.BLIF AS_000_i.BLIF \ +un1_dsack1_i.BLIF BGACK_030_INT_i.BLIF N_164_i.BLIF nEXP_SPACE_i.BLIF \ +N_228_i.BLIF RW_000_i.BLIF N_204_0.BLIF cycle_dma_i_0__n.BLIF N_171_i.BLIF \ +CLK_EXP_i.BLIF N_172_i.BLIF cycle_dma_i_1__n.BLIF \ +un11_amiga_bus_enable_high_i.BLIF DS_000_DMA_i.BLIF N_85_0.BLIF \ +AS_000_DMA_i.BLIF clk_000_d_i_3__n.BLIF ahigh_i_25__n.BLIF N_100_0.BLIF \ +ahigh_i_24__n.BLIF AS_030_D1_i.BLIF ahigh_i_27__n.BLIF N_104_0.BLIF \ +ahigh_i_26__n.BLIF N_105_0.BLIF ahigh_i_29__n.BLIF N_97_i.BLIF \ +ahigh_i_28__n.BLIF LDS_000_c_i.BLIF ahigh_i_31__n.BLIF UDS_000_c_i.BLIF \ +ahigh_i_30__n.BLIF N_96_i.BLIF sm_amiga_i_2__n.BLIF N_95_i.BLIF \ +sm_amiga_i_1__n.BLIF N_220_i.BLIF DTACK_D0_i.BLIF \ +un1_DS_000_ENABLE_0_sqmuxa_0.BLIF sm_amiga_i_i_7__n.BLIF VMA_INT_i.BLIF \ +sm_amiga_i_3__n.BLIF N_89_i.BLIF a_decode_i_20__n.BLIF N_84_i.BLIF \ +AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_83_i.BLIF cpu_est_i_0__n.BLIF N_82_i.BLIF \ +AS_030_i.BLIF N_80_i.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_79_i.BLIF \ +sm_amiga_i_6__n.BLIF N_78_0.BLIF AS_030_D0_i.BLIF N_74_i.BLIF \ +cpu_est_i_3__n.BLIF N_197_i.BLIF VPA_D_i.BLIF sm_amiga_i_5__n.BLIF \ +N_195_i.BLIF sm_amiga_i_4__n.BLIF N_196_i.BLIF cpu_est_i_1__n.BLIF \ +clk_000_d_i_0__n.BLIF N_194_i.BLIF clk_000_d_i_1__n.BLIF cpu_est_i_2__n.BLIF \ +N_190_i.BLIF DSACK1_INT_i.BLIF AS_000_INT_i.BLIF N_214_i.BLIF \ +a_decode_i_16__n.BLIF a_decode_i_19__n.BLIF N_184_i.BLIF a_decode_i_18__n.BLIF \ +pos_clk_size_dma_6_0_1__n.BLIF FPU_SENSE_i.BLIF N_183_i.BLIF \ +AS_030_000_SYNC_i.BLIF pos_clk_size_dma_6_0_0__n.BLIF sm_amiga_i_0__n.BLIF \ +N_182_i.BLIF N_187_i.BLIF N_38_0.BLIF N_188_i.BLIF N_179_i.BLIF N_189_i.BLIF \ +N_180_i.BLIF N_177_i.BLIF N_178_i.BLIF un2_ds_030_i.BLIF N_225_i.BLIF \ +un8_ciin_i.BLIF N_224_i.BLIF N_205_0.BLIF un3_as_030_i.BLIF N_160_i.BLIF \ +AS_030_c.BLIF N_161_i.BLIF un5_e_0.BLIF AS_000_c.BLIF N_159_i.BLIF \ +RW_000_c.BLIF N_158_i.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \ +UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ +AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF \ +AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF \ +A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ -SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D \ -SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D \ -IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ -IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ -IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ -SM_AMIGA_5_.D SM_AMIGA_5_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D \ -CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C \ -SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C CYCLE_DMA_0_.D \ -CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C \ -cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C \ -CLK_000_D_0_.D CLK_000_D_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ -inst_DTACK_D0.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_D0_2_.D IPL_D0_2_.C \ +SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \ +SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C \ +SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D \ +SM_AMIGA_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D \ +cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D \ +IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D \ +IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C CLK_000_D_0_.D CLK_000_D_0_.C \ +CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D \ +CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C SIZE_DMA_0_.D SIZE_DMA_0_.C \ +SIZE_DMA_1_.D SIZE_DMA_1_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \ +CYCLE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_DSACK1_INT.D inst_DSACK1_INT.C \ +inst_AS_000_INT.D inst_AS_000_INT.C inst_AMIGA_DS.D inst_AMIGA_DS.C \ +inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ +inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ +inst_DTACK_D0.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_AS_030_D1.D \ +inst_AS_030_D1.C inst_UDS_000_INT.D inst_UDS_000_INT.C BG_000DFFreg.D \ BG_000DFFreg.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_VMA_INTreg.D \ inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C inst_AS_030_000_SYNC.D \ inst_AS_030_000_SYNC.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C \ -inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D inst_AS_000_INT.C \ -inst_AMIGA_DS.D inst_AMIGA_DS.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D \ -inst_RW_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ -inst_AS_030_D1.D inst_AS_030_D1.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D \ CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ AHIGH_31_ AS_030 AS_000 \ RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \ -AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_23_0 UDS_000_c N_19_i N_22_0 LDS_000_c \ -N_18_i N_21_0 size_c_0__n ipl_c_i_2__n N_43_0 size_c_1__n ipl_c_i_1__n N_42_0 \ -vcc_n_n ahigh_c_24__n ipl_c_i_0__n un5_e N_41_0 gnd_n_n ahigh_c_25__n \ -DTACK_c_i un1_amiga_bus_enable_low N_45_0 un3_as_030 ahigh_c_26__n VPA_c_i \ -un1_UDS_000_INT N_44_0 un1_LDS_000_INT ahigh_c_27__n N_13_i \ -un1_DS_000_ENABLE_0_sqmuxa N_27_0 un10_ciin ahigh_c_28__n LDS_000_INT_i \ -un21_fpu_cs un1_LDS_000_INT_0 un21_berr ahigh_c_29__n UDS_000_INT_i un2_ds_030 \ -un1_UDS_000_INT_0 ahigh_c_30__n N_96_0_1 N_96_0_2 ahigh_c_31__n N_282_0_1 \ -N_282_0_2 N_282_0_3 N_282_0_4 pos_clk_un10_sm_amiga_i_1_n un10_ciin_1 \ -un10_ciin_2 un10_ciin_3 un10_ciin_4 un10_ciin_5 un10_ciin_6 un10_ciin_7 \ -un10_ciin_8 un10_ciin_9 un10_ciin_10 un10_ciin_11 N_201_1 N_201_2 N_131_i_1 \ -N_134_0_1 N_113_i_1 N_113_i_2 N_144_1 pos_clk_ipl_n N_144_2 N_143_1 N_143_2 \ -N_163_1 N_163_2 N_163_3 un21_fpu_cs_1 a_decode_c_16__n un21_berr_1_0 \ -pos_clk_cycle_dma_5_1_1__n a_decode_c_17__n N_199_1 AS_000_DMA_1_sqmuxa_1 \ -a_decode_c_18__n N_140_1 N_66_i_1 a_decode_c_19__n N_66_i_2 N_205_i_1 \ -a_decode_c_20__n N_205_i_2 N_180_1 a_decode_c_21__n N_180_2 \ -pos_clk_un9_clk_000_pe_n N_59_i_1 a_decode_c_22__n N_127_i_1 N_123_i_1 \ -a_decode_c_23__n N_121_i_1 N_119_i_1 N_6 a_c_0__n N_117_i_1 N_115_i_1 a_c_1__n \ -N_111_i_1 N_165_1 N_13 nEXP_SPACE_c N_162_1 N_148_1 N_18 BERR_c \ -pos_clk_ipl_1_n N_19 ds_000_dma_0_un3_n N_20 BG_030_c ds_000_dma_0_un1_n \ +AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_157_i UDS_000_c cpu_est_2_0_3__n N_156_i \ +LDS_000_c N_229_i cpu_est_2_0_2__n size_c_0__n N_126_i N_150_i size_c_1__n \ +pos_clk_un9_clk_000_pe_0_n N_20_i vcc_n_n ahigh_c_24__n N_23_0 un5_e N_19_i \ +gnd_n_n ahigh_c_25__n N_22_0 un1_amiga_bus_enable_low N_18_i un3_as_030 \ +ahigh_c_26__n N_21_0 un1_UDS_000_INT ipl_c_i_2__n un1_LDS_000_INT \ +ahigh_c_27__n N_43_0 un1_DS_000_ENABLE_0_sqmuxa ipl_c_i_1__n un21_fpu_cs \ +ahigh_c_28__n N_42_0 un21_berr ipl_c_i_0__n un8_ciin ahigh_c_29__n N_41_0 \ +un2_ds_030 N_13_i ahigh_c_30__n N_27_0 LDS_000_INT_i ahigh_c_31__n \ +un1_LDS_000_INT_0 UDS_000_INT_i un1_UDS_000_INT_0 N_104_0_1 N_104_0_2 \ +N_100_0_1 N_100_0_2 N_113_i_1 N_113_i_2 N_107_0_1 N_99_i_1 \ +pos_clk_un10_sm_amiga_i_1_n N_202_1 N_202_2 N_228_1 N_228_2 N_228_3 N_228_4 \ +N_228_5 N_150_1 N_150_2 N_126_1 N_126_2 pos_clk_ipl_n un8_ciin_1 un8_ciin_2 \ +N_201_1_1 N_201_1_2 N_201_1_3 N_201_1_4 N_201_1_5 a_decode_c_16__n N_201_1_6 \ +N_201_1_7 a_decode_c_17__n N_201_1_8 N_201_1_0 a_decode_c_18__n N_201_2 \ +pos_clk_cycle_dma_5_1_1__n a_decode_c_19__n N_176_1 AS_000_DMA_1_sqmuxa_1 \ +a_decode_c_20__n N_198_1 N_72_i_1 a_decode_c_21__n N_72_i_2 \ +pos_clk_un9_clk_000_pe_n N_206_i_1 a_decode_c_22__n N_206_i_2 N_186_1 \ +a_decode_c_23__n N_186_2 N_74_i_1 N_6 a_c_0__n N_121_i_1 N_117_i_1 a_c_1__n \ +N_115_i_1 N_127_i_1 N_13 nEXP_SPACE_c N_123_i_1 N_119_i_1 N_18 BERR_c \ +N_111_i_1 N_19 un21_berr_1 N_20 BG_030_c un21_fpu_cs_1 N_172_1 N_161_1 N_153_1 \ +pos_clk_ipl_1_n BGACK_000_c ds_000_dma_0_un3_n ds_000_dma_0_un1_n \ ds_000_dma_0_un0_n as_000_dma_0_un3_n as_000_dma_0_un1_n as_000_dma_0_un0_n \ -BGACK_000_c uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n \ -bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n CLK_OSZI_c lds_000_int_0_un3_n \ -lds_000_int_0_un1_n lds_000_int_0_un0_n as_030_d1_0_un3_n as_030_d1_0_un1_n \ -as_030_d1_0_un0_n FPU_SENSE_c rw_000_int_0_un3_n rw_000_int_0_un1_n \ -rw_000_int_0_un0_n as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n \ -as_030_000_sync_0_un0_n bgack_030_int_0_un3_n bgack_030_int_0_un1_n \ -cpu_est_2_1__n ipl_c_0__n bgack_030_int_0_un0_n cpu_est_2_2__n \ -cpu_est_0_1__un3_n cpu_est_2_3__n ipl_c_1__n cpu_est_0_1__un1_n \ -cpu_est_0_1__un0_n ipl_c_2__n cpu_est_0_2__un3_n cpu_est_0_2__un1_n N_60 \ -cpu_est_0_2__un0_n N_63 DTACK_c cpu_est_0_3__un3_n N_126 cpu_est_0_3__un1_n \ -N_150 cpu_est_0_3__un0_n N_151 ipl_030_0_0__un3_n N_219 VPA_c \ -ipl_030_0_0__un1_n N_175 ipl_030_0_0__un0_n ipl_030_0_1__un3_n N_59 RST_c \ -ipl_030_0_1__un1_n N_68 ipl_030_0_1__un0_n N_72 ipl_030_0_2__un3_n N_80 \ -ipl_030_0_2__un1_n N_93 RW_c ipl_030_0_2__un0_n N_98 ds_000_enable_0_un3_n \ -N_107 fc_c_0__n ds_000_enable_0_un1_n N_128 ds_000_enable_0_un0_n N_131 \ -fc_c_1__n vma_int_0_un3_n N_134 vma_int_0_un1_n N_135 vma_int_0_un0_n N_141 \ -AMIGA_BUS_DATA_DIR_c a_decode_15__n N_142 N_143 a_decode_14__n N_144 N_145 \ -a_decode_13__n N_146 N_205_i N_147 N_140_i a_decode_12__n N_148 AMIGA_DS_i \ -N_149 a_decode_11__n N_154 N_199_i N_155 N_198_i a_decode_10__n N_162 N_180_i \ -N_165 N_262_i a_decode_9__n N_259 AMIGA_BUS_DATA_DIR_c_0 N_260 pos_clk_un2_i_n \ -a_decode_8__n N_181 N_3_i N_182 N_32_0 a_decode_7__n N_183 N_4_i N_184 N_31_0 \ -a_decode_6__n N_185 N_220_i N_186 BG_030_c_i a_decode_5__n N_266 \ -pos_clk_un9_bg_030_0_n N_267 N_17_i a_decode_4__n N_268 N_24_0 N_190 N_16_i \ -a_decode_3__n N_191 N_25_0 N_201 N_15_i a_decode_2__n N_202 N_26_0 N_203 \ -N_12_i N_208 N_28_0 N_163 N_11_i N_282 N_29_0 un21_berr_1 N_5_i N_132 N_30_0 \ -N_96 a_c_i_0__n N_129 size_c_i_1__n un1_SM_AMIGA_0_sqmuxa_1 \ -pos_clk_un10_sm_amiga_i_n N_169 un1_dsack1_i N_170 N_69_i N_167 N_163_i N_168 \ -N_244_0 pos_clk_rw_000_int_5_n N_164_i pos_clk_un6_bgack_000_n N_165_i N_274 \ -un11_amiga_bus_enable_high_i N_164 un10_ciin_i N_244 N_60_0 N_5 N_274_i N_11 \ -pos_clk_un6_bgack_000_0_n N_12 RW_c_i N_15 pos_clk_rw_000_int_5_0_n N_16 \ -N_168_i N_17 N_167_i pos_clk_un9_bg_030_n N_170_i N_3 N_169_i N_205 \ -AS_000_DMA_1_sqmuxa N_38_0 N_4 un1_SM_AMIGA_0_sqmuxa_1_0 N_199 N_282_0 \ -pos_clk_un2_n clk_000_d_i_3__n N_140 N_96_0 N_262 N_129_i N_198 N_268_i N_180 \ -N_246_i un1_amiga_bus_enable_low_i N_132_0 un21_fpu_cs_i AS_000_i N_142_i \ -BGACK_030_INT_i N_141_i nEXP_SPACE_i N_135_0 cycle_dma_i_0__n N_134_0 RW_000_i \ -N_131_i CLK_EXP_i LDS_000_c_i cycle_dma_i_1__n UDS_000_c_i DS_000_DMA_i \ -N_128_i AS_000_DMA_i N_107_i a_i_1__n N_203_i AMIGA_BUS_ENABLE_DMA_LOW_i \ -un1_DS_000_ENABLE_0_sqmuxa_0 a_decode_i_19__n N_201_i a_decode_i_18__n N_202_i \ -a_decode_i_16__n VMA_INT_i AMIGA_BUS_ENABLE_DMA_HIGH_i N_98_i sm_amiga_i_0__n \ -N_93_i sm_amiga_i_5__n N_82_i sm_amiga_i_6__n N_80_i sm_amiga_i_i_7__n N_72_i \ -AS_030_i N_68_i AS_000_INT_i N_59_i DSACK1_INT_i N_190_i sm_amiga_i_1__n \ -N_191_i FPU_SENSE_i AS_030_D1_i N_267_i cpu_est_i_0__n cpu_est_i_3__n N_266_i \ -VPA_D_i sm_amiga_i_3__n N_186_i sm_amiga_i_4__n cpu_est_i_1__n N_185_i \ -clk_000_d_i_0__n clk_000_d_i_1__n N_183_i AS_030_D0_i N_184_i cpu_est_i_2__n \ -DTACK_D0_i N_182_i sm_amiga_i_2__n AS_030_000_SYNC_i N_181_i ahigh_i_30__n \ -ahigh_i_31__n N_260_i ahigh_i_28__n pos_clk_size_dma_6_0_1__n ahigh_i_29__n \ -N_259_i ahigh_i_26__n pos_clk_size_dma_6_0_0__n ahigh_i_27__n N_63_0 \ -ahigh_i_24__n N_155_i ahigh_i_25__n N_162_i N_187_i un5_e_0 N_188_i N_154_i \ -N_189_i cpu_est_2_0_3__n N_149_i N_208_i cpu_est_2_0_2__n N_147_i un2_ds_030_i \ -N_148_i N_219_i cpu_est_2_0_1__n N_175_i N_146_i un3_as_030_i N_36_0 AS_030_c \ -N_145_i N_35_0 AS_000_c N_143_i N_144_i RW_000_c pos_clk_un9_clk_000_pe_0_n \ -N_20_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ -SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE \ -AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE \ -DSACK1.OE VMA.OE CIIN.OE G_105 G_106 G_107 G_91 +CLK_OSZI_c uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n \ +bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n FPU_SENSE_c lds_000_int_0_un3_n \ +lds_000_int_0_un1_n lds_000_int_0_un0_n rw_000_int_0_un3_n rw_000_int_0_un1_n \ +rw_000_int_0_un0_n bgack_030_int_0_un3_n bgack_030_int_0_un1_n ipl_c_0__n \ +bgack_030_int_0_un0_n cpu_est_2_2__n as_030_000_sync_0_un3_n cpu_est_2_3__n \ +ipl_c_1__n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n ipl_c_2__n \ +cpu_est_0_1__un3_n cpu_est_0_1__un1_n cpu_est_0_1__un0_n N_205 DTACK_c \ +cpu_est_0_2__un3_n N_74 cpu_est_0_2__un1_n N_78 cpu_est_0_2__un0_n N_79 \ +cpu_est_0_3__un3_n N_80 VPA_c cpu_est_0_3__un1_n N_83 cpu_est_0_3__un0_n N_84 \ +ipl_030_0_0__un3_n N_89 RST_c ipl_030_0_0__un1_n N_95 ipl_030_0_0__un0_n N_96 \ +ipl_030_0_1__un3_n N_97 ipl_030_0_1__un1_n N_105 RW_c ipl_030_0_1__un0_n N_126 \ +ipl_030_0_2__un3_n N_150 fc_c_0__n ipl_030_0_2__un1_n N_153 ipl_030_0_2__un0_n \ +N_156 fc_c_1__n ds_000_enable_0_un3_n N_157 ds_000_enable_0_un1_n N_158 \ +ds_000_enable_0_un0_n N_159 AMIGA_BUS_DATA_DIR_c vma_int_0_un3_n N_160 \ +vma_int_0_un1_n N_161 vma_int_0_un0_n N_172 as_030_d1_0_un3_n N_177 \ +as_030_d1_0_un1_n N_178 N_181_i as_030_d1_0_un0_n N_179 N_37_0 a_decode_15__n \ +N_180 N_182 N_176_i a_decode_14__n N_183 N_175_i N_184 N_72_i a_decode_13__n \ +N_212 N_198_i N_213 AMIGA_DS_i a_decode_12__n N_214 N_186_i N_190 N_185_i \ +a_decode_11__n N_191 AMIGA_BUS_DATA_DIR_c_0 N_194 pos_clk_un2_i_n \ +a_decode_10__n N_195 N_3_i N_196 N_32_0 a_decode_9__n N_197 N_4_i N_202 N_31_0 \ +a_decode_8__n N_220 N_39_1_i N_224 N_34_0 a_decode_7__n N_225 BG_030_c_i N_228 \ +pos_clk_un9_bg_030_0_n a_decode_6__n N_229 N_17_i N_201_1 N_24_0 a_decode_5__n \ +N_104 N_16_i N_100 N_25_0 a_decode_4__n N_171 N_15_i N_204 N_26_0 \ +a_decode_3__n N_164 N_12_i N_162 N_28_0 a_decode_2__n N_163 N_5_i \ +cpu_est_2_1__n N_30_0 N_152 a_c_i_0__n N_11 size_c_i_1__n N_201 \ +pos_clk_un10_sm_amiga_i_n N_193 N_231_i N_192 pos_clk_un6_bgack_000_0_n N_107 \ +N_40_0 N_99 un1_SM_AMIGA_0_sqmuxa_1_0 N_219 RW_c_i N_81 \ +pos_clk_rw_000_int_5_0_n pos_clk_rw_000_int_5_n N_201_i \ +un1_SM_AMIGA_0_sqmuxa_1 N_81_i pos_clk_un6_bgack_000_n N_219_i N_231 N_202_i \ +N_5 N_191_i N_12 N_98_i N_15 N_99_i N_16 N_107_0 N_17 N_192_i \ +pos_clk_un9_bg_030_n N_193_i N_3 N_72 N_11_i AS_000_DMA_1_sqmuxa N_29_0 N_4 \ +VPA_c_i N_44_0 N_176 DTACK_c_i pos_clk_un2_n N_45_0 N_175 N_152_i N_185 \ +N_153_i N_198 cpu_est_2_0_1__n N_186 N_163_i N_181 N_162_i \ +un1_amiga_bus_enable_low_i un21_fpu_cs_i N_203_i AS_000_i un1_dsack1_i \ +BGACK_030_INT_i N_164_i nEXP_SPACE_i N_228_i RW_000_i N_204_0 cycle_dma_i_0__n \ +N_171_i CLK_EXP_i N_172_i cycle_dma_i_1__n un11_amiga_bus_enable_high_i \ +DS_000_DMA_i N_85_0 AS_000_DMA_i clk_000_d_i_3__n ahigh_i_25__n N_100_0 \ +ahigh_i_24__n AS_030_D1_i ahigh_i_27__n N_104_0 ahigh_i_26__n N_105_0 \ +ahigh_i_29__n N_97_i ahigh_i_28__n LDS_000_c_i ahigh_i_31__n UDS_000_c_i \ +ahigh_i_30__n N_96_i sm_amiga_i_2__n N_95_i sm_amiga_i_1__n N_220_i DTACK_D0_i \ +un1_DS_000_ENABLE_0_sqmuxa_0 sm_amiga_i_i_7__n VMA_INT_i sm_amiga_i_3__n \ +N_89_i a_decode_i_20__n N_84_i AMIGA_BUS_ENABLE_DMA_LOW_i N_83_i \ +cpu_est_i_0__n N_82_i AS_030_i N_80_i AMIGA_BUS_ENABLE_DMA_HIGH_i N_79_i \ +sm_amiga_i_6__n N_78_0 AS_030_D0_i N_74_i cpu_est_i_3__n N_197_i VPA_D_i \ +sm_amiga_i_5__n N_195_i sm_amiga_i_4__n N_196_i cpu_est_i_1__n \ +clk_000_d_i_0__n N_194_i clk_000_d_i_1__n cpu_est_i_2__n N_190_i DSACK1_INT_i \ +AS_000_INT_i N_214_i a_decode_i_16__n a_decode_i_19__n N_184_i \ +a_decode_i_18__n pos_clk_size_dma_6_0_1__n FPU_SENSE_i N_183_i \ +AS_030_000_SYNC_i pos_clk_size_dma_6_0_0__n sm_amiga_i_0__n N_182_i N_187_i \ +N_38_0 N_188_i N_179_i N_189_i N_180_i N_177_i N_178_i un2_ds_030_i N_225_i \ +un8_ciin_i N_224_i N_205_0 un3_as_030_i N_160_i AS_030_c N_161_i un5_e_0 \ +AS_000_c N_159_i RW_000_c N_158_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE \ +LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE \ +AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE \ +BERR.OE RW.OE DS_030.OE DSACK1.OE VMA.OE CIIN.OE G_105 G_106 G_107 G_91 +.names N_43_0.BLIF IPL_D0_2_.D +0 1 +.names N_127_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D +11 1 +.names N_123_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D +11 1 +.names N_121_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D +11 1 .names N_119_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D 11 1 .names N_117_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D @@ -343,6 +354,15 @@ DSACK1.OE VMA.OE CIIN.OE G_105 G_106 G_107 G_91 11 1 .names N_111_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D 11 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D +1- 1 +-1 1 .names N_21_0.BLIF IPL_030DFF_0_reg.D 0 1 .names N_22_0.BLIF IPL_030DFF_1_reg.D @@ -353,34 +373,31 @@ DSACK1.OE VMA.OE CIIN.OE G_105 G_106 G_107 G_91 0 1 .names N_42_0.BLIF IPL_D0_1_.D 0 1 -.names N_43_0.BLIF IPL_D0_2_.D -0 1 -.names N_127_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D -11 1 -.names N_123_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D -11 1 -.names N_121_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D -11 1 .names pos_clk_size_dma_6_0_0__n.BLIF SIZE_DMA_0_.D 0 1 .names pos_clk_size_dma_6_0_1__n.BLIF SIZE_DMA_1_.D 0 1 -.names N_66_i_1.BLIF N_66_i_2.BLIF CYCLE_DMA_0_.D +.names N_206_i_1.BLIF N_206_i_2.BLIF CYCLE_DMA_0_.D 11 1 .names pos_clk_cycle_dma_5_1_1__n.BLIF G_91.BLIF CYCLE_DMA_1_.D 11 1 -.names N_190_i.BLIF N_191_i.BLIF cpu_est_0_.D +.names N_162_i.BLIF N_163_i.BLIF cpu_est_0_.D 11 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D -1- 1 --1 1 -.names N_151.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +.names N_213.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names N_177_i.BLIF N_178_i.BLIF inst_DSACK1_INT.D +11 1 +.names N_179_i.BLIF N_180_i.BLIF inst_AS_000_INT.D +11 1 +.names N_37_0.BLIF inst_AMIGA_DS.D +0 1 +.names N_38_0.BLIF inst_A0_DMA.D +0 1 +.names N_212.BLIF inst_RW_000_DMA.D +0 1 +.names N_40_0.BLIF inst_AS_030_D0.D 0 1 .names N_44_0.BLIF inst_VPA_D.D 0 1 @@ -388,6 +405,11 @@ DSACK1.OE VMA.OE CIIN.OE G_105 G_106 G_107 G_91 0 1 .names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D 11 1 +.names as_030_d1_0_un1_n.BLIF as_030_d1_0_un0_n.BLIF inst_AS_030_D1.D +1- 1 +-1 1 +.names N_24_0.BLIF inst_UDS_000_INT.D +0 1 .names N_25_0.BLIF BG_000DFFreg.D 0 1 .names N_26_0.BLIF inst_LDS_000_INT.D @@ -404,235 +426,228 @@ DSACK1.OE VMA.OE CIIN.OE G_105 G_106 G_107 G_91 0 1 .names N_32_0.BLIF inst_DS_000_DMA.D 0 1 -.names N_167_i.BLIF N_168_i.BLIF inst_DSACK1_INT.D -11 1 -.names N_169_i.BLIF N_170_i.BLIF inst_AS_000_INT.D -11 1 -.names N_35_0.BLIF inst_AMIGA_DS.D -0 1 -.names N_36_0.BLIF inst_A0_DMA.D -0 1 -.names N_126.BLIF inst_RW_000_DMA.D -0 1 -.names N_38_0.BLIF inst_AS_030_D0.D -0 1 -.names N_150.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 -.names as_030_d1_0_un1_n.BLIF as_030_d1_0_un0_n.BLIF inst_AS_030_D1.D -1- 1 --1 1 -.names N_24_0.BLIF inst_UDS_000_INT.D -0 1 -.names N_220_i.BLIF inst_BGACK_030_INT_D.D +.names N_39_1_i.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names N_20_i.BLIF RST_c.BLIF N_23_0 -11 1 -.names N_19.BLIF N_19_i +.names N_157.BLIF N_157_i 0 1 -.names N_19_i.BLIF RST_c.BLIF N_22_0 +.names N_83.BLIF N_157_i.BLIF cpu_est_2_0_3__n 11 1 -.names N_18.BLIF N_18_i +.names N_156.BLIF N_156_i 0 1 -.names N_18_i.BLIF RST_c.BLIF N_21_0 -11 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n +.names N_229.BLIF N_229_i 0 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_43_0 +.names N_156_i.BLIF N_229_i.BLIF cpu_est_2_0_2__n 11 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n +.names N_126.BLIF N_126_i 0 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_42_0 +.names N_150.BLIF N_150_i +0 1 +.names N_126_i.BLIF N_150_i.BLIF pos_clk_un9_clk_000_pe_0_n 11 1 +.names N_20.BLIF N_20_i +0 1 .names vcc_n_n 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 +.names N_20_i.BLIF RST_c.BLIF N_23_0 +11 1 .names un5_e_0.BLIF un5_e 0 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_41_0 -11 1 -.names gnd_n_n -.names DTACK_c.BLIF DTACK_c_i +.names N_19.BLIF N_19_i 0 1 +.names gnd_n_n +.names N_19_i.BLIF RST_c.BLIF N_22_0 +11 1 .names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ un1_amiga_bus_enable_low 11 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_45_0 -11 1 +.names N_18.BLIF N_18_i +0 1 .names AS_000_DMA_i.BLIF AS_000_i.BLIF un3_as_030 11 1 -.names VPA_c.BLIF VPA_c_i -0 1 +.names N_18_i.BLIF RST_c.BLIF N_21_0 +11 1 .names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT 0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_44_0 -11 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n +0 1 .names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT 0 1 -.names N_13.BLIF N_13_i -0 1 +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_43_0 +11 1 .names un1_DS_000_ENABLE_0_sqmuxa_0.BLIF un1_DS_000_ENABLE_0_sqmuxa 0 1 +.names ipl_c_1__n.BLIF ipl_c_i_1__n +0 1 +.names un21_fpu_cs_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs +11 1 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_42_0 +11 1 +.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr +11 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names un8_ciin_1.BLIF un8_ciin_2.BLIF un8_ciin +11 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_41_0 +11 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un2_ds_030 +11 1 +.names N_13.BLIF N_13_i +0 1 .names N_13_i.BLIF RST_c.BLIF N_27_0 11 1 -.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin -11 1 .names inst_LDS_000_INT.BLIF LDS_000_INT_i 0 1 -.names un21_fpu_cs_1.BLIF N_282_0.BLIF un21_fpu_cs -11 1 .names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 11 1 -.names un21_berr_1_0.BLIF N_282_0.BLIF un21_berr -11 1 .names inst_UDS_000_INT.BLIF UDS_000_INT_i 0 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un2_ds_030 -11 1 .names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 11 1 -.names AS_030_000_SYNC_i.BLIF CLK_000_D_4_.BLIF N_96_0_1 +.names inst_BGACK_030_INT_D.BLIF AS_030_D1_i.BLIF N_104_0_1 11 1 -.names clk_000_d_i_3__n.BLIF nEXP_SPACE_c.BLIF N_96_0_2 +.names inst_BGACK_030_INTreg.BLIF N_85_0.BLIF N_104_0_2 11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_282_0_1 +.names N_85_0.BLIF CLK_000_D_4_.BLIF N_100_0_1 11 1 -.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_282_0_2 +.names AS_030_000_SYNC_i.BLIF clk_000_d_i_3__n.BLIF N_100_0_2 11 1 -.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_282_0_3 +.names N_192_i.BLIF RST_c.BLIF N_113_i_1 11 1 -.names N_282_0_1.BLIF N_282_0_2.BLIF N_282_0_4 +.names N_79.BLIF N_193_i.BLIF N_113_i_2 +11 1 +.names N_99.BLIF N_79_i.BLIF N_107_0_1 +11 1 +.names BERR_c.BLIF N_202_i.BLIF N_99_i_1 11 1 .names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n 11 1 -.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 +.names N_82_i.BLIF N_83_i.BLIF N_202_1 11 1 -.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_202_2 11 1 -.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 +.names AS_030_i.BLIF a_decode_c_17__n.BLIF N_228_1 11 1 -.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 +.names a_decode_i_16__n.BLIF a_decode_i_18__n.BLIF N_228_2 11 1 -.names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 +.names fc_c_1__n.BLIF a_decode_i_19__n.BLIF N_228_3 11 1 -.names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 +.names N_228_1.BLIF N_228_2.BLIF N_228_4 11 1 -.names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 +.names N_228_3.BLIF fc_c_0__n.BLIF N_228_5 11 1 -.names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 +.names N_79_i.BLIF N_229.BLIF N_150_1 11 1 -.names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_150_2 11 1 -.names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 +.names N_80_i.BLIF N_82_i.BLIF N_126_1 11 1 -.names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 -11 1 -.names N_80_i.BLIF N_82_i.BLIF N_201_1 -11 1 -.names VMA_INT_i.BLIF VPA_D_i.BLIF N_201_2 -11 1 -.names BERR_c.BLIF N_201_i.BLIF N_131_i_1 -11 1 -.names N_68_i.BLIF N_131.BLIF N_134_0_1 -11 1 -.names N_68.BLIF N_141_i.BLIF N_113_i_1 -11 1 -.names N_142_i.BLIF RST_c.BLIF N_113_i_2 -11 1 -.names N_68_i.BLIF N_208.BLIF N_144_1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_126_2 11 1 .names pos_clk_ipl_1_n.BLIF N_188_i.BLIF pos_clk_ipl_n 11 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_144_2 +.names AS_030_D0_i.BLIF a_decode_c_20__n.BLIF un8_ciin_1 11 1 -.names N_72_i.BLIF N_82_i.BLIF N_143_1 +.names a_decode_c_21__n.BLIF N_201_1.BLIF un8_ciin_2 11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_143_2 +.names a_decode_c_22__n.BLIF a_decode_c_23__n.BLIF N_201_1_1 11 1 -.names AS_030_D1_i.BLIF inst_BGACK_030_INT_D.BLIF N_163_1 +.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF N_201_1_2 11 1 -.names N_282.BLIF sm_amiga_i_i_7__n.BLIF N_163_2 +.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF N_201_1_3 11 1 -.names N_163_1.BLIF N_163_2.BLIF N_163_3 +.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF N_201_1_4 11 1 -.names un21_berr_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1 +.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF N_201_1_5 11 1 -.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr_1_0 +.names N_201_1_1.BLIF N_201_1_2.BLIF N_201_1_6 11 1 -.names AS_000_i.BLIF N_220_i.BLIF pos_clk_cycle_dma_5_1_1__n +.names N_201_1_3.BLIF N_201_1_4.BLIF N_201_1_7 11 1 -.names N_68_i.BLIF CYCLE_DMA_0_.BLIF N_199_1 +.names N_201_1_6.BLIF N_201_1_7.BLIF N_201_1_8 +11 1 +.names a_decode_c_19__n.BLIF a_decode_c_21__n.BLIF N_201_1_0 +11 1 +.names a_decode_i_20__n.BLIF N_201_1.BLIF N_201_2 +11 1 +.names AS_000_i.BLIF N_39_1_i.BLIF pos_clk_cycle_dma_5_1_1__n +11 1 +.names N_79_i.BLIF CYCLE_DMA_0_.BLIF N_176_1 11 1 .names CLK_EXP_i.BLIF inst_CLK_OUT_PRE_D.BLIF AS_000_DMA_1_sqmuxa_1 11 1 -.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF N_140_1 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF N_198_1 11 1 -.names AS_000_i.BLIF N_198_i.BLIF N_66_i_1 +.names AMIGA_DS_i.BLIF AS_000_i.BLIF N_72_i_1 11 1 -.names N_199_i.BLIF N_220_i.BLIF N_66_i_2 -11 1 -.names AMIGA_DS_i.BLIF AS_000_i.BLIF N_205_i_1 -11 1 -.names N_140_i.BLIF pos_clk_un2_n.BLIF N_205_i_2 -11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_180_1 -11 1 -.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_180_2 +.names N_198_i.BLIF pos_clk_un2_n.BLIF N_72_i_2 11 1 .names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n 0 1 -.names inst_AS_030_D0.BLIF CLK_000_D_0_.BLIF N_59_i_1 +.names AS_000_i.BLIF N_39_1_i.BLIF N_206_i_1 11 1 -.names N_267_i.BLIF N_268_i.BLIF N_127_i_1 +.names N_175_i.BLIF N_176_i.BLIF N_206_i_2 11 1 -.names N_93.BLIF N_266_i.BLIF N_123_i_1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_186_1 11 1 -.names N_68.BLIF N_186_i.BLIF N_121_i_1 +.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_186_2 11 1 -.names N_72.BLIF N_185_i.BLIF N_119_i_1 +.names inst_AS_030_D0.BLIF CLK_000_D_0_.BLIF N_74_i_1 11 1 .names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6 1- 1 -1 1 -.names N_183_i.BLIF N_184_i.BLIF N_117_i_1 +.names N_79.BLIF N_197_i.BLIF N_121_i_1 11 1 -.names N_72.BLIF N_182_i.BLIF N_115_i_1 +.names N_195_i.BLIF N_196_i.BLIF N_117_i_1 11 1 -.names N_72.BLIF N_181_i.BLIF N_111_i_1 +.names N_80.BLIF N_194_i.BLIF N_115_i_1 11 1 -.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_165_1 +.names N_190_i.BLIF N_191_i.BLIF N_127_i_1 11 1 .names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_13 1- 1 -1 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_162_1 +.names N_84.BLIF N_214_i.BLIF N_123_i_1 11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_148_1 +.names N_80.BLIF N_159_i.BLIF N_119_i_1 11 1 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_18 1- 1 -1 1 -.names N_189_i.BLIF N_187_i.BLIF pos_clk_ipl_1_n +.names N_80.BLIF N_158_i.BLIF N_111_i_1 11 1 .names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_19 1- 1 -1 1 -.names AS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n -0 1 +.names N_228.BLIF BGACK_000_c.BLIF un21_berr_1 +11 1 .names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_20 1- 1 -1 1 +.names N_228.BLIF BGACK_000_c.BLIF un21_fpu_cs_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_172_1 +11 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_161_1 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_153_1 +11 1 +.names N_189_i.BLIF N_187_i.BLIF pos_clk_ipl_1_n +11 1 +.names AS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n +0 1 .names inst_DS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n 11 1 -.names N_205.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +.names N_72.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n 11 1 .names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n 0 1 .names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n 11 1 -.names N_205.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +.names N_72.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n 11 1 .names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n 0 1 @@ -652,12 +667,6 @@ un1_amiga_bus_enable_low 11 1 .names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n 11 1 -.names RST_c.BLIF as_030_d1_0_un3_n -0 1 -.names inst_AS_030_D0.BLIF RST_c.BLIF as_030_d1_0_un1_n -11 1 -.names inst_AS_030_D1.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un0_n -11 1 .names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n 0 1 .names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ @@ -665,581 +674,586 @@ rw_000_int_0_un1_n 11 1 .names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 -.names N_244.BLIF as_030_000_sync_0_un3_n -0 1 -.names AS_030_c.BLIF N_244.BLIF as_030_000_sync_0_un1_n -11 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 .names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 .names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n -0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 .names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n 0 1 -.names N_68.BLIF cpu_est_0_1__un3_n +.names N_204.BLIF as_030_000_sync_0_un3_n 0 1 .names cpu_est_2_0_3__n.BLIF cpu_est_2_3__n 0 1 -.names cpu_est_1_.BLIF N_68.BLIF cpu_est_0_1__un1_n +.names inst_AS_030_000_SYNC.BLIF N_204.BLIF as_030_000_sync_0_un1_n +11 1 +.names AS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names N_79.BLIF cpu_est_0_1__un3_n +0 1 +.names cpu_est_1_.BLIF N_79.BLIF cpu_est_0_1__un1_n 11 1 .names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 -.names N_68.BLIF cpu_est_0_2__un3_n +.names N_205_0.BLIF N_205 0 1 -.names cpu_est_2_.BLIF N_68.BLIF cpu_est_0_2__un1_n +.names N_79.BLIF cpu_est_0_2__un3_n +0 1 +.names N_74_i.BLIF N_74 +0 1 +.names cpu_est_2_.BLIF N_79.BLIF cpu_est_0_2__un1_n 11 1 -.names N_60_0.BLIF N_60 +.names N_78_0.BLIF N_78 0 1 .names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n 11 1 -.names N_63_0.BLIF N_63 +.names N_79_i.BLIF N_79 0 1 -.names N_68.BLIF cpu_est_0_3__un3_n -0 1 -.names N_220_i.BLIF RW_000_i.BLIF N_126 -11 1 -.names cpu_est_3_.BLIF N_68.BLIF cpu_est_0_3__un1_n -11 1 -.names a_c_1__n.BLIF N_220_i.BLIF N_150 -11 1 -.names cpu_est_2_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names a_i_1__n.BLIF N_220_i.BLIF N_151 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_219 -11 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n -11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF N_175 -11 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n -0 1 -.names N_59_i.BLIF N_59 -0 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n -11 1 -.names N_68_i.BLIF N_68 -0 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names N_72_i.BLIF N_72 -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +.names N_79.BLIF cpu_est_0_3__un3_n 0 1 .names N_80_i.BLIF N_80 0 1 +.names cpu_est_3_.BLIF N_79.BLIF cpu_est_0_3__un1_n +11 1 +.names N_83_i.BLIF N_83 +0 1 +.names cpu_est_2_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names N_84_i.BLIF N_84 +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names N_89_i.BLIF N_89 +0 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names N_95_i.BLIF N_95 +0 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names N_96_i.BLIF N_96 +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names N_97_i.BLIF N_97 +0 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names N_105_0.BLIF N_105 +0 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names N_126_1.BLIF N_126_2.BLIF N_126 +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names N_150_1.BLIF N_150_2.BLIF N_150 +11 1 .names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n 11 1 -.names N_93_i.BLIF N_93 -0 1 +.names N_153_1.BLIF cpu_est_i_3__n.BLIF N_153 +11 1 .names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 -.names N_98_i.BLIF N_98 -0 1 -.names N_63.BLIF ds_000_enable_0_un3_n -0 1 -.names N_107_i.BLIF N_107 -0 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_63.BLIF ds_000_enable_0_un1_n +.names N_89.BLIF cpu_est_2_.BLIF N_156 11 1 -.names N_128_i.BLIF N_128 +.names N_78.BLIF ds_000_enable_0_un3_n 0 1 +.names N_89_i.BLIF cpu_est_2_.BLIF N_157 +11 1 +.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_78.BLIF ds_000_enable_0_un1_n +11 1 +.names N_97.BLIF sm_amiga_i_0__n.BLIF N_158 +11 1 .names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF \ ds_000_enable_0_un0_n 11 1 -.names N_131_i.BLIF N_131 -0 1 -.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n -0 1 -.names N_134_0.BLIF N_134 -0 1 -.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n -11 1 -.names N_135_0.BLIF N_135 -0 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names N_72.BLIF SM_AMIGA_2_.BLIF N_141 +.names N_105.BLIF sm_amiga_i_4__n.BLIF N_159 11 1 .names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c 0 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_142 -11 1 -.names N_143_1.BLIF N_143_2.BLIF N_143 -11 1 -.names N_144_1.BLIF N_144_2.BLIF N_144 -11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_145 -11 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF N_146 -11 1 -.names N_205_i_1.BLIF N_205_i_2.BLIF N_205_i -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_147 -11 1 -.names N_140.BLIF N_140_i +.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n 0 1 -.names N_148_1.BLIF cpu_est_i_3__n.BLIF N_148 +.names N_82_i.BLIF cpu_est_3_.BLIF N_160 11 1 -.names inst_AMIGA_DS.BLIF AMIGA_DS_i +.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names N_161_1.BLIF cpu_est_i_3__n.BLIF N_161 +11 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names N_172_1.BLIF AS_030_i.BLIF N_172 +11 1 +.names RST_c.BLIF as_030_d1_0_un3_n 0 1 -.names N_98.BLIF cpu_est_2_.BLIF N_149 +.names N_225.BLIF RST_c.BLIF N_177 11 1 -.names N_98_i.BLIF cpu_est_2_.BLIF N_154 +.names inst_AS_030_D0.BLIF RST_c.BLIF as_030_d1_0_un1_n 11 1 -.names N_199.BLIF N_199_i +.names N_97_i.BLIF RST_c.BLIF N_178 +11 1 +.names N_181.BLIF N_181_i 0 1 -.names N_82_i.BLIF cpu_est_3_.BLIF N_155 +.names inst_AS_030_D1.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un0_n +11 1 +.names N_224.BLIF RST_c.BLIF N_179 +11 1 +.names N_181_i.BLIF RST_c.BLIF N_37_0 +11 1 +.names N_84_i.BLIF RST_c.BLIF N_180 +11 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF N_182 +11 1 +.names N_176.BLIF N_176_i +0 1 +.names BGACK_030_INT_i.BLIF N_96.BLIF N_183 +11 1 +.names N_175.BLIF N_175_i +0 1 +.names BGACK_030_INT_i.BLIF N_96_i.BLIF N_184 +11 1 +.names N_72_i_1.BLIF N_72_i_2.BLIF N_72_i +11 1 +.names N_39_1_i.BLIF RW_000_i.BLIF N_212 11 1 .names N_198.BLIF N_198_i 0 1 -.names N_162_1.BLIF cpu_est_i_3__n.BLIF N_162 +.names N_39_1_i.BLIF N_81.BLIF N_213 11 1 -.names N_180.BLIF N_180_i +.names inst_AMIGA_DS.BLIF AMIGA_DS_i 0 1 -.names N_165_1.BLIF AS_030_i.BLIF N_165 +.names N_100.BLIF sm_amiga_i_6__n.BLIF N_214 11 1 -.names N_262.BLIF N_262_i +.names N_186.BLIF N_186_i 0 1 -.names BGACK_030_INT_i.BLIF N_128.BLIF N_259 +.names N_100.BLIF sm_amiga_i_i_7__n.BLIF N_190 11 1 -.names N_180_i.BLIF N_262_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +.names N_185.BLIF N_185_i +0 1 +.names N_80_i.BLIF SM_AMIGA_0_.BLIF N_191 11 1 -.names BGACK_030_INT_i.BLIF N_128_i.BLIF N_260 +.names N_185_i.BLIF N_186_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names N_107.BLIF sm_amiga_i_2__n.BLIF N_194 11 1 .names cycle_dma_i_0__n.BLIF cycle_dma_i_1__n.BLIF pos_clk_un2_i_n 11 1 -.names N_129.BLIF sm_amiga_i_0__n.BLIF N_181 +.names N_79_i.BLIF N_99.BLIF N_195 11 1 .names N_3.BLIF N_3_i 0 1 -.names N_134.BLIF sm_amiga_i_2__n.BLIF N_182 +.names N_95.BLIF sm_amiga_i_3__n.BLIF N_196 11 1 .names N_3_i.BLIF RST_c.BLIF N_32_0 11 1 -.names N_68_i.BLIF N_131.BLIF N_183 +.names N_84.BLIF sm_amiga_i_5__n.BLIF N_197 11 1 .names N_4.BLIF N_4_i 0 1 -.names N_107.BLIF sm_amiga_i_3__n.BLIF N_184 +.names N_202_1.BLIF N_202_2.BLIF N_202 11 1 .names N_4_i.BLIF RST_c.BLIF N_31_0 11 1 -.names N_135.BLIF sm_amiga_i_4__n.BLIF N_185 +.names N_84_i.BLIF RW_c.BLIF N_220 11 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_220_i +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_39_1_i 11 1 -.names N_93.BLIF sm_amiga_i_5__n.BLIF N_186 +.names AS_000_INT_i.BLIF AS_030_i.BLIF N_224 +11 1 +.names N_39_1_i.BLIF N_81_i.BLIF N_34_0 +11 1 +.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_225 11 1 .names BG_030_c.BLIF BG_030_c_i 0 1 -.names N_132.BLIF sm_amiga_i_6__n.BLIF N_266 +.names N_228_4.BLIF N_228_5.BLIF N_228 11 1 -.names BG_030_c_i.BLIF N_59.BLIF pos_clk_un9_bg_030_0_n +.names BG_030_c_i.BLIF N_74.BLIF pos_clk_un9_bg_030_0_n 11 1 -.names N_96.BLIF sm_amiga_i_i_7__n.BLIF N_267 +.names N_89_i.BLIF cpu_est_i_2__n.BLIF N_229 11 1 .names N_17.BLIF N_17_i 0 1 -.names N_72_i.BLIF SM_AMIGA_0_.BLIF N_268 +.names N_201_1_8.BLIF N_201_1_5.BLIF N_201_1 11 1 .names N_17_i.BLIF RST_c.BLIF N_24_0 11 1 -.names N_68.BLIF cpu_est_i_0__n.BLIF N_190 -11 1 +.names N_104_0.BLIF N_104 +0 1 .names N_16.BLIF N_16_i 0 1 -.names N_68_i.BLIF cpu_est_0_.BLIF N_191 -11 1 +.names N_100_0.BLIF N_100 +0 1 .names N_16_i.BLIF RST_c.BLIF N_25_0 11 1 -.names N_201_1.BLIF N_201_2.BLIF N_201 +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_171 11 1 .names N_15.BLIF N_15_i 0 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_202 -11 1 +.names N_204_0.BLIF N_204 +0 1 .names N_15_i.BLIF RST_c.BLIF N_26_0 11 1 -.names N_93_i.BLIF RW_c.BLIF N_203 +.names AS_030_i.BLIF N_104.BLIF N_164 11 1 .names N_12.BLIF N_12_i 0 1 -.names N_98_i.BLIF cpu_est_i_2__n.BLIF N_208 +.names N_79.BLIF cpu_est_i_0__n.BLIF N_162 11 1 .names N_12_i.BLIF RST_c.BLIF N_28_0 11 1 -.names N_163_3.BLIF un1_dsack1_i.BLIF N_163 -11 1 -.names N_11.BLIF N_11_i -0 1 -.names N_282_0.BLIF N_282 -0 1 -.names N_11_i.BLIF RST_c.BLIF N_29_0 -11 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 +.names N_79_i.BLIF cpu_est_0_.BLIF N_163 11 1 .names N_5.BLIF N_5_i 0 1 -.names N_132_0.BLIF N_132 +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n 0 1 .names N_5_i.BLIF RST_c.BLIF N_30_0 11 1 -.names N_96_0.BLIF N_96 -0 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_152 +11 1 .names a_c_0__n.BLIF a_c_i_0__n 0 1 -.names N_129_i.BLIF N_129 -0 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 -0 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ -pos_clk_un10_sm_amiga_i_n -11 1 -.names N_175.BLIF RST_c.BLIF N_169 -11 1 -.names inst_BGACK_030_INTreg.BLIF nEXP_SPACE_c.BLIF un1_dsack1_i -11 1 -.names N_93_i.BLIF RST_c.BLIF N_170 -11 1 -.names inst_BGACK_030_INTreg.BLIF RST_c.BLIF N_69_i -11 1 -.names N_219.BLIF RST_c.BLIF N_167 -11 1 -.names N_163.BLIF N_163_i -0 1 -.names N_129_i.BLIF RST_c.BLIF N_168 -11 1 -.names AS_030_i.BLIF N_163_i.BLIF N_244_0 -11 1 -.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n -0 1 -.names N_164.BLIF N_164_i -0 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n -0 1 -.names N_165.BLIF N_165_i -0 1 -.names AS_000_c.BLIF N_68_i.BLIF N_274 -11 1 -.names N_164_i.BLIF N_165_i.BLIF un11_amiga_bus_enable_high_i -11 1 -.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_164 -11 1 -.names un10_ciin.BLIF un10_ciin_i -0 1 -.names N_244_0.BLIF N_244 -0 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_60_0 -11 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_5 -1- 1 --1 1 -.names N_274.BLIF N_274_i -0 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_11 1- 1 -1 1 -.names BGACK_000_c.BLIF N_274_i.BLIF pos_clk_un6_bgack_000_0_n +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names N_201_1_0.BLIF N_201_2.BLIF N_201 11 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ +pos_clk_un10_sm_amiga_i_n +11 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_193 +11 1 +.names N_231.BLIF N_231_i +0 1 +.names N_80.BLIF SM_AMIGA_2_.BLIF N_192 +11 1 +.names BGACK_000_c.BLIF N_231_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names N_107_0.BLIF N_107 +0 1 +.names AS_030_i.BLIF RST_c.BLIF N_40_0 +11 1 +.names N_99_i.BLIF N_99 +0 1 +.names N_84.BLIF N_98_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +11 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_219 +11 1 +.names RW_c.BLIF RW_c_i +0 1 +.names N_81_i.BLIF N_81 +0 1 +.names N_98_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n +11 1 +.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n +0 1 +.names N_201.BLIF N_201_i +0 1 +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names a_c_1__n.BLIF N_201_i.BLIF N_81_i +11 1 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +0 1 +.names N_219.BLIF N_219_i +0 1 +.names AS_000_c.BLIF N_79_i.BLIF N_231 +11 1 +.names N_202.BLIF N_202_i +0 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_5 +1- 1 +-1 1 +.names N_191.BLIF N_191_i +0 1 .names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_12 1- 1 -1 1 -.names RW_c.BLIF RW_c_i -0 1 +.names N_191_i.BLIF SM_AMIGA_i_7_.BLIF N_98_i +11 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_15 1- 1 -1 1 -.names N_246_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n +.names N_99_i_1.BLIF N_219_i.BLIF N_99_i 11 1 .names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_16 1- 1 -1 1 -.names N_168.BLIF N_168_i -0 1 +.names N_107_0_1.BLIF SM_AMIGA_3_.BLIF N_107_0 +11 1 .names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_17 1- 1 -1 1 -.names N_167.BLIF N_167_i +.names N_192.BLIF N_192_i 0 1 .names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n 0 1 -.names N_170.BLIF N_170_i +.names N_193.BLIF N_193_i 0 1 .names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 1- 1 -1 1 -.names N_169.BLIF N_169_i +.names N_72_i.BLIF N_72 0 1 -.names N_205_i.BLIF N_205 +.names N_11.BLIF N_11_i 0 1 -.names AS_000_DMA_1_sqmuxa_1.BLIF N_205_i.BLIF AS_000_DMA_1_sqmuxa +.names AS_000_DMA_1_sqmuxa_1.BLIF N_72_i.BLIF AS_000_DMA_1_sqmuxa 11 1 -.names AS_030_i.BLIF RST_c.BLIF N_38_0 +.names N_11_i.BLIF RST_c.BLIF N_29_0 11 1 .names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 1- 1 -1 1 -.names N_93.BLIF N_246_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +.names VPA_c.BLIF VPA_c_i +0 1 +.names RST_c.BLIF VPA_c_i.BLIF N_44_0 11 1 -.names N_199_1.BLIF cycle_dma_i_1__n.BLIF N_199 -11 1 -.names N_282_0_4.BLIF N_282_0_3.BLIF N_282_0 +.names N_176_1.BLIF cycle_dma_i_1__n.BLIF N_176 11 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 .names pos_clk_un2_i_n.BLIF pos_clk_un2_n 0 1 -.names CLK_000_D_3_.BLIF clk_000_d_i_3__n +.names DTACK_c_i.BLIF RST_c.BLIF N_45_0 +11 1 +.names cycle_dma_i_0__n.BLIF N_79.BLIF N_175 +11 1 +.names N_152.BLIF N_152_i 0 1 -.names N_140_1.BLIF RW_000_i.BLIF N_140 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_185 11 1 -.names N_96_0_1.BLIF N_96_0_2.BLIF N_96_0 -11 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_262 -11 1 -.names N_68_i.BLIF SM_AMIGA_1_.BLIF N_129_i -11 1 -.names cycle_dma_i_0__n.BLIF N_68.BLIF N_198 -11 1 -.names N_268.BLIF N_268_i +.names N_153.BLIF N_153_i 0 1 -.names N_180_1.BLIF N_180_2.BLIF N_180 +.names N_198_1.BLIF RW_000_i.BLIF N_198 11 1 -.names N_268_i.BLIF SM_AMIGA_i_7_.BLIF N_246_i +.names N_152_i.BLIF N_153_i.BLIF cpu_est_2_0_1__n 11 1 +.names N_186_1.BLIF N_186_2.BLIF N_186 +11 1 +.names N_163.BLIF N_163_i +0 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_181 +11 1 +.names N_162.BLIF N_162_i +0 1 .names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i 0 1 -.names N_96_0.BLIF sm_amiga_i_i_7__n.BLIF N_132_0 -11 1 .names un21_fpu_cs.BLIF un21_fpu_cs_i 0 1 +.names inst_BGACK_030_INTreg.BLIF RST_c.BLIF N_203_i +11 1 .names AS_000_c.BLIF AS_000_i 0 1 -.names N_142.BLIF N_142_i -0 1 +.names inst_BGACK_030_INTreg.BLIF nEXP_SPACE_c.BLIF un1_dsack1_i +11 1 .names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 -.names N_141.BLIF N_141_i +.names N_164.BLIF N_164_i 0 1 .names nEXP_SPACE_c.BLIF nEXP_SPACE_i 0 1 -.names N_68_i.BLIF SM_AMIGA_5_.BLIF N_135_0 +.names N_228.BLIF N_228_i +0 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names N_164_i.BLIF N_228_i.BLIF N_204_0 11 1 .names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n 0 1 -.names N_134_0_1.BLIF SM_AMIGA_3_.BLIF N_134_0 -11 1 -.names RW_000_c.BLIF RW_000_i +.names N_171.BLIF N_171_i 0 1 -.names N_131_i_1.BLIF N_202_i.BLIF N_131_i -11 1 .names CLK_OUT_INTreg.BLIF CLK_EXP_i 0 1 -.names LDS_000_c.BLIF LDS_000_c_i +.names N_172.BLIF N_172_i 0 1 .names CYCLE_DMA_1_.BLIF cycle_dma_i_1__n 0 1 -.names UDS_000_c.BLIF UDS_000_c_i -0 1 +.names N_171_i.BLIF N_172_i.BLIF un11_amiga_bus_enable_high_i +11 1 .names inst_DS_000_DMA.BLIF DS_000_DMA_i 0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_128_i +.names sm_amiga_i_i_7__n.BLIF nEXP_SPACE_c.BLIF N_85_0 11 1 .names inst_AS_000_DMA.BLIF AS_000_DMA_i 0 1 -.names N_72_i.BLIF SM_AMIGA_4_.BLIF N_107_i -11 1 -.names a_c_1__n.BLIF a_i_1__n -0 1 -.names N_203.BLIF N_203_i -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names N_107.BLIF N_203_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0 -11 1 -.names a_decode_c_19__n.BLIF a_decode_i_19__n -0 1 -.names N_201.BLIF N_201_i -0 1 -.names a_decode_c_18__n.BLIF a_decode_i_18__n -0 1 -.names N_202.BLIF N_202_i -0 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i -0 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_98_i -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names N_72_i.BLIF SM_AMIGA_6_.BLIF N_93_i -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_82_i -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_80_i -11 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_72_i -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_68_i -11 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names N_59_i_1.BLIF nEXP_SPACE_c.BLIF N_59_i -11 1 -.names inst_DSACK1_INT.BLIF DSACK1_INT_i -0 1 -.names N_190.BLIF N_190_i -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names N_191.BLIF N_191_i -0 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names inst_AS_030_D1.BLIF AS_030_D1_i -0 1 -.names N_267.BLIF N_267_i -0 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names N_266.BLIF N_266_i -0 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_186.BLIF N_186_i -0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names N_185.BLIF N_185_i -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names N_183.BLIF N_183_i -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names N_184.BLIF N_184_i -0 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names N_182.BLIF N_182_i -0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names N_181.BLIF N_181_i -0 1 -.names ahigh_c_30__n.BLIF ahigh_i_30__n -0 1 -.names ahigh_c_31__n.BLIF ahigh_i_31__n -0 1 -.names N_260.BLIF N_260_i -0 1 -.names ahigh_c_28__n.BLIF ahigh_i_28__n -0 1 -.names N_260_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n -11 1 -.names ahigh_c_29__n.BLIF ahigh_i_29__n -0 1 -.names N_259.BLIF N_259_i -0 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n -0 1 -.names N_259_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n -11 1 -.names ahigh_c_27__n.BLIF ahigh_i_27__n -0 1 -.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF N_63_0 -11 1 -.names ahigh_c_24__n.BLIF ahigh_i_24__n -0 1 -.names N_155.BLIF N_155_i +.names CLK_000_D_3_.BLIF clk_000_d_i_3__n 0 1 .names ahigh_c_25__n.BLIF ahigh_i_25__n 0 1 -.names N_162.BLIF N_162_i +.names N_100_0_1.BLIF N_100_0_2.BLIF N_100_0 +11 1 +.names ahigh_c_24__n.BLIF ahigh_i_24__n +0 1 +.names inst_AS_030_D1.BLIF AS_030_D1_i +0 1 +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 +.names N_104_0_1.BLIF N_104_0_2.BLIF N_104_0 +11 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names N_79_i.BLIF SM_AMIGA_5_.BLIF N_105_0 +11 1 +.names ahigh_c_29__n.BLIF ahigh_i_29__n +0 1 +.names N_79_i.BLIF SM_AMIGA_1_.BLIF N_97_i +11 1 +.names ahigh_c_28__n.BLIF ahigh_i_28__n +0 1 +.names LDS_000_c.BLIF LDS_000_c_i +0 1 +.names ahigh_c_31__n.BLIF ahigh_i_31__n +0 1 +.names UDS_000_c.BLIF UDS_000_c_i +0 1 +.names ahigh_c_30__n.BLIF ahigh_i_30__n +0 1 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_96_i +11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names N_80_i.BLIF SM_AMIGA_4_.BLIF N_95_i +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_220.BLIF N_220_i +0 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names N_95.BLIF N_220_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0 +11 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_89_i +11 1 +.names a_decode_c_20__n.BLIF a_decode_i_20__n +0 1 +.names N_80_i.BLIF SM_AMIGA_6_.BLIF N_84_i +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_83_i +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_82_i +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_80_i +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_79_i +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF N_78_0 +11 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names N_74_i_1.BLIF nEXP_SPACE_c.BLIF N_74_i +11 1 +.names cpu_est_3_.BLIF cpu_est_i_3__n +0 1 +.names N_197.BLIF N_197_i +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names N_195.BLIF N_195_i +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names N_196.BLIF N_196_i +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names N_194.BLIF N_194_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names N_190.BLIF N_190_i +0 1 +.names inst_DSACK1_INT.BLIF DSACK1_INT_i +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_214.BLIF N_214_i +0 1 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names a_decode_c_19__n.BLIF a_decode_i_19__n +0 1 +.names N_184.BLIF N_184_i +0 1 +.names a_decode_c_18__n.BLIF a_decode_i_18__n +0 1 +.names N_184_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names N_183.BLIF N_183_i +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names N_183_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names N_182.BLIF N_182_i 0 1 .names G_105.BLIF N_187_i 0 1 -.names N_155_i.BLIF N_162_i.BLIF un5_e_0 +.names N_182_i.BLIF RST_c.BLIF N_38_0 11 1 .names G_106.BLIF N_188_i 0 1 -.names N_154.BLIF N_154_i +.names N_179.BLIF N_179_i 0 1 .names G_107.BLIF N_189_i 0 1 -.names N_80.BLIF N_154_i.BLIF cpu_est_2_0_3__n -11 1 -.names N_149.BLIF N_149_i +.names N_180.BLIF N_180_i 0 1 -.names N_208.BLIF N_208_i +.names N_177.BLIF N_177_i 0 1 -.names N_149_i.BLIF N_208_i.BLIF cpu_est_2_0_2__n -11 1 -.names N_147.BLIF N_147_i +.names N_178.BLIF N_178_i 0 1 .names un2_ds_030.BLIF un2_ds_030_i 0 1 -.names N_148.BLIF N_148_i +.names N_225.BLIF N_225_i 0 1 -.names N_219.BLIF N_219_i +.names un8_ciin.BLIF un8_ciin_i 0 1 -.names N_147_i.BLIF N_148_i.BLIF cpu_est_2_0_1__n +.names N_224.BLIF N_224_i +0 1 +.names nEXP_SPACE_i.BLIF un8_ciin_i.BLIF N_205_0 11 1 -.names N_175.BLIF N_175_i -0 1 -.names N_146.BLIF N_146_i -0 1 .names un3_as_030.BLIF un3_as_030_i 0 1 -.names N_146_i.BLIF RST_c.BLIF N_36_0 -11 1 -.names N_145.BLIF N_145_i +.names N_160.BLIF N_160_i 0 1 -.names N_145_i.BLIF RST_c.BLIF N_35_0 -11 1 -.names N_143.BLIF N_143_i +.names N_161.BLIF N_161_i 0 1 -.names N_144.BLIF N_144_i -0 1 -.names N_143_i.BLIF N_144_i.BLIF pos_clk_un9_clk_000_pe_0_n +.names N_160_i.BLIF N_161_i.BLIF un5_e_0 11 1 -.names N_20.BLIF N_20_i +.names N_159.BLIF N_159_i +0 1 +.names N_158.BLIF N_158_i 0 1 .names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_105 01 1 @@ -1256,7 +1270,7 @@ pos_clk_un10_sm_amiga_i_n 10 1 11 0 00 0 -.names CYCLE_DMA_1_.BLIF N_199.BLIF G_91 +.names CYCLE_DMA_1_.BLIF N_176.BLIF G_91 01 1 10 1 11 0 @@ -1282,7 +1296,7 @@ pos_clk_un10_sm_amiga_i_n .names un21_fpu_cs_i.BLIF FPU_CS 1 1 0 0 -.names N_219_i.BLIF DSACK1 +.names N_225_i.BLIF DSACK1 1 1 0 0 .names vcc_n_n.BLIF AVEC @@ -1306,7 +1320,7 @@ pos_clk_un10_sm_amiga_i_n .names un11_amiga_bus_enable_high_i.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 0 0 -.names un10_ciin.BLIF CIIN +.names un8_ciin.BLIF CIIN 1 1 0 0 .names IPL_030DFF_1_reg.BLIF IPL_030_1_ @@ -1315,6 +1329,18 @@ pos_clk_un10_sm_amiga_i_n .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF IPL_D0_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -1330,6 +1356,15 @@ pos_clk_un10_sm_amiga_i_n .names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 0 0 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_3_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C 1 1 0 0 @@ -1345,16 +1380,10 @@ pos_clk_un10_sm_amiga_i_n .names CLK_OSZI_c.BLIF IPL_D0_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF IPL_D0_2_.C +.names CLK_000.BLIF CLK_000_D_0_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C 1 1 0 0 .names CLK_000_D_0_.BLIF CLK_000_D_1_.D @@ -1396,24 +1425,30 @@ pos_clk_un10_sm_amiga_i_n .names CLK_OSZI_c.BLIF cpu_est_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_3_.C -1 1 -0 0 -.names CLK_000.BLIF CLK_000_D_0_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_0_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AMIGA_DS.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_VPA_D.C 1 1 0 0 @@ -1423,6 +1458,12 @@ pos_clk_un10_sm_amiga_i_n .names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_D1.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +0 0 .names CLK_OSZI_c.BLIF BG_000DFFreg.C 1 1 0 0 @@ -1447,33 +1488,6 @@ pos_clk_un10_sm_amiga_i_n .names CLK_OSZI_c.BLIF inst_DS_000_DMA.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AMIGA_DS.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_A0_DMA.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_D0.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_D1.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 @@ -1501,7 +1515,7 @@ pos_clk_un10_sm_amiga_i_n .names un3_as_030_i.BLIF AS_030 1 1 0 0 -.names N_175_i.BLIF AS_000 +.names N_224_i.BLIF AS_000 1 1 0 0 .names inst_RW_000_INT.BLIF RW_000 @@ -1711,16 +1725,16 @@ pos_clk_un10_sm_amiga_i_n .names BGACK_030_INT_i.BLIF AS_030.OE 1 1 0 0 -.names N_69_i.BLIF AS_000.OE +.names N_203_i.BLIF AS_000.OE 1 1 0 0 -.names N_69_i.BLIF RW_000.OE +.names N_203_i.BLIF RW_000.OE 1 1 0 0 -.names N_69_i.BLIF UDS_000.OE +.names N_203_i.BLIF UDS_000.OE 1 1 0 0 -.names N_69_i.BLIF LDS_000.OE +.names N_203_i.BLIF LDS_000.OE 1 1 0 0 .names BGACK_030_INT_i.BLIF SIZE_0_.OE @@ -1771,7 +1785,7 @@ pos_clk_un10_sm_amiga_i_n .names inst_BGACK_030_INTreg.BLIF VMA.OE 1 1 0 0 -.names N_60.BLIF CIIN.OE +.names N_205.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index 4899251..3beb46c 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,13 +1,13 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Sat Dec 30 00:43:37 2017 +#$ DATE Thu Jan 11 20:16:29 2018 #$ MODULE 68030_tk -#$ PINS 59 AHIGH_27_ AHIGH_26_ SIZE_1_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ \ -# A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ \ -# IPL_030_2_ A_DECODE_16_ IPL_2_ FC_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 \ -# nEXP_SPACE BERR BG_030 BG_000 BGACK_030 A_0_ BGACK_000 IPL_030_1_ IPL_030_0_ CLK_000 \ -# IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ FPU_CS FPU_SENSE DSACK1 DTACK AVEC E \ -# VPA VMA RST RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -# AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ +#$ PINS 59 SIZE_1_ SIZE_0_ AHIGH_30_ AHIGH_31_ AHIGH_29_ AHIGH_28_ A_DECODE_23_ \ +# AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ IPL_030_2_ A_DECODE_22_ A_DECODE_21_ IPL_2_ \ +# A_DECODE_20_ A_DECODE_19_ FC_1_ A_DECODE_18_ AS_030 A_DECODE_17_ AS_000 A_DECODE_16_ \ +# RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_000 \ +# CLK_OSZI CLK_DIV_OUT CLK_EXP A_0_ FPU_CS IPL_030_1_ FPU_SENSE IPL_030_0_ DSACK1 IPL_1_ \ +# DTACK IPL_0_ AVEC FC_0_ E A_1_ VPA VMA RST RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR \ +# AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN #$ NODES 53 inst_BGACK_030_INTreg cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ \ # inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 \ # inst_AS_030_D1 inst_AS_030_000_SYNC inst_AS_000_DMA inst_DS_000_DMA \ @@ -18,7 +18,7 @@ # SM_AMIGA_6_ inst_RW_000_INT SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ \ # CYCLE_DMA_1_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ \ # BG_000DFFreg CLK_OUT_INTreg IPL_030DFF_0_reg IPL_030DFF_1_reg SM_AMIGA_i_7_ \ -# IPL_030DFF_2_reg N_60 +# IPL_030DFF_2_reg N_205 .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF DTACK.BLIF VPA.BLIF \ @@ -39,46 +39,72 @@ inst_RW_000_INT.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF \ CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_DSACK1_INT.BLIF inst_AS_000_INT.BLIF \ SM_AMIGA_5_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF BG_000DFFreg.BLIF \ CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_1_reg.BLIF \ -SM_AMIGA_i_7_.BLIF IPL_030DFF_2_reg.BLIF N_60.BLIF AS_030.PIN.BLIF \ +SM_AMIGA_i_7_.BLIF IPL_030DFF_2_reg.BLIF N_205.BLIF AS_030.PIN.BLIF \ AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF \ AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF \ AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ -SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ -SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \ -IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \ -IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_D0_2_.D IPL_D0_2_.C \ SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \ -CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D \ -CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C SIZE_DMA_0_.D SIZE_DMA_0_.C \ -SIZE_DMA_1_.D SIZE_DMA_1_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \ -CYCLE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ -cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C CLK_000_D_0_.D CLK_000_D_0_.C \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_VPA_D.D \ -inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_DS_000_ENABLE.D \ -inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C inst_LDS_000_INT.D \ -inst_LDS_000_INT.C inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_INT.D \ -inst_RW_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \ -inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DSACK1_INT.D \ -inst_DSACK1_INT.C inst_AS_000_INT.D inst_AS_000_INT.C inst_AMIGA_DS.D \ -inst_AMIGA_DS.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D \ -inst_RW_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \ +SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C \ +SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_1_.D \ +cpu_est_1_.C cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D \ +IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ +IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C \ +CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D \ +CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C \ +SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C CYCLE_DMA_0_.D \ +CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ +inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D inst_AS_000_INT.C \ +inst_AMIGA_DS.D inst_AMIGA_DS.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D \ +inst_RW_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C \ +inst_DTACK_D0.D inst_DTACK_D0.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C \ inst_AS_030_D1.D inst_AS_030_D1.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ -inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D \ -CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ +BG_000DFFreg.D BG_000DFFreg.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ +inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C \ +inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D \ +inst_DS_000_DMA.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \ +CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ AHIGH_31_ AS_030 AS_000 \ RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \ -AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_60 AS_030.OE AS_000.OE RW_000.OE \ +AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_205 AS_030.OE AS_000.OE RW_000.OE \ UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE \ AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE \ A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE VMA.OE CIIN.OE cpu_est_2_.D.X1 \ cpu_est_2_.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 SM_AMIGA_i_7_.D.X1 \ SM_AMIGA_i_7_.D.X2 +.names IPL_2_.BLIF RST.BLIF IPL_D0_2_.D +1- 1 +-0 1 +01 0 +.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_3_.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_D_4_.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_i_7_.BLIF SM_AMIGA_6_.D +1100--100 1 +-1---0-1- 1 +-1--1--1- 1 +----01-1- 0 +------00- 0 +---1---0- 0 +--1----0- 0 +0------0- 0 +-0------- 0 +-------01 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_5_.BLIF SM_AMIGA_5_.D +1011- 1 +1-1-1 1 +10--1 1 +-10-- 0 +0---- 0 +---00 0 +--0-0 0 +-1--0 0 .names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_4_.BLIF \ SM_AMIGA_5_.BLIF SM_AMIGA_4_.D 1-01- 1 @@ -129,6 +155,28 @@ SM_AMIGA_0_.BLIF SM_AMIGA_0_.D ---00 0 --1-0 0 -0--0 0 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_3_.BLIF CLK_000_D_1_.BLIF \ +CLK_000_D_0_.BLIF cpu_est_1_.D +10010 1 +01--- 1 +-1-0- 1 +-1--1 1 +-01-- 0 +11-10 0 +-0-0- 0 +00--- 0 +-0--1 0 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_3_.D +111-10 1 +0--1-- 1 +---10- 1 +---1-1 1 +1-0-10 0 +10--10 0 +---00- 0 +0--0-- 0 +---0-1 0 .names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D 0-01100- 1 @@ -206,33 +254,6 @@ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D 0- 1 -1 1 10 0 -.names IPL_2_.BLIF RST.BLIF IPL_D0_2_.D -1- 1 --0 1 -01 0 -.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_D_3_.BLIF \ -CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_D_4_.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_i_7_.BLIF SM_AMIGA_6_.D -1100--100 1 --1---0-1- 1 --1--1--1- 1 -----01-1- 0 -------00- 0 ----1---0- 0 ---1----0- 0 -0------0- 0 --0------- 0 --------01 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_5_.BLIF SM_AMIGA_5_.D -1011- 1 -1-1-1 1 -10--1 1 --10-- 0 -0---- 0 ----00 0 ---0-0 0 --1--0 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ SIZE_DMA_0_.D -01- 1 @@ -276,34 +297,91 @@ CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF CYCLE_DMA_1_.D 110 0 00- 0 0-1 0 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_3_.BLIF CLK_000_D_1_.BLIF \ -CLK_000_D_0_.BLIF cpu_est_1_.D -10010 1 -01--- 1 --1-0- 1 --1--1 1 --01-- 0 -11-10 0 --0-0- 0 -00--- 0 --0--1 0 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ -CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF cpu_est_3_.D -111-10 1 -0--1-- 1 ----10- 1 ----1-1 1 -1-0-10 0 -10--10 0 ----00- 0 -0--0-- 0 ----0-1 0 -.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \ +.names A_DECODE_23_.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \ +A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \ +AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF \ +AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +-------1-------- 1 +-0-------------- 1 +------1-------1- 1 +------1------1-- 1 +------1-----1--- 1 +------1----1---- 1 +------1---1----- 1 +------1--1------ 1 +------1-1------- 1 +-----01--------- 1 +----1-1--------- 1 +---0--1--------- 1 +--0---1--------- 1 +0-----1--------- 1 +------1--------1 1 +111101-000000000 0 +-1----00-------- 0 +.names A_DECODE_23_.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \ +A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \ +AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF \ +AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.D +1-1101--00000000 1 +-------1-------- 1 +------0--------- 1 +-0-------------- 1 +-1----10------1- 0 +-1----10-----1-- 0 +-1----10----1--- 0 +-1----10---1---- 0 +-1----10--1----- 0 +-1----10-1------ 0 +-1----101------- 0 +-1---010-------- 0 +-1--1-10-------- 0 +-1-0--10-------- 0 +-10---10-------- 0 +01----10-------- 0 +-1----10-------1 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF \ +inst_DSACK1_INT.BLIF AS_030.PIN.BLIF inst_DSACK1_INT.D +---01- 1 +--1-1- 1 +-0--1- 1 +0----- 1 +---0-1 1 +--1--1 1 +-0---1 1 +1101-- 0 +1---00 0 +.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ +inst_AS_000_INT.BLIF AS_030.PIN.BLIF inst_AS_000_INT.D +---01- 1 +--0-1- 1 +-1--1- 1 +0----- 1 +---0-1 1 +--0--1 1 +-1---1 1 +1011-- 0 +1---00 0 +.names RST.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_AMIGA_DS.D +0-- 1 +-11 1 +10- 0 +1-0 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D +0-- 1 +-01 1 +11- 0 +1-0 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D -1- 1 0-- 1 --1 1 100 0 +.names RST.BLIF AS_030.PIN.BLIF inst_AS_030_D0.D +0- 1 +-1 1 +10 0 .names VPA.BLIF RST.BLIF inst_VPA_D.D 1- 1 -0 1 @@ -327,6 +405,18 @@ inst_DS_000_ENABLE.D --00---- 0 -1-0---- 0 0------- 0 +.names RST.BLIF inst_AS_030_D0.BLIF inst_AS_030_D1.BLIF inst_AS_030_D1.D +11- 1 +0-1 1 +10- 0 +0-0 0 +.names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A_0_.PIN.BLIF \ +inst_UDS_000_INT.D +-10- 1 +0--- 1 +--11 1 +100- 0 +1-10 0 .names nEXP_SPACE.BLIF BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF \ CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D ----01 1 @@ -350,13 +440,13 @@ cpu_est_3_.BLIF inst_VMA_INTreg.BLIF inst_VPA_D.BLIF CLK_000_D_1_.BLIF \ CLK_000_D_0_.BLIF inst_VMA_INTreg.D -0000--01 1 -----11-- 1 ------1--1 1 ------1-0- 1 ---0--1--- 1 ----11--- 1 ---1-1--- 1 --0---1--- 1 0-------- 1 +-----1-0- 1 +--0--1--- 1 +-0---1--- 1 +-----1--1 1 11100-010 0 1---10--- 0 1--1-0--- 0 @@ -442,65 +532,6 @@ CLK_OUT_INTreg.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF inst_DS_000_DMA.D 1-0-1010- 0 1-0010-0- 0 100-10-0- 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_1_.BLIF \ -inst_DSACK1_INT.BLIF AS_030.PIN.BLIF inst_DSACK1_INT.D ----01- 1 ---1-1- 1 --0--1- 1 -0----- 1 ----0-1 1 ---1--1 1 --0---1 1 -1101-- 0 -1---00 0 -.names RST.BLIF CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_6_.BLIF \ -inst_AS_000_INT.BLIF AS_030.PIN.BLIF inst_AS_000_INT.D ----01- 1 ---0-1- 1 --1--1- 1 -0----- 1 ----0-1 1 ---0--1 1 --1---1 1 -1011-- 0 -1---00 0 -.names RST.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_AMIGA_DS.D -0-- 1 --11 1 -10- 0 -1-0 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D -0-- 1 --01 1 -11- 0 -1-0 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D --1- 1 -0-- 1 ---1 1 -100 0 -.names RST.BLIF AS_030.PIN.BLIF inst_AS_030_D0.D -0- 1 --1 1 -10 0 -.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.D --0- 1 -0-- 1 ---1 1 -110 0 -.names RST.BLIF inst_AS_030_D0.BLIF inst_AS_030_D1.BLIF inst_AS_030_D1.D -11- 1 -0-1 1 -10- 0 -0-0 0 -.names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A_0_.PIN.BLIF \ -inst_UDS_000_INT.D --10- 1 -0--- 1 ---11 1 -100- 0 -1-10 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D 0- 1 -1 1 @@ -511,7 +542,7 @@ inst_UDS_000_INT.D .names A_DECODE_23_.BLIF nEXP_SPACE.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \ A_DECODE_20_.BLIF inst_AS_030_D0.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF \ AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF \ -AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF N_60 +AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF N_205 1-111000000000 1 -1------------ 1 -0----------1- 0 @@ -620,6 +651,18 @@ AHIGH_31_.PIN.BLIF CIIN .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI.BLIF IPL_D0_2_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_5_.C +1 1 +0 0 .names CLK_OSZI.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -635,6 +678,15 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF SM_AMIGA_0_.C 1 1 0 0 +.names CLK_OSZI.BLIF cpu_est_1_.C +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_2_.C +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_3_.C +1 1 +0 0 .names CLK_OSZI.BLIF IPL_030DFF_0_reg.C 1 1 0 0 @@ -650,16 +702,10 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF IPL_D0_1_.C 1 1 0 0 -.names CLK_OSZI.BLIF IPL_D0_2_.C +.names CLK_000.BLIF CLK_000_D_0_.D 1 1 0 0 -.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C -1 1 -0 0 -.names CLK_OSZI.BLIF SM_AMIGA_6_.C -1 1 -0 0 -.names CLK_OSZI.BLIF SM_AMIGA_5_.C +.names CLK_OSZI.BLIF CLK_000_D_0_.C 1 1 0 0 .names CLK_000_D_0_.BLIF CLK_000_D_1_.D @@ -701,24 +747,30 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF cpu_est_0_.C 1 1 0 0 -.names CLK_OSZI.BLIF cpu_est_1_.C -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_2_.C -1 1 -0 0 -.names CLK_OSZI.BLIF cpu_est_3_.C -1 1 -0 0 -.names CLK_000.BLIF CLK_000_D_0_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_D_0_.C -1 1 -0 0 .names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C 1 1 0 0 +.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_DSACK1_INT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AS_000_INT.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AMIGA_DS.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_A0_DMA.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_RW_000_DMA.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AS_030_D0.C +1 1 +0 0 .names CLK_OSZI.BLIF inst_VPA_D.C 1 1 0 0 @@ -728,6 +780,12 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF inst_DS_000_ENABLE.C 1 1 0 0 +.names CLK_OSZI.BLIF inst_AS_030_D1.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_UDS_000_INT.C +1 1 +0 0 .names CLK_OSZI.BLIF BG_000DFFreg.C 1 1 0 0 @@ -752,33 +810,6 @@ AHIGH_31_.PIN.BLIF CIIN .names CLK_OSZI.BLIF inst_DS_000_DMA.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_DSACK1_INT.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AS_000_INT.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AMIGA_DS.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_A0_DMA.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_RW_000_DMA.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AS_030_D0.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AS_030_D1.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_UDS_000_INT.C -1 1 -0 0 .names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 @@ -924,7 +955,7 @@ AS_030.PIN.BLIF BERR.OE .names inst_BGACK_030_INTreg.BLIF VMA.OE 1 1 0 0 -.names N_60.BLIF CIIN.OE +.names N_205.BLIF CIIN.OE 1 1 0 0 .names cpu_est_2_.BLIF cpu_est_2_.D.X1 diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index 65c3b42..537cf0a 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 2.0.00.17.20.15 -// Design '68030_tk' created Sat Dec 30 00:43:37 2017 +// Design '68030_tk' created Thu Jan 11 20:16:29 2018 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index ad2f4c6..fd6c3cf 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,11 +2,19 @@ Copyright(C), 1992-2015, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Sat Dec 30 00:43:37 2017 +Design bus68030 created Thu Jan 11 20:16:29 2018 P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- + 0 0 1 Pin AHIGH_30_ + 1 1 1 Pin AHIGH_30_.OE + 0 0 1 Pin AHIGH_31_ + 1 1 1 Pin AHIGH_31_.OE + 0 0 1 Pin AHIGH_29_ + 1 1 1 Pin AHIGH_29_.OE + 0 0 1 Pin AHIGH_28_ + 1 1 1 Pin AHIGH_28_.OE 0 0 1 Pin AHIGH_27_ 1 1 1 Pin AHIGH_27_.OE 0 0 1 Pin AHIGH_26_ @@ -15,8 +23,6 @@ Design bus68030 created Sat Dec 30 00:43:37 2017 1 1 1 Pin AHIGH_25_.OE 0 0 1 Pin AHIGH_24_ 1 1 1 Pin AHIGH_24_.OE - 0 0 1 Pin AHIGH_31_ - 1 1 1 Pin AHIGH_31_.OE 1 2 1 Pin AS_030- 1 1 1 Pin AS_030.OE 1 2 1 Pin AS_000- @@ -42,15 +48,12 @@ Design bus68030 created Sat Dec 30 00:43:37 2017 2 4 1 Pin AMIGA_BUS_ENABLE_HIGH- 1 13 1 Pin CIIN 1 1 1 Pin CIIN.OE - 0 0 1 Pin AHIGH_30_ - 1 1 1 Pin AHIGH_30_.OE - 0 0 1 Pin AHIGH_29_ - 1 1 1 Pin AHIGH_29_.OE - 0 0 1 Pin AHIGH_28_ - 1 1 1 Pin AHIGH_28_.OE 1 1 1 Pin SIZE_1_.OE 2 4 1 Pin SIZE_1_.D 1 1 1 Pin SIZE_1_.C + 1 1 1 Pin SIZE_0_.OE + 2 4 1 Pin SIZE_0_.D- + 1 1 1 Pin SIZE_0_.C 10 8 1 Pin IPL_030_2_.D- 1 1 1 Pin IPL_030_2_.C 1 2 1 Pin RW_000.OE @@ -73,9 +76,6 @@ Design bus68030 created Sat Dec 30 00:43:37 2017 1 1 1 Pin RW.OE 1 3 1 Pin RW.D- 1 1 1 Pin RW.C - 1 1 1 Pin SIZE_0_.OE - 2 4 1 Pin SIZE_0_.D- - 1 1 1 Pin SIZE_0_.C 3 3 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C 4 5 1 Node cpu_est_1_.D @@ -85,9 +85,9 @@ Design bus68030 created Sat Dec 30 00:43:37 2017 1 1 1 Node cpu_est_2_.C 4 6 1 Node cpu_est_3_.D 1 1 1 Node cpu_est_3_.C - 1 3 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- + 2 16 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C - 1 3 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- + 4 16 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 2 1 Node inst_AS_030_D0.D- 1 1 1 Node inst_AS_030_D0.C @@ -160,9 +160,9 @@ Design bus68030 created Sat Dec 30 00:43:37 2017 3 9 1 NodeX1 SM_AMIGA_i_7_.T.X1 1 9 1 NodeX2 SM_AMIGA_i_7_.T.X2 1 1 1 Node SM_AMIGA_i_7_.C - 2 14 1 Node N_60 + 2 14 1 Node N_205 ========= - 243 P-Term Total: 243 + 247 P-Term Total: 247 Total Pins: 59 Total Nodes: 42 Average P-Term/Output: 2 @@ -170,6 +170,22 @@ Design bus68030 created Sat Dec 30 00:43:37 2017 Equations: +AHIGH_30_ = (0); + +AHIGH_30_.OE = (!BGACK_030.Q); + +AHIGH_31_ = (0); + +AHIGH_31_.OE = (!BGACK_030.Q); + +AHIGH_29_ = (0); + +AHIGH_29_.OE = (!BGACK_030.Q); + +AHIGH_28_ = (0); + +AHIGH_28_.OE = (!BGACK_030.Q); + AHIGH_27_ = (0); AHIGH_27_.OE = (!BGACK_030.Q); @@ -186,10 +202,6 @@ AHIGH_24_ = (0); AHIGH_24_.OE = (!BGACK_030.Q); -AHIGH_31_ = (0); - -AHIGH_31_.OE = (!BGACK_030.Q); - !AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN); AS_030.OE = (!BGACK_030.Q); @@ -241,19 +253,7 @@ AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); -CIIN.OE = (N_60); - -AHIGH_30_ = (0); - -AHIGH_30_.OE = (!BGACK_030.Q); - -AHIGH_29_ = (0); - -AHIGH_29_.OE = (!BGACK_030.Q); - -AHIGH_28_ = (0); - -AHIGH_28_.OE = (!BGACK_030.Q); +CIIN.OE = (N_205); SIZE_1_.OE = (!BGACK_030.Q); @@ -262,6 +262,13 @@ SIZE_1_.D = (!RST SIZE_1_.C = (CLK_OSZI); +SIZE_0_.OE = (!BGACK_030.Q); + +!SIZE_0_.D = (RST & BGACK_030.Q + # RST & !UDS_000.PIN & !LDS_000.PIN); + +SIZE_0_.C = (CLK_OSZI); + !IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q @@ -342,13 +349,6 @@ RW.OE = (!BGACK_030.Q); RW.C = (CLK_OSZI); -SIZE_0_.OE = (!BGACK_030.Q); - -!SIZE_0_.D = (RST & BGACK_030.Q - # RST & !UDS_000.PIN & !LDS_000.PIN); - -SIZE_0_.C = (CLK_OSZI); - cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q # cpu_est_0_.Q & CLK_000_D_0_.Q # !cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); @@ -375,11 +375,15 @@ cpu_est_3_.D = (!cpu_est_0_.Q & cpu_est_3_.Q cpu_est_3_.C = (CLK_OSZI); -!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q); +!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q + # A_DECODE_23_ & RST & A_DECODE_22_ & A_DECODE_21_ & !A_DECODE_20_ & A_DECODE_19_ & !BGACK_030.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); -!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q); +inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (!RST + # !A_1_ + # BGACK_030.Q + # A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & !A_DECODE_20_ & A_DECODE_19_ & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); @@ -574,7 +578,7 @@ SM_AMIGA_i_7_.T.X2 = (nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_ SM_AMIGA_i_7_.C = (CLK_OSZI); -N_60 = (nEXP_SPACE +N_205 = (nEXP_SPACE # A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index 7d82ad3..5418a9a 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -35,17 +35,17 @@ DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000} DATA LOCATION BG_030:C_*_21 // INP DATA LOCATION CIIN:E_12_47 // OUT DATA LOCATION CLK_000:*_*_11 // INP -DATA LOCATION CLK_000_D_0_:D_9 // NOD -DATA LOCATION CLK_000_D_1_:H_5 // NOD -DATA LOCATION CLK_000_D_2_:H_6 // NOD -DATA LOCATION CLK_000_D_3_:F_13 // NOD +DATA LOCATION CLK_000_D_0_:F_0 // NOD +DATA LOCATION CLK_000_D_1_:A_8 // NOD +DATA LOCATION CLK_000_D_2_:H_2 // NOD +DATA LOCATION CLK_000_D_3_:D_2 // NOD DATA LOCATION CLK_000_D_4_:F_5 // NOD DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT DATA LOCATION CLK_EXP:B_1_10 // OUT DATA LOCATION CLK_OSZI:*_*_61 // Cin -DATA LOCATION CLK_OUT_INTreg:A_1 // NOD -DATA LOCATION CYCLE_DMA_0_:B_13 // NOD -DATA LOCATION CYCLE_DMA_1_:B_2 // NOD +DATA LOCATION CLK_OUT_INTreg:A_2 // NOD +DATA LOCATION CYCLE_DMA_0_:G_6 // NOD +DATA LOCATION CYCLE_DMA_1_:G_10 // NOD DATA LOCATION DSACK1:H_9_81 // OUT DATA LOCATION DS_030:A_0_98 // OUT DATA LOCATION DTACK:D_*_30 // INP @@ -60,11 +60,11 @@ DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_} DATA LOCATION IPL_0_:G_*_67 // INP DATA LOCATION IPL_1_:F_*_56 // INP DATA LOCATION IPL_2_:G_*_68 // INP -DATA LOCATION IPL_D0_0_:A_6 // NOD -DATA LOCATION IPL_D0_1_:D_6 // NOD -DATA LOCATION IPL_D0_2_:A_2 // NOD +DATA LOCATION IPL_D0_0_:F_9 // NOD +DATA LOCATION IPL_D0_1_:A_10 // NOD +DATA LOCATION IPL_D0_2_:C_6 // NOD DATA LOCATION LDS_000:D_12_31 // IO -DATA LOCATION N_60:E_9 // NOD +DATA LOCATION N_205:E_5 // NOD DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030} DATA LOCATION RN_BG_000:D_1 // NOD {BG_000} DATA LOCATION RN_IPL_030_0_:B_5 // NOD {IPL_030_0_} @@ -78,38 +78,38 @@ DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000} DATA LOCATION SIZE_0_:G_12_70 // IO DATA LOCATION SIZE_1_:H_12_79 // IO DATA LOCATION SM_AMIGA_0_:A_12 // NOD -DATA LOCATION SM_AMIGA_1_:A_5 // NOD -DATA LOCATION SM_AMIGA_2_:A_9 // NOD -DATA LOCATION SM_AMIGA_3_:A_13 // NOD -DATA LOCATION SM_AMIGA_4_:G_5 // NOD -DATA LOCATION SM_AMIGA_5_:F_12 // NOD -DATA LOCATION SM_AMIGA_6_:F_0 // NOD -DATA LOCATION SM_AMIGA_i_7_:F_8 // NOD +DATA LOCATION SM_AMIGA_1_:A_1 // NOD +DATA LOCATION SM_AMIGA_2_:C_9 // NOD +DATA LOCATION SM_AMIGA_3_:C_2 // NOD +DATA LOCATION SM_AMIGA_4_:A_5 // NOD +DATA LOCATION SM_AMIGA_5_:A_6 // NOD +DATA LOCATION SM_AMIGA_6_:B_13 // NOD +DATA LOCATION SM_AMIGA_i_7_:B_2 // NOD DATA LOCATION UDS_000:D_8_32 // IO DATA LOCATION VMA:D_0_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP -DATA LOCATION cpu_est_0_:G_9 // NOD -DATA LOCATION cpu_est_1_:D_13 // NOD -DATA LOCATION cpu_est_2_:D_2 // NOD -DATA LOCATION cpu_est_3_:A_8 // NOD -DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:A_10 // NOD -DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:C_10 // NOD -DATA LOCATION inst_AMIGA_DS:H_2 // NOD -DATA LOCATION inst_AS_000_DMA:C_13 // NOD -DATA LOCATION inst_AS_000_INT:C_6 // NOD -DATA LOCATION inst_AS_030_000_SYNC:F_4 // NOD -DATA LOCATION inst_AS_030_D0:E_8 // NOD +DATA LOCATION cpu_est_0_:F_4 // NOD +DATA LOCATION cpu_est_1_:G_5 // NOD +DATA LOCATION cpu_est_2_:D_13 // NOD +DATA LOCATION cpu_est_3_:D_9 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:E_9 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:E_8 // NOD +DATA LOCATION inst_AMIGA_DS:H_13 // NOD +DATA LOCATION inst_AS_000_DMA:G_13 // NOD +DATA LOCATION inst_AS_000_INT:C_13 // NOD +DATA LOCATION inst_AS_030_000_SYNC:F_8 // NOD +DATA LOCATION inst_AS_030_D0:F_12 // NOD DATA LOCATION inst_AS_030_D1:F_1 // NOD DATA LOCATION inst_BGACK_030_INT_D:E_13 // NOD -DATA LOCATION inst_CLK_OUT_PRE_50:H_13 // NOD -DATA LOCATION inst_CLK_OUT_PRE_D:E_5 // NOD +DATA LOCATION inst_CLK_OUT_PRE_50:H_6 // NOD +DATA LOCATION inst_CLK_OUT_PRE_D:H_5 // NOD DATA LOCATION inst_DSACK1_INT:G_2 // NOD -DATA LOCATION inst_DS_000_DMA:C_9 // NOD -DATA LOCATION inst_DS_000_ENABLE:C_2 // NOD -DATA LOCATION inst_DTACK_D0:F_9 // NOD -DATA LOCATION inst_LDS_000_INT:G_13 // NOD -DATA LOCATION inst_UDS_000_INT:B_6 // NOD -DATA LOCATION inst_VPA_D:G_6 // NOD +DATA LOCATION inst_DS_000_DMA:G_9 // NOD +DATA LOCATION inst_DS_000_ENABLE:A_13 // NOD +DATA LOCATION inst_DTACK_D0:F_13 // NOD +DATA LOCATION inst_LDS_000_INT:A_9 // NOD +DATA LOCATION inst_UDS_000_INT:D_6 // NOD +DATA LOCATION inst_VPA_D:B_6 // NOD DATA LOCATION nEXP_SPACE:*_*_14 // INP DATA IO_DIR AHIGH_24_:BI DATA IO_DIR AHIGH_25_:BI @@ -171,6 +171,16 @@ DATA IO_DIR VMA:OUT DATA IO_DIR VPA:IN DATA IO_DIR nEXP_SPACE:IN DATA GLB_CLOCK CLK_OSZI +DATA PW_LEVEL AHIGH_30_:1 +DATA SLEW AHIGH_30_:0 +DATA PW_LEVEL AHIGH_31_:1 +DATA SLEW AHIGH_31_:0 +DATA PW_LEVEL AHIGH_29_:1 +DATA SLEW AHIGH_29_:0 +DATA PW_LEVEL AHIGH_28_:1 +DATA SLEW AHIGH_28_:0 +DATA PW_LEVEL A_DECODE_23_:1 +DATA SLEW A_DECODE_23_:1 DATA PW_LEVEL AHIGH_27_:1 DATA SLEW AHIGH_27_:0 DATA PW_LEVEL AHIGH_26_:1 @@ -179,32 +189,28 @@ DATA PW_LEVEL AHIGH_25_:1 DATA SLEW AHIGH_25_:0 DATA PW_LEVEL AHIGH_24_:1 DATA SLEW AHIGH_24_:0 -DATA PW_LEVEL AHIGH_31_:1 -DATA SLEW AHIGH_31_:0 DATA PW_LEVEL A_DECODE_22_:1 DATA SLEW A_DECODE_22_:1 DATA PW_LEVEL A_DECODE_21_:1 DATA SLEW A_DECODE_21_:1 -DATA PW_LEVEL A_DECODE_23_:1 -DATA SLEW A_DECODE_23_:1 +DATA PW_LEVEL IPL_2_:1 +DATA SLEW IPL_2_:1 DATA PW_LEVEL A_DECODE_20_:1 DATA SLEW A_DECODE_20_:1 DATA PW_LEVEL A_DECODE_19_:1 DATA SLEW A_DECODE_19_:1 -DATA PW_LEVEL A_DECODE_18_:1 -DATA SLEW A_DECODE_18_:1 -DATA PW_LEVEL A_DECODE_17_:1 -DATA SLEW A_DECODE_17_:1 -DATA PW_LEVEL A_DECODE_16_:1 -DATA SLEW A_DECODE_16_:1 -DATA PW_LEVEL IPL_2_:1 -DATA SLEW IPL_2_:1 DATA PW_LEVEL FC_1_:1 DATA SLEW FC_1_:1 +DATA PW_LEVEL A_DECODE_18_:1 +DATA SLEW A_DECODE_18_:1 DATA PW_LEVEL AS_030:1 DATA SLEW AS_030:0 +DATA PW_LEVEL A_DECODE_17_:1 +DATA SLEW A_DECODE_17_:1 DATA PW_LEVEL AS_000:1 DATA SLEW AS_000:0 +DATA PW_LEVEL A_DECODE_16_:1 +DATA SLEW A_DECODE_16_:1 DATA PW_LEVEL DS_030:1 DATA SLEW DS_030:0 DATA PW_LEVEL UDS_000:1 @@ -219,31 +225,31 @@ DATA SLEW BG_030:1 DATA PW_LEVEL BGACK_000:1 DATA SLEW BGACK_000:1 DATA SLEW CLK_000:1 -DATA PW_LEVEL IPL_1_:1 -DATA SLEW IPL_1_:1 DATA SLEW CLK_OSZI:1 -DATA PW_LEVEL IPL_0_:1 -DATA SLEW IPL_0_:1 DATA PW_LEVEL CLK_DIV_OUT:1 DATA SLEW CLK_DIV_OUT:0 -DATA PW_LEVEL FC_0_:1 -DATA SLEW FC_0_:1 DATA PW_LEVEL CLK_EXP:1 DATA SLEW CLK_EXP:0 -DATA PW_LEVEL A_1_:1 -DATA SLEW A_1_:1 DATA PW_LEVEL FPU_CS:1 DATA SLEW FPU_CS:0 DATA PW_LEVEL FPU_SENSE:1 DATA SLEW FPU_SENSE:1 DATA PW_LEVEL DSACK1:1 DATA SLEW DSACK1:0 +DATA PW_LEVEL IPL_1_:1 +DATA SLEW IPL_1_:1 DATA PW_LEVEL DTACK:1 DATA SLEW DTACK:1 +DATA PW_LEVEL IPL_0_:1 +DATA SLEW IPL_0_:1 DATA PW_LEVEL AVEC:1 DATA SLEW AVEC:0 +DATA PW_LEVEL FC_0_:1 +DATA SLEW FC_0_:1 DATA PW_LEVEL E:1 DATA SLEW E:0 +DATA PW_LEVEL A_1_:1 +DATA SLEW A_1_:1 DATA SLEW VPA:1 DATA SLEW RST:1 DATA PW_LEVEL AMIGA_ADDR_ENABLE:1 @@ -256,14 +262,10 @@ DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1 DATA SLEW AMIGA_BUS_ENABLE_HIGH:0 DATA PW_LEVEL CIIN:1 DATA SLEW CIIN:0 -DATA PW_LEVEL AHIGH_30_:1 -DATA SLEW AHIGH_30_:0 -DATA PW_LEVEL AHIGH_29_:1 -DATA SLEW AHIGH_29_:0 -DATA PW_LEVEL AHIGH_28_:1 -DATA SLEW AHIGH_28_:0 DATA PW_LEVEL SIZE_1_:1 DATA SLEW SIZE_1_:0 +DATA PW_LEVEL SIZE_0_:1 +DATA SLEW SIZE_0_:0 DATA PW_LEVEL IPL_030_2_:1 DATA SLEW IPL_030_2_:0 DATA PW_LEVEL RW_000:1 @@ -282,8 +284,6 @@ DATA PW_LEVEL VMA:1 DATA SLEW VMA:0 DATA PW_LEVEL RW:1 DATA SLEW RW:0 -DATA PW_LEVEL SIZE_0_:1 -DATA SLEW SIZE_0_:0 DATA PW_LEVEL cpu_est_0_:1 DATA SLEW cpu_est_0_:1 DATA PW_LEVEL cpu_est_1_:1 @@ -366,8 +366,8 @@ DATA PW_LEVEL CLK_OUT_INTreg:1 DATA SLEW CLK_OUT_INTreg:1 DATA PW_LEVEL SM_AMIGA_i_7_:1 DATA SLEW SM_AMIGA_i_7_:1 -DATA PW_LEVEL N_60:1 -DATA SLEW N_60:1 +DATA PW_LEVEL N_205:1 +DATA SLEW N_205:1 DATA PW_LEVEL RN_IPL_030_2_:1 DATA PW_LEVEL RN_RW_000:1 DATA PW_LEVEL RN_BG_000:1 diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index f3a8101..479a3dd 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,22 +1,21 @@ -GROUP MACH_SEG_A DS_030 AVEC SM_AMIGA_2_ SM_AMIGA_3_ cpu_est_3_ SM_AMIGA_1_ - SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH IPL_D0_0_ IPL_D0_2_ CLK_OUT_INTreg +GROUP MACH_SEG_A DS_030 AVEC inst_DS_000_ENABLE inst_LDS_000_INT SM_AMIGA_4_ + SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_5_ IPL_D0_1_ CLK_OUT_INTreg CLK_000_D_1_ GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ - RN_IPL_030_2_ CLK_EXP AHIGH_31_ AHIGH_30_ AHIGH_29_ CYCLE_DMA_0_ - CYCLE_DMA_1_ inst_UDS_000_INT + RN_IPL_030_2_ CLK_EXP AHIGH_31_ AHIGH_30_ AHIGH_29_ SM_AMIGA_i_7_ + SM_AMIGA_6_ inst_VPA_D GROUP MACH_SEG_C AMIGA_BUS_ENABLE_LOW AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ - AHIGH_24_ inst_AS_000_DMA inst_DS_000_DMA inst_DS_000_ENABLE inst_AS_000_INT - inst_AMIGA_BUS_ENABLE_DMA_LOW + AHIGH_24_ SM_AMIGA_2_ SM_AMIGA_3_ inst_AS_000_INT IPL_D0_2_ GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 AMIGA_BUS_ENABLE_HIGH LDS_000 - UDS_000 AMIGA_ADDR_ENABLE cpu_est_1_ cpu_est_2_ IPL_D0_1_ CLK_000_D_0_ - -GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 N_60 inst_AS_030_D0 - inst_BGACK_030_INT_D inst_CLK_OUT_PRE_D -GROUP MACH_SEG_F inst_AS_030_000_SYNC SM_AMIGA_i_7_ SM_AMIGA_6_ SM_AMIGA_5_ - inst_AS_030_D1 inst_DTACK_D0 CLK_000_D_3_ CLK_000_D_4_ -GROUP MACH_SEG_G SIZE_0_ E A_0_ RW CLK_DIV_OUT inst_LDS_000_INT inst_DSACK1_INT - SM_AMIGA_4_ cpu_est_0_ inst_VPA_D + UDS_000 AMIGA_ADDR_ENABLE cpu_est_3_ cpu_est_2_ inst_UDS_000_INT + CLK_000_D_3_ +GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 inst_AMIGA_BUS_ENABLE_DMA_HIGH + inst_AMIGA_BUS_ENABLE_DMA_LOW N_205 inst_BGACK_030_INT_D +GROUP MACH_SEG_F inst_AS_030_000_SYNC inst_AS_030_D1 cpu_est_0_ inst_DTACK_D0 + IPL_D0_0_ inst_AS_030_D0 CLK_000_D_0_ CLK_000_D_4_ +GROUP MACH_SEG_G SIZE_0_ E A_0_ RW CLK_DIV_OUT inst_AS_000_DMA inst_DS_000_DMA + CYCLE_DMA_0_ CYCLE_DMA_1_ inst_DSACK1_INT cpu_est_1_ GROUP MACH_SEG_H RW_000 RN_RW_000 FPU_CS BGACK_030 RN_BGACK_030 SIZE_1_ - DSACK1 AS_030 inst_AMIGA_DS inst_CLK_OUT_PRE_50 CLK_000_D_2_ CLK_000_D_1_ - \ No newline at end of file + DSACK1 AS_030 inst_AMIGA_DS inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D + CLK_000_D_2_ \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index c99e83f..41a03e7 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -7022=02GQV \ No newline at end of file +083;=33y@yhP?H \ No newline at end of file diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index 72d0cd8..60ca937 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Sat Dec 30 00:43:46 2017 +DATE: Thu Jan 11 20:16:38 2018 ABEL mach447a * @@ -31,68 +31,69 @@ NOTE Spread Placement? Y * NOTE Run Time Upper Bound in 15 minutes 0 * NOTE Zero Hold Time For Input Registers? Y * NOTE Table of pin names and numbers* -NOTE PINS AHIGH_27_:16 AHIGH_26_:17 AHIGH_25_:18 AHIGH_24_:19* -NOTE PINS AHIGH_31_:4 A_DECODE_22_:84 A_DECODE_21_:94 A_DECODE_23_:85* -NOTE PINS A_DECODE_20_:93 A_DECODE_19_:97 A_DECODE_18_:95* -NOTE PINS A_DECODE_17_:59 A_DECODE_16_:96 IPL_2_:68 FC_1_:58* -NOTE PINS AS_030:82 AS_000:42 DS_030:98 UDS_000:32 LDS_000:31* -NOTE PINS nEXP_SPACE:14 BERR:41 BG_030:21 BGACK_000:28 CLK_000:11* -NOTE PINS IPL_1_:56 CLK_OSZI:61 IPL_0_:67 CLK_DIV_OUT:65* -NOTE PINS FC_0_:57 CLK_EXP:10 A_1_:60 FPU_CS:78 FPU_SENSE:91* -NOTE PINS DSACK1:81 DTACK:30 AVEC:92 E:66 VPA:36 RST:86 AMIGA_ADDR_ENABLE:33* -NOTE PINS AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20 AMIGA_BUS_ENABLE_HIGH:34* -NOTE PINS CIIN:47 AHIGH_30_:5 AHIGH_29_:6 AHIGH_28_:15 SIZE_1_:79* -NOTE PINS IPL_030_2_:9 RW_000:80 BG_000:29 BGACK_030:83 A_0_:69* -NOTE PINS IPL_030_1_:7 IPL_030_0_:8 VMA:35 RW:71 SIZE_0_:70* +NOTE PINS AHIGH_30_:5 AHIGH_31_:4 AHIGH_29_:6 AHIGH_28_:15* +NOTE PINS A_DECODE_23_:85 AHIGH_27_:16 AHIGH_26_:17 AHIGH_25_:18* +NOTE PINS AHIGH_24_:19 A_DECODE_22_:84 A_DECODE_21_:94 IPL_2_:68* +NOTE PINS A_DECODE_20_:93 A_DECODE_19_:97 FC_1_:58 A_DECODE_18_:95* +NOTE PINS AS_030:82 A_DECODE_17_:59 AS_000:42 A_DECODE_16_:96* +NOTE PINS DS_030:98 UDS_000:32 LDS_000:31 nEXP_SPACE:14 BERR:41* +NOTE PINS BG_030:21 BGACK_000:28 CLK_000:11 CLK_OSZI:61 CLK_DIV_OUT:65* +NOTE PINS CLK_EXP:10 FPU_CS:78 FPU_SENSE:91 DSACK1:81 IPL_1_:56* +NOTE PINS DTACK:30 IPL_0_:67 AVEC:92 FC_0_:57 E:66 A_1_:60* +NOTE PINS VPA:36 RST:86 AMIGA_ADDR_ENABLE:33 AMIGA_BUS_DATA_DIR:48* +NOTE PINS AMIGA_BUS_ENABLE_LOW:20 AMIGA_BUS_ENABLE_HIGH:34* +NOTE PINS CIIN:47 SIZE_1_:79 SIZE_0_:70 IPL_030_2_:9 RW_000:80* +NOTE PINS BG_000:29 BGACK_030:83 A_0_:69 IPL_030_1_:7 IPL_030_0_:8* +NOTE PINS VMA:35 RW:71 * NOTE Table of node names and numbers* -NOTE NODES RN_AHIGH_27_:157 RN_AHIGH_26_:155 RN_AHIGH_25_:167 * -NOTE NODES RN_AHIGH_24_:161 RN_AHIGH_31_:143 RN_AS_030:281 * +NOTE NODES RN_AHIGH_30_:125 RN_AHIGH_31_:143 RN_AHIGH_29_:137 * +NOTE NODES RN_AHIGH_28_:149 RN_AHIGH_27_:157 RN_AHIGH_26_:155 * +NOTE NODES RN_AHIGH_25_:167 RN_AHIGH_24_:161 RN_AS_030:281 * NOTE NODES RN_AS_000:203 RN_UDS_000:185 RN_LDS_000:191 RN_BERR:197 * -NOTE NODES RN_AHIGH_30_:125 RN_AHIGH_29_:137 RN_AHIGH_28_:149 * -NOTE NODES RN_SIZE_1_:287 RN_IPL_030_2_:131 RN_RW_000:269 * -NOTE NODES RN_BG_000:175 RN_BGACK_030:275 RN_A_0_:257 RN_IPL_030_1_:139 * -NOTE NODES RN_IPL_030_0_:133 RN_VMA:173 RN_RW:245 RN_SIZE_0_:263 * -NOTE NODES cpu_est_0_:259 cpu_est_1_:193 cpu_est_2_:176 * -NOTE NODES cpu_est_3_:113 inst_AMIGA_BUS_ENABLE_DMA_HIGH:116 * -NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_LOW:164 inst_AS_030_D0:209 * -NOTE NODES inst_AS_030_D1:223 inst_AS_030_000_SYNC:227 inst_AS_000_DMA:169 * -NOTE NODES inst_DS_000_DMA:163 inst_VPA_D:254 CLK_000_D_3_:241 * -NOTE NODES inst_DTACK_D0:235 inst_AMIGA_DS:272 CLK_000_D_1_:277 * -NOTE NODES CLK_000_D_0_:187 inst_CLK_OUT_PRE_50:289 inst_CLK_OUT_PRE_D:205 * -NOTE NODES IPL_D0_0_:110 IPL_D0_1_:182 IPL_D0_2_:104 CLK_000_D_2_:278 * -NOTE NODES CLK_000_D_4_:229 inst_UDS_000_INT:134 inst_DS_000_ENABLE:152 * -NOTE NODES inst_LDS_000_INT:265 inst_BGACK_030_INT_D:217 * -NOTE NODES SM_AMIGA_6_:221 SM_AMIGA_4_:253 SM_AMIGA_1_:109 * -NOTE NODES SM_AMIGA_0_:119 CYCLE_DMA_0_:145 CYCLE_DMA_1_:128 * -NOTE NODES inst_DSACK1_INT:248 inst_AS_000_INT:158 SM_AMIGA_5_:239 * -NOTE NODES SM_AMIGA_3_:121 SM_AMIGA_2_:115 CLK_OUT_INTreg:103 * -NOTE NODES SM_AMIGA_i_7_:233 N_60:211 * +NOTE NODES RN_SIZE_1_:287 RN_SIZE_0_:263 RN_IPL_030_2_:131 * +NOTE NODES RN_RW_000:269 RN_BG_000:175 RN_BGACK_030:275 * +NOTE NODES RN_A_0_:257 RN_IPL_030_1_:139 RN_IPL_030_0_:133 * +NOTE NODES RN_VMA:173 RN_RW:245 cpu_est_0_:227 cpu_est_1_:253 * +NOTE NODES cpu_est_2_:193 cpu_est_3_:187 inst_AMIGA_BUS_ENABLE_DMA_HIGH:211 * +NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_LOW:209 inst_AS_030_D0:239 * +NOTE NODES inst_AS_030_D1:223 inst_AS_030_000_SYNC:233 inst_AS_000_DMA:265 * +NOTE NODES inst_DS_000_DMA:259 inst_VPA_D:134 CLK_000_D_3_:176 * +NOTE NODES inst_DTACK_D0:241 inst_AMIGA_DS:289 CLK_000_D_1_:113 * +NOTE NODES CLK_000_D_0_:221 inst_CLK_OUT_PRE_50:278 inst_CLK_OUT_PRE_D:277 * +NOTE NODES IPL_D0_0_:235 IPL_D0_1_:116 IPL_D0_2_:158 CLK_000_D_2_:272 * +NOTE NODES CLK_000_D_4_:229 inst_UDS_000_INT:182 inst_DS_000_ENABLE:121 * +NOTE NODES inst_LDS_000_INT:115 inst_BGACK_030_INT_D:217 * +NOTE NODES SM_AMIGA_6_:145 SM_AMIGA_4_:109 SM_AMIGA_1_:103 * +NOTE NODES SM_AMIGA_0_:119 CYCLE_DMA_0_:254 CYCLE_DMA_1_:260 * +NOTE NODES inst_DSACK1_INT:248 inst_AS_000_INT:169 SM_AMIGA_5_:110 * +NOTE NODES SM_AMIGA_3_:152 SM_AMIGA_2_:163 CLK_OUT_INTreg:104 * +NOTE NODES SM_AMIGA_i_7_:128 N_205:205 * NOTE BLOCK 0 * L000000 + 111111111111111111110111111111111111111111111111111111111111111111 + 111111111111111110111111110110111111111111111111111111101111111111 + 101111101111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111011111111111111111011110111111111111111111111111111111111111111 - 111111111010111111111111111111111111111111111111111111111111111111 - 101111111111111111111111111111111111111111111011111111111111111111 - 111111101111111111111111111111111111111111111111111111111111111111 - 111111111111111111011111111111111111111111111111110111111101111111 - 111111111111110111111111111111111111110111111111111111111111011111 - 111111111111111111111111111110111111011110111111111111101111111111 - 111110111111111111111111111111110110111111101111111101111111111111* + 111111111110111111111111111111111111111111111111111111111111111111 + 111111111111101111011111111111111111111111111111110111111111111111 + 111101111111111111111111111111011111111111111111111111111111011111 + 111111111011111111111111111111111111011010111111111111111111111111 + 111111111111111111111111011111111011111111101111111111111111111111* L000594 000000000000000000000000000000000000000000000000000000000000000000* -L000660 111110111111111111111111111011111111111111111111111111111111111111* +L000660 111111111111111111111111111111111011111111111111111111101111111111* L000726 000000000000000000000000000000000000000000000000000000000000000000* L000792 000000000000000000000000000000000000000000000000000000000000000000* L000858 000000000000000000000000000000000000000000000000000000000000000000* L000924 000000000000000000000000000000000000000000000000000000000000000000* -L000990 111111111111111111111111111101111111111111111111111111111111111111* -L001056 000000000000000000000000000000000000000000000000000000000000000000* -L001122 000000000000000000000000000000000000000000000000000000000000000000* +L000990 111111111101111111111111110111111111111111011111111111111111101111* +L001056 111111111111111111111111011011111111111111011111111111111111101111* +L001122 111111111101111111111111011011111111111111011111111111111111111111* L001188 000000000000000000000000000000000000000000000000000000000000000000* L001254 000000000000000000000000000000000000000000000000000000000000000000* L001320 111111111111111111111111111111111111111111111111111111111111111111* -L001386 111111111011111111111111111111111111111111011111111111111111111111* +L001386 111111110111111111111111111111111111111111111111111111111111111111* L001452 111111111111111111111111111111111111111111111111111111111111111111* L001518 111111111111111111111111111111111111111111111111111111111111111111* L001584 111111111111111111111111111111111111111111111111111111111111111111* @@ -109,18 +110,18 @@ L002178 111111111111111111111111111111111111111111111111111111111111111111* L002244 111111111111111111111111111111111111111111111111111111111111111111* L002310 111111111111111111111111111111111111111111111111111111111111111111* L002376 111111111111111111111111111111111111111111111111111111111111111111* -L002442 111111111111110111111111111111111111110111011111111111101111111111* -L002508 111111111111111111111111111111111111011011011111111111101111111111* -L002574 111111111111110111111111111111111111011011011111111111111111111111* +L002442 111111111111111111111111111111111111011111011111111111111111011111* +L002508 111111111110111111111111111111111111011111011111111111111111111111* +L002574 111111111110111111111111111111011111111111011111111111111111011111* L002640 000000000000000000000000000000000000000000000000000000000000000000* L002706 000000000000000000000000000000000000000000000000000000000000000000* L002772 000000000000000000000000000000000000000000000000000000000000000000* -L002838 101111111111111111111111111111111111111111011111111111111111111111* -L002904 111111111111111111111111111111111111111111111111111111111111111111* -L002970 111111111111111111111111111111111111111111111111111111111111111111* -L003036 111111111111111111111111111111111111111111111111111111111111111111* -L003102 111111111111111111111111111111111111111111111111111111111111111111* +L002838 111111111101111111110111111111111111111111011111111111111111101111* +L002904 111111111111111111111111111111011111111111011111111111111111101111* +L002970 111111111101111111111111111111011111111111011111111111111111111111* +L003036 000000000000000000000000000000000000000000000000000000000000000000* +L003102 000000000000000000000000000000000000000000000000000000000000000000* L003168 111111111111111111111111111111111111111111111111111111111111111111* L003234 111111111111111111111111111111111111111111111111111111111111111111* L003300 111111111111111111111111111111111111111111111111111111111111111111* @@ -128,19 +129,19 @@ L003366 111111111111111111111111111111111111111111111111111111111111111111* L003432 111111111111111111111111111111111111111111111111111111111111111111* L003498 000000000000000000000000000000000000000000000000000000000000000000* -L003564 111111111111111111111011111111111111111111111111111111111111011111* -L003630 111111111111111111111111111111111111111111111111111111101111011111* -L003696 111111111111110111111111111111111111111111111111111111111111011111* -L003762 111111111111111011110111111111110111111111111111111111011101111111* -L003828 000000000000000000000000000000000000000000000000000000000000000000* -L003894 111111111110111011111011111111111011111111011111110110011110011111* -L003960 111011111101111011111111111111111111111111011111110111011111111111* -L004026 111111111111111111111111111111111111110111011111111111011111111111* -L004092 111111111111111011111111111111111111110111011111111111111111111111* -L004158 111111111111111011111111111111111110111111011111110111011111111111* +L003564 111111111101111111111111111111111111111111111111111111111111111111* +L003630 111111111111111111111111111111111111111111111111111111111111111111* +L003696 111111111111111111111111111111111111111111111111111111111111111111* +L003762 111111111111111111111111111111111111111111111111111111111111111111* +L003828 111111111111111111111111111111111111111111111111111111111111111111* +L003894 111111111111111111111111111111111111111111101111111111111111111111* +L003960 111101111111111111111011111111111111111111111111111111111111111111* +L004026 101111111111101111110111111101111111111111111111111111111111111111* +L004092 000000000000000000000000000000000000000000000000000000000000000000* +L004158 000000000000000000000000000000000000000000000000000000000000000000* L004224 000000000000000000000000000000000000000000000000000000000000000000* -L004290 111111101111111111111111111111111111111110011111111111111111111111* +L004290 111111101111111111111111111111111111111111011111111111111111111111* L004356 111111111111111111111111111111111111111111111111111111111111111111* L004422 111111111111111111111111111111111111111111111111111111111111111111* L004488 111111111111111111111111111111111111111111111111111111111111111111* @@ -152,16 +153,16 @@ L004818 111111111111111111111111111111111111111111111111111111111111111111* L004884 111111111111111111111111111111111111111111111111111111111111111111* L004950 000000000000000000000000000000000000000000000000000000000000000000* -L005016 111111111111111011111111111111111111011111011111111111011111111111* -L005082 111111111111111111011111111111111111111111011111111111011111111111* -L005148 111111111111111011011111111111111111111111011111111111111111111111* +L005016 111111111110111111111111011111111111111111011111111111111111011111* +L005082 111111111111111111011111111111111111111111011111111111111111011111* +L005148 111111111110111111011111111111111111111111011111111111111111111111* L005214 000000000000000000000000000000000000000000000000000000000000000000* L005280 000000000000000000000000000000000000000000000000000000000000000000* -L005346 111111111111111111111111111111111111111111101111110111111111111111* -L005412 111111111110111011111011111111111011111111111111110110011110011111* -L005478 111011111101111011111111111111111111111111111111110111011111111111* -L005544 111111111111110111111111111111111111111111010111111011101111111111* -L005610 111111111111111011111111111111111110111111111111110111011111111111* +L005346 111111111101111111111111111111111111011111011111111111111111101111* +L005412 111111111111111111111111111111111111111011011111110111111111111111* +L005478 111111111101111101110111111111111111111111011111111111111111101111* +L005544 000000000000000000000000000000000000000000000000000000000000000000* +L005610 000000000000000000000000000000000000000000000000000000000000000000* L005676 111111111111111111111111111111111111111110111111111111111111111111* L005742 111111111111111111111111111111111111111111111111111111111111111111* @@ -179,32 +180,32 @@ L006402 000000000000000000000000000000000000000000000000000000000000000000* L006534 0010* L006538 01100011111000* -L006552 00100110010011* -L006566 01010110010101* +L006552 10100110010011* +L006566 00010110010101* L006580 11101011111111* L006594 00110011111000* L006608 10100110010010* -L006622 01010110010001* +L006622 10100110010001* L006636 11101011110011* -L006650 10100110010000* +L006650 00110110010000* L006664 10100110010011* L006678 01010110010001* L006692 11100011110011* L006706 10100110010000* -L006720 10100111010010* +L006720 10100110010010* L006734 11011011110101* L006748 11111111111111* NOTE BLOCK 1 * L006762 111111111111111111110111111111111111111111111111111111111111111111 - 111111111111011111111111111111111111111111111111111111111111111111 - 101101101111111111111111111111111111111111111011111111110111111111 - 111111111111111111111111111111111011011111111111111111011111111111 - 111111111110111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111110111111111111111011111111111111111111111111111111111 - 111111110111111111111111111011111111111110111111111111111111111111 - 111111111111111111011111111111111111111111101111110110111111111111* + 111011111101011111111111111111111111111111111111111111111111111111 + 111110101011111111011111111110111111111111111111111111110111111111 + 101111111111111111111111111111111111011111111111111111011111111111 + 111111111111111111111111111111111111111111111111111011111111111111 + 111111111111111101111111111111011111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111011111 + 111111111111111111111111111111111111111110111111111111111111111111 + 111111111111111111111111110111110111111111100111111111111111111111* L007356 111111111111111111111111111111111111111111111111111111111111111111* L007422 000000000000000000000000000000000000000000000000000000000000000000* @@ -212,47 +213,47 @@ L007488 000000000000000000000000000000000000000000000000000000000000000000* L007554 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000000000000000000000000000000000000000000000000000000000000000000* +L008148 111110111101111111111111111101011011101111011111110111111111101111* +L008214 111111111111111111111111111111111111011111101111111111111111111111* +L008280 111111111111111111111111111111011111011111011111110111111111101111* +L008346 111110111101111111111111111101111011101111011111111111111111111111* L008412 000000000000000000000000000000000000000000000000000000000000000000* -L008478 111111010111111111111111111111010111111111011011111011111111111111* -L008544 111111010111111111111111111111101011111111011011111011111111111111* -L008610 111111101011111111111111111111010111111111011011111011111111111111* -L008676 111111101011111111111111111111101011111111011011111011111111111111* -L008742 111111111111111111111111111111111111111111011011111111101111111111* +L008478 010111011011111101101111111111111111111111011111111111111111111111* +L008544 101011011011111101101111111111111111111111011111111111111111111111* +L008610 010111101011111110101111111111111111111111011111111111111111111111* +L008676 101011101011111110101111111111111111111111011111111111111111111111* +L008742 111111111011111111111111111111111111111111011111111111101111111111* L008808 111111111111111111111111111111111111111111111111111111111111111111* -L008874 111111111111111111111111111111011011111111011111111111101111111111* -L008940 111111111111111111111111111111100111111111011111111111101111111111* -L009006 111111100111111111111111111111111111111111011111111111101111111111* -L009072 111111011011111111111111111111111111111111011111111111101111111111* -L009138 111111111111111111111111111111111111111111011111111011101111111111* -L009204 111111010111111111111111111111101011111111011011111011111111111111* -L009270 111111101011111111111111111111101011111111011011111011111111111111* -L009336 111111101011111111111111111111101011111111010111110111111111111111* -L009402 111111010111111111111111111111101011111111010111110111111111111111* -L009468 111111111111111111111111111111111011111111011111111111111011111111* +L008874 100111111111111111111111111111111111111111011111111111101111111111* +L008940 011011111111111111111111111111111111111111011111111111101111111111* +L009006 111111101111111101111111111111111111111111011111111111101111111111* +L009072 111111011111111110111111111111111111111111011111111111101111111111* +L009138 111111111111111111101111111111111111111111011111111111101111111111* +L009204 101011011011111101101111111111111111111111011111111111111111111111* +L009270 101011101011111110101111111111111111111111011111111111111111111111* +L009336 101011100111111110011111111111111111111111011111111111111111111111* +L009402 101011010111111101011111111111111111111111011111111111111111111111* +L009468 101111111111111111111111111111111111111111011111111111111011111111* L009534 111111111111111111111111111111111111111111111111111111111111111111* -L009600 111110111110111111111111111111111111111111011111111111111111111111* -L009666 101111111101111111111111111111111111111111011111111111111111111111* -L009732 000000000000000000000000000000000000000000000000000000000000000000* -L009798 000000000000000000000000000000000000000000000000000000000000000000* -L009864 000000000000000000000000000000000000000000000000000000000000000000* -L009930 111111111111111111111111111111101111111111011111111111111011111111* -L009996 111111100111111111111111111111111111111111011111111111111011111111* -L010062 111111011011111111111111111111111111111111011111111111111011111111* -L010128 111111111111111111111111111111111111111111011011110111111011111111* -L010194 111111111111111111111111111111111111111111010111111011111011111111* +L009600 111111111111111111111111111011111111111111011111111111111111111111* +L009666 111011111111111111111111111111111111111111011111111111111011111111* +L009732 111111101111111101111111111111111111111111011111111111111011111111* +L009798 111111011111111110111111111111111111111111011111111111111011111111* +L009864 111111111011111111011111111111111111111111011111111111111011111111* +L009930 111111110111111111101111111111111111111111011111111111111011111111* +L009996 000000000000000000000000000000000000000000000000000000000000000000* +L010062 000000000000000000000000000000000000000000000000000000000000000000* +L010128 000000000000000000000000000000000000000000000000000000000000000000* +L010194 000000000000000000000000000000000000000000000000000000000000000000* L010260 111111111111111111111111111111111111111110111111111111111111111111* L010326 000000000000000000000000000000000000000000000000000000000000000000* @@ -260,23 +261,23 @@ L010392 111111111111111111111111111111111111111111111111111111111111111111* L010458 111111111111111111111111111111111111111111111111111111111111111111* L010524 111111111111111111111111111111111111111111111111111111111111111111* L010590 111111111111111111111111111111111111111111111111111111111111111111* -L010656 111111101011111111111111111111010111111111011011111011111111111111* -L010722 111111101011111111111111111111101011111111011011111011111111111111* -L010788 111111101011111111111111111111010111111111010111110111111111111111* -L010854 111111101011111111111111111111101011111111010111110111111111111111* +L010656 010111101011111110101111111111111111111111011111111111111111111111* +L010722 101011101011111110101111111111111111111111011111111111111111111111* +L010788 010111100111111110011111111111111111111111011111111111111111111111* +L010854 101011100111111110011111111111111111111111011111111111111111111111* L010920 111111101111101111111111111111111111111111011111111111111111111111* L010986 111111111111111111111111111111111111111110111111111111111111111111* -L011052 111111111111101111111111111111011011111111011111111111111111111111* -L011118 111111111111101111111111111111100111111111011111111111111111111111* -L011184 111111111011101111111111111111111111111111011111111111111111111111* -L011250 111111111111101111111111111111111111111111011011110111111111111111* -L011316 111111111111101111111111111111111111111111010111111011111111111111* -L011382 111111111111111111111111111111111111111111111111111111111111111111* -L011448 111111111111111111111111111111111111111111111111111111111111111111* -L011514 111111111111111111111111111111111111111111111111111111111111111111* -L011580 111111111111111111111111111111111111111111111111111111111111111111* -L011646 111111111111111111111111111111111111111111111111111111111111111111* +L011052 100111111111101111111111111111111111111111011111111111111111111111* +L011118 011011111111101111111111111111111111111111011111111111111111111111* +L011184 111111111111101110111111111111111111111111011111111111111111111111* +L011250 111111111011101111011111111111111111111111011111111111111111111111* +L011316 111111110111101111101111111111111111111111011111111111111111111111* +L011382 000000000000000000000000000000000000000000000000000000000000000000* +L011448 000000000000000000000000000000000000000000000000000000000000000000* +L011514 000000000000000000000000000000000000000000000000000000000000000000* +L011580 000000000000000000000000000000000000000000000000000000000000000000* +L011646 000000000000000000000000000000000000000000000000000000000000000000* L011712 111111111111111111111111111111111111111110111111111111111111111111* L011778 000000000000000000000000000000000000000000000000000000000000000000* @@ -284,10 +285,10 @@ L011844 111111111111111111111111111111111111111111111111111111111111111111* L011910 111111111111111111111111111111111111111111111111111111111111111111* L011976 111111111111111111111111111111111111111111111111111111111111111111* L012042 111111111111111111111111111111111111111111111111111111111111111111* -L012108 111111111111111111110111111011111111111110011111111110111111111111* -L012174 111111111111110111110111111111111111111110011111111110111111111111* -L012240 111111111111111011111011110111111111111110011111111110111111111111* -L012306 111111111111111111110111111111111111011110011111111110111111111111* +L012108 111111111111111111110111111111111111111111011111111111111111011111* +L012174 111111111111111111110111111111111111111111011111111011111111111111* +L012240 111110111101111111111011111101111011101111011111111111111111111111* +L012306 000000000000000000000000000000000000000000000000000000000000000000* L012372 000000000000000000000000000000000000000000000000000000000000000000* L012438 000000000000000000000000000000000000000000000000000000000000000000* @@ -307,31 +308,31 @@ L013164 L013296 0010* L013300 00100011111000* L013314 00101111111111* -L013328 10100110010100* +L013328 00100111010100* L013342 11011111111110* L013356 11100110011000* L013370 11100110011111* -L013384 11100110011100* +L013384 01110110011100* L013398 11001011111110* L013412 00110011110000* L013426 11100110010011* L013440 11111011110111* -L013454 11111111110011* +L013454 11001111110011* L013468 00110011110000* L013482 10100110010010* L013496 11011011110001* L013510 11111111111111* NOTE BLOCK 2 * L013524 - 111111111111111111111101111111111111111111011111111111111111111111 - 111111111111111101111111110111111111111111111111111011111111111111 - 111111111111111111011111111111111111111111111111111111111111111111 - 111101111111111111110111111111111111111111111011111111111111111111 - 111111101110111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111100111111111111111111111111111111111111111111111111111 - 111111111111111111111111111110111111111010111111111111101111111111 - 101111111011111111111111011111111011111111111111111111111111111111* + 111111111111101111111111111111111111111111111111111111110111011111 + 111111111111111111111111110111111111111111111111111111111111111111 + 111111111011111111111101111111111111111111111111111111111111111111 + 111101111111111111111011111111111111111111111011111111111111111111 + 111111111110111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111011111111111111111111111 + 111111011111110110111111111111111111111111111111111111111111111111 + 111111111111111111101111111111111111011110111111111111111111111111 + 100111111111111111111111111111111110111111111111111111111111111111* L014118 111111111111111111111111111111111111111110111111111111111111111111* L014184 000000000000000000000000000000000000000000000000000000000000000000* @@ -346,11 +347,11 @@ L014712 000000000000000000000000000000000000000000000000000000000000000000* L014778 000000000000000000000000000000000000000000000000000000000000000000* L014844 111111111111111111111111111111111111111110111111111111111111111111* -L014910 011111111111110111111111111111111111111111110111111111101111111111* -L014976 011101111111111111111111111111111111111011111111111111111111111111* -L015042 011111111101110111111111111111111111111111111111110111101111111111* -L015108 000000000000000000000000000000000000000000000000000000000000000000* -L015174 000000000000000000000000000000000000000000000000000000000000000000* +L014910 101101111111111111111111111111111111111111111111111111111111111111* +L014976 111001011110110111111010111111111111111111101011111111111111111111* +L015042 111101011110101111111101111111111111111111111111111111111111111111* +L015108 011110101101111111111111111111111111011111111111111111111111111111* +L015174 111101011110111111111111111111111110111111111111111111111111111111* L015240 111111111111111111111111111111111111111111111111111111111111111111* L015306 111111111111111111111111111111111111111111111111111111111111111111* L015372 111111111111111111111111111111111111111111111111111111111111111111* @@ -370,11 +371,11 @@ L016164 111111111111111111111111111111111111111111111111111111111111111111* L016230 111111111111111111111111111111111111111111111111111111111111111111* L016296 111111111111111111111111111111111111111110111111111111111111111111* -L016362 011111111101110111111111111111111111111111111111111111101111111111* -L016428 011111111111111111101111111111111111111011111111111111111111111111* -L016494 000000000000000000000000000000000000000000000000000000000000000000* -L016560 000000000000000000000000000000000000000000000000000000000000000000* -L016626 000000000000000000000000000000000000000000000000000000000000000000* +L016362 011111111011111111111111111111111111111111111111111111111111111111* +L016428 111111111111111111111111111111111111111111111111111111111111111111* +L016494 111111111111111111111111111111111111111111111111111111111111111111* +L016560 111111111111111111111111111111111111111111111111111111111111111111* +L016626 111111111111111111111111111111111111111111111111111111111111111111* L016692 111111111111111111111111111111111111111111111111111111111111111111* L016758 111111111111111111111111111111111111111111111111111111111111111111* L016824 111111111111111111111111111111111111111111111111111111111111111111* @@ -387,18 +388,18 @@ L017154 111111111111111111111111111111111111111111111111111111111111111111* L017220 111111111111111111111111111111111111111111111111111111111111111111* L017286 111111111111111111111111111111111111111111111111111111111111111111* L017352 111111111111111111111111111111111111111111111111111111111111111111* -L017418 101111111111111111111111111111111111111111111111111111111111111111* -L017484 111111110111111111111111111111111111111111111111111111111111111111* -L017550 111111111111111111111011111111111111111111101111111111111111111111* -L017616 111111111111111111111111111111110111111111111111111111111111111111* -L017682 111111111111101111110111111111111111111111011111111111111111111111* +L017418 011001011110110111111010111111111111111111101011111111111111111111* +L017484 011101011110101111111101111111111111111111111111111111111111111111* +L017550 011111011111111111111111110111111111111111111111111111111111111111* +L017616 011111111110111111111111110111111111111111111111111111111111111111* +L017682 011101011110111111111111111111111110111111111111111111111111111111* L017748 111111111111111111111111111111111111111111111111111111111111111111* -L017814 011111011111111111111111111111111111111110111111111111111111111111* -L017880 111111111111111111111111100101111111111111111111111111111111111111* -L017946 000000000000000000000000000000000000000000000000000000000000000000* -L018012 000000000000000000000000000000000000000000000000000000000000000000* -L018078 000000000000000000000000000000000000000000000000000000000000000000* +L017814 111111111111111111111111111111111111111111111111111111111111111111* +L017880 111111111111111111111111111111111111111111111111111111111111111111* +L017946 111111111111111111111111111111111111111111111111111111111111111111* +L018012 111111111111111111111111111111111111111111111111111111111111111111* +L018078 111111111111111111111111111111111111111111111111111111111111111111* L018144 111111111111111111111111111111111111111111111111111111111111111111* L018210 111111111111111111111111111111111111111111111111111111111111111111* L018276 111111111111111111111111111111111111111111111111111111111111111111* @@ -411,18 +412,18 @@ L018606 111111111111111111111111111111111111111111111111111111111111111111* L018672 111111111111111111111111111111111111111111111111111111111111111111* L018738 111111111111111111111111111111111111111111111111111111111111111111* L018804 111111111111111111111111111111111111111111111111111111111111111111* -L018870 101111111111111111111111111111111111111111111111111111111111111111* -L018936 111111110111111111111111111111111111111111111111111111111111111111* -L019002 111111111111111111111011111111111111111111101111111111111111111111* -L019068 111111111111111111111101101101111111111111111111111111111111111111* -L019134 111111111111111111111111111111110111111111111111111111111111111111* +L018870 011111101101111111111111111111111111111111111111111111110111111111* +L018936 011111111111111111101111111111111111111111111111111111111111101111* +L019002 000000000000000000000000000000000000000000000000000000000000000000* +L019068 000000000000000000000000000000000000000000000000000000000000000000* +L019134 000000000000000000000000000000000000000000000000000000000000000000* L019200 000000000000000000000000000000000000000000000000000000000000000000* -L019266 111111111111101111110111111111111111111111011111111111111111111111* -L019332 000000000000000000000000000000000000000000000000000000000000000000* -L019398 000000000000000000000000000000000000000000000000000000000000000000* -L019464 000000000000000000000000000000000000000000000000000000000000000000* -L019530 000000000000000000000000000000000000000000000000000000000000000000* +L019266 111111111111111111111111111111111111111111111111111111111111111111* +L019332 111111111111111111111111111111111111111111111111111111111111111111* +L019398 111111111111111111111111111111111111111111111111111111111111111111* +L019464 111111111111111111111111111111111111111111111111111111111111111111* +L019530 111111111111111111111111111111111111111111111111111111111111111111* L019596 111111111111111111111111111111111111111111111111111111111111111111* L019662 111111111111111111111111111111111111111111111111111111111111111111* L019728 111111111111111111111111111111111111111111111111111111111111111111* @@ -434,50 +435,50 @@ L019926 L020058 0010* L020062 00100011110000* L020076 01101111110011* -L020090 10100110011100* +L020090 10100111011100* L020104 11101111110010* L020118 00111011110000* L020132 00000011110011* -L020146 11100110010110* +L020146 01010110010110* L020160 11100011110010* -L020174 00111111110001* +L020174 00110111110001* L020188 10100110010011* -L020202 01110110011110* -L020216 11100011111111* +L020202 11011111111110* +L020216 11110011111111* L020230 00111011111001* -L020244 10100110010011* -L020258 11110111110000* +L020244 11100110010011* +L020258 11010111110000* L020272 11111111111111* NOTE BLOCK 3 * L020286 - 111111011111111111101111111111111111111111111111111111111111111111 - 111111110101111111111111101111111111111111111111111111111111111111 - 111111111111111111111101111111111111111111101110111111111111111111 - 111111111111111111111011111111111111111111110111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111101111111111111111111111111111111111111111101111111 - 111111111111110111111111111111111111011111111111111111111111101111 - 111111111111111111111111111011111111111010111111111111111111111111 - 100101111111111111111111111111110111111111111111111111111111111111* + 111111111111111111111111111111111111111111111111111111110111111011 + 111111110111111111111111111111011111111111111111111111111111111111 + 101111111111111111111101111111111111111110111111111111111111111111 + 111111111111111111111011111111111111111111111011111111111111111111 + 111111111110111111111111111111111111111111111111111111111111111111 + 110111111111111111111111111111111111111111111111110111111111111111 + 111110011111110111111111111111111111110111111111111111111111111111 + 111111111111111111101111111111110111111111111110111111111111111111 + 111111111111111111111111111110111101011111101111111111111111111111* L020880 - 111111111111111111111111111111111111111101111111111111111111111111* -L020946 101011111111111111111111111111111111111111111111111111111111111111* -L021012 111011111111110111111111101011111011101111111111111111111110111111* -L021078 010111111111111011111111010111111011101111111110111111111101111111* + 111111111111111111111111111111111111111111111101111111111111111111* +L020946 111111111111111111111111111111111111101111101111111111111111111111* +L021012 111011101101111011111011111111111111101111111011111111111111111111* +L021078 111011011110111011110110111111111111011111010111111111111111111111* L021144 000000000000000000000000000000000000000000000000000000000000000000* L021210 000000000000000000000000000000000000000000000000000000000000000000* -L021276 011111111001110111111111111111111111111111111111111111111111011111* -L021342 011110111011111111111111111111111111111111111111111111111111111111* +L021276 111111111001111111111111111111011111111111011111111111111111110111* +L021342 111111111011111111111111111111111110111111011111111111111111111111* L021408 000000000000000000000000000000000000000000000000000000000000000000* L021474 000000000000000000000000000000000000000000000000000000000000000000* L021540 000000000000000000000000000000000000000000000000000000000000000000* L021606 111111111111111111111111111111111111111111111111111111111111111111* -L021672 111111111111111111111111111111110111111111111111111111111111111111* -L021738 111111111111111011111111010111111111111111111111111111111101111111* -L021804 000000000000000000000000000000000000000000000000000000000000000000* -L021870 000000000000000000000000000000000000000000000000000000000000000000* -L021936 000000000000000000000000000000000000000000000000000000000000000000* +L021672 111111111111111111111111111101111111111111111111111111111111111111* +L021738 111111111111111111111111111111111111111111111111111111111111111111* +L021804 111111111111111111111111111111111111111111111111111111111111111111* +L021870 111111111111111111111111111111111111111111111111111111111111111111* +L021936 111111111111111111111111111111111111111111111111111111111111111111* L022002 111111111111111111111111111111111111111111111111111111111111111111* L022068 111111111111111111111111111111111111111111111111111111111111111111* L022134 111111111111111111111111111111111111111111111111111111111111111111* @@ -485,8 +486,8 @@ L022200 111111111111111111111111111111111111111111111111111111111111111111* L022266 111111111111111111111111111111111111111111111111111111111111111111* L022332 111111111111111111111111111111111111111111111111111111111111111111* -L022398 111111111111111110111111111111111111111110111111111111111111111111* -L022464 111111111111111111111011111111111111111001111111111111111111111111* +L022398 111110111111111111111111111111111111111111111110111111111111111111* +L022464 111111111111111111101111111111111111111110111101111111111111111111* L022530 000000000000000000000000000000000000000000000000000000000000000000* L022596 000000000000000000000000000000000000000000000000000000000000000000* L022662 000000000000000000000000000000000000000000000000000000000000000000* @@ -496,29 +497,29 @@ L022860 111111111111111111111111111111111111111111111111111111111111111111* L022926 111111111111111111111111111111111111111111111111111111111111111111* L022992 111111111111111111111111111111111111111111111111111111111111111111* L023058 - 011111111111111111111111111111111111111101111111111111111111111111* -L023124 011111111111111111111111111111111111111111101111111111111111111111* -L023190 111111111111111111111111111111111111111111111111111111111111111111* -L023256 111111111111111111111111111111111111111111111111111111111111111111* -L023322 111111111111111111111111111111111111111111111111111111111111111111* -L023388 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111111111111111111011101111111111111111111* +L023124 111111111111111111111111111111111011111111011111111111111011111111* +L023190 101111111111111111111111111111111111111111011111111111110111111111* +L023256 000000000000000000000000000000000000000000000000000000000000000000* +L023322 000000000000000000000000000000000000000000000000000000000000000000* +L023388 000000000000000000000000000000000000000000000000000000000000000000* L023454 111111111111111111111111111111111111111111111111111111111111111111* L023520 111111111111111111111111111111111111111111111111111111111111111111* L023586 111111111111111111111111111111111111111111111111111111111111111111* L023652 111111111111111111111111111111111111111111111111111111111111111111* L023718 111111111111111111111111111111111111111111111111111111111111111111* L023784 - 011111111111111111111111111111111111111101111111111111111111111111* -L023850 111111111111111111111110111111111111111111110111111111111111111111* + 111111111111111111111111111111111111111111011101111111111111111111* +L023850 111111111111111111111111111111111011111111111111110111111111111111* L023916 111111111111111111111111111111111111111111111111111111111111111111* L023982 111111111111111111111111111111111111111111111111111111111111111111* L024048 111111111111111111111111111111111111111111111111111111111111111111* L024114 111111111111111111111111111111111111111111111111111111111111111111* -L024180 111111011111111111111111111111111111111111111111111111111111111111* -L024246 111111111111111111111111111111111111111111111111111111111111111111* -L024312 111111111111111111111111111111111111111111111111111111111111111111* -L024378 111111111111111111111111111111111111111111111111111111111111111111* -L024444 111111111111111111111111111111111111111111111111111111111111111111* +L024180 111111111111110111111011111111111111111111111111111111111111111111* +L024246 111111101111110111111111111111111111111111111111111111111111111111* +L024312 111111111101110111111111111111111111111111111111111111111111111111* +L024378 110111011110111111110111111111111111111111110111111111111111111111* +L024444 000000000000000000000000000000000000000000000000000000000000000000* L024510 000000000000000000000000000000000000000000000000000000000000000000* L024576 111111111111111111111111111111111111111111111111111111111111111111* @@ -533,15 +534,15 @@ L025104 111111111111111111111111111111111111111111111111111111111111111111* L025170 111111111111111111111111111111111111111111111111111111111111111111* L025236 111111111111111111111111111111111111111111111111111111111111111111* -L025302 111111111111111111101111111111111111111111110111111111111111111111* +L025302 111111111111111111111111111111111111111011111111110111111111111111* L025368 111111111111111111111111111111111111111111111111111111111111111111* L025434 111111111111111111111111111111111111111111111111111111111111111111* L025500 111111111111111111111111111111111111111111111111111111111111111111* L025566 111111111111111111111111111111111111111111111111111111111111111111* -L025632 111111111111111111111111101111111111111111111111111111111101111111* -L025698 111111111111111111111111111011111111111111111111111111111101111111* -L025764 111111111111110111111111111111111111111111111111111111111101111111* -L025830 111111111111111011111111010111111111101111111111111111111110111111* +L025632 110111111111111111111111111111111111111111111111111111111111111111* +L025698 111111011110111111110111111111111111111111110111111111111111111111* +L025764 000000000000000000000000000000000000000000000000000000000000000000* +L025830 000000000000000000000000000000000000000000000000000000000000000000* L025896 000000000000000000000000000000000000000000000000000000000000000000* L025962 000000000000000000000000000000000000000000000000000000000000000000* @@ -561,45 +562,45 @@ L026688 L026820 0010* L026824 10100111010000* L026838 11100110011110* -L026852 00100110010100* +L026852 00010110010100* L026866 11100011111111* L026880 11101111111001* L026894 00001011111111* -L026908 01010110010100* +L026908 11100110010100* L026922 11101011110011* L026936 01110011110010* -L026950 00000110010010* +L026950 10100110010010* L026964 11011011110001* L026978 11111111110011* L026992 01110011111010* -L027006 10100110011110* +L027006 00100110011110* L027020 11011011110001* L027034 11111111110011* NOTE BLOCK 4 * L027048 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111101111111111111111111111111111111111111110111110111111111 - 111111110111111111111111111111111111111101110111101111011111111111 - 111011011111111111111111111011111111111111111111111101111111111111 - 111111111111110111111111111111111111111111111111111111111111111111 - 111111111111111111111111011111111111011011111111111111111111111111 - 111111111111011111111111111110111001111111101111111111111111111111 - 111111111111111111101111111111011111111111111110111111111101111111 - 101110111111111101111110111111111111111111111111111111111111111110* + 111111111111111111111111111111111111111111111111111111111111011011 + 111111111111111111111111111111111111110111011111110111111111111111 + 111111111101111111111111110111111111111111110111101111111111111111 + 111011011111111111111111111111111111111111111111111101101111111111 + 111111111111110111111111111111111111111111111110111111111111111111 + 111111111111111111111111011111111111011111111111111111111111111111 + 111111110111011111111111111111111111111111111111111111111011111111 + 111111111111111111111111111110011101111110111111111111111111111110 + 101110111111111110101101111111111111111111111111111111111111111111* L027642 - 110111111111101101101111100111111110011111111111011111111111111111* + 110111111011101111111101101111111111011111111111011111011111111110* L027708 000000000000000000000000000000000000000000000000000000000000000000* L027774 000000000000000000000000000000000000000000000000000000000000000000* L027840 000000000000000000000000000000000000000000000000000000000000000000* L027906 000000000000000000000000000000000000000000000000000000000000000000* L027972 000000000000000000000000000000000000000000000000000000000000000000* -L028038 111110111110111111111111111111111111111111011110111111111111111111* -L028104 111111111111111111111111111111111111111111101101111111111111111111* +L028038 111110111111111111111111111111111111111110101111111111110111111111* +L028104 111111111111111111111111111111111111111101111111111111111011111111* L028170 000000000000000000000000000000000000000000000000000000000000000000* L028236 000000000000000000000000000000000000000000000000000000000000000000* L028302 000000000000000000000000000000000000000000000000000000000000000000* L028368 - 011111111111111111111111111111111111111111111101111111111111111111* + 011111111111111111111111111111111111111101111111111111111111111111* L028434 111111111111111111111111111111111111111111111111111111111111111111* L028500 111111111111111111111111111111111111111111111111111111111111111111* L028566 111111111111111111111111111111111111111111111111111111111111111111* @@ -612,16 +613,16 @@ L028962 111111111111111111111111111111111111111111111111111111111111111111* L029028 111111111111111111111111111111111111111111111111111111111111111111* L029094 000000000000000000000000000000000000000000000000000000000000000000* -L029160 111111111111111111101111111111111111111111111111111111101111111111* +L029160 111111111111111111111111111111111111111111111111111111111111101110* L029226 111111111111111111111111111111111111111111111111111111111111111111* L029292 111111111111111111111111111111111111111111111111111111111111111111* L029358 111111111111111111111111111111111111111111111111111111111111111111* L029424 111111111111111111111111111111111111111111111111111111111111111111* -L029490 111111111111111111111111111111111111110111111111111111111111111111* -L029556 111111111111111111111111111111111111111111111111111111111111111111* -L029622 111111111111111111111111111111111111111111111111111111111111111111* -L029688 111111111111111111111111111111111111111111111111111111111111111111* -L029754 111111111111111111111111111111111111111111111111111111111111111111* +L029490 111111101110111001011111111011011101111011111011111010111111111011* +L029556 111111111111111111111111111111111111111111011111111111111111111111* +L029622 000000000000000000000000000000000000000000000000000000000000000000* +L029688 000000000000000000000000000000000000000000000000000000000000000000* +L029754 000000000000000000000000000000000000000000000000000000000000000000* L029820 000000000000000000000000000000000000000000000000000000000000000000* L029886 111111111111111111111111111111111111111111111111111111111111111111* @@ -636,13 +637,13 @@ L030414 111111111111111111111111111111111111111111111111111111111111111111* L030480 111111111111111111111111111111111111111111111111111111111111111111* L030546 000000000000000000000000000000000000000000000000000000000000000000* -L030612 011111111111111111101111111111111111111111111111111111111111111111* -L030678 111111111111111111111111111111111111111111111111111111111111111111* -L030744 111111111111111111111111111111111111111111111111111111111111111111* -L030810 111111111111111111111111111111111111111111111111111111111111111111* -L030876 111111111111111111111111111111111111111111111111111111111111111111* -L030942 111111101011111011111101111111011011111110111011111010111001111101* -L031008 111111111101111111111111111111111111111111111111111111111111111111* +L030612 101111111111111111111111111111111111111111111111111111111111111111* +L030678 111111111111111111111111111111111111111101111111111111111111111111* +L030744 111111111111111111111111111111111111111111111110111111111111111111* +L030810 111111101110111001011111011011011110111011111011111010111111111111* +L030876 000000000000000000000000000000000000000000000000000000000000000000* +L030942 011111111111111111111111111111111111111110111110111111111111111111* +L031008 011111101110111001011111011011011110111010111011111010111111111111* L031074 000000000000000000000000000000000000000000000000000000000000000000* L031140 000000000000000000000000000000000000000000000000000000000000000000* L031206 000000000000000000000000000000000000000000000000000000000000000000* @@ -660,12 +661,12 @@ L031866 111111111111111111111111111111111111111111111111111111111111111111* L031932 111111111111111111111111111111111111111111111111111111111111111111* L031998 111111111111111111111111111101111111111111111111111111111111111111* -L032064 111111101011111011111101111111011011111110111011111010111001111101* +L032064 111111101110111001011111111011011101111011111011111010111111111011* L032130 111111111111111111111111111111111111111111111111111111111111111111* L032196 111111111111111111111111111111111111111111111111111111111111111111* L032262 111111111111111111111111111111111111111111111111111111111111111111* L032328 111111111111111111111111111111111111111111111111111111111111111111* -L032394 011111111111111111111111111111111111111111111110111111111111111111* +L032394 011111111111111111111111111111111111111110111111111111111111111111* L032460 111111111111111111111111111111111111111111111111111111111111111111* L032526 111111111111111111111111111111111111111111111111111111111111111111* L032592 111111111111111111111111111111111111111111111111111111111111111111* @@ -691,37 +692,37 @@ L033600 10101111110011* L033614 11011011110100* L033628 11110011110010* L033642 01111111111001* -L033656 00000110011111* -L033670 11010111110000* -L033684 11110011111111* -L033698 01110110010000* -L033712 10100111111110* -L033726 11011111110000* -L033740 11110011111111* -L033754 00111011110001* -L033768 01000110011111* -L033782 11010111111100* -L033796 11111111111111* +L033656 10101011111111* +L033670 11011111110000* +L033684 11111011111111* +L033698 10100110010000* +L033712 11100110011110* +L033726 11011111110001* +L033740 11110011111110* +L033754 00111011110000* +L033768 01000110011110* +L033782 11010111111101* +L033796 11111111111110* NOTE BLOCK 5 * L033810 - 111111111111111111111111111111101110111111111111111111111111111111 + 111111011111111111111111111111111110111111111111111111111111111111 111111111101111111111111111111111111111111111111111111111111111111 - 111111111111101111111111111110111111111110111111111111111111111111 - 111011111111111110111111111111111111111111111111111111111110111111 + 111111111111101111111111111111111111111110111111111111111111111111 + 101011111111111110111111111110111111011111111111111111111111111111 111111111111111111111011111111111111111111111111111011111111111111 - 111110111111111111111111011111111111111111111111011111111111111111 - 111111110111110111011101111111111011111111111111111111111111111111 - 111111111111111111111111111011111111111011101110111111111111111111 - 101111111111111111111111111111111111111111111111111111111111111111* + 111110111111111111111111011111111111111111111111111111111111111111 + 111111110111111111011101111111111111111111111111111111111111011111 + 111111111111111111111111111111111111111011111110111111111111111111 + 111111111111111111111111111111110111111111101111111111111111111111* L034404 000000000000000000000000000000000000000000000000000000000000000000* -L034470 011111111111111111111111110111111111111111111111110111111111111111* -L034536 011111111111111011111111111111111111111111111111110111111111111111* -L034602 011111111101111111111111111101101111111110111111111011111110111111* +L034470 111111011111111111111111111111111111111111111111111111111111111111* +L034536 000000000000000000000000000000000000000000000000000000000000000000* +L034602 000000000000000000000000000000000000000000000000000000000000000000* L034668 000000000000000000000000000000000000000000000000000000000000000000* L034734 000000000000000000000000000000000000000000000000000000000000000000* -L034800 011111111111111111111111111111110111111111111111111111111111111111* -L034866 101111111111111111110111111111111111111111111111111111111111111111* +L034800 111111111111111111111111111111111101111111011111111111111111111111* +L034866 111111111111111111110111111111111111111111101111111111111111111111* L034932 000000000000000000000000000000000000000000000000000000000000000000* L034998 000000000000000000000000000000000000000000000000000000000000000000* L035064 000000000000000000000000000000000000000000000000000000000000000000* @@ -739,16 +740,16 @@ L035724 111111111111111111111111111111111111111111111111111111111111111111* L035790 111111111111111111111111111111111111111111111111111111111111111111* L035856 000000000000000000000000000000000000000000000000000000000000000000* -L035922 011111111111111111111111111111111111111011111111111111111110111111* -L035988 011001111101111111111011111111111111111010111101111111111111111111* -L036054 011101111101111111111011011111111111111010111101111111111111111111* -L036120 011101110101111111111011111111111111111010111101111111111111111111* -L036186 011101111101111110111011111111111111111010111101111111111111111111* -L036252 111111111111111111111111111111011111111111111111111111111111111111* -L036318 011101111101111111111001111111111111111010111101111111111111111111* -L036384 011101111101101111111011111111111111111010111101111111111111111111* -L036450 000000000000000000000000000000000000000000000000000000000000000000* -L036516 000000000000000000000000000000000000000000000000000000000000000000* +L035922 111111111111111111111111111101111111111111111111111111111111101111* +L035988 111111111111111111111111111101111111111111111111110111111111111111* +L036054 111111111111111111111111111110111111111111111111111011111111011111* +L036120 000000000000000000000000000000000000000000000000000000000000000000* +L036186 000000000000000000000000000000000000000000000000000000000000000000* +L036252 111111111111111111111111111111110111111111111111111111111111111111* +L036318 111111111111111111111111111111111111111111111111111111111111111111* +L036384 111111111111111111111111111111111111111111111111111111111111111111* +L036450 111111111111111111111111111111111111111111111111111111111111111111* +L036516 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111111111111111111111111111111111111111111111111111111111111111111* -L037836 111111111111111111111111111111111111111111111111111111111111111111* -L037902 111111111111111111111111111111111111111111111111111111111111111111* -L037968 111111111111111111111111111111111111111111111111111111111111111111* +L037374 111111111111111111111111111111111111111010011111111111111111111111* +L037440 111001111101111111111011111111111111101011011101111111111111111111* +L037506 111101111101111111111011011111111111101011011101111111111111111111* +L037572 111101110101111111111011111111111111101011011101111111111111111111* +L037638 111101111101111110111011111111111111101011011101111111111111111111* +L037704 101111111111111111111111111111111111111111011111111111111111111111* +L037770 111101111101111111111001111111111111101011011101111111111111111111* +L037836 111101111101101111111011111111111111101011011101111111111111111111* +L037902 000000000000000000000000000000000000000000000000000000000000000000* +L037968 000000000000000000000000000000000000000000000000000000000000000000* L038034 000000000000000000000000000000000000000000000000000000000000000000* L038100 111111111111111111111111111111111111111111111111111111111111111111* @@ -787,12 +788,12 @@ L038628 111111111111111111111111111111111111111111111111111111111111111111* L038694 111111111111111111111111111111111111111111111111111111111111111111* L038760 000000000000000000000000000000000000000000000000000000000000000000* -L038826 011111111111110111111111111011111111111111111111110111111111111111* -L038892 011111111111111111111111111011111101111111111111111111111111111111* -L038958 011111111111110111111111111111111101111111111111111111111111111111* -L039024 000000000000000000000000000000000000000000000000000000000000000000* -L039090 000000000000000000000000000000000000000000000000000000000000000000* -L039156 111111111111111111111111111111111111111111011111111111111111111111* +L038826 111111111111111111111111111111111111111011011111111111111111111111* +L038892 111111111111111111111111111111111111111111111111111111111111111111* +L038958 111111111111111111111111111111111111111111111111111111111111111111* +L039024 111111111111111111111111111111111111111111111111111111111111111111* +L039090 111111111111111111111111111111111111111111111111111111111111111111* +L039156 111111111111111111101111111111111111111111011111111111111111111111* L039222 111111111111111111111111111111111111111111111111111111111111111111* L039288 111111111111111111111111111111111111111111111111111111111111111111* L039354 111111111111111111111111111111111111111111111111111111111111111111* @@ -813,49 +814,49 @@ L040212 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L040344 0010* -L040348 10100110011110* +L040348 00100110011110* L040362 10100110010010* L040376 11011111111110* L040390 11111011110011* -L040404 11100110011110* -L040418 00110110010010* +L040404 10100110011110* +L040418 00000110010010* L040432 11011111111111* L040446 11111011110011* -L040460 00100111011110* -L040474 01000110010010* +L040460 11100110011110* +L040474 01110110010010* L040488 11010011111110* L040502 11111011111111* -L040516 10100110011110* -L040530 00000110011110* +L040516 01110110011110* +L040530 01000110011110* L040544 11011111111111* L040558 11110011111111* NOTE BLOCK 6 * L040572 - 111011111111111111101111111111111111111111111111111111111111111111 - 111111111111111111111111111110111111111111111111111111101111111111 - 111111111111111111111111111111101111111111111111111111111111111111 - 111111111011111111111111111111111111111111111011111111111111111111 + 111111111111111111111111101111111111111111111111111111111111111111 + 111111111111111111111011111111111111111111111011111111111111111111 + 111111111111111111111111111111111111111111111110111111111111111111 + 111111101111111111111111111110111111111111111111111111111111111011 111111111110111111111111111111111111111111111111111111111111111111 - 111111111111101111111111111111111111111111011111111111111111111111 - 111111111111110111111111111111111111011111111111011111111011111111 - 111101111111111101111111111011111111111010111111111111111111111111 - 101111011111111111110111011111111111111111111111111111111111111111* + 110111111111111011111111111111111111111111111111111111111111111111 + 111111111111101111111111111111111111011111111111010111111111111111 + 111111111011111101111111111111111111111010111111111111111111111111 + 011110111111111111011111111111111111111111101111111111111111111111* L041166 111111111111111111111111111111111111111111111111111111111111111111* -L041232 011111111111111111111111111111111111111110111111111111111011111111* +L041232 111111111111101111111111111111111111111110011111111111111111111111* L041298 000000000000000000000000000000000000000000000000000000000000000000* L041364 000000000000000000000000000000000000000000000000000000000000000000* L041430 000000000000000000000000000000000000000000000000000000000000000000* L041496 000000000000000000000000000000000000000000000000000000000000000000* -L041562 111111111111111111111111011111111111111111111111111111111111111111* +L041562 011111111111111111111111111111111111111111111111111111111111111111* L041628 000000000000000000000000000000000000000000000000000000000000000000* L041694 000000000000000000000000000000000000000000000000000000000000000000* L041760 000000000000000000000000000000000000000000000000000000000000000000* L041826 000000000000000000000000000000000000000000000000000000000000000000* L041892 111111111111111111111111111111111111111111111111111111111111111111* -L041958 011101111111111011111111110111111111111111111111111111111111111111* -L042024 011111111011111111111111111111111111111011111111111111111111111111* +L041958 111111111110111111011111111111111111011111011111111111111111111111* +L042024 111111111111111111111111111111111111111011011111111111111111111011* L042090 000000000000000000000000000000000000000000000000000000000000000000* L042156 000000000000000000000000000000000000000000000000000000000000000000* L042222 000000000000000000000000000000000000000000000000000000000000000000* @@ -866,23 +867,23 @@ L042486 111111111111111111111111111111111111111111111111111111111111111111* L042552 111111111111111111111111111111111111111111111111111111111111111111* L042618 000000000000000000000000000000000000000000000000000000000000000000* -L042684 111111101111111111111111111111111111011111101111111111111111111111* -L042750 111111011111111111111111111111111111101111011111111111111111111111* +L042684 111011101111111111111111111111111111111111111111110111111111111111* +L042750 110111011111111111111111111111111111111111111111111011111111111111* L042816 000000000000000000000000000000000000000000000000000000000000000000* L042882 000000000000000000000000000000000000000000000000000000000000000000* L042948 000000000000000000000000000000000000000000000000000000000000000000* -L043014 011111111111111111111111110111111111111111110111111111111111111111* -L043080 011111111111111011111111111111111111111111110111111111111111111111* -L043146 010111111111111011111111110111111111111111111111111111111111111111* -L043212 000000000000000000000000000000000000000000000000000000000000000000* +L043014 111111011111111111111111111110111111111111111111111111111111111111* +L043080 111111011111111111111111111111111111101111111111111111111111111111* +L043146 111111011101111111111111111111111111111111111111111111111111111111* +L043212 111111101110111111111111111101111111011111111111111011111111111111* L043278 000000000000000000000000000000000000000000000000000000000000000000* L043344 000000000000000000000000000000000000000000000000000000000000000000* -L043410 011111111111111111111011111111111111111111111111111111111111111111* -L043476 111111111111111111111111111111111111111111111111111111111111111111* -L043542 111111111111111111111111111111111111111111111111111111111111111111* -L043608 111111111111111111111111111111111111111111111111111111111111111111* -L043674 111111111111111111111111111111111111111111111111111111111111111111* +L043410 111110111111111111111111111111111111101110011101111111111111111111* +L043476 111110111101111111111111111111111111111110011101111111111111111111* +L043542 111110111110111111111111111111111111011110011110111111111111111111* +L043608 111110111111111111111111111111111111111110010101111111111111111111* +L043674 000000000000000000000000000000000000000000000000000000000000000000* L043740 111111111111111111111111111111111111111111111111111111111111111111* L043806 111111111111111111111111111111111111111111111111111111111111111111* L043872 111111111111111111111111111111111111111111111111111111111111111111* @@ -890,47 +891,47 @@ L043938 111111111111111111111111111111111111111111111111111111111111111111* L044004 111111111111111111111111111111111111111111111111111111111111111111* L044070 111111111111111111111111111111111111111110111111111111111111111111* -L044136 101111111111111111111111111111111111111111111111111111111111111111* +L044136 111111111111111111111111111111111111111111101111111111111111111111* L044202 111111111111111101111111111111111111111110111111111111111111111111* L044268 000000000000000000000000000000000000000000000000000000000000000000* L044334 000000000000000000000000000000000000000000000000000000000000000000* L044400 000000000000000000000000000000000000000000000000000000000000000000* -L044466 111111111111111111111111111011111111111111111111111111011111111111* -L044532 111111111111110111111111111111111111111111111111111111011111111111* -L044598 111111111111111011111111110111111111111111111111111111101111111111* -L044664 000000000000000000000000000000000000000000000000000000000000000000* -L044730 000000000000000000000000000000000000000000000000000000000000000000* +L044466 111111111111111111111111111111111111111111101111111111111111111111* +L044532 111111111111110111111111111111111111111111111111111111111111111111* +L044598 111111111111111111111111111111111111111111111010111111111111111111* +L044664 111101111111111111111111111111111111111111111111111111111111111111* +L044730 111111111111101111111111111111111111111111110101111111111111111111* L044796 111111111111111111111111111111111111111110111111111111111111111111* -L044862 111111111111111111111111111111111111111111111111111111111111111111* -L044928 111111111111111111111111111111111111111111111111111111111111111111* -L044994 111111111111111111111111111111111111111111111111111111111111111111* -L045060 111111111111111111111111111111111111111111111111111111111111111111* -L045126 111111111111111111111111111111111111111111111111111111111111111111* -L045192 111111111111111111111111111111111111111111111111111111111111111111* -L045258 111111111111111111111111111111111111111111111111111111111111111111* -L045324 111111111111111111111111111111111111111111111111111111111111111111* -L045390 111111111111111111111111111111111111111111111111111111111111111111* -L045456 111111111111111111111111111111111111111111111111111111111111111111* +L044862 111110111110111111111111111111111111011110011101111111111111111111* +L044928 111110111111111111111111111111111111111110010111111111111111111111* +L044994 000000000000000000000000000000000000000000000000000000000000000000* +L045060 000000000000000000000000000000000000000000000000000000000000000000* +L045126 000000000000000000000000000000000000000000000000000000000000000000* +L045192 101111110111111111110111111111111111111111111111111111111111111111* +L045258 000000000000000000000000000000000000000000000000000000000000000000* +L045324 000000000000000000000000000000000000000000000000000000000000000000* +L045390 000000000000000000000000000000000000000000000000000000000000000000* +L045456 000000000000000000000000000000000000000000000000000000000000000000* L045522 111111111111111111111111111111111111111110111111111111111111111111* -L045588 011111111111111111111111111111111111111101111111111111111111111111* -L045654 011111111111111110111111111111111111111111111111101111111111111111* +L045588 111111111111111111111111111111111111111101011111111111111111111111* +L045654 111111111111111110111111111111111111111111011111101111111111111111* L045720 000000000000000000000000000000000000000000000000000000000000000000* L045786 000000000000000000000000000000000000000000000000000000000000000000* L045852 000000000000000000000000000000000000000000000000000000000000000000* -L045918 101111111111111111111111111111111111111111111111111111111111111111* -L045984 111111111110111111011111111111111111111111111111111111111111111111* -L046050 111111111101101111111111111101101111111111111111111111111111111111* -L046116 000000000000000000000000000000000000000000000000000000000000000000* -L046182 000000000000000000000000000000000000000000000000000000000000000000* +L045918 111111111111111111111111111111111111111111101111111111111111111111* +L045984 111111111111110111111111111111111111111111111111111111111111111111* +L046050 111111111111111111111111111111111111111111111010111111111111111111* +L046116 101111110111111111111111011111111111111111111111111111111111111111* +L046182 111101111111111111111111111111111111111111111111111111111111111111* L046248 000000000000000000000000000000000000000000000000000000000000000000* -L046314 111111111111111111111111111111111111111111111111111111111111111111* -L046380 111111111111111111111111111111111111111111111111111111111111111111* -L046446 111111111111111111111111111111111111111111111111111111111111111111* -L046512 111111111111111111111111111111111111111111111111111111111111111111* -L046578 111111111111111111111111111111111111111111111111111111111111111111* +L046314 111111111111101111111111111111111111111111110101111111111111111111* +L046380 000000000000000000000000000000000000000000000000000000000000000000* +L046446 000000000000000000000000000000000000000000000000000000000000000000* +L046512 000000000000000000000000000000000000000000000000000000000000000000* +L046578 000000000000000000000000000000000000000000000000000000000000000000* L046644 111111111111111111111111111111111111111111111111111111111111111111* L046710 111111111111111111111111111111111111111111111111111111111111111111* L046776 111111111111111111111111111111111111111111111111111111111111111111* @@ -946,46 +947,46 @@ L047138 11100110010101* L047152 11101011111111* L047166 10100011111000* L047180 10100110010010* -L047194 01010110010001* +L047194 10100110010001* L047208 11101011110011* L047222 10100110010000* L047236 10100110010011* -L047250 11010011110101* -L047264 11111011110011* +L047250 10100110010101* +L047264 11000011110011* L047278 11100110010010* L047292 10100110010010* -L047306 11011111110001* -L047320 11110011111111* +L047306 11111011110001* +L047320 11111111111111* NOTE BLOCK 7 * L047334 - 111111111111111111111111111111111111111111111111111111111111011111 + 111111111111111111110111111111111111111111111111111011111111111111 111111111111111110111111111111011111111111111111111111111111111111 - 111110111111111111111111111111111110111111111111111111111111111111 - 111011111111111111111111111011111111111111111111111111111111111011 + 111111111111111111111111111111111110111111111111111111111111111111 + 111011111111111111111111111011111111011111111110111111111111111111 111111111110111111111111111111111111111111111111111111111111111111 - 111111111111011011011111111111111111011111111111111111111111111111 - 111111110111111111111101111111111111111111111111010111111111111111 - 111111111111111111111111011111111111111110111111111111101111111110 - 101111111111111111111111111111111011110111111110111111111111111111* + 111111110111011111111111111111111111111111111111011111111111111111 + 011111011111111111111101111111111111111111111111111111111111110111 + 111111111111111011101111011111111111111110111111111111111111111111 + 111110111111111111111111111111111111110111101111111111111111101111* L047928 000000000000000000000000000000000000000000000000000000000000000000* -L047994 011101111111111111111111111111111111111111111110111111011111111111* -L048060 011101111111111111111111111111111111111111111110111011111111111111* -L048126 011101111110111111101111111111111111111111111110111111111111111111* -L048192 011101111101111110101111111111111111111111111111110111101111111111* +L047994 111111011111111111111111111111111111011111011111111111111111101111* +L048060 111111111110111111111111111111111111011111011111111111111111101111* +L048126 111111111111111111111011111111111111011111011111101111111111101111* +L048192 111111101101111110110111111111111111011111011111101111111111111111* L048258 000000000000000000000000000000000000000000000000000000000000000000* -L048324 110111111011101111111110110111111101011011111111111111111111111110* +L048324 110111110111101111101110110111111101111011111111111111111111111011* L048390 000000000000000000000000000000000000000000000000000000000000000000* L048456 000000000000000000000000000000000000000000000000000000000000000000* L048522 000000000000000000000000000000000000000000000000000000000000000000* L048588 000000000000000000000000000000000000000000000000000000000000000000* L048654 000000000000000000000000000000000000000000000000000000000000000000* -L048720 101111111111111111111111111111111111111111111111111111111111111111* -L048786 111111111111111111111111011111111111111111111111011111111111111111* -L048852 000000000000000000000000000000000000000000000000000000000000000000* -L048918 000000000000000000000000000000000000000000000000000000000000000000* -L048984 000000000000000000000000000000000000000000000000000000000000000000* +L048720 111111011111111111111111111111111111111111111111111111111111111111* +L048786 111111111111111111111111111111111111111111111111111111111111111111* +L048852 111111111111111111111111111111111111111111111111111111111111111111* +L048918 111111111111111111111111111111111111111111111111111111111111111111* +L048984 111111111111111111111111111111111111111111111111111111111111111111* L049050 111111111111111111111111111111111111111111111111111111111111111111* L049116 111111111111111111111111111111111111111111111111111111111111111111* L049182 111111111111111111111111111111111111111111111111111111111111111111* @@ -993,19 +994,19 @@ L049248 111111111111111111111111111111111111111111111111111111111111111111* L049314 111111111111111111111111111111111111111111111111111111111111111111* L049380 111111111111111111111111111111111111111111111111111111111111111111* -L049446 101111111111111111111111111111111111111111111111111111111111111111* -L049512 111111111111111111111111111111111111011101111111111111111111111111* -L049578 111111111111111111111111111111110111011111111111111011011111111111* +L049446 111111111111111111111111111111111111111111101111111111111111111111* +L049512 111111110111111111111111111111111111111101111111111111111111111111* +L049578 111101010110111111111111111111111111111111111111111111111111111111* L049644 000000000000000000000000000000000000000000000000000000000000000000* L049710 000000000000000000000000000000000000000000000000000000000000000000* -L049776 111111111111111111111111111111111111111111111111110111111111111111* +L049776 111111111111110111111111111111111111111111111111111111111111111111* L049842 111111111111111111111111111111111111111111111111111111111111111111* L049908 111111111111111111111111111111111111111111111111111111111111111111* L049974 111111111111111111111111111111111111111111111111111111111111111111* L050040 111111111111111111111111111111111111111111111111111111111111111111* L050106 111111111111111111111111111111111111111110111111111111111111111111* -L050172 111111111111111111111111111111111111111111111111111111011111111111* +L050172 111111111111111011111111111111111111111111111111111111111111111111* L050238 111111111111111111111111111111111111111111111111111111111111111111* L050304 111111111111111111111111111111111111111111111111111111111111111111* L050370 111111111111111111111111111111111111111111111111111111111111111111* @@ -1017,18 +1018,18 @@ L050700 111111111111111111111111111111111111111111111111111111111111111111* L050766 111111111111111111111111111111111111111111111111111111111111111111* L050832 111111111111111111111111111111011111111101111111111111111111111111* -L050898 111111111111111111111111111111111011111111111111111111111111101111* +L050898 111110111111111111111111111111111111111111111111111011111111111111* L050964 111111111111111111111111111111111111111111111111111111111111111111* L051030 111111111111111111111111111111111111111111111111111111111111111111* L051096 111111111111111111111111111111111111111111111111111111111111111111* L051162 111111111111111111111111111111111111111111111111111111111111111111* -L051228 111111111111111111111111111111111111111111111111111111111111111010* +L051228 111111111111111111101111111111111111111111111110111111111111111111* L051294 111111111111111111111111111111111111111111111111111111111111111111* L051360 111111111111111111111111111111111111111111111111111111111111111111* L051426 111111111111111111111111111111111111111111111111111111111111111111* L051492 111111111111111111111111111111111111111111111111111111111111111111* L051558 - 011111111111111111111111111111111111111101111111111111111111111111* + 111111111111111111111111111111111111111101011111111111111111111111* L051624 111111111111111111111111111111111111111111111111111111111111111111* L051690 111111111111111111111111111111111111111111111111111111111111111111* L051756 111111111111111111111111111111111111111111111111111111111111111111* @@ -1041,16 +1042,16 @@ L052152 111111111111111111111111111111111111111111111111111111111111111111* L052218 111111111111111111111111111111111111111111111111111111111111111111* L052284 111111111111111111111111111111111111111110111111111111111111111111* -L052350 101111111111111111111111111111111111111111111111111111111111111111* -L052416 111111111111111111111111101111111111111110111111101111111111111111* +L052350 111111111111111111111111111111111111111111101111111111111111111111* +L052416 101111111111111111111111101111111111111110111111111111111111111111* L052482 000000000000000000000000000000000000000000000000000000000000000000* L052548 000000000000000000000000000000000000000000000000000000000000000000* L052614 000000000000000000000000000000000000000000000000000000000000000000* -L052680 111111111111111011111111111111111111111111111111111111111111111111* -L052746 111111111111111111111111111111111111111111111111111111111111111111* -L052812 111111111111111111111111111111111111111111111111111111111111111111* -L052878 111111111111111111111111111111111111111111111111111111111111111111* -L052944 111111111111111111111111111111111111111111111111111111111111111111* +L052680 111111111111111111111111111111111111111111101111111111111111111111* +L052746 011111111111111111111111011111111111111111111111111111111111111111* +L052812 000000000000000000000000000000000000000000000000000000000000000000* +L052878 000000000000000000000000000000000000000000000000000000000000000000* +L052944 000000000000000000000000000000000000000000000000000000000000000000* L053010 111111111111111111111111111111111111111111111111111111111111111111* L053076 111111111111111111111111111111111111111111111111111111111111111111* @@ -1069,7 +1070,7 @@ L053736 L053868 0010* L053872 11100110011100* L053886 01101011110010* -L053900 10100110010001* +L053900 00010110010001* L053914 11101011110011* L053928 10100110010000* L053942 00000110011110* @@ -1080,7 +1081,7 @@ L053998 01000011111110* L054012 11011011110110* L054026 11111111110011* L054040 10100110010001* -L054054 00000110010011* +L054054 10100110010011* L054068 11010011111100* L054082 11111011111111* E1 @@ -1102,6 +1103,6 @@ E1 00000000 0 * -CFCEC* +C867E* U00000000000000000000000000000000* -85B5 +84FB diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index 921e29e..21b75fc 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; -DATE = 12/30/17; -TIME = 00:43:46; +DATE = 1/11/18; +TIME = 20:16:38; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -76,23 +76,26 @@ Usercode_Format = Hex; [LOCATION ASSIGNMENTS] Layer = OFF; +AHIGH_30_ = pin,5,-,B,-; +AHIGH_31_ = pin,4,-,B,-; +AHIGH_29_ = pin,6,-,B,-; +AHIGH_28_ = pin,15,-,C,-; +A_DECODE_23_ = pin,85,-,H,-; AHIGH_27_ = pin,16,-,C,-; AHIGH_26_ = pin,17,-,C,-; AHIGH_25_ = pin,18,-,C,-; AHIGH_24_ = pin,19,-,C,-; -AHIGH_31_ = pin,4,-,B,-; A_DECODE_22_ = pin,84,-,H,-; A_DECODE_21_ = pin,94,-,A,-; -A_DECODE_23_ = pin,85,-,H,-; +IPL_2_ = pin,68,-,G,-; A_DECODE_20_ = pin,93,-,A,-; A_DECODE_19_ = pin,97,-,A,-; -A_DECODE_18_ = pin,95,-,A,-; -A_DECODE_17_ = pin,59,-,F,-; -A_DECODE_16_ = pin,96,-,A,-; -IPL_2_ = pin,68,-,G,-; FC_1_ = pin,58,-,F,-; +A_DECODE_18_ = pin,95,-,A,-; AS_030 = pin,82,-,H,-; +A_DECODE_17_ = pin,59,-,F,-; AS_000 = pin,42,-,E,-; +A_DECODE_16_ = pin,96,-,A,-; DS_030 = pin,98,-,A,-; UDS_000 = pin,32,-,D,-; LDS_000 = pin,31,-,D,-; @@ -101,19 +104,19 @@ BERR = pin,41,-,E,-; BG_030 = pin,21,-,C,-; BGACK_000 = pin,28,-,D,-; CLK_000 = pin,11,-,-,-; -IPL_1_ = pin,56,-,F,-; CLK_OSZI = pin,61,-,-,-; -IPL_0_ = pin,67,-,G,-; CLK_DIV_OUT = pin,65,-,G,-; -FC_0_ = pin,57,-,F,-; CLK_EXP = pin,10,-,B,-; -A_1_ = pin,60,-,F,-; FPU_CS = pin,78,-,H,-; FPU_SENSE = pin,91,-,A,-; DSACK1 = pin,81,-,H,-; +IPL_1_ = pin,56,-,F,-; DTACK = pin,30,-,D,-; +IPL_0_ = pin,67,-,G,-; AVEC = pin,92,-,A,-; +FC_0_ = pin,57,-,F,-; E = pin,66,-,G,-; +A_1_ = pin,60,-,F,-; VPA = pin,36,-,-,-; RST = pin,86,-,-,-; AMIGA_ADDR_ENABLE = pin,33,-,D,-; @@ -121,10 +124,8 @@ AMIGA_BUS_DATA_DIR = pin,48,-,E,-; AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-; CIIN = pin,47,-,E,-; -AHIGH_30_ = pin,5,-,B,-; -AHIGH_29_ = pin,6,-,B,-; -AHIGH_28_ = pin,15,-,C,-; SIZE_1_ = pin,79,-,H,-; +SIZE_0_ = pin,70,-,G,-; IPL_030_2_ = pin,9,-,B,-; RW_000 = pin,80,-,H,-; BG_000 = pin,29,-,D,-; @@ -134,49 +135,48 @@ IPL_030_1_ = pin,7,-,B,-; IPL_030_0_ = pin,8,-,B,-; VMA = pin,35,-,D,-; RW = pin,71,-,G,-; -SIZE_0_ = pin,70,-,G,-; -cpu_est_0_ = node,-,-,G,9; -cpu_est_1_ = node,-,-,D,13; -cpu_est_2_ = node,-,-,D,2; -cpu_est_3_ = node,-,-,A,8; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,A,10; -inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,C,10; -inst_AS_030_D0 = node,-,-,E,8; +cpu_est_0_ = node,-,-,F,4; +cpu_est_1_ = node,-,-,G,5; +cpu_est_2_ = node,-,-,D,13; +cpu_est_3_ = node,-,-,D,9; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,E,9; +inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,E,8; +inst_AS_030_D0 = node,-,-,F,12; inst_AS_030_D1 = node,-,-,F,1; -inst_AS_030_000_SYNC = node,-,-,F,4; -inst_AS_000_DMA = node,-,-,C,13; -inst_DS_000_DMA = node,-,-,C,9; -inst_VPA_D = node,-,-,G,6; -CLK_000_D_3_ = node,-,-,F,13; -inst_DTACK_D0 = node,-,-,F,9; -inst_AMIGA_DS = node,-,-,H,2; -CLK_000_D_1_ = node,-,-,H,5; -CLK_000_D_0_ = node,-,-,D,9; -inst_CLK_OUT_PRE_50 = node,-,-,H,13; -inst_CLK_OUT_PRE_D = node,-,-,E,5; -IPL_D0_0_ = node,-,-,A,6; -IPL_D0_1_ = node,-,-,D,6; -IPL_D0_2_ = node,-,-,A,2; -CLK_000_D_2_ = node,-,-,H,6; +inst_AS_030_000_SYNC = node,-,-,F,8; +inst_AS_000_DMA = node,-,-,G,13; +inst_DS_000_DMA = node,-,-,G,9; +inst_VPA_D = node,-,-,B,6; +CLK_000_D_3_ = node,-,-,D,2; +inst_DTACK_D0 = node,-,-,F,13; +inst_AMIGA_DS = node,-,-,H,13; +CLK_000_D_1_ = node,-,-,A,8; +CLK_000_D_0_ = node,-,-,F,0; +inst_CLK_OUT_PRE_50 = node,-,-,H,6; +inst_CLK_OUT_PRE_D = node,-,-,H,5; +IPL_D0_0_ = node,-,-,F,9; +IPL_D0_1_ = node,-,-,A,10; +IPL_D0_2_ = node,-,-,C,6; +CLK_000_D_2_ = node,-,-,H,2; CLK_000_D_4_ = node,-,-,F,5; -inst_UDS_000_INT = node,-,-,B,6; -inst_DS_000_ENABLE = node,-,-,C,2; -inst_LDS_000_INT = node,-,-,G,13; +inst_UDS_000_INT = node,-,-,D,6; +inst_DS_000_ENABLE = node,-,-,A,13; +inst_LDS_000_INT = node,-,-,A,9; inst_BGACK_030_INT_D = node,-,-,E,13; -SM_AMIGA_6_ = node,-,-,F,0; -SM_AMIGA_4_ = node,-,-,G,5; -SM_AMIGA_1_ = node,-,-,A,5; +SM_AMIGA_6_ = node,-,-,B,13; +SM_AMIGA_4_ = node,-,-,A,5; +SM_AMIGA_1_ = node,-,-,A,1; SM_AMIGA_0_ = node,-,-,A,12; -CYCLE_DMA_0_ = node,-,-,B,13; -CYCLE_DMA_1_ = node,-,-,B,2; +CYCLE_DMA_0_ = node,-,-,G,6; +CYCLE_DMA_1_ = node,-,-,G,10; inst_DSACK1_INT = node,-,-,G,2; -inst_AS_000_INT = node,-,-,C,6; -SM_AMIGA_5_ = node,-,-,F,12; -SM_AMIGA_3_ = node,-,-,A,13; -SM_AMIGA_2_ = node,-,-,A,9; -CLK_OUT_INTreg = node,-,-,A,1; -SM_AMIGA_i_7_ = node,-,-,F,8; -N_60 = node,-,-,E,9; +inst_AS_000_INT = node,-,-,C,13; +SM_AMIGA_5_ = node,-,-,A,6; +SM_AMIGA_3_ = node,-,-,C,2; +SM_AMIGA_2_ = node,-,-,C,9; +CLK_OUT_INTreg = node,-,-,A,2; +SM_AMIGA_i_7_ = node,-,-,B,2; +N_205 = node,-,-,E,5; [GROUP ASSIGNMENTS] Layer = OFF; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index 5c8093c..3885962 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -1711,4 +1711,118 @@ 35 VPA 1 -1 -1 1 6 35 -1 29 DTACK 1 -1 -1 1 5 29 -1 20 BG_030 1 -1 -1 1 3 20 -1 - 10 CLK_000 1 -1 -1 1 3 10 -1 \ No newline at end of file + 10 CLK_000 1 -1 -1 1 3 10 -1 +108 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 81 AS_030 5 -1 7 7 0 2 3 4 5 6 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21 + 79 RW_000 5 336 7 2 4 6 79 -1 4 0 21 + 68 A_0_ 5 -1 6 2 0 3 68 -1 2 0 21 + 70 RW 5 -1 6 2 0 7 70 -1 1 0 21 + 31 UDS_000 5 -1 3 2 6 7 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 6 7 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 2 0 21 + 40 BERR 5 -1 4 1 2 40 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 335 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 340 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 339 1 0 6 -1 10 0 21 + 82 BGACK_030 5 338 7 0 82 -1 3 0 21 + 34 VMA 5 341 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 337 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 80 DSACK1 0 7 0 80 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 338 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 309 CLK_000_D_0_ 3 -1 5 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 308 CLK_000_D_1_ 3 -1 0 7 0 1 2 3 5 6 7 -1 -1 1 0 21 + 321 SM_AMIGA_6_ 3 -1 1 5 0 1 2 3 7 -1 -1 3 0 21 + 293 cpu_est_0_ 3 -1 5 4 2 3 5 6 -1 -1 3 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 3 1 3 5 -1 -1 7 0 21 + 296 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 294 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 4 0 21 + 333 SM_AMIGA_i_7_ 3 -1 1 3 1 5 7 -1 -1 3 1 21 + 324 SM_AMIGA_0_ 3 -1 0 3 0 1 7 -1 -1 3 0 21 + 299 inst_AS_030_D0 3 -1 5 3 3 4 5 -1 -1 1 0 21 + 295 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 1 1 21 + 303 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 6 0 21 + 302 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 6 0 21 + 331 SM_AMIGA_2_ 3 -1 2 2 0 2 -1 -1 5 0 21 + 341 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 323 SM_AMIGA_1_ 3 -1 0 2 0 6 -1 -1 3 0 21 + 322 SM_AMIGA_4_ 3 -1 0 2 0 2 -1 -1 3 0 21 + 319 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 318 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 3 0 21 + 328 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 327 inst_DSACK1_INT 3 -1 6 2 6 7 -1 -1 2 0 21 + 332 CLK_OUT_INTreg 3 -1 0 2 1 6 -1 -1 1 0 21 + 311 inst_CLK_OUT_PRE_D 3 -1 7 2 0 6 -1 -1 1 0 21 + 305 CLK_000_D_3_ 3 -1 3 2 1 5 -1 -1 1 0 21 + 304 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21 + 340 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 339 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 335 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 330 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 336 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 325 CYCLE_DMA_0_ 3 -1 6 1 6 -1 -1 4 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 4 1 2 -1 -1 4 0 21 + 329 SM_AMIGA_5_ 3 -1 0 1 0 -1 -1 3 0 21 + 337 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 334 N_205 3 -1 4 1 4 -1 -1 2 0 21 + 326 CYCLE_DMA_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 317 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 307 inst_AMIGA_DS 3 -1 7 1 6 -1 -1 2 0 21 + 300 inst_AS_030_D1 3 -1 5 1 5 -1 -1 2 0 21 + 297 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 4 1 3 -1 -1 2 0 21 + 320 inst_BGACK_030_INT_D 3 -1 4 1 5 -1 -1 1 0 21 + 316 CLK_000_D_4_ 3 -1 5 1 1 -1 -1 1 0 21 + 315 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 + 314 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 313 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 312 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 310 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 + 306 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 1 3 4 5 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 59 A_1_ 1 -1 -1 1 4 59 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 5 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 5 10 -1 \ No newline at end of file diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index 0ace62c..a4448dc 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,26 +8,29 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Sat Dec 30 00:43:46 2017 +; DATE Thu Jan 11 20:16:38 2018 +Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125 +Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143 +Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 137 +Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149 +Pin 85 A_DECODE_23_ Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 157 Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 155 Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167 Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161 -Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143 Pin 84 A_DECODE_22_ Pin 94 A_DECODE_21_ -Pin 85 A_DECODE_23_ +Pin 68 IPL_2_ Pin 93 A_DECODE_20_ Pin 97 A_DECODE_19_ -Pin 95 A_DECODE_18_ -Pin 59 A_DECODE_17_ -Pin 96 A_DECODE_16_ -Pin 68 IPL_2_ Pin 58 FC_1_ +Pin 95 A_DECODE_18_ Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281 +Pin 59 A_DECODE_17_ Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203 +Pin 96 A_DECODE_16_ Pin 98 DS_030 Comb ; S6=1 S9=1 Pair 101 Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185 Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191 @@ -36,19 +39,19 @@ Pin 41 BERR Comb ; S6=1 S9=1 Pair 197 Pin 21 BG_030 Pin 28 BGACK_000 Pin 11 CLK_000 -Pin 56 IPL_1_ Pin 61 CLK_OSZI -Pin 67 IPL_0_ Pin 65 CLK_DIV_OUT Comb ; S6=1 S9=1 Pair 247 -Pin 57 FC_0_ Pin 10 CLK_EXP Comb ; S6=1 S9=1 Pair 127 -Pin 60 A_1_ Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271 Pin 91 FPU_SENSE Pin 81 DSACK1 Comb ; S6=1 S9=1 Pair 283 +Pin 56 IPL_1_ Pin 30 DTACK +Pin 67 IPL_0_ Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 +Pin 57 FC_0_ Pin 66 E Comb ; S6=1 S9=1 Pair 251 +Pin 60 A_1_ Pin 36 VPA Pin 86 RST Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 181 @@ -56,10 +59,8 @@ Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199 Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 151 Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 179 Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 -Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125 -Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 137 -Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149 Pin 79 SIZE_1_ Reg ; S6=1 S9=1 Pair 287 +Pin 70 SIZE_0_ Reg ; S6=1 S9=1 Pair 263 Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131 Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269 Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175 @@ -69,21 +70,21 @@ Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 139 Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 133 Pin 35 VMA Reg ; S6=1 S9=1 Pair 173 Pin 71 RW Reg ; S6=1 S9=1 Pair 245 -Pin 70 SIZE_0_ Reg ; S6=1 S9=1 Pair 263 +Node 125 RN_AHIGH_30_ Comb ; S6=1 S9=1 +Node 143 RN_AHIGH_31_ Comb ; S6=1 S9=1 +Node 137 RN_AHIGH_29_ Comb ; S6=1 S9=1 +Node 149 RN_AHIGH_28_ Comb ; S6=1 S9=1 Node 157 RN_AHIGH_27_ Comb ; S6=1 S9=1 Node 155 RN_AHIGH_26_ Comb ; S6=1 S9=1 Node 167 RN_AHIGH_25_ Comb ; S6=1 S9=1 Node 161 RN_AHIGH_24_ Comb ; S6=1 S9=1 -Node 143 RN_AHIGH_31_ Comb ; S6=1 S9=1 Node 281 RN_AS_030 Comb ; S6=1 S9=1 Node 203 RN_AS_000 Comb ; S6=1 S9=1 Node 185 RN_UDS_000 Comb ; S6=1 S9=1 Node 191 RN_LDS_000 Comb ; S6=1 S9=1 Node 197 RN_BERR Comb ; S6=1 S9=1 -Node 125 RN_AHIGH_30_ Comb ; S6=1 S9=1 -Node 137 RN_AHIGH_29_ Comb ; S6=1 S9=1 -Node 149 RN_AHIGH_28_ Comb ; S6=1 S9=1 Node 287 RN_SIZE_1_ Reg ; S6=1 S9=1 +Node 263 RN_SIZE_0_ Reg ; S6=1 S9=1 Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1 Node 269 RN_RW_000 Reg ; S6=1 S9=1 Node 175 RN_BG_000 Reg ; S6=1 S9=1 @@ -93,48 +94,47 @@ Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1 Node 133 RN_IPL_030_0_ Reg ; S6=1 S9=1 Node 173 RN_VMA Reg ; S6=1 S9=1 Node 245 RN_RW Reg ; S6=1 S9=1 -Node 263 RN_SIZE_0_ Reg ; S6=1 S9=1 -Node 259 cpu_est_0_ Reg ; S6=1 S9=1 -Node 193 cpu_est_1_ Reg ; S6=1 S9=1 -Node 176 cpu_est_2_ Reg ; S6=1 S9=1 -Node 113 cpu_est_3_ Reg ; S6=1 S9=1 -Node 116 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 -Node 164 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 -Node 209 inst_AS_030_D0 Reg ; S6=1 S9=1 +Node 227 cpu_est_0_ Reg ; S6=1 S9=1 +Node 253 cpu_est_1_ Reg ; S6=1 S9=1 +Node 193 cpu_est_2_ Reg ; S6=1 S9=1 +Node 187 cpu_est_3_ Reg ; S6=1 S9=1 +Node 211 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 +Node 209 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 +Node 239 inst_AS_030_D0 Reg ; S6=1 S9=1 Node 223 inst_AS_030_D1 Reg ; S6=1 S9=1 -Node 227 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 -Node 169 inst_AS_000_DMA Reg ; S6=1 S9=1 -Node 163 inst_DS_000_DMA Reg ; S6=1 S9=1 -Node 254 inst_VPA_D Reg ; S6=1 S9=1 -Node 241 CLK_000_D_3_ Reg ; S6=1 S9=1 -Node 235 inst_DTACK_D0 Reg ; S6=1 S9=1 -Node 272 inst_AMIGA_DS Reg ; S6=1 S9=1 -Node 277 CLK_000_D_1_ Reg ; S6=1 S9=1 -Node 187 CLK_000_D_0_ Reg ; S6=1 S9=1 -Node 289 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 -Node 205 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 -Node 110 IPL_D0_0_ Reg ; S6=1 S9=1 -Node 182 IPL_D0_1_ Reg ; S6=1 S9=1 -Node 104 IPL_D0_2_ Reg ; S6=1 S9=1 -Node 278 CLK_000_D_2_ Reg ; S6=1 S9=1 +Node 233 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 265 inst_AS_000_DMA Reg ; S6=1 S9=1 +Node 259 inst_DS_000_DMA Reg ; S6=1 S9=1 +Node 134 inst_VPA_D Reg ; S6=1 S9=1 +Node 176 CLK_000_D_3_ Reg ; S6=1 S9=1 +Node 241 inst_DTACK_D0 Reg ; S6=1 S9=1 +Node 289 inst_AMIGA_DS Reg ; S6=1 S9=1 +Node 113 CLK_000_D_1_ Reg ; S6=1 S9=1 +Node 221 CLK_000_D_0_ Reg ; S6=1 S9=1 +Node 278 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 +Node 277 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 +Node 235 IPL_D0_0_ Reg ; S6=1 S9=1 +Node 116 IPL_D0_1_ Reg ; S6=1 S9=1 +Node 158 IPL_D0_2_ Reg ; S6=1 S9=1 +Node 272 CLK_000_D_2_ Reg ; S6=1 S9=1 Node 229 CLK_000_D_4_ Reg ; S6=1 S9=1 -Node 134 inst_UDS_000_INT Reg ; S6=1 S9=1 -Node 152 inst_DS_000_ENABLE Reg ; S6=1 S9=1 -Node 265 inst_LDS_000_INT Reg ; S6=1 S9=1 +Node 182 inst_UDS_000_INT Reg ; S6=1 S9=1 +Node 121 inst_DS_000_ENABLE Reg ; S6=1 S9=1 +Node 115 inst_LDS_000_INT Reg ; S6=1 S9=1 Node 217 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 -Node 221 SM_AMIGA_6_ Reg ; S6=1 S9=1 -Node 253 SM_AMIGA_4_ Reg ; S6=1 S9=1 -Node 109 SM_AMIGA_1_ Reg ; S6=1 S9=1 +Node 145 SM_AMIGA_6_ Reg ; S6=1 S9=1 +Node 109 SM_AMIGA_4_ Reg ; S6=1 S9=1 +Node 103 SM_AMIGA_1_ Reg ; S6=1 S9=1 Node 119 SM_AMIGA_0_ Reg ; S6=1 S9=1 -Node 145 CYCLE_DMA_0_ Reg ; S6=1 S9=1 -Node 128 CYCLE_DMA_1_ Reg ; S6=1 S9=1 +Node 254 CYCLE_DMA_0_ Reg ; S6=1 S9=1 +Node 260 CYCLE_DMA_1_ Reg ; S6=1 S9=1 Node 248 inst_DSACK1_INT Reg ; S6=1 S9=1 -Node 158 inst_AS_000_INT Reg ; S6=1 S9=1 -Node 239 SM_AMIGA_5_ Reg ; S6=1 S9=1 -Node 121 SM_AMIGA_3_ Reg ; S6=1 S9=1 -Node 115 SM_AMIGA_2_ Reg ; S6=1 S9=1 -Node 103 CLK_OUT_INTreg Reg ; S6=1 S9=1 -Node 233 SM_AMIGA_i_7_ Reg ; S6=1 S9=1 -Node 211 N_60 Comb ; S6=1 S9=1 +Node 169 inst_AS_000_INT Reg ; S6=1 S9=1 +Node 110 SM_AMIGA_5_ Reg ; S6=1 S9=1 +Node 152 SM_AMIGA_3_ Reg ; S6=1 S9=1 +Node 163 SM_AMIGA_2_ Reg ; S6=1 S9=1 +Node 104 CLK_OUT_INTreg Reg ; S6=1 S9=1 +Node 128 SM_AMIGA_i_7_ Reg ; S6=1 S9=1 +Node 205 N_205 Comb ; S6=1 S9=1 ; Unused Pins & Nodes ; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index 6fc95fa..1e2c78b 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Sat Dec 30 00:43:46 2017 -End : Sat Dec 30 00:43:46 2017 $$$ Elapsed time: 00:00:00 +Start: Thu Jan 11 20:16:38 2018 +End : Thu Jan 11 20:16:38 2018 $$$ Elapsed time: 00:00:00 =========================================================================== Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] @@ -21,16 +21,16 @@ Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 11 | 11 => 100% | 8 | 8 => 100% | 33 | 23 => 69% - 1 | 16 | 10 | 10 => 100% | 8 | 7 => 87% | 33 | 20 => 60% - 2 | 16 | 11 | 11 => 100% | 8 | 7 => 87% | 33 | 21 => 63% - 3 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 22 => 66% + 0 | 16 | 11 | 11 => 100% | 8 | 8 => 100% | 33 | 21 => 63% + 1 | 16 | 10 | 10 => 100% | 8 | 7 => 87% | 33 | 22 => 66% + 2 | 16 | 10 | 10 => 100% | 8 | 7 => 87% | 33 | 20 => 60% + 3 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 23 => 69% 4 | 16 | 8 | 8 => 100% | 8 | 4 => 50% | 33 | 30 => 90% - 5 | 16 | 8 | 8 => 100% | 8 | 5 => 62% | 33 | 24 => 72% - 6 | 16 | 10 | 10 => 100% | 8 | 7 => 87% | 33 | 23 => 69% + 5 | 16 | 8 | 8 => 100% | 8 | 5 => 62% | 33 | 22 => 66% + 6 | 16 | 11 | 11 => 100% | 8 | 7 => 87% | 33 | 22 => 66% 7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 25 => 75% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 23.50 => 71% + | Avg number of array inputs in used blocks : 23.13 => 70% * Input/Clock Signal count: 23 -> placed: 23 = 100% @@ -42,8 +42,8 @@ _|____|____|____|_______________|____|_____________|___|________________ Clock/Input Pins : 4 3 => 75% Logic Blocks : 8 8 => 100% Macrocells : 128 78 => 60% - PT Clusters : 128 44 => 34% - - Single PT Clusters : 128 40 => 31% + PT Clusters : 128 48 => 37% + - Single PT Clusters : 128 38 => 29% Input Registers : 0 * Routing Completion: 100% @@ -69,11 +69,11 @@ ___|__|__|____|____________________________________________________________ 10| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR 11| 3|OUT| 34|=> ....|....| AMIGA_BUS_ENABLE_HIGH 12| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW - 13| 4| IO| 42|=> 012.|4..7| AS_000 - 14| 7| IO| 82|=> ..23|4567| AS_030 + 13| 4| IO| 42|=> 0...|4.67| AS_000 + 14| 7| IO| 82|=> 0.23|4567| AS_030 15| 0|OUT| 92|=> ....|....| AVEC - 16| 6| IO| 69|=> .1..|..6.| A_0_ - 17| 5|INP| 60|=> 0.2.|....| A_1_ + 16| 6| IO| 69|=> 0..3|....| A_0_ + 17| 5|INP| 60|=> ....|4...| A_1_ 18| 0|INP| 96|=> ....|45.7| A_DECODE_16_ 19| 5|INP| 59|=> ....|45.7| A_DECODE_17_ 20| 0|INP| 95|=> ....|45.7| A_DECODE_18_ @@ -82,7 +82,7 @@ ___|__|__|____|____________________________________________________________ 23| 0|INP| 94|=> ....|4...| A_DECODE_21_ 24| 7|INP| 84|=> ....|4...| A_DECODE_22_ 25| 7|INP| 85|=> ....|4...| A_DECODE_23_ - 26| 4| IO| 41|=> 0...|....| BERR + 26| 4| IO| 41|=> ..2.|....| BERR 27| 3|INP| 28|=> ....|4..7| BGACK_000 28| 7| IO| 83|=> ....|....| BGACK_030 |=> Paired w/: RN_BGACK_030 @@ -90,18 +90,18 @@ ___|__|__|____|____________________________________________________________ |=> Paired w/: RN_BG_000 30| 2|INP| 21|=> ...3|....| BG_030 31| 4|OUT| 47|=> ....|....| CIIN - 32| +|INP| 11|=> ...3|....| CLK_000 - 33| 3|NOD| . |=> 0123|.567| CLK_000_D_0_ - 34| 7|NOD| . |=> 0123|.567| CLK_000_D_1_ - 35| 7|NOD| . |=> ....|.5..| CLK_000_D_2_ - 36| 5|NOD| . |=> ....|.5..| CLK_000_D_3_ - 37| 5|NOD| . |=> ....|.5..| CLK_000_D_4_ + 32| +|INP| 11|=> ....|.5..| CLK_000 + 33| 5|NOD| . |=> 0123|.567| CLK_000_D_0_ + 34| 0|NOD| . |=> 0123|.567| CLK_000_D_1_ + 35| 7|NOD| . |=> ...3|....| CLK_000_D_2_ + 36| 3|NOD| . |=> .1..|.5..| CLK_000_D_3_ + 37| 5|NOD| . |=> .1..|....| CLK_000_D_4_ 38| 6|OUT| 65|=> ....|....| CLK_DIV_OUT 39| 1|OUT| 10|=> ....|....| CLK_EXP 40| +|Cin| 61|=> ....|....| CLK_OSZI - 41| 0|NOD| . |=> .12.|..6.| CLK_OUT_INTreg - 42| 1|NOD| . |=> .12.|....| CYCLE_DMA_0_ - 43| 1|NOD| . |=> .12.|....| CYCLE_DMA_1_ + 41| 0|NOD| . |=> .1..|..6.| CLK_OUT_INTreg + 42| 6|NOD| . |=> ....|..6.| CYCLE_DMA_0_ + 43| 6|NOD| . |=> ....|..6.| CYCLE_DMA_1_ 44| 7|OUT| 81|=> ....|....| DSACK1 45| 0|OUT| 98|=> ....|....| DS_030 46| 3|INP| 30|=> ....|.5..| DTACK @@ -116,14 +116,14 @@ ___|__|__|____|____________________________________________________________ |=> Paired w/: RN_IPL_030_1_ 54| 1| IO| 9|=> ....|....| IPL_030_2_ |=> Paired w/: RN_IPL_030_2_ - 55| 6|INP| 67|=> 01..|....| IPL_0_ - 56| 5|INP| 56|=> .1.3|....| IPL_1_ - 57| 6|INP| 68|=> 01..|....| IPL_2_ - 58| 0|NOD| . |=> .1..|....| IPL_D0_0_ - 59| 3|NOD| . |=> .1..|....| IPL_D0_1_ - 60| 0|NOD| . |=> .1..|....| IPL_D0_2_ + 55| 6|INP| 67|=> .1..|.5..| IPL_0_ + 56| 5|INP| 56|=> 01..|....| IPL_1_ + 57| 6|INP| 68|=> .12.|....| IPL_2_ + 58| 5|NOD| . |=> .1..|....| IPL_D0_0_ + 59| 0|NOD| . |=> .1..|....| IPL_D0_1_ + 60| 2|NOD| . |=> .1..|....| IPL_D0_2_ 61| 3| IO| 31|=> ....|..67| LDS_000 - 62| 4|NOD| . |=> ....|4...| N_60 + 62| 4|NOD| . |=> ....|4...| N_205 63| 7|NOD| . |=> 0123|4567| RN_BGACK_030 |=> Paired w/: BGACK_030 64| 3|NOD| . |=> ...3|....| RN_BG_000 @@ -136,49 +136,49 @@ ___|__|__|____|____________________________________________________________ |=> Paired w/: IPL_030_2_ 68| 7|NOD| . |=> ....|...7| RN_RW_000 |=> Paired w/: RW_000 - 69| 3|NOD| . |=> 0..3|....| RN_VMA + 69| 3|NOD| . |=> ..23|....| RN_VMA |=> Paired w/: VMA 70| +|INP| 86|=> 0123|4567| RST - 71| 6| IO| 71|=> ..2.|...7| RW - 72| 7| IO| 80|=> ..2.|4.6.| RW_000 + 71| 6| IO| 71|=> 0...|...7| RW + 72| 7| IO| 80|=> ....|4.6.| RW_000 |=> Paired w/: RN_RW_000 - 73| 6| IO| 70|=> ....|..6.| SIZE_0_ - 74| 7| IO| 79|=> ....|..6.| SIZE_1_ - 75| 0|NOD| . |=> 0...|.5.7| SM_AMIGA_0_ + 73| 6| IO| 70|=> 0...|....| SIZE_0_ + 74| 7| IO| 79|=> 0...|....| SIZE_1_ + 75| 0|NOD| . |=> 01..|...7| SM_AMIGA_0_ 76| 0|NOD| . |=> 0...|..6.| SM_AMIGA_1_ - 77| 0|NOD| . |=> 0...|....| SM_AMIGA_2_ - 78| 0|NOD| . |=> 0...|....| SM_AMIGA_3_ - 79| 6|NOD| . |=> 0.2.|..6.| SM_AMIGA_4_ - 80| 5|NOD| . |=> ....|.56.| SM_AMIGA_5_ - 81| 5|NOD| . |=> .12.|.567| SM_AMIGA_6_ - 82| 5|NOD| . |=> ....|.5.7| SM_AMIGA_i_7_ + 77| 2|NOD| . |=> 0.2.|....| SM_AMIGA_2_ + 78| 2|NOD| . |=> ..2.|....| SM_AMIGA_3_ + 79| 0|NOD| . |=> 0.2.|....| SM_AMIGA_4_ + 80| 0|NOD| . |=> 0...|....| SM_AMIGA_5_ + 81| 1|NOD| . |=> 0123|...7| SM_AMIGA_6_ + 82| 1|NOD| . |=> .1..|.5.7| SM_AMIGA_i_7_ 83| 3| IO| 32|=> ....|..67| UDS_000 84| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 85| +|INP| 36|=> ....|..6.| VPA - 86| 6|NOD| . |=> 0..3|..6.| cpu_est_0_ - 87| 3|NOD| . |=> 0..3|..6.| cpu_est_1_ - 88| 3|NOD| . |=> 0..3|..6.| cpu_est_2_ - 89| 0|NOD| . |=> 0..3|..6.| cpu_est_3_ - 90| 0|NOD| . |=> ...3|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH - 91| 2|NOD| . |=> ..2.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW - 92| 7|NOD| . |=> ..2.|....| inst_AMIGA_DS - 93| 2|NOD| . |=> ..2.|...7| inst_AS_000_DMA + 85| +|INP| 36|=> .1..|....| VPA + 86| 5|NOD| . |=> ..23|.56.| cpu_est_0_ + 87| 6|NOD| . |=> ..23|..6.| cpu_est_1_ + 88| 3|NOD| . |=> ..23|..6.| cpu_est_2_ + 89| 3|NOD| . |=> ..23|..6.| cpu_est_3_ + 90| 4|NOD| . |=> ...3|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH + 91| 4|NOD| . |=> ..2.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW + 92| 7|NOD| . |=> ....|..6.| inst_AMIGA_DS + 93| 6|NOD| . |=> ....|..67| inst_AS_000_DMA 94| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT - 95| 5|NOD| . |=> ...3|.5..| inst_AS_030_000_SYNC - 96| 4|NOD| . |=> ...3|45..| inst_AS_030_D0 + 95| 5|NOD| . |=> .1.3|.5..| inst_AS_030_000_SYNC + 96| 5|NOD| . |=> ...3|45..| inst_AS_030_D0 97| 5|NOD| . |=> ....|.5..| inst_AS_030_D1 98| 4|NOD| . |=> ....|.5..| inst_BGACK_030_INT_D - 99| 7|NOD| . |=> ....|4..7| inst_CLK_OUT_PRE_50 - 100| 4|NOD| . |=> 0.2.|....| inst_CLK_OUT_PRE_D + 99| 7|NOD| . |=> ....|...7| inst_CLK_OUT_PRE_50 + 100| 7|NOD| . |=> 0...|..6.| inst_CLK_OUT_PRE_D 101| 6|NOD| . |=> ....|..67| inst_DSACK1_INT - 102| 2|NOD| . |=> 0.2.|....| inst_DS_000_DMA - 103| 2|NOD| . |=> ..23|....| inst_DS_000_ENABLE - 104| 5|NOD| . |=> 0...|....| inst_DTACK_D0 - 105| 6|NOD| . |=> ...3|..6.| inst_LDS_000_INT - 106| 1|NOD| . |=> .1.3|....| inst_UDS_000_INT - 107| 6|NOD| . |=> 0..3|....| inst_VPA_D - 108| +|INP| 14|=> ...3|45.7| nEXP_SPACE + 102| 6|NOD| . |=> 0...|..6.| inst_DS_000_DMA + 103| 0|NOD| . |=> 0..3|....| inst_DS_000_ENABLE + 104| 5|NOD| . |=> ..2.|....| inst_DTACK_D0 + 105| 0|NOD| . |=> 0..3|....| inst_LDS_000_INT + 106| 3|NOD| . |=> ...3|....| inst_UDS_000_INT + 107| 1|NOD| . |=> ..23|....| inst_VPA_D + 108| +|INP| 14|=> .1.3|45.7| nEXP_SPACE --------------------------------------------------------------------------- =========================================================================== < E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a Device Pin Assignments > @@ -299,19 +299,19 @@ ____|_____|_________|______________________________________________________ | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| DS_030|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1|CLK_OUT_INTreg|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 1| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 1]| 1 XOR free + 2|CLK_OUT_INTreg|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig 3| | ? | | S | | 4 free | 1 XOR free 4| AVEC|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free - 6| IPL_D0_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 5| SM_AMIGA_4_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free + 6| SM_AMIGA_5_|NOD| | S | 3 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| cpu_est_3_|NOD| | S | 4 | 4 to [ 8]| 1 XOR free - 9| SM_AMIGA_2_|NOD| | S | 5 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -10|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig + 8| CLK_000_D_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9|inst_LDS_000_INT|NOD| | S | 3 | 4 to [ 9]| 1 XOR free +10| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig 11| | ? | | S | | 4 free | 1 XOR free 12| SM_AMIGA_0_|NOD| | S | 3 | 4 to [12]| 1 XOR free -13| SM_AMIGA_3_|NOD| | S | 5 | 4 to [13]| 1 XOR to [13] as logic PT +13|inst_DS_000_ENABLE|NOD| | S | 3 | 4 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -325,20 +325,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| DS_030|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) - 1|CLK_OUT_INTreg|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) - 2| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 0| DS_030|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) + 1| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) + 2|CLK_OUT_INTreg|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) 3| | ? | | S | |=> can support up to [ 13] logic PT(s) - 4| AVEC|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) - 5| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) - 6| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 4| AVEC|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) + 5| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) + 6| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) 7| | ? | | S | |=> can support up to [ 9] logic PT(s) - 8| cpu_est_3_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) - 9| SM_AMIGA_2_|NOD| | S | 5 |=> can support up to [ 14] logic PT(s) -10|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 8| CLK_000_D_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 9|inst_LDS_000_INT|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) +10| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) 11| | ? | | S | |=> can support up to [ 9] logic PT(s) 12| SM_AMIGA_0_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) -13| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 15] logic PT(s) +13|inst_DS_000_ENABLE|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) 14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- @@ -351,19 +351,19 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| DS_030|OUT| | => | 5 6 ( 7) 0 | 96 97 ( 98) 91 - 1|CLK_OUT_INTreg|NOD| | => | 5 6 7 0 | 96 97 98 91 - 2| IPL_D0_2_|NOD| | => | 6 7 0 1 | 97 98 91 92 + 1| SM_AMIGA_1_|NOD| | => | 5 6 7 0 | 96 97 98 91 + 2|CLK_OUT_INTreg|NOD| | => | 6 7 0 1 | 97 98 91 92 3| | | | => | 6 7 0 1 | 97 98 91 92 4| AVEC|OUT| | => | 7 0 ( 1) 2 | 98 91 ( 92) 93 - 5| SM_AMIGA_1_|NOD| | => | 7 0 1 2 | 98 91 92 93 - 6| IPL_D0_0_|NOD| | => | 0 1 2 3 | 91 92 93 94 + 5| SM_AMIGA_4_|NOD| | => | 7 0 1 2 | 98 91 92 93 + 6| SM_AMIGA_5_|NOD| | => | 0 1 2 3 | 91 92 93 94 7| | | | => | 0 1 2 3 | 91 92 93 94 - 8| cpu_est_3_|NOD| | => | 1 2 3 4 | 92 93 94 95 - 9| SM_AMIGA_2_|NOD| | => | 1 2 3 4 | 92 93 94 95 -10|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 2 3 4 5 | 93 94 95 96 + 8| CLK_000_D_1_|NOD| | => | 1 2 3 4 | 92 93 94 95 + 9|inst_LDS_000_INT|NOD| | => | 1 2 3 4 | 92 93 94 95 +10| IPL_D0_1_|NOD| | => | 2 3 4 5 | 93 94 95 96 11| | | | => | 2 3 4 5 | 93 94 95 96 12| SM_AMIGA_0_|NOD| | => | 3 4 5 6 | 94 95 96 97 -13| SM_AMIGA_3_|NOD| | => | 3 4 5 6 | 94 95 96 97 +13|inst_DS_000_ENABLE|NOD| | => | 3 4 5 6 | 94 95 96 97 14| | | | => | 4 5 6 7 | 95 96 97 98 15| | | | => | 4 5 6 7 | 95 96 97 98 --------------------------------------------------------------------------- @@ -415,37 +415,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 91|INP FPU_SENSE|*|*] [RegIn 0 |102| -| | ] [MCell 0 |101|OUT DS_030| | ] - [MCell 1 |103|NOD CLK_OUT_INTreg| |*] + [MCell 1 |103|NOD SM_AMIGA_1_| |*] 1 [IOpin 1 | 92|OUT AVEC|*| ] [RegIn 1 |105| -| | ] - [MCell 2 |104|NOD IPL_D0_2_| |*] + [MCell 2 |104|NOD CLK_OUT_INTreg| |*] [MCell 3 |106| -| | ] 2 [IOpin 2 | 93|INP A_DECODE_20_|*|*] [RegIn 2 |108| -| | ] [MCell 4 |107|OUT AVEC| | ] - [MCell 5 |109|NOD SM_AMIGA_1_| |*] + [MCell 5 |109|NOD SM_AMIGA_4_| |*] 3 [IOpin 3 | 94|INP A_DECODE_21_|*|*] [RegIn 3 |111| -| | ] - [MCell 6 |110|NOD IPL_D0_0_| |*] + [MCell 6 |110|NOD SM_AMIGA_5_| |*] [MCell 7 |112| -| | ] 4 [IOpin 4 | 95|INP A_DECODE_18_|*|*] [RegIn 4 |114| -| | ] - [MCell 8 |113|NOD cpu_est_3_| |*] - [MCell 9 |115|NOD SM_AMIGA_2_| |*] + [MCell 8 |113|NOD CLK_000_D_1_| |*] + [MCell 9 |115|NOD inst_LDS_000_INT| |*] 5 [IOpin 5 | 96|INP A_DECODE_16_|*|*] [RegIn 5 |117| -| | ] - [MCell 10 |116|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] + [MCell 10 |116|NOD IPL_D0_1_| |*] [MCell 11 |118| -| | ] 6 [IOpin 6 | 97|INP A_DECODE_19_|*|*] [RegIn 6 |120| -| | ] [MCell 12 |119|NOD SM_AMIGA_0_| |*] - [MCell 13 |121|NOD SM_AMIGA_3_| |*] + [MCell 13 |121|NOD inst_DS_000_ENABLE| |*] 7 [IOpin 7 | 98|OUT DS_030|*| ] [RegIn 7 |123| -| | ] @@ -458,37 +458,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 2 ( 67)| IPL_0_ -Mux01| Mcel 5 9 ( 235)| inst_DTACK_D0 -Mux02| IOPin 4 1 ( 42)| AS_000 -Mux03| IOPin 5 0 ( 60)| A_1_ -Mux04| IOPin 6 3 ( 68)| IPL_2_ -Mux05| Mcel 6 6 ( 254)| inst_VPA_D -Mux06| ... | ... -Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ -Mux08| ... | ... +Mux00| IOPin 6 4 ( 69)| A_0_ +Mux01| ... | ... +Mux02| Mcel 0 9 ( 115)| inst_LDS_000_INT +Mux03| IOPin 5 4 ( 56)| IPL_1_ +Mux04| Mcel 7 5 ( 277)| inst_CLK_OUT_PRE_D +Mux05| Mcel 5 0 ( 221)| CLK_000_D_0_ +Mux06| IOPin 7 6 ( 79)| SIZE_1_ +Mux07| ... | ... +Mux08| IOPin 6 6 ( 71)| RW Mux09| Mcel 0 12 ( 119)| SM_AMIGA_0_ -Mux10| Mcel 6 9 ( 259)| cpu_est_0_ +Mux10| Mcel 1 13 ( 145)| SM_AMIGA_6_ Mux11| ... | ... -Mux12| ... | ... -Mux13| Mcel 2 9 ( 163)| inst_DS_000_DMA -Mux14| Mcel 4 5 ( 205)| inst_CLK_OUT_PRE_D -Mux15| ... | ... -Mux16| Mcel 3 2 ( 176)| cpu_est_2_ -Mux17| IOPin 4 0 ( 41)| BERR -Mux18| Mcel 0 5 ( 109)| SM_AMIGA_1_ -Mux19| Mcel 0 9 ( 115)| SM_AMIGA_2_ +Mux12| Mcel 0 1 ( 103)| SM_AMIGA_1_ +Mux13| Mcel 2 9 ( 163)| SM_AMIGA_2_ +Mux14| IOPin 6 5 ( 70)| SIZE_0_ +Mux15| Mcel 0 6 ( 110)| SM_AMIGA_5_ +Mux16| IOPin 4 1 ( 42)| AS_000 +Mux17| ... | ... +Mux18| Mcel 0 5 ( 109)| SM_AMIGA_4_ +Mux19| IOPin 7 3 ( 82)| AS_030 Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 5 ( 253)| SM_AMIGA_4_ +Mux22| ... | ... Mux23| ... | ... Mux24| ... | ... -Mux25| Mcel 0 13 ( 121)| SM_AMIGA_3_ -Mux26| Mcel 3 0 ( 173)| RN_VMA -Mux27| Mcel 7 5 ( 277)| CLK_000_D_1_ +Mux25| Mcel 0 13 ( 121)| inst_DS_000_ENABLE +Mux26| ... | ... +Mux27| Mcel 6 9 ( 259)| inst_DS_000_DMA Mux28| ... | ... -Mux29| Mcel 3 13 ( 193)| cpu_est_1_ -Mux30| Mcel 0 8 ( 113)| cpu_est_3_ +Mux29| ... | ... +Mux30| Mcel 0 8 ( 113)| CLK_000_D_1_ Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- @@ -504,18 +504,18 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| AHIGH_30_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| CYCLE_DMA_1_|NOD| | S | 2 | 4 to [ 2]| 1 XOR free + 2| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1| 4 to [ 2]| 1 XOR to [ 2] 3| | ? | | S | | 4 to [ 4]| 1 XOR to [ 4] as logic PT 4| IPL_030_2_| IO| | S |10 | 4 to [ 4]| 1 XOR to [ 4] as logic PT 5| IPL_030_0_| IO| | S |10 | 4 to [ 5]| 1 XOR to [ 5] as logic PT - 6|inst_UDS_000_INT|NOD| | S | 2 | 4 to [ 6]| 1 XOR free - 7| | ? | | S | | 4 to [ 5]| 1 XOR to [ 5] as logic PT + 6| inst_VPA_D|NOD| | S | 1 | 4 to [ 5]| 1 XOR to [ 6] for 1 PT sig + 7| | ? | | S | | 4 to [ 5]| 1 XOR free 8| AHIGH_29_| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig 9| IPL_030_1_| IO| | S |10 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -10| | ? | | S | | 4 to [ 9]| 1 XOR to [ 9] as logic PT -11| | ? | | S | | 4 free | 1 XOR free +10| | ? | | S | | 4 to [ 9]| 1 XOR free +11| | ? | | S | | 4 to [ 9]| 1 XOR free 12| AHIGH_31_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| CYCLE_DMA_0_|NOD| | S | 4 | 4 to [13]| 1 XOR free +13| SM_AMIGA_6_|NOD| | S | 3 | 4 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -531,18 +531,18 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ _|_________________|__|__|___|_____|_______________________________________ 0| AHIGH_30_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) 1| CLK_EXP|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 2| CYCLE_DMA_1_|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) + 2| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1|=> can support up to [ 8] logic PT(s) 3| | ? | | S | |=> [ 0] PT capacity 4| IPL_030_2_| IO| | S |10 |=> can support up to [ 10] logic PT(s) - 5| IPL_030_0_| IO| | S |10 |=> can support up to [ 10] logic PT(s) - 6|inst_UDS_000_INT|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) - 7| | ? | | S | |=> can support up to [ 4] logic PT(s) + 5| IPL_030_0_| IO| | S |10 |=> can support up to [ 14] logic PT(s) + 6| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 7| | ? | | S | |=> can support up to [ 5] logic PT(s) 8| AHIGH_29_| IO| | S | 1 |=> can support up to [ 5] logic PT(s) 9| IPL_030_1_| IO| | S |10 |=> can support up to [ 19] logic PT(s) -10| | ? | | S | |=> can support up to [ 9] logic PT(s) -11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12| AHIGH_31_| IO| | S | 1 |=> can support up to [ 15] logic PT(s) -13| CYCLE_DMA_0_|NOD| | S | 4 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 5] logic PT(s) +11| | ? | | S | |=> can support up to [ 5] logic PT(s) +12| AHIGH_31_| IO| | S | 1 |=> can support up to [ 10] logic PT(s) +13| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) 14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- @@ -556,18 +556,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| AHIGH_30_| IO| | => |( 5) 6 7 0 |( 5) 4 3 10 1| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) - 2| CYCLE_DMA_1_|NOD| | => | 6 7 0 1 | 4 3 10 9 + 2| SM_AMIGA_i_7_|NOD| | => | 6 7 0 1 | 4 3 10 9 3| | | | => | 6 7 0 1 | 4 3 10 9 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 5| IPL_030_0_| IO| | => | 7 0 1 ( 2)| 3 10 9 ( 8) - 6|inst_UDS_000_INT|NOD| | => | 0 1 2 3 | 10 9 8 7 + 6| inst_VPA_D|NOD| | => | 0 1 2 3 | 10 9 8 7 7| | | | => | 0 1 2 3 | 10 9 8 7 8| AHIGH_29_| IO| | => | 1 2 3 ( 4)| 9 8 7 ( 6) 9| IPL_030_1_| IO| | => | 1 2 ( 3) 4 | 9 8 ( 7) 6 10| | | | => | 2 3 4 5 | 8 7 6 5 11| | | | => | 2 3 4 5 | 8 7 6 5 12| AHIGH_31_| IO| | => | 3 4 5 ( 6)| 7 6 5 ( 4) -13| CYCLE_DMA_0_|NOD| | => | 3 4 5 6 | 7 6 5 4 +13| SM_AMIGA_6_|NOD| | => | 3 4 5 6 | 7 6 5 4 14| | | | => | 4 5 6 7 | 6 5 4 3 15| | | | => | 4 5 6 7 | 6 5 4 3 --------------------------------------------------------------------------- @@ -626,7 +626,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_] [RegIn 1 |129| -| | ] - [MCell 2 |128|NOD CYCLE_DMA_1_| |*] + [MCell 2 |128|NOD SM_AMIGA_i_7_| |*] [MCell 3 |130| -| | ] 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] @@ -636,7 +636,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] - [MCell 6 |134|NOD inst_UDS_000_INT| |*] + [MCell 6 |134|NOD inst_VPA_D| |*] [MCell 7 |136| -| | ] 4 [IOpin 4 | 6| IO AHIGH_29_|*|*] @@ -652,7 +652,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 4| IO AHIGH_31_|*|*] [RegIn 6 |144| -| | ] [MCell 12 |143| IO AHIGH_31_| | ] - [MCell 13 |145|NOD CYCLE_DMA_0_| |*] + [MCell 13 |145|NOD SM_AMIGA_6_| |*] 7 [IOpin 7 | 3| -| | ] [RegIn 7 |147| -| | ] @@ -665,37 +665,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 4 ( 69)| A_0_ -Mux01| ... | ... -Mux02| Mcel 1 6 ( 134)| inst_UDS_000_INT +Mux00| IOPin 6 2 ( 67)| IPL_0_ +Mux01| Mcel 5 9 ( 235)| IPL_D0_0_ +Mux02| Mcel 5 8 ( 233)| inst_AS_030_000_SYNC Mux03| IOPin 5 4 ( 56)| IPL_1_ -Mux04| Mcel 3 6 ( 182)| IPL_D0_1_ -Mux05| Mcel 5 0 ( 221)| SM_AMIGA_6_ +Mux04| IOPin 6 3 ( 68)| IPL_2_ +Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| Mcel 1 9 ( 139)| RN_IPL_030_1_ -Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ -Mux08| ... | ... -Mux09| Mcel 0 1 ( 103)| CLK_OUT_INTreg -Mux10| Mcel 1 13 ( 145)| CYCLE_DMA_0_ +Mux07| ... | ... +Mux08| Mcel 0 10 ( 116)| IPL_D0_1_ +Mux09| Mcel 2 6 ( 158)| IPL_D0_2_ +Mux10| Mcel 1 13 ( 145)| SM_AMIGA_6_ Mux11| ... | ... Mux12| ... | ... -Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux14| ... | ... -Mux15| Mcel 0 6 ( 110)| IPL_D0_0_ -Mux16| IOPin 6 2 ( 67)| IPL_0_ +Mux13| Input Pin ( 36)| VPA +Mux14| Mcel 5 5 ( 229)| CLK_000_D_4_ +Mux15| Mcel 0 12 ( 119)| SM_AMIGA_0_ +Mux16| Mcel 3 2 ( 176)| CLK_000_D_3_ Mux17| ... | ... -Mux18| Mcel 1 2 ( 128)| CYCLE_DMA_1_ +Mux18| Mcel 1 2 ( 128)| SM_AMIGA_i_7_ Mux19| ... | ... Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 Mux21| Input Pin ( 86)| RST -Mux22| IOPin 6 3 ( 68)| IPL_2_ +Mux22| Mcel 0 2 ( 104)| CLK_OUT_INTreg Mux23| ... | ... Mux24| ... | ... -Mux25| Mcel 0 2 ( 104)| IPL_D0_2_ -Mux26| IOPin 4 1 ( 42)| AS_000 +Mux25| Mcel 5 0 ( 221)| CLK_000_D_0_ +Mux26| ... | ... Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ Mux28| Mcel 1 5 ( 133)| RN_IPL_030_0_ Mux29| ... | ... -Mux30| ... | ... +Mux30| Mcel 0 8 ( 113)| CLK_000_D_1_ Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- @@ -711,19 +711,19 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| AHIGH_28_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2|inst_DS_000_ENABLE|NOD| | S | 3 | 4 to [ 2]| 1 XOR free + 2| SM_AMIGA_3_|NOD| | S | 5 | 4 to [ 2]| 1 XOR to [ 2] as logic PT 3| | ? | | S | | 4 free | 1 XOR free 4| AHIGH_26_| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig 5| AHIGH_27_| IO| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6|inst_AS_000_INT|NOD| | S | 2 | 4 to [ 6]| 1 XOR free + 6| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free 8| AHIGH_24_| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9|inst_DS_000_DMA|NOD| | S | 6 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [10] for 1 PT sig + 9| SM_AMIGA_2_|NOD| | S | 5 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| AHIGH_25_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13|inst_AS_000_DMA|NOD| | S | 6 | 4 to [13]| 1 XOR to [13] as logic PT -14| | ? | | S | | 4 to [13]| 1 XOR free +13|inst_AS_000_INT|NOD| | S | 2 | 4 to [13]| 1 XOR free +14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -738,20 +738,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ _|_________________|__|__|___|_____|_______________________________________ 0| AHIGH_28_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) - 2|inst_DS_000_ENABLE|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) + 2| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 18] logic PT(s) 3| | ? | | S | |=> can support up to [ 13] logic PT(s) - 4| AHIGH_26_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) - 5| AHIGH_27_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) - 6|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) - 7| | ? | | S | |=> can support up to [ 9] logic PT(s) - 8| AHIGH_24_| IO| | S | 1 |=> can support up to [ 10] logic PT(s) - 9|inst_DS_000_DMA|NOD| | S | 6 |=> can support up to [ 18] logic PT(s) -10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) -11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12| AHIGH_25_| IO| | S | 1 |=> can support up to [ 10] logic PT(s) -13|inst_AS_000_DMA|NOD| | S | 6 |=> can support up to [ 19] logic PT(s) -14| | ? | | S | |=> can support up to [ 6] logic PT(s) -15| | ? | | S | |=> can support up to [ 5] logic PT(s) + 4| AHIGH_26_| IO| | S | 1 |=> can support up to [ 18] logic PT(s) + 5| AHIGH_27_| IO| | S | 1 |=> can support up to [ 18] logic PT(s) + 6| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 13] logic PT(s) + 8| AHIGH_24_| IO| | S | 1 |=> can support up to [ 15] logic PT(s) + 9| SM_AMIGA_2_|NOD| | S | 5 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 14] logic PT(s) +12| AHIGH_25_| IO| | S | 1 |=> can support up to [ 15] logic PT(s) +13|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Node-Pin Assignments @@ -763,18 +763,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| AHIGH_28_| IO| | => | 5 6 7 ( 0)| 20 21 22 ( 15) 1|AMIGA_BUS_ENABLE_LOW|OUT| | => |( 5) 6 7 0 |( 20) 21 22 15 - 2|inst_DS_000_ENABLE|NOD| | => | 6 7 0 1 | 21 22 15 16 + 2| SM_AMIGA_3_|NOD| | => | 6 7 0 1 | 21 22 15 16 3| | | | => | 6 7 0 1 | 21 22 15 16 4| AHIGH_26_| IO| | => | 7 0 1 ( 2)| 22 15 16 ( 17) 5| AHIGH_27_| IO| | => | 7 0 ( 1) 2 | 22 15 ( 16) 17 - 6|inst_AS_000_INT|NOD| | => | 0 1 2 3 | 15 16 17 18 + 6| IPL_D0_2_|NOD| | => | 0 1 2 3 | 15 16 17 18 7| | | | => | 0 1 2 3 | 15 16 17 18 8| AHIGH_24_| IO| | => | 1 2 3 ( 4)| 16 17 18 ( 19) - 9|inst_DS_000_DMA|NOD| | => | 1 2 3 4 | 16 17 18 19 -10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 2 3 4 5 | 17 18 19 20 + 9| SM_AMIGA_2_|NOD| | => | 1 2 3 4 | 16 17 18 19 +10| | | | => | 2 3 4 5 | 17 18 19 20 11| | | | => | 2 3 4 5 | 17 18 19 20 12| AHIGH_25_| IO| | => |( 3) 4 5 6 |( 18) 19 20 21 -13|inst_AS_000_DMA|NOD| | => | 3 4 5 6 | 18 19 20 21 +13|inst_AS_000_INT|NOD| | => | 3 4 5 6 | 18 19 20 21 14| | | | => | 4 5 6 7 | 19 20 21 22 15| | | | => | 4 5 6 7 | 19 20 21 22 --------------------------------------------------------------------------- @@ -830,7 +830,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 16| IO AHIGH_27_|*|*] [RegIn 1 |153| -| | ] - [MCell 2 |152|NOD inst_DS_000_ENABLE| |*] + [MCell 2 |152|NOD SM_AMIGA_3_| |*] [MCell 3 |154| -| | ] 2 [IOpin 2 | 17| IO AHIGH_26_|*|*] @@ -840,23 +840,23 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 18| IO AHIGH_25_|*|*] [RegIn 3 |159| -| | ] - [MCell 6 |158|NOD inst_AS_000_INT| |*] + [MCell 6 |158|NOD IPL_D0_2_| |*] [MCell 7 |160| -| | ] 4 [IOpin 4 | 19| IO AHIGH_24_|*|*] [RegIn 4 |162| -| | ] [MCell 8 |161| IO AHIGH_24_| | ] - [MCell 9 |163|NOD inst_DS_000_DMA| |*] + [MCell 9 |163|NOD SM_AMIGA_2_| |*] 5 [IOpin 5 | 20|OUT AMIGA_BUS_ENABLE_LOW|*| ] [RegIn 5 |165| -| | ] - [MCell 10 |164|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] + [MCell 10 |164| -| | ] [MCell 11 |166| -| | ] 6 [IOpin 6 | 21|INP BG_030|*|*] [RegIn 6 |168| -| | ] [MCell 12 |167| IO AHIGH_25_| | ] - [MCell 13 |169|NOD inst_AS_000_DMA| |*] + [MCell 13 |169|NOD inst_AS_000_INT| |*] 7 [IOpin 7 | 22| -| | ] [RegIn 7 |171| -| | ] @@ -870,36 +870,36 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST -Mux01| ... | ... -Mux02| Mcel 2 2 ( 152)| inst_DS_000_ENABLE -Mux03| IOPin 5 0 ( 60)| A_1_ -Mux04| Mcel 7 2 ( 272)| inst_AMIGA_DS -Mux05| Mcel 5 0 ( 221)| SM_AMIGA_6_ -Mux06| IOPin 7 5 ( 80)| RW_000 -Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ -Mux08| Mcel 2 10 ( 164)| inst_AMIGA_BUS_ENABLE_DMA_LOW -Mux09| Mcel 2 6 ( 158)| inst_AS_000_INT -Mux10| Mcel 1 2 ( 128)| CYCLE_DMA_1_ -Mux11| Mcel 2 13 ( 169)| inst_AS_000_DMA -Mux12| Mcel 0 1 ( 103)| CLK_OUT_INTreg -Mux13| Mcel 2 9 ( 163)| inst_DS_000_DMA -Mux14| Mcel 4 5 ( 205)| inst_CLK_OUT_PRE_D +Mux01| Mcel 3 0 ( 173)| RN_VMA +Mux02| Mcel 2 2 ( 152)| SM_AMIGA_3_ +Mux03| Mcel 0 8 ( 113)| CLK_000_D_1_ +Mux04| IOPin 6 3 ( 68)| IPL_2_ +Mux05| Mcel 5 0 ( 221)| CLK_000_D_0_ +Mux06| Mcel 5 13 ( 241)| inst_DTACK_D0 +Mux07| Mcel 3 9 ( 187)| cpu_est_3_ +Mux08| Mcel 4 8 ( 209)| inst_AMIGA_BUS_ENABLE_DMA_LOW +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 5 4 ( 227)| cpu_est_0_ +Mux11| Mcel 1 6 ( 134)| inst_VPA_D +Mux12| ... | ... +Mux13| Mcel 2 9 ( 163)| SM_AMIGA_2_ +Mux14| ... | ... Mux15| ... | ... -Mux16| IOPin 4 1 ( 42)| AS_000 -Mux17| ... | ... -Mux18| ... | ... -Mux19| IOPin 7 3 ( 82)| AS_030 +Mux16| ... | ... +Mux17| IOPin 4 0 ( 41)| BERR +Mux18| Mcel 0 5 ( 109)| SM_AMIGA_4_ +Mux19| ... | ... Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Mcel 1 13 ( 145)| CYCLE_DMA_0_ -Mux22| Mcel 6 5 ( 253)| SM_AMIGA_4_ +Mux21| Mcel 3 13 ( 193)| cpu_est_2_ +Mux22| Mcel 6 5 ( 253)| cpu_est_1_ Mux23| ... | ... Mux24| ... | ... -Mux25| IOPin 6 6 ( 71)| RW +Mux25| ... | ... Mux26| ... | ... -Mux27| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux28| ... | ... +Mux27| ... | ... +Mux28| Mcel 1 13 ( 145)| SM_AMIGA_6_ Mux29| ... | ... -Mux30| ... | ... +Mux30| Mcel 2 13 ( 169)| inst_AS_000_INT Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- @@ -915,18 +915,18 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| VMA| IO| | S | 3 | 4 to [ 0]| 1 XOR free 1| BG_000| IO| | S | 2 | 4 to [ 1]| 1 XOR free - 2| cpu_est_2_|NOD| | S | 1 :+: 1| 4 to [ 2]| 1 XOR to [ 2] + 2| CLK_000_D_3_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig 3| | ? | | S | | 4 free | 1 XOR free 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 | 4 to [ 4]| 1 XOR free 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 6|inst_UDS_000_INT|NOD| | S | 2 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| UDS_000| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9| CLK_000_D_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig + 9| cpu_est_3_|NOD| | S | 4 | 4 to [ 9]| 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| LDS_000| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| cpu_est_1_|NOD| | S | 4 | 4 to [13]| 1 XOR free +13| cpu_est_2_|NOD| | S | 1 :+: 1| 4 to [13]| 1 XOR to [13] 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -940,20 +940,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| VMA| IO| | S | 3 |=> can support up to [ 5] logic PT(s) - 1| BG_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) - 2| cpu_est_2_|NOD| | S | 1 :+: 1|=> can support up to [ 9] logic PT(s) - 3| | ? | | S | |=> can support up to [ 9] logic PT(s) - 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 |=> can support up to [ 18] logic PT(s) - 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) - 6| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) - 7| | ? | | S | |=> can support up to [ 17] logic PT(s) - 8| UDS_000| IO| | S | 1 |=> can support up to [ 19] logic PT(s) - 9| CLK_000_D_0_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) -10| | ? | | S | |=> can support up to [ 18] logic PT(s) + 0| VMA| IO| | S | 3 |=> can support up to [ 9] logic PT(s) + 1| BG_000| IO| | S | 2 |=> can support up to [ 14] logic PT(s) + 2| CLK_000_D_3_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 13] logic PT(s) + 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 |=> can support up to [ 14] logic PT(s) + 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) + 6|inst_UDS_000_INT|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 9] logic PT(s) + 8| UDS_000| IO| | S | 1 |=> can support up to [ 15] logic PT(s) + 9| cpu_est_3_|NOD| | S | 4 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) 11| | ? | | S | |=> can support up to [ 14] logic PT(s) 12| LDS_000| IO| | S | 1 |=> can support up to [ 15] logic PT(s) -13| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 19] logic PT(s) +13| cpu_est_2_|NOD| | S | 1 :+: 1|=> can support up to [ 18] logic PT(s) 14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- @@ -967,18 +967,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| VMA| IO| | => | 5 6 7 ( 0)| 30 29 28 ( 35) 1| BG_000| IO| | => | 5 ( 6) 7 0 | 30 ( 29) 28 35 - 2| cpu_est_2_|NOD| | => | 6 7 0 1 | 29 28 35 34 + 2| CLK_000_D_3_|NOD| | => | 6 7 0 1 | 29 28 35 34 3| | | | => | 6 7 0 1 | 29 28 35 34 4|AMIGA_BUS_ENABLE_HIGH|OUT| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 5|AMIGA_ADDR_ENABLE|OUT| | => | 7 0 1 ( 2)| 28 35 34 ( 33) - 6| IPL_D0_1_|NOD| | => | 0 1 2 3 | 35 34 33 32 + 6|inst_UDS_000_INT|NOD| | => | 0 1 2 3 | 35 34 33 32 7| | | | => | 0 1 2 3 | 35 34 33 32 8| UDS_000| IO| | => | 1 2 ( 3) 4 | 34 33 ( 32) 31 - 9| CLK_000_D_0_|NOD| | => | 1 2 3 4 | 34 33 32 31 + 9| cpu_est_3_|NOD| | => | 1 2 3 4 | 34 33 32 31 10| | | | => | 2 3 4 5 | 33 32 31 30 11| | | | => | 2 3 4 5 | 33 32 31 30 12| LDS_000| IO| | => | 3 ( 4) 5 6 | 32 ( 31) 30 29 -13| cpu_est_1_|NOD| | => | 3 4 5 6 | 32 31 30 29 +13| cpu_est_2_|NOD| | => | 3 4 5 6 | 32 31 30 29 14| | | | => | 4 5 6 7 | 31 30 29 28 15| | | | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- @@ -1036,7 +1036,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 34|OUT AMIGA_BUS_ENABLE_HIGH|*| ] [RegIn 1 |177| -| | ] - [MCell 2 |176|NOD cpu_est_2_| |*] + [MCell 2 |176|NOD CLK_000_D_3_| |*] [MCell 3 |178| -| | ] 2 [IOpin 2 | 33|OUT AMIGA_ADDR_ENABLE|*| ] @@ -1046,13 +1046,13 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 32| IO UDS_000|*|*] [RegIn 3 |183| -| | ] - [MCell 6 |182|NOD IPL_D0_1_| |*] + [MCell 6 |182|NOD inst_UDS_000_INT| |*] [MCell 7 |184| -| | ] 4 [IOpin 4 | 31| IO LDS_000|*|*] [RegIn 4 |186| -| | ] [MCell 8 |185| IO UDS_000| | ] - [MCell 9 |187|NOD CLK_000_D_0_| |*] + [MCell 9 |187|NOD cpu_est_3_| |*] 5 [IOpin 5 | 30|INP DTACK|*|*] [RegIn 5 |189| -| | ] @@ -1062,7 +1062,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] [RegIn 6 |192| -| | ] [MCell 12 |191| IO LDS_000| | ] - [MCell 13 |193|NOD cpu_est_1_| |*] + [MCell 13 |193|NOD cpu_est_2_| |*] 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] @@ -1075,38 +1075,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| Mcel 3 0 ( 173)| RN_VMA -Mux02| Mcel 3 1 ( 175)| RN_BG_000 -Mux03| Input Pin ( 11)| CLK_000 +Mux00| IOPin 6 4 ( 69)| A_0_ +Mux01| Mcel 3 13 ( 193)| cpu_est_2_ +Mux02| Mcel 4 9 ( 211)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux03| Mcel 0 8 ( 113)| CLK_000_D_1_ Mux04| IOPin 2 6 ( 21)| BG_030 -Mux05| Input Pin ( 14)| nEXP_SPACE +Mux05| Mcel 5 0 ( 221)| CLK_000_D_0_ Mux06| ... | ... -Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ -Mux08| Mcel 0 10 ( 116)| inst_AMIGA_BUS_ENABLE_DMA_HIGH -Mux09| Mcel 6 13 ( 265)| inst_LDS_000_INT -Mux10| Mcel 5 4 ( 227)| inst_AS_030_000_SYNC -Mux11| Mcel 1 6 ( 134)| inst_UDS_000_INT -Mux12| Mcel 6 9 ( 259)| cpu_est_0_ -Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux14| ... | ... -Mux15| ... | ... -Mux16| Mcel 3 2 ( 176)| cpu_est_2_ -Mux17| ... | ... -Mux18| Mcel 0 8 ( 113)| cpu_est_3_ -Mux19| IOPin 7 3 ( 82)| AS_030 -Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| IOPin 5 4 ( 56)| IPL_1_ -Mux22| Mcel 2 2 ( 152)| inst_DS_000_ENABLE -Mux23| Mcel 6 6 ( 254)| inst_VPA_D +Mux07| Mcel 3 9 ( 187)| cpu_est_3_ +Mux08| ... | ... +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 5 4 ( 227)| cpu_est_0_ +Mux11| Mcel 1 6 ( 134)| inst_VPA_D +Mux12| ... | ... +Mux13| ... | ... +Mux14| Mcel 7 2 ( 272)| CLK_000_D_2_ +Mux15| Input Pin ( 14)| nEXP_SPACE +Mux16| Mcel 3 6 ( 182)| inst_UDS_000_INT +Mux17| Mcel 3 1 ( 175)| RN_BG_000 +Mux18| Mcel 3 0 ( 173)| RN_VMA +Mux19| Mcel 0 9 ( 115)| inst_LDS_000_INT +Mux20| Mcel 5 8 ( 233)| inst_AS_030_000_SYNC +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 6 5 ( 253)| cpu_est_1_ +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 Mux24| ... | ... -Mux25| ... | ... +Mux25| Mcel 0 13 ( 121)| inst_DS_000_ENABLE Mux26| ... | ... Mux27| ... | ... -Mux28| ... | ... -Mux29| Mcel 3 13 ( 193)| cpu_est_1_ -Mux30| Mcel 4 8 ( 209)| inst_AS_030_D0 -Mux31| ... | ... +Mux28| Mcel 1 13 ( 145)| SM_AMIGA_6_ +Mux29| ... | ... +Mux30| ... | ... +Mux31| Mcel 5 12 ( 239)| inst_AS_030_D0 Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -1124,11 +1124,11 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| AS_000| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 5| N_205|NOD| | S | 2 | 4 to [ 5]| 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9| N_60|NOD| | S | 2 | 4 to [ 9]| 1 XOR free + 8|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 4 | 4 to [ 8]| 1 XOR free + 9|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 | 4 to [ 9]| 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| CIIN|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig @@ -1149,13 +1149,13 @@ _|_________________|__|__|___|_____|_______________________________________ 0| BERR| IO| | S | 1 |=> can support up to [ 10] logic PT(s) 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 |=> can support up to [ 19] logic PT(s) 2| | ? | | S | |=> can support up to [ 14] logic PT(s) - 3| | ? | | S | |=> can support up to [ 18] logic PT(s) - 4| AS_000| IO| | S | 1 |=> can support up to [ 19] logic PT(s) - 5|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) - 6| | ? | | S | |=> can support up to [ 18] logic PT(s) - 7| | ? | | S | |=> can support up to [ 14] logic PT(s) - 8|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) - 9| N_60|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) + 3| | ? | | S | |=> can support up to [ 14] logic PT(s) + 4| AS_000| IO| | S | 1 |=> can support up to [ 15] logic PT(s) + 5| N_205|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) + 6| | ? | | S | |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 10] logic PT(s) + 8|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) + 9|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) 10| | ? | | S | |=> can support up to [ 14] logic PT(s) 11| | ? | | S | |=> can support up to [ 18] logic PT(s) 12| CIIN|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) @@ -1176,11 +1176,11 @@ _|_________________|__|_____|____________________|________________________ 2| | | | => | 6 7 0 1 | 47 48 41 42 3| | | | => | 6 7 0 1 | 47 48 41 42 4| AS_000| IO| | => | 7 0 ( 1) 2 | 48 41 ( 42) 43 - 5|inst_CLK_OUT_PRE_D|NOD| | => | 7 0 1 2 | 48 41 42 43 + 5| N_205|NOD| | => | 7 0 1 2 | 48 41 42 43 6| | | | => | 0 1 2 3 | 41 42 43 44 7| | | | => | 0 1 2 3 | 41 42 43 44 - 8|inst_AS_030_D0|NOD| | => | 1 2 3 4 | 42 43 44 45 - 9| N_60|NOD| | => | 1 2 3 4 | 42 43 44 45 + 8|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 1 2 3 4 | 42 43 44 45 + 9|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 1 2 3 4 | 42 43 44 45 10| | | | => | 2 3 4 5 | 43 44 45 46 11| | | | => | 2 3 4 5 | 43 44 45 46 12| CIIN|OUT| | => | 3 4 5 ( 6)| 44 45 46 ( 47) @@ -1246,7 +1246,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 43| -| | ] [RegIn 2 |204| -| | ] [MCell 4 |203| IO AS_000| | ] - [MCell 5 |205|NOD inst_CLK_OUT_PRE_D| |*] + [MCell 5 |205|NOD N_205| |*] 3 [IOpin 3 | 44| -| | ] [RegIn 3 |207| -| | ] @@ -1255,8 +1255,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 45| -| | ] [RegIn 4 |210| -| | ] - [MCell 8 |209|NOD inst_AS_030_D0| |*] - [MCell 9 |211|NOD N_60| |*] + [MCell 8 |209|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] + [MCell 9 |211|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] 5 [IOpin 5 | 46| -| | ] [RegIn 5 |213| -| | ] @@ -1283,35 +1283,35 @@ Mux00| Input Pin ( 86)| RST Mux01| IOPin 5 2 ( 58)| FC_1_ Mux02| IOPin 4 1 ( 42)| AS_000 Mux03| IOPin 2 1 ( 16)| AHIGH_27_ -Mux04| IOPin 1 4 ( 6)| AHIGH_29_ -Mux05| Input Pin ( 14)| nEXP_SPACE +Mux04| IOPin 0 4 ( 95)| A_DECODE_18_ +Mux05| IOPin 2 4 ( 19)| AHIGH_24_ Mux06| IOPin 0 5 ( 96)| A_DECODE_16_ Mux07| IOPin 2 0 ( 15)| AHIGH_28_ -Mux08| IOPin 0 0 ( 91)| FPU_SENSE -Mux09| IOPin 7 3 ( 82)| AS_030 +Mux08| IOPin 7 0 ( 85)| A_DECODE_23_ +Mux09| IOPin 7 1 ( 84)| A_DECODE_22_ Mux10| ... | ... -Mux11| IOPin 7 1 ( 84)| A_DECODE_22_ +Mux11| IOPin 0 0 ( 91)| FPU_SENSE Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ -Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ -Mux14| Mcel 4 9 ( 211)| N_60 +Mux13| IOPin 1 4 ( 6)| AHIGH_29_ +Mux14| Mcel 4 5 ( 205)| N_205 Mux15| IOPin 0 3 ( 94)| A_DECODE_21_ -Mux16| Mcel 4 8 ( 209)| inst_AS_030_D0 -Mux17| IOPin 0 4 ( 95)| A_DECODE_18_ +Mux16| ... | ... +Mux17| IOPin 0 2 ( 93)| A_DECODE_20_ Mux18| IOPin 3 7 ( 28)| BGACK_000 -Mux19| Mcel 7 13 ( 289)| inst_CLK_OUT_PRE_50 -Mux20| IOPin 2 4 ( 19)| AHIGH_24_ -Mux21| IOPin 7 5 ( 80)| RW_000 +Mux19| IOPin 1 5 ( 5)| AHIGH_30_ +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| Input Pin ( 14)| nEXP_SPACE Mux22| IOPin 2 3 ( 18)| AHIGH_25_ -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux23| IOPin 5 0 ( 60)| A_1_ Mux24| IOPin 5 3 ( 57)| FC_0_ Mux25| IOPin 1 6 ( 4)| AHIGH_31_ Mux26| IOPin 2 2 ( 17)| AHIGH_26_ -Mux27| Mcel 2 6 ( 158)| inst_AS_000_INT -Mux28| IOPin 1 5 ( 5)| AHIGH_30_ -Mux29| IOPin 0 2 ( 93)| A_DECODE_20_ -Mux30| ... | ... -Mux31| ... | ... -Mux32| IOPin 7 0 ( 85)| A_DECODE_23_ +Mux27| IOPin 5 1 ( 59)| A_DECODE_17_ +Mux28| IOPin 7 5 ( 80)| RW_000 +Mux29| ... | ... +Mux30| Mcel 2 13 ( 169)| inst_AS_000_INT +Mux31| Mcel 5 12 ( 239)| inst_AS_030_D0 +Mux32| IOPin 7 3 ( 82)| AS_030 --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Macrocell (MCell) Cluster Assignments @@ -1323,20 +1323,20 @@ Mux32| IOPin 7 0 ( 85)| A_DECODE_23_ | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| SM_AMIGA_6_|NOD| | S | 3 | 4 to [ 0]| 1 XOR free + 0| CLK_000_D_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1|inst_AS_030_D1|NOD| | S | 2 | 4 to [ 1]| 1 XOR free 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free - 4|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 4]| 1 XOR to [ 4] as logic PT - 5| CLK_000_D_4_|NOD| | S | 1 | 4 to [ 4]| 1 XOR to [ 5] for 1 PT sig + 4| cpu_est_0_|NOD| | S | 3 | 4 to [ 4]| 1 XOR free + 5| CLK_000_D_4_|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1| 4 to [ 8]| 1 XOR to [ 8] - 9| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig + 8|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 8]| 1 XOR to [ 8] as logic PT + 9| IPL_D0_0_|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| SM_AMIGA_5_|NOD| | S | 3 | 4 to [12]| 1 XOR free -13| CLK_000_D_3_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +12|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1350,20 +1350,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) - 1|inst_AS_030_D1|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) + 0| CLK_000_D_0_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 1|inst_AS_030_D1|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) 2| | ? | | S | |=> can support up to [ 10] logic PT(s) - 3| | ? | | S | |=> can support up to [ 10] logic PT(s) - 4|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 19] logic PT(s) - 5| CLK_000_D_4_|NOD| | S | 1 |=> can support up to [ 11] logic PT(s) - 6| | ? | | S | |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 14] logic PT(s) - 8| SM_AMIGA_i_7_|NOD| | S | 3 :+: 1|=> can support up to [ 18] logic PT(s) - 9| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) + 3| | ? | | S | |=> can support up to [ 14] logic PT(s) + 4| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) + 5| CLK_000_D_4_|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) + 6| | ? | | S | |=> can support up to [ 14] logic PT(s) + 7| | ? | | S | |=> can support up to [ 10] logic PT(s) + 8|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 19] logic PT(s) + 9| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 11] logic PT(s) 10| | ? | | S | |=> can support up to [ 14] logic PT(s) -11| | ? | | S | |=> can support up to [ 14] logic PT(s) -12| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) -13| CLK_000_D_3_|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) +11| | ? | | S | |=> can support up to [ 18] logic PT(s) +12|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +13| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) 14| | ? | | S | |=> can support up to [ 14] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- @@ -1375,20 +1375,20 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| SM_AMIGA_6_|NOD| | => | 5 6 7 0 | 55 54 53 60 + 0| CLK_000_D_0_|NOD| | => | 5 6 7 0 | 55 54 53 60 1|inst_AS_030_D1|NOD| | => | 5 6 7 0 | 55 54 53 60 2| | | | => | 6 7 0 1 | 54 53 60 59 3| | | | => | 6 7 0 1 | 54 53 60 59 - 4|inst_AS_030_000_SYNC|NOD| | => | 7 0 1 2 | 53 60 59 58 + 4| cpu_est_0_|NOD| | => | 7 0 1 2 | 53 60 59 58 5| CLK_000_D_4_|NOD| | => | 7 0 1 2 | 53 60 59 58 6| | | | => | 0 1 2 3 | 60 59 58 57 7| | | | => | 0 1 2 3 | 60 59 58 57 - 8| SM_AMIGA_i_7_|NOD| | => | 1 2 3 4 | 59 58 57 56 - 9| inst_DTACK_D0|NOD| | => | 1 2 3 4 | 59 58 57 56 + 8|inst_AS_030_000_SYNC|NOD| | => | 1 2 3 4 | 59 58 57 56 + 9| IPL_D0_0_|NOD| | => | 1 2 3 4 | 59 58 57 56 10| | | | => | 2 3 4 5 | 58 57 56 55 11| | | | => | 2 3 4 5 | 58 57 56 55 -12| SM_AMIGA_5_|NOD| | => | 3 4 5 6 | 57 56 55 54 -13| CLK_000_D_3_|NOD| | => | 3 4 5 6 | 57 56 55 54 +12|inst_AS_030_D0|NOD| | => | 3 4 5 6 | 57 56 55 54 +13| inst_DTACK_D0|NOD| | => | 3 4 5 6 | 57 56 55 54 14| | | | => | 4 5 6 7 | 56 55 54 53 15| | | | => | 4 5 6 7 | 56 55 54 53 --------------------------------------------------------------------------- @@ -1439,7 +1439,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 60|INP A_1_|*|*] [RegIn 0 |222| -| | ] - [MCell 0 |221|NOD SM_AMIGA_6_| |*] + [MCell 0 |221|NOD CLK_000_D_0_| |*] [MCell 1 |223|NOD inst_AS_030_D1| |*] 1 [IOpin 1 | 59|INP A_DECODE_17_|*|*] @@ -1449,7 +1449,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 58|INP FC_1_|*|*] [RegIn 2 |228| -| | ] - [MCell 4 |227|NOD inst_AS_030_000_SYNC| |*] + [MCell 4 |227|NOD cpu_est_0_| |*] [MCell 5 |229|NOD CLK_000_D_4_| |*] 3 [IOpin 3 | 57|INP FC_0_|*|*] @@ -1459,8 +1459,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 56|INP IPL_1_|*|*] [RegIn 4 |234| -| | ] - [MCell 8 |233|NOD SM_AMIGA_i_7_| |*] - [MCell 9 |235|NOD inst_DTACK_D0| |*] + [MCell 8 |233|NOD inst_AS_030_000_SYNC| |*] + [MCell 9 |235|NOD IPL_D0_0_| |*] 5 [IOpin 5 | 55| -| | ] [RegIn 5 |237| -| | ] @@ -1469,8 +1469,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 54| -| | ] [RegIn 6 |240| -| | ] - [MCell 12 |239|NOD SM_AMIGA_5_| |*] - [MCell 13 |241|NOD CLK_000_D_3_| |*] + [MCell 12 |239|NOD inst_AS_030_D0| |*] + [MCell 13 |241|NOD inst_DTACK_D0| |*] 7 [IOpin 7 | 53| -| | ] [RegIn 7 |243| -| | ] @@ -1483,37 +1483,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST +Mux00| IOPin 6 2 ( 67)| IPL_0_ Mux01| IOPin 5 2 ( 58)| FC_1_ Mux02| Mcel 4 13 ( 217)| inst_BGACK_030_INT_D -Mux03| ... | ... +Mux03| Input Pin ( 11)| CLK_000 Mux04| IOPin 0 4 ( 95)| A_DECODE_18_ Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| IOPin 5 3 ( 57)| FC_0_ -Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ +Mux07| ... | ... Mux08| IOPin 5 1 ( 59)| A_DECODE_17_ Mux09| IOPin 3 5 ( 30)| DTACK Mux10| Mcel 5 1 ( 223)| inst_AS_030_D1 Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ Mux12| IOPin 0 6 ( 97)| A_DECODE_19_ -Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux14| Mcel 5 5 ( 229)| CLK_000_D_4_ -Mux15| Mcel 5 13 ( 241)| CLK_000_D_3_ -Mux16| Mcel 4 8 ( 209)| inst_AS_030_D0 -Mux17| Mcel 5 12 ( 239)| SM_AMIGA_5_ -Mux18| ... | ... +Mux13| ... | ... +Mux14| Mcel 5 4 ( 227)| cpu_est_0_ +Mux15| ... | ... +Mux16| Mcel 3 2 ( 176)| CLK_000_D_3_ +Mux17| Mcel 5 12 ( 239)| inst_AS_030_D0 +Mux18| Mcel 1 2 ( 128)| SM_AMIGA_i_7_ Mux19| IOPin 7 3 ( 82)| AS_030 -Mux20| Mcel 5 8 ( 233)| SM_AMIGA_i_7_ -Mux21| Mcel 7 6 ( 278)| CLK_000_D_2_ +Mux20| Mcel 5 8 ( 233)| inst_AS_030_000_SYNC +Mux21| Input Pin ( 86)| RST Mux22| ... | ... Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| Mcel 0 12 ( 119)| SM_AMIGA_0_ -Mux25| Mcel 5 0 ( 221)| SM_AMIGA_6_ +Mux24| ... | ... +Mux25| Mcel 5 0 ( 221)| CLK_000_D_0_ Mux26| ... | ... Mux27| ... | ... Mux28| ... | ... -Mux29| Mcel 5 4 ( 227)| inst_AS_030_000_SYNC -Mux30| ... | ... +Mux29| ... | ... +Mux30| Mcel 0 8 ( 113)| CLK_000_D_1_ Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- @@ -1532,16 +1532,16 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 2|inst_DSACK1_INT|NOD| | S | 2 | 4 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| E|OUT| | S | 2 | 4 to [ 4]| 1 XOR free - 5| SM_AMIGA_4_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free - 6| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 5| cpu_est_1_|NOD| | S | 4 | 4 to [ 5]| 1 XOR free + 6| CYCLE_DMA_0_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| A_0_| IO| | S | 2 | 4 to [ 8]| 1 XOR free - 9| cpu_est_0_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free -10| | ? | | S | | 4 free | 1 XOR free -11| | ? | | S | | 4 free | 1 XOR free + 9|inst_DS_000_DMA|NOD| | S | 6 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +10| CYCLE_DMA_1_|NOD| | S | 2 | 4 to [10]| 1 XOR free +11| | ? | | S | | 4 to [ 9]| 1 XOR free 12| SIZE_0_| IO| | S | 2 | 4 to [12]| 1 XOR free -13|inst_LDS_000_INT|NOD| | S | 3 | 4 to [13]| 1 XOR free -14| | ? | | S | | 4 free | 1 XOR free +13|inst_AS_000_DMA|NOD| | S | 6 | 4 to [13]| 1 XOR to [13] as logic PT +14| | ? | | S | | 4 to [13]| 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -1558,18 +1558,18 @@ _|_________________|__|__|___|_____|_______________________________________ 1| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) 2|inst_DSACK1_INT|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) 3| | ? | | S | |=> can support up to [ 5] logic PT(s) - 4| E|OUT| | S | 2 |=> can support up to [ 14] logic PT(s) - 5| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) - 6| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 9] logic PT(s) - 8| A_0_| IO| | S | 2 |=> can support up to [ 15] logic PT(s) - 9| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) -10| | ? | | S | |=> can support up to [ 10] logic PT(s) -11| | ? | | S | |=> can support up to [ 10] logic PT(s) -12| SIZE_0_| IO| | S | 2 |=> can support up to [ 15] logic PT(s) -13|inst_LDS_000_INT|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) -14| | ? | | S | |=> can support up to [ 10] logic PT(s) -15| | ? | | S | |=> can support up to [ 10] logic PT(s) + 4| E|OUT| | S | 2 |=> can support up to [ 10] logic PT(s) + 5| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) + 6| CYCLE_DMA_0_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 5] logic PT(s) + 8| A_0_| IO| | S | 2 |=> can support up to [ 10] logic PT(s) + 9|inst_DS_000_DMA|NOD| | S | 6 |=> can support up to [ 10] logic PT(s) +10| CYCLE_DMA_1_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) +11| | ? | | S | |=> can support up to [ 1] logic PT(s) +12| SIZE_0_| IO| | S | 2 |=> can support up to [ 5] logic PT(s) +13|inst_AS_000_DMA|NOD| | S | 6 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 6] logic PT(s) +15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Node-Pin Assignments @@ -1584,15 +1584,15 @@ _|_________________|__|_____|____________________|________________________ 2|inst_DSACK1_INT|NOD| | => | 6 7 0 1 | 71 72 65 66 3| | | | => | 6 7 0 1 | 71 72 65 66 4| E|OUT| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 - 5| SM_AMIGA_4_|NOD| | => | 7 0 1 2 | 72 65 66 67 - 6| inst_VPA_D|NOD| | => | 0 1 2 3 | 65 66 67 68 + 5| cpu_est_1_|NOD| | => | 7 0 1 2 | 72 65 66 67 + 6| CYCLE_DMA_0_|NOD| | => | 0 1 2 3 | 65 66 67 68 7| | | | => | 0 1 2 3 | 65 66 67 68 8| A_0_| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69) - 9| cpu_est_0_|NOD| | => | 1 2 3 4 | 66 67 68 69 -10| | | | => | 2 3 4 5 | 67 68 69 70 + 9|inst_DS_000_DMA|NOD| | => | 1 2 3 4 | 66 67 68 69 +10| CYCLE_DMA_1_|NOD| | => | 2 3 4 5 | 67 68 69 70 11| | | | => | 2 3 4 5 | 67 68 69 70 12| SIZE_0_| IO| | => | 3 4 ( 5) 6 | 68 69 ( 70) 71 -13|inst_LDS_000_INT|NOD| | => | 3 4 5 6 | 68 69 70 71 +13|inst_AS_000_DMA|NOD| | => | 3 4 5 6 | 68 69 70 71 14| | | | => | 4 5 6 7 | 69 70 71 72 15| | | | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- @@ -1654,27 +1654,27 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 67|INP IPL_0_|*|*] [RegIn 2 |252| -| | ] [MCell 4 |251|OUT E| | ] - [MCell 5 |253|NOD SM_AMIGA_4_| |*] + [MCell 5 |253|NOD cpu_est_1_| |*] 3 [IOpin 3 | 68|INP IPL_2_|*|*] [RegIn 3 |255| -| | ] - [MCell 6 |254|NOD inst_VPA_D| |*] + [MCell 6 |254|NOD CYCLE_DMA_0_| |*] [MCell 7 |256| -| | ] 4 [IOpin 4 | 69| IO A_0_|*|*] [RegIn 4 |258| -| | ] [MCell 8 |257| IO A_0_| | ] - [MCell 9 |259|NOD cpu_est_0_| |*] + [MCell 9 |259|NOD inst_DS_000_DMA| |*] 5 [IOpin 5 | 70| IO SIZE_0_|*|*] [RegIn 5 |261| -| | ] - [MCell 10 |260| -| | ] + [MCell 10 |260|NOD CYCLE_DMA_1_| |*] [MCell 11 |262| -| | ] 6 [IOpin 6 | 71| IO RW|*|*] [RegIn 6 |264| -| | ] [MCell 12 |263| IO SIZE_0_| | ] - [MCell 13 |265|NOD inst_LDS_000_INT| |*] + [MCell 13 |265|NOD inst_AS_000_DMA| |*] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] @@ -1687,38 +1687,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| Mcel 5 12 ( 239)| SM_AMIGA_5_ -Mux02| Mcel 0 5 ( 109)| SM_AMIGA_1_ -Mux03| Mcel 3 2 ( 176)| cpu_est_2_ -Mux04| Mcel 6 2 ( 248)| inst_DSACK1_INT -Mux05| Mcel 5 0 ( 221)| SM_AMIGA_6_ -Mux06| IOPin 7 6 ( 79)| SIZE_1_ -Mux07| Mcel 3 9 ( 187)| CLK_000_D_0_ +Mux00| Mcel 0 2 ( 104)| CLK_OUT_INTreg +Mux01| Mcel 3 13 ( 193)| cpu_est_2_ +Mux02| IOPin 4 1 ( 42)| AS_000 +Mux03| Mcel 6 5 ( 253)| cpu_est_1_ +Mux04| Mcel 7 5 ( 277)| inst_CLK_OUT_PRE_D +Mux05| Mcel 5 0 ( 221)| CLK_000_D_0_ +Mux06| IOPin 7 5 ( 80)| RW_000 +Mux07| Mcel 7 13 ( 289)| inst_AMIGA_DS Mux08| IOPin 3 3 ( 32)| UDS_000 -Mux09| Mcel 6 13 ( 265)| inst_LDS_000_INT -Mux10| Input Pin ( 36)| VPA +Mux09| Mcel 0 1 ( 103)| SM_AMIGA_1_ +Mux10| Mcel 6 9 ( 259)| inst_DS_000_DMA Mux11| ... | ... -Mux12| Mcel 0 1 ( 103)| CLK_OUT_INTreg -Mux13| Mcel 7 5 ( 277)| CLK_000_D_1_ -Mux14| IOPin 6 5 ( 70)| SIZE_0_ -Mux15| IOPin 6 4 ( 69)| A_0_ +Mux12| Mcel 6 13 ( 265)| inst_AS_000_DMA +Mux13| ... | ... +Mux14| Mcel 5 4 ( 227)| cpu_est_0_ +Mux15| ... | ... Mux16| ... | ... Mux17| ... | ... -Mux18| Mcel 0 8 ( 113)| cpu_est_3_ +Mux18| Mcel 0 8 ( 113)| CLK_000_D_1_ Mux19| IOPin 7 3 ( 82)| AS_030 Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Mcel 3 13 ( 193)| cpu_est_1_ -Mux22| Mcel 6 5 ( 253)| SM_AMIGA_4_ -Mux23| ... | ... +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 6 10 ( 260)| CYCLE_DMA_1_ +Mux23| Mcel 6 6 ( 254)| CYCLE_DMA_0_ Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| ... | ... +Mux25| Mcel 3 9 ( 187)| cpu_est_3_ Mux26| ... | ... -Mux27| Mcel 6 9 ( 259)| cpu_est_0_ -Mux28| IOPin 7 5 ( 80)| RW_000 +Mux27| ... | ... +Mux28| ... | ... Mux29| ... | ... Mux30| ... | ... -Mux31| ... | ... +Mux31| Mcel 6 2 ( 248)| inst_DSACK1_INT Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -1733,18 +1733,18 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| RW_000| IO| | S | 4 | 4 to [ 0]| 1 XOR free 1| FPU_CS|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| inst_AMIGA_DS|NOD| | S | 2 | 4 to [ 2]| 1 XOR free + 2| CLK_000_D_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig 3| | ? | | S | | 4 free | 1 XOR free 4| BGACK_030| IO| | S | 3 | 4 to [ 4]| 1 XOR free - 5| CLK_000_D_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6| CLK_000_D_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 5|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 6|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free 8| AS_030| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig 9| DSACK1|OUT| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| SIZE_1_| IO| | S | 2 | 4 to [12]| 1 XOR free -13|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +13| inst_AMIGA_DS|NOD| | S | 2 | 4 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1758,21 +1758,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| RW_000| IO| | S | 4 |=> can support up to [ 9] logic PT(s) - 1| FPU_CS|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) - 2| inst_AMIGA_DS|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) - 3| | ? | | S | |=> can support up to [ 9] logic PT(s) + 0| RW_000| IO| | S | 4 |=> can support up to [ 13] logic PT(s) + 1| FPU_CS|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) + 2| CLK_000_D_2_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 13] logic PT(s) 4| BGACK_030| IO| | S | 3 |=> can support up to [ 18] logic PT(s) - 5| CLK_000_D_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 6| CLK_000_D_2_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 5|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 6|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) 7| | ? | | S | |=> can support up to [ 17] logic PT(s) 8| AS_030| IO| | S | 1 |=> can support up to [ 19] logic PT(s) 9| DSACK1|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) 10| | ? | | S | |=> can support up to [ 14] logic PT(s) -11| | ? | | S | |=> can support up to [ 14] logic PT(s) -12| SIZE_1_| IO| | S | 2 |=> can support up to [ 19] logic PT(s) -13|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) -14| | ? | | S | |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 10] logic PT(s) +12| SIZE_1_| IO| | S | 2 |=> can support up to [ 15] logic PT(s) +13| inst_AMIGA_DS|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -1785,18 +1785,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| RW_000| IO| | => |( 5) 6 7 0 |( 80) 79 78 85 1| FPU_CS|OUT| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85 - 2| inst_AMIGA_DS|NOD| | => | 6 7 0 1 | 79 78 85 84 + 2| CLK_000_D_2_|NOD| | => | 6 7 0 1 | 79 78 85 84 3| | | | => | 6 7 0 1 | 79 78 85 84 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) - 5| CLK_000_D_1_|NOD| | => | 7 0 1 2 | 78 85 84 83 - 6| CLK_000_D_2_|NOD| | => | 0 1 2 3 | 85 84 83 82 + 5|inst_CLK_OUT_PRE_D|NOD| | => | 7 0 1 2 | 78 85 84 83 + 6|inst_CLK_OUT_PRE_50|NOD| | => | 0 1 2 3 | 85 84 83 82 7| | | | => | 0 1 2 3 | 85 84 83 82 8| AS_030| IO| | => | 1 2 ( 3) 4 | 84 83 ( 82) 81 9| DSACK1|OUT| | => | 1 2 3 ( 4)| 84 83 82 ( 81) 10| | | | => | 2 3 4 5 | 83 82 81 80 11| | | | => | 2 3 4 5 | 83 82 81 80 12| SIZE_1_| IO| | => | 3 4 5 ( 6)| 82 81 80 ( 79) -13|inst_CLK_OUT_PRE_50|NOD| | => | 3 4 5 6 | 82 81 80 79 +13| inst_AMIGA_DS|NOD| | => | 3 4 5 6 | 82 81 80 79 14| | | | => | 4 5 6 7 | 81 80 79 78 15| | | | => | 4 5 6 7 | 81 80 79 78 --------------------------------------------------------------------------- @@ -1854,17 +1854,17 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 84|INP A_DECODE_22_|*|*] [RegIn 1 |273| -| | ] - [MCell 2 |272|NOD inst_AMIGA_DS| |*] + [MCell 2 |272|NOD CLK_000_D_2_| |*] [MCell 3 |274| -| | ] 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] [RegIn 2 |276| -| | ] [MCell 4 |275|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] - [MCell 5 |277|NOD CLK_000_D_1_| |*] + [MCell 5 |277|NOD inst_CLK_OUT_PRE_D| |*] 3 [IOpin 3 | 82| IO AS_030|*|*] [RegIn 3 |279| -| | ] - [MCell 6 |278|NOD CLK_000_D_2_| |*] + [MCell 6 |278|NOD inst_CLK_OUT_PRE_50| |*] [MCell 7 |280| -| | ] 4 [IOpin 4 | 81|OUT DSACK1|*| ] @@ -1880,7 +1880,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 79| IO SIZE_1_|*|*] [RegIn 6 |288| -| | ] [MCell 12 |287| IO SIZE_1_| | ] - [MCell 13 |289|NOD inst_CLK_OUT_PRE_50| |*] + [MCell 13 |289|NOD inst_AMIGA_DS| |*] 7 [IOpin 7 | 78|OUT FPU_CS|*| ] [RegIn 7 |291| -| | ] @@ -1893,37 +1893,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST +Mux00| IOPin 3 4 ( 31)| LDS_000 Mux01| IOPin 5 2 ( 58)| FC_1_ -Mux02| Mcel 5 8 ( 233)| SM_AMIGA_i_7_ -Mux03| ... | ... -Mux04| IOPin 0 4 ( 95)| A_DECODE_18_ -Mux05| Mcel 5 0 ( 221)| SM_AMIGA_6_ +Mux02| IOPin 4 1 ( 42)| AS_000 +Mux03| Mcel 0 8 ( 113)| CLK_000_D_1_ +Mux04| IOPin 3 7 ( 28)| BGACK_000 +Mux05| Mcel 5 0 ( 221)| CLK_000_D_0_ Mux06| IOPin 0 6 ( 97)| A_DECODE_19_ -Mux07| Mcel 7 13 ( 289)| inst_CLK_OUT_PRE_50 +Mux07| Mcel 7 6 ( 278)| inst_CLK_OUT_PRE_50 Mux08| IOPin 6 6 ( 71)| RW -Mux09| Mcel 0 12 ( 119)| SM_AMIGA_0_ -Mux10| ... | ... +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 1 13 ( 145)| SM_AMIGA_6_ Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ Mux12| IOPin 3 3 ( 32)| UDS_000 Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ Mux14| ... | ... Mux15| Input Pin ( 14)| nEXP_SPACE -Mux16| IOPin 4 1 ( 42)| AS_000 +Mux16| ... | ... Mux17| IOPin 5 3 ( 57)| FC_0_ -Mux18| IOPin 3 7 ( 28)| BGACK_000 +Mux18| Mcel 1 2 ( 128)| SM_AMIGA_i_7_ Mux19| IOPin 0 0 ( 91)| FPU_SENSE Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| ... | ... +Mux21| Input Pin ( 86)| RST Mux22| ... | ... -Mux23| Mcel 7 0 ( 269)| RN_RW_000 -Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| Mcel 3 9 ( 187)| CLK_000_D_0_ +Mux23| Mcel 6 2 ( 248)| inst_DSACK1_INT +Mux24| Mcel 0 12 ( 119)| SM_AMIGA_0_ +Mux25| Mcel 6 13 ( 265)| inst_AS_000_DMA Mux26| ... | ... -Mux27| Mcel 7 5 ( 277)| CLK_000_D_1_ +Mux27| ... | ... Mux28| ... | ... Mux29| ... | ... -Mux30| Mcel 2 13 ( 169)| inst_AS_000_DMA -Mux31| Mcel 6 2 ( 248)| inst_DSACK1_INT -Mux32| IOPin 7 3 ( 82)| AS_030 +Mux30| Mcel 7 0 ( 269)| RN_RW_000 +Mux31| IOPin 0 4 ( 95)| A_DECODE_18_ +Mux32| ... | ... --------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index d64aec7..bec1ae7 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic -Project Fitted on : Sat Dec 30 00:43:46 2017 +Project Fitted on : Thu Jan 11 20:16:38 2018 Device : M4A5-128/64 Package : 100TQFP @@ -41,7 +41,7 @@ Design_Summary Total Output Pins : 18 Total Bidir I/O Pins : 18 Total Flip-Flops : 52 - Total Product Terms : 177 + Total Product Terms : 181 Total Reserved Pins : 0 Total Reserved Blocks : 0 @@ -58,9 +58,9 @@ Logic Macrocells 128 79 49 --> 61% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 1 .. -CSM Outputs/Total Block Inputs 264 188 76 --> 71% -Logical Product Terms 640 179 461 --> 27% -Product Term Clusters 128 44 84 --> 34% +CSM Outputs/Total Block Inputs 264 185 79 --> 70% +Logical Product Terms 640 183 457 --> 28% +Product Term Clusters 128 46 82 --> 35%  Blocks_Resource_Summary @@ -71,13 +71,13 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 23 8 0 11 0 5 26 11 Lo -Block B 20 7 0 10 1 5 42 7 Lo -Block C 21 7 0 11 0 5 24 10 Lo -Block D 22 8 0 10 0 6 18 11 Lo -Block E 30 4 0 8 0 8 10 14 Lo -Block F 24 5 0 8 0 8 22 10 Lo -Block G 23 7 0 10 0 6 20 9 Lo +Block A 21 8 0 11 0 5 23 10 Lo +Block B 22 7 0 10 1 5 42 6 Lo +Block C 20 7 0 10 0 6 19 13 Lo +Block D 23 8 0 10 0 6 19 10 Lo +Block E 30 4 0 8 0 8 14 12 Lo +Block F 22 5 0 8 0 8 17 12 Lo +Block G 22 7 0 11 0 5 32 5 Lo Block H 25 8 0 10 0 6 17 12 Lo --------------------------------------------------------------------------------- @@ -287,7 +287,7 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 60 F . I/O A-C----- Low Slow A_1_ + 60 F . I/O ----E--- Low Slow A_1_ 96 A . I/O ----EF-H Low Slow A_DECODE_16_ 59 F . I/O ----EF-H Low Slow A_DECODE_17_ 95 A . I/O ----EF-H Low Slow A_DECODE_18_ @@ -302,12 +302,12 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 57 F . I/O ----EF-H Low Slow FC_0_ 58 F . I/O ----EF-H Low Slow FC_1_ 91 A . I/O ----E--H Low Slow FPU_SENSE - 67 G . I/O AB------ Low Slow IPL_0_ - 56 F . I/O -B-D---- Low Slow IPL_1_ - 68 G . I/O AB------ Low Slow IPL_2_ - 11 . . Ck/I ---D---- - Slow CLK_000 - 14 . . Ck/I ---DEF-H - Slow nEXP_SPACE - 36 . . Ded ------G- - Slow VPA + 67 G . I/O -B---F-- Low Slow IPL_0_ + 56 F . I/O AB------ Low Slow IPL_1_ + 68 G . I/O -BC----- Low Slow IPL_2_ + 11 . . Ck/I -----F-- - Slow CLK_000 + 14 . . Ck/I -B-DEF-H - Slow nEXP_SPACE + 36 . . Ded -B------ - Slow VPA 61 . . Ck/I ABCDEFGH - Slow CLK_OSZI 86 . . Ded ABCDEFGH - Slow RST ---------------------------------------------------------------------- @@ -366,15 +366,15 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 6 B 1 COM ----E--- Low Fast AHIGH_29_ 5 B 1 COM ----E--- Low Fast AHIGH_30_ 4 B 1 COM ----E--- Low Fast AHIGH_31_ - 42 E 1 COM ABC-E--H Low Fast AS_000 - 82 H 1 COM --CDEFGH Low Fast AS_030 - 69 G 2 DFF -B----G- Low Fast A_0_ - 41 E 1 COM A------- Low Fast BERR + 42 E 1 COM A---E-GH Low Fast AS_000 + 82 H 1 COM A-CDEFGH Low Fast AS_030 + 69 G 2 DFF A--D---- Low Fast A_0_ + 41 E 1 COM --C----- Low Fast BERR 31 D 1 COM ------GH Low Fast LDS_000 - 71 G 1 DFF --C----H Low Fast RW - 80 H 4 DFF --C-E-G- Low Fast RW_000 - 70 G 2 DFF ------G- Low Fast SIZE_0_ - 79 H 2 DFF ------G- Low Fast SIZE_1_ + 71 G 1 DFF A------H Low Fast RW + 80 H 4 DFF ----E-G- Low Fast RW_000 + 70 G 2 DFF A------- Low Fast SIZE_0_ + 79 H 2 DFF A------- Low Fast SIZE_1_ 32 D 1 COM ------GH Low Fast UDS_000 ---------------------------------------------------------------------- @@ -391,55 +391,55 @@ Buried_Signal_List Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - D9 D 1 DFF ABCD-FGH Low Slow CLK_000_D_0_ - H5 H 1 DFF ABCD-FGH Low Slow CLK_000_D_1_ - H6 H 1 DFF -----F-- Low Slow CLK_000_D_2_ - F13 F 1 DFF -----F-- Low Slow CLK_000_D_3_ - F5 F 1 DFF -----F-- Low Slow CLK_000_D_4_ - A1 A 1 DFF -BC---G- Low Slow CLK_OUT_INTreg - B13 B 4 DFF -BC----- Low Slow CYCLE_DMA_0_ - B2 B 2 DFF -BC----- Low Slow CYCLE_DMA_1_ - A6 A 1 DFF -B------ Low Slow IPL_D0_0_ - D6 D 1 DFF -B------ Low Slow IPL_D0_1_ - A2 A 1 DFF -B------ Low Slow IPL_D0_2_ - E9 E 2 COM ----E--- Low Slow N_60 + F0 F 1 DFF ABCD-FGH Low Slow CLK_000_D_0_ + A8 A 1 DFF ABCD-FGH Low Slow CLK_000_D_1_ + H2 H 1 DFF ---D---- Low Slow CLK_000_D_2_ + D2 D 1 DFF -B---F-- Low Slow CLK_000_D_3_ + F5 F 1 DFF -B------ Low Slow CLK_000_D_4_ + A2 A 1 DFF -B----G- Low Slow CLK_OUT_INTreg + G6 G 4 DFF ------G- Low Slow CYCLE_DMA_0_ + G10 G 2 DFF ------G- Low Slow CYCLE_DMA_1_ + F9 F 1 DFF -B------ Low Slow IPL_D0_0_ + A10 A 1 DFF -B------ Low Slow IPL_D0_1_ + C6 C 1 DFF -B------ Low Slow IPL_D0_2_ + E5 E 2 COM ----E--- Low Slow N_205 H4 H 3 DFF ABCDEFGH Low - RN_BGACK_030 --> BGACK_030 D1 D 2 DFF ---D---- Low - RN_BG_000 --> BG_000 B5 B 10 DFF -B------ Low - RN_IPL_030_0_ --> IPL_030_0_ B9 B 10 DFF -B------ Low - RN_IPL_030_1_ --> IPL_030_1_ B4 B 10 DFF -B------ Low - RN_IPL_030_2_ --> IPL_030_2_ H0 H 4 DFF -------H Low - RN_RW_000 --> RW_000 - D0 D 3 TFF A--D---- Low - RN_VMA --> VMA - A12 A 3 DFF A----F-H Low Slow SM_AMIGA_0_ - A5 A 3 DFF A-----G- Low Slow SM_AMIGA_1_ - A9 A 5 DFF A------- Low Slow SM_AMIGA_2_ - A13 A 5 TFF A------- Low Slow SM_AMIGA_3_ - G5 G 3 DFF A-C---G- Low Slow SM_AMIGA_4_ - F12 F 3 DFF -----FG- Low Slow SM_AMIGA_5_ - F0 F 3 DFF -BC--FGH Low Slow SM_AMIGA_6_ - F8 F 3 TFF -----F-H Low Slow SM_AMIGA_i_7_ - G9 G 3 DFF A--D--G- Low Slow cpu_est_0_ - D13 D 4 DFF A--D--G- Low Slow cpu_est_1_ - D2 D 1 DFF A--D--G- Low Slow cpu_est_2_ - A8 A 4 DFF A--D--G- Low Slow cpu_est_3_ - A10 A 1 DFF ---D---- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH - C10 C 1 DFF --C----- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW - H2 H 2 DFF --C----- Low Slow inst_AMIGA_DS - C13 C 6 DFF --C----H Low Slow inst_AS_000_DMA - C6 C 2 DFF --C-E--- Low Slow inst_AS_000_INT - F4 F 7 DFF ---D-F-- Low Slow inst_AS_030_000_SYNC - E8 E 1 DFF ---DEF-- Low Slow inst_AS_030_D0 + D0 D 3 TFF --CD---- Low - RN_VMA --> VMA + A12 A 3 DFF AB-----H Low Slow SM_AMIGA_0_ + A1 A 3 DFF A-----G- Low Slow SM_AMIGA_1_ + C9 C 5 DFF A-C----- Low Slow SM_AMIGA_2_ + C2 C 5 TFF --C----- Low Slow SM_AMIGA_3_ + A5 A 3 DFF A-C----- Low Slow SM_AMIGA_4_ + A6 A 3 DFF A------- Low Slow SM_AMIGA_5_ + B13 B 3 DFF ABCD---H Low Slow SM_AMIGA_6_ + B2 B 3 TFF -B---F-H Low Slow SM_AMIGA_i_7_ + F4 F 3 DFF --CD-FG- Low Slow cpu_est_0_ + G5 G 4 DFF --CD--G- Low Slow cpu_est_1_ + D13 D 1 DFF --CD--G- Low Slow cpu_est_2_ + D9 D 4 DFF --CD--G- Low Slow cpu_est_3_ + E9 E 2 DFF ---D---- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH + E8 E 4 DFF --C----- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW + H13 H 2 DFF ------G- Low Slow inst_AMIGA_DS + G13 G 6 DFF ------GH Low Slow inst_AS_000_DMA + C13 C 2 DFF --C-E--- Low Slow inst_AS_000_INT + F8 F 7 DFF -B-D-F-- Low Slow inst_AS_030_000_SYNC + F12 F 1 DFF ---DEF-- Low Slow inst_AS_030_D0 F1 F 2 DFF -----F-- Low Slow inst_AS_030_D1 E13 E 1 DFF -----F-- Low Slow inst_BGACK_030_INT_D - H13 H 1 DFF ----E--H Low Slow inst_CLK_OUT_PRE_50 - E5 E 1 DFF A-C----- Low Slow inst_CLK_OUT_PRE_D + H6 H 1 DFF -------H Low Slow inst_CLK_OUT_PRE_50 + H5 H 1 DFF A-----G- Low Slow inst_CLK_OUT_PRE_D G2 G 2 DFF ------GH Low Slow inst_DSACK1_INT - C9 C 6 DFF A-C----- Low Slow inst_DS_000_DMA - C2 C 3 DFF --CD---- Low Slow inst_DS_000_ENABLE - F9 F 1 DFF A------- Low Slow inst_DTACK_D0 - G13 G 3 DFF ---D--G- Low Slow inst_LDS_000_INT - B6 B 2 DFF -B-D---- Low Slow inst_UDS_000_INT - G6 G 1 DFF A--D---- Low Slow inst_VPA_D + G9 G 6 DFF A-----G- Low Slow inst_DS_000_DMA + A13 A 3 DFF A--D---- Low Slow inst_DS_000_ENABLE + F13 F 1 DFF --C----- Low Slow inst_DTACK_D0 + A9 A 3 DFF A--D---- Low Slow inst_LDS_000_INT + D6 D 2 DFF ---D---- Low Slow inst_UDS_000_INT + B6 B 1 DFF --CD---- Low Slow inst_VPA_D ---------------------------------------------------------------------- Power : Hi = High @@ -454,157 +454,170 @@ Signals_Fanout_List ~~~~~~~~~~~~~~~~~~~ Signal Source : Fanout List ----------------------------------------------------------------------------- - AHIGH_27_{ D}: CIIN{ E} N_60{ E} - AHIGH_26_{ D}: CIIN{ E} N_60{ E} - AHIGH_25_{ D}: CIIN{ E} N_60{ E} - AHIGH_24_{ D}: CIIN{ E} N_60{ E} - AHIGH_31_{ C}: CIIN{ E} N_60{ E} -A_DECODE_22_{ I}: CIIN{ E} N_60{ E} -A_DECODE_21_{ B}: CIIN{ E} N_60{ E} -A_DECODE_23_{ I}: CIIN{ E} N_60{ E} -A_DECODE_20_{ B}: CIIN{ E} N_60{ E} -A_DECODE_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} -A_DECODE_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} -A_DECODE_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} -A_DECODE_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} + AHIGH_30_{ C}: CIIN{ E}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E}inst_AMIGA_BUS_ENABLE_DMA_LOW{ E} + : N_205{ E} + AHIGH_31_{ C}: CIIN{ E}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E}inst_AMIGA_BUS_ENABLE_DMA_LOW{ E} + : N_205{ E} + AHIGH_29_{ C}: CIIN{ E}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E}inst_AMIGA_BUS_ENABLE_DMA_LOW{ E} + : N_205{ E} + AHIGH_28_{ D}: CIIN{ E}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E}inst_AMIGA_BUS_ENABLE_DMA_LOW{ E} + : N_205{ E} +A_DECODE_23_{ I}: CIIN{ E}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E}inst_AMIGA_BUS_ENABLE_DMA_LOW{ E} + : N_205{ E} + AHIGH_27_{ D}: CIIN{ E}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E}inst_AMIGA_BUS_ENABLE_DMA_LOW{ E} + : N_205{ E} + AHIGH_26_{ D}: CIIN{ E}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E}inst_AMIGA_BUS_ENABLE_DMA_LOW{ E} + : N_205{ E} + AHIGH_25_{ D}: CIIN{ E}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E}inst_AMIGA_BUS_ENABLE_DMA_LOW{ E} + : N_205{ E} + AHIGH_24_{ D}: CIIN{ E}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E}inst_AMIGA_BUS_ENABLE_DMA_LOW{ E} + : N_205{ E} +A_DECODE_22_{ I}: CIIN{ E}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E}inst_AMIGA_BUS_ENABLE_DMA_LOW{ E} + : N_205{ E} +A_DECODE_21_{ B}: CIIN{ E}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E}inst_AMIGA_BUS_ENABLE_DMA_LOW{ E} + : N_205{ E} IPL_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_2_{ A} + : IPL_D0_2_{ C} +A_DECODE_20_{ B}: CIIN{ E}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E}inst_AMIGA_BUS_ENABLE_DMA_LOW{ E} + : N_205{ E} +A_DECODE_19_{ B}: BERR{ E} FPU_CS{ H}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E} + :inst_AMIGA_BUS_ENABLE_DMA_LOW{ E}inst_AS_030_000_SYNC{ F} FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} +A_DECODE_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} AS_030{ I}: AS_000{ E} BERR{ E} FPU_CS{ H} - : DSACK1{ H}AMIGA_BUS_ENABLE_HIGH{ D} inst_AS_030_D0{ E} - :inst_AS_030_000_SYNC{ F}inst_DS_000_ENABLE{ C}inst_DSACK1_INT{ G} + : DSACK1{ H}AMIGA_BUS_ENABLE_HIGH{ D} inst_AS_030_D0{ F} + :inst_AS_030_000_SYNC{ F}inst_DS_000_ENABLE{ A}inst_DSACK1_INT{ G} :inst_AS_000_INT{ C} +A_DECODE_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} AS_000{ F}: AS_030{ H} DS_030{ A}AMIGA_BUS_DATA_DIR{ E} - : BGACK_030{ H}inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} - : CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ B} - UDS_000{ E}: SIZE_1_{ H} A_0_{ G} SIZE_0_{ G} + : BGACK_030{ H}inst_AS_000_DMA{ G}inst_DS_000_DMA{ G} + : CYCLE_DMA_0_{ G} CYCLE_DMA_1_{ G} +A_DECODE_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} + UDS_000{ E}: SIZE_1_{ H} SIZE_0_{ G} A_0_{ G} : inst_AMIGA_DS{ H} LDS_000{ E}: SIZE_1_{ H} SIZE_0_{ G} inst_AMIGA_DS{ H} nEXP_SPACE{. }: DSACK1{ H}AMIGA_BUS_DATA_DIR{ E} BG_000{ D} - :inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} - : N_60{ E} - BERR{ F}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} + :inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ B} SM_AMIGA_i_7_{ B} + : N_205{ E} + BERR{ F}: SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} BG_030{ D}: BG_000{ D} BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H} - CLK_000{. }: CLK_000_D_0_{ D} - IPL_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_1_{ D} - IPL_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_0_{ A} - FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} - A_1_{ G}:inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C} + CLK_000{. }: CLK_000_D_0_{ F} FPU_SENSE{ B}: BERR{ E} FPU_CS{ H} + IPL_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + : IPL_D0_1_{ A} DTACK{ E}: inst_DTACK_D0{ F} - VPA{. }: inst_VPA_D{ G} + IPL_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + : IPL_D0_0_{ F} + FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ F} + A_1_{ G}:inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E}inst_AMIGA_BUS_ENABLE_DMA_LOW{ E} + VPA{. }: inst_VPA_D{ B} RST{. }: AS_000{ E} UDS_000{ D} LDS_000{ D} - : SIZE_1_{ H} IPL_030_2_{ B} RW_000{ H} - : BG_000{ D} BGACK_030{ H} A_0_{ G} - : IPL_030_1_{ B} IPL_030_0_{ B} VMA{ D} - : RW{ G} SIZE_0_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A} - :inst_AMIGA_BUS_ENABLE_DMA_LOW{ C} inst_AS_030_D0{ E} inst_AS_030_D1{ F} - :inst_AS_030_000_SYNC{ F}inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} - : inst_VPA_D{ G} inst_DTACK_D0{ F} inst_AMIGA_DS{ H} - : IPL_D0_0_{ A} IPL_D0_1_{ D} IPL_D0_2_{ A} - :inst_UDS_000_INT{ B}inst_DS_000_ENABLE{ C}inst_LDS_000_INT{ G} - :inst_BGACK_030_INT_D{ E} SM_AMIGA_6_{ F} SM_AMIGA_4_{ G} - : SM_AMIGA_1_{ A} SM_AMIGA_0_{ A} CYCLE_DMA_0_{ B} - : CYCLE_DMA_1_{ B}inst_DSACK1_INT{ G}inst_AS_000_INT{ C} - : SM_AMIGA_5_{ F} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} - : SM_AMIGA_i_7_{ F} - AHIGH_30_{ C}: CIIN{ E} N_60{ E} - AHIGH_29_{ C}: CIIN{ E} N_60{ E} - AHIGH_28_{ D}: CIIN{ E} N_60{ E} - SIZE_1_{ I}:inst_LDS_000_INT{ G} + : SIZE_1_{ H} SIZE_0_{ G} IPL_030_2_{ B} + : RW_000{ H} BG_000{ D} BGACK_030{ H} + : A_0_{ G} IPL_030_1_{ B} IPL_030_0_{ B} + : VMA{ D} RW{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E} + :inst_AMIGA_BUS_ENABLE_DMA_LOW{ E} inst_AS_030_D0{ F} inst_AS_030_D1{ F} + :inst_AS_030_000_SYNC{ F}inst_AS_000_DMA{ G}inst_DS_000_DMA{ G} + : inst_VPA_D{ B} inst_DTACK_D0{ F} inst_AMIGA_DS{ H} + : IPL_D0_0_{ F} IPL_D0_1_{ A} IPL_D0_2_{ C} + :inst_UDS_000_INT{ D}inst_DS_000_ENABLE{ A}inst_LDS_000_INT{ A} + :inst_BGACK_030_INT_D{ E} SM_AMIGA_6_{ B} SM_AMIGA_4_{ A} + : SM_AMIGA_1_{ A} SM_AMIGA_0_{ A} CYCLE_DMA_0_{ G} + : CYCLE_DMA_1_{ G}inst_DSACK1_INT{ G}inst_AS_000_INT{ C} + : SM_AMIGA_5_{ A} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} + : SM_AMIGA_i_7_{ B} + SIZE_1_{ I}:inst_LDS_000_INT{ A} + SIZE_0_{ H}:inst_LDS_000_INT{ A} RN_IPL_030_2_{ C}: IPL_030_2_{ B} - RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_AS_000_DMA{ C} - :inst_DS_000_DMA{ C} + RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_AS_000_DMA{ G} + :inst_DS_000_DMA{ G} RN_RW_000{ I}: RW_000{ H} RN_BG_000{ E}: BG_000{ D} -RN_BGACK_030{ I}: AHIGH_27_{ C} AHIGH_26_{ C} AHIGH_25_{ C} - : AHIGH_24_{ C} AHIGH_31_{ B} AS_030{ H} +RN_BGACK_030{ I}: AHIGH_30_{ B} AHIGH_31_{ B} AHIGH_29_{ B} + : AHIGH_28_{ C} AHIGH_27_{ C} AHIGH_26_{ C} + : AHIGH_25_{ C} AHIGH_24_{ C} AS_030{ H} : AS_000{ E} DS_030{ A} UDS_000{ D} : LDS_000{ D} DSACK1{ H}AMIGA_BUS_DATA_DIR{ E} - :AMIGA_BUS_ENABLE_LOW{ C}AMIGA_BUS_ENABLE_HIGH{ D} AHIGH_30_{ B} - : AHIGH_29_{ B} AHIGH_28_{ C} SIZE_1_{ H} - : RW_000{ H} BGACK_030{ H} A_0_{ G} - : VMA{ D} RW{ G} SIZE_0_{ G} - :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ C}inst_AS_030_000_SYNC{ F} - :inst_BGACK_030_INT_D{ E} CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ B} - A_0_{ H}:inst_UDS_000_INT{ B}inst_LDS_000_INT{ G} + :AMIGA_BUS_ENABLE_LOW{ C}AMIGA_BUS_ENABLE_HIGH{ D} SIZE_1_{ H} + : SIZE_0_{ G} RW_000{ H} BGACK_030{ H} + : A_0_{ G} VMA{ D} RW{ G} + :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ E}inst_AMIGA_BUS_ENABLE_DMA_LOW{ E}inst_AS_030_000_SYNC{ F} + :inst_BGACK_030_INT_D{ E} CYCLE_DMA_0_{ G} CYCLE_DMA_1_{ G} + A_0_{ H}:inst_UDS_000_INT{ D}inst_LDS_000_INT{ A} RN_IPL_030_1_{ C}: IPL_030_1_{ B} RN_IPL_030_0_{ C}: IPL_030_0_{ B} - RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} - RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ C} - SIZE_0_{ H}:inst_LDS_000_INT{ G} - cpu_est_0_{ H}: VMA{ D} cpu_est_0_{ G} cpu_est_1_{ D} - : cpu_est_2_{ D} cpu_est_3_{ A} SM_AMIGA_3_{ A} - : SM_AMIGA_2_{ A} - cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} - : cpu_est_2_{ D} cpu_est_3_{ A} SM_AMIGA_3_{ A} - : SM_AMIGA_2_{ A} + RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} + RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ A} + cpu_est_0_{ G}: VMA{ D} cpu_est_0_{ F} cpu_est_1_{ G} + : cpu_est_2_{ D} cpu_est_3_{ D} SM_AMIGA_3_{ C} + : SM_AMIGA_2_{ C} + cpu_est_1_{ H}: E{ G} VMA{ D} cpu_est_1_{ G} + : cpu_est_2_{ D} cpu_est_3_{ D} SM_AMIGA_3_{ C} + : SM_AMIGA_2_{ C} cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_2_{ D} - : cpu_est_3_{ A} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} - cpu_est_3_{ B}: E{ G} VMA{ D} cpu_est_1_{ D} - : cpu_est_3_{ A} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} -inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}:AMIGA_BUS_ENABLE_HIGH{ D} -inst_AMIGA_BUS_ENABLE_DMA_LOW{ D}:AMIGA_BUS_ENABLE_LOW{ C} -inst_AS_030_D0{ F}: CIIN{ E} BG_000{ D} inst_AS_030_D1{ F} - : N_60{ E} + : cpu_est_3_{ D} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} + cpu_est_3_{ E}: E{ G} VMA{ D} cpu_est_1_{ G} + : cpu_est_3_{ D} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} +inst_AMIGA_BUS_ENABLE_DMA_HIGH{ F}:AMIGA_BUS_ENABLE_HIGH{ D} +inst_AMIGA_BUS_ENABLE_DMA_LOW{ F}:AMIGA_BUS_ENABLE_LOW{ C} +inst_AS_030_D0{ G}: CIIN{ E} BG_000{ D} inst_AS_030_D1{ F} + : N_205{ E} inst_AS_030_D1{ G}: inst_AS_030_D1{ F}inst_AS_030_000_SYNC{ F} -inst_AS_030_000_SYNC{ G}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} - : SM_AMIGA_i_7_{ F} -inst_AS_000_DMA{ D}: AS_030{ H}inst_AS_000_DMA{ C} -inst_DS_000_DMA{ D}: DS_030{ A}inst_DS_000_DMA{ C} - inst_VPA_D{ H}: VMA{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} -CLK_000_D_3_{ G}: CLK_000_D_4_{ F} SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} -inst_DTACK_D0{ G}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} -inst_AMIGA_DS{ I}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} -CLK_000_D_1_{ I}: RW_000{ H} BGACK_030{ H} VMA{ D} - : cpu_est_0_{ G} cpu_est_1_{ D} cpu_est_2_{ D} - : cpu_est_3_{ A} CLK_000_D_2_{ H}inst_DS_000_ENABLE{ C} - : SM_AMIGA_6_{ F} SM_AMIGA_4_{ G} SM_AMIGA_1_{ A} - : SM_AMIGA_0_{ A} CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ B} - :inst_DSACK1_INT{ G}inst_AS_000_INT{ C} SM_AMIGA_5_{ F} - : SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} SM_AMIGA_i_7_{ F} -CLK_000_D_0_{ E}: RW_000{ H} BG_000{ D} BGACK_030{ H} - : VMA{ D} cpu_est_0_{ G} cpu_est_1_{ D} - : cpu_est_2_{ D} cpu_est_3_{ A} CLK_000_D_1_{ H} - :inst_DS_000_ENABLE{ C} SM_AMIGA_6_{ F} SM_AMIGA_4_{ G} - : SM_AMIGA_1_{ A} SM_AMIGA_0_{ A} CYCLE_DMA_0_{ B} - : CYCLE_DMA_1_{ B}inst_DSACK1_INT{ G}inst_AS_000_INT{ C} - : SM_AMIGA_5_{ F} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} - : SM_AMIGA_i_7_{ F} -inst_CLK_OUT_PRE_50{ I}:inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_D{ E} -inst_CLK_OUT_PRE_D{ F}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} CLK_OUT_INTreg{ A} - IPL_D0_0_{ B}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - IPL_D0_1_{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - IPL_D0_2_{ B}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} -CLK_000_D_2_{ I}: CLK_000_D_3_{ F} -CLK_000_D_4_{ G}: SM_AMIGA_6_{ F} SM_AMIGA_i_7_{ F} -inst_UDS_000_INT{ C}: UDS_000{ D}inst_UDS_000_INT{ B} -inst_DS_000_ENABLE{ D}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ C} -inst_LDS_000_INT{ H}: LDS_000{ D}inst_LDS_000_INT{ G} +inst_AS_030_000_SYNC{ G}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ B} + : SM_AMIGA_i_7_{ B} +inst_AS_000_DMA{ H}: AS_030{ H}inst_AS_000_DMA{ G} +inst_DS_000_DMA{ H}: DS_030{ A}inst_DS_000_DMA{ G} + inst_VPA_D{ C}: VMA{ D} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} +CLK_000_D_3_{ E}: CLK_000_D_4_{ F} SM_AMIGA_6_{ B} SM_AMIGA_i_7_{ B} +inst_DTACK_D0{ G}: SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} +inst_AMIGA_DS{ I}:inst_AS_000_DMA{ G}inst_DS_000_DMA{ G} +CLK_000_D_1_{ B}: RW_000{ H} BGACK_030{ H} VMA{ D} + : cpu_est_0_{ F} cpu_est_1_{ G} cpu_est_2_{ D} + : cpu_est_3_{ D} CLK_000_D_2_{ H}inst_DS_000_ENABLE{ A} + : SM_AMIGA_6_{ B} SM_AMIGA_4_{ A} SM_AMIGA_1_{ A} + : SM_AMIGA_0_{ A} CYCLE_DMA_0_{ G} CYCLE_DMA_1_{ G} + :inst_DSACK1_INT{ G}inst_AS_000_INT{ C} SM_AMIGA_5_{ A} + : SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} SM_AMIGA_i_7_{ B} +CLK_000_D_0_{ G}: RW_000{ H} BG_000{ D} BGACK_030{ H} + : VMA{ D} cpu_est_0_{ F} cpu_est_1_{ G} + : cpu_est_2_{ D} cpu_est_3_{ D} CLK_000_D_1_{ A} + :inst_DS_000_ENABLE{ A} SM_AMIGA_6_{ B} SM_AMIGA_4_{ A} + : SM_AMIGA_1_{ A} SM_AMIGA_0_{ A} CYCLE_DMA_0_{ G} + : CYCLE_DMA_1_{ G}inst_DSACK1_INT{ G}inst_AS_000_INT{ C} + : SM_AMIGA_5_{ A} SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} + : SM_AMIGA_i_7_{ B} +inst_CLK_OUT_PRE_50{ I}:inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_D{ H} +inst_CLK_OUT_PRE_D{ I}:inst_AS_000_DMA{ G}inst_DS_000_DMA{ G} CLK_OUT_INTreg{ A} + IPL_D0_0_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_1_{ B}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_2_{ D}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} +CLK_000_D_2_{ I}: CLK_000_D_3_{ D} +CLK_000_D_4_{ G}: SM_AMIGA_6_{ B} SM_AMIGA_i_7_{ B} +inst_UDS_000_INT{ E}: UDS_000{ D}inst_UDS_000_INT{ D} +inst_DS_000_ENABLE{ B}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ A} +inst_LDS_000_INT{ B}: LDS_000{ D}inst_LDS_000_INT{ A} inst_BGACK_030_INT_D{ F}:inst_AS_030_000_SYNC{ F} -SM_AMIGA_6_{ G}: RW_000{ H}inst_UDS_000_INT{ B}inst_DS_000_ENABLE{ C} - :inst_LDS_000_INT{ G} SM_AMIGA_6_{ F}inst_AS_000_INT{ C} - : SM_AMIGA_5_{ F} -SM_AMIGA_4_{ H}:inst_DS_000_ENABLE{ C} SM_AMIGA_4_{ G} SM_AMIGA_3_{ A} +SM_AMIGA_6_{ C}: RW_000{ H}inst_UDS_000_INT{ D}inst_DS_000_ENABLE{ A} + :inst_LDS_000_INT{ A} SM_AMIGA_6_{ B}inst_AS_000_INT{ C} + : SM_AMIGA_5_{ A} +SM_AMIGA_4_{ B}:inst_DS_000_ENABLE{ A} SM_AMIGA_4_{ A} SM_AMIGA_3_{ C} SM_AMIGA_1_{ B}: SM_AMIGA_1_{ A} SM_AMIGA_0_{ A}inst_DSACK1_INT{ G} -SM_AMIGA_0_{ B}: RW_000{ H} SM_AMIGA_0_{ A} SM_AMIGA_i_7_{ F} -CYCLE_DMA_0_{ C}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} CYCLE_DMA_0_{ B} - : CYCLE_DMA_1_{ B} -CYCLE_DMA_1_{ C}:inst_AS_000_DMA{ C}inst_DS_000_DMA{ C} CYCLE_DMA_0_{ B} - : CYCLE_DMA_1_{ B} +SM_AMIGA_0_{ B}: RW_000{ H} SM_AMIGA_0_{ A} SM_AMIGA_i_7_{ B} +CYCLE_DMA_0_{ H}:inst_AS_000_DMA{ G}inst_DS_000_DMA{ G} CYCLE_DMA_0_{ G} + : CYCLE_DMA_1_{ G} +CYCLE_DMA_1_{ H}:inst_AS_000_DMA{ G}inst_DS_000_DMA{ G} CYCLE_DMA_0_{ G} + : CYCLE_DMA_1_{ G} inst_DSACK1_INT{ H}: DSACK1{ H}inst_DSACK1_INT{ G} inst_AS_000_INT{ D}: AS_000{ E}inst_AS_000_INT{ C} -SM_AMIGA_5_{ G}: SM_AMIGA_4_{ G} SM_AMIGA_5_{ F} -SM_AMIGA_3_{ B}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} -SM_AMIGA_2_{ B}: SM_AMIGA_1_{ A} SM_AMIGA_2_{ A} -CLK_OUT_INTreg{ B}: CLK_DIV_OUT{ G} CLK_EXP{ B}inst_AS_000_DMA{ C} - :inst_DS_000_DMA{ C} -SM_AMIGA_i_7_{ G}: RW_000{ H}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} - : SM_AMIGA_i_7_{ F} - N_60{ F}: CIIN{ E} +SM_AMIGA_5_{ B}: SM_AMIGA_4_{ A} SM_AMIGA_5_{ A} +SM_AMIGA_3_{ D}: SM_AMIGA_3_{ C} SM_AMIGA_2_{ C} +SM_AMIGA_2_{ D}: SM_AMIGA_1_{ A} SM_AMIGA_2_{ C} +CLK_OUT_INTreg{ B}: CLK_DIV_OUT{ G} CLK_EXP{ B}inst_AS_000_DMA{ G} + :inst_DS_000_DMA{ G} +SM_AMIGA_i_7_{ C}: RW_000{ H}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ B} + : SM_AMIGA_i_7_{ B} + N_205{ F}: CIIN{ E} ----------------------------------------------------------------------------- {.} : Indicates block location of signal @@ -622,15 +635,15 @@ Equations : +-----+-----+-----+-----+------------------------ | | | | | DS_030 | | | | | AVEC -| * | S | BS | BR | cpu_est_3_ +| * | S | BS | BR | CLK_000_D_1_ | * | S | BS | BR | SM_AMIGA_0_ -| * | S | BS | BR | CLK_OUT_INTreg | * | S | BS | BR | SM_AMIGA_1_ -| * | S | BS | BR | SM_AMIGA_2_ -| * | S | BS | BR | SM_AMIGA_3_ -| * | S | BS | BR | IPL_D0_2_ -| * | S | BS | BR | IPL_D0_0_ -| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH +| * | S | BS | BR | SM_AMIGA_4_ +| * | S | BS | BR | inst_LDS_000_INT +| * | S | BS | BR | inst_DS_000_ENABLE +| * | S | BS | BR | CLK_OUT_INTreg +| * | S | BS | BR | SM_AMIGA_5_ +| * | S | BS | BR | IPL_D0_1_ | | | | | A_DECODE_19_ | | | | | A_DECODE_16_ | | | | | A_DECODE_18_ @@ -653,9 +666,9 @@ Equations : | * | S | BS | BR | IPL_030_0_ | * | S | BS | BR | IPL_030_1_ | | | | | CLK_EXP -| * | S | BS | BR | CYCLE_DMA_0_ -| * | S | BS | BR | CYCLE_DMA_1_ -| * | S | BS | BR | inst_UDS_000_INT +| * | S | BS | BR | SM_AMIGA_6_ +| * | S | BS | BR | SM_AMIGA_i_7_ +| * | S | BS | BR | inst_VPA_D | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ | * | S | BS | BR | RN_IPL_030_2_ @@ -674,11 +687,10 @@ Equations : | | | | | AHIGH_27_ | | | | | AHIGH_28_ | | | | | AMIGA_BUS_ENABLE_LOW -| * | S | BS | BR | inst_DS_000_DMA -| * | S | BS | BR | inst_AS_000_DMA -| * | S | BS | BR | inst_DS_000_ENABLE +| * | S | BS | BR | SM_AMIGA_2_ | * | S | BS | BR | inst_AS_000_INT -| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW +| * | S | BS | BR | SM_AMIGA_3_ +| * | S | BS | BR | IPL_D0_2_ | | | | | BG_030 @@ -695,12 +707,12 @@ Equations : | | | | | AMIGA_BUS_ENABLE_HIGH | * | S | BS | BR | BG_000 | | | | | AMIGA_ADDR_ENABLE -| * | S | BS | BR | CLK_000_D_0_ -| * | S | BS | BR | cpu_est_1_ +| * | S | BS | BR | cpu_est_3_ | * | S | BS | BR | cpu_est_2_ | * | S | BS | BR | RN_VMA +| * | S | BS | BR | CLK_000_D_3_ | * | S | BS | BR | RN_BG_000 -| * | S | BS | BR | IPL_D0_1_ +| * | S | BS | BR | inst_UDS_000_INT | | | | | BGACK_000 | | | | | DTACK @@ -716,9 +728,9 @@ Equations : | | | | | BERR | | | | | AMIGA_BUS_DATA_DIR | | | | | CIIN -| * | S | BS | BR | inst_AS_030_D0 -| * | S | BS | BR | inst_CLK_OUT_PRE_D -| | | | | N_60 +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW +| | | | | N_205 +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH | * | S | BS | BR | inst_BGACK_030_INT_D @@ -729,19 +741,19 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| * | S | BS | BR | SM_AMIGA_6_ +| * | S | BS | BR | CLK_000_D_0_ +| * | S | BS | BR | cpu_est_0_ | * | S | BS | BR | inst_AS_030_000_SYNC -| * | S | BS | BR | SM_AMIGA_i_7_ -| * | S | BS | BR | SM_AMIGA_5_ +| * | S | BS | BR | inst_AS_030_D0 | * | S | BS | BR | inst_AS_030_D1 | * | S | BS | BR | CLK_000_D_4_ +| * | S | BS | BR | IPL_D0_0_ | * | S | BS | BR | inst_DTACK_D0 -| * | S | BS | BR | CLK_000_D_3_ | | | | | A_DECODE_17_ | | | | | FC_1_ | | | | | FC_0_ -| | | | | A_1_ | | | | | IPL_1_ +| | | | | A_1_ Block G @@ -756,11 +768,12 @@ Equations : | * | S | BS | BR | SIZE_0_ | | | | | E | | | | | CLK_DIV_OUT -| * | S | BS | BR | SM_AMIGA_4_ -| * | S | BS | BR | cpu_est_0_ -| * | S | BS | BR | inst_LDS_000_INT +| * | S | BS | BR | cpu_est_1_ +| * | S | BS | BR | inst_DS_000_DMA +| * | S | BS | BR | inst_AS_000_DMA | * | S | BS | BR | inst_DSACK1_INT -| * | S | BS | BR | inst_VPA_D +| * | S | BS | BR | CYCLE_DMA_0_ +| * | S | BS | BR | CYCLE_DMA_1_ | | | | | IPL_2_ | | | | | IPL_0_ @@ -779,11 +792,11 @@ Equations : | | | | | DSACK1 | | | | | FPU_CS | * | S | BS | BR | RN_BGACK_030 -| * | S | BS | BR | CLK_000_D_1_ -| * | S | BS | BR | inst_CLK_OUT_PRE_50 +| * | S | BS | BR | inst_CLK_OUT_PRE_D | * | S | BS | BR | RN_RW_000 | * | S | BS | BR | inst_AMIGA_DS | * | S | BS | BR | CLK_000_D_2_ +| * | S | BS | BR | inst_CLK_OUT_PRE_50 | | | | | A_DECODE_23_ | | | | | A_DECODE_22_ @@ -802,23 +815,23 @@ BLOCK_A_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx A0 IPL_0_ pin 67 mx A17 BERR pin 41 -mx A1 inst_DTACK_D0 mcell F9 mx A18 SM_AMIGA_1_ mcell A5 -mx A2 AS_000 pin 42 mx A19 SM_AMIGA_2_ mcell A9 -mx A3 A_1_ pin 60 mx A20 RN_BGACK_030 mcell H4 -mx A4 IPL_2_ pin 68 mx A21 RST pin 86 -mx A5 inst_VPA_D mcell G6 mx A22 SM_AMIGA_4_ mcell G5 -mx A6 ... ... mx A23 ... ... -mx A7 CLK_000_D_0_ mcell D9 mx A24 ... ... -mx A8 ... ... mx A25 SM_AMIGA_3_ mcell A13 -mx A9 SM_AMIGA_0_ mcell A12 mx A26 RN_VMA mcell D0 -mx A10 cpu_est_0_ mcell G9 mx A27 CLK_000_D_1_ mcell H5 +mx A0 A_0_ pin 69 mx A17 ... ... +mx A1 ... ... mx A18 SM_AMIGA_4_ mcell A5 +mx A2inst_LDS_000_INT mcell A9 mx A19 AS_030 pin 82 +mx A3 IPL_1_ pin 56 mx A20 RN_BGACK_030 mcell H4 +mx A4inst_CLK_OUT_PRE_D mcell H5 mx A21 RST pin 86 +mx A5 CLK_000_D_0_ mcell F0 mx A22 ... ... +mx A6 SIZE_1_ pin 79 mx A23 ... ... +mx A7 ... ... mx A24 ... ... +mx A8 RW pin 71 mx A25inst_DS_000_ENABLE mcell A13 +mx A9 SM_AMIGA_0_ mcell A12 mx A26 ... ... +mx A10 SM_AMIGA_6_ mcell B13 mx A27 inst_DS_000_DMA mcell G9 mx A11 ... ... mx A28 ... ... -mx A12 ... ... mx A29 cpu_est_1_ mcell D13 -mx A13 inst_DS_000_DMA mcell C9 mx A30 cpu_est_3_ mcell A8 -mx A14inst_CLK_OUT_PRE_D mcell E5 mx A31 ... ... -mx A15 ... ... mx A32 ... ... -mx A16 cpu_est_2_ mcell D2 +mx A12 SM_AMIGA_1_ mcell A1 mx A29 ... ... +mx A13 SM_AMIGA_2_ mcell C9 mx A30 CLK_000_D_1_ mcell A8 +mx A14 SIZE_0_ pin 70 mx A31 ... ... +mx A15 SM_AMIGA_5_ mcell A6 mx A32 ... ... +mx A16 AS_000 pin 42 ---------------------------------------------------------------------------- @@ -826,23 +839,23 @@ BLOCK_B_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx B0 A_0_ pin 69 mx B17 ... ... -mx B1 ... ... mx B18 CYCLE_DMA_1_ mcell B2 -mx B2inst_UDS_000_INT mcell B6 mx B19 ... ... +mx B0 IPL_0_ pin 67 mx B17 ... ... +mx B1 IPL_D0_0_ mcell F9 mx B18 SM_AMIGA_i_7_ mcell B2 +mx B2inst_AS_030_000_SYNC mcell F8 mx B19 ... ... mx B3 IPL_1_ pin 56 mx B20 RN_BGACK_030 mcell H4 -mx B4 IPL_D0_1_ mcell D6 mx B21 RST pin 86 -mx B5 SM_AMIGA_6_ mcell F0 mx B22 IPL_2_ pin 68 +mx B4 IPL_2_ pin 68 mx B21 RST pin 86 +mx B5 nEXP_SPACE pin 14 mx B22 CLK_OUT_INTreg mcell A2 mx B6 RN_IPL_030_1_ mcell B9 mx B23 ... ... -mx B7 CLK_000_D_0_ mcell D9 mx B24 ... ... -mx B8 ... ... mx B25 IPL_D0_2_ mcell A2 -mx B9 CLK_OUT_INTreg mcell A1 mx B26 AS_000 pin 42 -mx B10 CYCLE_DMA_0_ mcell B13 mx B27 RN_IPL_030_2_ mcell B4 +mx B7 ... ... mx B24 ... ... +mx B8 IPL_D0_1_ mcell A10 mx B25 CLK_000_D_0_ mcell F0 +mx B9 IPL_D0_2_ mcell C6 mx B26 ... ... +mx B10 SM_AMIGA_6_ mcell B13 mx B27 RN_IPL_030_2_ mcell B4 mx B11 ... ... mx B28 RN_IPL_030_0_ mcell B5 mx B12 ... ... mx B29 ... ... -mx B13 CLK_000_D_1_ mcell H5 mx B30 ... ... -mx B14 ... ... mx B31 ... ... -mx B15 IPL_D0_0_ mcell A6 mx B32 ... ... -mx B16 IPL_0_ pin 67 +mx B13 VPA pin 36 mx B30 CLK_000_D_1_ mcell A8 +mx B14 CLK_000_D_4_ mcell F5 mx B31 ... ... +mx B15 SM_AMIGA_0_ mcell A12 mx B32 ... ... +mx B16 CLK_000_D_3_ mcell D2 ---------------------------------------------------------------------------- @@ -850,23 +863,23 @@ BLOCK_C_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx C0 RST pin 86 mx C17 ... ... -mx C1 ... ... mx C18 ... ... -mx C2inst_DS_000_ENABLE mcell C2 mx C19 AS_030 pin 82 -mx C3 A_1_ pin 60 mx C20 RN_BGACK_030 mcell H4 -mx C4 inst_AMIGA_DS mcell H2 mx C21 CYCLE_DMA_0_ mcell B13 -mx C5 SM_AMIGA_6_ mcell F0 mx C22 SM_AMIGA_4_ mcell G5 -mx C6 RW_000 pin 80 mx C23 ... ... -mx C7 CLK_000_D_0_ mcell D9 mx C24 ... ... -mx C8inst_AMIGA_BUS_ENABLE_DMA_LOW mcell C10 mx C25 RW pin 71 -mx C9 inst_AS_000_INT mcell C6 mx C26 ... ... -mx C10 CYCLE_DMA_1_ mcell B2 mx C27 CLK_000_D_1_ mcell H5 -mx C11 inst_AS_000_DMA mcell C13 mx C28 ... ... -mx C12 CLK_OUT_INTreg mcell A1 mx C29 ... ... -mx C13 inst_DS_000_DMA mcell C9 mx C30 ... ... -mx C14inst_CLK_OUT_PRE_D mcell E5 mx C31 ... ... +mx C0 RST pin 86 mx C17 BERR pin 41 +mx C1 RN_VMA mcell D0 mx C18 SM_AMIGA_4_ mcell A5 +mx C2 SM_AMIGA_3_ mcell C2 mx C19 ... ... +mx C3 CLK_000_D_1_ mcell A8 mx C20 RN_BGACK_030 mcell H4 +mx C4 IPL_2_ pin 68 mx C21 cpu_est_2_ mcell D13 +mx C5 CLK_000_D_0_ mcell F0 mx C22 cpu_est_1_ mcell G5 +mx C6 inst_DTACK_D0 mcell F13 mx C23 ... ... +mx C7 cpu_est_3_ mcell D9 mx C24 ... ... +mx C8inst_AMIGA_BUS_ENABLE_DMA_LOW mcell E8 mx C25 ... ... +mx C9 AS_030 pin 82 mx C26 ... ... +mx C10 cpu_est_0_ mcell F4 mx C27 ... ... +mx C11 inst_VPA_D mcell B6 mx C28 SM_AMIGA_6_ mcell B13 +mx C12 ... ... mx C29 ... ... +mx C13 SM_AMIGA_2_ mcell C9 mx C30 inst_AS_000_INT mcell C13 +mx C14 ... ... mx C31 ... ... mx C15 ... ... mx C32 ... ... -mx C16 AS_000 pin 42 +mx C16 ... ... ---------------------------------------------------------------------------- @@ -874,23 +887,23 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 RST pin 86 mx D17 ... ... -mx D1 RN_VMA mcell D0 mx D18 cpu_est_3_ mcell A8 -mx D2 RN_BG_000 mcell D1 mx D19 AS_030 pin 82 -mx D3 CLK_000 pin 11 mx D20 RN_BGACK_030 mcell H4 -mx D4 BG_030 pin 21 mx D21 IPL_1_ pin 56 -mx D5 nEXP_SPACE pin 14 mx D22inst_DS_000_ENABLE mcell C2 -mx D6 ... ... mx D23 inst_VPA_D mcell G6 -mx D7 CLK_000_D_0_ mcell D9 mx D24 ... ... -mx D8inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell A10 mx D25 ... ... -mx D9inst_LDS_000_INT mcell G13 mx D26 ... ... -mx D10inst_AS_030_000_SYNC mcell F4 mx D27 ... ... -mx D11inst_UDS_000_INT mcell B6 mx D28 ... ... -mx D12 cpu_est_0_ mcell G9 mx D29 cpu_est_1_ mcell D13 -mx D13 CLK_000_D_1_ mcell H5 mx D30 inst_AS_030_D0 mcell E8 -mx D14 ... ... mx D31 ... ... -mx D15 ... ... mx D32 ... ... -mx D16 cpu_est_2_ mcell D2 +mx D0 A_0_ pin 69 mx D17 RN_BG_000 mcell D1 +mx D1 cpu_est_2_ mcell D13 mx D18 RN_VMA mcell D0 +mx D2inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell E9 mx D19inst_LDS_000_INT mcell A9 +mx D3 CLK_000_D_1_ mcell A8 mx D20inst_AS_030_000_SYNC mcell F8 +mx D4 BG_030 pin 21 mx D21 RST pin 86 +mx D5 CLK_000_D_0_ mcell F0 mx D22 cpu_est_1_ mcell G5 +mx D6 ... ... mx D23 RN_BGACK_030 mcell H4 +mx D7 cpu_est_3_ mcell D9 mx D24 ... ... +mx D8 ... ... mx D25inst_DS_000_ENABLE mcell A13 +mx D9 AS_030 pin 82 mx D26 ... ... +mx D10 cpu_est_0_ mcell F4 mx D27 ... ... +mx D11 inst_VPA_D mcell B6 mx D28 SM_AMIGA_6_ mcell B13 +mx D12 ... ... mx D29 ... ... +mx D13 ... ... mx D30 ... ... +mx D14 CLK_000_D_2_ mcell H2 mx D31 inst_AS_030_D0 mcell F12 +mx D15 nEXP_SPACE pin 14 mx D32 ... ... +mx D16inst_UDS_000_INT mcell D6 ---------------------------------------------------------------------------- @@ -898,23 +911,23 @@ BLOCK_E_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx E0 RST pin 86 mx E17 A_DECODE_18_ pin 95 +mx E0 RST pin 86 mx E17 A_DECODE_20_ pin 93 mx E1 FC_1_ pin 58 mx E18 BGACK_000 pin 28 -mx E2 AS_000 pin 42 mx E19inst_CLK_OUT_PRE_50 mcell H13 -mx E3 AHIGH_27_ pin 16 mx E20 AHIGH_24_ pin 19 -mx E4 AHIGH_29_ pin 6 mx E21 RW_000 pin 80 -mx E5 nEXP_SPACE pin 14 mx E22 AHIGH_25_ pin 18 -mx E6 A_DECODE_16_ pin 96 mx E23 RN_BGACK_030 mcell H4 +mx E2 AS_000 pin 42 mx E19 AHIGH_30_ pin 5 +mx E3 AHIGH_27_ pin 16 mx E20 RN_BGACK_030 mcell H4 +mx E4 A_DECODE_18_ pin 95 mx E21 nEXP_SPACE pin 14 +mx E5 AHIGH_24_ pin 19 mx E22 AHIGH_25_ pin 18 +mx E6 A_DECODE_16_ pin 96 mx E23 A_1_ pin 60 mx E7 AHIGH_28_ pin 15 mx E24 FC_0_ pin 57 -mx E8 FPU_SENSE pin 91 mx E25 AHIGH_31_ pin 4 -mx E9 AS_030 pin 82 mx E26 AHIGH_26_ pin 17 -mx E10 ... ... mx E27 inst_AS_000_INT mcell C6 -mx E11 A_DECODE_22_ pin 84 mx E28 AHIGH_30_ pin 5 -mx E12 A_DECODE_19_ pin 97 mx E29 A_DECODE_20_ pin 93 -mx E13 A_DECODE_17_ pin 59 mx E30 ... ... -mx E14 N_60 mcell E9 mx E31 ... ... -mx E15 A_DECODE_21_ pin 94 mx E32 A_DECODE_23_ pin 85 -mx E16 inst_AS_030_D0 mcell E8 +mx E8 A_DECODE_23_ pin 85 mx E25 AHIGH_31_ pin 4 +mx E9 A_DECODE_22_ pin 84 mx E26 AHIGH_26_ pin 17 +mx E10 ... ... mx E27 A_DECODE_17_ pin 59 +mx E11 FPU_SENSE pin 91 mx E28 RW_000 pin 80 +mx E12 A_DECODE_19_ pin 97 mx E29 ... ... +mx E13 AHIGH_29_ pin 6 mx E30 inst_AS_000_INT mcell C13 +mx E14 N_205 mcell E5 mx E31 inst_AS_030_D0 mcell F12 +mx E15 A_DECODE_21_ pin 94 mx E32 AS_030 pin 82 +mx E16 ... ... ---------------------------------------------------------------------------- @@ -922,23 +935,23 @@ BLOCK_F_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx F0 RST pin 86 mx F17 SM_AMIGA_5_ mcell F12 -mx F1 FC_1_ pin 58 mx F18 ... ... +mx F0 IPL_0_ pin 67 mx F17 inst_AS_030_D0 mcell F12 +mx F1 FC_1_ pin 58 mx F18 SM_AMIGA_i_7_ mcell B2 mx F2inst_BGACK_030_INT_D mcell E13 mx F19 AS_030 pin 82 -mx F3 ... ... mx F20 SM_AMIGA_i_7_ mcell F8 -mx F4 A_DECODE_18_ pin 95 mx F21 CLK_000_D_2_ mcell H6 +mx F3 CLK_000 pin 11 mx F20inst_AS_030_000_SYNC mcell F8 +mx F4 A_DECODE_18_ pin 95 mx F21 RST pin 86 mx F5 nEXP_SPACE pin 14 mx F22 ... ... mx F6 FC_0_ pin 57 mx F23 RN_BGACK_030 mcell H4 -mx F7 CLK_000_D_0_ mcell D9 mx F24 SM_AMIGA_0_ mcell A12 -mx F8 A_DECODE_17_ pin 59 mx F25 SM_AMIGA_6_ mcell F0 +mx F7 ... ... mx F24 ... ... +mx F8 A_DECODE_17_ pin 59 mx F25 CLK_000_D_0_ mcell F0 mx F9 DTACK pin 30 mx F26 ... ... mx F10 inst_AS_030_D1 mcell F1 mx F27 ... ... mx F11 A_DECODE_16_ pin 96 mx F28 ... ... -mx F12 A_DECODE_19_ pin 97 mx F29inst_AS_030_000_SYNC mcell F4 -mx F13 CLK_000_D_1_ mcell H5 mx F30 ... ... -mx F14 CLK_000_D_4_ mcell F5 mx F31 ... ... -mx F15 CLK_000_D_3_ mcell F13 mx F32 ... ... -mx F16 inst_AS_030_D0 mcell E8 +mx F12 A_DECODE_19_ pin 97 mx F29 ... ... +mx F13 ... ... mx F30 CLK_000_D_1_ mcell A8 +mx F14 cpu_est_0_ mcell F4 mx F31 ... ... +mx F15 ... ... mx F32 ... ... +mx F16 CLK_000_D_3_ mcell D2 ---------------------------------------------------------------------------- @@ -946,22 +959,22 @@ BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx G0 RST pin 86 mx G17 ... ... -mx G1 SM_AMIGA_5_ mcell F12 mx G18 cpu_est_3_ mcell A8 -mx G2 SM_AMIGA_1_ mcell A5 mx G19 AS_030 pin 82 -mx G3 cpu_est_2_ mcell D2 mx G20 RN_BGACK_030 mcell H4 -mx G4 inst_DSACK1_INT mcell G2 mx G21 cpu_est_1_ mcell D13 -mx G5 SM_AMIGA_6_ mcell F0 mx G22 SM_AMIGA_4_ mcell G5 -mx G6 SIZE_1_ pin 79 mx G23 ... ... -mx G7 CLK_000_D_0_ mcell D9 mx G24 LDS_000 pin 31 -mx G8 UDS_000 pin 32 mx G25 ... ... -mx G9inst_LDS_000_INT mcell G13 mx G26 ... ... -mx G10 VPA pin 36 mx G27 cpu_est_0_ mcell G9 -mx G11 ... ... mx G28 RW_000 pin 80 -mx G12 CLK_OUT_INTreg mcell A1 mx G29 ... ... -mx G13 CLK_000_D_1_ mcell H5 mx G30 ... ... -mx G14 SIZE_0_ pin 70 mx G31 ... ... -mx G15 A_0_ pin 69 mx G32 ... ... +mx G0 CLK_OUT_INTreg mcell A2 mx G17 ... ... +mx G1 cpu_est_2_ mcell D13 mx G18 CLK_000_D_1_ mcell A8 +mx G2 AS_000 pin 42 mx G19 AS_030 pin 82 +mx G3 cpu_est_1_ mcell G5 mx G20 RN_BGACK_030 mcell H4 +mx G4inst_CLK_OUT_PRE_D mcell H5 mx G21 RST pin 86 +mx G5 CLK_000_D_0_ mcell F0 mx G22 CYCLE_DMA_1_ mcell G10 +mx G6 RW_000 pin 80 mx G23 CYCLE_DMA_0_ mcell G6 +mx G7 inst_AMIGA_DS mcell H13 mx G24 LDS_000 pin 31 +mx G8 UDS_000 pin 32 mx G25 cpu_est_3_ mcell D9 +mx G9 SM_AMIGA_1_ mcell A1 mx G26 ... ... +mx G10 inst_DS_000_DMA mcell G9 mx G27 ... ... +mx G11 ... ... mx G28 ... ... +mx G12 inst_AS_000_DMA mcell G13 mx G29 ... ... +mx G13 ... ... mx G30 ... ... +mx G14 cpu_est_0_ mcell F4 mx G31 inst_DSACK1_INT mcell G2 +mx G15 ... ... mx G32 ... ... mx G16 ... ... ---------------------------------------------------------------------------- @@ -970,23 +983,23 @@ BLOCK_H_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx H0 RST pin 86 mx H17 FC_0_ pin 57 -mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28 -mx H2 SM_AMIGA_i_7_ mcell F8 mx H19 FPU_SENSE pin 91 -mx H3 ... ... mx H20 RN_BGACK_030 mcell H4 -mx H4 A_DECODE_18_ pin 95 mx H21 ... ... -mx H5 SM_AMIGA_6_ mcell F0 mx H22 ... ... -mx H6 A_DECODE_19_ pin 97 mx H23 RN_RW_000 mcell H0 -mx H7inst_CLK_OUT_PRE_50 mcell H13 mx H24 LDS_000 pin 31 -mx H8 RW pin 71 mx H25 CLK_000_D_0_ mcell D9 -mx H9 SM_AMIGA_0_ mcell A12 mx H26 ... ... -mx H10 ... ... mx H27 CLK_000_D_1_ mcell H5 +mx H0 LDS_000 pin 31 mx H17 FC_0_ pin 57 +mx H1 FC_1_ pin 58 mx H18 SM_AMIGA_i_7_ mcell B2 +mx H2 AS_000 pin 42 mx H19 FPU_SENSE pin 91 +mx H3 CLK_000_D_1_ mcell A8 mx H20 RN_BGACK_030 mcell H4 +mx H4 BGACK_000 pin 28 mx H21 RST pin 86 +mx H5 CLK_000_D_0_ mcell F0 mx H22 ... ... +mx H6 A_DECODE_19_ pin 97 mx H23 inst_DSACK1_INT mcell G2 +mx H7inst_CLK_OUT_PRE_50 mcell H6 mx H24 SM_AMIGA_0_ mcell A12 +mx H8 RW pin 71 mx H25 inst_AS_000_DMA mcell G13 +mx H9 AS_030 pin 82 mx H26 ... ... +mx H10 SM_AMIGA_6_ mcell B13 mx H27 ... ... mx H11 A_DECODE_16_ pin 96 mx H28 ... ... mx H12 UDS_000 pin 32 mx H29 ... ... -mx H13 A_DECODE_17_ pin 59 mx H30 inst_AS_000_DMA mcell C13 -mx H14 ... ... mx H31 inst_DSACK1_INT mcell G2 -mx H15 nEXP_SPACE pin 14 mx H32 AS_030 pin 82 -mx H16 AS_000 pin 42 +mx H13 A_DECODE_17_ pin 59 mx H30 RN_RW_000 mcell H0 +mx H14 ... ... mx H31 A_DECODE_18_ pin 95 +mx H15 nEXP_SPACE pin 14 mx H32 ... ... +mx H16 ... ... ---------------------------------------------------------------------------- CSM indicates the mux inputs from the Central Switch Matrix. @@ -1001,6 +1014,14 @@ PostFit_Equations P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- + 0 0 1 Pin AHIGH_30_ + 1 1 1 Pin AHIGH_30_.OE + 0 0 1 Pin AHIGH_31_ + 1 1 1 Pin AHIGH_31_.OE + 0 0 1 Pin AHIGH_29_ + 1 1 1 Pin AHIGH_29_.OE + 0 0 1 Pin AHIGH_28_ + 1 1 1 Pin AHIGH_28_.OE 0 0 1 Pin AHIGH_27_ 1 1 1 Pin AHIGH_27_.OE 0 0 1 Pin AHIGH_26_ @@ -1009,8 +1030,6 @@ PostFit_Equations 1 1 1 Pin AHIGH_25_.OE 0 0 1 Pin AHIGH_24_ 1 1 1 Pin AHIGH_24_.OE - 0 0 1 Pin AHIGH_31_ - 1 1 1 Pin AHIGH_31_.OE 1 2 1 Pin AS_030- 1 1 1 Pin AS_030.OE 1 2 1 Pin AS_000- @@ -1036,15 +1055,12 @@ PostFit_Equations 2 4 1 Pin AMIGA_BUS_ENABLE_HIGH- 1 13 1 Pin CIIN 1 1 1 Pin CIIN.OE - 0 0 1 Pin AHIGH_30_ - 1 1 1 Pin AHIGH_30_.OE - 0 0 1 Pin AHIGH_29_ - 1 1 1 Pin AHIGH_29_.OE - 0 0 1 Pin AHIGH_28_ - 1 1 1 Pin AHIGH_28_.OE 1 1 1 Pin SIZE_1_.OE 2 4 1 Pin SIZE_1_.D 1 1 1 Pin SIZE_1_.C + 1 1 1 Pin SIZE_0_.OE + 2 4 1 Pin SIZE_0_.D- + 1 1 1 Pin SIZE_0_.C 10 8 1 Pin IPL_030_2_.D- 1 1 1 Pin IPL_030_2_.C 1 2 1 Pin RW_000.OE @@ -1067,9 +1083,6 @@ PostFit_Equations 1 1 1 Pin RW.OE 1 3 1 Pin RW.D- 1 1 1 Pin RW.C - 1 1 1 Pin SIZE_0_.OE - 2 4 1 Pin SIZE_0_.D- - 1 1 1 Pin SIZE_0_.C 3 3 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C 4 5 1 Node cpu_est_1_.D @@ -1079,9 +1092,9 @@ PostFit_Equations 1 1 1 Node cpu_est_2_.C 4 6 1 Node cpu_est_3_.D 1 1 1 Node cpu_est_3_.C - 1 3 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- + 2 16 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C - 1 3 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- + 4 16 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 2 1 Node inst_AS_030_D0.D- 1 1 1 Node inst_AS_030_D0.C @@ -1154,9 +1167,9 @@ PostFit_Equations 3 9 1 NodeX1 SM_AMIGA_i_7_.T.X1 1 9 1 NodeX2 SM_AMIGA_i_7_.T.X2 1 1 1 Node SM_AMIGA_i_7_.C - 2 14 1 Node N_60 + 2 14 1 Node N_205 ========= - 243 P-Term Total: 243 + 247 P-Term Total: 247 Total Pins: 59 Total Nodes: 42 Average P-Term/Output: 2 @@ -1164,6 +1177,22 @@ PostFit_Equations Equations: +AHIGH_30_ = (0); + +AHIGH_30_.OE = (!BGACK_030.Q); + +AHIGH_31_ = (0); + +AHIGH_31_.OE = (!BGACK_030.Q); + +AHIGH_29_ = (0); + +AHIGH_29_.OE = (!BGACK_030.Q); + +AHIGH_28_ = (0); + +AHIGH_28_.OE = (!BGACK_030.Q); + AHIGH_27_ = (0); AHIGH_27_.OE = (!BGACK_030.Q); @@ -1180,10 +1209,6 @@ AHIGH_24_ = (0); AHIGH_24_.OE = (!BGACK_030.Q); -AHIGH_31_ = (0); - -AHIGH_31_.OE = (!BGACK_030.Q); - !AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN); AS_030.OE = (!BGACK_030.Q); @@ -1235,19 +1260,7 @@ AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); -CIIN.OE = (N_60); - -AHIGH_30_ = (0); - -AHIGH_30_.OE = (!BGACK_030.Q); - -AHIGH_29_ = (0); - -AHIGH_29_.OE = (!BGACK_030.Q); - -AHIGH_28_ = (0); - -AHIGH_28_.OE = (!BGACK_030.Q); +CIIN.OE = (N_205); SIZE_1_.OE = (!BGACK_030.Q); @@ -1256,6 +1269,13 @@ SIZE_1_.D = (!RST SIZE_1_.C = (CLK_OSZI); +SIZE_0_.OE = (!BGACK_030.Q); + +!SIZE_0_.D = (RST & BGACK_030.Q + # RST & !UDS_000.PIN & !LDS_000.PIN); + +SIZE_0_.C = (CLK_OSZI); + !IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q @@ -1336,13 +1356,6 @@ RW.OE = (!BGACK_030.Q); RW.C = (CLK_OSZI); -SIZE_0_.OE = (!BGACK_030.Q); - -!SIZE_0_.D = (RST & BGACK_030.Q - # RST & !UDS_000.PIN & !LDS_000.PIN); - -SIZE_0_.C = (CLK_OSZI); - cpu_est_0_.D = (cpu_est_0_.Q & !CLK_000_D_1_.Q # cpu_est_0_.Q & CLK_000_D_0_.Q # !cpu_est_0_.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q); @@ -1369,11 +1382,15 @@ cpu_est_3_.D = (!cpu_est_0_.Q & cpu_est_3_.Q cpu_est_3_.C = (CLK_OSZI); -!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q); +!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q + # A_DECODE_23_ & RST & A_DECODE_22_ & A_DECODE_21_ & !A_DECODE_20_ & A_DECODE_19_ & !BGACK_030.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); -!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q); +inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (!RST + # !A_1_ + # BGACK_030.Q + # A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & !A_DECODE_20_ & A_DECODE_19_ & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); @@ -1568,7 +1585,7 @@ SM_AMIGA_i_7_.T.X2 = (nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & !CLK_000_D_3_ SM_AMIGA_i_7_.C = (CLK_OSZI); -N_60 = (nEXP_SPACE +N_205 = (nEXP_SPACE # A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index 37bb500..4843ad2 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -54,6 +54,7 @@ inst_LDS_000_INT 1 1 1 1 .. .. 2 2 AS_000 .. .. .. .. 1 1 .. .. CIIN .. .. .. .. 1 1 .. .. SIZE_1_ 1 1 0 0 .. .. .. .. + SIZE_0_ 1 1 0 0 .. .. .. .. IPL_030_2_ 1 1 0 0 .. .. 1 1 RN_IPL_030_2_ 1 1 0 0 .. .. 1 1 RW_000 1 1 0 0 .. .. 1 1 @@ -68,7 +69,6 @@ inst_LDS_000_INT 1 1 1 1 .. .. 2 2 VMA 1 1 0 0 .. .. 1 1 RN_VMA 1 1 0 0 .. .. 1 1 RW 1 1 0 0 .. .. .. .. - SIZE_0_ 1 1 0 0 .. .. .. .. cpu_est_0_ .. .. .. .. .. .. 1 1 cpu_est_1_ .. .. 1 1 .. .. 1 1 cpu_est_2_ .. .. 1 1 .. .. 1 1 @@ -99,4 +99,4 @@ inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1 SM_AMIGA_2_ 1 1 .. .. .. .. 1 1 CLK_OUT_INTreg .. .. 1 1 .. .. 1 1 SM_AMIGA_i_7_ 1 1 .. .. .. .. 1 1 - N_60 .. .. .. .. 1 1 .. .. \ No newline at end of file + N_205 .. .. .. .. 1 1 .. .. \ No newline at end of file diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index 60c0ec6..7f23952 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,14 +1,14 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Sat Dec 30 00:43:37 2017 +#$ DATE Thu Jan 11 20:16:29 2018 #$ MODULE 68030_tk -#$ PINS 59 AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_000 IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA RST AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN AHIGH_30_ AHIGH_29_ AHIGH_28_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ IPL_030_0_ VMA RW SIZE_0_ -#$ NODES 42 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_D1 inst_AS_030_000_SYNC inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT inst_BGACK_030_INT_D SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ CLK_OUT_INTreg SM_AMIGA_i_7_ N_60 +#$ PINS 59 AHIGH_30_ AHIGH_31_ AHIGH_29_ AHIGH_28_ A_DECODE_23_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_DECODE_22_ A_DECODE_21_ IPL_2_ A_DECODE_20_ A_DECODE_19_ FC_1_ A_DECODE_18_ AS_030 A_DECODE_17_ AS_000 A_DECODE_16_ DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 IPL_1_ DTACK IPL_0_ AVEC FC_0_ E A_1_ VPA RST AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_1_ SIZE_0_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ IPL_030_0_ VMA RW +#$ NODES 42 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_D1 inst_AS_030_000_SYNC inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT inst_BGACK_030_INT_D SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ CLK_OUT_INTreg SM_AMIGA_i_7_ N_205 .type fr .i 90 .o 152 -.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_D1.Q inst_AS_030_000_SYNC.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q VMA.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_AMIGA_DS.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_4_.Q inst_UDS_000_INT.Q inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q inst_BGACK_030_INT_D.Q SM_AMIGA_6_.Q RW_000.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q IPL_030_1_.Q SM_AMIGA_i_7_.Q IPL_030_2_.Q N_60 AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN -.ob DS_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C SIZE_0_.C SIZE_1_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C CLK_000_D_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_VPA_D.C inst_DTACK_D0.C inst_DS_000_ENABLE.C BG_000.C inst_LDS_000_INT.C VMA.C RW_000.C inst_AS_030_000_SYNC.C BGACK_030.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_DSACK1_INT.C inst_AS_000_INT.C inst_AMIGA_DS.C A_0_.C RW.C inst_AS_030_D0.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D1.C inst_UDS_000_INT.C inst_BGACK_030_INT_D.C CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.C AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ N_60 AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE VMA.OE CIIN.OE BGACK_030.D cpu_est_0_.D cpu_est_1_.D cpu_est_2_.D cpu_est_3_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_D1.D inst_AS_030_000_SYNC.D inst_AS_000_DMA.D inst_DS_000_DMA.D VMA.T inst_VPA_D.D CLK_000_D_3_.D inst_DTACK_D0.D inst_AMIGA_DS.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_4_.D SIZE_0_.D SIZE_1_.D A_0_.D RW.D inst_UDS_000_INT.D inst_DS_000_ENABLE.D inst_LDS_000_INT.D inst_BGACK_030_INT_D.D SM_AMIGA_6_.D RW_000.D SM_AMIGA_4_.D SM_AMIGA_1_.D SM_AMIGA_0_.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D inst_DSACK1_INT.D inst_AS_000_INT.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D BG_000.D CLK_OUT_INTreg.D IPL_030_0_.D IPL_030_1_.D SM_AMIGA_i_7_.T IPL_030_2_.D -.p 421 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_D1.Q inst_AS_030_000_SYNC.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q VMA.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_AMIGA_DS.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_4_.Q inst_UDS_000_INT.Q inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q inst_BGACK_030_INT_D.Q SM_AMIGA_6_.Q RW_000.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q IPL_030_1_.Q SM_AMIGA_i_7_.Q IPL_030_2_.Q N_205 AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN +.ob DS_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C SIZE_0_.C SIZE_1_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C cpu_est_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_DSACK1_INT.C inst_AS_000_INT.C inst_AMIGA_DS.C A_0_.C RW.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C inst_DS_000_ENABLE.C inst_AS_030_D1.C inst_UDS_000_INT.C BG_000.C inst_LDS_000_INT.C VMA.C RW_000.C inst_AS_030_000_SYNC.C BGACK_030.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_BGACK_030_INT_D.C CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.C AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ N_205 AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE VMA.OE CIIN.OE BGACK_030.D cpu_est_0_.D cpu_est_1_.D cpu_est_2_.D cpu_est_3_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_D1.D inst_AS_030_000_SYNC.D inst_AS_000_DMA.D inst_DS_000_DMA.D VMA.T inst_VPA_D.D CLK_000_D_3_.D inst_DTACK_D0.D inst_AMIGA_DS.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_4_.D SIZE_0_.D SIZE_1_.D A_0_.D RW.D inst_UDS_000_INT.D inst_DS_000_ENABLE.D inst_LDS_000_INT.D inst_BGACK_030_INT_D.D SM_AMIGA_6_.D RW_000.D SM_AMIGA_4_.D SM_AMIGA_1_.D SM_AMIGA_0_.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D inst_DSACK1_INT.D inst_AS_000_INT.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D BG_000.D CLK_OUT_INTreg.D IPL_030_0_.D IPL_030_1_.D SM_AMIGA_i_7_.T IPL_030_2_.D +.p 447 ------------------------------------------------------------------------------------------ ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -1---------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --0--------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -28,7 +28,11 @@ -------------------1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------0-------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +0---------------------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0---------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0--------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------1-------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------0------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------0------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------1------------------------------------------------------------------ ~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~11~~~~~~~~~~~~~~~~~~~~~~1~~~1~~~~~~~~~~~~~~~~~~ ---1-------------------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -183,6 +187,15 @@ -----------------------0----------------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------------------11------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------0---------------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1--------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1---------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1----------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1-----------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1-------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1--------------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1---------------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +1-----------1101---------------------------------------------------------------00000000--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1-----------111---------------0------------------------------------------------00000000--- ~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------1---------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------1-----------------------10--------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ @@ -221,7 +234,11 @@ -----------1-----------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~ -----------------------0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0000~~~~~~~~~~~~~~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------1-----------0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------1----------10------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +0----------1----------10------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------10---------10------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1-0--------10------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1--1-------10------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1---0------10------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------1----------00------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------00---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------1--------------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -399,20 +416,29 @@ -----------1-----------------------------------------1------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------------1---------- ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0---------------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10-------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------------------------1--------- ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0----------------------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10--------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------------------------1-------- ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0-----------------------------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10---------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------------------------------1------- ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0------------------------------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10----------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------------------------------1------ ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0-------------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10-----------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------------------------1----- ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0--------------------------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------------------1---- ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0---------------------------------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10-------------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------------------------------1--- ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0----------------------------------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10--------------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +1----------11101-------0-------------------------------------------------------00000000--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------1-----------------------------------------1---------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ -----------1-----------------------------------------1---------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ -----------1------------1-----------0----0----------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index 3ea4ce5..3c400eb 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,14 +1,14 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Sat Dec 30 00:43:37 2017 +#$ DATE Thu Jan 11 20:16:29 2018 #$ MODULE 68030_tk -#$ PINS 59 AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_000 IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA RST AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN AHIGH_30_ AHIGH_29_ AHIGH_28_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ IPL_030_0_ VMA RW SIZE_0_ -#$ NODES 42 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_D1 inst_AS_030_000_SYNC inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT inst_BGACK_030_INT_D SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ CLK_OUT_INTreg SM_AMIGA_i_7_ N_60 +#$ PINS 59 AHIGH_30_ AHIGH_31_ AHIGH_29_ AHIGH_28_ A_DECODE_23_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_DECODE_22_ A_DECODE_21_ IPL_2_ A_DECODE_20_ A_DECODE_19_ FC_1_ A_DECODE_18_ AS_030 A_DECODE_17_ AS_000 A_DECODE_16_ DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 IPL_1_ DTACK IPL_0_ AVEC FC_0_ E A_1_ VPA RST AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_1_ SIZE_0_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ IPL_030_0_ VMA RW +#$ NODES 42 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_D1 inst_AS_030_000_SYNC inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D CLK_000_D_3_ inst_DTACK_D0 inst_AMIGA_DS CLK_000_D_1_ CLK_000_D_0_ inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_D IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_4_ inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT inst_BGACK_030_INT_D SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ SM_AMIGA_3_ SM_AMIGA_2_ CLK_OUT_INTreg SM_AMIGA_i_7_ N_205 .type fr .i 90 .o 152 -.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_D1.Q inst_AS_030_000_SYNC.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q VMA.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_AMIGA_DS.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_4_.Q inst_UDS_000_INT.Q inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q inst_BGACK_030_INT_D.Q SM_AMIGA_6_.Q RW_000.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q IPL_030_1_.Q SM_AMIGA_i_7_.Q IPL_030_2_.Q N_60 AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN -.ob DS_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C SIZE_0_.C SIZE_1_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C CLK_000_D_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_VPA_D.C inst_DTACK_D0.C inst_DS_000_ENABLE.C BG_000.C inst_LDS_000_INT.C VMA.C RW_000.C inst_AS_030_000_SYNC.C BGACK_030.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_DSACK1_INT.C inst_AS_000_INT.C inst_AMIGA_DS.C A_0_.C RW.C inst_AS_030_D0.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D1.C inst_UDS_000_INT.C inst_BGACK_030_INT_D.C CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.C AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ N_60 AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE VMA.OE CIIN.OE BGACK_030.D cpu_est_0_.D cpu_est_1_.D cpu_est_2_.D cpu_est_3_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_D1.D inst_AS_030_000_SYNC.D inst_AS_000_DMA.D inst_DS_000_DMA.D VMA.T inst_VPA_D.D CLK_000_D_3_.D inst_DTACK_D0.D inst_AMIGA_DS.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_4_.D SIZE_0_.D SIZE_1_.D A_0_.D RW.D inst_UDS_000_INT.D inst_DS_000_ENABLE.D inst_LDS_000_INT.D inst_BGACK_030_INT_D.D SM_AMIGA_6_.D RW_000.D SM_AMIGA_4_.D SM_AMIGA_1_.D SM_AMIGA_0_.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D inst_DSACK1_INT.D inst_AS_000_INT.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D BG_000.D CLK_OUT_INTreg.D IPL_030_0_.D IPL_030_1_.D SM_AMIGA_i_7_.T IPL_030_2_.D -.p 421 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ BGACK_030.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_D1.Q inst_AS_030_000_SYNC.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q VMA.Q inst_VPA_D.Q CLK_000_D_3_.Q inst_DTACK_D0.Q inst_AMIGA_DS.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_D.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_4_.Q inst_UDS_000_INT.Q inst_DS_000_ENABLE.Q inst_LDS_000_INT.Q inst_BGACK_030_INT_D.Q SM_AMIGA_6_.Q RW_000.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q IPL_030_1_.Q SM_AMIGA_i_7_.Q IPL_030_2_.Q N_205 AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN +.ob DS_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C SIZE_0_.C SIZE_1_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C cpu_est_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_DSACK1_INT.C inst_AS_000_INT.C inst_AMIGA_DS.C A_0_.C RW.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C inst_DS_000_ENABLE.C inst_AS_030_D1.C inst_UDS_000_INT.C BG_000.C inst_LDS_000_INT.C VMA.C RW_000.C inst_AS_030_000_SYNC.C BGACK_030.C inst_AS_000_DMA.C inst_DS_000_DMA.C inst_BGACK_030_INT_D.C CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.C AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ N_205 AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE VMA.OE CIIN.OE BGACK_030.D cpu_est_0_.D cpu_est_1_.D cpu_est_2_.D cpu_est_3_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_D1.D inst_AS_030_000_SYNC.D inst_AS_000_DMA.D inst_DS_000_DMA.D VMA.T inst_VPA_D.D CLK_000_D_3_.D inst_DTACK_D0.D inst_AMIGA_DS.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_D.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_4_.D SIZE_0_.D SIZE_1_.D A_0_.D RW.D inst_UDS_000_INT.D inst_DS_000_ENABLE.D inst_LDS_000_INT.D inst_BGACK_030_INT_D.D SM_AMIGA_6_.D RW_000.D SM_AMIGA_4_.D SM_AMIGA_1_.D SM_AMIGA_0_.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D inst_DSACK1_INT.D inst_AS_000_INT.D SM_AMIGA_5_.D SM_AMIGA_3_.T SM_AMIGA_2_.D BG_000.D CLK_OUT_INTreg.D IPL_030_0_.D IPL_030_1_.D SM_AMIGA_i_7_.T IPL_030_2_.D +.p 447 ------------------------------------------------------------------------------------------ ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -1---------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --0--------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -28,7 +28,11 @@ -------------------1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------0-------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +0---------------------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0---------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0--------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------1-------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------0------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------0------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------1------------------------------------------------------------------ ~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~11~~~~~~~~~~~~~~~~~~~~~~1~~~1~~~~~~~~~~~~~~~~~~ ---1-------------------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -183,6 +187,15 @@ -----------------------0----------------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------------------11------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------0---------------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1--------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1---------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1----------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1-----------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1-------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1--------------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1---------------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +1-----------1101---------------------------------------------------------------00000000--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1-----------111---------------0------------------------------------------------00000000--- ~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------1---------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------1-----------------------10--------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ @@ -221,7 +234,11 @@ -----------1-----------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~ -----------------------0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0000~~~~~~~~~~~~~~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------1-----------0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------1----------10------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +0----------1----------10------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------10---------10------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1-0--------10------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1--1-------10------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1---0------10------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------1----------00------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------00---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------1--------------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -399,20 +416,29 @@ -----------1-----------------------------------------1------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------------1---------- ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0---------------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10-------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------------------------1--------- ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0----------------------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10--------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------------------------1-------- ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0-----------------------------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10---------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------------------------------1------- ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0------------------------------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10----------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------------------------------1------ ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0-------------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10-----------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------------------------1----- ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0--------------------------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------------------1---- ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0---------------------------------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10-------------------------------------------------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------------------------------1--- ~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---0----------------------------------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1----------10--------------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +1----------11101-------0-------------------------------------------------------00000000--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------1-----------------------------------------1---------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ -----------1-----------------------------------------1---------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ -----------1------------1-----------0----0----------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index def45c3..01ca5a7 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,14 +1,14 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Sat Dec 30 00:43:37 2017 +#$ DATE Thu Jan 11 20:16:29 2018 #$ MODULE BUS68030 -#$ PINS 59 AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ - A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ - A_DECODE_16_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR - BG_030 BGACK_000 CLK_000 IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ - FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA RST AMIGA_ADDR_ENABLE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN AHIGH_30_ - AHIGH_29_ AHIGH_28_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ - IPL_030_0_ VMA RW SIZE_0_ +#$ PINS 59 AHIGH_30_ AHIGH_31_ AHIGH_29_ AHIGH_28_ A_DECODE_23_ AHIGH_27_ + AHIGH_26_ AHIGH_25_ AHIGH_24_ A_DECODE_22_ A_DECODE_21_ IPL_2_ A_DECODE_20_ + A_DECODE_19_ FC_1_ A_DECODE_18_ AS_030 A_DECODE_17_ AS_000 A_DECODE_16_ DS_030 + UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_000 CLK_OSZI CLK_DIV_OUT + CLK_EXP FPU_CS FPU_SENSE DSACK1 IPL_1_ DTACK IPL_0_ AVEC FC_0_ E A_1_ VPA RST + AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH + CIIN SIZE_1_ SIZE_0_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ + IPL_030_0_ VMA RW #$ NODES 42 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_D1 inst_AS_030_000_SYNC inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D @@ -17,7 +17,7 @@ CLK_000_D_2_ CLK_000_D_4_ inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT inst_BGACK_030_INT_D SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ - SM_AMIGA_3_ SM_AMIGA_2_ CLK_OUT_INTreg SM_AMIGA_i_7_ N_60 + SM_AMIGA_3_ SM_AMIGA_2_ CLK_OUT_INTreg SM_AMIGA_i_7_ N_205 .type f .i 90 .o 154 @@ -34,107 +34,106 @@ inst_BGACK_030_INT_D.Q SM_AMIGA_6_.Q RW_000.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q - IPL_030_1_.Q SM_AMIGA_i_7_.Q IPL_030_2_.Q N_60 AS_030.PIN AS_000.PIN RW_000.PIN + IPL_030_1_.Q SM_AMIGA_i_7_.Q IPL_030_2_.Q N_205 AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN -.ob AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE - AHIGH_24_ AHIGH_24_.OE AHIGH_31_ AHIGH_31_.OE AS_030% AS_030.OE AS_000% - AS_000.OE DS_030% DS_030.OE UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE - CLK_DIV_OUT CLK_EXP FPU_CS% DSACK1% DSACK1.OE AVEC E AMIGA_ADDR_ENABLE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH% CIIN CIIN.OE - AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE SIZE_1_.D - SIZE_1_.C SIZE_1_.OE IPL_030_2_.D% IPL_030_2_.C RW_000.D% RW_000.C RW_000.OE - BG_000.D% BG_000.C BGACK_030.D BGACK_030.C A_0_.D A_0_.C A_0_.OE IPL_030_1_.D% - IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C VMA.T VMA.C VMA.OE RW.D% RW.C RW.OE - SIZE_0_.D% SIZE_0_.C SIZE_0_.OE cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D - cpu_est_1_.C cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D - cpu_est_3_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% inst_AMIGA_BUS_ENABLE_DMA_HIGH.C - inst_AMIGA_BUS_ENABLE_DMA_LOW.D% inst_AMIGA_BUS_ENABLE_DMA_LOW.C - inst_AS_030_D0.D% inst_AS_030_D0.C inst_AS_030_D1.D inst_AS_030_D1.C - inst_AS_030_000_SYNC.D% inst_AS_030_000_SYNC.C inst_AS_000_DMA.D - inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_VPA_D.D% inst_VPA_D.C - CLK_000_D_3_.D CLK_000_D_3_.C inst_DTACK_D0.D% inst_DTACK_D0.C inst_AMIGA_DS.D - inst_AMIGA_DS.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C - inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D - inst_CLK_OUT_PRE_D.C IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C - IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_4_.D - CLK_000_D_4_.C inst_UDS_000_INT.D% inst_UDS_000_INT.C inst_DS_000_ENABLE.D - inst_DS_000_ENABLE.C inst_LDS_000_INT.D inst_LDS_000_INT.C - inst_BGACK_030_INT_D.D% inst_BGACK_030_INT_D.C SM_AMIGA_6_.D SM_AMIGA_6_.C - SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D - SM_AMIGA_0_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C - inst_DSACK1_INT.D% inst_DSACK1_INT.C inst_AS_000_INT.D% inst_AS_000_INT.C - SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.T SM_AMIGA_3_.C SM_AMIGA_2_.D - SM_AMIGA_2_.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C SM_AMIGA_i_7_.T.X1 - SM_AMIGA_i_7_.T.X2 SM_AMIGA_i_7_.C N_60 +.ob AHIGH_30_ AHIGH_30_.OE AHIGH_31_ AHIGH_31_.OE AHIGH_29_ AHIGH_29_.OE + AHIGH_28_ AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_ + AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE AS_030% AS_030.OE AS_000% AS_000.OE DS_030% + DS_030.OE UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE CLK_DIV_OUT + CLK_EXP FPU_CS% DSACK1% DSACK1.OE AVEC E AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR + AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH% CIIN CIIN.OE SIZE_1_.D SIZE_1_.C + SIZE_1_.OE SIZE_0_.D% SIZE_0_.C SIZE_0_.OE IPL_030_2_.D% IPL_030_2_.C RW_000.D% + RW_000.C RW_000.OE BG_000.D% BG_000.C BGACK_030.D BGACK_030.C A_0_.D A_0_.C + A_0_.OE IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C VMA.T VMA.C VMA.OE + RW.D% RW.C RW.OE cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C + cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C + inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% inst_AMIGA_BUS_ENABLE_DMA_HIGH.C + inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% + inst_AS_030_D0.C inst_AS_030_D1.D inst_AS_030_D1.C inst_AS_030_000_SYNC.D% + inst_AS_030_000_SYNC.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D + inst_DS_000_DMA.C inst_VPA_D.D% inst_VPA_D.C CLK_000_D_3_.D CLK_000_D_3_.C + inst_DTACK_D0.D% inst_DTACK_D0.C inst_AMIGA_DS.D inst_AMIGA_DS.C CLK_000_D_1_.D + CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_OUT_PRE_50.D + inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D% + IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_2_.D + CLK_000_D_2_.C CLK_000_D_4_.D CLK_000_D_4_.C inst_UDS_000_INT.D% + inst_UDS_000_INT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_LDS_000_INT.D + inst_LDS_000_INT.C inst_BGACK_030_INT_D.D% inst_BGACK_030_INT_D.C SM_AMIGA_6_.D + SM_AMIGA_6_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_1_.D SM_AMIGA_1_.C + SM_AMIGA_0_.D SM_AMIGA_0_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D + CYCLE_DMA_1_.C inst_DSACK1_INT.D% inst_DSACK1_INT.C inst_AS_000_INT.D% + inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.T SM_AMIGA_3_.C + SM_AMIGA_2_.D SM_AMIGA_2_.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C SM_AMIGA_i_7_.T.X1 + SM_AMIGA_i_7_.T.X2 SM_AMIGA_i_7_.C N_205 .phase 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-----------1------------------------------------------------------------0----------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000 -----------1------------------1----------------------------------------------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000 -----------0-------------------1---------------------------------------------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000 diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index 5e7852b..82a5b1f 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,14 +1,14 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Sat Dec 30 00:43:37 2017 +#$ DATE Thu Jan 11 20:16:29 2018 #$ MODULE BUS68030 -#$ PINS 59 AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ - A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ - A_DECODE_16_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR - BG_030 BGACK_000 CLK_000 IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ - FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA RST AMIGA_ADDR_ENABLE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN AHIGH_30_ - AHIGH_29_ AHIGH_28_ SIZE_1_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ - IPL_030_0_ VMA RW SIZE_0_ +#$ PINS 59 AHIGH_30_ AHIGH_31_ AHIGH_29_ AHIGH_28_ A_DECODE_23_ AHIGH_27_ + AHIGH_26_ AHIGH_25_ AHIGH_24_ A_DECODE_22_ A_DECODE_21_ IPL_2_ A_DECODE_20_ + A_DECODE_19_ FC_1_ A_DECODE_18_ AS_030 A_DECODE_17_ AS_000 A_DECODE_16_ DS_030 + UDS_000 LDS_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_000 CLK_OSZI CLK_DIV_OUT + CLK_EXP FPU_CS FPU_SENSE DSACK1 IPL_1_ DTACK IPL_0_ AVEC FC_0_ E A_1_ VPA RST + AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH + CIIN SIZE_1_ SIZE_0_ IPL_030_2_ RW_000 BG_000 BGACK_030 A_0_ IPL_030_1_ + IPL_030_0_ VMA RW #$ NODES 42 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_D1 inst_AS_030_000_SYNC inst_AS_000_DMA inst_DS_000_DMA inst_VPA_D @@ -17,7 +17,7 @@ CLK_000_D_2_ CLK_000_D_4_ inst_UDS_000_INT inst_DS_000_ENABLE inst_LDS_000_INT inst_BGACK_030_INT_D SM_AMIGA_6_ SM_AMIGA_4_ SM_AMIGA_1_ SM_AMIGA_0_ CYCLE_DMA_0_ CYCLE_DMA_1_ inst_DSACK1_INT inst_AS_000_INT SM_AMIGA_5_ - SM_AMIGA_3_ SM_AMIGA_2_ CLK_OUT_INTreg SM_AMIGA_i_7_ N_60 + SM_AMIGA_3_ SM_AMIGA_2_ CLK_OUT_INTreg SM_AMIGA_i_7_ N_205 .type f .i 90 .o 154 @@ -34,107 +34,106 @@ inst_BGACK_030_INT_D.Q SM_AMIGA_6_.Q RW_000.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q SM_AMIGA_0_.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q inst_DSACK1_INT.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q BG_000.Q CLK_OUT_INTreg.Q IPL_030_0_.Q - IPL_030_1_.Q SM_AMIGA_i_7_.Q IPL_030_2_.Q N_60 AS_030.PIN AS_000.PIN RW_000.PIN + IPL_030_1_.Q SM_AMIGA_i_7_.Q IPL_030_2_.Q N_205 AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN -.ob AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_ AHIGH_25_.OE - AHIGH_24_ AHIGH_24_.OE AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE AS_000- - AS_000.OE DS_030- DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE - CLK_DIV_OUT CLK_EXP FPU_CS- DSACK1- DSACK1.OE AVEC E AMIGA_ADDR_ENABLE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH- CIIN CIIN.OE - AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE AHIGH_28_ AHIGH_28_.OE SIZE_1_.D - SIZE_1_.C SIZE_1_.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- RW_000.C RW_000.OE - BG_000.D- BG_000.C BGACK_030.D BGACK_030.C A_0_.D A_0_.C A_0_.OE IPL_030_1_.D- - IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C VMA.T VMA.C VMA.OE RW.D- RW.C RW.OE - SIZE_0_.D- SIZE_0_.C SIZE_0_.OE cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D - cpu_est_1_.C cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D - cpu_est_3_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C - inst_AMIGA_BUS_ENABLE_DMA_LOW.D- inst_AMIGA_BUS_ENABLE_DMA_LOW.C - inst_AS_030_D0.D- inst_AS_030_D0.C inst_AS_030_D1.D inst_AS_030_D1.C - inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C inst_AS_000_DMA.D - inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_VPA_D.D- inst_VPA_D.C - CLK_000_D_3_.D CLK_000_D_3_.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_AMIGA_DS.D - inst_AMIGA_DS.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C - inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D - inst_CLK_OUT_PRE_D.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C - IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_4_.D - CLK_000_D_4_.C inst_UDS_000_INT.D- inst_UDS_000_INT.C inst_DS_000_ENABLE.D - inst_DS_000_ENABLE.C inst_LDS_000_INT.D inst_LDS_000_INT.C - inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C SM_AMIGA_6_.D SM_AMIGA_6_.C - SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D - SM_AMIGA_0_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C - inst_DSACK1_INT.D- inst_DSACK1_INT.C inst_AS_000_INT.D- inst_AS_000_INT.C - SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.T SM_AMIGA_3_.C SM_AMIGA_2_.D - SM_AMIGA_2_.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C SM_AMIGA_i_7_.T.X1 - SM_AMIGA_i_7_.T.X2 SM_AMIGA_i_7_.C N_60 +.ob AHIGH_30_ AHIGH_30_.OE AHIGH_31_ AHIGH_31_.OE AHIGH_29_ AHIGH_29_.OE + AHIGH_28_ AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_ + AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE AS_030- AS_030.OE AS_000- AS_000.OE DS_030- + DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE CLK_DIV_OUT + CLK_EXP FPU_CS- DSACK1- DSACK1.OE AVEC E AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR + AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH- CIIN CIIN.OE SIZE_1_.D SIZE_1_.C + SIZE_1_.OE SIZE_0_.D- SIZE_0_.C SIZE_0_.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- + RW_000.C RW_000.OE BG_000.D- BG_000.C BGACK_030.D BGACK_030.C A_0_.D A_0_.C + A_0_.OE IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C VMA.T VMA.C VMA.OE + RW.D- RW.C RW.OE cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C + cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C + inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C + inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- + inst_AS_030_D0.C inst_AS_030_D1.D inst_AS_030_D1.C inst_AS_030_000_SYNC.D- + inst_AS_030_000_SYNC.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D + inst_DS_000_DMA.C inst_VPA_D.D- inst_VPA_D.C CLK_000_D_3_.D CLK_000_D_3_.C + inst_DTACK_D0.D- inst_DTACK_D0.C inst_AMIGA_DS.D inst_AMIGA_DS.C CLK_000_D_1_.D + CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_OUT_PRE_50.D + inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C IPL_D0_0_.D- + IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D + CLK_000_D_2_.C CLK_000_D_4_.D CLK_000_D_4_.C inst_UDS_000_INT.D- + inst_UDS_000_INT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_LDS_000_INT.D + inst_LDS_000_INT.C inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C SM_AMIGA_6_.D + SM_AMIGA_6_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_1_.D SM_AMIGA_1_.C + SM_AMIGA_0_.D SM_AMIGA_0_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D + CYCLE_DMA_1_.C inst_DSACK1_INT.D- inst_DSACK1_INT.C inst_AS_000_INT.D- + inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_3_.T SM_AMIGA_3_.C + SM_AMIGA_2_.D SM_AMIGA_2_.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C SM_AMIGA_i_7_.T.X1 + SM_AMIGA_i_7_.T.X2 SM_AMIGA_i_7_.C N_205 .phase 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 -.p 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+1----------11101-------0-------------------------------------------------------00000000--- 0000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000 +----------------------0------------------------------------------------------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000 +1-----------1101---------------------------------------------------------------00000000--- 0000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000 -----------1------------------------------------------------------------0----------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000 -----------1------------------1----------------------------------------------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000 -----------0-------------------1---------------------------------------------------------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000 diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index c80ce69..f18cd97 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 12/30/17; -TIME = 00:43:46; +DATE = 1/11/18; +TIME = 20:16:38; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -179,52 +179,52 @@ AMIGA_ADDR_ENABLE = OUTPUT,33,3,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-; CLK_EXP = OUTPUT,10,1,-; RN_BGACK_030 = NODE,-1,7,-; -CLK_000_D_0_ = NODE,*,3,-; -CLK_000_D_1_ = NODE,*,7,-; -SM_AMIGA_6_ = NODE,*,5,-; -cpu_est_3_ = NODE,*,0,-; -cpu_est_1_ = NODE,*,3,-; -SM_AMIGA_0_ = NODE,*,0,-; -SM_AMIGA_4_ = NODE,*,6,-; -cpu_est_0_ = NODE,*,6,-; -CLK_OUT_INTreg = NODE,*,0,-; -inst_AS_030_D0 = NODE,*,4,-; -cpu_est_2_ = NODE,*,3,-; +CLK_000_D_0_ = NODE,*,5,-; +CLK_000_D_1_ = NODE,*,0,-; +SM_AMIGA_6_ = NODE,*,1,-; +cpu_est_0_ = NODE,*,5,-; inst_AS_030_000_SYNC = NODE,*,5,-; -inst_DS_000_DMA = NODE,*,2,-; -inst_AS_000_DMA = NODE,*,2,-; -CYCLE_DMA_0_ = NODE,*,1,-; +cpu_est_3_ = NODE,*,3,-; +cpu_est_1_ = NODE,*,6,-; +SM_AMIGA_i_7_ = NODE,*,1,-; +SM_AMIGA_0_ = NODE,*,0,-; +inst_AS_030_D0 = NODE,*,5,-; +cpu_est_2_ = NODE,*,3,-; +inst_DS_000_DMA = NODE,*,6,-; +inst_AS_000_DMA = NODE,*,6,-; +SM_AMIGA_2_ = NODE,*,2,-; RN_VMA = NODE,-1,3,-; -SM_AMIGA_i_7_ = NODE,*,5,-; -SM_AMIGA_5_ = NODE,*,5,-; SM_AMIGA_1_ = NODE,*,0,-; -inst_LDS_000_INT = NODE,*,6,-; -inst_DS_000_ENABLE = NODE,*,2,-; +SM_AMIGA_4_ = NODE,*,0,-; +inst_LDS_000_INT = NODE,*,0,-; +inst_DS_000_ENABLE = NODE,*,0,-; inst_AS_000_INT = NODE,*,2,-; inst_DSACK1_INT = NODE,*,6,-; -CYCLE_DMA_1_ = NODE,*,1,-; -inst_UDS_000_INT = NODE,*,1,-; -inst_CLK_OUT_PRE_D = NODE,*,4,-; -inst_CLK_OUT_PRE_50 = NODE,*,7,-; -inst_VPA_D = NODE,*,6,-; +CLK_OUT_INTreg = NODE,*,0,-; +inst_CLK_OUT_PRE_D = NODE,*,7,-; +CLK_000_D_3_ = NODE,*,3,-; +inst_VPA_D = NODE,*,1,-; RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; RN_IPL_030_2_ = NODE,-1,1,-; -SM_AMIGA_2_ = NODE,*,0,-; -SM_AMIGA_3_ = NODE,*,0,-; +SM_AMIGA_3_ = NODE,*,2,-; RN_RW_000 = NODE,-1,7,-; +CYCLE_DMA_0_ = NODE,*,6,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,4,-; +SM_AMIGA_5_ = NODE,*,0,-; RN_BG_000 = NODE,-1,3,-; -N_60 = NODE,*,4,-; +N_205 = NODE,*,4,-; +CYCLE_DMA_1_ = NODE,*,6,-; +inst_UDS_000_INT = NODE,*,3,-; inst_AMIGA_DS = NODE,*,7,-; inst_AS_030_D1 = NODE,*,5,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,4,-; inst_BGACK_030_INT_D = NODE,*,4,-; CLK_000_D_4_ = NODE,*,5,-; CLK_000_D_2_ = NODE,*,7,-; -IPL_D0_2_ = NODE,*,0,-; -IPL_D0_1_ = NODE,*,3,-; -IPL_D0_0_ = NODE,*,0,-; +IPL_D0_2_ = NODE,*,2,-; +IPL_D0_1_ = NODE,*,0,-; +IPL_D0_0_ = NODE,*,5,-; +inst_CLK_OUT_PRE_50 = NODE,*,7,-; inst_DTACK_D0 = NODE,*,5,-; -CLK_000_D_3_ = NODE,*,5,-; -inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,2,-; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,0,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index d5cbe9e..f50180f 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 12/30/17; -TIME = 00:43:46; +DATE = 1/11/18; +TIME = 20:16:38; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -142,23 +142,26 @@ layer = OFF; [LOCATION ASSIGNMENT] Layer = OFF; +AHIGH_30_ = BIDIR,5, B,-; +AHIGH_31_ = BIDIR,4, B,-; +AHIGH_29_ = BIDIR,6, B,-; +AHIGH_28_ = BIDIR,15, C,-; +A_DECODE_23_ = INPUT,85, H,-; AHIGH_27_ = BIDIR,16, C,-; AHIGH_26_ = BIDIR,17, C,-; AHIGH_25_ = BIDIR,18, C,-; AHIGH_24_ = BIDIR,19, C,-; -AHIGH_31_ = BIDIR,4, B,-; A_DECODE_22_ = INPUT,84, H,-; A_DECODE_21_ = INPUT,94, A,-; -A_DECODE_23_ = INPUT,85, H,-; +IPL_2_ = INPUT,68, G,-; A_DECODE_20_ = INPUT,93, A,-; A_DECODE_19_ = INPUT,97, A,-; -A_DECODE_18_ = INPUT,95, A,-; -A_DECODE_17_ = INPUT,59, F,-; -A_DECODE_16_ = INPUT,96, A,-; -IPL_2_ = INPUT,68, G,-; FC_1_ = INPUT,58, F,-; +A_DECODE_18_ = INPUT,95, A,-; AS_030 = BIDIR,82, H,-; +A_DECODE_17_ = INPUT,59, F,-; AS_000 = BIDIR,42, E,-; +A_DECODE_16_ = INPUT,96, A,-; DS_030 = OUTPUT,98, A,-; UDS_000 = BIDIR,32, D,-; LDS_000 = BIDIR,31, D,-; @@ -167,19 +170,19 @@ BERR = BIDIR,41, E,-; BG_030 = INPUT,21, C,-; BGACK_000 = INPUT,28, D,-; CLK_000 = INPUT,11,-,-; -IPL_1_ = INPUT,56, F,-; CLK_OSZI = INPUT,61,-,-; -IPL_0_ = INPUT,67, G,-; CLK_DIV_OUT = OUTPUT,65, G,-; -FC_0_ = INPUT,57, F,-; CLK_EXP = OUTPUT,10, B,-; -A_1_ = INPUT,60, F,-; FPU_CS = OUTPUT,78, H,-; FPU_SENSE = INPUT,91, A,-; DSACK1 = OUTPUT,81, H,-; +IPL_1_ = INPUT,56, F,-; DTACK = INPUT,30, D,-; +IPL_0_ = INPUT,67, G,-; AVEC = OUTPUT,92, A,-; +FC_0_ = INPUT,57, F,-; E = OUTPUT,66, G,-; +A_1_ = INPUT,60, F,-; VPA = INPUT,36,-,-; RST = INPUT,86,-,-; AMIGA_ADDR_ENABLE = OUTPUT,33, D,-; @@ -187,10 +190,8 @@ AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-; CIIN = OUTPUT,47, E,-; -AHIGH_30_ = BIDIR,5, B,-; -AHIGH_29_ = BIDIR,6, B,-; -AHIGH_28_ = BIDIR,15, C,-; SIZE_1_ = BIDIR,79, H,-; +SIZE_0_ = BIDIR,70, G,-; IPL_030_2_ = OUTPUT,9, B,-; RW_000 = BIDIR,80, H,-; BG_000 = OUTPUT,29, D,-; @@ -200,46 +201,45 @@ IPL_030_1_ = OUTPUT,7, B,-; IPL_030_0_ = OUTPUT,8, B,-; VMA = OUTPUT,35, D,-; RW = BIDIR,71, G,-; -SIZE_0_ = BIDIR,70, G,-; -cpu_est_0_ = NODE,9, G,-; -cpu_est_1_ = NODE,13, D,-; -cpu_est_2_ = NODE,2, D,-; -cpu_est_3_ = NODE,8, A,-; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,10, A,-; -inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,10, C,-; -inst_AS_030_D0 = NODE,8, E,-; +cpu_est_0_ = NODE,4, F,-; +cpu_est_1_ = NODE,5, G,-; +cpu_est_2_ = NODE,13, D,-; +cpu_est_3_ = NODE,9, D,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,9, E,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,8, E,-; +inst_AS_030_D0 = NODE,12, F,-; inst_AS_030_D1 = NODE,1, F,-; -inst_AS_030_000_SYNC = NODE,4, F,-; -inst_AS_000_DMA = NODE,13, C,-; -inst_DS_000_DMA = NODE,9, C,-; -inst_VPA_D = NODE,6, G,-; -CLK_000_D_3_ = NODE,13, F,-; -inst_DTACK_D0 = NODE,9, F,-; -inst_AMIGA_DS = NODE,2, H,-; -CLK_000_D_1_ = NODE,5, H,-; -CLK_000_D_0_ = NODE,9, D,-; -inst_CLK_OUT_PRE_50 = NODE,13, H,-; -inst_CLK_OUT_PRE_D = NODE,5, E,-; -IPL_D0_0_ = NODE,6, A,-; -IPL_D0_1_ = NODE,6, D,-; -IPL_D0_2_ = NODE,2, A,-; -CLK_000_D_2_ = NODE,6, H,-; +inst_AS_030_000_SYNC = NODE,8, F,-; +inst_AS_000_DMA = NODE,13, G,-; +inst_DS_000_DMA = NODE,9, G,-; +inst_VPA_D = NODE,6, B,-; +CLK_000_D_3_ = NODE,2, D,-; +inst_DTACK_D0 = NODE,13, F,-; +inst_AMIGA_DS = NODE,13, H,-; +CLK_000_D_1_ = NODE,8, A,-; +CLK_000_D_0_ = NODE,0, F,-; +inst_CLK_OUT_PRE_50 = NODE,6, H,-; +inst_CLK_OUT_PRE_D = NODE,5, H,-; +IPL_D0_0_ = NODE,9, F,-; +IPL_D0_1_ = NODE,10, A,-; +IPL_D0_2_ = NODE,6, C,-; +CLK_000_D_2_ = NODE,2, H,-; CLK_000_D_4_ = NODE,5, F,-; -inst_UDS_000_INT = NODE,6, B,-; -inst_DS_000_ENABLE = NODE,2, C,-; -inst_LDS_000_INT = NODE,13, G,-; +inst_UDS_000_INT = NODE,6, D,-; +inst_DS_000_ENABLE = NODE,13, A,-; +inst_LDS_000_INT = NODE,9, A,-; inst_BGACK_030_INT_D = NODE,13, E,-; -SM_AMIGA_6_ = NODE,0, F,-; -SM_AMIGA_4_ = NODE,5, G,-; -SM_AMIGA_1_ = NODE,5, A,-; +SM_AMIGA_6_ = NODE,13, B,-; +SM_AMIGA_4_ = NODE,5, A,-; +SM_AMIGA_1_ = NODE,1, A,-; SM_AMIGA_0_ = NODE,12, A,-; -CYCLE_DMA_0_ = NODE,13, B,-; -CYCLE_DMA_1_ = NODE,2, B,-; +CYCLE_DMA_0_ = NODE,6, G,-; +CYCLE_DMA_1_ = NODE,10, G,-; inst_DSACK1_INT = NODE,2, G,-; -inst_AS_000_INT = NODE,6, C,-; -SM_AMIGA_5_ = NODE,12, F,-; -SM_AMIGA_3_ = NODE,13, A,-; -SM_AMIGA_2_ = NODE,9, A,-; -CLK_OUT_INTreg = NODE,1, A,-; -SM_AMIGA_i_7_ = NODE,8, F,-; -N_60 = NODE,9, E,-; +inst_AS_000_INT = NODE,13, C,-; +SM_AMIGA_5_ = NODE,6, A,-; +SM_AMIGA_3_ = NODE,2, C,-; +SM_AMIGA_2_ = NODE,9, C,-; +CLK_OUT_INTreg = NODE,2, A,-; +SM_AMIGA_i_7_ = NODE,2, B,-; +N_205 = NODE,5, E,-; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index 65e32ff..8140b29 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 2.0.00.17.20.15 -Design '68030_tk' created Sat Dec 30 00:43:37 2017 +Design '68030_tk' created Thu Jan 11 20:16:29 2018 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.zip b/Logic/68030_tk.zip index 6d92857..1eb2d54 100644 Binary files a/Logic/68030_tk.zip and b/Logic/68030_tk.zip differ diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index cb9b713..c2252bf 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,207 +1,209 @@ -#$ DATE Sat Dec 30 00:43:37 2017 +#$ DATE Thu Jan 11 20:16:29 2018 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 75 AHIGH_27_ AHIGH_26_ SIZE_1_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ IPL_030_2_ A_DECODE_16_ A_DECODE_15_ IPL_2_ A_DECODE_14_ A_DECODE_13_ FC_1_ A_DECODE_12_ AS_030 A_DECODE_11_ AS_000 A_DECODE_10_ RW_000 A_DECODE_9_ DS_030 A_DECODE_8_ UDS_000 A_DECODE_7_ LDS_000 A_DECODE_6_ nEXP_SPACE A_DECODE_5_ BERR A_DECODE_4_ BG_030 A_DECODE_3_ BG_000 A_DECODE_2_ BGACK_030 A_0_ BGACK_000 IPL_030_1_ CLK_030 IPL_030_0_ CLK_000 IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ -#$ NODES 508 N_23_0 UDS_000_c N_19_i N_22_0 LDS_000_c N_18_i N_21_0 size_c_0__n ipl_c_i_2__n N_43_0 \ -# size_c_1__n ipl_c_i_1__n inst_BGACK_030_INTreg N_42_0 vcc_n_n ahigh_c_24__n ipl_c_i_0__n un5_e N_41_0 gnd_n_n \ -# ahigh_c_25__n DTACK_c_i un1_amiga_bus_enable_low N_45_0 un3_as_030 ahigh_c_26__n VPA_c_i un1_UDS_000_INT N_44_0 un1_LDS_000_INT \ -# ahigh_c_27__n N_13_i un1_DS_000_ENABLE_0_sqmuxa N_27_0 un10_ciin ahigh_c_28__n LDS_000_INT_i un21_fpu_cs un1_LDS_000_INT_0 un21_berr \ -# ahigh_c_29__n UDS_000_INT_i un2_ds_030 un1_UDS_000_INT_0 cpu_est_0_ ahigh_c_30__n N_96_0_1 cpu_est_1_ N_96_0_2 cpu_est_2_ \ -# ahigh_c_31__n N_282_0_1 cpu_est_3_ N_282_0_2 inst_AMIGA_BUS_ENABLE_DMA_HIGH N_282_0_3 inst_AMIGA_BUS_ENABLE_DMA_LOW N_282_0_4 inst_AS_030_D0 pos_clk_un10_sm_amiga_i_1_n \ -# inst_AS_030_D1 un10_ciin_1 inst_AS_030_000_SYNC un10_ciin_2 inst_AS_000_DMA un10_ciin_3 inst_DS_000_DMA un10_ciin_4 inst_VMA_INTreg un10_ciin_5 \ -# inst_VPA_D un10_ciin_6 CLK_000_D_3_ un10_ciin_7 inst_DTACK_D0 un10_ciin_8 inst_AMIGA_DS un10_ciin_9 CLK_000_D_1_ un10_ciin_10 \ -# CLK_000_D_0_ un10_ciin_11 inst_CLK_OUT_PRE_50 N_201_1 inst_CLK_OUT_PRE_D N_201_2 IPL_D0_0_ N_131_i_1 IPL_D0_1_ N_134_0_1 \ -# IPL_D0_2_ N_113_i_1 CLK_000_D_2_ N_113_i_2 CLK_000_D_4_ N_144_1 pos_clk_ipl_n N_144_2 SIZE_DMA_0_ N_143_1 \ -# SIZE_DMA_1_ N_143_2 inst_A0_DMA N_163_1 inst_RW_000_DMA N_163_2 inst_UDS_000_INT N_163_3 inst_DS_000_ENABLE un21_fpu_cs_1 \ -# inst_LDS_000_INT a_decode_c_16__n un21_berr_1_0 inst_BGACK_030_INT_D pos_clk_cycle_dma_5_1_1__n SM_AMIGA_6_ a_decode_c_17__n N_199_1 inst_RW_000_INT AS_000_DMA_1_sqmuxa_1 \ -# SM_AMIGA_4_ a_decode_c_18__n N_140_1 SM_AMIGA_1_ N_66_i_1 SM_AMIGA_0_ a_decode_c_19__n N_66_i_2 CYCLE_DMA_0_ N_205_i_1 \ -# CYCLE_DMA_1_ a_decode_c_20__n N_205_i_2 inst_DSACK1_INT N_180_1 inst_AS_000_INT a_decode_c_21__n N_180_2 pos_clk_un9_clk_000_pe_n N_59_i_1 \ -# SM_AMIGA_5_ a_decode_c_22__n N_127_i_1 SM_AMIGA_3_ N_123_i_1 SM_AMIGA_2_ a_decode_c_23__n N_121_i_1 N_119_i_1 N_6 \ -# a_c_0__n N_117_i_1 N_115_i_1 a_c_1__n N_111_i_1 N_165_1 N_13 nEXP_SPACE_c N_162_1 N_148_1 \ -# N_18 BERR_c pos_clk_ipl_1_n N_19 ds_000_dma_0_un3_n N_20 BG_030_c ds_000_dma_0_un1_n ds_000_dma_0_un0_n BG_000DFFreg \ -# as_000_dma_0_un3_n as_000_dma_0_un1_n as_000_dma_0_un0_n BGACK_000_c uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n \ -# CLK_OSZI_c lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n CLK_OUT_INTreg as_030_d1_0_un3_n as_030_d1_0_un1_n as_030_d1_0_un0_n FPU_SENSE_c rw_000_int_0_un3_n \ -# rw_000_int_0_un1_n IPL_030DFF_0_reg rw_000_int_0_un0_n as_030_000_sync_0_un3_n IPL_030DFF_1_reg as_030_000_sync_0_un1_n SM_AMIGA_i_7_ as_030_000_sync_0_un0_n IPL_030DFF_2_reg bgack_030_int_0_un3_n \ -# bgack_030_int_0_un1_n cpu_est_2_1__n ipl_c_0__n bgack_030_int_0_un0_n cpu_est_2_2__n cpu_est_0_1__un3_n cpu_est_2_3__n ipl_c_1__n cpu_est_0_1__un1_n G_105 \ -# cpu_est_0_1__un0_n G_106 ipl_c_2__n cpu_est_0_2__un3_n G_107 cpu_est_0_2__un1_n N_60 cpu_est_0_2__un0_n N_63 DTACK_c \ -# cpu_est_0_3__un3_n N_126 cpu_est_0_3__un1_n N_150 cpu_est_0_3__un0_n N_151 ipl_030_0_0__un3_n N_219 VPA_c ipl_030_0_0__un1_n \ -# N_175 ipl_030_0_0__un0_n ipl_030_0_1__un3_n N_59 RST_c ipl_030_0_1__un1_n N_68 ipl_030_0_1__un0_n N_72 ipl_030_0_2__un3_n \ -# N_80 ipl_030_0_2__un1_n N_93 RW_c ipl_030_0_2__un0_n N_98 ds_000_enable_0_un3_n N_107 fc_c_0__n ds_000_enable_0_un1_n \ -# N_128 ds_000_enable_0_un0_n N_131 fc_c_1__n vma_int_0_un3_n N_134 vma_int_0_un1_n N_135 vma_int_0_un0_n N_141 \ -# AMIGA_BUS_DATA_DIR_c a_decode_15__n N_142 N_143 a_decode_14__n N_144 N_145 a_decode_13__n N_146 N_205_i \ -# N_147 N_140_i a_decode_12__n N_148 AMIGA_DS_i N_149 a_decode_11__n N_154 N_199_i N_155 \ -# N_198_i a_decode_10__n N_162 N_180_i N_165 N_262_i a_decode_9__n N_259 AMIGA_BUS_DATA_DIR_c_0 N_260 \ -# pos_clk_un2_i_n a_decode_8__n N_181 N_3_i N_182 N_32_0 a_decode_7__n N_183 N_4_i N_184 \ -# N_31_0 a_decode_6__n N_185 N_220_i N_186 BG_030_c_i a_decode_5__n N_266 pos_clk_un9_bg_030_0_n N_267 \ -# N_17_i a_decode_4__n N_268 N_24_0 N_190 N_16_i a_decode_3__n N_191 N_25_0 N_201 \ -# N_15_i a_decode_2__n N_202 N_26_0 N_203 N_12_i N_208 N_28_0 N_163 N_11_i \ -# N_282 N_29_0 un21_berr_1 N_5_i N_132 N_30_0 N_96 a_c_i_0__n N_129 size_c_i_1__n \ -# un1_SM_AMIGA_0_sqmuxa_1 pos_clk_un10_sm_amiga_i_n N_169 un1_dsack1_i N_170 N_69_i N_167 N_163_i N_168 N_244_0 \ -# pos_clk_rw_000_int_5_n N_164_i pos_clk_un6_bgack_000_n N_165_i N_274 un11_amiga_bus_enable_high_i N_164 un10_ciin_i N_244 N_60_0 \ -# N_5 N_274_i N_11 pos_clk_un6_bgack_000_0_n N_12 RW_c_i N_15 pos_clk_rw_000_int_5_0_n N_16 N_168_i \ -# N_17 N_167_i pos_clk_un9_bg_030_n G_91 N_170_i N_3 N_169_i N_205 AS_000_DMA_1_sqmuxa N_38_0 \ -# N_4 un1_SM_AMIGA_0_sqmuxa_1_0 N_199 N_282_0 pos_clk_un2_n clk_000_d_i_3__n N_140 N_96_0 N_262 N_129_i \ -# N_198 N_268_i N_180 N_246_i un1_amiga_bus_enable_low_i N_132_0 un21_fpu_cs_i AS_000_i N_142_i BGACK_030_INT_i \ -# N_141_i nEXP_SPACE_i N_135_0 cycle_dma_i_0__n N_134_0 RW_000_i N_131_i CLK_EXP_i LDS_000_c_i cycle_dma_i_1__n \ -# UDS_000_c_i DS_000_DMA_i N_128_i AS_000_DMA_i N_107_i a_i_1__n N_203_i AMIGA_BUS_ENABLE_DMA_LOW_i un1_DS_000_ENABLE_0_sqmuxa_0 a_decode_i_19__n \ -# N_201_i a_decode_i_18__n N_202_i a_decode_i_16__n VMA_INT_i AMIGA_BUS_ENABLE_DMA_HIGH_i N_98_i sm_amiga_i_0__n N_93_i sm_amiga_i_5__n \ -# N_82_i sm_amiga_i_6__n N_80_i sm_amiga_i_i_7__n N_72_i AS_030_i N_68_i AS_000_INT_i N_59_i DSACK1_INT_i \ -# N_190_i sm_amiga_i_1__n N_191_i FPU_SENSE_i AS_030_D1_i N_267_i cpu_est_i_0__n cpu_est_i_3__n N_266_i VPA_D_i \ -# sm_amiga_i_3__n N_186_i sm_amiga_i_4__n cpu_est_i_1__n N_185_i clk_000_d_i_0__n clk_000_d_i_1__n N_183_i AS_030_D0_i N_184_i \ -# cpu_est_i_2__n DTACK_D0_i N_182_i sm_amiga_i_2__n AS_030_000_SYNC_i N_181_i ahigh_i_30__n ahigh_i_31__n N_260_i ahigh_i_28__n \ -# pos_clk_size_dma_6_0_1__n ahigh_i_29__n N_259_i ahigh_i_26__n pos_clk_size_dma_6_0_0__n ahigh_i_27__n N_63_0 ahigh_i_24__n N_155_i ahigh_i_25__n \ -# N_162_i N_187_i un5_e_0 N_188_i N_154_i N_189_i cpu_est_2_0_3__n N_149_i N_208_i cpu_est_2_0_2__n \ -# N_147_i un2_ds_030_i N_148_i N_219_i cpu_est_2_0_1__n N_175_i N_146_i un3_as_030_i N_36_0 AS_030_c \ -# N_145_i N_35_0 AS_000_c N_143_i N_144_i RW_000_c pos_clk_un9_clk_000_pe_0_n N_20_i +#$ PINS 75 SIZE_1_ SIZE_0_ AHIGH_30_ AHIGH_31_ AHIGH_29_ AHIGH_28_ A_DECODE_23_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ IPL_030_2_ A_DECODE_22_ A_DECODE_21_ IPL_2_ A_DECODE_20_ A_DECODE_19_ FC_1_ A_DECODE_18_ AS_030 A_DECODE_17_ AS_000 A_DECODE_16_ RW_000 A_DECODE_15_ DS_030 A_DECODE_14_ UDS_000 A_DECODE_13_ LDS_000 A_DECODE_12_ nEXP_SPACE A_DECODE_11_ BERR A_DECODE_10_ BG_030 A_DECODE_9_ BG_000 A_DECODE_8_ BGACK_030 A_DECODE_7_ BGACK_000 A_DECODE_6_ CLK_030 A_DECODE_5_ CLK_000 A_DECODE_4_ CLK_OSZI A_DECODE_3_ CLK_DIV_OUT A_DECODE_2_ CLK_EXP A_0_ FPU_CS IPL_030_1_ FPU_SENSE IPL_030_0_ DSACK1 IPL_1_ DTACK IPL_0_ AVEC FC_0_ E A_1_ VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN +#$ NODES 514 N_157_i UDS_000_c cpu_est_2_0_3__n N_156_i LDS_000_c N_229_i cpu_est_2_0_2__n size_c_0__n N_126_i N_150_i \ +# size_c_1__n pos_clk_un9_clk_000_pe_0_n inst_BGACK_030_INTreg N_20_i vcc_n_n ahigh_c_24__n N_23_0 un5_e N_19_i gnd_n_n \ +# ahigh_c_25__n N_22_0 un1_amiga_bus_enable_low N_18_i un3_as_030 ahigh_c_26__n N_21_0 un1_UDS_000_INT ipl_c_i_2__n un1_LDS_000_INT \ +# ahigh_c_27__n N_43_0 un1_DS_000_ENABLE_0_sqmuxa ipl_c_i_1__n un21_fpu_cs ahigh_c_28__n N_42_0 un21_berr ipl_c_i_0__n un8_ciin \ +# ahigh_c_29__n N_41_0 un2_ds_030 N_13_i cpu_est_0_ ahigh_c_30__n N_27_0 cpu_est_1_ LDS_000_INT_i cpu_est_2_ \ +# ahigh_c_31__n un1_LDS_000_INT_0 cpu_est_3_ UDS_000_INT_i inst_AMIGA_BUS_ENABLE_DMA_HIGH un1_UDS_000_INT_0 inst_AMIGA_BUS_ENABLE_DMA_LOW N_104_0_1 inst_AS_030_D0 N_104_0_2 \ +# inst_AS_030_D1 N_100_0_1 inst_AS_030_000_SYNC N_100_0_2 inst_AS_000_DMA N_113_i_1 inst_DS_000_DMA N_113_i_2 inst_VMA_INTreg N_107_0_1 \ +# inst_VPA_D N_99_i_1 CLK_000_D_3_ pos_clk_un10_sm_amiga_i_1_n inst_DTACK_D0 N_202_1 inst_AMIGA_DS N_202_2 CLK_000_D_1_ N_228_1 \ +# CLK_000_D_0_ N_228_2 inst_CLK_OUT_PRE_50 N_228_3 inst_CLK_OUT_PRE_D N_228_4 IPL_D0_0_ N_228_5 IPL_D0_1_ N_150_1 \ +# IPL_D0_2_ N_150_2 CLK_000_D_2_ N_126_1 CLK_000_D_4_ N_126_2 pos_clk_ipl_n un8_ciin_1 SIZE_DMA_0_ un8_ciin_2 \ +# SIZE_DMA_1_ N_201_1_1 inst_A0_DMA N_201_1_2 inst_RW_000_DMA N_201_1_3 inst_UDS_000_INT N_201_1_4 inst_DS_000_ENABLE N_201_1_5 \ +# inst_LDS_000_INT a_decode_c_16__n N_201_1_6 inst_BGACK_030_INT_D N_201_1_7 SM_AMIGA_6_ a_decode_c_17__n N_201_1_8 inst_RW_000_INT N_201_1_0 \ +# SM_AMIGA_4_ a_decode_c_18__n N_201_2 SM_AMIGA_1_ pos_clk_cycle_dma_5_1_1__n SM_AMIGA_0_ a_decode_c_19__n N_176_1 CYCLE_DMA_0_ AS_000_DMA_1_sqmuxa_1 \ +# CYCLE_DMA_1_ a_decode_c_20__n N_198_1 inst_DSACK1_INT N_72_i_1 inst_AS_000_INT a_decode_c_21__n N_72_i_2 pos_clk_un9_clk_000_pe_n N_206_i_1 \ +# SM_AMIGA_5_ a_decode_c_22__n N_206_i_2 SM_AMIGA_3_ N_186_1 SM_AMIGA_2_ a_decode_c_23__n N_186_2 N_74_i_1 N_6 \ +# a_c_0__n N_121_i_1 N_117_i_1 a_c_1__n N_115_i_1 N_127_i_1 N_13 nEXP_SPACE_c N_123_i_1 N_119_i_1 \ +# N_18 BERR_c N_111_i_1 N_19 un21_berr_1 N_20 BG_030_c un21_fpu_cs_1 N_172_1 BG_000DFFreg \ +# N_161_1 N_153_1 pos_clk_ipl_1_n BGACK_000_c ds_000_dma_0_un3_n ds_000_dma_0_un1_n ds_000_dma_0_un0_n as_000_dma_0_un3_n as_000_dma_0_un1_n as_000_dma_0_un0_n \ +# CLK_OSZI_c uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n CLK_OUT_INTreg bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n FPU_SENSE_c lds_000_int_0_un3_n \ +# lds_000_int_0_un1_n IPL_030DFF_0_reg lds_000_int_0_un0_n rw_000_int_0_un3_n IPL_030DFF_1_reg rw_000_int_0_un1_n rw_000_int_0_un0_n SM_AMIGA_i_7_ IPL_030DFF_2_reg bgack_030_int_0_un3_n \ +# bgack_030_int_0_un1_n ipl_c_0__n bgack_030_int_0_un0_n cpu_est_2_2__n as_030_000_sync_0_un3_n cpu_est_2_3__n ipl_c_1__n as_030_000_sync_0_un1_n G_105 as_030_000_sync_0_un0_n \ +# G_106 ipl_c_2__n cpu_est_0_1__un3_n G_107 cpu_est_0_1__un1_n cpu_est_0_1__un0_n N_205 DTACK_c cpu_est_0_2__un3_n N_74 \ +# cpu_est_0_2__un1_n N_78 cpu_est_0_2__un0_n N_79 cpu_est_0_3__un3_n N_80 VPA_c cpu_est_0_3__un1_n N_83 cpu_est_0_3__un0_n \ +# N_84 ipl_030_0_0__un3_n N_89 RST_c ipl_030_0_0__un1_n N_95 ipl_030_0_0__un0_n N_96 ipl_030_0_1__un3_n N_97 \ +# ipl_030_0_1__un1_n N_105 RW_c ipl_030_0_1__un0_n N_126 ipl_030_0_2__un3_n N_150 fc_c_0__n ipl_030_0_2__un1_n N_153 \ +# ipl_030_0_2__un0_n N_156 fc_c_1__n ds_000_enable_0_un3_n N_157 ds_000_enable_0_un1_n N_158 ds_000_enable_0_un0_n N_159 AMIGA_BUS_DATA_DIR_c \ +# vma_int_0_un3_n N_160 vma_int_0_un1_n N_161 vma_int_0_un0_n N_172 as_030_d1_0_un3_n N_177 as_030_d1_0_un1_n N_178 \ +# N_181_i as_030_d1_0_un0_n N_179 N_37_0 a_decode_15__n N_180 N_182 N_176_i a_decode_14__n N_183 \ +# N_175_i N_184 N_72_i a_decode_13__n N_212 N_198_i N_213 AMIGA_DS_i a_decode_12__n N_214 \ +# N_186_i N_190 N_185_i a_decode_11__n N_191 AMIGA_BUS_DATA_DIR_c_0 N_194 pos_clk_un2_i_n a_decode_10__n N_195 \ +# N_3_i N_196 N_32_0 a_decode_9__n N_197 N_4_i N_202 N_31_0 a_decode_8__n N_220 \ +# N_39_1_i N_224 N_34_0 a_decode_7__n N_225 BG_030_c_i N_228 pos_clk_un9_bg_030_0_n a_decode_6__n N_229 \ +# N_17_i N_201_1 N_24_0 a_decode_5__n N_104 N_16_i N_100 N_25_0 a_decode_4__n N_171 \ +# N_15_i N_204 N_26_0 a_decode_3__n N_164 N_12_i N_162 N_28_0 a_decode_2__n N_163 \ +# N_5_i cpu_est_2_1__n N_30_0 N_152 a_c_i_0__n N_11 size_c_i_1__n N_201 pos_clk_un10_sm_amiga_i_n N_193 \ +# N_231_i N_192 pos_clk_un6_bgack_000_0_n N_107 N_40_0 N_99 un1_SM_AMIGA_0_sqmuxa_1_0 N_219 RW_c_i N_81 \ +# pos_clk_rw_000_int_5_0_n pos_clk_rw_000_int_5_n N_201_i un1_SM_AMIGA_0_sqmuxa_1 N_81_i pos_clk_un6_bgack_000_n N_219_i N_231 N_202_i N_5 \ +# N_191_i N_12 N_98_i N_15 N_99_i N_16 N_107_0 N_17 N_192_i pos_clk_un9_bg_030_n \ +# N_193_i N_3 N_72 N_11_i AS_000_DMA_1_sqmuxa N_29_0 N_4 VPA_c_i G_91 N_44_0 \ +# N_176 DTACK_c_i pos_clk_un2_n N_45_0 N_175 N_152_i N_185 N_153_i N_198 cpu_est_2_0_1__n \ +# N_186 N_163_i N_181 N_162_i un1_amiga_bus_enable_low_i un21_fpu_cs_i N_203_i AS_000_i un1_dsack1_i BGACK_030_INT_i \ +# N_164_i nEXP_SPACE_i N_228_i RW_000_i N_204_0 cycle_dma_i_0__n N_171_i CLK_EXP_i N_172_i cycle_dma_i_1__n \ +# un11_amiga_bus_enable_high_i DS_000_DMA_i N_85_0 AS_000_DMA_i clk_000_d_i_3__n ahigh_i_25__n N_100_0 ahigh_i_24__n AS_030_D1_i ahigh_i_27__n \ +# N_104_0 ahigh_i_26__n N_105_0 ahigh_i_29__n N_97_i ahigh_i_28__n LDS_000_c_i ahigh_i_31__n UDS_000_c_i ahigh_i_30__n \ +# N_96_i sm_amiga_i_2__n N_95_i sm_amiga_i_1__n N_220_i DTACK_D0_i un1_DS_000_ENABLE_0_sqmuxa_0 sm_amiga_i_i_7__n VMA_INT_i sm_amiga_i_3__n \ +# N_89_i a_decode_i_20__n N_84_i AMIGA_BUS_ENABLE_DMA_LOW_i N_83_i cpu_est_i_0__n N_82_i AS_030_i N_80_i AMIGA_BUS_ENABLE_DMA_HIGH_i \ +# N_79_i sm_amiga_i_6__n N_78_0 AS_030_D0_i N_74_i cpu_est_i_3__n N_197_i VPA_D_i sm_amiga_i_5__n N_195_i \ +# sm_amiga_i_4__n N_196_i cpu_est_i_1__n clk_000_d_i_0__n N_194_i clk_000_d_i_1__n cpu_est_i_2__n N_190_i DSACK1_INT_i AS_000_INT_i \ +# N_214_i a_decode_i_16__n a_decode_i_19__n N_184_i a_decode_i_18__n pos_clk_size_dma_6_0_1__n FPU_SENSE_i N_183_i AS_030_000_SYNC_i pos_clk_size_dma_6_0_0__n \ +# sm_amiga_i_0__n N_182_i N_187_i N_38_0 N_188_i N_179_i N_189_i N_180_i N_177_i N_178_i \ +# un2_ds_030_i N_225_i un8_ciin_i N_224_i N_205_0 un3_as_030_i N_160_i AS_030_c N_161_i un5_e_0 \ +# AS_000_c N_159_i RW_000_c N_158_i .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ DTACK.BLIF VPA.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF A_DECODE_17_.BLIF \ A_DECODE_16_.BLIF A_DECODE_15_.BLIF A_DECODE_14_.BLIF A_DECODE_13_.BLIF A_DECODE_12_.BLIF A_DECODE_11_.BLIF A_DECODE_10_.BLIF A_DECODE_9_.BLIF A_DECODE_8_.BLIF \ A_DECODE_7_.BLIF A_DECODE_6_.BLIF A_DECODE_5_.BLIF A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \ - A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_23_0.BLIF UDS_000_c.BLIF N_19_i.BLIF N_22_0.BLIF LDS_000_c.BLIF N_18_i.BLIF N_21_0.BLIF size_c_0__n.BLIF \ - ipl_c_i_2__n.BLIF N_43_0.BLIF size_c_1__n.BLIF ipl_c_i_1__n.BLIF inst_BGACK_030_INTreg.BLIF N_42_0.BLIF vcc_n_n.BLIF ahigh_c_24__n.BLIF ipl_c_i_0__n.BLIF \ - un5_e.BLIF N_41_0.BLIF gnd_n_n.BLIF ahigh_c_25__n.BLIF DTACK_c_i.BLIF un1_amiga_bus_enable_low.BLIF N_45_0.BLIF un3_as_030.BLIF ahigh_c_26__n.BLIF \ - VPA_c_i.BLIF un1_UDS_000_INT.BLIF N_44_0.BLIF un1_LDS_000_INT.BLIF ahigh_c_27__n.BLIF N_13_i.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF N_27_0.BLIF un10_ciin.BLIF \ - ahigh_c_28__n.BLIF LDS_000_INT_i.BLIF un21_fpu_cs.BLIF un1_LDS_000_INT_0.BLIF un21_berr.BLIF ahigh_c_29__n.BLIF UDS_000_INT_i.BLIF un2_ds_030.BLIF un1_UDS_000_INT_0.BLIF \ - cpu_est_0_.BLIF ahigh_c_30__n.BLIF N_96_0_1.BLIF cpu_est_1_.BLIF N_96_0_2.BLIF cpu_est_2_.BLIF ahigh_c_31__n.BLIF N_282_0_1.BLIF cpu_est_3_.BLIF \ - N_282_0_2.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_282_0_3.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_282_0_4.BLIF inst_AS_030_D0.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF inst_AS_030_D1.BLIF un10_ciin_1.BLIF \ - inst_AS_030_000_SYNC.BLIF un10_ciin_2.BLIF inst_AS_000_DMA.BLIF un10_ciin_3.BLIF inst_DS_000_DMA.BLIF un10_ciin_4.BLIF inst_VMA_INTreg.BLIF un10_ciin_5.BLIF inst_VPA_D.BLIF \ - un10_ciin_6.BLIF CLK_000_D_3_.BLIF un10_ciin_7.BLIF inst_DTACK_D0.BLIF un10_ciin_8.BLIF inst_AMIGA_DS.BLIF un10_ciin_9.BLIF CLK_000_D_1_.BLIF un10_ciin_10.BLIF \ - CLK_000_D_0_.BLIF un10_ciin_11.BLIF inst_CLK_OUT_PRE_50.BLIF N_201_1.BLIF inst_CLK_OUT_PRE_D.BLIF N_201_2.BLIF IPL_D0_0_.BLIF N_131_i_1.BLIF IPL_D0_1_.BLIF \ - N_134_0_1.BLIF IPL_D0_2_.BLIF N_113_i_1.BLIF CLK_000_D_2_.BLIF N_113_i_2.BLIF CLK_000_D_4_.BLIF N_144_1.BLIF pos_clk_ipl_n.BLIF N_144_2.BLIF \ - SIZE_DMA_0_.BLIF N_143_1.BLIF SIZE_DMA_1_.BLIF N_143_2.BLIF inst_A0_DMA.BLIF N_163_1.BLIF inst_RW_000_DMA.BLIF N_163_2.BLIF inst_UDS_000_INT.BLIF \ - N_163_3.BLIF inst_DS_000_ENABLE.BLIF un21_fpu_cs_1.BLIF inst_LDS_000_INT.BLIF a_decode_c_16__n.BLIF un21_berr_1_0.BLIF inst_BGACK_030_INT_D.BLIF pos_clk_cycle_dma_5_1_1__n.BLIF SM_AMIGA_6_.BLIF \ - a_decode_c_17__n.BLIF N_199_1.BLIF inst_RW_000_INT.BLIF AS_000_DMA_1_sqmuxa_1.BLIF SM_AMIGA_4_.BLIF a_decode_c_18__n.BLIF N_140_1.BLIF SM_AMIGA_1_.BLIF N_66_i_1.BLIF \ - SM_AMIGA_0_.BLIF a_decode_c_19__n.BLIF N_66_i_2.BLIF CYCLE_DMA_0_.BLIF N_205_i_1.BLIF CYCLE_DMA_1_.BLIF a_decode_c_20__n.BLIF N_205_i_2.BLIF inst_DSACK1_INT.BLIF \ - N_180_1.BLIF inst_AS_000_INT.BLIF a_decode_c_21__n.BLIF N_180_2.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_59_i_1.BLIF SM_AMIGA_5_.BLIF a_decode_c_22__n.BLIF N_127_i_1.BLIF \ - SM_AMIGA_3_.BLIF N_123_i_1.BLIF SM_AMIGA_2_.BLIF a_decode_c_23__n.BLIF N_121_i_1.BLIF N_119_i_1.BLIF N_6.BLIF a_c_0__n.BLIF N_117_i_1.BLIF \ - N_115_i_1.BLIF a_c_1__n.BLIF N_111_i_1.BLIF N_165_1.BLIF N_13.BLIF nEXP_SPACE_c.BLIF N_162_1.BLIF N_148_1.BLIF N_18.BLIF \ - BERR_c.BLIF pos_clk_ipl_1_n.BLIF N_19.BLIF ds_000_dma_0_un3_n.BLIF N_20.BLIF BG_030_c.BLIF ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF BG_000DFFreg.BLIF \ - as_000_dma_0_un3_n.BLIF as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF BGACK_000_c.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF \ - bg_000_0_un0_n.BLIF CLK_OSZI_c.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF CLK_OUT_INTreg.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un1_n.BLIF as_030_d1_0_un0_n.BLIF \ - FPU_SENSE_c.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un1_n.BLIF IPL_030DFF_0_reg.BLIF rw_000_int_0_un0_n.BLIF as_030_000_sync_0_un3_n.BLIF IPL_030DFF_1_reg.BLIF as_030_000_sync_0_un1_n.BLIF SM_AMIGA_i_7_.BLIF \ - as_030_000_sync_0_un0_n.BLIF IPL_030DFF_2_reg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un1_n.BLIF cpu_est_2_1__n.BLIF ipl_c_0__n.BLIF bgack_030_int_0_un0_n.BLIF cpu_est_2_2__n.BLIF cpu_est_0_1__un3_n.BLIF \ - cpu_est_2_3__n.BLIF ipl_c_1__n.BLIF cpu_est_0_1__un1_n.BLIF G_105.BLIF cpu_est_0_1__un0_n.BLIF G_106.BLIF ipl_c_2__n.BLIF cpu_est_0_2__un3_n.BLIF G_107.BLIF \ - cpu_est_0_2__un1_n.BLIF N_60.BLIF cpu_est_0_2__un0_n.BLIF N_63.BLIF DTACK_c.BLIF cpu_est_0_3__un3_n.BLIF N_126.BLIF cpu_est_0_3__un1_n.BLIF N_150.BLIF \ - cpu_est_0_3__un0_n.BLIF N_151.BLIF ipl_030_0_0__un3_n.BLIF N_219.BLIF VPA_c.BLIF ipl_030_0_0__un1_n.BLIF N_175.BLIF ipl_030_0_0__un0_n.BLIF ipl_030_0_1__un3_n.BLIF \ - N_59.BLIF RST_c.BLIF ipl_030_0_1__un1_n.BLIF N_68.BLIF ipl_030_0_1__un0_n.BLIF N_72.BLIF ipl_030_0_2__un3_n.BLIF N_80.BLIF ipl_030_0_2__un1_n.BLIF \ - N_93.BLIF RW_c.BLIF ipl_030_0_2__un0_n.BLIF N_98.BLIF ds_000_enable_0_un3_n.BLIF N_107.BLIF fc_c_0__n.BLIF ds_000_enable_0_un1_n.BLIF N_128.BLIF \ - ds_000_enable_0_un0_n.BLIF N_131.BLIF fc_c_1__n.BLIF vma_int_0_un3_n.BLIF N_134.BLIF vma_int_0_un1_n.BLIF N_135.BLIF vma_int_0_un0_n.BLIF N_141.BLIF \ - AMIGA_BUS_DATA_DIR_c.BLIF a_decode_15__n.BLIF N_142.BLIF N_143.BLIF a_decode_14__n.BLIF N_144.BLIF N_145.BLIF a_decode_13__n.BLIF N_146.BLIF \ - N_205_i.BLIF N_147.BLIF N_140_i.BLIF a_decode_12__n.BLIF N_148.BLIF AMIGA_DS_i.BLIF N_149.BLIF a_decode_11__n.BLIF N_154.BLIF \ - N_199_i.BLIF N_155.BLIF N_198_i.BLIF a_decode_10__n.BLIF N_162.BLIF N_180_i.BLIF N_165.BLIF N_262_i.BLIF a_decode_9__n.BLIF \ - N_259.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_260.BLIF pos_clk_un2_i_n.BLIF a_decode_8__n.BLIF N_181.BLIF N_3_i.BLIF N_182.BLIF N_32_0.BLIF \ - a_decode_7__n.BLIF N_183.BLIF N_4_i.BLIF N_184.BLIF N_31_0.BLIF a_decode_6__n.BLIF N_185.BLIF N_220_i.BLIF N_186.BLIF \ - BG_030_c_i.BLIF a_decode_5__n.BLIF N_266.BLIF pos_clk_un9_bg_030_0_n.BLIF N_267.BLIF N_17_i.BLIF a_decode_4__n.BLIF N_268.BLIF N_24_0.BLIF \ - N_190.BLIF N_16_i.BLIF a_decode_3__n.BLIF N_191.BLIF N_25_0.BLIF N_201.BLIF N_15_i.BLIF a_decode_2__n.BLIF N_202.BLIF \ - N_26_0.BLIF N_203.BLIF N_12_i.BLIF N_208.BLIF N_28_0.BLIF N_163.BLIF N_11_i.BLIF N_282.BLIF N_29_0.BLIF \ - un21_berr_1.BLIF N_5_i.BLIF N_132.BLIF N_30_0.BLIF N_96.BLIF a_c_i_0__n.BLIF N_129.BLIF size_c_i_1__n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ - pos_clk_un10_sm_amiga_i_n.BLIF N_169.BLIF un1_dsack1_i.BLIF N_170.BLIF N_69_i.BLIF N_167.BLIF N_163_i.BLIF N_168.BLIF N_244_0.BLIF \ - pos_clk_rw_000_int_5_n.BLIF N_164_i.BLIF pos_clk_un6_bgack_000_n.BLIF N_165_i.BLIF N_274.BLIF un11_amiga_bus_enable_high_i.BLIF N_164.BLIF un10_ciin_i.BLIF N_244.BLIF \ - N_60_0.BLIF N_5.BLIF N_274_i.BLIF N_11.BLIF pos_clk_un6_bgack_000_0_n.BLIF N_12.BLIF RW_c_i.BLIF N_15.BLIF pos_clk_rw_000_int_5_0_n.BLIF \ - N_16.BLIF N_168_i.BLIF N_17.BLIF N_167_i.BLIF pos_clk_un9_bg_030_n.BLIF G_91.BLIF N_170_i.BLIF N_3.BLIF N_169_i.BLIF \ - N_205.BLIF AS_000_DMA_1_sqmuxa.BLIF N_38_0.BLIF N_4.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF N_199.BLIF N_282_0.BLIF pos_clk_un2_n.BLIF clk_000_d_i_3__n.BLIF \ - N_140.BLIF N_96_0.BLIF N_262.BLIF N_129_i.BLIF N_198.BLIF N_268_i.BLIF N_180.BLIF N_246_i.BLIF un1_amiga_bus_enable_low_i.BLIF \ - N_132_0.BLIF un21_fpu_cs_i.BLIF AS_000_i.BLIF N_142_i.BLIF BGACK_030_INT_i.BLIF N_141_i.BLIF nEXP_SPACE_i.BLIF N_135_0.BLIF cycle_dma_i_0__n.BLIF \ - N_134_0.BLIF RW_000_i.BLIF N_131_i.BLIF CLK_EXP_i.BLIF LDS_000_c_i.BLIF cycle_dma_i_1__n.BLIF UDS_000_c_i.BLIF DS_000_DMA_i.BLIF N_128_i.BLIF \ - AS_000_DMA_i.BLIF N_107_i.BLIF a_i_1__n.BLIF N_203_i.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF a_decode_i_19__n.BLIF N_201_i.BLIF a_decode_i_18__n.BLIF \ - N_202_i.BLIF a_decode_i_16__n.BLIF VMA_INT_i.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_98_i.BLIF sm_amiga_i_0__n.BLIF N_93_i.BLIF sm_amiga_i_5__n.BLIF N_82_i.BLIF \ - sm_amiga_i_6__n.BLIF N_80_i.BLIF sm_amiga_i_i_7__n.BLIF N_72_i.BLIF AS_030_i.BLIF N_68_i.BLIF AS_000_INT_i.BLIF N_59_i.BLIF DSACK1_INT_i.BLIF \ - N_190_i.BLIF sm_amiga_i_1__n.BLIF N_191_i.BLIF FPU_SENSE_i.BLIF AS_030_D1_i.BLIF N_267_i.BLIF cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_266_i.BLIF \ - VPA_D_i.BLIF sm_amiga_i_3__n.BLIF N_186_i.BLIF sm_amiga_i_4__n.BLIF cpu_est_i_1__n.BLIF N_185_i.BLIF clk_000_d_i_0__n.BLIF clk_000_d_i_1__n.BLIF N_183_i.BLIF \ - AS_030_D0_i.BLIF N_184_i.BLIF cpu_est_i_2__n.BLIF DTACK_D0_i.BLIF N_182_i.BLIF sm_amiga_i_2__n.BLIF AS_030_000_SYNC_i.BLIF N_181_i.BLIF ahigh_i_30__n.BLIF \ - ahigh_i_31__n.BLIF N_260_i.BLIF ahigh_i_28__n.BLIF pos_clk_size_dma_6_0_1__n.BLIF ahigh_i_29__n.BLIF N_259_i.BLIF ahigh_i_26__n.BLIF pos_clk_size_dma_6_0_0__n.BLIF ahigh_i_27__n.BLIF \ - N_63_0.BLIF ahigh_i_24__n.BLIF N_155_i.BLIF ahigh_i_25__n.BLIF N_162_i.BLIF N_187_i.BLIF un5_e_0.BLIF N_188_i.BLIF N_154_i.BLIF \ - N_189_i.BLIF cpu_est_2_0_3__n.BLIF N_149_i.BLIF N_208_i.BLIF cpu_est_2_0_2__n.BLIF N_147_i.BLIF un2_ds_030_i.BLIF N_148_i.BLIF N_219_i.BLIF \ - cpu_est_2_0_1__n.BLIF N_175_i.BLIF N_146_i.BLIF un3_as_030_i.BLIF N_36_0.BLIF AS_030_c.BLIF N_145_i.BLIF N_35_0.BLIF AS_000_c.BLIF \ - N_143_i.BLIF N_144_i.BLIF RW_000_c.BLIF pos_clk_un9_clk_000_pe_0_n.BLIF N_20_i.BLIF AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN \ - LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN \ - AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN + A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_157_i.BLIF UDS_000_c.BLIF cpu_est_2_0_3__n.BLIF N_156_i.BLIF LDS_000_c.BLIF N_229_i.BLIF cpu_est_2_0_2__n.BLIF size_c_0__n.BLIF \ + N_126_i.BLIF N_150_i.BLIF size_c_1__n.BLIF pos_clk_un9_clk_000_pe_0_n.BLIF inst_BGACK_030_INTreg.BLIF N_20_i.BLIF vcc_n_n.BLIF ahigh_c_24__n.BLIF N_23_0.BLIF \ + un5_e.BLIF N_19_i.BLIF gnd_n_n.BLIF ahigh_c_25__n.BLIF N_22_0.BLIF un1_amiga_bus_enable_low.BLIF N_18_i.BLIF un3_as_030.BLIF ahigh_c_26__n.BLIF \ + N_21_0.BLIF un1_UDS_000_INT.BLIF ipl_c_i_2__n.BLIF un1_LDS_000_INT.BLIF ahigh_c_27__n.BLIF N_43_0.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF ipl_c_i_1__n.BLIF un21_fpu_cs.BLIF \ + ahigh_c_28__n.BLIF N_42_0.BLIF un21_berr.BLIF ipl_c_i_0__n.BLIF un8_ciin.BLIF ahigh_c_29__n.BLIF N_41_0.BLIF un2_ds_030.BLIF N_13_i.BLIF \ + cpu_est_0_.BLIF ahigh_c_30__n.BLIF N_27_0.BLIF cpu_est_1_.BLIF LDS_000_INT_i.BLIF cpu_est_2_.BLIF ahigh_c_31__n.BLIF un1_LDS_000_INT_0.BLIF cpu_est_3_.BLIF \ + UDS_000_INT_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF un1_UDS_000_INT_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_104_0_1.BLIF inst_AS_030_D0.BLIF N_104_0_2.BLIF inst_AS_030_D1.BLIF N_100_0_1.BLIF \ + inst_AS_030_000_SYNC.BLIF N_100_0_2.BLIF inst_AS_000_DMA.BLIF N_113_i_1.BLIF inst_DS_000_DMA.BLIF N_113_i_2.BLIF inst_VMA_INTreg.BLIF N_107_0_1.BLIF inst_VPA_D.BLIF \ + N_99_i_1.BLIF CLK_000_D_3_.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF inst_DTACK_D0.BLIF N_202_1.BLIF inst_AMIGA_DS.BLIF N_202_2.BLIF CLK_000_D_1_.BLIF N_228_1.BLIF \ + CLK_000_D_0_.BLIF N_228_2.BLIF inst_CLK_OUT_PRE_50.BLIF N_228_3.BLIF inst_CLK_OUT_PRE_D.BLIF N_228_4.BLIF IPL_D0_0_.BLIF N_228_5.BLIF IPL_D0_1_.BLIF \ + N_150_1.BLIF IPL_D0_2_.BLIF N_150_2.BLIF CLK_000_D_2_.BLIF N_126_1.BLIF CLK_000_D_4_.BLIF N_126_2.BLIF pos_clk_ipl_n.BLIF un8_ciin_1.BLIF \ + SIZE_DMA_0_.BLIF un8_ciin_2.BLIF SIZE_DMA_1_.BLIF N_201_1_1.BLIF inst_A0_DMA.BLIF N_201_1_2.BLIF inst_RW_000_DMA.BLIF N_201_1_3.BLIF inst_UDS_000_INT.BLIF \ + N_201_1_4.BLIF inst_DS_000_ENABLE.BLIF N_201_1_5.BLIF inst_LDS_000_INT.BLIF a_decode_c_16__n.BLIF N_201_1_6.BLIF inst_BGACK_030_INT_D.BLIF N_201_1_7.BLIF SM_AMIGA_6_.BLIF \ + a_decode_c_17__n.BLIF N_201_1_8.BLIF inst_RW_000_INT.BLIF N_201_1_0.BLIF SM_AMIGA_4_.BLIF a_decode_c_18__n.BLIF N_201_2.BLIF SM_AMIGA_1_.BLIF pos_clk_cycle_dma_5_1_1__n.BLIF \ + SM_AMIGA_0_.BLIF a_decode_c_19__n.BLIF N_176_1.BLIF CYCLE_DMA_0_.BLIF AS_000_DMA_1_sqmuxa_1.BLIF CYCLE_DMA_1_.BLIF a_decode_c_20__n.BLIF N_198_1.BLIF inst_DSACK1_INT.BLIF \ + N_72_i_1.BLIF inst_AS_000_INT.BLIF a_decode_c_21__n.BLIF N_72_i_2.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_206_i_1.BLIF SM_AMIGA_5_.BLIF a_decode_c_22__n.BLIF N_206_i_2.BLIF \ + SM_AMIGA_3_.BLIF N_186_1.BLIF SM_AMIGA_2_.BLIF a_decode_c_23__n.BLIF N_186_2.BLIF N_74_i_1.BLIF N_6.BLIF a_c_0__n.BLIF N_121_i_1.BLIF \ + N_117_i_1.BLIF a_c_1__n.BLIF N_115_i_1.BLIF N_127_i_1.BLIF N_13.BLIF nEXP_SPACE_c.BLIF N_123_i_1.BLIF N_119_i_1.BLIF N_18.BLIF \ + BERR_c.BLIF N_111_i_1.BLIF N_19.BLIF un21_berr_1.BLIF N_20.BLIF BG_030_c.BLIF un21_fpu_cs_1.BLIF N_172_1.BLIF BG_000DFFreg.BLIF \ + N_161_1.BLIF N_153_1.BLIF pos_clk_ipl_1_n.BLIF BGACK_000_c.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un1_n.BLIF \ + as_000_dma_0_un0_n.BLIF CLK_OSZI_c.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF CLK_OUT_INTreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF \ + FPU_SENSE_c.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF IPL_030DFF_0_reg.BLIF lds_000_int_0_un0_n.BLIF rw_000_int_0_un3_n.BLIF IPL_030DFF_1_reg.BLIF rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF \ + SM_AMIGA_i_7_.BLIF IPL_030DFF_2_reg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un1_n.BLIF ipl_c_0__n.BLIF bgack_030_int_0_un0_n.BLIF cpu_est_2_2__n.BLIF as_030_000_sync_0_un3_n.BLIF cpu_est_2_3__n.BLIF \ + ipl_c_1__n.BLIF as_030_000_sync_0_un1_n.BLIF G_105.BLIF as_030_000_sync_0_un0_n.BLIF G_106.BLIF ipl_c_2__n.BLIF cpu_est_0_1__un3_n.BLIF G_107.BLIF cpu_est_0_1__un1_n.BLIF \ + cpu_est_0_1__un0_n.BLIF N_205.BLIF DTACK_c.BLIF cpu_est_0_2__un3_n.BLIF N_74.BLIF cpu_est_0_2__un1_n.BLIF N_78.BLIF cpu_est_0_2__un0_n.BLIF N_79.BLIF \ + cpu_est_0_3__un3_n.BLIF N_80.BLIF VPA_c.BLIF cpu_est_0_3__un1_n.BLIF N_83.BLIF cpu_est_0_3__un0_n.BLIF N_84.BLIF ipl_030_0_0__un3_n.BLIF N_89.BLIF \ + RST_c.BLIF ipl_030_0_0__un1_n.BLIF N_95.BLIF ipl_030_0_0__un0_n.BLIF N_96.BLIF ipl_030_0_1__un3_n.BLIF N_97.BLIF ipl_030_0_1__un1_n.BLIF N_105.BLIF \ + RW_c.BLIF ipl_030_0_1__un0_n.BLIF N_126.BLIF ipl_030_0_2__un3_n.BLIF N_150.BLIF fc_c_0__n.BLIF ipl_030_0_2__un1_n.BLIF N_153.BLIF ipl_030_0_2__un0_n.BLIF \ + N_156.BLIF fc_c_1__n.BLIF ds_000_enable_0_un3_n.BLIF N_157.BLIF ds_000_enable_0_un1_n.BLIF N_158.BLIF ds_000_enable_0_un0_n.BLIF N_159.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ + vma_int_0_un3_n.BLIF N_160.BLIF vma_int_0_un1_n.BLIF N_161.BLIF vma_int_0_un0_n.BLIF N_172.BLIF as_030_d1_0_un3_n.BLIF N_177.BLIF as_030_d1_0_un1_n.BLIF \ + N_178.BLIF N_181_i.BLIF as_030_d1_0_un0_n.BLIF N_179.BLIF N_37_0.BLIF a_decode_15__n.BLIF N_180.BLIF N_182.BLIF N_176_i.BLIF \ + a_decode_14__n.BLIF N_183.BLIF N_175_i.BLIF N_184.BLIF N_72_i.BLIF a_decode_13__n.BLIF N_212.BLIF N_198_i.BLIF N_213.BLIF \ + AMIGA_DS_i.BLIF a_decode_12__n.BLIF N_214.BLIF N_186_i.BLIF N_190.BLIF N_185_i.BLIF a_decode_11__n.BLIF N_191.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF \ + N_194.BLIF pos_clk_un2_i_n.BLIF a_decode_10__n.BLIF N_195.BLIF N_3_i.BLIF N_196.BLIF N_32_0.BLIF a_decode_9__n.BLIF N_197.BLIF \ + N_4_i.BLIF N_202.BLIF N_31_0.BLIF a_decode_8__n.BLIF N_220.BLIF N_39_1_i.BLIF N_224.BLIF N_34_0.BLIF a_decode_7__n.BLIF \ + N_225.BLIF BG_030_c_i.BLIF N_228.BLIF pos_clk_un9_bg_030_0_n.BLIF a_decode_6__n.BLIF N_229.BLIF N_17_i.BLIF N_201_1.BLIF N_24_0.BLIF \ + a_decode_5__n.BLIF N_104.BLIF N_16_i.BLIF N_100.BLIF N_25_0.BLIF a_decode_4__n.BLIF N_171.BLIF N_15_i.BLIF N_204.BLIF \ + N_26_0.BLIF a_decode_3__n.BLIF N_164.BLIF N_12_i.BLIF N_162.BLIF N_28_0.BLIF a_decode_2__n.BLIF N_163.BLIF N_5_i.BLIF \ + cpu_est_2_1__n.BLIF N_30_0.BLIF N_152.BLIF a_c_i_0__n.BLIF N_11.BLIF size_c_i_1__n.BLIF N_201.BLIF pos_clk_un10_sm_amiga_i_n.BLIF N_193.BLIF \ + N_231_i.BLIF N_192.BLIF pos_clk_un6_bgack_000_0_n.BLIF N_107.BLIF N_40_0.BLIF N_99.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF N_219.BLIF RW_c_i.BLIF \ + N_81.BLIF pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n.BLIF N_201_i.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF N_81_i.BLIF pos_clk_un6_bgack_000_n.BLIF N_219_i.BLIF N_231.BLIF \ + N_202_i.BLIF N_5.BLIF N_191_i.BLIF N_12.BLIF N_98_i.BLIF N_15.BLIF N_99_i.BLIF N_16.BLIF N_107_0.BLIF \ + N_17.BLIF N_192_i.BLIF pos_clk_un9_bg_030_n.BLIF N_193_i.BLIF N_3.BLIF N_72.BLIF N_11_i.BLIF AS_000_DMA_1_sqmuxa.BLIF N_29_0.BLIF \ + N_4.BLIF VPA_c_i.BLIF G_91.BLIF N_44_0.BLIF N_176.BLIF DTACK_c_i.BLIF pos_clk_un2_n.BLIF N_45_0.BLIF N_175.BLIF \ + N_152_i.BLIF N_185.BLIF N_153_i.BLIF N_198.BLIF cpu_est_2_0_1__n.BLIF N_186.BLIF N_163_i.BLIF N_181.BLIF N_162_i.BLIF \ + un1_amiga_bus_enable_low_i.BLIF un21_fpu_cs_i.BLIF N_203_i.BLIF AS_000_i.BLIF un1_dsack1_i.BLIF BGACK_030_INT_i.BLIF N_164_i.BLIF nEXP_SPACE_i.BLIF N_228_i.BLIF \ + RW_000_i.BLIF N_204_0.BLIF cycle_dma_i_0__n.BLIF N_171_i.BLIF CLK_EXP_i.BLIF N_172_i.BLIF cycle_dma_i_1__n.BLIF un11_amiga_bus_enable_high_i.BLIF DS_000_DMA_i.BLIF \ + N_85_0.BLIF AS_000_DMA_i.BLIF clk_000_d_i_3__n.BLIF ahigh_i_25__n.BLIF N_100_0.BLIF ahigh_i_24__n.BLIF AS_030_D1_i.BLIF ahigh_i_27__n.BLIF N_104_0.BLIF \ + ahigh_i_26__n.BLIF N_105_0.BLIF ahigh_i_29__n.BLIF N_97_i.BLIF ahigh_i_28__n.BLIF LDS_000_c_i.BLIF ahigh_i_31__n.BLIF UDS_000_c_i.BLIF ahigh_i_30__n.BLIF \ + N_96_i.BLIF sm_amiga_i_2__n.BLIF N_95_i.BLIF sm_amiga_i_1__n.BLIF N_220_i.BLIF DTACK_D0_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF sm_amiga_i_i_7__n.BLIF VMA_INT_i.BLIF \ + sm_amiga_i_3__n.BLIF N_89_i.BLIF a_decode_i_20__n.BLIF N_84_i.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_83_i.BLIF cpu_est_i_0__n.BLIF N_82_i.BLIF AS_030_i.BLIF \ + N_80_i.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_79_i.BLIF sm_amiga_i_6__n.BLIF N_78_0.BLIF AS_030_D0_i.BLIF N_74_i.BLIF cpu_est_i_3__n.BLIF N_197_i.BLIF \ + VPA_D_i.BLIF sm_amiga_i_5__n.BLIF N_195_i.BLIF sm_amiga_i_4__n.BLIF N_196_i.BLIF cpu_est_i_1__n.BLIF clk_000_d_i_0__n.BLIF N_194_i.BLIF clk_000_d_i_1__n.BLIF \ + cpu_est_i_2__n.BLIF N_190_i.BLIF DSACK1_INT_i.BLIF AS_000_INT_i.BLIF N_214_i.BLIF a_decode_i_16__n.BLIF a_decode_i_19__n.BLIF N_184_i.BLIF a_decode_i_18__n.BLIF \ + pos_clk_size_dma_6_0_1__n.BLIF FPU_SENSE_i.BLIF N_183_i.BLIF AS_030_000_SYNC_i.BLIF pos_clk_size_dma_6_0_0__n.BLIF sm_amiga_i_0__n.BLIF N_182_i.BLIF N_187_i.BLIF N_38_0.BLIF \ + N_188_i.BLIF N_179_i.BLIF N_189_i.BLIF N_180_i.BLIF N_177_i.BLIF N_178_i.BLIF un2_ds_030_i.BLIF N_225_i.BLIF un8_ciin_i.BLIF \ + N_224_i.BLIF N_205_0.BLIF un3_as_030_i.BLIF N_160_i.BLIF AS_030_c.BLIF N_161_i.BLIF un5_e_0.BLIF AS_000_c.BLIF N_159_i.BLIF \ + RW_000_c.BLIF N_158_i.BLIF AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN \ + AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN \ + BERR.PIN RW.PIN .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E VMA \ - AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C \ - SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ - IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ - SM_AMIGA_5_.D SM_AMIGA_5_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C SIZE_DMA_0_.D \ - SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ - cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ - inst_DTACK_D0.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C \ - inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D \ - inst_AS_000_INT.C inst_AMIGA_DS.D inst_AMIGA_DS.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ - inst_AS_030_D1.D inst_AS_030_D1.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D \ - inst_CLK_OUT_PRE_D.C G_105.X1 G_105.X2 G_106.X1 G_106.X2 G_107.X1 G_107.X2 G_91.X1 G_91.X2 SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_23_0 UDS_000_c \ - N_19_i N_22_0 LDS_000_c N_18_i N_21_0 size_c_0__n ipl_c_i_2__n N_43_0 size_c_1__n ipl_c_i_1__n N_42_0 \ - vcc_n_n ahigh_c_24__n ipl_c_i_0__n un5_e N_41_0 gnd_n_n ahigh_c_25__n DTACK_c_i un1_amiga_bus_enable_low N_45_0 un3_as_030 \ - ahigh_c_26__n VPA_c_i un1_UDS_000_INT N_44_0 un1_LDS_000_INT ahigh_c_27__n N_13_i un1_DS_000_ENABLE_0_sqmuxa N_27_0 un10_ciin ahigh_c_28__n \ - LDS_000_INT_i un21_fpu_cs un1_LDS_000_INT_0 un21_berr ahigh_c_29__n UDS_000_INT_i un2_ds_030 un1_UDS_000_INT_0 ahigh_c_30__n N_96_0_1 N_96_0_2 \ - ahigh_c_31__n N_282_0_1 N_282_0_2 N_282_0_3 N_282_0_4 pos_clk_un10_sm_amiga_i_1_n un10_ciin_1 un10_ciin_2 un10_ciin_3 un10_ciin_4 un10_ciin_5 \ - un10_ciin_6 un10_ciin_7 un10_ciin_8 un10_ciin_9 un10_ciin_10 un10_ciin_11 N_201_1 N_201_2 N_131_i_1 N_134_0_1 N_113_i_1 \ - N_113_i_2 N_144_1 pos_clk_ipl_n N_144_2 N_143_1 N_143_2 N_163_1 N_163_2 N_163_3 un21_fpu_cs_1 a_decode_c_16__n \ - un21_berr_1_0 pos_clk_cycle_dma_5_1_1__n a_decode_c_17__n N_199_1 AS_000_DMA_1_sqmuxa_1 a_decode_c_18__n N_140_1 N_66_i_1 a_decode_c_19__n N_66_i_2 N_205_i_1 \ - a_decode_c_20__n N_205_i_2 N_180_1 a_decode_c_21__n N_180_2 pos_clk_un9_clk_000_pe_n N_59_i_1 a_decode_c_22__n N_127_i_1 N_123_i_1 a_decode_c_23__n \ - N_121_i_1 N_119_i_1 N_6 a_c_0__n N_117_i_1 N_115_i_1 a_c_1__n N_111_i_1 N_165_1 N_13 nEXP_SPACE_c \ - N_162_1 N_148_1 N_18 BERR_c pos_clk_ipl_1_n N_19 ds_000_dma_0_un3_n N_20 BG_030_c ds_000_dma_0_un1_n ds_000_dma_0_un0_n \ - as_000_dma_0_un3_n as_000_dma_0_un1_n as_000_dma_0_un0_n BGACK_000_c uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n CLK_OSZI_c \ - lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n as_030_d1_0_un3_n as_030_d1_0_un1_n as_030_d1_0_un0_n FPU_SENSE_c rw_000_int_0_un3_n rw_000_int_0_un1_n rw_000_int_0_un0_n as_030_000_sync_0_un3_n \ - as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n bgack_030_int_0_un3_n bgack_030_int_0_un1_n cpu_est_2_1__n ipl_c_0__n bgack_030_int_0_un0_n cpu_est_2_2__n cpu_est_0_1__un3_n cpu_est_2_3__n ipl_c_1__n \ - cpu_est_0_1__un1_n cpu_est_0_1__un0_n ipl_c_2__n cpu_est_0_2__un3_n cpu_est_0_2__un1_n N_60 cpu_est_0_2__un0_n N_63 DTACK_c cpu_est_0_3__un3_n N_126 \ - cpu_est_0_3__un1_n N_150 cpu_est_0_3__un0_n N_151 ipl_030_0_0__un3_n N_219 VPA_c ipl_030_0_0__un1_n N_175 ipl_030_0_0__un0_n ipl_030_0_1__un3_n \ - N_59 RST_c ipl_030_0_1__un1_n N_68 ipl_030_0_1__un0_n N_72 ipl_030_0_2__un3_n N_80 ipl_030_0_2__un1_n N_93 RW_c \ - ipl_030_0_2__un0_n N_98 ds_000_enable_0_un3_n N_107 fc_c_0__n ds_000_enable_0_un1_n N_128 ds_000_enable_0_un0_n N_131 fc_c_1__n vma_int_0_un3_n \ - N_134 vma_int_0_un1_n N_135 vma_int_0_un0_n N_141 AMIGA_BUS_DATA_DIR_c a_decode_15__n N_142 N_143 a_decode_14__n N_144 \ - N_145 a_decode_13__n N_146 N_205_i N_147 N_140_i a_decode_12__n N_148 AMIGA_DS_i N_149 a_decode_11__n \ - N_154 N_199_i N_155 N_198_i a_decode_10__n N_162 N_180_i N_165 N_262_i a_decode_9__n N_259 \ - AMIGA_BUS_DATA_DIR_c_0 N_260 pos_clk_un2_i_n a_decode_8__n N_181 N_3_i N_182 N_32_0 a_decode_7__n N_183 N_4_i \ - N_184 N_31_0 a_decode_6__n N_185 N_220_i N_186 BG_030_c_i a_decode_5__n N_266 pos_clk_un9_bg_030_0_n N_267 \ - N_17_i a_decode_4__n N_268 N_24_0 N_190 N_16_i a_decode_3__n N_191 N_25_0 N_201 N_15_i \ - a_decode_2__n N_202 N_26_0 N_203 N_12_i N_208 N_28_0 N_163 N_11_i N_282 N_29_0 \ - un21_berr_1 N_5_i N_132 N_30_0 N_96 a_c_i_0__n N_129 size_c_i_1__n un1_SM_AMIGA_0_sqmuxa_1 pos_clk_un10_sm_amiga_i_n N_169 \ - un1_dsack1_i N_170 N_69_i N_167 N_163_i N_168 N_244_0 pos_clk_rw_000_int_5_n N_164_i pos_clk_un6_bgack_000_n N_165_i \ - N_274 un11_amiga_bus_enable_high_i N_164 un10_ciin_i N_244 N_60_0 N_5 N_274_i N_11 pos_clk_un6_bgack_000_0_n N_12 \ - RW_c_i N_15 pos_clk_rw_000_int_5_0_n N_16 N_168_i N_17 N_167_i pos_clk_un9_bg_030_n N_170_i N_3 N_169_i \ - N_205 AS_000_DMA_1_sqmuxa N_38_0 N_4 un1_SM_AMIGA_0_sqmuxa_1_0 N_199 N_282_0 pos_clk_un2_n clk_000_d_i_3__n N_140 N_96_0 \ - N_262 N_129_i N_198 N_268_i N_180 N_246_i un1_amiga_bus_enable_low_i N_132_0 un21_fpu_cs_i AS_000_i N_142_i \ - BGACK_030_INT_i N_141_i nEXP_SPACE_i N_135_0 cycle_dma_i_0__n N_134_0 RW_000_i N_131_i CLK_EXP_i LDS_000_c_i cycle_dma_i_1__n \ - UDS_000_c_i DS_000_DMA_i N_128_i AS_000_DMA_i N_107_i a_i_1__n N_203_i AMIGA_BUS_ENABLE_DMA_LOW_i un1_DS_000_ENABLE_0_sqmuxa_0 a_decode_i_19__n N_201_i \ - a_decode_i_18__n N_202_i a_decode_i_16__n VMA_INT_i AMIGA_BUS_ENABLE_DMA_HIGH_i N_98_i sm_amiga_i_0__n N_93_i sm_amiga_i_5__n N_82_i sm_amiga_i_6__n \ - N_80_i sm_amiga_i_i_7__n N_72_i AS_030_i N_68_i AS_000_INT_i N_59_i DSACK1_INT_i N_190_i sm_amiga_i_1__n N_191_i \ - FPU_SENSE_i AS_030_D1_i N_267_i cpu_est_i_0__n cpu_est_i_3__n N_266_i VPA_D_i sm_amiga_i_3__n N_186_i sm_amiga_i_4__n cpu_est_i_1__n \ - N_185_i clk_000_d_i_0__n clk_000_d_i_1__n N_183_i AS_030_D0_i N_184_i cpu_est_i_2__n DTACK_D0_i N_182_i sm_amiga_i_2__n AS_030_000_SYNC_i \ - N_181_i ahigh_i_30__n ahigh_i_31__n N_260_i ahigh_i_28__n pos_clk_size_dma_6_0_1__n ahigh_i_29__n N_259_i ahigh_i_26__n pos_clk_size_dma_6_0_0__n ahigh_i_27__n \ - N_63_0 ahigh_i_24__n N_155_i ahigh_i_25__n N_162_i N_187_i un5_e_0 N_188_i N_154_i N_189_i cpu_est_2_0_3__n \ - N_149_i N_208_i cpu_est_2_0_2__n N_147_i un2_ds_030_i N_148_i N_219_i cpu_est_2_0_1__n N_175_i N_146_i un3_as_030_i \ - N_36_0 AS_030_c N_145_i N_35_0 AS_000_c N_143_i N_144_i RW_000_c pos_clk_un9_clk_000_pe_0_n N_20_i \ - AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE \ - AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE \ - DS_030.OE DSACK1.OE VMA.OE CIIN.OE + AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C \ + SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D \ + SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \ + IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D \ + CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \ + CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_DSACK1_INT.D \ + inst_DSACK1_INT.C inst_AS_000_INT.D inst_AS_000_INT.C inst_AMIGA_DS.D inst_AMIGA_DS.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \ + inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_AS_030_D1.D inst_AS_030_D1.C inst_UDS_000_INT.D inst_UDS_000_INT.C BG_000DFFreg.D \ + BG_000DFFreg.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_VMA_INTreg.D inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ + inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_D.D \ + inst_CLK_OUT_PRE_D.C G_105.X1 G_105.X2 G_106.X1 G_106.X2 G_107.X1 G_107.X2 G_91.X1 G_91.X2 SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_157_i UDS_000_c \ + cpu_est_2_0_3__n N_156_i LDS_000_c N_229_i cpu_est_2_0_2__n size_c_0__n N_126_i N_150_i size_c_1__n pos_clk_un9_clk_000_pe_0_n N_20_i \ + vcc_n_n ahigh_c_24__n N_23_0 un5_e N_19_i gnd_n_n ahigh_c_25__n N_22_0 un1_amiga_bus_enable_low N_18_i un3_as_030 \ + ahigh_c_26__n N_21_0 un1_UDS_000_INT ipl_c_i_2__n un1_LDS_000_INT ahigh_c_27__n N_43_0 un1_DS_000_ENABLE_0_sqmuxa ipl_c_i_1__n un21_fpu_cs ahigh_c_28__n \ + N_42_0 un21_berr ipl_c_i_0__n un8_ciin ahigh_c_29__n N_41_0 un2_ds_030 N_13_i ahigh_c_30__n N_27_0 LDS_000_INT_i \ + ahigh_c_31__n un1_LDS_000_INT_0 UDS_000_INT_i un1_UDS_000_INT_0 N_104_0_1 N_104_0_2 N_100_0_1 N_100_0_2 N_113_i_1 N_113_i_2 N_107_0_1 \ + N_99_i_1 pos_clk_un10_sm_amiga_i_1_n N_202_1 N_202_2 N_228_1 N_228_2 N_228_3 N_228_4 N_228_5 N_150_1 N_150_2 \ + N_126_1 N_126_2 pos_clk_ipl_n un8_ciin_1 un8_ciin_2 N_201_1_1 N_201_1_2 N_201_1_3 N_201_1_4 N_201_1_5 a_decode_c_16__n \ + N_201_1_6 N_201_1_7 a_decode_c_17__n N_201_1_8 N_201_1_0 a_decode_c_18__n N_201_2 pos_clk_cycle_dma_5_1_1__n a_decode_c_19__n N_176_1 AS_000_DMA_1_sqmuxa_1 \ + a_decode_c_20__n N_198_1 N_72_i_1 a_decode_c_21__n N_72_i_2 pos_clk_un9_clk_000_pe_n N_206_i_1 a_decode_c_22__n N_206_i_2 N_186_1 a_decode_c_23__n \ + N_186_2 N_74_i_1 N_6 a_c_0__n N_121_i_1 N_117_i_1 a_c_1__n N_115_i_1 N_127_i_1 N_13 nEXP_SPACE_c \ + N_123_i_1 N_119_i_1 N_18 BERR_c N_111_i_1 N_19 un21_berr_1 N_20 BG_030_c un21_fpu_cs_1 N_172_1 \ + N_161_1 N_153_1 pos_clk_ipl_1_n BGACK_000_c ds_000_dma_0_un3_n ds_000_dma_0_un1_n ds_000_dma_0_un0_n as_000_dma_0_un3_n as_000_dma_0_un1_n as_000_dma_0_un0_n CLK_OSZI_c \ + uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n FPU_SENSE_c lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n rw_000_int_0_un3_n \ + rw_000_int_0_un1_n rw_000_int_0_un0_n bgack_030_int_0_un3_n bgack_030_int_0_un1_n ipl_c_0__n bgack_030_int_0_un0_n cpu_est_2_2__n as_030_000_sync_0_un3_n cpu_est_2_3__n ipl_c_1__n as_030_000_sync_0_un1_n \ + as_030_000_sync_0_un0_n ipl_c_2__n cpu_est_0_1__un3_n cpu_est_0_1__un1_n cpu_est_0_1__un0_n N_205 DTACK_c cpu_est_0_2__un3_n N_74 cpu_est_0_2__un1_n N_78 \ + cpu_est_0_2__un0_n N_79 cpu_est_0_3__un3_n N_80 VPA_c cpu_est_0_3__un1_n N_83 cpu_est_0_3__un0_n N_84 ipl_030_0_0__un3_n N_89 \ + RST_c ipl_030_0_0__un1_n N_95 ipl_030_0_0__un0_n N_96 ipl_030_0_1__un3_n N_97 ipl_030_0_1__un1_n N_105 RW_c ipl_030_0_1__un0_n \ + N_126 ipl_030_0_2__un3_n N_150 fc_c_0__n ipl_030_0_2__un1_n N_153 ipl_030_0_2__un0_n N_156 fc_c_1__n ds_000_enable_0_un3_n N_157 \ + ds_000_enable_0_un1_n N_158 ds_000_enable_0_un0_n N_159 AMIGA_BUS_DATA_DIR_c vma_int_0_un3_n N_160 vma_int_0_un1_n N_161 vma_int_0_un0_n N_172 \ + as_030_d1_0_un3_n N_177 as_030_d1_0_un1_n N_178 N_181_i as_030_d1_0_un0_n N_179 N_37_0 a_decode_15__n N_180 N_182 \ + N_176_i a_decode_14__n N_183 N_175_i N_184 N_72_i a_decode_13__n N_212 N_198_i N_213 AMIGA_DS_i \ + a_decode_12__n N_214 N_186_i N_190 N_185_i a_decode_11__n N_191 AMIGA_BUS_DATA_DIR_c_0 N_194 pos_clk_un2_i_n a_decode_10__n \ + N_195 N_3_i N_196 N_32_0 a_decode_9__n N_197 N_4_i N_202 N_31_0 a_decode_8__n N_220 \ + N_39_1_i N_224 N_34_0 a_decode_7__n N_225 BG_030_c_i N_228 pos_clk_un9_bg_030_0_n a_decode_6__n N_229 N_17_i \ + N_201_1 N_24_0 a_decode_5__n N_104 N_16_i N_100 N_25_0 a_decode_4__n N_171 N_15_i N_204 \ + N_26_0 a_decode_3__n N_164 N_12_i N_162 N_28_0 a_decode_2__n N_163 N_5_i cpu_est_2_1__n N_30_0 \ + N_152 a_c_i_0__n N_11 size_c_i_1__n N_201 pos_clk_un10_sm_amiga_i_n N_193 N_231_i N_192 pos_clk_un6_bgack_000_0_n N_107 \ + N_40_0 N_99 un1_SM_AMIGA_0_sqmuxa_1_0 N_219 RW_c_i N_81 pos_clk_rw_000_int_5_0_n pos_clk_rw_000_int_5_n N_201_i un1_SM_AMIGA_0_sqmuxa_1 N_81_i \ + pos_clk_un6_bgack_000_n N_219_i N_231 N_202_i N_5 N_191_i N_12 N_98_i N_15 N_99_i N_16 \ + N_107_0 N_17 N_192_i pos_clk_un9_bg_030_n N_193_i N_3 N_72 N_11_i AS_000_DMA_1_sqmuxa N_29_0 N_4 \ + VPA_c_i N_44_0 N_176 DTACK_c_i pos_clk_un2_n N_45_0 N_175 N_152_i N_185 N_153_i N_198 \ + cpu_est_2_0_1__n N_186 N_163_i N_181 N_162_i un1_amiga_bus_enable_low_i un21_fpu_cs_i N_203_i AS_000_i un1_dsack1_i BGACK_030_INT_i \ + N_164_i nEXP_SPACE_i N_228_i RW_000_i N_204_0 cycle_dma_i_0__n N_171_i CLK_EXP_i N_172_i cycle_dma_i_1__n un11_amiga_bus_enable_high_i \ + DS_000_DMA_i N_85_0 AS_000_DMA_i clk_000_d_i_3__n ahigh_i_25__n N_100_0 ahigh_i_24__n AS_030_D1_i ahigh_i_27__n N_104_0 ahigh_i_26__n \ + N_105_0 ahigh_i_29__n N_97_i ahigh_i_28__n LDS_000_c_i ahigh_i_31__n UDS_000_c_i ahigh_i_30__n N_96_i sm_amiga_i_2__n N_95_i \ + sm_amiga_i_1__n N_220_i DTACK_D0_i un1_DS_000_ENABLE_0_sqmuxa_0 sm_amiga_i_i_7__n VMA_INT_i sm_amiga_i_3__n N_89_i a_decode_i_20__n N_84_i AMIGA_BUS_ENABLE_DMA_LOW_i \ + N_83_i cpu_est_i_0__n N_82_i AS_030_i N_80_i AMIGA_BUS_ENABLE_DMA_HIGH_i N_79_i sm_amiga_i_6__n N_78_0 AS_030_D0_i N_74_i \ + cpu_est_i_3__n N_197_i VPA_D_i sm_amiga_i_5__n N_195_i sm_amiga_i_4__n N_196_i cpu_est_i_1__n clk_000_d_i_0__n N_194_i clk_000_d_i_1__n \ + cpu_est_i_2__n N_190_i DSACK1_INT_i AS_000_INT_i N_214_i a_decode_i_16__n a_decode_i_19__n N_184_i a_decode_i_18__n pos_clk_size_dma_6_0_1__n FPU_SENSE_i \ + N_183_i AS_030_000_SYNC_i pos_clk_size_dma_6_0_0__n sm_amiga_i_0__n N_182_i N_187_i N_38_0 N_188_i N_179_i N_189_i N_180_i \ + N_177_i N_178_i un2_ds_030_i N_225_i un8_ciin_i N_224_i N_205_0 un3_as_030_i N_160_i AS_030_c N_161_i \ + un5_e_0 AS_000_c N_159_i RW_000_c N_158_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE \ + LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE \ + AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE VMA.OE CIIN.OE .names un3_as_030_i.BLIF AS_030 1 1 .names AS_030.PIN AS_030_c 1 1 .names BGACK_030_INT_i.BLIF AS_030.OE 1 1 -.names N_175_i.BLIF AS_000 +.names N_224_i.BLIF AS_000 1 1 .names AS_000.PIN AS_000_c 1 1 -.names N_69_i.BLIF AS_000.OE +.names N_203_i.BLIF AS_000.OE 1 1 .names inst_RW_000_INT.BLIF RW_000 1 1 .names RW_000.PIN RW_000_c 1 1 -.names N_69_i.BLIF RW_000.OE +.names N_203_i.BLIF RW_000.OE 1 1 .names un1_UDS_000_INT.BLIF UDS_000 1 1 .names UDS_000.PIN UDS_000_c 1 1 -.names N_69_i.BLIF UDS_000.OE +.names N_203_i.BLIF UDS_000.OE 1 1 .names un1_LDS_000_INT.BLIF LDS_000 1 1 .names LDS_000.PIN LDS_000_c 1 1 -.names N_69_i.BLIF LDS_000.OE +.names N_203_i.BLIF LDS_000.OE 1 1 .names SIZE_DMA_0_.BLIF SIZE_0_ 1 1 @@ -285,7 +287,7 @@ 1 1 .names BGACK_030_INT_i.BLIF DS_030.OE 1 1 -.names N_219_i.BLIF DSACK1 +.names N_225_i.BLIF DSACK1 1 1 .names un1_dsack1_i.BLIF DSACK1.OE 1 1 @@ -293,1144 +295,1156 @@ 1 1 .names inst_BGACK_030_INTreg.BLIF VMA.OE 1 1 -.names un10_ciin.BLIF CIIN +.names un8_ciin.BLIF CIIN 1 1 -.names N_60.BLIF CIIN.OE -1 1 -.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_282_0_3 -11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -.names N_282_0_1.BLIF N_282_0_2.BLIF N_282_0_4 -11 1 -.names N_68_i.BLIF SM_AMIGA_5_.BLIF N_135_0 -11 1 -.names N_282_0_4.BLIF N_282_0_3.BLIF N_282_0 -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF pos_clk_un10_sm_amiga_i_n -11 1 -.names N_98_i.BLIF cpu_est_i_2__n.BLIF N_208 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 -11 1 -.names N_143_i.BLIF N_144_i.BLIF pos_clk_un9_clk_000_pe_0_n -11 1 -.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 -11 1 -.names N_145_i.BLIF RST_c.BLIF N_35_0 -11 1 -.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 -11 1 -.names N_146_i.BLIF RST_c.BLIF N_36_0 -11 1 -.names N_21_0.BLIF IPL_030DFF_0_reg.D -0 1 -.names N_147_i.BLIF N_148_i.BLIF cpu_est_2_0_1__n -11 1 -.names CLK_OSZI_c.BLIF cpu_est_3_.C -1 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n -0 1 -.names N_149_i.BLIF N_208_i.BLIF cpu_est_2_0_2__n -11 1 -.names N_43_0.BLIF IPL_D0_2_.D -0 1 -.names N_80.BLIF N_154_i.BLIF cpu_est_2_0_3__n -11 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n -0 1 -.names N_155_i.BLIF N_162_i.BLIF un5_e_0 -11 1 -.names N_42_0.BLIF IPL_D0_1_.D -0 1 -.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF N_63_0 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_0_.C -1 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names N_259_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n -11 1 -.names N_41_0.BLIF IPL_D0_0_.D -0 1 -.names N_260_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n -11 1 -.names DTACK_c.BLIF DTACK_c_i -0 1 -.names N_190_i.BLIF N_191_i.BLIF cpu_est_0_.D -11 1 -.names N_45_0.BLIF inst_DTACK_D0.D -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C -1 1 -.names VPA_c.BLIF VPA_c_i -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names N_44_0.BLIF inst_VPA_D.D -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_68_i -11 1 -.names N_13.BLIF N_13_i -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names N_27_0.BLIF inst_VMA_INTreg.D -0 1 -.names BGACK_030_INT_i.BLIF N_128.BLIF N_259 -11 1 -.names CLK_OSZI_c.BLIF inst_VPA_D.C +.names N_205.BLIF CIIN.OE 1 1 .names inst_LDS_000_INT.BLIF LDS_000_INT_i 0 1 -.names BGACK_030_INT_i.BLIF N_128_i.BLIF N_260 +.names N_79_i.BLIF SM_AMIGA_5_.BLIF N_105_0 11 1 .names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT 0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +.names inst_VPA_D.BLIF VPA_D_i 0 1 -.names N_147.BLIF N_147_i +.names inst_UDS_000_INT.BLIF UDS_000_INT_i 0 1 -.names N_134.BLIF sm_amiga_i_2__n.BLIF N_182 -11 1 -.names N_148.BLIF N_148_i +.names cpu_est_3_.BLIF cpu_est_i_3__n 0 1 -.names N_68_i.BLIF N_131.BLIF N_183 -11 1 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C 1 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n +.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT 0 1 -.names N_107.BLIF sm_amiga_i_3__n.BLIF N_184 -11 1 -.names N_146.BLIF N_146_i +.names inst_AS_030_D0.BLIF AS_030_D0_i 0 1 -.names N_135.BLIF sm_amiga_i_4__n.BLIF N_185 +.names inst_BGACK_030_INT_D.BLIF AS_030_D1_i.BLIF N_104_0_1 11 1 -.names N_36_0.BLIF inst_A0_DMA.D -0 1 -.names N_72_i.BLIF SM_AMIGA_0_.BLIF N_268 +.names sm_amiga_i_i_7__n.BLIF nEXP_SPACE_c.BLIF N_85_0 11 1 -.names N_145.BLIF N_145_i -0 1 -.names N_68.BLIF cpu_est_i_0__n.BLIF N_190 +.names inst_BGACK_030_INTreg.BLIF N_85_0.BLIF N_104_0_2 11 1 -.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +.names N_171_i.BLIF N_172_i.BLIF un11_amiga_bus_enable_high_i +11 1 +.names N_104_0_1.BLIF N_104_0_2.BLIF N_104_0 +11 1 +.names N_164_i.BLIF N_228_i.BLIF N_204_0 +11 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C 1 1 -.names N_35_0.BLIF inst_AMIGA_DS.D -0 1 -.names N_68_i.BLIF cpu_est_0_.BLIF N_191 +.names N_85_0.BLIF CLK_000_D_4_.BLIF N_100_0_1 11 1 -.names N_143.BLIF N_143_i -0 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names N_144.BLIF N_144_i -0 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_202 +.names inst_BGACK_030_INTreg.BLIF nEXP_SPACE_c.BLIF un1_dsack1_i 11 1 +.names AS_030_000_SYNC_i.BLIF clk_000_d_i_3__n.BLIF N_100_0_2 +11 1 +.names inst_BGACK_030_INTreg.BLIF RST_c.BLIF N_203_i +11 1 +.names N_100_0_1.BLIF N_100_0_2.BLIF N_100_0 +11 1 +.names N_162_i.BLIF N_163_i.BLIF cpu_est_0_.D +11 1 +.names N_192_i.BLIF RST_c.BLIF N_113_i_1 +11 1 +.names N_179_i.BLIF N_180_i.BLIF inst_AS_000_INT.D +11 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C +1 1 +.names N_79.BLIF N_193_i.BLIF N_113_i_2 +11 1 +.names N_182_i.BLIF RST_c.BLIF N_38_0 +11 1 +.names N_113_i_1.BLIF N_113_i_2.BLIF SM_AMIGA_1_.D +11 1 +.names N_183_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names N_99.BLIF N_79_i.BLIF N_107_0_1 +11 1 +.names N_184_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names N_150.BLIF N_150_i +0 1 +.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF N_78_0 +11 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C +1 1 .names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n 0 1 -.names N_93_i.BLIF RW_c.BLIF N_203 -11 1 -.names CLK_OSZI_c.BLIF BG_000DFFreg.C -1 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 .names N_20.BLIF N_20_i 0 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_79_i +11 1 .names N_23_0.BLIF IPL_030DFF_2_reg.D 0 1 -.names ahigh_c_28__n.BLIF ahigh_i_28__n +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n 0 1 .names N_19.BLIF N_19_i 0 1 -.names ahigh_c_29__n.BLIF ahigh_i_29__n -0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_80_i +11 1 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 .names N_22_0.BLIF IPL_030DFF_1_reg.D 0 1 -.names ahigh_c_30__n.BLIF ahigh_i_30__n -0 1 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_82_i +11 1 .names N_18.BLIF N_18_i 0 1 -.names ahigh_c_31__n.BLIF ahigh_i_31__n +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_83_i +11 1 +.names N_21_0.BLIF IPL_030DFF_0_reg.D 0 1 -.names N_182.BLIF N_182_i +.names N_80_i.BLIF SM_AMIGA_6_.BLIF N_84_i +11 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n 0 1 -.names N_181.BLIF N_181_i +.names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 -.names N_260.BLIF N_260_i -0 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C 1 1 -.names pos_clk_size_dma_6_0_1__n.BLIF SIZE_DMA_1_.D +.names N_43_0.BLIF IPL_D0_2_.D 0 1 -.names N_72.BLIF SM_AMIGA_2_.BLIF N_141 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_89_i 11 1 -.names N_259.BLIF N_259_i +.names ipl_c_1__n.BLIF ipl_c_i_1__n 0 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_142 +.names N_95.BLIF N_220_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0 11 1 -.names pos_clk_size_dma_6_0_0__n.BLIF SIZE_DMA_0_.D +.names N_42_0.BLIF IPL_D0_1_.D 0 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_145 -11 1 -.names N_63_0.BLIF N_63 +.names a_decode_c_19__n.BLIF a_decode_i_19__n 0 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF N_146 -11 1 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names a_decode_c_18__n.BLIF a_decode_i_18__n +0 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 1 -.names N_155.BLIF N_155_i +.names N_41_0.BLIF IPL_D0_0_.D 0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_147 -11 1 -.names N_162.BLIF N_162_i +.names a_decode_c_16__n.BLIF a_decode_i_16__n 0 1 -.names N_98.BLIF cpu_est_2_.BLIF N_149 +.names N_13.BLIF N_13_i +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_177.BLIF N_177_i +0 1 +.names AS_000_INT_i.BLIF AS_030_i.BLIF N_224 11 1 +.names N_178.BLIF N_178_i +0 1 +.names inst_DSACK1_INT.BLIF DSACK1_INT_i +0 1 +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +1 1 +.names un8_ciin.BLIF un8_ciin_i +0 1 +.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_225 +11 1 +.names N_205_0.BLIF N_205 +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names N_160.BLIF N_160_i +0 1 +.names N_89_i.BLIF cpu_est_i_2__n.BLIF N_229 +11 1 +.names N_161.BLIF N_161_i +0 1 +.names N_126_i.BLIF N_150_i.BLIF pos_clk_un9_clk_000_pe_0_n +11 1 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 .names un5_e_0.BLIF un5_e 0 1 -.names N_98_i.BLIF cpu_est_2_.BLIF N_154 +.names N_156_i.BLIF N_229_i.BLIF cpu_est_2_0_2__n 11 1 -.names N_154.BLIF N_154_i +.names N_159.BLIF N_159_i 0 1 -.names N_82_i.BLIF cpu_est_3_.BLIF N_155 +.names N_83.BLIF N_157_i.BLIF cpu_est_2_0_3__n 11 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +.names N_158.BLIF N_158_i +0 1 +.names N_160_i.BLIF N_161_i.BLIF un5_e_0 +11 1 +.names N_157.BLIF N_157_i +0 1 +.names nEXP_SPACE_i.BLIF un8_ciin_i.BLIF N_205_0 +11 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_DS.C 1 1 .names cpu_est_2_0_3__n.BLIF cpu_est_2_3__n 0 1 +.names N_177_i.BLIF N_178_i.BLIF inst_DSACK1_INT.D +11 1 +.names N_156.BLIF N_156_i +0 1 +.names N_105.BLIF sm_amiga_i_4__n.BLIF N_159 +11 1 +.names N_229.BLIF N_229_i +0 1 +.names N_82_i.BLIF cpu_est_3_.BLIF N_160 +11 1 +.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +.names N_126.BLIF N_126_i +0 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names N_74_i.BLIF N_74 +0 1 +.names N_225.BLIF RST_c.BLIF N_177 +11 1 +.names N_197.BLIF N_197_i +0 1 +.names N_97_i.BLIF RST_c.BLIF N_178 +11 1 +.names N_195.BLIF N_195_i +0 1 +.names N_224.BLIF RST_c.BLIF N_179 +11 1 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +.names N_196.BLIF N_196_i +0 1 +.names N_84_i.BLIF RST_c.BLIF N_180 +11 1 +.names N_194.BLIF N_194_i +0 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF N_182 +11 1 +.names N_190.BLIF N_190_i +0 1 +.names BGACK_030_INT_i.BLIF N_96.BLIF N_183 +11 1 +.names N_214.BLIF N_214_i +0 1 +.names BGACK_030_INT_i.BLIF N_96_i.BLIF N_184 +11 1 +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +1 1 +.names N_184.BLIF N_184_i +0 1 +.names N_80_i.BLIF SM_AMIGA_0_.BLIF N_191 +11 1 +.names pos_clk_size_dma_6_0_1__n.BLIF SIZE_DMA_1_.D +0 1 +.names N_95.BLIF sm_amiga_i_3__n.BLIF N_196 +11 1 +.names N_183.BLIF N_183_i +0 1 +.names N_84.BLIF sm_amiga_i_5__n.BLIF N_197 +11 1 +.names pos_clk_size_dma_6_0_0__n.BLIF SIZE_DMA_0_.D +0 1 +.names N_84_i.BLIF RW_c.BLIF N_220 +11 1 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +.names N_182.BLIF N_182_i +0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names N_149.BLIF N_149_i +.names N_38_0.BLIF inst_A0_DMA.D 0 1 .names G_105.BLIF N_187_i 0 1 -.names N_208.BLIF N_208_i +.names N_179.BLIF N_179_i 0 1 .names G_106.BLIF N_188_i 0 1 -.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n +.names N_180.BLIF N_180_i 0 1 .names G_107.BLIF N_189_i 0 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 +.names N_105_0.BLIF N_105 +0 1 +.names N_97_i.BLIF N_97 +0 1 +.names LDS_000_c.BLIF LDS_000_c_i +0 1 +.names UDS_000_c.BLIF UDS_000_c_i +0 1 +.names N_89.BLIF cpu_est_2_.BLIF N_156 +11 1 +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +1 1 +.names N_96_i.BLIF N_96 +0 1 +.names N_89_i.BLIF cpu_est_2_.BLIF N_157 +11 1 +.names N_95_i.BLIF N_95 +0 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names N_220.BLIF N_220_i +0 1 +.names N_97.BLIF sm_amiga_i_0__n.BLIF N_158 +11 1 +.names un1_DS_000_ENABLE_0_sqmuxa_0.BLIF un1_DS_000_ENABLE_0_sqmuxa +0 1 +.names N_213.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names CLK_OSZI_c.BLIF inst_AS_030_D1.C 1 1 .names inst_VMA_INTreg.BLIF VMA_INT_i 0 1 -.names ahigh_c_24__n.BLIF ahigh_i_24__n +.names N_212.BLIF inst_RW_000_DMA.D 0 1 -.names N_98_i.BLIF N_98 -0 1 -.names ahigh_c_25__n.BLIF ahigh_i_25__n -0 1 -.names N_93_i.BLIF N_93 -0 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n -0 1 -.names N_80_i.BLIF N_80 -0 1 -.names ahigh_c_27__n.BLIF ahigh_i_27__n -0 1 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -.names N_72_i.BLIF N_72 -0 1 -.names N_126.BLIF inst_RW_000_DMA.D -0 1 -.names N_68_i.BLIF N_68 -0 1 -.names N_150.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 -.names N_59_i.BLIF N_59 -0 1 -.names N_151.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D -0 1 -.names N_190.BLIF N_190_i -0 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_42_0 -11 1 -.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C -1 1 -.names N_191.BLIF N_191_i +.names N_89_i.BLIF N_89 0 1 .names ipl_c_i_2__n.BLIF RST_c.BLIF N_43_0 11 1 -.names N_267.BLIF N_267_i +.names N_84_i.BLIF N_84 0 1 .names N_18_i.BLIF RST_c.BLIF N_21_0 11 1 -.names N_266.BLIF N_266_i +.names N_83_i.BLIF N_83 0 1 .names N_19_i.BLIF RST_c.BLIF N_22_0 11 1 -.names N_186.BLIF N_186_i +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +.names N_80_i.BLIF N_80 0 1 .names N_20_i.BLIF RST_c.BLIF N_23_0 11 1 -.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C -1 1 -.names N_185.BLIF N_185_i +.names N_79_i.BLIF N_79 0 1 -.names N_68.BLIF cpu_est_0_1__un3_n +.names N_79.BLIF cpu_est_0_2__un3_n 0 1 -.names N_183.BLIF N_183_i +.names N_78_0.BLIF N_78 0 1 -.names cpu_est_1_.BLIF N_68.BLIF cpu_est_0_1__un1_n +.names cpu_est_2_.BLIF N_79.BLIF cpu_est_0_2__un1_n 11 1 -.names N_184.BLIF N_184_i -0 1 -.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names N_268.BLIF N_268_i -0 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C -1 1 -.names N_132_0.BLIF N_132 -0 1 -.names N_68.BLIF cpu_est_0_2__un3_n -0 1 -.names N_142.BLIF N_142_i -0 1 -.names cpu_est_2_.BLIF N_68.BLIF cpu_est_0_2__un1_n -11 1 -.names N_141.BLIF N_141_i +.names N_45_0.BLIF inst_DTACK_D0.D 0 1 .names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n 11 1 -.names N_135_0.BLIF N_135 +.names CLK_OSZI_c.BLIF BG_000DFFreg.C +1 1 +.names N_152.BLIF N_152_i 0 1 .names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_DS.C -1 1 -.names N_134_0.BLIF N_134 +.names N_153.BLIF N_153_i 0 1 -.names N_68.BLIF cpu_est_0_3__un3_n +.names N_79.BLIF cpu_est_0_3__un3_n 0 1 -.names N_131_i.BLIF N_131 +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n 0 1 -.names cpu_est_3_.BLIF N_68.BLIF cpu_est_0_3__un1_n +.names cpu_est_3_.BLIF N_79.BLIF cpu_est_0_3__un1_n 11 1 -.names LDS_000_c.BLIF LDS_000_c_i +.names N_163.BLIF N_163_i 0 1 .names cpu_est_2_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 -.names UDS_000_c.BLIF UDS_000_c_i +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +.names N_162.BLIF N_162_i 0 1 .names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_A0_DMA.C -1 1 -.names N_128_i.BLIF N_128 +.names N_164.BLIF N_164_i 0 1 .names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n 0 1 -.names N_107_i.BLIF N_107 +.names N_228.BLIF N_228_i 0 1 .names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n 11 1 -.names N_203.BLIF N_203_i +.names N_204_0.BLIF N_204 0 1 .names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names un1_DS_000_ENABLE_0_sqmuxa_0.BLIF un1_DS_000_ENABLE_0_sqmuxa +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +.names N_171.BLIF N_171_i 0 1 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_18 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C -1 1 -.names N_201.BLIF N_201_i +.names N_172.BLIF N_172_i 0 1 .names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n 0 1 -.names N_202.BLIF N_202_i +.names CLK_000_D_3_.BLIF clk_000_d_i_3__n 0 1 .names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n 11 1 -.names N_60_0.BLIF N_60 +.names N_100_0.BLIF N_100 0 1 .names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 -.names N_274.BLIF N_274_i +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +.names inst_AS_030_D1.BLIF AS_030_D1_i 0 1 .names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_19 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_AS_030_D0.C -1 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +.names N_104_0.BLIF N_104 0 1 .names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n 0 1 -.names RW_c.BLIF RW_c_i +.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n 0 1 .names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n 11 1 -.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n +.names N_201.BLIF N_201_i 0 1 .names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 -.names N_168.BLIF N_168_i +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +.names N_81_i.BLIF N_81 0 1 .names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_20 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -.names N_167.BLIF N_167_i +.names N_219.BLIF N_219_i 0 1 .names un3_as_030.BLIF un3_as_030_i 0 1 -.names N_170.BLIF N_170_i +.names N_202.BLIF N_202_i 0 1 -.names N_175.BLIF N_175_i +.names N_224.BLIF N_224_i 0 1 -.names N_169.BLIF N_169_i +.names N_191.BLIF N_191_i 0 1 -.names N_219.BLIF N_219_i +.names N_225.BLIF N_225_i 0 1 -.names N_38_0.BLIF inst_AS_030_D0.D +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +.names N_99_i.BLIF N_99 0 1 .names un2_ds_030.BLIF un2_ds_030_i 0 1 -.names CLK_OSZI_c.BLIF inst_AS_030_D1.C -1 1 -.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +.names N_107_0.BLIF N_107 0 1 -.names N_63.BLIF ds_000_enable_0_un3_n +.names N_78.BLIF ds_000_enable_0_un3_n 0 1 -.names N_282_0.BLIF N_282 +.names N_192.BLIF N_192_i 0 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_63.BLIF ds_000_enable_0_un1_n +.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_78.BLIF ds_000_enable_0_un1_n 11 1 -.names CLK_000_D_3_.BLIF clk_000_d_i_3__n +.names N_193.BLIF N_193_i 0 1 .names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n 11 1 -.names N_96_0.BLIF N_96 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +.names N_11.BLIF N_11_i 0 1 .names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6 1- 1 -1 1 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C -1 1 -.names N_129_i.BLIF N_129 +.names N_29_0.BLIF inst_AS_030_000_SYNC.D 0 1 .names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n 0 1 -.names N_15.BLIF N_15_i +.names VPA_c.BLIF VPA_c_i 0 1 .names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n 11 1 -.names N_26_0.BLIF inst_LDS_000_INT.D +.names N_44_0.BLIF inst_VPA_D.D 0 1 .names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n 11 1 -.names N_12.BLIF N_12_i +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +.names DTACK_c.BLIF DTACK_c_i 0 1 .names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_13 1- 1 -1 1 +.names N_16.BLIF N_16_i +0 1 +.names RST_c.BLIF as_030_d1_0_un3_n +0 1 +.names N_25_0.BLIF BG_000DFFreg.D +0 1 +.names inst_AS_030_D0.BLIF RST_c.BLIF as_030_d1_0_un1_n +11 1 +.names N_15.BLIF N_15_i +0 1 +.names inst_AS_030_D1.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un0_n +11 1 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 -.names N_28_0.BLIF inst_RW_000_INT.D +.names N_26_0.BLIF inst_LDS_000_INT.D +0 1 +.names as_030_d1_0_un1_n.BLIF as_030_d1_0_un0_n.BLIF inst_AS_030_D1.D +1- 1 +-1 1 +.names N_12.BLIF N_12_i 0 1 .names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D 11 1 -.names N_11.BLIF N_11_i +.names N_28_0.BLIF inst_RW_000_INT.D 0 1 .names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 11 1 -.names N_29_0.BLIF inst_AS_030_000_SYNC.D -0 1 -.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 -11 1 .names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D 1 1 .names N_5.BLIF N_5_i 0 1 -.names N_13_i.BLIF RST_c.BLIF N_27_0 +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 11 1 .names N_30_0.BLIF inst_BGACK_030_INTreg.D 0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_44_0 +.names N_13_i.BLIF RST_c.BLIF N_27_0 11 1 .names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 .names a_c_0__n.BLIF a_c_i_0__n 0 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_45_0 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_41_0 11 1 .names size_c_1__n.BLIF size_c_i_1__n 0 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_41_0 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_42_0 11 1 -.names N_163.BLIF N_163_i +.names N_231.BLIF N_231_i 0 1 .names vcc_n_n 1 -.names N_244_0.BLIF N_244 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n 0 1 .names gnd_n_n .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C 1 1 -.names N_164.BLIF N_164_i +.names N_40_0.BLIF inst_AS_030_D0.D 0 1 .names A_DECODE_15_.BLIF a_decode_15__n 1 1 -.names N_165.BLIF N_165_i +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 0 1 .names A_DECODE_14_.BLIF a_decode_14__n 1 1 -.names un10_ciin.BLIF un10_ciin_i +.names RW_c.BLIF RW_c_i 0 1 .names A_DECODE_13_.BLIF a_decode_13__n 1 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D 1 1 -.names N_180.BLIF N_180_i +.names inst_AMIGA_DS.BLIF AMIGA_DS_i 0 1 .names A_DECODE_12_.BLIF a_decode_12__n 1 1 -.names N_262.BLIF N_262_i +.names N_186.BLIF N_186_i 0 1 .names A_DECODE_11_.BLIF a_decode_11__n 1 1 .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C 1 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +.names N_185.BLIF N_185_i 0 1 .names A_DECODE_10_.BLIF a_decode_10__n 1 1 -.names pos_clk_un2_i_n.BLIF pos_clk_un2_n +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c 0 1 .names A_DECODE_9_.BLIF a_decode_9__n 1 1 -.names N_3.BLIF N_3_i +.names pos_clk_un2_i_n.BLIF pos_clk_un2_n 0 1 .names A_DECODE_8_.BLIF a_decode_8__n 1 1 .names IPL_D0_0_.BLIF G_105.X1 1 1 -.names N_32_0.BLIF inst_DS_000_DMA.D +.names N_3.BLIF N_3_i 0 1 .names A_DECODE_7_.BLIF a_decode_7__n 1 1 -.names N_4.BLIF N_4_i +.names N_32_0.BLIF inst_DS_000_DMA.D 0 1 .names A_DECODE_6_.BLIF a_decode_6__n 1 1 .names ipl_c_0__n.BLIF G_105.X2 1 1 -.names N_31_0.BLIF inst_AS_000_DMA.D +.names N_4.BLIF N_4_i 0 1 .names A_DECODE_5_.BLIF a_decode_5__n 1 1 -.names N_220_i.BLIF inst_BGACK_030_INT_D.D +.names N_31_0.BLIF inst_AS_000_DMA.D 0 1 .names A_DECODE_4_.BLIF a_decode_4__n 1 1 -.names BG_030_c.BLIF BG_030_c_i +.names N_39_1_i.BLIF inst_BGACK_030_INT_D.D 0 1 .names A_DECODE_3_.BLIF a_decode_3__n 1 1 .names IPL_D0_1_.BLIF G_106.X1 1 1 -.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n +.names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D 0 1 .names A_DECODE_2_.BLIF a_decode_2__n 1 1 -.names N_17.BLIF N_17_i +.names A_DECODE_16_.BLIF a_decode_c_16__n +1 1 +.names BG_030_c.BLIF BG_030_c_i 0 1 .names ipl_c_1__n.BLIF G_106.X2 1 1 -.names N_24_0.BLIF inst_UDS_000_INT.D -0 1 -.names N_16.BLIF N_16_i -0 1 -.names N_25_0.BLIF BG_000DFFreg.D -0 1 -.names IPL_D0_2_.BLIF G_107.X1 -1 1 -.names N_205_i.BLIF N_205 -0 1 -.names N_140.BLIF N_140_i -0 1 -.names ipl_c_2__n.BLIF G_107.X2 -1 1 -.names A_DECODE_16_.BLIF a_decode_c_16__n -1 1 -.names inst_AMIGA_DS.BLIF AMIGA_DS_i -0 1 .names A_DECODE_17_.BLIF a_decode_c_17__n 1 1 -.names N_199.BLIF N_199_i +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n 0 1 .names A_DECODE_18_.BLIF a_decode_c_18__n 1 1 -.names N_198.BLIF N_198_i +.names N_17.BLIF N_17_i +0 1 +.names A_DECODE_19_.BLIF a_decode_c_19__n +1 1 +.names N_24_0.BLIF inst_UDS_000_INT.D +0 1 +.names IPL_D0_2_.BLIF G_107.X1 +1 1 +.names A_DECODE_20_.BLIF a_decode_c_20__n +1 1 +.names N_181.BLIF N_181_i +0 1 +.names A_DECODE_21_.BLIF a_decode_c_21__n +1 1 +.names N_37_0.BLIF inst_AMIGA_DS.D +0 1 +.names ipl_c_2__n.BLIF G_107.X2 +1 1 +.names A_DECODE_22_.BLIF a_decode_c_22__n +1 1 +.names N_176.BLIF N_176_i +0 1 +.names A_DECODE_23_.BLIF a_decode_c_23__n +1 1 +.names N_175.BLIF N_175_i +0 1 +.names N_72_i.BLIF N_72 0 1 .names CYCLE_DMA_1_.BLIF G_91.X1 1 1 -.names A_DECODE_19_.BLIF a_decode_c_19__n -1 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names A_DECODE_20_.BLIF a_decode_c_20__n -1 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_262 -11 1 -.names N_199.BLIF G_91.X2 -1 1 -.names A_DECODE_21_.BLIF a_decode_c_21__n -1 1 -.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n -0 1 -.names A_DECODE_22_.BLIF a_decode_c_22__n -1 1 -.names cycle_dma_i_0__n.BLIF N_68.BLIF N_198 -11 1 -.names A_DECODE_23_.BLIF a_decode_c_23__n -1 1 -.names N_180_i.BLIF N_262_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names CLK_000_D_2_.BLIF CLK_000_D_3_.D -1 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 .names A_1_.BLIF a_c_1__n 1 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +.names N_198.BLIF N_198_i 0 1 .names nEXP_SPACE.BLIF nEXP_SPACE_c 1 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +.names RW_000_c.BLIF RW_000_i 0 1 +.names N_176.BLIF G_91.X2 +1 1 +.names N_185_i.BLIF N_186_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 .names BG_030.BLIF BG_030_c 1 1 -.names un21_fpu_cs.BLIF un21_fpu_cs_i +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 .names BG_000DFFreg.BLIF BG_000 1 1 -.names a_c_1__n.BLIF N_220_i.BLIF N_150 -11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D +1 1 .names inst_BGACK_030_INTreg.BLIF BGACK_030 1 1 -.names a_c_1__n.BLIF a_i_1__n +.names AS_000_c.BLIF AS_000_i 0 1 .names BGACK_000.BLIF BGACK_000_c 1 1 -.names a_i_1__n.BLIF N_220_i.BLIF N_151 +.names N_181_i.BLIF RST_c.BLIF N_37_0 +11 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_181 11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 .names CLK_000.BLIF CLK_000_D_0_.D 1 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF un3_as_030 -11 1 +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i +0 1 .names CLK_OSZI.BLIF CLK_OSZI_c 1 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i +.names un21_fpu_cs.BLIF un21_fpu_cs_i 0 1 .names CLK_OUT_INTreg.BLIF CLK_DIV_OUT 1 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names CLK_OUT_INTreg.BLIF CLK_EXP +1 1 +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un3_as_030 +11 1 +.names un21_fpu_cs_i.BLIF FPU_CS +1 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names FPU_SENSE.BLIF FPU_SENSE_c +1 1 .names AS_000_i.BLIF DS_000_DMA_i.BLIF un2_ds_030 11 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP +.names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 .names AS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n 0 1 -.names un21_fpu_cs_i.BLIF FPU_CS +.names IPL_030DFF_1_reg.BLIF IPL_030_1_ 1 1 .names inst_DS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n 11 1 -.names FPU_SENSE.BLIF FPU_SENSE_c +.names IPL_030DFF_2_reg.BLIF IPL_030_2_ 1 1 -.names N_205.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +.names N_72.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n 11 1 -.names IPL_030DFF_0_reg.BLIF IPL_030_0_ +.names IPL_0_.BLIF ipl_c_0__n 1 1 .names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 1- 1 -1 1 -.names IPL_030DFF_1_reg.BLIF IPL_030_1_ +.names IPL_1_.BLIF ipl_c_1__n 1 1 .names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n 0 1 -.names IPL_030DFF_2_reg.BLIF IPL_030_2_ +.names IPL_2_.BLIF ipl_c_2__n 1 1 .names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n 11 1 -.names IPL_0_.BLIF ipl_c_0__n -1 1 -.names N_205.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +.names N_72.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n 11 1 -.names IPL_1_.BLIF ipl_c_1__n +.names DTACK.BLIF DTACK_c 1 1 .names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 1- 1 -1 1 -.names IPL_2_.BLIF ipl_c_2__n +.names vcc_n_n.BLIF AVEC 1 1 .names N_4_i.BLIF RST_c.BLIF N_31_0 11 1 +.names un5_e.BLIF E +1 1 .names N_3_i.BLIF RST_c.BLIF N_32_0 11 1 -.names DTACK.BLIF DTACK_c +.names VPA.BLIF VPA_c 1 1 .names cycle_dma_i_0__n.BLIF cycle_dma_i_1__n.BLIF pos_clk_un2_i_n 11 1 -.names vcc_n_n.BLIF AVEC -1 1 .names CYCLE_DMA_1_.BLIF cycle_dma_i_1__n 0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C -1 1 -.names un5_e.BLIF E +.names RST.BLIF RST_c 1 1 .names CLK_OUT_INTreg.BLIF CLK_EXP_i 0 1 -.names VPA.BLIF VPA_c -1 1 -.names N_15_i.BLIF RST_c.BLIF N_26_0 -11 1 -.names RST.BLIF RST_c -1 1 -.names N_16_i.BLIF RST_c.BLIF N_25_0 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 -.names N_17_i.BLIF RST_c.BLIF N_24_0 -11 1 -.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n +.names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n 0 1 +.names CLK_OSZI_c.BLIF IPL_D0_2_.C +1 1 .names FC_0_.BLIF fc_c_0__n 1 1 -.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n +.names cycle_dma_i_0__n.BLIF N_79.BLIF N_175 11 1 .names FC_1_.BLIF fc_c_1__n 1 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_185 11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C -1 1 .names gnd_n_n.BLIF AMIGA_ADDR_ENABLE 1 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_17 -1- 1 --1 1 +.names N_5_i.BLIF RST_c.BLIF N_30_0 +11 1 .names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR 1 1 -.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n -0 1 +.names N_12_i.BLIF RST_c.BLIF N_28_0 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +1 1 .names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW 1 1 -.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n +.names N_15_i.BLIF RST_c.BLIF N_26_0 11 1 .names un11_amiga_bus_enable_high_i.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 +.names N_16_i.BLIF RST_c.BLIF N_25_0 +11 1 +.names N_17_i.BLIF RST_c.BLIF N_24_0 +11 1 +.names N_161_1.BLIF cpu_est_i_3__n.BLIF N_161 +11 1 +.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_153_1 +11 1 +.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n +11 1 +.names N_153_1.BLIF cpu_est_i_3__n.BLIF N_153 +11 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names N_189_i.BLIF N_187_i.BLIF pos_clk_ipl_1_n +11 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_17 +1- 1 +-1 1 +.names pos_clk_ipl_1_n.BLIF N_188_i.BLIF pos_clk_ipl_n +11 1 +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +.names N_190_i.BLIF N_191_i.BLIF N_127_i_1 +11 1 +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names N_127_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D +11 1 .names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 +.names N_84.BLIF N_214_i.BLIF N_123_i_1 +11 1 .names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_16 1- 1 -1 1 -.names N_183_i.BLIF N_184_i.BLIF N_117_i_1 +.names N_123_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D 11 1 .names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n 0 1 -.names N_117_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +1 1 +.names N_80.BLIF N_159_i.BLIF N_119_i_1 11 1 .names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n 11 1 -.names N_72.BLIF N_182_i.BLIF N_115_i_1 +.names N_119_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D 11 1 .names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n 11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -.names N_115_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D +.names N_80.BLIF N_158_i.BLIF N_111_i_1 11 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_15 1- 1 -1 1 -.names N_72.BLIF N_181_i.BLIF N_111_i_1 -11 1 -.names RST_c.BLIF as_030_d1_0_un3_n -0 1 .names N_111_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D 11 1 -.names inst_AS_030_D0.BLIF RST_c.BLIF as_030_d1_0_un1_n -11 1 -.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_165_1 -11 1 -.names inst_AS_030_D1.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C -1 1 -.names N_165_1.BLIF AS_030_i.BLIF N_165 -11 1 -.names as_030_d1_0_un1_n.BLIF as_030_d1_0_un0_n.BLIF inst_AS_030_D1.D -1- 1 --1 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_162_1 -11 1 .names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n 0 1 -.names N_162_1.BLIF cpu_est_i_3__n.BLIF N_162 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +.names N_228.BLIF BGACK_000_c.BLIF un21_berr_1 11 1 .names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un1_n 11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_148_1 +.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr 11 1 .names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C -1 1 -.names N_148_1.BLIF cpu_est_i_3__n.BLIF N_148 +.names N_228.BLIF BGACK_000_c.BLIF un21_fpu_cs_1 11 1 .names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_12 1- 1 -1 1 -.names N_189_i.BLIF N_187_i.BLIF pos_clk_ipl_1_n -11 1 -.names N_244.BLIF as_030_000_sync_0_un3_n -0 1 -.names pos_clk_ipl_1_n.BLIF N_188_i.BLIF pos_clk_ipl_n -11 1 -.names AS_030_c.BLIF N_244.BLIF as_030_000_sync_0_un1_n -11 1 -.names N_140_i.BLIF pos_clk_un2_n.BLIF N_205_i_2 -11 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C -1 1 -.names N_205_i_1.BLIF N_205_i_2.BLIF N_205_i -11 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_11 -1- 1 --1 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_180_1 +.names un21_fpu_cs_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs 11 1 .names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_180_2 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_172_1 11 1 .names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 -.names N_180_1.BLIF N_180_2.BLIF N_180 +.names N_172_1.BLIF AS_030_i.BLIF N_172 11 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n 11 1 -.names CLK_OSZI_c.BLIF IPL_D0_0_.C -1 1 -.names inst_AS_030_D0.BLIF CLK_000_D_0_.BLIF N_59_i_1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_161_1 11 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_5 1- 1 -1 1 -.names N_59_i_1.BLIF nEXP_SPACE_c.BLIF N_59_i +.names N_72_i_1.BLIF N_72_i_2.BLIF N_72_i 11 1 -.names BG_030_c_i.BLIF N_59.BLIF pos_clk_un9_bg_030_0_n +.names BG_030_c_i.BLIF N_74.BLIF pos_clk_un9_bg_030_0_n 11 1 -.names N_267_i.BLIF N_268_i.BLIF N_127_i_1 -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names N_127_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D -11 1 -.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low -11 1 -.names CLK_OSZI_c.BLIF IPL_D0_1_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C 1 1 -.names N_93.BLIF N_266_i.BLIF N_123_i_1 +.names AS_000_i.BLIF N_39_1_i.BLIF N_206_i_1 11 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_220_i +.names N_39_1_i.BLIF RW_000_i.BLIF N_212 11 1 -.names N_123_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D +.names N_175_i.BLIF N_176_i.BLIF N_206_i_2 11 1 -.names N_220_i.BLIF RW_000_i.BLIF N_126 +.names N_39_1_i.BLIF N_81.BLIF N_213 11 1 -.names N_68.BLIF N_186_i.BLIF N_121_i_1 +.names N_206_i_1.BLIF N_206_i_2.BLIF CYCLE_DMA_0_.D 11 1 -.names N_93.BLIF sm_amiga_i_5__n.BLIF N_186 +.names N_39_1_i.BLIF N_81_i.BLIF N_34_0 11 1 -.names N_121_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_186_1 11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names CLK_OSZI_c.BLIF IPL_D0_2_.C +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_39_1_i +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 -.names N_72.BLIF N_185_i.BLIF N_119_i_1 +.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_186_2 11 1 -.names N_129.BLIF sm_amiga_i_0__n.BLIF N_181 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_219 11 1 -.names N_119_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +.names N_186_1.BLIF N_186_2.BLIF N_186 11 1 -.names N_93_i.BLIF RST_c.BLIF N_170 +.names N_79_i.BLIF N_99.BLIF N_195 11 1 -.names un21_fpu_cs_1.BLIF N_282_0.BLIF un21_fpu_cs +.names inst_AS_030_D0.BLIF CLK_000_D_0_.BLIF N_74_i_1 11 1 -.names N_175.BLIF RST_c.BLIF N_169 +.names N_107.BLIF sm_amiga_i_2__n.BLIF N_194 11 1 -.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr_1_0 +.names N_74_i_1.BLIF nEXP_SPACE_c.BLIF N_74_i 11 1 -.names N_129_i.BLIF RST_c.BLIF N_168 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 -.names un21_berr_1_0.BLIF N_282_0.BLIF un21_berr -11 1 -.names N_219.BLIF RST_c.BLIF N_167 -11 1 -.names AS_000_i.BLIF N_220_i.BLIF pos_clk_cycle_dma_5_1_1__n -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i -0 1 -.names pos_clk_cycle_dma_5_1_1__n.BLIF G_91.BLIF CYCLE_DMA_1_.D -11 1 -.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_164 -11 1 -.names N_68_i.BLIF CYCLE_DMA_0_.BLIF N_199_1 -11 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -.names N_199_1.BLIF cycle_dma_i_1__n.BLIF N_199 -11 1 -.names a_decode_c_19__n.BLIF a_decode_i_19__n -0 1 -.names CLK_EXP_i.BLIF inst_CLK_OUT_PRE_D.BLIF AS_000_DMA_1_sqmuxa_1 -11 1 -.names a_decode_c_18__n.BLIF a_decode_i_18__n -0 1 -.names AS_000_DMA_1_sqmuxa_1.BLIF N_205_i.BLIF AS_000_DMA_1_sqmuxa -11 1 -.names N_5_i.BLIF RST_c.BLIF N_30_0 -11 1 -.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF N_140_1 -11 1 -.names N_11_i.BLIF RST_c.BLIF N_29_0 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -.names N_140_1.BLIF RW_000_i.BLIF N_140 -11 1 -.names N_12_i.BLIF RST_c.BLIF N_28_0 -11 1 -.names AS_000_i.BLIF N_198_i.BLIF N_66_i_1 -11 1 -.names N_164_i.BLIF N_165_i.BLIF un11_amiga_bus_enable_high_i -11 1 -.names N_199_i.BLIF N_220_i.BLIF N_66_i_2 -11 1 -.names AS_030_i.BLIF N_163_i.BLIF N_244_0 -11 1 -.names CLK_000_D_0_.BLIF CLK_000_D_1_.D -1 1 -.names N_66_i_1.BLIF N_66_i_2.BLIF CYCLE_DMA_0_.D -11 1 -.names inst_BGACK_030_INTreg.BLIF RST_c.BLIF N_69_i -11 1 -.names AMIGA_DS_i.BLIF AS_000_i.BLIF N_205_i_1 -11 1 -.names inst_BGACK_030_INTreg.BLIF nEXP_SPACE_c.BLIF un1_dsack1_i -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_1_.C -1 1 -.names N_134_0_1.BLIF SM_AMIGA_3_.BLIF N_134_0 -11 1 -.names AS_000_c.BLIF N_68_i.BLIF N_274 -11 1 -.names N_68.BLIF N_141_i.BLIF N_113_i_1 -11 1 -.names inst_DSACK1_INT.BLIF DSACK1_INT_i -0 1 -.names N_142_i.BLIF RST_c.BLIF N_113_i_2 -11 1 -.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_219 -11 1 -.names CLK_000_D_1_.BLIF CLK_000_D_2_.D -1 1 -.names N_113_i_1.BLIF N_113_i_2.BLIF SM_AMIGA_1_.D -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names N_68_i.BLIF N_208.BLIF N_144_1 -11 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names CLK_OSZI_c.BLIF CLK_000_D_2_.C -1 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_144_2 -11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF N_175 -11 1 -.names N_144_1.BLIF N_144_2.BLIF N_144 -11 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names N_72_i.BLIF N_82_i.BLIF N_143_1 -11 1 -.names N_96.BLIF sm_amiga_i_i_7__n.BLIF N_267 -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_143_2 -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_D_3_.C -1 1 -.names N_143_1.BLIF N_143_2.BLIF N_143 -11 1 -.names N_132.BLIF sm_amiga_i_6__n.BLIF N_266 -11 1 -.names AS_030_D1_i.BLIF inst_BGACK_030_INT_D.BLIF N_163_1 -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names N_282.BLIF sm_amiga_i_i_7__n.BLIF N_163_2 -11 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names CLK_000_D_3_.BLIF CLK_000_D_4_.D -1 1 -.names N_163_1.BLIF N_163_2.BLIF N_163_3 -11 1 -.names inst_AS_030_D1.BLIF AS_030_D1_i -0 1 -.names N_163_3.BLIF un1_dsack1_i.BLIF N_163 -11 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names CLK_OSZI_c.BLIF CLK_000_D_4_.C -1 1 -.names un21_berr_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1 -11 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 -11 1 -.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 -11 1 -.names N_96_0.BLIF sm_amiga_i_i_7__n.BLIF N_132_0 -11 1 -.names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 -11 1 -.names N_268_i.BLIF SM_AMIGA_i_7_.BLIF N_246_i -11 1 -.names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 +.names N_79.BLIF N_197_i.BLIF N_121_i_1 11 1 .names SM_AMIGA_1_.BLIF sm_amiga_i_1__n 0 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C -1 1 -.names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 +.names N_121_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D 11 1 -.names N_68_i.BLIF SM_AMIGA_1_.BLIF N_129_i +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_193 11 1 -.names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 +.names N_195_i.BLIF N_196_i.BLIF N_117_i_1 11 1 -.names N_93.BLIF N_246_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +.names N_80.BLIF SM_AMIGA_2_.BLIF N_192 11 1 -.names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 +.names N_117_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D 11 1 -.names AS_030_i.BLIF RST_c.BLIF N_38_0 -11 1 -.names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 -11 1 -.names N_169_i.BLIF N_170_i.BLIF inst_AS_000_INT.D -11 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C -1 1 -.names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 -11 1 -.names N_167_i.BLIF N_168_i.BLIF inst_DSACK1_INT.D -11 1 -.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin -11 1 -.names N_246_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n -11 1 -.names N_80_i.BLIF N_82_i.BLIF N_201_1 -11 1 -.names BGACK_000_c.BLIF N_274_i.BLIF pos_clk_un6_bgack_000_0_n -11 1 -.names VMA_INT_i.BLIF VPA_D_i.BLIF N_201_2 -11 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_60_0 -11 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C -1 1 -.names N_201_1.BLIF N_201_2.BLIF N_201 -11 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +.names ahigh_c_31__n.BLIF ahigh_i_31__n 0 1 -.names BERR_c.BLIF N_201_i.BLIF N_131_i_1 -11 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_72_i -11 1 -.names N_131_i_1.BLIF N_202_i.BLIF N_131_i -11 1 -.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_80_i -11 1 -.names N_68_i.BLIF N_131.BLIF N_134_0_1 -11 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_82_i -11 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C +.names CLK_OSZI_c.BLIF cpu_est_2_.C 1 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i +.names N_80.BLIF N_194_i.BLIF N_115_i_1 +11 1 +.names ahigh_c_30__n.BLIF ahigh_i_30__n 0 1 -.names N_72_i.BLIF SM_AMIGA_6_.BLIF N_93_i +.names N_115_i_1.BLIF RST_c.BLIF SM_AMIGA_2_.D 11 1 -.names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT +.names ahigh_c_29__n.BLIF ahigh_i_29__n 0 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n +.names N_201_1_6.BLIF N_201_1_7.BLIF N_201_1_8 +11 1 +.names ahigh_c_28__n.BLIF ahigh_i_28__n 0 1 -.names AS_030_000_SYNC_i.BLIF CLK_000_D_4_.BLIF N_96_0_1 +.names N_201_1_8.BLIF N_201_1_5.BLIF N_201_1 11 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_98_i -11 1 -.names clk_000_d_i_3__n.BLIF nEXP_SPACE_c.BLIF N_96_0_2 -11 1 -.names N_107.BLIF N_203_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 +.names CLK_OSZI_c.BLIF cpu_est_3_.C 1 1 -.names N_96_0_1.BLIF N_96_0_2.BLIF N_96_0 +.names a_decode_c_19__n.BLIF a_decode_c_21__n.BLIF N_201_1_0 +11 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names a_decode_i_20__n.BLIF N_201_1.BLIF N_201_2 +11 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 +.names N_201_1_0.BLIF N_201_2.BLIF N_201 +11 1 +.names ahigh_c_24__n.BLIF ahigh_i_24__n +0 1 +.names AS_000_i.BLIF N_39_1_i.BLIF pos_clk_cycle_dma_5_1_1__n +11 1 +.names N_11_i.BLIF RST_c.BLIF N_29_0 +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C +1 1 +.names pos_clk_cycle_dma_5_1_1__n.BLIF G_91.BLIF CYCLE_DMA_1_.D +11 1 +.names N_204.BLIF as_030_000_sync_0_un3_n +0 1 +.names N_79_i.BLIF CYCLE_DMA_0_.BLIF N_176_1 +11 1 +.names inst_AS_030_000_SYNC.BLIF N_204.BLIF as_030_000_sync_0_un1_n +11 1 +.names N_176_1.BLIF cycle_dma_i_1__n.BLIF N_176 +11 1 +.names AS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names CLK_EXP_i.BLIF inst_CLK_OUT_PRE_D.BLIF AS_000_DMA_1_sqmuxa_1 +11 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_11 +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C +1 1 +.names AS_000_DMA_1_sqmuxa_1.BLIF N_72_i.BLIF AS_000_DMA_1_sqmuxa +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF N_198_1 +11 1 +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low +11 1 +.names N_198_1.BLIF RW_000_i.BLIF N_198 +11 1 +.names a_decode_c_20__n.BLIF a_decode_i_20__n +0 1 +.names AMIGA_DS_i.BLIF AS_000_i.BLIF N_72_i_1 +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +1 1 +.names N_198_i.BLIF pos_clk_un2_n.BLIF N_72_i_2 +11 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_150_2 +11 1 +.names N_191_i.BLIF SM_AMIGA_i_7_.BLIF N_98_i +11 1 +.names N_150_1.BLIF N_150_2.BLIF N_150 +11 1 +.names a_c_1__n.BLIF N_201_i.BLIF N_81_i +11 1 +.names N_80_i.BLIF N_82_i.BLIF N_126_1 +11 1 +.names N_98_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n +11 1 +.names CLK_OSZI_c.BLIF IPL_D0_0_.C +1 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_126_2 +11 1 +.names N_84.BLIF N_98_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +11 1 +.names N_126_1.BLIF N_126_2.BLIF N_126 +11 1 +.names AS_030_i.BLIF RST_c.BLIF N_40_0 +11 1 +.names AS_030_D0_i.BLIF a_decode_c_20__n.BLIF un8_ciin_1 +11 1 +.names BGACK_000_c.BLIF N_231_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names a_decode_c_21__n.BLIF N_201_1.BLIF un8_ciin_2 +11 1 +.names AS_000_c.BLIF N_79_i.BLIF N_231 +11 1 +.names CLK_OSZI_c.BLIF IPL_D0_1_.C +1 1 +.names un8_ciin_1.BLIF un8_ciin_2.BLIF un8_ciin +11 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names a_decode_c_22__n.BLIF a_decode_c_23__n.BLIF N_201_1_1 +11 1 +.names N_152_i.BLIF N_153_i.BLIF cpu_est_2_0_1__n +11 1 +.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF N_201_1_2 +11 1 +.names N_100.BLIF sm_amiga_i_i_7__n.BLIF N_190 +11 1 +.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF N_201_1_3 +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C +1 1 +.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF N_201_1_4 +11 1 +.names N_100.BLIF sm_amiga_i_6__n.BLIF N_214 +11 1 +.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF N_201_1_5 +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i +0 1 +.names N_201_1_1.BLIF N_201_1_2.BLIF N_201_1_6 +11 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_171 +11 1 +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D +1 1 +.names N_201_1_3.BLIF N_201_1_4.BLIF N_201_1_7 +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_107_0_1.BLIF SM_AMIGA_3_.BLIF N_107_0 +11 1 +.names AS_030_i.BLIF N_104.BLIF N_164 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_1_.C +1 1 +.names BERR_c.BLIF N_202_i.BLIF N_99_i_1 +11 1 +.names N_79_i.BLIF cpu_est_0_.BLIF N_163 +11 1 +.names N_99_i_1.BLIF N_219_i.BLIF N_99_i +11 1 +.names N_79.BLIF cpu_est_i_0__n.BLIF N_162 +11 1 +.names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names CLK_000_D_1_.BLIF CLK_000_D_2_.D +1 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF pos_clk_un10_sm_amiga_i_n +11 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_152 +11 1 +.names N_82_i.BLIF N_83_i.BLIF N_202_1 +11 1 +.names N_79.BLIF cpu_est_0_1__un3_n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_D_2_.C +1 1 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_202_2 +11 1 +.names cpu_est_1_.BLIF N_79.BLIF cpu_est_0_1__un1_n +11 1 +.names N_202_1.BLIF N_202_2.BLIF N_202 +11 1 +.names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names AS_030_i.BLIF a_decode_c_17__n.BLIF N_228_1 +11 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names a_decode_i_16__n.BLIF a_decode_i_18__n.BLIF N_228_2 +11 1 +.names DTACK_c_i.BLIF RST_c.BLIF N_45_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_3_.C +1 1 +.names fc_c_1__n.BLIF a_decode_i_19__n.BLIF N_228_3 +11 1 +.names RST_c.BLIF VPA_c_i.BLIF N_44_0 +11 1 +.names N_228_1.BLIF N_228_2.BLIF N_228_4 11 1 .names SM_AMIGA_4_.BLIF sm_amiga_i_4__n 0 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_282_0_1 +.names N_228_3.BLIF fc_c_0__n.BLIF N_228_5 11 1 -.names N_72_i.BLIF SM_AMIGA_4_.BLIF N_107_i +.names N_80_i.BLIF SM_AMIGA_4_.BLIF N_95_i 11 1 -.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_282_0_2 +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D +1 1 +.names N_228_4.BLIF N_228_5.BLIF N_228 11 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_128_i +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_96_i 11 1 +.names N_79_i.BLIF N_229.BLIF N_150_1 +11 1 +.names N_79_i.BLIF SM_AMIGA_1_.BLIF N_97_i +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_4_.C +1 1 +.names N_27_0.BLIF inst_VMA_INTreg.D +0 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index 4b3d549..e442429 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,94 +1,94 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Sat Dec 30 00:43:37 2017 +#$ DATE Thu Jan 11 20:16:29 2018 #$ MODULE bus68030 -#$ PINS 75 AHIGH_27_ AHIGH_26_ SIZE_1_ AHIGH_25_ AHIGH_24_ AHIGH_31_ A_DECODE_22_ \ -# A_DECODE_21_ A_DECODE_23_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ \ -# IPL_030_2_ A_DECODE_16_ A_DECODE_15_ IPL_2_ A_DECODE_14_ A_DECODE_13_ FC_1_ \ -# A_DECODE_12_ AS_030 A_DECODE_11_ AS_000 A_DECODE_10_ RW_000 A_DECODE_9_ DS_030 \ -# A_DECODE_8_ UDS_000 A_DECODE_7_ LDS_000 A_DECODE_6_ nEXP_SPACE A_DECODE_5_ BERR \ -# A_DECODE_4_ BG_030 A_DECODE_3_ BG_000 A_DECODE_2_ BGACK_030 A_0_ BGACK_000 IPL_030_1_ \ -# CLK_030 IPL_030_0_ CLK_000 IPL_1_ CLK_OSZI IPL_0_ CLK_DIV_OUT FC_0_ CLK_EXP A_1_ FPU_CS \ -# FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR \ -# AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ \ -# AHIGH_28_ -#$ NODES 508 N_23_0 UDS_000_c N_19_i N_22_0 LDS_000_c N_18_i N_21_0 size_c_0__n \ -# ipl_c_i_2__n N_43_0 size_c_1__n ipl_c_i_1__n inst_BGACK_030_INTreg N_42_0 vcc_n_n \ -# ahigh_c_24__n ipl_c_i_0__n un5_e N_41_0 gnd_n_n ahigh_c_25__n DTACK_c_i \ -# un1_amiga_bus_enable_low N_45_0 un3_as_030 ahigh_c_26__n VPA_c_i un1_UDS_000_INT \ -# N_44_0 un1_LDS_000_INT ahigh_c_27__n N_13_i un1_DS_000_ENABLE_0_sqmuxa N_27_0 \ -# un10_ciin ahigh_c_28__n LDS_000_INT_i un21_fpu_cs un1_LDS_000_INT_0 un21_berr \ -# ahigh_c_29__n UDS_000_INT_i un2_ds_030 un1_UDS_000_INT_0 cpu_est_0_ ahigh_c_30__n \ -# N_96_0_1 cpu_est_1_ N_96_0_2 cpu_est_2_ ahigh_c_31__n N_282_0_1 cpu_est_3_ N_282_0_2 \ -# inst_AMIGA_BUS_ENABLE_DMA_HIGH N_282_0_3 inst_AMIGA_BUS_ENABLE_DMA_LOW N_282_0_4 \ -# inst_AS_030_D0 pos_clk_un10_sm_amiga_i_1_n inst_AS_030_D1 un10_ciin_1 \ -# inst_AS_030_000_SYNC un10_ciin_2 inst_AS_000_DMA un10_ciin_3 inst_DS_000_DMA \ -# un10_ciin_4 inst_VMA_INTreg un10_ciin_5 inst_VPA_D un10_ciin_6 CLK_000_D_3_ \ -# un10_ciin_7 inst_DTACK_D0 un10_ciin_8 inst_AMIGA_DS un10_ciin_9 CLK_000_D_1_ \ -# un10_ciin_10 CLK_000_D_0_ un10_ciin_11 inst_CLK_OUT_PRE_50 N_201_1 \ -# inst_CLK_OUT_PRE_D N_201_2 IPL_D0_0_ N_131_i_1 IPL_D0_1_ N_134_0_1 IPL_D0_2_ \ -# N_113_i_1 CLK_000_D_2_ N_113_i_2 CLK_000_D_4_ N_144_1 pos_clk_ipl_n N_144_2 \ -# SIZE_DMA_0_ N_143_1 SIZE_DMA_1_ N_143_2 inst_A0_DMA N_163_1 inst_RW_000_DMA N_163_2 \ -# inst_UDS_000_INT N_163_3 inst_DS_000_ENABLE un21_fpu_cs_1 inst_LDS_000_INT \ -# a_decode_c_16__n un21_berr_1_0 inst_BGACK_030_INT_D pos_clk_cycle_dma_5_1_1__n \ -# SM_AMIGA_6_ a_decode_c_17__n N_199_1 inst_RW_000_INT AS_000_DMA_1_sqmuxa_1 \ -# SM_AMIGA_4_ a_decode_c_18__n N_140_1 SM_AMIGA_1_ N_66_i_1 SM_AMIGA_0_ \ -# a_decode_c_19__n N_66_i_2 CYCLE_DMA_0_ N_205_i_1 CYCLE_DMA_1_ a_decode_c_20__n \ -# N_205_i_2 inst_DSACK1_INT N_180_1 inst_AS_000_INT a_decode_c_21__n N_180_2 \ -# pos_clk_un9_clk_000_pe_n N_59_i_1 SM_AMIGA_5_ a_decode_c_22__n N_127_i_1 \ -# SM_AMIGA_3_ N_123_i_1 SM_AMIGA_2_ a_decode_c_23__n N_121_i_1 N_119_i_1 N_6 a_c_0__n \ -# N_117_i_1 N_115_i_1 a_c_1__n N_111_i_1 N_165_1 N_13 nEXP_SPACE_c N_162_1 N_148_1 N_18 \ -# BERR_c pos_clk_ipl_1_n N_19 ds_000_dma_0_un3_n N_20 BG_030_c ds_000_dma_0_un1_n \ -# ds_000_dma_0_un0_n BG_000DFFreg as_000_dma_0_un3_n as_000_dma_0_un1_n \ -# as_000_dma_0_un0_n BGACK_000_c uds_000_int_0_un3_n uds_000_int_0_un1_n \ -# uds_000_int_0_un0_n bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n CLK_OSZI_c \ -# lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n CLK_OUT_INTreg \ -# as_030_d1_0_un3_n as_030_d1_0_un1_n as_030_d1_0_un0_n FPU_SENSE_c \ -# rw_000_int_0_un3_n rw_000_int_0_un1_n IPL_030DFF_0_reg rw_000_int_0_un0_n \ -# as_030_000_sync_0_un3_n IPL_030DFF_1_reg as_030_000_sync_0_un1_n SM_AMIGA_i_7_ \ -# as_030_000_sync_0_un0_n IPL_030DFF_2_reg bgack_030_int_0_un3_n \ -# bgack_030_int_0_un1_n cpu_est_2_1__n ipl_c_0__n bgack_030_int_0_un0_n \ -# cpu_est_2_2__n cpu_est_0_1__un3_n cpu_est_2_3__n ipl_c_1__n cpu_est_0_1__un1_n \ -# G_105 cpu_est_0_1__un0_n G_106 ipl_c_2__n cpu_est_0_2__un3_n G_107 \ -# cpu_est_0_2__un1_n N_60 cpu_est_0_2__un0_n N_63 DTACK_c cpu_est_0_3__un3_n N_126 \ -# cpu_est_0_3__un1_n N_150 cpu_est_0_3__un0_n N_151 ipl_030_0_0__un3_n N_219 VPA_c \ -# ipl_030_0_0__un1_n N_175 ipl_030_0_0__un0_n ipl_030_0_1__un3_n N_59 RST_c \ -# ipl_030_0_1__un1_n N_68 ipl_030_0_1__un0_n N_72 ipl_030_0_2__un3_n N_80 \ -# ipl_030_0_2__un1_n N_93 RW_c ipl_030_0_2__un0_n N_98 ds_000_enable_0_un3_n N_107 \ -# fc_c_0__n ds_000_enable_0_un1_n N_128 ds_000_enable_0_un0_n N_131 fc_c_1__n \ -# vma_int_0_un3_n N_134 vma_int_0_un1_n N_135 vma_int_0_un0_n N_141 \ -# AMIGA_BUS_DATA_DIR_c a_decode_15__n N_142 N_143 a_decode_14__n N_144 N_145 \ -# a_decode_13__n N_146 N_205_i N_147 N_140_i a_decode_12__n N_148 AMIGA_DS_i N_149 \ -# a_decode_11__n N_154 N_199_i N_155 N_198_i a_decode_10__n N_162 N_180_i N_165 N_262_i \ -# a_decode_9__n N_259 AMIGA_BUS_DATA_DIR_c_0 N_260 pos_clk_un2_i_n a_decode_8__n N_181 \ -# N_3_i N_182 N_32_0 a_decode_7__n N_183 N_4_i N_184 N_31_0 a_decode_6__n N_185 N_220_i \ -# N_186 BG_030_c_i a_decode_5__n N_266 pos_clk_un9_bg_030_0_n N_267 N_17_i \ -# a_decode_4__n N_268 N_24_0 N_190 N_16_i a_decode_3__n N_191 N_25_0 N_201 N_15_i \ -# a_decode_2__n N_202 N_26_0 N_203 N_12_i N_208 N_28_0 N_163 N_11_i N_282 N_29_0 \ -# un21_berr_1 N_5_i N_132 N_30_0 N_96 a_c_i_0__n N_129 size_c_i_1__n \ -# un1_SM_AMIGA_0_sqmuxa_1 pos_clk_un10_sm_amiga_i_n N_169 un1_dsack1_i N_170 N_69_i \ -# N_167 N_163_i N_168 N_244_0 pos_clk_rw_000_int_5_n N_164_i pos_clk_un6_bgack_000_n \ -# N_165_i N_274 un11_amiga_bus_enable_high_i N_164 un10_ciin_i N_244 N_60_0 N_5 N_274_i \ -# N_11 pos_clk_un6_bgack_000_0_n N_12 RW_c_i N_15 pos_clk_rw_000_int_5_0_n N_16 N_168_i \ -# N_17 N_167_i pos_clk_un9_bg_030_n G_91 N_170_i N_3 N_169_i N_205 AS_000_DMA_1_sqmuxa \ -# N_38_0 N_4 un1_SM_AMIGA_0_sqmuxa_1_0 N_199 N_282_0 pos_clk_un2_n clk_000_d_i_3__n \ -# N_140 N_96_0 N_262 N_129_i N_198 N_268_i N_180 N_246_i un1_amiga_bus_enable_low_i \ -# N_132_0 un21_fpu_cs_i AS_000_i N_142_i BGACK_030_INT_i N_141_i nEXP_SPACE_i N_135_0 \ -# cycle_dma_i_0__n N_134_0 RW_000_i N_131_i CLK_EXP_i LDS_000_c_i cycle_dma_i_1__n \ -# UDS_000_c_i DS_000_DMA_i N_128_i AS_000_DMA_i N_107_i a_i_1__n N_203_i \ -# AMIGA_BUS_ENABLE_DMA_LOW_i un1_DS_000_ENABLE_0_sqmuxa_0 a_decode_i_19__n N_201_i \ -# a_decode_i_18__n N_202_i a_decode_i_16__n VMA_INT_i AMIGA_BUS_ENABLE_DMA_HIGH_i \ -# N_98_i sm_amiga_i_0__n N_93_i sm_amiga_i_5__n N_82_i sm_amiga_i_6__n N_80_i \ -# sm_amiga_i_i_7__n N_72_i AS_030_i N_68_i AS_000_INT_i N_59_i DSACK1_INT_i N_190_i \ -# sm_amiga_i_1__n N_191_i FPU_SENSE_i AS_030_D1_i N_267_i cpu_est_i_0__n \ -# cpu_est_i_3__n N_266_i VPA_D_i sm_amiga_i_3__n N_186_i sm_amiga_i_4__n \ -# cpu_est_i_1__n N_185_i clk_000_d_i_0__n clk_000_d_i_1__n N_183_i AS_030_D0_i N_184_i \ -# cpu_est_i_2__n DTACK_D0_i N_182_i sm_amiga_i_2__n AS_030_000_SYNC_i N_181_i \ -# ahigh_i_30__n ahigh_i_31__n N_260_i ahigh_i_28__n pos_clk_size_dma_6_0_1__n \ -# ahigh_i_29__n N_259_i ahigh_i_26__n pos_clk_size_dma_6_0_0__n ahigh_i_27__n N_63_0 \ -# ahigh_i_24__n N_155_i ahigh_i_25__n N_162_i N_187_i un5_e_0 N_188_i N_154_i N_189_i \ -# cpu_est_2_0_3__n N_149_i N_208_i cpu_est_2_0_2__n N_147_i un2_ds_030_i N_148_i \ -# N_219_i cpu_est_2_0_1__n N_175_i N_146_i un3_as_030_i N_36_0 AS_030_c N_145_i N_35_0 \ -# AS_000_c N_143_i N_144_i RW_000_c pos_clk_un9_clk_000_pe_0_n N_20_i +#$ PINS 75 SIZE_1_ SIZE_0_ AHIGH_30_ AHIGH_31_ AHIGH_29_ AHIGH_28_ A_DECODE_23_ \ +# AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ IPL_030_2_ A_DECODE_22_ A_DECODE_21_ IPL_2_ \ +# A_DECODE_20_ A_DECODE_19_ FC_1_ A_DECODE_18_ AS_030 A_DECODE_17_ AS_000 A_DECODE_16_ \ +# RW_000 A_DECODE_15_ DS_030 A_DECODE_14_ UDS_000 A_DECODE_13_ LDS_000 A_DECODE_12_ \ +# nEXP_SPACE A_DECODE_11_ BERR A_DECODE_10_ BG_030 A_DECODE_9_ BG_000 A_DECODE_8_ \ +# BGACK_030 A_DECODE_7_ BGACK_000 A_DECODE_6_ CLK_030 A_DECODE_5_ CLK_000 A_DECODE_4_ \ +# CLK_OSZI A_DECODE_3_ CLK_DIV_OUT A_DECODE_2_ CLK_EXP A_0_ FPU_CS IPL_030_1_ FPU_SENSE \ +# IPL_030_0_ DSACK1 IPL_1_ DTACK IPL_0_ AVEC FC_0_ E A_1_ VPA VMA RST RESET RW \ +# AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH \ +# CIIN +#$ NODES 514 N_157_i UDS_000_c cpu_est_2_0_3__n N_156_i LDS_000_c N_229_i \ +# cpu_est_2_0_2__n size_c_0__n N_126_i N_150_i size_c_1__n pos_clk_un9_clk_000_pe_0_n \ +# inst_BGACK_030_INTreg N_20_i vcc_n_n ahigh_c_24__n N_23_0 un5_e N_19_i gnd_n_n \ +# ahigh_c_25__n N_22_0 un1_amiga_bus_enable_low N_18_i un3_as_030 ahigh_c_26__n N_21_0 \ +# un1_UDS_000_INT ipl_c_i_2__n un1_LDS_000_INT ahigh_c_27__n N_43_0 \ +# un1_DS_000_ENABLE_0_sqmuxa ipl_c_i_1__n un21_fpu_cs ahigh_c_28__n N_42_0 un21_berr \ +# ipl_c_i_0__n un8_ciin ahigh_c_29__n N_41_0 un2_ds_030 N_13_i cpu_est_0_ ahigh_c_30__n \ +# N_27_0 cpu_est_1_ LDS_000_INT_i cpu_est_2_ ahigh_c_31__n un1_LDS_000_INT_0 \ +# cpu_est_3_ UDS_000_INT_i inst_AMIGA_BUS_ENABLE_DMA_HIGH un1_UDS_000_INT_0 \ +# inst_AMIGA_BUS_ENABLE_DMA_LOW N_104_0_1 inst_AS_030_D0 N_104_0_2 inst_AS_030_D1 \ +# N_100_0_1 inst_AS_030_000_SYNC N_100_0_2 inst_AS_000_DMA N_113_i_1 inst_DS_000_DMA \ +# N_113_i_2 inst_VMA_INTreg N_107_0_1 inst_VPA_D N_99_i_1 CLK_000_D_3_ \ +# pos_clk_un10_sm_amiga_i_1_n inst_DTACK_D0 N_202_1 inst_AMIGA_DS N_202_2 \ +# CLK_000_D_1_ N_228_1 CLK_000_D_0_ N_228_2 inst_CLK_OUT_PRE_50 N_228_3 \ +# inst_CLK_OUT_PRE_D N_228_4 IPL_D0_0_ N_228_5 IPL_D0_1_ N_150_1 IPL_D0_2_ N_150_2 \ +# CLK_000_D_2_ N_126_1 CLK_000_D_4_ N_126_2 pos_clk_ipl_n un8_ciin_1 SIZE_DMA_0_ \ +# un8_ciin_2 SIZE_DMA_1_ N_201_1_1 inst_A0_DMA N_201_1_2 inst_RW_000_DMA N_201_1_3 \ +# inst_UDS_000_INT N_201_1_4 inst_DS_000_ENABLE N_201_1_5 inst_LDS_000_INT \ +# a_decode_c_16__n N_201_1_6 inst_BGACK_030_INT_D N_201_1_7 SM_AMIGA_6_ \ +# a_decode_c_17__n N_201_1_8 inst_RW_000_INT N_201_1_0 SM_AMIGA_4_ a_decode_c_18__n \ +# N_201_2 SM_AMIGA_1_ pos_clk_cycle_dma_5_1_1__n SM_AMIGA_0_ a_decode_c_19__n N_176_1 \ +# CYCLE_DMA_0_ AS_000_DMA_1_sqmuxa_1 CYCLE_DMA_1_ a_decode_c_20__n N_198_1 \ +# inst_DSACK1_INT N_72_i_1 inst_AS_000_INT a_decode_c_21__n N_72_i_2 \ +# pos_clk_un9_clk_000_pe_n N_206_i_1 SM_AMIGA_5_ a_decode_c_22__n N_206_i_2 \ +# SM_AMIGA_3_ N_186_1 SM_AMIGA_2_ a_decode_c_23__n N_186_2 N_74_i_1 N_6 a_c_0__n \ +# N_121_i_1 N_117_i_1 a_c_1__n N_115_i_1 N_127_i_1 N_13 nEXP_SPACE_c N_123_i_1 N_119_i_1 \ +# N_18 BERR_c N_111_i_1 N_19 un21_berr_1 N_20 BG_030_c un21_fpu_cs_1 N_172_1 BG_000DFFreg \ +# N_161_1 N_153_1 pos_clk_ipl_1_n BGACK_000_c ds_000_dma_0_un3_n ds_000_dma_0_un1_n \ +# ds_000_dma_0_un0_n as_000_dma_0_un3_n as_000_dma_0_un1_n as_000_dma_0_un0_n \ +# CLK_OSZI_c uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n \ +# CLK_OUT_INTreg bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n FPU_SENSE_c \ +# lds_000_int_0_un3_n lds_000_int_0_un1_n IPL_030DFF_0_reg lds_000_int_0_un0_n \ +# rw_000_int_0_un3_n IPL_030DFF_1_reg rw_000_int_0_un1_n rw_000_int_0_un0_n \ +# SM_AMIGA_i_7_ IPL_030DFF_2_reg bgack_030_int_0_un3_n bgack_030_int_0_un1_n \ +# ipl_c_0__n bgack_030_int_0_un0_n cpu_est_2_2__n as_030_000_sync_0_un3_n \ +# cpu_est_2_3__n ipl_c_1__n as_030_000_sync_0_un1_n G_105 as_030_000_sync_0_un0_n \ +# G_106 ipl_c_2__n cpu_est_0_1__un3_n G_107 cpu_est_0_1__un1_n cpu_est_0_1__un0_n \ +# N_205 DTACK_c cpu_est_0_2__un3_n N_74 cpu_est_0_2__un1_n N_78 cpu_est_0_2__un0_n N_79 \ +# cpu_est_0_3__un3_n N_80 VPA_c cpu_est_0_3__un1_n N_83 cpu_est_0_3__un0_n N_84 \ +# ipl_030_0_0__un3_n N_89 RST_c ipl_030_0_0__un1_n N_95 ipl_030_0_0__un0_n N_96 \ +# ipl_030_0_1__un3_n N_97 ipl_030_0_1__un1_n N_105 RW_c ipl_030_0_1__un0_n N_126 \ +# ipl_030_0_2__un3_n N_150 fc_c_0__n ipl_030_0_2__un1_n N_153 ipl_030_0_2__un0_n N_156 \ +# fc_c_1__n ds_000_enable_0_un3_n N_157 ds_000_enable_0_un1_n N_158 \ +# ds_000_enable_0_un0_n N_159 AMIGA_BUS_DATA_DIR_c vma_int_0_un3_n N_160 \ +# vma_int_0_un1_n N_161 vma_int_0_un0_n N_172 as_030_d1_0_un3_n N_177 \ +# as_030_d1_0_un1_n N_178 N_181_i as_030_d1_0_un0_n N_179 N_37_0 a_decode_15__n N_180 \ +# N_182 N_176_i a_decode_14__n N_183 N_175_i N_184 N_72_i a_decode_13__n N_212 N_198_i \ +# N_213 AMIGA_DS_i a_decode_12__n N_214 N_186_i N_190 N_185_i a_decode_11__n N_191 \ +# AMIGA_BUS_DATA_DIR_c_0 N_194 pos_clk_un2_i_n a_decode_10__n N_195 N_3_i N_196 N_32_0 \ +# a_decode_9__n N_197 N_4_i N_202 N_31_0 a_decode_8__n N_220 N_39_1_i N_224 N_34_0 \ +# a_decode_7__n N_225 BG_030_c_i N_228 pos_clk_un9_bg_030_0_n a_decode_6__n N_229 \ +# N_17_i N_201_1 N_24_0 a_decode_5__n N_104 N_16_i N_100 N_25_0 a_decode_4__n N_171 N_15_i \ +# N_204 N_26_0 a_decode_3__n N_164 N_12_i N_162 N_28_0 a_decode_2__n N_163 N_5_i \ +# cpu_est_2_1__n N_30_0 N_152 a_c_i_0__n N_11 size_c_i_1__n N_201 \ +# pos_clk_un10_sm_amiga_i_n N_193 N_231_i N_192 pos_clk_un6_bgack_000_0_n N_107 N_40_0 \ +# N_99 un1_SM_AMIGA_0_sqmuxa_1_0 N_219 RW_c_i N_81 pos_clk_rw_000_int_5_0_n \ +# pos_clk_rw_000_int_5_n N_201_i un1_SM_AMIGA_0_sqmuxa_1 N_81_i \ +# pos_clk_un6_bgack_000_n N_219_i N_231 N_202_i N_5 N_191_i N_12 N_98_i N_15 N_99_i N_16 \ +# N_107_0 N_17 N_192_i pos_clk_un9_bg_030_n N_193_i N_3 N_72 N_11_i AS_000_DMA_1_sqmuxa \ +# N_29_0 N_4 VPA_c_i G_91 N_44_0 N_176 DTACK_c_i pos_clk_un2_n N_45_0 N_175 N_152_i N_185 \ +# N_153_i N_198 cpu_est_2_0_1__n N_186 N_163_i N_181 N_162_i un1_amiga_bus_enable_low_i \ +# un21_fpu_cs_i N_203_i AS_000_i un1_dsack1_i BGACK_030_INT_i N_164_i nEXP_SPACE_i \ +# N_228_i RW_000_i N_204_0 cycle_dma_i_0__n N_171_i CLK_EXP_i N_172_i cycle_dma_i_1__n \ +# un11_amiga_bus_enable_high_i DS_000_DMA_i N_85_0 AS_000_DMA_i clk_000_d_i_3__n \ +# ahigh_i_25__n N_100_0 ahigh_i_24__n AS_030_D1_i ahigh_i_27__n N_104_0 ahigh_i_26__n \ +# N_105_0 ahigh_i_29__n N_97_i ahigh_i_28__n LDS_000_c_i ahigh_i_31__n UDS_000_c_i \ +# ahigh_i_30__n N_96_i sm_amiga_i_2__n N_95_i sm_amiga_i_1__n N_220_i DTACK_D0_i \ +# un1_DS_000_ENABLE_0_sqmuxa_0 sm_amiga_i_i_7__n VMA_INT_i sm_amiga_i_3__n N_89_i \ +# a_decode_i_20__n N_84_i AMIGA_BUS_ENABLE_DMA_LOW_i N_83_i cpu_est_i_0__n N_82_i \ +# AS_030_i N_80_i AMIGA_BUS_ENABLE_DMA_HIGH_i N_79_i sm_amiga_i_6__n N_78_0 \ +# AS_030_D0_i N_74_i cpu_est_i_3__n N_197_i VPA_D_i sm_amiga_i_5__n N_195_i \ +# sm_amiga_i_4__n N_196_i cpu_est_i_1__n clk_000_d_i_0__n N_194_i clk_000_d_i_1__n \ +# cpu_est_i_2__n N_190_i DSACK1_INT_i AS_000_INT_i N_214_i a_decode_i_16__n \ +# a_decode_i_19__n N_184_i a_decode_i_18__n pos_clk_size_dma_6_0_1__n FPU_SENSE_i \ +# N_183_i AS_030_000_SYNC_i pos_clk_size_dma_6_0_0__n sm_amiga_i_0__n N_182_i N_187_i \ +# N_38_0 N_188_i N_179_i N_189_i N_180_i N_177_i N_178_i un2_ds_030_i N_225_i un8_ciin_i \ +# N_224_i N_205_0 un3_as_030_i N_160_i AS_030_c N_161_i un5_e_0 AS_000_c N_159_i RW_000_c \ +# N_158_i .model bus68030 .inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF DTACK.BLIF VPA.BLIF \ @@ -101,238 +101,249 @@ A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF A_1_.BLIF \ SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF \ LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF \ AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF \ -A_0_.BLIF N_23_0.BLIF UDS_000_c.BLIF N_19_i.BLIF N_22_0.BLIF LDS_000_c.BLIF \ -N_18_i.BLIF N_21_0.BLIF size_c_0__n.BLIF ipl_c_i_2__n.BLIF N_43_0.BLIF \ -size_c_1__n.BLIF ipl_c_i_1__n.BLIF inst_BGACK_030_INTreg.BLIF N_42_0.BLIF \ -vcc_n_n.BLIF ahigh_c_24__n.BLIF ipl_c_i_0__n.BLIF un5_e.BLIF N_41_0.BLIF \ -gnd_n_n.BLIF ahigh_c_25__n.BLIF DTACK_c_i.BLIF un1_amiga_bus_enable_low.BLIF \ -N_45_0.BLIF un3_as_030.BLIF ahigh_c_26__n.BLIF VPA_c_i.BLIF \ -un1_UDS_000_INT.BLIF N_44_0.BLIF un1_LDS_000_INT.BLIF ahigh_c_27__n.BLIF \ -N_13_i.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF N_27_0.BLIF un10_ciin.BLIF \ -ahigh_c_28__n.BLIF LDS_000_INT_i.BLIF un21_fpu_cs.BLIF un1_LDS_000_INT_0.BLIF \ -un21_berr.BLIF ahigh_c_29__n.BLIF UDS_000_INT_i.BLIF un2_ds_030.BLIF \ -un1_UDS_000_INT_0.BLIF cpu_est_0_.BLIF ahigh_c_30__n.BLIF N_96_0_1.BLIF \ -cpu_est_1_.BLIF N_96_0_2.BLIF cpu_est_2_.BLIF ahigh_c_31__n.BLIF \ -N_282_0_1.BLIF cpu_est_3_.BLIF N_282_0_2.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_282_0_3.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_282_0_4.BLIF inst_AS_030_D0.BLIF \ -pos_clk_un10_sm_amiga_i_1_n.BLIF inst_AS_030_D1.BLIF un10_ciin_1.BLIF \ -inst_AS_030_000_SYNC.BLIF un10_ciin_2.BLIF inst_AS_000_DMA.BLIF \ -un10_ciin_3.BLIF inst_DS_000_DMA.BLIF un10_ciin_4.BLIF inst_VMA_INTreg.BLIF \ -un10_ciin_5.BLIF inst_VPA_D.BLIF un10_ciin_6.BLIF CLK_000_D_3_.BLIF \ -un10_ciin_7.BLIF inst_DTACK_D0.BLIF un10_ciin_8.BLIF inst_AMIGA_DS.BLIF \ -un10_ciin_9.BLIF CLK_000_D_1_.BLIF un10_ciin_10.BLIF CLK_000_D_0_.BLIF \ -un10_ciin_11.BLIF inst_CLK_OUT_PRE_50.BLIF N_201_1.BLIF \ -inst_CLK_OUT_PRE_D.BLIF N_201_2.BLIF IPL_D0_0_.BLIF N_131_i_1.BLIF \ -IPL_D0_1_.BLIF N_134_0_1.BLIF IPL_D0_2_.BLIF N_113_i_1.BLIF CLK_000_D_2_.BLIF \ -N_113_i_2.BLIF CLK_000_D_4_.BLIF N_144_1.BLIF pos_clk_ipl_n.BLIF N_144_2.BLIF \ -SIZE_DMA_0_.BLIF N_143_1.BLIF SIZE_DMA_1_.BLIF N_143_2.BLIF inst_A0_DMA.BLIF \ -N_163_1.BLIF inst_RW_000_DMA.BLIF N_163_2.BLIF inst_UDS_000_INT.BLIF \ -N_163_3.BLIF inst_DS_000_ENABLE.BLIF un21_fpu_cs_1.BLIF inst_LDS_000_INT.BLIF \ -a_decode_c_16__n.BLIF un21_berr_1_0.BLIF inst_BGACK_030_INT_D.BLIF \ -pos_clk_cycle_dma_5_1_1__n.BLIF SM_AMIGA_6_.BLIF a_decode_c_17__n.BLIF \ -N_199_1.BLIF inst_RW_000_INT.BLIF AS_000_DMA_1_sqmuxa_1.BLIF SM_AMIGA_4_.BLIF \ -a_decode_c_18__n.BLIF N_140_1.BLIF SM_AMIGA_1_.BLIF N_66_i_1.BLIF \ -SM_AMIGA_0_.BLIF a_decode_c_19__n.BLIF N_66_i_2.BLIF CYCLE_DMA_0_.BLIF \ -N_205_i_1.BLIF CYCLE_DMA_1_.BLIF a_decode_c_20__n.BLIF N_205_i_2.BLIF \ -inst_DSACK1_INT.BLIF N_180_1.BLIF inst_AS_000_INT.BLIF a_decode_c_21__n.BLIF \ -N_180_2.BLIF pos_clk_un9_clk_000_pe_n.BLIF N_59_i_1.BLIF SM_AMIGA_5_.BLIF \ -a_decode_c_22__n.BLIF N_127_i_1.BLIF SM_AMIGA_3_.BLIF N_123_i_1.BLIF \ -SM_AMIGA_2_.BLIF a_decode_c_23__n.BLIF N_121_i_1.BLIF N_119_i_1.BLIF N_6.BLIF \ -a_c_0__n.BLIF N_117_i_1.BLIF N_115_i_1.BLIF a_c_1__n.BLIF N_111_i_1.BLIF \ -N_165_1.BLIF N_13.BLIF nEXP_SPACE_c.BLIF N_162_1.BLIF N_148_1.BLIF N_18.BLIF \ -BERR_c.BLIF pos_clk_ipl_1_n.BLIF N_19.BLIF ds_000_dma_0_un3_n.BLIF N_20.BLIF \ -BG_030_c.BLIF ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF \ -BG_000DFFreg.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un1_n.BLIF \ -as_000_dma_0_un0_n.BLIF BGACK_000_c.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF bg_000_0_un3_n.BLIF \ -bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF CLK_OSZI_c.BLIF \ -lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF \ -CLK_OUT_INTreg.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un1_n.BLIF \ -as_030_d1_0_un0_n.BLIF FPU_SENSE_c.BLIF rw_000_int_0_un3_n.BLIF \ -rw_000_int_0_un1_n.BLIF IPL_030DFF_0_reg.BLIF rw_000_int_0_un0_n.BLIF \ -as_030_000_sync_0_un3_n.BLIF IPL_030DFF_1_reg.BLIF \ -as_030_000_sync_0_un1_n.BLIF SM_AMIGA_i_7_.BLIF as_030_000_sync_0_un0_n.BLIF \ -IPL_030DFF_2_reg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un1_n.BLIF \ -cpu_est_2_1__n.BLIF ipl_c_0__n.BLIF bgack_030_int_0_un0_n.BLIF \ -cpu_est_2_2__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_2_3__n.BLIF \ -ipl_c_1__n.BLIF cpu_est_0_1__un1_n.BLIF G_105.BLIF cpu_est_0_1__un0_n.BLIF \ -G_106.BLIF ipl_c_2__n.BLIF cpu_est_0_2__un3_n.BLIF G_107.BLIF \ -cpu_est_0_2__un1_n.BLIF N_60.BLIF cpu_est_0_2__un0_n.BLIF N_63.BLIF \ -DTACK_c.BLIF cpu_est_0_3__un3_n.BLIF N_126.BLIF cpu_est_0_3__un1_n.BLIF \ -N_150.BLIF cpu_est_0_3__un0_n.BLIF N_151.BLIF ipl_030_0_0__un3_n.BLIF \ -N_219.BLIF VPA_c.BLIF ipl_030_0_0__un1_n.BLIF N_175.BLIF \ -ipl_030_0_0__un0_n.BLIF ipl_030_0_1__un3_n.BLIF N_59.BLIF RST_c.BLIF \ -ipl_030_0_1__un1_n.BLIF N_68.BLIF ipl_030_0_1__un0_n.BLIF N_72.BLIF \ -ipl_030_0_2__un3_n.BLIF N_80.BLIF ipl_030_0_2__un1_n.BLIF N_93.BLIF RW_c.BLIF \ -ipl_030_0_2__un0_n.BLIF N_98.BLIF ds_000_enable_0_un3_n.BLIF N_107.BLIF \ -fc_c_0__n.BLIF ds_000_enable_0_un1_n.BLIF N_128.BLIF \ -ds_000_enable_0_un0_n.BLIF N_131.BLIF fc_c_1__n.BLIF vma_int_0_un3_n.BLIF \ -N_134.BLIF vma_int_0_un1_n.BLIF N_135.BLIF vma_int_0_un0_n.BLIF N_141.BLIF \ -AMIGA_BUS_DATA_DIR_c.BLIF a_decode_15__n.BLIF N_142.BLIF N_143.BLIF \ -a_decode_14__n.BLIF N_144.BLIF N_145.BLIF a_decode_13__n.BLIF N_146.BLIF \ -N_205_i.BLIF N_147.BLIF N_140_i.BLIF a_decode_12__n.BLIF N_148.BLIF \ -AMIGA_DS_i.BLIF N_149.BLIF a_decode_11__n.BLIF N_154.BLIF N_199_i.BLIF \ -N_155.BLIF N_198_i.BLIF a_decode_10__n.BLIF N_162.BLIF N_180_i.BLIF N_165.BLIF \ -N_262_i.BLIF a_decode_9__n.BLIF N_259.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF \ -N_260.BLIF pos_clk_un2_i_n.BLIF a_decode_8__n.BLIF N_181.BLIF N_3_i.BLIF \ -N_182.BLIF N_32_0.BLIF a_decode_7__n.BLIF N_183.BLIF N_4_i.BLIF N_184.BLIF \ -N_31_0.BLIF a_decode_6__n.BLIF N_185.BLIF N_220_i.BLIF N_186.BLIF \ -BG_030_c_i.BLIF a_decode_5__n.BLIF N_266.BLIF pos_clk_un9_bg_030_0_n.BLIF \ -N_267.BLIF N_17_i.BLIF a_decode_4__n.BLIF N_268.BLIF N_24_0.BLIF N_190.BLIF \ -N_16_i.BLIF a_decode_3__n.BLIF N_191.BLIF N_25_0.BLIF N_201.BLIF N_15_i.BLIF \ -a_decode_2__n.BLIF N_202.BLIF N_26_0.BLIF N_203.BLIF N_12_i.BLIF N_208.BLIF \ -N_28_0.BLIF N_163.BLIF N_11_i.BLIF N_282.BLIF N_29_0.BLIF un21_berr_1.BLIF \ -N_5_i.BLIF N_132.BLIF N_30_0.BLIF N_96.BLIF a_c_i_0__n.BLIF N_129.BLIF \ -size_c_i_1__n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF pos_clk_un10_sm_amiga_i_n.BLIF \ -N_169.BLIF un1_dsack1_i.BLIF N_170.BLIF N_69_i.BLIF N_167.BLIF N_163_i.BLIF \ -N_168.BLIF N_244_0.BLIF pos_clk_rw_000_int_5_n.BLIF N_164_i.BLIF \ -pos_clk_un6_bgack_000_n.BLIF N_165_i.BLIF N_274.BLIF \ -un11_amiga_bus_enable_high_i.BLIF N_164.BLIF un10_ciin_i.BLIF N_244.BLIF \ -N_60_0.BLIF N_5.BLIF N_274_i.BLIF N_11.BLIF pos_clk_un6_bgack_000_0_n.BLIF \ -N_12.BLIF RW_c_i.BLIF N_15.BLIF pos_clk_rw_000_int_5_0_n.BLIF N_16.BLIF \ -N_168_i.BLIF N_17.BLIF N_167_i.BLIF pos_clk_un9_bg_030_n.BLIF G_91.BLIF \ -N_170_i.BLIF N_3.BLIF N_169_i.BLIF N_205.BLIF AS_000_DMA_1_sqmuxa.BLIF \ -N_38_0.BLIF N_4.BLIF un1_SM_AMIGA_0_sqmuxa_1_0.BLIF N_199.BLIF N_282_0.BLIF \ -pos_clk_un2_n.BLIF clk_000_d_i_3__n.BLIF N_140.BLIF N_96_0.BLIF N_262.BLIF \ -N_129_i.BLIF N_198.BLIF N_268_i.BLIF N_180.BLIF N_246_i.BLIF \ -un1_amiga_bus_enable_low_i.BLIF N_132_0.BLIF un21_fpu_cs_i.BLIF AS_000_i.BLIF \ -N_142_i.BLIF BGACK_030_INT_i.BLIF N_141_i.BLIF nEXP_SPACE_i.BLIF N_135_0.BLIF \ -cycle_dma_i_0__n.BLIF N_134_0.BLIF RW_000_i.BLIF N_131_i.BLIF CLK_EXP_i.BLIF \ -LDS_000_c_i.BLIF cycle_dma_i_1__n.BLIF UDS_000_c_i.BLIF DS_000_DMA_i.BLIF \ -N_128_i.BLIF AS_000_DMA_i.BLIF N_107_i.BLIF a_i_1__n.BLIF N_203_i.BLIF \ -AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF \ -a_decode_i_19__n.BLIF N_201_i.BLIF a_decode_i_18__n.BLIF N_202_i.BLIF \ -a_decode_i_16__n.BLIF VMA_INT_i.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \ -N_98_i.BLIF sm_amiga_i_0__n.BLIF N_93_i.BLIF sm_amiga_i_5__n.BLIF N_82_i.BLIF \ -sm_amiga_i_6__n.BLIF N_80_i.BLIF sm_amiga_i_i_7__n.BLIF N_72_i.BLIF \ -AS_030_i.BLIF N_68_i.BLIF AS_000_INT_i.BLIF N_59_i.BLIF DSACK1_INT_i.BLIF \ -N_190_i.BLIF sm_amiga_i_1__n.BLIF N_191_i.BLIF FPU_SENSE_i.BLIF \ -AS_030_D1_i.BLIF N_267_i.BLIF cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF \ -N_266_i.BLIF VPA_D_i.BLIF sm_amiga_i_3__n.BLIF N_186_i.BLIF \ -sm_amiga_i_4__n.BLIF cpu_est_i_1__n.BLIF N_185_i.BLIF clk_000_d_i_0__n.BLIF \ -clk_000_d_i_1__n.BLIF N_183_i.BLIF AS_030_D0_i.BLIF N_184_i.BLIF \ -cpu_est_i_2__n.BLIF DTACK_D0_i.BLIF N_182_i.BLIF sm_amiga_i_2__n.BLIF \ -AS_030_000_SYNC_i.BLIF N_181_i.BLIF ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF \ -N_260_i.BLIF ahigh_i_28__n.BLIF pos_clk_size_dma_6_0_1__n.BLIF \ -ahigh_i_29__n.BLIF N_259_i.BLIF ahigh_i_26__n.BLIF \ -pos_clk_size_dma_6_0_0__n.BLIF ahigh_i_27__n.BLIF N_63_0.BLIF \ -ahigh_i_24__n.BLIF N_155_i.BLIF ahigh_i_25__n.BLIF N_162_i.BLIF N_187_i.BLIF \ -un5_e_0.BLIF N_188_i.BLIF N_154_i.BLIF N_189_i.BLIF cpu_est_2_0_3__n.BLIF \ -N_149_i.BLIF N_208_i.BLIF cpu_est_2_0_2__n.BLIF N_147_i.BLIF un2_ds_030_i.BLIF \ -N_148_i.BLIF N_219_i.BLIF cpu_est_2_0_1__n.BLIF N_175_i.BLIF N_146_i.BLIF \ -un3_as_030_i.BLIF N_36_0.BLIF AS_030_c.BLIF N_145_i.BLIF N_35_0.BLIF \ -AS_000_c.BLIF N_143_i.BLIF N_144_i.BLIF RW_000_c.BLIF \ -pos_clk_un9_clk_000_pe_0_n.BLIF N_20_i.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ -RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ -SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \ -AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \ -AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF +A_0_.BLIF N_157_i.BLIF UDS_000_c.BLIF cpu_est_2_0_3__n.BLIF N_156_i.BLIF \ +LDS_000_c.BLIF N_229_i.BLIF cpu_est_2_0_2__n.BLIF size_c_0__n.BLIF \ +N_126_i.BLIF N_150_i.BLIF size_c_1__n.BLIF pos_clk_un9_clk_000_pe_0_n.BLIF \ +inst_BGACK_030_INTreg.BLIF N_20_i.BLIF vcc_n_n.BLIF ahigh_c_24__n.BLIF \ +N_23_0.BLIF un5_e.BLIF N_19_i.BLIF gnd_n_n.BLIF ahigh_c_25__n.BLIF N_22_0.BLIF \ +un1_amiga_bus_enable_low.BLIF N_18_i.BLIF un3_as_030.BLIF ahigh_c_26__n.BLIF \ +N_21_0.BLIF un1_UDS_000_INT.BLIF ipl_c_i_2__n.BLIF un1_LDS_000_INT.BLIF \ +ahigh_c_27__n.BLIF N_43_0.BLIF un1_DS_000_ENABLE_0_sqmuxa.BLIF \ +ipl_c_i_1__n.BLIF un21_fpu_cs.BLIF ahigh_c_28__n.BLIF N_42_0.BLIF \ +un21_berr.BLIF ipl_c_i_0__n.BLIF un8_ciin.BLIF ahigh_c_29__n.BLIF N_41_0.BLIF \ +un2_ds_030.BLIF N_13_i.BLIF cpu_est_0_.BLIF ahigh_c_30__n.BLIF N_27_0.BLIF \ +cpu_est_1_.BLIF LDS_000_INT_i.BLIF cpu_est_2_.BLIF ahigh_c_31__n.BLIF \ +un1_LDS_000_INT_0.BLIF cpu_est_3_.BLIF UDS_000_INT_i.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF un1_UDS_000_INT_0.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_104_0_1.BLIF inst_AS_030_D0.BLIF \ +N_104_0_2.BLIF inst_AS_030_D1.BLIF N_100_0_1.BLIF inst_AS_030_000_SYNC.BLIF \ +N_100_0_2.BLIF inst_AS_000_DMA.BLIF N_113_i_1.BLIF inst_DS_000_DMA.BLIF \ +N_113_i_2.BLIF inst_VMA_INTreg.BLIF N_107_0_1.BLIF inst_VPA_D.BLIF \ +N_99_i_1.BLIF CLK_000_D_3_.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF \ +inst_DTACK_D0.BLIF N_202_1.BLIF inst_AMIGA_DS.BLIF N_202_2.BLIF \ +CLK_000_D_1_.BLIF N_228_1.BLIF CLK_000_D_0_.BLIF N_228_2.BLIF \ +inst_CLK_OUT_PRE_50.BLIF N_228_3.BLIF inst_CLK_OUT_PRE_D.BLIF N_228_4.BLIF \ +IPL_D0_0_.BLIF N_228_5.BLIF IPL_D0_1_.BLIF N_150_1.BLIF IPL_D0_2_.BLIF \ +N_150_2.BLIF CLK_000_D_2_.BLIF N_126_1.BLIF CLK_000_D_4_.BLIF N_126_2.BLIF \ +pos_clk_ipl_n.BLIF un8_ciin_1.BLIF SIZE_DMA_0_.BLIF un8_ciin_2.BLIF \ +SIZE_DMA_1_.BLIF N_201_1_1.BLIF inst_A0_DMA.BLIF N_201_1_2.BLIF \ +inst_RW_000_DMA.BLIF N_201_1_3.BLIF inst_UDS_000_INT.BLIF N_201_1_4.BLIF \ +inst_DS_000_ENABLE.BLIF N_201_1_5.BLIF inst_LDS_000_INT.BLIF \ +a_decode_c_16__n.BLIF N_201_1_6.BLIF inst_BGACK_030_INT_D.BLIF N_201_1_7.BLIF \ +SM_AMIGA_6_.BLIF a_decode_c_17__n.BLIF N_201_1_8.BLIF inst_RW_000_INT.BLIF \ +N_201_1_0.BLIF SM_AMIGA_4_.BLIF a_decode_c_18__n.BLIF N_201_2.BLIF \ +SM_AMIGA_1_.BLIF pos_clk_cycle_dma_5_1_1__n.BLIF SM_AMIGA_0_.BLIF \ +a_decode_c_19__n.BLIF N_176_1.BLIF CYCLE_DMA_0_.BLIF \ +AS_000_DMA_1_sqmuxa_1.BLIF CYCLE_DMA_1_.BLIF a_decode_c_20__n.BLIF \ +N_198_1.BLIF inst_DSACK1_INT.BLIF N_72_i_1.BLIF inst_AS_000_INT.BLIF \ +a_decode_c_21__n.BLIF N_72_i_2.BLIF pos_clk_un9_clk_000_pe_n.BLIF \ +N_206_i_1.BLIF SM_AMIGA_5_.BLIF a_decode_c_22__n.BLIF N_206_i_2.BLIF \ +SM_AMIGA_3_.BLIF N_186_1.BLIF SM_AMIGA_2_.BLIF a_decode_c_23__n.BLIF \ +N_186_2.BLIF N_74_i_1.BLIF N_6.BLIF a_c_0__n.BLIF N_121_i_1.BLIF \ +N_117_i_1.BLIF a_c_1__n.BLIF N_115_i_1.BLIF N_127_i_1.BLIF N_13.BLIF \ +nEXP_SPACE_c.BLIF N_123_i_1.BLIF N_119_i_1.BLIF N_18.BLIF BERR_c.BLIF \ +N_111_i_1.BLIF N_19.BLIF un21_berr_1.BLIF N_20.BLIF BG_030_c.BLIF \ +un21_fpu_cs_1.BLIF N_172_1.BLIF BG_000DFFreg.BLIF N_161_1.BLIF N_153_1.BLIF \ +pos_clk_ipl_1_n.BLIF BGACK_000_c.BLIF ds_000_dma_0_un3_n.BLIF \ +ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF as_000_dma_0_un3_n.BLIF \ +as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF CLK_OSZI_c.BLIF \ +uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF \ +CLK_OUT_INTreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF \ +bg_000_0_un0_n.BLIF FPU_SENSE_c.BLIF lds_000_int_0_un3_n.BLIF \ +lds_000_int_0_un1_n.BLIF IPL_030DFF_0_reg.BLIF lds_000_int_0_un0_n.BLIF \ +rw_000_int_0_un3_n.BLIF IPL_030DFF_1_reg.BLIF rw_000_int_0_un1_n.BLIF \ +rw_000_int_0_un0_n.BLIF SM_AMIGA_i_7_.BLIF IPL_030DFF_2_reg.BLIF \ +bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un1_n.BLIF ipl_c_0__n.BLIF \ +bgack_030_int_0_un0_n.BLIF cpu_est_2_2__n.BLIF as_030_000_sync_0_un3_n.BLIF \ +cpu_est_2_3__n.BLIF ipl_c_1__n.BLIF as_030_000_sync_0_un1_n.BLIF G_105.BLIF \ +as_030_000_sync_0_un0_n.BLIF G_106.BLIF ipl_c_2__n.BLIF \ +cpu_est_0_1__un3_n.BLIF G_107.BLIF cpu_est_0_1__un1_n.BLIF \ +cpu_est_0_1__un0_n.BLIF N_205.BLIF DTACK_c.BLIF cpu_est_0_2__un3_n.BLIF \ +N_74.BLIF cpu_est_0_2__un1_n.BLIF N_78.BLIF cpu_est_0_2__un0_n.BLIF N_79.BLIF \ +cpu_est_0_3__un3_n.BLIF N_80.BLIF VPA_c.BLIF cpu_est_0_3__un1_n.BLIF N_83.BLIF \ +cpu_est_0_3__un0_n.BLIF N_84.BLIF ipl_030_0_0__un3_n.BLIF N_89.BLIF RST_c.BLIF \ +ipl_030_0_0__un1_n.BLIF N_95.BLIF ipl_030_0_0__un0_n.BLIF N_96.BLIF \ +ipl_030_0_1__un3_n.BLIF N_97.BLIF ipl_030_0_1__un1_n.BLIF N_105.BLIF RW_c.BLIF \ +ipl_030_0_1__un0_n.BLIF N_126.BLIF ipl_030_0_2__un3_n.BLIF N_150.BLIF \ +fc_c_0__n.BLIF ipl_030_0_2__un1_n.BLIF N_153.BLIF ipl_030_0_2__un0_n.BLIF \ +N_156.BLIF fc_c_1__n.BLIF ds_000_enable_0_un3_n.BLIF N_157.BLIF \ +ds_000_enable_0_un1_n.BLIF N_158.BLIF ds_000_enable_0_un0_n.BLIF N_159.BLIF \ +AMIGA_BUS_DATA_DIR_c.BLIF vma_int_0_un3_n.BLIF N_160.BLIF vma_int_0_un1_n.BLIF \ +N_161.BLIF vma_int_0_un0_n.BLIF N_172.BLIF as_030_d1_0_un3_n.BLIF N_177.BLIF \ +as_030_d1_0_un1_n.BLIF N_178.BLIF N_181_i.BLIF as_030_d1_0_un0_n.BLIF \ +N_179.BLIF N_37_0.BLIF a_decode_15__n.BLIF N_180.BLIF N_182.BLIF N_176_i.BLIF \ +a_decode_14__n.BLIF N_183.BLIF N_175_i.BLIF N_184.BLIF N_72_i.BLIF \ +a_decode_13__n.BLIF N_212.BLIF N_198_i.BLIF N_213.BLIF AMIGA_DS_i.BLIF \ +a_decode_12__n.BLIF N_214.BLIF N_186_i.BLIF N_190.BLIF N_185_i.BLIF \ +a_decode_11__n.BLIF N_191.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_194.BLIF \ +pos_clk_un2_i_n.BLIF a_decode_10__n.BLIF N_195.BLIF N_3_i.BLIF N_196.BLIF \ +N_32_0.BLIF a_decode_9__n.BLIF N_197.BLIF N_4_i.BLIF N_202.BLIF N_31_0.BLIF \ +a_decode_8__n.BLIF N_220.BLIF N_39_1_i.BLIF N_224.BLIF N_34_0.BLIF \ +a_decode_7__n.BLIF N_225.BLIF BG_030_c_i.BLIF N_228.BLIF \ +pos_clk_un9_bg_030_0_n.BLIF a_decode_6__n.BLIF N_229.BLIF N_17_i.BLIF \ +N_201_1.BLIF N_24_0.BLIF a_decode_5__n.BLIF N_104.BLIF N_16_i.BLIF N_100.BLIF \ +N_25_0.BLIF a_decode_4__n.BLIF N_171.BLIF N_15_i.BLIF N_204.BLIF N_26_0.BLIF \ +a_decode_3__n.BLIF N_164.BLIF N_12_i.BLIF N_162.BLIF N_28_0.BLIF \ +a_decode_2__n.BLIF N_163.BLIF N_5_i.BLIF cpu_est_2_1__n.BLIF N_30_0.BLIF \ +N_152.BLIF a_c_i_0__n.BLIF N_11.BLIF size_c_i_1__n.BLIF N_201.BLIF \ +pos_clk_un10_sm_amiga_i_n.BLIF N_193.BLIF N_231_i.BLIF N_192.BLIF \ +pos_clk_un6_bgack_000_0_n.BLIF N_107.BLIF N_40_0.BLIF N_99.BLIF \ +un1_SM_AMIGA_0_sqmuxa_1_0.BLIF N_219.BLIF RW_c_i.BLIF N_81.BLIF \ +pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n.BLIF N_201_i.BLIF \ +un1_SM_AMIGA_0_sqmuxa_1.BLIF N_81_i.BLIF pos_clk_un6_bgack_000_n.BLIF \ +N_219_i.BLIF N_231.BLIF N_202_i.BLIF N_5.BLIF N_191_i.BLIF N_12.BLIF \ +N_98_i.BLIF N_15.BLIF N_99_i.BLIF N_16.BLIF N_107_0.BLIF N_17.BLIF \ +N_192_i.BLIF pos_clk_un9_bg_030_n.BLIF N_193_i.BLIF N_3.BLIF N_72.BLIF \ +N_11_i.BLIF AS_000_DMA_1_sqmuxa.BLIF N_29_0.BLIF N_4.BLIF VPA_c_i.BLIF \ +G_91.BLIF N_44_0.BLIF N_176.BLIF DTACK_c_i.BLIF pos_clk_un2_n.BLIF N_45_0.BLIF \ +N_175.BLIF N_152_i.BLIF N_185.BLIF N_153_i.BLIF N_198.BLIF \ +cpu_est_2_0_1__n.BLIF N_186.BLIF N_163_i.BLIF N_181.BLIF N_162_i.BLIF \ +un1_amiga_bus_enable_low_i.BLIF un21_fpu_cs_i.BLIF N_203_i.BLIF AS_000_i.BLIF \ +un1_dsack1_i.BLIF BGACK_030_INT_i.BLIF N_164_i.BLIF nEXP_SPACE_i.BLIF \ +N_228_i.BLIF RW_000_i.BLIF N_204_0.BLIF cycle_dma_i_0__n.BLIF N_171_i.BLIF \ +CLK_EXP_i.BLIF N_172_i.BLIF cycle_dma_i_1__n.BLIF \ +un11_amiga_bus_enable_high_i.BLIF DS_000_DMA_i.BLIF N_85_0.BLIF \ +AS_000_DMA_i.BLIF clk_000_d_i_3__n.BLIF ahigh_i_25__n.BLIF N_100_0.BLIF \ +ahigh_i_24__n.BLIF AS_030_D1_i.BLIF ahigh_i_27__n.BLIF N_104_0.BLIF \ +ahigh_i_26__n.BLIF N_105_0.BLIF ahigh_i_29__n.BLIF N_97_i.BLIF \ +ahigh_i_28__n.BLIF LDS_000_c_i.BLIF ahigh_i_31__n.BLIF UDS_000_c_i.BLIF \ +ahigh_i_30__n.BLIF N_96_i.BLIF sm_amiga_i_2__n.BLIF N_95_i.BLIF \ +sm_amiga_i_1__n.BLIF N_220_i.BLIF DTACK_D0_i.BLIF \ +un1_DS_000_ENABLE_0_sqmuxa_0.BLIF sm_amiga_i_i_7__n.BLIF VMA_INT_i.BLIF \ +sm_amiga_i_3__n.BLIF N_89_i.BLIF a_decode_i_20__n.BLIF N_84_i.BLIF \ +AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_83_i.BLIF cpu_est_i_0__n.BLIF N_82_i.BLIF \ +AS_030_i.BLIF N_80_i.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_79_i.BLIF \ +sm_amiga_i_6__n.BLIF N_78_0.BLIF AS_030_D0_i.BLIF N_74_i.BLIF \ +cpu_est_i_3__n.BLIF N_197_i.BLIF VPA_D_i.BLIF sm_amiga_i_5__n.BLIF \ +N_195_i.BLIF sm_amiga_i_4__n.BLIF N_196_i.BLIF cpu_est_i_1__n.BLIF \ +clk_000_d_i_0__n.BLIF N_194_i.BLIF clk_000_d_i_1__n.BLIF cpu_est_i_2__n.BLIF \ +N_190_i.BLIF DSACK1_INT_i.BLIF AS_000_INT_i.BLIF N_214_i.BLIF \ +a_decode_i_16__n.BLIF a_decode_i_19__n.BLIF N_184_i.BLIF a_decode_i_18__n.BLIF \ +pos_clk_size_dma_6_0_1__n.BLIF FPU_SENSE_i.BLIF N_183_i.BLIF \ +AS_030_000_SYNC_i.BLIF pos_clk_size_dma_6_0_0__n.BLIF sm_amiga_i_0__n.BLIF \ +N_182_i.BLIF N_187_i.BLIF N_38_0.BLIF N_188_i.BLIF N_179_i.BLIF N_189_i.BLIF \ +N_180_i.BLIF N_177_i.BLIF N_178_i.BLIF un2_ds_030_i.BLIF N_225_i.BLIF \ +un8_ciin_i.BLIF N_224_i.BLIF N_205_0.BLIF un3_as_030_i.BLIF N_160_i.BLIF \ +AS_030_c.BLIF N_161_i.BLIF un5_e_0.BLIF AS_000_c.BLIF N_159_i.BLIF \ +RW_000_c.BLIF N_158_i.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \ +UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ +AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF \ +AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF \ +A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ -SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D \ -SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D \ -IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ -IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ -IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ -SM_AMIGA_5_.D SM_AMIGA_5_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D \ -CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C \ -SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C CYCLE_DMA_0_.D \ -CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C \ -cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C \ -CLK_000_D_0_.D CLK_000_D_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ -inst_DTACK_D0.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ IPL_D0_2_.D IPL_D0_2_.C \ +SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \ +SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C \ +SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D \ +SM_AMIGA_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D \ +cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D \ +IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D \ +IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C CLK_000_D_0_.D CLK_000_D_0_.C \ +CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D \ +CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C SIZE_DMA_0_.D SIZE_DMA_0_.C \ +SIZE_DMA_1_.D SIZE_DMA_1_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \ +CYCLE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_DSACK1_INT.D inst_DSACK1_INT.C \ +inst_AS_000_INT.D inst_AS_000_INT.C inst_AMIGA_DS.D inst_AMIGA_DS.C \ +inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ +inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ +inst_DTACK_D0.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_AS_030_D1.D \ +inst_AS_030_D1.C inst_UDS_000_INT.D inst_UDS_000_INT.C BG_000DFFreg.D \ BG_000DFFreg.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_VMA_INTreg.D \ inst_VMA_INTreg.C inst_RW_000_INT.D inst_RW_000_INT.C inst_AS_030_000_SYNC.D \ inst_AS_030_000_SYNC.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C \ -inst_DSACK1_INT.D inst_DSACK1_INT.C inst_AS_000_INT.D inst_AS_000_INT.C \ -inst_AMIGA_DS.D inst_AMIGA_DS.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D \ -inst_RW_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ -inst_AS_030_D1.D inst_AS_030_D1.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C CLK_OUT_INTreg.D \ CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C SIZE_1_ AHIGH_31_ AS_030 AS_000 \ RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ \ -AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_23_0 UDS_000_c N_19_i N_22_0 LDS_000_c \ -N_18_i N_21_0 size_c_0__n ipl_c_i_2__n N_43_0 size_c_1__n ipl_c_i_1__n N_42_0 \ -vcc_n_n ahigh_c_24__n ipl_c_i_0__n un5_e N_41_0 gnd_n_n ahigh_c_25__n \ -DTACK_c_i un1_amiga_bus_enable_low N_45_0 un3_as_030 ahigh_c_26__n VPA_c_i \ -un1_UDS_000_INT N_44_0 un1_LDS_000_INT ahigh_c_27__n N_13_i \ -un1_DS_000_ENABLE_0_sqmuxa N_27_0 un10_ciin ahigh_c_28__n LDS_000_INT_i \ -un21_fpu_cs un1_LDS_000_INT_0 un21_berr ahigh_c_29__n UDS_000_INT_i un2_ds_030 \ -un1_UDS_000_INT_0 ahigh_c_30__n N_96_0_1 N_96_0_2 ahigh_c_31__n N_282_0_1 \ -N_282_0_2 N_282_0_3 N_282_0_4 pos_clk_un10_sm_amiga_i_1_n un10_ciin_1 \ -un10_ciin_2 un10_ciin_3 un10_ciin_4 un10_ciin_5 un10_ciin_6 un10_ciin_7 \ -un10_ciin_8 un10_ciin_9 un10_ciin_10 un10_ciin_11 N_201_1 N_201_2 N_131_i_1 \ -N_134_0_1 N_113_i_1 N_113_i_2 N_144_1 pos_clk_ipl_n N_144_2 N_143_1 N_143_2 \ -N_163_1 N_163_2 N_163_3 un21_fpu_cs_1 a_decode_c_16__n un21_berr_1_0 \ -pos_clk_cycle_dma_5_1_1__n a_decode_c_17__n N_199_1 AS_000_DMA_1_sqmuxa_1 \ -a_decode_c_18__n N_140_1 N_66_i_1 a_decode_c_19__n N_66_i_2 N_205_i_1 \ -a_decode_c_20__n N_205_i_2 N_180_1 a_decode_c_21__n N_180_2 \ -pos_clk_un9_clk_000_pe_n N_59_i_1 a_decode_c_22__n N_127_i_1 N_123_i_1 \ -a_decode_c_23__n N_121_i_1 N_119_i_1 N_6 a_c_0__n N_117_i_1 N_115_i_1 a_c_1__n \ -N_111_i_1 N_165_1 N_13 nEXP_SPACE_c N_162_1 N_148_1 N_18 BERR_c \ -pos_clk_ipl_1_n N_19 ds_000_dma_0_un3_n N_20 BG_030_c ds_000_dma_0_un1_n \ +AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_157_i UDS_000_c cpu_est_2_0_3__n N_156_i \ +LDS_000_c N_229_i cpu_est_2_0_2__n size_c_0__n N_126_i N_150_i size_c_1__n \ +pos_clk_un9_clk_000_pe_0_n N_20_i vcc_n_n ahigh_c_24__n N_23_0 un5_e N_19_i \ +gnd_n_n ahigh_c_25__n N_22_0 un1_amiga_bus_enable_low N_18_i un3_as_030 \ +ahigh_c_26__n N_21_0 un1_UDS_000_INT ipl_c_i_2__n un1_LDS_000_INT \ +ahigh_c_27__n N_43_0 un1_DS_000_ENABLE_0_sqmuxa ipl_c_i_1__n un21_fpu_cs \ +ahigh_c_28__n N_42_0 un21_berr ipl_c_i_0__n un8_ciin ahigh_c_29__n N_41_0 \ +un2_ds_030 N_13_i ahigh_c_30__n N_27_0 LDS_000_INT_i ahigh_c_31__n \ +un1_LDS_000_INT_0 UDS_000_INT_i un1_UDS_000_INT_0 N_104_0_1 N_104_0_2 \ +N_100_0_1 N_100_0_2 N_113_i_1 N_113_i_2 N_107_0_1 N_99_i_1 \ +pos_clk_un10_sm_amiga_i_1_n N_202_1 N_202_2 N_228_1 N_228_2 N_228_3 N_228_4 \ +N_228_5 N_150_1 N_150_2 N_126_1 N_126_2 pos_clk_ipl_n un8_ciin_1 un8_ciin_2 \ +N_201_1_1 N_201_1_2 N_201_1_3 N_201_1_4 N_201_1_5 a_decode_c_16__n N_201_1_6 \ +N_201_1_7 a_decode_c_17__n N_201_1_8 N_201_1_0 a_decode_c_18__n N_201_2 \ +pos_clk_cycle_dma_5_1_1__n a_decode_c_19__n N_176_1 AS_000_DMA_1_sqmuxa_1 \ +a_decode_c_20__n N_198_1 N_72_i_1 a_decode_c_21__n N_72_i_2 \ +pos_clk_un9_clk_000_pe_n N_206_i_1 a_decode_c_22__n N_206_i_2 N_186_1 \ +a_decode_c_23__n N_186_2 N_74_i_1 N_6 a_c_0__n N_121_i_1 N_117_i_1 a_c_1__n \ +N_115_i_1 N_127_i_1 N_13 nEXP_SPACE_c N_123_i_1 N_119_i_1 N_18 BERR_c \ +N_111_i_1 N_19 un21_berr_1 N_20 BG_030_c un21_fpu_cs_1 N_172_1 N_161_1 N_153_1 \ +pos_clk_ipl_1_n BGACK_000_c ds_000_dma_0_un3_n ds_000_dma_0_un1_n \ ds_000_dma_0_un0_n as_000_dma_0_un3_n as_000_dma_0_un1_n as_000_dma_0_un0_n \ -BGACK_000_c uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n \ -bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n CLK_OSZI_c lds_000_int_0_un3_n \ -lds_000_int_0_un1_n lds_000_int_0_un0_n as_030_d1_0_un3_n as_030_d1_0_un1_n \ -as_030_d1_0_un0_n FPU_SENSE_c rw_000_int_0_un3_n rw_000_int_0_un1_n \ -rw_000_int_0_un0_n as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n \ -as_030_000_sync_0_un0_n bgack_030_int_0_un3_n bgack_030_int_0_un1_n \ -cpu_est_2_1__n ipl_c_0__n bgack_030_int_0_un0_n cpu_est_2_2__n \ -cpu_est_0_1__un3_n cpu_est_2_3__n ipl_c_1__n cpu_est_0_1__un1_n \ -cpu_est_0_1__un0_n ipl_c_2__n cpu_est_0_2__un3_n cpu_est_0_2__un1_n N_60 \ -cpu_est_0_2__un0_n N_63 DTACK_c cpu_est_0_3__un3_n N_126 cpu_est_0_3__un1_n \ -N_150 cpu_est_0_3__un0_n N_151 ipl_030_0_0__un3_n N_219 VPA_c \ -ipl_030_0_0__un1_n N_175 ipl_030_0_0__un0_n ipl_030_0_1__un3_n N_59 RST_c \ -ipl_030_0_1__un1_n N_68 ipl_030_0_1__un0_n N_72 ipl_030_0_2__un3_n N_80 \ -ipl_030_0_2__un1_n N_93 RW_c ipl_030_0_2__un0_n N_98 ds_000_enable_0_un3_n \ -N_107 fc_c_0__n ds_000_enable_0_un1_n N_128 ds_000_enable_0_un0_n N_131 \ -fc_c_1__n vma_int_0_un3_n N_134 vma_int_0_un1_n N_135 vma_int_0_un0_n N_141 \ -AMIGA_BUS_DATA_DIR_c a_decode_15__n N_142 N_143 a_decode_14__n N_144 N_145 \ -a_decode_13__n N_146 N_205_i N_147 N_140_i a_decode_12__n N_148 AMIGA_DS_i \ -N_149 a_decode_11__n N_154 N_199_i N_155 N_198_i a_decode_10__n N_162 N_180_i \ -N_165 N_262_i a_decode_9__n N_259 AMIGA_BUS_DATA_DIR_c_0 N_260 pos_clk_un2_i_n \ -a_decode_8__n N_181 N_3_i N_182 N_32_0 a_decode_7__n N_183 N_4_i N_184 N_31_0 \ -a_decode_6__n N_185 N_220_i N_186 BG_030_c_i a_decode_5__n N_266 \ -pos_clk_un9_bg_030_0_n N_267 N_17_i a_decode_4__n N_268 N_24_0 N_190 N_16_i \ -a_decode_3__n N_191 N_25_0 N_201 N_15_i a_decode_2__n N_202 N_26_0 N_203 \ -N_12_i N_208 N_28_0 N_163 N_11_i N_282 N_29_0 un21_berr_1 N_5_i N_132 N_30_0 \ -N_96 a_c_i_0__n N_129 size_c_i_1__n un1_SM_AMIGA_0_sqmuxa_1 \ -pos_clk_un10_sm_amiga_i_n N_169 un1_dsack1_i N_170 N_69_i N_167 N_163_i N_168 \ -N_244_0 pos_clk_rw_000_int_5_n N_164_i pos_clk_un6_bgack_000_n N_165_i N_274 \ -un11_amiga_bus_enable_high_i N_164 un10_ciin_i N_244 N_60_0 N_5 N_274_i N_11 \ -pos_clk_un6_bgack_000_0_n N_12 RW_c_i N_15 pos_clk_rw_000_int_5_0_n N_16 \ -N_168_i N_17 N_167_i pos_clk_un9_bg_030_n N_170_i N_3 N_169_i N_205 \ -AS_000_DMA_1_sqmuxa N_38_0 N_4 un1_SM_AMIGA_0_sqmuxa_1_0 N_199 N_282_0 \ -pos_clk_un2_n clk_000_d_i_3__n N_140 N_96_0 N_262 N_129_i N_198 N_268_i N_180 \ -N_246_i un1_amiga_bus_enable_low_i N_132_0 un21_fpu_cs_i AS_000_i N_142_i \ -BGACK_030_INT_i N_141_i nEXP_SPACE_i N_135_0 cycle_dma_i_0__n N_134_0 RW_000_i \ -N_131_i CLK_EXP_i LDS_000_c_i cycle_dma_i_1__n UDS_000_c_i DS_000_DMA_i \ -N_128_i AS_000_DMA_i N_107_i a_i_1__n N_203_i AMIGA_BUS_ENABLE_DMA_LOW_i \ -un1_DS_000_ENABLE_0_sqmuxa_0 a_decode_i_19__n N_201_i a_decode_i_18__n N_202_i \ -a_decode_i_16__n VMA_INT_i AMIGA_BUS_ENABLE_DMA_HIGH_i N_98_i sm_amiga_i_0__n \ -N_93_i sm_amiga_i_5__n N_82_i sm_amiga_i_6__n N_80_i sm_amiga_i_i_7__n N_72_i \ -AS_030_i N_68_i AS_000_INT_i N_59_i DSACK1_INT_i N_190_i sm_amiga_i_1__n \ -N_191_i FPU_SENSE_i AS_030_D1_i N_267_i cpu_est_i_0__n cpu_est_i_3__n N_266_i \ -VPA_D_i sm_amiga_i_3__n N_186_i sm_amiga_i_4__n cpu_est_i_1__n N_185_i \ -clk_000_d_i_0__n clk_000_d_i_1__n N_183_i AS_030_D0_i N_184_i cpu_est_i_2__n \ -DTACK_D0_i N_182_i sm_amiga_i_2__n AS_030_000_SYNC_i N_181_i ahigh_i_30__n \ -ahigh_i_31__n N_260_i ahigh_i_28__n pos_clk_size_dma_6_0_1__n ahigh_i_29__n \ -N_259_i ahigh_i_26__n pos_clk_size_dma_6_0_0__n ahigh_i_27__n N_63_0 \ -ahigh_i_24__n N_155_i ahigh_i_25__n N_162_i N_187_i un5_e_0 N_188_i N_154_i \ -N_189_i cpu_est_2_0_3__n N_149_i N_208_i cpu_est_2_0_2__n N_147_i un2_ds_030_i \ -N_148_i N_219_i cpu_est_2_0_1__n N_175_i N_146_i un3_as_030_i N_36_0 AS_030_c \ -N_145_i N_35_0 AS_000_c N_143_i N_144_i RW_000_c pos_clk_un9_clk_000_pe_0_n \ -N_20_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ -SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE \ -AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE \ -DSACK1.OE VMA.OE CIIN.OE G_105 G_106 G_107 G_91 +CLK_OSZI_c uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n \ +bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n FPU_SENSE_c lds_000_int_0_un3_n \ +lds_000_int_0_un1_n lds_000_int_0_un0_n rw_000_int_0_un3_n rw_000_int_0_un1_n \ +rw_000_int_0_un0_n bgack_030_int_0_un3_n bgack_030_int_0_un1_n ipl_c_0__n \ +bgack_030_int_0_un0_n cpu_est_2_2__n as_030_000_sync_0_un3_n cpu_est_2_3__n \ +ipl_c_1__n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n ipl_c_2__n \ +cpu_est_0_1__un3_n cpu_est_0_1__un1_n cpu_est_0_1__un0_n N_205 DTACK_c \ +cpu_est_0_2__un3_n N_74 cpu_est_0_2__un1_n N_78 cpu_est_0_2__un0_n N_79 \ +cpu_est_0_3__un3_n N_80 VPA_c cpu_est_0_3__un1_n N_83 cpu_est_0_3__un0_n N_84 \ +ipl_030_0_0__un3_n N_89 RST_c ipl_030_0_0__un1_n N_95 ipl_030_0_0__un0_n N_96 \ +ipl_030_0_1__un3_n N_97 ipl_030_0_1__un1_n N_105 RW_c ipl_030_0_1__un0_n N_126 \ +ipl_030_0_2__un3_n N_150 fc_c_0__n ipl_030_0_2__un1_n N_153 ipl_030_0_2__un0_n \ +N_156 fc_c_1__n ds_000_enable_0_un3_n N_157 ds_000_enable_0_un1_n N_158 \ +ds_000_enable_0_un0_n N_159 AMIGA_BUS_DATA_DIR_c vma_int_0_un3_n N_160 \ +vma_int_0_un1_n N_161 vma_int_0_un0_n N_172 as_030_d1_0_un3_n N_177 \ +as_030_d1_0_un1_n N_178 N_181_i as_030_d1_0_un0_n N_179 N_37_0 a_decode_15__n \ +N_180 N_182 N_176_i a_decode_14__n N_183 N_175_i N_184 N_72_i a_decode_13__n \ +N_212 N_198_i N_213 AMIGA_DS_i a_decode_12__n N_214 N_186_i N_190 N_185_i \ +a_decode_11__n N_191 AMIGA_BUS_DATA_DIR_c_0 N_194 pos_clk_un2_i_n \ +a_decode_10__n N_195 N_3_i N_196 N_32_0 a_decode_9__n N_197 N_4_i N_202 N_31_0 \ +a_decode_8__n N_220 N_39_1_i N_224 N_34_0 a_decode_7__n N_225 BG_030_c_i N_228 \ +pos_clk_un9_bg_030_0_n a_decode_6__n N_229 N_17_i N_201_1 N_24_0 a_decode_5__n \ +N_104 N_16_i N_100 N_25_0 a_decode_4__n N_171 N_15_i N_204 N_26_0 \ +a_decode_3__n N_164 N_12_i N_162 N_28_0 a_decode_2__n N_163 N_5_i \ +cpu_est_2_1__n N_30_0 N_152 a_c_i_0__n N_11 size_c_i_1__n N_201 \ +pos_clk_un10_sm_amiga_i_n N_193 N_231_i N_192 pos_clk_un6_bgack_000_0_n N_107 \ +N_40_0 N_99 un1_SM_AMIGA_0_sqmuxa_1_0 N_219 RW_c_i N_81 \ +pos_clk_rw_000_int_5_0_n pos_clk_rw_000_int_5_n N_201_i \ +un1_SM_AMIGA_0_sqmuxa_1 N_81_i pos_clk_un6_bgack_000_n N_219_i N_231 N_202_i \ +N_5 N_191_i N_12 N_98_i N_15 N_99_i N_16 N_107_0 N_17 N_192_i \ +pos_clk_un9_bg_030_n N_193_i N_3 N_72 N_11_i AS_000_DMA_1_sqmuxa N_29_0 N_4 \ +VPA_c_i N_44_0 N_176 DTACK_c_i pos_clk_un2_n N_45_0 N_175 N_152_i N_185 \ +N_153_i N_198 cpu_est_2_0_1__n N_186 N_163_i N_181 N_162_i \ +un1_amiga_bus_enable_low_i un21_fpu_cs_i N_203_i AS_000_i un1_dsack1_i \ +BGACK_030_INT_i N_164_i nEXP_SPACE_i N_228_i RW_000_i N_204_0 cycle_dma_i_0__n \ +N_171_i CLK_EXP_i N_172_i cycle_dma_i_1__n un11_amiga_bus_enable_high_i \ +DS_000_DMA_i N_85_0 AS_000_DMA_i clk_000_d_i_3__n ahigh_i_25__n N_100_0 \ +ahigh_i_24__n AS_030_D1_i ahigh_i_27__n N_104_0 ahigh_i_26__n N_105_0 \ +ahigh_i_29__n N_97_i ahigh_i_28__n LDS_000_c_i ahigh_i_31__n UDS_000_c_i \ +ahigh_i_30__n N_96_i sm_amiga_i_2__n N_95_i sm_amiga_i_1__n N_220_i DTACK_D0_i \ +un1_DS_000_ENABLE_0_sqmuxa_0 sm_amiga_i_i_7__n VMA_INT_i sm_amiga_i_3__n \ +N_89_i a_decode_i_20__n N_84_i AMIGA_BUS_ENABLE_DMA_LOW_i N_83_i \ +cpu_est_i_0__n N_82_i AS_030_i N_80_i AMIGA_BUS_ENABLE_DMA_HIGH_i N_79_i \ +sm_amiga_i_6__n N_78_0 AS_030_D0_i N_74_i cpu_est_i_3__n N_197_i VPA_D_i \ +sm_amiga_i_5__n N_195_i sm_amiga_i_4__n N_196_i cpu_est_i_1__n \ +clk_000_d_i_0__n N_194_i clk_000_d_i_1__n cpu_est_i_2__n N_190_i DSACK1_INT_i \ +AS_000_INT_i N_214_i a_decode_i_16__n a_decode_i_19__n N_184_i \ +a_decode_i_18__n pos_clk_size_dma_6_0_1__n FPU_SENSE_i N_183_i \ +AS_030_000_SYNC_i pos_clk_size_dma_6_0_0__n sm_amiga_i_0__n N_182_i N_187_i \ +N_38_0 N_188_i N_179_i N_189_i N_180_i N_177_i N_178_i un2_ds_030_i N_225_i \ +un8_ciin_i N_224_i N_205_0 un3_as_030_i N_160_i AS_030_c N_161_i un5_e_0 \ +AS_000_c N_159_i RW_000_c N_158_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE \ +LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE \ +AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE \ +BERR.OE RW.OE DS_030.OE DSACK1.OE VMA.OE CIIN.OE G_105 G_106 G_107 G_91 +.names N_43_0.BLIF IPL_D0_2_.D +0 1 +.names N_127_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D +11 1 +.names N_123_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D +11 1 +.names N_121_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D +11 1 .names N_119_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D 11 1 .names N_117_i_1.BLIF RST_c.BLIF SM_AMIGA_3_.D @@ -343,6 +354,15 @@ DSACK1.OE VMA.OE CIIN.OE G_105 G_106 G_107 G_91 11 1 .names N_111_i_1.BLIF RST_c.BLIF SM_AMIGA_0_.D 11 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D +1- 1 +-1 1 .names N_21_0.BLIF IPL_030DFF_0_reg.D 0 1 .names N_22_0.BLIF IPL_030DFF_1_reg.D @@ -353,34 +373,31 @@ DSACK1.OE VMA.OE CIIN.OE G_105 G_106 G_107 G_91 0 1 .names N_42_0.BLIF IPL_D0_1_.D 0 1 -.names N_43_0.BLIF IPL_D0_2_.D -0 1 -.names N_127_i_1.BLIF RST_c.BLIF SM_AMIGA_i_7_.D -11 1 -.names N_123_i_1.BLIF RST_c.BLIF SM_AMIGA_6_.D -11 1 -.names N_121_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D -11 1 .names pos_clk_size_dma_6_0_0__n.BLIF SIZE_DMA_0_.D 0 1 .names pos_clk_size_dma_6_0_1__n.BLIF SIZE_DMA_1_.D 0 1 -.names N_66_i_1.BLIF N_66_i_2.BLIF CYCLE_DMA_0_.D +.names N_206_i_1.BLIF N_206_i_2.BLIF CYCLE_DMA_0_.D 11 1 .names pos_clk_cycle_dma_5_1_1__n.BLIF G_91.BLIF CYCLE_DMA_1_.D 11 1 -.names N_190_i.BLIF N_191_i.BLIF cpu_est_0_.D +.names N_162_i.BLIF N_163_i.BLIF cpu_est_0_.D 11 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D -1- 1 --1 1 -.names N_151.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +.names N_213.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names N_177_i.BLIF N_178_i.BLIF inst_DSACK1_INT.D +11 1 +.names N_179_i.BLIF N_180_i.BLIF inst_AS_000_INT.D +11 1 +.names N_37_0.BLIF inst_AMIGA_DS.D +0 1 +.names N_38_0.BLIF inst_A0_DMA.D +0 1 +.names N_212.BLIF inst_RW_000_DMA.D +0 1 +.names N_40_0.BLIF inst_AS_030_D0.D 0 1 .names N_44_0.BLIF inst_VPA_D.D 0 1 @@ -388,6 +405,11 @@ DSACK1.OE VMA.OE CIIN.OE G_105 G_106 G_107 G_91 0 1 .names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D 11 1 +.names as_030_d1_0_un1_n.BLIF as_030_d1_0_un0_n.BLIF inst_AS_030_D1.D +1- 1 +-1 1 +.names N_24_0.BLIF inst_UDS_000_INT.D +0 1 .names N_25_0.BLIF BG_000DFFreg.D 0 1 .names N_26_0.BLIF inst_LDS_000_INT.D @@ -404,235 +426,228 @@ DSACK1.OE VMA.OE CIIN.OE G_105 G_106 G_107 G_91 0 1 .names N_32_0.BLIF inst_DS_000_DMA.D 0 1 -.names N_167_i.BLIF N_168_i.BLIF inst_DSACK1_INT.D -11 1 -.names N_169_i.BLIF N_170_i.BLIF inst_AS_000_INT.D -11 1 -.names N_35_0.BLIF inst_AMIGA_DS.D -0 1 -.names N_36_0.BLIF inst_A0_DMA.D -0 1 -.names N_126.BLIF inst_RW_000_DMA.D -0 1 -.names N_38_0.BLIF inst_AS_030_D0.D -0 1 -.names N_150.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 -.names as_030_d1_0_un1_n.BLIF as_030_d1_0_un0_n.BLIF inst_AS_030_D1.D -1- 1 --1 1 -.names N_24_0.BLIF inst_UDS_000_INT.D -0 1 -.names N_220_i.BLIF inst_BGACK_030_INT_D.D +.names N_39_1_i.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names N_20_i.BLIF RST_c.BLIF N_23_0 -11 1 -.names N_19.BLIF N_19_i +.names N_157.BLIF N_157_i 0 1 -.names N_19_i.BLIF RST_c.BLIF N_22_0 +.names N_83.BLIF N_157_i.BLIF cpu_est_2_0_3__n 11 1 -.names N_18.BLIF N_18_i +.names N_156.BLIF N_156_i 0 1 -.names N_18_i.BLIF RST_c.BLIF N_21_0 -11 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n +.names N_229.BLIF N_229_i 0 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_43_0 +.names N_156_i.BLIF N_229_i.BLIF cpu_est_2_0_2__n 11 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n +.names N_126.BLIF N_126_i 0 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_42_0 +.names N_150.BLIF N_150_i +0 1 +.names N_126_i.BLIF N_150_i.BLIF pos_clk_un9_clk_000_pe_0_n 11 1 +.names N_20.BLIF N_20_i +0 1 .names vcc_n_n 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 +.names N_20_i.BLIF RST_c.BLIF N_23_0 +11 1 .names un5_e_0.BLIF un5_e 0 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_41_0 -11 1 -.names gnd_n_n -.names DTACK_c.BLIF DTACK_c_i +.names N_19.BLIF N_19_i 0 1 +.names gnd_n_n +.names N_19_i.BLIF RST_c.BLIF N_22_0 +11 1 .names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ un1_amiga_bus_enable_low 11 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_45_0 -11 1 +.names N_18.BLIF N_18_i +0 1 .names AS_000_DMA_i.BLIF AS_000_i.BLIF un3_as_030 11 1 -.names VPA_c.BLIF VPA_c_i -0 1 +.names N_18_i.BLIF RST_c.BLIF N_21_0 +11 1 .names un1_UDS_000_INT_0.BLIF un1_UDS_000_INT 0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_44_0 -11 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n +0 1 .names un1_LDS_000_INT_0.BLIF un1_LDS_000_INT 0 1 -.names N_13.BLIF N_13_i -0 1 +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_43_0 +11 1 .names un1_DS_000_ENABLE_0_sqmuxa_0.BLIF un1_DS_000_ENABLE_0_sqmuxa 0 1 +.names ipl_c_1__n.BLIF ipl_c_i_1__n +0 1 +.names un21_fpu_cs_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs +11 1 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_42_0 +11 1 +.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr +11 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names un8_ciin_1.BLIF un8_ciin_2.BLIF un8_ciin +11 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_41_0 +11 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un2_ds_030 +11 1 +.names N_13.BLIF N_13_i +0 1 .names N_13_i.BLIF RST_c.BLIF N_27_0 11 1 -.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin -11 1 .names inst_LDS_000_INT.BLIF LDS_000_INT_i 0 1 -.names un21_fpu_cs_1.BLIF N_282_0.BLIF un21_fpu_cs -11 1 .names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un1_LDS_000_INT_0 11 1 -.names un21_berr_1_0.BLIF N_282_0.BLIF un21_berr -11 1 .names inst_UDS_000_INT.BLIF UDS_000_INT_i 0 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un2_ds_030 -11 1 .names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un1_UDS_000_INT_0 11 1 -.names AS_030_000_SYNC_i.BLIF CLK_000_D_4_.BLIF N_96_0_1 +.names inst_BGACK_030_INT_D.BLIF AS_030_D1_i.BLIF N_104_0_1 11 1 -.names clk_000_d_i_3__n.BLIF nEXP_SPACE_c.BLIF N_96_0_2 +.names inst_BGACK_030_INTreg.BLIF N_85_0.BLIF N_104_0_2 11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_282_0_1 +.names N_85_0.BLIF CLK_000_D_4_.BLIF N_100_0_1 11 1 -.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_282_0_2 +.names AS_030_000_SYNC_i.BLIF clk_000_d_i_3__n.BLIF N_100_0_2 11 1 -.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_282_0_3 +.names N_192_i.BLIF RST_c.BLIF N_113_i_1 11 1 -.names N_282_0_1.BLIF N_282_0_2.BLIF N_282_0_4 +.names N_79.BLIF N_193_i.BLIF N_113_i_2 +11 1 +.names N_99.BLIF N_79_i.BLIF N_107_0_1 +11 1 +.names BERR_c.BLIF N_202_i.BLIF N_99_i_1 11 1 .names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n 11 1 -.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 +.names N_82_i.BLIF N_83_i.BLIF N_202_1 11 1 -.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 +.names VMA_INT_i.BLIF VPA_D_i.BLIF N_202_2 11 1 -.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 +.names AS_030_i.BLIF a_decode_c_17__n.BLIF N_228_1 11 1 -.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 +.names a_decode_i_16__n.BLIF a_decode_i_18__n.BLIF N_228_2 11 1 -.names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 +.names fc_c_1__n.BLIF a_decode_i_19__n.BLIF N_228_3 11 1 -.names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 +.names N_228_1.BLIF N_228_2.BLIF N_228_4 11 1 -.names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 +.names N_228_3.BLIF fc_c_0__n.BLIF N_228_5 11 1 -.names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 +.names N_79_i.BLIF N_229.BLIF N_150_1 11 1 -.names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_150_2 11 1 -.names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 +.names N_80_i.BLIF N_82_i.BLIF N_126_1 11 1 -.names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 -11 1 -.names N_80_i.BLIF N_82_i.BLIF N_201_1 -11 1 -.names VMA_INT_i.BLIF VPA_D_i.BLIF N_201_2 -11 1 -.names BERR_c.BLIF N_201_i.BLIF N_131_i_1 -11 1 -.names N_68_i.BLIF N_131.BLIF N_134_0_1 -11 1 -.names N_68.BLIF N_141_i.BLIF N_113_i_1 -11 1 -.names N_142_i.BLIF RST_c.BLIF N_113_i_2 -11 1 -.names N_68_i.BLIF N_208.BLIF N_144_1 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_126_2 11 1 .names pos_clk_ipl_1_n.BLIF N_188_i.BLIF pos_clk_ipl_n 11 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_144_2 +.names AS_030_D0_i.BLIF a_decode_c_20__n.BLIF un8_ciin_1 11 1 -.names N_72_i.BLIF N_82_i.BLIF N_143_1 +.names a_decode_c_21__n.BLIF N_201_1.BLIF un8_ciin_2 11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_143_2 +.names a_decode_c_22__n.BLIF a_decode_c_23__n.BLIF N_201_1_1 11 1 -.names AS_030_D1_i.BLIF inst_BGACK_030_INT_D.BLIF N_163_1 +.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF N_201_1_2 11 1 -.names N_282.BLIF sm_amiga_i_i_7__n.BLIF N_163_2 +.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF N_201_1_3 11 1 -.names N_163_1.BLIF N_163_2.BLIF N_163_3 +.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF N_201_1_4 11 1 -.names un21_berr_1.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1 +.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF N_201_1_5 11 1 -.names un21_berr_1.BLIF FPU_SENSE_c.BLIF un21_berr_1_0 +.names N_201_1_1.BLIF N_201_1_2.BLIF N_201_1_6 11 1 -.names AS_000_i.BLIF N_220_i.BLIF pos_clk_cycle_dma_5_1_1__n +.names N_201_1_3.BLIF N_201_1_4.BLIF N_201_1_7 11 1 -.names N_68_i.BLIF CYCLE_DMA_0_.BLIF N_199_1 +.names N_201_1_6.BLIF N_201_1_7.BLIF N_201_1_8 +11 1 +.names a_decode_c_19__n.BLIF a_decode_c_21__n.BLIF N_201_1_0 +11 1 +.names a_decode_i_20__n.BLIF N_201_1.BLIF N_201_2 +11 1 +.names AS_000_i.BLIF N_39_1_i.BLIF pos_clk_cycle_dma_5_1_1__n +11 1 +.names N_79_i.BLIF CYCLE_DMA_0_.BLIF N_176_1 11 1 .names CLK_EXP_i.BLIF inst_CLK_OUT_PRE_D.BLIF AS_000_DMA_1_sqmuxa_1 11 1 -.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF N_140_1 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF N_198_1 11 1 -.names AS_000_i.BLIF N_198_i.BLIF N_66_i_1 +.names AMIGA_DS_i.BLIF AS_000_i.BLIF N_72_i_1 11 1 -.names N_199_i.BLIF N_220_i.BLIF N_66_i_2 -11 1 -.names AMIGA_DS_i.BLIF AS_000_i.BLIF N_205_i_1 -11 1 -.names N_140_i.BLIF pos_clk_un2_n.BLIF N_205_i_2 -11 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_180_1 -11 1 -.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_180_2 +.names N_198_i.BLIF pos_clk_un2_n.BLIF N_72_i_2 11 1 .names pos_clk_un9_clk_000_pe_0_n.BLIF pos_clk_un9_clk_000_pe_n 0 1 -.names inst_AS_030_D0.BLIF CLK_000_D_0_.BLIF N_59_i_1 +.names AS_000_i.BLIF N_39_1_i.BLIF N_206_i_1 11 1 -.names N_267_i.BLIF N_268_i.BLIF N_127_i_1 +.names N_175_i.BLIF N_176_i.BLIF N_206_i_2 11 1 -.names N_93.BLIF N_266_i.BLIF N_123_i_1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_186_1 11 1 -.names N_68.BLIF N_186_i.BLIF N_121_i_1 +.names RW_000_c.BLIF nEXP_SPACE_i.BLIF N_186_2 11 1 -.names N_72.BLIF N_185_i.BLIF N_119_i_1 +.names inst_AS_030_D0.BLIF CLK_000_D_0_.BLIF N_74_i_1 11 1 .names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6 1- 1 -1 1 -.names N_183_i.BLIF N_184_i.BLIF N_117_i_1 +.names N_79.BLIF N_197_i.BLIF N_121_i_1 11 1 -.names N_72.BLIF N_182_i.BLIF N_115_i_1 +.names N_195_i.BLIF N_196_i.BLIF N_117_i_1 11 1 -.names N_72.BLIF N_181_i.BLIF N_111_i_1 +.names N_80.BLIF N_194_i.BLIF N_115_i_1 11 1 -.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_165_1 +.names N_190_i.BLIF N_191_i.BLIF N_127_i_1 11 1 .names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_13 1- 1 -1 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_162_1 +.names N_84.BLIF N_214_i.BLIF N_123_i_1 11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_148_1 +.names N_80.BLIF N_159_i.BLIF N_119_i_1 11 1 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_18 1- 1 -1 1 -.names N_189_i.BLIF N_187_i.BLIF pos_clk_ipl_1_n +.names N_80.BLIF N_158_i.BLIF N_111_i_1 11 1 .names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_19 1- 1 -1 1 -.names AS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n -0 1 +.names N_228.BLIF BGACK_000_c.BLIF un21_berr_1 +11 1 .names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_20 1- 1 -1 1 +.names N_228.BLIF BGACK_000_c.BLIF un21_fpu_cs_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF AS_030_000_SYNC_i.BLIF N_172_1 +11 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_161_1 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_153_1 +11 1 +.names N_189_i.BLIF N_187_i.BLIF pos_clk_ipl_1_n +11 1 +.names AS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n +0 1 .names inst_DS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n 11 1 -.names N_205.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +.names N_72.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n 11 1 .names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n 0 1 .names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n 11 1 -.names N_205.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +.names N_72.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n 11 1 .names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n 0 1 @@ -652,12 +667,6 @@ un1_amiga_bus_enable_low 11 1 .names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n 11 1 -.names RST_c.BLIF as_030_d1_0_un3_n -0 1 -.names inst_AS_030_D0.BLIF RST_c.BLIF as_030_d1_0_un1_n -11 1 -.names inst_AS_030_D1.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un0_n -11 1 .names un1_SM_AMIGA_0_sqmuxa_1.BLIF rw_000_int_0_un3_n 0 1 .names pos_clk_rw_000_int_5_n.BLIF un1_SM_AMIGA_0_sqmuxa_1.BLIF \ @@ -665,581 +674,586 @@ rw_000_int_0_un1_n 11 1 .names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 -.names N_244.BLIF as_030_000_sync_0_un3_n -0 1 -.names AS_030_c.BLIF N_244.BLIF as_030_000_sync_0_un1_n -11 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 .names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 .names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n -0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 .names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n 0 1 -.names N_68.BLIF cpu_est_0_1__un3_n +.names N_204.BLIF as_030_000_sync_0_un3_n 0 1 .names cpu_est_2_0_3__n.BLIF cpu_est_2_3__n 0 1 -.names cpu_est_1_.BLIF N_68.BLIF cpu_est_0_1__un1_n +.names inst_AS_030_000_SYNC.BLIF N_204.BLIF as_030_000_sync_0_un1_n +11 1 +.names AS_030_c.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names N_79.BLIF cpu_est_0_1__un3_n +0 1 +.names cpu_est_1_.BLIF N_79.BLIF cpu_est_0_1__un1_n 11 1 .names cpu_est_2_1__n.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 -.names N_68.BLIF cpu_est_0_2__un3_n +.names N_205_0.BLIF N_205 0 1 -.names cpu_est_2_.BLIF N_68.BLIF cpu_est_0_2__un1_n +.names N_79.BLIF cpu_est_0_2__un3_n +0 1 +.names N_74_i.BLIF N_74 +0 1 +.names cpu_est_2_.BLIF N_79.BLIF cpu_est_0_2__un1_n 11 1 -.names N_60_0.BLIF N_60 +.names N_78_0.BLIF N_78 0 1 .names cpu_est_2_2__n.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n 11 1 -.names N_63_0.BLIF N_63 +.names N_79_i.BLIF N_79 0 1 -.names N_68.BLIF cpu_est_0_3__un3_n -0 1 -.names N_220_i.BLIF RW_000_i.BLIF N_126 -11 1 -.names cpu_est_3_.BLIF N_68.BLIF cpu_est_0_3__un1_n -11 1 -.names a_c_1__n.BLIF N_220_i.BLIF N_150 -11 1 -.names cpu_est_2_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names a_i_1__n.BLIF N_220_i.BLIF N_151 -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_219 -11 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n -11 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF N_175 -11 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n -0 1 -.names N_59_i.BLIF N_59 -0 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n -11 1 -.names N_68_i.BLIF N_68 -0 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names N_72_i.BLIF N_72 -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +.names N_79.BLIF cpu_est_0_3__un3_n 0 1 .names N_80_i.BLIF N_80 0 1 +.names cpu_est_3_.BLIF N_79.BLIF cpu_est_0_3__un1_n +11 1 +.names N_83_i.BLIF N_83 +0 1 +.names cpu_est_2_3__n.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names N_84_i.BLIF N_84 +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names N_89_i.BLIF N_89 +0 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names N_95_i.BLIF N_95 +0 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names N_96_i.BLIF N_96 +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names N_97_i.BLIF N_97 +0 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names N_105_0.BLIF N_105 +0 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names N_126_1.BLIF N_126_2.BLIF N_126 +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names N_150_1.BLIF N_150_2.BLIF N_150 +11 1 .names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n 11 1 -.names N_93_i.BLIF N_93 -0 1 +.names N_153_1.BLIF cpu_est_i_3__n.BLIF N_153 +11 1 .names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 -.names N_98_i.BLIF N_98 -0 1 -.names N_63.BLIF ds_000_enable_0_un3_n -0 1 -.names N_107_i.BLIF N_107 -0 1 -.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_63.BLIF ds_000_enable_0_un1_n +.names N_89.BLIF cpu_est_2_.BLIF N_156 11 1 -.names N_128_i.BLIF N_128 +.names N_78.BLIF ds_000_enable_0_un3_n 0 1 +.names N_89_i.BLIF cpu_est_2_.BLIF N_157 +11 1 +.names un1_DS_000_ENABLE_0_sqmuxa.BLIF N_78.BLIF ds_000_enable_0_un1_n +11 1 +.names N_97.BLIF sm_amiga_i_0__n.BLIF N_158 +11 1 .names inst_DS_000_ENABLE.BLIF ds_000_enable_0_un3_n.BLIF \ ds_000_enable_0_un0_n 11 1 -.names N_131_i.BLIF N_131 -0 1 -.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n -0 1 -.names N_134_0.BLIF N_134 -0 1 -.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n -11 1 -.names N_135_0.BLIF N_135 -0 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names N_72.BLIF SM_AMIGA_2_.BLIF N_141 +.names N_105.BLIF sm_amiga_i_4__n.BLIF N_159 11 1 .names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c 0 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_142 -11 1 -.names N_143_1.BLIF N_143_2.BLIF N_143 -11 1 -.names N_144_1.BLIF N_144_2.BLIF N_144 -11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_145 -11 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF N_146 -11 1 -.names N_205_i_1.BLIF N_205_i_2.BLIF N_205_i -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_147 -11 1 -.names N_140.BLIF N_140_i +.names pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un3_n 0 1 -.names N_148_1.BLIF cpu_est_i_3__n.BLIF N_148 +.names N_82_i.BLIF cpu_est_3_.BLIF N_160 11 1 -.names inst_AMIGA_DS.BLIF AMIGA_DS_i +.names cpu_est_i_1__n.BLIF pos_clk_un9_clk_000_pe_n.BLIF vma_int_0_un1_n +11 1 +.names N_161_1.BLIF cpu_est_i_3__n.BLIF N_161 +11 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names N_172_1.BLIF AS_030_i.BLIF N_172 +11 1 +.names RST_c.BLIF as_030_d1_0_un3_n 0 1 -.names N_98.BLIF cpu_est_2_.BLIF N_149 +.names N_225.BLIF RST_c.BLIF N_177 11 1 -.names N_98_i.BLIF cpu_est_2_.BLIF N_154 +.names inst_AS_030_D0.BLIF RST_c.BLIF as_030_d1_0_un1_n 11 1 -.names N_199.BLIF N_199_i +.names N_97_i.BLIF RST_c.BLIF N_178 +11 1 +.names N_181.BLIF N_181_i 0 1 -.names N_82_i.BLIF cpu_est_3_.BLIF N_155 +.names inst_AS_030_D1.BLIF as_030_d1_0_un3_n.BLIF as_030_d1_0_un0_n +11 1 +.names N_224.BLIF RST_c.BLIF N_179 +11 1 +.names N_181_i.BLIF RST_c.BLIF N_37_0 +11 1 +.names N_84_i.BLIF RST_c.BLIF N_180 +11 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF N_182 +11 1 +.names N_176.BLIF N_176_i +0 1 +.names BGACK_030_INT_i.BLIF N_96.BLIF N_183 +11 1 +.names N_175.BLIF N_175_i +0 1 +.names BGACK_030_INT_i.BLIF N_96_i.BLIF N_184 +11 1 +.names N_72_i_1.BLIF N_72_i_2.BLIF N_72_i +11 1 +.names N_39_1_i.BLIF RW_000_i.BLIF N_212 11 1 .names N_198.BLIF N_198_i 0 1 -.names N_162_1.BLIF cpu_est_i_3__n.BLIF N_162 +.names N_39_1_i.BLIF N_81.BLIF N_213 11 1 -.names N_180.BLIF N_180_i +.names inst_AMIGA_DS.BLIF AMIGA_DS_i 0 1 -.names N_165_1.BLIF AS_030_i.BLIF N_165 +.names N_100.BLIF sm_amiga_i_6__n.BLIF N_214 11 1 -.names N_262.BLIF N_262_i +.names N_186.BLIF N_186_i 0 1 -.names BGACK_030_INT_i.BLIF N_128.BLIF N_259 +.names N_100.BLIF sm_amiga_i_i_7__n.BLIF N_190 11 1 -.names N_180_i.BLIF N_262_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +.names N_185.BLIF N_185_i +0 1 +.names N_80_i.BLIF SM_AMIGA_0_.BLIF N_191 11 1 -.names BGACK_030_INT_i.BLIF N_128_i.BLIF N_260 +.names N_185_i.BLIF N_186_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names N_107.BLIF sm_amiga_i_2__n.BLIF N_194 11 1 .names cycle_dma_i_0__n.BLIF cycle_dma_i_1__n.BLIF pos_clk_un2_i_n 11 1 -.names N_129.BLIF sm_amiga_i_0__n.BLIF N_181 +.names N_79_i.BLIF N_99.BLIF N_195 11 1 .names N_3.BLIF N_3_i 0 1 -.names N_134.BLIF sm_amiga_i_2__n.BLIF N_182 +.names N_95.BLIF sm_amiga_i_3__n.BLIF N_196 11 1 .names N_3_i.BLIF RST_c.BLIF N_32_0 11 1 -.names N_68_i.BLIF N_131.BLIF N_183 +.names N_84.BLIF sm_amiga_i_5__n.BLIF N_197 11 1 .names N_4.BLIF N_4_i 0 1 -.names N_107.BLIF sm_amiga_i_3__n.BLIF N_184 +.names N_202_1.BLIF N_202_2.BLIF N_202 11 1 .names N_4_i.BLIF RST_c.BLIF N_31_0 11 1 -.names N_135.BLIF sm_amiga_i_4__n.BLIF N_185 +.names N_84_i.BLIF RW_c.BLIF N_220 11 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_220_i +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_39_1_i 11 1 -.names N_93.BLIF sm_amiga_i_5__n.BLIF N_186 +.names AS_000_INT_i.BLIF AS_030_i.BLIF N_224 +11 1 +.names N_39_1_i.BLIF N_81_i.BLIF N_34_0 +11 1 +.names AS_030_i.BLIF DSACK1_INT_i.BLIF N_225 11 1 .names BG_030_c.BLIF BG_030_c_i 0 1 -.names N_132.BLIF sm_amiga_i_6__n.BLIF N_266 +.names N_228_4.BLIF N_228_5.BLIF N_228 11 1 -.names BG_030_c_i.BLIF N_59.BLIF pos_clk_un9_bg_030_0_n +.names BG_030_c_i.BLIF N_74.BLIF pos_clk_un9_bg_030_0_n 11 1 -.names N_96.BLIF sm_amiga_i_i_7__n.BLIF N_267 +.names N_89_i.BLIF cpu_est_i_2__n.BLIF N_229 11 1 .names N_17.BLIF N_17_i 0 1 -.names N_72_i.BLIF SM_AMIGA_0_.BLIF N_268 +.names N_201_1_8.BLIF N_201_1_5.BLIF N_201_1 11 1 .names N_17_i.BLIF RST_c.BLIF N_24_0 11 1 -.names N_68.BLIF cpu_est_i_0__n.BLIF N_190 -11 1 +.names N_104_0.BLIF N_104 +0 1 .names N_16.BLIF N_16_i 0 1 -.names N_68_i.BLIF cpu_est_0_.BLIF N_191 -11 1 +.names N_100_0.BLIF N_100 +0 1 .names N_16_i.BLIF RST_c.BLIF N_25_0 11 1 -.names N_201_1.BLIF N_201_2.BLIF N_201 +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_171 11 1 .names N_15.BLIF N_15_i 0 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_202 -11 1 +.names N_204_0.BLIF N_204 +0 1 .names N_15_i.BLIF RST_c.BLIF N_26_0 11 1 -.names N_93_i.BLIF RW_c.BLIF N_203 +.names AS_030_i.BLIF N_104.BLIF N_164 11 1 .names N_12.BLIF N_12_i 0 1 -.names N_98_i.BLIF cpu_est_i_2__n.BLIF N_208 +.names N_79.BLIF cpu_est_i_0__n.BLIF N_162 11 1 .names N_12_i.BLIF RST_c.BLIF N_28_0 11 1 -.names N_163_3.BLIF un1_dsack1_i.BLIF N_163 -11 1 -.names N_11.BLIF N_11_i -0 1 -.names N_282_0.BLIF N_282 -0 1 -.names N_11_i.BLIF RST_c.BLIF N_29_0 -11 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un21_berr_1 +.names N_79_i.BLIF cpu_est_0_.BLIF N_163 11 1 .names N_5.BLIF N_5_i 0 1 -.names N_132_0.BLIF N_132 +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n 0 1 .names N_5_i.BLIF RST_c.BLIF N_30_0 11 1 -.names N_96_0.BLIF N_96 -0 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_152 +11 1 .names a_c_0__n.BLIF a_c_i_0__n 0 1 -.names N_129_i.BLIF N_129 -0 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 -0 1 -.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ -pos_clk_un10_sm_amiga_i_n -11 1 -.names N_175.BLIF RST_c.BLIF N_169 -11 1 -.names inst_BGACK_030_INTreg.BLIF nEXP_SPACE_c.BLIF un1_dsack1_i -11 1 -.names N_93_i.BLIF RST_c.BLIF N_170 -11 1 -.names inst_BGACK_030_INTreg.BLIF RST_c.BLIF N_69_i -11 1 -.names N_219.BLIF RST_c.BLIF N_167 -11 1 -.names N_163.BLIF N_163_i -0 1 -.names N_129_i.BLIF RST_c.BLIF N_168 -11 1 -.names AS_030_i.BLIF N_163_i.BLIF N_244_0 -11 1 -.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n -0 1 -.names N_164.BLIF N_164_i -0 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n -0 1 -.names N_165.BLIF N_165_i -0 1 -.names AS_000_c.BLIF N_68_i.BLIF N_274 -11 1 -.names N_164_i.BLIF N_165_i.BLIF un11_amiga_bus_enable_high_i -11 1 -.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF BGACK_030_INT_i.BLIF N_164 -11 1 -.names un10_ciin.BLIF un10_ciin_i -0 1 -.names N_244_0.BLIF N_244 -0 1 -.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_60_0 -11 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_5 -1- 1 --1 1 -.names N_274.BLIF N_274_i -0 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_11 1- 1 -1 1 -.names BGACK_000_c.BLIF N_274_i.BLIF pos_clk_un6_bgack_000_0_n +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names N_201_1_0.BLIF N_201_2.BLIF N_201 11 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ +pos_clk_un10_sm_amiga_i_n +11 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_193 +11 1 +.names N_231.BLIF N_231_i +0 1 +.names N_80.BLIF SM_AMIGA_2_.BLIF N_192 +11 1 +.names BGACK_000_c.BLIF N_231_i.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names N_107_0.BLIF N_107 +0 1 +.names AS_030_i.BLIF RST_c.BLIF N_40_0 +11 1 +.names N_99_i.BLIF N_99 +0 1 +.names N_84.BLIF N_98_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +11 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_219 +11 1 +.names RW_c.BLIF RW_c_i +0 1 +.names N_81_i.BLIF N_81 +0 1 +.names N_98_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n +11 1 +.names pos_clk_rw_000_int_5_0_n.BLIF pos_clk_rw_000_int_5_n +0 1 +.names N_201.BLIF N_201_i +0 1 +.names un1_SM_AMIGA_0_sqmuxa_1_0.BLIF un1_SM_AMIGA_0_sqmuxa_1 +0 1 +.names a_c_1__n.BLIF N_201_i.BLIF N_81_i +11 1 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +0 1 +.names N_219.BLIF N_219_i +0 1 +.names AS_000_c.BLIF N_79_i.BLIF N_231 +11 1 +.names N_202.BLIF N_202_i +0 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_5 +1- 1 +-1 1 +.names N_191.BLIF N_191_i +0 1 .names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_12 1- 1 -1 1 -.names RW_c.BLIF RW_c_i -0 1 +.names N_191_i.BLIF SM_AMIGA_i_7_.BLIF N_98_i +11 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_15 1- 1 -1 1 -.names N_246_i.BLIF RW_c_i.BLIF pos_clk_rw_000_int_5_0_n +.names N_99_i_1.BLIF N_219_i.BLIF N_99_i 11 1 .names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_16 1- 1 -1 1 -.names N_168.BLIF N_168_i -0 1 +.names N_107_0_1.BLIF SM_AMIGA_3_.BLIF N_107_0 +11 1 .names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_17 1- 1 -1 1 -.names N_167.BLIF N_167_i +.names N_192.BLIF N_192_i 0 1 .names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n 0 1 -.names N_170.BLIF N_170_i +.names N_193.BLIF N_193_i 0 1 .names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 1- 1 -1 1 -.names N_169.BLIF N_169_i +.names N_72_i.BLIF N_72 0 1 -.names N_205_i.BLIF N_205 +.names N_11.BLIF N_11_i 0 1 -.names AS_000_DMA_1_sqmuxa_1.BLIF N_205_i.BLIF AS_000_DMA_1_sqmuxa +.names AS_000_DMA_1_sqmuxa_1.BLIF N_72_i.BLIF AS_000_DMA_1_sqmuxa 11 1 -.names AS_030_i.BLIF RST_c.BLIF N_38_0 +.names N_11_i.BLIF RST_c.BLIF N_29_0 11 1 .names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_4 1- 1 -1 1 -.names N_93.BLIF N_246_i.BLIF un1_SM_AMIGA_0_sqmuxa_1_0 +.names VPA_c.BLIF VPA_c_i +0 1 +.names RST_c.BLIF VPA_c_i.BLIF N_44_0 11 1 -.names N_199_1.BLIF cycle_dma_i_1__n.BLIF N_199 -11 1 -.names N_282_0_4.BLIF N_282_0_3.BLIF N_282_0 +.names N_176_1.BLIF cycle_dma_i_1__n.BLIF N_176 11 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 .names pos_clk_un2_i_n.BLIF pos_clk_un2_n 0 1 -.names CLK_000_D_3_.BLIF clk_000_d_i_3__n +.names DTACK_c_i.BLIF RST_c.BLIF N_45_0 +11 1 +.names cycle_dma_i_0__n.BLIF N_79.BLIF N_175 +11 1 +.names N_152.BLIF N_152_i 0 1 -.names N_140_1.BLIF RW_000_i.BLIF N_140 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_185 11 1 -.names N_96_0_1.BLIF N_96_0_2.BLIF N_96_0 -11 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_262 -11 1 -.names N_68_i.BLIF SM_AMIGA_1_.BLIF N_129_i -11 1 -.names cycle_dma_i_0__n.BLIF N_68.BLIF N_198 -11 1 -.names N_268.BLIF N_268_i +.names N_153.BLIF N_153_i 0 1 -.names N_180_1.BLIF N_180_2.BLIF N_180 +.names N_198_1.BLIF RW_000_i.BLIF N_198 11 1 -.names N_268_i.BLIF SM_AMIGA_i_7_.BLIF N_246_i +.names N_152_i.BLIF N_153_i.BLIF cpu_est_2_0_1__n 11 1 +.names N_186_1.BLIF N_186_2.BLIF N_186 +11 1 +.names N_163.BLIF N_163_i +0 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_181 +11 1 +.names N_162.BLIF N_162_i +0 1 .names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i 0 1 -.names N_96_0.BLIF sm_amiga_i_i_7__n.BLIF N_132_0 -11 1 .names un21_fpu_cs.BLIF un21_fpu_cs_i 0 1 +.names inst_BGACK_030_INTreg.BLIF RST_c.BLIF N_203_i +11 1 .names AS_000_c.BLIF AS_000_i 0 1 -.names N_142.BLIF N_142_i -0 1 +.names inst_BGACK_030_INTreg.BLIF nEXP_SPACE_c.BLIF un1_dsack1_i +11 1 .names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i 0 1 -.names N_141.BLIF N_141_i +.names N_164.BLIF N_164_i 0 1 .names nEXP_SPACE_c.BLIF nEXP_SPACE_i 0 1 -.names N_68_i.BLIF SM_AMIGA_5_.BLIF N_135_0 +.names N_228.BLIF N_228_i +0 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names N_164_i.BLIF N_228_i.BLIF N_204_0 11 1 .names CYCLE_DMA_0_.BLIF cycle_dma_i_0__n 0 1 -.names N_134_0_1.BLIF SM_AMIGA_3_.BLIF N_134_0 -11 1 -.names RW_000_c.BLIF RW_000_i +.names N_171.BLIF N_171_i 0 1 -.names N_131_i_1.BLIF N_202_i.BLIF N_131_i -11 1 .names CLK_OUT_INTreg.BLIF CLK_EXP_i 0 1 -.names LDS_000_c.BLIF LDS_000_c_i +.names N_172.BLIF N_172_i 0 1 .names CYCLE_DMA_1_.BLIF cycle_dma_i_1__n 0 1 -.names UDS_000_c.BLIF UDS_000_c_i -0 1 +.names N_171_i.BLIF N_172_i.BLIF un11_amiga_bus_enable_high_i +11 1 .names inst_DS_000_DMA.BLIF DS_000_DMA_i 0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_128_i +.names sm_amiga_i_i_7__n.BLIF nEXP_SPACE_c.BLIF N_85_0 11 1 .names inst_AS_000_DMA.BLIF AS_000_DMA_i 0 1 -.names N_72_i.BLIF SM_AMIGA_4_.BLIF N_107_i -11 1 -.names a_c_1__n.BLIF a_i_1__n -0 1 -.names N_203.BLIF N_203_i -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names N_107.BLIF N_203_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0 -11 1 -.names a_decode_c_19__n.BLIF a_decode_i_19__n -0 1 -.names N_201.BLIF N_201_i -0 1 -.names a_decode_c_18__n.BLIF a_decode_i_18__n -0 1 -.names N_202.BLIF N_202_i -0 1 -.names a_decode_c_16__n.BLIF a_decode_i_16__n -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i -0 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_98_i -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names N_72_i.BLIF SM_AMIGA_6_.BLIF N_93_i -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_82_i -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_80_i -11 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_72_i -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_68_i -11 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names N_59_i_1.BLIF nEXP_SPACE_c.BLIF N_59_i -11 1 -.names inst_DSACK1_INT.BLIF DSACK1_INT_i -0 1 -.names N_190.BLIF N_190_i -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names N_191.BLIF N_191_i -0 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names inst_AS_030_D1.BLIF AS_030_D1_i -0 1 -.names N_267.BLIF N_267_i -0 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names N_266.BLIF N_266_i -0 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_186.BLIF N_186_i -0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names N_185.BLIF N_185_i -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names N_183.BLIF N_183_i -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names N_184.BLIF N_184_i -0 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names N_182.BLIF N_182_i -0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names N_181.BLIF N_181_i -0 1 -.names ahigh_c_30__n.BLIF ahigh_i_30__n -0 1 -.names ahigh_c_31__n.BLIF ahigh_i_31__n -0 1 -.names N_260.BLIF N_260_i -0 1 -.names ahigh_c_28__n.BLIF ahigh_i_28__n -0 1 -.names N_260_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n -11 1 -.names ahigh_c_29__n.BLIF ahigh_i_29__n -0 1 -.names N_259.BLIF N_259_i -0 1 -.names ahigh_c_26__n.BLIF ahigh_i_26__n -0 1 -.names N_259_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n -11 1 -.names ahigh_c_27__n.BLIF ahigh_i_27__n -0 1 -.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF N_63_0 -11 1 -.names ahigh_c_24__n.BLIF ahigh_i_24__n -0 1 -.names N_155.BLIF N_155_i +.names CLK_000_D_3_.BLIF clk_000_d_i_3__n 0 1 .names ahigh_c_25__n.BLIF ahigh_i_25__n 0 1 -.names N_162.BLIF N_162_i +.names N_100_0_1.BLIF N_100_0_2.BLIF N_100_0 +11 1 +.names ahigh_c_24__n.BLIF ahigh_i_24__n +0 1 +.names inst_AS_030_D1.BLIF AS_030_D1_i +0 1 +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 +.names N_104_0_1.BLIF N_104_0_2.BLIF N_104_0 +11 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names N_79_i.BLIF SM_AMIGA_5_.BLIF N_105_0 +11 1 +.names ahigh_c_29__n.BLIF ahigh_i_29__n +0 1 +.names N_79_i.BLIF SM_AMIGA_1_.BLIF N_97_i +11 1 +.names ahigh_c_28__n.BLIF ahigh_i_28__n +0 1 +.names LDS_000_c.BLIF LDS_000_c_i +0 1 +.names ahigh_c_31__n.BLIF ahigh_i_31__n +0 1 +.names UDS_000_c.BLIF UDS_000_c_i +0 1 +.names ahigh_c_30__n.BLIF ahigh_i_30__n +0 1 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_96_i +11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names N_80_i.BLIF SM_AMIGA_4_.BLIF N_95_i +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_220.BLIF N_220_i +0 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names N_95.BLIF N_220_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0 +11 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_89_i +11 1 +.names a_decode_c_20__n.BLIF a_decode_i_20__n +0 1 +.names N_80_i.BLIF SM_AMIGA_6_.BLIF N_84_i +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_83_i +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_82_i +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF N_80_i +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_79_i +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names AS_030_i.BLIF un1_DS_000_ENABLE_0_sqmuxa_0.BLIF N_78_0 +11 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names N_74_i_1.BLIF nEXP_SPACE_c.BLIF N_74_i +11 1 +.names cpu_est_3_.BLIF cpu_est_i_3__n +0 1 +.names N_197.BLIF N_197_i +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names N_195.BLIF N_195_i +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names N_196.BLIF N_196_i +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names N_194.BLIF N_194_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names N_190.BLIF N_190_i +0 1 +.names inst_DSACK1_INT.BLIF DSACK1_INT_i +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_214.BLIF N_214_i +0 1 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names a_decode_c_19__n.BLIF a_decode_i_19__n +0 1 +.names N_184.BLIF N_184_i +0 1 +.names a_decode_c_18__n.BLIF a_decode_i_18__n +0 1 +.names N_184_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names N_183.BLIF N_183_i +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names N_183_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names N_182.BLIF N_182_i 0 1 .names G_105.BLIF N_187_i 0 1 -.names N_155_i.BLIF N_162_i.BLIF un5_e_0 +.names N_182_i.BLIF RST_c.BLIF N_38_0 11 1 .names G_106.BLIF N_188_i 0 1 -.names N_154.BLIF N_154_i +.names N_179.BLIF N_179_i 0 1 .names G_107.BLIF N_189_i 0 1 -.names N_80.BLIF N_154_i.BLIF cpu_est_2_0_3__n -11 1 -.names N_149.BLIF N_149_i +.names N_180.BLIF N_180_i 0 1 -.names N_208.BLIF N_208_i +.names N_177.BLIF N_177_i 0 1 -.names N_149_i.BLIF N_208_i.BLIF cpu_est_2_0_2__n -11 1 -.names N_147.BLIF N_147_i +.names N_178.BLIF N_178_i 0 1 .names un2_ds_030.BLIF un2_ds_030_i 0 1 -.names N_148.BLIF N_148_i +.names N_225.BLIF N_225_i 0 1 -.names N_219.BLIF N_219_i +.names un8_ciin.BLIF un8_ciin_i 0 1 -.names N_147_i.BLIF N_148_i.BLIF cpu_est_2_0_1__n +.names N_224.BLIF N_224_i +0 1 +.names nEXP_SPACE_i.BLIF un8_ciin_i.BLIF N_205_0 11 1 -.names N_175.BLIF N_175_i -0 1 -.names N_146.BLIF N_146_i -0 1 .names un3_as_030.BLIF un3_as_030_i 0 1 -.names N_146_i.BLIF RST_c.BLIF N_36_0 -11 1 -.names N_145.BLIF N_145_i +.names N_160.BLIF N_160_i 0 1 -.names N_145_i.BLIF RST_c.BLIF N_35_0 -11 1 -.names N_143.BLIF N_143_i +.names N_161.BLIF N_161_i 0 1 -.names N_144.BLIF N_144_i -0 1 -.names N_143_i.BLIF N_144_i.BLIF pos_clk_un9_clk_000_pe_0_n +.names N_160_i.BLIF N_161_i.BLIF un5_e_0 11 1 -.names N_20.BLIF N_20_i +.names N_159.BLIF N_159_i +0 1 +.names N_158.BLIF N_158_i 0 1 .names IPL_030DFF_2_reg.BLIF IPL_030_2_ 1 1 @@ -1262,7 +1276,7 @@ pos_clk_un10_sm_amiga_i_n .names un21_fpu_cs_i.BLIF FPU_CS 1 1 0 0 -.names N_219_i.BLIF DSACK1 +.names N_225_i.BLIF DSACK1 1 1 0 0 .names vcc_n_n.BLIF AVEC @@ -1286,7 +1300,7 @@ pos_clk_un10_sm_amiga_i_n .names un11_amiga_bus_enable_high_i.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 0 0 -.names un10_ciin.BLIF CIIN +.names un8_ciin.BLIF CIIN 1 1 0 0 .names IPL_030DFF_1_reg.BLIF IPL_030_1_ @@ -1295,6 +1309,18 @@ pos_clk_un10_sm_amiga_i_n .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF IPL_D0_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -1310,6 +1336,15 @@ pos_clk_un10_sm_amiga_i_n .names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 0 0 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_3_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C 1 1 0 0 @@ -1325,16 +1360,10 @@ pos_clk_un10_sm_amiga_i_n .names CLK_OSZI_c.BLIF IPL_D0_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF IPL_D0_2_.C +.names CLK_000.BLIF CLK_000_D_0_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C 1 1 0 0 .names CLK_000_D_0_.BLIF CLK_000_D_1_.D @@ -1376,24 +1405,30 @@ pos_clk_un10_sm_amiga_i_n .names CLK_OSZI_c.BLIF cpu_est_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF cpu_est_3_.C -1 1 -0 0 -.names CLK_000.BLIF CLK_000_D_0_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_D_0_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AMIGA_DS.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_VPA_D.C 1 1 0 0 @@ -1403,6 +1438,12 @@ pos_clk_un10_sm_amiga_i_n .names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_D1.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +0 0 .names CLK_OSZI_c.BLIF BG_000DFFreg.C 1 1 0 0 @@ -1427,33 +1468,6 @@ pos_clk_un10_sm_amiga_i_n .names CLK_OSZI_c.BLIF inst_DS_000_DMA.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AMIGA_DS.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_A0_DMA.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_D0.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_D1.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 @@ -1481,7 +1495,7 @@ pos_clk_un10_sm_amiga_i_n .names un3_as_030_i.BLIF AS_030 1 1 0 0 -.names N_175_i.BLIF AS_000 +.names N_224_i.BLIF AS_000 1 1 0 0 .names inst_RW_000_INT.BLIF RW_000 @@ -1691,16 +1705,16 @@ pos_clk_un10_sm_amiga_i_n .names BGACK_030_INT_i.BLIF AS_030.OE 1 1 0 0 -.names N_69_i.BLIF AS_000.OE +.names N_203_i.BLIF AS_000.OE 1 1 0 0 -.names N_69_i.BLIF RW_000.OE +.names N_203_i.BLIF RW_000.OE 1 1 0 0 -.names N_69_i.BLIF UDS_000.OE +.names N_203_i.BLIF UDS_000.OE 1 1 0 0 -.names N_69_i.BLIF LDS_000.OE +.names N_203_i.BLIF LDS_000.OE 1 1 0 0 .names BGACK_030_INT_i.BLIF SIZE_0_.OE @@ -1751,7 +1765,7 @@ pos_clk_un10_sm_amiga_i_n .names inst_BGACK_030_INTreg.BLIF VMA.OE 1 1 0 0 -.names N_60.BLIF CIIN.OE +.names N_205.BLIF CIIN.OE 1 1 0 0 .names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_105 @@ -1769,7 +1783,7 @@ pos_clk_un10_sm_amiga_i_n 10 1 11 0 00 0 -.names CYCLE_DMA_1_.BLIF N_199.BLIF G_91 +.names CYCLE_DMA_1_.BLIF N_176.BLIF G_91 01 1 10 1 11 0 diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index c1387ce..c72b8a4 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2017 12 30 0 43 31) + (timeStamp 2018 1 11 20 16 24) (author "Synopsys, Inc.") (program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R")) ) @@ -140,6 +140,14 @@ (port CIIN (direction OUTPUT)) ) (contents + (instance (rename IPL_D0_2 "IPL_D0[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -150,6 +158,12 @@ ) (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename IPL_030DFF_0 "IPL_030DFF[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename IPL_030DFF_1 "IPL_030DFF[1]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -160,13 +174,7 @@ ) (instance (rename IPL_D0_1 "IPL_D0[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename IPL_D0_2 "IPL_D0[2]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_D_0 "CLK_000_D[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_D_1 "CLK_000_D[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -186,22 +194,32 @@ ) (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_D_0 "CLK_000_D[0]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance AMIGA_BUS_ENABLE_DMA_HIGH (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance DSACK1_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AMIGA_DS (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance A0_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance RW_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_030_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance VPA_D (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance DTACK_D0 (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance DS_000_ENABLE (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance AS_030_D1 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance UDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance BG_000DFF (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance LDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) @@ -218,24 +236,6 @@ ) (instance DS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance DSACK1_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AMIGA_DS (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance A0_DMA (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance RW_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AS_030_D0 (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AMIGA_BUS_ENABLE_DMA_LOW (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AS_030_D1 (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance UDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance BGACK_030_INT_D (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance CLK_OUT_INT (viewRef prim (cellRef DFF (libraryRef mach))) @@ -319,95 +319,108 @@ (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_HIGH (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_3 "SM_AMIGA_srsts_i_0_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_3 "SM_AMIGA_srsts_i_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_2 "SM_AMIGA_srsts_i_0_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_2 "SM_AMIGA_srsts_i_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_0 "SM_AMIGA_srsts_i_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_0 "SM_AMIGA_srsts_i_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un11_amiga_bus_enable_high_0_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un11_amiga_bus_enable_high_0_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_0_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_0_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a2_0_1_1 "cpu_est_2_0_0_a2_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a2_0_1 "cpu_est_2_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a3_0_1_1 "cpu_est_2_0_0_a3_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a3_0_1 "cpu_est_2_0_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance G_108_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance G_108 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_as_000_dma6_i_0_0_2 "pos_clk.as_000_dma6_i_0_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_as_000_dma6_i_0_0 "pos_clk.as_000_dma6_i_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_iv_0_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_0_a3_i_1 "pos_clk.un6_bg_030_0_a3_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_0_a3_i "pos_clk.un6_bg_030_0_a3_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_1_0 "SM_AMIGA_nss_i_i_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_0 "SM_AMIGA_nss_i_i_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_6 "SM_AMIGA_srsts_i_0_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_6 "SM_AMIGA_srsts_i_0_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_5 "SM_AMIGA_srsts_i_0_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_5 "SM_AMIGA_srsts_i_0_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_4 "SM_AMIGA_srsts_i_0_0_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_4 "SM_AMIGA_srsts_i_0_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_fpu_cs_0_a3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_berr_0_a3_0_a2_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_berr_0_a3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_1_0 "SM_AMIGA_nss_i_i_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0 "SM_AMIGA_nss_i_i_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_6 "SM_AMIGA_srsts_i_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_6 "SM_AMIGA_srsts_i_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_4 "SM_AMIGA_srsts_i_0_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_4 "SM_AMIGA_srsts_i_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_0 "SM_AMIGA_srsts_i_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0 "SM_AMIGA_srsts_i_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_berr_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_berr_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un11_amiga_bus_enable_high_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un11_amiga_bus_enable_high_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_as_000_dma6_i_0 "pos_clk.as_000_dma6_i_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_1 "pos_clk.CYCLE_DMA_5_0_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_2 "pos_clk.CYCLE_DMA_5_0_i_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i "pos_clk.CYCLE_DMA_5_0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_a3_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_i_1 "pos_clk.un6_bg_030_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_5 "SM_AMIGA_srsts_i_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_5 "SM_AMIGA_srsts_i_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_3 "SM_AMIGA_srsts_i_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_3 "SM_AMIGA_srsts_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_2 "SM_AMIGA_srsts_i_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_2 "SM_AMIGA_srsts_i_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_0_a3_1_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_0_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_0_0_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_CYCLE_DMA_5_1_1 "pos_clk.CYCLE_DMA_5_1_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_CYCLE_DMA_5_1 "pos_clk.CYCLE_DMA_5_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance G_90_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance G_90 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_000_DMA_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_000_DMA_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_as_000_dma6_i_0_0_a2_1 "pos_clk.as_000_dma6_i_0_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_as_000_dma6_i_0_0_a2 "pos_clk.as_000_dma6_i_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_1 "pos_clk.CYCLE_DMA_5_0_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_2 "pos_clk.CYCLE_DMA_5_0_i_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i "pos_clk.CYCLE_DMA_5_0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_as_000_dma6_i_0_0_1 "pos_clk.as_000_dma6_i_0_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_2 "SM_AMIGA_srsts_i_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1_1 "SM_AMIGA_srsts_i_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_2_1 "SM_AMIGA_srsts_i_0_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_1 "SM_AMIGA_srsts_i_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_0_1 "pos_clk.un9_clk_000_pe_0_0_a2_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_0_2 "pos_clk.un9_clk_000_pe_0_0_a2_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_0 "pos_clk.un9_clk_000_pe_0_0_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_1 "pos_clk.un9_clk_000_pe_0_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a2_2 "pos_clk.un9_clk_000_pe_0_0_a2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_a2 "pos_clk.un9_clk_000_pe_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d1_i_i_a2_1 "pos_clk.un34_as_030_d1_i_i_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d1_i_i_a2_2 "pos_clk.un34_as_030_d1_i_i_a2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d1_i_i_a2_3 "pos_clk.un34_as_030_d1_i_i_a2_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d1_i_i_a2 "pos_clk.un34_as_030_d1_i_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_fpu_cs_0_a3_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_9 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_10 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_11 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_1_1_3 "SM_AMIGA_srsts_i_0_0_a2_1_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_1_2_3 "SM_AMIGA_srsts_i_0_0_a2_1_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_1_3 "SM_AMIGA_srsts_i_0_0_a2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_1_3 "SM_AMIGA_srsts_i_0_0_o2_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_3 "SM_AMIGA_srsts_i_0_0_o2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_1_2 "SM_AMIGA_srsts_i_0_0_o2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_1_0 "SM_AMIGA_nss_i_i_0_0_o2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_2_0 "SM_AMIGA_nss_i_i_0_0_o2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0 "SM_AMIGA_nss_i_i_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d1_i_i_o2_1 "pos_clk.un34_as_030_d1_i_i_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d1_i_i_o2_2 "pos_clk.un34_as_030_d1_i_i_o2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d1_i_i_o2_3 "pos_clk.un34_as_030_d1_i_i_o2_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d1_i_i_o2_4 "pos_clk.un34_as_030_d1_i_i_o2_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d1_i_i_o2 "pos_clk.un34_as_030_d1_i_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_as_000_dma6_i_a3_1 "pos_clk.as_000_dma6_i_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_as_000_dma6_i_a3 "pos_clk.as_000_dma6_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_as_000_dma6_i_0_1 "pos_clk.as_000_dma6_i_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_as_000_dma6_i_0_2 "pos_clk.as_000_dma6_i_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_a3_0_2 "pos_clk.un9_clk_000_pe_0_a3_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_a3_0 "pos_clk.un9_clk_000_pe_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_a3_1 "pos_clk.un9_clk_000_pe_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_a3_2 "pos_clk.un9_clk_000_pe_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_a3 "pos_clk.un9_clk_000_pe_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_0_a3_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_0_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_0_a3_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_0_a3_1_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_0_a3_1_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_0_a3_1_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_0_a3_1_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_0_a3_1_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_0_a3_1_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_2 "SM_AMIGA_srsts_i_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_0_1_3 "SM_AMIGA_srsts_i_0_o2_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_0_3 "SM_AMIGA_srsts_i_0_o2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un10_sm_amiga_1 "pos_clk.un10_sm_amiga_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_un10_sm_amiga "pos_clk.un10_sm_amiga") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_1_3 "SM_AMIGA_srsts_i_0_a2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_2_3 "SM_AMIGA_srsts_i_0_a2_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_3 "SM_AMIGA_srsts_i_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_a2_1 "pos_clk.un34_as_030_d1_i_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_a2_2 "pos_clk.un34_as_030_d1_i_a2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_a2_3 "pos_clk.un34_as_030_d1_i_a2_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_a2_4 "pos_clk.un34_as_030_d1_i_a2_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_a2_5 "pos_clk.un34_as_030_d1_i_a2_5") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_a2 "pos_clk.un34_as_030_d1_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_a3_0_1 "pos_clk.un9_clk_000_pe_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_o2_1 "pos_clk.un34_as_030_d1_i_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_o2_2 "pos_clk.un34_as_030_d1_i_o2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_o2 "pos_clk.un34_as_030_d1_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_1_6 "SM_AMIGA_srsts_i_0_o2_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_2_6 "SM_AMIGA_srsts_i_0_o2_2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_6 "SM_AMIGA_srsts_i_0_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_1 "SM_AMIGA_srsts_i_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_2_1 "SM_AMIGA_srsts_i_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1 "SM_AMIGA_srsts_i_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_1_2 "SM_AMIGA_srsts_i_0_o2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_150_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_i "pos_clk.un9_clk_000_pe_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_20_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_2 "IPL_030_1_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_18_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_030_1_i_0 "IPL_030_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_c_i_2 "IPL_c_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_D0_0_i_2 "IPL_D0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -415,137 +428,127 @@ (instance (rename IPL_D0_0_i_1 "IPL_D0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_c_i_0 "IPL_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_D0_0_i_0 "IPL_D0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_D_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_13_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_147_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_148_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_i_1 "cpu_est_2_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_146_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance A0_DMA_0_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_145_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_DS_0_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_143_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_144_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_i "pos_clk.un9_clk_000_pe_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_20_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_2 "IPL_030_1_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_18_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_182_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_181_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_260_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_259_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_155_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_162_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un5_e_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_154_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_i_3 "cpu_est_2_0_0_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_149_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_208_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_i_2 "cpu_est_2_0_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_o2_i_2 "cpu_est_2_0_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_o2_i_3 "cpu_est_2_0_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_1 "SM_AMIGA_srsts_i_0_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_130_i_0_o2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_0_a3_i_i "pos_clk.un6_bg_030_0_a3_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_177_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_178_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un8_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un11_ciin_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_160_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_161_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un5_e_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_159_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_158_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_157_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_i_3 "cpu_est_2_0_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_156_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_229_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_i_2 "cpu_est_2_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_126_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_i_i "pos_clk.un6_bg_030_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_197_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_195_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_196_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_194_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_190_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_191_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_267_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_266_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_186_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_185_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_183_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_214_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_184_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_268_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_6 "SM_AMIGA_srsts_i_0_0_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_142_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_141_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_4 "SM_AMIGA_srsts_i_0_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_2 "SM_AMIGA_srsts_i_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_i_3 "SM_AMIGA_srsts_i_0_0_o2_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_183_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_182_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance A0_DMA_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_179_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_180_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_4 "SM_AMIGA_srsts_i_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_0_i_0 "SM_AMIGA_srsts_i_0_o2_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance LDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance UDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_o2_i_0 "pos_clk.SIZE_DMA_6_0_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_3 "SM_AMIGA_srsts_i_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_203_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_201_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_202_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un13_ciin_i_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_274_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000_0_0_i "pos_clk.un6_bgack_000_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_RW_000_INT_5_0_0_i "pos_clk.RW_000_INT_5_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_168_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_167_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_170_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_169_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_D0_0_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d1_i_i_o2_i "pos_clk.un34_as_030_d1_i_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_o2_i_0 "pos_clk.SIZE_DMA_6_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_3 "SM_AMIGA_srsts_i_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_220_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_DS_000_ENABLE_0_sqmuxa_0_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_o2_i_2 "cpu_est_2_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_o2_i_3 "cpu_est_2_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_0 "SM_AMIGA_srsts_i_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_000_NE_0_o3_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_152_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_153_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_i_1 "cpu_est_2_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_163_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_162_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_164_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_228_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_i "pos_clk.un34_as_030_d1_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_171_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_172_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename CLK_000_D_i_3 "CLK_000_D_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_o2_i_0 "SM_AMIGA_nss_i_i_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_0 "SM_AMIGA_srsts_i_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_6 "SM_AMIGA_srsts_i_0_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_o2_i "pos_clk.un34_as_030_d1_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_INT_5_0_i "pos_clk.RW_000_INT_5_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_201_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_0_0_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_219_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_202_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_191_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_0_i_3 "SM_AMIGA_srsts_i_0_o2_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_2 "SM_AMIGA_srsts_i_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_192_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_193_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_11_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_D_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_16_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_15_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance LDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_12_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance RW_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_11_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_5_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BGACK_030_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_163_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d1_i_i_i "pos_clk.un34_as_030_d1_i_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_164_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_165_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un10_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_180_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_262_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_iv_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_231_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0_i "pos_clk.un6_bgack_000_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_D0_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_DS_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_186_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_185_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance G_99_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_3_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_4_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_rst_2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_DMA_0_1_0_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename pos_clk_un9_bg_030_i "pos_clk.un9_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_17_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance UDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_16_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_as_000_dma6_i_0_0_i "pos_clk.as_000_dma6_i_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_140_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_DS_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_199_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_181_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_DS_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_176_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_175_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_as_000_dma6_i_0_i "pos_clk.as_000_dma6_i_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_198_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance I_208 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_iv_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_a2 "pos_clk.CYCLE_DMA_5_0_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_iv_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance I_207 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_DS_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_DS_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_amiga_bus_enable_low_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un21_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_LOW_0_i_a3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_1 "A_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_i_a3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un3_as_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -564,6 +567,11 @@ (instance (rename CYCLE_DMA_i_1 "CYCLE_DMA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance CLK_EXP_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance G_91 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_a3 "pos_clk.CYCLE_DMA_5_0_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_iv_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance BG_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance UDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -579,152 +587,147 @@ (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_030_D1_0_r "AS_030_D1_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_030_D1_0_m "AS_030_D1_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_D1_0_n "AS_030_D1_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_D1_0_p "AS_030_D1_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_DMA_0_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_DMA_0_1_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_0_3 "SM_AMIGA_srsts_i_0_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a3_3 "SM_AMIGA_srsts_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a3_2 "SM_AMIGA_srsts_i_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a3_0_1 "SM_AMIGA_srsts_i_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a3_1 "SM_AMIGA_srsts_i_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_215 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_216 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_213 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_214 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_211 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_212 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_209 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_210 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_DMA_LOW_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un1_amiga_bus_enable_low (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_rst_2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_DMA_0_i_a3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_5 "SM_AMIGA_srsts_i_0_0_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_0 "SM_AMIGA_srsts_i_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_0_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_0_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_0_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_0_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un11_amiga_bus_enable_high_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_DECODE_i_16 "A_DECODE_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_DECODE_i_19 "A_DECODE_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_DECODE_i_18 "A_DECODE_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un11_amiga_bus_enable_high_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un34_as_030_d1_i_i "pos_clk.un34_as_030_d1_i_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_dsack1_0_o3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000_0_0_a2 "pos_clk.un6_bgack_000_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_DSACK1_INT_1_i_a2_0_a2 "pos_clk.DSACK1_INT_1_i_a2_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_210 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_AS_000_INT_1_i_a2_0_a2 "pos_clk.AS_000_INT_1_i_a2_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a2_0 "SM_AMIGA_nss_i_i_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_6 "SM_AMIGA_srsts_i_0_0_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un21_berr_0_a3_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_6 "SM_AMIGA_srsts_i_0_0_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_RW_000_INT_5_0_0_o2 "pos_clk.RW_000_INT_5_0_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_0 "SM_AMIGA_srsts_i_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_D0_0_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_0_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_0_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_RW_000_INT_5_0_0 "pos_clk.RW_000_INT_5_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000_0_0 "pos_clk.un6_bgack_000_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un13_ciin_i_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_1 "SM_AMIGA_srsts_i_0_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_o2_3 "cpu_est_2_0_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0_o2 "pos_clk.un9_clk_000_pe_0_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_0_sqmuxa_1_0_1_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_o2_2 "cpu_est_2_0_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_3 "SM_AMIGA_srsts_i_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_o2_0 "pos_clk.SIZE_DMA_6_0_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_DECODE_i_20 "A_DECODE_i[20]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_4 "SM_AMIGA_srsts_i_0_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a2_0_2 "cpu_est_2_0_0_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_clk_000_pe_0_0 "pos_clk.un9_clk_000_pe_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_DS_0_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance A0_DMA_0_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_1 "cpu_est_2_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_2 "cpu_est_2_0_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_3 "cpu_est_2_0_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_0 "pos_clk.SIZE_DMA_6_0_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_1 "pos_clk.SIZE_DMA_6_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0_0_0 "cpu_est_0_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_130_i_0_o2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_a2_0 "pos_clk.SIZE_DMA_6_0_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0_a2_1 "pos_clk.SIZE_DMA_6_0_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_2 "SM_AMIGA_srsts_i_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_3 "SM_AMIGA_srsts_i_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_3 "SM_AMIGA_srsts_i_0_0_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_4 "SM_AMIGA_srsts_i_0_0_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0_a2_0_0 "SM_AMIGA_nss_i_i_0_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0_0_a2_0 "cpu_est_0_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0_0_a2_0_0 "cpu_est_0_0_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_0_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_RW_000_INT_5_0 "pos_clk.RW_000_INT_5_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_D0_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0_a2 "pos_clk.un6_bgack_000_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_2_3 "SM_AMIGA_srsts_i_0_0_a2_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_214 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_215 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_212 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_213 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_105 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_106 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_107 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_1 "SM_AMIGA_srsts_i_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_1 "SM_AMIGA_srsts_i_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_DS_0_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance A0_DMA_0_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_a2_1 "cpu_est_2_0_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_a2_2 "cpu_est_2_0_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_a2_3 "cpu_est_2_0_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_187_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_188_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_189_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_218 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_1 "cpu_est_2_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_a3_0 "SM_AMIGA_nss_i_i_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a3_6 "SM_AMIGA_srsts_i_0_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un11_amiga_bus_enable_high_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance I_219 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_216 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_217 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_126_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_150_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_151_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_1 "IPL_D0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_D0_0_2 "IPL_D0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_1_1 "IPL_030_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_1_2 "IPL_030_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i_a3 "pos_clk.un34_as_030_d1_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_a3_0_0 "cpu_est_0_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_a3_0 "cpu_est_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a3_1 "cpu_est_2_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_3 "SM_AMIGA_srsts_i_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_o2_0 "pos_clk.SIZE_DMA_6_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_0_0 "SM_AMIGA_srsts_i_0_o2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_4 "SM_AMIGA_srsts_i_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_0_6 "SM_AMIGA_srsts_i_0_o2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un11_amiga_bus_enable_high_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un34_as_030_d1_i "pos_clk.un34_as_030_d1_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_dsack1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_2_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_0 "cpu_est_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance A0_DMA_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0 "pos_clk.SIZE_DMA_6_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_1 "pos_clk.SIZE_DMA_6_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_000_NE_0_o3_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_0 "SM_AMIGA_srsts_i_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0_o2 "pos_clk.un9_clk_000_pe_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_o2_3 "cpu_est_2_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_1_0_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_o2_2 "cpu_est_2_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DS_000_ENABLE_0_sqmuxa_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_DECODE_i_19 "A_DECODE_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_DECODE_i_18 "A_DECODE_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_DECODE_i_16 "A_DECODE_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_AS_000_INT_1_i_a2 "pos_clk.AS_000_INT_1_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_DSACK1_INT_1_i_a2 "pos_clk.DSACK1_INT_1_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a2_2 "cpu_est_2_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_clk_000_pe_0 "pos_clk.un9_clk_000_pe_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_2 "cpu_est_2_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_3 "cpu_est_2_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un11_ciin_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a3_4 "SM_AMIGA_srsts_i_0_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_0_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_0_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_0_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_0_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance A0_DMA_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_a3_0 "pos_clk.SIZE_DMA_6_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_a3_1 "pos_clk.SIZE_DMA_6_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_a3_0_0 "SM_AMIGA_nss_i_i_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a3_0_3 "SM_AMIGA_srsts_i_0_a3_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a3_5 "SM_AMIGA_srsts_i_0_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DS_000_ENABLE_0_sqmuxa_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_187_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_188_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_189_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_105 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_106 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_107 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a3_2 "cpu_est_2_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a3_3 "cpu_est_2_0_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a3_0 "SM_AMIGA_srsts_i_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_213_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_212_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_2 "IPL_D0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_1 "IPL_030_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_2 "IPL_030_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -746,8 +749,8 @@ (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance un3_as_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_175_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_219_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_224_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_225_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un2_ds_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DS_000_ENABLE_0_r "DS_000_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DS_000_ENABLE_0_m "DS_000_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -757,21 +760,25 @@ (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_030_D1_0_r "AS_030_D1_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_030_D1_0_m "AS_030_D1_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_D1_0_n "AS_030_D1_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_D1_0_p "AS_030_D1_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_UDS_000_INT (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_LDS_000_INT (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance VMA_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_D0_0_0 "IPL_D0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_D0_0_1 "IPL_D0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) - (portRef I0 (instanceRef un1_dsack1_0_o3_0)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_sqmuxa_i_0)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_2_sqmuxa_i)) + (portRef I0 (instanceRef un1_dsack1_0)) (portRef I0 (instanceRef BGACK_030_INT_0_n)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a3)) (portRef I0 (instanceRef BGACK_030_INT_i)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2)) - (portRef I0 (instanceRef un11_amiga_bus_enable_high_0_0_a2_0_1)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_o2_2)) + (portRef I0 (instanceRef un11_amiga_bus_enable_high_0_a3_0_1)) (portRef I0 (instanceRef BGACK_030)) (portRef OE (instanceRef VMA)) )) @@ -779,7 +786,7 @@ (portRef I0 (instanceRef AVEC)) )) (net un5_e (joined - (portRef O (instanceRef un5_e_0_0_i)) + (portRef O (instanceRef un5_e_0_i)) (portRef I0 (instanceRef E)) )) (net GND (joined @@ -811,54 +818,54 @@ (portRef I0 (instanceRef LDS_000)) )) (net un1_DS_000_ENABLE_0_sqmuxa (joined - (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o2_i)) + (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_i)) (portRef I0 (instanceRef DS_000_ENABLE_0_m)) )) - (net un10_ciin (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2)) - (portRef I0 (instanceRef un10_ciin_i)) - (portRef I0 (instanceRef CIIN)) - )) (net un21_fpu_cs (joined - (portRef O (instanceRef un21_fpu_cs_0_a3_0_a2)) + (portRef O (instanceRef un21_fpu_cs_0_a3)) (portRef I0 (instanceRef un21_fpu_cs_i)) )) (net un21_berr (joined - (portRef O (instanceRef un21_berr_0_a3_0_a2)) + (portRef O (instanceRef un21_berr_0_a3)) (portRef OE (instanceRef BERR)) )) + (net un8_ciin (joined + (portRef O (instanceRef un8_ciin_0_a3)) + (portRef I0 (instanceRef un8_ciin_i)) + (portRef I0 (instanceRef CIIN)) + )) (net un2_ds_030 (joined (portRef O (instanceRef un2_ds_030)) (portRef I0 (instanceRef un2_ds_030_i)) )) (net (rename cpu_est_0 "cpu_est[0]") (joined (portRef Q (instanceRef cpu_est_0)) - (portRef I1 (instanceRef cpu_est_0_0_0_a2_0_0)) + (portRef I0 (instanceRef cpu_est_2_0_0_o2_2)) (portRef I0 (instanceRef cpu_est_i_0)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_2)) - (portRef I0 (instanceRef cpu_est_2_0_0_a2_0_1_1)) + (portRef I1 (instanceRef cpu_est_0_0_a3_0_0)) + (portRef I0 (instanceRef cpu_est_2_0_0_a3_0_1_1)) )) (net (rename cpu_est_1 "cpu_est[1]") (joined (portRef Q (instanceRef cpu_est_1)) - (portRef I0 (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_1)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_o2_2)) + (portRef I1 (instanceRef cpu_est_2_0_0_o2_2)) (portRef I0 (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef un5_e_0_0_a2_0_1)) + (portRef I0 (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_2_0_0_a3_1)) + (portRef I0 (instanceRef un5_e_0_a3_0_1)) )) (net (rename cpu_est_2 "cpu_est[2]") (joined (portRef Q (instanceRef cpu_est_2)) (portRef I0 (instanceRef cpu_est_0_2__m)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_3)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a3_3)) + (portRef I1 (instanceRef cpu_est_2_0_0_a3_2)) (portRef I0 (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef un5_e_0_0_a2_0_1)) + (portRef I1 (instanceRef un5_e_0_a3_0_1)) )) (net (rename cpu_est_3 "cpu_est[3]") (joined (portRef Q (instanceRef cpu_est_3)) (portRef I0 (instanceRef cpu_est_0_3__m)) - (portRef I1 (instanceRef un5_e_0_0_a2)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_3)) + (portRef I1 (instanceRef un5_e_0_a3)) + (portRef I0 (instanceRef cpu_est_2_0_0_o2_3)) (portRef I0 (instanceRef cpu_est_i_3)) )) (net AMIGA_BUS_ENABLE_DMA_HIGH (joined @@ -871,19 +878,19 @@ )) (net AS_030_D0 (joined (portRef Q (instanceRef AS_030_D0)) - (portRef I0 (instanceRef AS_030_D0_i)) (portRef I0 (instanceRef AS_030_D1_0_m)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a3_i_1)) + (portRef I0 (instanceRef AS_030_D0_i)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_i_1)) )) (net AS_030_D1 (joined (portRef Q (instanceRef AS_030_D1)) - (portRef I0 (instanceRef AS_030_D1_i)) (portRef I0 (instanceRef AS_030_D1_0_n)) + (portRef I0 (instanceRef AS_030_D1_i)) )) (net AS_030_000_SYNC (joined (portRef Q (instanceRef AS_030_000_SYNC)) (portRef I0 (instanceRef AS_030_000_SYNC_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) )) (net AS_000_DMA (joined (portRef Q (instanceRef AS_000_DMA)) @@ -903,8 +910,8 @@ )) (net VPA_D (joined (portRef Q (instanceRef VPA_D)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) (portRef I0 (instanceRef VPA_D_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0_3)) )) (net (rename CLK_000_D_3 "CLK_000_D[3]") (joined (portRef Q (instanceRef CLK_000_D_3)) @@ -921,15 +928,15 @@ )) (net (rename CLK_000_D_1 "CLK_000_D[1]") (joined (portRef Q (instanceRef CLK_000_D_1)) - (portRef I0 (instanceRef N_130_i_0_o2_i_o2)) + (portRef I0 (instanceRef CLK_000_NE_0_o3_i_o2)) (portRef I0 (instanceRef CLK_000_D_i_1)) (portRef D (instanceRef CLK_000_D_2)) )) (net (rename CLK_000_D_0 "CLK_000_D[0]") (joined (portRef Q (instanceRef CLK_000_D_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0)) (portRef I0 (instanceRef CLK_000_D_i_0)) - (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a3_i_1)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_i_1)) (portRef D (instanceRef CLK_000_D_1)) )) (net CLK_OUT_PRE_50 (joined @@ -960,7 +967,7 @@ )) (net (rename CLK_000_D_4 "CLK_000_D[4]") (joined (portRef Q (instanceRef CLK_000_D_4)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_1_6)) )) (net (rename pos_clk_ipl "pos_clk.ipl") (joined (portRef O (instanceRef G_108)) @@ -1005,11 +1012,11 @@ )) (net BGACK_030_INT_D (joined (portRef Q (instanceRef BGACK_030_INT_D)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_a2_1)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_o2_1)) )) (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined (portRef Q (instanceRef SM_AMIGA_6)) - (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_o2)) (portRef I0 (instanceRef SM_AMIGA_i_6)) (portRef I1 (instanceRef LDS_000_INT_0_m)) (portRef I0 (instanceRef LDS_000_INT_0_r)) @@ -1023,30 +1030,30 @@ )) (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined (portRef Q (instanceRef SM_AMIGA_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_3)) (portRef I0 (instanceRef SM_AMIGA_i_4)) )) (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined (portRef Q (instanceRef SM_AMIGA_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_0_0)) (portRef I0 (instanceRef SM_AMIGA_i_1)) )) (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined (portRef Q (instanceRef SM_AMIGA_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_0)) (portRef I0 (instanceRef SM_AMIGA_i_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a3_0_0)) )) (net (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (joined (portRef Q (instanceRef CYCLE_DMA_0)) (portRef I0 (instanceRef CYCLE_DMA_i_0)) - (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_0_a2_1)) + (portRef I0 (instanceRef pos_clk_as_000_dma6_i_a3_1)) (portRef I1 (instanceRef G_90_1)) )) (net (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (joined (portRef Q (instanceRef CYCLE_DMA_1)) (portRef I0 (instanceRef G_91)) (portRef I0 (instanceRef CYCLE_DMA_i_1)) - (portRef I1 (instanceRef pos_clk_as_000_dma6_i_0_0_a2_1)) + (portRef I1 (instanceRef pos_clk_as_000_dma6_i_a3_1)) )) (net DSACK1_INT (joined (portRef Q (instanceRef DSACK1_INT)) @@ -1057,23 +1064,23 @@ (portRef I0 (instanceRef AS_000_INT_i)) )) (net (rename pos_clk_un9_clk_000_pe "pos_clk.un9_clk_000_pe") (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_i)) + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_i)) (portRef I1 (instanceRef VMA_INT_0_m)) (portRef I0 (instanceRef VMA_INT_0_r)) )) (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined (portRef Q (instanceRef SM_AMIGA_5)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_4)) (portRef I0 (instanceRef SM_AMIGA_i_5)) )) (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined (portRef Q (instanceRef SM_AMIGA_3)) (portRef I0 (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_2)) )) (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined (portRef Q (instanceRef SM_AMIGA_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a3_1)) (portRef I0 (instanceRef SM_AMIGA_i_2)) )) (net (rename pos_clk_CYCLE_DMA_5_1 "pos_clk.CYCLE_DMA_5[1]") (joined @@ -1164,16 +1171,20 @@ (portRef O (instanceRef DS_000_DMA_1_i)) (portRef D (instanceRef DS_000_DMA)) )) - (net N_35 (joined - (portRef O (instanceRef AMIGA_DS_0_0_0_i)) + (net N_34 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_i)) + (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) + )) + (net N_37 (joined + (portRef O (instanceRef AMIGA_DS_0_0_i)) (portRef D (instanceRef AMIGA_DS)) )) - (net N_36 (joined - (portRef O (instanceRef A0_DMA_0_0_0_i)) + (net N_38 (joined + (portRef O (instanceRef A0_DMA_0_0_i)) (portRef D (instanceRef A0_DMA)) )) - (net N_38 (joined - (portRef O (instanceRef AS_030_D0_0_0_0_i)) + (net N_40 (joined + (portRef O (instanceRef AS_030_D0_0_0_i)) (portRef D (instanceRef AS_030_D0)) )) (net N_41 (joined @@ -1202,27 +1213,23 @@ )) (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined (portRef Q (instanceRef SM_AMIGA_i_7)) - (portRef I1 (instanceRef pos_clk_RW_000_INT_5_0_0_o2)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_o3)) (portRef I0 (instanceRef SM_AMIGA_i_i_7)) )) (net (rename pos_clk_SIZE_DMA_6_0 "pos_clk.SIZE_DMA_6[0]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_0)) + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) (portRef D (instanceRef SIZE_DMA_0)) )) (net (rename pos_clk_SIZE_DMA_6_1 "pos_clk.SIZE_DMA_6[1]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_1)) + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_i_1)) (portRef D (instanceRef SIZE_DMA_1)) )) - (net (rename cpu_est_2_1 "cpu_est_2[1]") (joined - (portRef O (instanceRef cpu_est_2_0_0_0_i_1)) - (portRef I0 (instanceRef cpu_est_0_1__n)) - )) (net (rename cpu_est_2_2 "cpu_est_2[2]") (joined - (portRef O (instanceRef cpu_est_2_0_0_0_i_2)) + (portRef O (instanceRef cpu_est_2_0_0_i_2)) (portRef I0 (instanceRef cpu_est_0_2__n)) )) (net (rename cpu_est_2_3 "cpu_est_2[3]") (joined - (portRef O (instanceRef cpu_est_2_0_0_0_i_3)) + (portRef O (instanceRef cpu_est_2_0_0_i_3)) (portRef I0 (instanceRef cpu_est_0_3__n)) )) (net N_187 (joined @@ -1237,298 +1244,305 @@ (portRef O (instanceRef G_107)) (portRef I0 (instanceRef N_189_i)) )) - (net N_60 (joined - (portRef O (instanceRef un13_ciin_i_0_0_i)) + (net N_39_1 (joined + (portRef O (instanceRef RW_000_DMA_0_1_0_o3_i)) + (portRef D (instanceRef BGACK_030_INT_D)) + )) + (net N_205 (joined + (portRef O (instanceRef un11_ciin_i_0_i)) (portRef OE (instanceRef CIIN)) )) - (net N_63 (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_i)) + (net N_74 (joined + (portRef O (instanceRef pos_clk_un6_bg_030_i_i)) + (portRef I1 (instanceRef pos_clk_un9_bg_030)) + )) + (net N_78 (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_i)) (portRef I1 (instanceRef DS_000_ENABLE_0_m)) (portRef I0 (instanceRef DS_000_ENABLE_0_r)) )) - (net N_126 (joined - (portRef O (instanceRef RW_000_DMA_0_i_a3_0_a2)) - (portRef I0 (instanceRef N_126_i)) - )) - (net N_150 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_i_a3_0_a2)) - (portRef I0 (instanceRef N_150_i)) - )) - (net N_151 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_i_a3_0_a2)) - (portRef I0 (instanceRef N_151_i)) - )) - (net N_219 (joined - (portRef O (instanceRef pos_clk_DSACK1_INT_1_i_a2_0_a2)) - (portRef I0 (instanceRef N_219_i)) - (portRef I0 (instanceRef DSACK1_INT_0_i_0_a2)) - )) - (net N_175 (joined - (portRef O (instanceRef pos_clk_AS_000_INT_1_i_a2_0_a2)) - (portRef I0 (instanceRef N_175_i)) - (portRef I0 (instanceRef AS_000_INT_0_i_0_a2)) - )) - (net N_220 (joined - (portRef O (instanceRef un1_rst_2_i_o2_i)) - (portRef D (instanceRef BGACK_030_INT_D)) - )) - (net N_59 (joined - (portRef O (instanceRef pos_clk_un6_bg_030_0_a3_i_i)) - (portRef I1 (instanceRef pos_clk_un9_bg_030)) - )) - (net N_68 (joined - (portRef O (instanceRef N_130_i_0_o2_i_o2_i)) + (net N_79 (joined + (portRef O (instanceRef CLK_000_NE_0_o3_i_o2_i)) (portRef I1 (instanceRef cpu_est_0_3__m)) (portRef I0 (instanceRef cpu_est_0_3__r)) (portRef I1 (instanceRef cpu_est_0_2__m)) (portRef I0 (instanceRef cpu_est_0_2__r)) (portRef I1 (instanceRef cpu_est_0_1__m)) (portRef I0 (instanceRef cpu_est_0_1__r)) - (portRef I0 (instanceRef cpu_est_0_0_0_a2_0)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_a2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_5)) - )) - (net N_72 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_2)) + (portRef I0 (instanceRef cpu_est_0_0_a3_0)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_a3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_2_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_5)) )) (net N_80 (joined - (portRef O (instanceRef cpu_est_2_0_0_0_o2_i_3)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_3)) + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a3_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_4)) )) - (net N_93 (joined - (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_o2_i)) - (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_6)) + (net N_83 (joined + (portRef O (instanceRef cpu_est_2_0_0_o2_i_3)) + (portRef I0 (instanceRef cpu_est_2_0_0_3)) )) - (net N_98 (joined - (portRef O (instanceRef cpu_est_2_0_0_0_o2_i_2)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_2)) + (net N_84 (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_o2_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a3_5)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_6)) )) - (net N_107 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) - (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o2)) + (net N_89 (joined + (portRef O (instanceRef cpu_est_2_0_0_o2_i_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_a3_2)) )) - (net N_128 (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_i_0)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_0)) + (net N_95 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a3_0_3)) + (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3)) )) - (net N_131 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_i_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_1_2)) + (net N_96 (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_i_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a3_0)) )) - (net N_134 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2)) + (net N_97 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_0_i_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a3_0)) )) - (net N_135 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_4)) + (net N_105 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a3_4)) )) - (net N_141 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1)) - (portRef I0 (instanceRef N_141_i)) + (net N_126 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3)) + (portRef I0 (instanceRef N_126_i)) )) - (net N_142 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1)) - (portRef I0 (instanceRef N_142_i)) + (net N_150 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3_0)) + (portRef I0 (instanceRef N_150_i)) )) - (net N_143 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2)) - (portRef I0 (instanceRef N_143_i)) + (net N_153 (joined + (portRef O (instanceRef cpu_est_2_0_0_a3_0_1)) + (portRef I0 (instanceRef N_153_i)) )) - (net N_144 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0)) - (portRef I0 (instanceRef N_144_i)) + (net N_156 (joined + (portRef O (instanceRef cpu_est_2_0_0_a3_2)) + (portRef I0 (instanceRef N_156_i)) )) - (net N_145 (joined - (portRef O (instanceRef AMIGA_DS_0_0_0_a2)) - (portRef I0 (instanceRef N_145_i)) + (net N_157 (joined + (portRef O (instanceRef cpu_est_2_0_0_a3_3)) + (portRef I0 (instanceRef N_157_i)) )) - (net N_146 (joined - (portRef O (instanceRef A0_DMA_0_0_0_a2)) - (portRef I0 (instanceRef N_146_i)) + (net N_158 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a3_0)) + (portRef I0 (instanceRef N_158_i)) )) - (net N_147 (joined - (portRef O (instanceRef cpu_est_2_0_0_0_a2_1)) - (portRef I0 (instanceRef N_147_i)) + (net N_159 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a3_4)) + (portRef I0 (instanceRef N_159_i)) )) - (net N_148 (joined - (portRef O (instanceRef cpu_est_2_0_0_a2_0_1)) - (portRef I0 (instanceRef N_148_i)) + (net N_160 (joined + (portRef O (instanceRef un5_e_0_a3)) + (portRef I0 (instanceRef N_160_i)) )) - (net N_149 (joined - (portRef O (instanceRef cpu_est_2_0_0_0_a2_2)) - (portRef I0 (instanceRef N_149_i)) + (net N_161 (joined + (portRef O (instanceRef un5_e_0_a3_0)) + (portRef I0 (instanceRef N_161_i)) )) - (net N_154 (joined - (portRef O (instanceRef cpu_est_2_0_0_0_a2_3)) - (portRef I0 (instanceRef N_154_i)) + (net N_172 (joined + (portRef O (instanceRef un11_amiga_bus_enable_high_0_a3_0)) + (portRef I0 (instanceRef N_172_i)) )) - (net N_155 (joined - (portRef O (instanceRef un5_e_0_0_a2)) - (portRef I0 (instanceRef N_155_i)) + (net N_177 (joined + (portRef O (instanceRef DSACK1_INT_0_i_a3)) + (portRef I0 (instanceRef N_177_i)) )) - (net N_162 (joined - (portRef O (instanceRef un5_e_0_0_a2_0)) - (portRef I0 (instanceRef N_162_i)) + (net N_178 (joined + (portRef O (instanceRef DSACK1_INT_0_i_a3_0)) + (portRef I0 (instanceRef N_178_i)) )) - (net N_165 (joined - (portRef O (instanceRef un11_amiga_bus_enable_high_0_0_a2_0)) - (portRef I0 (instanceRef N_165_i)) + (net N_179 (joined + (portRef O (instanceRef AS_000_INT_0_i_a3)) + (portRef I0 (instanceRef N_179_i)) )) - (net N_259 (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_0)) - (portRef I0 (instanceRef N_259_i)) - )) - (net N_260 (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_1)) - (portRef I0 (instanceRef N_260_i)) - )) - (net N_181 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0)) - (portRef I0 (instanceRef N_181_i)) + (net N_180 (joined + (portRef O (instanceRef AS_000_INT_0_i_a3_0)) + (portRef I0 (instanceRef N_180_i)) )) (net N_182 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_2)) + (portRef O (instanceRef A0_DMA_0_0_a3)) (portRef I0 (instanceRef N_182_i)) )) (net N_183 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_a3_0)) (portRef I0 (instanceRef N_183_i)) )) (net N_184 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_a3_1)) (portRef I0 (instanceRef N_184_i)) )) - (net N_185 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_4)) - (portRef I0 (instanceRef N_185_i)) + (net N_212 (joined + (portRef O (instanceRef RW_000_DMA_0_i_a3)) + (portRef I0 (instanceRef N_212_i)) )) - (net N_186 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_5)) - (portRef I0 (instanceRef N_186_i)) + (net N_213 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_i_a3)) + (portRef I0 (instanceRef N_213_i)) )) - (net N_266 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_6)) - (portRef I0 (instanceRef N_266_i)) - )) - (net N_267 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) - (portRef I0 (instanceRef N_267_i)) - )) - (net N_268 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_0)) - (portRef I0 (instanceRef N_268_i)) + (net N_214 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a3_6)) + (portRef I0 (instanceRef N_214_i)) )) (net N_190 (joined - (portRef O (instanceRef cpu_est_0_0_0_a2_0)) + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a3_0)) (portRef I0 (instanceRef N_190_i)) )) (net N_191 (joined - (portRef O (instanceRef cpu_est_0_0_0_a2_0_0)) + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a3_0_0)) (portRef I0 (instanceRef N_191_i)) )) - (net N_201 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) - (portRef I0 (instanceRef N_201_i)) + (net N_194 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a3_2)) + (portRef I0 (instanceRef N_194_i)) + )) + (net N_195 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a3_3)) + (portRef I0 (instanceRef N_195_i)) + )) + (net N_196 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a3_0_3)) + (portRef I0 (instanceRef N_196_i)) + )) + (net N_197 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a3_5)) + (portRef I0 (instanceRef N_197_i)) )) (net N_202 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_3)) (portRef I0 (instanceRef N_202_i)) )) - (net N_203 (joined - (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_a2)) - (portRef I0 (instanceRef N_203_i)) + (net N_220 (joined + (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_a2)) + (portRef I0 (instanceRef N_220_i)) )) - (net N_208 (joined - (portRef O (instanceRef cpu_est_2_0_0_a2_0_2)) - (portRef I0 (instanceRef N_208_i)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_1)) + (net N_224 (joined + (portRef O (instanceRef pos_clk_AS_000_INT_1_i_a2)) + (portRef I0 (instanceRef N_224_i)) + (portRef I0 (instanceRef AS_000_INT_0_i_a3)) )) - (net N_163 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_a2)) - (portRef I0 (instanceRef N_163_i)) + (net N_225 (joined + (portRef O (instanceRef pos_clk_DSACK1_INT_1_i_a2)) + (portRef I0 (instanceRef N_225_i)) + (portRef I0 (instanceRef DSACK1_INT_0_i_a3)) )) - (net N_282 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_o2_i)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_a2_2)) + (net N_228 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_a2)) + (portRef I0 (instanceRef N_228_i)) + (portRef I0 (instanceRef un21_fpu_cs_0_a3_1)) + (portRef I0 (instanceRef un21_berr_0_a3_1)) )) - (net un21_berr_1 (joined - (portRef O (instanceRef un21_berr_0_a3_0_a2_1)) - (portRef I0 (instanceRef un21_fpu_cs_0_a3_0_a2_1)) - (portRef I0 (instanceRef un21_berr_0_a3_0_a2_1_0)) + (net N_229 (joined + (portRef O (instanceRef cpu_est_2_0_0_a2_2)) + (portRef I0 (instanceRef N_229_i)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_1)) )) - (net N_132 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_6)) + (net N_201_1 (joined + (portRef O (instanceRef un8_ciin_0_a3_1)) + (portRef I1 (instanceRef un8_ciin_0_a3_2)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_a2_2)) )) - (net N_96 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_i_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) + (net N_104 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_o2_i)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_a3)) )) - (net N_129 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0)) + (net N_100 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a3_6)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a3_0)) )) - (net un1_SM_AMIGA_0_sqmuxa_1 (joined - (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_i)) - (portRef I1 (instanceRef RW_000_INT_0_m)) - (portRef I0 (instanceRef RW_000_INT_0_r)) + (net N_171 (joined + (portRef O (instanceRef un11_amiga_bus_enable_high_0_a3)) + (portRef I0 (instanceRef N_171_i)) )) - (net N_169 (joined - (portRef O (instanceRef AS_000_INT_0_i_0_a2)) - (portRef I0 (instanceRef N_169_i)) - )) - (net N_170 (joined - (portRef O (instanceRef AS_000_INT_0_i_0_a2_0)) - (portRef I0 (instanceRef N_170_i)) - )) - (net N_167 (joined - (portRef O (instanceRef DSACK1_INT_0_i_0_a2)) - (portRef I0 (instanceRef N_167_i)) - )) - (net N_168 (joined - (portRef O (instanceRef DSACK1_INT_0_i_0_a2_0)) - (portRef I0 (instanceRef N_168_i)) - )) - (net (rename pos_clk_RW_000_INT_5 "pos_clk.RW_000_INT_5") (joined - (portRef O (instanceRef pos_clk_RW_000_INT_5_0_0_i)) - (portRef I0 (instanceRef RW_000_INT_0_m)) - )) - (net (rename pos_clk_un6_bgack_000 "pos_clk.un6_bgack_000") (joined - (portRef O (instanceRef pos_clk_un6_bgack_000_0_0_i)) - (portRef I1 (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_r)) - )) - (net N_274 (joined - (portRef O (instanceRef pos_clk_un6_bgack_000_0_0_a2)) - (portRef I0 (instanceRef N_274_i)) - )) - (net N_164 (joined - (portRef O (instanceRef un11_amiga_bus_enable_high_0_0_a2)) - (portRef I0 (instanceRef N_164_i)) - )) - (net N_244 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_i)) + (net N_204 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i)) (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) )) - (net N_5 (joined - (portRef O (instanceRef BGACK_030_INT_0_p)) - (portRef I0 (instanceRef N_5_i)) + (net N_164 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_a3)) + (portRef I0 (instanceRef N_164_i)) + )) + (net N_162 (joined + (portRef O (instanceRef cpu_est_0_0_a3_0)) + (portRef I0 (instanceRef N_162_i)) + )) + (net N_163 (joined + (portRef O (instanceRef cpu_est_0_0_a3_0_0)) + (portRef I0 (instanceRef N_163_i)) + )) + (net (rename cpu_est_2_1 "cpu_est_2[1]") (joined + (portRef O (instanceRef cpu_est_2_0_0_i_1)) + (portRef I0 (instanceRef cpu_est_0_1__n)) + )) + (net N_152 (joined + (portRef O (instanceRef cpu_est_2_0_0_a3_1)) + (portRef I0 (instanceRef N_152_i)) )) (net N_11 (joined (portRef O (instanceRef AS_030_000_SYNC_0_p)) (portRef I0 (instanceRef N_11_i)) )) + (net N_201 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_a2)) + (portRef I0 (instanceRef N_201_i)) + )) + (net N_193 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a3_0_1)) + (portRef I0 (instanceRef N_193_i)) + )) + (net N_192 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a3_1)) + (portRef I0 (instanceRef N_192_i)) + )) + (net N_107 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a3_2)) + )) + (net N_99 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_0_i_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a3_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_1_2)) + )) + (net N_219 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_0_3)) + (portRef I0 (instanceRef N_219_i)) + )) + (net N_81 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_o3_i)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_i_a3)) + )) + (net (rename pos_clk_RW_000_INT_5 "pos_clk.RW_000_INT_5") (joined + (portRef O (instanceRef pos_clk_RW_000_INT_5_0_i)) + (portRef I0 (instanceRef RW_000_INT_0_m)) + )) + (net un1_SM_AMIGA_0_sqmuxa_1 (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_i)) + (portRef I1 (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_r)) + )) + (net (rename pos_clk_un6_bgack_000 "pos_clk.un6_bgack_000") (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0_i)) + (portRef I1 (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_r)) + )) + (net N_231 (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0_a2)) + (portRef I0 (instanceRef N_231_i)) + )) + (net N_5 (joined + (portRef O (instanceRef BGACK_030_INT_0_p)) + (portRef I0 (instanceRef N_5_i)) + )) (net N_12 (joined (portRef O (instanceRef RW_000_INT_0_p)) (portRef I0 (instanceRef N_12_i)) @@ -1550,16 +1564,12 @@ (portRef I1 (instanceRef BG_000_0_m)) (portRef I0 (instanceRef BG_000_0_r)) )) - (net (rename un1_CYCLE_DMA_2 "un1_CYCLE_DMA[2]") (joined - (portRef O (instanceRef G_91)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1)) - )) (net N_3 (joined (portRef O (instanceRef DS_000_DMA_0_p)) (portRef I0 (instanceRef N_3_i)) )) - (net N_205 (joined - (portRef O (instanceRef pos_clk_as_000_dma6_i_0_0_i)) + (net N_72 (joined + (portRef O (instanceRef pos_clk_as_000_dma6_i_0_i)) (portRef I0 (instanceRef AS_000_DMA_0_n)) (portRef I0 (instanceRef DS_000_DMA_0_n)) )) @@ -1574,30 +1584,38 @@ (portRef O (instanceRef AS_000_DMA_0_p)) (portRef I0 (instanceRef N_4_i)) )) - (net N_199 (joined + (net (rename un1_CYCLE_DMA_2 "un1_CYCLE_DMA[2]") (joined + (portRef O (instanceRef G_91)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1)) + )) + (net N_176 (joined (portRef O (instanceRef G_90)) (portRef I1 (instanceRef G_91)) - (portRef I0 (instanceRef N_199_i)) + (portRef I0 (instanceRef N_176_i)) )) (net (rename pos_clk_un2 "pos_clk.un2") (joined (portRef O (instanceRef G_99_i)) - (portRef I1 (instanceRef pos_clk_as_000_dma6_i_0_0_2)) + (portRef I1 (instanceRef pos_clk_as_000_dma6_i_0_2)) )) - (net N_140 (joined - (portRef O (instanceRef pos_clk_as_000_dma6_i_0_0_a2)) - (portRef I0 (instanceRef N_140_i)) + (net N_175 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_a3)) + (portRef I0 (instanceRef N_175_i)) )) - (net N_262 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2)) - (portRef I0 (instanceRef N_262_i)) + (net N_185 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a3)) + (portRef I0 (instanceRef N_185_i)) )) (net N_198 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_a2)) + (portRef O (instanceRef pos_clk_as_000_dma6_i_a3)) (portRef I0 (instanceRef N_198_i)) )) - (net N_180 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0)) - (portRef I0 (instanceRef N_180_i)) + (net N_186 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a3_0)) + (portRef I0 (instanceRef N_186_i)) + )) + (net N_181 (joined + (portRef O (instanceRef AMIGA_DS_0_0_a3)) + (portRef I0 (instanceRef N_181_i)) )) (net un1_amiga_bus_enable_low_i (joined (portRef O (instanceRef un1_amiga_bus_enable_low_i)) @@ -1611,20 +1629,20 @@ (portRef O (instanceRef I_207)) (portRef I0 (instanceRef un2_ds_030)) (portRef I1 (instanceRef un3_as_030)) - (portRef I1 (instanceRef pos_clk_as_000_dma6_i_0_0_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) + (portRef I1 (instanceRef pos_clk_as_000_dma6_i_0_1)) (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_1)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a3_0_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) )) (net BGACK_030_INT_i (joined (portRef O (instanceRef BGACK_030_INT_i)) - (portRef I0 (instanceRef A0_DMA_0_0_0_a2)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_1)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_0)) - (portRef I1 (instanceRef un11_amiga_bus_enable_high_0_0_a2)) - (portRef I0 (instanceRef un1_rst_2_i_o2)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a3_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a3_0)) + (portRef I0 (instanceRef A0_DMA_0_0_a3)) + (portRef I1 (instanceRef un11_amiga_bus_enable_high_0_a3)) (portRef I1 (instanceRef un1_amiga_bus_enable_low)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_1)) + (portRef I0 (instanceRef RW_000_DMA_0_1_0_o3)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a3_0_1)) (portRef OE (instanceRef AHIGH_24)) (portRef OE (instanceRef AHIGH_25)) (portRef OE (instanceRef AHIGH_26)) @@ -1642,19 +1660,19 @@ )) (net nEXP_SPACE_i (joined (portRef O (instanceRef nEXP_SPACE_i)) - (portRef I0 (instanceRef un13_ciin_i_0_0)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_2)) - )) - (net (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (joined - (portRef O (instanceRef CYCLE_DMA_i_0)) - (portRef I0 (instanceRef G_99)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_a2)) + (portRef I0 (instanceRef un11_ciin_i_0)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a3_0_2)) )) (net RW_000_i (joined (portRef O (instanceRef I_208)) - (portRef I1 (instanceRef RW_000_DMA_0_i_a3_0_a2)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2)) - (portRef I1 (instanceRef pos_clk_as_000_dma6_i_0_0_a2)) + (portRef I1 (instanceRef RW_000_DMA_0_i_a3)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a3)) + (portRef I1 (instanceRef pos_clk_as_000_dma6_i_a3)) + )) + (net (rename CYCLE_DMA_i_0 "CYCLE_DMA_i[0]") (joined + (portRef O (instanceRef CYCLE_DMA_i_0)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_a3)) + (portRef I0 (instanceRef G_99)) )) (net CLK_EXP_i (joined (portRef O (instanceRef CLK_EXP_i)) @@ -1673,173 +1691,168 @@ (portRef O (instanceRef AS_000_DMA_i)) (portRef I0 (instanceRef un3_as_030)) )) - (net (rename A_i_1 "A_i[1]") (joined - (portRef O (instanceRef A_i_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_i_a3_0_a2)) + (net (rename AHIGH_i_25 "AHIGH_i[25]") (joined + (portRef O (instanceRef I_209)) + (portRef I1 (instanceRef un8_ciin_0_a3_1_2)) + )) + (net (rename AHIGH_i_24 "AHIGH_i[24]") (joined + (portRef O (instanceRef I_210)) + (portRef I0 (instanceRef un8_ciin_0_a3_1_2)) + )) + (net (rename AHIGH_i_27 "AHIGH_i[27]") (joined + (portRef O (instanceRef I_211)) + (portRef I1 (instanceRef un8_ciin_0_a3_1_3)) + )) + (net (rename AHIGH_i_26 "AHIGH_i[26]") (joined + (portRef O (instanceRef I_212)) + (portRef I0 (instanceRef un8_ciin_0_a3_1_3)) + )) + (net (rename AHIGH_i_29 "AHIGH_i[29]") (joined + (portRef O (instanceRef I_213)) + (portRef I1 (instanceRef un8_ciin_0_a3_1_4)) + )) + (net (rename AHIGH_i_28 "AHIGH_i[28]") (joined + (portRef O (instanceRef I_214)) + (portRef I0 (instanceRef un8_ciin_0_a3_1_4)) + )) + (net (rename AHIGH_i_31 "AHIGH_i[31]") (joined + (portRef O (instanceRef I_215)) + (portRef I1 (instanceRef un8_ciin_0_a3_1_5)) + )) + (net (rename AHIGH_i_30 "AHIGH_i[30]") (joined + (portRef O (instanceRef I_216)) + (portRef I0 (instanceRef un8_ciin_0_a3_1_5)) + )) + (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined + (portRef O (instanceRef SM_AMIGA_i_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a3_0_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a3_2)) + )) + (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined + (portRef O (instanceRef SM_AMIGA_i_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a3_0_1)) + )) + (net DTACK_D0_i (joined + (portRef O (instanceRef DTACK_D0_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_0_3)) + )) + (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined + (portRef O (instanceRef SM_AMIGA_i_i_7)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0_6)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a3_0)) + )) + (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined + (portRef O (instanceRef SM_AMIGA_i_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a3_0_3)) + )) + (net (rename A_DECODE_i_20 "A_DECODE_i[20]") (joined + (portRef O (instanceRef A_DECODE_i_20)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_a2_2)) )) (net AMIGA_BUS_ENABLE_DMA_LOW_i (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) (portRef I0 (instanceRef un1_amiga_bus_enable_low)) )) - (net (rename A_DECODE_i_19 "A_DECODE_i[19]") (joined - (portRef O (instanceRef A_DECODE_i_19)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_3)) + (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined + (portRef O (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef cpu_est_2_0_0_o2_3)) + (portRef I1 (instanceRef cpu_est_2_0_0_a3_1)) + (portRef I1 (instanceRef cpu_est_0_0_a3_0)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3_2)) )) - (net (rename A_DECODE_i_18 "A_DECODE_i[18]") (joined - (portRef O (instanceRef A_DECODE_i_18)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_3)) - )) - (net (rename A_DECODE_i_16 "A_DECODE_i[16]") (joined - (portRef O (instanceRef A_DECODE_i_16)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_2)) + (net AS_030_i (joined + (portRef O (instanceRef I_219)) + (portRef I0 (instanceRef pos_clk_DSACK1_INT_1_i_a2)) + (portRef I1 (instanceRef pos_clk_AS_000_INT_1_i_a2)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_a3)) + (portRef I0 (instanceRef AS_030_D0_0_0)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_a2_1)) + (portRef I1 (instanceRef un11_amiga_bus_enable_high_0_a3_0)) )) (net AMIGA_BUS_ENABLE_DMA_HIGH_i (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_i)) - (portRef I0 (instanceRef un11_amiga_bus_enable_high_0_0_a2)) - )) - (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined - (portRef O (instanceRef SM_AMIGA_i_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0)) - )) - (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined - (portRef O (instanceRef SM_AMIGA_i_5)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_5)) + (portRef I0 (instanceRef un11_amiga_bus_enable_high_0_a3)) )) (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined (portRef O (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_6)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a3_6)) )) - (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined - (portRef O (instanceRef SM_AMIGA_i_i_7)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_6)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_a2_2)) - )) - (net AS_030_i (joined - (portRef O (instanceRef I_210)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) - (portRef I0 (instanceRef AS_030_D0_0_0_0)) - (portRef I0 (instanceRef un21_berr_0_a3_0_a2_1)) - (portRef I1 (instanceRef pos_clk_AS_000_INT_1_i_a2_0_a2)) - (portRef I0 (instanceRef pos_clk_DSACK1_INT_1_i_a2_0_a2)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i)) - (portRef I1 (instanceRef un11_amiga_bus_enable_high_0_0_a2_0)) - )) - (net AS_000_INT_i (joined - (portRef O (instanceRef AS_000_INT_i)) - (portRef I0 (instanceRef pos_clk_AS_000_INT_1_i_a2_0_a2)) - )) - (net DSACK1_INT_i (joined - (portRef O (instanceRef DSACK1_INT_i)) - (portRef I1 (instanceRef pos_clk_DSACK1_INT_1_i_a2_0_a2)) - )) - (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined - (portRef O (instanceRef SM_AMIGA_i_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1)) - )) - (net FPU_SENSE_i (joined - (portRef O (instanceRef FPU_SENSE_i)) - (portRef I1 (instanceRef un21_fpu_cs_0_a3_0_a2_1)) - )) - (net AS_030_D1_i (joined - (portRef O (instanceRef AS_030_D1_i)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_a2_1)) - )) - (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined - (portRef O (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_1)) - (portRef I1 (instanceRef cpu_est_0_0_0_a2_0)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_o2_3)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_2)) + (net AS_030_D0_i (joined + (portRef O (instanceRef AS_030_D0_i)) + (portRef I0 (instanceRef un8_ciin_0_a3_1_0)) )) (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined (portRef O (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_2)) - (portRef I1 (instanceRef cpu_est_2_0_0_a2_0_1)) - (portRef I1 (instanceRef un5_e_0_0_a2_0)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a3_0_1)) + (portRef I1 (instanceRef un5_e_0_a3_0)) )) (net VPA_D_i (joined (portRef O (instanceRef VPA_D_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_2_3)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_2_3)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_2)) )) - (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined - (portRef O (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) + (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined + (portRef O (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a3_5)) )) (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined (portRef O (instanceRef SM_AMIGA_i_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a3_4)) )) (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined (portRef O (instanceRef cpu_est_i_1)) (portRef I0 (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_o2)) - (portRef I1 (instanceRef cpu_est_2_0_0_a2_0_1_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_o2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a3_0_1_1)) )) (net (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (joined (portRef O (instanceRef CLK_000_D_i_0)) - (portRef I1 (instanceRef N_130_i_0_o2_i_o2)) + (portRef I1 (instanceRef CLK_000_NE_0_o3_i_o2)) )) (net (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (joined (portRef O (instanceRef CLK_000_D_i_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_1)) - )) - (net AS_030_D0_i (joined - (portRef O (instanceRef AS_030_D0_i)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_0)) )) (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined (portRef O (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef cpu_est_2_0_0_a2_0_2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_o2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a2_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_o2)) )) - (net DTACK_D0_i (joined - (portRef O (instanceRef DTACK_D0_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) + (net DSACK1_INT_i (joined + (portRef O (instanceRef DSACK1_INT_i)) + (portRef I1 (instanceRef pos_clk_DSACK1_INT_1_i_a2)) )) - (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined - (portRef O (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2)) + (net AS_000_INT_i (joined + (portRef O (instanceRef AS_000_INT_i)) + (portRef I0 (instanceRef pos_clk_AS_000_INT_1_i_a2)) + )) + (net (rename A_DECODE_i_16 "A_DECODE_i[16]") (joined + (portRef O (instanceRef A_DECODE_i_16)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_a2_2)) + )) + (net (rename A_DECODE_i_19 "A_DECODE_i[19]") (joined + (portRef O (instanceRef A_DECODE_i_19)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_a2_3)) + )) + (net (rename A_DECODE_i_18 "A_DECODE_i[18]") (joined + (portRef O (instanceRef A_DECODE_i_18)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_a2_2)) + )) + (net FPU_SENSE_i (joined + (portRef O (instanceRef FPU_SENSE_i)) + (portRef I1 (instanceRef un21_fpu_cs_0_a3)) )) (net AS_030_000_SYNC_i (joined (portRef O (instanceRef AS_030_000_SYNC_i)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) - (portRef I1 (instanceRef un11_amiga_bus_enable_high_0_0_a2_0_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_2_6)) + (portRef I1 (instanceRef un11_amiga_bus_enable_high_0_a3_0_1)) )) - (net (rename AHIGH_i_30 "AHIGH_i[30]") (joined - (portRef O (instanceRef I_212)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_4)) - )) - (net (rename AHIGH_i_31 "AHIGH_i[31]") (joined - (portRef O (instanceRef I_213)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_4)) - )) - (net (rename AHIGH_i_28 "AHIGH_i[28]") (joined - (portRef O (instanceRef I_214)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_3)) - )) - (net (rename AHIGH_i_29 "AHIGH_i[29]") (joined - (portRef O (instanceRef I_215)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_3)) - )) - (net (rename AHIGH_i_26 "AHIGH_i[26]") (joined - (portRef O (instanceRef I_216)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_2)) - )) - (net (rename AHIGH_i_27 "AHIGH_i[27]") (joined - (portRef O (instanceRef I_217)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_2)) - )) - (net (rename AHIGH_i_24 "AHIGH_i[24]") (joined - (portRef O (instanceRef I_218)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_1)) - )) - (net (rename AHIGH_i_25 "AHIGH_i[25]") (joined - (portRef O (instanceRef I_219)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_1)) + (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined + (portRef O (instanceRef SM_AMIGA_i_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a3_0)) )) (net N_187_i (joined (portRef O (instanceRef N_187_i)) @@ -1857,28 +1870,24 @@ (portRef O (instanceRef CLK_OUT_PRE_50_i)) (portRef D (instanceRef CLK_OUT_PRE_50)) )) - (net N_150_i (joined - (portRef O (instanceRef N_150_i)) - (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) - )) - (net N_126_i (joined - (portRef O (instanceRef N_126_i)) + (net N_212_i (joined + (portRef O (instanceRef N_212_i)) (portRef D (instanceRef RW_000_DMA)) )) - (net N_151_i (joined - (portRef O (instanceRef N_151_i)) + (net N_213_i (joined + (portRef O (instanceRef N_213_i)) (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) )) (net un2_ds_030_i (joined (portRef O (instanceRef un2_ds_030_i)) (portRef I0 (instanceRef DS_030)) )) - (net N_219_i (joined - (portRef O (instanceRef N_219_i)) + (net N_225_i (joined + (portRef O (instanceRef N_225_i)) (portRef I0 (instanceRef DSACK1)) )) - (net N_175_i (joined - (portRef O (instanceRef N_175_i)) + (net N_224_i (joined + (portRef O (instanceRef N_224_i)) (portRef I0 (instanceRef AS_000)) )) (net un3_as_030_i (joined @@ -1887,8 +1896,8 @@ )) (net AS_030_c (joined (portRef O (instanceRef AS_030)) - (portRef I0 (instanceRef I_210)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef I_219)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) )) (net AS_030 (joined (portRef AS_030) @@ -1896,7 +1905,7 @@ )) (net AS_000_c (joined (portRef O (instanceRef AS_000)) - (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0_a2)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_a2)) (portRef I0 (instanceRef I_207)) )) (net AS_000 (joined @@ -1906,7 +1915,7 @@ (net RW_000_c (joined (portRef O (instanceRef RW_000)) (portRef I0 (instanceRef I_208)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_2)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a3_0_2)) )) (net RW_000 (joined (portRef IO (instanceRef RW_000)) @@ -1918,8 +1927,8 @@ )) (net UDS_000_c (joined (portRef O (instanceRef UDS_000)) - (portRef I1 (instanceRef A0_DMA_0_0_0_a2)) - (portRef I1 (instanceRef AMIGA_DS_0_0_0_a2)) + (portRef I1 (instanceRef A0_DMA_0_0_a3)) + (portRef I1 (instanceRef AMIGA_DS_0_0_a3)) (portRef I0 (instanceRef UDS_000_c_i)) )) (net UDS_000 (joined @@ -1928,7 +1937,7 @@ )) (net LDS_000_c (joined (portRef O (instanceRef LDS_000)) - (portRef I0 (instanceRef AMIGA_DS_0_0_0_a2)) + (portRef I0 (instanceRef AMIGA_DS_0_0_a3)) (portRef I0 (instanceRef LDS_000_c_i)) )) (net LDS_000 (joined @@ -1953,7 +1962,7 @@ )) (net (rename AHIGH_c_24 "AHIGH_c[24]") (joined (portRef O (instanceRef AHIGH_24)) - (portRef I0 (instanceRef I_218)) + (portRef I0 (instanceRef I_210)) )) (net (rename AHIGH_24 "AHIGH[24]") (joined (portRef IO (instanceRef AHIGH_24)) @@ -1961,7 +1970,7 @@ )) (net (rename AHIGH_c_25 "AHIGH_c[25]") (joined (portRef O (instanceRef AHIGH_25)) - (portRef I0 (instanceRef I_219)) + (portRef I0 (instanceRef I_209)) )) (net (rename AHIGH_25 "AHIGH[25]") (joined (portRef IO (instanceRef AHIGH_25)) @@ -1969,7 +1978,7 @@ )) (net (rename AHIGH_c_26 "AHIGH_c[26]") (joined (portRef O (instanceRef AHIGH_26)) - (portRef I0 (instanceRef I_216)) + (portRef I0 (instanceRef I_212)) )) (net (rename AHIGH_26 "AHIGH[26]") (joined (portRef IO (instanceRef AHIGH_26)) @@ -1977,7 +1986,7 @@ )) (net (rename AHIGH_c_27 "AHIGH_c[27]") (joined (portRef O (instanceRef AHIGH_27)) - (portRef I0 (instanceRef I_217)) + (portRef I0 (instanceRef I_211)) )) (net (rename AHIGH_27 "AHIGH[27]") (joined (portRef IO (instanceRef AHIGH_27)) @@ -1993,7 +2002,7 @@ )) (net (rename AHIGH_c_29 "AHIGH_c[29]") (joined (portRef O (instanceRef AHIGH_29)) - (portRef I0 (instanceRef I_215)) + (portRef I0 (instanceRef I_213)) )) (net (rename AHIGH_29 "AHIGH[29]") (joined (portRef IO (instanceRef AHIGH_29)) @@ -2001,7 +2010,7 @@ )) (net (rename AHIGH_c_30 "AHIGH_c[30]") (joined (portRef O (instanceRef AHIGH_30)) - (portRef I0 (instanceRef I_212)) + (portRef I0 (instanceRef I_216)) )) (net (rename AHIGH_30 "AHIGH[30]") (joined (portRef IO (instanceRef AHIGH_30)) @@ -2009,7 +2018,7 @@ )) (net (rename AHIGH_c_31 "AHIGH_c[31]") (joined (portRef O (instanceRef AHIGH_31)) - (portRef I0 (instanceRef I_213)) + (portRef I0 (instanceRef I_215)) )) (net (rename AHIGH_31 "AHIGH[31]") (joined (portRef (member ahigh 0)) @@ -2123,7 +2132,7 @@ )) (net (rename A_DECODE_c_17 "A_DECODE_c[17]") (joined (portRef O (instanceRef A_DECODE_17)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_2)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_a2_1)) )) (net (rename A_DECODE_17 "A_DECODE[17]") (joined (portRef (member a_decode 6)) @@ -2140,6 +2149,7 @@ (net (rename A_DECODE_c_19 "A_DECODE_c[19]") (joined (portRef O (instanceRef A_DECODE_19)) (portRef I0 (instanceRef A_DECODE_i_19)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_a2_1)) )) (net (rename A_DECODE_19 "A_DECODE[19]") (joined (portRef (member a_decode 4)) @@ -2147,7 +2157,8 @@ )) (net (rename A_DECODE_c_20 "A_DECODE_c[20]") (joined (portRef O (instanceRef A_DECODE_20)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_6)) + (portRef I0 (instanceRef A_DECODE_i_20)) + (portRef I1 (instanceRef un8_ciin_0_a3_1_0)) )) (net (rename A_DECODE_20 "A_DECODE[20]") (joined (portRef (member a_decode 3)) @@ -2155,7 +2166,8 @@ )) (net (rename A_DECODE_c_21 "A_DECODE_c[21]") (joined (portRef O (instanceRef A_DECODE_21)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_6)) + (portRef I0 (instanceRef un8_ciin_0_a3_2)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_a2_1)) )) (net (rename A_DECODE_21 "A_DECODE[21]") (joined (portRef (member a_decode 2)) @@ -2163,7 +2175,7 @@ )) (net (rename A_DECODE_c_22 "A_DECODE_c[22]") (joined (portRef O (instanceRef A_DECODE_22)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_11)) + (portRef I0 (instanceRef un8_ciin_0_a3_1_1)) )) (net (rename A_DECODE_22 "A_DECODE[22]") (joined (portRef (member a_decode 1)) @@ -2171,7 +2183,7 @@ )) (net (rename A_DECODE_c_23 "A_DECODE_c[23]") (joined (portRef O (instanceRef A_DECODE_23)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_5)) + (portRef I1 (instanceRef un8_ciin_0_a3_1_1)) )) (net (rename A_DECODE_23 "A_DECODE[23]") (joined (portRef (member a_decode 0)) @@ -2188,8 +2200,7 @@ )) (net (rename A_c_1 "A_c[1]") (joined (portRef O (instanceRef A_1)) - (portRef I0 (instanceRef A_i_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_i_a3_0_a2)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_o3)) )) (net (rename A_1 "A[1]") (joined (portRef (member a 0)) @@ -2197,10 +2208,10 @@ )) (net nEXP_SPACE_c (joined (portRef O (instanceRef nEXP_SPACE)) - (portRef I1 (instanceRef un1_dsack1_0_o3_0)) + (portRef I1 (instanceRef un1_dsack1_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_0_6)) (portRef I0 (instanceRef nEXP_SPACE_i)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0)) - (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a3_i)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_i)) )) (net nEXP_SPACE (joined (portRef nEXP_SPACE) @@ -2208,7 +2219,7 @@ )) (net BERR_c (joined (portRef O (instanceRef BERR)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0_1_3)) )) (net BERR (joined (portRef BERR) @@ -2238,9 +2249,10 @@ )) (net BGACK_000_c (joined (portRef O (instanceRef BGACK_000)) - (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0)) - (portRef I1 (instanceRef un21_berr_0_a3_0_a2_1)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0)) (portRef I0 (instanceRef BGACK_030_INT_0_m)) + (portRef I1 (instanceRef un21_fpu_cs_0_a3_1)) + (portRef I1 (instanceRef un21_berr_0_a3_1)) )) (net BGACK_000 (joined (portRef BGACK_000) @@ -2341,7 +2353,7 @@ (net FPU_SENSE_c (joined (portRef O (instanceRef FPU_SENSE)) (portRef I0 (instanceRef FPU_SENSE_i)) - (portRef I1 (instanceRef un21_berr_0_a3_0_a2_1_0)) + (portRef I1 (instanceRef un21_berr_0_a3)) )) (net FPU_SENSE (joined (portRef FPU_SENSE) @@ -2438,45 +2450,45 @@ )) (net RST_c (joined (portRef O (instanceRef RST)) + (portRef I1 (instanceRef IPL_D0_0_1)) (portRef I1 (instanceRef IPL_D0_0_0)) - (portRef I1 (instanceRef DTACK_D0_0)) - (portRef I0 (instanceRef VPA_D_0)) (portRef I1 (instanceRef VMA_INT_1)) (portRef I1 (instanceRef DS_000_ENABLE_1)) + (portRef I1 (instanceRef AS_030_D1_0_m)) + (portRef I0 (instanceRef AS_030_D1_0_r)) (portRef I1 (instanceRef IPL_030_1_2)) (portRef I1 (instanceRef IPL_030_1_1)) (portRef I1 (instanceRef IPL_030_1_0)) (portRef I1 (instanceRef IPL_D0_0_2)) - (portRef I1 (instanceRef IPL_D0_0_1)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) - (portRef I1 (instanceRef A0_DMA_0_0_0)) - (portRef I1 (instanceRef AMIGA_DS_0_0_0)) - (portRef I1 (instanceRef AS_030_D0_0_0_0)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_sqmuxa_i_0)) - (portRef I1 (instanceRef RW_000_INT_1)) + (portRef I1 (instanceRef AS_000_INT_0_i_a3_0)) + (portRef I1 (instanceRef AS_000_INT_0_i_a3)) + (portRef I1 (instanceRef DSACK1_INT_0_i_a3_0)) + (portRef I1 (instanceRef DSACK1_INT_0_i_a3)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) + (portRef I1 (instanceRef A0_DMA_0_0)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_2_sqmuxa_i)) + (portRef I0 (instanceRef VPA_D_0)) + (portRef I1 (instanceRef DTACK_D0_0)) + (portRef I1 (instanceRef AS_030_D0_0_0)) (portRef I1 (instanceRef AS_030_000_SYNC_1)) - (portRef I1 (instanceRef BGACK_030_INT_1)) - (portRef I1 (instanceRef DSACK1_INT_0_i_0_a2)) - (portRef I1 (instanceRef DSACK1_INT_0_i_0_a2_0)) - (portRef I1 (instanceRef AS_000_INT_0_i_0_a2)) - (portRef I1 (instanceRef AS_000_INT_0_i_0_a2_0)) - (portRef I1 (instanceRef un1_rst_2_i_o2)) - (portRef I1 (instanceRef AS_030_D1_0_m)) - (portRef I0 (instanceRef AS_030_D1_0_r)) + (portRef I1 (instanceRef RW_000_DMA_0_1_0_o3)) (portRef I1 (instanceRef UDS_000_INT_1)) (portRef I1 (instanceRef BG_000_1)) (portRef I1 (instanceRef LDS_000_INT_1)) + (portRef I1 (instanceRef RW_000_INT_1)) + (portRef I1 (instanceRef BGACK_030_INT_1)) (portRef I1 (instanceRef DS_000_DMA_1)) (portRef I1 (instanceRef AS_000_DMA_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_2_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_5)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_6)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_3)) + (portRef I1 (instanceRef AMIGA_DS_0_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_6)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0)) )) (net RST (joined (portRef RST) @@ -2491,7 +2503,7 @@ )) (net RW_c (joined (portRef O (instanceRef RW)) - (portRef I1 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_a2)) + (portRef I1 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_a2)) (portRef I0 (instanceRef RW_c_i)) )) (net RW (joined @@ -2500,7 +2512,7 @@ )) (net (rename FC_c_0 "FC_c[0]") (joined (portRef O (instanceRef FC_0)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_1)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_a2_5)) )) (net (rename FC_0 "FC[0]") (joined (portRef (member fc 1)) @@ -2508,7 +2520,7 @@ )) (net (rename FC_c_1 "FC_c[1]") (joined (portRef O (instanceRef FC_1)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_1)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_a2_3)) )) (net (rename FC_1 "FC[1]") (joined (portRef (member fc 0)) @@ -2519,7 +2531,7 @@ (portRef AMIGA_ADDR_ENABLE) )) (net AMIGA_BUS_DATA_DIR_c (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_i)) + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_i)) (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR)) )) (net AMIGA_BUS_DATA_DIR (joined @@ -2538,42 +2550,50 @@ (portRef O (instanceRef CIIN)) (portRef CIIN) )) - (net N_205_i (joined - (portRef O (instanceRef pos_clk_as_000_dma6_i_0_0)) - (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_0_i)) - (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa)) + (net N_181_i (joined + (portRef O (instanceRef N_181_i)) + (portRef I0 (instanceRef AMIGA_DS_0_0)) )) - (net N_140_i (joined - (portRef O (instanceRef N_140_i)) - (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_0_2)) + (net N_37_0 (joined + (portRef O (instanceRef AMIGA_DS_0_0)) + (portRef I0 (instanceRef AMIGA_DS_0_0_i)) )) - (net AMIGA_DS_i (joined - (portRef O (instanceRef AMIGA_DS_i)) - (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_0_1)) - )) - (net N_66_i (joined + (net N_206_i (joined (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i)) (portRef D (instanceRef CYCLE_DMA_0)) )) - (net N_199_i (joined - (portRef O (instanceRef N_199_i)) + (net N_176_i (joined + (portRef O (instanceRef N_176_i)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_2)) + )) + (net N_175_i (joined + (portRef O (instanceRef N_175_i)) (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_2)) )) + (net N_72_i (joined + (portRef O (instanceRef pos_clk_as_000_dma6_i_0)) + (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_i)) + (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa)) + )) (net N_198_i (joined (portRef O (instanceRef N_198_i)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) + (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_2)) )) - (net N_180_i (joined - (portRef O (instanceRef N_180_i)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0)) + (net AMIGA_DS_i (joined + (portRef O (instanceRef AMIGA_DS_i)) + (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_1)) )) - (net N_262_i (joined - (portRef O (instanceRef N_262_i)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0)) + (net N_186_i (joined + (portRef O (instanceRef N_186_i)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0)) + )) + (net N_185_i (joined + (portRef O (instanceRef N_185_i)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0)) )) (net AMIGA_BUS_DATA_DIR_c_0 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_i)) + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_i)) )) (net (rename pos_clk_un2_i "pos_clk.un2_i") (joined (portRef O (instanceRef G_99)) @@ -2595,14 +2615,18 @@ (portRef O (instanceRef AS_000_DMA_1)) (portRef I0 (instanceRef AS_000_DMA_1_i)) )) - (net N_220_i (joined - (portRef O (instanceRef un1_rst_2_i_o2)) - (portRef I0 (instanceRef RW_000_DMA_0_i_a3_0_a2)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_i_a3_0_a2)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_i_a3_0_a2)) - (portRef I0 (instanceRef un1_rst_2_i_o2_i)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_2)) + (net N_39_1_i (joined + (portRef O (instanceRef RW_000_DMA_0_1_0_o3)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_i_a3)) + (portRef I0 (instanceRef RW_000_DMA_0_i_a3)) + (portRef I0 (instanceRef RW_000_DMA_0_1_0_o3_i)) (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_1)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) + )) + (net N_34_0 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_i)) )) (net BG_030_c_i (joined (portRef O (instanceRef BG_030_c_i)) @@ -2644,14 +2668,6 @@ (portRef O (instanceRef RW_000_INT_1)) (portRef I0 (instanceRef RW_000_INT_1_i)) )) - (net N_11_i (joined - (portRef O (instanceRef N_11_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_1)) - )) - (net N_29_0 (joined - (portRef O (instanceRef AS_030_000_SYNC_1)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_i)) - )) (net N_5_i (joined (portRef O (instanceRef N_5_i)) (portRef I0 (instanceRef BGACK_030_INT_1)) @@ -2672,400 +2688,430 @@ (portRef O (instanceRef pos_clk_un10_sm_amiga)) (portRef I0 (instanceRef LDS_000_INT_0_m)) )) - (net un1_dsack1_i (joined - (portRef O (instanceRef un1_dsack1_0_o3_0)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_a2)) - (portRef OE (instanceRef DSACK1)) + (net N_231_i (joined + (portRef O (instanceRef N_231_i)) + (portRef I1 (instanceRef pos_clk_un6_bgack_000_0)) )) - (net N_69_i (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_sqmuxa_i_0)) + (net (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_i)) + )) + (net N_40_0 (joined + (portRef O (instanceRef AS_030_D0_0_0)) + (portRef I0 (instanceRef AS_030_D0_0_0_i)) + )) + (net un1_SM_AMIGA_0_sqmuxa_1_0 (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_i)) + )) + (net RW_c_i (joined + (portRef O (instanceRef RW_c_i)) + (portRef I1 (instanceRef pos_clk_RW_000_INT_5_0)) + )) + (net (rename pos_clk_RW_000_INT_5_0 "pos_clk.RW_000_INT_5_0") (joined + (portRef O (instanceRef pos_clk_RW_000_INT_5_0)) + (portRef I0 (instanceRef pos_clk_RW_000_INT_5_0_i)) + )) + (net N_201_i (joined + (portRef O (instanceRef N_201_i)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_o3)) + )) + (net N_81_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_o3)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_o3_i)) + )) + (net N_219_i (joined + (portRef O (instanceRef N_219_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_0_3)) + )) + (net N_202_i (joined + (portRef O (instanceRef N_202_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_0_1_3)) + )) + (net N_191_i (joined + (portRef O (instanceRef N_191_i)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_o3)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_1_0)) + )) + (net N_98_i (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_o3)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0)) + (portRef I0 (instanceRef pos_clk_RW_000_INT_5_0)) + )) + (net N_99_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_0_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0_i_3)) + )) + (net N_107_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_i_2)) + )) + (net N_192_i (joined + (portRef O (instanceRef N_192_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_1)) + )) + (net N_193_i (joined + (portRef O (instanceRef N_193_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_2_1)) + )) + (net N_113_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1)) + (portRef D (instanceRef SM_AMIGA_1)) + )) + (net N_11_i (joined + (portRef O (instanceRef N_11_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_1)) + )) + (net N_29_0 (joined + (portRef O (instanceRef AS_030_000_SYNC_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_i)) + )) + (net VPA_c_i (joined + (portRef O (instanceRef VPA_c_i)) + (portRef I1 (instanceRef VPA_D_0)) + )) + (net N_44_0 (joined + (portRef O (instanceRef VPA_D_0)) + (portRef I0 (instanceRef VPA_D_0_i)) + )) + (net DTACK_c_i (joined + (portRef O (instanceRef DTACK_c_i)) + (portRef I0 (instanceRef DTACK_D0_0)) + )) + (net N_45_0 (joined + (portRef O (instanceRef DTACK_D0_0)) + (portRef I0 (instanceRef DTACK_D0_0_i)) + )) + (net N_152_i (joined + (portRef O (instanceRef N_152_i)) + (portRef I0 (instanceRef cpu_est_2_0_0_1)) + )) + (net N_153_i (joined + (portRef O (instanceRef N_153_i)) + (portRef I1 (instanceRef cpu_est_2_0_0_1)) + )) + (net (rename cpu_est_2_0_1 "cpu_est_2_0[1]") (joined + (portRef O (instanceRef cpu_est_2_0_0_1)) + (portRef I0 (instanceRef cpu_est_2_0_0_i_1)) + )) + (net N_163_i (joined + (portRef O (instanceRef N_163_i)) + (portRef I1 (instanceRef cpu_est_0_0_0)) + )) + (net N_162_i (joined + (portRef O (instanceRef N_162_i)) + (portRef I0 (instanceRef cpu_est_0_0_0)) + )) + (net N_200_i (joined + (portRef O (instanceRef cpu_est_0_0_0)) + (portRef D (instanceRef cpu_est_0)) + )) + (net N_203_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_2_sqmuxa_i)) (portRef OE (instanceRef AS_000)) (portRef OE (instanceRef LDS_000)) (portRef OE (instanceRef RW_000)) (portRef OE (instanceRef UDS_000)) )) - (net N_163_i (joined - (portRef O (instanceRef N_163_i)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i)) - )) - (net N_244_0 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_i)) + (net un1_dsack1_i (joined + (portRef O (instanceRef un1_dsack1_0)) + (portRef OE (instanceRef DSACK1)) )) (net N_164_i (joined (portRef O (instanceRef N_164_i)) - (portRef I0 (instanceRef un11_amiga_bus_enable_high_0_0)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i)) )) - (net N_165_i (joined - (portRef O (instanceRef N_165_i)) - (portRef I1 (instanceRef un11_amiga_bus_enable_high_0_0)) + (net N_228_i (joined + (portRef O (instanceRef N_228_i)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i)) + )) + (net N_204_0 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i)) + )) + (net N_171_i (joined + (portRef O (instanceRef N_171_i)) + (portRef I0 (instanceRef un11_amiga_bus_enable_high_0)) + )) + (net N_172_i (joined + (portRef O (instanceRef N_172_i)) + (portRef I1 (instanceRef un11_amiga_bus_enable_high_0)) )) (net un11_amiga_bus_enable_high_i (joined - (portRef O (instanceRef un11_amiga_bus_enable_high_0_0)) + (portRef O (instanceRef un11_amiga_bus_enable_high_0)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_HIGH)) )) - (net un10_ciin_i (joined - (portRef O (instanceRef un10_ciin_i)) - (portRef I1 (instanceRef un13_ciin_i_0_0)) - )) - (net N_60_0 (joined - (portRef O (instanceRef un13_ciin_i_0_0)) - (portRef I0 (instanceRef un13_ciin_i_0_0_i)) - )) - (net N_274_i (joined - (portRef O (instanceRef N_274_i)) - (portRef I1 (instanceRef pos_clk_un6_bgack_000_0_0)) - )) - (net (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (joined - (portRef O (instanceRef pos_clk_un6_bgack_000_0_0)) - (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0_i)) - )) - (net RW_c_i (joined - (portRef O (instanceRef RW_c_i)) - (portRef I1 (instanceRef pos_clk_RW_000_INT_5_0_0)) - )) - (net (rename pos_clk_RW_000_INT_5_0 "pos_clk.RW_000_INT_5_0") (joined - (portRef O (instanceRef pos_clk_RW_000_INT_5_0_0)) - (portRef I0 (instanceRef pos_clk_RW_000_INT_5_0_0_i)) - )) - (net N_168_i (joined - (portRef O (instanceRef N_168_i)) - (portRef I1 (instanceRef DSACK1_INT_0_i_0)) - )) - (net N_167_i (joined - (portRef O (instanceRef N_167_i)) - (portRef I0 (instanceRef DSACK1_INT_0_i_0)) - )) - (net N_206_i (joined - (portRef O (instanceRef DSACK1_INT_0_i_0)) - (portRef D (instanceRef DSACK1_INT)) - )) - (net N_170_i (joined - (portRef O (instanceRef N_170_i)) - (portRef I1 (instanceRef AS_000_INT_0_i_0)) - )) - (net N_169_i (joined - (portRef O (instanceRef N_169_i)) - (portRef I0 (instanceRef AS_000_INT_0_i_0)) - )) - (net N_48_i (joined - (portRef O (instanceRef AS_000_INT_0_i_0)) - (portRef D (instanceRef AS_000_INT)) - )) - (net N_38_0 (joined - (portRef O (instanceRef AS_030_D0_0_0_0)) - (portRef I0 (instanceRef AS_030_D0_0_0_0_i)) - )) - (net un1_SM_AMIGA_0_sqmuxa_1_0 (joined - (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1)) - (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1_i)) - )) - (net N_282_0 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_o2)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_i)) - (portRef I1 (instanceRef un21_berr_0_a3_0_a2)) - (portRef I1 (instanceRef un21_fpu_cs_0_a3_0_a2)) + (net N_85_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_0_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_1_6)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_o2_2)) )) (net (rename CLK_000_D_i_3 "CLK_000_D_i[3]") (joined (portRef O (instanceRef CLK_000_D_i_3)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_2_6)) )) - (net N_96_0 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_6)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_i_0)) + (net N_100_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_i_6)) )) - (net N_129_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0)) - (portRef I0 (instanceRef DSACK1_INT_0_i_0_a2_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_0)) + (net AS_030_D1_i (joined + (portRef O (instanceRef AS_030_D1_i)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_o2_1)) )) - (net N_268_i (joined - (portRef O (instanceRef N_268_i)) - (portRef I0 (instanceRef pos_clk_RW_000_INT_5_0_0_o2)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) + (net N_104_0 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_o2)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_o2_i)) )) - (net N_246_i (joined - (portRef O (instanceRef pos_clk_RW_000_INT_5_0_0_o2)) - (portRef I0 (instanceRef pos_clk_RW_000_INT_5_0_0)) - (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_1)) + (net N_105_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_i_4)) )) - (net N_132_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_6)) - )) - (net N_113_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1)) - (portRef D (instanceRef SM_AMIGA_1)) - )) - (net N_142_i (joined - (portRef O (instanceRef N_142_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_2_1)) - )) - (net N_141_i (joined - (portRef O (instanceRef N_141_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_1)) - )) - (net N_135_0 (joined - (portRef O (instanceRef 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(portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a2_1)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_i_0)) + (net N_96_i (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a3_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_i_0)) )) - (net N_107_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_3)) + (net N_95_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_i_3)) )) - (net N_203_i (joined - (portRef O (instanceRef N_203_i)) - (portRef I1 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o2)) + (net N_220_i (joined + (portRef O (instanceRef N_220_i)) + (portRef I1 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3)) )) (net un1_DS_000_ENABLE_0_sqmuxa_0 (joined - (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o2)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) - (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_0_o2_i)) - )) - (net N_201_i (joined - (portRef O (instanceRef N_201_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_1_3)) - )) - (net N_202_i (joined - (portRef O (instanceRef N_202_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) + (portRef O (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3)) + (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_i)) + (portRef I0 (instanceRef un1_DS_000_ENABLE_0_sqmuxa_0_o3_i)) )) (net VMA_INT_i (joined (portRef O (instanceRef VMA_INT_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_2_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_2_3)) )) - (net N_98_i (joined - (portRef O (instanceRef cpu_est_2_0_0_0_o2_2)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_3)) - (portRef I0 (instanceRef cpu_est_2_0_0_a2_0_2)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_i_2)) + (net N_89_i (joined + (portRef O (instanceRef cpu_est_2_0_0_o2_2)) + (portRef I0 (instanceRef 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(portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_1)) + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_o2)) + (portRef I0 (instanceRef un5_e_0_a3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_1_3)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3_1)) )) (net N_80_i (joined - (portRef O (instanceRef cpu_est_2_0_0_0_o2_3)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_i_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_1_3)) + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a3_0_0)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_1_0_0_o2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_i_0)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3_1)) )) - (net N_72_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_1)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) - (portRef I0 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SM_AMIGA_srsts_i_0_a3_3)) + (portRef I0 (instanceRef CLK_000_NE_0_o3_i_o2_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_1_2)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_1)) (portRef I0 (instanceRef G_90_1)) )) - (net N_59_i (joined - (portRef O (instanceRef pos_clk_un6_bg_030_0_a3_i)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a3_i_i)) + (net N_78_0 (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_i)) + )) + (net N_74_i (joined + (portRef O (instanceRef pos_clk_un6_bg_030_i)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_i_i)) + )) + (net N_197_i (joined + (portRef O (instanceRef N_197_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_5)) + )) + (net N_121_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_5)) + (portRef D (instanceRef SM_AMIGA_5)) + )) + (net N_195_i (joined + (portRef O (instanceRef N_195_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_3)) + )) + (net N_196_i (joined + (portRef O (instanceRef N_196_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_3)) + )) + (net N_117_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_3)) + (portRef D (instanceRef SM_AMIGA_3)) + )) + (net N_194_i (joined + (portRef O (instanceRef N_194_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_2)) + )) + (net N_115_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_2)) + (portRef D (instanceRef SM_AMIGA_2)) )) (net N_190_i (joined (portRef O (instanceRef N_190_i)) - (portRef I0 (instanceRef cpu_est_0_0_0_0)) - )) - (net N_191_i (joined - (portRef O (instanceRef N_191_i)) - (portRef I1 (instanceRef cpu_est_0_0_0_0)) - )) - (net N_200_i (joined - (portRef O (instanceRef cpu_est_0_0_0_0)) - (portRef D (instanceRef cpu_est_0)) - )) - (net N_267_i (joined - (portRef O (instanceRef N_267_i)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_1_0)) )) (net N_127_i (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_0)) + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0)) (portRef D (instanceRef SM_AMIGA_i_7)) )) - (net N_266_i (joined - (portRef O (instanceRef N_266_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_6)) + (net N_214_i (joined + (portRef O (instanceRef N_214_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_6)) )) (net N_123_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_6)) + (portRef O (instanceRef SM_AMIGA_srsts_i_0_6)) (portRef D (instanceRef SM_AMIGA_6)) )) - (net N_186_i (joined - (portRef O (instanceRef N_186_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_5)) - )) - (net N_121_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_5)) - (portRef D (instanceRef SM_AMIGA_5)) - )) - (net N_185_i (joined - (portRef O (instanceRef N_185_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) - )) - (net N_119_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_4)) - (portRef D (instanceRef SM_AMIGA_4)) - )) - (net N_183_i (joined - (portRef O (instanceRef N_183_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) - )) (net N_184_i (joined (portRef O (instanceRef N_184_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) )) - (net N_117_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_3)) - (portRef D (instanceRef SM_AMIGA_3)) + (net (rename pos_clk_SIZE_DMA_6_0_1 "pos_clk.SIZE_DMA_6_0[1]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_1)) + )) + (net N_183_i (joined + (portRef O (instanceRef N_183_i)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) + )) + (net (rename pos_clk_SIZE_DMA_6_0_0 "pos_clk.SIZE_DMA_6_0[0]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) )) (net N_182_i (joined (portRef O (instanceRef N_182_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_2)) + (portRef I0 (instanceRef A0_DMA_0_0)) )) - (net N_115_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_2)) - (portRef D (instanceRef SM_AMIGA_2)) + (net N_38_0 (joined + (portRef O (instanceRef A0_DMA_0_0)) + (portRef I0 (instanceRef A0_DMA_0_0_i)) )) - (net N_181_i (joined - (portRef O (instanceRef N_181_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_0)) + (net N_179_i (joined + (portRef O (instanceRef N_179_i)) + (portRef I0 (instanceRef AS_000_INT_0_i)) )) - (net N_111_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_0)) - (portRef D (instanceRef SM_AMIGA_0)) + (net N_180_i (joined + (portRef O (instanceRef N_180_i)) + (portRef I1 (instanceRef AS_000_INT_0_i)) )) - (net N_260_i (joined - (portRef O (instanceRef N_260_i)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) + (net N_209_i (joined + (portRef O (instanceRef AS_000_INT_0_i)) + (portRef D (instanceRef AS_000_INT)) )) - (net (rename pos_clk_SIZE_DMA_6_0_1 "pos_clk.SIZE_DMA_6_0[1]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_1)) + (net N_177_i (joined + (portRef O (instanceRef N_177_i)) + (portRef I0 (instanceRef DSACK1_INT_0_i)) )) - (net N_259_i (joined - (portRef O (instanceRef N_259_i)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) - )) - (net (rename pos_clk_SIZE_DMA_6_0_0 "pos_clk.SIZE_DMA_6_0[0]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_0)) - )) - (net N_63_0 (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i_0)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i_0_i)) - )) - (net N_155_i (joined - (portRef O (instanceRef N_155_i)) - (portRef I0 (instanceRef un5_e_0_0)) - )) - (net N_162_i (joined - (portRef O (instanceRef N_162_i)) - (portRef I1 (instanceRef un5_e_0_0)) - )) - (net un5_e_0 (joined - (portRef O (instanceRef un5_e_0_0)) - (portRef I0 (instanceRef un5_e_0_0_i)) - )) - (net N_154_i (joined - (portRef O (instanceRef N_154_i)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_3)) - )) - (net (rename cpu_est_2_0_3 "cpu_est_2_0[3]") (joined - (portRef O (instanceRef cpu_est_2_0_0_0_3)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_i_3)) - )) - (net N_149_i (joined - (portRef O (instanceRef N_149_i)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_2)) + (net N_178_i (joined + (portRef O (instanceRef N_178_i)) + (portRef I1 (instanceRef DSACK1_INT_0_i)) )) (net N_208_i (joined - (portRef O (instanceRef N_208_i)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_2)) + (portRef O (instanceRef DSACK1_INT_0_i)) + (portRef D (instanceRef DSACK1_INT)) + )) + (net un8_ciin_i (joined + (portRef O (instanceRef un8_ciin_i)) + (portRef I1 (instanceRef un11_ciin_i_0)) + )) + (net N_205_0 (joined + (portRef O (instanceRef un11_ciin_i_0)) + (portRef I0 (instanceRef un11_ciin_i_0_i)) + )) + (net N_160_i (joined + (portRef O (instanceRef N_160_i)) + (portRef I0 (instanceRef un5_e_0)) + )) + (net N_161_i (joined + (portRef O (instanceRef N_161_i)) + (portRef I1 (instanceRef un5_e_0)) + )) + (net un5_e_0 (joined + (portRef O (instanceRef un5_e_0)) + (portRef I0 (instanceRef un5_e_0_i)) + )) + (net N_159_i (joined + (portRef O (instanceRef N_159_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_4)) + )) + (net N_119_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_4)) + (portRef D (instanceRef SM_AMIGA_4)) + )) + (net N_158_i (joined + (portRef O (instanceRef N_158_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_0)) + )) + (net N_111_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0)) + (portRef D (instanceRef SM_AMIGA_0)) + )) + (net N_157_i (joined + (portRef O (instanceRef N_157_i)) + (portRef I1 (instanceRef cpu_est_2_0_0_3)) + )) + (net (rename cpu_est_2_0_3 "cpu_est_2_0[3]") (joined + (portRef O (instanceRef cpu_est_2_0_0_3)) + (portRef I0 (instanceRef cpu_est_2_0_0_i_3)) + )) + (net N_156_i (joined + (portRef O (instanceRef N_156_i)) + (portRef I0 (instanceRef cpu_est_2_0_0_2)) + )) + (net N_229_i (joined + (portRef O (instanceRef N_229_i)) + (portRef I1 (instanceRef cpu_est_2_0_0_2)) )) (net (rename cpu_est_2_0_2 "cpu_est_2_0[2]") (joined - (portRef O (instanceRef cpu_est_2_0_0_0_2)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_i_2)) + (portRef O (instanceRef cpu_est_2_0_0_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_i_2)) )) - (net N_147_i (joined - (portRef O (instanceRef N_147_i)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_1)) + (net N_126_i (joined + (portRef O (instanceRef N_126_i)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0)) )) - (net N_148_i (joined - (portRef O (instanceRef N_148_i)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_1)) - )) - (net (rename cpu_est_2_0_1 "cpu_est_2_0[1]") (joined - (portRef O (instanceRef cpu_est_2_0_0_0_1)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_i_1)) - )) - (net N_146_i (joined - (portRef O (instanceRef N_146_i)) - (portRef I0 (instanceRef A0_DMA_0_0_0)) - )) - (net N_36_0 (joined - (portRef O (instanceRef A0_DMA_0_0_0)) - (portRef I0 (instanceRef A0_DMA_0_0_0_i)) - )) - (net N_145_i (joined - (portRef O (instanceRef N_145_i)) - (portRef I0 (instanceRef AMIGA_DS_0_0_0)) - )) - (net N_35_0 (joined - (portRef O (instanceRef AMIGA_DS_0_0_0)) - (portRef I0 (instanceRef AMIGA_DS_0_0_0_i)) - )) - (net N_143_i (joined - (portRef O (instanceRef N_143_i)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0)) - )) - (net N_144_i (joined - (portRef O (instanceRef N_144_i)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0)) + (net N_150_i (joined + (portRef O (instanceRef N_150_i)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0)) )) (net (rename pos_clk_un9_clk_000_pe_0 "pos_clk.un9_clk_000_pe_0") (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_i)) + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_i)) )) (net N_20_i (joined (portRef O (instanceRef N_20_i)) @@ -3115,22 +3161,6 @@ (portRef O (instanceRef IPL_D0_0_0)) (portRef I0 (instanceRef IPL_D0_0_i_0)) )) - (net DTACK_c_i (joined - (portRef O (instanceRef DTACK_c_i)) - (portRef I0 (instanceRef DTACK_D0_0)) - )) - (net N_45_0 (joined - (portRef O (instanceRef DTACK_D0_0)) - (portRef I0 (instanceRef DTACK_D0_0_i)) - )) - (net VPA_c_i (joined - (portRef O (instanceRef VPA_c_i)) - (portRef I1 (instanceRef VPA_D_0)) - )) - (net N_44_0 (joined - (portRef O (instanceRef VPA_D_0)) - (portRef I0 (instanceRef VPA_D_0_i)) - )) (net N_13_i (joined (portRef O (instanceRef N_13_i)) (portRef I0 (instanceRef VMA_INT_1)) @@ -3155,143 +3185,139 @@ (portRef O (instanceRef un1_UDS_000_INT)) (portRef I0 (instanceRef un1_UDS_000_INT_i)) )) - (net N_96_0_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) + (net N_104_0_1 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_o2_1)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_o2)) )) - (net N_96_0_2 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) + (net N_104_0_2 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_o2_2)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_o2)) )) - (net N_282_0_1 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_o2_1)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_4)) + (net N_100_0_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_1_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_6)) )) - (net N_282_0_2 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_o2_2)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_o2_4)) + (net N_100_0_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_2_6)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_6)) )) - (net N_282_0_3 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_o2_3)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_o2)) + (net N_113_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1)) )) - (net N_282_0_4 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_o2_4)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_o2)) + (net N_113_i_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_2_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1)) + )) + (net N_107_0_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_2)) + )) + (net N_99_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_0_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0_3)) )) (net (rename pos_clk_un10_sm_amiga_i_1 "pos_clk.un10_sm_amiga_i_1") (joined (portRef O (instanceRef pos_clk_un10_sm_amiga_1)) (portRef I0 (instanceRef pos_clk_un10_sm_amiga)) )) - (net un10_ciin_1 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_1)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_7)) + (net N_202_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_3)) )) - (net un10_ciin_2 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_2)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_7)) + (net N_202_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_2_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_3)) )) - (net un10_ciin_3 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_3)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_8)) + (net N_228_1 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_a2_1)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_a2_4)) )) - (net un10_ciin_4 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_4)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_8)) + (net N_228_2 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_a2_2)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_a2_4)) )) - (net un10_ciin_5 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_5)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_9)) + (net N_228_3 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_a2_3)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_a2_5)) )) - (net un10_ciin_6 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_6)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_9)) + (net N_228_4 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_a2_4)) + (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_a2)) )) - (net un10_ciin_7 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_7)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_10)) + (net N_228_5 (joined + (portRef O (instanceRef pos_clk_un34_as_030_d1_i_a2_5)) + (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_a2)) )) - (net un10_ciin_8 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_8)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2_10)) + (net N_150_1 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0)) )) - (net un10_ciin_9 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_9)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2_11)) + (net N_150_2 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3_0_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3_0)) )) - (net un10_ciin_10 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_10)) - (portRef I0 (instanceRef un13_ciin_i_0_0_a2)) + (net N_126_1 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3_1)) + (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_a3)) )) - (net un10_ciin_11 (joined - (portRef O (instanceRef un13_ciin_i_0_0_a2_11)) - (portRef I1 (instanceRef un13_ciin_i_0_0_a2)) + (net N_126_2 (joined + (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_a3_2)) + (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_a3)) )) - (net N_201_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_1_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) + (net un8_ciin_1 (joined + (portRef O (instanceRef un8_ciin_0_a3_1_0)) + (portRef I0 (instanceRef un8_ciin_0_a3)) + )) + (net un8_ciin_2 (joined + (portRef O (instanceRef un8_ciin_0_a3_2)) + (portRef I1 (instanceRef un8_ciin_0_a3)) + )) + (net N_201_1_1 (joined + (portRef O (instanceRef un8_ciin_0_a3_1_1)) + (portRef I0 (instanceRef un8_ciin_0_a3_1_6)) + )) + (net N_201_1_2 (joined + (portRef O (instanceRef un8_ciin_0_a3_1_2)) + (portRef I1 (instanceRef un8_ciin_0_a3_1_6)) + )) + (net N_201_1_3 (joined + (portRef O (instanceRef un8_ciin_0_a3_1_3)) + (portRef I0 (instanceRef un8_ciin_0_a3_1_7)) + )) + (net N_201_1_4 (joined + (portRef O (instanceRef un8_ciin_0_a3_1_4)) + (portRef I1 (instanceRef un8_ciin_0_a3_1_7)) + )) + (net N_201_1_5 (joined + (portRef O (instanceRef un8_ciin_0_a3_1_5)) + (portRef I1 (instanceRef un8_ciin_0_a3_1)) + )) + (net N_201_1_6 (joined + (portRef O (instanceRef un8_ciin_0_a3_1_6)) + (portRef I0 (instanceRef un8_ciin_0_a3_1_8)) + )) + (net N_201_1_7 (joined + (portRef O (instanceRef un8_ciin_0_a3_1_7)) + (portRef I1 (instanceRef un8_ciin_0_a3_1_8)) + )) + (net N_201_1_8 (joined + (portRef O (instanceRef un8_ciin_0_a3_1_8)) + (portRef I0 (instanceRef un8_ciin_0_a3_1)) + )) + (net N_201_1_0 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_a2_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_a2)) )) (net N_201_2 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_2_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) - )) - (net N_131_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_1_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) - )) - (net N_134_0_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_2)) - )) - (net N_113_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1)) - )) - (net N_113_i_2 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_2_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1)) - )) - (net N_144_1 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_1)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0)) - )) - (net N_144_2 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0_2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_0)) - )) - (net N_143_1 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_1)) - (portRef I0 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2)) - )) - (net N_143_2 (joined - (portRef O (instanceRef pos_clk_un9_clk_000_pe_0_0_a2_2)) - (portRef I1 (instanceRef pos_clk_un9_clk_000_pe_0_0_a2)) - )) - (net N_163_1 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_a2_1)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_a2_3)) - )) - (net N_163_2 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_a2_2)) - (portRef I1 (instanceRef pos_clk_un34_as_030_d1_i_i_a2_3)) - )) - (net N_163_3 (joined - (portRef O (instanceRef pos_clk_un34_as_030_d1_i_i_a2_3)) - (portRef I0 (instanceRef pos_clk_un34_as_030_d1_i_i_a2)) - )) - (net un21_fpu_cs_1 (joined - (portRef O (instanceRef un21_fpu_cs_0_a3_0_a2_1)) - (portRef I0 (instanceRef un21_fpu_cs_0_a3_0_a2)) - )) - (net un21_berr_1_0 (joined - (portRef O (instanceRef un21_berr_0_a3_0_a2_1_0)) - (portRef I0 (instanceRef un21_berr_0_a3_0_a2)) + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_a2_2)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_0_a2)) )) (net (rename pos_clk_CYCLE_DMA_5_1_1 "pos_clk.CYCLE_DMA_5_1[1]") (joined (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_1)) (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1)) )) - (net N_199_1 (joined + (net N_176_1 (joined (portRef O (instanceRef G_90_1)) (portRef I0 (instanceRef G_90)) )) @@ -3299,77 +3325,85 @@ (portRef O (instanceRef AS_000_DMA_1_sqmuxa_1)) (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa)) )) - (net N_140_1 (joined - (portRef O (instanceRef pos_clk_as_000_dma6_i_0_0_a2_1)) - (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_0_a2)) + (net N_198_1 (joined + (portRef O (instanceRef pos_clk_as_000_dma6_i_a3_1)) + (portRef I0 (instanceRef pos_clk_as_000_dma6_i_a3)) )) - (net N_66_i_1 (joined + (net N_72_i_1 (joined + (portRef O (instanceRef pos_clk_as_000_dma6_i_0_1)) + (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0)) + )) + (net N_72_i_2 (joined + (portRef O (instanceRef pos_clk_as_000_dma6_i_0_2)) + (portRef I1 (instanceRef pos_clk_as_000_dma6_i_0)) + )) + (net N_206_i_1 (joined (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i)) )) - (net N_66_i_2 (joined + (net N_206_i_2 (joined (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_2)) (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i)) )) - (net N_205_i_1 (joined - (portRef O (instanceRef pos_clk_as_000_dma6_i_0_0_1)) - (portRef I0 (instanceRef pos_clk_as_000_dma6_i_0_0)) + (net N_186_1 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a3_0_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a3_0)) )) - (net N_205_i_2 (joined - (portRef O (instanceRef pos_clk_as_000_dma6_i_0_0_2)) - (portRef I1 (instanceRef pos_clk_as_000_dma6_i_0_0)) + (net N_186_2 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a3_0_2)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_a3_0)) )) - (net N_180_1 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_1)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0)) - )) - (net N_180_2 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0_2)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_iv_0_0_a2_0)) - )) - (net N_59_i_1 (joined - (portRef O (instanceRef pos_clk_un6_bg_030_0_a3_i_1)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a3_i)) - )) - (net N_127_i_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_0)) - )) - (net N_123_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_6)) + (net N_74_i_1 (joined + (portRef O (instanceRef pos_clk_un6_bg_030_i_1)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_i)) )) (net N_121_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_5)) - )) - (net N_119_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_4)) + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_5)) )) (net N_117_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_3)) + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_3)) )) (net N_115_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_2)) + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_2)) + )) + (net N_127_i_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0)) + )) + (net N_123_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_6)) + )) + (net N_119_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_4)) )) (net N_111_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_0)) + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0)) )) - (net N_165_1 (joined - (portRef O (instanceRef un11_amiga_bus_enable_high_0_0_a2_0_1)) - (portRef I0 (instanceRef un11_amiga_bus_enable_high_0_0_a2_0)) + (net un21_berr_1 (joined + (portRef O (instanceRef un21_berr_0_a3_1)) + (portRef I0 (instanceRef un21_berr_0_a3)) )) - (net N_162_1 (joined - (portRef O (instanceRef un5_e_0_0_a2_0_1)) - (portRef I0 (instanceRef un5_e_0_0_a2_0)) + (net un21_fpu_cs_1 (joined + (portRef O (instanceRef un21_fpu_cs_0_a3_1)) + (portRef I0 (instanceRef un21_fpu_cs_0_a3)) )) - (net N_148_1 (joined - (portRef O (instanceRef cpu_est_2_0_0_a2_0_1_1)) - (portRef I0 (instanceRef cpu_est_2_0_0_a2_0_1)) + (net N_172_1 (joined + (portRef O (instanceRef un11_amiga_bus_enable_high_0_a3_0_1)) + (portRef I0 (instanceRef un11_amiga_bus_enable_high_0_a3_0)) + )) + (net N_161_1 (joined + (portRef O (instanceRef un5_e_0_a3_0_1)) + (portRef I0 (instanceRef un5_e_0_a3_0)) + )) + (net N_153_1 (joined + (portRef O (instanceRef cpu_est_2_0_0_a3_0_1_1)) + (portRef I0 (instanceRef cpu_est_2_0_0_a3_0_1)) )) (net (rename pos_clk_ipl_1 "pos_clk.ipl_1") (joined (portRef O (instanceRef G_108_1)) @@ -3435,18 +3469,6 @@ (portRef O (instanceRef LDS_000_INT_0_n)) (portRef I1 (instanceRef LDS_000_INT_0_p)) )) - (net (rename AS_030_D1_0_un3 "AS_030_D1_0.un3") (joined - (portRef O (instanceRef AS_030_D1_0_r)) - (portRef I1 (instanceRef AS_030_D1_0_n)) - )) - (net (rename AS_030_D1_0_un1 "AS_030_D1_0.un1") (joined - (portRef O (instanceRef AS_030_D1_0_m)) - (portRef I0 (instanceRef AS_030_D1_0_p)) - )) - (net (rename AS_030_D1_0_un0 "AS_030_D1_0.un0") (joined - (portRef O (instanceRef AS_030_D1_0_n)) - (portRef I1 (instanceRef AS_030_D1_0_p)) - )) (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined (portRef O (instanceRef RW_000_INT_0_r)) (portRef I1 (instanceRef RW_000_INT_0_n)) @@ -3459,18 +3481,6 @@ (portRef O (instanceRef RW_000_INT_0_n)) (portRef I1 (instanceRef RW_000_INT_0_p)) )) - (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_r)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) - )) - (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) - )) - (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_n)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) - )) (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined (portRef O (instanceRef BGACK_030_INT_0_r)) (portRef I1 (instanceRef BGACK_030_INT_0_n)) @@ -3483,6 +3493,18 @@ (portRef O (instanceRef BGACK_030_INT_0_n)) (portRef I1 (instanceRef BGACK_030_INT_0_p)) )) + (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_r)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) + )) + (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) + )) + (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_n)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) + )) (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined (portRef O (instanceRef cpu_est_0_1__r)) (portRef I1 (instanceRef cpu_est_0_1__n)) @@ -3579,6 +3601,18 @@ (portRef O (instanceRef VMA_INT_0_n)) (portRef I1 (instanceRef VMA_INT_0_p)) )) + (net (rename AS_030_D1_0_un3 "AS_030_D1_0.un3") (joined + (portRef O (instanceRef AS_030_D1_0_r)) + (portRef I1 (instanceRef AS_030_D1_0_n)) + )) + (net (rename AS_030_D1_0_un1 "AS_030_D1_0.un1") (joined + (portRef O (instanceRef AS_030_D1_0_m)) + (portRef I0 (instanceRef AS_030_D1_0_p)) + )) + (net (rename AS_030_D1_0_un0 "AS_030_D1_0.un0") (joined + (portRef O (instanceRef AS_030_D1_0_n)) + (portRef I1 (instanceRef AS_030_D1_0_p)) + )) ) (property orig_inst_of (string "BUS68030")) ) diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index 8fee42f..9e0ff86 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/amiga/hardwarehacks/68030-tk/github/logic\BUS68030.prj -#-- Written on Sat Dec 30 00:43:20 2017 +#-- Written on Thu Jan 11 20:16:10 2018 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index cc82f41..1e1516a 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -187,9 +187,9 @@ NR#3H_8PED;R4 RNP3ONsEDVHC;R( RNP38lFkVDCHRDC(N; P#R3$VM_lRNb"sIF "R\B\:\ks#C#l\\NC0x\l\NH\oN\sEN8sINCOEN \#\ndUjj -0\H\o0LEk\F\Do\HO\jnUdnj-Ujjj-#Lk38PE\M"\"N; -POR3DMCNk#b_0.Cb_l0HC3RjjUcn(;6j -RNP3CODNbMk_C#0b04_HRlCj43j66n.jN; -P#R30Dl0H0#0HRlCjj3jjjjj;P +POR3DMCNk#b_0.Cb_l0HC3Rjj.d46;jj +RNP3CODNbMk_C#0b04_HRlCjj3jjjjj;P +NR03#lH0D#H00ljCR36j4nj.6;P NRHFsoM_H#F0_VAR"zU1nj"dj;P NRs3FHNohl"CRAnz1Ujjd"N; P#R3$lM_#_s##HC08;Rj @@ -201,8 +201,8 @@ PVR3D_FIDbFF#s_LFM CR j;}N; P$R#M#_HlCHG8MDNo;R4 RNP3M#$_#lV_FoskHb_8;Rj -RNP3M#$_lMkOsEN#gRnn -j;N3PR#_$MD HMC8sHR "{j((dd-Uc.Bcw-7c w(-g6Aq-nBd(w.cAj}Ug"N; +RNP3M#$_lMkOsEN#4R(4 +n;N3PR#_$MD HMC8sHRA"{( j4j-dw(U(w-7cjB(-UUj -44.gcjn46}4U"N; POR38#L_NRPC{P NRM#$_VsCCMsCOOC_D FORN{ P$R1#l0CRN{ @@ -364,145 +364,145 @@ MMRk47_p1j_jjh_QaN; M#R3N_PCM_C0VoDN#.4R6 n;okMRM74_1j_jjh_ q Ap_#j_JGlkNN; M#R3N_PCM_C0VoDN#.4R6 -n;okMRM_4jOMHH;M -NRN3#PMC_CV0_D#No46R.no; -MMRk.V4_bOk_#N; +n;okMRM_.4V_bkO +#;N3MR#CNP_0MC_NVDoR#4.;6n +RoMk4M._sLCsN; M#R3N_PCM_C0VoDN#.4R6 -n;okMRM_.4LsCs;M +n;okMRMOU_H;HM +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR.kM__8#j;dj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRnh_;M NRN3#PMC_CV0_D#No46R.no; -MMRk.#_8_jjd;M -NRN3#PMC_CV0_D#No46R.no; -M_RhnN; +M_RhUN; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_ -U;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh;_g -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_jN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;4d -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_cN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;4U -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_gN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;.j -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_4N; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;.. -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_dN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;.c -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_6N; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;.n -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_(N; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;.U -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_gN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_;dj -RNM3P#NCC_M0D_VN4o#Rn.6;M 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in 64-bit mode @@ -55,7 +55,7 @@ State machine has 8 reachable states with original encodings of: At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat Dec 30 00:43:29 2017 +# Thu Jan 11 20:16:21 2018 ###########################################################] Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 @@ -65,7 +65,7 @@ File C:\users\matze\amiga\hardwarehacks\68030-tk\github\logic\synwork\BUS68030_c At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat Dec 30 00:43:31 2017 +# Thu Jan 11 20:16:23 2018 ###########################################################] Map & Optimize Report @@ -93,8 +93,8 @@ BI_DIR 18 uses BUFTH 4 uses IBUF 39 uses OBUF 14 uses -AND2 221 uses -INV 203 uses +AND2 225 uses +INV 205 uses OR2 17 uses XOR2 4 uses @@ -106,6 +106,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat Dec 30 00:43:31 2017 +# Thu Jan 11 20:16:24 2018 ###########################################################] diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs index 3bae7cf..d0ea552 100644 Binary files a/Logic/BUS68030.srs and b/Logic/BUS68030.srs differ diff --git a/Logic/Programming.xcf b/Logic/Programming.xcf index d56682f..e1bc248 100644 --- a/Logic/Programming.xcf +++ b/Logic/Programming.xcf @@ -19,8 +19,8 @@ 0 C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\GitHub\Logic\68030_tk.jed - 02/24/17 22:00:28 - 0x1D0F + 12/30/17 00:43:46 + 0xFCEC Erase,Program,Verify