diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index ad31bea..0a4c926 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -312,7 +312,7 @@ begin AMIGA_BUS_ENABLE_INT <= '1'; - if( CLK_000_D2='0' and CLK_000_D3= '1' and AS_030_000_SYNC = '0')then + if( CLK_000_D1='0' and CLK_000_D2= '1' and AS_030_000_SYNC = '0')then if(nEXP_SPACE ='1')then AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga @@ -324,12 +324,8 @@ begin when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe if(CLK_000_D0='1')then --go to s2 SM_AMIGA <= AS_SET_P; --as for amiga set! - RW_000_INT <= RW; - end if; - when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here - if(CLK_000_D2='1')then AS_000_INT <= '0'; - + RW_000_INT <= RW; if (RW='1' and DS_030 = '0') then --read: set udl/lds if(A0='0') then UDS_000_INT <= '0'; @@ -343,12 +339,9 @@ begin end if; end if; end if; - + when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here if(CLK_000_D0='0')then --go to s3 SM_AMIGA<=AS_SET_N; - end if; - when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write - if(CLK_000_D0='1')then --go to s4 if (RW='0' and DS_030 = '0') then --write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late if(A0='0') then UDS_000_INT <= '0'; @@ -361,6 +354,9 @@ begin LDS_000_INT <= '1'; end if; end if; + end if; + when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write + if(CLK_000_D0='1')then --go to s4 SM_AMIGA <= SAMPLE_DTACK_P; end if; when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA @@ -371,22 +367,28 @@ begin SM_AMIGA<=DATA_FETCH_N; end if; when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock - if(CLK_000_D0='1')then --go to s6 + if(CLK_000_D0 = '1')then --go to s6 SM_AMIGA<=DATA_FETCH_P; - DSACK1_INT <='0'; - AS_030_000_SYNC <= '1'; --cycle end end if; when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus! --if( CLK_000_D2 ='1' AND CLK_000_D3 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge - + DSACK1_INT <='0'; + AS_030_000_SYNC <= '1'; --cycle end --els if( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge SM_AMIGA<=END_CYCLE_N; + if(AS_030 ='1') then + AMIGA_BUS_ENABLE_INT <= '1'; + end if; end if; when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock - if(CLK_000_D0='1')then --go to s0 - RW_000_INT <= '1'; + if(AS_030 ='1') then + AMIGA_BUS_ENABLE_INT <= '1'; + end if; + + if(CLK_000_D0='1')then --go to s0 SM_AMIGA<=IDLE_P; + RW_000_INT <= '1'; end if; end case; diff --git a/Logic/68030_TK.STY b/Logic/68030_TK.STY index 87516c2..f0ce556 100644 --- a/Logic/68030_TK.STY +++ b/Logic/68030_TK.STY @@ -1,6 +1,6 @@ -[synthesis-type] -tool=Synplify [STRATEGY-LIST] Normal=True, 1385910337 [TOUCHED-REPORT] Design.tt4File=1401573640 +[synthesis-type] +tool=Synplify diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index aac282c..96487b0 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -186085,3 +186085,3480 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 06/01/14 01:03:18 ########### + +########## Tcl recorder starts at 06/07/14 21:37:39 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 21:37:39 ########### + + +########## Tcl recorder starts at 06/07/14 21:37:39 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 21:37:39 ########### + + +########## Tcl recorder starts at 06/07/14 21:44:21 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 21:44:21 ########### + + +########## Tcl recorder starts at 06/07/14 21:44:21 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 21:44:21 ########### + + +########## Tcl recorder starts at 06/07/14 21:45:19 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 21:45:19 ########### + + +########## Tcl recorder starts at 06/07/14 21:45:19 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 21:45:19 ########### + + +########## Tcl recorder starts at 06/07/14 21:47:19 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 21:47:19 ########### + + +########## Tcl recorder starts at 06/07/14 21:47:19 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 21:47:19 ########### + + +########## Tcl recorder starts at 06/07/14 21:49:30 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 21:49:30 ########### + + +########## Tcl recorder starts at 06/07/14 21:49:31 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 21:49:31 ########### + + +########## Tcl recorder starts at 06/07/14 22:01:17 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:01:17 ########### + + +########## Tcl recorder starts at 06/07/14 22:01:17 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:01:17 ########### + + +########## Tcl recorder starts at 06/07/14 22:02:45 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:02:45 ########### + + +########## Tcl recorder starts at 06/07/14 22:02:45 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:02:45 ########### + + +########## Tcl recorder starts at 06/07/14 22:21:50 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:21:50 ########### + + +########## Tcl recorder starts at 06/07/14 22:21:50 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:21:50 ########### + + +########## Tcl recorder starts at 06/07/14 22:23:38 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:23:38 ########### + + +########## Tcl recorder starts at 06/07/14 22:23:38 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:23:38 ########### + + +########## Tcl recorder starts at 06/07/14 22:25:58 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:25:58 ########### + + +########## Tcl recorder starts at 06/07/14 22:25:58 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:25:58 ########### + + +########## Tcl recorder starts at 06/07/14 22:30:53 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:30:53 ########### + + +########## Tcl recorder starts at 06/07/14 22:30:53 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:30:53 ########### + + +########## Tcl recorder starts at 06/07/14 22:33:35 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:33:35 ########### + + +########## Tcl recorder starts at 06/07/14 22:33:35 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:33:35 ########### + + +########## Tcl recorder starts at 06/07/14 22:36:29 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:36:29 ########### + + +########## Tcl recorder starts at 06/07/14 22:36:29 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:36:29 ########### + + +########## Tcl recorder starts at 06/07/14 22:49:11 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:49:11 ########### + + +########## Tcl recorder starts at 06/07/14 22:49:12 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:49:12 ########### + + +########## Tcl recorder starts at 06/07/14 22:55:44 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:55:44 ########### + + +########## Tcl recorder starts at 06/07/14 22:55:44 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:55:44 ########### + + +########## Tcl recorder starts at 06/07/14 22:57:25 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:57:25 ########### + + +########## Tcl recorder starts at 06/07/14 22:57:25 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:57:25 ########### + + +########## Tcl recorder starts at 06/07/14 22:58:56 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:58:56 ########### + + +########## Tcl recorder starts at 06/07/14 22:58:56 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 22:58:56 ########### + + +########## Tcl recorder starts at 06/07/14 23:01:19 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 23:01:19 ########### + + +########## Tcl recorder starts at 06/07/14 23:01:19 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 23:01:19 ########### + + +########## Tcl recorder starts at 06/07/14 23:03:12 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 23:03:13 ########### + + +########## Tcl recorder starts at 06/07/14 23:03:13 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 06/07/14 23:03:13 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index bdff8d8..26691b5 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,81 +1,111 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sun Jun 01 01:03:24 2014 +#$ DATE Sat Jun 07 23:03:19 2014 #$ MODULE 68030_tk -#$ PINS 59 A_26_ A_25_ SIZE_1_ A_24_ A_23_ A_31_ A_22_ A_21_ IPL_030_2_ A_20_ A_19_ \ -# IPL_2_ A_18_ A_17_ FC_1_ A_16_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ RW_000 IPL_1_ DS_030 \ -# IPL_0_ UDS_000 FC_0_ LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 \ -# CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET \ -# RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \ -# A_28_ A_27_ -#$ NODES 410 BG_030_c BG_000DFFSHreg inst_BGACK_030_INTreg BGACK_000_c \ -# inst_FPU_CS_INTreg inst_avec_expreg CLK_030_c inst_VMA_INTreg inst_AS_030_000_SYNC \ -# CLK_000_c inst_BGACK_030_INT_D inst_AS_000_DMA CLK_OSZI_c inst_VPA_D \ -# inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 CLK_OUT_INTreg inst_CLK_000_D1 \ -# inst_CLK_000_D2 inst_DTACK_D0 IPL_030DFFSH_0_reg inst_CLK_OUT_PRE_50 \ -# inst_CLK_OUT_PRE_25 IPL_030DFFSH_1_reg SM_AMIGA_7_ vcc_n_n IPL_030DFFSH_2_reg \ -# gnd_n_n state_machine_un10_clk_000_d0_n ipl_c_0__n inst_AS_000_INT SM_AMIGA_6_ \ -# ipl_c_1__n SM_AMIGA_0_ SM_AMIGA_5_ ipl_c_2__n SM_AMIGA_2_ inst_RW_000_INT DSACK1_c \ -# inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT \ -# state_machine_un3_clk_out_pre_50_n inst_CLK_000_D3 inst_CLK_030_H \ -# state_machine_un12_clk_000_d0_n inst_DS_000_DMA SIZE_DMA_0_ SIZE_DMA_1_ RST_c \ -# inst_A0_DMA AMIGA_BUS_ENABLE_INT_2_sqmuxa RESETDFFRHreg SM_AMIGA_4_ SM_AMIGA_3_ \ -# RW_c SM_AMIGA_1_ un1_DSACK1_INT_0_sqmuxa_3 fc_c_0__n fc_c_1__n \ -# state_machine_un10_bg_030_n state_machine_lds_000_int_7_n \ -# state_machine_uds_000_int_7_n AMIGA_BUS_DATA_DIR_c \ -# state_machine_un6_bgack_000_0_n N_194_0 N_119_i N_120_i N_197_0 \ -# state_machine_ds_000_dma_3_0_n N_171_i state_machine_size_dma_4_0_1__n N_130_i \ -# N_131_i CLK_OUT_PRE_25_0 N_132_i N_133_i N_134_i sm_amiga_ns_0_5__n N_135_i N_139_i \ -# cpu_est_0_ N_140_i cpu_est_1_ AMIGA_BUS_DATA_DIR_c_0 cpu_est_2_ N_141_i \ -# cpu_est_3_reg N_52_i N_143_i N_142_i state_machine_rw_000_int_7_iv_i_n \ -# cpu_est_ns_1__n N_62_0 cpu_est_ns_2__n N_161_i N_193 N_155_i N_196 N_63_0 N_28 N_66_i \ -# N_30 N_76_i N_55 CLK_000_D1_i N_62 N_77_i N_63 N_79_0 N_66 N_199_0 N_67 sm_amiga_i_2__n \ -# N_69 N_201_0 N_70 N_203_0 N_71 cpu_est_ns_0_1__n N_75 N_167_i N_76 N_170_i N_77 N_136_i \ -# N_79 N_137_i N_90 N_202_0 N_200 N_200_0 N_202 N_169_i N_204 N_198_0 N_114 N_168_i N_115 \ -# un1_DSACK1_INT_0_sqmuxa_3_0 N_116 N_90_i N_117 AS_030_c_i N_118 N_75_i N_120 N_71_i \ -# N_121 N_69_i N_122 N_67_i N_124 N_150_i N_125 N_151_i N_128 N_129 N_145_i N_132 N_146_i \ -# N_136 N_147_i N_137 cpu_est_ns_0_2__n N_138 N_144_i N_140 N_55_0 N_142 N_138_i N_144 \ -# N_172_i N_145 N_149_i N_146 N_129_i N_147 N_148 N_128_i N_150 sm_amiga_ns_0_0__n N_151 \ -# N_70_i N_155 N_124_i N_166 state_machine_lds_000_int_7_0_n N_167 \ -# state_machine_uds_000_int_7_0_n N_168 N_122_i N_169 N_30_0 N_170 N_121_i N_172 N_28_0 \ -# N_220 N_117_i N_230 N_118_i N_133 N_196_0 N_143 N_116_i N_143_2 N_195_i N_203 BG_030_c_i \ -# N_201 N_115_i N_199 state_machine_un10_bg_030_0_n N_161 N_193_0 N_141 N_204_i N_139 \ -# state_machine_un10_clk_000_d0_i_n N_135 state_machine_un12_clk_000_d0_0_n N_134 \ -# N_69_i_1 N_131 N_76_i_1 N_130 N_76_i_2 N_171 N_76_i_3 state_machine_ds_000_dma_3_n \ -# N_76_i_4 N_197 N_76_i_5 N_119 N_220_1 N_194 N_220_2 state_machine_un6_bgack_000_n \ -# N_230_1 N_143_2_i N_230_2 a_i_18__n N_230_3 a_i_16__n N_230_4 a_i_19__n N_230_5 \ -# sm_amiga_i_4__n N_230_6 sm_amiga_i_5__n cpu_est_ns_0_1_1__n sm_amiga_i_3__n \ -# cpu_est_ns_0_2_1__n CLK_000_D0_i N_122_1 sm_amiga_i_0__n N_122_2 sm_amiga_i_1__n \ -# N_122_3 RW_i N_115_1 CLK_030_H_i N_115_2 CLK_030_i state_machine_un10_clk_000_d0_1_n \ -# DTACK_D0_i state_machine_un10_clk_000_d0_2_n BGACK_030_INT_i N_133_1 AS_000_i \ -# N_133_2 UDS_000_i N_143_1 LDS_000_i cpu_est_ns_0_1_2__n RW_000_i N_55_0_1 \ -# sm_amiga_i_6__n state_machine_lds_000_int_7_0_1_n cpu_est_i_3__n \ -# state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_196_0_1 CLK_000_D2_i N_155_1 \ -# cpu_est_i_1__n N_148_1 cpu_est_i_0__n N_142_1 VMA_INT_i N_140_1 VPA_D_i N_132_1 \ -# AS_000_DMA_i N_124_1 nEXP_SPACE_i state_machine_a0_dma_2_1_n cpu_est_i_2__n N_120_1 \ -# A0_i N_118_1 size_i_1__n N_117_1 DS_030_i N_116_1 AS_030_000_SYNC_i \ -# AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 a_i_30__n N_204_1 a_i_31__n bgack_030_int_0_un3_n \ -# a_i_28__n bgack_030_int_0_un1_n a_i_29__n bgack_030_int_0_un0_n a_i_26__n \ -# as_000_dma_0_un3_n a_i_27__n as_000_dma_0_un1_n a_i_24__n as_000_dma_0_un0_n \ -# a_i_25__n ds_000_dma_0_un3_n RST_i ds_000_dma_0_un1_n ds_000_dma_0_un0_n \ -# clk_030_h_0_un3_n N_114_i clk_030_h_0_un1_n FPU_CS_INT_i clk_030_h_0_un0_n \ -# CLK_OUT_PRE_50_D_i rw_000_int_0_un3_n AS_030_c rw_000_int_0_un1_n \ -# rw_000_int_0_un0_n AS_000_c state_machine_uds_000_int_7_0_m3_un3_n \ -# state_machine_uds_000_int_7_0_m3_un1_n RW_000_c \ -# state_machine_uds_000_int_7_0_m3_un0_n ipl_030_0_0__un3_n DS_030_c \ -# ipl_030_0_0__un1_n ipl_030_0_0__un0_n UDS_000_c ipl_030_0_1__un3_n \ -# ipl_030_0_1__un1_n LDS_000_c ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n \ -# ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n cpu_estse_0_un3_n \ -# cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_17__n \ -# cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n cpu_estse_2_un3_n cpu_estse_2_un1_n \ -# a_c_19__n cpu_estse_2_un0_n as_030_000_sync_0_un3_n a_c_20__n \ -# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n a_c_21__n uds_000_int_0_un3_n \ -# uds_000_int_0_un1_n a_c_22__n uds_000_int_0_un0_n lds_000_int_0_un3_n a_c_23__n \ -# lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_24__n fpu_cs_int_0_un3_n \ -# fpu_cs_int_0_un1_n a_c_25__n fpu_cs_int_0_un0_n avec_exp_0_un3_n a_c_26__n \ -# avec_exp_0_un1_n avec_exp_0_un0_n a_c_27__n bg_000_0_un3_n bg_000_0_un1_n a_c_28__n \ -# bg_000_0_un0_n as_000_int_0_un3_n a_c_29__n as_000_int_0_un1_n as_000_int_0_un0_n \ -# a_c_30__n dsack1_int_0_un3_n dsack1_int_0_un1_n a_c_31__n dsack1_int_0_un0_n \ -# vma_int_0_un3_n A0_c vma_int_0_un1_n vma_int_0_un0_n nEXP_SPACE_c +#$ PINS 59 A_22_ A_21_ SIZE_1_ A_20_ A_19_ A_31_ A_18_ A_17_ IPL_030_2_ A_16_ IPL_030_1_ \ +# IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 \ +# nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT \ +# CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE \ +# AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ \ +# A_25_ A_24_ A_23_ +#$ NODES 407 a_c_28__n a_c_29__n a_c_30__n inst_BGACK_030_INTreg a_c_31__n \ +# inst_FPU_CS_INTreg inst_avec_expreg A0_c inst_VMA_INTreg inst_AS_030_000_SYNC \ +# nEXP_SPACE_c inst_BGACK_030_INT_D inst_AS_000_DMA inst_VPA_D BG_030_c \ +# inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 BG_000DFFSHreg inst_CLK_000_D1 inst_DTACK_D0 \ +# inst_CLK_OUT_PRE_50 BGACK_000_c inst_CLK_OUT_PRE_25 SM_AMIGA_1_ CLK_030_c vcc_n_n \ +# gnd_n_n CLK_000_c inst_AS_000_INT SM_AMIGA_6_ CLK_OSZI_c SM_AMIGA_0_ SM_AMIGA_7_ \ +# inst_RW_000_INT CLK_OUT_INTreg inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT \ +# IPL_030DFFSH_0_reg state_machine_un3_clk_out_pre_50_n inst_CLK_000_D2 \ +# IPL_030DFFSH_1_reg inst_CLK_030_H inst_DS_000_DMA IPL_030DFFSH_2_reg SIZE_DMA_0_ \ +# SIZE_DMA_1_ ipl_c_0__n inst_A0_DMA SM_AMIGA_5_ ipl_c_1__n SM_AMIGA_4_ SM_AMIGA_3_ \ +# ipl_c_2__n SM_AMIGA_2_ DSACK1_c RST_c RESETDFFRHreg RW_c fc_c_0__n CLK_OUT_PRE_25_0 \ +# fc_c_1__n AMIGA_BUS_DATA_DIR_c cpu_est_0_ state_machine_un3_clk_000_d1_i_n \ +# cpu_est_1_ state_machine_un6_bgack_000_0_n cpu_est_2_ cpu_est_ns_0_1__n \ +# cpu_est_3_reg N_159_i cpu_estse N_158_i N_149_i N_150_i N_153_i AS_000_DMA_0_sqmuxa \ +# N_152_i state_machine_un8_bgack_030_int_n N_160_i N_92 N_154_i \ +# state_machine_un49_clk_000_d0_n state_machine_un10_clk_000_d0_2_i_n N_210 N_156_i \ +# N_220 N_157_i CLK_030_H_1_sqmuxa cpu_est_ns_0_2__n AS_000_DMA_1_sqmuxa \ +# state_machine_un10_clk_000_d0_i_n DS_000_DMA_1_sqmuxa \ +# state_machine_un12_clk_000_d0_0_n state_machine_un24_bgack_030_int_n \ +# FPU_CS_INT_1_sqmuxa_i state_machine_clk_030_h_2_n un1_as_030_000_sync8_1_0 \ +# state_machine_clk_030_h_2_f1_n AS_030_000_SYNC_0_sqmuxa_2_i \ +# state_machine_ds_000_dma_3_n un1_as_030_000_sync8_0 N_87 un1_SM_AMIGA_12_0 N_93 \ +# state_machine_un3_clk_030_i_n N_94 state_machine_un57_clk_000_d0_i_n N_88 \ +# state_machine_un51_clk_000_d0_i_n N_90 state_machine_un53_clk_000_d0_0_n N_164_1 \ +# state_machine_un3_bgack_030_int_d_i_n state_machine_un10_bgack_030_int_n \ +# un1_bgack_030_int_d_0 UDS_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i \ +# UDS_000_INT_0_sqmuxa AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i \ +# state_machine_un25_clk_000_d0_n N_86_0 N_164 N_101_i RW_li_m N_85_i N_181 N_84_0 \ +# RW_000_i_m N_97_i N_163 un1_SM_AMIGA_8 N_96_i N_100 N_95_i N_91 sm_amiga_ns_0_5__n \ +# state_machine_un31_bgack_030_int_n N_88_i state_machine_lds_000_int_7_n N_89_i \ +# state_machine_uds_000_int_7_n sm_amiga_ns_0_0__n RW_000_INT_0_sqmuxa_1 \ +# AMIGA_BUS_ENABLE_INT_2_sqmuxa_i un1_AS_030_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i \ +# N_59 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 un1_bgack_030_int_d BG_030_c_i \ +# un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un8_bg_030_i_n \ +# state_machine_un10_bg_030_n state_machine_un10_bg_030_0_n \ +# state_machine_un3_bgack_030_int_d_n state_machine_un5_bgack_030_int_d_i_n \ +# AMIGA_BUS_ENABLE_INT_3_sqmuxa N_59_0 N_86 state_machine_un10_bgack_030_int_0_n \ +# AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 N_181_i N_84 A0_c_i \ +# AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 state_machine_uds_000_int_7_0_n \ +# state_machine_un8_bg_030_n state_machine_lds_000_int_7_0_n \ +# AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_size_dma_4_0_0__n N_89 \ +# state_machine_size_dma_4_0_1__n N_95 N_91_i N_96 N_97 N_100_i N_99 un1_SM_AMIGA_8_0 \ +# state_machine_un28_clk_000_d1_n N_164_i N_101 N_163_i un1_SM_AMIGA_12 \ +# AMIGA_BUS_DATA_DIR_c_0 AS_030_000_SYNC_1_sqmuxa RW_000_i_m_i \ +# un1_as_030_000_sync8_1 RW_li_m_i AS_000_INT_1_sqmuxa \ +# state_machine_rw_000_int_7_iv_i_n DSACK1_INT_1_sqmuxa size_c_i_1__n \ +# state_machine_un10_clk_000_d0_n state_machine_un25_clk_000_d0_i_n \ +# state_machine_un12_clk_000_d0_n N_90_i state_machine_un51_clk_000_d0_n \ +# state_machine_un53_clk_000_d0_n N_94_i state_machine_un57_clk_000_d0_n N_93_i \ +# AS_030_000_SYNC_0_sqmuxa_2 sm_amiga_ns_0_4__n AS_030_000_SYNC_0_sqmuxa N_87_0 \ +# state_machine_un3_clk_030_n state_machine_ds_000_dma_3_0_n FPU_CS_INT_1_sqmuxa \ +# CLK_030_H_i state_machine_un28_clk_030_n CLK_030_H_1_sqmuxa_i \ +# un1_as_030_000_sync8 state_machine_clk_030_h_2_f1_0_n N_150 un3_dtack_i \ +# state_machine_un5_clk_000_d0_n N_92_i state_machine_un3_clk_000_d1_n \ +# cpu_est_ns_2__n un3_dtack_i_1 N_157 state_machine_un25_clk_000_d0_i_1_n N_156 \ +# cpu_est_ns_0_1_2__n state_machine_un10_clk_000_d0_2_n N_210_1 N_154 N_210_2 N_160 \ +# N_220_1 N_152 N_220_2 N_153 N_220_3 N_158 N_220_4 N_159 N_220_5 cpu_est_ns_1__n N_220_6 \ +# state_machine_un6_bgack_000_n DS_000_DMA_1_sqmuxa_1 AS_030_000_SYNC_i \ +# UDS_000_INT_0_sqmuxa_1_1 CLK_000_D1_i UDS_000_INT_0_sqmuxa_1_2 cpu_est_i_3__n \ +# UDS_000_INT_0_sqmuxa_1_0 cpu_est_i_2__n UDS_000_INT_0_sqmuxa_2 cpu_est_i_1__n \ +# N_164_1_0 cpu_est_i_0__n RW_li_m_1 VPA_D_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 \ +# CLK_000_D0_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 state_machine_un28_clk_030_i_n \ +# N_101_1 VMA_INT_i un1_bgack_030_int_d_0_1 AS_030_i state_machine_un8_bg_030_1_n \ +# AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n sm_amiga_i_1__n \ +# state_machine_un57_clk_000_d0_1_n DTACK_D0_i state_machine_un49_clk_000_d0_1_n \ +# a_i_19__n AS_030_000_SYNC_0_sqmuxa_1 a_i_16__n AS_030_000_SYNC_0_sqmuxa_2_0 \ +# a_i_18__n state_machine_un28_clk_030_1_n state_machine_un5_clk_000_d0_i_0_n \ +# state_machine_un28_clk_030_2_n nEXP_SPACE_i state_machine_un28_clk_030_3_n \ +# sm_amiga_i_7__n state_machine_un28_clk_030_4_n sm_amiga_i_0__n \ +# state_machine_un28_clk_030_5_n N_99_i state_machine_un5_clk_000_d0_1_n \ +# sm_amiga_i_2__n state_machine_un5_clk_000_d0_2_n BGACK_030_INT_i \ +# state_machine_un10_clk_000_d0_1_n BGACK_030_INT_D_i \ +# state_machine_un10_clk_000_d0_2_0_n sm_amiga_i_6__n \ +# state_machine_un10_clk_000_d0_3_n UDS_000_i cpu_est_ns_0_1_1__n LDS_000_i \ +# cpu_est_ns_0_2_1__n AS_000_DMA_0_sqmuxa_i state_machine_un28_clk_000_d1_1_n \ +# state_machine_un8_bgack_030_int_i_n cpu_estse_2_un3_n \ +# state_machine_un31_bgack_030_int_i_n cpu_estse_2_un1_n sm_amiga_i_5__n \ +# cpu_estse_2_un0_n RW_i cpu_estse_1_un3_n RW_000_i cpu_estse_1_un1_n \ +# UDS_000_INT_0_sqmuxa_i cpu_estse_1_un0_n UDS_000_INT_0_sqmuxa_1_i \ +# cpu_estse_0_un3_n AS_000_i cpu_estse_0_un1_n DS_030_i cpu_estse_0_un0_n \ +# state_machine_un49_clk_000_d0_i_n ipl_030_0_2__un3_n CLK_030_i ipl_030_0_2__un1_n \ +# state_machine_un24_bgack_030_int_i_n ipl_030_0_2__un0_n AS_000_DMA_i \ +# ipl_030_0_1__un3_n sm_amiga_i_4__n ipl_030_0_1__un1_n a_i_30__n ipl_030_0_1__un0_n \ +# a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n a_i_29__n \ +# ipl_030_0_0__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n bgack_030_int_0_un1_n \ +# a_i_24__n bgack_030_int_0_un0_n a_i_25__n as_030_000_sync_0_un3_n RST_i \ +# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n FPU_CS_INT_i fpu_cs_int_0_un3_n \ +# CLK_OUT_PRE_50_D_i fpu_cs_int_0_un1_n AS_030_c fpu_cs_int_0_un0_n \ +# as_000_int_0_un3_n AS_000_c as_000_int_0_un1_n as_000_int_0_un0_n RW_000_c \ +# dsack1_int_0_un3_n dsack1_int_0_un1_n DS_030_c dsack1_int_0_un0_n vma_int_0_un3_n \ +# UDS_000_c vma_int_0_un1_n vma_int_0_un0_n LDS_000_c avec_exp_0_un3_n \ +# avec_exp_0_un1_n size_c_0__n avec_exp_0_un0_n bg_000_0_un3_n size_c_1__n \ +# bg_000_0_un1_n bg_000_0_un0_n a_c_16__n lds_000_int_0_un3_n lds_000_int_0_un1_n \ +# a_c_17__n lds_000_int_0_un0_n uds_000_int_0_un3_n a_c_18__n uds_000_int_0_un1_n \ +# uds_000_int_0_un0_n a_c_19__n rw_000_int_0_un3_n rw_000_int_0_un1_n a_c_20__n \ +# rw_000_int_0_un0_n as_000_dma_0_un3_n a_c_21__n as_000_dma_0_un1_n \ +# as_000_dma_0_un0_n a_c_22__n ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_23__n \ +# ds_000_dma_0_un0_n clk_030_h_0_un3_n a_c_24__n clk_030_h_0_un1_n clk_030_h_0_un0_n \ +# a_c_25__n a_c_26__n a_c_27__n .model bus68030 .inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \ @@ -83,220 +113,282 @@ A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \ A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \ A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF \ AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF \ -DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF \ -inst_BGACK_030_INTreg.BLIF BGACK_000_c.BLIF inst_FPU_CS_INTreg.BLIF \ -inst_avec_expreg.BLIF CLK_030_c.BLIF inst_VMA_INTreg.BLIF \ -inst_AS_030_000_SYNC.BLIF CLK_000_c.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_AS_000_DMA.BLIF CLK_OSZI_c.BLIF inst_VPA_D.BLIF \ -inst_CLK_OUT_PRE_50_D.BLIF inst_CLK_000_D0.BLIF CLK_OUT_INTreg.BLIF \ -inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF inst_DTACK_D0.BLIF \ -IPL_030DFFSH_0_reg.BLIF inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF \ -IPL_030DFFSH_1_reg.BLIF SM_AMIGA_7_.BLIF vcc_n_n.BLIF IPL_030DFFSH_2_reg.BLIF \ -gnd_n_n.BLIF state_machine_un10_clk_000_d0_n.BLIF ipl_c_0__n.BLIF \ -inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF ipl_c_1__n.BLIF SM_AMIGA_0_.BLIF \ -SM_AMIGA_5_.BLIF ipl_c_2__n.BLIF SM_AMIGA_2_.BLIF inst_RW_000_INT.BLIF \ -DSACK1_c.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF \ -state_machine_un3_clk_out_pre_50_n.BLIF inst_CLK_000_D3.BLIF \ -inst_CLK_030_H.BLIF state_machine_un12_clk_000_d0_n.BLIF inst_DS_000_DMA.BLIF \ -SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF RST_c.BLIF inst_A0_DMA.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF RESETDFFRHreg.BLIF SM_AMIGA_4_.BLIF \ -SM_AMIGA_3_.BLIF RW_c.BLIF SM_AMIGA_1_.BLIF un1_DSACK1_INT_0_sqmuxa_3.BLIF \ -fc_c_0__n.BLIF fc_c_1__n.BLIF state_machine_un10_bg_030_n.BLIF \ -state_machine_lds_000_int_7_n.BLIF state_machine_uds_000_int_7_n.BLIF \ -AMIGA_BUS_DATA_DIR_c.BLIF state_machine_un6_bgack_000_0_n.BLIF N_194_0.BLIF \ -N_119_i.BLIF N_120_i.BLIF N_197_0.BLIF state_machine_ds_000_dma_3_0_n.BLIF \ -N_171_i.BLIF state_machine_size_dma_4_0_1__n.BLIF N_130_i.BLIF N_131_i.BLIF \ -CLK_OUT_PRE_25_0.BLIF N_132_i.BLIF N_133_i.BLIF N_134_i.BLIF \ -sm_amiga_ns_0_5__n.BLIF N_135_i.BLIF N_139_i.BLIF cpu_est_0_.BLIF N_140_i.BLIF \ -cpu_est_1_.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF cpu_est_2_.BLIF N_141_i.BLIF \ -cpu_est_3_reg.BLIF N_52_i.BLIF N_143_i.BLIF N_142_i.BLIF \ -state_machine_rw_000_int_7_iv_i_n.BLIF cpu_est_ns_1__n.BLIF N_62_0.BLIF \ -cpu_est_ns_2__n.BLIF N_161_i.BLIF N_193.BLIF N_155_i.BLIF N_196.BLIF \ -N_63_0.BLIF N_28.BLIF N_66_i.BLIF N_30.BLIF N_76_i.BLIF N_55.BLIF \ -CLK_000_D1_i.BLIF N_62.BLIF N_77_i.BLIF N_63.BLIF N_79_0.BLIF N_66.BLIF \ -N_199_0.BLIF N_67.BLIF sm_amiga_i_2__n.BLIF N_69.BLIF N_201_0.BLIF N_70.BLIF \ -N_203_0.BLIF N_71.BLIF cpu_est_ns_0_1__n.BLIF N_75.BLIF N_167_i.BLIF N_76.BLIF \ -N_170_i.BLIF N_77.BLIF N_136_i.BLIF N_79.BLIF N_137_i.BLIF N_90.BLIF \ -N_202_0.BLIF N_200.BLIF N_200_0.BLIF N_202.BLIF N_169_i.BLIF N_204.BLIF \ -N_198_0.BLIF N_114.BLIF N_168_i.BLIF N_115.BLIF \ -un1_DSACK1_INT_0_sqmuxa_3_0.BLIF N_116.BLIF N_90_i.BLIF N_117.BLIF \ -AS_030_c_i.BLIF N_118.BLIF N_75_i.BLIF N_120.BLIF N_71_i.BLIF N_121.BLIF \ -N_69_i.BLIF N_122.BLIF N_67_i.BLIF N_124.BLIF N_150_i.BLIF N_125.BLIF \ -N_151_i.BLIF N_128.BLIF N_129.BLIF N_145_i.BLIF N_132.BLIF N_146_i.BLIF \ -N_136.BLIF N_147_i.BLIF N_137.BLIF cpu_est_ns_0_2__n.BLIF N_138.BLIF \ -N_144_i.BLIF N_140.BLIF N_55_0.BLIF N_142.BLIF N_138_i.BLIF N_144.BLIF \ -N_172_i.BLIF N_145.BLIF N_149_i.BLIF N_146.BLIF N_129_i.BLIF N_147.BLIF \ -N_148.BLIF N_128_i.BLIF N_150.BLIF sm_amiga_ns_0_0__n.BLIF N_151.BLIF \ -N_70_i.BLIF N_155.BLIF N_124_i.BLIF N_166.BLIF \ -state_machine_lds_000_int_7_0_n.BLIF N_167.BLIF \ -state_machine_uds_000_int_7_0_n.BLIF N_168.BLIF N_122_i.BLIF N_169.BLIF \ -N_30_0.BLIF N_170.BLIF N_121_i.BLIF N_172.BLIF N_28_0.BLIF N_220.BLIF \ -N_117_i.BLIF N_230.BLIF N_118_i.BLIF N_133.BLIF N_196_0.BLIF N_143.BLIF \ -N_116_i.BLIF N_143_2.BLIF N_195_i.BLIF N_203.BLIF BG_030_c_i.BLIF N_201.BLIF \ -N_115_i.BLIF N_199.BLIF state_machine_un10_bg_030_0_n.BLIF N_161.BLIF \ -N_193_0.BLIF N_141.BLIF N_204_i.BLIF N_139.BLIF \ -state_machine_un10_clk_000_d0_i_n.BLIF N_135.BLIF \ -state_machine_un12_clk_000_d0_0_n.BLIF N_134.BLIF N_69_i_1.BLIF N_131.BLIF \ -N_76_i_1.BLIF N_130.BLIF N_76_i_2.BLIF N_171.BLIF N_76_i_3.BLIF \ -state_machine_ds_000_dma_3_n.BLIF N_76_i_4.BLIF N_197.BLIF N_76_i_5.BLIF \ -N_119.BLIF N_220_1.BLIF N_194.BLIF N_220_2.BLIF \ -state_machine_un6_bgack_000_n.BLIF N_230_1.BLIF N_143_2_i.BLIF N_230_2.BLIF \ -a_i_18__n.BLIF N_230_3.BLIF a_i_16__n.BLIF N_230_4.BLIF a_i_19__n.BLIF \ -N_230_5.BLIF sm_amiga_i_4__n.BLIF N_230_6.BLIF sm_amiga_i_5__n.BLIF \ -cpu_est_ns_0_1_1__n.BLIF sm_amiga_i_3__n.BLIF cpu_est_ns_0_2_1__n.BLIF \ -CLK_000_D0_i.BLIF N_122_1.BLIF sm_amiga_i_0__n.BLIF N_122_2.BLIF \ -sm_amiga_i_1__n.BLIF N_122_3.BLIF RW_i.BLIF N_115_1.BLIF CLK_030_H_i.BLIF \ -N_115_2.BLIF CLK_030_i.BLIF state_machine_un10_clk_000_d0_1_n.BLIF \ -DTACK_D0_i.BLIF state_machine_un10_clk_000_d0_2_n.BLIF BGACK_030_INT_i.BLIF \ -N_133_1.BLIF AS_000_i.BLIF N_133_2.BLIF UDS_000_i.BLIF N_143_1.BLIF \ -LDS_000_i.BLIF cpu_est_ns_0_1_2__n.BLIF RW_000_i.BLIF N_55_0_1.BLIF \ -sm_amiga_i_6__n.BLIF state_machine_lds_000_int_7_0_1_n.BLIF \ -cpu_est_i_3__n.BLIF state_machine_uds_000_int_7_0_1_n.BLIF \ -sm_amiga_i_7__n.BLIF N_196_0_1.BLIF CLK_000_D2_i.BLIF N_155_1.BLIF \ -cpu_est_i_1__n.BLIF N_148_1.BLIF cpu_est_i_0__n.BLIF N_142_1.BLIF \ -VMA_INT_i.BLIF N_140_1.BLIF VPA_D_i.BLIF N_132_1.BLIF AS_000_DMA_i.BLIF \ -N_124_1.BLIF nEXP_SPACE_i.BLIF state_machine_a0_dma_2_1_n.BLIF \ -cpu_est_i_2__n.BLIF N_120_1.BLIF A0_i.BLIF N_118_1.BLIF size_i_1__n.BLIF \ -N_117_1.BLIF DS_030_i.BLIF N_116_1.BLIF AS_030_000_SYNC_i.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF a_i_30__n.BLIF N_204_1.BLIF \ -a_i_31__n.BLIF bgack_030_int_0_un3_n.BLIF a_i_28__n.BLIF \ -bgack_030_int_0_un1_n.BLIF a_i_29__n.BLIF bgack_030_int_0_un0_n.BLIF \ -a_i_26__n.BLIF as_000_dma_0_un3_n.BLIF a_i_27__n.BLIF as_000_dma_0_un1_n.BLIF \ -a_i_24__n.BLIF as_000_dma_0_un0_n.BLIF a_i_25__n.BLIF ds_000_dma_0_un3_n.BLIF \ -RST_i.BLIF ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF \ -clk_030_h_0_un3_n.BLIF N_114_i.BLIF clk_030_h_0_un1_n.BLIF FPU_CS_INT_i.BLIF \ -clk_030_h_0_un0_n.BLIF CLK_OUT_PRE_50_D_i.BLIF rw_000_int_0_un3_n.BLIF \ -AS_030_c.BLIF rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF AS_000_c.BLIF \ -state_machine_uds_000_int_7_0_m3_un3_n.BLIF \ -state_machine_uds_000_int_7_0_m3_un1_n.BLIF RW_000_c.BLIF \ -state_machine_uds_000_int_7_0_m3_un0_n.BLIF ipl_030_0_0__un3_n.BLIF \ -DS_030_c.BLIF ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF UDS_000_c.BLIF \ -ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF LDS_000_c.BLIF \ -ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF size_c_0__n.BLIF \ -ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF size_c_1__n.BLIF \ -cpu_estse_0_un3_n.BLIF cpu_estse_0_un1_n.BLIF a_c_16__n.BLIF \ -cpu_estse_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF a_c_17__n.BLIF \ -cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF a_c_18__n.BLIF \ -cpu_estse_2_un3_n.BLIF cpu_estse_2_un1_n.BLIF a_c_19__n.BLIF \ -cpu_estse_2_un0_n.BLIF as_030_000_sync_0_un3_n.BLIF a_c_20__n.BLIF \ -as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF a_c_21__n.BLIF \ -uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF a_c_22__n.BLIF \ -uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF a_c_23__n.BLIF \ -lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_c_24__n.BLIF \ -fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF a_c_25__n.BLIF \ -fpu_cs_int_0_un0_n.BLIF avec_exp_0_un3_n.BLIF a_c_26__n.BLIF \ -avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF a_c_27__n.BLIF bg_000_0_un3_n.BLIF \ -bg_000_0_un1_n.BLIF a_c_28__n.BLIF bg_000_0_un0_n.BLIF as_000_int_0_un3_n.BLIF \ -a_c_29__n.BLIF as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF a_c_30__n.BLIF \ -dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF a_c_31__n.BLIF \ -dsack1_int_0_un0_n.BLIF vma_int_0_un3_n.BLIF A0_c.BLIF vma_int_0_un1_n.BLIF \ -vma_int_0_un0_n.BLIF nEXP_SPACE_c.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ -RW_000.PIN.BLIF DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ -SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF \ -RW.PIN.BLIF +DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF a_c_28__n.BLIF a_c_29__n.BLIF \ +a_c_30__n.BLIF inst_BGACK_030_INTreg.BLIF a_c_31__n.BLIF \ +inst_FPU_CS_INTreg.BLIF inst_avec_expreg.BLIF A0_c.BLIF inst_VMA_INTreg.BLIF \ +inst_AS_030_000_SYNC.BLIF nEXP_SPACE_c.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_AS_000_DMA.BLIF inst_VPA_D.BLIF BG_030_c.BLIF inst_CLK_OUT_PRE_50_D.BLIF \ +inst_CLK_000_D0.BLIF BG_000DFFSHreg.BLIF inst_CLK_000_D1.BLIF \ +inst_DTACK_D0.BLIF inst_CLK_OUT_PRE_50.BLIF BGACK_000_c.BLIF \ +inst_CLK_OUT_PRE_25.BLIF SM_AMIGA_1_.BLIF CLK_030_c.BLIF vcc_n_n.BLIF \ +gnd_n_n.BLIF CLK_000_c.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF \ +CLK_OSZI_c.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.BLIF inst_RW_000_INT.BLIF \ +CLK_OUT_INTreg.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \ +inst_DSACK1_INT.BLIF IPL_030DFFSH_0_reg.BLIF \ +state_machine_un3_clk_out_pre_50_n.BLIF inst_CLK_000_D2.BLIF \ +IPL_030DFFSH_1_reg.BLIF inst_CLK_030_H.BLIF inst_DS_000_DMA.BLIF \ +IPL_030DFFSH_2_reg.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF ipl_c_0__n.BLIF \ +inst_A0_DMA.BLIF SM_AMIGA_5_.BLIF ipl_c_1__n.BLIF SM_AMIGA_4_.BLIF \ +SM_AMIGA_3_.BLIF ipl_c_2__n.BLIF SM_AMIGA_2_.BLIF DSACK1_c.BLIF RST_c.BLIF \ +RESETDFFRHreg.BLIF RW_c.BLIF fc_c_0__n.BLIF CLK_OUT_PRE_25_0.BLIF \ +fc_c_1__n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF cpu_est_0_.BLIF \ +state_machine_un3_clk_000_d1_i_n.BLIF cpu_est_1_.BLIF \ +state_machine_un6_bgack_000_0_n.BLIF cpu_est_2_.BLIF cpu_est_ns_0_1__n.BLIF \ +cpu_est_3_reg.BLIF N_159_i.BLIF cpu_estse.BLIF N_158_i.BLIF N_149_i.BLIF \ +N_150_i.BLIF N_153_i.BLIF AS_000_DMA_0_sqmuxa.BLIF N_152_i.BLIF \ +state_machine_un8_bgack_030_int_n.BLIF N_160_i.BLIF N_92.BLIF N_154_i.BLIF \ +state_machine_un49_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \ +N_210.BLIF N_156_i.BLIF N_220.BLIF N_157_i.BLIF CLK_030_H_1_sqmuxa.BLIF \ +cpu_est_ns_0_2__n.BLIF AS_000_DMA_1_sqmuxa.BLIF \ +state_machine_un10_clk_000_d0_i_n.BLIF DS_000_DMA_1_sqmuxa.BLIF \ +state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un24_bgack_030_int_n.BLIF \ +FPU_CS_INT_1_sqmuxa_i.BLIF state_machine_clk_030_h_2_n.BLIF \ +un1_as_030_000_sync8_1_0.BLIF state_machine_clk_030_h_2_f1_n.BLIF \ +AS_030_000_SYNC_0_sqmuxa_2_i.BLIF state_machine_ds_000_dma_3_n.BLIF \ +un1_as_030_000_sync8_0.BLIF N_87.BLIF un1_SM_AMIGA_12_0.BLIF N_93.BLIF \ +state_machine_un3_clk_030_i_n.BLIF N_94.BLIF \ +state_machine_un57_clk_000_d0_i_n.BLIF N_88.BLIF \ +state_machine_un51_clk_000_d0_i_n.BLIF N_90.BLIF \ +state_machine_un53_clk_000_d0_0_n.BLIF N_164_1.BLIF \ +state_machine_un3_bgack_030_int_d_i_n.BLIF \ +state_machine_un10_bgack_030_int_n.BLIF un1_bgack_030_int_d_0.BLIF \ +UDS_000_INT_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \ +UDS_000_INT_0_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF \ +state_machine_un25_clk_000_d0_n.BLIF N_86_0.BLIF N_164.BLIF N_101_i.BLIF \ +RW_li_m.BLIF N_85_i.BLIF N_181.BLIF N_84_0.BLIF RW_000_i_m.BLIF N_97_i.BLIF \ +N_163.BLIF un1_SM_AMIGA_8.BLIF N_96_i.BLIF N_100.BLIF N_95_i.BLIF N_91.BLIF \ +sm_amiga_ns_0_5__n.BLIF state_machine_un31_bgack_030_int_n.BLIF N_88_i.BLIF \ +state_machine_lds_000_int_7_n.BLIF N_89_i.BLIF \ +state_machine_uds_000_int_7_n.BLIF sm_amiga_ns_0_0__n.BLIF \ +RW_000_INT_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF \ +un1_AS_030_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF N_59.BLIF \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF un1_bgack_030_int_d.BLIF \ +BG_030_c_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \ +state_machine_un8_bg_030_i_n.BLIF state_machine_un10_bg_030_n.BLIF \ +state_machine_un10_bg_030_0_n.BLIF state_machine_un3_bgack_030_int_d_n.BLIF \ +state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF \ +N_59_0.BLIF N_86.BLIF state_machine_un10_bgack_030_int_0_n.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF N_181_i.BLIF N_84.BLIF A0_c_i.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF state_machine_uds_000_int_7_0_n.BLIF \ +state_machine_un8_bg_030_n.BLIF state_machine_lds_000_int_7_0_n.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF state_machine_size_dma_4_0_0__n.BLIF \ +N_89.BLIF state_machine_size_dma_4_0_1__n.BLIF N_95.BLIF N_91_i.BLIF N_96.BLIF \ +N_97.BLIF N_100_i.BLIF N_99.BLIF un1_SM_AMIGA_8_0.BLIF \ +state_machine_un28_clk_000_d1_n.BLIF N_164_i.BLIF N_101.BLIF N_163_i.BLIF \ +un1_SM_AMIGA_12.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF AS_030_000_SYNC_1_sqmuxa.BLIF \ +RW_000_i_m_i.BLIF un1_as_030_000_sync8_1.BLIF RW_li_m_i.BLIF \ +AS_000_INT_1_sqmuxa.BLIF state_machine_rw_000_int_7_iv_i_n.BLIF \ +DSACK1_INT_1_sqmuxa.BLIF size_c_i_1__n.BLIF \ +state_machine_un10_clk_000_d0_n.BLIF state_machine_un25_clk_000_d0_i_n.BLIF \ +state_machine_un12_clk_000_d0_n.BLIF N_90_i.BLIF \ +state_machine_un51_clk_000_d0_n.BLIF state_machine_un53_clk_000_d0_n.BLIF \ +N_94_i.BLIF state_machine_un57_clk_000_d0_n.BLIF N_93_i.BLIF \ +AS_030_000_SYNC_0_sqmuxa_2.BLIF sm_amiga_ns_0_4__n.BLIF \ +AS_030_000_SYNC_0_sqmuxa.BLIF N_87_0.BLIF state_machine_un3_clk_030_n.BLIF \ +state_machine_ds_000_dma_3_0_n.BLIF FPU_CS_INT_1_sqmuxa.BLIF CLK_030_H_i.BLIF \ +state_machine_un28_clk_030_n.BLIF CLK_030_H_1_sqmuxa_i.BLIF \ +un1_as_030_000_sync8.BLIF state_machine_clk_030_h_2_f1_0_n.BLIF N_150.BLIF \ +un3_dtack_i.BLIF state_machine_un5_clk_000_d0_n.BLIF N_92_i.BLIF \ +state_machine_un3_clk_000_d1_n.BLIF cpu_est_ns_2__n.BLIF un3_dtack_i_1.BLIF \ +N_157.BLIF state_machine_un25_clk_000_d0_i_1_n.BLIF N_156.BLIF \ +cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_n.BLIF N_210_1.BLIF \ +N_154.BLIF N_210_2.BLIF N_160.BLIF N_220_1.BLIF N_152.BLIF N_220_2.BLIF \ +N_153.BLIF N_220_3.BLIF N_158.BLIF N_220_4.BLIF N_159.BLIF N_220_5.BLIF \ +cpu_est_ns_1__n.BLIF N_220_6.BLIF state_machine_un6_bgack_000_n.BLIF \ +DS_000_DMA_1_sqmuxa_1.BLIF AS_030_000_SYNC_i.BLIF \ +UDS_000_INT_0_sqmuxa_1_1.BLIF CLK_000_D1_i.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ +cpu_est_i_3__n.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF cpu_est_i_2__n.BLIF \ +UDS_000_INT_0_sqmuxa_2.BLIF cpu_est_i_1__n.BLIF N_164_1_0.BLIF \ +cpu_est_i_0__n.BLIF RW_li_m_1.BLIF VPA_D_i.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF CLK_000_D0_i.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF state_machine_un28_clk_030_i_n.BLIF \ +N_101_1.BLIF VMA_INT_i.BLIF un1_bgack_030_int_d_0_1.BLIF AS_030_i.BLIF \ +state_machine_un8_bg_030_1_n.BLIF AS_030_000_SYNC_0_sqmuxa_i.BLIF \ +state_machine_un8_bg_030_2_n.BLIF sm_amiga_i_1__n.BLIF \ +state_machine_un57_clk_000_d0_1_n.BLIF DTACK_D0_i.BLIF \ +state_machine_un49_clk_000_d0_1_n.BLIF a_i_19__n.BLIF \ +AS_030_000_SYNC_0_sqmuxa_1.BLIF a_i_16__n.BLIF \ +AS_030_000_SYNC_0_sqmuxa_2_0.BLIF a_i_18__n.BLIF \ +state_machine_un28_clk_030_1_n.BLIF state_machine_un5_clk_000_d0_i_0_n.BLIF \ +state_machine_un28_clk_030_2_n.BLIF nEXP_SPACE_i.BLIF \ +state_machine_un28_clk_030_3_n.BLIF sm_amiga_i_7__n.BLIF \ +state_machine_un28_clk_030_4_n.BLIF sm_amiga_i_0__n.BLIF \ +state_machine_un28_clk_030_5_n.BLIF N_99_i.BLIF \ +state_machine_un5_clk_000_d0_1_n.BLIF sm_amiga_i_2__n.BLIF \ +state_machine_un5_clk_000_d0_2_n.BLIF BGACK_030_INT_i.BLIF \ +state_machine_un10_clk_000_d0_1_n.BLIF BGACK_030_INT_D_i.BLIF \ +state_machine_un10_clk_000_d0_2_0_n.BLIF sm_amiga_i_6__n.BLIF \ +state_machine_un10_clk_000_d0_3_n.BLIF UDS_000_i.BLIF cpu_est_ns_0_1_1__n.BLIF \ +LDS_000_i.BLIF cpu_est_ns_0_2_1__n.BLIF AS_000_DMA_0_sqmuxa_i.BLIF \ +state_machine_un28_clk_000_d1_1_n.BLIF \ +state_machine_un8_bgack_030_int_i_n.BLIF cpu_estse_2_un3_n.BLIF \ +state_machine_un31_bgack_030_int_i_n.BLIF cpu_estse_2_un1_n.BLIF \ +sm_amiga_i_5__n.BLIF cpu_estse_2_un0_n.BLIF RW_i.BLIF cpu_estse_1_un3_n.BLIF \ +RW_000_i.BLIF cpu_estse_1_un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \ +cpu_estse_1_un0_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF cpu_estse_0_un3_n.BLIF \ +AS_000_i.BLIF cpu_estse_0_un1_n.BLIF DS_030_i.BLIF cpu_estse_0_un0_n.BLIF \ +state_machine_un49_clk_000_d0_i_n.BLIF ipl_030_0_2__un3_n.BLIF CLK_030_i.BLIF \ +ipl_030_0_2__un1_n.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \ +ipl_030_0_2__un0_n.BLIF AS_000_DMA_i.BLIF ipl_030_0_1__un3_n.BLIF \ +sm_amiga_i_4__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_30__n.BLIF \ +ipl_030_0_1__un0_n.BLIF a_i_31__n.BLIF ipl_030_0_0__un3_n.BLIF a_i_28__n.BLIF \ +ipl_030_0_0__un1_n.BLIF a_i_29__n.BLIF ipl_030_0_0__un0_n.BLIF a_i_26__n.BLIF \ +bgack_030_int_0_un3_n.BLIF a_i_27__n.BLIF bgack_030_int_0_un1_n.BLIF \ +a_i_24__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_25__n.BLIF \ +as_030_000_sync_0_un3_n.BLIF RST_i.BLIF as_030_000_sync_0_un1_n.BLIF \ +as_030_000_sync_0_un0_n.BLIF FPU_CS_INT_i.BLIF fpu_cs_int_0_un3_n.BLIF \ +CLK_OUT_PRE_50_D_i.BLIF fpu_cs_int_0_un1_n.BLIF AS_030_c.BLIF \ +fpu_cs_int_0_un0_n.BLIF as_000_int_0_un3_n.BLIF AS_000_c.BLIF \ +as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF RW_000_c.BLIF \ +dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF DS_030_c.BLIF \ +dsack1_int_0_un0_n.BLIF vma_int_0_un3_n.BLIF UDS_000_c.BLIF \ +vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF LDS_000_c.BLIF avec_exp_0_un3_n.BLIF \ +avec_exp_0_un1_n.BLIF size_c_0__n.BLIF avec_exp_0_un0_n.BLIF \ +bg_000_0_un3_n.BLIF size_c_1__n.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF \ +a_c_16__n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF \ +a_c_17__n.BLIF lds_000_int_0_un0_n.BLIF uds_000_int_0_un3_n.BLIF \ +a_c_18__n.BLIF uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF \ +a_c_19__n.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un1_n.BLIF a_c_20__n.BLIF \ +rw_000_int_0_un0_n.BLIF as_000_dma_0_un3_n.BLIF a_c_21__n.BLIF \ +as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF a_c_22__n.BLIF \ +ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un1_n.BLIF a_c_23__n.BLIF \ +ds_000_dma_0_un0_n.BLIF clk_030_h_0_un3_n.BLIF a_c_24__n.BLIF \ +clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF a_c_25__n.BLIF a_c_26__n.BLIF \ +a_c_27__n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF DS_030.PIN.BLIF \ +UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ +A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \ -cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C \ -cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR SM_AMIGA_0_.D \ -SM_AMIGA_0_.C SM_AMIGA_0_.AR SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP \ -IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ -IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ -IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D \ -SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ -SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \ -SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \ -SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ -inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_VMA_INTreg.D \ -inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D \ -inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_DMA_0_.D SIZE_DMA_0_.C \ -SIZE_DMA_0_.AP inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP \ -inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \ -inst_avec_expreg.D inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D \ -BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C \ -inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_000_INT.AP inst_RW_000_INT.D \ -inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.D \ -inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.D \ -inst_CLK_030_H.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP \ -inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_DTACK_D0.D inst_DTACK_D0.C \ -inst_DTACK_D0.AP inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP \ -CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D3.D \ -inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_000_D1.D inst_CLK_000_D1.C \ -inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \ -inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C \ -inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D inst_CLK_000_D0.C \ -inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \ +CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR \ +cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C \ +cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR IPL_030DFFSH_0_reg.D \ +IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ +IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ +IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ +SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \ +SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \ +SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \ +SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \ +SM_AMIGA_0_.C SM_AMIGA_0_.AR inst_VMA_INTreg.D inst_VMA_INTreg.C \ +inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ +inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C \ +inst_CLK_OUT_PRE_25.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP \ +SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP inst_LDS_000_INT.D \ +inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D \ +inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_avec_expreg.D \ +inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ +BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP \ +inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP inst_AS_000_INT.D \ +inst_AS_000_INT.C inst_AS_000_INT.AP inst_DSACK1_INT.D inst_DSACK1_INT.C \ +inst_DSACK1_INT.AP inst_RW_000_INT.D inst_RW_000_INT.C inst_RW_000_INT.AP \ +inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ +inst_CLK_030_H.D inst_CLK_030_H.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ +inst_UDS_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_DTACK_D0.D \ +inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.D inst_CLK_000_D2.C \ +inst_CLK_000_D2.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR \ +inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D \ +inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D \ +inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D \ +inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \ inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR \ RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR SIZE_1_ AS_030 AS_000 RW_000 \ -DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ BG_030_c BGACK_000_c \ -CLK_030_c CLK_000_c CLK_OSZI_c vcc_n_n gnd_n_n state_machine_un10_clk_000_d0_n \ -ipl_c_0__n ipl_c_1__n ipl_c_2__n DSACK1_c state_machine_un3_clk_out_pre_50_n \ -state_machine_un12_clk_000_d0_n RST_c AMIGA_BUS_ENABLE_INT_2_sqmuxa RW_c \ -un1_DSACK1_INT_0_sqmuxa_3 fc_c_0__n fc_c_1__n state_machine_un10_bg_030_n \ -state_machine_lds_000_int_7_n state_machine_uds_000_int_7_n \ -AMIGA_BUS_DATA_DIR_c state_machine_un6_bgack_000_0_n N_194_0 N_119_i N_120_i \ -N_197_0 state_machine_ds_000_dma_3_0_n N_171_i state_machine_size_dma_4_0_1__n \ -N_130_i N_131_i N_132_i N_133_i N_134_i sm_amiga_ns_0_5__n N_135_i N_139_i \ -N_140_i AMIGA_BUS_DATA_DIR_c_0 N_141_i N_52_i N_143_i N_142_i \ -state_machine_rw_000_int_7_iv_i_n cpu_est_ns_1__n N_62_0 cpu_est_ns_2__n \ -N_161_i N_193 N_155_i N_196 N_63_0 N_28 N_66_i N_30 N_76_i N_55 CLK_000_D1_i \ -N_62 N_77_i N_63 N_79_0 N_66 N_199_0 N_67 sm_amiga_i_2__n N_69 N_201_0 N_70 \ -N_203_0 N_71 cpu_est_ns_0_1__n N_75 N_167_i N_76 N_170_i N_77 N_136_i N_79 \ -N_137_i N_90 N_202_0 N_200 N_200_0 N_202 N_169_i N_204 N_198_0 N_114 N_168_i \ -N_115 un1_DSACK1_INT_0_sqmuxa_3_0 N_116 N_90_i N_117 AS_030_c_i N_118 N_75_i \ -N_120 N_71_i N_121 N_69_i N_122 N_67_i N_124 N_150_i N_125 N_151_i N_128 N_129 \ -N_145_i N_132 N_146_i N_136 N_147_i N_137 cpu_est_ns_0_2__n N_138 N_144_i \ -N_140 N_55_0 N_142 N_138_i N_144 N_172_i N_145 N_149_i N_146 N_129_i N_147 \ -N_148 N_128_i N_150 sm_amiga_ns_0_0__n N_151 N_70_i N_155 N_124_i N_166 \ -state_machine_lds_000_int_7_0_n N_167 state_machine_uds_000_int_7_0_n N_168 \ -N_122_i N_169 N_30_0 N_170 N_121_i N_172 N_28_0 N_220 N_117_i N_230 N_118_i \ -N_133 N_196_0 N_143 N_116_i N_143_2 N_195_i N_203 BG_030_c_i N_201 N_115_i \ -N_199 state_machine_un10_bg_030_0_n N_161 N_193_0 N_141 N_204_i N_139 \ -state_machine_un10_clk_000_d0_i_n N_135 state_machine_un12_clk_000_d0_0_n \ -N_134 N_69_i_1 N_131 N_76_i_1 N_130 N_76_i_2 N_171 N_76_i_3 \ -state_machine_ds_000_dma_3_n N_76_i_4 N_197 N_76_i_5 N_119 N_220_1 N_194 \ -N_220_2 state_machine_un6_bgack_000_n N_230_1 N_143_2_i N_230_2 a_i_18__n \ -N_230_3 a_i_16__n N_230_4 a_i_19__n N_230_5 sm_amiga_i_4__n N_230_6 \ -sm_amiga_i_5__n cpu_est_ns_0_1_1__n sm_amiga_i_3__n cpu_est_ns_0_2_1__n \ -CLK_000_D0_i N_122_1 sm_amiga_i_0__n N_122_2 sm_amiga_i_1__n N_122_3 RW_i \ -N_115_1 CLK_030_H_i N_115_2 CLK_030_i state_machine_un10_clk_000_d0_1_n \ -DTACK_D0_i state_machine_un10_clk_000_d0_2_n BGACK_030_INT_i N_133_1 AS_000_i \ -N_133_2 UDS_000_i N_143_1 LDS_000_i cpu_est_ns_0_1_2__n RW_000_i N_55_0_1 \ -sm_amiga_i_6__n state_machine_lds_000_int_7_0_1_n cpu_est_i_3__n \ -state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_196_0_1 CLK_000_D2_i \ -N_155_1 cpu_est_i_1__n N_148_1 cpu_est_i_0__n N_142_1 VMA_INT_i N_140_1 \ -VPA_D_i N_132_1 AS_000_DMA_i N_124_1 nEXP_SPACE_i state_machine_a0_dma_2_1_n \ -cpu_est_i_2__n N_120_1 A0_i N_118_1 size_i_1__n N_117_1 DS_030_i N_116_1 \ -AS_030_000_SYNC_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 a_i_30__n N_204_1 a_i_31__n \ -bgack_030_int_0_un3_n a_i_28__n bgack_030_int_0_un1_n a_i_29__n \ -bgack_030_int_0_un0_n a_i_26__n as_000_dma_0_un3_n a_i_27__n \ -as_000_dma_0_un1_n a_i_24__n as_000_dma_0_un0_n a_i_25__n ds_000_dma_0_un3_n \ -RST_i ds_000_dma_0_un1_n ds_000_dma_0_un0_n clk_030_h_0_un3_n N_114_i \ -clk_030_h_0_un1_n FPU_CS_INT_i clk_030_h_0_un0_n CLK_OUT_PRE_50_D_i \ -rw_000_int_0_un3_n AS_030_c rw_000_int_0_un1_n rw_000_int_0_un0_n AS_000_c \ -state_machine_uds_000_int_7_0_m3_un3_n state_machine_uds_000_int_7_0_m3_un1_n \ -RW_000_c state_machine_uds_000_int_7_0_m3_un0_n ipl_030_0_0__un3_n DS_030_c \ -ipl_030_0_0__un1_n ipl_030_0_0__un0_n UDS_000_c ipl_030_0_1__un3_n \ -ipl_030_0_1__un1_n LDS_000_c ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n \ -ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n cpu_estse_0_un3_n \ -cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_17__n \ -cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n cpu_estse_2_un3_n \ -cpu_estse_2_un1_n a_c_19__n cpu_estse_2_un0_n as_030_000_sync_0_un3_n \ -a_c_20__n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n a_c_21__n \ -uds_000_int_0_un3_n uds_000_int_0_un1_n a_c_22__n uds_000_int_0_un0_n \ -lds_000_int_0_un3_n a_c_23__n lds_000_int_0_un1_n lds_000_int_0_un0_n \ -a_c_24__n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n a_c_25__n fpu_cs_int_0_un0_n \ -avec_exp_0_un3_n a_c_26__n avec_exp_0_un1_n avec_exp_0_un0_n a_c_27__n \ -bg_000_0_un3_n bg_000_0_un1_n a_c_28__n bg_000_0_un0_n as_000_int_0_un3_n \ -a_c_29__n as_000_int_0_un1_n as_000_int_0_un0_n a_c_30__n dsack1_int_0_un3_n \ -dsack1_int_0_un1_n a_c_31__n dsack1_int_0_un0_n vma_int_0_un3_n A0_c \ -vma_int_0_un1_n vma_int_0_un0_n nEXP_SPACE_c AS_030.OE AS_000.OE RW_000.OE \ -DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE \ -RW.OE BERR.OE CIIN.OE CLK_OUT_PRE_25_0 -.names N_150_i.BLIF N_151_i.BLIF cpu_est_0_.D -11 1 +DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ a_c_28__n a_c_29__n \ +a_c_30__n a_c_31__n A0_c nEXP_SPACE_c BG_030_c BGACK_000_c CLK_030_c vcc_n_n \ +gnd_n_n CLK_000_c CLK_OSZI_c state_machine_un3_clk_out_pre_50_n ipl_c_0__n \ +ipl_c_1__n ipl_c_2__n DSACK1_c RST_c RW_c fc_c_0__n fc_c_1__n \ +AMIGA_BUS_DATA_DIR_c state_machine_un3_clk_000_d1_i_n \ +state_machine_un6_bgack_000_0_n cpu_est_ns_0_1__n N_159_i N_158_i N_149_i \ +N_150_i N_153_i AS_000_DMA_0_sqmuxa N_152_i state_machine_un8_bgack_030_int_n \ +N_160_i N_92 N_154_i state_machine_un49_clk_000_d0_n \ +state_machine_un10_clk_000_d0_2_i_n N_210 N_156_i N_220 N_157_i \ +CLK_030_H_1_sqmuxa cpu_est_ns_0_2__n AS_000_DMA_1_sqmuxa \ +state_machine_un10_clk_000_d0_i_n DS_000_DMA_1_sqmuxa \ +state_machine_un12_clk_000_d0_0_n state_machine_un24_bgack_030_int_n \ +FPU_CS_INT_1_sqmuxa_i state_machine_clk_030_h_2_n un1_as_030_000_sync8_1_0 \ +state_machine_clk_030_h_2_f1_n AS_030_000_SYNC_0_sqmuxa_2_i \ +state_machine_ds_000_dma_3_n un1_as_030_000_sync8_0 N_87 un1_SM_AMIGA_12_0 \ +N_93 state_machine_un3_clk_030_i_n N_94 state_machine_un57_clk_000_d0_i_n N_88 \ +state_machine_un51_clk_000_d0_i_n N_90 state_machine_un53_clk_000_d0_0_n \ +N_164_1 state_machine_un3_bgack_030_int_d_i_n \ +state_machine_un10_bgack_030_int_n un1_bgack_030_int_d_0 \ +UDS_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i UDS_000_INT_0_sqmuxa \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i state_machine_un25_clk_000_d0_n N_86_0 N_164 \ +N_101_i RW_li_m N_85_i N_181 N_84_0 RW_000_i_m N_97_i N_163 un1_SM_AMIGA_8 \ +N_96_i N_100 N_95_i N_91 sm_amiga_ns_0_5__n state_machine_un31_bgack_030_int_n \ +N_88_i state_machine_lds_000_int_7_n N_89_i state_machine_uds_000_int_7_n \ +sm_amiga_ns_0_0__n RW_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_2_sqmuxa_i \ +un1_AS_030_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i N_59 \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 un1_bgack_030_int_d BG_030_c_i \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un8_bg_030_i_n \ +state_machine_un10_bg_030_n state_machine_un10_bg_030_0_n \ +state_machine_un3_bgack_030_int_d_n state_machine_un5_bgack_030_int_d_i_n \ +AMIGA_BUS_ENABLE_INT_3_sqmuxa N_59_0 N_86 state_machine_un10_bgack_030_int_0_n \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 N_181_i N_84 A0_c_i \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 state_machine_uds_000_int_7_0_n \ +state_machine_un8_bg_030_n state_machine_lds_000_int_7_0_n \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_size_dma_4_0_0__n N_89 \ +state_machine_size_dma_4_0_1__n N_95 N_91_i N_96 N_97 N_100_i N_99 \ +un1_SM_AMIGA_8_0 state_machine_un28_clk_000_d1_n N_164_i N_101 N_163_i \ +un1_SM_AMIGA_12 AMIGA_BUS_DATA_DIR_c_0 AS_030_000_SYNC_1_sqmuxa RW_000_i_m_i \ +un1_as_030_000_sync8_1 RW_li_m_i AS_000_INT_1_sqmuxa \ +state_machine_rw_000_int_7_iv_i_n DSACK1_INT_1_sqmuxa size_c_i_1__n \ +state_machine_un10_clk_000_d0_n state_machine_un25_clk_000_d0_i_n \ +state_machine_un12_clk_000_d0_n N_90_i state_machine_un51_clk_000_d0_n \ +state_machine_un53_clk_000_d0_n N_94_i state_machine_un57_clk_000_d0_n N_93_i \ +AS_030_000_SYNC_0_sqmuxa_2 sm_amiga_ns_0_4__n AS_030_000_SYNC_0_sqmuxa N_87_0 \ +state_machine_un3_clk_030_n state_machine_ds_000_dma_3_0_n FPU_CS_INT_1_sqmuxa \ +CLK_030_H_i state_machine_un28_clk_030_n CLK_030_H_1_sqmuxa_i \ +un1_as_030_000_sync8 state_machine_clk_030_h_2_f1_0_n N_150 un3_dtack_i \ +state_machine_un5_clk_000_d0_n N_92_i state_machine_un3_clk_000_d1_n \ +cpu_est_ns_2__n un3_dtack_i_1 N_157 state_machine_un25_clk_000_d0_i_1_n N_156 \ +cpu_est_ns_0_1_2__n state_machine_un10_clk_000_d0_2_n N_210_1 N_154 N_210_2 \ +N_160 N_220_1 N_152 N_220_2 N_153 N_220_3 N_158 N_220_4 N_159 N_220_5 \ +cpu_est_ns_1__n N_220_6 state_machine_un6_bgack_000_n DS_000_DMA_1_sqmuxa_1 \ +AS_030_000_SYNC_i UDS_000_INT_0_sqmuxa_1_1 CLK_000_D1_i \ +UDS_000_INT_0_sqmuxa_1_2 cpu_est_i_3__n UDS_000_INT_0_sqmuxa_1_0 \ +cpu_est_i_2__n UDS_000_INT_0_sqmuxa_2 cpu_est_i_1__n N_164_1_0 cpu_est_i_0__n \ +RW_li_m_1 VPA_D_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 CLK_000_D0_i \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 state_machine_un28_clk_030_i_n N_101_1 \ +VMA_INT_i un1_bgack_030_int_d_0_1 AS_030_i state_machine_un8_bg_030_1_n \ +AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n sm_amiga_i_1__n \ +state_machine_un57_clk_000_d0_1_n DTACK_D0_i state_machine_un49_clk_000_d0_1_n \ +a_i_19__n AS_030_000_SYNC_0_sqmuxa_1 a_i_16__n AS_030_000_SYNC_0_sqmuxa_2_0 \ +a_i_18__n state_machine_un28_clk_030_1_n state_machine_un5_clk_000_d0_i_0_n \ +state_machine_un28_clk_030_2_n nEXP_SPACE_i state_machine_un28_clk_030_3_n \ +sm_amiga_i_7__n state_machine_un28_clk_030_4_n sm_amiga_i_0__n \ +state_machine_un28_clk_030_5_n N_99_i state_machine_un5_clk_000_d0_1_n \ +sm_amiga_i_2__n state_machine_un5_clk_000_d0_2_n BGACK_030_INT_i \ +state_machine_un10_clk_000_d0_1_n BGACK_030_INT_D_i \ +state_machine_un10_clk_000_d0_2_0_n sm_amiga_i_6__n \ +state_machine_un10_clk_000_d0_3_n UDS_000_i cpu_est_ns_0_1_1__n LDS_000_i \ +cpu_est_ns_0_2_1__n AS_000_DMA_0_sqmuxa_i state_machine_un28_clk_000_d1_1_n \ +state_machine_un8_bgack_030_int_i_n cpu_estse_2_un3_n \ +state_machine_un31_bgack_030_int_i_n cpu_estse_2_un1_n sm_amiga_i_5__n \ +cpu_estse_2_un0_n RW_i cpu_estse_1_un3_n RW_000_i cpu_estse_1_un1_n \ +UDS_000_INT_0_sqmuxa_i cpu_estse_1_un0_n UDS_000_INT_0_sqmuxa_1_i \ +cpu_estse_0_un3_n AS_000_i cpu_estse_0_un1_n DS_030_i cpu_estse_0_un0_n \ +state_machine_un49_clk_000_d0_i_n ipl_030_0_2__un3_n CLK_030_i \ +ipl_030_0_2__un1_n state_machine_un24_bgack_030_int_i_n ipl_030_0_2__un0_n \ +AS_000_DMA_i ipl_030_0_1__un3_n sm_amiga_i_4__n ipl_030_0_1__un1_n a_i_30__n \ +ipl_030_0_1__un0_n a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n \ +a_i_29__n ipl_030_0_0__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n \ +bgack_030_int_0_un1_n a_i_24__n bgack_030_int_0_un0_n a_i_25__n \ +as_030_000_sync_0_un3_n RST_i as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n \ +FPU_CS_INT_i fpu_cs_int_0_un3_n CLK_OUT_PRE_50_D_i fpu_cs_int_0_un1_n AS_030_c \ +fpu_cs_int_0_un0_n as_000_int_0_un3_n AS_000_c as_000_int_0_un1_n \ +as_000_int_0_un0_n RW_000_c dsack1_int_0_un3_n dsack1_int_0_un1_n DS_030_c \ +dsack1_int_0_un0_n vma_int_0_un3_n UDS_000_c vma_int_0_un1_n vma_int_0_un0_n \ +LDS_000_c avec_exp_0_un3_n avec_exp_0_un1_n size_c_0__n avec_exp_0_un0_n \ +bg_000_0_un3_n size_c_1__n bg_000_0_un1_n bg_000_0_un0_n a_c_16__n \ +lds_000_int_0_un3_n lds_000_int_0_un1_n a_c_17__n lds_000_int_0_un0_n \ +uds_000_int_0_un3_n a_c_18__n uds_000_int_0_un1_n uds_000_int_0_un0_n \ +a_c_19__n rw_000_int_0_un3_n rw_000_int_0_un1_n a_c_20__n rw_000_int_0_un0_n \ +as_000_dma_0_un3_n a_c_21__n as_000_dma_0_un1_n as_000_dma_0_un0_n a_c_22__n \ +ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_23__n ds_000_dma_0_un0_n \ +clk_030_h_0_un3_n a_c_24__n clk_030_h_0_un1_n clk_030_h_0_un0_n a_c_25__n \ +a_c_26__n a_c_27__n AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE \ +LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE \ +CIIN.OE CLK_OUT_PRE_25_0 cpu_estse .names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 @@ -306,10 +398,6 @@ RW.OE BERR.OE CIIN.OE CLK_OUT_PRE_25_0 .names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D 1- 1 -1 1 -.names CLK_000_D0_i.BLIF N_135_i.BLIF SM_AMIGA_0_.D -11 1 -.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D -0 1 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D 1- 1 -1 1 @@ -321,21 +409,20 @@ RW.OE BERR.OE CIIN.OE CLK_OUT_PRE_25_0 -1 1 .names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D 0 1 -.names N_129_i.BLIF N_198_0.BLIF SM_AMIGA_6_.D +.names N_88_i.BLIF N_90_i.BLIF SM_AMIGA_6_.D 11 1 -.names inst_CLK_000_D0.BLIF N_200.BLIF SM_AMIGA_5_.D +.names inst_CLK_000_D0.BLIF N_91_i.BLIF SM_AMIGA_5_.D 11 1 -.names CLK_000_D0_i.BLIF N_130_i.BLIF SM_AMIGA_4_.D -11 1 -.names N_131_i.BLIF N_132_i.BLIF SM_AMIGA_3_.D +.names CLK_000_D0_i.BLIF N_92_i.BLIF SM_AMIGA_4_.D 11 1 +.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D +0 1 .names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D 0 1 -.names inst_CLK_000_D0.BLIF N_201.BLIF SM_AMIGA_1_.D +.names inst_CLK_000_D0.BLIF N_97_i.BLIF SM_AMIGA_1_.D +11 1 +.names CLK_000_D0_i.BLIF N_86.BLIF SM_AMIGA_0_.D 11 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D -1- 1 --1 1 .names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 -1 1 @@ -343,7 +430,9 @@ RW.OE BERR.OE CIIN.OE CLK_OUT_PRE_25_0 inst_BGACK_030_INTreg.D 1- 1 -1 1 -.names N_125.BLIF SIZE_DMA_0_.D +.names state_machine_size_dma_4_0_0__n.BLIF SIZE_DMA_0_.D +0 1 +.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D 0 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D 1- 1 @@ -366,6 +455,9 @@ inst_BGACK_030_INTreg.D .names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D 1- 1 -1 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D +1- 1 +-1 1 .names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D 1- 1 -1 1 @@ -379,651 +471,675 @@ inst_AS_030_000_SYNC.D .names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D 1- 1 -1 1 -.names state_machine_a0_dma_2_1_n.BLIF N_166.BLIF inst_A0_DMA.D +.names UDS_000_c.BLIF state_machine_un8_bgack_030_int_n.BLIF inst_A0_DMA.D 11 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 .names vcc_n_n 1 .names gnd_n_n -.names state_machine_un10_clk_000_d0_1_n.BLIF \ -state_machine_un10_clk_000_d0_2_n.BLIF state_machine_un10_clk_000_d0_n -11 1 .names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF \ state_machine_un3_clk_out_pre_50_n 11 1 -.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n -0 1 -.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF sm_amiga_i_7__n.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa -11 1 -.names un1_DSACK1_INT_0_sqmuxa_3_0.BLIF un1_DSACK1_INT_0_sqmuxa_3 -0 1 -.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n -0 1 -.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n -0 1 -.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n -0 1 .names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c 0 1 -.names BGACK_000_c.BLIF N_77.BLIF state_machine_un6_bgack_000_0_n +.names state_machine_un3_clk_000_d1_n.BLIF state_machine_un3_clk_000_d1_i_n +0 1 +.names BGACK_000_c.BLIF state_machine_un3_clk_000_d1_i_n.BLIF \ +state_machine_un6_bgack_000_0_n 11 1 -.names CLK_030_c.BLIF N_143_2.BLIF N_194_0 -11 1 -.names N_119.BLIF N_119_i -0 1 -.names N_120.BLIF N_120_i -0 1 -.names N_119_i.BLIF N_120_i.BLIF N_197_0 -11 1 -.names AS_000_DMA_i.BLIF N_143_2.BLIF state_machine_ds_000_dma_3_0_n -11 1 -.names N_171.BLIF N_171_i -0 1 -.names N_143_2.BLIF N_171_i.BLIF state_machine_size_dma_4_0_1__n -11 1 -.names N_130.BLIF N_130_i -0 1 -.names N_131.BLIF N_131_i -0 1 -.names N_132.BLIF N_132_i -0 1 -.names N_133.BLIF N_133_i -0 1 -.names N_134.BLIF N_134_i -0 1 -.names N_133_i.BLIF N_134_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names N_135.BLIF N_135_i -0 1 -.names N_139.BLIF N_139_i -0 1 -.names N_140.BLIF N_140_i -0 1 -.names N_139_i.BLIF N_140_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names N_141.BLIF N_141_i -0 1 -.names N_141_i.BLIF N_143_2.BLIF N_52_i -11 1 -.names N_143.BLIF N_143_i -0 1 -.names N_142.BLIF N_142_i -0 1 -.names N_142_i.BLIF N_143_i.BLIF state_machine_rw_000_int_7_iv_i_n -11 1 -.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n -0 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_62_0 -11 1 -.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n -0 1 -.names N_161.BLIF N_161_i -0 1 -.names N_193_0.BLIF N_193 -0 1 -.names N_155.BLIF N_155_i -0 1 -.names N_196_0.BLIF N_196 -0 1 -.names N_155_i.BLIF N_161_i.BLIF N_63_0 -11 1 -.names N_28_0.BLIF N_28 -0 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_66_i -11 1 -.names N_30_0.BLIF N_30 -0 1 -.names N_76_i_4.BLIF N_76_i_5.BLIF N_76_i -11 1 -.names N_55_0.BLIF N_55 -0 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i -0 1 -.names N_62_0.BLIF N_62 -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_77_i -11 1 -.names N_63_0.BLIF N_63 -0 1 -.names CLK_030_i.BLIF N_143_2.BLIF N_79_0 -11 1 -.names N_66_i.BLIF N_66 -0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_199_0 -11 1 -.names N_67_i.BLIF N_67 -0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names N_69_i.BLIF N_69 -0 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_201_0 -11 1 -.names state_machine_uds_000_int_7_0_m3_un1_n.BLIF \ -state_machine_uds_000_int_7_0_m3_un0_n.BLIF N_70 -1- 1 --1 1 -.names AS_000_DMA_i.BLIF CLK_030_c.BLIF N_203_0 -11 1 -.names N_71_i.BLIF N_71 -0 1 .names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n 11 1 -.names N_75_i.BLIF N_75 +.names N_159.BLIF N_159_i 0 1 -.names N_167.BLIF N_167_i +.names N_158.BLIF N_158_i 0 1 -.names N_76_i.BLIF N_76 +.names N_158_i.BLIF N_159_i.BLIF N_149_i +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_150_i +11 1 +.names N_153.BLIF N_153_i 0 1 -.names N_170.BLIF N_170_i +.names CLK_030_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ +AS_000_DMA_0_sqmuxa +11 1 +.names N_152.BLIF N_152_i 0 1 -.names N_77_i.BLIF N_77 +.names N_164_1.BLIF state_machine_un10_bgack_030_int_n.BLIF \ +state_machine_un8_bgack_030_int_n +11 1 +.names N_160.BLIF N_160_i 0 1 -.names N_136.BLIF N_136_i +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_92 +11 1 +.names N_154.BLIF N_154_i 0 1 -.names N_79_0.BLIF N_79 +.names state_machine_un49_clk_000_d0_1_n.BLIF \ +state_machine_un53_clk_000_d0_n.BLIF state_machine_un49_clk_000_d0_n +11 1 +.names state_machine_un10_clk_000_d0_2_n.BLIF \ +state_machine_un10_clk_000_d0_2_i_n 0 1 -.names N_137.BLIF N_137_i +.names N_210_1.BLIF N_210_2.BLIF N_210 +11 1 +.names N_156.BLIF N_156_i 0 1 -.names N_90_i.BLIF N_90 +.names N_220_5.BLIF N_220_6.BLIF N_220 +11 1 +.names N_157.BLIF N_157_i 0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_6_.BLIF N_202_0 +.names AS_000_DMA_i.BLIF CLK_030_c.BLIF CLK_030_H_1_sqmuxa 11 1 -.names N_200_0.BLIF N_200 -0 1 -.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_200_0 +.names cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \ +cpu_est_ns_0_2__n 11 1 -.names N_202_0.BLIF N_202 -0 1 -.names N_169.BLIF N_169_i -0 1 -.names N_204_1.BLIF VPA_D_i.BLIF N_204 -11 1 -.names N_71.BLIF N_169_i.BLIF N_198_0 -11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_114 -11 1 -.names N_168.BLIF N_168_i -0 1 -.names N_115_1.BLIF N_115_2.BLIF N_115 -11 1 -.names N_75_i.BLIF N_168_i.BLIF un1_DSACK1_INT_0_sqmuxa_3_0 -11 1 -.names N_116_1.BLIF N_69_i.BLIF N_116 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_90_i -11 1 -.names N_117_1.BLIF RW_c.BLIF N_117 -11 1 -.names AS_030_c.BLIF AS_030_c_i -0 1 -.names N_118_1.BLIF RW_i.BLIF N_118 -11 1 -.names AS_030_c_i.BLIF N_114_i.BLIF N_75_i -11 1 -.names N_120_1.BLIF N_166.BLIF N_120 -11 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_71_i -11 1 -.names CLK_030_c.BLIF N_76_i.BLIF N_121 -11 1 -.names N_69_i_1.BLIF inst_CLK_000_D3.BLIF N_69_i -11 1 -.names N_122_3.BLIF nEXP_SPACE_c.BLIF N_122 -11 1 -.names inst_CLK_000_D2.BLIF SM_AMIGA_5_.BLIF N_67_i -11 1 -.names N_124_1.BLIF size_i_1__n.BLIF N_124 -11 1 -.names N_150.BLIF N_150_i -0 1 -.names N_166.BLIF N_171.BLIF N_125 -11 1 -.names N_151.BLIF N_151_i -0 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF N_128 -11 1 -.names N_202.BLIF sm_amiga_i_7__n.BLIF N_129 -11 1 -.names N_145.BLIF N_145_i -0 1 -.names N_132_1.BLIF inst_CLK_000_D1.BLIF N_132 -11 1 -.names N_146.BLIF N_146_i -0 1 -.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_136 -11 1 -.names N_147.BLIF N_147_i -0 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_137 -11 1 -.names cpu_est_ns_0_1_2__n.BLIF N_146_i.BLIF cpu_est_ns_0_2__n -11 1 -.names N_90.BLIF cpu_est_2_.BLIF N_138 -11 1 -.names N_144.BLIF N_144_i -0 1 -.names N_140_1.BLIF nEXP_SPACE_i.BLIF N_140 -11 1 -.names N_55_0_1.BLIF RW_000_i.BLIF N_55_0 -11 1 -.names N_142_1.BLIF SM_AMIGA_6_.BLIF N_142 -11 1 -.names N_138.BLIF N_138_i -0 1 -.names inst_CLK_030_H.BLIF CLK_030_i.BLIF N_144 -11 1 -.names N_172.BLIF N_172_i -0 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_145 -11 1 -.names N_138_i.BLIF N_172_i.BLIF N_149_i -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_146 -11 1 -.names N_129.BLIF N_129_i -0 1 -.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_147 -11 1 -.names N_148_1.BLIF nEXP_SPACE_i.BLIF N_148 -11 1 -.names N_128.BLIF N_128_i -0 1 -.names N_77.BLIF cpu_est_i_0__n.BLIF N_150 -11 1 -.names N_128_i.BLIF N_198_0.BLIF sm_amiga_ns_0_0__n -11 1 -.names N_77_i.BLIF cpu_est_0_.BLIF N_151 -11 1 -.names N_70.BLIF N_70_i -0 1 -.names N_155_1.BLIF VPA_D_i.BLIF N_155 -11 1 -.names N_124.BLIF N_124_i -0 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_166 -11 1 -.names state_machine_lds_000_int_7_0_1_n.BLIF N_70_i.BLIF \ -state_machine_lds_000_int_7_0_n -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_167 -11 1 -.names state_machine_uds_000_int_7_0_1_n.BLIF DS_030_i.BLIF \ -state_machine_uds_000_int_7_0_n -11 1 -.names N_69_i.BLIF N_71_i.BLIF N_168 -11 1 -.names N_122.BLIF N_122_i -0 1 -.names N_69.BLIF SM_AMIGA_7_.BLIF N_169 -11 1 -.names N_122_i.BLIF un1_DSACK1_INT_0_sqmuxa_3_0.BLIF N_30_0 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_170 -11 1 -.names N_121.BLIF N_121_i -0 1 -.names N_167.BLIF cpu_est_i_3__n.BLIF N_172 -11 1 -.names AS_030_c_i.BLIF N_121_i.BLIF N_28_0 -11 1 -.names N_220_1.BLIF N_220_2.BLIF N_220 -11 1 -.names N_117.BLIF N_117_i -0 1 -.names N_230_5.BLIF N_230_6.BLIF N_230 -11 1 -.names N_118.BLIF N_118_i -0 1 -.names N_133_1.BLIF N_133_2.BLIF N_133 -11 1 -.names N_196_0_1.BLIF N_117_i.BLIF N_196_0 -11 1 -.names N_143_1.BLIF RW_000_i.BLIF N_143 -11 1 -.names N_116.BLIF N_116_i -0 1 -.names N_62.BLIF N_166.BLIF N_143_2 -11 1 -.names inst_BGACK_030_INTreg.BLIF N_116_i.BLIF N_195_i -11 1 -.names N_203_0.BLIF N_203 -0 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names N_201_0.BLIF N_201 -0 1 -.names N_115.BLIF N_115_i -0 1 -.names N_199_0.BLIF N_199 -0 1 -.names BG_030_c_i.BLIF N_115_i.BLIF state_machine_un10_bg_030_0_n -11 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_161 -11 1 -.names AS_030_c_i.BLIF N_67.BLIF N_193_0 -11 1 -.names CLK_030_H_i.BLIF N_203.BLIF N_141 -11 1 -.names N_204.BLIF N_204_i -0 1 -.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_139 +.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_n.BLIF \ +AS_000_DMA_1_sqmuxa 11 1 .names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n 0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_135 +.names DS_000_DMA_1_sqmuxa_1.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \ +DS_000_DMA_1_sqmuxa 11 1 -.names N_204_i.BLIF state_machine_un10_clk_000_d0_i_n.BLIF \ -state_machine_un12_clk_000_d0_0_n +.names state_machine_un5_clk_000_d0_i_0_n.BLIF \ +state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n 11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_134 +.names inst_CLK_030_H.BLIF CLK_030_i.BLIF state_machine_un24_bgack_030_int_n 11 1 -.names CLK_000_D2_i.BLIF AS_030_000_SYNC_i.BLIF N_69_i_1 +.names FPU_CS_INT_1_sqmuxa.BLIF FPU_CS_INT_1_sqmuxa_i +0 1 +.names state_machine_clk_030_h_2_f1_n.BLIF \ +state_machine_un8_bgack_030_int_n.BLIF state_machine_clk_030_h_2_n 11 1 -.names N_66.BLIF sm_amiga_i_3__n.BLIF N_131 -11 1 -.names BGACK_000_c.BLIF a_i_19__n.BLIF N_76_i_1 -11 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_130 -11 1 -.names a_i_16__n.BLIF a_i_18__n.BLIF N_76_i_2 -11 1 -.names LDS_000_i.BLIF UDS_000_i.BLIF N_171 -11 1 -.names a_c_17__n.BLIF fc_c_0__n.BLIF N_76_i_3 +.names FPU_CS_INT_1_sqmuxa_i.BLIF state_machine_un3_clk_030_n.BLIF \ +un1_as_030_000_sync8_1_0 11 1 +.names state_machine_clk_030_h_2_f1_0_n.BLIF state_machine_clk_030_h_2_f1_n +0 1 +.names AS_030_000_SYNC_0_sqmuxa_2.BLIF AS_030_000_SYNC_0_sqmuxa_2_i +0 1 .names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n 0 1 -.names N_76_i_1.BLIF N_76_i_2.BLIF N_76_i_4 +.names AS_030_000_SYNC_0_sqmuxa_2_i.BLIF state_machine_un3_clk_030_n.BLIF \ +un1_as_030_000_sync8_0 11 1 -.names N_197_0.BLIF N_197 +.names N_87_0.BLIF N_87 0 1 -.names N_76_i_3.BLIF fc_c_1__n.BLIF N_76_i_5 +.names AS_030_i.BLIF N_85_i.BLIF un1_SM_AMIGA_12_0 11 1 -.names inst_CLK_000_D0.BLIF N_199.BLIF N_119 +.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_93 11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_220_1 +.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un3_clk_030_i_n 11 1 -.names N_194_0.BLIF N_194 +.names SM_AMIGA_3_.BLIF state_machine_un49_clk_000_d0_i_n.BLIF N_94 +11 1 +.names state_machine_un57_clk_000_d0_n.BLIF state_machine_un57_clk_000_d0_i_n 0 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_220_2 +.names N_84.BLIF SM_AMIGA_7_.BLIF N_88 11 1 -.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n +.names state_machine_un51_clk_000_d0_n.BLIF state_machine_un51_clk_000_d0_i_n 0 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_230_1 +.names N_87.BLIF sm_amiga_i_7__n.BLIF N_90 11 1 -.names N_143_2.BLIF N_143_2_i -0 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_230_2 +.names state_machine_un51_clk_000_d0_i_n.BLIF \ +state_machine_un57_clk_000_d0_i_n.BLIF state_machine_un53_clk_000_d0_0_n 11 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_230_3 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_164_1 11 1 -.names a_c_16__n.BLIF a_i_16__n +.names state_machine_un3_bgack_030_int_d_n.BLIF \ +state_machine_un3_bgack_030_int_d_i_n 0 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_230_4 +.names state_machine_un10_bgack_030_int_0_n.BLIF \ +state_machine_un10_bgack_030_int_n +0 1 +.names un1_bgack_030_int_d_0_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \ +un1_bgack_030_int_d_0 11 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names N_230_1.BLIF N_230_2.BLIF N_230_5 +.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ +UDS_000_INT_0_sqmuxa_1 11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i 0 1 -.names N_230_3.BLIF N_230_4.BLIF N_230_6 +.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \ +UDS_000_INT_0_sqmuxa 11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i 0 1 -.names N_136_i.BLIF N_137_i.BLIF cpu_est_ns_0_1_1__n +.names state_machine_un25_clk_000_d0_i_n.BLIF state_machine_un25_clk_000_d0_n +0 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_86_0 11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_167_i.BLIF N_170_i.BLIF cpu_est_ns_0_2_1__n +.names N_164_1_0.BLIF nEXP_SPACE_i.BLIF N_164 11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i +.names N_101.BLIF N_101_i 0 1 -.names inst_BGACK_030_INTreg.BLIF CLK_030_c.BLIF N_122_1 +.names RW_li_m_1.BLIF SM_AMIGA_6_.BLIF RW_li_m 11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names N_76.BLIF SM_AMIGA_7_.BLIF N_122_2 +.names N_101_i.BLIF sm_amiga_i_1__n.BLIF N_85_i 11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names N_122_1.BLIF N_122_2.BLIF N_122_3 +.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_181 11 1 -.names RW_c.BLIF RW_i +.names nEXP_SPACE_c.BLIF state_machine_un28_clk_000_d1_n.BLIF N_84_0 +11 1 +.names AS_000_DMA_0_sqmuxa.BLIF RW_000_i.BLIF RW_000_i_m +11 1 +.names N_97.BLIF N_97_i 0 1 -.names AS_030_c.BLIF CLK_000_c.BLIF N_115_1 +.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_163 +11 1 +.names un1_SM_AMIGA_8_0.BLIF un1_SM_AMIGA_8 +0 1 +.names N_96.BLIF N_96_i +0 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_100 +11 1 +.names N_95.BLIF N_95_i +0 1 +.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_91 +11 1 +.names N_95_i.BLIF N_96_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF state_machine_un31_bgack_030_int_n +11 1 +.names N_88.BLIF N_88_i +0 1 +.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n +0 1 +.names N_89.BLIF N_89_i +0 1 +.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n +0 1 +.names N_88_i.BLIF N_89_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names AS_000_DMA_0_sqmuxa_i.BLIF un1_SM_AMIGA_8.BLIF RW_000_INT_0_sqmuxa_1 +11 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i +0 1 +.names AS_030_i.BLIF N_181.BLIF un1_AS_030_2 +11 1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i +0 1 +.names N_59_0.BLIF N_59 +0 1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 +11 1 +.names un1_bgack_030_int_d_0.BLIF un1_bgack_030_int_d +0 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa +0 1 +.names state_machine_un8_bg_030_n.BLIF state_machine_un8_bg_030_i_n +0 1 +.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n +0 1 +.names BG_030_c_i.BLIF state_machine_un8_bg_030_i_n.BLIF \ +state_machine_un10_bg_030_0_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF \ +state_machine_un3_bgack_030_int_d_n +11 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +state_machine_un5_bgack_030_int_d_i_n +11 1 +.names N_86.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \ +AMIGA_BUS_ENABLE_INT_3_sqmuxa +11 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF N_59_0 +11 1 +.names N_86_0.BLIF N_86 +0 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF state_machine_un10_bgack_030_int_0_n +11 1 +.names inst_BGACK_030_INTreg.BLIF N_84.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 +11 1 +.names N_181.BLIF N_181_i +0 1 +.names N_84_0.BLIF N_84 +0 1 +.names A0_c.BLIF A0_c_i +0 1 +.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AS_030_i.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 +11 1 +.names A0_c_i.BLIF N_181_i.BLIF state_machine_uds_000_int_7_0_n +11 1 +.names state_machine_un8_bg_030_1_n.BLIF state_machine_un8_bg_030_2_n.BLIF \ +state_machine_un8_bg_030_n +11 1 +.names N_181_i.BLIF state_machine_un25_clk_000_d0_n.BLIF \ +state_machine_lds_000_int_7_0_n +11 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_un31_bgack_030_int_n.BLIF state_machine_size_dma_4_0_0__n +11 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF N_89 +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_un31_bgack_030_int_i_n.BLIF state_machine_size_dma_4_0_1__n +11 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_95 +11 1 +.names N_91.BLIF N_91_i +0 1 +.names SM_AMIGA_3_.BLIF state_machine_un49_clk_000_d0_n.BLIF N_96 +11 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_97 +11 1 +.names N_100.BLIF N_100_i +0 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_1_.BLIF N_99 +11 1 +.names inst_CLK_000_D0.BLIF N_100_i.BLIF un1_SM_AMIGA_8_0 +11 1 +.names state_machine_un28_clk_000_d1_1_n.BLIF CLK_000_D1_i.BLIF \ +state_machine_un28_clk_000_d1_n +11 1 +.names N_164.BLIF N_164_i +0 1 +.names N_101_1.BLIF state_machine_un28_clk_000_d1_n.BLIF N_101 +11 1 +.names N_163.BLIF N_163_i +0 1 +.names un1_SM_AMIGA_12_0.BLIF un1_SM_AMIGA_12 +0 1 +.names N_163_i.BLIF N_164_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names N_85_i.BLIF un1_as_030_000_sync8.BLIF AS_030_000_SYNC_1_sqmuxa +11 1 +.names RW_000_i_m.BLIF RW_000_i_m_i +0 1 +.names un1_as_030_000_sync8_1_0.BLIF un1_as_030_000_sync8_1 +0 1 +.names RW_li_m.BLIF RW_li_m_i +0 1 +.names AS_030_i.BLIF N_59.BLIF AS_000_INT_1_sqmuxa +11 1 +.names RW_000_i_m_i.BLIF RW_li_m_i.BLIF state_machine_rw_000_int_7_iv_i_n +11 1 +.names AS_030_i.BLIF sm_amiga_i_1__n.BLIF DSACK1_INT_1_sqmuxa +11 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names state_machine_un10_clk_000_d0_3_n.BLIF cpu_est_i_3__n.BLIF \ +state_machine_un10_clk_000_d0_n +11 1 +.names state_machine_un25_clk_000_d0_i_1_n.BLIF size_c_i_1__n.BLIF \ +state_machine_un25_clk_000_d0_i_n +11 1 +.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n +0 1 +.names N_90.BLIF N_90_i +0 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF state_machine_un51_clk_000_d0_n +11 1 +.names state_machine_un53_clk_000_d0_0_n.BLIF state_machine_un53_clk_000_d0_n +0 1 +.names N_94.BLIF N_94_i +0 1 +.names state_machine_un57_clk_000_d0_1_n.BLIF VMA_INT_i.BLIF \ +state_machine_un57_clk_000_d0_n +11 1 +.names N_93.BLIF N_93_i +0 1 +.names AS_030_000_SYNC_0_sqmuxa_i.BLIF AS_030_i.BLIF \ +AS_030_000_SYNC_0_sqmuxa_2 +11 1 +.names N_93_i.BLIF N_94_i.BLIF sm_amiga_ns_0_4__n +11 1 +.names AS_030_000_SYNC_0_sqmuxa_1.BLIF AS_030_000_SYNC_0_sqmuxa_2_0.BLIF \ +AS_030_000_SYNC_0_sqmuxa +11 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_6_.BLIF N_87_0 +11 1 +.names state_machine_un3_clk_030_i_n.BLIF state_machine_un3_clk_030_n +0 1 +.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_ds_000_dma_3_0_n +11 1 +.names AS_030_i.BLIF state_machine_un28_clk_030_i_n.BLIF FPU_CS_INT_1_sqmuxa 11 1 .names inst_CLK_030_H.BLIF CLK_030_H_i 0 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_115_2 +.names state_machine_un28_clk_030_4_n.BLIF state_machine_un28_clk_030_5_n.BLIF \ +state_machine_un28_clk_030_n 11 1 -.names CLK_030_c.BLIF CLK_030_i +.names CLK_030_H_1_sqmuxa.BLIF CLK_030_H_1_sqmuxa_i 0 1 -.names inst_AS_000_INT.BLIF inst_CLK_000_D0.BLIF \ -state_machine_un10_clk_000_d0_1_n +.names un1_as_030_000_sync8_0.BLIF un1_as_030_000_sync8 +0 1 +.names CLK_030_H_1_sqmuxa_i.BLIF CLK_030_H_i.BLIF \ +state_machine_clk_030_h_2_f1_0_n 11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i +.names N_150_i.BLIF N_150 0 1 -.names N_172.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n +.names un3_dtack_i_1.BLIF BGACK_030_INT_i.BLIF un3_dtack_i 11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_133_1 +.names state_machine_un5_clk_000_d0_1_n.BLIF \ +state_machine_un5_clk_000_d0_2_n.BLIF state_machine_un5_clk_000_d0_n 11 1 -.names AS_000_c.BLIF AS_000_i +.names N_92.BLIF N_92_i 0 1 -.names N_63.BLIF SM_AMIGA_3_.BLIF N_133_2 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF state_machine_un3_clk_000_d1_n 11 1 -.names UDS_000_c.BLIF UDS_000_i +.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n 0 1 -.names CLK_030_i.BLIF N_143_2.BLIF N_143_1 +.names nEXP_SPACE_i.BLIF AS_000_DMA_i.BLIF un3_dtack_i_1 11 1 -.names LDS_000_c.BLIF LDS_000_i -0 1 -.names N_147_i.BLIF N_145_i.BLIF cpu_est_ns_0_1_2__n +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_157 11 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_143_2.BLIF N_144_i.BLIF N_55_0_1 +.names size_c_0__n.BLIF A0_c_i.BLIF state_machine_un25_clk_000_d0_i_1_n 11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names N_124_i.BLIF DS_030_i.BLIF state_machine_lds_000_int_7_0_1_n +.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_156 11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names N_70_i.BLIF A0_i.BLIF state_machine_uds_000_int_7_0_1_n +.names N_157_i.BLIF N_156_i.BLIF cpu_est_ns_0_1_2__n 11 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names N_118_i.BLIF AS_030_c_i.BLIF N_196_0_1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n 11 1 -.names inst_CLK_000_D2.BLIF CLK_000_D2_i -0 1 -.names N_90_i.BLIF VMA_INT_i.BLIF N_155_1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_210_1 11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names AS_000_DMA_i.BLIF BGACK_030_INT_i.BLIF N_148_1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_154 11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names N_79.BLIF RW_i.BLIF N_142_1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_210_2 11 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names N_166.BLIF RW_c.BLIF N_140_1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_160 11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names N_63.BLIF CLK_000_D0_i.BLIF N_132_1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_220_1 11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names A0_i.BLIF size_c_0__n.BLIF N_124_1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_152 11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names UDS_000_c.BLIF LDS_000_i.BLIF state_machine_a0_dma_2_1_n +.names a_i_26__n.BLIF a_i_27__n.BLIF N_220_2 11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names CLK_030_i.BLIF N_62.BLIF N_120_1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_153 11 1 -.names A0_c.BLIF A0_i -0 1 -.names DS_030_i.BLIF N_66_i.BLIF N_118_1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_220_3 11 1 -.names size_c_1__n.BLIF size_i_1__n -0 1 -.names DS_030_i.BLIF N_67_i.BLIF N_117_1 +.names N_150.BLIF cpu_est_2_.BLIF N_158 11 1 -.names DS_030_c.BLIF DS_030_i +.names a_i_30__n.BLIF a_i_31__n.BLIF N_220_4 +11 1 +.names N_160.BLIF cpu_est_i_3__n.BLIF N_159 +11 1 +.names N_220_1.BLIF N_220_2.BLIF N_220_5 +11 1 +.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n 0 1 -.names N_71.BLIF inst_BGACK_030_INT_D.BLIF N_116_1 +.names N_220_3.BLIF N_220_4.BLIF N_220_6 +11 1 +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n +0 1 +.names RW_000_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ +DS_000_DMA_1_sqmuxa_1 11 1 .names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i 0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 +.names CLK_000_D0_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF UDS_000_INT_0_sqmuxa_1_2 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names inst_CLK_000_D0.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 +11 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_2 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names N_164_1.BLIF RW_c.BLIF N_164_1_0 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names AS_000_DMA_0_sqmuxa_i.BLIF RW_i.BLIF RW_li_m_1 +11 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names N_99_i.BLIF sm_amiga_i_0__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 +11 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names sm_amiga_i_7__n.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 +11 1 +.names state_machine_un28_clk_030_n.BLIF state_machine_un28_clk_030_i_n +0 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_101_1 +11 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names state_machine_un3_bgack_030_int_d_i_n.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF un1_bgack_030_int_d_0_1 +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names AS_030_c.BLIF CLK_000_c.BLIF state_machine_un8_bg_030_1_n +11 1 +.names AS_030_000_SYNC_0_sqmuxa.BLIF AS_030_000_SYNC_0_sqmuxa_i +0 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF state_machine_un8_bg_030_2_n +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names VPA_D_i.BLIF N_150_i.BLIF state_machine_un57_clk_000_d0_1_n +11 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF \ +state_machine_un49_clk_000_d0_1_n +11 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_7_.BLIF AS_030_000_SYNC_0_sqmuxa_1 +11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names nEXP_SPACE_c.BLIF state_machine_un28_clk_030_i_n.BLIF \ +AS_030_000_SYNC_0_sqmuxa_2_0 +11 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un28_clk_030_1_n +11 1 +.names state_machine_un5_clk_000_d0_n.BLIF state_machine_un5_clk_000_d0_i_0_n +0 1 +.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un28_clk_030_2_n +11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un28_clk_030_3_n +11 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names state_machine_un28_clk_030_1_n.BLIF state_machine_un28_clk_030_2_n.BLIF \ +state_machine_un28_clk_030_4_n +11 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names state_machine_un28_clk_030_3_n.BLIF fc_c_0__n.BLIF \ +state_machine_un28_clk_030_5_n +11 1 +.names N_99.BLIF N_99_i +0 1 +.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un5_clk_000_d0_1_n +11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF state_machine_un5_clk_000_d0_2_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names state_machine_un10_clk_000_d0_2_n.BLIF inst_AS_000_INT.BLIF \ +state_machine_un10_clk_000_d0_1_n +11 1 +.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i +0 1 +.names inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF \ +state_machine_un10_clk_000_d0_2_0_n +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names state_machine_un10_clk_000_d0_1_n.BLIF \ +state_machine_un10_clk_000_d0_2_0_n.BLIF state_machine_un10_clk_000_d0_3_n +11 1 +.names UDS_000_c.BLIF UDS_000_i +0 1 +.names N_152_i.BLIF N_153_i.BLIF cpu_est_ns_0_1_1__n +11 1 +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names N_154_i.BLIF N_160_i.BLIF cpu_est_ns_0_2_1__n +11 1 +.names AS_000_DMA_0_sqmuxa.BLIF AS_000_DMA_0_sqmuxa_i +0 1 +.names inst_CLK_000_D2.BLIF AS_030_000_SYNC_i.BLIF \ +state_machine_un28_clk_000_d1_1_n +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_un8_bgack_030_int_i_n +0 1 +.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_2_un3_n +0 1 +.names state_machine_un31_bgack_030_int_n.BLIF \ +state_machine_un31_bgack_030_int_i_n +0 1 +.names N_149_i.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse_2_un1_n +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names cpu_est_3_reg.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n +11 1 +.names RW_c.BLIF RW_i +0 1 +.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_1_un3_n +0 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names cpu_est_ns_2__n.BLIF state_machine_un3_clk_000_d1_n.BLIF \ +cpu_estse_1_un1_n +11 1 +.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i +0 1 +.names cpu_est_2_.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n +11 1 +.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i +0 1 +.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_0_un3_n +0 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names cpu_est_ns_1__n.BLIF state_machine_un3_clk_000_d1_n.BLIF \ +cpu_estse_0_un1_n +11 1 +.names DS_030_c.BLIF DS_030_i +0 1 +.names cpu_est_1_.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n +11 1 +.names state_machine_un49_clk_000_d0_n.BLIF state_machine_un49_clk_000_d0_i_n +0 1 +.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_2__un3_n +0 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names ipl_c_2__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_2__un1_n +11 1 +.names state_machine_un24_bgack_030_int_n.BLIF \ +state_machine_un24_bgack_030_int_i_n +0 1 +.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_1__un3_n +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names ipl_c_1__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_1__un1_n 11 1 .names a_c_30__n.BLIF a_i_30__n 0 1 -.names CLK_000_D0_i.BLIF N_170.BLIF N_204_1 +.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 .names a_c_31__n.BLIF a_i_31__n 0 1 -.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_0__un3_n 0 1 .names a_c_28__n.BLIF a_i_28__n 0 1 +.names ipl_c_0__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_0__un1_n +11 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 .names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ bgack_030_int_0_un1_n 11 1 -.names a_c_29__n.BLIF a_i_29__n +.names a_c_24__n.BLIF a_i_24__n 0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names N_194.BLIF as_000_dma_0_un3_n -0 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names N_143_2_i.BLIF N_194.BLIF as_000_dma_0_un1_n -11 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 .names a_c_25__n.BLIF a_i_25__n 0 1 -.names N_55.BLIF ds_000_dma_0_un3_n +.names AS_030_000_SYNC_1_sqmuxa.BLIF as_030_000_sync_0_un3_n 0 1 .names RST_c.BLIF RST_i 0 1 -.names state_machine_ds_000_dma_3_n.BLIF N_55.BLIF ds_000_dma_0_un1_n +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_1_sqmuxa.BLIF \ +as_030_000_sync_0_un1_n 11 1 -.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names RST_c.BLIF clk_030_h_0_un3_n -0 1 -.names N_114.BLIF N_114_i -0 1 -.names N_52_i.BLIF RST_c.BLIF clk_030_h_0_un1_n +.names un1_SM_AMIGA_12.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un0_n 11 1 .names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i 0 1 -.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n -11 1 +.names un1_as_030_000_sync8_1.BLIF fpu_cs_int_0_un3_n +0 1 .names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i 0 1 -.names N_197.BLIF rw_000_int_0_un3_n +.names inst_FPU_CS_INTreg.BLIF un1_as_030_000_sync8_1.BLIF fpu_cs_int_0_un1_n +11 1 +.names AS_030_c.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n +11 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 -.names state_machine_rw_000_int_7_iv_i_n.BLIF N_197.BLIF rw_000_int_0_un1_n +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +.names N_59.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 -.names RW_c.BLIF state_machine_uds_000_int_7_0_m3_un3_n +.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n 0 1 -.names N_67.BLIF RW_c.BLIF state_machine_uds_000_int_7_0_m3_un1_n +.names inst_DSACK1_INT.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n 11 1 -.names N_66.BLIF state_machine_uds_000_int_7_0_m3_un3_n.BLIF \ -state_machine_uds_000_int_7_0_m3_un0_n +.names sm_amiga_i_1__n.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n 11 1 -.names N_77.BLIF ipl_030_0_0__un3_n +.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n 0 1 -.names IPL_030DFFSH_0_reg.BLIF N_77.BLIF ipl_030_0_0__un1_n +.names state_machine_un5_clk_000_d0_i_0_n.BLIF \ +state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n 11 1 -.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n 11 1 -.names N_77.BLIF ipl_030_0_1__un3_n +.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un3_n 0 1 -.names IPL_030DFFSH_1_reg.BLIF N_77.BLIF ipl_030_0_1__un1_n -11 1 -.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names N_77.BLIF ipl_030_0_2__un3_n -0 1 -.names IPL_030DFFSH_2_reg.BLIF N_77.BLIF ipl_030_0_2__un1_n -11 1 -.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names N_77.BLIF cpu_estse_0_un3_n -0 1 -.names cpu_est_1_.BLIF N_77.BLIF cpu_estse_0_un1_n -11 1 -.names cpu_est_ns_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n -11 1 -.names N_77.BLIF cpu_estse_1_un3_n -0 1 -.names cpu_est_2_.BLIF N_77.BLIF cpu_estse_1_un1_n -11 1 -.names cpu_est_ns_2__n.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n -11 1 -.names N_77.BLIF cpu_estse_2_un3_n -0 1 -.names cpu_est_3_reg.BLIF N_77.BLIF cpu_estse_2_un1_n -11 1 -.names N_149_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n -11 1 -.names N_30.BLIF as_030_000_sync_0_un3_n -0 1 -.names un1_DSACK1_INT_0_sqmuxa_3.BLIF N_30.BLIF as_030_000_sync_0_un1_n -11 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 -.names N_196.BLIF uds_000_int_0_un3_n -0 1 -.names state_machine_uds_000_int_7_n.BLIF N_196.BLIF uds_000_int_0_un1_n -11 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names N_196.BLIF lds_000_int_0_un3_n -0 1 -.names state_machine_lds_000_int_7_n.BLIF N_196.BLIF lds_000_int_0_un1_n -11 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names N_28.BLIF fpu_cs_int_0_un3_n -0 1 -.names AS_030_c.BLIF N_28.BLIF fpu_cs_int_0_un1_n -11 1 -.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n -11 1 -.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un3_n -0 1 -.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \ +.names inst_avec_expreg.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \ avec_exp_0_un1_n 11 1 -.names N_195_i.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un0_n +.names un1_bgack_030_int_d.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un0_n 11 1 .names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n 0 1 @@ -1031,24 +1147,46 @@ avec_exp_0_un1_n 11 1 .names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names N_193.BLIF as_000_int_0_un3_n +.names un1_AS_030_2.BLIF lds_000_int_0_un3_n 0 1 -.names N_67.BLIF N_193.BLIF as_000_int_0_un1_n +.names inst_LDS_000_INT.BLIF un1_AS_030_2.BLIF lds_000_int_0_un1_n 11 1 -.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +.names state_machine_lds_000_int_7_n.BLIF lds_000_int_0_un3_n.BLIF \ +lds_000_int_0_un0_n 11 1 -.names N_75.BLIF dsack1_int_0_un3_n +.names un1_AS_030_2.BLIF uds_000_int_0_un3_n 0 1 -.names N_114_i.BLIF N_75.BLIF dsack1_int_0_un1_n +.names inst_UDS_000_INT.BLIF un1_AS_030_2.BLIF uds_000_int_0_un1_n 11 1 -.names inst_DSACK1_INT.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF \ +uds_000_int_0_un0_n 11 1 -.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n +.names RW_000_INT_0_sqmuxa_1.BLIF rw_000_int_0_un3_n 0 1 -.names state_machine_un10_clk_000_d0_n.BLIF \ -state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n +.names inst_RW_000_INT.BLIF RW_000_INT_0_sqmuxa_1.BLIF rw_000_int_0_un1_n 11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +.names state_machine_rw_000_int_7_iv_i_n.BLIF rw_000_int_0_un3_n.BLIF \ +rw_000_int_0_un0_n +11 1 +.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n +0 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n +11 1 +.names state_machine_un8_bgack_030_int_i_n.BLIF as_000_dma_0_un3_n.BLIF \ +as_000_dma_0_un0_n +11 1 +.names DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n +0 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n +11 1 +.names state_machine_ds_000_dma_3_n.BLIF ds_000_dma_0_un3_n.BLIF \ +ds_000_dma_0_un0_n +11 1 +.names RST_c.BLIF clk_030_h_0_un3_n +0 1 +.names state_machine_clk_030_h_2_n.BLIF RST_c.BLIF clk_030_h_0_un1_n +11 1 +.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n 11 1 .names inst_CLK_OUT_PRE_25.BLIF state_machine_un3_clk_out_pre_50_n.BLIF \ CLK_OUT_PRE_25_0 @@ -1056,6 +1194,11 @@ CLK_OUT_PRE_25_0 10 1 11 0 00 0 +.names cpu_est_0_.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse +01 1 +10 1 +11 0 +00 0 .names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ 1 1 0 0 @@ -1101,7 +1244,7 @@ CLK_OUT_PRE_25_0 .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_220.BLIF CIIN +.names N_210.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -1110,12 +1253,6 @@ CLK_OUT_PRE_25_0 .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -0 0 -.names RST_i.BLIF cpu_est_0_.AR -1 1 -0 0 .names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 0 0 @@ -1134,16 +1271,13 @@ CLK_OUT_PRE_25_0 .names RST_i.BLIF cpu_est_3_reg.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +.names cpu_estse.BLIF cpu_est_0_.D 1 1 0 0 -.names RST_i.BLIF SM_AMIGA_0_.AR +.names CLK_OSZI_c.BLIF cpu_est_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C -1 1 -0 0 -.names RST_i.BLIF SIZE_DMA_1_.AP +.names RST_i.BLIF cpu_est_0_.AR 1 1 0 0 .names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C @@ -1206,10 +1340,10 @@ CLK_OUT_PRE_25_0 .names RST_i.BLIF SM_AMIGA_1_.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 0 0 -.names RST_i.BLIF inst_DSACK1_INT.AP +.names RST_i.BLIF SM_AMIGA_0_.AR 1 1 0 0 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C @@ -1239,6 +1373,12 @@ CLK_OUT_PRE_25_0 .names RST_i.BLIF SIZE_DMA_0_.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names RST_i.BLIF SIZE_DMA_1_.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_LDS_000_INT.C 1 1 0 0 @@ -1281,6 +1421,12 @@ CLK_OUT_PRE_25_0 .names RST_i.BLIF inst_AS_000_INT.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +1 1 +0 0 +.names RST_i.BLIF inst_DSACK1_INT.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_RW_000_INT.C 1 1 0 0 @@ -1335,15 +1481,6 @@ CLK_OUT_PRE_25_0 .names RST_i.BLIF CLK_OUT_INTreg.AR 1 1 0 0 -.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C -1 1 -0 0 -.names RST_i.BLIF inst_CLK_000_D3.AP -1 1 -0 0 .names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D 1 1 0 0 @@ -1440,6 +1577,24 @@ CLK_OUT_PRE_25_0 .names SIZE_DMA_0_.BLIF SIZE_0_ 1 1 0 0 +.names A_28_.BLIF a_c_28__n +1 1 +0 0 +.names A_29_.BLIF a_c_29__n +1 1 +0 0 +.names A_30_.BLIF a_c_30__n +1 1 +0 0 +.names A_31_.BLIF a_c_31__n +1 1 +0 0 +.names A0.PIN.BLIF A0_c +1 1 +0 0 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +0 0 .names BG_030.BLIF BG_030_c 1 1 0 0 @@ -1539,25 +1694,7 @@ CLK_OUT_PRE_25_0 .names A_27_.BLIF a_c_27__n 1 1 0 0 -.names A_28_.BLIF a_c_28__n -1 1 -0 0 -.names A_29_.BLIF a_c_29__n -1 1 -0 0 -.names A_30_.BLIF a_c_30__n -1 1 -0 0 -.names A_31_.BLIF a_c_31__n -1 1 -0 0 -.names A0.PIN.BLIF A0_c -1 1 -0 0 -.names nEXP_SPACE.BLIF nEXP_SPACE_c -1 1 -0 0 -.names N_148.BLIF AS_030.OE +.names un3_dtack_i.BLIF AS_030.OE 1 1 0 0 .names inst_BGACK_030_INTreg.BLIF AS_000.OE @@ -1566,7 +1703,7 @@ CLK_OUT_PRE_25_0 .names inst_BGACK_030_INTreg.BLIF RW_000.OE 1 1 0 0 -.names N_148.BLIF DS_030.OE +.names un3_dtack_i.BLIF DS_030.OE 1 1 0 0 .names inst_BGACK_030_INTreg.BLIF UDS_000.OE @@ -1575,19 +1712,19 @@ CLK_OUT_PRE_25_0 .names inst_BGACK_030_INTreg.BLIF LDS_000.OE 1 1 0 0 -.names N_148.BLIF SIZE_0_.OE +.names un3_dtack_i.BLIF SIZE_0_.OE 1 1 0 0 -.names N_148.BLIF SIZE_1_.OE +.names un3_dtack_i.BLIF SIZE_1_.OE 1 1 0 0 -.names N_148.BLIF A0.OE +.names un3_dtack_i.BLIF A0.OE 1 1 0 0 .names nEXP_SPACE_c.BLIF DSACK1.OE 1 1 0 0 -.names N_148.BLIF DTACK.OE +.names un3_dtack_i.BLIF DTACK.OE 1 1 0 0 .names BGACK_030_INT_i.BLIF RW.OE @@ -1596,7 +1733,7 @@ CLK_OUT_PRE_25_0 .names FPU_CS_INT_i.BLIF BERR.OE 1 1 0 0 -.names N_230.BLIF CIIN.OE +.names N_220.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index 87a1d7b..cd4a0b2 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,89 +1,82 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sun Jun 01 01:03:24 2014 +#$ DATE Sat Jun 07 23:03:19 2014 #$ MODULE 68030_tk -#$ PINS 59 A_26_ A_25_ SIZE_1_ A_24_ A_23_ A_31_ A_22_ A_21_ IPL_030_2_ A_20_ A_19_ \ -# IPL_2_ A_18_ A_17_ FC_1_ A_16_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ RW_000 IPL_1_ DS_030 \ -# IPL_0_ UDS_000 FC_0_ LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 \ -# CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET \ -# RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \ -# A_28_ A_27_ -#$ NODES 44 BG_000DFFSHreg inst_BGACK_030_INTreg inst_FPU_CS_INTreg \ -# inst_avec_expreg inst_VMA_INTreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D \ -# inst_AS_000_DMA inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 CLK_OUT_INTreg \ -# inst_CLK_000_D1 inst_CLK_000_D2 inst_DTACK_D0 IPL_030DFFSH_0_reg \ -# inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 IPL_030DFFSH_1_reg SM_AMIGA_7_ \ -# IPL_030DFFSH_2_reg inst_AS_000_INT SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_5_ SM_AMIGA_2_ \ -# inst_RW_000_INT inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT inst_CLK_000_D3 \ -# inst_CLK_030_H inst_DS_000_DMA SIZE_DMA_0_ SIZE_DMA_1_ inst_A0_DMA RESETDFFRHreg \ -# SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_1_ cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_reg +#$ PINS 59 A_22_ A_21_ SIZE_1_ A_20_ A_19_ A_31_ A_18_ A_17_ IPL_030_2_ A_16_ IPL_030_1_ \ +# IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 \ +# nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT \ +# CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE \ +# AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ \ +# A_25_ A_24_ A_23_ +#$ NODES 43 inst_BGACK_030_INTreg inst_FPU_CS_INTreg inst_avec_expreg \ +# inst_VMA_INTreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA \ +# inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 BG_000DFFSHreg inst_CLK_000_D1 \ +# inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_1_ inst_AS_000_INT \ +# SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_7_ inst_RW_000_INT CLK_OUT_INTreg inst_UDS_000_INT \ +# inst_LDS_000_INT inst_DSACK1_INT IPL_030DFFSH_0_reg inst_CLK_000_D2 \ +# IPL_030DFFSH_1_reg inst_CLK_030_H inst_DS_000_DMA IPL_030DFFSH_2_reg SIZE_DMA_0_ \ +# SIZE_DMA_1_ inst_A0_DMA SM_AMIGA_5_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ \ +# RESETDFFRHreg cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_reg .model bus68030 .inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \ A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \ A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \ -A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF BG_000DFFSHreg.BLIF \ -inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF inst_avec_expreg.BLIF \ -inst_VMA_INTreg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_AS_000_DMA.BLIF inst_VPA_D.BLIF inst_CLK_OUT_PRE_50_D.BLIF \ -inst_CLK_000_D0.BLIF CLK_OUT_INTreg.BLIF inst_CLK_000_D1.BLIF \ -inst_CLK_000_D2.BLIF inst_DTACK_D0.BLIF IPL_030DFFSH_0_reg.BLIF \ -inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF IPL_030DFFSH_1_reg.BLIF \ -SM_AMIGA_7_.BLIF IPL_030DFFSH_2_reg.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_0_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_2_.BLIF inst_RW_000_INT.BLIF \ -inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF \ -inst_CLK_000_D3.BLIF inst_CLK_030_H.BLIF inst_DS_000_DMA.BLIF SIZE_DMA_0_.BLIF \ -SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF RESETDFFRHreg.BLIF SM_AMIGA_4_.BLIF \ -SM_AMIGA_3_.BLIF SM_AMIGA_1_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ +A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_FPU_CS_INTreg.BLIF inst_avec_expreg.BLIF inst_VMA_INTreg.BLIF \ +inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF \ +inst_VPA_D.BLIF inst_CLK_OUT_PRE_50_D.BLIF inst_CLK_000_D0.BLIF \ +BG_000DFFSHreg.BLIF inst_CLK_000_D1.BLIF inst_DTACK_D0.BLIF \ +inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF SM_AMIGA_1_.BLIF \ +inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.BLIF \ +inst_RW_000_INT.BLIF CLK_OUT_INTreg.BLIF inst_UDS_000_INT.BLIF \ +inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF IPL_030DFFSH_0_reg.BLIF \ +inst_CLK_000_D2.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_030_H.BLIF \ +inst_DS_000_DMA.BLIF IPL_030DFFSH_2_reg.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF \ +inst_A0_DMA.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \ +SM_AMIGA_2_.BLIF RESETDFFRHreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ cpu_est_2_.BLIF cpu_est_3_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ RW_000.PIN.BLIF DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF \ RW.PIN.BLIF .outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \ -cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C \ -cpu_est_2_.AR cpu_est_3_reg.C cpu_est_3_reg.AR SM_AMIGA_0_.D SM_AMIGA_0_.C \ -SM_AMIGA_0_.AR SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP IPL_030DFFSH_0_reg.D \ +CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR \ +cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.C cpu_est_3_reg.AR \ +cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR IPL_030DFFSH_0_reg.D \ IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \ SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \ SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \ -SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR inst_DSACK1_INT.D \ -inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_VMA_INTreg.C inst_VMA_INTreg.AP \ +SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \ +SM_AMIGA_0_.C SM_AMIGA_0_.AR inst_VMA_INTreg.C inst_VMA_INTreg.AP \ inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \ inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR \ -SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP inst_LDS_000_INT.D \ -inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D \ -inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_avec_expreg.D \ -inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ -BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP \ -inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP inst_AS_000_INT.D \ -inst_AS_000_INT.C inst_AS_000_INT.AP inst_RW_000_INT.D inst_RW_000_INT.C \ +SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP SIZE_DMA_1_.D SIZE_DMA_1_.C \ +SIZE_DMA_1_.AP inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP \ +inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \ +inst_avec_expreg.D inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D \ +BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C \ +inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \ +inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_000_INT.AP inst_DSACK1_INT.D \ +inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_RW_000_INT.D inst_RW_000_INT.C \ inst_RW_000_INT.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ inst_AS_030_000_SYNC.AP inst_CLK_030_H.D inst_CLK_030_H.C inst_UDS_000_INT.D \ inst_UDS_000_INT.C inst_UDS_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C \ inst_A0_DMA.AP inst_DTACK_D0.D inst_DTACK_D0.C inst_DTACK_D0.AP \ inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_OUT_INTreg.D \ -CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D3.D inst_CLK_000_D3.C \ -inst_CLK_000_D3.AP inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP \ -inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP \ -inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR \ -inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D \ -inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ -inst_CLK_OUT_PRE_50.AR RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR \ -SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ \ -AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ -SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE inst_VMA_INTreg.D.X1 \ +CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C \ +inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \ +inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C \ +inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D inst_CLK_000_D0.C \ +inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \ +inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR \ +RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR SIZE_1_ AS_030 AS_000 RW_000 \ +DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ AS_030.OE AS_000.OE \ +RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE \ +DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE inst_VMA_INTreg.D.X1 \ inst_VMA_INTreg.D.X2 cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF cpu_est_0_.D -100 1 --11 1 -0-1 1 -101 0 --10 0 -0-0 0 .names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF \ cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_1_.D 1010-- 1 @@ -110,19 +103,6 @@ cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_2_.D --010- 0 -1--0- 0 0---0- 0 -.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.D -01- 1 -0-1 1 --00 0 -1-- 0 -.names inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ -LDS_000.PIN.BLIF SIZE_DMA_1_.D ---00 1 ---11 1 --1-- 1 -1--- 1 -0010 0 -0001 0 .names IPL_0_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_0_reg.D 110- 1 @@ -148,28 +128,28 @@ IPL_030DFFSH_2_reg.BLIF IPL_030DFFSH_2_reg.D --10 0 -0-0 0 .names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D2.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_0_.BLIF inst_CLK_000_D3.BLIF \ +inst_CLK_000_D1.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.BLIF inst_CLK_000_D2.BLIF \ SM_AMIGA_7_.D ---1--1- 1 ----11-- 1 --1--1-- 1 -0---1-- 1 -----1-0 1 -10-0-01 0 +--1-1-- 1 +---1-1- 1 +-1---1- 1 +0----1- 1 +-----10 1 +10-00-1 0 1000--1 0 ----00- 0 ---0-0-- 0 +--0--0- 0 .names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D2.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.BLIF inst_CLK_000_D3.BLIF \ +inst_CLK_000_D1.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF inst_CLK_000_D2.BLIF \ SM_AMIGA_6_.D -10-01-1 1 ---0-01- 1 +10-0-11 1 +--0-10- 1 ----00- 0 ---1-0-- 0 ----11-- 0 --1--1-- 0 -0---1-- 0 -----1-0 0 +--1--0- 0 +---1-1- 0 +-1---1- 0 +0----1- 0 +-----10 0 .names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_5_.D 11- 1 1-1 1 @@ -183,10 +163,10 @@ SM_AMIGA_6_.D .names inst_VMA_INTreg.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF \ inst_CLK_000_D1.BLIF inst_DTACK_D0.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \ cpu_est_1_.BLIF cpu_est_3_reg.BLIF SM_AMIGA_3_.D ---1--1--- 1 --0----11- 1 -1--1-1-- 1 +-0----11- 1 10----1-- 1 +--1--1--- 1 ---0--1-- 1 -0----1-0 1 --1---1-- 1 @@ -195,31 +175,28 @@ cpu_est_1_.BLIF cpu_est_3_reg.BLIF SM_AMIGA_3_.D -----00-- 0 --0---0-- 0 .names inst_VMA_INTreg.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF inst_DTACK_D0.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_3_.BLIF \ +inst_CLK_000_D1.BLIF inst_DTACK_D0.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \ cpu_est_1_.BLIF cpu_est_3_reg.BLIF SM_AMIGA_2_.D -0001--101 1 --1010-1-- 1 ---0--1--- 1 --1--10--- 0 --0---0-1- 0 -10---0--- 0 +0001-1-01 1 +-10101--- 1 +--0---1-- 1 +-1--1-0-- 0 +-0----01- 0 +10----0-- 0 -----00-- 0 ----0-0--- 0 --0---0--0 0 +---0--0-- 0 +-0----0-0 0 --1------ 0 -.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_1_.D +.names inst_CLK_000_D0.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.D 11- 1 1-1 1 -00 0 0-- 0 -.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF inst_DSACK1_INT.BLIF \ -AS_030.PIN.BLIF inst_DSACK1_INT.D --01- 1 -0-1- 1 --0-1 1 -0--1 1 -11-- 0 ---00 0 +.names inst_CLK_000_D0.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D +01- 1 +0-1 1 +-00 0 +1-- 0 .names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \ inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D 1-10 1 @@ -234,32 +211,40 @@ LDS_000.PIN.BLIF SIZE_DMA_0_.D 1--- 1 ---1 1 0000 0 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_5_.BLIF \ -inst_LDS_000_INT.BLIF SM_AMIGA_4_.BLIF AS_030.PIN.BLIF DS_030.PIN.BLIF \ -SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF RW.PIN.BLIF inst_LDS_000_INT.D -1---1-01000 1 --11---01001 1 ----10-----0 1 -0--1------0 1 ---01------1 1 --0-1------1 1 ----1--1---- 1 -----01----0 1 -0----1----0 1 ---0--1----1 1 --0---1----1 1 ------11---- 1 -1---1-0--10 0 -1---1-0-1-0 0 -1---1-00--0 0 --11---0--11 0 --11---0-1-1 0 --11---00--1 0 ----000----0 0 -0--0-0----0 0 ---00-0----1 0 --0-0-0----1 0 ----0-01---- 0 +.names inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ +LDS_000.PIN.BLIF SIZE_DMA_1_.D +--00 1 +--11 1 +-1-- 1 +1--- 1 +0010 0 +0001 0 +.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF inst_LDS_000_INT.BLIF \ +SM_AMIGA_5_.BLIF AS_030.PIN.BLIF DS_030.PIN.BLIF SIZE_0_.PIN.BLIF \ +SIZE_1_.PIN.BLIF A0.PIN.BLIF RW.PIN.BLIF inst_LDS_000_INT.D +0-10------ 1 +-01------1 1 +0--01----- 1 +-0--1----1 1 +0--1-01000 1 +11---01001 1 +1---1----0 1 +1-1------0 1 +0---1----1 1 +0-1------1 1 +----11---- 1 +--1--1---- 1 +0-000----- 0 +-00-0----1 0 +0--1-0--10 0 +0--1-0-1-0 0 +0--1-00--0 0 +11---0--11 0 +11---0-1-1 0 +11---00--1 0 +--0-01---- 0 +1-0-0----0 0 +0-0-0----1 0 .names FC_1_.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \ A_16_.BLIF FC_0_.BLIF inst_FPU_CS_INTreg.BLIF AS_030.PIN.BLIF \ inst_FPU_CS_INTreg.D @@ -275,17 +260,26 @@ inst_FPU_CS_INTreg.D 11100101-0 0 --------00 0 .names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_avec_expreg.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_CLK_000_D2.BLIF \ -SM_AMIGA_7_.BLIF inst_CLK_000_D3.BLIF inst_avec_expreg.D --11---0- 1 --1---11- 1 --1-1--1- 1 -01----1- 1 --1--0--- 1 --1----10 1 -1--01011 0 ---0-1-0- 0 --0------ 0 +inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_CLK_000_D0.BLIF \ +inst_CLK_000_D1.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.BLIF \ +inst_CLK_000_D2.BLIF AS_030.PIN.BLIF inst_avec_expreg.D +-1-----0010- 1 +-1----1001-- 1 +-1-1---001-- 1 +01-----001-- 1 +-11------0-- 1 +-11-----1--- 1 +-1---0-1---1 1 +-11----1---- 1 +-1-----1-1-1 1 +-1--0------- 1 +-1------1--1 1 +1--01-00011- 0 +--0-11--00-- 0 +--0-1--000-- 0 +--0-1---1--0 0 +--0-1--1---0 0 +-0---------- 0 .names nEXP_SPACE.BLIF BG_030.BLIF CLK_000.BLIF BG_000DFFSHreg.BLIF \ SM_AMIGA_7_.BLIF AS_030.PIN.BLIF BG_000DFFSHreg.D ---10- 1 @@ -323,7 +317,7 @@ AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_AS_000_DMA.D 00-00- 0 -000-0 0 00-0-0 0 -.names inst_CLK_000_D2.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF \ +.names inst_CLK_000_D0.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF \ AS_030.PIN.BLIF inst_AS_000_INT.D -10- 1 01-- 1 @@ -331,6 +325,11 @@ AS_030.PIN.BLIF inst_AS_000_INT.D 0--1 1 1-1- 0 -0-0 0 +.names SM_AMIGA_1_.BLIF inst_DSACK1_INT.BLIF AS_030.PIN.BLIF inst_DSACK1_INT.D +01- 1 +0-1 1 +-00 0 +1-- 0 .names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \ SM_AMIGA_6_.BLIF SM_AMIGA_0_.BLIF inst_RW_000_INT.BLIF AS_000.PIN.BLIF \ RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF RW.PIN.BLIF \ @@ -369,39 +368,27 @@ inst_RW_000_INT.D 1-0--0----- 0 .names FC_1_.BLIF nEXP_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF \ A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D2.BLIF \ -SM_AMIGA_7_.BLIF SM_AMIGA_2_.BLIF inst_CLK_000_D3.BLIF AS_030.PIN.BLIF \ -inst_AS_030_000_SYNC.D -1-1-00101-1------ 1 --0----------01-1- 1 ------------1--1-- 1 -----------1--0--- 1 ----------01------ 1 ----0------1------ 1 --0--------1------ 1 -----------------1 1 --1-1----01---10-0 0 --1-1---1-1---10-0 0 --1-1--0--1---10-0 0 --1-1-1---1---10-0 0 --1-11----1---10-0 0 --101-----1---10-0 0 -01-1-----1---10-0 0 --1-1----01-0-1--0 0 --1-1---1-1-0-1--0 0 --1-1--0--1-0-1--0 0 --1-1-1---1-0-1--0 0 --1-11----1-0-1--0 0 --101-----1-0-1--0 0 -01-1-----1-0-1--0 0 -----------0---000 0 -----------00---00 0 -----------0--00-0 0 -----------0-1-0-0 0 -----------00-0--0 0 -----------001---0 0 --1--------0---0-0 0 --1--------00----0 0 +inst_AS_030_000_SYNC.BLIF inst_CLK_000_D1.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_7_.BLIF inst_CLK_000_D2.BLIF AS_030.PIN.BLIF inst_AS_030_000_SYNC.D +1-1-00101-1----- 1 +-0---------0-11- 1 +----------1--0-- 1 +---------01----- 1 +---0------1----- 1 +-0--------1----- 1 +------------1--- 1 +---------------1 1 +-1-1----01--01-0 0 +-1-1---1-1--01-0 0 +-1-1--0--1--01-0 0 +-1-1-1---1--01-0 0 +-1-11----1--01-0 0 +-101-----1--01-0 0 +01-1-----1--01-0 0 +----------0-0-00 0 +----------0-00-0 0 +----------010--0 0 +-1--------0-0--0 0 .names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ inst_CLK_030_H.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ inst_CLK_030_H.D @@ -416,28 +403,28 @@ inst_CLK_030_H.D ---10--- 0 -0--0--- 0 0---0--- 0 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_5_.BLIF \ -inst_UDS_000_INT.BLIF SM_AMIGA_4_.BLIF AS_030.PIN.BLIF DS_030.PIN.BLIF \ -A0.PIN.BLIF RW.PIN.BLIF inst_UDS_000_INT.D -1---1-010 1 --11---011 1 ----10---0 1 -0--1----0 1 ---01----1 1 --0-1----1 1 ----1--1-- 1 -----01--0 1 -0----1--0 1 ---0--1--1 1 --0---1--1 1 ------11-- 1 -1---1-000 0 --11---001 0 ----000--0 0 -0--0-0--0 0 ---00-0--1 0 --0-0-0--1 0 ----0-01-- 0 +.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF inst_UDS_000_INT.BLIF \ +SM_AMIGA_5_.BLIF AS_030.PIN.BLIF DS_030.PIN.BLIF A0.PIN.BLIF RW.PIN.BLIF \ +inst_UDS_000_INT.D +--10---0 1 +-01----1 1 +---01--0 1 +-0--1--1 1 +0--1-010 1 +11---011 1 +1-1----0 1 +0-1----1 1 +--1--1-- 1 +1---1--0 1 +0---1--1 1 +----11-- 1 +--000--0 0 +-00-0--1 0 +0--1-000 0 +11---001 0 +--0-01-- 0 +1-0-0--0 0 +0-0-0--1 0 .names inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ LDS_000.PIN.BLIF inst_A0_DMA.D 0010 1 @@ -507,12 +494,6 @@ AMIGA_BUS_DATA_DIR .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 -.names CLK_OSZI.BLIF cpu_est_0_.C -1 1 -0 0 -.names RST.BLIF cpu_est_0_.AR -0 1 -1 0 .names CLK_OSZI.BLIF cpu_est_1_.C 1 1 0 0 @@ -531,16 +512,17 @@ AMIGA_BUS_DATA_DIR .names RST.BLIF cpu_est_3_reg.AR 0 1 1 0 -.names CLK_OSZI.BLIF SM_AMIGA_0_.C +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF cpu_est_0_.D +100 1 +-11 1 +0-1 1 +101 0 +-10 0 +0-0 0 +.names CLK_OSZI.BLIF cpu_est_0_.C 1 1 0 0 -.names RST.BLIF SM_AMIGA_0_.AR -0 1 -1 0 -.names CLK_OSZI.BLIF SIZE_DMA_1_.C -1 1 -0 0 -.names RST.BLIF SIZE_DMA_1_.AP +.names RST.BLIF cpu_est_0_.AR 0 1 1 0 .names CLK_OSZI.BLIF IPL_030DFFSH_0_reg.C @@ -603,10 +585,10 @@ AMIGA_BUS_DATA_DIR .names RST.BLIF SM_AMIGA_1_.AR 0 1 1 0 -.names CLK_OSZI.BLIF inst_DSACK1_INT.C +.names CLK_OSZI.BLIF SM_AMIGA_0_.C 1 1 0 0 -.names RST.BLIF inst_DSACK1_INT.AP +.names RST.BLIF SM_AMIGA_0_.AR 0 1 1 0 .names CLK_OSZI.BLIF inst_VMA_INTreg.C @@ -641,6 +623,12 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D .names RST.BLIF SIZE_DMA_0_.AP 0 1 1 0 +.names CLK_OSZI.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names RST.BLIF SIZE_DMA_1_.AP +0 1 +1 0 .names CLK_OSZI.BLIF inst_LDS_000_INT.C 1 1 0 0 @@ -683,6 +671,12 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D .names RST.BLIF inst_AS_000_INT.AP 0 1 1 0 +.names CLK_OSZI.BLIF inst_DSACK1_INT.C +1 1 +0 0 +.names RST.BLIF inst_DSACK1_INT.AP +0 1 +1 0 .names CLK_OSZI.BLIF inst_RW_000_INT.C 1 1 0 0 @@ -737,15 +731,6 @@ inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D .names RST.BLIF CLK_OUT_INTreg.AR 0 1 1 0 -.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D -1 1 -0 0 -.names CLK_OSZI.BLIF inst_CLK_000_D3.C -1 1 -0 0 -.names RST.BLIF inst_CLK_000_D3.AP -0 1 -1 0 .names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D 1 1 0 0 diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index c8e7089..4f888df 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 1.7.00.05.28.13 -// Design '68030_tk' created Sun Jun 01 01:03:24 2014 +// Design '68030_tk' created Sat Jun 07 23:03:19 2014 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index 9a0f404..1a4d320 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,7 +2,7 @@ Copyright(C), 1992-2013, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Sun Jun 01 01:03:24 2014 +Design bus68030 created Sat Jun 07 23:03:19 2014 P-Terms Fan-in Fan-out Type Name (attributes) @@ -17,9 +17,7 @@ Design bus68030 created Sun Jun 01 01:03:24 2014 1 1 1 Pin DTACK 1 3 1 Pin DTACK.OE 1 0 1 Pin AVEC - 3 8 1 Pin AVEC_EXP.D- - 1 1 1 Pin AVEC_EXP.AP - 1 1 1 Pin AVEC_EXP.C + 1 1 1 Pin AVEC_EXP 1 1 1 Pin RW 1 1 1 Pin RW.OE 1 1 1 Pin AMIGA_BUS_ENABLE @@ -34,30 +32,30 @@ Design bus68030 created Sun Jun 01 01:03:24 2014 3 4 1 Pin IPL_030_2_.D 1 1 1 Pin IPL_030_2_.AP 1 1 1 Pin IPL_030_2_.C + 3 4 1 Pin IPL_030_1_.D + 1 1 1 Pin IPL_030_1_.AP + 1 1 1 Pin IPL_030_1_.C + 3 4 1 Pin IPL_030_0_.D + 1 1 1 Pin IPL_030_0_.AP + 1 1 1 Pin IPL_030_0_.C 1 3 1 Pin AS_030.OE 4 6 1 Pin AS_030.D 1 1 1 Pin AS_030.AP 1 1 1 Pin AS_030.C - 3 4 1 Pin IPL_030_1_.D - 1 1 1 Pin IPL_030_1_.AP - 1 1 1 Pin IPL_030_1_.C 1 1 1 Pin AS_000.OE 2 4 1 Pin AS_000.D- 1 1 1 Pin AS_000.AP 1 1 1 Pin AS_000.C - 3 4 1 Pin IPL_030_0_.D - 1 1 1 Pin IPL_030_0_.AP - 1 1 1 Pin IPL_030_0_.C 1 3 1 Pin DS_030.OE 7 9 1 Pin DS_030.D 1 1 1 Pin DS_030.AP 1 1 1 Pin DS_030.C 1 1 1 Pin UDS_000.OE - 7 9 1 Pin UDS_000.D- + 7 8 1 Pin UDS_000.D- 1 1 1 Pin UDS_000.AP 1 1 1 Pin UDS_000.C 1 1 1 Pin LDS_000.OE - 11 11 1 Pin LDS_000.D- + 11 10 1 Pin LDS_000.D- 1 1 1 Pin LDS_000.AP 1 1 1 Pin LDS_000.C 1 3 1 Pin A0.OE @@ -77,7 +75,7 @@ Design bus68030 created Sun Jun 01 01:03:24 2014 1 1 1 Pin FPU_CS.AP 1 1 1 Pin FPU_CS.C 1 1 1 Pin DSACK1.OE - 2 4 1 Pin DSACK1.D- + 2 3 1 Pin DSACK1.D 1 1 1 Pin DSACK1.AP 1 1 1 Pin DSACK1.C 3 6 1 PinX1 E.D.X1 @@ -95,7 +93,10 @@ Design bus68030 created Sun Jun 01 01:03:24 2014 1 4 1 Pin SIZE_0_.D- 1 1 1 Pin SIZE_0_.AP 1 1 1 Pin SIZE_0_.C - 8 17 1 Node inst_AS_030_000_SYNC.D + 6 12 1 Node inst_avec_expreg.D- + 1 1 1 Node inst_avec_expreg.AP + 1 1 1 Node inst_avec_expreg.C + 8 16 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C 1 1 1 Node inst_BGACK_030_INT_D.D @@ -113,9 +114,6 @@ Design bus68030 created Sun Jun 01 01:03:24 2014 1 1 1 Node inst_CLK_000_D1.D 1 1 1 Node inst_CLK_000_D1.AP 1 1 1 Node inst_CLK_000_D1.C - 1 1 1 Node inst_CLK_000_D2.D - 1 1 1 Node inst_CLK_000_D2.AP - 1 1 1 Node inst_CLK_000_D2.C 1 1 1 Node inst_DTACK_D0.D 1 1 1 Node inst_DTACK_D0.AP 1 1 1 Node inst_DTACK_D0.C @@ -125,38 +123,38 @@ Design bus68030 created Sun Jun 01 01:03:24 2014 1 1 1 Node inst_CLK_OUT_PRE_25.AR 3 3 1 Node inst_CLK_OUT_PRE_25.D 1 1 1 Node inst_CLK_OUT_PRE_25.C - 4 7 1 Node SM_AMIGA_7_.D- - 1 1 1 Node SM_AMIGA_7_.AP - 1 1 1 Node SM_AMIGA_7_.C + 1 1 1 Node SM_AMIGA_1_.AR + 2 3 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C 1 1 1 Node SM_AMIGA_6_.AR 2 7 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C 1 1 1 Node SM_AMIGA_0_.AR 2 3 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C - 1 1 1 Node SM_AMIGA_5_.AR - 2 3 1 Node SM_AMIGA_5_.D - 1 1 1 Node SM_AMIGA_5_.C - 1 1 1 Node SM_AMIGA_2_.AR - 3 9 1 Node SM_AMIGA_2_.D - 1 1 1 Node SM_AMIGA_2_.C + 4 7 1 Node SM_AMIGA_7_.D- + 1 1 1 Node SM_AMIGA_7_.AP + 1 1 1 Node SM_AMIGA_7_.C 14 11 1 Node inst_RW_000_INT.D- 1 1 1 Node inst_RW_000_INT.AP 1 1 1 Node inst_RW_000_INT.C - 1 1 1 Node inst_CLK_000_D3.D - 1 1 1 Node inst_CLK_000_D3.AP - 1 1 1 Node inst_CLK_000_D3.C + 1 1 1 Node inst_CLK_000_D2.D + 1 1 1 Node inst_CLK_000_D2.AP + 1 1 1 Node inst_CLK_000_D2.C 5 8 1 Node inst_CLK_030_H.D 1 1 1 Node inst_CLK_030_H.C + 1 1 1 Node SM_AMIGA_5_.AR + 2 3 1 Node SM_AMIGA_5_.D + 1 1 1 Node SM_AMIGA_5_.C 1 1 1 Node SM_AMIGA_4_.AR 2 3 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C 1 1 1 Node SM_AMIGA_3_.AR 4 9 1 Node SM_AMIGA_3_.D- 1 1 1 Node SM_AMIGA_3_.C - 1 1 1 Node SM_AMIGA_1_.AR - 2 3 1 Node SM_AMIGA_1_.D - 1 1 1 Node SM_AMIGA_1_.C + 1 1 1 Node SM_AMIGA_2_.AR + 3 9 1 Node SM_AMIGA_2_.D + 1 1 1 Node SM_AMIGA_2_.C 1 1 1 Node cpu_est_0_.AR 3 3 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C @@ -168,7 +166,7 @@ Design bus68030 created Sun Jun 01 01:03:24 2014 1 1 1 Node cpu_est_2_.AR 1 1 1 Node cpu_est_2_.C ========= - 248 P-Term Total: 248 + 249 P-Term Total: 249 Total Pins: 59 Total Nodes: 24 Average P-Term/Output: 2 @@ -196,19 +194,13 @@ DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); AVEC = (1); -!AVEC_EXP.D = (!BGACK_030.Q - # inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q & !AVEC_EXP - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q); - -AVEC_EXP.AP = (!RST); - -AVEC_EXP.C = (CLK_OSZI); +AVEC_EXP = (inst_avec_expreg.Q); RW = (inst_RW_000_INT.Q); RW.OE = (!BGACK_030.Q); -AMIGA_BUS_ENABLE = (AVEC_EXP); +AMIGA_BUS_ENABLE = (inst_avec_expreg.Q); AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW.PIN # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW.PIN); @@ -236,6 +228,22 @@ IPL_030_2_.AP = (!RST); IPL_030_2_.C = (CLK_OSZI); +IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q + # inst_CLK_000_D1.Q & IPL_030_1_.Q + # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); + +IPL_030_1_.AP = (!RST); + +IPL_030_1_.C = (CLK_OSZI); + +IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q + # inst_CLK_000_D1.Q & IPL_030_0_.Q + # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); + +IPL_030_0_.AP = (!RST); + +IPL_030_0_.C = (CLK_OSZI); + AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); AS_030.D = (BGACK_030.Q @@ -247,31 +255,15 @@ AS_030.AP = (!RST); AS_030.C = (CLK_OSZI); -IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q - # inst_CLK_000_D1.Q & IPL_030_1_.Q - # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); - -IPL_030_1_.AP = (!RST); - -IPL_030_1_.C = (CLK_OSZI); - AS_000.OE = (BGACK_030.Q); -!AS_000.D = (inst_CLK_000_D2.Q & SM_AMIGA_5_.Q +!AS_000.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q # !AS_000.Q & !AS_030.PIN); AS_000.AP = (!RST); AS_000.C = (CLK_OSZI); -IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q - # inst_CLK_000_D1.Q & IPL_030_0_.Q - # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); - -IPL_030_0_.AP = (!RST); - -IPL_030_0_.C = (CLK_OSZI); - DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); DS_030.D = (BGACK_030.Q @@ -289,12 +281,12 @@ DS_030.C = (CLK_OSZI); UDS_000.OE = (BGACK_030.Q); !UDS_000.D = (!UDS_000.Q & !AS_030.PIN & DS_030.PIN - # !inst_CLK_000_D2.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN - # !SM_AMIGA_5_.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN - # !inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & !RW.PIN - # !UDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN & !RW.PIN - # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN & RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !A0.PIN & !RW.PIN); + # !inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN + # !SM_AMIGA_6_.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN + # inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & !RW.PIN + # !UDS_000.Q & !SM_AMIGA_5_.Q & !AS_030.PIN & !RW.PIN + # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & !A0.PIN & RW.PIN + # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN & !RW.PIN); UDS_000.AP = (!RST); @@ -303,16 +295,16 @@ UDS_000.C = (CLK_OSZI); LDS_000.OE = (BGACK_030.Q); !LDS_000.D = (!LDS_000.Q & !AS_030.PIN & DS_030.PIN - # !inst_CLK_000_D2.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN - # !SM_AMIGA_5_.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN - # !inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & !RW.PIN - # !LDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN & !RW.PIN - # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !SIZE_0_.PIN & RW.PIN - # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_1_.PIN & RW.PIN - # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & A0.PIN & RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !SIZE_0_.PIN & !RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & SIZE_1_.PIN & !RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & A0.PIN & !RW.PIN); + # !inst_CLK_000_D0.Q & !LDS_000.Q & !SM_AMIGA_5_.Q & !AS_030.PIN + # !inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN + # !SM_AMIGA_6_.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN + # inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & !RW.PIN + # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & !SIZE_0_.PIN & RW.PIN + # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & SIZE_1_.PIN & RW.PIN + # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & A0.PIN & RW.PIN + # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !SIZE_0_.PIN & !RW.PIN + # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_1_.PIN & !RW.PIN + # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & A0.PIN & !RW.PIN); LDS_000.AP = (!RST); @@ -355,8 +347,8 @@ FPU_CS.C = (CLK_OSZI); DSACK1.OE = (nEXP_SPACE); -!DSACK1.D = (inst_CLK_000_D0.Q & SM_AMIGA_2_.Q - # !DSACK1.Q & !AS_030.PIN); +DSACK1.D = (!SM_AMIGA_1_.Q & DSACK1.Q + # !SM_AMIGA_1_.Q & AS_030.PIN); DSACK1.AP = (!RST); @@ -395,13 +387,24 @@ SIZE_0_.AP = (!RST); SIZE_0_.C = (CLK_OSZI); -inst_AS_030_000_SYNC.D = (AS_030.PIN +!inst_avec_expreg.D = (!BGACK_030.Q + # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_1_.Q & !AS_030.PIN + # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_0_.Q & !AS_030.PIN + # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & inst_CLK_000_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q + # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q + # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q); + +inst_avec_expreg.AP = (!RST); + +inst_avec_expreg.C = (CLK_OSZI); + +inst_AS_030_000_SYNC.D = (SM_AMIGA_1_.Q + # AS_030.PIN # !nEXP_SPACE & inst_AS_030_000_SYNC.Q # !CLK_030 & inst_AS_030_000_SYNC.Q # !BGACK_030.Q & inst_AS_030_000_SYNC.Q # inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q - # !nEXP_SPACE & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q + # !nEXP_SPACE & !inst_CLK_000_D1.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q # FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q); inst_AS_030_000_SYNC.AP = (!RST); @@ -438,12 +441,6 @@ inst_CLK_000_D1.AP = (!RST); inst_CLK_000_D1.C = (CLK_OSZI); -inst_CLK_000_D2.D = (inst_CLK_000_D1.Q); - -inst_CLK_000_D2.AP = (!RST); - -inst_CLK_000_D2.C = (CLK_OSZI); - inst_DTACK_D0.D = (DTACK.PIN); inst_DTACK_D0.AP = (!RST); @@ -464,43 +461,35 @@ inst_CLK_OUT_PRE_25.D = (inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_25.Q inst_CLK_OUT_PRE_25.C = (CLK_OSZI); -!SM_AMIGA_7_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q - # !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D0.Q & !inst_CLK_000_D2.Q & inst_CLK_000_D3.Q - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & !SM_AMIGA_0_.Q & inst_CLK_000_D3.Q); +SM_AMIGA_1_.AR = (!RST); -SM_AMIGA_7_.AP = (!RST); +SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q + # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q); -SM_AMIGA_7_.C = (CLK_OSZI); +SM_AMIGA_1_.C = (CLK_OSZI); SM_AMIGA_6_.AR = (!RST); -SM_AMIGA_6_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q); +SM_AMIGA_6_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q + # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q); SM_AMIGA_6_.C = (CLK_OSZI); SM_AMIGA_0_.AR = (!RST); -SM_AMIGA_0_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_0_.Q - # !inst_CLK_000_D0.Q & SM_AMIGA_1_.Q); +SM_AMIGA_0_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_1_.Q + # !inst_CLK_000_D0.Q & SM_AMIGA_0_.Q); SM_AMIGA_0_.C = (CLK_OSZI); -SM_AMIGA_5_.AR = (!RST); +!SM_AMIGA_7_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q + # !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q + # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q + # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_0_.Q & inst_CLK_000_D2.Q); -SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_5_.Q); +SM_AMIGA_7_.AP = (!RST); -SM_AMIGA_5_.C = (CLK_OSZI); - -SM_AMIGA_2_.AR = (!RST); - -SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q - # inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q - # !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); - -SM_AMIGA_2_.C = (CLK_OSZI); +SM_AMIGA_7_.C = (CLK_OSZI); !inst_RW_000_INT.D = (CLK_030 & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q # BGACK_030.Q & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q @@ -521,11 +510,11 @@ inst_RW_000_INT.AP = (!RST); inst_RW_000_INT.C = (CLK_OSZI); -inst_CLK_000_D3.D = (inst_CLK_000_D2.Q); +inst_CLK_000_D2.D = (inst_CLK_000_D1.Q); -inst_CLK_000_D3.AP = (!RST); +inst_CLK_000_D2.AP = (!RST); -inst_CLK_000_D3.C = (CLK_OSZI); +inst_CLK_000_D2.C = (CLK_OSZI); inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q # !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN @@ -535,6 +524,13 @@ inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q inst_CLK_030_H.C = (CLK_OSZI); +SM_AMIGA_5_.AR = (!RST); + +SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q + # inst_CLK_000_D0.Q & SM_AMIGA_5_.Q); + +SM_AMIGA_5_.C = (CLK_OSZI); + SM_AMIGA_4_.AR = (!RST); SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q @@ -551,12 +547,13 @@ SM_AMIGA_3_.AR = (!RST); SM_AMIGA_3_.C = (CLK_OSZI); -SM_AMIGA_1_.AR = (!RST); +SM_AMIGA_2_.AR = (!RST); -SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_2_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_1_.Q); +SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q + # inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q + # !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); -SM_AMIGA_1_.C = (CLK_OSZI); +SM_AMIGA_2_.C = (CLK_OSZI); cpu_est_0_.AR = (!RST); diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index 0b0c368..b71dba5 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -10,7 +10,7 @@ DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_1_20 // OUT DATA LOCATION AS_000:D_4_33 // IO {RN_AS_000} DATA LOCATION AS_030:H_6_82 // IO {RN_AS_030} DATA LOCATION AVEC:A_2_92 // OUT -DATA LOCATION AVEC_EXP:C_0_22 // IO {RN_AVEC_EXP} +DATA LOCATION AVEC_EXP:C_0_22 // OUT DATA LOCATION A_16_:A_*_96 // INP DATA LOCATION A_17_:F_*_59 // INP DATA LOCATION A_18_:A_*_95 // INP @@ -55,7 +55,6 @@ DATA LOCATION LDS_000:D_8_31 // IO {RN_LDS_000} DATA LOCATION RESET:B_1_3 // OUT DATA LOCATION RN_AS_000:D_4 // NOD {AS_000} DATA LOCATION RN_AS_030:H_6 // NOD {AS_030} -DATA LOCATION RN_AVEC_EXP:C_0 // NOD {AVEC_EXP} DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030} DATA LOCATION RN_BG_000:D_2 // NOD {BG_000} DATA LOCATION RN_DSACK1:H_8 // NOD {DSACK1} @@ -70,36 +69,36 @@ DATA LOCATION RN_UDS_000:D_6 // NOD {UDS_000} DATA LOCATION RN_VMA:D_1 // NOD {VMA} DATA LOCATION RST:*_*_86 // INP DATA LOCATION RW:G_0_71 // IO -DATA LOCATION RW_000:H_1_80 // IO +DATA LOCATION RW_000:H_0_80 // IO DATA LOCATION SIZE_0_:G_1_70 // IO -DATA LOCATION SIZE_1_:H_0_79 // IO -DATA LOCATION SM_AMIGA_0_:A_1 // NOD -DATA LOCATION SM_AMIGA_1_:H_7 // NOD -DATA LOCATION SM_AMIGA_2_:G_5 // NOD -DATA LOCATION SM_AMIGA_3_:G_6 // NOD -DATA LOCATION SM_AMIGA_4_:D_9 // NOD -DATA LOCATION SM_AMIGA_5_:B_8 // NOD -DATA LOCATION SM_AMIGA_6_:B_9 // NOD -DATA LOCATION SM_AMIGA_7_:B_5 // NOD +DATA LOCATION SIZE_1_:H_1_79 // IO +DATA LOCATION SM_AMIGA_0_:H_9 // NOD +DATA LOCATION SM_AMIGA_1_:B_3 // NOD +DATA LOCATION SM_AMIGA_2_:A_1 // NOD +DATA LOCATION SM_AMIGA_3_:A_4 // NOD +DATA LOCATION SM_AMIGA_4_:A_5 // NOD +DATA LOCATION SM_AMIGA_5_:D_11 // NOD +DATA LOCATION SM_AMIGA_6_:G_6 // NOD +DATA LOCATION SM_AMIGA_7_:H_5 // NOD DATA LOCATION UDS_000:D_6_32 // IO {RN_UDS_000} DATA LOCATION VMA:D_1_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP -DATA LOCATION cpu_est_0_:C_2 // NOD -DATA LOCATION cpu_est_1_:B_3 // NOD -DATA LOCATION cpu_est_2_:G_4 // NOD -DATA LOCATION inst_AS_030_000_SYNC:C_3 // NOD -DATA LOCATION inst_BGACK_030_INT_D:D_10 // NOD -DATA LOCATION inst_CLK_000_D0:D_5 // NOD -DATA LOCATION inst_CLK_000_D1:D_7 // NOD -DATA LOCATION inst_CLK_000_D2:H_3 // NOD -DATA LOCATION inst_CLK_000_D3:C_4 // NOD -DATA LOCATION inst_CLK_030_H:H_5 // NOD +DATA LOCATION cpu_est_0_:D_10 // NOD +DATA LOCATION cpu_est_1_:D_7 // NOD +DATA LOCATION cpu_est_2_:D_9 // NOD +DATA LOCATION inst_AS_030_000_SYNC:H_7 // NOD +DATA LOCATION inst_BGACK_030_INT_D:B_9 // NOD +DATA LOCATION inst_CLK_000_D0:H_3 // NOD +DATA LOCATION inst_CLK_000_D1:D_5 // NOD +DATA LOCATION inst_CLK_000_D2:H_10 // NOD +DATA LOCATION inst_CLK_030_H:B_5 // NOD DATA LOCATION inst_CLK_OUT_PRE_25:B_7 // NOD -DATA LOCATION inst_CLK_OUT_PRE_50:H_9 // NOD +DATA LOCATION inst_CLK_OUT_PRE_50:H_11 // NOD DATA LOCATION inst_CLK_OUT_PRE_50_D:H_12 // NOD -DATA LOCATION inst_DTACK_D0:H_11 // NOD -DATA LOCATION inst_RW_000_INT:A_3 // NOD -DATA LOCATION inst_VPA_D:H_10 // NOD +DATA LOCATION inst_DTACK_D0:B_8 // NOD +DATA LOCATION inst_RW_000_INT:G_5 // NOD +DATA LOCATION inst_VPA_D:A_3 // NOD +DATA LOCATION inst_avec_expreg:G_4 // NOD DATA LOCATION nEXP_SPACE:*_*_14 // INP DATA IO_DIR A0:BI DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT @@ -161,16 +160,6 @@ DATA IO_DIR VMA:OUT DATA IO_DIR VPA:IN DATA IO_DIR nEXP_SPACE:IN DATA GLB_CLOCK CLK_OSZI -DATA PW_LEVEL A_26_:0 -DATA SLEW A_26_:1 -DATA PW_LEVEL A_25_:0 -DATA SLEW A_25_:1 -DATA PW_LEVEL A_24_:0 -DATA SLEW A_24_:1 -DATA PW_LEVEL A_23_:0 -DATA SLEW A_23_:1 -DATA PW_LEVEL A_31_:0 -DATA SLEW A_31_:1 DATA PW_LEVEL A_22_:0 DATA SLEW A_22_:1 DATA PW_LEVEL A_21_:0 @@ -179,24 +168,26 @@ DATA PW_LEVEL A_20_:0 DATA SLEW A_20_:1 DATA PW_LEVEL A_19_:0 DATA SLEW A_19_:1 -DATA PW_LEVEL IPL_2_:0 -DATA SLEW IPL_2_:1 +DATA PW_LEVEL A_31_:0 +DATA SLEW A_31_:1 DATA PW_LEVEL A_18_:0 DATA SLEW A_18_:1 DATA PW_LEVEL A_17_:0 DATA SLEW A_17_:1 -DATA PW_LEVEL FC_1_:0 -DATA SLEW FC_1_:1 DATA PW_LEVEL A_16_:0 DATA SLEW A_16_:1 -DATA PW_LEVEL RW_000:0 -DATA SLEW RW_000:1 +DATA PW_LEVEL IPL_2_:0 +DATA SLEW IPL_2_:1 DATA PW_LEVEL IPL_1_:0 DATA SLEW IPL_1_:1 +DATA PW_LEVEL FC_1_:0 +DATA SLEW FC_1_:1 DATA PW_LEVEL IPL_0_:0 DATA SLEW IPL_0_:1 DATA PW_LEVEL FC_0_:0 DATA SLEW FC_0_:1 +DATA PW_LEVEL RW_000:0 +DATA SLEW RW_000:1 DATA SLEW nEXP_SPACE:1 DATA PW_LEVEL BERR:0 DATA SLEW BERR:1 @@ -235,18 +226,26 @@ DATA PW_LEVEL A_28_:0 DATA SLEW A_28_:1 DATA PW_LEVEL A_27_:0 DATA SLEW A_27_:1 +DATA PW_LEVEL A_26_:0 +DATA SLEW A_26_:1 +DATA PW_LEVEL A_25_:0 +DATA SLEW A_25_:1 +DATA PW_LEVEL A_24_:0 +DATA SLEW A_24_:1 +DATA PW_LEVEL A_23_:0 +DATA SLEW A_23_:1 DATA PW_LEVEL SIZE_1_:0 DATA SLEW SIZE_1_:1 DATA PW_LEVEL IPL_030_2_:0 DATA SLEW IPL_030_2_:1 -DATA PW_LEVEL AS_030:0 -DATA SLEW AS_030:1 DATA PW_LEVEL IPL_030_1_:0 DATA SLEW IPL_030_1_:1 -DATA PW_LEVEL AS_000:0 -DATA SLEW AS_000:1 DATA PW_LEVEL IPL_030_0_:0 DATA SLEW IPL_030_0_:1 +DATA PW_LEVEL AS_030:0 +DATA SLEW AS_030:1 +DATA PW_LEVEL AS_000:0 +DATA SLEW AS_000:1 DATA PW_LEVEL DS_030:0 DATA SLEW DS_030:1 DATA PW_LEVEL UDS_000:0 @@ -273,6 +272,8 @@ DATA PW_LEVEL RESET:0 DATA SLEW RESET:1 DATA PW_LEVEL SIZE_0_:0 DATA SLEW SIZE_0_:1 +DATA PW_LEVEL inst_avec_expreg:0 +DATA SLEW inst_avec_expreg:1 DATA PW_LEVEL inst_AS_030_000_SYNC:0 DATA SLEW inst_AS_030_000_SYNC:1 DATA PW_LEVEL inst_BGACK_030_INT_D:0 @@ -285,36 +286,34 @@ DATA PW_LEVEL inst_CLK_000_D0:0 DATA SLEW inst_CLK_000_D0:1 DATA PW_LEVEL inst_CLK_000_D1:0 DATA SLEW inst_CLK_000_D1:1 -DATA PW_LEVEL inst_CLK_000_D2:0 -DATA SLEW inst_CLK_000_D2:1 DATA PW_LEVEL inst_DTACK_D0:0 DATA SLEW inst_DTACK_D0:1 DATA PW_LEVEL inst_CLK_OUT_PRE_50:0 DATA SLEW inst_CLK_OUT_PRE_50:1 DATA PW_LEVEL inst_CLK_OUT_PRE_25:0 DATA SLEW inst_CLK_OUT_PRE_25:1 -DATA PW_LEVEL SM_AMIGA_7_:0 -DATA SLEW SM_AMIGA_7_:1 +DATA PW_LEVEL SM_AMIGA_1_:0 +DATA SLEW SM_AMIGA_1_:1 DATA PW_LEVEL SM_AMIGA_6_:0 DATA SLEW SM_AMIGA_6_:1 DATA PW_LEVEL SM_AMIGA_0_:0 DATA SLEW SM_AMIGA_0_:1 -DATA PW_LEVEL SM_AMIGA_5_:0 -DATA SLEW SM_AMIGA_5_:1 -DATA PW_LEVEL SM_AMIGA_2_:0 -DATA SLEW SM_AMIGA_2_:1 +DATA PW_LEVEL SM_AMIGA_7_:0 +DATA SLEW SM_AMIGA_7_:1 DATA PW_LEVEL inst_RW_000_INT:0 DATA SLEW inst_RW_000_INT:1 -DATA PW_LEVEL inst_CLK_000_D3:0 -DATA SLEW inst_CLK_000_D3:1 +DATA PW_LEVEL inst_CLK_000_D2:0 +DATA SLEW inst_CLK_000_D2:1 DATA PW_LEVEL inst_CLK_030_H:0 DATA SLEW inst_CLK_030_H:1 +DATA PW_LEVEL SM_AMIGA_5_:0 +DATA SLEW SM_AMIGA_5_:1 DATA PW_LEVEL SM_AMIGA_4_:0 DATA SLEW SM_AMIGA_4_:1 DATA PW_LEVEL SM_AMIGA_3_:0 DATA SLEW SM_AMIGA_3_:1 -DATA PW_LEVEL SM_AMIGA_1_:0 -DATA SLEW SM_AMIGA_1_:1 +DATA PW_LEVEL SM_AMIGA_2_:0 +DATA SLEW SM_AMIGA_2_:1 DATA PW_LEVEL cpu_est_0_:0 DATA SLEW cpu_est_0_:1 DATA PW_LEVEL cpu_est_1_:0 @@ -322,10 +321,10 @@ DATA SLEW cpu_est_1_:1 DATA PW_LEVEL cpu_est_2_:0 DATA SLEW cpu_est_2_:1 DATA PW_LEVEL RN_IPL_030_2_:0 -DATA PW_LEVEL RN_AS_030:0 DATA PW_LEVEL RN_IPL_030_1_:0 -DATA PW_LEVEL RN_AS_000:0 DATA PW_LEVEL RN_IPL_030_0_:0 +DATA PW_LEVEL RN_AS_030:0 +DATA PW_LEVEL RN_AS_000:0 DATA PW_LEVEL RN_DS_030:0 DATA PW_LEVEL RN_UDS_000:0 DATA PW_LEVEL RN_LDS_000:0 @@ -335,5 +334,4 @@ DATA PW_LEVEL RN_FPU_CS:0 DATA PW_LEVEL RN_DSACK1:0 DATA PW_LEVEL RN_E:0 DATA PW_LEVEL RN_VMA:0 -DATA PW_LEVEL RN_AVEC_EXP:0 END diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index 8af8540..aeb34c7 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,16 +1,17 @@ -GROUP MACH_SEG_A DS_030 RN_DS_030 inst_RW_000_INT SM_AMIGA_0_ AVEC +GROUP MACH_SEG_A DS_030 RN_DS_030 SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_4_ inst_VPA_D + AVEC GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ - RN_IPL_030_2_ CLK_EXP RESET SM_AMIGA_7_ SM_AMIGA_6_ cpu_est_1_ inst_CLK_OUT_PRE_25 - SM_AMIGA_5_ -GROUP MACH_SEG_C AVEC_EXP RN_AVEC_EXP inst_AS_030_000_SYNC cpu_est_0_ inst_CLK_000_D3 - AMIGA_BUS_ENABLE_LOW + RN_IPL_030_2_ CLK_EXP RESET inst_CLK_OUT_PRE_25 SM_AMIGA_1_ inst_DTACK_D0 + inst_BGACK_030_INT_D inst_CLK_030_H +GROUP MACH_SEG_C AVEC_EXP AMIGA_BUS_ENABLE_LOW GROUP MACH_SEG_D LDS_000 RN_LDS_000 UDS_000 RN_UDS_000 VMA RN_VMA BG_000 - RN_BG_000 AS_000 RN_AS_000 SM_AMIGA_4_ inst_CLK_000_D0 inst_BGACK_030_INT_D + RN_BG_000 AS_000 RN_AS_000 cpu_est_1_ cpu_est_2_ SM_AMIGA_5_ cpu_est_0_ inst_CLK_000_D1 DTACK AMIGA_BUS_ENABLE GROUP MACH_SEG_E CIIN AMIGA_BUS_DATA_DIR BERR -GROUP MACH_SEG_G E RN_E A0 SIZE_0_ CLK_DIV_OUT SM_AMIGA_2_ SM_AMIGA_3_ - cpu_est_2_ RW +GROUP MACH_SEG_G E RN_E A0 SIZE_0_ CLK_DIV_OUT inst_avec_expreg inst_RW_000_INT + SM_AMIGA_6_ RW GROUP MACH_SEG_H FPU_CS RN_FPU_CS AS_030 RN_AS_030 SIZE_1_ DSACK1 RN_DSACK1 - BGACK_030 RN_BGACK_030 SM_AMIGA_1_ inst_VPA_D inst_DTACK_D0 inst_CLK_OUT_PRE_50_D - inst_CLK_OUT_PRE_50 inst_CLK_000_D2 RW_000 inst_CLK_030_H \ No newline at end of file + BGACK_030 RN_BGACK_030 inst_AS_030_000_SYNC SM_AMIGA_7_ SM_AMIGA_0_ + inst_CLK_000_D0 inst_CLK_OUT_PRE_50_D inst_CLK_OUT_PRE_50 inst_CLK_000_D2 + RW_000 \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index 361b712..9f5ca81 100644 Binary files a/Logic/68030_tk.ipr and b/Logic/68030_tk.ipr differ diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index dfc04e9..48a39c0 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Sun Jun 01 01:03:29 2014 +DATE: Sat Jun 07 23:03:24 2014 ABEL mach447a * @@ -31,80 +31,79 @@ NOTE Spread Placement? N * NOTE Run Time Upper Bound in 15 minutes 0 * NOTE Zero Hold Time For Input Registers? Y * NOTE Table of pin names and numbers* -NOTE PINS A_26_:17 A_25_:18 A_24_:19 A_23_:84 A_31_:4 A_22_:85* -NOTE PINS A_21_:94 A_20_:93 A_19_:97 IPL_2_:68 A_18_:95 A_17_:59* -NOTE PINS FC_1_:58 A_16_:96 RW_000:80 IPL_1_:56 IPL_0_:67* -NOTE PINS FC_0_:57 nEXP_SPACE:14 BERR:41 BG_030:21 BGACK_000:28* -NOTE PINS CLK_030:64 CLK_000:11 CLK_OSZI:61 CLK_DIV_OUT:65* -NOTE PINS DTACK:30 AVEC:92 AVEC_EXP:22 VPA:36 RST:86 RW:71* -NOTE PINS AMIGA_BUS_ENABLE:34 AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20* -NOTE PINS CIIN:47 A_30_:5 A_29_:6 A_28_:15 A_27_:16 SIZE_1_:79* -NOTE PINS IPL_030_2_:9 AS_030:82 IPL_030_1_:7 AS_000:33 IPL_030_0_:8* -NOTE PINS DS_030:98 UDS_000:32 LDS_000:31 A0:69 BG_000:29* -NOTE PINS BGACK_030:83 CLK_EXP:10 FPU_CS:78 DSACK1:81 E:66* -NOTE PINS VMA:35 RESET:3 SIZE_0_:70 * +NOTE PINS A_22_:85 A_21_:94 A_20_:93 A_19_:97 A_31_:4 A_18_:95* +NOTE PINS A_17_:59 A_16_:96 IPL_2_:68 IPL_1_:56 FC_1_:58* +NOTE PINS IPL_0_:67 FC_0_:57 RW_000:80 nEXP_SPACE:14 BERR:41* +NOTE PINS BG_030:21 BGACK_000:28 CLK_030:64 CLK_000:11 CLK_OSZI:61* +NOTE PINS CLK_DIV_OUT:65 DTACK:30 AVEC:92 AVEC_EXP:22 VPA:36* +NOTE PINS RST:86 RW:71 AMIGA_BUS_ENABLE:34 AMIGA_BUS_DATA_DIR:48* +NOTE PINS AMIGA_BUS_ENABLE_LOW:20 CIIN:47 A_30_:5 A_29_:6* +NOTE PINS A_28_:15 A_27_:16 A_26_:17 A_25_:18 A_24_:19 A_23_:84* +NOTE PINS SIZE_1_:79 IPL_030_2_:9 IPL_030_1_:7 IPL_030_0_:8* +NOTE PINS AS_030:82 AS_000:33 DS_030:98 UDS_000:32 LDS_000:31* +NOTE PINS A0:69 BG_000:29 BGACK_030:83 CLK_EXP:10 FPU_CS:78* +NOTE PINS DSACK1:81 E:66 VMA:35 RESET:3 SIZE_0_:70 * NOTE Table of node names and numbers* -NOTE NODES RN_RW_000:271 RN_DTACK:173 RN_AVEC_EXP:149 RN_RW:245 * -NOTE NODES RN_SIZE_1_:269 RN_IPL_030_2_:128 RN_AS_030:278 * -NOTE NODES RN_IPL_030_1_:134 RN_AS_000:179 RN_IPL_030_0_:131 * -NOTE NODES RN_DS_030:101 RN_UDS_000:182 RN_LDS_000:185 RN_A0:257 * -NOTE NODES RN_BG_000:176 RN_BGACK_030:275 RN_FPU_CS:272 * -NOTE NODES RN_DSACK1:281 RN_E:248 RN_VMA:175 RN_SIZE_0_:247 * -NOTE NODES inst_AS_030_000_SYNC:154 inst_BGACK_030_INT_D:188 * -NOTE NODES inst_VPA_D:284 inst_CLK_OUT_PRE_50_D:287 inst_CLK_000_D0:181 * -NOTE NODES inst_CLK_000_D1:184 inst_CLK_000_D2:274 inst_DTACK_D0:286 * -NOTE NODES inst_CLK_OUT_PRE_50:283 inst_CLK_OUT_PRE_25:136 * -NOTE NODES SM_AMIGA_7_:133 SM_AMIGA_6_:139 SM_AMIGA_0_:103 * -NOTE NODES SM_AMIGA_5_:137 SM_AMIGA_2_:253 inst_RW_000_INT:106 * -NOTE NODES inst_CLK_000_D3:155 inst_CLK_030_H:277 SM_AMIGA_4_:187 * -NOTE NODES SM_AMIGA_3_:254 SM_AMIGA_1_:280 cpu_est_0_:152 * -NOTE NODES cpu_est_1_:130 cpu_est_2_:251 * +NOTE NODES RN_RW_000:269 RN_DTACK:173 RN_RW:245 RN_SIZE_1_:271 * +NOTE NODES RN_IPL_030_2_:128 RN_IPL_030_1_:134 RN_IPL_030_0_:131 * +NOTE NODES RN_AS_030:278 RN_AS_000:179 RN_DS_030:101 RN_UDS_000:182 * +NOTE NODES RN_LDS_000:185 RN_A0:257 RN_BG_000:176 RN_BGACK_030:275 * +NOTE NODES RN_FPU_CS:272 RN_DSACK1:281 RN_E:248 RN_VMA:175 * +NOTE NODES RN_SIZE_0_:247 inst_avec_expreg:251 inst_AS_030_000_SYNC:280 * +NOTE NODES inst_BGACK_030_INT_D:139 inst_VPA_D:106 inst_CLK_OUT_PRE_50_D:287 * +NOTE NODES inst_CLK_000_D0:274 inst_CLK_000_D1:181 inst_DTACK_D0:137 * +NOTE NODES inst_CLK_OUT_PRE_50:286 inst_CLK_OUT_PRE_25:136 * +NOTE NODES SM_AMIGA_1_:130 SM_AMIGA_6_:254 SM_AMIGA_0_:283 * +NOTE NODES SM_AMIGA_7_:277 inst_RW_000_INT:253 inst_CLK_000_D2:284 * +NOTE NODES inst_CLK_030_H:133 SM_AMIGA_5_:190 SM_AMIGA_4_:109 * +NOTE NODES SM_AMIGA_3_:107 SM_AMIGA_2_:103 cpu_est_0_:188 * +NOTE NODES cpu_est_1_:184 cpu_est_2_:187 * NOTE BLOCK 0 * L000000 111111111011111111111111111111111111111111111111111111111111111111 - 111111111101011110111111111111111111111111111111111111111111111111 + 111111111101111111111111111111111111111111111111111111111111111111 + 111111111111111101111111111111111111111111111111111111110111111111 + 111111111111111111111111111111111111111111111110111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111011111111111111111111111111111111011111111011111111 - 111111111111111111111101011011111111111110101101110111111111111111 - 101111111111111111011111111111011111111111111111111111111111111111* + 111111011111111111111111111111111111111111111111111111111111111111 + 111111111111101111111111110111111111111111111111011111111111111111 + 110101111111110111111110011111111111111110101111110101111111111111 + 101111111111111111010111111111011101111111111111111111111111111111* L000594 000000000000000000000000000000000000000000000000000000000000000000* L000660 111111111111111111111111111111111111111101111111111111111111111111* -L000726 111111111111111111111111111111111111111111111101111111111111111111* +L000726 111111111111111111111111111111111111111111111111111101111111111111* L000792 111111111111111111111111011111111111111111111111011111111111111111* -L000858 111111111011111111111111110111111111111111011111111111111111111111* -L000924 111111111111111111111111111111111111111111011111111111110111111111* -L000990 111111111111111111011110111111111111111111111111111111111111111111* -L001056 111111111111110111111110111111111111111111111111111111111111111111* -L001122 000000000000000000000000000000000000000000000000000000000000000000* +L000858 111111111011111111111111111111111111111111011111111111110111111111* +L000924 111111111111011111111111111111111111111111011111111111111111111111* +L000990 110111111111110110111110111111111111111111111111110111111111111111* +L001056 111111111111111111011110111111111111111111111111111111111111111111* +L001122 110111111111110111111110111011111110111111111101111011111111111111* L001188 000000000000000000000000000000000000000000000000000000000000000000* L001254 000000000000000000000000000000000000000000000000000000000000000000* L001320 111111111111111111111111111111111111111111111111111111111111111111* L001386 111111111111111111111111111111111111111111111111111111111111111111* -L001452 111111110111111111111111111111011111111111111111111111111011111111* -L001518 111111111111111111111111111011011111111111111111111111111011111111* +L001452 111111110111101111111111111111011111111111111111111111111111111111* +L001518 111111111111101111111111111111011111111111111111111111111011111111* L001584 000000000000000000000000000000000000000000000000000000000000000000* L001650 000000000000000000000000000000000000000000000000000000000000000000* -L001716 111111110111111111111110111111111111111111111111111011111111111111* -L001782 111111111111111111111110111111111111111101111111111011111111111111* -L001848 111111110111101111101111111111111111111111111111111011111111111111* -L001914 111111111111101111101111111111111111111101111111111011111111111111* -L001980 111111111111111111111110111111111111111111111101111011111111111111* +L001716 111111111111111111110111111111111111111111111111111111111111111111* +L001782 000000000000000000000000000000000000000000000000000000000000000000* +L001848 000000000000000000000000000000000000000000000000000000000000000000* +L001914 000000000000000000000000000000000000000000000000000000000000000000* +L001980 000000000000000000000000000000000000000000000000000000000000000000* L002046 000000000000000000000000000000000000000000000000000000000000000000* -L002112 111111111111101111101111111111111111111111111101111011111111111111* -L002178 111111111011111111111111101111111111111110111110111111111011111111* -L002244 111111111111111111111110011111111111111111111111011011111111111111* -L002310 111111111111101111101111011111111111111111111111011011111111111111* -L002376 111111111011111111111111111111111111111110111110101111111011111111* -L002442 111111110111011110111101111111111111111111111111111111111111111111* -L002508 111111111111011110111101111111111111111101111111111111111111111111* -L002574 111111111111011110111101111111111111111111111101111111111111111111* -L002640 111111111111011110111101011111111111111111111111011111111111111111* +L002112 111111111111110110111110111111111111111111111111110111111111111111* +L002178 111011111111111111111110111111111111111111111111111111111111111111* +L002244 111010111111111111111111111111111111111111111111111111111111111111* +L002310 111111111111110111111110111011111110111111111101111011111111111111* +L002376 000000000000000000000000000000000000000000000000000000000000000000* +L002442 111111011111111111111110111111111111111111111111111111111111111111* +L002508 111101111111111111111110111111111111111111111111111111111111111111* +L002574 000000000000000000000000000000000000000000000000000000000000000000* +L002640 000000000000000000000000000000000000000000000000000000000000000000* L002706 000000000000000000000000000000000000000000000000000000000000000000* L002772 000000000000000000000000000000000000000000000000000000000000000000* @@ -173,33 +172,33 @@ L006534 0010* L006538 10100110011000* L006552 10100100011110* L006566 00001111110000* -L006580 11100110011111* -L006594 11111111110000* -L006608 11001011110010* -L006622 11110011110000* -L006636 11110111110011* -L006650 11110011110000* -L006664 11111011110010* -L006678 11110111110001* -L006692 11111111110011* -L006706 11110011110000* +L006580 00100110011111* +L006594 11100100010000* +L006608 10100100010010* +L006622 11011011110000* +L006636 11110011110011* +L006650 11111111110001* +L006664 11110011110011* +L006678 11111011110000* +L006692 11111111110010* +L006706 11110011110001* L006720 11111011110011* -L006734 11110111110101* +L006734 11110111110100* L006748 11111111110011* NOTE BLOCK 1 * L006762 + 111111111111111111111111111111111111111110111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111101011111111111111111111111111111111111111111111111111111 - 110101101011111111111111111111111101111111111111111111110111111111 - 111111111111111111110111010101111011111111100110111111011111111111 + 111101101011111111111111111111111111111111111111011111110111111111 + 111111111101111111110111111111111011111111111111111111011111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111101111111111111111111111111111111111 - 111111111111111101111110111111111111111111111111111111111111111111 - 111111111111110111111111111111111111101111111111111111111111111111 - 101111111111111111011111111111111111111111111111111111111111111111* + 111011111111111110111111111111111111111111111111111111111111111111 + 011111111111111111111111111101111111111111111111111111111111111111 + 111111111111110111111110011111111111111111111110111101111111101111 + 111111111111111111011111111111111111111111101111111111111111111111* L007356 111111111111111111111111111111111111111111111111111111111111111111* -L007422 110111111111111111111111111111111111111111111111111111111111111111* +L007422 111111111111111111111111111111111111111111111111011111111111111111* L007488 000000000000000000000000000000000000000000000000000000000000000000* L007554 000000000000000000000000000000000000000000000000000000000000000000* L007620 000000000000000000000000000000000000000000000000000000000000000000* @@ -211,52 +210,52 @@ L007950 000000000000000000000000000000000000000000000000000000000000000000* L008016 000000000000000000000000000000000000000000000000000000000000000000* L008082 111111111111111111111111111111111111111111111111111111111111111111* -L008148 111111110111110110111111111111111111111111111111111111111111111111* -L008214 111111111111111011110111111111111111111111111111111111111111111111* -L008280 111111111111111101110111111111111111111111111111111111111111111111* +L008148 111111110111111011111101111111111111111111111111111111111111111111* +L008214 111111111111111111110110111111111111111111111111111111111111111111* +L008280 111111111111110111110111111111111111111111111111111111111111111111* L008346 000000000000000000000000000000000000000000000000000000000000000000* L008412 000000000000000000000000000000000000000000000000000000000000000000* -L008478 111111111111110110111111111011111111111111101110111111111111111111* -L008544 111111111111110110111111111011111111111111011101111111111111111111* -L008610 111111111111110110111111111111111111111111100101111111111111111111* -L008676 111111111111110110111111111111111111111111010110111111111111111111* +L008478 111111111101111111111101111111111111111111111111111111111111111111* +L008544 111111111111111111011101111111111111111111111111111111111111111111* +L008610 000000000000000000000000000000000000000000000000000000000000000000* +L008676 000000000000000000000000000000000000000000000000000000000000000000* L008742 000000000000000000000000000000000000000000000000000000000000000000* L008808 111111111111111111111111111111111111111111111111111111111111111111* -L008874 111111111111110110111111111111110111111111111111111111111111111111* -L008940 111111111111111011111111111111111111111111111111111111011111111111* -L009006 111111111111111101111111111111111111111111111111111111011111111111* +L008874 111111111111111011111101111111110111111111111111111111111111111111* +L008940 111111111111111111111110111111111111111111111111111111011111111111* +L009006 111111111111110111111111111111111111111111111111111111011111111111* L009072 000000000000000000000000000000000000000000000000000000000000000000* L009138 000000000000000000000000000000000000000000000000000000000000000000* -L009204 111111111111111011111111111111111111111111111111111111111011111111* -L009270 111111111111111111101111111111111111111111111111111111111011111111* -L009336 111111111101111011111111101101111111101111111111111111111111111111* -L009402 111111111101111111101111101101111111101111111111111111111111111111* -L009468 000000000000000000000000000000000000000000000000000000000000000000* +L009204 111111111111111111111111111111111111111111101111111111110111111111* +L009270 111111111111111111111111101111111111111101011110111110111111101111* +L009336 111111111111111111111111101111111111111111111110111110110111111111* +L009402 101111111111111111111111111111111111111101011110111110111111101111* +L009468 101111111111111111111111111111111111111111111110111110110111111111* L009534 111111111111111111111111111111111111111111111111111111111111111111* -L009600 111111011111110110111111111111111111111111111111111111111111111111* -L009666 111101111111111011111111111111111111111111111111111111111111111111* -L009732 111101111111111101111111111111111111111111111111111111111111111111* +L009600 111111011111111011111101111111111111111111111111111111111111111111* +L009666 111101111111111111111110111111111111111111111111111111111111111111* +L009732 111101111111110111111111111111111111111111111111111111111111111111* L009798 000000000000000000000000000000000000000000000000000000000000000000* L009864 000000000000000000000000000000000000000000000000000000000000000000* -L009930 110111111111111111111111111111011111111111111111111111111111111111* -L009996 110111111111111111111110111111111111111111111111111111111111111111* -L010062 111011111111111111111101111111101111111111111111111111111111111111* +L009930 111111111111111101111111111111111111111111111111011111111111111111* +L009996 111011111111111111111111111111111111111111111111011111111111111111* +L010062 110111111111111110111111111111111111111111111111101111111111111111* L010128 000000000000000000000000000000000000000000000000000000000000000000* L010194 000000000000000000000000000000000000000000000000000000000000000000* L010260 000000000000000000000000000000000000000000000000000000000000000000* -L010326 111111111111010111111111111111111111111111111111111111111111111111* -L010392 111111111111110111111111111111111101111111111111111111111111111111* +L010326 111111111111111111111111111101111111111111111111111111111111111111* +L010392 000000000000000000000000000000000000000000000000000000000000000000* L010458 000000000000000000000000000000000000000000000000000000000000000000* L010524 000000000000000000000000000000000000000000000000000000000000000000* L010590 000000000000000000000000000000000000000000000000000000000000000000* -L010656 111111111111011011111111111111111111111111111111111111111011111111* -L010722 111111111101111111111111101101111111101111111111111111110111111111* -L010788 000000000000000000000000000000000000000000000000000000000000000000* -L010854 000000000000000000000000000000000000000000000000000000000000000000* -L010920 000000000000000000000000000000000000000000000000000000000000000000* +L010656 111111111111111111111111111111111111111111111101111111111111111111* +L010722 111111111111111111111111111111111111111111111111111111111111111111* +L010788 111111111111111111111111111111111111111111111111111111111111111111* +L010854 111111111111111111111111111111111111111111111111111111111111111111* +L010920 111111111111111111111111111111111111111111111111111111111111111111* L010986 000000000000000000000000000000000000000000000000000000000000000000* L011052 111111111111111111111111111111111111111111111111111111111111111111* @@ -295,18 +294,18 @@ L013032 111111111111111111111111111111111111111111111111111111111111111111* L013098 111111111111111111111111111111111111111111111111111111111111111111* L013164 000000000000000000000000000000000000000000000000000000000000000000 - 101111111111111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111111111111111111101111111111111111111111* L013296 0010* L013300 00100100010000* L013314 00100100011110* L013328 10100110010000* -L013342 10100101011111* +L013342 10100100011111* L013356 10100110010001* -L013370 11100110011111* +L013370 10100110011111* L013384 10100110010000* L013398 10100100011110* -L013412 10100100010000* -L013426 10100100010011* +L013412 00100110010000* +L013426 00010110010011* L013440 11011111110001* L013454 11110011110011* L013468 11111011110000* @@ -315,46 +314,46 @@ L013496 11110011111100* L013510 11111011111111* NOTE BLOCK 2 * L013524 - 111111111111111111111111111111111111111110111111111111111111111111 - 111111111101111111111111111111111111111111111111111111111111111111 - 111111111111101111111111111111111111111111111111111111110111111111 - 111011100111111110111111111101111111111111110111111111111111111111 - 111111111111111111011111111111111111111111111111111111111111111111 - 111101111111111111111111011111111111011111111111111111111111111111 - 111111111111111111111101110111111101111111111111111111111111111111 - 111111111111110111111011111111111111111011111110111111111111111111 - 101111111111111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111110111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111* L014118 000000000000000000000000000000000000000000000000000000000000000000* -L014184 111111111111111111111111111111111111111111111110111111111111111111* -L014250 111101111111111111101111111111111111111111111111111111111011111111* -L014316 111101111001111111111011111101111111111111111111111111110111111111* +L014184 111101111111111111111111111111111111111111111111111111111111111111* +L014250 000000000000000000000000000000000000000000000000000000000000000000* +L014316 000000000000000000000000000000000000000000000000000000000000000000* L014382 000000000000000000000000000000000000000000000000000000000000000000* L014448 000000000000000000000000000000000000000000000000000000000000000000* L014514 111111111111111111111111111111111111111111111111111111111111111111* -L014580 000000000000000000000000000000000000000000000000000000000000000000* -L014646 000000000000000000000000000000000000000000000000000000000000000000* -L014712 000000000000000000000000000000000000000000000000000000000000000000* -L014778 000000000000000000000000000000000000000000000000000000000000000000* +L014580 111111111111111111111111111111111111111111111111111111111111111111* +L014646 111111111111111111111111111111111111111111111111111111111111111111* +L014712 111111111111111111111111111111111111111111111111111111111111111111* +L014778 111111111111111111111111111111111111111111111111111111111111111111* L014844 000000000000000000000000000000000000000000000000000000000000000000* -L014910 111111111111111011111111111111111111111111110111111111111111111111* -L014976 111111111111111111111111110111111111111111110111111111111111111111* -L015042 111111111111110111111111111011111111111111111011111111111111111111* -L015108 000000000000000000000000000000000000000000000000000000000000000000* -L015174 000000000000000000000000000000000000000000000000000000000000000000* -L015240 111111011111110111111111111111111111111111111111111111111111111111* -L015306 111111110110111111111111111111111111111111111111111111111111111111* -L015372 111111110111111111111111111111111111111110111111111111111111111111* -L015438 110111110111011101111110101111111110011111111111111111111111111111* -L015504 111111110111111111111111111111111111111111111110111111111111111111* +L014910 111111111111111111111111111111111111111111111111111111111111111111* +L014976 111111111111111111111111111111111111111111111111111111111111111111* +L015042 111111111111111111111111111111111111111111111111111111111111111111* +L015108 111111111111111111111111111111111111111111111111111111111111111111* +L015174 111111111111111111111111111111111111111111111111111111111111111111* +L015240 111111111111111111111111111111111111111111111111111111111111111111* +L015306 111111111111111111111111111111111111111111111111111111111111111111* +L015372 111111111111111111111111111111111111111111111111111111111111111111* +L015438 111111111111111111111111111111111111111111111111111111111111111111* +L015504 111111111111111111111111111111111111111111111111111111111111111111* L015570 000000000000000000000000000000000000000000000000000000000000000000* -L015636 111111111111111111110111111111111111111111111111111111111111111111* -L015702 111111110111111111111111111111111111111111111111111111111011111111* -L015768 111111111110111111111011111101111111111111111111111111110111111111* -L015834 111111111111111111111111111111111111110111111111111111111111111111* -L015900 000000000000000000000000000000000000000000000000000000000000000000* +L015636 111111111111111111111111111111111111111111111111111111111111111111* +L015702 111111111111111111111111111111111111111111111111111111111111111111* +L015768 111111111111111111111111111111111111111111111111111111111111111111* +L015834 111111111111111111111111111111111111111111111111111111111111111111* +L015900 111111111111111111111111111111111111111111111111111111111111111111* L015966 111111111111111111111111111111111111111111111111111111111111111111* L016032 111111111111111111111111111111111111111111111111111111111111111111* L016098 111111111111111111111111111111111111111111111111111111111111111111* @@ -422,35 +421,35 @@ L019794 111111111111111111111111111111111111111111111111111111111111111111* L019860 111111111111111111111111111111111111111111111111111111111111111111* L019926 000000000000000000000000000000000000000000000000000000000000000000 - 101111111111111111111111111111111111111111111111111111111111111111* -L020058 0010* -L020062 11100110011100* -L020076 00101011110010* -L020090 10100100010001* -L020104 10100110010011* -L020118 00110110010000* -L020132 11010011110010* -L020146 11111111110000* -L020160 11111011110011* -L020174 11110011110001* + 000000000000000000000000000000000000000000000000000000000000000000* +L020058 0000* +L020062 00100011111100* +L020076 00010111110011* +L020090 11010011110001* +L020104 11110111110011* +L020118 11110011110000* +L020132 11110111110011* +L020146 11110011110001* +L020160 11110111110011* +L020174 11110011110000* L020188 11111011110011* -L020202 11110111111110* +L020202 11110111111111* L020216 11111111111111* L020230 11110011110000* -L020244 11111011110010* +L020244 11111011110011* L020258 11110111110101* L020272 11111111111111* NOTE BLOCK 3 * L020286 - 111111011111111111111111111111111111111111111111111111111111111111 - 111111110111111111111111111110011111111111111111111011111111111111 - 101111111111111101111111111111111111111111111111111111111111110111 - 111110111111111111111111110111111111111111110110111111111111111111 - 111111111101111111011111111111111111111111111111111111111111111111 - 111111111111101111111111111111111111101111111111111111111111111111 - 111111111111111111111111011111110111111111111111111111111111111110 - 111111111111111011110110111111111111111010111111011111111111011111 - 111111111111111111111111111111111101111111101111111111110111111111* + 111111111111111111111111111111111111111111111111011111111111111111 + 111111111111111110111111111111011110111111110111111111111111111111 + 111111111111111111111111111111111111101111111110111111111111111111 + 111110111111111111111111111111111111111111111111111111111111111011 + 111111111101111111111111111111111111111111111111111111111111111111 + 111111111111101111111111111111111111110101111111111111111111111111 + 111111111111111111111111010111110111111111111111111111111111111110 + 101111111011111011101001111101111111111111111111110111111111011111 + 111111011111111111111111111111111111111111101111111111011111111111* L020880 111111111111111111111111111111111111111111111111111111111111111111* L020946 111111111111111111111111111111111111111111111111111111111111111101* @@ -458,83 +457,83 @@ L021012 000000000000000000000000000000000000000000000000000000000000000000* L021078 000000000000000000000000000000000000000000000000000000000000000000* L021144 000000000000000000000000000000000000000000000000000000000000000000* L021210 000000000000000000000000000000000000000000000000000000000000000000* -L021276 111111111111111111111111111011111101101111110111101111111111111111* -L021342 111111111111111111111111111111111101111111111111111111111111111111* -L021408 111101111111111111110111110111111110111111111010011111111111111111* +L021276 111111111111111111111011111011111111111101111111111011011111111111* +L021342 111111111111111111111111111111111111111111111111111111011111111111* +L021408 111111111111111111110111010101111111111110111111111111101111111011* L021474 000000000000000000000000000000000000000000000000000000000000000000* L021540 000000000000000000000000000000000000000000000000000000000000000000* L021606 111111111111111111111111111111111111111111111111111111111111111111* -L021672 111111111011111111111111111111111111111111111111111111111011111111* -L021738 111111011011111111111111111111011111110111111111111111111111110111* +L021672 111111101111111111111111111111111111111111111011111111111111111111* +L021738 111111110111111111011111111111011111111111111011011111111111111111* L021804 000000000000000000000000000000000000000000000000000000000000000000* L021870 000000000000000000000000000000000000000000000000000000000000000000* L021936 000000000000000000000000000000000000000000000000000000000000000000* -L022002 111111111111111111011111111111111111111111111111111111111111111111* +L022002 111101111111111111111111111111111111111111111111111111111111111111* L022068 000000000000000000000000000000000000000000000000000000000000000000* L022134 000000000000000000000000000000000000000000000000000000000000000000* L022200 000000000000000000000000000000000000000000000000000000000000000000* L022266 000000000000000000000000000000000000000000000000000000000000000000* L022332 - 111111111111111111111111111111111111111101111111111111111111111111* -L022398 111111111111111101111101111111111111111111111111111111111111111111* -L022464 111111111111111111111011111111111111111011111111111111111111111111* + 011111111111111111111111111111111111111111111111111111111111111111* +L022398 111111111111111111110111111111111111111111111101111111111111111111* +L022464 111111111111111111101111111110111111111111111111111111111111111111* L022530 000000000000000000000000000000000000000000000000000000000000000000* L022596 000000000000000000000000000000000000000000000000000000000000000000* L022662 000000000000000000000000000000000000000000000000000000000000000000* -L022728 111111011111111111111111111111111111111111111111111111111111111111* -L022794 111111111101111111111111111111111111111011111111111111111111101111* -L022860 111111111111111111111110111111111111111011111111110111111111101111* -L022926 111111111111111110111111111111111111111011111111110111111111101111* -L022992 101111111110111101111101111111111111111111111111110111111111111111* +L022728 111111111111111111110111111111111111111111111111111111111111111111* +L022794 111111111101111111101111111111111111111111111111111111111111101111* +L022860 111111111111111101101011111111111111111111111111111111111111101111* +L022926 111111111111111101101111111111111111111111111110111111111111101111* +L022992 111111111110111101110111111111111111101111111101111111111111111111* L023058 - 111111111111111111111111111111111111111101111111111111111111111111* -L023124 111111111111111111111111111111111111111011111111101011111111101111* -L023190 111111111111111111111111101111111111111011111111111011111111101111* -L023256 101111111110111111111111011111111111111111111111011011111111111111* + 011111111111111111111111111111111111111111111111111111111111111111* +L023124 111111111111111110100111111111111111111111111111111111111111101111* +L023190 111111111111111110101111111111111111111011111111111111111111101111* +L023256 111111111110111110111011111111111111100111111111111111111111111111* L023322 000000000000000000000000000000000000000000000000000000000000000000* L023388 000000000000000000000000000000000000000000000000000000000000000000* -L023454 111111111111111111111111111111111111111111111111011111111111111111* -L023520 111111111101111111111111111111111011111011111111111111111111111111* -L023586 111111111111111111111110111111111011111011111111110111111111111111* -L023652 111111111111111110111111111111111011111011111111110111111111111111* -L023718 111111111110111101111101111110111111111111111111110111111111111111* +L023454 111111111111111111101011111111111011111011111111111111111111111111* +L023520 111111111101111111101111111111111011111111111111111111111111111111* +L023586 111111111111111101101011111111111011111111111111111111111111111111* +L023652 111111111111111101101111111111111011111111111110111111111111111111* +L023718 111111111110111101110111111111111110111111111101111111111111111111* L023784 - 111111111111111111111111111111111111111101111111111111111111111111* -L023850 111111111110011101111101111111111111111111111111110111111111111111* -L023916 011111111110111101111101111111111111111111111111110111111111111111* -L023982 111111111111111111111111111111111011111011111111101011111111111111* -L024048 111111111111111111111111101111111011111011111111111011111111111111* -L024114 111111111110111111111111011110111111111111111111011011111111111111* -L024180 111111111111111101111111111111111111111111111111101111111111111111* -L024246 111111111111111111111111011111111111111111111111101111111111111111* -L024312 000000000000000000000000000000000000000000000000000000000000000000* -L024378 000000000000000000000000000000000000000000000000000000000000000000* -L024444 000000000000000000000000000000000000000000000000000000000000000000* + 011111111111111111111111111111111111111111111111111111111111111111* +L023850 111111111110011101110111111111111111111111111101111111111111111111* +L023916 111111111110111101110111111111111111011111111101111111111111111111* +L023982 111111111111111110100111111111111011111111111111111111111111111111* +L024048 111111111110111110111011111111111110110111111111111111111111111111* +L024114 111111111110011110111011111111111111110111111111111111111111111111* +L024180 111111111111111111111111011111111111111111111111111111111111111111* +L024246 111111111111111111110110101011111111111111111111111111111111111011* +L024312 111111111111111111110110011011111111111111111111111111111111110111* +L024378 111111111111111111110110101111111111111101111111111111111111110111* +L024444 111111111111111111110110011111111111111101111111111111111111111011* L024510 - 111111111111111011111111111111101111111110111111111111111111111111* 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-L044136 111111111111111101111111111111111111111110111111111110101111111111* -L044202 111111111111111111111111111111111111111111111111111111111111111111* -L044268 111111111111111111111111111111111111111111111111111111111111111111* -L044334 111111111111111111111111111111111111111111111111111111111111111111* -L044400 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111111101111111110111111111111111111101111* +L044136 101111111111111111111111011111111111111110111111111110111111111111* +L044202 111111111111111111111011111111111111111111111101111111101111111111* +L044268 111111111111111111111111111111011111011111111111101111011110111111* +L044334 000000000000000000000000000000000000000000000000000000000000000000* +L044400 000000000000000000000000000000000000000000000000000000000000000000* L044466 111111111111111111111111111111111111111111111111111111111111111111* L044532 111111111111111111111111111111111111111111111111111111111111111111* L044598 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000000000000000000000000000000000000000000000000000000000000000000* L047106 0010* L047110 00100011111100* L047124 01100100011111* L047138 00100110010001* -L047152 00100110011111* -L047166 00100110010000* -L047180 10100110010010* -L047194 11100110010000* -L047208 11101111110011* -L047222 00110100010001* +L047152 00010110011111* +L047166 11100100010000* +L047180 11100100010010* +L047194 10110110010000* +L047208 11001111110011* +L047222 00000100010001* L047236 11001011110011* L047250 11111111111110* L047264 11110011110010* @@ -950,90 +949,90 @@ L047306 11110011110000* L047320 11111011111110* NOTE BLOCK 7 * L047334 - 111111111111111111111111111111111111111110111111111111111111111111 + 111111011111111111111111111111111111111111111111111111111011111111 111111111111111111111111111111011111111111111111111111111111111111 111111111111111111111111111111111110111111111111111111111111111111 - 111011111111111111111111111111111111111111111011111111101111111111 + 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L049314 000000000000000000000000000000000000000000000000000000000000000000* L049380 111111111111111111111111111111111111111111111111111111111111111111* -L049446 111111111111111111111111111111111111011111111101111111111111111111* -L049512 111111111111111110111111111111111111011111111111011111111111111111* -L049578 000000000000000000000000000000000000000000000000000000000000000000* -L049644 000000000000000000000000000000000000000000000000000000000000000000* +L049446 111111111111111111111011111111111111111111111111111111101111111111* +L049512 111111111110111111111111111111111111111111111111111111101111111111* +L049578 111111111111111111111011111111011111011110111111101111111111111111* +L049644 111111111110111111111111111111011111011110111111101111111111111111* L049710 000000000000000000000000000000000000000000000000000000000000000000* -L049776 111111111111111111111111110111111111111111101111111111111111111111* -L049842 111111111111111111111111101111111111111101011110111110111111101111* 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111111111111111111111011111111111111110111111111111111111111111111* +L051294 111111111101111111111011111111111111111111111111111111111111111111* L051360 000000000000000000000000000000000000000000000000000000000000000000* L051426 000000000000000000000000000000000000000000000000000000000000000000* L051492 000000000000000000000000000000000000000000000000000000000000000000* L051558 111111111111111111111111111111111111111111111101111111111111111111* -L051624 111111111111111111110111111111111111111111111111111111111111111111* +L051624 111111111111111111111111111111111111111111111111011111111111111111* L051690 000000000000000000000000000000000000000000000000000000000000000000* L051756 000000000000000000000000000000000000000000000000000000000000000000* L051822 000000000000000000000000000000000000000000000000000000000000000000* L051888 000000000000000000000000000000000000000000000000000000000000000000* -L051954 111111111111111111011111111111111111111111111111111111111111111111* +L051954 111111111111111111111111111111111111111111111011111111111111111111* L052020 000000000000000000000000000000000000000000000000000000000000000000* L052086 000000000000000000000000000000000000000000000000000000000000000000* L052152 000000000000000000000000000000000000000000000000000000000000000000* L052218 000000000000000000000000000000000000000000000000000000000000000000* L052284 - 111111111111111111111111111111101111111111111110111111111111101111* -L052350 111111111101111111111111111111111111111111111111111111111111111111* + 111111111111111011111111111111101111111111111110111111111111111111* +L052350 111111111111111111111111111111111111111111110111111111111111111111* L052416 111111111111111111111111111111111111111111111111111111111111111111* L052482 111111111111111111111111111111111111111111111111111111111111111111* L052548 111111111111111111111111111111111111111111111111111111111111111111* @@ -1059,19 +1058,19 @@ L053736 000000000000000000000000000000000000000000000000000000000000000000 111111111111111111111111111111111111111111101111111111111111111111* L053868 0010* -L053872 11100110011010* -L053886 00101011110010* +L053872 00100011111010* +L053886 11100110010011* L053900 11100110011001* -L053914 00100110010011* -L053928 10100110010000* -L053942 10100110011110* -L053956 10100110010000* -L053970 10100100010011* -L053984 11100110010001* -L053998 00100100010011* -L054012 00100110011110* -L054026 00100110010010* -L054040 00010100010010* +L053914 00010110010011* +L053928 10010110010000* +L053942 11010110011110* +L053956 10010110010000* +L053970 10100110010011* +L053984 10100110010001* +L053998 10100100010011* +L054012 00100110010110* +L054026 00100100010010* +L054040 00010100011010* L054054 11010011110011* L054068 11111011110011* L054082 11111111111111* @@ -1094,6 +1093,6 @@ E1 10000010 1 * -C527D* +C5EEA* U00000000000000000000000000000000* -E1E7 +DC8D diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index 2b7a354..f6f21df 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; -DATE = 6/1/14; -TIME = 01:03:29; +DATE = 6/7/14; +TIME = 23:03:24; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -76,24 +76,20 @@ Usercode_Format = Hex; [LOCATION ASSIGNMENTS] Layer = OFF; -A_26_ = pin,17,-,C,-; -A_25_ = pin,18,-,C,-; -A_24_ = pin,19,-,C,-; -A_23_ = pin,84,-,H,-; -A_31_ = pin,4,-,B,-; A_22_ = pin,85,-,H,-; A_21_ = pin,94,-,A,-; A_20_ = pin,93,-,A,-; A_19_ = pin,97,-,A,-; -IPL_2_ = pin,68,-,G,-; +A_31_ = pin,4,-,B,-; A_18_ = pin,95,-,A,-; A_17_ = pin,59,-,F,-; -FC_1_ = pin,58,-,F,-; A_16_ = pin,96,-,A,-; -RW_000 = pin,80,-,H,-; +IPL_2_ = pin,68,-,G,-; IPL_1_ = pin,56,-,F,-; +FC_1_ = pin,58,-,F,-; IPL_0_ = pin,67,-,G,-; FC_0_ = pin,57,-,F,-; +RW_000 = pin,80,-,H,-; nEXP_SPACE = pin,14,-,-,-; BERR = pin,41,-,E,-; BG_030 = pin,21,-,C,-; @@ -116,12 +112,16 @@ A_30_ = pin,5,-,B,-; A_29_ = pin,6,-,B,-; A_28_ = pin,15,-,C,-; A_27_ = pin,16,-,C,-; +A_26_ = pin,17,-,C,-; +A_25_ = pin,18,-,C,-; +A_24_ = pin,19,-,C,-; +A_23_ = pin,84,-,H,-; SIZE_1_ = pin,79,-,H,-; IPL_030_2_ = pin,9,-,B,-; -AS_030 = pin,82,-,H,-; IPL_030_1_ = pin,7,-,B,-; -AS_000 = pin,33,-,D,-; IPL_030_0_ = pin,8,-,B,-; +AS_030 = pin,82,-,H,-; +AS_000 = pin,33,-,D,-; DS_030 = pin,98,-,A,-; UDS_000 = pin,32,-,D,-; LDS_000 = pin,31,-,D,-; @@ -135,30 +135,30 @@ E = pin,66,-,G,-; VMA = pin,35,-,D,-; RESET = pin,3,-,B,-; SIZE_0_ = pin,70,-,G,-; -inst_AS_030_000_SYNC = node,-,-,C,3; -inst_BGACK_030_INT_D = node,-,-,D,10; -inst_VPA_D = node,-,-,H,10; +inst_avec_expreg = node,-,-,G,4; +inst_AS_030_000_SYNC = node,-,-,H,7; +inst_BGACK_030_INT_D = node,-,-,B,9; +inst_VPA_D = node,-,-,A,3; inst_CLK_OUT_PRE_50_D = node,-,-,H,12; -inst_CLK_000_D0 = node,-,-,D,5; -inst_CLK_000_D1 = node,-,-,D,7; -inst_CLK_000_D2 = node,-,-,H,3; -inst_DTACK_D0 = node,-,-,H,11; -inst_CLK_OUT_PRE_50 = node,-,-,H,9; +inst_CLK_000_D0 = node,-,-,H,3; +inst_CLK_000_D1 = node,-,-,D,5; +inst_DTACK_D0 = node,-,-,B,8; +inst_CLK_OUT_PRE_50 = node,-,-,H,11; inst_CLK_OUT_PRE_25 = node,-,-,B,7; -SM_AMIGA_7_ = node,-,-,B,5; -SM_AMIGA_6_ = node,-,-,B,9; -SM_AMIGA_0_ = node,-,-,A,1; -SM_AMIGA_5_ = node,-,-,B,8; -SM_AMIGA_2_ = node,-,-,G,5; -inst_RW_000_INT = node,-,-,A,3; -inst_CLK_000_D3 = node,-,-,C,4; -inst_CLK_030_H = node,-,-,H,5; -SM_AMIGA_4_ = node,-,-,D,9; -SM_AMIGA_3_ = node,-,-,G,6; -SM_AMIGA_1_ = node,-,-,H,7; -cpu_est_0_ = node,-,-,C,2; -cpu_est_1_ = node,-,-,B,3; -cpu_est_2_ = node,-,-,G,4; +SM_AMIGA_1_ = node,-,-,B,3; +SM_AMIGA_6_ = node,-,-,G,6; +SM_AMIGA_0_ = node,-,-,H,9; +SM_AMIGA_7_ = node,-,-,H,5; +inst_RW_000_INT = node,-,-,G,5; +inst_CLK_000_D2 = node,-,-,H,10; +inst_CLK_030_H = node,-,-,B,5; +SM_AMIGA_5_ = node,-,-,D,11; +SM_AMIGA_4_ = node,-,-,A,5; +SM_AMIGA_3_ = node,-,-,A,4; +SM_AMIGA_2_ = node,-,-,A,1; +cpu_est_0_ = node,-,-,D,10; +cpu_est_1_ = node,-,-,D,7; +cpu_est_2_ = node,-,-,D,9; [GROUP ASSIGNMENTS] Layer = OFF; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index 9a58f18..206f291 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -83714,6 +83714,1972 @@ 15 A_27_ 1 -1 -1 1 4 15 -1 14 A_28_ 1 -1 -1 1 4 14 -1 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +98 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 319 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 324 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 323 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 318 7 3 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21 + 97 DS_030 5 322 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 328 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 7 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 7 29 -1 1 0 21 + 65 E 5 329 6 0 65 -1 3 1 21 + 21 AVEC_EXP 5 331 2 0 21 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 321 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 320 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 330 3 0 34 -1 2 1 21 + 28 BG_000 5 325 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 326 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 318 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 314 cpu_est_0_ 3 -1 2 4 1 2 3 6 -1 -1 3 0 21 + 298 inst_CLK_000_D1 3 -1 3 4 1 2 6 7 -1 -1 1 0 21 + 308 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21 + 315 cpu_est_1_ 3 -1 1 3 1 3 6 -1 -1 4 0 21 + 303 SM_AMIGA_7_ 3 -1 1 3 1 2 3 -1 -1 4 0 21 + 329 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21 + 316 cpu_est_2_ 3 -1 6 3 1 3 6 -1 -1 3 1 21 + 305 SM_AMIGA_2_ 3 -1 6 3 2 6 7 -1 -1 3 0 21 + 299 inst_CLK_000_D2 3 -1 7 3 1 2 3 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 1 2 -1 -1 8 0 21 + 310 inst_CLK_030_H 3 -1 7 2 0 7 -1 -1 5 0 21 + 331 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 330 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21 + 327 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 313 SM_AMIGA_0_ 3 -1 0 2 0 1 -1 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21 + 307 SM_AMIGA_6_ 3 -1 1 2 0 1 -1 -1 2 0 21 + 306 SM_AMIGA_1_ 3 -1 7 2 0 7 -1 -1 2 0 21 + 304 SM_AMIGA_5_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 309 inst_CLK_000_D3 3 -1 2 2 1 2 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21 + 321 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 320 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 300 inst_DTACK_D0 3 -1 7 1 6 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 63 CLK_030 1 -1 -1 3 0 2 7 63 -1 + 96 A_19_ 1 -1 -1 2 2 7 96 -1 + 95 A_16_ 1 -1 -1 2 2 7 95 -1 + 94 A_18_ 1 -1 -1 2 2 7 94 -1 + 58 A_17_ 1 -1 -1 2 2 7 58 -1 + 57 FC_1_ 1 -1 -1 2 2 7 57 -1 + 56 FC_0_ 1 -1 -1 2 2 7 56 -1 + 27 BGACK_000 1 -1 -1 2 2 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +98 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 321 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 324 3 3 0 6 7 30 -1 10 0 21 + 31 UDS_000 5 323 3 3 0 6 7 31 -1 6 0 21 + 81 AS_030 5 320 7 3 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21 + 97 DS_030 5 322 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 328 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 7 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 65 E 5 329 6 0 65 -1 3 1 21 + 21 AVEC_EXP 5 331 2 0 21 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 330 3 0 34 -1 2 1 21 + 28 BG_000 5 325 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 326 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 2 5 0 1 3 6 7 -1 -1 1 0 21 + 320 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 298 inst_CLK_000_D1 3 -1 7 4 1 3 6 7 -1 -1 1 0 21 + 307 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21 + 315 cpu_est_1_ 3 -1 3 3 1 3 6 -1 -1 4 0 21 + 304 SM_AMIGA_7_ 3 -1 1 3 1 2 3 -1 -1 4 0 21 + 329 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21 + 308 SM_AMIGA_2_ 3 -1 1 3 1 2 7 -1 -1 3 0 21 + 311 SM_AMIGA_4_ 3 -1 6 3 1 3 6 -1 -1 2 0 21 + 306 SM_AMIGA_1_ 3 -1 7 3 0 6 7 -1 -1 2 0 21 + 305 SM_AMIGA_5_ 3 -1 0 3 0 3 6 -1 -1 2 0 21 + 300 inst_CLK_000_D3 3 -1 7 3 1 2 7 -1 -1 1 0 21 + 299 inst_CLK_000_D2 3 -1 3 3 1 2 7 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 1 2 -1 -1 8 0 21 + 309 inst_CLK_030_H 3 -1 7 2 0 7 -1 -1 5 0 21 + 331 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 3 0 21 + 316 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 314 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 + 303 inst_CLK_OUT_PRE_25 3 -1 6 2 1 6 -1 -1 3 0 21 + 330 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 327 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 313 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 2 0 21 + 310 SM_AMIGA_6_ 3 -1 1 2 0 1 -1 -1 2 0 21 + 302 inst_CLK_OUT_PRE_50 3 -1 7 2 6 7 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 1 2 1 3 -1 -1 1 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 312 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21 + 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 321 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 301 inst_DTACK_D0 3 -1 2 1 1 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 6 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 7 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 63 CLK_030 1 -1 -1 3 0 2 7 63 -1 + 96 A_19_ 1 -1 -1 2 2 7 96 -1 + 95 A_16_ 1 -1 -1 2 2 7 95 -1 + 94 A_18_ 1 -1 -1 2 2 7 94 -1 + 58 A_17_ 1 -1 -1 2 2 7 58 -1 + 57 FC_1_ 1 -1 -1 2 2 7 57 -1 + 56 FC_0_ 1 -1 -1 2 2 7 56 -1 + 27 BGACK_000 1 -1 -1 2 2 7 27 -1 + 10 CLK_000 1 -1 -1 2 2 3 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +99 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 322 3 5 0 1 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 325 3 4 0 1 6 7 30 -1 10 0 21 + 31 UDS_000 5 324 3 4 0 1 6 7 31 -1 6 0 21 + 81 AS_030 5 321 7 3 0 3 7 81 -1 4 0 21 + 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21 + 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21 + 97 DS_030 5 323 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 329 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 7 29 -1 1 0 21 + 65 E 5 330 6 0 65 -1 3 1 21 + 21 AVEC_EXP 5 332 2 0 21 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21 + 82 BGACK_030 5 327 7 0 82 -1 2 0 21 + 77 FPU_CS 5 328 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 331 3 0 34 -1 2 1 21 + 28 BG_000 5 326 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 327 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 2 0 21 + 321 RN_AS_030 3 81 7 5 0 1 3 6 7 81 -1 4 0 21 + 298 inst_CLK_000_D1 3 -1 3 5 1 2 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 6 5 1 2 3 6 7 -1 -1 1 0 21 + 316 cpu_est_1_ 3 -1 2 4 1 2 3 6 -1 -1 4 0 21 + 330 RN_E 3 65 6 4 1 2 3 6 65 -1 3 1 21 + 315 cpu_est_0_ 3 -1 7 4 2 3 6 7 -1 -1 3 0 21 + 304 SM_AMIGA_7_ 3 -1 2 3 0 2 3 -1 -1 4 0 21 + 317 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 3 1 21 + 309 SM_AMIGA_2_ 3 -1 1 3 0 1 7 -1 -1 3 0 21 + 303 inst_CLK_OUT_PRE_25 3 -1 2 3 1 2 6 -1 -1 3 0 21 + 308 inst_CLK_000_D3 3 -1 0 3 0 1 2 -1 -1 1 0 21 + 307 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21 + 293 inst_AS_030_000_SYNC 3 -1 0 2 0 2 -1 -1 8 0 21 + 310 inst_CLK_030_H 3 -1 1 2 0 1 -1 -1 5 0 21 + 332 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 3 0 21 + 331 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 328 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 314 SM_AMIGA_0_ 3 -1 7 2 2 7 -1 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 311 SM_AMIGA_6_ 3 -1 2 2 2 6 -1 -1 2 0 21 + 306 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 2 0 21 + 305 SM_AMIGA_5_ 3 -1 6 2 3 6 -1 -1 2 0 21 + 302 inst_CLK_OUT_PRE_50 3 -1 7 2 2 7 -1 -1 1 0 21 + 300 inst_CLK_000_D4 3 -1 1 2 0 7 -1 -1 1 0 21 + 299 inst_CLK_000_D2 3 -1 3 2 0 2 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 1 2 1 3 -1 -1 1 0 21 + 325 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 324 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 313 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21 + 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 329 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 322 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 301 inst_DTACK_D0 3 -1 7 1 1 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 2 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 7 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 2 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 4 0 1 6 7 63 -1 + 96 A_19_ 1 -1 -1 2 0 7 96 -1 + 95 A_16_ 1 -1 -1 2 0 7 95 -1 + 94 A_18_ 1 -1 -1 2 0 7 94 -1 + 58 A_17_ 1 -1 -1 2 0 7 58 -1 + 57 FC_1_ 1 -1 -1 2 0 7 57 -1 + 56 FC_0_ 1 -1 -1 2 0 7 56 -1 + 27 BGACK_000 1 -1 -1 2 0 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 6 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +98 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 321 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 324 3 3 0 6 7 30 -1 10 0 21 + 31 UDS_000 5 323 3 3 0 6 7 31 -1 6 0 21 + 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21 + 81 AS_030 5 320 7 2 3 7 81 -1 4 0 21 + 97 DS_030 5 322 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 328 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 7 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 7 29 -1 1 0 21 + 65 E 5 329 6 0 65 -1 3 1 21 + 21 AVEC_EXP 5 331 2 0 21 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 317 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 330 3 0 34 -1 2 1 21 + 28 BG_000 5 325 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 326 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 7 6 0 1 2 3 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 7 5 1 2 3 6 7 -1 -1 1 0 21 + 320 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 303 SM_AMIGA_7_ 3 -1 6 4 2 3 6 7 -1 -1 4 0 21 + 304 SM_AMIGA_5_ 3 -1 1 4 0 1 3 6 -1 -1 2 0 21 + 307 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21 + 293 inst_AS_030_000_SYNC 3 -1 7 3 2 6 7 -1 -1 8 0 21 + 315 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 329 RN_E 3 65 6 3 2 3 6 65 -1 3 1 21 + 314 cpu_est_0_ 3 -1 1 3 1 3 6 -1 -1 3 0 21 + 306 SM_AMIGA_2_ 3 -1 2 3 0 2 7 -1 -1 3 0 21 + 311 SM_AMIGA_4_ 3 -1 6 3 2 3 6 -1 -1 2 0 21 + 305 SM_AMIGA_0_ 3 -1 1 3 0 1 6 -1 -1 2 0 21 + 308 inst_CLK_000_D3 3 -1 7 3 2 6 7 -1 -1 1 0 21 + 299 inst_CLK_000_D2 3 -1 3 3 2 6 7 -1 -1 1 0 21 + 309 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21 + 331 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 3 0 21 + 316 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 330 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 327 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 313 SM_AMIGA_1_ 3 -1 0 2 0 1 -1 -1 2 0 21 + 310 SM_AMIGA_6_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 312 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 4 0 21 + 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 321 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 300 inst_DTACK_D0 3 -1 7 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 2 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 10 CLK_000 1 -1 -1 2 3 7 10 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +98 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 321 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 324 3 3 0 6 7 30 -1 10 0 21 + 31 UDS_000 5 323 3 3 0 6 7 31 -1 6 0 21 + 81 AS_030 5 320 7 3 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21 + 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21 + 97 DS_030 5 322 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 328 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 7 29 -1 1 0 21 + 65 E 5 329 6 0 65 -1 3 1 21 + 21 AVEC_EXP 5 331 2 0 21 -1 3 0 21 + 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 317 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 330 3 0 34 -1 2 1 21 + 28 BG_000 5 325 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 326 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 3 5 0 1 2 6 7 -1 -1 1 0 21 + 320 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 306 SM_AMIGA_2_ 3 -1 0 4 0 1 2 7 -1 -1 3 0 21 + 315 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 303 SM_AMIGA_7_ 3 -1 1 3 1 2 3 -1 -1 4 0 21 + 329 RN_E 3 65 6 3 0 3 6 65 -1 3 1 21 + 314 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 304 SM_AMIGA_6_ 3 -1 2 3 2 3 6 -1 -1 2 0 21 + 299 inst_CLK_000_D2 3 -1 7 3 1 2 7 -1 -1 1 0 21 + 307 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 1 2 -1 -1 8 0 21 + 309 inst_CLK_030_H 3 -1 7 2 0 7 -1 -1 5 0 21 + 331 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 3 0 21 + 316 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 330 RN_VMA 3 34 3 2 0 3 34 -1 2 1 21 + 327 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 3 2 0 3 -1 -1 2 0 21 + 305 SM_AMIGA_0_ 3 -1 1 2 1 6 -1 -1 2 0 21 + 308 inst_CLK_000_D3 3 -1 7 2 1 2 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 1 2 0 3 -1 -1 1 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 312 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 0 21 + 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 321 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 313 SM_AMIGA_1_ 3 -1 1 1 1 -1 -1 2 0 21 + 310 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 2 0 21 + 300 inst_DTACK_D0 3 -1 7 1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 63 CLK_030 1 -1 -1 4 0 2 6 7 63 -1 + 96 A_19_ 1 -1 -1 2 2 7 96 -1 + 95 A_16_ 1 -1 -1 2 2 7 95 -1 + 94 A_18_ 1 -1 -1 2 2 7 94 -1 + 58 A_17_ 1 -1 -1 2 2 7 58 -1 + 57 FC_1_ 1 -1 -1 2 2 7 57 -1 + 56 FC_0_ 1 -1 -1 2 2 7 56 -1 + 27 BGACK_000 1 -1 -1 2 2 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +98 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 321 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 324 3 3 0 6 7 30 -1 10 0 21 + 31 UDS_000 5 323 3 3 0 6 7 31 -1 6 0 21 + 81 AS_030 5 320 7 3 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21 + 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21 + 97 DS_030 5 322 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 328 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 65 E 5 329 6 0 65 -1 3 1 21 + 21 AVEC_EXP 5 331 2 0 21 -1 3 0 21 + 8 IPL_030_2_ 5 319 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 317 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 330 3 0 34 -1 2 1 21 + 28 BG_000 5 325 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 326 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 320 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 315 cpu_est_1_ 3 -1 1 4 0 1 3 6 -1 -1 4 0 21 + 329 RN_E 3 65 6 4 0 1 3 6 65 -1 3 1 21 + 298 inst_CLK_000_D1 3 -1 3 4 0 1 6 7 -1 -1 1 0 21 + 316 cpu_est_2_ 3 -1 1 3 1 3 6 -1 -1 3 1 21 + 314 cpu_est_0_ 3 -1 6 3 1 3 6 -1 -1 3 0 21 + 306 SM_AMIGA_2_ 3 -1 0 3 0 2 7 -1 -1 3 0 21 + 304 SM_AMIGA_0_ 3 -1 1 3 1 2 6 -1 -1 2 0 21 + 303 SM_AMIGA_6_ 3 -1 2 3 2 3 6 -1 -1 2 0 21 + 307 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21 + 309 inst_CLK_030_H 3 -1 7 2 0 7 -1 -1 5 0 21 + 305 SM_AMIGA_7_ 3 -1 2 2 2 3 -1 -1 4 0 21 + 331 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 6 2 1 6 -1 -1 3 0 21 + 330 RN_VMA 3 34 3 2 0 3 34 -1 2 1 21 + 327 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 313 SM_AMIGA_1_ 3 -1 7 2 1 7 -1 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 3 2 0 3 -1 -1 2 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 7 2 6 7 -1 -1 1 0 21 + 299 inst_CLK_000_D2 3 -1 7 2 2 7 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 1 2 0 3 -1 -1 1 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 1 2 -1 -1 8 0 21 + 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 312 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 0 21 + 319 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 321 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 310 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 2 0 21 + 308 inst_CLK_000_D3 3 -1 7 1 2 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 1 1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 6 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 2 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 4 0 2 6 7 63 -1 + 96 A_19_ 1 -1 -1 2 2 7 96 -1 + 95 A_16_ 1 -1 -1 2 2 7 95 -1 + 94 A_18_ 1 -1 -1 2 2 7 94 -1 + 58 A_17_ 1 -1 -1 2 2 7 58 -1 + 57 FC_1_ 1 -1 -1 2 2 7 57 -1 + 56 FC_0_ 1 -1 -1 2 2 7 56 -1 + 27 BGACK_000 1 -1 -1 2 2 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 10 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 6 0 21 + 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21 + 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 327 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 7 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 65 E 5 328 6 0 65 -1 3 1 21 + 21 AVEC_EXP 5 330 2 0 21 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 317 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 316 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 1 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 7 6 0 1 2 3 6 7 -1 -1 1 0 21 + 304 SM_AMIGA_7_ 3 -1 6 5 1 2 3 6 7 -1 -1 4 0 21 + 298 inst_CLK_000_D1 3 -1 3 5 1 2 3 6 7 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 7 4 1 2 6 7 -1 -1 8 0 21 + 319 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 307 inst_CLK_000_D2 3 -1 7 4 1 2 6 7 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21 + 314 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 3 2 3 6 65 -1 3 1 21 + 310 SM_AMIGA_4_ 3 -1 0 3 0 2 3 -1 -1 2 0 21 + 303 SM_AMIGA_0_ 3 -1 2 3 0 2 6 -1 -1 2 0 21 + 302 SM_AMIGA_6_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 308 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21 + 330 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 3 0 21 + 315 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 + 305 SM_AMIGA_2_ 3 -1 2 2 2 7 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 326 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 312 SM_AMIGA_1_ 3 -1 7 2 2 7 -1 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 1 2 0 1 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 311 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 4 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 317 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 316 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 299 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 10 CLK_000 1 -1 -1 2 3 7 10 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +99 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 322 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 325 3 3 0 6 7 30 -1 10 0 21 + 31 UDS_000 5 324 3 3 0 6 7 31 -1 6 0 21 + 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21 + 81 AS_030 5 321 7 2 3 7 81 -1 4 0 21 + 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21 + 97 DS_030 5 323 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 329 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 65 E 5 330 6 0 65 -1 3 1 21 + 21 AVEC_EXP 5 332 2 0 21 -1 3 0 21 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21 + 82 BGACK_030 5 327 7 0 82 -1 2 0 21 + 77 FPU_CS 5 328 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 331 3 0 34 -1 2 1 21 + 28 BG_000 5 326 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 327 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 321 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 316 cpu_est_1_ 3 -1 3 4 0 2 3 6 -1 -1 4 0 21 + 303 SM_AMIGA_7_ 3 -1 6 4 2 3 6 7 -1 -1 4 0 21 + 330 RN_E 3 65 6 4 0 2 3 6 65 -1 3 1 21 + 305 SM_AMIGA_6_ 3 -1 2 4 1 2 3 6 -1 -1 2 0 21 + 293 inst_AS_030_000_SYNC 3 -1 7 3 2 6 7 -1 -1 8 0 21 + 308 SM_AMIGA_2_ 3 -1 2 3 1 2 7 -1 -1 3 0 21 + 331 RN_VMA 3 34 3 3 0 2 3 34 -1 2 1 21 + 304 SM_AMIGA_0_ 3 -1 1 3 1 2 6 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 7 3 2 6 7 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 2 3 0 2 3 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21 + 309 inst_CLK_030_H 3 -1 7 2 0 7 -1 -1 5 0 21 + 313 SM_AMIGA_3_ 3 -1 0 2 0 2 -1 -1 4 0 21 + 332 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 3 0 21 + 317 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 315 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 328 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 0 2 0 3 -1 -1 2 0 21 + 311 SM_AMIGA_5_ 3 -1 1 2 0 1 -1 -1 2 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21 + 300 inst_DTACK_D0 3 -1 1 2 0 2 -1 -1 1 0 21 + 325 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 323 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 324 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 329 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 326 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 322 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 314 SM_AMIGA_1_ 3 -1 1 1 1 -1 -1 2 0 21 + 310 inst_CLK_000_D3 3 -1 7 1 0 -1 -1 1 0 21 + 299 inst_CLK_000_D4 3 -1 0 1 7 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 2 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 318 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 321 3 3 0 6 7 30 -1 10 0 21 + 31 UDS_000 5 320 3 3 0 6 7 31 -1 6 0 21 + 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21 + 81 AS_030 5 317 7 2 3 7 81 -1 4 0 21 + 97 DS_030 5 319 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 325 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 7 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 7 29 -1 1 0 21 + 65 E 5 326 6 0 65 -1 3 1 21 + 21 AVEC_EXP 5 330 2 0 21 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 328 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 327 3 0 34 -1 2 1 21 + 28 BG_000 5 322 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 323 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 7 6 0 1 2 3 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 7 5 1 2 3 6 7 -1 -1 1 0 21 + 317 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 6 4 1 2 3 6 -1 -1 4 0 21 + 326 RN_E 3 65 6 4 1 2 3 6 65 -1 3 1 21 + 302 SM_AMIGA_6_ 3 -1 2 4 0 2 3 6 -1 -1 2 0 21 + 306 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21 + 304 SM_AMIGA_7_ 3 -1 7 3 2 3 7 -1 -1 4 0 21 + 327 RN_VMA 3 34 3 3 1 2 3 34 -1 2 1 21 + 303 SM_AMIGA_0_ 3 -1 0 3 0 2 7 -1 -1 2 0 21 + 295 inst_VPA_D 3 -1 1 3 1 2 3 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 7 2 2 7 -1 -1 8 0 21 + 308 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21 + 311 SM_AMIGA_3_ 3 -1 1 2 1 2 -1 -1 4 0 21 + 330 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 3 0 21 + 315 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 + 305 SM_AMIGA_2_ 3 -1 2 2 2 7 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 324 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 312 SM_AMIGA_1_ 3 -1 2 2 0 2 -1 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 3 2 2 7 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 7 2 1 2 -1 -1 1 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 319 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 325 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 322 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 318 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 2 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 10 CLK_000 1 -1 -1 3 2 3 7 10 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 10 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 6 0 21 + 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21 + 81 AS_030 5 319 7 2 3 7 81 -1 4 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 327 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 7 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 65 E 5 328 6 0 65 -1 3 1 21 + 21 AVEC_EXP 5 330 2 0 21 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 317 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 316 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 1 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 7 6 0 1 2 3 6 7 -1 -1 1 0 21 + 304 SM_AMIGA_7_ 3 -1 6 5 1 2 3 6 7 -1 -1 4 0 21 + 298 inst_CLK_000_D1 3 -1 3 5 1 2 3 6 7 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 7 4 1 2 6 7 -1 -1 8 0 21 + 319 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 307 inst_CLK_000_D2 3 -1 7 4 1 2 6 7 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21 + 314 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 3 2 3 6 65 -1 3 1 21 + 310 SM_AMIGA_4_ 3 -1 0 3 0 2 3 -1 -1 2 0 21 + 303 SM_AMIGA_0_ 3 -1 2 3 0 2 6 -1 -1 2 0 21 + 302 SM_AMIGA_6_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 308 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21 + 330 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 3 0 21 + 315 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 313 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 + 305 SM_AMIGA_2_ 3 -1 2 2 2 7 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 2 3 34 -1 2 1 21 + 326 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 312 SM_AMIGA_1_ 3 -1 7 2 2 7 -1 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 1 2 0 1 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 311 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 4 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 317 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 316 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 299 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 10 CLK_000 1 -1 -1 2 3 7 10 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 10 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 6 0 21 + 81 AS_030 5 319 7 3 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 327 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 7 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 2 29 -1 1 0 21 + 65 E 5 328 6 0 65 -1 3 1 21 + 21 AVEC_EXP 5 330 2 0 21 -1 3 0 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 317 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 316 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 1 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 7 5 1 2 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 303 SM_AMIGA_6_ 3 -1 1 4 0 1 3 6 -1 -1 2 0 21 + 306 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21 + 314 cpu_est_1_ 3 -1 3 3 1 3 6 -1 -1 4 0 21 + 305 SM_AMIGA_7_ 3 -1 2 3 1 2 3 -1 -1 4 0 21 + 328 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21 + 313 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 0 3 0 1 6 -1 -1 3 0 21 + 304 SM_AMIGA_0_ 3 -1 7 3 0 2 7 -1 -1 2 0 21 + 302 SM_AMIGA_1_ 3 -1 6 3 2 6 7 -1 -1 2 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 1 2 -1 -1 8 0 21 + 308 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21 + 330 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 3 0 21 + 315 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 312 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 326 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 3 2 1 2 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 7 2 0 7 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 7 2 1 3 -1 -1 1 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 311 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 317 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 316 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 299 inst_DTACK_D0 3 -1 2 1 1 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 0 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 63 CLK_030 1 -1 -1 4 0 2 6 7 63 -1 + 96 A_19_ 1 -1 -1 2 2 7 96 -1 + 95 A_16_ 1 -1 -1 2 2 7 95 -1 + 94 A_18_ 1 -1 -1 2 2 7 94 -1 + 58 A_17_ 1 -1 -1 2 2 7 58 -1 + 57 FC_1_ 1 -1 -1 2 2 7 57 -1 + 56 FC_0_ 1 -1 -1 2 2 7 56 -1 + 27 BGACK_000 1 -1 -1 2 2 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 10 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 6 0 21 + 81 AS_030 5 319 7 3 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 6 3 0 3 4 70 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 327 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 79 RW_000 5 -1 7 1 0 79 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 7 29 -1 1 0 21 + 21 AVEC_EXP 5 330 2 0 21 -1 4 0 21 + 65 E 5 328 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 317 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 316 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 1 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 3 5 1 2 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 306 inst_RW_000_INT 3 -1 0 3 0 6 7 -1 -1 14 0 21 + 303 SM_AMIGA_7_ 3 -1 1 3 1 2 3 -1 -1 4 0 21 + 313 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 0 3 0 1 6 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 305 SM_AMIGA_0_ 3 -1 2 3 0 1 2 -1 -1 2 0 21 + 304 SM_AMIGA_6_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 302 SM_AMIGA_1_ 3 -1 0 3 0 2 7 -1 -1 2 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 1 2 -1 -1 8 0 21 + 308 inst_CLK_030_H 3 -1 7 2 0 7 -1 -1 5 0 21 + 330 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 4 0 21 + 314 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 2 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 312 SM_AMIGA_2_ 3 -1 6 2 0 6 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 3 6 34 -1 2 1 21 + 326 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 3 2 1 2 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 7 2 0 7 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 1 2 3 6 -1 -1 1 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 311 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 4 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 317 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 316 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 299 inst_DTACK_D0 3 -1 7 1 6 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 0 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 63 CLK_030 1 -1 -1 3 0 2 7 63 -1 + 96 A_19_ 1 -1 -1 2 2 7 96 -1 + 95 A_16_ 1 -1 -1 2 2 7 95 -1 + 94 A_18_ 1 -1 -1 2 2 7 94 -1 + 58 A_17_ 1 -1 -1 2 2 7 58 -1 + 57 FC_1_ 1 -1 -1 2 2 7 57 -1 + 56 FC_0_ 1 -1 -1 2 2 7 56 -1 + 27 BGACK_000 1 -1 -1 2 2 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 5 0 1 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 4 0 1 6 7 30 -1 10 0 21 + 31 UDS_000 5 322 3 4 0 1 6 7 31 -1 6 0 21 + 81 AS_030 5 319 7 3 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21 + 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 327 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 7 29 -1 1 0 21 + 21 AVEC_EXP 5 330 2 0 21 -1 4 0 21 + 65 E 5 328 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 316 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 1 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 5 0 1 3 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 303 SM_AMIGA_7_ 3 -1 1 3 1 2 3 -1 -1 4 0 21 + 328 RN_E 3 65 6 3 0 3 6 65 -1 3 1 21 + 313 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 2 3 1 2 6 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 6 3 0 3 6 -1 -1 2 0 21 + 304 SM_AMIGA_6_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 302 SM_AMIGA_1_ 3 -1 7 3 1 2 7 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 1 3 1 2 7 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 1 2 -1 -1 8 0 21 + 308 inst_CLK_030_H 3 -1 1 2 0 1 -1 -1 5 0 21 + 330 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 4 0 21 + 315 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 312 SM_AMIGA_2_ 3 -1 0 2 0 7 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 0 3 34 -1 2 1 21 + 326 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 305 SM_AMIGA_0_ 3 -1 1 2 1 6 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 7 2 1 2 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 311 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 21 + 299 inst_DTACK_D0 3 -1 7 1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 2 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 63 CLK_030 1 -1 -1 5 0 1 2 6 7 63 -1 + 96 A_19_ 1 -1 -1 2 2 7 96 -1 + 95 A_16_ 1 -1 -1 2 2 7 95 -1 + 94 A_18_ 1 -1 -1 2 2 7 94 -1 + 58 A_17_ 1 -1 -1 2 2 7 58 -1 + 57 FC_1_ 1 -1 -1 2 2 7 57 -1 + 56 FC_0_ 1 -1 -1 2 2 7 56 -1 + 27 BGACK_000 1 -1 -1 2 2 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 10 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 6 0 21 + 81 AS_030 5 319 7 3 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21 + 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 327 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 21 AVEC_EXP 5 330 2 0 21 -1 4 0 21 + 65 E 5 328 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 316 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 1 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 3 5 0 1 2 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 313 cpu_est_0_ 3 -1 7 4 0 3 6 7 -1 -1 3 0 21 + 314 cpu_est_1_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 302 SM_AMIGA_7_ 3 -1 1 3 1 2 3 -1 -1 4 0 21 + 328 RN_E 3 65 6 3 0 3 6 65 -1 3 1 21 + 315 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 3 1 21 + 306 SM_AMIGA_2_ 3 -1 0 3 0 2 7 -1 -1 3 0 21 + 304 SM_AMIGA_6_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 307 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 1 2 -1 -1 8 0 21 + 309 inst_CLK_030_H 3 -1 6 2 0 6 -1 -1 5 0 21 + 330 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 4 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 0 3 34 -1 2 1 21 + 326 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 3 2 0 3 -1 -1 2 0 21 + 305 SM_AMIGA_0_ 3 -1 1 2 1 6 -1 -1 2 0 21 + 303 SM_AMIGA_1_ 3 -1 2 2 1 2 -1 -1 2 0 21 + 308 inst_CLK_000_D2 3 -1 7 2 1 2 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 312 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 310 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 2 0 21 + 299 inst_DTACK_D0 3 -1 1 1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 63 CLK_030 1 -1 -1 4 0 2 6 7 63 -1 + 96 A_19_ 1 -1 -1 2 2 7 96 -1 + 95 A_16_ 1 -1 -1 2 2 7 95 -1 + 94 A_18_ 1 -1 -1 2 2 7 94 -1 + 58 A_17_ 1 -1 -1 2 2 7 58 -1 + 57 FC_1_ 1 -1 -1 2 2 7 57 -1 + 56 FC_0_ 1 -1 -1 2 2 7 56 -1 + 27 BGACK_000 1 -1 -1 2 2 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 319 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 7 0 21 + 70 RW 5 -1 6 3 3 4 7 70 -1 1 0 21 + 79 RW_000 5 320 7 2 0 6 79 -1 5 0 21 + 81 AS_030 5 318 7 2 3 7 81 -1 4 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 327 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 21 AVEC_EXP 5 330 2 0 21 -1 4 0 21 + 65 E 5 328 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 316 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 315 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 1 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 0 6 0 1 2 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 7 6 0 1 2 3 6 7 -1 -1 1 0 21 + 318 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 313 cpu_est_1_ 3 -1 3 4 0 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 4 0 2 3 6 65 -1 3 1 21 + 302 SM_AMIGA_7_ 3 -1 7 3 2 3 7 -1 -1 4 0 21 + 305 SM_AMIGA_2_ 3 -1 0 3 0 1 7 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 3 0 2 3 34 -1 2 1 21 + 303 SM_AMIGA_1_ 3 -1 1 3 1 2 6 -1 -1 2 0 21 + 295 inst_VPA_D 3 -1 1 3 0 2 3 -1 -1 1 0 21 + 293 inst_AS_030_000_SYNC 3 -1 7 2 2 7 -1 -1 8 0 21 + 330 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 4 0 21 + 311 SM_AMIGA_3_ 3 -1 2 2 0 2 -1 -1 4 0 21 + 314 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 312 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 326 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 306 SM_AMIGA_0_ 3 -1 6 2 6 7 -1 -1 2 0 21 + 304 SM_AMIGA_6_ 3 -1 7 2 3 7 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 7 2 2 7 -1 -1 1 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 6 2 1 6 -1 -1 1 0 21 + 299 inst_DTACK_D0 3 -1 1 2 0 2 -1 -1 1 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 320 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 308 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 315 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 319 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 6 1 1 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 7 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 6 0 2 3 4 6 7 13 -1 + 10 CLK_000 1 -1 -1 3 3 6 7 10 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 5 0 1 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 4 0 1 6 7 30 -1 10 0 21 + 31 UDS_000 5 322 3 4 0 1 6 7 31 -1 6 0 21 + 81 AS_030 5 319 7 3 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21 + 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 327 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 7 29 -1 1 0 21 + 21 AVEC_EXP 5 330 2 0 21 -1 4 0 21 + 65 E 5 328 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 316 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 1 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 2 0 21 + 298 inst_CLK_000_D1 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 297 inst_CLK_000_D0 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 5 0 1 3 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 303 SM_AMIGA_7_ 3 -1 1 3 1 2 3 -1 -1 4 0 21 + 328 RN_E 3 65 6 3 0 3 6 65 -1 3 1 21 + 313 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 2 3 1 2 6 -1 -1 3 0 21 + 310 SM_AMIGA_4_ 3 -1 6 3 0 3 6 -1 -1 2 0 21 + 304 SM_AMIGA_6_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 302 SM_AMIGA_1_ 3 -1 7 3 1 2 7 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 1 3 1 2 7 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 1 2 -1 -1 8 0 21 + 308 inst_CLK_030_H 3 -1 1 2 0 1 -1 -1 5 0 21 + 330 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 4 0 21 + 315 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 312 SM_AMIGA_2_ 3 -1 0 2 0 7 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 0 3 34 -1 2 1 21 + 326 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 305 SM_AMIGA_0_ 3 -1 1 2 1 6 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 7 2 1 2 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 10 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 6 0 21 + 311 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 0 21 + 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 21 + 299 inst_DTACK_D0 3 -1 7 1 0 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 7 1 2 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 63 CLK_030 1 -1 -1 5 0 1 2 6 7 63 -1 + 96 A_19_ 1 -1 -1 2 2 7 96 -1 + 95 A_16_ 1 -1 -1 2 2 7 95 -1 + 94 A_18_ 1 -1 -1 2 2 7 94 -1 + 58 A_17_ 1 -1 -1 2 2 7 58 -1 + 57 FC_1_ 1 -1 -1 2 2 7 57 -1 + 56 FC_0_ 1 -1 -1 2 2 7 56 -1 + 27 BGACK_000 1 -1 -1 2 2 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 320 3 4 0 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 323 3 3 0 6 7 30 -1 11 0 21 + 31 UDS_000 5 322 3 3 0 6 7 31 -1 7 0 21 + 81 AS_030 5 319 7 3 2 3 7 81 -1 4 0 21 + 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21 + 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21 + 97 DS_030 5 321 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 327 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 7 29 -1 1 0 21 + 21 AVEC_EXP 5 330 2 0 21 -1 4 0 21 + 65 E 5 328 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 318 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 317 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 316 1 0 6 -1 3 0 21 + 82 BGACK_030 5 325 7 0 82 -1 2 0 21 + 77 FPU_CS 5 326 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 1 21 + 28 BG_000 5 324 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 325 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 2 0 21 + 297 inst_CLK_000_D0 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D1 3 -1 3 5 0 1 2 6 7 -1 -1 1 0 21 + 319 RN_AS_030 3 81 7 4 0 3 6 7 81 -1 4 0 21 + 314 cpu_est_1_ 3 -1 6 3 1 3 6 -1 -1 4 0 21 + 303 SM_AMIGA_7_ 3 -1 1 3 1 2 3 -1 -1 4 0 21 + 328 RN_E 3 65 6 3 1 3 6 65 -1 3 1 21 + 313 cpu_est_0_ 3 -1 0 3 0 3 6 -1 -1 3 0 21 + 301 inst_CLK_OUT_PRE_25 3 -1 0 3 0 1 6 -1 -1 3 0 21 + 305 SM_AMIGA_0_ 3 -1 7 3 1 6 7 -1 -1 2 0 21 + 304 SM_AMIGA_6_ 3 -1 2 3 2 3 6 -1 -1 2 0 21 + 302 SM_AMIGA_1_ 3 -1 1 3 1 2 7 -1 -1 2 0 21 + 300 inst_CLK_OUT_PRE_50 3 -1 7 3 0 3 7 -1 -1 1 0 21 + 306 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21 + 293 inst_AS_030_000_SYNC 3 -1 2 2 1 2 -1 -1 8 0 21 + 330 RN_AVEC_EXP 3 21 2 2 2 3 21 -1 4 0 21 + 315 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 329 RN_VMA 3 34 3 2 1 3 34 -1 2 1 21 + 326 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 309 SM_AMIGA_5_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 307 inst_CLK_000_D2 3 -1 7 2 1 2 -1 -1 1 0 21 + 295 inst_VPA_D 3 -1 7 2 1 3 -1 -1 1 0 21 + 323 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 322 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 321 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 308 inst_CLK_030_H 3 -1 0 1 0 -1 -1 5 0 21 + 311 SM_AMIGA_3_ 3 -1 1 1 1 -1 -1 4 0 21 + 318 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 317 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 316 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 312 SM_AMIGA_2_ 3 -1 1 1 1 -1 -1 3 0 21 + 327 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 324 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 320 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 310 SM_AMIGA_4_ 3 -1 1 1 1 -1 -1 2 0 21 + 299 inst_DTACK_D0 3 -1 7 1 1 -1 -1 1 0 21 + 296 inst_CLK_OUT_PRE_50_D 3 -1 3 1 0 -1 -1 1 0 21 + 294 inst_BGACK_030_INT_D 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 85 RST 1 -1 -1 6 0 1 2 3 6 7 85 -1 + 63 CLK_030 1 -1 -1 4 0 2 6 7 63 -1 + 96 A_19_ 1 -1 -1 2 2 7 96 -1 + 95 A_16_ 1 -1 -1 2 2 7 95 -1 + 94 A_18_ 1 -1 -1 2 2 7 94 -1 + 58 A_17_ 1 -1 -1 2 2 7 58 -1 + 57 FC_1_ 1 -1 -1 2 2 7 57 -1 + 56 FC_0_ 1 -1 -1 2 2 7 56 -1 + 27 BGACK_000 1 -1 -1 2 2 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 321 3 5 0 1 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 324 3 4 0 1 6 7 30 -1 11 0 21 + 31 UDS_000 5 323 3 4 0 1 6 7 31 -1 7 0 21 + 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21 + 81 AS_030 5 320 7 2 3 7 81 -1 4 0 21 + 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21 + 97 DS_030 5 322 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 328 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 65 E 5 329 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 330 3 0 34 -1 2 1 21 + 28 BG_000 5 325 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 326 RN_BGACK_030 3 82 7 6 0 1 3 4 6 7 82 -1 2 0 21 + 320 RN_AS_030 3 81 7 5 0 1 3 6 7 81 -1 4 0 21 + 299 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21 + 293 inst_avec_expreg 3 -1 6 3 2 3 6 -1 -1 6 0 21 + 315 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 306 SM_AMIGA_7_ 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 329 RN_E 3 65 6 3 0 3 6 65 -1 3 1 21 + 303 SM_AMIGA_1_ 3 -1 1 3 1 6 7 -1 -1 2 0 21 + 307 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21 + 294 inst_AS_030_000_SYNC 3 -1 7 2 6 7 -1 -1 8 0 21 + 309 inst_CLK_030_H 3 -1 1 2 0 1 -1 -1 5 0 21 + 316 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 314 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 + 313 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 330 RN_VMA 3 34 3 2 0 3 34 -1 2 1 21 + 327 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 321 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21 + 310 SM_AMIGA_5_ 3 -1 3 2 0 3 -1 -1 2 0 21 + 305 SM_AMIGA_0_ 3 -1 7 2 6 7 -1 -1 2 0 21 + 304 SM_AMIGA_6_ 3 -1 6 2 3 6 -1 -1 2 0 21 + 308 inst_CLK_000_D2 3 -1 7 2 6 7 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 312 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 0 21 + 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 0 1 0 -1 -1 2 0 21 + 300 inst_DTACK_D0 3 -1 1 1 0 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 1 1 6 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 4 0 1 6 7 63 -1 + 10 CLK_000 1 -1 -1 2 3 7 10 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +97 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 32 AS_000 5 321 3 5 0 1 4 6 7 32 -1 2 0 21 + 30 LDS_000 5 324 3 4 0 1 6 7 30 -1 11 0 21 + 31 UDS_000 5 323 3 4 0 1 6 7 31 -1 7 0 21 + 81 AS_030 5 320 7 3 3 6 7 81 -1 4 0 21 + 70 RW 5 -1 6 3 3 4 6 70 -1 1 0 21 + 79 RW_000 5 -1 7 2 0 6 79 -1 1 0 21 + 97 DS_030 5 322 0 1 3 97 -1 7 0 21 + 80 DSACK1 5 328 7 1 3 80 -1 2 0 21 + 78 SIZE_1_ 5 -1 7 1 3 78 -1 2 0 21 + 69 SIZE_0_ 5 -1 6 1 3 69 -1 1 0 21 + 68 A0 5 -1 6 1 3 68 -1 1 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 65 E 5 329 6 0 65 -1 3 1 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 34 VMA 5 330 3 0 34 -1 2 1 21 + 28 BG_000 5 325 3 0 28 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 326 RN_BGACK_030 3 82 7 6 0 1 3 4 6 7 82 -1 2 0 21 + 320 RN_AS_030 3 81 7 5 0 1 3 6 7 81 -1 4 0 21 + 299 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 21 + 298 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 21 + 293 inst_avec_expreg 3 -1 6 3 2 3 6 -1 -1 6 0 21 + 315 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 21 + 306 SM_AMIGA_7_ 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 329 RN_E 3 65 6 3 0 3 6 65 -1 3 1 21 + 303 SM_AMIGA_1_ 3 -1 1 3 1 6 7 -1 -1 2 0 21 + 307 inst_RW_000_INT 3 -1 6 2 6 7 -1 -1 14 0 21 + 294 inst_AS_030_000_SYNC 3 -1 7 2 6 7 -1 -1 8 0 21 + 309 inst_CLK_030_H 3 -1 1 2 0 1 -1 -1 5 0 21 + 316 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 21 + 314 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 21 + 313 SM_AMIGA_2_ 3 -1 0 2 0 1 -1 -1 3 0 21 + 302 inst_CLK_OUT_PRE_25 3 -1 1 2 1 6 -1 -1 3 0 21 + 330 RN_VMA 3 34 3 2 0 3 34 -1 2 1 21 + 327 RN_FPU_CS 3 77 7 2 4 7 77 -1 2 0 21 + 310 SM_AMIGA_5_ 3 -1 3 2 0 3 -1 -1 2 0 21 + 305 SM_AMIGA_0_ 3 -1 7 2 6 7 -1 -1 2 0 21 + 304 SM_AMIGA_6_ 3 -1 6 2 3 6 -1 -1 2 0 21 + 308 inst_CLK_000_D2 3 -1 7 2 6 7 -1 -1 1 0 21 + 301 inst_CLK_OUT_PRE_50 3 -1 7 2 1 7 -1 -1 1 0 21 + 296 inst_VPA_D 3 -1 0 2 0 3 -1 -1 1 0 21 + 324 RN_LDS_000 3 30 3 1 3 30 -1 11 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 7 0 21 + 322 RN_DS_030 3 97 0 1 0 97 -1 7 0 21 + 312 SM_AMIGA_3_ 3 -1 0 1 0 -1 -1 4 0 21 + 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 328 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 325 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 321 RN_AS_000 3 32 3 1 3 32 -1 2 0 21 + 311 SM_AMIGA_4_ 3 -1 0 1 0 -1 -1 2 0 21 + 300 inst_DTACK_D0 3 -1 1 1 0 -1 -1 1 0 21 + 297 inst_CLK_OUT_PRE_50_D 3 -1 7 1 1 -1 -1 1 0 21 + 295 inst_BGACK_030_INT_D 3 -1 1 1 6 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 63 CLK_030 1 -1 -1 4 0 1 6 7 63 -1 + 10 CLK_000 1 -1 -1 2 3 7 10 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 5 A_29_ 1 -1 -1 1 4 5 -1 4 A_30_ 1 -1 -1 1 4 4 -1 3 A_31_ 1 -1 -1 1 4 3 -1 \ No newline at end of file diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index 8051e4f..925b6d9 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,27 +8,23 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Sun Jun 01 01:03:29 2014 +; DATE Sat Jun 07 23:03:24 2014 -Pin 17 A_26_ -Pin 18 A_25_ -Pin 19 A_24_ -Pin 84 A_23_ -Pin 4 A_31_ Pin 85 A_22_ Pin 94 A_21_ Pin 93 A_20_ Pin 97 A_19_ -Pin 68 IPL_2_ +Pin 4 A_31_ Pin 95 A_18_ Pin 59 A_17_ -Pin 58 FC_1_ Pin 96 A_16_ -Pin 80 RW_000 Comb ; S6=1 S9=1 Pair 271 +Pin 68 IPL_2_ Pin 56 IPL_1_ +Pin 58 FC_1_ Pin 67 IPL_0_ Pin 57 FC_0_ +Pin 80 RW_000 Comb ; S6=1 S9=1 Pair 269 Pin 14 nEXP_SPACE Pin 41 BERR Comb ; S6=1 S9=1 Pair 200 Pin 21 BG_030 @@ -39,7 +35,7 @@ Pin 61 CLK_OSZI Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 250 Pin 30 DTACK Comb ; S6=1 S9=1 Pair 173 Pin 92 AVEC Comb ; S6=1 S9=1 Pair 104 -Pin 22 AVEC_EXP Reg ; S6=1 S9=1 Pair 149 +Pin 22 AVEC_EXP Comb ; S6=1 S9=1 Pair 149 Pin 36 VPA Pin 86 RST Pin 71 RW Comb ; S6=1 S9=1 Pair 245 @@ -51,12 +47,16 @@ Pin 5 A_30_ Pin 6 A_29_ Pin 15 A_28_ Pin 16 A_27_ -Pin 79 SIZE_1_ Reg ; S6=1 S9=1 Pair 269 +Pin 17 A_26_ +Pin 18 A_25_ +Pin 19 A_24_ +Pin 84 A_23_ +Pin 79 SIZE_1_ Reg ; S6=1 S9=1 Pair 271 Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 128 -Pin 82 AS_030 Reg ; S6=1 S9=1 Pair 278 Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 134 -Pin 33 AS_000 Reg ; S6=1 S9=1 Pair 179 Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 131 +Pin 82 AS_030 Reg ; S6=1 S9=1 Pair 278 +Pin 33 AS_000 Reg ; S6=1 S9=1 Pair 179 Pin 98 DS_030 Reg ; S6=1 S9=1 Pair 101 Pin 32 UDS_000 Reg ; S6=1 S9=1 Pair 182 Pin 31 LDS_000 Reg ; S6=1 S9=1 Pair 185 @@ -70,16 +70,15 @@ Pin 66 E Reg ; S6=1 S9=1 Pair 248 Pin 35 VMA Reg ; S6=1 S9=1 Pair 175 Pin 3 RESET Reg ; S6=0 S9=1 Pair 127 Pin 70 SIZE_0_ Reg ; S6=0 S9=1 Pair 247 -Node 271 RN_RW_000 Comb ; S6=1 S9=1 +Node 269 RN_RW_000 Comb ; S6=1 S9=1 Node 173 RN_DTACK Comb ; S6=1 S9=1 -Node 149 RN_AVEC_EXP Reg ; S6=1 S9=1 Node 245 RN_RW Comb ; S6=1 S9=1 -Node 269 RN_SIZE_1_ Reg ; S6=1 S9=1 +Node 271 RN_SIZE_1_ Reg ; S6=1 S9=1 Node 128 RN_IPL_030_2_ Reg ; S6=1 S9=1 -Node 278 RN_AS_030 Reg ; S6=1 S9=1 Node 134 RN_IPL_030_1_ Reg ; S6=1 S9=1 -Node 179 RN_AS_000 Reg ; S6=1 S9=1 Node 131 RN_IPL_030_0_ Reg ; S6=1 S9=1 +Node 278 RN_AS_030 Reg ; S6=1 S9=1 +Node 179 RN_AS_000 Reg ; S6=1 S9=1 Node 101 RN_DS_030 Reg ; S6=1 S9=1 Node 182 RN_UDS_000 Reg ; S6=1 S9=1 Node 185 RN_LDS_000 Reg ; S6=1 S9=1 @@ -91,29 +90,29 @@ Node 281 RN_DSACK1 Reg ; S6=1 S9=1 Node 248 RN_E Reg ; S6=1 S9=1 Node 175 RN_VMA Reg ; S6=1 S9=1 Node 247 RN_SIZE_0_ Reg ; S6=0 S9=1 -Node 154 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 -Node 188 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 -Node 284 inst_VPA_D Reg ; S6=1 S9=1 +Node 251 inst_avec_expreg Reg ; S6=0 S9=1 +Node 280 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 139 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 +Node 106 inst_VPA_D Reg ; S6=1 S9=1 Node 287 inst_CLK_OUT_PRE_50_D Reg ; S6=0 S9=1 -Node 181 inst_CLK_000_D0 Reg ; S6=1 S9=1 -Node 184 inst_CLK_000_D1 Reg ; S6=1 S9=1 -Node 274 inst_CLK_000_D2 Reg ; S6=1 S9=1 -Node 286 inst_DTACK_D0 Reg ; S6=1 S9=1 -Node 283 inst_CLK_OUT_PRE_50 Reg ; S6=0 S9=1 +Node 274 inst_CLK_000_D0 Reg ; S6=1 S9=1 +Node 181 inst_CLK_000_D1 Reg ; S6=1 S9=1 +Node 137 inst_DTACK_D0 Reg ; S6=1 S9=1 +Node 286 inst_CLK_OUT_PRE_50 Reg ; S6=0 S9=1 Node 136 inst_CLK_OUT_PRE_25 Reg ; S6=0 S9=1 -Node 133 SM_AMIGA_7_ Reg ; S6=1 S9=1 -Node 139 SM_AMIGA_6_ Reg ; S6=0 S9=1 -Node 103 SM_AMIGA_0_ Reg ; S6=0 S9=1 -Node 137 SM_AMIGA_5_ Reg ; S6=0 S9=1 -Node 253 SM_AMIGA_2_ Reg ; S6=1 S9=1 -Node 106 inst_RW_000_INT Reg ; S6=1 S9=1 -Node 155 inst_CLK_000_D3 Reg ; S6=1 S9=1 -Node 277 inst_CLK_030_H Reg ; S6=1 S9=1 -Node 187 SM_AMIGA_4_ Reg ; S6=0 S9=1 -Node 254 SM_AMIGA_3_ Reg ; S6=1 S9=1 -Node 280 SM_AMIGA_1_ Reg ; S6=0 S9=1 -Node 152 cpu_est_0_ Reg ; S6=0 S9=1 -Node 130 cpu_est_1_ Reg ; S6=0 S9=1 -Node 251 cpu_est_2_ Reg ; S6=1 S9=1 +Node 130 SM_AMIGA_1_ Reg ; S6=0 S9=1 +Node 254 SM_AMIGA_6_ Reg ; S6=1 S9=1 +Node 283 SM_AMIGA_0_ Reg ; S6=0 S9=1 +Node 277 SM_AMIGA_7_ Reg ; S6=1 S9=1 +Node 253 inst_RW_000_INT Reg ; S6=0 S9=1 +Node 284 inst_CLK_000_D2 Reg ; S6=1 S9=1 +Node 133 inst_CLK_030_H Reg ; S6=1 S9=1 +Node 190 SM_AMIGA_5_ Reg ; S6=0 S9=1 +Node 109 SM_AMIGA_4_ Reg ; S6=0 S9=1 +Node 107 SM_AMIGA_3_ Reg ; S6=0 S9=1 +Node 103 SM_AMIGA_2_ Reg ; S6=0 S9=1 +Node 188 cpu_est_0_ Reg ; S6=0 S9=1 +Node 184 cpu_est_1_ Reg ; S6=0 S9=1 +Node 187 cpu_est_2_ Reg ; S6=0 S9=1 ; Unused Pins & Nodes ; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index eb507f2..c095a36 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Sun Jun 01 01:03:29 2014 -End : Sun Jun 01 01:03:29 2014 $$$ Elapsed time: 00:00:00 +Start: Sat Jun 07 23:03:24 2014 +End : Sat Jun 07 23:03:24 2014 $$$ Elapsed time: 00:00:00 =========================================================================== Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] @@ -21,16 +21,16 @@ Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030 | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 4 | 4 => 100% | 8 | 7 => 87% | 33 | 17 => 51% - 1 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 24 => 72% - 2 | 16 | 5 | 5 => 100% | 8 | 8 => 100% | 33 | 22 => 66% - 3 | 16 | 11 | 11 => 100% | 8 | 8 => 100% | 33 | 29 => 87% + 0 | 16 | 6 | 6 => 100% | 8 | 7 => 87% | 33 | 23 => 69% + 1 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 22 => 66% + 2 | 16 | 2 | 2 => 100% | 8 | 8 => 100% | 33 | 1 => 3% + 3 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 29 => 87% 4 | 16 | 3 | 3 => 100% | 8 | 3 => 37% | 33 | 17 => 51% 5 | 16 | 0 | 0 => n/a | 8 | 4 => 50% | 33 | 0 => 0% - 6 | 16 | 8 | 8 => 100% | 8 | 7 => 87% | 33 | 21 => 63% - 7 | 16 | 13 | 13 => 100% | 8 | 8 => 100% | 33 | 27 => 81% + 6 | 16 | 8 | 8 => 100% | 8 | 7 => 87% | 33 | 27 => 81% + 7 | 16 | 13 | 13 => 100% | 8 | 8 => 100% | 33 | 28 => 84% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 22.43 => 67% + | Avg number of array inputs in used blocks : 21.00 => 63% * Input/Clock Signal count: 29 -> placed: 29 = 100% @@ -42,12 +42,12 @@ _|____|____|____|_______________|____|_____________|___|________________ Clock/Input Pins : 4 4 => 100% Logic Blocks : 8 7 => 87% Macrocells : 128 54 => 42% - PT Clusters : 128 39 => 30% + PT Clusters : 128 40 => 31% - Single PT Clusters : 128 22 => 17% Input Registers : 0 * Routing Completion: 100% -* Attempts: Place [ 98] Route [ 0] +* Attempts: Place [ 97] Route [ 0] =========================================================================== Signal Fanout Table =========================================================================== @@ -61,17 +61,16 @@ ___|__|__|____|____________________________________________________________ 2| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR 3| 3|OUT| 34|=> ....|....| AMIGA_BUS_ENABLE 4| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW - 5| 3| IO| 33|=> 0...|4.67| AS_000 + 5| 3| IO| 33|=> 01..|4.67| AS_000 |=> Paired w/: RN_AS_000 - 6| 7| IO| 82|=> ..23|...7| AS_030 + 6| 7| IO| 82|=> ...3|..67| AS_030 |=> Paired w/: RN_AS_030 7| 0|OUT| 92|=> ....|....| AVEC - 8| 2| IO| 22|=> ....|....| AVEC_EXP - |=> Paired w/: RN_AVEC_EXP - 9| 0|INP| 96|=> ..2.|...7| A_16_ - 10| 5|INP| 59|=> ..2.|...7| A_17_ - 11| 0|INP| 95|=> ..2.|...7| A_18_ - 12| 0|INP| 97|=> ..2.|...7| A_19_ + 8| 2|OUT| 22|=> ....|....| AVEC_EXP + 9| 0|INP| 96|=> ....|...7| A_16_ + 10| 5|INP| 59|=> ....|...7| A_17_ + 11| 0|INP| 95|=> ....|...7| A_18_ + 12| 0|INP| 97|=> ....|...7| A_19_ 13| 0|INP| 93|=> ....|4...| A_20_ 14| 0|INP| 94|=> ....|4...| A_21_ 15| 7|INP| 85|=> ....|4...| A_22_ @@ -85,15 +84,15 @@ ___|__|__|____|____________________________________________________________ 23| 1|INP| 5|=> ....|4...| A_30_ 24| 1|INP| 4|=> ....|4...| A_31_ 25| 4|OUT| 41|=> ....|....| BERR - 26| 3|INP| 28|=> ..2.|...7| BGACK_000 + 26| 3|INP| 28|=> ....|...7| BGACK_000 27| 7| IO| 83|=> ....|....| BGACK_030 |=> Paired w/: RN_BGACK_030 28| 3| IO| 29|=> ....|....| BG_000 |=> Paired w/: RN_BG_000 29| 2|INP| 21|=> ...3|....| BG_030 30| 4|OUT| 47|=> ....|....| CIIN - 31| +|INP| 11|=> ...3|....| CLK_000 - 32| +|INP| 64|=> 0.2.|...7| CLK_030 + 31| +|INP| 11|=> ...3|...7| CLK_000 + 32| +|INP| 64|=> 01..|..67| CLK_030 33| 6|OUT| 65|=> ....|....| CLK_DIV_OUT 34| 1|OUT| 10|=> ....|....| CLK_EXP 35| +|Cin| 61|=> ....|....| CLK_OSZI @@ -101,11 +100,11 @@ ___|__|__|____|____________________________________________________________ |=> Paired w/: RN_DSACK1 37| 0| IO| 98|=> ...3|....| DS_030 |=> Paired w/: RN_DS_030 - 38| 3| IO| 30|=> ....|...7| DTACK + 38| 3| IO| 30|=> .1..|....| DTACK 39| 6| IO| 66|=> ....|....| E |=> Paired w/: RN_E - 40| 5|INP| 57|=> ..2.|...7| FC_0_ - 41| 5|INP| 58|=> ..2.|...7| FC_1_ + 40| 5|INP| 57|=> ....|...7| FC_0_ + 41| 5|INP| 58|=> ....|...7| FC_1_ 42| 7| IO| 78|=> ....|....| FPU_CS |=> Paired w/: RN_FPU_CS 43| 1| IO| 8|=> ....|....| IPL_030_0_ @@ -117,74 +116,72 @@ ___|__|__|____|____________________________________________________________ 46| 6|INP| 67|=> .1..|....| IPL_0_ 47| 5|INP| 56|=> .1..|....| IPL_1_ 48| 6|INP| 68|=> .1..|....| IPL_2_ - 49| 3| IO| 31|=> 0...|..67| LDS_000 + 49| 3| IO| 31|=> 01..|..67| LDS_000 |=> Paired w/: RN_LDS_000 50| 1|OUT| 3|=> ....|....| RESET 51| 3|NOD| . |=> ...3|....| RN_AS_000 |=> Paired w/: AS_000 - 52| 7|NOD| . |=> 0..3|..67| RN_AS_030 + 52| 7|NOD| . |=> 01.3|..67| RN_AS_030 |=> Paired w/: AS_030 - 53| 2|NOD| . |=> ..23|....| RN_AVEC_EXP - |=> Paired w/: AVEC_EXP - 54| 7|NOD| . |=> 0.23|4.67| RN_BGACK_030 + 53| 7|NOD| . |=> 01.3|4.67| RN_BGACK_030 |=> Paired w/: BGACK_030 - 55| 3|NOD| . |=> ...3|....| RN_BG_000 + 54| 3|NOD| . |=> ...3|....| RN_BG_000 |=> Paired w/: BG_000 - 56| 7|NOD| . |=> ....|...7| RN_DSACK1 + 55| 7|NOD| . |=> ....|...7| RN_DSACK1 |=> Paired w/: DSACK1 - 57| 0|NOD| . |=> 0...|....| RN_DS_030 + 56| 0|NOD| . |=> 0...|....| RN_DS_030 |=> Paired w/: DS_030 - 58| 6|NOD| . |=> .1.3|..6.| RN_E + 57| 6|NOD| . |=> 0..3|..6.| RN_E |=> Paired w/: E - 59| 7|NOD| . |=> ....|4..7| RN_FPU_CS + 58| 7|NOD| . |=> ....|4..7| RN_FPU_CS |=> Paired w/: FPU_CS - 60| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + 59| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ |=> Paired w/: IPL_030_0_ - 61| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + 60| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ |=> Paired w/: IPL_030_1_ - 62| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + 61| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ |=> Paired w/: IPL_030_2_ - 63| 3|NOD| . |=> ...3|....| RN_LDS_000 + 62| 3|NOD| . |=> ...3|....| RN_LDS_000 |=> Paired w/: LDS_000 - 64| 3|NOD| . |=> ...3|....| RN_UDS_000 + 63| 3|NOD| . |=> ...3|....| RN_UDS_000 |=> Paired w/: UDS_000 - 65| 3|NOD| . |=> ...3|..6.| RN_VMA + 64| 3|NOD| . |=> 0..3|....| RN_VMA |=> Paired w/: VMA - 66| +|INP| 86|=> 0123|..67| RST - 67| 6| IO| 71|=> 0..3|4...| RW - 68| 7| IO| 80|=> 0...|....| RW_000 - 69| 6| IO| 70|=> ...3|....| SIZE_0_ - 70| 7| IO| 79|=> ...3|....| SIZE_1_ - 71| 0|NOD| . |=> 01..|....| SM_AMIGA_0_ - 72| 7|NOD| . |=> 0...|...7| SM_AMIGA_1_ - 73| 6|NOD| . |=> ..2.|..67| SM_AMIGA_2_ - 74| 6|NOD| . |=> ....|..6.| SM_AMIGA_3_ - 75| 3|NOD| . |=> ...3|..6.| SM_AMIGA_4_ - 76| 1|NOD| . |=> .1.3|....| SM_AMIGA_5_ - 77| 1|NOD| . |=> 01..|....| SM_AMIGA_6_ - 78| 1|NOD| . |=> .123|....| SM_AMIGA_7_ - 79| 3| IO| 32|=> 0...|..67| UDS_000 + 65| +|INP| 86|=> 01.3|..67| RST + 66| 6| IO| 71|=> ...3|4.6.| RW + 67| 7| IO| 80|=> 0...|..6.| RW_000 + 68| 6| IO| 70|=> ...3|....| SIZE_0_ + 69| 7| IO| 79|=> ...3|....| SIZE_1_ + 70| 7|NOD| . |=> ....|..67| SM_AMIGA_0_ + 71| 1|NOD| . |=> .1..|..67| SM_AMIGA_1_ + 72| 0|NOD| . |=> 01..|....| SM_AMIGA_2_ + 73| 0|NOD| . |=> 0...|....| SM_AMIGA_3_ + 74| 0|NOD| . |=> 0...|....| SM_AMIGA_4_ + 75| 3|NOD| . |=> 0..3|....| SM_AMIGA_5_ + 76| 6|NOD| . |=> ...3|..6.| SM_AMIGA_6_ + 77| 7|NOD| . |=> ...3|..67| SM_AMIGA_7_ + 78| 3| IO| 32|=> 01..|..67| UDS_000 |=> Paired w/: RN_UDS_000 - 80| 3| IO| 35|=> ....|....| VMA + 79| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 81| +|INP| 36|=> ....|...7| VPA - 82| 2|NOD| . |=> .123|..6.| cpu_est_0_ - 83| 1|NOD| . |=> .1.3|..6.| cpu_est_1_ - 84| 6|NOD| . |=> .1.3|..6.| cpu_est_2_ - 85| 2|NOD| . |=> .12.|....| inst_AS_030_000_SYNC - 86| 3|NOD| . |=> ..2.|....| inst_BGACK_030_INT_D - 87| 3|NOD| . |=> 0123|..67| inst_CLK_000_D0 - 88| 3|NOD| . |=> .12.|..67| inst_CLK_000_D1 - 89| 7|NOD| . |=> .123|....| inst_CLK_000_D2 - 90| 2|NOD| . |=> .12.|....| inst_CLK_000_D3 - 91| 7|NOD| . |=> 0...|...7| inst_CLK_030_H - 92| 1|NOD| . |=> .1..|..6.| inst_CLK_OUT_PRE_25 - 93| 7|NOD| . |=> .1..|...7| inst_CLK_OUT_PRE_50 - 94| 7|NOD| . |=> .1..|....| inst_CLK_OUT_PRE_50_D - 95| 7|NOD| . |=> ....|..6.| inst_DTACK_D0 - 96| 0|NOD| . |=> 0...|..67| inst_RW_000_INT - 97| 7|NOD| . |=> ...3|..6.| inst_VPA_D - 98| +|INP| 14|=> 0123|4.67| nEXP_SPACE + 80| +|INP| 36|=> 0...|....| VPA + 81| 3|NOD| . |=> ...3|..6.| cpu_est_0_ + 82| 3|NOD| . |=> 0..3|..6.| cpu_est_1_ + 83| 3|NOD| . |=> ...3|..6.| cpu_est_2_ + 84| 7|NOD| . |=> ....|..67| inst_AS_030_000_SYNC + 85| 1|NOD| . |=> ....|..6.| inst_BGACK_030_INT_D + 86| 7|NOD| . |=> 01.3|..67| inst_CLK_000_D0 + 87| 3|NOD| . |=> 01.3|..67| inst_CLK_000_D1 + 88| 7|NOD| . |=> ....|..67| inst_CLK_000_D2 + 89| 1|NOD| . |=> 01..|....| inst_CLK_030_H + 90| 1|NOD| . |=> .1..|..6.| inst_CLK_OUT_PRE_25 + 91| 7|NOD| . |=> .1..|...7| inst_CLK_OUT_PRE_50 + 92| 7|NOD| . |=> .1..|....| inst_CLK_OUT_PRE_50_D + 93| 1|NOD| . |=> 0...|....| inst_DTACK_D0 + 94| 6|NOD| . |=> ....|..67| inst_RW_000_INT + 95| 0|NOD| . |=> 0..3|....| inst_VPA_D + 96| 6|NOD| . |=> ..23|..6.| inst_avec_expreg + 97| +|INP| 14|=> 0..3|4.67| nEXP_SPACE --------------------------------------------------------------------------- =========================================================================== < C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments > @@ -305,11 +302,11 @@ ____|_____|_________|______________________________________________________ | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| DS_030| IO| | S | 7 | 4 to [ 0]| 1 XOR to [ 0] as logic PT - 1| SM_AMIGA_0_|NOD| | S | 2 | 4 to [ 1]| 1 XOR free + 1| SM_AMIGA_2_|NOD| | S | 3 | 4 to [ 1]| 1 XOR free 2| AVEC|OUT| | S | 1 | 4 to [ 0]| 1 XOR to [ 2] for 1 PT sig - 3|inst_RW_000_INT|NOD| | S |14 | 4 to [ 3]| 1 XOR to [ 3] as logic PT - 4| | ? | | S | | 4 to [ 3]| 1 XOR to [ 3] as logic PT - 5| | ? | | S | | 4 to [ 3]| 1 XOR free + 3| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 4| SM_AMIGA_3_|NOD| | S | 4 | 4 to [ 4]| 1 XOR free + 5| SM_AMIGA_4_|NOD| | S | 2 | 4 to [ 5]| 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| | ? | | S | | 4 free | 1 XOR free @@ -332,11 +329,11 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| DS_030| IO| | S | 7 |=> can support up to [ 9] logic PT(s) - 1| SM_AMIGA_0_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) - 2| AVEC|OUT| | S | 1 |=> can support up to [ 1] logic PT(s) - 3|inst_RW_000_INT|NOD| | S |14 |=> can support up to [ 15] logic PT(s) - 4| | ? | | S | |=> can support up to [ 5] logic PT(s) - 5| | ? | | S | |=> can support up to [ 11] logic PT(s) + 1| SM_AMIGA_2_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) + 2| AVEC|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) + 3| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 4| SM_AMIGA_3_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) + 5| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) 6| | ? | | S | |=> can support up to [ 15] logic PT(s) 7| | ? | | S | |=> can support up to [ 20] logic PT(s) 8| | ? | | S | |=> can support up to [ 20] logic PT(s) @@ -357,11 +354,11 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| DS_030| IO| | => | 5 6 ( 7) 0 | 96 97 ( 98) 91 - 1| SM_AMIGA_0_|NOD| | => | 5 6 7 0 | 96 97 98 91 + 1| SM_AMIGA_2_|NOD| | => | 5 6 7 0 | 96 97 98 91 2| AVEC|OUT| | => | 6 7 0 ( 1)| 97 98 91 ( 92) - 3|inst_RW_000_INT|NOD| | => | 6 7 0 1 | 97 98 91 92 - 4| | | | => | 7 0 1 2 | 98 91 92 93 - 5| | | | => | 7 0 1 2 | 98 91 92 93 + 3| inst_VPA_D|NOD| | => | 6 7 0 1 | 97 98 91 92 + 4| SM_AMIGA_3_|NOD| | => | 7 0 1 2 | 98 91 92 93 + 5| SM_AMIGA_4_|NOD| | => | 7 0 1 2 | 98 91 92 93 6| | | | => | 0 1 2 3 | 91 92 93 94 7| | | | => | 0 1 2 3 | 91 92 93 94 8| | | | => | 1 2 3 4 | 92 93 94 95 @@ -422,17 +419,17 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 91| -| | ] [RegIn 0 |102| -| | ] [MCell 0 |101|NOD RN_DS_030| |*] paired w/[ DS_030] - [MCell 1 |103|NOD SM_AMIGA_0_| |*] + [MCell 1 |103|NOD SM_AMIGA_2_| |*] 1 [IOpin 1 | 92|OUT AVEC|*| ] [RegIn 1 |105| -| | ] [MCell 2 |104|OUT AVEC| | ] - [MCell 3 |106|NOD inst_RW_000_INT| |*] + [MCell 3 |106|NOD inst_VPA_D| |*] 2 [IOpin 2 | 93|INP A_20_|*|*] [RegIn 2 |108| -| | ] - [MCell 4 |107| -| | ] - [MCell 5 |109| -| | ] + [MCell 4 |107|NOD SM_AMIGA_3_| |*] + [MCell 5 |109|NOD SM_AMIGA_4_| |*] 3 [IOpin 3 | 94|INP A_21_|*|*] [RegIn 3 |111| -| | ] @@ -466,34 +463,34 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST -Mux01| ... | ... -Mux02| ... | ... -Mux03| ... | ... +Mux01| Mcel 0 4 ( 107)| SM_AMIGA_3_ +Mux02| Mcel 0 5 ( 109)| SM_AMIGA_4_ +Mux03| Mcel 3 11 ( 190)| SM_AMIGA_5_ Mux04| Input Pin ( 64)| CLK_030 Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| Mcel 1 9 ( 139)| SM_AMIGA_6_ -Mux07| Mcel 7 7 ( 280)| SM_AMIGA_1_ -Mux08| IOPin 6 6 ( 71)| RW -Mux09| Mcel 0 1 ( 103)| SM_AMIGA_0_ -Mux10| ... | ... -Mux11| Mcel 3 5 ( 181)| inst_CLK_000_D0 +Mux06| IOPin 7 5 ( 80)| RW_000 +Mux07| Mcel 3 5 ( 181)| inst_CLK_000_D1 +Mux08| Mcel 1 8 ( 137)| inst_DTACK_D0 +Mux09| Mcel 0 1 ( 103)| SM_AMIGA_2_ +Mux10| Input Pin ( 36)| VPA +Mux11| Mcel 7 3 ( 274)| inst_CLK_000_D0 Mux12| IOPin 3 3 ( 32)| UDS_000 -Mux13| Mcel 7 5 ( 277)| inst_CLK_030_H +Mux13| Mcel 3 7 ( 184)| cpu_est_1_ Mux14| ... | ... Mux15| Mcel 0 0 ( 101)| RN_DS_030 Mux16| ... | ... -Mux17| ... | ... +Mux17| Mcel 3 1 ( 175)| RN_VMA Mux18| ... | ... Mux19| ... | ... Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 Mux21| Mcel 7 6 ( 278)| RN_AS_030 Mux22| ... | ... -Mux23| IOPin 3 2 ( 33)| AS_000 +Mux23| Mcel 6 2 ( 248)| RN_E Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| Mcel 0 3 ( 106)| inst_RW_000_INT -Mux26| ... | ... +Mux25| Mcel 0 3 ( 106)| inst_VPA_D +Mux26| IOPin 3 2 ( 33)| AS_000 Mux27| ... | ... -Mux28| IOPin 7 5 ( 80)| RW_000 +Mux28| Mcel 1 5 ( 133)| inst_CLK_030_H Mux29| ... | ... Mux30| ... | ... Mux31| ... | ... @@ -512,13 +509,13 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| RESET|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig 2| IPL_030_2_| IO| | S | 3 | 4 to [ 2]| 1 XOR free - 3| cpu_est_1_|NOD| | S | 4 | 4 to [ 3]| 1 XOR free + 3| SM_AMIGA_1_|NOD| | S | 2 | 4 to [ 3]| 1 XOR free 4| IPL_030_0_| IO| | S | 3 | 4 to [ 4]| 1 XOR free - 5| SM_AMIGA_7_|NOD| | S | 4 | 4 to [ 5]| 1 XOR free + 5|inst_CLK_030_H|NOD| | S | 5 | 4 to [ 5]| 1 XOR to [ 5] as logic PT 6| IPL_030_1_| IO| | S | 3 | 4 to [ 6]| 1 XOR free 7|inst_CLK_OUT_PRE_25|NOD| | S | 3 | 4 to [ 7]| 1 XOR free - 8| SM_AMIGA_5_|NOD| | S | 2 | 4 to [ 8]| 1 XOR free - 9| SM_AMIGA_6_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free + 8| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| | ? | | S | | 4 free | 1 XOR free @@ -539,14 +536,14 @@ _|_________________|__|__|___|_____|_______________________________________ 0| CLK_EXP|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) 1| RESET|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) 2| IPL_030_2_| IO| | S | 3 |=> can support up to [ 9] logic PT(s) - 3| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) + 3| SM_AMIGA_1_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) 4| IPL_030_0_| IO| | S | 3 |=> can support up to [ 5] logic PT(s) - 5| SM_AMIGA_7_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) - 6| IPL_030_1_| IO| | S | 3 |=> can support up to [ 5] logic PT(s) - 7|inst_CLK_OUT_PRE_25|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) - 8| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) - 9| SM_AMIGA_6_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) -10| | ? | | S | |=> can support up to [ 15] logic PT(s) + 5|inst_CLK_030_H|NOD| | S | 5 |=> can support up to [ 5] logic PT(s) + 6| IPL_030_1_| IO| | S | 3 |=> can support up to [ 9] logic PT(s) + 7|inst_CLK_OUT_PRE_25|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) + 8| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 9|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 19] logic PT(s) 11| | ? | | S | |=> can support up to [ 20] logic PT(s) 12| | ? | | S | |=> can support up to [ 20] logic PT(s) 13| | ? | | S | |=> can support up to [ 20] logic PT(s) @@ -564,13 +561,13 @@ _|_________________|__|_____|____________________|________________________ 0| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) 1| RESET|OUT| | => | 5 6 ( 7) 0 | 5 4 ( 3) 10 2| IPL_030_2_| IO| | => | 6 7 0 ( 1)| 4 3 10 ( 9) - 3| cpu_est_1_|NOD| | => | 6 7 0 1 | 4 3 10 9 + 3| SM_AMIGA_1_|NOD| | => | 6 7 0 1 | 4 3 10 9 4| IPL_030_0_| IO| | => | 7 0 1 ( 2)| 3 10 9 ( 8) - 5| SM_AMIGA_7_|NOD| | => | 7 0 1 2 | 3 10 9 8 + 5|inst_CLK_030_H|NOD| | => | 7 0 1 2 | 3 10 9 8 6| IPL_030_1_| IO| | => | 0 1 2 ( 3)| 10 9 8 ( 7) 7|inst_CLK_OUT_PRE_25|NOD| | => | 0 1 2 3 | 10 9 8 7 - 8| SM_AMIGA_5_|NOD| | => | 1 2 3 4 | 9 8 7 6 - 9| SM_AMIGA_6_|NOD| | => | 1 2 3 4 | 9 8 7 6 + 8| inst_DTACK_D0|NOD| | => | 1 2 3 4 | 9 8 7 6 + 9|inst_BGACK_030_INT_D|NOD| | => | 1 2 3 4 | 9 8 7 6 10| | | | => | 2 3 4 5 | 8 7 6 5 11| | | | => | 2 3 4 5 | 8 7 6 5 12| | | | => | 3 4 5 6 | 7 6 5 4 @@ -634,12 +631,12 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_] [RegIn 1 |129| -| | ] [MCell 2 |128|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] - [MCell 3 |130|NOD cpu_est_1_| |*] + [MCell 3 |130|NOD SM_AMIGA_1_| |*] 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] [RegIn 2 |132| -| | ] [MCell 4 |131|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] - [MCell 5 |133|NOD SM_AMIGA_7_| |*] + [MCell 5 |133|NOD inst_CLK_030_H| |*] 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] @@ -648,8 +645,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 6|INP A_29_|*|*] [RegIn 4 |138| -| | ] - [MCell 8 |137|NOD SM_AMIGA_5_| |*] - [MCell 9 |139|NOD SM_AMIGA_6_| |*] + [MCell 8 |137|NOD inst_DTACK_D0| |*] + [MCell 9 |139|NOD inst_BGACK_030_INT_D| |*] 5 [IOpin 5 | 5|INP A_30_|*|*] [RegIn 5 |141| -| | ] @@ -672,37 +669,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| Mcel 1 7 ( 136)| inst_CLK_OUT_PRE_25 +Mux00| IOPin 3 4 ( 31)| LDS_000 +Mux01| Mcel 7 11 ( 286)| inst_CLK_OUT_PRE_50 Mux02| Mcel 1 6 ( 134)| RN_IPL_030_1_ Mux03| IOPin 5 4 ( 56)| IPL_1_ Mux04| IOPin 6 3 ( 68)| IPL_2_ -Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| Mcel 1 9 ( 139)| SM_AMIGA_6_ -Mux07| Mcel 3 5 ( 181)| inst_CLK_000_D0 -Mux08| Mcel 3 7 ( 184)| inst_CLK_000_D1 -Mux09| Mcel 0 1 ( 103)| SM_AMIGA_0_ +Mux05| Mcel 1 3 ( 130)| SM_AMIGA_1_ +Mux06| ... | ... +Mux07| Mcel 3 5 ( 181)| inst_CLK_000_D1 +Mux08| Mcel 7 12 ( 287)| inst_CLK_OUT_PRE_50_D +Mux09| Mcel 0 1 ( 103)| SM_AMIGA_2_ Mux10| Mcel 1 2 ( 128)| RN_IPL_030_2_ -Mux11| Mcel 7 9 ( 283)| inst_CLK_OUT_PRE_50 -Mux12| Mcel 2 3 ( 154)| inst_AS_030_000_SYNC -Mux13| Mcel 1 3 ( 130)| cpu_est_1_ -Mux14| Mcel 2 4 ( 155)| inst_CLK_000_D3 -Mux15| Mcel 7 12 ( 287)| inst_CLK_OUT_PRE_50_D +Mux11| Mcel 7 3 ( 274)| inst_CLK_000_D0 +Mux12| IOPin 3 3 ( 32)| UDS_000 +Mux13| ... | ... +Mux14| IOPin 3 5 ( 30)| DTACK +Mux15| ... | ... Mux16| IOPin 6 2 ( 67)| IPL_0_ -Mux17| Mcel 1 8 ( 137)| SM_AMIGA_5_ -Mux18| Mcel 7 3 ( 274)| inst_CLK_000_D2 +Mux17| ... | ... +Mux18| ... | ... Mux19| ... | ... -Mux20| ... | ... -Mux21| Mcel 6 4 ( 251)| cpu_est_2_ -Mux22| Mcel 2 2 ( 152)| cpu_est_0_ -Mux23| Mcel 6 2 ( 248)| RN_E -Mux24| ... | ... +Mux20| Input Pin ( 64)| CLK_030 +Mux21| Input Pin ( 86)| RST +Mux22| ... | ... +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux24| Mcel 1 7 ( 136)| inst_CLK_OUT_PRE_25 Mux25| ... | ... -Mux26| ... | ... +Mux26| IOPin 3 2 ( 33)| AS_000 Mux27| Mcel 1 4 ( 131)| RN_IPL_030_0_ -Mux28| Mcel 1 5 ( 133)| SM_AMIGA_7_ +Mux28| Mcel 1 5 ( 133)| inst_CLK_030_H Mux29| ... | ... -Mux30| ... | ... +Mux30| Mcel 7 6 ( 278)| RN_AS_030 Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- @@ -716,11 +713,11 @@ Mux32| ... | ... | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| AVEC_EXP| IO| | S | 3 | 4 to [ 0]| 1 XOR free + 0| AVEC_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| cpu_est_0_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free - 3|inst_AS_030_000_SYNC|NOD| | S | 8 | 4 to [ 3]| 1 XOR to [ 3] as logic PT - 4|inst_CLK_000_D3|NOD| | S | 1 | 4 to [ 3]| 1 XOR to [ 4] for 1 PT sig + 2| | ? | | S | | 4 free | 1 XOR free + 3| | ? | | S | | 4 free | 1 XOR free + 4| | ? | | S | | 4 free | 1 XOR free 5| | ? | | S | | 4 free | 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free @@ -743,12 +740,12 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| AVEC_EXP| IO| | S | 3 |=> can support up to [ 9] logic PT(s) - 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) - 2| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) - 3|inst_AS_030_000_SYNC|NOD| | S | 8 |=> can support up to [ 14] logic PT(s) - 4|inst_CLK_000_D3|NOD| | S | 1 |=> can support up to [ 11] logic PT(s) - 5| | ? | | S | |=> can support up to [ 15] logic PT(s) + 0| AVEC_EXP|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) + 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) + 2| | ? | | S | |=> can support up to [ 19] logic PT(s) + 3| | ? | | S | |=> can support up to [ 20] logic PT(s) + 4| | ? | | S | |=> can support up to [ 20] logic PT(s) + 5| | ? | | S | |=> can support up to [ 20] logic PT(s) 6| | ? | | S | |=> can support up to [ 20] logic PT(s) 7| | ? | | S | |=> can support up to [ 20] logic PT(s) 8| | ? | | S | |=> can support up to [ 20] logic PT(s) @@ -768,11 +765,11 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 2] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| AVEC_EXP| IO| | => | 5 6 ( 7) 0 | 20 21 ( 22) 15 + 0| AVEC_EXP|OUT| | => | 5 6 ( 7) 0 | 20 21 ( 22) 15 1|AMIGA_BUS_ENABLE_LOW|OUT| | => |( 5) 6 7 0 |( 20) 21 22 15 - 2| cpu_est_0_|NOD| | => | 6 7 0 1 | 21 22 15 16 - 3|inst_AS_030_000_SYNC|NOD| | => | 6 7 0 1 | 21 22 15 16 - 4|inst_CLK_000_D3|NOD| | => | 7 0 1 2 | 22 15 16 17 + 2| | | | => | 6 7 0 1 | 21 22 15 16 + 3| | | | => | 6 7 0 1 | 21 22 15 16 + 4| | | | => | 7 0 1 2 | 22 15 16 17 5| | | | => | 7 0 1 2 | 22 15 16 17 6| | | | => | 0 1 2 3 | 15 16 17 18 7| | | | => | 0 1 2 3 | 15 16 17 18 @@ -801,7 +798,7 @@ _|_________________|__|___|_____|___________________________________________ 4| A_24_|INP|*| 19| => | 8 9 10 11 12 13 14 15 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | 10 11 12 13 14 15 0 ( 1) 6| BG_030|INP|*| 21| => | 12 13 14 15 0 1 2 3 - 7| AVEC_EXP| IO|*| 22| => | 14 15 ( 0) 1 2 3 4 5 + 7| AVEC_EXP|OUT|*| 22| => | 14 15 ( 0) 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > IO/Node and IO/Input Macrocell Pairing Table @@ -819,8 +816,7 @@ _|_________________|__|___|_____|__________________________________________ 4| A_24_|INP|*| 19| => | Input macrocell [ -] 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | Input macrocell [ -] 6| BG_030|INP|*| 21| => | Input macrocell [ -] - 7| AVEC_EXP| IO|*| 22| => | Input macrocell [ -] - | | | | | | IO paired w/ node [ RN_AVEC_EXP] + 7| AVEC_EXP|OUT|*| 22| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Input Multiplexer (IMX) Assignments @@ -833,17 +829,17 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 15|INP A_28_|*|*] [RegIn 0 |150| -| | ] - [MCell 0 |149|NOD RN_AVEC_EXP| |*] paired w/[ AVEC_EXP] + [MCell 0 |149|OUT AVEC_EXP| | ] [MCell 1 |151|OUT AMIGA_BUS_ENABLE_LOW| | ] 1 [IOpin 1 | 16|INP A_27_|*|*] [RegIn 1 |153| -| | ] - [MCell 2 |152|NOD cpu_est_0_| |*] - [MCell 3 |154|NOD inst_AS_030_000_SYNC| |*] + [MCell 2 |152| -| | ] + [MCell 3 |154| -| | ] 2 [IOpin 2 | 17|INP A_26_|*|*] [RegIn 2 |156| -| | ] - [MCell 4 |155|NOD inst_CLK_000_D3| |*] + [MCell 4 |155| -| | ] [MCell 5 |157| -| | ] 3 [IOpin 3 | 18|INP A_25_|*|*] @@ -866,7 +862,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number [MCell 12 |167| -| | ] [MCell 13 |169| -| | ] - 7 [IOpin 7 | 22| IO AVEC_EXP|*| ] paired w/[ RN_AVEC_EXP] + 7 [IOpin 7 | 22|OUT AVEC_EXP|*| ] [RegIn 7 |171| -| | ] [MCell 14 |170| -| | ] [MCell 15 |172| -| | ] @@ -877,35 +873,35 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| IOPin 5 2 ( 58)| FC_1_ -Mux02| Mcel 3 10 ( 188)| inst_BGACK_030_INT_D -Mux03| Mcel 6 5 ( 253)| SM_AMIGA_2_ -Mux04| Mcel 2 3 ( 154)| inst_AS_030_000_SYNC -Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| IOPin 5 3 ( 57)| FC_0_ -Mux07| Mcel 3 5 ( 181)| inst_CLK_000_D0 -Mux08| IOPin 5 1 ( 59)| A_17_ -Mux09| Mcel 2 0 ( 149)| RN_AVEC_EXP -Mux10| Mcel 7 3 ( 274)| inst_CLK_000_D2 -Mux11| IOPin 0 5 ( 96)| A_16_ -Mux12| IOPin 0 6 ( 97)| A_19_ -Mux13| Mcel 3 7 ( 184)| inst_CLK_000_D1 -Mux14| Mcel 2 4 ( 155)| inst_CLK_000_D3 +Mux00| ... | ... +Mux01| ... | ... +Mux02| Mcel 6 4 ( 251)| inst_avec_expreg +Mux03| ... | ... +Mux04| ... | ... +Mux05| ... | ... +Mux06| ... | ... +Mux07| ... | ... +Mux08| ... | ... +Mux09| ... | ... +Mux10| ... | ... +Mux11| ... | ... +Mux12| ... | ... +Mux13| ... | ... +Mux14| ... | ... Mux15| ... | ... Mux16| ... | ... -Mux17| IOPin 0 4 ( 95)| A_18_ -Mux18| IOPin 3 7 ( 28)| BGACK_000 -Mux19| IOPin 7 3 ( 82)| AS_030 -Mux20| Input Pin ( 64)| CLK_030 +Mux17| ... | ... +Mux18| ... | ... +Mux19| ... | ... +Mux20| ... | ... Mux21| ... | ... -Mux22| Mcel 2 2 ( 152)| cpu_est_0_ -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux22| ... | ... +Mux23| ... | ... Mux24| ... | ... Mux25| ... | ... Mux26| ... | ... Mux27| ... | ... -Mux28| Mcel 1 5 ( 133)| SM_AMIGA_7_ +Mux28| ... | ... Mux29| ... | ... Mux30| ... | ... Mux31| ... | ... @@ -926,15 +922,15 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 2| BG_000| IO| | S | 2 | 4 to [ 2]| 1 XOR free 3|AMIGA_BUS_ENABLE|OUT| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig 4| AS_000| IO| | S | 2 | 4 to [ 4]| 1 XOR free - 5|inst_CLK_000_D0|NOD| | S | 1 | 4 to [ 6]| 1 XOR to [ 5] for 1 PT sig + 5|inst_CLK_000_D1|NOD| | S | 1 | 4 to [ 6]| 1 XOR to [ 5] for 1 PT sig 6| UDS_000| IO| | S | 7 | 4 to [ 6]| 1 XOR to [ 6] as logic PT - 7|inst_CLK_000_D1|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 7] for 1 PT sig + 7| cpu_est_1_|NOD| | S | 4 | 4 to [ 8]| 1 XOR free 8| LDS_000| IO| | S |11 | 4 to [ 8]| 1 XOR to [ 8] as logic PT - 9| SM_AMIGA_4_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free -10|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [10] for 1 PT sig -11| | ? | | S | | 4 free | 1 XOR free -12| | ? | | S | | 4 free | 1 XOR free -13| | ? | | S | | 4 free | 1 XOR free + 9| cpu_est_2_|NOD| | S | 3 :+: 1| 4 to [ 7]| 1 XOR to [ 9] +10| cpu_est_0_|NOD| | S | 3 | 4 to [ 8]| 1 XOR free +11| SM_AMIGA_5_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free +12| | ? | | S | | 4 to [10]| 1 XOR free +13| | ? | | S | | 4 to [11]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -953,16 +949,16 @@ _|_________________|__|__|___|_____|_______________________________________ 2| BG_000| IO| | S | 2 |=> can support up to [ 9] logic PT(s) 3|AMIGA_BUS_ENABLE|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) 4| AS_000| IO| | S | 2 |=> can support up to [ 9] logic PT(s) - 5|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) + 5|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) 6| UDS_000| IO| | S | 7 |=> can support up to [ 9] logic PT(s) - 7|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) - 8| LDS_000| IO| | S |11 |=> can support up to [ 13] logic PT(s) - 9| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) -10|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 11] logic PT(s) -11| | ? | | S | |=> can support up to [ 15] logic PT(s) -12| | ? | | S | |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 20] logic PT(s) -14| | ? | | S | |=> can support up to [ 15] logic PT(s) + 7| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 4] logic PT(s) + 8| LDS_000| IO| | S |11 |=> can support up to [ 15] logic PT(s) + 9| cpu_est_2_|NOD| | S | 3 :+: 1|=> can support up to [ 5] logic PT(s) +10| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) +11| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) +12| | ? | | S | |=> can support up to [ 6] logic PT(s) +13| | ? | | S | |=> can support up to [ 11] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -978,13 +974,13 @@ _|_________________|__|_____|____________________|________________________ 2| BG_000| IO| | => |( 6) 7 0 1 |( 29) 28 35 34 3|AMIGA_BUS_ENABLE|OUT| | => | 6 7 0 ( 1)| 29 28 35 ( 34) 4| AS_000| IO| | => | 7 0 1 ( 2)| 28 35 34 ( 33) - 5|inst_CLK_000_D0|NOD| | => | 7 0 1 2 | 28 35 34 33 + 5|inst_CLK_000_D1|NOD| | => | 7 0 1 2 | 28 35 34 33 6| UDS_000| IO| | => | 0 1 2 ( 3)| 35 34 33 ( 32) - 7|inst_CLK_000_D1|NOD| | => | 0 1 2 3 | 35 34 33 32 + 7| cpu_est_1_|NOD| | => | 0 1 2 3 | 35 34 33 32 8| LDS_000| IO| | => | 1 2 3 ( 4)| 34 33 32 ( 31) - 9| SM_AMIGA_4_|NOD| | => | 1 2 3 4 | 34 33 32 31 -10|inst_BGACK_030_INT_D|NOD| | => | 2 3 4 5 | 33 32 31 30 -11| | | | => | 2 3 4 5 | 33 32 31 30 + 9| cpu_est_2_|NOD| | => | 1 2 3 4 | 34 33 32 31 +10| cpu_est_0_|NOD| | => | 2 3 4 5 | 33 32 31 30 +11| SM_AMIGA_5_|NOD| | => | 2 3 4 5 | 33 32 31 30 12| | | | => | 3 4 5 6 | 32 31 30 29 13| | | | => | 3 4 5 6 | 32 31 30 29 14| | | | => | 4 5 6 7 | 31 30 29 28 @@ -1053,22 +1049,22 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 33| IO AS_000|*|*] paired w/[ RN_AS_000] [RegIn 2 |180| -| | ] [MCell 4 |179|NOD RN_AS_000| |*] paired w/[ AS_000] - [MCell 5 |181|NOD inst_CLK_000_D0| |*] + [MCell 5 |181|NOD inst_CLK_000_D1| |*] 3 [IOpin 3 | 32| IO UDS_000|*|*] paired w/[ RN_UDS_000] [RegIn 3 |183| -| | ] [MCell 6 |182|NOD RN_UDS_000| |*] paired w/[ UDS_000] - [MCell 7 |184|NOD inst_CLK_000_D1| |*] + [MCell 7 |184|NOD cpu_est_1_| |*] 4 [IOpin 4 | 31| IO LDS_000|*|*] paired w/[ RN_LDS_000] [RegIn 4 |186| -| | ] [MCell 8 |185|NOD RN_LDS_000| |*] paired w/[ LDS_000] - [MCell 9 |187|NOD SM_AMIGA_4_| |*] + [MCell 9 |187|NOD cpu_est_2_| |*] 5 [IOpin 5 | 30| IO DTACK|*|*] [RegIn 5 |189| -| | ] - [MCell 10 |188|NOD inst_BGACK_030_INT_D| |*] - [MCell 11 |190| -| | ] + [MCell 10 |188|NOD cpu_est_0_| |*] + [MCell 11 |190|NOD SM_AMIGA_5_| |*] 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] [RegIn 6 |192| -| | ] @@ -1086,38 +1082,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 4 ( 69)| A0 +Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 Mux01| ... | ... -Mux02| Mcel 6 4 ( 251)| cpu_est_2_ -Mux03| Input Pin ( 11)| CLK_000 -Mux04| IOPin 2 6 ( 21)| BG_030 +Mux02| Mcel 6 4 ( 251)| inst_avec_expreg +Mux03| Mcel 3 2 ( 176)| RN_BG_000 +Mux04| Mcel 7 5 ( 277)| SM_AMIGA_7_ Mux05| IOPin 0 7 ( 98)| DS_030 Mux06| IOPin 7 6 ( 79)| SIZE_1_ Mux07| Mcel 7 6 ( 278)| RN_AS_030 -Mux08| Mcel 1 8 ( 137)| SM_AMIGA_5_ -Mux09| Mcel 2 0 ( 149)| RN_AVEC_EXP -Mux10| Mcel 3 4 ( 179)| RN_AS_000 -Mux11| Mcel 7 3 ( 274)| inst_CLK_000_D2 -Mux12| Mcel 3 9 ( 187)| SM_AMIGA_4_ -Mux13| Mcel 1 3 ( 130)| cpu_est_1_ -Mux14| IOPin 6 5 ( 70)| SIZE_0_ +Mux08| IOPin 6 6 ( 71)| RW +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 7 3 ( 274)| inst_CLK_000_D0 +Mux11| Mcel 3 5 ( 181)| inst_CLK_000_D1 +Mux12| Mcel 3 9 ( 187)| cpu_est_2_ +Mux13| Mcel 3 7 ( 184)| cpu_est_1_ +Mux14| Mcel 3 4 ( 179)| RN_AS_000 Mux15| Input Pin ( 14)| nEXP_SPACE Mux16| Mcel 3 8 ( 185)| RN_LDS_000 -Mux17| Mcel 3 1 ( 175)| RN_VMA -Mux18| Mcel 7 10 ( 284)| inst_VPA_D -Mux19| IOPin 7 3 ( 82)| AS_030 -Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux17| IOPin 6 5 ( 70)| SIZE_0_ +Mux18| IOPin 6 4 ( 69)| A0 +Mux19| Mcel 3 11 ( 190)| SM_AMIGA_5_ +Mux20| Mcel 3 10 ( 188)| cpu_est_0_ Mux21| Input Pin ( 86)| RST -Mux22| Mcel 2 2 ( 152)| cpu_est_0_ -Mux23| Mcel 6 2 ( 248)| RN_E -Mux24| Mcel 3 5 ( 181)| inst_CLK_000_D0 -Mux25| IOPin 6 6 ( 71)| RW +Mux22| IOPin 2 6 ( 21)| BG_030 +Mux23| Mcel 6 6 ( 254)| SM_AMIGA_6_ +Mux24| Input Pin ( 11)| CLK_000 +Mux25| Mcel 0 3 ( 106)| inst_VPA_D Mux26| ... | ... -Mux27| ... | ... -Mux28| Mcel 3 2 ( 176)| RN_BG_000 +Mux27| Mcel 3 1 ( 175)| RN_VMA +Mux28| ... | ... Mux29| ... | ... Mux30| Mcel 3 6 ( 182)| RN_UDS_000 -Mux31| Mcel 1 5 ( 133)| SM_AMIGA_7_ +Mux31| Mcel 6 2 ( 248)| RN_E Mux32| IOPin 7 4 ( 81)| DSACK1 --------------------------------------------------------------------------- =========================================================================== @@ -1422,12 +1418,12 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| RW| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| SIZE_0_| IO| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig 2| E| IO| | S | 3 :+: 1| 4 to [ 2]| 1 XOR to [ 2] - 3| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig - 4| cpu_est_2_|NOD| | S | 3 :+: 1| 4 to [ 4]| 1 XOR to [ 4] - 5| SM_AMIGA_2_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free - 6| SM_AMIGA_3_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free - 7| | ? | | S | | 4 free | 1 XOR free - 8| A0| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 3| CLK_DIV_OUT|OUT| | S | 1 | 4 to [ 4]| 1 XOR to [ 3] for 1 PT sig + 4|inst_avec_expreg|NOD| | S | 6 | 4 to [ 4]| 1 XOR to [ 4] as logic PT + 5|inst_RW_000_INT|NOD| | S |14 | 4 to [ 5]| 1 XOR to [ 5] as logic PT + 6| SM_AMIGA_6_|NOD| | S | 2 | 4 to [ 5]| 1 XOR to [ 5] as logic PT + 7| | ? | | S | | 4 to [ 5]| 1 XOR free + 8| A0| IO| | S | 1 | 4 to [ 6]| 1 XOR to [ 8] for 1 PT sig 9| | ? | | S | | 4 free | 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free @@ -1447,15 +1443,15 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| RW| IO| | S | 1 |=> can support up to [ 9] logic PT(s) - 1| SIZE_0_| IO| | S | 1 |=> can support up to [ 13] logic PT(s) - 2| E| IO| | S | 3 :+: 1|=> can support up to [ 12] logic PT(s) - 3| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) - 4| cpu_est_2_|NOD| | S | 3 :+: 1|=> can support up to [ 8] logic PT(s) - 5| SM_AMIGA_2_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) - 6| SM_AMIGA_3_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) - 7| | ? | | S | |=> can support up to [ 14] logic PT(s) - 8| A0| IO| | S | 1 |=> can support up to [ 20] logic PT(s) - 9| | ? | | S | |=> can support up to [ 19] logic PT(s) + 1| SIZE_0_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) + 2| E| IO| | S | 3 :+: 1|=> can support up to [ 8] logic PT(s) + 3| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 1] logic PT(s) + 4|inst_avec_expreg|NOD| | S | 6 |=> can support up to [ 9] logic PT(s) + 5|inst_RW_000_INT|NOD| | S |14 |=> can support up to [ 15] logic PT(s) + 6| SM_AMIGA_6_|NOD| | S | 2 |=> can support up to [ 4] logic PT(s) + 7| | ? | | S | |=> can support up to [ 6] logic PT(s) + 8| A0| IO| | S | 1 |=> can support up to [ 11] logic PT(s) + 9| | ? | | S | |=> can support up to [ 15] logic PT(s) 10| | ? | | S | |=> can support up to [ 20] logic PT(s) 11| | ? | | S | |=> can support up to [ 20] logic PT(s) 12| | ? | | S | |=> can support up to [ 20] logic PT(s) @@ -1475,9 +1471,9 @@ _|_________________|__|_____|____________________|________________________ 1| SIZE_0_| IO| | => |( 5) 6 7 0 |( 70) 71 72 65 2| E| IO| | => | 6 7 0 ( 1)| 71 72 65 ( 66) 3| CLK_DIV_OUT|OUT| | => | 6 7 ( 0) 1 | 71 72 ( 65) 66 - 4| cpu_est_2_|NOD| | => | 7 0 1 2 | 72 65 66 67 - 5| SM_AMIGA_2_|NOD| | => | 7 0 1 2 | 72 65 66 67 - 6| SM_AMIGA_3_|NOD| | => | 0 1 2 3 | 65 66 67 68 + 4|inst_avec_expreg|NOD| | => | 7 0 1 2 | 72 65 66 67 + 5|inst_RW_000_INT|NOD| | => | 7 0 1 2 | 72 65 66 67 + 6| SM_AMIGA_6_|NOD| | => | 0 1 2 3 | 65 66 67 68 7| | | | => | 0 1 2 3 | 65 66 67 68 8| A0| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69) 9| | | | => | 1 2 3 4 | 66 67 68 69 @@ -1546,12 +1542,12 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 67|INP IPL_0_|*|*] [RegIn 2 |252| -| | ] - [MCell 4 |251|NOD cpu_est_2_| |*] - [MCell 5 |253|NOD SM_AMIGA_2_| |*] + [MCell 4 |251|NOD inst_avec_expreg| |*] + [MCell 5 |253|NOD inst_RW_000_INT| |*] 3 [IOpin 3 | 68|INP IPL_2_|*|*] [RegIn 3 |255| -| | ] - [MCell 6 |254|NOD SM_AMIGA_3_| |*] + [MCell 6 |254|NOD SM_AMIGA_6_| |*] [MCell 7 |256| -| | ] 4 [IOpin 4 | 69| IO A0|*|*] @@ -1580,38 +1576,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| Mcel 7 11 ( 286)| inst_DTACK_D0 -Mux02| Mcel 3 1 ( 175)| RN_VMA -Mux03| Mcel 6 5 ( 253)| SM_AMIGA_2_ -Mux04| Mcel 6 2 ( 248)| RN_E -Mux05| Mcel 1 3 ( 130)| cpu_est_1_ -Mux06| Mcel 0 3 ( 106)| inst_RW_000_INT -Mux07| Mcel 3 5 ( 181)| inst_CLK_000_D0 -Mux08| IOPin 3 3 ( 32)| UDS_000 -Mux09| ... | ... -Mux10| ... | ... -Mux11| Mcel 6 4 ( 251)| cpu_est_2_ -Mux12| Mcel 3 9 ( 187)| SM_AMIGA_4_ -Mux13| Mcel 3 7 ( 184)| inst_CLK_000_D1 +Mux00| IOPin 3 4 ( 31)| LDS_000 +Mux01| Mcel 1 7 ( 136)| inst_CLK_OUT_PRE_25 +Mux02| Mcel 3 10 ( 188)| cpu_est_0_ +Mux03| Mcel 6 5 ( 253)| inst_RW_000_INT +Mux04| Input Pin ( 64)| CLK_030 +Mux05| Mcel 7 9 ( 283)| SM_AMIGA_0_ +Mux06| Mcel 1 9 ( 139)| inst_BGACK_030_INT_D +Mux07| Mcel 3 9 ( 187)| cpu_est_2_ +Mux08| Mcel 3 7 ( 184)| cpu_est_1_ +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 7 3 ( 274)| inst_CLK_000_D0 +Mux11| Mcel 6 4 ( 251)| inst_avec_expreg +Mux12| IOPin 3 3 ( 32)| UDS_000 +Mux13| Mcel 1 3 ( 130)| SM_AMIGA_1_ Mux14| ... | ... Mux15| Input Pin ( 14)| nEXP_SPACE Mux16| ... | ... Mux17| ... | ... -Mux18| Mcel 7 10 ( 284)| inst_VPA_D +Mux18| Mcel 7 10 ( 284)| inst_CLK_000_D2 Mux19| ... | ... Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux21| Mcel 7 6 ( 278)| RN_AS_030 -Mux22| Mcel 2 2 ( 152)| cpu_est_0_ -Mux23| Mcel 6 6 ( 254)| SM_AMIGA_3_ -Mux24| Mcel 1 7 ( 136)| inst_CLK_OUT_PRE_25 -Mux25| ... | ... +Mux21| Input Pin ( 86)| RST +Mux22| ... | ... +Mux23| Mcel 6 6 ( 254)| SM_AMIGA_6_ +Mux24| Mcel 3 5 ( 181)| inst_CLK_000_D1 +Mux25| IOPin 6 6 ( 71)| RW Mux26| IOPin 3 2 ( 33)| AS_000 -Mux27| IOPin 3 4 ( 31)| LDS_000 -Mux28| ... | ... -Mux29| ... | ... -Mux30| ... | ... -Mux31| ... | ... +Mux27| Mcel 7 5 ( 277)| SM_AMIGA_7_ +Mux28| IOPin 7 5 ( 80)| RW_000 +Mux29| Mcel 7 7 ( 280)| inst_AS_030_000_SYNC +Mux30| Mcel 7 6 ( 278)| RN_AS_030 +Mux31| Mcel 6 2 ( 248)| RN_E Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -1624,18 +1620,18 @@ Mux32| ... | ... | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| SIZE_1_| IO| | S | 2 | 4 to [ 0]| 1 XOR free - 1| RW_000| IO| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 0| RW_000| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1| SIZE_1_| IO| | S | 2 | 4 to [ 1]| 1 XOR free 2| FPU_CS| IO| | S | 2 | 4 to [ 2]| 1 XOR free - 3|inst_CLK_000_D2|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig - 4| BGACK_030| IO| | S | 2 | 4 to [ 4]| 1 XOR free - 5|inst_CLK_030_H|NOD| | S | 5 | 4 to [ 5]| 1 XOR to [ 5] as logic PT - 6| AS_030| IO| | S | 4 | 4 to [ 6]| 1 XOR free - 7| SM_AMIGA_1_|NOD| | S | 2 | 4 to [ 7]| 1 XOR free + 3|inst_CLK_000_D0|NOD| | S | 1 | 4 to [ 4]| 1 XOR to [ 3] for 1 PT sig + 4| BGACK_030| IO| | S | 2 | 4 to [ 5]| 1 XOR free + 5| SM_AMIGA_7_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free + 6| AS_030| IO| | S | 4 | 4 to [ 7]| 1 XOR free + 7|inst_AS_030_000_SYNC|NOD| | S | 8 | 4 to [ 7]| 1 XOR to [ 7] as logic PT 8| DSACK1| IO| | S | 2 | 4 to [ 8]| 1 XOR free - 9|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig -10| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig -11| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig + 9| SM_AMIGA_0_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free +10|inst_CLK_000_D2|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig 12|inst_CLK_OUT_PRE_50_D|NOD| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig 13| | ? | | S | | 4 free | 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free @@ -1651,18 +1647,18 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| SIZE_1_| IO| | S | 2 |=> can support up to [ 9] logic PT(s) - 1| RW_000| IO| | S | 1 |=> can support up to [ 9] logic PT(s) - 2| FPU_CS| IO| | S | 2 |=> can support up to [ 13] logic PT(s) - 3|inst_CLK_000_D2|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) - 4| BGACK_030| IO| | S | 2 |=> can support up to [ 9] logic PT(s) - 5|inst_CLK_030_H|NOD| | S | 5 |=> can support up to [ 5] logic PT(s) + 0| RW_000| IO| | S | 1 |=> can support up to [ 5] logic PT(s) + 1| SIZE_1_| IO| | S | 2 |=> can support up to [ 9] logic PT(s) + 2| FPU_CS| IO| | S | 2 |=> can support up to [ 5] logic PT(s) + 3|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) + 4| BGACK_030| IO| | S | 2 |=> can support up to [ 4] logic PT(s) + 5| SM_AMIGA_7_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) 6| AS_030| IO| | S | 4 |=> can support up to [ 5] logic PT(s) - 7| SM_AMIGA_1_|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) - 8| DSACK1| IO| | S | 2 |=> can support up to [ 13] logic PT(s) - 9|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) -10| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) -11| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 7|inst_AS_030_000_SYNC|NOD| | S | 8 |=> can support up to [ 10] logic PT(s) + 8| DSACK1| IO| | S | 2 |=> can support up to [ 9] logic PT(s) + 9| SM_AMIGA_0_|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) +10|inst_CLK_000_D2|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) +11|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) 12|inst_CLK_OUT_PRE_50_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) 13| | ? | | S | |=> can support up to [ 19] logic PT(s) 14| | ? | | S | |=> can support up to [ 15] logic PT(s) @@ -1676,18 +1672,18 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 7] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| SIZE_1_| IO| | => | 5 ( 6) 7 0 | 80 ( 79) 78 85 - 1| RW_000| IO| | => |( 5) 6 7 0 |( 80) 79 78 85 + 0| RW_000| IO| | => |( 5) 6 7 0 |( 80) 79 78 85 + 1| SIZE_1_| IO| | => | 5 ( 6) 7 0 | 80 ( 79) 78 85 2| FPU_CS| IO| | => | 6 ( 7) 0 1 | 79 ( 78) 85 84 - 3|inst_CLK_000_D2|NOD| | => | 6 7 0 1 | 79 78 85 84 + 3|inst_CLK_000_D0|NOD| | => | 6 7 0 1 | 79 78 85 84 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) - 5|inst_CLK_030_H|NOD| | => | 7 0 1 2 | 78 85 84 83 + 5| SM_AMIGA_7_|NOD| | => | 7 0 1 2 | 78 85 84 83 6| AS_030| IO| | => | 0 1 2 ( 3)| 85 84 83 ( 82) - 7| SM_AMIGA_1_|NOD| | => | 0 1 2 3 | 85 84 83 82 + 7|inst_AS_030_000_SYNC|NOD| | => | 0 1 2 3 | 85 84 83 82 8| DSACK1| IO| | => | 1 2 3 ( 4)| 84 83 82 ( 81) - 9|inst_CLK_OUT_PRE_50|NOD| | => | 1 2 3 4 | 84 83 82 81 -10| inst_VPA_D|NOD| | => | 2 3 4 5 | 83 82 81 80 -11| inst_DTACK_D0|NOD| | => | 2 3 4 5 | 83 82 81 80 + 9| SM_AMIGA_0_|NOD| | => | 1 2 3 4 | 84 83 82 81 +10|inst_CLK_000_D2|NOD| | => | 2 3 4 5 | 83 82 81 80 +11|inst_CLK_OUT_PRE_50|NOD| | => | 2 3 4 5 | 83 82 81 80 12|inst_CLK_OUT_PRE_50_D|NOD| | => | 3 4 5 6 | 82 81 80 79 13| | | | => | 3 4 5 6 | 82 81 80 79 14| | | | => | 4 5 6 7 | 81 80 79 78 @@ -1707,8 +1703,8 @@ _|_________________|__|___|_____|___________________________________________ 2| BGACK_030| IO|*| 83| => | ( 4) 5 6 7 8 9 10 11 3| AS_030| IO|*| 82| => | ( 6) 7 8 9 10 11 12 13 4| DSACK1| IO|*| 81| => | ( 8) 9 10 11 12 13 14 15 - 5| RW_000| IO|*| 80| => | 10 11 12 13 14 15 0 ( 1) - 6| SIZE_1_| IO|*| 79| => | 12 13 14 15 ( 0) 1 2 3 + 5| RW_000| IO|*| 80| => | 10 11 12 13 14 15 ( 0) 1 + 6| SIZE_1_| IO|*| 79| => | 12 13 14 15 0 ( 1) 2 3 7| FPU_CS| IO|*| 78| => | 14 15 0 1 ( 2) 3 4 5 --------------------------------------------------------------------------- =========================================================================== @@ -1744,33 +1740,33 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 85|INP A_22_|*|*] [RegIn 0 |270| -| | ] - [MCell 0 |269| IO SIZE_1_| | ] - [MCell 1 |271| IO RW_000| | ] + [MCell 0 |269| IO RW_000| | ] + [MCell 1 |271| IO SIZE_1_| | ] 1 [IOpin 1 | 84|INP A_23_|*|*] [RegIn 1 |273| -| | ] [MCell 2 |272|NOD RN_FPU_CS| |*] paired w/[ FPU_CS] - [MCell 3 |274|NOD inst_CLK_000_D2| |*] + [MCell 3 |274|NOD inst_CLK_000_D0| |*] 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] [RegIn 2 |276| -| | ] [MCell 4 |275|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] - [MCell 5 |277|NOD inst_CLK_030_H| |*] + [MCell 5 |277|NOD SM_AMIGA_7_| |*] 3 [IOpin 3 | 82| IO AS_030|*|*] paired w/[ RN_AS_030] [RegIn 3 |279| -| | ] [MCell 6 |278|NOD RN_AS_030| |*] paired w/[ AS_030] - [MCell 7 |280|NOD SM_AMIGA_1_| |*] + [MCell 7 |280|NOD inst_AS_030_000_SYNC| |*] 4 [IOpin 4 | 81| IO DSACK1|*|*] paired w/[ RN_DSACK1] [RegIn 4 |282| -| | ] [MCell 8 |281|NOD RN_DSACK1| |*] paired w/[ DSACK1] - [MCell 9 |283|NOD inst_CLK_OUT_PRE_50| |*] + [MCell 9 |283|NOD SM_AMIGA_0_| |*] 5 [IOpin 5 | 80| IO RW_000|*|*] [RegIn 5 |285| -| | ] - [MCell 10 |284|NOD inst_VPA_D| |*] - [MCell 11 |286|NOD inst_DTACK_D0| |*] + [MCell 10 |284|NOD inst_CLK_000_D2| |*] + [MCell 11 |286|NOD inst_CLK_OUT_PRE_50| |*] 6 [IOpin 6 | 79| IO SIZE_1_|*|*] [RegIn 6 |288| -| | ] @@ -1791,34 +1787,34 @@ IMX No. | +---- Block IO Pin or Macrocell Number Mux00| IOPin 3 4 ( 31)| LDS_000 Mux01| IOPin 5 2 ( 58)| FC_1_ Mux02| ... | ... -Mux03| Mcel 7 8 ( 281)| RN_DSACK1 -Mux04| IOPin 0 4 ( 95)| A_18_ -Mux05| Mcel 7 9 ( 283)| inst_CLK_OUT_PRE_50 +Mux03| Input Pin ( 11)| CLK_000 +Mux04| IOPin 3 7 ( 28)| BGACK_000 +Mux05| Mcel 7 9 ( 283)| SM_AMIGA_0_ Mux06| IOPin 0 6 ( 97)| A_19_ -Mux07| Mcel 7 7 ( 280)| SM_AMIGA_1_ -Mux08| Mcel 3 7 ( 184)| inst_CLK_000_D1 -Mux09| IOPin 3 5 ( 30)| DTACK -Mux10| Input Pin ( 36)| VPA +Mux07| Mcel 7 6 ( 278)| RN_AS_030 +Mux08| IOPin 5 1 ( 59)| A_17_ +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 7 3 ( 274)| inst_CLK_000_D0 Mux11| IOPin 0 5 ( 96)| A_16_ Mux12| IOPin 3 3 ( 32)| UDS_000 -Mux13| Mcel 7 5 ( 277)| inst_CLK_030_H +Mux13| Mcel 7 8 ( 281)| RN_DSACK1 Mux14| Mcel 7 2 ( 272)| RN_FPU_CS Mux15| Input Pin ( 14)| nEXP_SPACE Mux16| ... | ... Mux17| IOPin 5 3 ( 57)| FC_0_ -Mux18| IOPin 3 7 ( 28)| BGACK_000 -Mux19| IOPin 7 3 ( 82)| AS_030 -Mux20| Input Pin ( 64)| CLK_030 +Mux18| Mcel 7 10 ( 284)| inst_CLK_000_D2 +Mux19| Mcel 1 3 ( 130)| SM_AMIGA_1_ +Mux20| Mcel 7 7 ( 280)| inst_AS_030_000_SYNC Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 5 ( 253)| SM_AMIGA_2_ +Mux22| Mcel 7 11 ( 286)| inst_CLK_OUT_PRE_50 Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| Mcel 3 5 ( 181)| inst_CLK_000_D0 -Mux25| Mcel 0 3 ( 106)| inst_RW_000_INT +Mux24| Mcel 3 5 ( 181)| inst_CLK_000_D1 +Mux25| ... | ... Mux26| IOPin 3 2 ( 33)| AS_000 -Mux27| IOPin 5 1 ( 59)| A_17_ -Mux28| ... | ... +Mux27| Mcel 7 5 ( 277)| SM_AMIGA_7_ +Mux28| Input Pin ( 64)| CLK_030 Mux29| ... | ... -Mux30| Mcel 7 6 ( 278)| RN_AS_030 -Mux31| ... | ... -Mux32| ... | ... +Mux30| ... | ... +Mux31| IOPin 0 4 ( 95)| A_18_ +Mux32| Mcel 6 5 ( 253)| inst_RW_000_INT --------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index 21bf7b8..796ee6f 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic -Project Fitted on : Sun Jun 01 01:03:29 2014 +Project Fitted on : Sat Jun 07 23:03:24 2014 Device : M4A5-128/64 Package : 100TQFP @@ -40,8 +40,8 @@ Design_Summary Total Input Pins : 29 Total Output Pins : 18 Total Bidir I/O Pins : 12 - Total Flip-Flops : 45 - Total Product Terms : 143 + Total Flip-Flops : 44 + Total Product Terms : 146 Total Reserved Pins : 0 Total Reserved Blocks : 0 @@ -58,9 +58,9 @@ Logic Macrocells 128 54 74 --> 42% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 0 .. -CSM Outputs/Total Block Inputs 264 157 107 --> 59% -Logical Product Terms 640 146 494 --> 22% -Product Term Clusters 128 39 89 --> 30% +CSM Outputs/Total Block Inputs 264 147 117 --> 55% +Logical Product Terms 640 149 491 --> 23% +Product Term Clusters 128 40 88 --> 31%  Blocks_Resource_Summary @@ -71,14 +71,14 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 17 7 0 4 0 12 24 10 Hi -Block B 24 8 0 10 0 6 26 8 Hi -Block C 22 8 0 5 0 11 16 12 Hi -Block D 29 8 0 11 0 5 32 7 Hi +Block A 23 7 0 6 0 10 18 11 Hi +Block B 22 8 0 10 0 6 23 10 Hi +Block C 1 8 0 2 0 14 2 16 Hi +Block D 29 8 0 12 0 4 41 4 Hi Block E 17 3 0 3 0 13 4 15 Hi Block F 0 4 0 0 0 16 0 16 Hi -Block G 21 7 0 8 0 8 19 12 Hi -Block H 27 8 0 13 0 3 25 9 Hi +Block G 27 7 0 8 0 8 30 9 Hi +Block H 28 8 0 13 0 3 31 7 Hi --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. @@ -287,10 +287,10 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 96 A . I/O --C----H Hi Slow A_16_ - 59 F . I/O --C----H Hi Slow A_17_ - 95 A . I/O --C----H Hi Slow A_18_ - 97 A . I/O --C----H Hi Slow A_19_ + 96 A . I/O -------H Hi Slow A_16_ + 59 F . I/O -------H Hi Slow A_17_ + 95 A . I/O -------H Hi Slow A_18_ + 97 A . I/O -------H Hi Slow A_19_ 93 A . I/O ----E--- Hi Slow A_20_ 94 A . I/O ----E--- Hi Slow A_21_ 85 H . I/O ----E--- Hi Slow A_22_ @@ -303,19 +303,19 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 6 B . I/O ----E--- Hi Slow A_29_ 5 B . I/O ----E--- Hi Slow A_30_ 4 B . I/O ----E--- Hi Slow A_31_ - 28 D . I/O --C----H Hi Slow BGACK_000 + 28 D . I/O -------H Hi Slow BGACK_000 21 C . I/O ---D---- Hi Slow BG_030 - 57 F . I/O --C----H Hi Slow FC_0_ - 58 F . I/O --C----H Hi Slow FC_1_ + 57 F . I/O -------H Hi Slow FC_0_ + 58 F . I/O -------H Hi Slow FC_1_ 67 G . I/O -B------ Hi Slow IPL_0_ 56 F . I/O -B------ Hi Slow IPL_1_ 68 G . I/O -B------ Hi Slow IPL_2_ - 11 . . Ck/I ---D---- - Slow CLK_000 - 14 . . Ck/I ABCDE-GH - Slow nEXP_SPACE - 36 . . Ded -------H - Slow VPA - 61 . . Ck/I ABCD--GH - Slow CLK_OSZI - 64 . . Ck/I A-C----H - Slow CLK_030 - 86 . . Ded ABCD--GH - Slow RST + 11 . . Ck/I ---D---H - Slow CLK_000 + 14 . . Ck/I A--DE-GH - Slow nEXP_SPACE + 36 . . Ded A------- - Slow VPA + 61 . . Ck/I AB-D--GH - Slow CLK_OSZI + 64 . . Ck/I AB----GH - Slow CLK_030 + 86 . . Ded AB-D--GH - Slow RST ---------------------------------------------------------------------- Power : Hi = High @@ -335,7 +335,7 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 34 D 1 COM -------- Hi Slow AMIGA_BUS_ENABLE 20 C 1 COM -------- Hi Slow AMIGA_BUS_ENABLE_LOW 92 A 1 COM -------- Hi Slow AVEC - 22 C 3 DFF * -------- Hi Slow AVEC_EXP + 22 C 1 COM -------- Hi Slow AVEC_EXP 41 E 1 COM -------- Hi Slow BERR 83 H 2 DFF * -------- Hi Slow BGACK_030 29 D 2 DFF * -------- Hi Slow BG_000 @@ -365,17 +365,17 @@ Bidir_Signal_List Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- 69 G 1 DFF * ---D---- Hi Slow A0 - 33 D 2 DFF * A---E-GH Hi Slow AS_000 - 82 H 4 DFF * --CD---H Hi Slow AS_030 + 33 D 2 DFF * AB--E-GH Hi Slow AS_000 + 82 H 4 DFF * ---D--GH Hi Slow AS_030 81 H 2 DFF * ---D---- Hi Slow DSACK1 98 A 7 DFF * ---D---- Hi Slow DS_030 - 30 D 1 COM -------H Hi Slow DTACK - 31 D 11 DFF * A-----GH Hi Slow LDS_000 - 71 G 1 COM A--DE--- Hi Slow RW - 80 H 1 COM A------- Hi Slow RW_000 + 30 D 1 COM -B------ Hi Slow DTACK + 31 D 11 DFF * AB----GH Hi Slow LDS_000 + 71 G 1 COM ---DE-G- Hi Slow RW + 80 H 1 COM A-----G- Hi Slow RW_000 70 G 1 DFF * ---D---- Hi Slow SIZE_0_ 79 H 2 DFF * ---D---- Hi Slow SIZE_1_ - 32 D 7 DFF * A-----GH Hi Slow UDS_000 + 32 D 7 DFF * AB----GH Hi Slow UDS_000 ---------------------------------------------------------------------- Power : Hi = High @@ -392,44 +392,43 @@ Buried_Signal_List #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- D4 D 2 DFF * ---D---- Hi - RN_AS_000 --> AS_000 - H6 H 4 DFF * A--D--GH Hi - RN_AS_030 --> AS_030 - C0 C 3 DFF * --CD---- Hi - RN_AVEC_EXP --> AVEC_EXP - H4 H 2 DFF * A-CDE-GH Hi - RN_BGACK_030 --> BGACK_030 + H6 H 4 DFF * AB-D--GH Hi - RN_AS_030 --> AS_030 + H4 H 2 DFF * AB-DE-GH Hi - RN_BGACK_030 --> BGACK_030 D2 D 2 DFF * ---D---- Hi - RN_BG_000 --> BG_000 H8 H 2 DFF * -------H Hi - RN_DSACK1 --> DSACK1 A0 A 7 DFF * A------- Hi - RN_DS_030 --> DS_030 - G2 G 3 DFF * -B-D--G- Hi - RN_E --> E + G2 G 3 DFF * A--D--G- Hi - RN_E --> E H2 H 2 DFF * ----E--H Hi - RN_FPU_CS --> FPU_CS B4 B 3 DFF * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_ B6 B 3 DFF * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_ B2 B 3 DFF * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_ D8 D 11 DFF * ---D---- Hi - RN_LDS_000 --> LDS_000 D6 D 7 DFF * ---D---- Hi - RN_UDS_000 --> UDS_000 - D1 D 2 DFF * ---D--G- Hi - RN_VMA --> VMA - A1 A 2 DFF * AB------ Hi Slow SM_AMIGA_0_ - H7 H 2 DFF * A------H Hi Slow SM_AMIGA_1_ - G5 G 3 DFF * --C---GH Hi Slow SM_AMIGA_2_ - G6 G 4 DFF * ------G- Hi Slow SM_AMIGA_3_ - D9 D 2 DFF * ---D--G- Hi Slow SM_AMIGA_4_ - B8 B 2 DFF * -B-D---- Hi Slow SM_AMIGA_5_ - B9 B 2 DFF * AB------ Hi Slow SM_AMIGA_6_ - B5 B 4 DFF * -BCD---- Hi Slow SM_AMIGA_7_ - C2 C 3 DFF * -BCD--G- Hi Slow cpu_est_0_ - B3 B 4 TFF * -B-D--G- Hi Slow cpu_est_1_ - G4 G 3 DFF * -B-D--G- Hi Slow cpu_est_2_ - C3 C 8 DFF * -BC----- Hi Slow inst_AS_030_000_SYNC - D10 D 1 DFF * --C----- Hi Slow inst_BGACK_030_INT_D - D5 D 1 DFF * ABCD--GH Hi Slow inst_CLK_000_D0 - D7 D 1 DFF * -BC---GH Hi Slow inst_CLK_000_D1 - H3 H 1 DFF * -BCD---- Hi Slow inst_CLK_000_D2 - C4 C 1 DFF * -BC----- Hi Slow inst_CLK_000_D3 - H5 H 5 DFF A------H Hi Slow inst_CLK_030_H + D1 D 2 DFF * A--D---- Hi - RN_VMA --> VMA + H9 H 2 DFF * ------GH Hi Slow SM_AMIGA_0_ + B3 B 2 DFF * -B----GH Hi Slow SM_AMIGA_1_ + A1 A 3 DFF * AB------ Hi Slow SM_AMIGA_2_ + A4 A 4 DFF * A------- Hi Slow SM_AMIGA_3_ + A5 A 2 DFF * A------- Hi Slow SM_AMIGA_4_ + D11 D 2 DFF * A--D---- Hi Slow SM_AMIGA_5_ + G6 G 2 DFF * ---D--G- Hi Slow SM_AMIGA_6_ + H5 H 4 DFF * ---D--GH Hi Slow SM_AMIGA_7_ + D10 D 3 DFF * ---D--G- Hi Slow cpu_est_0_ + D7 D 4 TFF * A--D--G- Hi Slow cpu_est_1_ + D9 D 3 DFF * ---D--G- Hi Slow cpu_est_2_ + H7 H 8 DFF * ------GH Hi Slow inst_AS_030_000_SYNC + B9 B 1 DFF * ------G- Hi Slow inst_BGACK_030_INT_D + H3 H 1 DFF * AB-D--GH Hi Slow inst_CLK_000_D0 + D5 D 1 DFF * AB-D--GH Hi Slow inst_CLK_000_D1 + H10 H 1 DFF * ------GH Hi Slow inst_CLK_000_D2 + B5 B 5 DFF AB------ Hi Slow inst_CLK_030_H B7 B 3 DFF * -B----G- Hi Slow inst_CLK_OUT_PRE_25 - H9 H 1 DFF * -B-----H Hi Slow inst_CLK_OUT_PRE_50 + H11 H 1 DFF * -B-----H Hi Slow inst_CLK_OUT_PRE_50 H12 H 1 DFF * -B------ Hi Slow inst_CLK_OUT_PRE_50_D - H11 H 1 DFF * ------G- Hi Slow inst_DTACK_D0 - A3 A 14 DFF * A-----GH Hi Slow inst_RW_000_INT - H10 H 1 DFF * ---D--G- Hi Slow inst_VPA_D + B8 B 1 DFF * A------- Hi Slow inst_DTACK_D0 + G5 G 14 DFF * ------GH Hi Slow inst_RW_000_INT + A3 A 1 DFF * A--D---- Hi Slow inst_VPA_D + G4 G 6 DFF * --CD--G- Hi Slow inst_avec_expreg ---------------------------------------------------------------------- Power : Hi = High @@ -444,142 +443,141 @@ Signals_Fanout_List ~~~~~~~~~~~~~~~~~~~ Signal Source : Fanout List ----------------------------------------------------------------------------- - A_26_{ D}: CIIN{ E} - A_25_{ D}: CIIN{ E} - A_24_{ D}: CIIN{ E} - A_23_{ I}: CIIN{ E} - A_31_{ C}: CIIN{ E} A_22_{ I}: CIIN{ E} A_21_{ B}: CIIN{ E} A_20_{ B}: CIIN{ E} - A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ C} + A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_31_{ C}: CIIN{ E} + A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} IPL_2_{ H}: IPL_030_2_{ B} - A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ C} - A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ C} - FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ C} - A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ C} - RW_000{ I}: DS_030{ A}inst_RW_000_INT{ A} IPL_1_{ G}: IPL_030_1_{ B} + FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} IPL_0_{ H}: IPL_030_0_{ B} - FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ C} - nEXP_SPACE{. }: DTACK{ D} AVEC_EXP{ C}AMIGA_BUS_DATA_DIR{ E} - : SIZE_1_{ H} AS_030{ H} DS_030{ A} - : A0{ G} BG_000{ D} DSACK1{ H} - : SIZE_0_{ G}inst_AS_030_000_SYNC{ C} SM_AMIGA_7_{ B} - : SM_AMIGA_6_{ B} + FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + RW_000{ I}: DS_030{ A}inst_RW_000_INT{ G} + nEXP_SPACE{. }: DTACK{ D}AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} + : AS_030{ H} DS_030{ A} A0{ G} + : BG_000{ D} DSACK1{ H} SIZE_0_{ G} + :inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ G} + : SM_AMIGA_7_{ H} BG_030{ D}: BG_000{ D} - BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ H} CLK_030{. }: AS_030{ H} DS_030{ A} FPU_CS{ H} - :inst_AS_030_000_SYNC{ C}inst_RW_000_INT{ A} inst_CLK_030_H{ H} - CLK_000{. }: BG_000{ D}inst_CLK_000_D0{ D} - DTACK{ E}: inst_DTACK_D0{ H} -RN_AVEC_EXP{ D}: AVEC_EXP{ C}AMIGA_BUS_ENABLE{ D} - VPA{. }: inst_VPA_D{ H} - RST{. }: CLK_DIV_OUT{ G} AVEC_EXP{ C} SIZE_1_{ H} - : IPL_030_2_{ B} AS_030{ H} IPL_030_1_{ B} - : AS_000{ D} IPL_030_0_{ B} DS_030{ A} - : UDS_000{ D} LDS_000{ D} A0{ G} - : BG_000{ D} BGACK_030{ H} CLK_EXP{ B} - : FPU_CS{ H} DSACK1{ H} E{ G} - : VMA{ D} RESET{ B} SIZE_0_{ G} - :inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ D} inst_VPA_D{ H} - :inst_CLK_OUT_PRE_50_D{ H}inst_CLK_000_D0{ D}inst_CLK_000_D1{ D} - :inst_CLK_000_D2{ H} inst_DTACK_D0{ H}inst_CLK_OUT_PRE_50{ H} - :inst_CLK_OUT_PRE_25{ B} SM_AMIGA_7_{ B} SM_AMIGA_6_{ B} - : SM_AMIGA_0_{ A} SM_AMIGA_5_{ B} SM_AMIGA_2_{ G} - :inst_RW_000_INT{ A}inst_CLK_000_D3{ C} inst_CLK_030_H{ H} - : SM_AMIGA_4_{ D} SM_AMIGA_3_{ G} SM_AMIGA_1_{ H} - : cpu_est_0_{ C} cpu_est_1_{ B} cpu_est_2_{ G} + :inst_AS_030_000_SYNC{ H}inst_RW_000_INT{ G} inst_CLK_030_H{ B} + CLK_000{. }: BG_000{ D}inst_CLK_000_D0{ H} + DTACK{ E}: inst_DTACK_D0{ B} + VPA{. }: inst_VPA_D{ A} + RST{. }: CLK_DIV_OUT{ G} SIZE_1_{ H} IPL_030_2_{ B} + : IPL_030_1_{ B} IPL_030_0_{ B} AS_030{ H} + : AS_000{ D} DS_030{ A} UDS_000{ D} + : LDS_000{ D} A0{ G} BG_000{ D} + : BGACK_030{ H} CLK_EXP{ B} FPU_CS{ H} + : DSACK1{ H} E{ G} VMA{ D} + : RESET{ B} SIZE_0_{ G}inst_avec_expreg{ G} + :inst_AS_030_000_SYNC{ H}inst_BGACK_030_INT_D{ B} inst_VPA_D{ A} + :inst_CLK_OUT_PRE_50_D{ H}inst_CLK_000_D0{ H}inst_CLK_000_D1{ D} + : inst_DTACK_D0{ B}inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_25{ B} + : SM_AMIGA_1_{ B} SM_AMIGA_6_{ G} SM_AMIGA_0_{ H} + : SM_AMIGA_7_{ H}inst_RW_000_INT{ G}inst_CLK_000_D2{ H} + : inst_CLK_030_H{ B} SM_AMIGA_5_{ D} SM_AMIGA_4_{ A} + : SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} cpu_est_0_{ D} + : cpu_est_1_{ D} cpu_est_2_{ D} RW{ H}:AMIGA_BUS_DATA_DIR{ E} UDS_000{ D} LDS_000{ D} - :inst_RW_000_INT{ A} + :inst_RW_000_INT{ G} A_30_{ C}: CIIN{ E} A_29_{ C}: CIIN{ E} A_28_{ D}: CIIN{ E} A_27_{ D}: CIIN{ E} + A_26_{ D}: CIIN{ E} + A_25_{ D}: CIIN{ E} + A_24_{ D}: CIIN{ E} + A_23_{ I}: CIIN{ E} SIZE_1_{ I}: LDS_000{ D} RN_IPL_030_2_{ C}: IPL_030_2_{ B} +RN_IPL_030_1_{ C}: IPL_030_1_{ B} +RN_IPL_030_0_{ C}: IPL_030_0_{ B} AS_030{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} : BG_000{ D} FPU_CS{ H} DSACK1{ H} - :inst_AS_030_000_SYNC{ C} + :inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} RN_AS_030{ I}: DTACK{ D} SIZE_1_{ H} AS_030{ H} : DS_030{ A} A0{ G} SIZE_0_{ G} - : inst_CLK_030_H{ H} -RN_IPL_030_1_{ C}: IPL_030_1_{ B} + : inst_CLK_030_H{ B} AS_000{ E}:AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H} : DS_030{ A} A0{ G} SIZE_0_{ G} - :inst_RW_000_INT{ A} inst_CLK_030_H{ H} + :inst_RW_000_INT{ G} inst_CLK_030_H{ B} RN_AS_000{ E}: AS_000{ D} VMA{ D} -RN_IPL_030_0_{ C}: IPL_030_0_{ B} DS_030{ B}: UDS_000{ D} LDS_000{ D} RN_DS_030{ B}: DS_030{ A} UDS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A} - : A0{ G} SIZE_0_{ G}inst_RW_000_INT{ A} - : inst_CLK_030_H{ H} + : A0{ G} SIZE_0_{ G}inst_RW_000_INT{ G} + : inst_CLK_030_H{ B} RN_UDS_000{ E}: UDS_000{ D} LDS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A} - : A0{ G} SIZE_0_{ G}inst_RW_000_INT{ A} - : inst_CLK_030_H{ H} + : A0{ G} SIZE_0_{ G}inst_RW_000_INT{ G} + : inst_CLK_030_H{ B} RN_LDS_000{ E}: LDS_000{ D} A0{ H}: UDS_000{ D} LDS_000{ D} RN_BG_000{ E}: BG_000{ D} -RN_BGACK_030{ I}: RW_000{ H} DTACK{ D} AVEC_EXP{ C} - : RW{ G}AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} - : AS_030{ H} AS_000{ D} DS_030{ A} - : UDS_000{ D} LDS_000{ D} A0{ G} - : BGACK_030{ H} SIZE_0_{ G}inst_AS_030_000_SYNC{ C} - :inst_BGACK_030_INT_D{ D}inst_RW_000_INT{ A} inst_CLK_030_H{ H} +RN_BGACK_030{ I}: RW_000{ H} DTACK{ D} RW{ G} + :AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} AS_030{ H} + : AS_000{ D} DS_030{ A} UDS_000{ D} + : LDS_000{ D} A0{ G} BGACK_030{ H} + : SIZE_0_{ G}inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} + :inst_BGACK_030_INT_D{ B}inst_RW_000_INT{ G} inst_CLK_030_H{ B} RN_FPU_CS{ I}: BERR{ E} FPU_CS{ H} DSACK1{ I}: DTACK{ D} RN_DSACK1{ I}: DSACK1{ H} - RN_E{ H}: E{ G} VMA{ D} SM_AMIGA_2_{ G} - : SM_AMIGA_3_{ G} cpu_est_1_{ B} cpu_est_2_{ G} - RN_VMA{ E}: VMA{ D} SM_AMIGA_2_{ G} SM_AMIGA_3_{ G} + RN_E{ H}: E{ G} VMA{ D} SM_AMIGA_3_{ A} + : SM_AMIGA_2_{ A} cpu_est_1_{ D} cpu_est_2_{ D} + RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} SIZE_0_{ H}: LDS_000{ D} -inst_AS_030_000_SYNC{ D}: AVEC_EXP{ C}inst_AS_030_000_SYNC{ C} SM_AMIGA_7_{ B} - : SM_AMIGA_6_{ B} -inst_BGACK_030_INT_D{ E}: AVEC_EXP{ C} - inst_VPA_D{ I}: VMA{ D} SM_AMIGA_2_{ G} SM_AMIGA_3_{ G} +inst_avec_expreg{ H}: AVEC_EXP{ C}AMIGA_BUS_ENABLE{ D}inst_avec_expreg{ G} +inst_AS_030_000_SYNC{ I}:inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ G} + : SM_AMIGA_7_{ H} +inst_BGACK_030_INT_D{ C}:inst_avec_expreg{ G} + inst_VPA_D{ B}: VMA{ D} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} inst_CLK_OUT_PRE_50_D{ I}:inst_CLK_OUT_PRE_25{ B} -inst_CLK_000_D0{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : UDS_000{ D} LDS_000{ D} BGACK_030{ H} - : DSACK1{ H} E{ G} VMA{ D} - :inst_AS_030_000_SYNC{ C}inst_CLK_000_D1{ D} SM_AMIGA_7_{ B} - : SM_AMIGA_6_{ B} SM_AMIGA_0_{ A} SM_AMIGA_5_{ B} - : SM_AMIGA_2_{ G}inst_RW_000_INT{ A} SM_AMIGA_4_{ D} - : SM_AMIGA_3_{ G} SM_AMIGA_1_{ H} cpu_est_0_{ C} - : cpu_est_1_{ B} cpu_est_2_{ G} +inst_CLK_000_D0{ I}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + : AS_000{ D} UDS_000{ D} LDS_000{ D} + : BGACK_030{ H} E{ G} VMA{ D} + :inst_avec_expreg{ G}inst_CLK_000_D1{ D} SM_AMIGA_1_{ B} + : SM_AMIGA_6_{ G} SM_AMIGA_0_{ H} SM_AMIGA_7_{ H} + :inst_RW_000_INT{ G} SM_AMIGA_5_{ D} SM_AMIGA_4_{ A} + : SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} cpu_est_0_{ D} + : cpu_est_1_{ D} cpu_est_2_{ D} inst_CLK_000_D1{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : BGACK_030{ H} E{ G}inst_CLK_000_D2{ H} - : SM_AMIGA_2_{ G} SM_AMIGA_3_{ G} cpu_est_0_{ C} - : cpu_est_1_{ B} cpu_est_2_{ G} -inst_CLK_000_D2{ I}: AVEC_EXP{ C} AS_000{ D} UDS_000{ D} - : LDS_000{ D}inst_AS_030_000_SYNC{ C} SM_AMIGA_7_{ B} - : SM_AMIGA_6_{ B}inst_CLK_000_D3{ C} -inst_DTACK_D0{ I}: SM_AMIGA_2_{ G} SM_AMIGA_3_{ G} + : BGACK_030{ H} E{ G}inst_avec_expreg{ G} + :inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ G} SM_AMIGA_7_{ H} + :inst_CLK_000_D2{ H} SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} + : cpu_est_0_{ D} cpu_est_1_{ D} cpu_est_2_{ D} +inst_DTACK_D0{ C}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} inst_CLK_OUT_PRE_50{ I}:inst_CLK_OUT_PRE_50_D{ H}inst_CLK_OUT_PRE_50{ H}inst_CLK_OUT_PRE_25{ B} inst_CLK_OUT_PRE_25{ C}: CLK_DIV_OUT{ G} CLK_EXP{ B}inst_CLK_OUT_PRE_25{ B} -SM_AMIGA_7_{ C}: AVEC_EXP{ C} BG_000{ D}inst_AS_030_000_SYNC{ C} - : SM_AMIGA_7_{ B} SM_AMIGA_6_{ B} -SM_AMIGA_6_{ C}: SM_AMIGA_6_{ B} SM_AMIGA_5_{ B}inst_RW_000_INT{ A} -SM_AMIGA_0_{ B}: SM_AMIGA_7_{ B} SM_AMIGA_0_{ A}inst_RW_000_INT{ A} -SM_AMIGA_5_{ C}: AS_000{ D} UDS_000{ D} LDS_000{ D} - : SM_AMIGA_5_{ B} SM_AMIGA_4_{ D} -SM_AMIGA_2_{ H}: DSACK1{ H}inst_AS_030_000_SYNC{ C} SM_AMIGA_2_{ G} - : SM_AMIGA_1_{ H} -inst_RW_000_INT{ B}: RW_000{ H} RW{ G}inst_RW_000_INT{ A} -inst_CLK_000_D3{ D}: AVEC_EXP{ C}inst_AS_030_000_SYNC{ C} SM_AMIGA_7_{ B} - : SM_AMIGA_6_{ B} -inst_CLK_030_H{ I}: DS_030{ A} inst_CLK_030_H{ H} -SM_AMIGA_4_{ E}: UDS_000{ D} LDS_000{ D} SM_AMIGA_4_{ D} - : SM_AMIGA_3_{ G} -SM_AMIGA_3_{ H}: SM_AMIGA_2_{ G} SM_AMIGA_3_{ G} -SM_AMIGA_1_{ I}: SM_AMIGA_0_{ A} SM_AMIGA_1_{ H} - cpu_est_0_{ D}: E{ G} VMA{ D} cpu_est_0_{ C} - : cpu_est_1_{ B} cpu_est_2_{ G} - cpu_est_1_{ C}: E{ G} VMA{ D} SM_AMIGA_2_{ G} - : SM_AMIGA_3_{ G} cpu_est_1_{ B} cpu_est_2_{ G} - cpu_est_2_{ H}: E{ G} VMA{ D} cpu_est_1_{ B} - : cpu_est_2_{ G} +SM_AMIGA_1_{ C}: DSACK1{ H}inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} + : SM_AMIGA_1_{ B} SM_AMIGA_0_{ H} +SM_AMIGA_6_{ H}: AS_000{ D} UDS_000{ D} LDS_000{ D} + : SM_AMIGA_6_{ G}inst_RW_000_INT{ G} SM_AMIGA_5_{ D} +SM_AMIGA_0_{ I}:inst_avec_expreg{ G} SM_AMIGA_0_{ H} SM_AMIGA_7_{ H} + :inst_RW_000_INT{ G} +SM_AMIGA_7_{ I}: BG_000{ D}inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} + : SM_AMIGA_6_{ G} SM_AMIGA_7_{ H} +inst_RW_000_INT{ H}: RW_000{ H} RW{ G}inst_RW_000_INT{ G} +inst_CLK_000_D2{ I}:inst_avec_expreg{ G}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ G} + : SM_AMIGA_7_{ H} +inst_CLK_030_H{ C}: DS_030{ A} inst_CLK_030_H{ B} +SM_AMIGA_5_{ E}: UDS_000{ D} LDS_000{ D} SM_AMIGA_5_{ D} + : SM_AMIGA_4_{ A} +SM_AMIGA_4_{ B}: SM_AMIGA_4_{ A} SM_AMIGA_3_{ A} +SM_AMIGA_3_{ B}: SM_AMIGA_3_{ A} SM_AMIGA_2_{ A} +SM_AMIGA_2_{ B}: SM_AMIGA_1_{ B} SM_AMIGA_2_{ A} + cpu_est_0_{ E}: E{ G} VMA{ D} cpu_est_0_{ D} + : cpu_est_1_{ D} cpu_est_2_{ D} + cpu_est_1_{ E}: E{ G} VMA{ D} SM_AMIGA_3_{ A} + : SM_AMIGA_2_{ A} cpu_est_1_{ D} cpu_est_2_{ D} + cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} + : cpu_est_2_{ D} ----------------------------------------------------------------------------- {.} : Indicates block location of signal @@ -597,9 +595,11 @@ Equations : +-----+-----+-----+-----+------------------------ | * | S | BS | BR | DS_030 | | | | | AVEC -| * | S | BS | BR | inst_RW_000_INT -| * | S | BR | BS | SM_AMIGA_0_ +| * | S | BR | BS | SM_AMIGA_2_ +| * | S | BS | BR | inst_VPA_D | * | S | BS | BR | RN_DS_030 +| * | S | BR | BS | SM_AMIGA_3_ +| * | S | BR | BS | SM_AMIGA_4_ | | | | | A_19_ | | | | | A_16_ | | | | | A_18_ @@ -619,32 +619,28 @@ Equations : | * | S | BS | BR | IPL_030_1_ | * | S | BR | BS | CLK_EXP | * | S | BR | BS | RESET -| * | S | BR | BS | cpu_est_1_ -| * | S | BS | BR | SM_AMIGA_7_ +| * | S | BR | BS | SM_AMIGA_1_ +| * | S | BR | BR | inst_CLK_030_H | * | S | BR | BS | inst_CLK_OUT_PRE_25 -| * | S | BR | BS | SM_AMIGA_5_ -| * | S | BR | BS | SM_AMIGA_6_ | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ | * | S | BS | BR | RN_IPL_030_2_ +| * | S | BS | BR | inst_DTACK_D0 +| * | S | BS | BR | inst_BGACK_030_INT_D | | | | | A_29_ | | | | | A_30_ | | | | | A_31_ Block C -block level set pt : !RST +block level set pt : block level reset pt : Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| * | S | BS | BR | AVEC_EXP +| | | | | AVEC_EXP | | | | | AMIGA_BUS_ENABLE_LOW -| * | S | BR | BS | cpu_est_0_ -| * | S | BS | BR | inst_AS_030_000_SYNC -| * | S | BS | BR | RN_AVEC_EXP -| * | S | BS | BR | inst_CLK_000_D3 | | | | | BG_030 | | | | | A_24_ | | | | | A_25_ @@ -667,15 +663,16 @@ Equations : | * | S | BS | BR | VMA | * | S | BS | BR | BG_000 | | | | | AMIGA_BUS_ENABLE -| * | S | BS | BR | inst_CLK_000_D0 | * | S | BS | BR | inst_CLK_000_D1 +| * | S | BR | BS | cpu_est_1_ +| * | S | BR | BS | cpu_est_2_ +| * | S | BR | BS | cpu_est_0_ | * | S | BS | BR | RN_VMA -| * | S | BR | BS | SM_AMIGA_4_ +| * | S | BR | BS | SM_AMIGA_5_ | * | S | BS | BR | RN_LDS_000 | * | S | BS | BR | RN_UDS_000 | * | S | BS | BR | RN_BG_000 | * | S | BS | BR | RN_AS_000 -| * | S | BS | BR | inst_BGACK_030_INT_D | | | | | BGACK_000 @@ -716,10 +713,10 @@ Equations : | * | S | BR | BS | A0 | * | S | BS | BR | E | * | S | BS | BR | CLK_DIV_OUT +| * | S | BR | BS | inst_avec_expreg | * | S | BS | BR | RN_E -| * | S | BS | BR | cpu_est_2_ -| * | S | BS | BR | SM_AMIGA_2_ -| * | S | BS | BR | SM_AMIGA_3_ +| * | S | BR | BS | inst_RW_000_INT +| * | S | BS | BR | SM_AMIGA_6_ | | | | | IPL_2_ | | | | | IPL_0_ @@ -732,21 +729,21 @@ Equations : | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | AS_030 +| | | | | RW_000 | * | S | BS | BR | DSACK1 | * | S | BS | BR | SIZE_1_ -| | | | | RW_000 | * | S | BS | BR | BGACK_030 | * | S | BS | BR | FPU_CS | * | S | BS | BR | RN_BGACK_030 | * | S | BS | BR | RN_AS_030 -| * | S | BS | BR | inst_CLK_000_D2 -| * | S | BR | BR | inst_CLK_030_H +| * | S | BS | BR | inst_CLK_000_D0 +| * | S | BS | BR | SM_AMIGA_7_ +| * | S | BS | BR | inst_AS_030_000_SYNC | * | S | BS | BR | RN_FPU_CS -| * | S | BR | BS | SM_AMIGA_1_ +| * | S | BR | BS | SM_AMIGA_0_ +| * | S | BS | BR | inst_CLK_000_D2 | * | S | BR | BS | inst_CLK_OUT_PRE_50 -| * | S | BS | BR | inst_VPA_D | * | S | BS | BR | RN_DSACK1 -| * | S | BS | BR | inst_DTACK_D0 | * | S | BR | BS | inst_CLK_OUT_PRE_50_D | | | | | A_22_ | | | | | A_23_ @@ -766,20 +763,20 @@ BLOCK_A_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx A0 RST pin 86 mx A17 ... ... -mx A1 ... ... mx A18 ... ... -mx A2 ... ... mx A19 ... ... -mx A3 ... ... mx A20 RN_BGACK_030 mcell H4 +mx A0 RST pin 86 mx A17 RN_VMA mcell D1 +mx A1 SM_AMIGA_3_ mcell A4 mx A18 ... ... +mx A2 SM_AMIGA_4_ mcell A5 mx A19 ... ... +mx A3 SM_AMIGA_5_ mcell D11 mx A20 RN_BGACK_030 mcell H4 mx A4 CLK_030 pin 64 mx A21 RN_AS_030 mcell H6 mx A5 nEXP_SPACE pin 14 mx A22 ... ... -mx A6 SM_AMIGA_6_ mcell B9 mx A23 AS_000 pin 33 -mx A7 SM_AMIGA_1_ mcell H7 mx A24 LDS_000 pin 31 -mx A8 RW pin 71 mx A25 inst_RW_000_INT mcell A3 -mx A9 SM_AMIGA_0_ mcell A1 mx A26 ... ... -mx A10 ... ... mx A27 ... ... -mx A11 inst_CLK_000_D0 mcell D5 mx A28 RW_000 pin 80 +mx A6 RW_000 pin 80 mx A23 RN_E mcell G2 +mx A7 inst_CLK_000_D1 mcell D5 mx A24 LDS_000 pin 31 +mx A8 inst_DTACK_D0 mcell B8 mx A25 inst_VPA_D mcell A3 +mx A9 SM_AMIGA_2_ mcell A1 mx A26 AS_000 pin 33 +mx A10 VPA pin 36 mx A27 ... ... +mx A11 inst_CLK_000_D0 mcell H3 mx A28 inst_CLK_030_H mcell B5 mx A12 UDS_000 pin 32 mx A29 ... ... -mx A13 inst_CLK_030_H mcell H5 mx A30 ... ... +mx A13 cpu_est_1_ mcell D7 mx A30 ... ... mx A14 ... ... mx A31 ... ... mx A15 RN_DS_030 mcell A0 mx A32 ... ... mx A16 ... ... @@ -790,22 +787,22 @@ BLOCK_B_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx B0 RST pin 86 mx B17 SM_AMIGA_5_ mcell B8 -mx B1inst_CLK_OUT_PRE_25 mcell B7 mx B18 inst_CLK_000_D2 mcell H3 +mx B0 LDS_000 pin 31 mx B17 ... ... +mx B1inst_CLK_OUT_PRE_50 mcell H11 mx B18 ... ... mx B2 RN_IPL_030_1_ mcell B6 mx B19 ... ... -mx B3 IPL_1_ pin 56 mx B20 ... ... -mx B4 IPL_2_ pin 68 mx B21 cpu_est_2_ mcell G4 -mx B5 nEXP_SPACE pin 14 mx B22 cpu_est_0_ mcell C2 -mx B6 SM_AMIGA_6_ mcell B9 mx B23 RN_E mcell G2 -mx B7 inst_CLK_000_D0 mcell D5 mx B24 ... ... -mx B8 inst_CLK_000_D1 mcell D7 mx B25 ... ... -mx B9 SM_AMIGA_0_ mcell A1 mx B26 ... ... +mx B3 IPL_1_ pin 56 mx B20 CLK_030 pin 64 +mx B4 IPL_2_ pin 68 mx B21 RST pin 86 +mx B5 SM_AMIGA_1_ mcell B3 mx B22 ... ... +mx B6 ... ... mx B23 RN_BGACK_030 mcell H4 +mx B7 inst_CLK_000_D1 mcell D5 mx B24inst_CLK_OUT_PRE_25 mcell B7 +mx B8inst_CLK_OUT_PRE_50_D mcell H12 mx B25 ... ... +mx B9 SM_AMIGA_2_ mcell A1 mx B26 AS_000 pin 33 mx B10 RN_IPL_030_2_ mcell B2 mx B27 RN_IPL_030_0_ mcell B4 -mx B11inst_CLK_OUT_PRE_50 mcell H9 mx B28 SM_AMIGA_7_ mcell B5 -mx B12inst_AS_030_000_SYNC mcell C3 mx B29 ... ... -mx B13 cpu_est_1_ mcell B3 mx B30 ... ... -mx B14 inst_CLK_000_D3 mcell C4 mx B31 ... ... -mx B15inst_CLK_OUT_PRE_50_D mcell H12 mx B32 ... ... +mx B11 inst_CLK_000_D0 mcell H3 mx B28 inst_CLK_030_H mcell B5 +mx B12 UDS_000 pin 32 mx B29 ... ... +mx B13 ... ... mx B30 RN_AS_030 mcell H6 +mx B14 DTACK pin 30 mx B31 ... ... +mx B15 ... ... mx B32 ... ... mx B16 IPL_0_ pin 67 ---------------------------------------------------------------------------- @@ -814,21 +811,21 @@ BLOCK_C_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx C0 RST pin 86 mx C17 A_18_ pin 95 -mx C1 FC_1_ pin 58 mx C18 BGACK_000 pin 28 -mx C2inst_BGACK_030_INT_D mcell D10 mx C19 AS_030 pin 82 -mx C3 SM_AMIGA_2_ mcell G5 mx C20 CLK_030 pin 64 -mx C4inst_AS_030_000_SYNC mcell C3 mx C21 ... ... -mx C5 nEXP_SPACE pin 14 mx C22 cpu_est_0_ mcell C2 -mx C6 FC_0_ pin 57 mx C23 RN_BGACK_030 mcell H4 -mx C7 inst_CLK_000_D0 mcell D5 mx C24 ... ... -mx C8 A_17_ pin 59 mx C25 ... ... -mx C9 RN_AVEC_EXP mcell C0 mx C26 ... ... -mx C10 inst_CLK_000_D2 mcell H3 mx C27 ... ... -mx C11 A_16_ pin 96 mx C28 SM_AMIGA_7_ mcell B5 -mx C12 A_19_ pin 97 mx C29 ... ... -mx C13 inst_CLK_000_D1 mcell D7 mx C30 ... ... -mx C14 inst_CLK_000_D3 mcell C4 mx C31 ... ... +mx C0 ... ... mx C17 ... ... +mx C1 ... ... mx C18 ... ... +mx C2inst_avec_expreg mcell G4 mx C19 ... ... +mx C3 ... ... mx C20 ... ... +mx C4 ... ... mx C21 ... ... +mx C5 ... ... mx C22 ... ... +mx C6 ... ... mx C23 ... ... +mx C7 ... ... mx C24 ... ... +mx C8 ... ... mx C25 ... ... +mx C9 ... ... mx C26 ... ... +mx C10 ... ... mx C27 ... ... +mx C11 ... ... mx C28 ... ... +mx C12 ... ... mx C29 ... ... +mx C13 ... ... mx C30 ... ... +mx C14 ... ... mx C31 ... ... mx C15 ... ... mx C32 ... ... mx C16 ... ... ---------------------------------------------------------------------------- @@ -838,21 +835,21 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 A0 pin 69 mx D17 RN_VMA mcell D1 -mx D1 ... ... mx D18 inst_VPA_D mcell H10 -mx D2 cpu_est_2_ mcell G4 mx D19 AS_030 pin 82 -mx D3 CLK_000 pin 11 mx D20 RN_BGACK_030 mcell H4 -mx D4 BG_030 pin 21 mx D21 RST pin 86 -mx D5 DS_030 pin 98 mx D22 cpu_est_0_ mcell C2 -mx D6 SIZE_1_ pin 79 mx D23 RN_E mcell G2 -mx D7 RN_AS_030 mcell H6 mx D24 inst_CLK_000_D0 mcell D5 -mx D8 SM_AMIGA_5_ mcell B8 mx D25 RW pin 71 -mx D9 RN_AVEC_EXP mcell C0 mx D26 ... ... -mx D10 RN_AS_000 mcell D4 mx D27 ... ... -mx D11 inst_CLK_000_D2 mcell H3 mx D28 RN_BG_000 mcell D2 -mx D12 SM_AMIGA_4_ mcell D9 mx D29 ... ... -mx D13 cpu_est_1_ mcell B3 mx D30 RN_UDS_000 mcell D6 -mx D14 SIZE_0_ pin 70 mx D31 SM_AMIGA_7_ mcell B5 +mx D0 RN_BGACK_030 mcell H4 mx D17 SIZE_0_ pin 70 +mx D1 ... ... mx D18 A0 pin 69 +mx D2inst_avec_expreg mcell G4 mx D19 SM_AMIGA_5_ mcell D11 +mx D3 RN_BG_000 mcell D2 mx D20 cpu_est_0_ mcell D10 +mx D4 SM_AMIGA_7_ mcell H5 mx D21 RST pin 86 +mx D5 DS_030 pin 98 mx D22 BG_030 pin 21 +mx D6 SIZE_1_ pin 79 mx D23 SM_AMIGA_6_ mcell G6 +mx D7 RN_AS_030 mcell H6 mx D24 CLK_000 pin 11 +mx D8 RW pin 71 mx D25 inst_VPA_D mcell A3 +mx D9 AS_030 pin 82 mx D26 ... ... +mx D10 inst_CLK_000_D0 mcell H3 mx D27 RN_VMA mcell D1 +mx D11 inst_CLK_000_D1 mcell D5 mx D28 ... ... +mx D12 cpu_est_2_ mcell D9 mx D29 ... ... +mx D13 cpu_est_1_ mcell D7 mx D30 RN_UDS_000 mcell D6 +mx D14 RN_AS_000 mcell D4 mx D31 RN_E mcell G2 mx D15 nEXP_SPACE pin 14 mx D32 DSACK1 pin 81 mx D16 RN_LDS_000 mcell D8 ---------------------------------------------------------------------------- @@ -886,21 +883,21 @@ BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx G0 RST pin 86 mx G17 ... ... -mx G1 inst_DTACK_D0 mcell H11 mx G18 inst_VPA_D mcell H10 -mx G2 RN_VMA mcell D1 mx G19 ... ... -mx G3 SM_AMIGA_2_ mcell G5 mx G20 RN_BGACK_030 mcell H4 -mx G4 RN_E mcell G2 mx G21 RN_AS_030 mcell H6 -mx G5 cpu_est_1_ mcell B3 mx G22 cpu_est_0_ mcell C2 -mx G6 inst_RW_000_INT mcell A3 mx G23 SM_AMIGA_3_ mcell G6 -mx G7 inst_CLK_000_D0 mcell D5 mx G24inst_CLK_OUT_PRE_25 mcell B7 -mx G8 UDS_000 pin 32 mx G25 ... ... -mx G9 ... ... mx G26 AS_000 pin 33 -mx G10 ... ... mx G27 LDS_000 pin 31 -mx G11 cpu_est_2_ mcell G4 mx G28 ... ... -mx G12 SM_AMIGA_4_ mcell D9 mx G29 ... ... -mx G13 inst_CLK_000_D1 mcell D7 mx G30 ... ... -mx G14 ... ... mx G31 ... ... +mx G0 LDS_000 pin 31 mx G17 ... ... +mx G1inst_CLK_OUT_PRE_25 mcell B7 mx G18 inst_CLK_000_D2 mcell H10 +mx G2 cpu_est_0_ mcell D10 mx G19 ... ... +mx G3 inst_RW_000_INT mcell G5 mx G20 RN_BGACK_030 mcell H4 +mx G4 CLK_030 pin 64 mx G21 RST pin 86 +mx G5 SM_AMIGA_0_ mcell H9 mx G22 ... ... +mx G6inst_BGACK_030_INT_D mcell B9 mx G23 SM_AMIGA_6_ mcell G6 +mx G7 cpu_est_2_ mcell D9 mx G24 inst_CLK_000_D1 mcell D5 +mx G8 cpu_est_1_ mcell D7 mx G25 RW pin 71 +mx G9 AS_030 pin 82 mx G26 AS_000 pin 33 +mx G10 inst_CLK_000_D0 mcell H3 mx G27 SM_AMIGA_7_ mcell H5 +mx G11inst_avec_expreg mcell G4 mx G28 RW_000 pin 80 +mx G12 UDS_000 pin 32 mx G29inst_AS_030_000_SYNC mcell H7 +mx G13 SM_AMIGA_1_ mcell B3 mx G30 RN_AS_030 mcell H6 +mx G14 ... ... mx G31 RN_E mcell G2 mx G15 nEXP_SPACE pin 14 mx G32 ... ... mx G16 ... ... ---------------------------------------------------------------------------- @@ -911,21 +908,21 @@ BLOCK_H_LOGIC_ARRAY_FANIN CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx H0 LDS_000 pin 31 mx H17 FC_0_ pin 57 -mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28 -mx H2 ... ... mx H19 AS_030 pin 82 -mx H3 RN_DSACK1 mcell H8 mx H20 CLK_030 pin 64 -mx H4 A_18_ pin 95 mx H21 RST pin 86 -mx H5inst_CLK_OUT_PRE_50 mcell H9 mx H22 SM_AMIGA_2_ mcell G5 +mx H1 FC_1_ pin 58 mx H18 inst_CLK_000_D2 mcell H10 +mx H2 ... ... mx H19 SM_AMIGA_1_ mcell B3 +mx H3 CLK_000 pin 11 mx H20inst_AS_030_000_SYNC mcell H7 +mx H4 BGACK_000 pin 28 mx H21 RST pin 86 +mx H5 SM_AMIGA_0_ mcell H9 mx H22inst_CLK_OUT_PRE_50 mcell H11 mx H6 A_19_ pin 97 mx H23 RN_BGACK_030 mcell H4 -mx H7 SM_AMIGA_1_ mcell H7 mx H24 inst_CLK_000_D0 mcell D5 -mx H8 inst_CLK_000_D1 mcell D7 mx H25 inst_RW_000_INT mcell A3 -mx H9 DTACK pin 30 mx H26 AS_000 pin 33 -mx H10 VPA pin 36 mx H27 A_17_ pin 59 -mx H11 A_16_ pin 96 mx H28 ... ... +mx H7 RN_AS_030 mcell H6 mx H24 inst_CLK_000_D1 mcell D5 +mx H8 A_17_ pin 59 mx H25 ... ... +mx H9 AS_030 pin 82 mx H26 AS_000 pin 33 +mx H10 inst_CLK_000_D0 mcell H3 mx H27 SM_AMIGA_7_ mcell H5 +mx H11 A_16_ pin 96 mx H28 CLK_030 pin 64 mx H12 UDS_000 pin 32 mx H29 ... ... -mx H13 inst_CLK_030_H mcell H5 mx H30 RN_AS_030 mcell H6 -mx H14 RN_FPU_CS mcell H2 mx H31 ... ... -mx H15 nEXP_SPACE pin 14 mx H32 ... ... +mx H13 RN_DSACK1 mcell H8 mx H30 ... ... +mx H14 RN_FPU_CS mcell H2 mx H31 A_18_ pin 95 +mx H15 nEXP_SPACE pin 14 mx H32 inst_RW_000_INT mcell G5 mx H16 ... ... ---------------------------------------------------------------------------- @@ -951,9 +948,7 @@ PostFit_Equations 1 1 1 Pin DTACK 1 3 1 Pin DTACK.OE 1 0 1 Pin AVEC - 3 8 1 Pin AVEC_EXP.D- - 1 1 1 Pin AVEC_EXP.AP - 1 1 1 Pin AVEC_EXP.C + 1 1 1 Pin AVEC_EXP 1 1 1 Pin RW 1 1 1 Pin RW.OE 1 1 1 Pin AMIGA_BUS_ENABLE @@ -968,30 +963,30 @@ PostFit_Equations 3 4 1 Pin IPL_030_2_.D 1 1 1 Pin IPL_030_2_.AP 1 1 1 Pin IPL_030_2_.C + 3 4 1 Pin IPL_030_1_.D + 1 1 1 Pin IPL_030_1_.AP + 1 1 1 Pin IPL_030_1_.C + 3 4 1 Pin IPL_030_0_.D + 1 1 1 Pin IPL_030_0_.AP + 1 1 1 Pin IPL_030_0_.C 1 3 1 Pin AS_030.OE 4 6 1 Pin AS_030.D 1 1 1 Pin AS_030.AP 1 1 1 Pin AS_030.C - 3 4 1 Pin IPL_030_1_.D - 1 1 1 Pin IPL_030_1_.AP - 1 1 1 Pin IPL_030_1_.C 1 1 1 Pin AS_000.OE 2 4 1 Pin AS_000.D- 1 1 1 Pin AS_000.AP 1 1 1 Pin AS_000.C - 3 4 1 Pin IPL_030_0_.D - 1 1 1 Pin IPL_030_0_.AP - 1 1 1 Pin IPL_030_0_.C 1 3 1 Pin DS_030.OE 7 9 1 Pin DS_030.D 1 1 1 Pin DS_030.AP 1 1 1 Pin DS_030.C 1 1 1 Pin UDS_000.OE - 7 9 1 Pin UDS_000.D- + 7 8 1 Pin UDS_000.D- 1 1 1 Pin UDS_000.AP 1 1 1 Pin UDS_000.C 1 1 1 Pin LDS_000.OE - 11 11 1 Pin LDS_000.D- + 11 10 1 Pin LDS_000.D- 1 1 1 Pin LDS_000.AP 1 1 1 Pin LDS_000.C 1 3 1 Pin A0.OE @@ -1011,7 +1006,7 @@ PostFit_Equations 1 1 1 Pin FPU_CS.AP 1 1 1 Pin FPU_CS.C 1 1 1 Pin DSACK1.OE - 2 4 1 Pin DSACK1.D- + 2 3 1 Pin DSACK1.D 1 1 1 Pin DSACK1.AP 1 1 1 Pin DSACK1.C 3 6 1 PinX1 E.D.X1 @@ -1029,7 +1024,10 @@ PostFit_Equations 1 4 1 Pin SIZE_0_.D- 1 1 1 Pin SIZE_0_.AP 1 1 1 Pin SIZE_0_.C - 8 17 1 Node inst_AS_030_000_SYNC.D + 6 12 1 Node inst_avec_expreg.D- + 1 1 1 Node inst_avec_expreg.AP + 1 1 1 Node inst_avec_expreg.C + 8 16 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C 1 1 1 Node inst_BGACK_030_INT_D.D @@ -1047,9 +1045,6 @@ PostFit_Equations 1 1 1 Node inst_CLK_000_D1.D 1 1 1 Node inst_CLK_000_D1.AP 1 1 1 Node inst_CLK_000_D1.C - 1 1 1 Node inst_CLK_000_D2.D - 1 1 1 Node inst_CLK_000_D2.AP - 1 1 1 Node inst_CLK_000_D2.C 1 1 1 Node inst_DTACK_D0.D 1 1 1 Node inst_DTACK_D0.AP 1 1 1 Node inst_DTACK_D0.C @@ -1059,38 +1054,38 @@ PostFit_Equations 1 1 1 Node inst_CLK_OUT_PRE_25.AR 3 3 1 Node inst_CLK_OUT_PRE_25.D 1 1 1 Node inst_CLK_OUT_PRE_25.C - 4 7 1 Node SM_AMIGA_7_.D- - 1 1 1 Node SM_AMIGA_7_.AP - 1 1 1 Node SM_AMIGA_7_.C + 1 1 1 Node SM_AMIGA_1_.AR + 2 3 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C 1 1 1 Node SM_AMIGA_6_.AR 2 7 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C 1 1 1 Node SM_AMIGA_0_.AR 2 3 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C - 1 1 1 Node SM_AMIGA_5_.AR - 2 3 1 Node SM_AMIGA_5_.D - 1 1 1 Node SM_AMIGA_5_.C - 1 1 1 Node SM_AMIGA_2_.AR - 3 9 1 Node SM_AMIGA_2_.D - 1 1 1 Node SM_AMIGA_2_.C + 4 7 1 Node SM_AMIGA_7_.D- + 1 1 1 Node SM_AMIGA_7_.AP + 1 1 1 Node SM_AMIGA_7_.C 14 11 1 Node inst_RW_000_INT.D- 1 1 1 Node inst_RW_000_INT.AP 1 1 1 Node inst_RW_000_INT.C - 1 1 1 Node inst_CLK_000_D3.D - 1 1 1 Node inst_CLK_000_D3.AP - 1 1 1 Node inst_CLK_000_D3.C + 1 1 1 Node inst_CLK_000_D2.D + 1 1 1 Node inst_CLK_000_D2.AP + 1 1 1 Node inst_CLK_000_D2.C 5 8 1 Node inst_CLK_030_H.D 1 1 1 Node inst_CLK_030_H.C + 1 1 1 Node SM_AMIGA_5_.AR + 2 3 1 Node SM_AMIGA_5_.D + 1 1 1 Node SM_AMIGA_5_.C 1 1 1 Node SM_AMIGA_4_.AR 2 3 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C 1 1 1 Node SM_AMIGA_3_.AR 4 9 1 Node SM_AMIGA_3_.D- 1 1 1 Node SM_AMIGA_3_.C - 1 1 1 Node SM_AMIGA_1_.AR - 2 3 1 Node SM_AMIGA_1_.D - 1 1 1 Node SM_AMIGA_1_.C + 1 1 1 Node SM_AMIGA_2_.AR + 3 9 1 Node SM_AMIGA_2_.D + 1 1 1 Node SM_AMIGA_2_.C 1 1 1 Node cpu_est_0_.AR 3 3 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C @@ -1102,7 +1097,7 @@ PostFit_Equations 1 1 1 Node cpu_est_2_.AR 1 1 1 Node cpu_est_2_.C ========= - 248 P-Term Total: 248 + 249 P-Term Total: 249 Total Pins: 59 Total Nodes: 24 Average P-Term/Output: 2 @@ -1130,19 +1125,13 @@ DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); AVEC = (1); -!AVEC_EXP.D = (!BGACK_030.Q - # inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q & !AVEC_EXP - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q); - -AVEC_EXP.AP = (!RST); - -AVEC_EXP.C = (CLK_OSZI); +AVEC_EXP = (inst_avec_expreg.Q); RW = (inst_RW_000_INT.Q); RW.OE = (!BGACK_030.Q); -AMIGA_BUS_ENABLE = (AVEC_EXP); +AMIGA_BUS_ENABLE = (inst_avec_expreg.Q); AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW.PIN # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW.PIN); @@ -1170,6 +1159,22 @@ IPL_030_2_.AP = (!RST); IPL_030_2_.C = (CLK_OSZI); +IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q + # inst_CLK_000_D1.Q & IPL_030_1_.Q + # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); + +IPL_030_1_.AP = (!RST); + +IPL_030_1_.C = (CLK_OSZI); + +IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q + # inst_CLK_000_D1.Q & IPL_030_0_.Q + # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); + +IPL_030_0_.AP = (!RST); + +IPL_030_0_.C = (CLK_OSZI); + AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); AS_030.D = (BGACK_030.Q @@ -1181,31 +1186,15 @@ AS_030.AP = (!RST); AS_030.C = (CLK_OSZI); -IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q - # inst_CLK_000_D1.Q & IPL_030_1_.Q - # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); - -IPL_030_1_.AP = (!RST); - -IPL_030_1_.C = (CLK_OSZI); - AS_000.OE = (BGACK_030.Q); -!AS_000.D = (inst_CLK_000_D2.Q & SM_AMIGA_5_.Q +!AS_000.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q # !AS_000.Q & !AS_030.PIN); AS_000.AP = (!RST); AS_000.C = (CLK_OSZI); -IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q - # inst_CLK_000_D1.Q & IPL_030_0_.Q - # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); - -IPL_030_0_.AP = (!RST); - -IPL_030_0_.C = (CLK_OSZI); - DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & !AS_030.Q); DS_030.D = (BGACK_030.Q @@ -1223,12 +1212,12 @@ DS_030.C = (CLK_OSZI); UDS_000.OE = (BGACK_030.Q); !UDS_000.D = (!UDS_000.Q & !AS_030.PIN & DS_030.PIN - # !inst_CLK_000_D2.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN - # !SM_AMIGA_5_.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN - # !inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & !RW.PIN - # !UDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN & !RW.PIN - # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN & RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !A0.PIN & !RW.PIN); + # !inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN + # !SM_AMIGA_6_.Q & !UDS_000.Q & !AS_030.PIN & RW.PIN + # inst_CLK_000_D0.Q & !UDS_000.Q & !AS_030.PIN & !RW.PIN + # !UDS_000.Q & !SM_AMIGA_5_.Q & !AS_030.PIN & !RW.PIN + # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & !A0.PIN & RW.PIN + # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN & !RW.PIN); UDS_000.AP = (!RST); @@ -1237,16 +1226,16 @@ UDS_000.C = (CLK_OSZI); LDS_000.OE = (BGACK_030.Q); !LDS_000.D = (!LDS_000.Q & !AS_030.PIN & DS_030.PIN - # !inst_CLK_000_D2.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN - # !SM_AMIGA_5_.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN - # !inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & !RW.PIN - # !LDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN & !RW.PIN - # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !SIZE_0_.PIN & RW.PIN - # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_1_.PIN & RW.PIN - # inst_CLK_000_D2.Q & SM_AMIGA_5_.Q & !DS_030.PIN & A0.PIN & RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & !SIZE_0_.PIN & !RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & SIZE_1_.PIN & !RW.PIN - # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q & !DS_030.PIN & A0.PIN & !RW.PIN); + # !inst_CLK_000_D0.Q & !LDS_000.Q & !SM_AMIGA_5_.Q & !AS_030.PIN + # !inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN + # !SM_AMIGA_6_.Q & !LDS_000.Q & !AS_030.PIN & RW.PIN + # inst_CLK_000_D0.Q & !LDS_000.Q & !AS_030.PIN & !RW.PIN + # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & !SIZE_0_.PIN & RW.PIN + # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & SIZE_1_.PIN & RW.PIN + # inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !DS_030.PIN & A0.PIN & RW.PIN + # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & !SIZE_0_.PIN & !RW.PIN + # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_1_.PIN & !RW.PIN + # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q & !DS_030.PIN & A0.PIN & !RW.PIN); LDS_000.AP = (!RST); @@ -1289,8 +1278,8 @@ FPU_CS.C = (CLK_OSZI); DSACK1.OE = (nEXP_SPACE); -!DSACK1.D = (inst_CLK_000_D0.Q & SM_AMIGA_2_.Q - # !DSACK1.Q & !AS_030.PIN); +DSACK1.D = (!SM_AMIGA_1_.Q & DSACK1.Q + # !SM_AMIGA_1_.Q & AS_030.PIN); DSACK1.AP = (!RST); @@ -1329,13 +1318,24 @@ SIZE_0_.AP = (!RST); SIZE_0_.C = (CLK_OSZI); -inst_AS_030_000_SYNC.D = (AS_030.PIN +!inst_avec_expreg.D = (!BGACK_030.Q + # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_1_.Q & !AS_030.PIN + # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & SM_AMIGA_0_.Q & !AS_030.PIN + # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & inst_CLK_000_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q + # !inst_avec_expreg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q + # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_0_.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q); + +inst_avec_expreg.AP = (!RST); + +inst_avec_expreg.C = (CLK_OSZI); + +inst_AS_030_000_SYNC.D = (SM_AMIGA_1_.Q + # AS_030.PIN # !nEXP_SPACE & inst_AS_030_000_SYNC.Q # !CLK_030 & inst_AS_030_000_SYNC.Q # !BGACK_030.Q & inst_AS_030_000_SYNC.Q # inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q - # !nEXP_SPACE & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q + # !nEXP_SPACE & !inst_CLK_000_D1.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q # FC_1_ & BGACK_000 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q); inst_AS_030_000_SYNC.AP = (!RST); @@ -1372,12 +1372,6 @@ inst_CLK_000_D1.AP = (!RST); inst_CLK_000_D1.C = (CLK_OSZI); -inst_CLK_000_D2.D = (inst_CLK_000_D1.Q); - -inst_CLK_000_D2.AP = (!RST); - -inst_CLK_000_D2.C = (CLK_OSZI); - inst_DTACK_D0.D = (DTACK.PIN); inst_DTACK_D0.AP = (!RST); @@ -1398,43 +1392,35 @@ inst_CLK_OUT_PRE_25.D = (inst_CLK_OUT_PRE_50_D.Q & inst_CLK_OUT_PRE_25.Q inst_CLK_OUT_PRE_25.C = (CLK_OSZI); -!SM_AMIGA_7_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q - # !SM_AMIGA_7_.Q & !SM_AMIGA_0_.Q - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D0.Q & !inst_CLK_000_D2.Q & inst_CLK_000_D3.Q - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & !SM_AMIGA_0_.Q & inst_CLK_000_D3.Q); +SM_AMIGA_1_.AR = (!RST); -SM_AMIGA_7_.AP = (!RST); +SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q + # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q); -SM_AMIGA_7_.C = (CLK_OSZI); +SM_AMIGA_1_.C = (CLK_OSZI); SM_AMIGA_6_.AR = (!RST); -SM_AMIGA_6_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q & SM_AMIGA_6_.Q - # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D2.Q & SM_AMIGA_7_.Q & inst_CLK_000_D3.Q); +SM_AMIGA_6_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q + # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & SM_AMIGA_7_.Q & inst_CLK_000_D2.Q); SM_AMIGA_6_.C = (CLK_OSZI); SM_AMIGA_0_.AR = (!RST); -SM_AMIGA_0_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_0_.Q - # !inst_CLK_000_D0.Q & SM_AMIGA_1_.Q); +SM_AMIGA_0_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_1_.Q + # !inst_CLK_000_D0.Q & SM_AMIGA_0_.Q); SM_AMIGA_0_.C = (CLK_OSZI); -SM_AMIGA_5_.AR = (!RST); +!SM_AMIGA_7_.D = (!inst_CLK_000_D0.Q & !SM_AMIGA_7_.Q + # !SM_AMIGA_0_.Q & !SM_AMIGA_7_.Q + # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & inst_CLK_000_D2.Q + # nEXP_SPACE & !inst_AS_030_000_SYNC.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_0_.Q & inst_CLK_000_D2.Q); -SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_5_.Q); +SM_AMIGA_7_.AP = (!RST); -SM_AMIGA_5_.C = (CLK_OSZI); - -SM_AMIGA_2_.AR = (!RST); - -SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q - # inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q - # !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); - -SM_AMIGA_2_.C = (CLK_OSZI); +SM_AMIGA_7_.C = (CLK_OSZI); !inst_RW_000_INT.D = (CLK_030 & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q # BGACK_030.Q & !inst_CLK_000_D0.Q & !inst_RW_000_INT.Q @@ -1455,11 +1441,11 @@ inst_RW_000_INT.AP = (!RST); inst_RW_000_INT.C = (CLK_OSZI); -inst_CLK_000_D3.D = (inst_CLK_000_D2.Q); +inst_CLK_000_D2.D = (inst_CLK_000_D1.Q); -inst_CLK_000_D3.AP = (!RST); +inst_CLK_000_D2.AP = (!RST); -inst_CLK_000_D3.C = (CLK_OSZI); +inst_CLK_000_D2.C = (CLK_OSZI); inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q # !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN @@ -1469,6 +1455,13 @@ inst_CLK_030_H.D = (!RST & inst_CLK_030_H.Q inst_CLK_030_H.C = (CLK_OSZI); +SM_AMIGA_5_.AR = (!RST); + +SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_6_.Q + # inst_CLK_000_D0.Q & SM_AMIGA_5_.Q); + +SM_AMIGA_5_.C = (CLK_OSZI); + SM_AMIGA_4_.AR = (!RST); SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q @@ -1485,12 +1478,13 @@ SM_AMIGA_3_.AR = (!RST); SM_AMIGA_3_.C = (CLK_OSZI); -SM_AMIGA_1_.AR = (!RST); +SM_AMIGA_2_.AR = (!RST); -SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_2_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_1_.Q); +SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q + # inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & !inst_DTACK_D0.Q & SM_AMIGA_3_.Q + # !VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & inst_CLK_000_D1.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); -SM_AMIGA_1_.C = (CLK_OSZI); +SM_AMIGA_2_.C = (CLK_OSZI); cpu_est_0_.AR = (!RST); diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index 1f36523..f60aec6 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -35,21 +35,19 @@ SIGNAL NAME min max min max min max min max inst_DTACK_D0 1 2 .. .. .. .. 1 1 inst_RW_000_INT 1 1 1 2 .. .. 2 2 DTACK .. .. .. .. 1 1 .. .. - AVEC_EXP 1 1 0 1 .. .. 1 1 - RN_AVEC_EXP 1 1 0 1 .. .. 1 1 AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. .. CIIN .. .. .. .. 1 1 .. .. SIZE_1_ 1 1 0 0 .. .. .. .. IPL_030_2_ 1 1 0 0 .. .. 1 1 RN_IPL_030_2_ 1 1 0 0 .. .. 1 1 - AS_030 1 1 0 0 .. .. 1 1 - RN_AS_030 1 1 0 0 .. .. 1 1 IPL_030_1_ 1 1 0 0 .. .. 1 1 RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 - AS_000 1 1 0 0 .. .. 1 1 - RN_AS_000 1 1 0 0 .. .. 1 1 IPL_030_0_ 1 1 0 0 .. .. 1 1 RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 + AS_030 1 1 0 0 .. .. 1 1 + RN_AS_030 1 1 0 0 .. .. 1 1 + AS_000 1 1 0 0 .. .. 1 1 + RN_AS_000 1 1 0 0 .. .. 1 1 DS_030 1 1 0 0 .. .. 1 1 RN_DS_030 1 1 0 0 .. .. 1 1 UDS_000 1 1 0 0 .. .. 1 1 @@ -70,25 +68,25 @@ AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. .. VMA .. .. 0 0 .. .. 1 1 RN_VMA .. .. 0 0 .. .. 1 1 SIZE_0_ 1 1 0 0 .. .. .. .. +inst_avec_expreg 1 1 1 1 .. .. .. .. inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1 inst_BGACK_030_INT_D .. .. .. .. .. .. 1 1 inst_VPA_D 1 1 .. .. .. .. 1 1 inst_CLK_OUT_PRE_50_D .. .. .. .. .. .. 1 1 inst_CLK_000_D0 1 1 .. .. .. .. 1 1 inst_CLK_000_D1 .. .. .. .. .. .. 1 1 - inst_CLK_000_D2 .. .. .. .. .. .. 1 1 inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1 inst_CLK_OUT_PRE_25 .. .. .. .. .. .. 1 1 - SM_AMIGA_7_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_1_ .. .. .. .. .. .. 1 1 SM_AMIGA_6_ 1 1 .. .. .. .. 1 1 SM_AMIGA_0_ .. .. .. .. .. .. 1 1 - SM_AMIGA_5_ .. .. .. .. .. .. 1 1 - SM_AMIGA_2_ .. .. .. .. .. .. 1 1 - inst_CLK_000_D3 .. .. .. .. .. .. 1 1 + SM_AMIGA_7_ 1 1 .. .. .. .. 1 1 + inst_CLK_000_D2 .. .. .. .. .. .. 1 1 inst_CLK_030_H 1 1 .. .. .. .. 1 1 + SM_AMIGA_5_ .. .. .. .. .. .. 1 1 SM_AMIGA_4_ .. .. .. .. .. .. 1 1 SM_AMIGA_3_ .. .. .. .. .. .. 1 1 - SM_AMIGA_1_ .. .. .. .. .. .. 1 1 + SM_AMIGA_2_ .. .. .. .. .. .. 1 1 cpu_est_0_ .. .. .. .. .. .. 1 1 cpu_est_1_ .. .. .. .. .. .. 1 1 cpu_est_2_ .. .. .. .. .. .. 1 1 \ No newline at end of file diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index 3587338..a6027aa 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,375 +1,370 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sun Jun 01 01:03:24 2014 +#$ DATE Sat Jun 07 23:03:19 2014 #$ MODULE 68030_tk -#$ PINS 59 A_26_ A_25_ A_24_ A_23_ A_31_ A_22_ A_21_ A_20_ A_19_ IPL_2_ A_18_ A_17_ FC_1_ A_16_ RW_000 IPL_1_ IPL_0_ FC_0_ nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ SIZE_1_ IPL_030_2_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ DS_030 UDS_000 LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_ -#$ NODES 25 inst_avec_expreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_7_ SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_5_ SM_AMIGA_2_ inst_RW_000_INT inst_CLK_000_D3 inst_CLK_030_H SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_1_ cpu_est_0_ cpu_est_1_ cpu_est_2_ +#$ PINS 59 A_22_ A_21_ A_20_ A_19_ A_31_ A_18_ A_17_ A_16_ IPL_2_ IPL_1_ FC_1_ IPL_0_ FC_0_ RW_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ SIZE_1_ IPL_030_2_ IPL_030_1_ IPL_030_0_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_ +#$ NODES 24 inst_avec_expreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_1_ SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_7_ inst_RW_000_INT inst_CLK_000_D2 inst_CLK_030_H SM_AMIGA_5_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_ .type fr -.i 80 -.o 158 -.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q inst_avec_expreg.Q VMA.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q inst_CLK_OUT_PRE_50_D.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_DTACK_D0.Q IPL_030_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q IPL_030_1_.Q SM_AMIGA_7_.Q IPL_030_2_.Q AS_000.Q SM_AMIGA_6_.Q SM_AMIGA_0_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q inst_RW_000_INT.Q UDS_000.Q LDS_000.Q DSACK1.Q inst_CLK_000_D3.Q inst_CLK_030_H.Q DS_030.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN RW.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR SIZE_1_.C SIZE_1_.AP IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR DSACK1.C DSACK1.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_0_.C SIZE_0_.AP LDS_000.C LDS_000.AP FPU_CS.C FPU_CS.AP inst_avec_expreg.C inst_avec_expreg.AP BG_000.C BG_000.AP DS_030.C DS_030.AP AS_030.C AS_030.AP AS_000.C AS_000.AP inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.C UDS_000.C UDS_000.AP A0.C A0.AP inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_EXP.C CLK_EXP.AR inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESET.C RESET.AR RW_000 DTACK RW AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D BG_000.D BGACK_030.D FPU_CS.D inst_avec_expreg.D VMA.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D AS_030.D inst_VPA_D.D inst_CLK_OUT_PRE_50_D.D inst_CLK_000_D0.D CLK_EXP.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_DTACK_D0.D IPL_030_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D IPL_030_1_.D SM_AMIGA_7_.D IPL_030_2_.D AS_000.D SM_AMIGA_6_.D SM_AMIGA_0_.D SM_AMIGA_5_.D SM_AMIGA_2_.D inst_RW_000_INT.D UDS_000.D LDS_000.D DSACK1.D inst_CLK_000_D3.D inst_CLK_030_H.D DS_030.D SIZE_0_.D SIZE_1_.D A0.D RESET.D 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~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------1------------------------------------------------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------0-------------0------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -----------------------------------------------------0--0------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ------------------------------------------0--------------0-----------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -----------------------------------------------------0---0-----------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ----------------------------------------------------------------------1---------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------1----------1------------------0--0----1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------------------------------------------1----------1------------------0---1---1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------------------------------------------1----------1------------------0----1--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------------------------------------------1----------1------------------0----0--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -------------------------------0------------------------------------------------0 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1--------------------------------1----------1----------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ -------------------------------1--------1----------1----------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ ----------------------------------------0---------------0------------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ----------------------------------------0----------------0-----------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ --------------------------------------------------------0-----0------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ---------------------------------------------------------0----0------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ----------------------------------------1----------1------------------1---------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ ----------------------------------------1----------1---------------------11-----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ ----------------------------------------1---------------------1---------0--0----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ----------------------------------------1---------------------1---------0---1---0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ----------------------------------------1---------------------1---------0----1--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ----------------------------------------1---------------------1---------0----0--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +.i 79 +.o 155 +.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q inst_avec_expreg.Q VMA.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q inst_CLK_OUT_PRE_50_D.Q inst_CLK_000_D0.Q BG_000.Q inst_CLK_000_D1.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q SM_AMIGA_1_.Q AS_000.Q SM_AMIGA_6_.Q SM_AMIGA_0_.Q SM_AMIGA_7_.Q inst_RW_000_INT.Q UDS_000.Q LDS_000.Q DSACK1.Q IPL_030_0_.Q inst_CLK_000_D2.Q IPL_030_1_.Q inst_CLK_030_H.Q DS_030.Q IPL_030_2_.Q SM_AMIGA_5_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN RW.PIN +.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR cpu_est_0_.C cpu_est_0_.AR IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_0_.C SIZE_0_.AP SIZE_1_.C SIZE_1_.AP LDS_000.C LDS_000.AP FPU_CS.C FPU_CS.AP inst_avec_expreg.C inst_avec_expreg.AP BG_000.C BG_000.AP DS_030.C DS_030.AP AS_030.C AS_030.AP AS_000.C AS_000.AP DSACK1.C DSACK1.AP inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.C UDS_000.C UDS_000.AP A0.C A0.AP inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_EXP.C CLK_EXP.AR inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESET.C RESET.AR RW_000 DTACK RW AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D FPU_CS.D inst_avec_expreg.D VMA.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D AS_030.D inst_VPA_D.D inst_CLK_OUT_PRE_50_D.D inst_CLK_000_D0.D BG_000.D inst_CLK_000_D1.D inst_DTACK_D0.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D SM_AMIGA_1_.D AS_000.D SM_AMIGA_6_.D SM_AMIGA_0_.D SM_AMIGA_7_.D inst_RW_000_INT.D CLK_EXP.D UDS_000.D LDS_000.D DSACK1.D IPL_030_0_.D inst_CLK_000_D2.D IPL_030_1_.D inst_CLK_030_H.D DS_030.D IPL_030_2_.D SIZE_0_.D SIZE_1_.D A0.D SM_AMIGA_5_.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_2_.D RESET.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D +.p 358 +------------------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +---1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1---------------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0-------------------------------------------------------------------- ~~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +0----------0000000------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------1111--------------------------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~11~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~1~11~~~~~~~~~~ +-----1-----------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0---------------------------1------------------------------------------------ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1--------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +------1-------------------------------1-------01------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------1-------01------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +----------0---------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------0----------------------------1--------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------------------------------0-------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +----------------------------------------1-----------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------------------------------1--------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +--------------------------------------0--------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +--------------------------------------0------------1-------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +--------------------------------------1---------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +--------------------------------------0---------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +--------------------------------1---0------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +--------------------------------------1----------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +----------------------------------------0--------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +------------------------------------1----1-------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +------------------------------------1-0-10-------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------1-----------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-----------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------0------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +----------------------------------------1----------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +--------------------------------1------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-0----------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +--------------------------------1-------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0------------------------1--1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +--------------------------------------1-0----------------------00-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +--------------------------------------0--------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------1------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------------------------11------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +--------------------------------------1-0----------------------1-0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------------1-0-----------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------------0---------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +----------------------------------------1-------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------------1-0----------------------1--1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------------------------0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------0---0-0-1--------------------1--0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------1-0-----------------------011------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-----------------------------------------------------------------01------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------------1-0----------------------1-01------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +------------------------------------0------------------------1----0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +--------------------------------------1-0----------------------1-10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +--------------------------------------1------1-----------------0110------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-0-----------------------000------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-------------------------------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0----------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------0-----1----------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------0----------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +----------------------------------------------0--------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1-----------------1-------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------------1---1------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------0-------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +---------------------------------------1---------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~1~11~~~~~~~~~~ +--------------------------------------1-------01--------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0----------1------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0--1------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1---------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +------1--------------------------------------------------1-----------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------------------------------------------------01-----------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------------------------------------------1-------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------1------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------------------1--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +------1---1------------------0-----0--------------------------------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-----------------------------0--------------------------1-----------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------0----------------------0--------------------------------------01-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +-----------------------------------------------------------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~ +--------------------------------------1-------01-----------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0----------1---------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0--1---------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +------1---1------------------0-----0--------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-----------------------------0--------------------------1-----------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------0----------------------0--------------------------------------01--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0--------------------------------------0--10------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +-----------------------------------------------------------------------00------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +----------------------------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1-------------------------------1-------1-------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------1-------1-------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-----------1---------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0---1---------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0------------1--------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0----1--------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +--------------------------------------0----------------------------1----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0--------------------1----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1---------------------1---------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +---0-------------------------0--------------------------------------0---------1 ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1------------------------11-----1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-----------------------0----1--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-----------------------0--100--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +-----------------------------1------------------------------------------------0 ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-----------1---------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1------------1--------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1--------0------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1----------------------------1----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------0-------1----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------1----------0----1--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------1----------0--100--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------------------- 0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +1------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~000~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----0------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------0----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0---------------------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~00~0~0~0~0~0~0~0~0~0~0~0~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------1-------------------------------------------------------------------- ~~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~~0~0~0~0~0~0~0~0~0~0~0~0~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------0------------------------------------------------------------ ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------0----------------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------0---------------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------0--------------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~000~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +----------1------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +-----------------------------0------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~00~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------0----------------------------------------------- ~~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~000~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~0~0~~~~~ +--------------------------------------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~0~~~~~0~~ +-----------------------------0--------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------0-----0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----------------------------------0--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +-----------------------------0----------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +-0------------------------------------1-0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +--------------------------0-----------1-0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +---------------------------0----------1-0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +------------------------------------1-0-10------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +------------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0----11----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1-----0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------00----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +--------------------------------0------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------0--0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +---0--------------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1--------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1-------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1---------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0---------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0-0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------00------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------0--1---1--------00------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------0--1---------0--00------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1-------------------------------0----------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------0----------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +------1---------------------------------------00-0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1----------------00-0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +----------------------------------------1------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +---1-----------------------------0----0-0-------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +---1-----------------------------0------0------0------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +---1-----------------------------01-----0---0--01-----1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-----0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0----------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +----------------------------------------1--------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +------0-------------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +----------0---------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +-----------------------------------1--------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +--------------------------------------0-------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +----------------------------------------1-----------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +----------------------------------------------0------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +-----------------------------------------------------------00------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +--------------------------------------0----------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +------------------------------------------------------------00----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +--------------------------------1---0-------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +----------------------------------------0---------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +------------------------------------1----1--------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +--------------------------------------------0-----------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------------00---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +--------------------------------0------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-0----------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +--------------------------------------0------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +----------------------------------------1----------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +------------------------------------0-------------------------0-1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +--------------------------------0-------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0-0------------------------10-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-0-----------------------11------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +--------------------------------0--------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +----------------------------------------1------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +---------------------------------------------------------------010------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +--------------------------------0---------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------0---0-0-1-----------------------0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +----------------------------------------------------------------111------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +---------------------------------------------------------------0-01------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +--------------------------------------0---------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +----------------------------------------1-------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +------------------------------------0-------------------------0---0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------------------------------01-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +--------------------------------------1-0----------------------10-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +-----------------------------------------------------------------10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +---------------------------------------------------------------0-10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +---------------------------------------------------------------1-00------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +----------------------------------------------------------------100------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +---10--1----------------------------------------1------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--1--11---------------0010--1--------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------0------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------0--1---------1----------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1-----------------------------0----------0----------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------0------1---0----------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------0---------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------0--1------------1-------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--01--1----------------------1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1-01----------------------1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--1---------------1------1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--1----------------1-----1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--1-----------------0----1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--1------------------1---1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--1---------------------01--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------0----------0---0------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +---------------------------------0----------0---------0------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0------------0-------0-------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +----------1---------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +--------------------------------------0----------0------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------00-0------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------0----------------0--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------0---------------0--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +------0----------------------0--------------------------------------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0-----0--------------------------------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0----------------------0-----0--------------------1-----------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----------------------------0-----0--------------------------------01-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------0----------------------0--------------------------------------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +------1----------------------0---------------------------0----------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----------------------------0--------------------------00----------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +----------1------------------------------------------------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +--------------------------------------0----------0---------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------00-0---------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0--------------------------------------0--01------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +------0----------------------0--------------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0-----0--------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0----------------------0-----0--------------------1-----------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----------------------------0-----0--------------------------------01--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------0----------------------0--------------------------------------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +------1----------------------0---------------------------0----------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----------------------------0--------------------------00----------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----------------------------0--------------------------------------0--10------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +-----------------------------0--------------------------------------0--00------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ +----------------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--------------------------------------------------------------------------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1------------------------------------------------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-----------0----------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0---0----------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0------------0---------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0----0---------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------1---------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-----------------------0--0----1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-----------------------0---1---1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-----------------------0----1--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-----------------------0----0--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +-----------------------------0------------------------------------------------0 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1-------------------------------1-------1-------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------1-------1-------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-----------0----------------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1------------0---------------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------0--------0-------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1---------------------1---------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1------------------------11-----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------1----------0--0----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------1----------0---1---0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------1----------0----1--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------1----------0----0--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index c9a069d..3170b16 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,375 +1,370 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sun Jun 01 01:03:24 2014 +#$ DATE Sat Jun 07 23:03:19 2014 #$ MODULE 68030_tk -#$ PINS 59 A_26_ A_25_ A_24_ A_23_ A_31_ A_22_ A_21_ A_20_ A_19_ IPL_2_ A_18_ A_17_ FC_1_ A_16_ RW_000 IPL_1_ IPL_0_ FC_0_ nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ SIZE_1_ IPL_030_2_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ DS_030 UDS_000 LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_ -#$ NODES 25 inst_avec_expreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_7_ SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_5_ SM_AMIGA_2_ inst_RW_000_INT inst_CLK_000_D3 inst_CLK_030_H SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_1_ cpu_est_0_ cpu_est_1_ cpu_est_2_ +#$ PINS 59 A_22_ A_21_ A_20_ A_19_ A_31_ A_18_ A_17_ A_16_ IPL_2_ IPL_1_ FC_1_ IPL_0_ FC_0_ RW_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ SIZE_1_ IPL_030_2_ IPL_030_1_ IPL_030_0_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_ +#$ NODES 24 inst_avec_expreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_1_ SM_AMIGA_6_ SM_AMIGA_0_ SM_AMIGA_7_ inst_RW_000_INT inst_CLK_000_D2 inst_CLK_030_H SM_AMIGA_5_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_ .type fr -.i 80 -.o 158 -.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q inst_avec_expreg.Q VMA.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q inst_CLK_OUT_PRE_50_D.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_DTACK_D0.Q IPL_030_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q IPL_030_1_.Q SM_AMIGA_7_.Q IPL_030_2_.Q AS_000.Q SM_AMIGA_6_.Q SM_AMIGA_0_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q inst_RW_000_INT.Q UDS_000.Q LDS_000.Q DSACK1.Q inst_CLK_000_D3.Q inst_CLK_030_H.Q DS_030.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN RW.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR SIZE_1_.C SIZE_1_.AP IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR DSACK1.C DSACK1.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_0_.C SIZE_0_.AP LDS_000.C LDS_000.AP FPU_CS.C FPU_CS.AP inst_avec_expreg.C inst_avec_expreg.AP BG_000.C BG_000.AP DS_030.C DS_030.AP AS_030.C AS_030.AP AS_000.C AS_000.AP inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.C UDS_000.C UDS_000.AP A0.C A0.AP inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_EXP.C CLK_EXP.AR inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESET.C RESET.AR RW_000 DTACK RW AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D BG_000.D BGACK_030.D FPU_CS.D inst_avec_expreg.D VMA.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D AS_030.D inst_VPA_D.D inst_CLK_OUT_PRE_50_D.D inst_CLK_000_D0.D CLK_EXP.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_DTACK_D0.D IPL_030_0_.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D IPL_030_1_.D SM_AMIGA_7_.D IPL_030_2_.D AS_000.D SM_AMIGA_6_.D SM_AMIGA_0_.D SM_AMIGA_5_.D SM_AMIGA_2_.D inst_RW_000_INT.D UDS_000.D LDS_000.D DSACK1.D inst_CLK_000_D3.D inst_CLK_030_H.D DS_030.D SIZE_0_.D SIZE_1_.D A0.D RESET.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_1_.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D -.p 363 --------------------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ ----1---------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1--------------------------------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------------0-----------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------0---------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ----------------------------------0------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------10-----------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ ----------------------------------------0------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -----------------------------------------1-----------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ --------------------------------------0---------------0-----------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ----------------------------------0-------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------0-0------------------------10-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------10------------------------11------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ----------------------------------0--------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0--------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------1-------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------------------------------010------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ----------------------------------0---------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------0---0-01------------------------0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ------------------------------------------------------------------111------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ -----------------------------------------------------------------0-01------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ----------------------------------------0---------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -----------------------------------------1--------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 --------------------------------------0---------------0-------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ -----------------------------------------------------------------01-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ----------------------------------------10-----------------------10-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -------------------------------------------------------------------10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -----------------------------------------------------------------0-10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ -----------------------------------------------------------------1-00------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ------------------------------------------------------------------100------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ----10--1---------------------------------------1--------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---1--11---------------0010--1---------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------0------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1------------------------------0----0----------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------0----0-1--------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---01--1-----------------------1--------0-------1--------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1-01-----------------------1--------0-------1--------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1---------------1-------1--------0-------1--------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1----------------1------1--------0-------1--------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1-----------------0-----1--------0-------1--------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1------------------1----1--------0-------1--------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1---------------------0-1--------0-------1--------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------0----0-------0--------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------0------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ----1------------------------------0------------------0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------0------1-----------0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---01--1-----------------------1----------------1-----0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1-01-----------------------1----------------1-----0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1---------------1-------1----------------1-----0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1----------------1------1----------------1-----0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1-----------------0-----1----------------1-----0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1------------------1----1----------------1-----0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1--1---------------------0-1----------------1-----0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------0------------0-----0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------0----------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----------------------------------0----0------------------0---------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------0------------------0----0---------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ -----------1----------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ----------------------------------------0--------------0--------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ ---------------------------------------------------00--0--------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ --------------------------------------------------------0------------0--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ---------------------------------------------------------0-----------0--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -------------------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ -------0-----------------------0--------------------------------------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------0-----0--------------------------------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0-----------------------0-----0----------------------1---------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -------------------------------0-----0--------------------------------01-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -------0-----------------------0--------------------------------------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ -------1-----------------------0-----------------------------0--------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -------------------------------0----------------------------00--------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ --------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ -----------1-------------------------------------------------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ----------------------------------------0--------------0-----------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ ---------------------------------------------------00--0-----------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ -------------------------------0--------------------------------------0--01------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -------0-----------------------0--------------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------0-----0--------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0-----------------------0-----0----------------------1---------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -------------------------------0-----0--------------------------------01--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -------0-----------------------0--------------------------------------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ -------1-----------------------0-----------------------------0--------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -------------------------------0----------------------------00--------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -------------------------------0--------------------------------------0--10------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -------------------------------0--------------------------------------0--00------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ------------------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1---------------------------------------------------------------------------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------1------------------------------------------------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------0-------------0------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -----------------------------------------------------0--0------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ------------------------------------------0--------------0-----------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -----------------------------------------------------0---0-----------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ----------------------------------------------------------------------1---------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------1----------1------------------0--0----1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------------------------------------------1----------1------------------0---1---1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------------------------------------------1----------1------------------0----1--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ------------------------------------------1----------1------------------0----0--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ -------------------------------0------------------------------------------------0 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------1--------------------------------1----------1----------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ -------------------------------1--------1----------1----------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ ----------------------------------------0---------------0------------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ----------------------------------------0----------------0-----------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ --------------------------------------------------------0-----0------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ---------------------------------------------------------0----0------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ----------------------------------------1----------1------------------1---------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ ----------------------------------------1----------1---------------------11-----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ ----------------------------------------1---------------------1---------0--0----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ----------------------------------------1---------------------1---------0---1---0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ----------------------------------------1---------------------1---------0----1--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ ----------------------------------------1---------------------1---------0----0--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +.i 79 +.o 155 +.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q inst_avec_expreg.Q VMA.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q inst_CLK_OUT_PRE_50_D.Q inst_CLK_000_D0.Q BG_000.Q inst_CLK_000_D1.Q inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q SM_AMIGA_1_.Q AS_000.Q SM_AMIGA_6_.Q SM_AMIGA_0_.Q SM_AMIGA_7_.Q inst_RW_000_INT.Q UDS_000.Q LDS_000.Q DSACK1.Q IPL_030_0_.Q inst_CLK_000_D2.Q IPL_030_1_.Q inst_CLK_030_H.Q DS_030.Q IPL_030_2_.Q SM_AMIGA_5_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN RW.PIN +.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR cpu_est_0_.C cpu_est_0_.AR IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_0_.C SIZE_0_.AP SIZE_1_.C SIZE_1_.AP LDS_000.C LDS_000.AP FPU_CS.C FPU_CS.AP inst_avec_expreg.C inst_avec_expreg.AP BG_000.C BG_000.AP DS_030.C DS_030.AP AS_030.C AS_030.AP AS_000.C AS_000.AP DSACK1.C DSACK1.AP inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.C UDS_000.C UDS_000.AP A0.C A0.AP inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP CLK_EXP.C CLK_EXP.AR inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESET.C RESET.AR RW_000 DTACK RW AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D FPU_CS.D inst_avec_expreg.D VMA.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D AS_030.D inst_VPA_D.D inst_CLK_OUT_PRE_50_D.D inst_CLK_000_D0.D BG_000.D inst_CLK_000_D1.D inst_DTACK_D0.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D SM_AMIGA_1_.D AS_000.D SM_AMIGA_6_.D SM_AMIGA_0_.D SM_AMIGA_7_.D inst_RW_000_INT.D CLK_EXP.D UDS_000.D LDS_000.D DSACK1.D IPL_030_0_.D inst_CLK_000_D2.D IPL_030_1_.D inst_CLK_030_H.D DS_030.D IPL_030_2_.D SIZE_0_.D SIZE_1_.D A0.D SM_AMIGA_5_.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_2_.D RESET.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D +.p 358 +------------------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +---1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1---------------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0-------------------------------------------------------------------- ~~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +0----------0000000------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------1111--------------------------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~11~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~1~11~~~~~~~~~~ +-----1-----------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0---------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----0------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0-----------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1-------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0-----1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------1----1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------0-1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------0------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------1----------------------------------------------- ~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0-----------------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0--------------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--1--1----------------0010--1----1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0---1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1----0-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1----------------------------1------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0-------------------------0-----0------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~111~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1---1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1-----1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0-----------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------0-------------------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +-1------------------------------------1-0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-----1--------------------------------1-0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------1-----------1-0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +---------------------------1----------1-0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +------------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1-----1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------01----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0----10----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1-1------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-----1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-----1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0------1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +---------------------------------------------10-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1-1---------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1--------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +------1-------------------------------1-------01------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------1-------01------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +---0--------------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1--------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1-------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +---0-------------------------1--------------0--01------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1---1----------0--01------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1----------1---0--01------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1-1----------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1--------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1--------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-------1-0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1-------------------------------0----------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------0----------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +------1---------------------------------------0--1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1----------------0--1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------0-------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +----------------------------------------1------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +---0------------------------------------0-------1-----1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1-----------------------------0------0-------1-----1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-----0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------------0--01-----0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0----------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +----------------------------------------1--------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +----------0---------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------0----------------------------1--------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------------------------------0-------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +----------------------------------------1-----------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------------------------------1--------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +--------------------------------------0--------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +--------------------------------------0------------1-------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +--------------------------------------1---------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +--------------------------------------0---------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +--------------------------------1---0------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +--------------------------------------1----------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +----------------------------------------0--------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +------------------------------------1----1-------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +------------------------------------1-0-10-------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------1-----------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-----------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------0------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +----------------------------------------1----------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +--------------------------------1------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-0----------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +--------------------------------1-------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0------------------------1--1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +--------------------------------------1-0----------------------00-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +--------------------------------------0--------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------1------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------------------------11------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +--------------------------------------1-0----------------------1-0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------------1-0-----------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------------0---------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +----------------------------------------1-------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------------1-0----------------------1--1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----------------------------------------------------------------0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------0---0-0-1--------------------1--0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------1-0-----------------------011------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-----------------------------------------------------------------01------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------------1-0----------------------1-01------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +------------------------------------0------------------------1----0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +--------------------------------------1-0----------------------1-10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +--------------------------------------1------1-----------------0110------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-0-----------------------000------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-------------------------------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0----------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------0-----1----------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------0----------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +----------------------------------------------0--------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1-----------------1-------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------------1---1------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------0-------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +---------------------------------------1---------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~1~11~~~~~~~~~~ +--------------------------------------1-------01--------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0----------1------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0--1------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1---------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +------1--------------------------------------------------1-----------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------------------------------------------------01-----------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------------------------------------------1-------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------1------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------------------1--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +------1---1------------------0-----0--------------------------------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-----------------------------0--------------------------1-----------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------0----------------------0--------------------------------------01-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +-----------------------------------------------------------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~ +--------------------------------------1-------01-----------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0----------1---------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0--1---------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +------1---1------------------0-----0--------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-----------------------------0--------------------------1-----------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +------0----------------------0--------------------------------------01--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0--------------------------------------0--10------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +-----------------------------------------------------------------------00------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +----------------------------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1-------------------------------1-------1-------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------1-------1-------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-----------1---------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0---1---------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0------------1--------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0----1--------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +--------------------------------------0----------------------------1----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0--------------------1----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1---------------------1---------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +---0-------------------------0--------------------------------------0---------1 ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1------------------------11-----1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-----------------------0----1--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-----------------------0--100--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +-----------------------------1------------------------------------------------0 ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-----------1---------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1------------1--------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1--------0------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1----------------------------1----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------0-------1----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------1----------0----1--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------1----------0--100--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------------------- 0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +1------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~000~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----0------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------0----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0---------------------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~00~0~0~0~0~0~0~0~0~0~0~0~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------1-------------------------------------------------------------------- ~~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~0~~0~0~0~0~0~0~0~0~0~0~0~0~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------0------------------------------------------------------------ ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------0----------------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------0---------------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------0--------------------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~000~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +----------1------------------1------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +-----------------------------0------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~00~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------0----------------------------------------------- ~~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------1------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~000~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~0~0~~~~~ +--------------------------------------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~0~~~~~0~~ +-----------------------------0--------0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------0-----0---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----------------------------------0--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +-----------------------------0----------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +-0------------------------------------1-0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +--------------------------0-----------1-0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +---------------------------0----------1-0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +------------------------------------1-0-10------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +------------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0----11----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1-----0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------00----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +--------------------------------0------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------0--0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +---0--------------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1--------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1-------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1---------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0---------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0-0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------00------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------0--1---1--------00------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------0--1---------0--00------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1-------------------------------0----------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------0----------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +------1---------------------------------------00-0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1----------------00-0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +----------------------------------------1------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +---1-----------------------------0----0-0-------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +---1-----------------------------0------0------0------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +---1-----------------------------01-----0---0--01-----1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-----0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0----------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +----------------------------------------1--------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +------0-------------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +----------0---------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +-----------------------------------1--------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +--------------------------------------0-------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +----------------------------------------1-----------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +----------------------------------------------0------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +-----------------------------------------------------------00------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +--------------------------------------0----------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +------------------------------------------------------------00----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +--------------------------------1---0-------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +----------------------------------------0---------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +------------------------------------1----1--------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +--------------------------------------------0-----------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------------00---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +--------------------------------0------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-0----------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +--------------------------------------0------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +----------------------------------------1----------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +------------------------------------0-------------------------0-1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +--------------------------------0-------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0-0------------------------10-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-0-----------------------11------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +--------------------------------0--------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +----------------------------------------1------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +---------------------------------------------------------------010------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +--------------------------------0---------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------0---0-0-1-----------------------0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +----------------------------------------------------------------111------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +---------------------------------------------------------------0-01------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +--------------------------------------0---------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +----------------------------------------1-------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +------------------------------------0-------------------------0---0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------------------------------01-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +--------------------------------------1-0----------------------10-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +-----------------------------------------------------------------10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +---------------------------------------------------------------0-10------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +---------------------------------------------------------------1-00------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +----------------------------------------------------------------100------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +---10--1----------------------------------------1------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--1--11---------------0010--1--------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------0------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------0--1---------1----------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1-----------------------------0----------0----------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------0------1---0----------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------0---------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------0--1------------1-------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--01--1----------------------1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1-01----------------------1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--1---------------1------1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--1----------------1-----1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--1-----------------0----1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--1------------------1---1--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--1---------------------01--------------0---1------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------0----------0---0------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------0--------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +---------------------------------0----------0---------0------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0------------0-------0-------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +----------1---------------------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +--------------------------------------0----------0------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------00-0------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------0----------------0--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------0---------------0--1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +------0----------------------0--------------------------------------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0-----0--------------------------------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0----------------------0-----0--------------------1-----------0--0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----------------------------0-----0--------------------------------01-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------0----------------------0--------------------------------------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +------1----------------------0---------------------------0----------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----------------------------0--------------------------00----------00-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------------------------------------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +----------1------------------------------------------------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +--------------------------------------0----------0---------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------00-0---------------------11------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0--------------------------------------0--01------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +------0----------------------0--------------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0-----0--------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0----------------------0-----0--------------------1-----------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----------------------------0-----0--------------------------------01--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +------0----------------------0--------------------------------------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +------1----------------------0---------------------------0----------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----------------------------0--------------------------00----------00--0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-----------------------------0--------------------------------------0--10------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +-----------------------------0--------------------------------------0--00------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ +----------------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--------------------------------------------------------------------------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1------------------------------------------------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-----------0----------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0---0----------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0------------0---------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +----------------------------------------------0----0---------------0----------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------1---------1 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-----------------------0--0----1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-----------------------0---1---1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-----------------------0----1--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-----------------------0----0--1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +-----------------------------0------------------------------------------------0 ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1-------------------------------1-------1-------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------1--------1-------1-------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-----------0----------------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1------------0---------------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------0--------0-------0----------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1---------------------1---------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1------------------------11-----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------1----------0--0----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------1----------0---1---0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------1----------0----1--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------------------1----------0----0--0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index f7e3a05..e08dda8 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,200 +1,202 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sun Jun 01 01:03:24 2014 +#$ DATE Sat Jun 07 23:03:19 2014 #$ MODULE BUS68030 -#$ PINS 59 A_26_ A_25_ A_24_ A_23_ A_31_ A_22_ A_21_ A_20_ A_19_ IPL_2_ A_18_ - A_17_ FC_1_ A_16_ RW_000 IPL_1_ IPL_0_ FC_0_ nEXP_SPACE BERR BG_030 BGACK_000 - CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW - AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ - A_27_ SIZE_1_ IPL_030_2_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ DS_030 UDS_000 - LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_ -#$ NODES 24 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D - inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 - inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_7_ SM_AMIGA_6_ - SM_AMIGA_0_ SM_AMIGA_5_ SM_AMIGA_2_ inst_RW_000_INT inst_CLK_000_D3 - inst_CLK_030_H SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_1_ cpu_est_0_ cpu_est_1_ - cpu_est_2_ +#$ PINS 59 A_22_ A_21_ A_20_ A_19_ A_31_ A_18_ A_17_ A_16_ IPL_2_ IPL_1_ FC_1_ + IPL_0_ FC_0_ RW_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI + CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR + AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ + SIZE_1_ IPL_030_2_ IPL_030_1_ IPL_030_0_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 + BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_ +#$ NODES 24 inst_avec_expreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D + inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_DTACK_D0 + inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_1_ SM_AMIGA_6_ SM_AMIGA_0_ + SM_AMIGA_7_ inst_RW_000_INT inst_CLK_000_D2 inst_CLK_030_H SM_AMIGA_5_ + SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_ .type f -.i 80 -.o 160 +.i 79 +.o 158 .ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ - A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q VMA.Q - inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q - inst_CLK_OUT_PRE_50_D.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q - inst_DTACK_D0.Q IPL_030_0_.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q - IPL_030_1_.Q SM_AMIGA_7_.Q IPL_030_2_.Q AS_000.Q SM_AMIGA_6_.Q SM_AMIGA_0_.Q - SM_AMIGA_5_.Q SM_AMIGA_2_.Q inst_RW_000_INT.Q UDS_000.Q LDS_000.Q DSACK1.Q - inst_CLK_000_D3.Q inst_CLK_030_H.Q DS_030.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q - SM_AMIGA_1_.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN - RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN - DSACK1.PIN DTACK.PIN RW.PIN AVEC_EXP + A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q inst_avec_expreg.Q + VMA.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q + inst_CLK_OUT_PRE_50_D.Q inst_CLK_000_D0.Q BG_000.Q inst_CLK_000_D1.Q + inst_DTACK_D0.Q inst_CLK_OUT_PRE_50.Q inst_CLK_OUT_PRE_25.Q SM_AMIGA_1_.Q + AS_000.Q SM_AMIGA_6_.Q SM_AMIGA_0_.Q SM_AMIGA_7_.Q inst_RW_000_INT.Q UDS_000.Q + LDS_000.Q DSACK1.Q IPL_030_0_.Q inst_CLK_000_D2.Q IPL_030_1_.Q inst_CLK_030_H.Q + DS_030.Q IPL_030_2_.Q SM_AMIGA_5_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q + cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN RW_000.PIN + DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN + DTACK.PIN RW.PIN .ob RW_000 RW_000.OE BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C CLK_DIV_OUT.AR - DTACK DTACK.OE AVEC AVEC_EXP.D% AVEC_EXP.C AVEC_EXP.AP RW RW.OE AMIGA_BUS_ENABLE - AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE SIZE_1_.D% SIZE_1_.C - SIZE_1_.AP SIZE_1_.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP AS_030.D AS_030.C - AS_030.AP AS_030.OE IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP AS_000.D% AS_000.C - AS_000.AP AS_000.OE IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP DS_030.D DS_030.C - DS_030.AP DS_030.OE UDS_000.D% UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D% - LDS_000.C LDS_000.AP LDS_000.OE A0.D A0.C A0.AP A0.OE BG_000.D% BG_000.C - BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D CLK_EXP.C CLK_EXP.AR - FPU_CS.D% FPU_CS.C FPU_CS.AP DSACK1.D% DSACK1.C DSACK1.AP DSACK1.OE E.D.X1 - E.D.X2 E.C E.AR VMA.D.X1 VMA.D.X2 VMA.C VMA.AP RESET.D RESET.C RESET.AR - SIZE_0_.D% SIZE_0_.C SIZE_0_.AP SIZE_0_.OE inst_AS_030_000_SYNC.D - inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_BGACK_030_INT_D.D - inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_VPA_D.D inst_VPA_D.C - inst_VPA_D.AP inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C - inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP - inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_CLK_000_D2.D - inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_DTACK_D0.D inst_DTACK_D0.C - inst_DTACK_D0.AP inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C - inst_CLK_OUT_PRE_50.AR inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C - inst_CLK_OUT_PRE_25.AR SM_AMIGA_7_.D% SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D - SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR - SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C - SM_AMIGA_2_.AR inst_RW_000_INT.D% inst_RW_000_INT.C inst_RW_000_INT.AP - inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_030_H.D - inst_CLK_030_H.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D% - SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR - cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.T cpu_est_1_.C cpu_est_1_.AR - cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_2_.AR -.phase 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 -.p 138 ------------------------------------------------------1-------------------------- 1000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -------------------------------1------------------------------------------------- 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00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +--------------------------------------1-0----------------------1010------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +-----------------------------------------------------------------1------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index 6228616..5503d92 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,200 +1,202 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sun Jun 01 01:03:24 2014 +#$ DATE Sat Jun 07 23:03:19 2014 #$ MODULE BUS68030 -#$ PINS 59 A_26_ A_25_ A_24_ A_23_ A_31_ A_22_ A_21_ A_20_ A_19_ IPL_2_ A_18_ - A_17_ FC_1_ A_16_ RW_000 IPL_1_ IPL_0_ FC_0_ nEXP_SPACE BERR BG_030 BGACK_000 - CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW - AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ - A_27_ SIZE_1_ IPL_030_2_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ DS_030 UDS_000 - LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_ -#$ NODES 24 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D - inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 - inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_7_ SM_AMIGA_6_ - SM_AMIGA_0_ SM_AMIGA_5_ SM_AMIGA_2_ inst_RW_000_INT inst_CLK_000_D3 - inst_CLK_030_H SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_1_ cpu_est_0_ cpu_est_1_ - cpu_est_2_ +#$ PINS 59 A_22_ A_21_ A_20_ A_19_ A_31_ A_18_ A_17_ A_16_ IPL_2_ IPL_1_ FC_1_ + IPL_0_ FC_0_ RW_000 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI + CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR + AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ + SIZE_1_ IPL_030_2_ IPL_030_1_ IPL_030_0_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 + BG_000 BGACK_030 CLK_EXP FPU_CS DSACK1 E VMA RESET SIZE_0_ +#$ NODES 24 inst_avec_expreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D + inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_DTACK_D0 + inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_1_ SM_AMIGA_6_ SM_AMIGA_0_ + SM_AMIGA_7_ inst_RW_000_INT inst_CLK_000_D2 inst_CLK_030_H SM_AMIGA_5_ + SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_ .type f -.i 80 -.o 160 +.i 79 +.o 158 .ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ - A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q VMA.Q - inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q AS_030.Q inst_VPA_D.Q - inst_CLK_OUT_PRE_50_D.Q inst_CLK_000_D0.Q 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00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000 +--------------------------------------1-0-----------------------011------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000 +--------------------------------------1-0----------------------1-01------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001001000 +--------------------------------------1-0----------------------1-10------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000 +--------------------------------------1-0----------------------000------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +--------------------------------------1-0----------------------1010------------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +-----------------------------------------------------------------1------------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index 24cfb13..3e99f94 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 6/1/14; -TIME = 01:03:29; +DATE = 6/7/14; +TIME = 23:03:24; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -139,15 +139,14 @@ LDS_000 = BIDIR,31,3,-; UDS_000 = BIDIR,32,3,-; AS_030 = BIDIR,82,7,-; RW = OUTPUT,71,6,-; +RW_000 = OUTPUT,80,7,-; DS_030 = BIDIR,98,0,-; DSACK1 = BIDIR,81,7,-; SIZE_1_ = OUTPUT,79,7,-; -RW_000 = OUTPUT,80,7,-; SIZE_0_ = OUTPUT,70,6,-; A0 = OUTPUT,69,6,-; DTACK = OUTPUT,30,3,-; E = OUTPUT,66,6,-; -AVEC_EXP = OUTPUT,22,2,-; IPL_030_2_ = OUTPUT,9,1,-; IPL_030_0_ = OUTPUT,8,1,-; IPL_030_1_ = OUTPUT,7,1,-; @@ -161,46 +160,46 @@ CLK_DIV_OUT = OUTPUT,65,6,-; CIIN = OUTPUT,47,4,-; BERR = OUTPUT,41,4,-; AMIGA_BUS_ENABLE = OUTPUT,34,3,-; +AVEC_EXP = OUTPUT,22,2,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-; CLK_EXP = OUTPUT,10,1,-; RESET = OUTPUT,3,1,-; RN_BGACK_030 = NODE,-1,7,-; -inst_CLK_000_D0 = NODE,*,3,-; RN_AS_030 = NODE,-1,7,-; -cpu_est_0_ = NODE,*,2,-; inst_CLK_000_D1 = NODE,*,3,-; -inst_RW_000_INT = NODE,*,0,-; -cpu_est_1_ = NODE,*,1,-; -SM_AMIGA_7_ = NODE,*,1,-; +inst_CLK_000_D0 = NODE,*,7,-; +inst_avec_expreg = NODE,*,6,-; +cpu_est_1_ = NODE,*,3,-; +SM_AMIGA_7_ = NODE,*,7,-; RN_E = NODE,-1,6,-; -cpu_est_2_ = NODE,*,6,-; -SM_AMIGA_2_ = NODE,*,6,-; -inst_CLK_000_D2 = NODE,*,7,-; -inst_AS_030_000_SYNC = NODE,*,2,-; -inst_CLK_030_H = NODE,*,7,-; -RN_AVEC_EXP = NODE,-1,2,-; +SM_AMIGA_1_ = NODE,*,1,-; +inst_RW_000_INT = NODE,*,6,-; +inst_AS_030_000_SYNC = NODE,*,7,-; +inst_CLK_030_H = NODE,*,1,-; +cpu_est_2_ = NODE,*,3,-; +cpu_est_0_ = NODE,*,3,-; +SM_AMIGA_2_ = NODE,*,0,-; inst_CLK_OUT_PRE_25 = NODE,*,1,-; RN_VMA = NODE,-1,3,-; RN_FPU_CS = NODE,-1,7,-; -SM_AMIGA_1_ = NODE,*,7,-; -SM_AMIGA_4_ = NODE,*,3,-; -SM_AMIGA_5_ = NODE,*,1,-; -SM_AMIGA_0_ = NODE,*,0,-; -SM_AMIGA_6_ = NODE,*,1,-; -inst_CLK_000_D3 = NODE,*,2,-; +SM_AMIGA_5_ = NODE,*,3,-; +SM_AMIGA_0_ = NODE,*,7,-; +SM_AMIGA_6_ = NODE,*,6,-; +inst_CLK_000_D2 = NODE,*,7,-; inst_CLK_OUT_PRE_50 = NODE,*,7,-; -inst_VPA_D = NODE,*,7,-; +inst_VPA_D = NODE,*,0,-; RN_LDS_000 = NODE,-1,3,-; RN_UDS_000 = NODE,-1,3,-; RN_DS_030 = NODE,-1,0,-; -SM_AMIGA_3_ = NODE,*,6,-; +SM_AMIGA_3_ = NODE,*,0,-; RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; RN_IPL_030_2_ = NODE,-1,1,-; RN_DSACK1 = NODE,-1,7,-; RN_BG_000 = NODE,-1,3,-; RN_AS_000 = NODE,-1,3,-; -inst_DTACK_D0 = NODE,*,7,-; +SM_AMIGA_4_ = NODE,*,0,-; +inst_DTACK_D0 = NODE,*,1,-; inst_CLK_OUT_PRE_50_D = NODE,*,7,-; -inst_BGACK_030_INT_D = NODE,*,3,-; +inst_BGACK_030_INT_D = NODE,*,1,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index f4e3003..f793977 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 6/1/14; -TIME = 01:03:29; +DATE = 6/7/14; +TIME = 23:03:24; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -134,24 +134,20 @@ layer = OFF; [LOCATION ASSIGNMENT] Layer = OFF; -A_26_ = INPUT,17, C,-; -A_25_ = INPUT,18, C,-; -A_24_ = INPUT,19, C,-; -A_23_ = INPUT,84, H,-; -A_31_ = INPUT,4, B,-; A_22_ = INPUT,85, H,-; A_21_ = INPUT,94, A,-; A_20_ = INPUT,93, A,-; A_19_ = INPUT,97, A,-; -IPL_2_ = INPUT,68, G,-; +A_31_ = INPUT,4, B,-; A_18_ = INPUT,95, A,-; A_17_ = INPUT,59, F,-; -FC_1_ = INPUT,58, F,-; A_16_ = INPUT,96, A,-; -RW_000 = BIDIR,80, H,-; +IPL_2_ = INPUT,68, G,-; IPL_1_ = INPUT,56, F,-; +FC_1_ = INPUT,58, F,-; IPL_0_ = INPUT,67, G,-; FC_0_ = INPUT,57, F,-; +RW_000 = BIDIR,80, H,-; nEXP_SPACE = INPUT,14,-,-; BERR = OUTPUT,41, E,-; BG_030 = INPUT,21, C,-; @@ -174,12 +170,16 @@ A_30_ = INPUT,5, B,-; A_29_ = INPUT,6, B,-; A_28_ = INPUT,15, C,-; A_27_ = INPUT,16, C,-; +A_26_ = INPUT,17, C,-; +A_25_ = INPUT,18, C,-; +A_24_ = INPUT,19, C,-; +A_23_ = INPUT,84, H,-; SIZE_1_ = BIDIR,79, H,-; IPL_030_2_ = OUTPUT,9, B,-; -AS_030 = BIDIR,82, H,-; IPL_030_1_ = OUTPUT,7, B,-; -AS_000 = BIDIR,33, D,-; IPL_030_0_ = OUTPUT,8, B,-; +AS_030 = BIDIR,82, H,-; +AS_000 = BIDIR,33, D,-; DS_030 = BIDIR,98, A,-; UDS_000 = BIDIR,32, D,-; LDS_000 = BIDIR,31, D,-; @@ -193,27 +193,27 @@ E = OUTPUT,66, G,-; VMA = OUTPUT,35, D,-; RESET = OUTPUT,3, B,-; SIZE_0_ = BIDIR,70, G,-; -inst_AS_030_000_SYNC = NODE,3, C,-; -inst_BGACK_030_INT_D = NODE,10, D,-; -inst_VPA_D = NODE,10, H,-; +inst_avec_expreg = NODE,4, G,-; +inst_AS_030_000_SYNC = NODE,7, H,-; +inst_BGACK_030_INT_D = NODE,9, B,-; +inst_VPA_D = NODE,3, A,-; inst_CLK_OUT_PRE_50_D = NODE,12, H,-; -inst_CLK_000_D0 = NODE,5, D,-; -inst_CLK_000_D1 = NODE,7, D,-; -inst_CLK_000_D2 = NODE,3, H,-; -inst_DTACK_D0 = NODE,11, H,-; -inst_CLK_OUT_PRE_50 = NODE,9, H,-; +inst_CLK_000_D0 = NODE,3, H,-; +inst_CLK_000_D1 = NODE,5, D,-; +inst_DTACK_D0 = NODE,8, B,-; +inst_CLK_OUT_PRE_50 = NODE,11, H,-; inst_CLK_OUT_PRE_25 = NODE,7, B,-; -SM_AMIGA_7_ = NODE,5, B,-; -SM_AMIGA_6_ = NODE,9, B,-; -SM_AMIGA_0_ = NODE,1, A,-; -SM_AMIGA_5_ = NODE,8, B,-; -SM_AMIGA_2_ = NODE,5, G,-; -inst_RW_000_INT = NODE,3, A,-; -inst_CLK_000_D3 = NODE,4, C,-; -inst_CLK_030_H = NODE,5, H,-; -SM_AMIGA_4_ = NODE,9, D,-; -SM_AMIGA_3_ = NODE,6, G,-; -SM_AMIGA_1_ = NODE,7, H,-; -cpu_est_0_ = NODE,2, C,-; -cpu_est_1_ = NODE,3, B,-; -cpu_est_2_ = NODE,4, G,-; +SM_AMIGA_1_ = NODE,3, B,-; +SM_AMIGA_6_ = NODE,6, G,-; +SM_AMIGA_0_ = NODE,9, H,-; +SM_AMIGA_7_ = NODE,5, H,-; +inst_RW_000_INT = NODE,5, G,-; +inst_CLK_000_D2 = NODE,10, H,-; +inst_CLK_030_H = NODE,5, B,-; +SM_AMIGA_5_ = NODE,11, D,-; +SM_AMIGA_4_ = NODE,5, A,-; +SM_AMIGA_3_ = NODE,4, A,-; +SM_AMIGA_2_ = NODE,1, A,-; +cpu_est_0_ = NODE,10, D,-; +cpu_est_1_ = NODE,7, D,-; +cpu_est_2_ = NODE,9, D,-; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index 9eaf7f8..a267e73 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 1.7.00.05.28.13 -Design '68030_tk' created Sun Jun 01 01:03:24 2014 +Design '68030_tk' created Sat Jun 07 23:03:19 2014 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index dc88bac..4a32b0f 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,155 +1,153 @@ -#$ DATE Sun Jun 01 01:03:24 2014 +#$ DATE Sat Jun 07 23:03:19 2014 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 59 A_26_ A_25_ SIZE_1_ A_24_ A_23_ A_31_ A_22_ A_21_ IPL_030_2_ A_20_ A_19_ IPL_2_ A_18_ A_17_ FC_1_ A_16_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ RW_000 IPL_1_ DS_030 IPL_0_ UDS_000 FC_0_ LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ -#$ NODES 410 BG_030_c BG_000DFFSHreg inst_BGACK_030_INTreg BGACK_000_c inst_FPU_CS_INTreg inst_avec_expreg CLK_030_c inst_VMA_INTreg inst_AS_030_000_SYNC CLK_000_c \ -# inst_BGACK_030_INT_D inst_AS_000_DMA CLK_OSZI_c inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 CLK_OUT_INTreg inst_CLK_000_D1 inst_CLK_000_D2 inst_DTACK_D0 \ -# IPL_030DFFSH_0_reg inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 IPL_030DFFSH_1_reg SM_AMIGA_7_ vcc_n_n IPL_030DFFSH_2_reg gnd_n_n state_machine_un10_clk_000_d0_n ipl_c_0__n \ -# inst_AS_000_INT SM_AMIGA_6_ ipl_c_1__n SM_AMIGA_0_ SM_AMIGA_5_ ipl_c_2__n SM_AMIGA_2_ inst_RW_000_INT DSACK1_c inst_UDS_000_INT \ -# inst_LDS_000_INT inst_DSACK1_INT state_machine_un3_clk_out_pre_50_n inst_CLK_000_D3 inst_CLK_030_H state_machine_un12_clk_000_d0_n inst_DS_000_DMA SIZE_DMA_0_ SIZE_DMA_1_ RST_c \ -# inst_A0_DMA AMIGA_BUS_ENABLE_INT_2_sqmuxa RESETDFFRHreg SM_AMIGA_4_ SM_AMIGA_3_ RW_c SM_AMIGA_1_ un1_DSACK1_INT_0_sqmuxa_3 fc_c_0__n fc_c_1__n \ -# state_machine_un10_bg_030_n state_machine_lds_000_int_7_n state_machine_uds_000_int_7_n AMIGA_BUS_DATA_DIR_c state_machine_un6_bgack_000_0_n N_194_0 N_119_i N_120_i N_197_0 state_machine_ds_000_dma_3_0_n \ -# N_171_i state_machine_size_dma_4_0_1__n N_130_i N_131_i CLK_OUT_PRE_25_0 N_132_i N_133_i N_134_i sm_amiga_ns_0_5__n N_135_i \ -# N_139_i cpu_est_0_ N_140_i cpu_est_1_ AMIGA_BUS_DATA_DIR_c_0 cpu_est_2_ N_141_i cpu_est_3_reg N_52_i N_143_i \ -# N_142_i state_machine_rw_000_int_7_iv_i_n cpu_est_ns_1__n N_62_0 cpu_est_ns_2__n N_161_i N_193 N_155_i N_196 N_63_0 \ -# N_28 N_66_i N_30 N_76_i N_55 CLK_000_D1_i N_62 N_77_i N_63 N_79_0 \ -# N_66 N_199_0 N_67 sm_amiga_i_2__n N_69 N_201_0 N_70 N_203_0 N_71 cpu_est_ns_0_1__n \ -# N_75 N_167_i N_76 N_170_i N_77 N_136_i N_79 N_137_i N_90 N_202_0 \ -# N_200 N_200_0 N_202 N_169_i N_204 N_198_0 N_114 N_168_i N_115 un1_DSACK1_INT_0_sqmuxa_3_0 \ -# N_116 N_90_i N_117 AS_030_c_i N_118 N_75_i N_120 N_71_i N_121 N_69_i \ -# N_122 N_67_i N_124 N_150_i N_125 N_151_i N_128 N_129 N_145_i N_132 \ -# N_146_i N_136 N_147_i N_137 cpu_est_ns_0_2__n N_138 N_144_i N_140 N_55_0 N_142 \ -# N_138_i N_144 N_172_i N_145 N_149_i N_146 N_129_i N_147 N_148 N_128_i \ -# N_150 sm_amiga_ns_0_0__n N_151 N_70_i N_155 N_124_i N_166 state_machine_lds_000_int_7_0_n N_167 state_machine_uds_000_int_7_0_n \ -# N_168 N_122_i N_169 N_30_0 N_170 N_121_i N_172 N_28_0 N_220 N_117_i \ -# N_230 N_118_i N_133 N_196_0 N_143 N_116_i N_143_2 N_195_i N_203 BG_030_c_i \ -# N_201 N_115_i N_199 state_machine_un10_bg_030_0_n N_161 N_193_0 N_141 N_204_i N_139 state_machine_un10_clk_000_d0_i_n \ -# N_135 state_machine_un12_clk_000_d0_0_n N_134 N_69_i_1 N_131 N_76_i_1 N_130 N_76_i_2 N_171 N_76_i_3 \ -# state_machine_ds_000_dma_3_n N_76_i_4 N_197 N_76_i_5 N_119 N_220_1 N_194 N_220_2 state_machine_un6_bgack_000_n N_230_1 \ -# N_143_2_i N_230_2 a_i_18__n N_230_3 a_i_16__n N_230_4 a_i_19__n N_230_5 sm_amiga_i_4__n N_230_6 \ -# sm_amiga_i_5__n cpu_est_ns_0_1_1__n sm_amiga_i_3__n cpu_est_ns_0_2_1__n CLK_000_D0_i N_122_1 sm_amiga_i_0__n N_122_2 sm_amiga_i_1__n N_122_3 \ -# RW_i N_115_1 CLK_030_H_i N_115_2 CLK_030_i state_machine_un10_clk_000_d0_1_n DTACK_D0_i state_machine_un10_clk_000_d0_2_n BGACK_030_INT_i N_133_1 \ -# AS_000_i N_133_2 UDS_000_i N_143_1 LDS_000_i cpu_est_ns_0_1_2__n RW_000_i N_55_0_1 sm_amiga_i_6__n state_machine_lds_000_int_7_0_1_n \ -# cpu_est_i_3__n state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_196_0_1 CLK_000_D2_i N_155_1 cpu_est_i_1__n N_148_1 cpu_est_i_0__n N_142_1 \ -# VMA_INT_i N_140_1 VPA_D_i N_132_1 AS_000_DMA_i N_124_1 nEXP_SPACE_i state_machine_a0_dma_2_1_n cpu_est_i_2__n N_120_1 \ -# A0_i N_118_1 size_i_1__n N_117_1 DS_030_i N_116_1 AS_030_000_SYNC_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 a_i_30__n N_204_1 \ -# a_i_31__n bgack_030_int_0_un3_n a_i_28__n bgack_030_int_0_un1_n a_i_29__n bgack_030_int_0_un0_n a_i_26__n as_000_dma_0_un3_n a_i_27__n as_000_dma_0_un1_n \ -# a_i_24__n as_000_dma_0_un0_n a_i_25__n ds_000_dma_0_un3_n RST_i ds_000_dma_0_un1_n ds_000_dma_0_un0_n clk_030_h_0_un3_n N_114_i clk_030_h_0_un1_n \ -# FPU_CS_INT_i clk_030_h_0_un0_n CLK_OUT_PRE_50_D_i rw_000_int_0_un3_n AS_030_c rw_000_int_0_un1_n rw_000_int_0_un0_n AS_000_c state_machine_uds_000_int_7_0_m3_un3_n state_machine_uds_000_int_7_0_m3_un1_n \ -# RW_000_c state_machine_uds_000_int_7_0_m3_un0_n ipl_030_0_0__un3_n DS_030_c ipl_030_0_0__un1_n ipl_030_0_0__un0_n UDS_000_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n LDS_000_c \ -# ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n cpu_estse_0_un3_n cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n \ -# cpu_estse_1_un3_n a_c_17__n cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n cpu_estse_2_un3_n cpu_estse_2_un1_n a_c_19__n cpu_estse_2_un0_n as_030_000_sync_0_un3_n \ -# a_c_20__n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n a_c_21__n uds_000_int_0_un3_n uds_000_int_0_un1_n a_c_22__n uds_000_int_0_un0_n lds_000_int_0_un3_n a_c_23__n \ -# lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_24__n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n a_c_25__n fpu_cs_int_0_un0_n avec_exp_0_un3_n a_c_26__n avec_exp_0_un1_n \ -# avec_exp_0_un0_n a_c_27__n bg_000_0_un3_n bg_000_0_un1_n a_c_28__n bg_000_0_un0_n as_000_int_0_un3_n a_c_29__n as_000_int_0_un1_n as_000_int_0_un0_n \ -# a_c_30__n dsack1_int_0_un3_n dsack1_int_0_un1_n a_c_31__n dsack1_int_0_un0_n vma_int_0_un3_n A0_c vma_int_0_un1_n vma_int_0_un0_n nEXP_SPACE_c \ -# +#$ PINS 59 A_22_ A_21_ SIZE_1_ A_20_ A_19_ A_31_ A_18_ A_17_ IPL_030_2_ A_16_ IPL_030_1_ IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ +#$ NODES 407 a_c_28__n a_c_29__n a_c_30__n inst_BGACK_030_INTreg a_c_31__n inst_FPU_CS_INTreg inst_avec_expreg A0_c inst_VMA_INTreg inst_AS_030_000_SYNC \ +# nEXP_SPACE_c inst_BGACK_030_INT_D inst_AS_000_DMA inst_VPA_D BG_030_c inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 BG_000DFFSHreg inst_CLK_000_D1 inst_DTACK_D0 \ +# inst_CLK_OUT_PRE_50 BGACK_000_c inst_CLK_OUT_PRE_25 SM_AMIGA_1_ CLK_030_c vcc_n_n gnd_n_n CLK_000_c inst_AS_000_INT SM_AMIGA_6_ \ +# CLK_OSZI_c SM_AMIGA_0_ SM_AMIGA_7_ inst_RW_000_INT CLK_OUT_INTreg inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT IPL_030DFFSH_0_reg state_machine_un3_clk_out_pre_50_n \ +# inst_CLK_000_D2 IPL_030DFFSH_1_reg inst_CLK_030_H inst_DS_000_DMA IPL_030DFFSH_2_reg SIZE_DMA_0_ SIZE_DMA_1_ ipl_c_0__n inst_A0_DMA SM_AMIGA_5_ \ +# ipl_c_1__n SM_AMIGA_4_ SM_AMIGA_3_ ipl_c_2__n SM_AMIGA_2_ DSACK1_c RST_c RESETDFFRHreg RW_c fc_c_0__n \ +# CLK_OUT_PRE_25_0 fc_c_1__n AMIGA_BUS_DATA_DIR_c cpu_est_0_ state_machine_un3_clk_000_d1_i_n cpu_est_1_ state_machine_un6_bgack_000_0_n cpu_est_2_ cpu_est_ns_0_1__n cpu_est_3_reg \ +# N_159_i cpu_estse N_158_i N_149_i N_150_i N_153_i AS_000_DMA_0_sqmuxa N_152_i state_machine_un8_bgack_030_int_n N_160_i \ +# N_92 N_154_i state_machine_un49_clk_000_d0_n state_machine_un10_clk_000_d0_2_i_n N_210 N_156_i N_220 N_157_i CLK_030_H_1_sqmuxa cpu_est_ns_0_2__n \ +# AS_000_DMA_1_sqmuxa state_machine_un10_clk_000_d0_i_n DS_000_DMA_1_sqmuxa state_machine_un12_clk_000_d0_0_n state_machine_un24_bgack_030_int_n FPU_CS_INT_1_sqmuxa_i state_machine_clk_030_h_2_n un1_as_030_000_sync8_1_0 state_machine_clk_030_h_2_f1_n AS_030_000_SYNC_0_sqmuxa_2_i \ +# state_machine_ds_000_dma_3_n un1_as_030_000_sync8_0 N_87 un1_SM_AMIGA_12_0 N_93 state_machine_un3_clk_030_i_n N_94 state_machine_un57_clk_000_d0_i_n N_88 state_machine_un51_clk_000_d0_i_n \ +# N_90 state_machine_un53_clk_000_d0_0_n N_164_1 state_machine_un3_bgack_030_int_d_i_n state_machine_un10_bgack_030_int_n un1_bgack_030_int_d_0 UDS_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i UDS_000_INT_0_sqmuxa AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i \ +# state_machine_un25_clk_000_d0_n N_86_0 N_164 N_101_i RW_li_m N_85_i N_181 N_84_0 RW_000_i_m N_97_i \ +# N_163 un1_SM_AMIGA_8 N_96_i N_100 N_95_i N_91 sm_amiga_ns_0_5__n state_machine_un31_bgack_030_int_n N_88_i state_machine_lds_000_int_7_n \ +# N_89_i state_machine_uds_000_int_7_n sm_amiga_ns_0_0__n RW_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_2_sqmuxa_i un1_AS_030_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i N_59 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 un1_bgack_030_int_d \ +# BG_030_c_i un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un8_bg_030_i_n state_machine_un10_bg_030_n state_machine_un10_bg_030_0_n state_machine_un3_bgack_030_int_d_n state_machine_un5_bgack_030_int_d_i_n AMIGA_BUS_ENABLE_INT_3_sqmuxa N_59_0 N_86 \ +# state_machine_un10_bgack_030_int_0_n AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 N_181_i N_84 A0_c_i AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 state_machine_uds_000_int_7_0_n state_machine_un8_bg_030_n state_machine_lds_000_int_7_0_n AMIGA_BUS_ENABLE_INT_2_sqmuxa \ +# state_machine_size_dma_4_0_0__n N_89 state_machine_size_dma_4_0_1__n N_95 N_91_i N_96 N_97 N_100_i N_99 un1_SM_AMIGA_8_0 \ +# state_machine_un28_clk_000_d1_n N_164_i N_101 N_163_i un1_SM_AMIGA_12 AMIGA_BUS_DATA_DIR_c_0 AS_030_000_SYNC_1_sqmuxa RW_000_i_m_i un1_as_030_000_sync8_1 RW_li_m_i \ +# AS_000_INT_1_sqmuxa state_machine_rw_000_int_7_iv_i_n DSACK1_INT_1_sqmuxa size_c_i_1__n state_machine_un10_clk_000_d0_n state_machine_un25_clk_000_d0_i_n state_machine_un12_clk_000_d0_n N_90_i state_machine_un51_clk_000_d0_n state_machine_un53_clk_000_d0_n \ +# N_94_i state_machine_un57_clk_000_d0_n N_93_i AS_030_000_SYNC_0_sqmuxa_2 sm_amiga_ns_0_4__n AS_030_000_SYNC_0_sqmuxa N_87_0 state_machine_un3_clk_030_n state_machine_ds_000_dma_3_0_n FPU_CS_INT_1_sqmuxa \ +# CLK_030_H_i state_machine_un28_clk_030_n CLK_030_H_1_sqmuxa_i un1_as_030_000_sync8 state_machine_clk_030_h_2_f1_0_n N_150 un3_dtack_i state_machine_un5_clk_000_d0_n N_92_i state_machine_un3_clk_000_d1_n \ +# cpu_est_ns_2__n un3_dtack_i_1 N_157 state_machine_un25_clk_000_d0_i_1_n N_156 cpu_est_ns_0_1_2__n state_machine_un10_clk_000_d0_2_n N_210_1 N_154 N_210_2 \ +# N_160 N_220_1 N_152 N_220_2 N_153 N_220_3 N_158 N_220_4 N_159 N_220_5 \ +# cpu_est_ns_1__n N_220_6 state_machine_un6_bgack_000_n DS_000_DMA_1_sqmuxa_1 AS_030_000_SYNC_i UDS_000_INT_0_sqmuxa_1_1 CLK_000_D1_i UDS_000_INT_0_sqmuxa_1_2 cpu_est_i_3__n UDS_000_INT_0_sqmuxa_1_0 \ +# cpu_est_i_2__n UDS_000_INT_0_sqmuxa_2 cpu_est_i_1__n N_164_1_0 cpu_est_i_0__n RW_li_m_1 VPA_D_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 CLK_000_D0_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 \ +# state_machine_un28_clk_030_i_n N_101_1 VMA_INT_i un1_bgack_030_int_d_0_1 AS_030_i state_machine_un8_bg_030_1_n AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n sm_amiga_i_1__n state_machine_un57_clk_000_d0_1_n \ +# DTACK_D0_i state_machine_un49_clk_000_d0_1_n a_i_19__n AS_030_000_SYNC_0_sqmuxa_1 a_i_16__n AS_030_000_SYNC_0_sqmuxa_2_0 a_i_18__n state_machine_un28_clk_030_1_n state_machine_un5_clk_000_d0_i_0_n state_machine_un28_clk_030_2_n \ +# nEXP_SPACE_i state_machine_un28_clk_030_3_n sm_amiga_i_7__n state_machine_un28_clk_030_4_n sm_amiga_i_0__n state_machine_un28_clk_030_5_n N_99_i state_machine_un5_clk_000_d0_1_n sm_amiga_i_2__n state_machine_un5_clk_000_d0_2_n \ +# BGACK_030_INT_i state_machine_un10_clk_000_d0_1_n BGACK_030_INT_D_i state_machine_un10_clk_000_d0_2_0_n sm_amiga_i_6__n state_machine_un10_clk_000_d0_3_n UDS_000_i cpu_est_ns_0_1_1__n LDS_000_i cpu_est_ns_0_2_1__n \ +# AS_000_DMA_0_sqmuxa_i state_machine_un28_clk_000_d1_1_n state_machine_un8_bgack_030_int_i_n cpu_estse_2_un3_n state_machine_un31_bgack_030_int_i_n cpu_estse_2_un1_n sm_amiga_i_5__n cpu_estse_2_un0_n RW_i cpu_estse_1_un3_n \ +# RW_000_i cpu_estse_1_un1_n UDS_000_INT_0_sqmuxa_i cpu_estse_1_un0_n UDS_000_INT_0_sqmuxa_1_i cpu_estse_0_un3_n AS_000_i cpu_estse_0_un1_n DS_030_i cpu_estse_0_un0_n \ +# state_machine_un49_clk_000_d0_i_n ipl_030_0_2__un3_n CLK_030_i ipl_030_0_2__un1_n state_machine_un24_bgack_030_int_i_n ipl_030_0_2__un0_n AS_000_DMA_i ipl_030_0_1__un3_n sm_amiga_i_4__n ipl_030_0_1__un1_n \ +# a_i_30__n ipl_030_0_1__un0_n a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n a_i_29__n ipl_030_0_0__un0_n a_i_26__n bgack_030_int_0_un3_n \ +# a_i_27__n bgack_030_int_0_un1_n a_i_24__n bgack_030_int_0_un0_n a_i_25__n as_030_000_sync_0_un3_n RST_i as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n FPU_CS_INT_i \ +# fpu_cs_int_0_un3_n CLK_OUT_PRE_50_D_i fpu_cs_int_0_un1_n AS_030_c fpu_cs_int_0_un0_n as_000_int_0_un3_n AS_000_c as_000_int_0_un1_n as_000_int_0_un0_n RW_000_c \ +# dsack1_int_0_un3_n dsack1_int_0_un1_n DS_030_c dsack1_int_0_un0_n vma_int_0_un3_n UDS_000_c vma_int_0_un1_n vma_int_0_un0_n LDS_000_c avec_exp_0_un3_n \ +# avec_exp_0_un1_n size_c_0__n avec_exp_0_un0_n bg_000_0_un3_n size_c_1__n bg_000_0_un1_n bg_000_0_un0_n a_c_16__n lds_000_int_0_un3_n lds_000_int_0_un1_n \ +# a_c_17__n lds_000_int_0_un0_n uds_000_int_0_un3_n a_c_18__n uds_000_int_0_un1_n uds_000_int_0_un0_n a_c_19__n rw_000_int_0_un3_n rw_000_int_0_un1_n a_c_20__n \ +# rw_000_int_0_un0_n as_000_dma_0_un3_n a_c_21__n as_000_dma_0_un1_n as_000_dma_0_un0_n a_c_22__n ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_23__n ds_000_dma_0_un0_n \ +# clk_030_h_0_un3_n a_c_24__n clk_030_h_0_un1_n clk_030_h_0_un0_n a_c_25__n a_c_26__n a_c_27__n .model bus68030 .inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF \ VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \ A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF IPL_1_.BLIF \ - IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF inst_BGACK_030_INTreg.BLIF BGACK_000_c.BLIF inst_FPU_CS_INTreg.BLIF inst_avec_expreg.BLIF CLK_030_c.BLIF \ - inst_VMA_INTreg.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_c.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF CLK_OSZI_c.BLIF inst_VPA_D.BLIF inst_CLK_OUT_PRE_50_D.BLIF inst_CLK_000_D0.BLIF \ - CLK_OUT_INTreg.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF inst_DTACK_D0.BLIF IPL_030DFFSH_0_reg.BLIF inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF IPL_030DFFSH_1_reg.BLIF SM_AMIGA_7_.BLIF \ - vcc_n_n.BLIF IPL_030DFFSH_2_reg.BLIF gnd_n_n.BLIF state_machine_un10_clk_000_d0_n.BLIF ipl_c_0__n.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF ipl_c_1__n.BLIF SM_AMIGA_0_.BLIF \ - SM_AMIGA_5_.BLIF ipl_c_2__n.BLIF SM_AMIGA_2_.BLIF inst_RW_000_INT.BLIF DSACK1_c.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF state_machine_un3_clk_out_pre_50_n.BLIF \ - inst_CLK_000_D3.BLIF inst_CLK_030_H.BLIF state_machine_un12_clk_000_d0_n.BLIF inst_DS_000_DMA.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF RST_c.BLIF inst_A0_DMA.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \ - RESETDFFRHreg.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF RW_c.BLIF SM_AMIGA_1_.BLIF un1_DSACK1_INT_0_sqmuxa_3.BLIF fc_c_0__n.BLIF fc_c_1__n.BLIF state_machine_un10_bg_030_n.BLIF \ - state_machine_lds_000_int_7_n.BLIF state_machine_uds_000_int_7_n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF state_machine_un6_bgack_000_0_n.BLIF N_194_0.BLIF N_119_i.BLIF N_120_i.BLIF N_197_0.BLIF state_machine_ds_000_dma_3_0_n.BLIF \ - N_171_i.BLIF state_machine_size_dma_4_0_1__n.BLIF N_130_i.BLIF N_131_i.BLIF CLK_OUT_PRE_25_0.BLIF N_132_i.BLIF N_133_i.BLIF N_134_i.BLIF sm_amiga_ns_0_5__n.BLIF \ - N_135_i.BLIF N_139_i.BLIF cpu_est_0_.BLIF N_140_i.BLIF cpu_est_1_.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF cpu_est_2_.BLIF N_141_i.BLIF cpu_est_3_reg.BLIF \ - N_52_i.BLIF N_143_i.BLIF N_142_i.BLIF state_machine_rw_000_int_7_iv_i_n.BLIF cpu_est_ns_1__n.BLIF N_62_0.BLIF cpu_est_ns_2__n.BLIF N_161_i.BLIF N_193.BLIF \ - N_155_i.BLIF N_196.BLIF N_63_0.BLIF N_28.BLIF N_66_i.BLIF N_30.BLIF N_76_i.BLIF N_55.BLIF CLK_000_D1_i.BLIF \ - N_62.BLIF N_77_i.BLIF N_63.BLIF N_79_0.BLIF N_66.BLIF N_199_0.BLIF N_67.BLIF sm_amiga_i_2__n.BLIF N_69.BLIF \ - N_201_0.BLIF N_70.BLIF N_203_0.BLIF N_71.BLIF cpu_est_ns_0_1__n.BLIF N_75.BLIF N_167_i.BLIF N_76.BLIF N_170_i.BLIF \ - N_77.BLIF N_136_i.BLIF N_79.BLIF N_137_i.BLIF N_90.BLIF N_202_0.BLIF N_200.BLIF N_200_0.BLIF N_202.BLIF \ - N_169_i.BLIF N_204.BLIF N_198_0.BLIF N_114.BLIF N_168_i.BLIF N_115.BLIF un1_DSACK1_INT_0_sqmuxa_3_0.BLIF N_116.BLIF N_90_i.BLIF \ - N_117.BLIF AS_030_c_i.BLIF N_118.BLIF N_75_i.BLIF N_120.BLIF N_71_i.BLIF N_121.BLIF N_69_i.BLIF N_122.BLIF \ - N_67_i.BLIF N_124.BLIF N_150_i.BLIF N_125.BLIF N_151_i.BLIF N_128.BLIF N_129.BLIF N_145_i.BLIF N_132.BLIF \ - N_146_i.BLIF N_136.BLIF N_147_i.BLIF N_137.BLIF cpu_est_ns_0_2__n.BLIF N_138.BLIF N_144_i.BLIF N_140.BLIF N_55_0.BLIF \ - N_142.BLIF N_138_i.BLIF N_144.BLIF N_172_i.BLIF N_145.BLIF N_149_i.BLIF N_146.BLIF N_129_i.BLIF N_147.BLIF \ - N_148.BLIF N_128_i.BLIF N_150.BLIF sm_amiga_ns_0_0__n.BLIF N_151.BLIF N_70_i.BLIF N_155.BLIF N_124_i.BLIF N_166.BLIF \ - state_machine_lds_000_int_7_0_n.BLIF N_167.BLIF state_machine_uds_000_int_7_0_n.BLIF N_168.BLIF N_122_i.BLIF N_169.BLIF N_30_0.BLIF N_170.BLIF N_121_i.BLIF \ - N_172.BLIF N_28_0.BLIF N_220.BLIF N_117_i.BLIF N_230.BLIF N_118_i.BLIF N_133.BLIF N_196_0.BLIF N_143.BLIF \ - N_116_i.BLIF N_143_2.BLIF N_195_i.BLIF N_203.BLIF BG_030_c_i.BLIF N_201.BLIF N_115_i.BLIF N_199.BLIF state_machine_un10_bg_030_0_n.BLIF \ - N_161.BLIF N_193_0.BLIF N_141.BLIF N_204_i.BLIF N_139.BLIF state_machine_un10_clk_000_d0_i_n.BLIF N_135.BLIF state_machine_un12_clk_000_d0_0_n.BLIF N_134.BLIF \ - N_69_i_1.BLIF N_131.BLIF N_76_i_1.BLIF N_130.BLIF N_76_i_2.BLIF N_171.BLIF N_76_i_3.BLIF state_machine_ds_000_dma_3_n.BLIF N_76_i_4.BLIF \ - N_197.BLIF N_76_i_5.BLIF N_119.BLIF N_220_1.BLIF N_194.BLIF N_220_2.BLIF state_machine_un6_bgack_000_n.BLIF N_230_1.BLIF N_143_2_i.BLIF \ - N_230_2.BLIF a_i_18__n.BLIF N_230_3.BLIF a_i_16__n.BLIF N_230_4.BLIF a_i_19__n.BLIF N_230_5.BLIF sm_amiga_i_4__n.BLIF N_230_6.BLIF \ - sm_amiga_i_5__n.BLIF cpu_est_ns_0_1_1__n.BLIF sm_amiga_i_3__n.BLIF cpu_est_ns_0_2_1__n.BLIF CLK_000_D0_i.BLIF N_122_1.BLIF sm_amiga_i_0__n.BLIF N_122_2.BLIF sm_amiga_i_1__n.BLIF \ - N_122_3.BLIF RW_i.BLIF N_115_1.BLIF CLK_030_H_i.BLIF N_115_2.BLIF CLK_030_i.BLIF state_machine_un10_clk_000_d0_1_n.BLIF DTACK_D0_i.BLIF state_machine_un10_clk_000_d0_2_n.BLIF \ - BGACK_030_INT_i.BLIF N_133_1.BLIF AS_000_i.BLIF N_133_2.BLIF UDS_000_i.BLIF N_143_1.BLIF LDS_000_i.BLIF cpu_est_ns_0_1_2__n.BLIF RW_000_i.BLIF \ - N_55_0_1.BLIF sm_amiga_i_6__n.BLIF state_machine_lds_000_int_7_0_1_n.BLIF cpu_est_i_3__n.BLIF state_machine_uds_000_int_7_0_1_n.BLIF sm_amiga_i_7__n.BLIF N_196_0_1.BLIF CLK_000_D2_i.BLIF N_155_1.BLIF \ - cpu_est_i_1__n.BLIF N_148_1.BLIF cpu_est_i_0__n.BLIF N_142_1.BLIF VMA_INT_i.BLIF N_140_1.BLIF VPA_D_i.BLIF N_132_1.BLIF AS_000_DMA_i.BLIF \ - N_124_1.BLIF nEXP_SPACE_i.BLIF state_machine_a0_dma_2_1_n.BLIF cpu_est_i_2__n.BLIF N_120_1.BLIF A0_i.BLIF N_118_1.BLIF size_i_1__n.BLIF N_117_1.BLIF \ - DS_030_i.BLIF N_116_1.BLIF AS_030_000_SYNC_i.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF a_i_30__n.BLIF N_204_1.BLIF a_i_31__n.BLIF bgack_030_int_0_un3_n.BLIF a_i_28__n.BLIF \ - bgack_030_int_0_un1_n.BLIF a_i_29__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_26__n.BLIF as_000_dma_0_un3_n.BLIF a_i_27__n.BLIF as_000_dma_0_un1_n.BLIF a_i_24__n.BLIF as_000_dma_0_un0_n.BLIF \ - a_i_25__n.BLIF ds_000_dma_0_un3_n.BLIF RST_i.BLIF ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF clk_030_h_0_un3_n.BLIF N_114_i.BLIF clk_030_h_0_un1_n.BLIF FPU_CS_INT_i.BLIF \ - clk_030_h_0_un0_n.BLIF CLK_OUT_PRE_50_D_i.BLIF rw_000_int_0_un3_n.BLIF AS_030_c.BLIF rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF AS_000_c.BLIF state_machine_uds_000_int_7_0_m3_un3_n.BLIF state_machine_uds_000_int_7_0_m3_un1_n.BLIF \ - RW_000_c.BLIF state_machine_uds_000_int_7_0_m3_un0_n.BLIF ipl_030_0_0__un3_n.BLIF DS_030_c.BLIF ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF UDS_000_c.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF \ - LDS_000_c.BLIF ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF size_c_0__n.BLIF ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF size_c_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un1_n.BLIF \ - a_c_16__n.BLIF cpu_estse_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF a_c_17__n.BLIF cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF a_c_18__n.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un1_n.BLIF \ - a_c_19__n.BLIF cpu_estse_2_un0_n.BLIF as_030_000_sync_0_un3_n.BLIF a_c_20__n.BLIF as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF a_c_21__n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF \ - a_c_22__n.BLIF uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF a_c_23__n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_c_24__n.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF \ - a_c_25__n.BLIF fpu_cs_int_0_un0_n.BLIF avec_exp_0_un3_n.BLIF a_c_26__n.BLIF avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF a_c_27__n.BLIF bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF \ - a_c_28__n.BLIF bg_000_0_un0_n.BLIF as_000_int_0_un3_n.BLIF a_c_29__n.BLIF as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF a_c_30__n.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF \ - a_c_31__n.BLIF dsack1_int_0_un0_n.BLIF vma_int_0_un3_n.BLIF A0_c.BLIF vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF nEXP_SPACE_c.BLIF AS_030.PIN AS_000.PIN \ - RW_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN \ - RW.PIN + IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF inst_BGACK_030_INTreg.BLIF a_c_31__n.BLIF inst_FPU_CS_INTreg.BLIF inst_avec_expreg.BLIF \ + A0_c.BLIF inst_VMA_INTreg.BLIF inst_AS_030_000_SYNC.BLIF nEXP_SPACE_c.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF inst_VPA_D.BLIF BG_030_c.BLIF inst_CLK_OUT_PRE_50_D.BLIF \ + inst_CLK_000_D0.BLIF BG_000DFFSHreg.BLIF inst_CLK_000_D1.BLIF inst_DTACK_D0.BLIF inst_CLK_OUT_PRE_50.BLIF BGACK_000_c.BLIF inst_CLK_OUT_PRE_25.BLIF SM_AMIGA_1_.BLIF CLK_030_c.BLIF \ + vcc_n_n.BLIF gnd_n_n.BLIF CLK_000_c.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF CLK_OSZI_c.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.BLIF inst_RW_000_INT.BLIF \ + CLK_OUT_INTreg.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF IPL_030DFFSH_0_reg.BLIF state_machine_un3_clk_out_pre_50_n.BLIF inst_CLK_000_D2.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_030_H.BLIF \ + inst_DS_000_DMA.BLIF IPL_030DFFSH_2_reg.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF ipl_c_0__n.BLIF inst_A0_DMA.BLIF SM_AMIGA_5_.BLIF ipl_c_1__n.BLIF SM_AMIGA_4_.BLIF \ + SM_AMIGA_3_.BLIF ipl_c_2__n.BLIF SM_AMIGA_2_.BLIF DSACK1_c.BLIF RST_c.BLIF RESETDFFRHreg.BLIF RW_c.BLIF fc_c_0__n.BLIF CLK_OUT_PRE_25_0.BLIF \ + fc_c_1__n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF cpu_est_0_.BLIF state_machine_un3_clk_000_d1_i_n.BLIF cpu_est_1_.BLIF state_machine_un6_bgack_000_0_n.BLIF cpu_est_2_.BLIF cpu_est_ns_0_1__n.BLIF cpu_est_3_reg.BLIF \ + N_159_i.BLIF cpu_estse.BLIF N_158_i.BLIF N_149_i.BLIF N_150_i.BLIF N_153_i.BLIF AS_000_DMA_0_sqmuxa.BLIF N_152_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ + N_160_i.BLIF N_92.BLIF N_154_i.BLIF state_machine_un49_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF N_210.BLIF N_156_i.BLIF N_220.BLIF N_157_i.BLIF \ + CLK_030_H_1_sqmuxa.BLIF cpu_est_ns_0_2__n.BLIF AS_000_DMA_1_sqmuxa.BLIF state_machine_un10_clk_000_d0_i_n.BLIF DS_000_DMA_1_sqmuxa.BLIF state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un24_bgack_030_int_n.BLIF FPU_CS_INT_1_sqmuxa_i.BLIF state_machine_clk_030_h_2_n.BLIF \ + un1_as_030_000_sync8_1_0.BLIF state_machine_clk_030_h_2_f1_n.BLIF AS_030_000_SYNC_0_sqmuxa_2_i.BLIF state_machine_ds_000_dma_3_n.BLIF un1_as_030_000_sync8_0.BLIF N_87.BLIF un1_SM_AMIGA_12_0.BLIF N_93.BLIF state_machine_un3_clk_030_i_n.BLIF \ + N_94.BLIF state_machine_un57_clk_000_d0_i_n.BLIF N_88.BLIF state_machine_un51_clk_000_d0_i_n.BLIF N_90.BLIF state_machine_un53_clk_000_d0_0_n.BLIF N_164_1.BLIF state_machine_un3_bgack_030_int_d_i_n.BLIF state_machine_un10_bgack_030_int_n.BLIF \ + un1_bgack_030_int_d_0.BLIF UDS_000_INT_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF UDS_000_INT_0_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF state_machine_un25_clk_000_d0_n.BLIF N_86_0.BLIF N_164.BLIF N_101_i.BLIF \ + RW_li_m.BLIF N_85_i.BLIF N_181.BLIF N_84_0.BLIF RW_000_i_m.BLIF N_97_i.BLIF N_163.BLIF un1_SM_AMIGA_8.BLIF N_96_i.BLIF \ + N_100.BLIF N_95_i.BLIF N_91.BLIF sm_amiga_ns_0_5__n.BLIF state_machine_un31_bgack_030_int_n.BLIF N_88_i.BLIF state_machine_lds_000_int_7_n.BLIF N_89_i.BLIF state_machine_uds_000_int_7_n.BLIF \ + sm_amiga_ns_0_0__n.BLIF RW_000_INT_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AS_030_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF N_59.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF un1_bgack_030_int_d.BLIF BG_030_c_i.BLIF \ + un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF state_machine_un8_bg_030_i_n.BLIF state_machine_un10_bg_030_n.BLIF state_machine_un10_bg_030_0_n.BLIF state_machine_un3_bgack_030_int_d_n.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF N_59_0.BLIF N_86.BLIF \ + state_machine_un10_bgack_030_int_0_n.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF N_181_i.BLIF N_84.BLIF A0_c_i.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF state_machine_uds_000_int_7_0_n.BLIF state_machine_un8_bg_030_n.BLIF state_machine_lds_000_int_7_0_n.BLIF \ + AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF state_machine_size_dma_4_0_0__n.BLIF N_89.BLIF state_machine_size_dma_4_0_1__n.BLIF N_95.BLIF N_91_i.BLIF N_96.BLIF N_97.BLIF N_100_i.BLIF \ + N_99.BLIF un1_SM_AMIGA_8_0.BLIF state_machine_un28_clk_000_d1_n.BLIF N_164_i.BLIF N_101.BLIF N_163_i.BLIF un1_SM_AMIGA_12.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF AS_030_000_SYNC_1_sqmuxa.BLIF \ + RW_000_i_m_i.BLIF un1_as_030_000_sync8_1.BLIF RW_li_m_i.BLIF AS_000_INT_1_sqmuxa.BLIF state_machine_rw_000_int_7_iv_i_n.BLIF DSACK1_INT_1_sqmuxa.BLIF size_c_i_1__n.BLIF state_machine_un10_clk_000_d0_n.BLIF state_machine_un25_clk_000_d0_i_n.BLIF \ + state_machine_un12_clk_000_d0_n.BLIF N_90_i.BLIF state_machine_un51_clk_000_d0_n.BLIF state_machine_un53_clk_000_d0_n.BLIF N_94_i.BLIF state_machine_un57_clk_000_d0_n.BLIF N_93_i.BLIF AS_030_000_SYNC_0_sqmuxa_2.BLIF sm_amiga_ns_0_4__n.BLIF \ + AS_030_000_SYNC_0_sqmuxa.BLIF N_87_0.BLIF state_machine_un3_clk_030_n.BLIF state_machine_ds_000_dma_3_0_n.BLIF FPU_CS_INT_1_sqmuxa.BLIF CLK_030_H_i.BLIF state_machine_un28_clk_030_n.BLIF CLK_030_H_1_sqmuxa_i.BLIF un1_as_030_000_sync8.BLIF \ + state_machine_clk_030_h_2_f1_0_n.BLIF N_150.BLIF un3_dtack_i.BLIF state_machine_un5_clk_000_d0_n.BLIF N_92_i.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_est_ns_2__n.BLIF un3_dtack_i_1.BLIF N_157.BLIF \ + state_machine_un25_clk_000_d0_i_1_n.BLIF N_156.BLIF cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_n.BLIF N_210_1.BLIF N_154.BLIF N_210_2.BLIF N_160.BLIF N_220_1.BLIF \ + N_152.BLIF N_220_2.BLIF N_153.BLIF N_220_3.BLIF N_158.BLIF N_220_4.BLIF N_159.BLIF N_220_5.BLIF cpu_est_ns_1__n.BLIF \ + N_220_6.BLIF state_machine_un6_bgack_000_n.BLIF DS_000_DMA_1_sqmuxa_1.BLIF AS_030_000_SYNC_i.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF CLK_000_D1_i.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF cpu_est_i_3__n.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF \ + cpu_est_i_2__n.BLIF UDS_000_INT_0_sqmuxa_2.BLIF cpu_est_i_1__n.BLIF N_164_1_0.BLIF cpu_est_i_0__n.BLIF RW_li_m_1.BLIF VPA_D_i.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF CLK_000_D0_i.BLIF \ + AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF state_machine_un28_clk_030_i_n.BLIF N_101_1.BLIF VMA_INT_i.BLIF un1_bgack_030_int_d_0_1.BLIF AS_030_i.BLIF state_machine_un8_bg_030_1_n.BLIF AS_030_000_SYNC_0_sqmuxa_i.BLIF state_machine_un8_bg_030_2_n.BLIF \ + sm_amiga_i_1__n.BLIF state_machine_un57_clk_000_d0_1_n.BLIF DTACK_D0_i.BLIF state_machine_un49_clk_000_d0_1_n.BLIF a_i_19__n.BLIF AS_030_000_SYNC_0_sqmuxa_1.BLIF a_i_16__n.BLIF AS_030_000_SYNC_0_sqmuxa_2_0.BLIF a_i_18__n.BLIF \ + state_machine_un28_clk_030_1_n.BLIF state_machine_un5_clk_000_d0_i_0_n.BLIF state_machine_un28_clk_030_2_n.BLIF nEXP_SPACE_i.BLIF state_machine_un28_clk_030_3_n.BLIF sm_amiga_i_7__n.BLIF state_machine_un28_clk_030_4_n.BLIF sm_amiga_i_0__n.BLIF state_machine_un28_clk_030_5_n.BLIF \ + N_99_i.BLIF state_machine_un5_clk_000_d0_1_n.BLIF sm_amiga_i_2__n.BLIF state_machine_un5_clk_000_d0_2_n.BLIF BGACK_030_INT_i.BLIF state_machine_un10_clk_000_d0_1_n.BLIF BGACK_030_INT_D_i.BLIF state_machine_un10_clk_000_d0_2_0_n.BLIF sm_amiga_i_6__n.BLIF \ + state_machine_un10_clk_000_d0_3_n.BLIF UDS_000_i.BLIF cpu_est_ns_0_1_1__n.BLIF LDS_000_i.BLIF cpu_est_ns_0_2_1__n.BLIF AS_000_DMA_0_sqmuxa_i.BLIF state_machine_un28_clk_000_d1_1_n.BLIF state_machine_un8_bgack_030_int_i_n.BLIF cpu_estse_2_un3_n.BLIF \ + state_machine_un31_bgack_030_int_i_n.BLIF cpu_estse_2_un1_n.BLIF sm_amiga_i_5__n.BLIF cpu_estse_2_un0_n.BLIF RW_i.BLIF cpu_estse_1_un3_n.BLIF RW_000_i.BLIF cpu_estse_1_un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \ + cpu_estse_1_un0_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF cpu_estse_0_un3_n.BLIF AS_000_i.BLIF cpu_estse_0_un1_n.BLIF DS_030_i.BLIF cpu_estse_0_un0_n.BLIF state_machine_un49_clk_000_d0_i_n.BLIF ipl_030_0_2__un3_n.BLIF \ + CLK_030_i.BLIF ipl_030_0_2__un1_n.BLIF state_machine_un24_bgack_030_int_i_n.BLIF ipl_030_0_2__un0_n.BLIF AS_000_DMA_i.BLIF ipl_030_0_1__un3_n.BLIF sm_amiga_i_4__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_30__n.BLIF \ + ipl_030_0_1__un0_n.BLIF a_i_31__n.BLIF ipl_030_0_0__un3_n.BLIF a_i_28__n.BLIF ipl_030_0_0__un1_n.BLIF a_i_29__n.BLIF ipl_030_0_0__un0_n.BLIF a_i_26__n.BLIF bgack_030_int_0_un3_n.BLIF \ + a_i_27__n.BLIF bgack_030_int_0_un1_n.BLIF a_i_24__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_25__n.BLIF as_030_000_sync_0_un3_n.BLIF RST_i.BLIF as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ + FPU_CS_INT_i.BLIF fpu_cs_int_0_un3_n.BLIF CLK_OUT_PRE_50_D_i.BLIF fpu_cs_int_0_un1_n.BLIF AS_030_c.BLIF fpu_cs_int_0_un0_n.BLIF as_000_int_0_un3_n.BLIF AS_000_c.BLIF as_000_int_0_un1_n.BLIF \ + as_000_int_0_un0_n.BLIF RW_000_c.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF DS_030_c.BLIF dsack1_int_0_un0_n.BLIF vma_int_0_un3_n.BLIF UDS_000_c.BLIF vma_int_0_un1_n.BLIF \ + vma_int_0_un0_n.BLIF LDS_000_c.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un1_n.BLIF size_c_0__n.BLIF avec_exp_0_un0_n.BLIF bg_000_0_un3_n.BLIF size_c_1__n.BLIF bg_000_0_un1_n.BLIF \ + bg_000_0_un0_n.BLIF a_c_16__n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF a_c_17__n.BLIF lds_000_int_0_un0_n.BLIF uds_000_int_0_un3_n.BLIF a_c_18__n.BLIF uds_000_int_0_un1_n.BLIF \ + uds_000_int_0_un0_n.BLIF a_c_19__n.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un1_n.BLIF a_c_20__n.BLIF rw_000_int_0_un0_n.BLIF as_000_dma_0_un3_n.BLIF a_c_21__n.BLIF as_000_dma_0_un1_n.BLIF \ + as_000_dma_0_un0_n.BLIF a_c_22__n.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un1_n.BLIF a_c_23__n.BLIF ds_000_dma_0_un0_n.BLIF clk_030_h_0_un3_n.BLIF a_c_24__n.BLIF clk_030_h_0_un1_n.BLIF \ + clk_030_h_0_un0_n.BLIF a_c_25__n.BLIF a_c_26__n.BLIF a_c_27__n.BLIF AS_030.PIN AS_000.PIN RW_000.PIN DS_030.PIN UDS_000.PIN \ + LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK1.PIN DTACK.PIN RW.PIN .outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC AVEC_EXP E VMA \ - RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.D \ - cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR \ - SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C \ - IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D \ - SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ - inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C \ - inst_CLK_OUT_PRE_25.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_avec_expreg.D \ - inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \ - inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_000_INT.AP inst_RW_000_INT.D inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.D inst_CLK_030_H.C \ + RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D \ + cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ + IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C \ + SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \ + SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP \ + inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP SIZE_DMA_1_.D SIZE_DMA_1_.C \ + SIZE_DMA_1_.AP inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_avec_expreg.D inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D \ + BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_000_INT.AP \ + inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_RW_000_INT.D inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.D inst_CLK_030_H.C \ inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_DTACK_D0.D inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.D inst_CLK_000_D2.C \ - inst_CLK_000_D2.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D \ - inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \ - inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR CLK_OUT_PRE_25_0.X1 CLK_OUT_PRE_25_0.X2 SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ BG_030_c BGACK_000_c CLK_030_c \ - CLK_000_c CLK_OSZI_c vcc_n_n gnd_n_n state_machine_un10_clk_000_d0_n ipl_c_0__n ipl_c_1__n ipl_c_2__n DSACK1_c state_machine_un3_clk_out_pre_50_n state_machine_un12_clk_000_d0_n \ - RST_c AMIGA_BUS_ENABLE_INT_2_sqmuxa RW_c un1_DSACK1_INT_0_sqmuxa_3 fc_c_0__n fc_c_1__n state_machine_un10_bg_030_n state_machine_lds_000_int_7_n state_machine_uds_000_int_7_n AMIGA_BUS_DATA_DIR_c state_machine_un6_bgack_000_0_n \ - N_194_0 N_119_i N_120_i N_197_0 state_machine_ds_000_dma_3_0_n N_171_i state_machine_size_dma_4_0_1__n N_130_i N_131_i N_132_i N_133_i \ - N_134_i sm_amiga_ns_0_5__n N_135_i N_139_i N_140_i AMIGA_BUS_DATA_DIR_c_0 N_141_i N_52_i N_143_i N_142_i state_machine_rw_000_int_7_iv_i_n \ - cpu_est_ns_1__n N_62_0 cpu_est_ns_2__n N_161_i N_193 N_155_i N_196 N_63_0 N_28 N_66_i N_30 \ - N_76_i N_55 CLK_000_D1_i N_62 N_77_i N_63 N_79_0 N_66 N_199_0 N_67 sm_amiga_i_2__n \ - N_69 N_201_0 N_70 N_203_0 N_71 cpu_est_ns_0_1__n N_75 N_167_i N_76 N_170_i N_77 \ - N_136_i N_79 N_137_i N_90 N_202_0 N_200 N_200_0 N_202 N_169_i N_204 N_198_0 \ - N_114 N_168_i N_115 un1_DSACK1_INT_0_sqmuxa_3_0 N_116 N_90_i N_117 AS_030_c_i N_118 N_75_i N_120 \ - N_71_i N_121 N_69_i N_122 N_67_i N_124 N_150_i N_125 N_151_i N_128 N_129 \ - N_145_i N_132 N_146_i N_136 N_147_i N_137 cpu_est_ns_0_2__n N_138 N_144_i N_140 N_55_0 \ - N_142 N_138_i N_144 N_172_i N_145 N_149_i N_146 N_129_i N_147 N_148 N_128_i \ - N_150 sm_amiga_ns_0_0__n N_151 N_70_i N_155 N_124_i N_166 state_machine_lds_000_int_7_0_n N_167 state_machine_uds_000_int_7_0_n N_168 \ - N_122_i N_169 N_30_0 N_170 N_121_i N_172 N_28_0 N_220 N_117_i N_230 N_118_i \ - N_133 N_196_0 N_143 N_116_i N_143_2 N_195_i N_203 BG_030_c_i N_201 N_115_i N_199 \ - state_machine_un10_bg_030_0_n N_161 N_193_0 N_141 N_204_i N_139 state_machine_un10_clk_000_d0_i_n N_135 state_machine_un12_clk_000_d0_0_n N_134 N_69_i_1 \ - N_131 N_76_i_1 N_130 N_76_i_2 N_171 N_76_i_3 state_machine_ds_000_dma_3_n N_76_i_4 N_197 N_76_i_5 N_119 \ - N_220_1 N_194 N_220_2 state_machine_un6_bgack_000_n N_230_1 N_143_2_i N_230_2 a_i_18__n N_230_3 a_i_16__n N_230_4 \ - a_i_19__n N_230_5 sm_amiga_i_4__n N_230_6 sm_amiga_i_5__n cpu_est_ns_0_1_1__n sm_amiga_i_3__n cpu_est_ns_0_2_1__n CLK_000_D0_i N_122_1 sm_amiga_i_0__n \ - N_122_2 sm_amiga_i_1__n N_122_3 RW_i N_115_1 CLK_030_H_i N_115_2 CLK_030_i state_machine_un10_clk_000_d0_1_n DTACK_D0_i state_machine_un10_clk_000_d0_2_n \ - BGACK_030_INT_i N_133_1 AS_000_i N_133_2 UDS_000_i N_143_1 LDS_000_i cpu_est_ns_0_1_2__n RW_000_i N_55_0_1 sm_amiga_i_6__n \ - state_machine_lds_000_int_7_0_1_n cpu_est_i_3__n state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_196_0_1 CLK_000_D2_i N_155_1 cpu_est_i_1__n N_148_1 cpu_est_i_0__n N_142_1 \ - VMA_INT_i N_140_1 VPA_D_i N_132_1 AS_000_DMA_i N_124_1 nEXP_SPACE_i state_machine_a0_dma_2_1_n cpu_est_i_2__n N_120_1 A0_i \ - N_118_1 size_i_1__n N_117_1 DS_030_i N_116_1 AS_030_000_SYNC_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 a_i_30__n N_204_1 a_i_31__n bgack_030_int_0_un3_n \ - a_i_28__n bgack_030_int_0_un1_n a_i_29__n bgack_030_int_0_un0_n a_i_26__n as_000_dma_0_un3_n a_i_27__n as_000_dma_0_un1_n a_i_24__n as_000_dma_0_un0_n a_i_25__n \ - ds_000_dma_0_un3_n RST_i ds_000_dma_0_un1_n ds_000_dma_0_un0_n clk_030_h_0_un3_n N_114_i clk_030_h_0_un1_n FPU_CS_INT_i clk_030_h_0_un0_n CLK_OUT_PRE_50_D_i rw_000_int_0_un3_n \ - AS_030_c rw_000_int_0_un1_n rw_000_int_0_un0_n AS_000_c state_machine_uds_000_int_7_0_m3_un3_n state_machine_uds_000_int_7_0_m3_un1_n RW_000_c state_machine_uds_000_int_7_0_m3_un0_n ipl_030_0_0__un3_n DS_030_c ipl_030_0_0__un1_n \ - ipl_030_0_0__un0_n UDS_000_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n LDS_000_c ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n \ - cpu_estse_0_un3_n cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_17__n cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n cpu_estse_2_un3_n cpu_estse_2_un1_n \ - a_c_19__n cpu_estse_2_un0_n as_030_000_sync_0_un3_n a_c_20__n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n a_c_21__n uds_000_int_0_un3_n uds_000_int_0_un1_n a_c_22__n uds_000_int_0_un0_n \ - lds_000_int_0_un3_n a_c_23__n lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_24__n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n a_c_25__n fpu_cs_int_0_un0_n avec_exp_0_un3_n a_c_26__n \ - avec_exp_0_un1_n avec_exp_0_un0_n a_c_27__n bg_000_0_un3_n bg_000_0_un1_n a_c_28__n bg_000_0_un0_n as_000_int_0_un3_n a_c_29__n as_000_int_0_un1_n as_000_int_0_un0_n \ - a_c_30__n dsack1_int_0_un3_n dsack1_int_0_un1_n a_c_31__n dsack1_int_0_un0_n vma_int_0_un3_n A0_c vma_int_0_un1_n vma_int_0_un0_n nEXP_SPACE_c \ - AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE \ - DSACK1.OE DTACK.OE RW.OE BERR.OE CIIN.OE + inst_CLK_000_D2.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D \ + inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR \ + RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR cpu_estse.X1 cpu_estse.X2 CLK_OUT_PRE_25_0.X1 CLK_OUT_PRE_25_0.X2 SIZE_1_ AS_030 AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ a_c_28__n a_c_29__n a_c_30__n a_c_31__n \ + A0_c nEXP_SPACE_c BG_030_c BGACK_000_c CLK_030_c vcc_n_n gnd_n_n CLK_000_c CLK_OSZI_c state_machine_un3_clk_out_pre_50_n ipl_c_0__n \ + ipl_c_1__n ipl_c_2__n DSACK1_c RST_c RW_c fc_c_0__n fc_c_1__n AMIGA_BUS_DATA_DIR_c state_machine_un3_clk_000_d1_i_n state_machine_un6_bgack_000_0_n cpu_est_ns_0_1__n \ + N_159_i N_158_i N_149_i N_150_i N_153_i AS_000_DMA_0_sqmuxa N_152_i state_machine_un8_bgack_030_int_n N_160_i N_92 N_154_i \ + state_machine_un49_clk_000_d0_n state_machine_un10_clk_000_d0_2_i_n N_210 N_156_i N_220 N_157_i CLK_030_H_1_sqmuxa cpu_est_ns_0_2__n AS_000_DMA_1_sqmuxa state_machine_un10_clk_000_d0_i_n DS_000_DMA_1_sqmuxa \ + state_machine_un12_clk_000_d0_0_n state_machine_un24_bgack_030_int_n FPU_CS_INT_1_sqmuxa_i state_machine_clk_030_h_2_n un1_as_030_000_sync8_1_0 state_machine_clk_030_h_2_f1_n AS_030_000_SYNC_0_sqmuxa_2_i state_machine_ds_000_dma_3_n un1_as_030_000_sync8_0 N_87 un1_SM_AMIGA_12_0 \ + N_93 state_machine_un3_clk_030_i_n N_94 state_machine_un57_clk_000_d0_i_n N_88 state_machine_un51_clk_000_d0_i_n N_90 state_machine_un53_clk_000_d0_0_n N_164_1 state_machine_un3_bgack_030_int_d_i_n state_machine_un10_bgack_030_int_n \ + un1_bgack_030_int_d_0 UDS_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i UDS_000_INT_0_sqmuxa AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i state_machine_un25_clk_000_d0_n N_86_0 N_164 N_101_i RW_li_m N_85_i \ + N_181 N_84_0 RW_000_i_m N_97_i N_163 un1_SM_AMIGA_8 N_96_i N_100 N_95_i N_91 sm_amiga_ns_0_5__n \ + state_machine_un31_bgack_030_int_n N_88_i state_machine_lds_000_int_7_n N_89_i state_machine_uds_000_int_7_n sm_amiga_ns_0_0__n RW_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_2_sqmuxa_i un1_AS_030_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i N_59 \ + un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 un1_bgack_030_int_d BG_030_c_i un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un8_bg_030_i_n state_machine_un10_bg_030_n state_machine_un10_bg_030_0_n state_machine_un3_bgack_030_int_d_n state_machine_un5_bgack_030_int_d_i_n AMIGA_BUS_ENABLE_INT_3_sqmuxa N_59_0 \ + N_86 state_machine_un10_bgack_030_int_0_n AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 N_181_i N_84 A0_c_i AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 state_machine_uds_000_int_7_0_n state_machine_un8_bg_030_n state_machine_lds_000_int_7_0_n AMIGA_BUS_ENABLE_INT_2_sqmuxa \ + state_machine_size_dma_4_0_0__n N_89 state_machine_size_dma_4_0_1__n N_95 N_91_i N_96 N_97 N_100_i N_99 un1_SM_AMIGA_8_0 state_machine_un28_clk_000_d1_n \ + N_164_i N_101 N_163_i un1_SM_AMIGA_12 AMIGA_BUS_DATA_DIR_c_0 AS_030_000_SYNC_1_sqmuxa RW_000_i_m_i un1_as_030_000_sync8_1 RW_li_m_i AS_000_INT_1_sqmuxa state_machine_rw_000_int_7_iv_i_n \ + DSACK1_INT_1_sqmuxa size_c_i_1__n state_machine_un10_clk_000_d0_n state_machine_un25_clk_000_d0_i_n state_machine_un12_clk_000_d0_n N_90_i state_machine_un51_clk_000_d0_n state_machine_un53_clk_000_d0_n N_94_i state_machine_un57_clk_000_d0_n N_93_i \ + AS_030_000_SYNC_0_sqmuxa_2 sm_amiga_ns_0_4__n AS_030_000_SYNC_0_sqmuxa N_87_0 state_machine_un3_clk_030_n state_machine_ds_000_dma_3_0_n FPU_CS_INT_1_sqmuxa CLK_030_H_i state_machine_un28_clk_030_n CLK_030_H_1_sqmuxa_i un1_as_030_000_sync8 \ + state_machine_clk_030_h_2_f1_0_n N_150 un3_dtack_i state_machine_un5_clk_000_d0_n N_92_i state_machine_un3_clk_000_d1_n cpu_est_ns_2__n un3_dtack_i_1 N_157 state_machine_un25_clk_000_d0_i_1_n N_156 \ + cpu_est_ns_0_1_2__n state_machine_un10_clk_000_d0_2_n N_210_1 N_154 N_210_2 N_160 N_220_1 N_152 N_220_2 N_153 N_220_3 \ + N_158 N_220_4 N_159 N_220_5 cpu_est_ns_1__n N_220_6 state_machine_un6_bgack_000_n DS_000_DMA_1_sqmuxa_1 AS_030_000_SYNC_i UDS_000_INT_0_sqmuxa_1_1 CLK_000_D1_i \ + UDS_000_INT_0_sqmuxa_1_2 cpu_est_i_3__n UDS_000_INT_0_sqmuxa_1_0 cpu_est_i_2__n UDS_000_INT_0_sqmuxa_2 cpu_est_i_1__n N_164_1_0 cpu_est_i_0__n RW_li_m_1 VPA_D_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 \ + CLK_000_D0_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 state_machine_un28_clk_030_i_n N_101_1 VMA_INT_i un1_bgack_030_int_d_0_1 AS_030_i state_machine_un8_bg_030_1_n AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n sm_amiga_i_1__n \ + state_machine_un57_clk_000_d0_1_n DTACK_D0_i state_machine_un49_clk_000_d0_1_n a_i_19__n AS_030_000_SYNC_0_sqmuxa_1 a_i_16__n AS_030_000_SYNC_0_sqmuxa_2_0 a_i_18__n state_machine_un28_clk_030_1_n state_machine_un5_clk_000_d0_i_0_n state_machine_un28_clk_030_2_n \ + nEXP_SPACE_i state_machine_un28_clk_030_3_n sm_amiga_i_7__n state_machine_un28_clk_030_4_n sm_amiga_i_0__n state_machine_un28_clk_030_5_n N_99_i state_machine_un5_clk_000_d0_1_n sm_amiga_i_2__n state_machine_un5_clk_000_d0_2_n BGACK_030_INT_i \ + state_machine_un10_clk_000_d0_1_n BGACK_030_INT_D_i state_machine_un10_clk_000_d0_2_0_n sm_amiga_i_6__n state_machine_un10_clk_000_d0_3_n UDS_000_i cpu_est_ns_0_1_1__n LDS_000_i cpu_est_ns_0_2_1__n AS_000_DMA_0_sqmuxa_i state_machine_un28_clk_000_d1_1_n \ + state_machine_un8_bgack_030_int_i_n cpu_estse_2_un3_n state_machine_un31_bgack_030_int_i_n cpu_estse_2_un1_n sm_amiga_i_5__n cpu_estse_2_un0_n RW_i cpu_estse_1_un3_n RW_000_i cpu_estse_1_un1_n UDS_000_INT_0_sqmuxa_i \ + cpu_estse_1_un0_n UDS_000_INT_0_sqmuxa_1_i cpu_estse_0_un3_n AS_000_i cpu_estse_0_un1_n DS_030_i cpu_estse_0_un0_n state_machine_un49_clk_000_d0_i_n ipl_030_0_2__un3_n CLK_030_i ipl_030_0_2__un1_n \ + state_machine_un24_bgack_030_int_i_n ipl_030_0_2__un0_n AS_000_DMA_i ipl_030_0_1__un3_n sm_amiga_i_4__n ipl_030_0_1__un1_n a_i_30__n ipl_030_0_1__un0_n a_i_31__n ipl_030_0_0__un3_n a_i_28__n \ + ipl_030_0_0__un1_n a_i_29__n ipl_030_0_0__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n bgack_030_int_0_un1_n a_i_24__n bgack_030_int_0_un0_n a_i_25__n as_030_000_sync_0_un3_n \ + RST_i as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n FPU_CS_INT_i fpu_cs_int_0_un3_n CLK_OUT_PRE_50_D_i fpu_cs_int_0_un1_n AS_030_c fpu_cs_int_0_un0_n as_000_int_0_un3_n AS_000_c \ + as_000_int_0_un1_n as_000_int_0_un0_n RW_000_c dsack1_int_0_un3_n dsack1_int_0_un1_n DS_030_c dsack1_int_0_un0_n vma_int_0_un3_n UDS_000_c vma_int_0_un1_n vma_int_0_un0_n \ + LDS_000_c avec_exp_0_un3_n avec_exp_0_un1_n size_c_0__n avec_exp_0_un0_n bg_000_0_un3_n size_c_1__n bg_000_0_un1_n bg_000_0_un0_n a_c_16__n lds_000_int_0_un3_n \ + lds_000_int_0_un1_n a_c_17__n lds_000_int_0_un0_n uds_000_int_0_un3_n a_c_18__n uds_000_int_0_un1_n uds_000_int_0_un0_n a_c_19__n rw_000_int_0_un3_n rw_000_int_0_un1_n a_c_20__n \ + rw_000_int_0_un0_n as_000_dma_0_un3_n a_c_21__n as_000_dma_0_un1_n as_000_dma_0_un0_n a_c_22__n ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_23__n ds_000_dma_0_un0_n clk_030_h_0_un3_n \ + a_c_24__n clk_030_h_0_un1_n clk_030_h_0_un0_n a_c_25__n a_c_26__n a_c_27__n AS_030.OE AS_000.OE RW_000.OE \ + DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE \ + BERR.OE CIIN.OE .names inst_AS_000_DMA.BLIF AS_030 1 1 .names AS_030.PIN AS_030_c 1 1 -.names N_148.BLIF AS_030.OE +.names un3_dtack_i.BLIF AS_030.OE 1 1 .names inst_AS_000_INT.BLIF AS_000 1 1 @@ -167,7 +165,7 @@ 1 1 .names DS_030.PIN DS_030_c 1 1 -.names N_148.BLIF DS_030.OE +.names un3_dtack_i.BLIF DS_030.OE 1 1 .names inst_UDS_000_INT.BLIF UDS_000 1 1 @@ -185,19 +183,19 @@ 1 1 .names SIZE_0_.PIN size_c_0__n 1 1 -.names N_148.BLIF SIZE_0_.OE +.names un3_dtack_i.BLIF SIZE_0_.OE 1 1 .names SIZE_DMA_1_.BLIF SIZE_1_ 1 1 .names SIZE_1_.PIN size_c_1__n 1 1 -.names N_148.BLIF SIZE_1_.OE +.names un3_dtack_i.BLIF SIZE_1_.OE 1 1 .names inst_A0_DMA.BLIF A0 1 1 .names A0.PIN A0_c 1 1 -.names N_148.BLIF A0.OE +.names un3_dtack_i.BLIF A0.OE 1 1 .names inst_DSACK1_INT.BLIF DSACK1 1 1 @@ -209,7 +207,7 @@ 1 1 .names DTACK.PIN inst_DTACK_D0.D 1 1 -.names N_148.BLIF DTACK.OE +.names un3_dtack_i.BLIF DTACK.OE 1 1 .names inst_RW_000_INT.BLIF RW 1 1 @@ -221,1032 +219,1023 @@ 1 1 .names FPU_CS_INT_i.BLIF BERR.OE 1 1 -.names N_220.BLIF CIIN +.names N_210.BLIF CIIN 1 1 -.names N_230.BLIF CIIN.OE +.names N_220.BLIF CIIN.OE 1 1 -.names N_90_i.BLIF N_90 +.names N_86_0.BLIF N_86 0 1 -.names AS_030_c.BLIF AS_030_c_i -0 1 -.names RST_i.BLIF inst_CLK_OUT_PRE_50_D.AR -1 1 -.names N_75_i.BLIF N_75 -0 1 -.names N_71_i.BLIF N_71 -0 1 -.names N_69_i.BLIF N_69 -0 1 -.names CLK_000_c.BLIF inst_CLK_000_D0.D -1 1 -.names N_67_i.BLIF N_67 -0 1 -.names N_150.BLIF N_150_i -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C -1 1 -.names N_151.BLIF N_151_i -0 1 -.names N_161.BLIF N_161_i -0 1 -.names RST_i.BLIF inst_CLK_000_D0.AP -1 1 -.names N_155.BLIF N_155_i -0 1 -.names N_63_0.BLIF N_63 -0 1 -.names N_66_i.BLIF N_66 -0 1 -.names N_76_i.BLIF N_76 +.names N_101.BLIF N_101_i 0 1 .names CLK_OSZI_c.BLIF inst_VPA_D.C 1 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i +.names N_84_0.BLIF N_84 0 1 -.names N_77_i.BLIF N_77 +.names N_97.BLIF N_97_i 0 1 .names RST_i.BLIF inst_VPA_D.AP 1 1 -.names N_79_0.BLIF N_79 +.names N_96.BLIF N_96_i 0 1 -.names N_199_0.BLIF N_199 +.names N_95.BLIF N_95_i 0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +.names N_150_i.BLIF N_150 0 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -.names N_201_0.BLIF N_201 +.names N_153.BLIF N_153_i 0 1 .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C 1 1 -.names N_203_0.BLIF N_203 +.names N_152.BLIF N_152_i 0 1 -.names RST_i.BLIF cpu_est_0_.AR -1 1 -.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n +.names N_160.BLIF N_160_i 0 1 .names RST_i.BLIF inst_CLK_OUT_PRE_50.AR 1 1 -.names N_167.BLIF N_167_i +.names N_154.BLIF N_154_i 0 1 -.names N_170.BLIF N_170_i +.names state_machine_un10_clk_000_d0_2_n.BLIF state_machine_un10_clk_000_d0_2_i_n 0 1 -.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D +.names N_156.BLIF N_156_i +0 1 +.names vcc_n_n.BLIF RESETDFFRHreg.D +1 1 +.names N_157.BLIF N_157_i 0 1 .names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 -.names vcc_n_n.BLIF RESETDFFRHreg.D -1 1 -.names N_130.BLIF N_130_i +.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n 0 1 -.names N_131.BLIF N_131_i +.names CLK_OSZI_c.BLIF RESETDFFRHreg.C +1 1 +.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n 0 1 .names RST_i.BLIF cpu_est_1_.AR 1 1 -.names CLK_OSZI_c.BLIF RESETDFFRHreg.C -1 1 -.names N_132.BLIF N_132_i -0 1 -.names N_133.BLIF N_133_i +.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n 0 1 .names RST_i.BLIF RESETDFFRHreg.AR 1 1 -.names N_134.BLIF N_134_i +.names FPU_CS_INT_1_sqmuxa.BLIF FPU_CS_INT_1_sqmuxa_i 0 1 -.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D +.names un1_as_030_000_sync8_1_0.BLIF un1_as_030_000_sync8_1 +0 1 +.names AS_030_000_SYNC_0_sqmuxa_2.BLIF AS_030_000_SYNC_0_sqmuxa_2_i 0 1 .names CLK_OSZI_c.BLIF cpu_est_2_.C 1 1 -.names N_135.BLIF N_135_i -0 1 -.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_PRE_25_0.X1 +.names cpu_est_0_.BLIF cpu_estse.X1 1 1 -.names N_139.BLIF N_139_i +.names un1_as_030_000_sync8_0.BLIF un1_as_030_000_sync8 +0 1 +.names state_machine_un3_clk_000_d1_n.BLIF state_machine_un3_clk_000_d1_i_n 0 1 .names RST_i.BLIF cpu_est_2_.AR 1 1 -.names N_140.BLIF N_140_i -0 1 -.names state_machine_un3_clk_out_pre_50_n.BLIF CLK_OUT_PRE_25_0.X2 -1 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names N_141.BLIF N_141_i -0 1 -.names N_143.BLIF N_143_i -0 1 -.names CLK_OSZI_c.BLIF cpu_est_3_reg.C -1 1 -.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D -1 1 -.names N_142.BLIF N_142_i -0 1 -.names N_62_0.BLIF N_62 -0 1 -.names RST_i.BLIF cpu_est_3_reg.AR +.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse.X2 1 1 .names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n 0 1 -.names N_194_0.BLIF N_194 +.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n 0 1 -.names N_119.BLIF N_119_i +.names N_159.BLIF N_159_i 0 1 -.names N_120.BLIF N_120_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_PRE_25_0.X1 1 1 -.names N_197_0.BLIF N_197 +.names N_158.BLIF N_158_i 0 1 -.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n -0 1 -.names RST_i.BLIF SM_AMIGA_0_.AR +.names CLK_OSZI_c.BLIF cpu_est_3_reg.C 1 1 -.names N_171.BLIF N_171_i -0 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_152 +11 1 +.names state_machine_un3_clk_out_pre_50_n.BLIF CLK_OUT_PRE_25_0.X2 1 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names RST_i.BLIF cpu_est_3_reg.AR +1 1 +.names BGACK_000_c.BLIF state_machine_un3_clk_000_d1_i_n.BLIF state_machine_un6_bgack_000_0_n +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names cpu_estse.BLIF cpu_est_0_.D +1 1 +.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_2_un3_n +0 1 +.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D +1 1 +.names N_149_i.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse_2_un1_n +11 1 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +.names cpu_est_3_reg.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n +11 1 +.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D +1- 1 +-1 1 +.names RST_i.BLIF cpu_est_0_.AR +1 1 +.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_1_un3_n +0 1 +.names cpu_est_ns_2__n.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse_1_un1_n +11 1 +.names cpu_est_2_.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n +11 1 +.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C +1 1 +.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_0_un3_n +0 1 +.names cpu_est_ns_1__n.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse_0_un1_n +11 1 +.names RST_i.BLIF IPL_030DFFSH_0_reg.AP +1 1 +.names cpu_est_1_.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n +11 1 +.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_2__un3_n +0 1 +.names ipl_c_2__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_2__un1_n +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +1 1 +.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D +1- 1 +-1 1 +.names RST_i.BLIF IPL_030DFFSH_1_reg.AP +1 1 +.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_1__un3_n +0 1 +.names ipl_c_1__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_1__un1_n +11 1 +.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C +1 1 +.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_0__un3_n +0 1 +.names ipl_c_0__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_0__un1_n +11 1 +.names RST_i.BLIF IPL_030DFFSH_2_reg.AP +1 1 +.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D +1- 1 +-1 1 .names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 .names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 -.names RST_i.BLIF SIZE_DMA_1_.AP +.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C 1 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n 11 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D 1- 1 -1 1 -.names N_143_2.BLIF N_143_2_i -0 1 -.names N_194.BLIF as_000_dma_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C -1 1 -.names N_143_2_i.BLIF N_194.BLIF as_000_dma_0_un1_n -11 1 -.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 -.names RST_i.BLIF IPL_030DFFSH_0_reg.AP -1 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D -1- 1 --1 1 -.names N_55.BLIF ds_000_dma_0_un3_n -0 1 -.names state_machine_ds_000_dma_3_n.BLIF N_55.BLIF ds_000_dma_0_un1_n -11 1 -.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C -1 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D -1- 1 --1 1 -.names RST_c.BLIF clk_030_h_0_un3_n -0 1 -.names RST_i.BLIF IPL_030DFFSH_1_reg.AP -1 1 -.names N_52_i.BLIF RST_c.BLIF clk_030_h_0_un1_n -11 1 -.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n -11 1 -.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D -1- 1 --1 1 -.names N_197.BLIF rw_000_int_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C -1 1 -.names state_machine_rw_000_int_7_iv_i_n.BLIF N_197.BLIF rw_000_int_0_un1_n -11 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n -11 1 -.names RST_i.BLIF IPL_030DFFSH_2_reg.AP -1 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D -1- 1 --1 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_135 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C -1 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_134 -11 1 .names RST_i.BLIF SM_AMIGA_7_.AP 1 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_66.BLIF sm_amiga_i_3__n.BLIF N_131 +.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_150_i +11 1 +.names N_158_i.BLIF N_159_i.BLIF N_149_i +11 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_160 11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 .names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_130 +.names N_160.BLIF cpu_est_i_3__n.BLIF N_159 11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF N_128 +.names N_150.BLIF cpu_est_2_.BLIF N_158 11 1 .names RST_i.BLIF SM_AMIGA_6_.AR 1 1 -.names inst_CLK_000_D0.BLIF N_201.BLIF SM_AMIGA_1_.D +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_157 11 1 -.names N_166.BLIF N_171.BLIF N_125 +.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_156 11 1 -.names inst_CLK_000_D0.BLIF N_199.BLIF N_119 -11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_114 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n 11 1 .names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 -.names BGACK_000_c.BLIF N_77.BLIF state_machine_un6_bgack_000_0_n -11 1 -.names UDS_000_c.BLIF UDS_000_i +.names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_154 +11 1 .names RST_i.BLIF SM_AMIGA_5_.AR 1 1 -.names LDS_000_c.BLIF LDS_000_i -0 1 -.names LDS_000_i.BLIF UDS_000_i.BLIF N_171 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_153 11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +.names cpu_est_3_reg.BLIF cpu_est_i_3__n 0 1 -.names AS_000_c.BLIF AS_000_i +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names AS_030_000_SYNC_0_sqmuxa.BLIF AS_030_000_SYNC_0_sqmuxa_i 0 1 .names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_166 +.names AS_030_000_SYNC_0_sqmuxa_i.BLIF AS_030_i.BLIF AS_030_000_SYNC_0_sqmuxa_2 +11 1 +.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un3_clk_030_i_n 11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 .names RST_i.BLIF SM_AMIGA_4_.AR 1 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_161 -11 1 -.names CLK_030_c.BLIF CLK_030_i +.names AS_030_c.BLIF AS_030_i 0 1 -.names inst_CLK_030_H.BLIF CLK_030_i.BLIF N_144 +.names AS_030_i.BLIF state_machine_un28_clk_030_i_n.BLIF FPU_CS_INT_1_sqmuxa +11 1 +.names AS_030_i.BLIF N_85_i.BLIF un1_SM_AMIGA_12_0 +11 1 +.names AS_030_000_SYNC_0_sqmuxa_2_i.BLIF state_machine_un3_clk_030_n.BLIF un1_as_030_000_sync8_0 11 1 -.names inst_CLK_030_H.BLIF CLK_030_H_i -0 1 .names CLK_OSZI_c.BLIF SM_AMIGA_3_.C 1 1 -.names A_16_.BLIF a_c_16__n -1 1 -.names CLK_030_H_i.BLIF N_203.BLIF N_141 +.names FPU_CS_INT_1_sqmuxa_i.BLIF state_machine_un3_clk_030_n.BLIF un1_as_030_000_sync8_1_0 +11 1 +.names N_85_i.BLIF un1_as_030_000_sync8.BLIF AS_030_000_SYNC_1_sqmuxa 11 1 -.names A_17_.BLIF a_c_17__n -1 1 -.names RW_c.BLIF RW_i -0 1 .names RST_i.BLIF SM_AMIGA_3_.AR 1 1 -.names A_18_.BLIF a_c_18__n -1 1 -.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_139 -11 1 -.names A_19_.BLIF a_c_19__n -1 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_77_i -11 1 -.names A_20_.BLIF a_c_20__n -1 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_66_i -11 1 -.names A_21_.BLIF a_c_21__n -1 1 -.names N_155_i.BLIF N_161_i.BLIF N_63_0 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names state_machine_un28_clk_030_n.BLIF state_machine_un28_clk_030_i_n +0 1 +.names state_machine_un5_clk_000_d0_i_0_n.BLIF state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n 11 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 .names CLK_OSZI_c.BLIF SM_AMIGA_2_.C 1 1 -.names A_22_.BLIF a_c_22__n -1 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_62_0 -11 1 -.names A_23_.BLIF a_c_23__n -1 1 -.names N_142_i.BLIF N_143_i.BLIF state_machine_rw_000_int_7_iv_i_n +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF state_machine_un3_clk_000_d1_n 11 1 .names RST_i.BLIF SM_AMIGA_2_.AR 1 1 -.names A_24_.BLIF a_c_24__n -1 1 -.names N_141_i.BLIF N_143_2.BLIF N_52_i -11 1 -.names A_25_.BLIF a_c_25__n -1 1 -.names N_139_i.BLIF N_140_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names A_26_.BLIF a_c_26__n -1 1 -.names CLK_000_D0_i.BLIF N_135_i.BLIF SM_AMIGA_0_.D -11 1 -.names A_27_.BLIF a_c_27__n -1 1 -.names N_133_i.BLIF N_134_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 -.names A_28_.BLIF a_c_28__n -1 1 -.names N_131_i.BLIF N_132_i.BLIF SM_AMIGA_3_.D -11 1 -.names A_29_.BLIF a_c_29__n -1 1 -.names CLK_000_D0_i.BLIF N_130_i.BLIF SM_AMIGA_4_.D -11 1 -.names RST_i.BLIF SM_AMIGA_1_.AR -1 1 -.names A_30_.BLIF a_c_30__n -1 1 -.names N_143_2.BLIF N_171_i.BLIF state_machine_size_dma_4_0_1__n -11 1 -.names A_31_.BLIF a_c_31__n -1 1 -.names AS_000_DMA_i.BLIF N_143_2.BLIF state_machine_ds_000_dma_3_0_n -11 1 -.names N_119_i.BLIF N_120_i.BLIF N_197_0 -11 1 -.names nEXP_SPACE.BLIF nEXP_SPACE_c -1 1 -.names CLK_030_c.BLIF N_143_2.BLIF N_194_0 -11 1 -.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C -1 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_71_i -11 1 -.names BG_030.BLIF BG_030_c -1 1 -.names AS_030_c_i.BLIF N_114_i.BLIF N_75_i -11 1 -.names RST_i.BLIF inst_DSACK1_INT.AP -1 1 -.names BG_000DFFSHreg.BLIF BG_000 -1 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n +.names AS_030_000_SYNC_1_sqmuxa.BLIF as_030_000_sync_0_un3_n 0 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030 -1 1 -.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_90_i +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_1_sqmuxa.BLIF as_030_000_sync_0_un1_n 11 1 -.names BGACK_000.BLIF BGACK_000_c -1 1 -.names N_75_i.BLIF N_168_i.BLIF un1_DSACK1_INT_0_sqmuxa_3_0 -11 1 -.names CLK_030.BLIF CLK_030_c -1 1 -.names N_71.BLIF N_169_i.BLIF N_198_0 -11 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -.names CLK_000.BLIF CLK_000_c -1 1 -.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_200_0 -11 1 -.names CLK_OSZI.BLIF CLK_OSZI_c -1 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names RST_i.BLIF inst_VMA_INTreg.AP -1 1 -.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT -1 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_6_.BLIF N_202_0 -11 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP -1 1 -.names N_62.BLIF N_166.BLIF N_143_2 -11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS -1 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ -1 1 -.names AS_000_DMA_i.BLIF CLK_030_c.BLIF N_203_0 -11 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ -1 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_201_0 -11 1 -.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ -1 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_199_0 -11 1 -.names RST_i.BLIF inst_BGACK_030_INTreg.AP -1 1 -.names IPL_0_.BLIF ipl_c_0__n -1 1 -.names CLK_030_i.BLIF N_143_2.BLIF N_79_0 -11 1 -.names IPL_1_.BLIF ipl_c_1__n -1 1 -.names N_167.BLIF cpu_est_i_3__n.BLIF N_172 -11 1 -.names IPL_2_.BLIF ipl_c_2__n -1 1 -.names N_204_i.BLIF state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n -11 1 -.names AS_030_c_i.BLIF N_67.BLIF N_193_0 -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C -1 1 -.names BG_030_c_i.BLIF N_115_i.BLIF state_machine_un10_bg_030_0_n -11 1 -.names vcc_n_n.BLIF AVEC -1 1 -.names inst_BGACK_030_INTreg.BLIF N_116_i.BLIF N_195_i -11 1 -.names RST_i.BLIF inst_CLK_OUT_PRE_25.AR -1 1 -.names inst_avec_expreg.BLIF AVEC_EXP -1 1 -.names AS_030_c_i.BLIF N_121_i.BLIF N_28_0 -11 1 -.names cpu_est_3_reg.BLIF E -1 1 -.names N_122_i.BLIF un1_DSACK1_INT_0_sqmuxa_3_0.BLIF N_30_0 -11 1 -.names VPA.BLIF inst_VPA_D.D -1 1 -.names N_128_i.BLIF N_198_0.BLIF sm_amiga_ns_0_0__n -11 1 -.names inst_VMA_INTreg.BLIF VMA -1 1 -.names N_129_i.BLIF N_198_0.BLIF SM_AMIGA_6_.D -11 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C -1 1 -.names RST.BLIF RST_c -1 1 -.names N_138_i.BLIF N_172_i.BLIF N_149_i -11 1 -.names RESETDFFRHreg.BLIF RESET -1 1 -.names N_150_i.BLIF N_151_i.BLIF cpu_est_0_.D -11 1 -.names RST_i.BLIF SIZE_DMA_0_.AP -1 1 -.names inst_CLK_000_D2.BLIF CLK_000_D2_i -0 1 -.names FC_0_.BLIF fc_c_0__n -1 1 -.names inst_CLK_000_D2.BLIF SM_AMIGA_5_.BLIF N_67_i -11 1 -.names FC_1_.BLIF fc_c_1__n -1 1 -.names RW_c.BLIF state_machine_uds_000_int_7_0_m3_un3_n -0 1 -.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE -1 1 -.names N_67.BLIF RW_c.BLIF state_machine_uds_000_int_7_0_m3_un1_n -11 1 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 -.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR -1 1 -.names N_66.BLIF state_machine_uds_000_int_7_0_m3_un3_n.BLIF state_machine_uds_000_int_7_0_m3_un0_n -11 1 -.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW -1 1 -.names state_machine_uds_000_int_7_0_m3_un1_n.BLIF state_machine_uds_000_int_7_0_m3_un0_n.BLIF N_70 -1- 1 --1 1 -.names RST_i.BLIF inst_LDS_000_INT.AP -1 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names CLK_030_i.BLIF N_62.BLIF N_120_1 -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_145 -11 1 -.names N_120_1.BLIF N_166.BLIF N_120 -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_146 -11 1 -.names DS_030_i.BLIF N_66_i.BLIF N_118_1 -11 1 -.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_147 -11 1 -.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C -1 1 -.names N_118_1.BLIF RW_i.BLIF N_118 -11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names DS_030_i.BLIF N_67_i.BLIF N_117_1 -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names RST_i.BLIF inst_FPU_CS_INTreg.AP -1 1 -.names N_117_1.BLIF RW_c.BLIF N_117 -11 1 -.names N_77.BLIF cpu_est_i_0__n.BLIF N_150 -11 1 -.names N_71.BLIF inst_BGACK_030_INT_D.BLIF N_116_1 -11 1 -.names N_77_i.BLIF cpu_est_0_.BLIF N_151 -11 1 -.names N_116_1.BLIF N_69_i.BLIF N_116 -11 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names CLK_OSZI_c.BLIF inst_avec_expreg.C -1 1 -.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF sm_amiga_i_7__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names CLK_000_D0_i.BLIF N_170.BLIF N_204_1 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_167 -11 1 -.names RST_i.BLIF inst_avec_expreg.AP -1 1 -.names N_204_1.BLIF VPA_D_i.BLIF N_204 -11 1 -.names N_69_i.BLIF N_71_i.BLIF N_168 -11 1 -.names N_196_0_1.BLIF N_117_i.BLIF N_196_0 -11 1 -.names N_69.BLIF SM_AMIGA_7_.BLIF N_169 -11 1 -.names N_90_i.BLIF VMA_INT_i.BLIF N_155_1 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names N_155_1.BLIF VPA_D_i.BLIF N_155 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_170 -11 1 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -.names AS_000_DMA_i.BLIF BGACK_030_INT_i.BLIF N_148_1 -11 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names N_148_1.BLIF nEXP_SPACE_i.BLIF N_148 -11 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 -.names N_79.BLIF RW_i.BLIF N_142_1 -11 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names N_142_1.BLIF SM_AMIGA_6_.BLIF N_142 -11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names N_166.BLIF RW_c.BLIF N_140_1 -11 1 -.names N_140_1.BLIF nEXP_SPACE_i.BLIF N_140 -11 1 -.names DS_030_c.BLIF DS_030_i -0 1 -.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C -1 1 -.names N_63.BLIF CLK_000_D0_i.BLIF N_132_1 -11 1 -.names CLK_030_c.BLIF N_76_i.BLIF N_121 -11 1 -.names N_132_1.BLIF inst_CLK_000_D1.BLIF N_132 -11 1 -.names A0_c.BLIF A0_i -0 1 -.names RST_i.BLIF inst_DS_000_DMA.AP -1 1 -.names A0_i.BLIF size_c_0__n.BLIF N_124_1 -11 1 -.names size_c_1__n.BLIF size_i_1__n -0 1 -.names N_124_1.BLIF size_i_1__n.BLIF N_124 -11 1 -.names inst_CLK_000_D0.BLIF N_200.BLIF SM_AMIGA_5_.D -11 1 -.names UDS_000_c.BLIF LDS_000_i.BLIF state_machine_a0_dma_2_1_n -11 1 -.names N_202.BLIF sm_amiga_i_7__n.BLIF N_129 -11 1 -.names state_machine_a0_dma_2_1_n.BLIF N_166.BLIF inst_A0_DMA.D -11 1 -.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_136 -11 1 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -.names state_machine_un10_clk_000_d0_1_n.BLIF state_machine_un10_clk_000_d0_2_n.BLIF state_machine_un10_clk_000_d0_n -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_133_1 -11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_137 -11 1 -.names RST_i.BLIF inst_AS_000_DMA.AP -1 1 -.names N_63.BLIF SM_AMIGA_3_.BLIF N_133_2 -11 1 -.names N_90.BLIF cpu_est_2_.BLIF N_138 -11 1 -.names N_133_1.BLIF N_133_2.BLIF N_133 -11 1 -.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D -0 1 -.names CLK_030_i.BLIF N_143_2.BLIF N_143_1 -11 1 -.names RST_c.BLIF RST_i -0 1 -.names N_143_1.BLIF RW_000_i.BLIF N_143 -11 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C -1 1 -.names N_147_i.BLIF N_145_i.BLIF cpu_est_ns_0_1_2__n -11 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names cpu_est_ns_0_1_2__n.BLIF N_146_i.BLIF cpu_est_ns_0_2__n -11 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names RST_i.BLIF inst_AS_000_INT.AP -1 1 -.names N_143_2.BLIF N_144_i.BLIF N_55_0_1 -11 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names N_55_0_1.BLIF RW_000_i.BLIF N_55_0 -11 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names N_124_i.BLIF DS_030_i.BLIF state_machine_lds_000_int_7_0_1_n -11 1 -.names N_125.BLIF SIZE_DMA_0_.D -0 1 -.names state_machine_lds_000_int_7_0_1_n.BLIF N_70_i.BLIF state_machine_lds_000_int_7_0_n -11 1 -.names N_77.BLIF ipl_030_0_0__un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 -.names N_70_i.BLIF A0_i.BLIF state_machine_uds_000_int_7_0_1_n -11 1 -.names IPL_030DFFSH_0_reg.BLIF N_77.BLIF ipl_030_0_0__un1_n -11 1 -.names state_machine_uds_000_int_7_0_1_n.BLIF DS_030_i.BLIF state_machine_uds_000_int_7_0_n -11 1 -.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names RST_i.BLIF inst_RW_000_INT.AP -1 1 -.names N_118_i.BLIF AS_030_c_i.BLIF N_196_0_1 -11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D -1- 1 --1 1 -.names N_230_1.BLIF N_230_2.BLIF N_230_5 -11 1 -.names N_77.BLIF ipl_030_0_1__un3_n -0 1 -.names N_230_3.BLIF N_230_4.BLIF N_230_6 -11 1 -.names IPL_030DFFSH_1_reg.BLIF N_77.BLIF ipl_030_0_1__un1_n -11 1 -.names N_230_5.BLIF N_230_6.BLIF N_230 -11 1 -.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -.names N_136_i.BLIF N_137_i.BLIF cpu_est_ns_0_1_1__n -11 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D -1- 1 --1 1 -.names N_167_i.BLIF N_170_i.BLIF cpu_est_ns_0_2_1__n -11 1 -.names N_77.BLIF ipl_030_0_2__un3_n -0 1 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP -1 1 -.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n -11 1 -.names IPL_030DFFSH_2_reg.BLIF N_77.BLIF ipl_030_0_2__un1_n -11 1 -.names inst_BGACK_030_INTreg.BLIF CLK_030_c.BLIF N_122_1 -11 1 -.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names N_76.BLIF SM_AMIGA_7_.BLIF N_122_2 -11 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D -1- 1 --1 1 -.names N_122_1.BLIF N_122_2.BLIF N_122_3 -11 1 -.names N_77.BLIF cpu_estse_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_030_H.C -1 1 -.names N_122_3.BLIF nEXP_SPACE_c.BLIF N_122 -11 1 -.names cpu_est_1_.BLIF N_77.BLIF cpu_estse_0_un1_n -11 1 -.names AS_030_c.BLIF CLK_000_c.BLIF N_115_1 -11 1 -.names cpu_est_ns_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n -11 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_115_2 -11 1 -.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names N_115_1.BLIF N_115_2.BLIF N_115 -11 1 -.names N_77.BLIF cpu_estse_1_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C -1 1 -.names inst_AS_000_INT.BLIF inst_CLK_000_D0.BLIF state_machine_un10_clk_000_d0_1_n -11 1 -.names cpu_est_2_.BLIF N_77.BLIF cpu_estse_1_un1_n -11 1 -.names N_172.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n -11 1 -.names cpu_est_ns_2__n.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n -11 1 -.names RST_i.BLIF inst_UDS_000_INT.AP -1 1 -.names CLK_000_D2_i.BLIF AS_030_000_SYNC_i.BLIF N_69_i_1 -11 1 -.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names N_69_i_1.BLIF inst_CLK_000_D3.BLIF N_69_i -11 1 -.names N_77.BLIF cpu_estse_2_un3_n -0 1 -.names BGACK_000_c.BLIF a_i_19__n.BLIF N_76_i_1 -11 1 -.names cpu_est_3_reg.BLIF N_77.BLIF cpu_estse_2_un1_n -11 1 -.names a_i_16__n.BLIF a_i_18__n.BLIF N_76_i_2 -11 1 -.names N_149_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_A0_DMA.C -1 1 -.names a_c_17__n.BLIF fc_c_0__n.BLIF N_76_i_3 -11 1 -.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D -1- 1 --1 1 -.names N_76_i_1.BLIF N_76_i_2.BLIF N_76_i_4 -11 1 -.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i -0 1 -.names RST_i.BLIF inst_A0_DMA.AP -1 1 -.names N_76_i_3.BLIF fc_c_1__n.BLIF N_76_i_5 -11 1 -.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF state_machine_un3_clk_out_pre_50_n -11 1 -.names N_76_i_4.BLIF N_76_i_5.BLIF N_76_i -11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i -0 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_220_1 -11 1 -.names N_30.BLIF as_030_000_sync_0_un3_n -0 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_220_2 -11 1 -.names un1_DSACK1_INT_0_sqmuxa_3.BLIF N_30.BLIF as_030_000_sync_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C -1 1 -.names N_220_1.BLIF N_220_2.BLIF N_220 -11 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n -11 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_230_1 +.names un1_SM_AMIGA_12.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n 11 1 .names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D 1- 1 -1 1 -.names RST_i.BLIF inst_DTACK_D0.AP +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C 1 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_230_2 -11 1 -.names N_196.BLIF uds_000_int_0_un3_n +.names un1_as_030_000_sync8_1.BLIF fpu_cs_int_0_un3_n 0 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_230_3 +.names inst_FPU_CS_INTreg.BLIF un1_as_030_000_sync8_1.BLIF fpu_cs_int_0_un1_n 11 1 -.names state_machine_uds_000_int_7_n.BLIF N_196.BLIF uds_000_int_0_un1_n -11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_230_4 -11 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D +.names RST_i.BLIF SM_AMIGA_1_.AR 1 1 -.names N_122.BLIF N_122_i -0 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D -1- 1 --1 1 -.names N_30_0.BLIF N_30 -0 1 -.names N_196.BLIF lds_000_int_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C +.names AS_030_c.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n +11 1 +.names A_16_.BLIF a_c_16__n 1 1 -.names N_121.BLIF N_121_i -0 1 -.names state_machine_lds_000_int_7_n.BLIF N_196.BLIF lds_000_int_0_un1_n -11 1 -.names N_28_0.BLIF N_28 -0 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names RST_i.BLIF inst_CLK_000_D2.AP -1 1 -.names N_117.BLIF N_117_i -0 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D -1- 1 --1 1 -.names N_118.BLIF N_118_i -0 1 -.names N_28.BLIF fpu_cs_int_0_un3_n -0 1 -.names N_196_0.BLIF N_196 -0 1 -.names AS_030_c.BLIF N_28.BLIF fpu_cs_int_0_un1_n -11 1 -.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_INTreg.D -1 1 -.names N_116.BLIF N_116_i -0 1 -.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n -11 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 .names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D 1- 1 -1 1 -.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +.names A_17_.BLIF a_c_17__n 1 1 -.names N_115.BLIF N_115_i +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 -.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un3_n -0 1 -.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n -0 1 -.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un1_n -11 1 -.names RST_i.BLIF CLK_OUT_INTreg.AR +.names A_18_.BLIF a_c_18__n 1 1 -.names N_193_0.BLIF N_193 -0 1 -.names N_195_i.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un0_n +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names N_204.BLIF N_204_i -0 1 -.names avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF inst_avec_expreg.D -1- 1 --1 1 -.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n -0 1 -.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n -0 1 -.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 -.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n -0 1 -.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n -11 1 -.names N_145.BLIF N_145_i -0 1 -.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C +.names A_19_.BLIF a_c_19__n 1 1 -.names N_146.BLIF N_146_i -0 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D -1- 1 --1 1 -.names N_147.BLIF N_147_i -0 1 -.names N_193.BLIF as_000_int_0_un3_n -0 1 -.names RST_i.BLIF inst_CLK_000_D3.AP +.names N_59.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names A_20_.BLIF a_c_20__n 1 1 -.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n -0 1 -.names N_67.BLIF N_193.BLIF as_000_int_0_un1_n -11 1 -.names N_144.BLIF N_144_i -0 1 -.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 -.names N_55_0.BLIF N_55 -0 1 .names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D 1- 1 -1 1 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D +.names RST_i.BLIF SM_AMIGA_0_.AR 1 1 -.names N_138.BLIF N_138_i -0 1 -.names N_114.BLIF N_114_i -0 1 -.names N_172.BLIF N_172_i -0 1 -.names N_75.BLIF dsack1_int_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C +.names A_21_.BLIF a_c_21__n 1 1 -.names N_129.BLIF N_129_i +.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n 0 1 -.names N_114_i.BLIF N_75.BLIF dsack1_int_0_un1_n +.names A_22_.BLIF a_c_22__n +1 1 +.names inst_DSACK1_INT.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n 11 1 -.names N_128.BLIF N_128_i -0 1 -.names inst_DSACK1_INT.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n -11 1 -.names RST_i.BLIF inst_CLK_000_D1.AP +.names A_23_.BLIF a_c_23__n +1 1 +.names sm_amiga_i_1__n.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +11 1 +.names A_24_.BLIF a_c_24__n 1 1 -.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D -0 1 .names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D 1- 1 -1 1 -.names N_70.BLIF N_70_i +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +.names A_25_.BLIF a_c_25__n +1 1 +.names state_machine_un5_clk_000_d0_n.BLIF state_machine_un5_clk_000_d0_i_0_n 0 1 +.names A_26_.BLIF a_c_26__n +1 1 .names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n 0 1 -.names N_124.BLIF N_124_i -0 1 -.names state_machine_un10_clk_000_d0_n.BLIF state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n -11 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D +.names RST_i.BLIF inst_VMA_INTreg.AP +1 1 +.names A_27_.BLIF a_c_27__n +1 1 +.names state_machine_un5_clk_000_d0_i_0_n.BLIF state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n +11 1 +.names A_28_.BLIF a_c_28__n 1 1 -.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n -0 1 .names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n 11 1 -.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n -0 1 +.names A_29_.BLIF a_c_29__n +1 1 .names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 -1 1 +.names A_30_.BLIF a_c_30__n +1 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +.names A_31_.BLIF a_c_31__n +1 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names RST_i.BLIF inst_BGACK_030_INTreg.AP +1 1 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF state_machine_un51_clk_000_d0_n +11 1 +.names BG_030.BLIF BG_030_c +1 1 +.names state_machine_un51_clk_000_d0_i_n.BLIF state_machine_un57_clk_000_d0_i_n.BLIF state_machine_un53_clk_000_d0_0_n +11 1 +.names BG_000DFFSHreg.BLIF BG_000 +1 1 +.names AS_030_i.BLIF N_59.BLIF AS_000_INT_1_sqmuxa +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C +1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names BGACK_000.BLIF BGACK_000_c +1 1 +.names AS_030_i.BLIF sm_amiga_i_1__n.BLIF DSACK1_INT_1_sqmuxa +11 1 +.names RST_i.BLIF inst_CLK_OUT_PRE_25.AR +1 1 +.names CLK_030.BLIF CLK_030_c +1 1 +.names SM_AMIGA_3_.BLIF state_machine_un49_clk_000_d0_n.BLIF N_96 +11 1 +.names CLK_000.BLIF CLK_000_c +1 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names CLK_OSZI.BLIF CLK_OSZI_c +1 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_97 +11 1 +.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT +1 1 +.names CLK_000_D0_i.BLIF N_86.BLIF SM_AMIGA_0_.D +11 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +.names CLK_OUT_INTreg.BLIF CLK_EXP +1 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_1_.BLIF N_99 +11 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS +1 1 +.names N_88_i.BLIF N_89_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names RST_i.BLIF SIZE_DMA_0_.AP +1 1 +.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ +1 1 +.names N_95_i.BLIF N_96_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ +1 1 +.names inst_CLK_000_D0.BLIF N_97_i.BLIF SM_AMIGA_1_.D +11 1 +.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ +1 1 +.names nEXP_SPACE_c.BLIF state_machine_un28_clk_000_d1_n.BLIF N_84_0 +11 1 +.names IPL_0_.BLIF ipl_c_0__n +1 1 +.names N_101_i.BLIF sm_amiga_i_1__n.BLIF N_85_i +11 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +.names IPL_1_.BLIF ipl_c_1__n +1 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_86_0 +11 1 +.names IPL_2_.BLIF ipl_c_2__n +1 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names RST_i.BLIF SIZE_DMA_1_.AP +1 1 +.names N_99.BLIF N_99_i +0 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names vcc_n_n.BLIF AVEC +1 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names inst_avec_expreg.BLIF AVEC_EXP +1 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF N_59_0 +11 1 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +.names cpu_est_3_reg.BLIF E +1 1 +.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un3_n +0 1 +.names VPA.BLIF inst_VPA_D.D +1 1 +.names inst_avec_expreg.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un1_n +11 1 +.names RST_i.BLIF inst_LDS_000_INT.AP +1 1 +.names inst_VMA_INTreg.BLIF VMA +1 1 +.names un1_bgack_030_int_d.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un0_n +11 1 +.names RST.BLIF RST_c +1 1 +.names avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF inst_avec_expreg.D +1- 1 +-1 1 +.names RESETDFFRHreg.BLIF RESET +1 1 +.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C +1 1 +.names FC_0_.BLIF fc_c_0__n +1 1 +.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names FC_1_.BLIF fc_c_1__n +1 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +1- 1 +-1 1 +.names RST_i.BLIF inst_FPU_CS_INTreg.AP +1 1 +.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE +1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF state_machine_un3_bgack_030_int_d_n +11 1 +.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR +1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF state_machine_un5_bgack_030_int_d_i_n +11 1 +.names CLK_OSZI_c.BLIF inst_avec_expreg.C +1 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF state_machine_un5_clk_000_d0_2_n +11 1 +.names N_86.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa +11 1 +.names state_machine_un5_clk_000_d0_1_n.BLIF state_machine_un5_clk_000_d0_2_n.BLIF state_machine_un5_clk_000_d0_n +11 1 +.names inst_BGACK_030_INTreg.BLIF N_84.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 +11 1 +.names RST_i.BLIF inst_avec_expreg.AP +1 1 +.names state_machine_un10_clk_000_d0_2_n.BLIF inst_AS_000_INT.BLIF state_machine_un10_clk_000_d0_1_n +11 1 +.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AS_030_i.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 +11 1 +.names inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF state_machine_un10_clk_000_d0_2_0_n +11 1 +.names BG_030_c_i.BLIF state_machine_un8_bg_030_i_n.BLIF state_machine_un10_bg_030_0_n +11 1 +.names state_machine_un10_clk_000_d0_1_n.BLIF state_machine_un10_clk_000_d0_2_0_n.BLIF state_machine_un10_clk_000_d0_3_n +11 1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 +11 1 +.names state_machine_un10_clk_000_d0_3_n.BLIF cpu_est_i_3__n.BLIF state_machine_un10_clk_000_d0_n +11 1 +.names N_84.BLIF SM_AMIGA_7_.BLIF N_88 +11 1 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +.names N_152_i.BLIF N_153_i.BLIF cpu_est_ns_0_1_1__n +11 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF N_89 +11 1 +.names N_154_i.BLIF N_160_i.BLIF cpu_est_ns_0_2_1__n +11 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_95 +11 1 +.names RST_i.BLIF BG_000DFFSHreg.AP +1 1 +.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n +11 1 +.names state_machine_un31_bgack_030_int_n.BLIF state_machine_un31_bgack_030_int_i_n +0 1 +.names inst_CLK_000_D2.BLIF AS_030_000_SYNC_i.BLIF state_machine_un28_clk_000_d1_1_n +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF state_machine_un31_bgack_030_int_n.BLIF state_machine_size_dma_4_0_0__n +11 1 +.names state_machine_un28_clk_000_d1_1_n.BLIF CLK_000_D1_i.BLIF state_machine_un28_clk_000_d1_n +11 1 +.names N_181_i.BLIF state_machine_un25_clk_000_d0_n.BLIF state_machine_lds_000_int_7_0_n +11 1 +.names state_machine_un8_bg_030_1_n.BLIF state_machine_un8_bg_030_2_n.BLIF state_machine_un8_bg_030_n +11 1 +.names A0_c_i.BLIF N_181_i.BLIF state_machine_uds_000_int_7_0_n +11 1 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +.names VPA_D_i.BLIF N_150_i.BLIF state_machine_un57_clk_000_d0_1_n +11 1 +.names AS_000_DMA_0_sqmuxa.BLIF AS_000_DMA_0_sqmuxa_i +0 1 +.names state_machine_un57_clk_000_d0_1_n.BLIF VMA_INT_i.BLIF state_machine_un57_clk_000_d0_n +11 1 +.names AS_000_DMA_0_sqmuxa_i.BLIF un1_SM_AMIGA_8.BLIF RW_000_INT_0_sqmuxa_1 +11 1 +.names RST_i.BLIF inst_DS_000_DMA.AP +1 1 +.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF state_machine_un49_clk_000_d0_1_n +11 1 +.names AS_030_i.BLIF N_181.BLIF un1_AS_030_2 +11 1 +.names state_machine_un49_clk_000_d0_1_n.BLIF state_machine_un53_clk_000_d0_n.BLIF state_machine_un49_clk_000_d0_n +11 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF state_machine_un31_bgack_030_int_n +11 1 +.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_7_.BLIF AS_030_000_SYNC_0_sqmuxa_1 +11 1 +.names UDS_000_c.BLIF UDS_000_i +0 1 +.names nEXP_SPACE_c.BLIF state_machine_un28_clk_030_i_n.BLIF AS_030_000_SYNC_0_sqmuxa_2_0 +11 1 +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +.names AS_030_000_SYNC_0_sqmuxa_1.BLIF AS_030_000_SYNC_0_sqmuxa_2_0.BLIF AS_030_000_SYNC_0_sqmuxa +11 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF state_machine_un10_bgack_030_int_0_n +11 1 +.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un28_clk_030_1_n +11 1 +.names un1_AS_030_2.BLIF lds_000_int_0_un3_n +0 1 +.names RST_i.BLIF inst_AS_000_DMA.AP +1 1 +.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un28_clk_030_2_n +11 1 +.names inst_LDS_000_INT.BLIF un1_AS_030_2.BLIF lds_000_int_0_un1_n +11 1 +.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un28_clk_030_3_n +11 1 +.names state_machine_lds_000_int_7_n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names state_machine_un28_clk_030_1_n.BLIF state_machine_un28_clk_030_2_n.BLIF state_machine_un28_clk_030_4_n +11 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D +1- 1 +-1 1 +.names state_machine_un28_clk_030_3_n.BLIF fc_c_0__n.BLIF state_machine_un28_clk_030_5_n +11 1 +.names un1_AS_030_2.BLIF uds_000_int_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +.names state_machine_un28_clk_030_4_n.BLIF state_machine_un28_clk_030_5_n.BLIF state_machine_un28_clk_030_n +11 1 +.names inst_UDS_000_INT.BLIF un1_AS_030_2.BLIF uds_000_int_0_un1_n +11 1 +.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un5_clk_000_d0_1_n +11 1 +.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names RST_i.BLIF inst_AS_000_INT.AP +1 1 +.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_2 +11 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D +1- 1 +-1 1 +.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF UDS_000_INT_0_sqmuxa +11 1 +.names RW_000_INT_0_sqmuxa_1.BLIF rw_000_int_0_un3_n +0 1 +.names N_164_1.BLIF RW_c.BLIF N_164_1_0 +11 1 +.names inst_RW_000_INT.BLIF RW_000_INT_0_sqmuxa_1.BLIF rw_000_int_0_un1_n +11 1 +.names N_164_1_0.BLIF nEXP_SPACE_i.BLIF N_164 +11 1 +.names state_machine_rw_000_int_7_iv_i_n.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +1 1 +.names AS_000_DMA_0_sqmuxa_i.BLIF RW_i.BLIF RW_li_m_1 +11 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D +1- 1 +-1 1 +.names RW_li_m_1.BLIF SM_AMIGA_6_.BLIF RW_li_m +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names RST_i.BLIF inst_DSACK1_INT.AP +1 1 +.names N_99_i.BLIF sm_amiga_i_0__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 +11 1 +.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i +0 1 +.names sm_amiga_i_7__n.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 +11 1 +.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_181 +11 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa +11 1 +.names RW_000_i_m_i.BLIF RW_li_m_i.BLIF state_machine_rw_000_int_7_iv_i_n +11 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_101_1 +11 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +.names N_101_1.BLIF state_machine_un28_clk_000_d1_n.BLIF N_101 +11 1 +.names AS_000_DMA_0_sqmuxa.BLIF RW_000_i.BLIF RW_000_i_m +11 1 +.names state_machine_un3_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF un1_bgack_030_int_d_0_1 +11 1 +.names N_163_i.BLIF N_164_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names RST_i.BLIF inst_RW_000_INT.AP +1 1 +.names un1_bgack_030_int_d_0_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF un1_bgack_030_int_d_0 +11 1 +.names RW_c.BLIF RW_i +0 1 +.names AS_030_c.BLIF CLK_000_c.BLIF state_machine_un8_bg_030_1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_163 +11 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF state_machine_un8_bg_030_2_n +11 1 +.names inst_CLK_000_D0.BLIF N_100_i.BLIF un1_SM_AMIGA_8_0 +11 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_210_2 +11 1 +.names inst_CLK_000_D0.BLIF N_91_i.BLIF SM_AMIGA_5_.D +11 1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +.names N_210_1.BLIF N_210_2.BLIF N_210 +11 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_100 +11 1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_220_1 +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names RST_i.BLIF inst_AS_030_000_SYNC.AP +1 1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_220_2 +11 1 +.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_91 +11 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_220_3 +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF state_machine_un31_bgack_030_int_i_n.BLIF state_machine_size_dma_4_0_1__n +11 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_220_4 +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF state_machine_un8_bgack_030_int_i_n +0 1 +.names N_220_1.BLIF N_220_2.BLIF N_220_5 +11 1 +.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C +1 1 +.names N_220_3.BLIF N_220_4.BLIF N_220_6 +11 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n +11 1 +.names N_220_5.BLIF N_220_6.BLIF N_220 +11 1 +.names state_machine_un8_bgack_030_int_i_n.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names RW_000_i.BLIF state_machine_un8_bgack_030_int_n.BLIF DS_000_DMA_1_sqmuxa_1 +11 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D +1- 1 +-1 1 +.names DS_000_DMA_1_sqmuxa_1.BLIF state_machine_un24_bgack_030_int_i_n.BLIF DS_000_DMA_1_sqmuxa +11 1 +.names DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +.names CLK_000_D0_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 +11 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n +11 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF UDS_000_INT_0_sqmuxa_1_2 +11 1 +.names state_machine_ds_000_dma_3_n.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names RST_i.BLIF inst_UDS_000_INT.AP +1 1 +.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF UDS_000_INT_0_sqmuxa_1 +11 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D +1- 1 +-1 1 +.names inst_CLK_000_D0.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 +11 1 +.names RST_c.BLIF clk_030_h_0_un3_n +0 1 +.names N_93.BLIF N_93_i +0 1 +.names state_machine_clk_030_h_2_n.BLIF RST_c.BLIF clk_030_h_0_un1_n +11 1 +.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D +0 1 +.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +.names N_87_0.BLIF N_87 +0 1 +.names clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF inst_CLK_030_H.D +1- 1 +-1 1 +.names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n +0 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_6_.BLIF N_87_0 +11 1 +.names RST_i.BLIF inst_A0_DMA.AP +1 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names N_93_i.BLIF N_94_i.BLIF sm_amiga_ns_0_4__n +11 1 +.names CLK_030_H_1_sqmuxa.BLIF CLK_030_H_1_sqmuxa_i +0 1 +.names N_88_i.BLIF N_90_i.BLIF SM_AMIGA_6_.D +11 1 +.names state_machine_clk_030_h_2_f1_0_n.BLIF state_machine_clk_030_h_2_f1_n +0 1 +.names state_machine_un49_clk_000_d0_n.BLIF state_machine_un49_clk_000_d0_i_n +0 1 +.names N_92.BLIF N_92_i +0 1 +.names SM_AMIGA_3_.BLIF state_machine_un49_clk_000_d0_i_n.BLIF N_94 +11 1 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 +.names nEXP_SPACE_i.BLIF AS_000_DMA_i.BLIF un3_dtack_i_1 +11 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_93 +11 1 +.names un3_dtack_i_1.BLIF BGACK_030_INT_i.BLIF un3_dtack_i +11 1 +.names N_87.BLIF sm_amiga_i_7__n.BLIF N_90 +11 1 +.names RST_i.BLIF inst_DTACK_D0.AP +1 1 +.names size_c_0__n.BLIF A0_c_i.BLIF state_machine_un25_clk_000_d0_i_1_n +11 1 +.names N_164_1.BLIF state_machine_un10_bgack_030_int_n.BLIF state_machine_un8_bgack_030_int_n +11 1 +.names state_machine_un25_clk_000_d0_i_1_n.BLIF size_c_i_1__n.BLIF state_machine_un25_clk_000_d0_i_n +11 1 +.names DS_030_c.BLIF DS_030_i +0 1 +.names N_157_i.BLIF N_156_i.BLIF cpu_est_ns_0_1_2__n +11 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D +1 1 +.names cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF cpu_est_ns_0_2__n +11 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_164_1 +11 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_210_1 +11 1 +.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C +1 1 +.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n +0 1 +.names state_machine_size_dma_4_0_0__n.BLIF SIZE_DMA_0_.D +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names RST_i.BLIF inst_CLK_000_D2.AP +1 1 +.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D +0 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_92 +11 1 +.names N_91.BLIF N_91_i +0 1 +.names CLK_000_D0_i.BLIF N_92_i.BLIF SM_AMIGA_4_.D +11 1 +.names N_100.BLIF N_100_i +0 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names inst_CLK_OUT_PRE_25.BLIF CLK_OUT_INTreg.D +1 1 +.names un1_SM_AMIGA_8_0.BLIF un1_SM_AMIGA_8 +0 1 +.names AS_000_DMA_i.BLIF CLK_030_c.BLIF CLK_030_H_1_sqmuxa +11 1 +.names N_164.BLIF N_164_i +0 1 +.names state_machine_un24_bgack_030_int_n.BLIF state_machine_un24_bgack_030_int_i_n +0 1 +.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +1 1 +.names N_163.BLIF N_163_i +0 1 +.names state_machine_clk_030_h_2_f1_n.BLIF state_machine_un8_bgack_030_int_n.BLIF state_machine_clk_030_h_2_n +11 1 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c +0 1 +.names CLK_030_H_1_sqmuxa_i.BLIF CLK_030_H_i.BLIF state_machine_clk_030_h_2_f1_0_n +11 1 +.names RST_i.BLIF CLK_OUT_INTreg.AR +1 1 +.names RW_000_i_m.BLIF RW_000_i_m_i +0 1 +.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_n.BLIF state_machine_ds_000_dma_3_0_n +11 1 +.names RW_li_m.BLIF RW_li_m_i +0 1 +.names UDS_000_c.BLIF state_machine_un8_bgack_030_int_n.BLIF inst_A0_DMA.D +11 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_n.BLIF AS_000_DMA_1_sqmuxa +11 1 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D +1 1 +.names state_machine_un25_clk_000_d0_i_n.BLIF state_machine_un25_clk_000_d0_n +0 1 +.names CLK_030_i.BLIF state_machine_un8_bgack_030_int_n.BLIF AS_000_DMA_0_sqmuxa +11 1 +.names N_90.BLIF N_90_i +0 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C +1 1 +.names N_94.BLIF N_94_i +0 1 +.names inst_CLK_030_H.BLIF CLK_030_i.BLIF state_machine_un24_bgack_030_int_n +11 1 +.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D +0 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D +0 1 +.names RST_i.BLIF inst_CLK_000_D1.AP +1 1 +.names N_88.BLIF N_88_i +0 1 +.names RST_c.BLIF RST_i +0 1 +.names N_89.BLIF N_89_i +0 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 +.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D +0 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D +1 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i +0 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i +0 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 .names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 -.names N_136.BLIF N_136_i +.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa 0 1 -.names vcc_n_n -1 -.names N_137.BLIF N_137_i +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names a_c_29__n.BLIF a_i_29__n 0 1 -.names gnd_n_n .names RST_i.BLIF inst_BGACK_030_INT_D.AP 1 1 -.names N_202_0.BLIF N_202 +.names state_machine_un8_bg_030_n.BLIF state_machine_un8_bg_030_i_n 0 1 -.names N_200_0.BLIF N_200 +.names a_c_30__n.BLIF a_i_30__n 0 1 -.names N_169.BLIF N_169_i +.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n +0 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names N_59_0.BLIF N_59 +0 1 +.names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50_D.D 1 1 -.names N_168.BLIF N_168_i +.names state_machine_un10_bgack_030_int_0_n.BLIF state_machine_un10_bgack_030_int_n 0 1 -.names un1_DSACK1_INT_0_sqmuxa_3_0.BLIF un1_DSACK1_INT_0_sqmuxa_3 +.names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF state_machine_un3_clk_out_pre_50_n +11 1 +.names N_181.BLIF N_181_i +0 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i 0 1 .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50_D.C 1 1 +.names A0_c.BLIF A0_c_i +0 1 +.names vcc_n_n +1 +.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n +0 1 +.names gnd_n_n +.names RST_i.BLIF inst_CLK_OUT_PRE_50_D.AR +1 1 +.names un1_SM_AMIGA_12_0.BLIF un1_SM_AMIGA_12 +0 1 +.names state_machine_un3_clk_030_i_n.BLIF state_machine_un3_clk_030_n +0 1 +.names state_machine_un57_clk_000_d0_n.BLIF state_machine_un57_clk_000_d0_i_n +0 1 +.names CLK_000_c.BLIF inst_CLK_000_D0.D +1 1 +.names state_machine_un51_clk_000_d0_n.BLIF state_machine_un51_clk_000_d0_i_n +0 1 +.names state_machine_un53_clk_000_d0_0_n.BLIF state_machine_un53_clk_000_d0_n +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C +1 1 +.names state_machine_un3_bgack_030_int_d_n.BLIF state_machine_un3_bgack_030_int_d_i_n +0 1 +.names un1_bgack_030_int_d_0.BLIF un1_bgack_030_int_d +0 1 +.names RST_i.BLIF inst_CLK_000_D0.AP +1 1 +.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i +0 1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i +0 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index e3d94f4..cce867e 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,81 +1,111 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sun Jun 01 01:03:24 2014 +#$ DATE Sat Jun 07 23:03:19 2014 #$ MODULE bus68030 -#$ PINS 59 A_26_ A_25_ SIZE_1_ A_24_ A_23_ A_31_ A_22_ A_21_ IPL_030_2_ A_20_ A_19_ \ -# IPL_2_ A_18_ A_17_ FC_1_ A_16_ AS_030 IPL_030_1_ AS_000 IPL_030_0_ RW_000 IPL_1_ DS_030 \ -# IPL_0_ UDS_000 FC_0_ LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 \ -# CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET \ -# RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \ -# A_28_ A_27_ -#$ NODES 410 BG_030_c BG_000DFFSHreg inst_BGACK_030_INTreg BGACK_000_c \ -# inst_FPU_CS_INTreg inst_avec_expreg CLK_030_c inst_VMA_INTreg inst_AS_030_000_SYNC \ -# CLK_000_c inst_BGACK_030_INT_D inst_AS_000_DMA CLK_OSZI_c inst_VPA_D \ -# inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 CLK_OUT_INTreg inst_CLK_000_D1 \ -# inst_CLK_000_D2 inst_DTACK_D0 IPL_030DFFSH_0_reg inst_CLK_OUT_PRE_50 \ -# inst_CLK_OUT_PRE_25 IPL_030DFFSH_1_reg SM_AMIGA_7_ vcc_n_n IPL_030DFFSH_2_reg \ -# gnd_n_n state_machine_un10_clk_000_d0_n ipl_c_0__n inst_AS_000_INT SM_AMIGA_6_ \ -# ipl_c_1__n SM_AMIGA_0_ SM_AMIGA_5_ ipl_c_2__n SM_AMIGA_2_ inst_RW_000_INT DSACK1_c \ -# inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT \ -# state_machine_un3_clk_out_pre_50_n inst_CLK_000_D3 inst_CLK_030_H \ -# state_machine_un12_clk_000_d0_n inst_DS_000_DMA SIZE_DMA_0_ SIZE_DMA_1_ RST_c \ -# inst_A0_DMA AMIGA_BUS_ENABLE_INT_2_sqmuxa RESETDFFRHreg SM_AMIGA_4_ SM_AMIGA_3_ \ -# RW_c SM_AMIGA_1_ un1_DSACK1_INT_0_sqmuxa_3 fc_c_0__n fc_c_1__n \ -# state_machine_un10_bg_030_n state_machine_lds_000_int_7_n \ -# state_machine_uds_000_int_7_n AMIGA_BUS_DATA_DIR_c \ -# state_machine_un6_bgack_000_0_n N_194_0 N_119_i N_120_i N_197_0 \ -# state_machine_ds_000_dma_3_0_n N_171_i state_machine_size_dma_4_0_1__n N_130_i \ -# N_131_i CLK_OUT_PRE_25_0 N_132_i N_133_i N_134_i sm_amiga_ns_0_5__n N_135_i N_139_i \ -# cpu_est_0_ N_140_i cpu_est_1_ AMIGA_BUS_DATA_DIR_c_0 cpu_est_2_ N_141_i \ -# cpu_est_3_reg N_52_i N_143_i N_142_i state_machine_rw_000_int_7_iv_i_n \ -# cpu_est_ns_1__n N_62_0 cpu_est_ns_2__n N_161_i N_193 N_155_i N_196 N_63_0 N_28 N_66_i \ -# N_30 N_76_i N_55 CLK_000_D1_i N_62 N_77_i N_63 N_79_0 N_66 N_199_0 N_67 sm_amiga_i_2__n \ -# N_69 N_201_0 N_70 N_203_0 N_71 cpu_est_ns_0_1__n N_75 N_167_i N_76 N_170_i N_77 N_136_i \ -# N_79 N_137_i N_90 N_202_0 N_200 N_200_0 N_202 N_169_i N_204 N_198_0 N_114 N_168_i N_115 \ -# un1_DSACK1_INT_0_sqmuxa_3_0 N_116 N_90_i N_117 AS_030_c_i N_118 N_75_i N_120 N_71_i \ -# N_121 N_69_i N_122 N_67_i N_124 N_150_i N_125 N_151_i N_128 N_129 N_145_i N_132 N_146_i \ -# N_136 N_147_i N_137 cpu_est_ns_0_2__n N_138 N_144_i N_140 N_55_0 N_142 N_138_i N_144 \ -# N_172_i N_145 N_149_i N_146 N_129_i N_147 N_148 N_128_i N_150 sm_amiga_ns_0_0__n N_151 \ -# N_70_i N_155 N_124_i N_166 state_machine_lds_000_int_7_0_n N_167 \ -# state_machine_uds_000_int_7_0_n N_168 N_122_i N_169 N_30_0 N_170 N_121_i N_172 N_28_0 \ -# N_220 N_117_i N_230 N_118_i N_133 N_196_0 N_143 N_116_i N_143_2 N_195_i N_203 BG_030_c_i \ -# N_201 N_115_i N_199 state_machine_un10_bg_030_0_n N_161 N_193_0 N_141 N_204_i N_139 \ -# state_machine_un10_clk_000_d0_i_n N_135 state_machine_un12_clk_000_d0_0_n N_134 \ -# N_69_i_1 N_131 N_76_i_1 N_130 N_76_i_2 N_171 N_76_i_3 state_machine_ds_000_dma_3_n \ -# N_76_i_4 N_197 N_76_i_5 N_119 N_220_1 N_194 N_220_2 state_machine_un6_bgack_000_n \ -# N_230_1 N_143_2_i N_230_2 a_i_18__n N_230_3 a_i_16__n N_230_4 a_i_19__n N_230_5 \ -# sm_amiga_i_4__n N_230_6 sm_amiga_i_5__n cpu_est_ns_0_1_1__n sm_amiga_i_3__n \ -# cpu_est_ns_0_2_1__n CLK_000_D0_i N_122_1 sm_amiga_i_0__n N_122_2 sm_amiga_i_1__n \ -# N_122_3 RW_i N_115_1 CLK_030_H_i N_115_2 CLK_030_i state_machine_un10_clk_000_d0_1_n \ -# DTACK_D0_i state_machine_un10_clk_000_d0_2_n BGACK_030_INT_i N_133_1 AS_000_i \ -# N_133_2 UDS_000_i N_143_1 LDS_000_i cpu_est_ns_0_1_2__n RW_000_i N_55_0_1 \ -# sm_amiga_i_6__n state_machine_lds_000_int_7_0_1_n cpu_est_i_3__n \ -# state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_196_0_1 CLK_000_D2_i N_155_1 \ -# cpu_est_i_1__n N_148_1 cpu_est_i_0__n N_142_1 VMA_INT_i N_140_1 VPA_D_i N_132_1 \ -# AS_000_DMA_i N_124_1 nEXP_SPACE_i state_machine_a0_dma_2_1_n cpu_est_i_2__n N_120_1 \ -# A0_i N_118_1 size_i_1__n N_117_1 DS_030_i N_116_1 AS_030_000_SYNC_i \ -# AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 a_i_30__n N_204_1 a_i_31__n bgack_030_int_0_un3_n \ -# a_i_28__n bgack_030_int_0_un1_n a_i_29__n bgack_030_int_0_un0_n a_i_26__n \ -# as_000_dma_0_un3_n a_i_27__n as_000_dma_0_un1_n a_i_24__n as_000_dma_0_un0_n \ -# a_i_25__n ds_000_dma_0_un3_n RST_i ds_000_dma_0_un1_n ds_000_dma_0_un0_n \ -# clk_030_h_0_un3_n N_114_i clk_030_h_0_un1_n FPU_CS_INT_i clk_030_h_0_un0_n \ -# CLK_OUT_PRE_50_D_i rw_000_int_0_un3_n AS_030_c rw_000_int_0_un1_n \ -# rw_000_int_0_un0_n AS_000_c state_machine_uds_000_int_7_0_m3_un3_n \ -# state_machine_uds_000_int_7_0_m3_un1_n RW_000_c \ -# state_machine_uds_000_int_7_0_m3_un0_n ipl_030_0_0__un3_n DS_030_c \ -# ipl_030_0_0__un1_n ipl_030_0_0__un0_n UDS_000_c ipl_030_0_1__un3_n \ -# ipl_030_0_1__un1_n LDS_000_c ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n \ -# ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n cpu_estse_0_un3_n \ -# cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_17__n \ -# cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n cpu_estse_2_un3_n cpu_estse_2_un1_n \ -# a_c_19__n cpu_estse_2_un0_n as_030_000_sync_0_un3_n a_c_20__n \ -# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n a_c_21__n uds_000_int_0_un3_n \ -# uds_000_int_0_un1_n a_c_22__n uds_000_int_0_un0_n lds_000_int_0_un3_n a_c_23__n \ -# lds_000_int_0_un1_n lds_000_int_0_un0_n a_c_24__n fpu_cs_int_0_un3_n \ -# fpu_cs_int_0_un1_n a_c_25__n fpu_cs_int_0_un0_n avec_exp_0_un3_n a_c_26__n \ -# avec_exp_0_un1_n avec_exp_0_un0_n a_c_27__n bg_000_0_un3_n bg_000_0_un1_n a_c_28__n \ -# bg_000_0_un0_n as_000_int_0_un3_n a_c_29__n as_000_int_0_un1_n as_000_int_0_un0_n \ -# a_c_30__n dsack1_int_0_un3_n dsack1_int_0_un1_n a_c_31__n dsack1_int_0_un0_n \ -# vma_int_0_un3_n A0_c vma_int_0_un1_n vma_int_0_un0_n nEXP_SPACE_c +#$ PINS 59 A_22_ A_21_ SIZE_1_ A_20_ A_19_ A_31_ A_18_ A_17_ IPL_030_2_ A_16_ IPL_030_1_ \ +# IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 \ +# nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT \ +# CLK_EXP FPU_CS DSACK1 DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE \ +# AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ \ +# A_25_ A_24_ A_23_ +#$ NODES 407 a_c_28__n a_c_29__n a_c_30__n inst_BGACK_030_INTreg a_c_31__n \ +# inst_FPU_CS_INTreg inst_avec_expreg A0_c inst_VMA_INTreg inst_AS_030_000_SYNC \ +# nEXP_SPACE_c inst_BGACK_030_INT_D inst_AS_000_DMA inst_VPA_D BG_030_c \ +# inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 BG_000DFFSHreg inst_CLK_000_D1 inst_DTACK_D0 \ +# inst_CLK_OUT_PRE_50 BGACK_000_c inst_CLK_OUT_PRE_25 SM_AMIGA_1_ CLK_030_c vcc_n_n \ +# gnd_n_n CLK_000_c inst_AS_000_INT SM_AMIGA_6_ CLK_OSZI_c SM_AMIGA_0_ SM_AMIGA_7_ \ +# inst_RW_000_INT CLK_OUT_INTreg inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT \ +# IPL_030DFFSH_0_reg state_machine_un3_clk_out_pre_50_n inst_CLK_000_D2 \ +# IPL_030DFFSH_1_reg inst_CLK_030_H inst_DS_000_DMA IPL_030DFFSH_2_reg SIZE_DMA_0_ \ +# SIZE_DMA_1_ ipl_c_0__n inst_A0_DMA SM_AMIGA_5_ ipl_c_1__n SM_AMIGA_4_ SM_AMIGA_3_ \ +# ipl_c_2__n SM_AMIGA_2_ DSACK1_c RST_c RESETDFFRHreg RW_c fc_c_0__n CLK_OUT_PRE_25_0 \ +# fc_c_1__n AMIGA_BUS_DATA_DIR_c cpu_est_0_ state_machine_un3_clk_000_d1_i_n \ +# cpu_est_1_ state_machine_un6_bgack_000_0_n cpu_est_2_ cpu_est_ns_0_1__n \ +# cpu_est_3_reg N_159_i cpu_estse N_158_i N_149_i N_150_i N_153_i AS_000_DMA_0_sqmuxa \ +# N_152_i state_machine_un8_bgack_030_int_n N_160_i N_92 N_154_i \ +# state_machine_un49_clk_000_d0_n state_machine_un10_clk_000_d0_2_i_n N_210 N_156_i \ +# N_220 N_157_i CLK_030_H_1_sqmuxa cpu_est_ns_0_2__n AS_000_DMA_1_sqmuxa \ +# state_machine_un10_clk_000_d0_i_n DS_000_DMA_1_sqmuxa \ +# state_machine_un12_clk_000_d0_0_n state_machine_un24_bgack_030_int_n \ +# FPU_CS_INT_1_sqmuxa_i state_machine_clk_030_h_2_n un1_as_030_000_sync8_1_0 \ +# state_machine_clk_030_h_2_f1_n AS_030_000_SYNC_0_sqmuxa_2_i \ +# state_machine_ds_000_dma_3_n un1_as_030_000_sync8_0 N_87 un1_SM_AMIGA_12_0 N_93 \ +# state_machine_un3_clk_030_i_n N_94 state_machine_un57_clk_000_d0_i_n N_88 \ +# state_machine_un51_clk_000_d0_i_n N_90 state_machine_un53_clk_000_d0_0_n N_164_1 \ +# state_machine_un3_bgack_030_int_d_i_n state_machine_un10_bgack_030_int_n \ +# un1_bgack_030_int_d_0 UDS_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i \ +# UDS_000_INT_0_sqmuxa AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i \ +# state_machine_un25_clk_000_d0_n N_86_0 N_164 N_101_i RW_li_m N_85_i N_181 N_84_0 \ +# RW_000_i_m N_97_i N_163 un1_SM_AMIGA_8 N_96_i N_100 N_95_i N_91 sm_amiga_ns_0_5__n \ +# state_machine_un31_bgack_030_int_n N_88_i state_machine_lds_000_int_7_n N_89_i \ +# state_machine_uds_000_int_7_n sm_amiga_ns_0_0__n RW_000_INT_0_sqmuxa_1 \ +# AMIGA_BUS_ENABLE_INT_2_sqmuxa_i un1_AS_030_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i \ +# N_59 un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 un1_bgack_030_int_d BG_030_c_i \ +# un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un8_bg_030_i_n \ +# state_machine_un10_bg_030_n state_machine_un10_bg_030_0_n \ +# state_machine_un3_bgack_030_int_d_n state_machine_un5_bgack_030_int_d_i_n \ +# AMIGA_BUS_ENABLE_INT_3_sqmuxa N_59_0 N_86 state_machine_un10_bgack_030_int_0_n \ +# AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 N_181_i N_84 A0_c_i \ +# AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 state_machine_uds_000_int_7_0_n \ +# state_machine_un8_bg_030_n state_machine_lds_000_int_7_0_n \ +# AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_size_dma_4_0_0__n N_89 \ +# state_machine_size_dma_4_0_1__n N_95 N_91_i N_96 N_97 N_100_i N_99 un1_SM_AMIGA_8_0 \ +# state_machine_un28_clk_000_d1_n N_164_i N_101 N_163_i un1_SM_AMIGA_12 \ +# AMIGA_BUS_DATA_DIR_c_0 AS_030_000_SYNC_1_sqmuxa RW_000_i_m_i \ +# un1_as_030_000_sync8_1 RW_li_m_i AS_000_INT_1_sqmuxa \ +# state_machine_rw_000_int_7_iv_i_n DSACK1_INT_1_sqmuxa size_c_i_1__n \ +# state_machine_un10_clk_000_d0_n state_machine_un25_clk_000_d0_i_n \ +# state_machine_un12_clk_000_d0_n N_90_i state_machine_un51_clk_000_d0_n \ +# state_machine_un53_clk_000_d0_n N_94_i state_machine_un57_clk_000_d0_n N_93_i \ +# AS_030_000_SYNC_0_sqmuxa_2 sm_amiga_ns_0_4__n AS_030_000_SYNC_0_sqmuxa N_87_0 \ +# state_machine_un3_clk_030_n state_machine_ds_000_dma_3_0_n FPU_CS_INT_1_sqmuxa \ +# CLK_030_H_i state_machine_un28_clk_030_n CLK_030_H_1_sqmuxa_i \ +# un1_as_030_000_sync8 state_machine_clk_030_h_2_f1_0_n N_150 un3_dtack_i \ +# state_machine_un5_clk_000_d0_n N_92_i state_machine_un3_clk_000_d1_n \ +# cpu_est_ns_2__n un3_dtack_i_1 N_157 state_machine_un25_clk_000_d0_i_1_n N_156 \ +# cpu_est_ns_0_1_2__n state_machine_un10_clk_000_d0_2_n N_210_1 N_154 N_210_2 N_160 \ +# N_220_1 N_152 N_220_2 N_153 N_220_3 N_158 N_220_4 N_159 N_220_5 cpu_est_ns_1__n N_220_6 \ +# state_machine_un6_bgack_000_n DS_000_DMA_1_sqmuxa_1 AS_030_000_SYNC_i \ +# UDS_000_INT_0_sqmuxa_1_1 CLK_000_D1_i UDS_000_INT_0_sqmuxa_1_2 cpu_est_i_3__n \ +# UDS_000_INT_0_sqmuxa_1_0 cpu_est_i_2__n UDS_000_INT_0_sqmuxa_2 cpu_est_i_1__n \ +# N_164_1_0 cpu_est_i_0__n RW_li_m_1 VPA_D_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 \ +# CLK_000_D0_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 state_machine_un28_clk_030_i_n \ +# N_101_1 VMA_INT_i un1_bgack_030_int_d_0_1 AS_030_i state_machine_un8_bg_030_1_n \ +# AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n sm_amiga_i_1__n \ +# state_machine_un57_clk_000_d0_1_n DTACK_D0_i state_machine_un49_clk_000_d0_1_n \ +# a_i_19__n AS_030_000_SYNC_0_sqmuxa_1 a_i_16__n AS_030_000_SYNC_0_sqmuxa_2_0 \ +# a_i_18__n state_machine_un28_clk_030_1_n state_machine_un5_clk_000_d0_i_0_n \ +# state_machine_un28_clk_030_2_n nEXP_SPACE_i state_machine_un28_clk_030_3_n \ +# sm_amiga_i_7__n state_machine_un28_clk_030_4_n sm_amiga_i_0__n \ +# state_machine_un28_clk_030_5_n N_99_i state_machine_un5_clk_000_d0_1_n \ +# sm_amiga_i_2__n state_machine_un5_clk_000_d0_2_n BGACK_030_INT_i \ +# state_machine_un10_clk_000_d0_1_n BGACK_030_INT_D_i \ +# state_machine_un10_clk_000_d0_2_0_n sm_amiga_i_6__n \ +# state_machine_un10_clk_000_d0_3_n UDS_000_i cpu_est_ns_0_1_1__n LDS_000_i \ +# cpu_est_ns_0_2_1__n AS_000_DMA_0_sqmuxa_i state_machine_un28_clk_000_d1_1_n \ +# state_machine_un8_bgack_030_int_i_n cpu_estse_2_un3_n \ +# state_machine_un31_bgack_030_int_i_n cpu_estse_2_un1_n sm_amiga_i_5__n \ +# cpu_estse_2_un0_n RW_i cpu_estse_1_un3_n RW_000_i cpu_estse_1_un1_n \ +# UDS_000_INT_0_sqmuxa_i cpu_estse_1_un0_n UDS_000_INT_0_sqmuxa_1_i \ +# cpu_estse_0_un3_n AS_000_i cpu_estse_0_un1_n DS_030_i cpu_estse_0_un0_n \ +# state_machine_un49_clk_000_d0_i_n ipl_030_0_2__un3_n CLK_030_i ipl_030_0_2__un1_n \ +# state_machine_un24_bgack_030_int_i_n ipl_030_0_2__un0_n AS_000_DMA_i \ +# ipl_030_0_1__un3_n sm_amiga_i_4__n ipl_030_0_1__un1_n a_i_30__n ipl_030_0_1__un0_n \ +# a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n a_i_29__n \ +# ipl_030_0_0__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n bgack_030_int_0_un1_n \ +# a_i_24__n bgack_030_int_0_un0_n a_i_25__n as_030_000_sync_0_un3_n RST_i \ +# as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n FPU_CS_INT_i fpu_cs_int_0_un3_n \ +# CLK_OUT_PRE_50_D_i fpu_cs_int_0_un1_n AS_030_c fpu_cs_int_0_un0_n \ +# as_000_int_0_un3_n AS_000_c as_000_int_0_un1_n as_000_int_0_un0_n RW_000_c \ +# dsack1_int_0_un3_n dsack1_int_0_un1_n DS_030_c dsack1_int_0_un0_n vma_int_0_un3_n \ +# UDS_000_c vma_int_0_un1_n vma_int_0_un0_n LDS_000_c avec_exp_0_un3_n \ +# avec_exp_0_un1_n size_c_0__n avec_exp_0_un0_n bg_000_0_un3_n size_c_1__n \ +# bg_000_0_un1_n bg_000_0_un0_n a_c_16__n lds_000_int_0_un3_n lds_000_int_0_un1_n \ +# a_c_17__n lds_000_int_0_un0_n uds_000_int_0_un3_n a_c_18__n uds_000_int_0_un1_n \ +# uds_000_int_0_un0_n a_c_19__n rw_000_int_0_un3_n rw_000_int_0_un1_n a_c_20__n \ +# rw_000_int_0_un0_n as_000_dma_0_un3_n a_c_21__n as_000_dma_0_un1_n \ +# as_000_dma_0_un0_n a_c_22__n ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_23__n \ +# ds_000_dma_0_un0_n clk_030_h_0_un3_n a_c_24__n clk_030_h_0_un1_n clk_030_h_0_un0_n \ +# a_c_25__n a_c_26__n a_c_27__n .model bus68030 .inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \ @@ -83,220 +113,282 @@ A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF \ A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \ A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF \ AS_000.BLIF RW_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF \ -DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF \ -inst_BGACK_030_INTreg.BLIF BGACK_000_c.BLIF inst_FPU_CS_INTreg.BLIF \ -inst_avec_expreg.BLIF CLK_030_c.BLIF inst_VMA_INTreg.BLIF \ -inst_AS_030_000_SYNC.BLIF CLK_000_c.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_AS_000_DMA.BLIF CLK_OSZI_c.BLIF inst_VPA_D.BLIF \ -inst_CLK_OUT_PRE_50_D.BLIF inst_CLK_000_D0.BLIF CLK_OUT_INTreg.BLIF \ -inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF inst_DTACK_D0.BLIF \ -IPL_030DFFSH_0_reg.BLIF inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF \ -IPL_030DFFSH_1_reg.BLIF SM_AMIGA_7_.BLIF vcc_n_n.BLIF IPL_030DFFSH_2_reg.BLIF \ -gnd_n_n.BLIF state_machine_un10_clk_000_d0_n.BLIF ipl_c_0__n.BLIF \ -inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF ipl_c_1__n.BLIF SM_AMIGA_0_.BLIF \ -SM_AMIGA_5_.BLIF ipl_c_2__n.BLIF SM_AMIGA_2_.BLIF inst_RW_000_INT.BLIF \ -DSACK1_c.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF \ -state_machine_un3_clk_out_pre_50_n.BLIF inst_CLK_000_D3.BLIF \ -inst_CLK_030_H.BLIF state_machine_un12_clk_000_d0_n.BLIF inst_DS_000_DMA.BLIF \ -SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF RST_c.BLIF inst_A0_DMA.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF RESETDFFRHreg.BLIF SM_AMIGA_4_.BLIF \ -SM_AMIGA_3_.BLIF RW_c.BLIF SM_AMIGA_1_.BLIF un1_DSACK1_INT_0_sqmuxa_3.BLIF \ -fc_c_0__n.BLIF fc_c_1__n.BLIF state_machine_un10_bg_030_n.BLIF \ -state_machine_lds_000_int_7_n.BLIF state_machine_uds_000_int_7_n.BLIF \ -AMIGA_BUS_DATA_DIR_c.BLIF state_machine_un6_bgack_000_0_n.BLIF N_194_0.BLIF \ -N_119_i.BLIF N_120_i.BLIF N_197_0.BLIF state_machine_ds_000_dma_3_0_n.BLIF \ -N_171_i.BLIF state_machine_size_dma_4_0_1__n.BLIF N_130_i.BLIF N_131_i.BLIF \ -CLK_OUT_PRE_25_0.BLIF N_132_i.BLIF N_133_i.BLIF N_134_i.BLIF \ -sm_amiga_ns_0_5__n.BLIF N_135_i.BLIF N_139_i.BLIF cpu_est_0_.BLIF N_140_i.BLIF \ -cpu_est_1_.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF cpu_est_2_.BLIF N_141_i.BLIF \ -cpu_est_3_reg.BLIF N_52_i.BLIF N_143_i.BLIF N_142_i.BLIF \ -state_machine_rw_000_int_7_iv_i_n.BLIF cpu_est_ns_1__n.BLIF N_62_0.BLIF \ -cpu_est_ns_2__n.BLIF N_161_i.BLIF N_193.BLIF N_155_i.BLIF N_196.BLIF \ -N_63_0.BLIF N_28.BLIF N_66_i.BLIF N_30.BLIF N_76_i.BLIF N_55.BLIF \ -CLK_000_D1_i.BLIF N_62.BLIF N_77_i.BLIF N_63.BLIF N_79_0.BLIF N_66.BLIF \ -N_199_0.BLIF N_67.BLIF sm_amiga_i_2__n.BLIF N_69.BLIF N_201_0.BLIF N_70.BLIF \ -N_203_0.BLIF N_71.BLIF cpu_est_ns_0_1__n.BLIF N_75.BLIF N_167_i.BLIF N_76.BLIF \ -N_170_i.BLIF N_77.BLIF N_136_i.BLIF N_79.BLIF N_137_i.BLIF N_90.BLIF \ -N_202_0.BLIF N_200.BLIF N_200_0.BLIF N_202.BLIF N_169_i.BLIF N_204.BLIF \ -N_198_0.BLIF N_114.BLIF N_168_i.BLIF N_115.BLIF \ -un1_DSACK1_INT_0_sqmuxa_3_0.BLIF N_116.BLIF N_90_i.BLIF N_117.BLIF \ -AS_030_c_i.BLIF N_118.BLIF N_75_i.BLIF N_120.BLIF N_71_i.BLIF N_121.BLIF \ -N_69_i.BLIF N_122.BLIF N_67_i.BLIF N_124.BLIF N_150_i.BLIF N_125.BLIF \ -N_151_i.BLIF N_128.BLIF N_129.BLIF N_145_i.BLIF N_132.BLIF N_146_i.BLIF \ -N_136.BLIF N_147_i.BLIF N_137.BLIF cpu_est_ns_0_2__n.BLIF N_138.BLIF \ -N_144_i.BLIF N_140.BLIF N_55_0.BLIF N_142.BLIF N_138_i.BLIF N_144.BLIF \ -N_172_i.BLIF N_145.BLIF N_149_i.BLIF N_146.BLIF N_129_i.BLIF N_147.BLIF \ -N_148.BLIF N_128_i.BLIF N_150.BLIF sm_amiga_ns_0_0__n.BLIF N_151.BLIF \ -N_70_i.BLIF N_155.BLIF N_124_i.BLIF N_166.BLIF \ -state_machine_lds_000_int_7_0_n.BLIF N_167.BLIF \ -state_machine_uds_000_int_7_0_n.BLIF N_168.BLIF N_122_i.BLIF N_169.BLIF \ -N_30_0.BLIF N_170.BLIF N_121_i.BLIF N_172.BLIF N_28_0.BLIF N_220.BLIF \ -N_117_i.BLIF N_230.BLIF N_118_i.BLIF N_133.BLIF N_196_0.BLIF N_143.BLIF \ -N_116_i.BLIF N_143_2.BLIF N_195_i.BLIF N_203.BLIF BG_030_c_i.BLIF N_201.BLIF \ -N_115_i.BLIF N_199.BLIF state_machine_un10_bg_030_0_n.BLIF N_161.BLIF \ -N_193_0.BLIF N_141.BLIF N_204_i.BLIF N_139.BLIF \ -state_machine_un10_clk_000_d0_i_n.BLIF N_135.BLIF \ -state_machine_un12_clk_000_d0_0_n.BLIF N_134.BLIF N_69_i_1.BLIF N_131.BLIF \ -N_76_i_1.BLIF N_130.BLIF N_76_i_2.BLIF N_171.BLIF N_76_i_3.BLIF \ -state_machine_ds_000_dma_3_n.BLIF N_76_i_4.BLIF N_197.BLIF N_76_i_5.BLIF \ -N_119.BLIF N_220_1.BLIF N_194.BLIF N_220_2.BLIF \ -state_machine_un6_bgack_000_n.BLIF N_230_1.BLIF N_143_2_i.BLIF N_230_2.BLIF \ -a_i_18__n.BLIF N_230_3.BLIF a_i_16__n.BLIF N_230_4.BLIF a_i_19__n.BLIF \ -N_230_5.BLIF sm_amiga_i_4__n.BLIF N_230_6.BLIF sm_amiga_i_5__n.BLIF \ -cpu_est_ns_0_1_1__n.BLIF sm_amiga_i_3__n.BLIF cpu_est_ns_0_2_1__n.BLIF \ -CLK_000_D0_i.BLIF N_122_1.BLIF sm_amiga_i_0__n.BLIF N_122_2.BLIF \ -sm_amiga_i_1__n.BLIF N_122_3.BLIF RW_i.BLIF N_115_1.BLIF CLK_030_H_i.BLIF \ -N_115_2.BLIF CLK_030_i.BLIF state_machine_un10_clk_000_d0_1_n.BLIF \ -DTACK_D0_i.BLIF state_machine_un10_clk_000_d0_2_n.BLIF BGACK_030_INT_i.BLIF \ -N_133_1.BLIF AS_000_i.BLIF N_133_2.BLIF UDS_000_i.BLIF N_143_1.BLIF \ -LDS_000_i.BLIF cpu_est_ns_0_1_2__n.BLIF RW_000_i.BLIF N_55_0_1.BLIF \ -sm_amiga_i_6__n.BLIF state_machine_lds_000_int_7_0_1_n.BLIF \ -cpu_est_i_3__n.BLIF state_machine_uds_000_int_7_0_1_n.BLIF \ -sm_amiga_i_7__n.BLIF N_196_0_1.BLIF CLK_000_D2_i.BLIF N_155_1.BLIF \ -cpu_est_i_1__n.BLIF N_148_1.BLIF cpu_est_i_0__n.BLIF N_142_1.BLIF \ -VMA_INT_i.BLIF N_140_1.BLIF VPA_D_i.BLIF N_132_1.BLIF AS_000_DMA_i.BLIF \ -N_124_1.BLIF nEXP_SPACE_i.BLIF state_machine_a0_dma_2_1_n.BLIF \ -cpu_est_i_2__n.BLIF N_120_1.BLIF A0_i.BLIF N_118_1.BLIF size_i_1__n.BLIF \ -N_117_1.BLIF DS_030_i.BLIF N_116_1.BLIF AS_030_000_SYNC_i.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF a_i_30__n.BLIF N_204_1.BLIF \ -a_i_31__n.BLIF bgack_030_int_0_un3_n.BLIF a_i_28__n.BLIF \ -bgack_030_int_0_un1_n.BLIF a_i_29__n.BLIF bgack_030_int_0_un0_n.BLIF \ -a_i_26__n.BLIF as_000_dma_0_un3_n.BLIF a_i_27__n.BLIF as_000_dma_0_un1_n.BLIF \ -a_i_24__n.BLIF as_000_dma_0_un0_n.BLIF a_i_25__n.BLIF ds_000_dma_0_un3_n.BLIF \ -RST_i.BLIF ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF \ -clk_030_h_0_un3_n.BLIF N_114_i.BLIF clk_030_h_0_un1_n.BLIF FPU_CS_INT_i.BLIF \ -clk_030_h_0_un0_n.BLIF CLK_OUT_PRE_50_D_i.BLIF rw_000_int_0_un3_n.BLIF \ -AS_030_c.BLIF rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF AS_000_c.BLIF \ -state_machine_uds_000_int_7_0_m3_un3_n.BLIF \ -state_machine_uds_000_int_7_0_m3_un1_n.BLIF RW_000_c.BLIF \ -state_machine_uds_000_int_7_0_m3_un0_n.BLIF ipl_030_0_0__un3_n.BLIF \ -DS_030_c.BLIF ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF UDS_000_c.BLIF \ -ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF LDS_000_c.BLIF \ -ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF size_c_0__n.BLIF \ -ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF size_c_1__n.BLIF \ -cpu_estse_0_un3_n.BLIF cpu_estse_0_un1_n.BLIF a_c_16__n.BLIF \ -cpu_estse_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF a_c_17__n.BLIF \ -cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF a_c_18__n.BLIF \ -cpu_estse_2_un3_n.BLIF cpu_estse_2_un1_n.BLIF a_c_19__n.BLIF \ -cpu_estse_2_un0_n.BLIF as_030_000_sync_0_un3_n.BLIF a_c_20__n.BLIF \ -as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF a_c_21__n.BLIF \ -uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF a_c_22__n.BLIF \ -uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF a_c_23__n.BLIF \ -lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_c_24__n.BLIF \ -fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF a_c_25__n.BLIF \ -fpu_cs_int_0_un0_n.BLIF avec_exp_0_un3_n.BLIF a_c_26__n.BLIF \ -avec_exp_0_un1_n.BLIF avec_exp_0_un0_n.BLIF a_c_27__n.BLIF bg_000_0_un3_n.BLIF \ -bg_000_0_un1_n.BLIF a_c_28__n.BLIF bg_000_0_un0_n.BLIF as_000_int_0_un3_n.BLIF \ -a_c_29__n.BLIF as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF a_c_30__n.BLIF \ -dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF a_c_31__n.BLIF \ -dsack1_int_0_un0_n.BLIF vma_int_0_un3_n.BLIF A0_c.BLIF vma_int_0_un1_n.BLIF \ -vma_int_0_un0_n.BLIF nEXP_SPACE_c.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ -RW_000.PIN.BLIF DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ -SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF \ -RW.PIN.BLIF +DSACK1.BLIF DTACK.BLIF RW.BLIF SIZE_0_.BLIF a_c_28__n.BLIF a_c_29__n.BLIF \ +a_c_30__n.BLIF inst_BGACK_030_INTreg.BLIF a_c_31__n.BLIF \ +inst_FPU_CS_INTreg.BLIF inst_avec_expreg.BLIF A0_c.BLIF inst_VMA_INTreg.BLIF \ +inst_AS_030_000_SYNC.BLIF nEXP_SPACE_c.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_AS_000_DMA.BLIF inst_VPA_D.BLIF BG_030_c.BLIF inst_CLK_OUT_PRE_50_D.BLIF \ +inst_CLK_000_D0.BLIF BG_000DFFSHreg.BLIF inst_CLK_000_D1.BLIF \ +inst_DTACK_D0.BLIF inst_CLK_OUT_PRE_50.BLIF BGACK_000_c.BLIF \ +inst_CLK_OUT_PRE_25.BLIF SM_AMIGA_1_.BLIF CLK_030_c.BLIF vcc_n_n.BLIF \ +gnd_n_n.BLIF CLK_000_c.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF \ +CLK_OSZI_c.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.BLIF inst_RW_000_INT.BLIF \ +CLK_OUT_INTreg.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \ +inst_DSACK1_INT.BLIF IPL_030DFFSH_0_reg.BLIF \ +state_machine_un3_clk_out_pre_50_n.BLIF inst_CLK_000_D2.BLIF \ +IPL_030DFFSH_1_reg.BLIF inst_CLK_030_H.BLIF inst_DS_000_DMA.BLIF \ +IPL_030DFFSH_2_reg.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF ipl_c_0__n.BLIF \ +inst_A0_DMA.BLIF SM_AMIGA_5_.BLIF ipl_c_1__n.BLIF SM_AMIGA_4_.BLIF \ +SM_AMIGA_3_.BLIF ipl_c_2__n.BLIF SM_AMIGA_2_.BLIF DSACK1_c.BLIF RST_c.BLIF \ +RESETDFFRHreg.BLIF RW_c.BLIF fc_c_0__n.BLIF CLK_OUT_PRE_25_0.BLIF \ +fc_c_1__n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF cpu_est_0_.BLIF \ +state_machine_un3_clk_000_d1_i_n.BLIF cpu_est_1_.BLIF \ +state_machine_un6_bgack_000_0_n.BLIF cpu_est_2_.BLIF cpu_est_ns_0_1__n.BLIF \ +cpu_est_3_reg.BLIF N_159_i.BLIF cpu_estse.BLIF N_158_i.BLIF N_149_i.BLIF \ +N_150_i.BLIF N_153_i.BLIF AS_000_DMA_0_sqmuxa.BLIF N_152_i.BLIF \ +state_machine_un8_bgack_030_int_n.BLIF N_160_i.BLIF N_92.BLIF N_154_i.BLIF \ +state_machine_un49_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \ +N_210.BLIF N_156_i.BLIF N_220.BLIF N_157_i.BLIF CLK_030_H_1_sqmuxa.BLIF \ +cpu_est_ns_0_2__n.BLIF AS_000_DMA_1_sqmuxa.BLIF \ +state_machine_un10_clk_000_d0_i_n.BLIF DS_000_DMA_1_sqmuxa.BLIF \ +state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un24_bgack_030_int_n.BLIF \ +FPU_CS_INT_1_sqmuxa_i.BLIF state_machine_clk_030_h_2_n.BLIF \ +un1_as_030_000_sync8_1_0.BLIF state_machine_clk_030_h_2_f1_n.BLIF \ +AS_030_000_SYNC_0_sqmuxa_2_i.BLIF state_machine_ds_000_dma_3_n.BLIF \ +un1_as_030_000_sync8_0.BLIF N_87.BLIF un1_SM_AMIGA_12_0.BLIF N_93.BLIF \ +state_machine_un3_clk_030_i_n.BLIF N_94.BLIF \ +state_machine_un57_clk_000_d0_i_n.BLIF N_88.BLIF \ +state_machine_un51_clk_000_d0_i_n.BLIF N_90.BLIF \ +state_machine_un53_clk_000_d0_0_n.BLIF N_164_1.BLIF \ +state_machine_un3_bgack_030_int_d_i_n.BLIF \ +state_machine_un10_bgack_030_int_n.BLIF un1_bgack_030_int_d_0.BLIF \ +UDS_000_INT_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \ +UDS_000_INT_0_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF \ +state_machine_un25_clk_000_d0_n.BLIF N_86_0.BLIF N_164.BLIF N_101_i.BLIF \ +RW_li_m.BLIF N_85_i.BLIF N_181.BLIF N_84_0.BLIF RW_000_i_m.BLIF N_97_i.BLIF \ +N_163.BLIF un1_SM_AMIGA_8.BLIF N_96_i.BLIF N_100.BLIF N_95_i.BLIF N_91.BLIF \ +sm_amiga_ns_0_5__n.BLIF state_machine_un31_bgack_030_int_n.BLIF N_88_i.BLIF \ +state_machine_lds_000_int_7_n.BLIF N_89_i.BLIF \ +state_machine_uds_000_int_7_n.BLIF sm_amiga_ns_0_0__n.BLIF \ +RW_000_INT_0_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF \ +un1_AS_030_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF N_59.BLIF \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF un1_bgack_030_int_d.BLIF \ +BG_030_c_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \ +state_machine_un8_bg_030_i_n.BLIF state_machine_un10_bg_030_n.BLIF \ +state_machine_un10_bg_030_0_n.BLIF state_machine_un3_bgack_030_int_d_n.BLIF \ +state_machine_un5_bgack_030_int_d_i_n.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF \ +N_59_0.BLIF N_86.BLIF state_machine_un10_bgack_030_int_0_n.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF N_181_i.BLIF N_84.BLIF A0_c_i.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF state_machine_uds_000_int_7_0_n.BLIF \ +state_machine_un8_bg_030_n.BLIF state_machine_lds_000_int_7_0_n.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF state_machine_size_dma_4_0_0__n.BLIF \ +N_89.BLIF state_machine_size_dma_4_0_1__n.BLIF N_95.BLIF N_91_i.BLIF N_96.BLIF \ +N_97.BLIF N_100_i.BLIF N_99.BLIF un1_SM_AMIGA_8_0.BLIF \ +state_machine_un28_clk_000_d1_n.BLIF N_164_i.BLIF N_101.BLIF N_163_i.BLIF \ +un1_SM_AMIGA_12.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF AS_030_000_SYNC_1_sqmuxa.BLIF \ +RW_000_i_m_i.BLIF un1_as_030_000_sync8_1.BLIF RW_li_m_i.BLIF \ +AS_000_INT_1_sqmuxa.BLIF state_machine_rw_000_int_7_iv_i_n.BLIF \ +DSACK1_INT_1_sqmuxa.BLIF size_c_i_1__n.BLIF \ +state_machine_un10_clk_000_d0_n.BLIF state_machine_un25_clk_000_d0_i_n.BLIF \ +state_machine_un12_clk_000_d0_n.BLIF N_90_i.BLIF \ +state_machine_un51_clk_000_d0_n.BLIF state_machine_un53_clk_000_d0_n.BLIF \ +N_94_i.BLIF state_machine_un57_clk_000_d0_n.BLIF N_93_i.BLIF \ +AS_030_000_SYNC_0_sqmuxa_2.BLIF sm_amiga_ns_0_4__n.BLIF \ +AS_030_000_SYNC_0_sqmuxa.BLIF N_87_0.BLIF state_machine_un3_clk_030_n.BLIF \ +state_machine_ds_000_dma_3_0_n.BLIF FPU_CS_INT_1_sqmuxa.BLIF CLK_030_H_i.BLIF \ +state_machine_un28_clk_030_n.BLIF CLK_030_H_1_sqmuxa_i.BLIF \ +un1_as_030_000_sync8.BLIF state_machine_clk_030_h_2_f1_0_n.BLIF N_150.BLIF \ +un3_dtack_i.BLIF state_machine_un5_clk_000_d0_n.BLIF N_92_i.BLIF \ +state_machine_un3_clk_000_d1_n.BLIF cpu_est_ns_2__n.BLIF un3_dtack_i_1.BLIF \ +N_157.BLIF state_machine_un25_clk_000_d0_i_1_n.BLIF N_156.BLIF \ +cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_n.BLIF N_210_1.BLIF \ +N_154.BLIF N_210_2.BLIF N_160.BLIF N_220_1.BLIF N_152.BLIF N_220_2.BLIF \ +N_153.BLIF N_220_3.BLIF N_158.BLIF N_220_4.BLIF N_159.BLIF N_220_5.BLIF \ +cpu_est_ns_1__n.BLIF N_220_6.BLIF state_machine_un6_bgack_000_n.BLIF \ +DS_000_DMA_1_sqmuxa_1.BLIF AS_030_000_SYNC_i.BLIF \ +UDS_000_INT_0_sqmuxa_1_1.BLIF CLK_000_D1_i.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ +cpu_est_i_3__n.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF cpu_est_i_2__n.BLIF \ +UDS_000_INT_0_sqmuxa_2.BLIF cpu_est_i_1__n.BLIF N_164_1_0.BLIF \ +cpu_est_i_0__n.BLIF RW_li_m_1.BLIF VPA_D_i.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF CLK_000_D0_i.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF state_machine_un28_clk_030_i_n.BLIF \ +N_101_1.BLIF VMA_INT_i.BLIF un1_bgack_030_int_d_0_1.BLIF AS_030_i.BLIF \ +state_machine_un8_bg_030_1_n.BLIF AS_030_000_SYNC_0_sqmuxa_i.BLIF \ +state_machine_un8_bg_030_2_n.BLIF sm_amiga_i_1__n.BLIF \ +state_machine_un57_clk_000_d0_1_n.BLIF DTACK_D0_i.BLIF \ +state_machine_un49_clk_000_d0_1_n.BLIF a_i_19__n.BLIF \ +AS_030_000_SYNC_0_sqmuxa_1.BLIF a_i_16__n.BLIF \ +AS_030_000_SYNC_0_sqmuxa_2_0.BLIF a_i_18__n.BLIF \ +state_machine_un28_clk_030_1_n.BLIF state_machine_un5_clk_000_d0_i_0_n.BLIF \ +state_machine_un28_clk_030_2_n.BLIF nEXP_SPACE_i.BLIF \ +state_machine_un28_clk_030_3_n.BLIF sm_amiga_i_7__n.BLIF \ +state_machine_un28_clk_030_4_n.BLIF sm_amiga_i_0__n.BLIF \ +state_machine_un28_clk_030_5_n.BLIF N_99_i.BLIF \ +state_machine_un5_clk_000_d0_1_n.BLIF sm_amiga_i_2__n.BLIF \ +state_machine_un5_clk_000_d0_2_n.BLIF BGACK_030_INT_i.BLIF \ +state_machine_un10_clk_000_d0_1_n.BLIF BGACK_030_INT_D_i.BLIF \ +state_machine_un10_clk_000_d0_2_0_n.BLIF sm_amiga_i_6__n.BLIF \ +state_machine_un10_clk_000_d0_3_n.BLIF UDS_000_i.BLIF cpu_est_ns_0_1_1__n.BLIF \ +LDS_000_i.BLIF cpu_est_ns_0_2_1__n.BLIF AS_000_DMA_0_sqmuxa_i.BLIF \ +state_machine_un28_clk_000_d1_1_n.BLIF \ +state_machine_un8_bgack_030_int_i_n.BLIF cpu_estse_2_un3_n.BLIF \ +state_machine_un31_bgack_030_int_i_n.BLIF cpu_estse_2_un1_n.BLIF \ +sm_amiga_i_5__n.BLIF cpu_estse_2_un0_n.BLIF RW_i.BLIF cpu_estse_1_un3_n.BLIF \ +RW_000_i.BLIF cpu_estse_1_un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \ +cpu_estse_1_un0_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF cpu_estse_0_un3_n.BLIF \ +AS_000_i.BLIF cpu_estse_0_un1_n.BLIF DS_030_i.BLIF cpu_estse_0_un0_n.BLIF \ +state_machine_un49_clk_000_d0_i_n.BLIF ipl_030_0_2__un3_n.BLIF CLK_030_i.BLIF \ +ipl_030_0_2__un1_n.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \ +ipl_030_0_2__un0_n.BLIF AS_000_DMA_i.BLIF ipl_030_0_1__un3_n.BLIF \ +sm_amiga_i_4__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_30__n.BLIF \ +ipl_030_0_1__un0_n.BLIF a_i_31__n.BLIF ipl_030_0_0__un3_n.BLIF a_i_28__n.BLIF \ +ipl_030_0_0__un1_n.BLIF a_i_29__n.BLIF ipl_030_0_0__un0_n.BLIF a_i_26__n.BLIF \ +bgack_030_int_0_un3_n.BLIF a_i_27__n.BLIF bgack_030_int_0_un1_n.BLIF \ +a_i_24__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_25__n.BLIF \ +as_030_000_sync_0_un3_n.BLIF RST_i.BLIF as_030_000_sync_0_un1_n.BLIF \ +as_030_000_sync_0_un0_n.BLIF FPU_CS_INT_i.BLIF fpu_cs_int_0_un3_n.BLIF \ +CLK_OUT_PRE_50_D_i.BLIF fpu_cs_int_0_un1_n.BLIF AS_030_c.BLIF \ +fpu_cs_int_0_un0_n.BLIF as_000_int_0_un3_n.BLIF AS_000_c.BLIF \ +as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF RW_000_c.BLIF \ +dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF DS_030_c.BLIF \ +dsack1_int_0_un0_n.BLIF vma_int_0_un3_n.BLIF UDS_000_c.BLIF \ +vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF LDS_000_c.BLIF avec_exp_0_un3_n.BLIF \ +avec_exp_0_un1_n.BLIF size_c_0__n.BLIF avec_exp_0_un0_n.BLIF \ +bg_000_0_un3_n.BLIF size_c_1__n.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF \ +a_c_16__n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF \ +a_c_17__n.BLIF lds_000_int_0_un0_n.BLIF uds_000_int_0_un3_n.BLIF \ +a_c_18__n.BLIF uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF \ +a_c_19__n.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un1_n.BLIF a_c_20__n.BLIF \ +rw_000_int_0_un0_n.BLIF as_000_dma_0_un3_n.BLIF a_c_21__n.BLIF \ +as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF a_c_22__n.BLIF \ +ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un1_n.BLIF a_c_23__n.BLIF \ +ds_000_dma_0_un0_n.BLIF clk_030_h_0_un3_n.BLIF a_c_24__n.BLIF \ +clk_030_h_0_un1_n.BLIF clk_030_h_0_un0_n.BLIF a_c_25__n.BLIF a_c_26__n.BLIF \ +a_c_27__n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF DS_030.PIN.BLIF \ +UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ +A0.PIN.BLIF DSACK1.PIN.BLIF DTACK.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -CIIN IPL_030_1_ IPL_030_0_ cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \ -cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C \ -cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR SM_AMIGA_0_.D \ -SM_AMIGA_0_.C SM_AMIGA_0_.AR SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP \ -IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ -IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ -IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D \ -SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ -SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \ -SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \ -SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ -inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_VMA_INTreg.D \ -inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D \ -inst_CLK_OUT_PRE_25.C inst_CLK_OUT_PRE_25.AR SIZE_DMA_0_.D SIZE_DMA_0_.C \ -SIZE_DMA_0_.AP inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP \ -inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \ -inst_avec_expreg.D inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D \ -BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C \ -inst_DS_000_DMA.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \ -inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_000_INT.AP inst_RW_000_INT.D \ -inst_RW_000_INT.C inst_RW_000_INT.AP inst_AS_030_000_SYNC.D \ -inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_CLK_030_H.D \ -inst_CLK_030_H.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP \ -inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_DTACK_D0.D inst_DTACK_D0.C \ -inst_DTACK_D0.AP inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP \ -CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_000_D3.D \ -inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_CLK_000_D1.D inst_CLK_000_D1.C \ -inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C \ -inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D inst_CLK_OUT_PRE_50_D.C \ -inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D inst_CLK_000_D0.C \ -inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \ +CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR \ +cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C \ +cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR IPL_030DFFSH_0_reg.D \ +IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ +IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ +IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ +SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \ +SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \ +SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \ +SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \ +SM_AMIGA_0_.C SM_AMIGA_0_.AR inst_VMA_INTreg.D inst_VMA_INTreg.C \ +inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ +inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C \ +inst_CLK_OUT_PRE_25.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP \ +SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP inst_LDS_000_INT.D \ +inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_FPU_CS_INTreg.D \ +inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_avec_expreg.D \ +inst_avec_expreg.C inst_avec_expreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ +BG_000DFFSHreg.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP \ +inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP inst_AS_000_INT.D \ +inst_AS_000_INT.C inst_AS_000_INT.AP inst_DSACK1_INT.D inst_DSACK1_INT.C \ +inst_DSACK1_INT.AP inst_RW_000_INT.D inst_RW_000_INT.C inst_RW_000_INT.AP \ +inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ +inst_CLK_030_H.D inst_CLK_030_H.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ +inst_UDS_000_INT.AP inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP inst_DTACK_D0.D \ +inst_DTACK_D0.C inst_DTACK_D0.AP inst_CLK_000_D2.D inst_CLK_000_D2.C \ +inst_CLK_000_D2.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR \ +inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP inst_BGACK_030_INT_D.D \ +inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_OUT_PRE_50_D.D \ +inst_CLK_OUT_PRE_50_D.C inst_CLK_OUT_PRE_50_D.AR inst_CLK_000_D0.D \ +inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \ inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C inst_CLK_OUT_PRE_50.AR \ RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR SIZE_1_ AS_030 AS_000 RW_000 \ -DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ BG_030_c BGACK_000_c \ -CLK_030_c CLK_000_c CLK_OSZI_c vcc_n_n gnd_n_n state_machine_un10_clk_000_d0_n \ -ipl_c_0__n ipl_c_1__n ipl_c_2__n DSACK1_c state_machine_un3_clk_out_pre_50_n \ -state_machine_un12_clk_000_d0_n RST_c AMIGA_BUS_ENABLE_INT_2_sqmuxa RW_c \ -un1_DSACK1_INT_0_sqmuxa_3 fc_c_0__n fc_c_1__n state_machine_un10_bg_030_n \ -state_machine_lds_000_int_7_n state_machine_uds_000_int_7_n \ -AMIGA_BUS_DATA_DIR_c state_machine_un6_bgack_000_0_n N_194_0 N_119_i N_120_i \ -N_197_0 state_machine_ds_000_dma_3_0_n N_171_i state_machine_size_dma_4_0_1__n \ -N_130_i N_131_i N_132_i N_133_i N_134_i sm_amiga_ns_0_5__n N_135_i N_139_i \ -N_140_i AMIGA_BUS_DATA_DIR_c_0 N_141_i N_52_i N_143_i N_142_i \ -state_machine_rw_000_int_7_iv_i_n cpu_est_ns_1__n N_62_0 cpu_est_ns_2__n \ -N_161_i N_193 N_155_i N_196 N_63_0 N_28 N_66_i N_30 N_76_i N_55 CLK_000_D1_i \ -N_62 N_77_i N_63 N_79_0 N_66 N_199_0 N_67 sm_amiga_i_2__n N_69 N_201_0 N_70 \ -N_203_0 N_71 cpu_est_ns_0_1__n N_75 N_167_i N_76 N_170_i N_77 N_136_i N_79 \ -N_137_i N_90 N_202_0 N_200 N_200_0 N_202 N_169_i N_204 N_198_0 N_114 N_168_i \ -N_115 un1_DSACK1_INT_0_sqmuxa_3_0 N_116 N_90_i N_117 AS_030_c_i N_118 N_75_i \ -N_120 N_71_i N_121 N_69_i N_122 N_67_i N_124 N_150_i N_125 N_151_i N_128 N_129 \ -N_145_i N_132 N_146_i N_136 N_147_i N_137 cpu_est_ns_0_2__n N_138 N_144_i \ -N_140 N_55_0 N_142 N_138_i N_144 N_172_i N_145 N_149_i N_146 N_129_i N_147 \ -N_148 N_128_i N_150 sm_amiga_ns_0_0__n N_151 N_70_i N_155 N_124_i N_166 \ -state_machine_lds_000_int_7_0_n N_167 state_machine_uds_000_int_7_0_n N_168 \ -N_122_i N_169 N_30_0 N_170 N_121_i N_172 N_28_0 N_220 N_117_i N_230 N_118_i \ -N_133 N_196_0 N_143 N_116_i N_143_2 N_195_i N_203 BG_030_c_i N_201 N_115_i \ -N_199 state_machine_un10_bg_030_0_n N_161 N_193_0 N_141 N_204_i N_139 \ -state_machine_un10_clk_000_d0_i_n N_135 state_machine_un12_clk_000_d0_0_n \ -N_134 N_69_i_1 N_131 N_76_i_1 N_130 N_76_i_2 N_171 N_76_i_3 \ -state_machine_ds_000_dma_3_n N_76_i_4 N_197 N_76_i_5 N_119 N_220_1 N_194 \ -N_220_2 state_machine_un6_bgack_000_n N_230_1 N_143_2_i N_230_2 a_i_18__n \ -N_230_3 a_i_16__n N_230_4 a_i_19__n N_230_5 sm_amiga_i_4__n N_230_6 \ -sm_amiga_i_5__n cpu_est_ns_0_1_1__n sm_amiga_i_3__n cpu_est_ns_0_2_1__n \ -CLK_000_D0_i N_122_1 sm_amiga_i_0__n N_122_2 sm_amiga_i_1__n N_122_3 RW_i \ -N_115_1 CLK_030_H_i N_115_2 CLK_030_i state_machine_un10_clk_000_d0_1_n \ -DTACK_D0_i state_machine_un10_clk_000_d0_2_n BGACK_030_INT_i N_133_1 AS_000_i \ -N_133_2 UDS_000_i N_143_1 LDS_000_i cpu_est_ns_0_1_2__n RW_000_i N_55_0_1 \ -sm_amiga_i_6__n state_machine_lds_000_int_7_0_1_n cpu_est_i_3__n \ -state_machine_uds_000_int_7_0_1_n sm_amiga_i_7__n N_196_0_1 CLK_000_D2_i \ -N_155_1 cpu_est_i_1__n N_148_1 cpu_est_i_0__n N_142_1 VMA_INT_i N_140_1 \ -VPA_D_i N_132_1 AS_000_DMA_i N_124_1 nEXP_SPACE_i state_machine_a0_dma_2_1_n \ -cpu_est_i_2__n N_120_1 A0_i N_118_1 size_i_1__n N_117_1 DS_030_i N_116_1 \ -AS_030_000_SYNC_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 a_i_30__n N_204_1 a_i_31__n \ -bgack_030_int_0_un3_n a_i_28__n bgack_030_int_0_un1_n a_i_29__n \ -bgack_030_int_0_un0_n a_i_26__n as_000_dma_0_un3_n a_i_27__n \ -as_000_dma_0_un1_n a_i_24__n as_000_dma_0_un0_n a_i_25__n ds_000_dma_0_un3_n \ -RST_i ds_000_dma_0_un1_n ds_000_dma_0_un0_n clk_030_h_0_un3_n N_114_i \ -clk_030_h_0_un1_n FPU_CS_INT_i clk_030_h_0_un0_n CLK_OUT_PRE_50_D_i \ -rw_000_int_0_un3_n AS_030_c rw_000_int_0_un1_n rw_000_int_0_un0_n AS_000_c \ -state_machine_uds_000_int_7_0_m3_un3_n state_machine_uds_000_int_7_0_m3_un1_n \ -RW_000_c state_machine_uds_000_int_7_0_m3_un0_n ipl_030_0_0__un3_n DS_030_c \ -ipl_030_0_0__un1_n ipl_030_0_0__un0_n UDS_000_c ipl_030_0_1__un3_n \ -ipl_030_0_1__un1_n LDS_000_c ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n \ -ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n cpu_estse_0_un3_n \ -cpu_estse_0_un1_n a_c_16__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_17__n \ -cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_18__n cpu_estse_2_un3_n \ -cpu_estse_2_un1_n a_c_19__n cpu_estse_2_un0_n as_030_000_sync_0_un3_n \ -a_c_20__n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n a_c_21__n \ -uds_000_int_0_un3_n uds_000_int_0_un1_n a_c_22__n uds_000_int_0_un0_n \ -lds_000_int_0_un3_n a_c_23__n lds_000_int_0_un1_n lds_000_int_0_un0_n \ -a_c_24__n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n a_c_25__n fpu_cs_int_0_un0_n \ -avec_exp_0_un3_n a_c_26__n avec_exp_0_un1_n avec_exp_0_un0_n a_c_27__n \ -bg_000_0_un3_n bg_000_0_un1_n a_c_28__n bg_000_0_un0_n as_000_int_0_un3_n \ -a_c_29__n as_000_int_0_un1_n as_000_int_0_un0_n a_c_30__n dsack1_int_0_un3_n \ -dsack1_int_0_un1_n a_c_31__n dsack1_int_0_un0_n vma_int_0_un3_n A0_c \ -vma_int_0_un1_n vma_int_0_un0_n nEXP_SPACE_c AS_030.OE AS_000.OE RW_000.OE \ -DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE \ -RW.OE BERR.OE CIIN.OE CLK_OUT_PRE_25_0 -.names N_150_i.BLIF N_151_i.BLIF cpu_est_0_.D -11 1 +DS_030 UDS_000 LDS_000 A0 DSACK1 DTACK RW SIZE_0_ a_c_28__n a_c_29__n \ +a_c_30__n a_c_31__n A0_c nEXP_SPACE_c BG_030_c BGACK_000_c CLK_030_c vcc_n_n \ +gnd_n_n CLK_000_c CLK_OSZI_c state_machine_un3_clk_out_pre_50_n ipl_c_0__n \ +ipl_c_1__n ipl_c_2__n DSACK1_c RST_c RW_c fc_c_0__n fc_c_1__n \ +AMIGA_BUS_DATA_DIR_c state_machine_un3_clk_000_d1_i_n \ +state_machine_un6_bgack_000_0_n cpu_est_ns_0_1__n N_159_i N_158_i N_149_i \ +N_150_i N_153_i AS_000_DMA_0_sqmuxa N_152_i state_machine_un8_bgack_030_int_n \ +N_160_i N_92 N_154_i state_machine_un49_clk_000_d0_n \ +state_machine_un10_clk_000_d0_2_i_n N_210 N_156_i N_220 N_157_i \ +CLK_030_H_1_sqmuxa cpu_est_ns_0_2__n AS_000_DMA_1_sqmuxa \ +state_machine_un10_clk_000_d0_i_n DS_000_DMA_1_sqmuxa \ +state_machine_un12_clk_000_d0_0_n state_machine_un24_bgack_030_int_n \ +FPU_CS_INT_1_sqmuxa_i state_machine_clk_030_h_2_n un1_as_030_000_sync8_1_0 \ +state_machine_clk_030_h_2_f1_n AS_030_000_SYNC_0_sqmuxa_2_i \ +state_machine_ds_000_dma_3_n un1_as_030_000_sync8_0 N_87 un1_SM_AMIGA_12_0 \ +N_93 state_machine_un3_clk_030_i_n N_94 state_machine_un57_clk_000_d0_i_n N_88 \ +state_machine_un51_clk_000_d0_i_n N_90 state_machine_un53_clk_000_d0_0_n \ +N_164_1 state_machine_un3_bgack_030_int_d_i_n \ +state_machine_un10_bgack_030_int_n un1_bgack_030_int_d_0 \ +UDS_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_3_sqmuxa_i UDS_000_INT_0_sqmuxa \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i state_machine_un25_clk_000_d0_n N_86_0 N_164 \ +N_101_i RW_li_m N_85_i N_181 N_84_0 RW_000_i_m N_97_i N_163 un1_SM_AMIGA_8 \ +N_96_i N_100 N_95_i N_91 sm_amiga_ns_0_5__n state_machine_un31_bgack_030_int_n \ +N_88_i state_machine_lds_000_int_7_n N_89_i state_machine_uds_000_int_7_n \ +sm_amiga_ns_0_0__n RW_000_INT_0_sqmuxa_1 AMIGA_BUS_ENABLE_INT_2_sqmuxa_i \ +un1_AS_030_2 AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i N_59 \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 un1_bgack_030_int_d BG_030_c_i \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_un8_bg_030_i_n \ +state_machine_un10_bg_030_n state_machine_un10_bg_030_0_n \ +state_machine_un3_bgack_030_int_d_n state_machine_un5_bgack_030_int_d_i_n \ +AMIGA_BUS_ENABLE_INT_3_sqmuxa N_59_0 N_86 state_machine_un10_bgack_030_int_0_n \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 N_181_i N_84 A0_c_i \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 state_machine_uds_000_int_7_0_n \ +state_machine_un8_bg_030_n state_machine_lds_000_int_7_0_n \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa state_machine_size_dma_4_0_0__n N_89 \ +state_machine_size_dma_4_0_1__n N_95 N_91_i N_96 N_97 N_100_i N_99 \ +un1_SM_AMIGA_8_0 state_machine_un28_clk_000_d1_n N_164_i N_101 N_163_i \ +un1_SM_AMIGA_12 AMIGA_BUS_DATA_DIR_c_0 AS_030_000_SYNC_1_sqmuxa RW_000_i_m_i \ +un1_as_030_000_sync8_1 RW_li_m_i AS_000_INT_1_sqmuxa \ +state_machine_rw_000_int_7_iv_i_n DSACK1_INT_1_sqmuxa size_c_i_1__n \ +state_machine_un10_clk_000_d0_n state_machine_un25_clk_000_d0_i_n \ +state_machine_un12_clk_000_d0_n N_90_i state_machine_un51_clk_000_d0_n \ +state_machine_un53_clk_000_d0_n N_94_i state_machine_un57_clk_000_d0_n N_93_i \ +AS_030_000_SYNC_0_sqmuxa_2 sm_amiga_ns_0_4__n AS_030_000_SYNC_0_sqmuxa N_87_0 \ +state_machine_un3_clk_030_n state_machine_ds_000_dma_3_0_n FPU_CS_INT_1_sqmuxa \ +CLK_030_H_i state_machine_un28_clk_030_n CLK_030_H_1_sqmuxa_i \ +un1_as_030_000_sync8 state_machine_clk_030_h_2_f1_0_n N_150 un3_dtack_i \ +state_machine_un5_clk_000_d0_n N_92_i state_machine_un3_clk_000_d1_n \ +cpu_est_ns_2__n un3_dtack_i_1 N_157 state_machine_un25_clk_000_d0_i_1_n N_156 \ +cpu_est_ns_0_1_2__n state_machine_un10_clk_000_d0_2_n N_210_1 N_154 N_210_2 \ +N_160 N_220_1 N_152 N_220_2 N_153 N_220_3 N_158 N_220_4 N_159 N_220_5 \ +cpu_est_ns_1__n N_220_6 state_machine_un6_bgack_000_n DS_000_DMA_1_sqmuxa_1 \ +AS_030_000_SYNC_i UDS_000_INT_0_sqmuxa_1_1 CLK_000_D1_i \ +UDS_000_INT_0_sqmuxa_1_2 cpu_est_i_3__n UDS_000_INT_0_sqmuxa_1_0 \ +cpu_est_i_2__n UDS_000_INT_0_sqmuxa_2 cpu_est_i_1__n N_164_1_0 cpu_est_i_0__n \ +RW_li_m_1 VPA_D_i AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 CLK_000_D0_i \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 state_machine_un28_clk_030_i_n N_101_1 \ +VMA_INT_i un1_bgack_030_int_d_0_1 AS_030_i state_machine_un8_bg_030_1_n \ +AS_030_000_SYNC_0_sqmuxa_i state_machine_un8_bg_030_2_n sm_amiga_i_1__n \ +state_machine_un57_clk_000_d0_1_n DTACK_D0_i state_machine_un49_clk_000_d0_1_n \ +a_i_19__n AS_030_000_SYNC_0_sqmuxa_1 a_i_16__n AS_030_000_SYNC_0_sqmuxa_2_0 \ +a_i_18__n state_machine_un28_clk_030_1_n state_machine_un5_clk_000_d0_i_0_n \ +state_machine_un28_clk_030_2_n nEXP_SPACE_i state_machine_un28_clk_030_3_n \ +sm_amiga_i_7__n state_machine_un28_clk_030_4_n sm_amiga_i_0__n \ +state_machine_un28_clk_030_5_n N_99_i state_machine_un5_clk_000_d0_1_n \ +sm_amiga_i_2__n state_machine_un5_clk_000_d0_2_n BGACK_030_INT_i \ +state_machine_un10_clk_000_d0_1_n BGACK_030_INT_D_i \ +state_machine_un10_clk_000_d0_2_0_n sm_amiga_i_6__n \ +state_machine_un10_clk_000_d0_3_n UDS_000_i cpu_est_ns_0_1_1__n LDS_000_i \ +cpu_est_ns_0_2_1__n AS_000_DMA_0_sqmuxa_i state_machine_un28_clk_000_d1_1_n \ +state_machine_un8_bgack_030_int_i_n cpu_estse_2_un3_n \ +state_machine_un31_bgack_030_int_i_n cpu_estse_2_un1_n sm_amiga_i_5__n \ +cpu_estse_2_un0_n RW_i cpu_estse_1_un3_n RW_000_i cpu_estse_1_un1_n \ +UDS_000_INT_0_sqmuxa_i cpu_estse_1_un0_n UDS_000_INT_0_sqmuxa_1_i \ +cpu_estse_0_un3_n AS_000_i cpu_estse_0_un1_n DS_030_i cpu_estse_0_un0_n \ +state_machine_un49_clk_000_d0_i_n ipl_030_0_2__un3_n CLK_030_i \ +ipl_030_0_2__un1_n state_machine_un24_bgack_030_int_i_n ipl_030_0_2__un0_n \ +AS_000_DMA_i ipl_030_0_1__un3_n sm_amiga_i_4__n ipl_030_0_1__un1_n a_i_30__n \ +ipl_030_0_1__un0_n a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n \ +a_i_29__n ipl_030_0_0__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n \ +bgack_030_int_0_un1_n a_i_24__n bgack_030_int_0_un0_n a_i_25__n \ +as_030_000_sync_0_un3_n RST_i as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n \ +FPU_CS_INT_i fpu_cs_int_0_un3_n CLK_OUT_PRE_50_D_i fpu_cs_int_0_un1_n AS_030_c \ +fpu_cs_int_0_un0_n as_000_int_0_un3_n AS_000_c as_000_int_0_un1_n \ +as_000_int_0_un0_n RW_000_c dsack1_int_0_un3_n dsack1_int_0_un1_n DS_030_c \ +dsack1_int_0_un0_n vma_int_0_un3_n UDS_000_c vma_int_0_un1_n vma_int_0_un0_n \ +LDS_000_c avec_exp_0_un3_n avec_exp_0_un1_n size_c_0__n avec_exp_0_un0_n \ +bg_000_0_un3_n size_c_1__n bg_000_0_un1_n bg_000_0_un0_n a_c_16__n \ +lds_000_int_0_un3_n lds_000_int_0_un1_n a_c_17__n lds_000_int_0_un0_n \ +uds_000_int_0_un3_n a_c_18__n uds_000_int_0_un1_n uds_000_int_0_un0_n \ +a_c_19__n rw_000_int_0_un3_n rw_000_int_0_un1_n a_c_20__n rw_000_int_0_un0_n \ +as_000_dma_0_un3_n a_c_21__n as_000_dma_0_un1_n as_000_dma_0_un0_n a_c_22__n \ +ds_000_dma_0_un3_n ds_000_dma_0_un1_n a_c_23__n ds_000_dma_0_un0_n \ +clk_030_h_0_un3_n a_c_24__n clk_030_h_0_un1_n clk_030_h_0_un0_n a_c_25__n \ +a_c_26__n a_c_27__n AS_030.OE AS_000.OE RW_000.OE DS_030.OE UDS_000.OE \ +LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK1.OE DTACK.OE RW.OE BERR.OE \ +CIIN.OE CLK_OUT_PRE_25_0 cpu_estse .names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 @@ -306,10 +398,6 @@ RW.OE BERR.OE CIIN.OE CLK_OUT_PRE_25_0 .names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D 1- 1 -1 1 -.names CLK_000_D0_i.BLIF N_135_i.BLIF SM_AMIGA_0_.D -11 1 -.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D -0 1 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D 1- 1 -1 1 @@ -321,21 +409,20 @@ RW.OE BERR.OE CIIN.OE CLK_OUT_PRE_25_0 -1 1 .names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D 0 1 -.names N_129_i.BLIF N_198_0.BLIF SM_AMIGA_6_.D +.names N_88_i.BLIF N_90_i.BLIF SM_AMIGA_6_.D 11 1 -.names inst_CLK_000_D0.BLIF N_200.BLIF SM_AMIGA_5_.D +.names inst_CLK_000_D0.BLIF N_91_i.BLIF SM_AMIGA_5_.D 11 1 -.names CLK_000_D0_i.BLIF N_130_i.BLIF SM_AMIGA_4_.D -11 1 -.names N_131_i.BLIF N_132_i.BLIF SM_AMIGA_3_.D +.names CLK_000_D0_i.BLIF N_92_i.BLIF SM_AMIGA_4_.D 11 1 +.names sm_amiga_ns_0_4__n.BLIF SM_AMIGA_3_.D +0 1 .names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D 0 1 -.names inst_CLK_000_D0.BLIF N_201.BLIF SM_AMIGA_1_.D +.names inst_CLK_000_D0.BLIF N_97_i.BLIF SM_AMIGA_1_.D +11 1 +.names CLK_000_D0_i.BLIF N_86.BLIF SM_AMIGA_0_.D 11 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D -1- 1 --1 1 .names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 -1 1 @@ -343,7 +430,9 @@ RW.OE BERR.OE CIIN.OE CLK_OUT_PRE_25_0 inst_BGACK_030_INTreg.D 1- 1 -1 1 -.names N_125.BLIF SIZE_DMA_0_.D +.names state_machine_size_dma_4_0_0__n.BLIF SIZE_DMA_0_.D +0 1 +.names state_machine_size_dma_4_0_1__n.BLIF SIZE_DMA_1_.D 0 1 .names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D 1- 1 @@ -366,6 +455,9 @@ inst_BGACK_030_INTreg.D .names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D 1- 1 -1 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D +1- 1 +-1 1 .names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF inst_RW_000_INT.D 1- 1 -1 1 @@ -379,651 +471,675 @@ inst_AS_030_000_SYNC.D .names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D 1- 1 -1 1 -.names state_machine_a0_dma_2_1_n.BLIF N_166.BLIF inst_A0_DMA.D +.names UDS_000_c.BLIF state_machine_un8_bgack_030_int_n.BLIF inst_A0_DMA.D 11 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 .names vcc_n_n 1 .names gnd_n_n -.names state_machine_un10_clk_000_d0_1_n.BLIF \ -state_machine_un10_clk_000_d0_2_n.BLIF state_machine_un10_clk_000_d0_n -11 1 .names inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_50_D_i.BLIF \ state_machine_un3_clk_out_pre_50_n 11 1 -.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n -0 1 -.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF sm_amiga_i_7__n.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa -11 1 -.names un1_DSACK1_INT_0_sqmuxa_3_0.BLIF un1_DSACK1_INT_0_sqmuxa_3 -0 1 -.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n -0 1 -.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n -0 1 -.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n -0 1 .names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c 0 1 -.names BGACK_000_c.BLIF N_77.BLIF state_machine_un6_bgack_000_0_n +.names state_machine_un3_clk_000_d1_n.BLIF state_machine_un3_clk_000_d1_i_n +0 1 +.names BGACK_000_c.BLIF state_machine_un3_clk_000_d1_i_n.BLIF \ +state_machine_un6_bgack_000_0_n 11 1 -.names CLK_030_c.BLIF N_143_2.BLIF N_194_0 -11 1 -.names N_119.BLIF N_119_i -0 1 -.names N_120.BLIF N_120_i -0 1 -.names N_119_i.BLIF N_120_i.BLIF N_197_0 -11 1 -.names AS_000_DMA_i.BLIF N_143_2.BLIF state_machine_ds_000_dma_3_0_n -11 1 -.names N_171.BLIF N_171_i -0 1 -.names N_143_2.BLIF N_171_i.BLIF state_machine_size_dma_4_0_1__n -11 1 -.names N_130.BLIF N_130_i -0 1 -.names N_131.BLIF N_131_i -0 1 -.names N_132.BLIF N_132_i -0 1 -.names N_133.BLIF N_133_i -0 1 -.names N_134.BLIF N_134_i -0 1 -.names N_133_i.BLIF N_134_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names N_135.BLIF N_135_i -0 1 -.names N_139.BLIF N_139_i -0 1 -.names N_140.BLIF N_140_i -0 1 -.names N_139_i.BLIF N_140_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names N_141.BLIF N_141_i -0 1 -.names N_141_i.BLIF N_143_2.BLIF N_52_i -11 1 -.names N_143.BLIF N_143_i -0 1 -.names N_142.BLIF N_142_i -0 1 -.names N_142_i.BLIF N_143_i.BLIF state_machine_rw_000_int_7_iv_i_n -11 1 -.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n -0 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_62_0 -11 1 -.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n -0 1 -.names N_161.BLIF N_161_i -0 1 -.names N_193_0.BLIF N_193 -0 1 -.names N_155.BLIF N_155_i -0 1 -.names N_196_0.BLIF N_196 -0 1 -.names N_155_i.BLIF N_161_i.BLIF N_63_0 -11 1 -.names N_28_0.BLIF N_28 -0 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_66_i -11 1 -.names N_30_0.BLIF N_30 -0 1 -.names N_76_i_4.BLIF N_76_i_5.BLIF N_76_i -11 1 -.names N_55_0.BLIF N_55 -0 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i -0 1 -.names N_62_0.BLIF N_62 -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_77_i -11 1 -.names N_63_0.BLIF N_63 -0 1 -.names CLK_030_i.BLIF N_143_2.BLIF N_79_0 -11 1 -.names N_66_i.BLIF N_66 -0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_199_0 -11 1 -.names N_67_i.BLIF N_67 -0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names N_69_i.BLIF N_69 -0 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_201_0 -11 1 -.names state_machine_uds_000_int_7_0_m3_un1_n.BLIF \ -state_machine_uds_000_int_7_0_m3_un0_n.BLIF N_70 -1- 1 --1 1 -.names AS_000_DMA_i.BLIF CLK_030_c.BLIF N_203_0 -11 1 -.names N_71_i.BLIF N_71 -0 1 .names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n 11 1 -.names N_75_i.BLIF N_75 +.names N_159.BLIF N_159_i 0 1 -.names N_167.BLIF N_167_i +.names N_158.BLIF N_158_i 0 1 -.names N_76_i.BLIF N_76 +.names N_158_i.BLIF N_159_i.BLIF N_149_i +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_150_i +11 1 +.names N_153.BLIF N_153_i 0 1 -.names N_170.BLIF N_170_i +.names CLK_030_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ +AS_000_DMA_0_sqmuxa +11 1 +.names N_152.BLIF N_152_i 0 1 -.names N_77_i.BLIF N_77 +.names N_164_1.BLIF state_machine_un10_bgack_030_int_n.BLIF \ +state_machine_un8_bgack_030_int_n +11 1 +.names N_160.BLIF N_160_i 0 1 -.names N_136.BLIF N_136_i +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_92 +11 1 +.names N_154.BLIF N_154_i 0 1 -.names N_79_0.BLIF N_79 +.names state_machine_un49_clk_000_d0_1_n.BLIF \ +state_machine_un53_clk_000_d0_n.BLIF state_machine_un49_clk_000_d0_n +11 1 +.names state_machine_un10_clk_000_d0_2_n.BLIF \ +state_machine_un10_clk_000_d0_2_i_n 0 1 -.names N_137.BLIF N_137_i +.names N_210_1.BLIF N_210_2.BLIF N_210 +11 1 +.names N_156.BLIF N_156_i 0 1 -.names N_90_i.BLIF N_90 +.names N_220_5.BLIF N_220_6.BLIF N_220 +11 1 +.names N_157.BLIF N_157_i 0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_6_.BLIF N_202_0 +.names AS_000_DMA_i.BLIF CLK_030_c.BLIF CLK_030_H_1_sqmuxa 11 1 -.names N_200_0.BLIF N_200 -0 1 -.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_200_0 +.names cpu_est_ns_0_1_2__n.BLIF state_machine_un10_clk_000_d0_2_i_n.BLIF \ +cpu_est_ns_0_2__n 11 1 -.names N_202_0.BLIF N_202 -0 1 -.names N_169.BLIF N_169_i -0 1 -.names N_204_1.BLIF VPA_D_i.BLIF N_204 -11 1 -.names N_71.BLIF N_169_i.BLIF N_198_0 -11 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_114 -11 1 -.names N_168.BLIF N_168_i -0 1 -.names N_115_1.BLIF N_115_2.BLIF N_115 -11 1 -.names N_75_i.BLIF N_168_i.BLIF un1_DSACK1_INT_0_sqmuxa_3_0 -11 1 -.names N_116_1.BLIF N_69_i.BLIF N_116 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_90_i -11 1 -.names N_117_1.BLIF RW_c.BLIF N_117 -11 1 -.names AS_030_c.BLIF AS_030_c_i -0 1 -.names N_118_1.BLIF RW_i.BLIF N_118 -11 1 -.names AS_030_c_i.BLIF N_114_i.BLIF N_75_i -11 1 -.names N_120_1.BLIF N_166.BLIF N_120 -11 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_71_i -11 1 -.names CLK_030_c.BLIF N_76_i.BLIF N_121 -11 1 -.names N_69_i_1.BLIF inst_CLK_000_D3.BLIF N_69_i -11 1 -.names N_122_3.BLIF nEXP_SPACE_c.BLIF N_122 -11 1 -.names inst_CLK_000_D2.BLIF SM_AMIGA_5_.BLIF N_67_i -11 1 -.names N_124_1.BLIF size_i_1__n.BLIF N_124 -11 1 -.names N_150.BLIF N_150_i -0 1 -.names N_166.BLIF N_171.BLIF N_125 -11 1 -.names N_151.BLIF N_151_i -0 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF N_128 -11 1 -.names N_202.BLIF sm_amiga_i_7__n.BLIF N_129 -11 1 -.names N_145.BLIF N_145_i -0 1 -.names N_132_1.BLIF inst_CLK_000_D1.BLIF N_132 -11 1 -.names N_146.BLIF N_146_i -0 1 -.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_136 -11 1 -.names N_147.BLIF N_147_i -0 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_137 -11 1 -.names cpu_est_ns_0_1_2__n.BLIF N_146_i.BLIF cpu_est_ns_0_2__n -11 1 -.names N_90.BLIF cpu_est_2_.BLIF N_138 -11 1 -.names N_144.BLIF N_144_i -0 1 -.names N_140_1.BLIF nEXP_SPACE_i.BLIF N_140 -11 1 -.names N_55_0_1.BLIF RW_000_i.BLIF N_55_0 -11 1 -.names N_142_1.BLIF SM_AMIGA_6_.BLIF N_142 -11 1 -.names N_138.BLIF N_138_i -0 1 -.names inst_CLK_030_H.BLIF CLK_030_i.BLIF N_144 -11 1 -.names N_172.BLIF N_172_i -0 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_145 -11 1 -.names N_138_i.BLIF N_172_i.BLIF N_149_i -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_146 -11 1 -.names N_129.BLIF N_129_i -0 1 -.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_147 -11 1 -.names N_148_1.BLIF nEXP_SPACE_i.BLIF N_148 -11 1 -.names N_128.BLIF N_128_i -0 1 -.names N_77.BLIF cpu_est_i_0__n.BLIF N_150 -11 1 -.names N_128_i.BLIF N_198_0.BLIF sm_amiga_ns_0_0__n -11 1 -.names N_77_i.BLIF cpu_est_0_.BLIF N_151 -11 1 -.names N_70.BLIF N_70_i -0 1 -.names N_155_1.BLIF VPA_D_i.BLIF N_155 -11 1 -.names N_124.BLIF N_124_i -0 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_166 -11 1 -.names state_machine_lds_000_int_7_0_1_n.BLIF N_70_i.BLIF \ -state_machine_lds_000_int_7_0_n -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_167 -11 1 -.names state_machine_uds_000_int_7_0_1_n.BLIF DS_030_i.BLIF \ -state_machine_uds_000_int_7_0_n -11 1 -.names N_69_i.BLIF N_71_i.BLIF N_168 -11 1 -.names N_122.BLIF N_122_i -0 1 -.names N_69.BLIF SM_AMIGA_7_.BLIF N_169 -11 1 -.names N_122_i.BLIF un1_DSACK1_INT_0_sqmuxa_3_0.BLIF N_30_0 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_170 -11 1 -.names N_121.BLIF N_121_i -0 1 -.names N_167.BLIF cpu_est_i_3__n.BLIF N_172 -11 1 -.names AS_030_c_i.BLIF N_121_i.BLIF N_28_0 -11 1 -.names N_220_1.BLIF N_220_2.BLIF N_220 -11 1 -.names N_117.BLIF N_117_i -0 1 -.names N_230_5.BLIF N_230_6.BLIF N_230 -11 1 -.names N_118.BLIF N_118_i -0 1 -.names N_133_1.BLIF N_133_2.BLIF N_133 -11 1 -.names N_196_0_1.BLIF N_117_i.BLIF N_196_0 -11 1 -.names N_143_1.BLIF RW_000_i.BLIF N_143 -11 1 -.names N_116.BLIF N_116_i -0 1 -.names N_62.BLIF N_166.BLIF N_143_2 -11 1 -.names inst_BGACK_030_INTreg.BLIF N_116_i.BLIF N_195_i -11 1 -.names N_203_0.BLIF N_203 -0 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names N_201_0.BLIF N_201 -0 1 -.names N_115.BLIF N_115_i -0 1 -.names N_199_0.BLIF N_199 -0 1 -.names BG_030_c_i.BLIF N_115_i.BLIF state_machine_un10_bg_030_0_n -11 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_161 -11 1 -.names AS_030_c_i.BLIF N_67.BLIF N_193_0 -11 1 -.names CLK_030_H_i.BLIF N_203.BLIF N_141 -11 1 -.names N_204.BLIF N_204_i -0 1 -.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_139 +.names CLK_030_c.BLIF state_machine_un8_bgack_030_int_n.BLIF \ +AS_000_DMA_1_sqmuxa 11 1 .names state_machine_un10_clk_000_d0_n.BLIF state_machine_un10_clk_000_d0_i_n 0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_135 +.names DS_000_DMA_1_sqmuxa_1.BLIF state_machine_un24_bgack_030_int_i_n.BLIF \ +DS_000_DMA_1_sqmuxa 11 1 -.names N_204_i.BLIF state_machine_un10_clk_000_d0_i_n.BLIF \ -state_machine_un12_clk_000_d0_0_n +.names state_machine_un5_clk_000_d0_i_0_n.BLIF \ +state_machine_un10_clk_000_d0_i_n.BLIF state_machine_un12_clk_000_d0_0_n 11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_134 +.names inst_CLK_030_H.BLIF CLK_030_i.BLIF state_machine_un24_bgack_030_int_n 11 1 -.names CLK_000_D2_i.BLIF AS_030_000_SYNC_i.BLIF N_69_i_1 +.names FPU_CS_INT_1_sqmuxa.BLIF FPU_CS_INT_1_sqmuxa_i +0 1 +.names state_machine_clk_030_h_2_f1_n.BLIF \ +state_machine_un8_bgack_030_int_n.BLIF state_machine_clk_030_h_2_n 11 1 -.names N_66.BLIF sm_amiga_i_3__n.BLIF N_131 -11 1 -.names BGACK_000_c.BLIF a_i_19__n.BLIF N_76_i_1 -11 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_130 -11 1 -.names a_i_16__n.BLIF a_i_18__n.BLIF N_76_i_2 -11 1 -.names LDS_000_i.BLIF UDS_000_i.BLIF N_171 -11 1 -.names a_c_17__n.BLIF fc_c_0__n.BLIF N_76_i_3 +.names FPU_CS_INT_1_sqmuxa_i.BLIF state_machine_un3_clk_030_n.BLIF \ +un1_as_030_000_sync8_1_0 11 1 +.names state_machine_clk_030_h_2_f1_0_n.BLIF state_machine_clk_030_h_2_f1_n +0 1 +.names AS_030_000_SYNC_0_sqmuxa_2.BLIF AS_030_000_SYNC_0_sqmuxa_2_i +0 1 .names state_machine_ds_000_dma_3_0_n.BLIF state_machine_ds_000_dma_3_n 0 1 -.names N_76_i_1.BLIF N_76_i_2.BLIF N_76_i_4 +.names AS_030_000_SYNC_0_sqmuxa_2_i.BLIF state_machine_un3_clk_030_n.BLIF \ +un1_as_030_000_sync8_0 11 1 -.names N_197_0.BLIF N_197 +.names N_87_0.BLIF N_87 0 1 -.names N_76_i_3.BLIF fc_c_1__n.BLIF N_76_i_5 +.names AS_030_i.BLIF N_85_i.BLIF un1_SM_AMIGA_12_0 11 1 -.names inst_CLK_000_D0.BLIF N_199.BLIF N_119 +.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_93 11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_220_1 +.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un3_clk_030_i_n 11 1 -.names N_194_0.BLIF N_194 +.names SM_AMIGA_3_.BLIF state_machine_un49_clk_000_d0_i_n.BLIF N_94 +11 1 +.names state_machine_un57_clk_000_d0_n.BLIF state_machine_un57_clk_000_d0_i_n 0 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_220_2 +.names N_84.BLIF SM_AMIGA_7_.BLIF N_88 11 1 -.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n +.names state_machine_un51_clk_000_d0_n.BLIF state_machine_un51_clk_000_d0_i_n 0 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_230_1 +.names N_87.BLIF sm_amiga_i_7__n.BLIF N_90 11 1 -.names N_143_2.BLIF N_143_2_i -0 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_230_2 +.names state_machine_un51_clk_000_d0_i_n.BLIF \ +state_machine_un57_clk_000_d0_i_n.BLIF state_machine_un53_clk_000_d0_0_n 11 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_230_3 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_164_1 11 1 -.names a_c_16__n.BLIF a_i_16__n +.names state_machine_un3_bgack_030_int_d_n.BLIF \ +state_machine_un3_bgack_030_int_d_i_n 0 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_230_4 +.names state_machine_un10_bgack_030_int_0_n.BLIF \ +state_machine_un10_bgack_030_int_n +0 1 +.names un1_bgack_030_int_d_0_1.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i.BLIF \ +un1_bgack_030_int_d_0 11 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names N_230_1.BLIF N_230_2.BLIF N_230_5 +.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ +UDS_000_INT_0_sqmuxa_1 11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_3_sqmuxa_i 0 1 -.names N_230_3.BLIF N_230_4.BLIF N_230_6 +.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \ +UDS_000_INT_0_sqmuxa 11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_1.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i 0 1 -.names N_136_i.BLIF N_137_i.BLIF cpu_est_ns_0_1_1__n +.names state_machine_un25_clk_000_d0_i_n.BLIF state_machine_un25_clk_000_d0_n +0 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_1__n.BLIF N_86_0 11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_167_i.BLIF N_170_i.BLIF cpu_est_ns_0_2_1__n +.names N_164_1_0.BLIF nEXP_SPACE_i.BLIF N_164 11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i +.names N_101.BLIF N_101_i 0 1 -.names inst_BGACK_030_INTreg.BLIF CLK_030_c.BLIF N_122_1 +.names RW_li_m_1.BLIF SM_AMIGA_6_.BLIF RW_li_m 11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names N_76.BLIF SM_AMIGA_7_.BLIF N_122_2 +.names N_101_i.BLIF sm_amiga_i_1__n.BLIF N_85_i 11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names N_122_1.BLIF N_122_2.BLIF N_122_3 +.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_181 11 1 -.names RW_c.BLIF RW_i +.names nEXP_SPACE_c.BLIF state_machine_un28_clk_000_d1_n.BLIF N_84_0 +11 1 +.names AS_000_DMA_0_sqmuxa.BLIF RW_000_i.BLIF RW_000_i_m +11 1 +.names N_97.BLIF N_97_i 0 1 -.names AS_030_c.BLIF CLK_000_c.BLIF N_115_1 +.names inst_BGACK_030_INTreg.BLIF RW_i.BLIF N_163 +11 1 +.names un1_SM_AMIGA_8_0.BLIF un1_SM_AMIGA_8 +0 1 +.names N_96.BLIF N_96_i +0 1 +.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_100 +11 1 +.names N_95.BLIF N_95_i +0 1 +.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_91 +11 1 +.names N_95_i.BLIF N_96_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF state_machine_un31_bgack_030_int_n +11 1 +.names N_88.BLIF N_88_i +0 1 +.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n +0 1 +.names N_89.BLIF N_89_i +0 1 +.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n +0 1 +.names N_88_i.BLIF N_89_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names AS_000_DMA_0_sqmuxa_i.BLIF un1_SM_AMIGA_8.BLIF RW_000_INT_0_sqmuxa_1 +11 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_i +0 1 +.names AS_030_i.BLIF N_181.BLIF un1_AS_030_2 +11 1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i +0 1 +.names N_59_0.BLIF N_59 +0 1 +.names AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_i.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 +11 1 +.names un1_bgack_030_int_d_0.BLIF un1_bgack_030_int_d +0 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0.BLIF \ +un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa +0 1 +.names state_machine_un8_bg_030_n.BLIF state_machine_un8_bg_030_i_n +0 1 +.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n +0 1 +.names BG_030_c_i.BLIF state_machine_un8_bg_030_i_n.BLIF \ +state_machine_un10_bg_030_0_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF \ +state_machine_un3_bgack_030_int_d_n +11 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +state_machine_un5_bgack_030_int_d_i_n +11 1 +.names N_86.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \ +AMIGA_BUS_ENABLE_INT_3_sqmuxa +11 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_6_.BLIF N_59_0 +11 1 +.names N_86_0.BLIF N_86 +0 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF state_machine_un10_bgack_030_int_0_n +11 1 +.names inst_BGACK_030_INTreg.BLIF N_84.BLIF AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 +11 1 +.names N_181.BLIF N_181_i +0 1 +.names N_84_0.BLIF N_84 +0 1 +.names A0_c.BLIF A0_c_i +0 1 +.names AMIGA_BUS_ENABLE_INT_3_sqmuxa.BLIF AS_030_i.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 +11 1 +.names A0_c_i.BLIF N_181_i.BLIF state_machine_uds_000_int_7_0_n +11 1 +.names state_machine_un8_bg_030_1_n.BLIF state_machine_un8_bg_030_2_n.BLIF \ +state_machine_un8_bg_030_n +11 1 +.names N_181_i.BLIF state_machine_un25_clk_000_d0_n.BLIF \ +state_machine_lds_000_int_7_0_n +11 1 +.names AMIGA_BUS_ENABLE_INT_2_sqmuxa_1.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_2.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_un31_bgack_030_int_n.BLIF state_machine_size_dma_4_0_0__n +11 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF N_89 +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_un31_bgack_030_int_i_n.BLIF state_machine_size_dma_4_0_1__n +11 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_95 +11 1 +.names N_91.BLIF N_91_i +0 1 +.names SM_AMIGA_3_.BLIF state_machine_un49_clk_000_d0_n.BLIF N_96 +11 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_97 +11 1 +.names N_100.BLIF N_100_i +0 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_1_.BLIF N_99 +11 1 +.names inst_CLK_000_D0.BLIF N_100_i.BLIF un1_SM_AMIGA_8_0 +11 1 +.names state_machine_un28_clk_000_d1_1_n.BLIF CLK_000_D1_i.BLIF \ +state_machine_un28_clk_000_d1_n +11 1 +.names N_164.BLIF N_164_i +0 1 +.names N_101_1.BLIF state_machine_un28_clk_000_d1_n.BLIF N_101 +11 1 +.names N_163.BLIF N_163_i +0 1 +.names un1_SM_AMIGA_12_0.BLIF un1_SM_AMIGA_12 +0 1 +.names N_163_i.BLIF N_164_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names N_85_i.BLIF un1_as_030_000_sync8.BLIF AS_030_000_SYNC_1_sqmuxa +11 1 +.names RW_000_i_m.BLIF RW_000_i_m_i +0 1 +.names un1_as_030_000_sync8_1_0.BLIF un1_as_030_000_sync8_1 +0 1 +.names RW_li_m.BLIF RW_li_m_i +0 1 +.names AS_030_i.BLIF N_59.BLIF AS_000_INT_1_sqmuxa +11 1 +.names RW_000_i_m_i.BLIF RW_li_m_i.BLIF state_machine_rw_000_int_7_iv_i_n +11 1 +.names AS_030_i.BLIF sm_amiga_i_1__n.BLIF DSACK1_INT_1_sqmuxa +11 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names state_machine_un10_clk_000_d0_3_n.BLIF cpu_est_i_3__n.BLIF \ +state_machine_un10_clk_000_d0_n +11 1 +.names state_machine_un25_clk_000_d0_i_1_n.BLIF size_c_i_1__n.BLIF \ +state_machine_un25_clk_000_d0_i_n +11 1 +.names state_machine_un12_clk_000_d0_0_n.BLIF state_machine_un12_clk_000_d0_n +0 1 +.names N_90.BLIF N_90_i +0 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF state_machine_un51_clk_000_d0_n +11 1 +.names state_machine_un53_clk_000_d0_0_n.BLIF state_machine_un53_clk_000_d0_n +0 1 +.names N_94.BLIF N_94_i +0 1 +.names state_machine_un57_clk_000_d0_1_n.BLIF VMA_INT_i.BLIF \ +state_machine_un57_clk_000_d0_n +11 1 +.names N_93.BLIF N_93_i +0 1 +.names AS_030_000_SYNC_0_sqmuxa_i.BLIF AS_030_i.BLIF \ +AS_030_000_SYNC_0_sqmuxa_2 +11 1 +.names N_93_i.BLIF N_94_i.BLIF sm_amiga_ns_0_4__n +11 1 +.names AS_030_000_SYNC_0_sqmuxa_1.BLIF AS_030_000_SYNC_0_sqmuxa_2_0.BLIF \ +AS_030_000_SYNC_0_sqmuxa +11 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_6_.BLIF N_87_0 +11 1 +.names state_machine_un3_clk_030_i_n.BLIF state_machine_un3_clk_030_n +0 1 +.names AS_000_DMA_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_ds_000_dma_3_0_n +11 1 +.names AS_030_i.BLIF state_machine_un28_clk_030_i_n.BLIF FPU_CS_INT_1_sqmuxa 11 1 .names inst_CLK_030_H.BLIF CLK_030_H_i 0 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_115_2 +.names state_machine_un28_clk_030_4_n.BLIF state_machine_un28_clk_030_5_n.BLIF \ +state_machine_un28_clk_030_n 11 1 -.names CLK_030_c.BLIF CLK_030_i +.names CLK_030_H_1_sqmuxa.BLIF CLK_030_H_1_sqmuxa_i 0 1 -.names inst_AS_000_INT.BLIF inst_CLK_000_D0.BLIF \ -state_machine_un10_clk_000_d0_1_n +.names un1_as_030_000_sync8_0.BLIF un1_as_030_000_sync8 +0 1 +.names CLK_030_H_1_sqmuxa_i.BLIF CLK_030_H_i.BLIF \ +state_machine_clk_030_h_2_f1_0_n 11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i +.names N_150_i.BLIF N_150 0 1 -.names N_172.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n +.names un3_dtack_i_1.BLIF BGACK_030_INT_i.BLIF un3_dtack_i 11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_133_1 +.names state_machine_un5_clk_000_d0_1_n.BLIF \ +state_machine_un5_clk_000_d0_2_n.BLIF state_machine_un5_clk_000_d0_n 11 1 -.names AS_000_c.BLIF AS_000_i +.names N_92.BLIF N_92_i 0 1 -.names N_63.BLIF SM_AMIGA_3_.BLIF N_133_2 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF state_machine_un3_clk_000_d1_n 11 1 -.names UDS_000_c.BLIF UDS_000_i +.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n 0 1 -.names CLK_030_i.BLIF N_143_2.BLIF N_143_1 +.names nEXP_SPACE_i.BLIF AS_000_DMA_i.BLIF un3_dtack_i_1 11 1 -.names LDS_000_c.BLIF LDS_000_i -0 1 -.names N_147_i.BLIF N_145_i.BLIF cpu_est_ns_0_1_2__n +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_157 11 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_143_2.BLIF N_144_i.BLIF N_55_0_1 +.names size_c_0__n.BLIF A0_c_i.BLIF state_machine_un25_clk_000_d0_i_1_n 11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names N_124_i.BLIF DS_030_i.BLIF state_machine_lds_000_int_7_0_1_n +.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_156 11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names N_70_i.BLIF A0_i.BLIF state_machine_uds_000_int_7_0_1_n +.names N_157_i.BLIF N_156_i.BLIF cpu_est_ns_0_1_2__n 11 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names N_118_i.BLIF AS_030_c_i.BLIF N_196_0_1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un10_clk_000_d0_2_n 11 1 -.names inst_CLK_000_D2.BLIF CLK_000_D2_i -0 1 -.names N_90_i.BLIF VMA_INT_i.BLIF N_155_1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_210_1 11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names AS_000_DMA_i.BLIF BGACK_030_INT_i.BLIF N_148_1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_154 11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names N_79.BLIF RW_i.BLIF N_142_1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_210_2 11 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names N_166.BLIF RW_c.BLIF N_140_1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_160 11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names N_63.BLIF CLK_000_D0_i.BLIF N_132_1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_220_1 11 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names A0_i.BLIF size_c_0__n.BLIF N_124_1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_152 11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names UDS_000_c.BLIF LDS_000_i.BLIF state_machine_a0_dma_2_1_n +.names a_i_26__n.BLIF a_i_27__n.BLIF N_220_2 11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names CLK_030_i.BLIF N_62.BLIF N_120_1 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_153 11 1 -.names A0_c.BLIF A0_i -0 1 -.names DS_030_i.BLIF N_66_i.BLIF N_118_1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_220_3 11 1 -.names size_c_1__n.BLIF size_i_1__n -0 1 -.names DS_030_i.BLIF N_67_i.BLIF N_117_1 +.names N_150.BLIF cpu_est_2_.BLIF N_158 11 1 -.names DS_030_c.BLIF DS_030_i +.names a_i_30__n.BLIF a_i_31__n.BLIF N_220_4 +11 1 +.names N_160.BLIF cpu_est_i_3__n.BLIF N_159 +11 1 +.names N_220_1.BLIF N_220_2.BLIF N_220_5 +11 1 +.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n 0 1 -.names N_71.BLIF inst_BGACK_030_INT_D.BLIF N_116_1 +.names N_220_3.BLIF N_220_4.BLIF N_220_6 +11 1 +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n +0 1 +.names RW_000_i.BLIF state_machine_un8_bgack_030_int_n.BLIF \ +DS_000_DMA_1_sqmuxa_1 11 1 .names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i 0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 +.names CLK_000_D0_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF UDS_000_INT_0_sqmuxa_1_2 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names inst_CLK_000_D0.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 +11 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_2 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names N_164_1.BLIF RW_c.BLIF N_164_1_0 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names AS_000_DMA_0_sqmuxa_i.BLIF RW_i.BLIF RW_li_m_1 +11 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names N_99_i.BLIF sm_amiga_i_0__n.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 +11 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names sm_amiga_i_7__n.BLIF state_machine_un5_bgack_030_int_d_i_n.BLIF \ +AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 +11 1 +.names state_machine_un28_clk_030_n.BLIF state_machine_un28_clk_030_i_n +0 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_i.BLIF N_101_1 +11 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names state_machine_un3_bgack_030_int_d_i_n.BLIF \ +AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i.BLIF un1_bgack_030_int_d_0_1 +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names AS_030_c.BLIF CLK_000_c.BLIF state_machine_un8_bg_030_1_n +11 1 +.names AS_030_000_SYNC_0_sqmuxa.BLIF AS_030_000_SYNC_0_sqmuxa_i +0 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF state_machine_un8_bg_030_2_n +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names VPA_D_i.BLIF N_150_i.BLIF state_machine_un57_clk_000_d0_1_n +11 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF \ +state_machine_un49_clk_000_d0_1_n +11 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names inst_BGACK_030_INTreg.BLIF SM_AMIGA_7_.BLIF AS_030_000_SYNC_0_sqmuxa_1 +11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names nEXP_SPACE_c.BLIF state_machine_un28_clk_030_i_n.BLIF \ +AS_030_000_SYNC_0_sqmuxa_2_0 +11 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un28_clk_030_1_n +11 1 +.names state_machine_un5_clk_000_d0_n.BLIF state_machine_un5_clk_000_d0_i_0_n +0 1 +.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un28_clk_030_2_n +11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un28_clk_030_3_n +11 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names state_machine_un28_clk_030_1_n.BLIF state_machine_un28_clk_030_2_n.BLIF \ +state_machine_un28_clk_030_4_n +11 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names state_machine_un28_clk_030_3_n.BLIF fc_c_0__n.BLIF \ +state_machine_un28_clk_030_5_n +11 1 +.names N_99.BLIF N_99_i +0 1 +.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un5_clk_000_d0_1_n +11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF state_machine_un5_clk_000_d0_2_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names state_machine_un10_clk_000_d0_2_n.BLIF inst_AS_000_INT.BLIF \ +state_machine_un10_clk_000_d0_1_n +11 1 +.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i +0 1 +.names inst_CLK_000_D0.BLIF cpu_est_i_0__n.BLIF \ +state_machine_un10_clk_000_d0_2_0_n +11 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names state_machine_un10_clk_000_d0_1_n.BLIF \ +state_machine_un10_clk_000_d0_2_0_n.BLIF state_machine_un10_clk_000_d0_3_n +11 1 +.names UDS_000_c.BLIF UDS_000_i +0 1 +.names N_152_i.BLIF N_153_i.BLIF cpu_est_ns_0_1_1__n +11 1 +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names N_154_i.BLIF N_160_i.BLIF cpu_est_ns_0_2_1__n +11 1 +.names AS_000_DMA_0_sqmuxa.BLIF AS_000_DMA_0_sqmuxa_i +0 1 +.names inst_CLK_000_D2.BLIF AS_030_000_SYNC_i.BLIF \ +state_machine_un28_clk_000_d1_1_n +11 1 +.names state_machine_un8_bgack_030_int_n.BLIF \ +state_machine_un8_bgack_030_int_i_n +0 1 +.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_2_un3_n +0 1 +.names state_machine_un31_bgack_030_int_n.BLIF \ +state_machine_un31_bgack_030_int_i_n +0 1 +.names N_149_i.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse_2_un1_n +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names cpu_est_3_reg.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n +11 1 +.names RW_c.BLIF RW_i +0 1 +.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_1_un3_n +0 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names cpu_est_ns_2__n.BLIF state_machine_un3_clk_000_d1_n.BLIF \ +cpu_estse_1_un1_n +11 1 +.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i +0 1 +.names cpu_est_2_.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n +11 1 +.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i +0 1 +.names state_machine_un3_clk_000_d1_n.BLIF cpu_estse_0_un3_n +0 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names cpu_est_ns_1__n.BLIF state_machine_un3_clk_000_d1_n.BLIF \ +cpu_estse_0_un1_n +11 1 +.names DS_030_c.BLIF DS_030_i +0 1 +.names cpu_est_1_.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n +11 1 +.names state_machine_un49_clk_000_d0_n.BLIF state_machine_un49_clk_000_d0_i_n +0 1 +.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_2__un3_n +0 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names ipl_c_2__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_2__un1_n +11 1 +.names state_machine_un24_bgack_030_int_n.BLIF \ +state_machine_un24_bgack_030_int_i_n +0 1 +.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_1__un3_n +0 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names ipl_c_1__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_1__un1_n 11 1 .names a_c_30__n.BLIF a_i_30__n 0 1 -.names CLK_000_D0_i.BLIF N_170.BLIF N_204_1 +.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 .names a_c_31__n.BLIF a_i_31__n 0 1 -.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +.names state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_0__un3_n 0 1 .names a_c_28__n.BLIF a_i_28__n 0 1 +.names ipl_c_0__n.BLIF state_machine_un3_clk_000_d1_n.BLIF ipl_030_0_0__un1_n +11 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 .names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ bgack_030_int_0_un1_n 11 1 -.names a_c_29__n.BLIF a_i_29__n +.names a_c_24__n.BLIF a_i_24__n 0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names N_194.BLIF as_000_dma_0_un3_n -0 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names N_143_2_i.BLIF N_194.BLIF as_000_dma_0_un1_n -11 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 .names a_c_25__n.BLIF a_i_25__n 0 1 -.names N_55.BLIF ds_000_dma_0_un3_n +.names AS_030_000_SYNC_1_sqmuxa.BLIF as_030_000_sync_0_un3_n 0 1 .names RST_c.BLIF RST_i 0 1 -.names state_machine_ds_000_dma_3_n.BLIF N_55.BLIF ds_000_dma_0_un1_n +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_1_sqmuxa.BLIF \ +as_030_000_sync_0_un1_n 11 1 -.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names RST_c.BLIF clk_030_h_0_un3_n -0 1 -.names N_114.BLIF N_114_i -0 1 -.names N_52_i.BLIF RST_c.BLIF clk_030_h_0_un1_n +.names un1_SM_AMIGA_12.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un0_n 11 1 .names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i 0 1 -.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n -11 1 +.names un1_as_030_000_sync8_1.BLIF fpu_cs_int_0_un3_n +0 1 .names inst_CLK_OUT_PRE_50_D.BLIF CLK_OUT_PRE_50_D_i 0 1 -.names N_197.BLIF rw_000_int_0_un3_n +.names inst_FPU_CS_INTreg.BLIF un1_as_030_000_sync8_1.BLIF fpu_cs_int_0_un1_n +11 1 +.names AS_030_c.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n +11 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 -.names state_machine_rw_000_int_7_iv_i_n.BLIF N_197.BLIF rw_000_int_0_un1_n +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n +.names N_59.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 -.names RW_c.BLIF state_machine_uds_000_int_7_0_m3_un3_n +.names DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un3_n 0 1 -.names N_67.BLIF RW_c.BLIF state_machine_uds_000_int_7_0_m3_un1_n +.names inst_DSACK1_INT.BLIF DSACK1_INT_1_sqmuxa.BLIF dsack1_int_0_un1_n 11 1 -.names N_66.BLIF state_machine_uds_000_int_7_0_m3_un3_n.BLIF \ -state_machine_uds_000_int_7_0_m3_un0_n +.names sm_amiga_i_1__n.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n 11 1 -.names N_77.BLIF ipl_030_0_0__un3_n +.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n 0 1 -.names IPL_030DFFSH_0_reg.BLIF N_77.BLIF ipl_030_0_0__un1_n +.names state_machine_un5_clk_000_d0_i_0_n.BLIF \ +state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n 11 1 -.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n 11 1 -.names N_77.BLIF ipl_030_0_1__un3_n +.names un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un3_n 0 1 -.names IPL_030DFFSH_1_reg.BLIF N_77.BLIF ipl_030_0_1__un1_n -11 1 -.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names N_77.BLIF ipl_030_0_2__un3_n -0 1 -.names IPL_030DFFSH_2_reg.BLIF N_77.BLIF ipl_030_0_2__un1_n -11 1 -.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names N_77.BLIF cpu_estse_0_un3_n -0 1 -.names cpu_est_1_.BLIF N_77.BLIF cpu_estse_0_un1_n -11 1 -.names cpu_est_ns_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n -11 1 -.names N_77.BLIF cpu_estse_1_un3_n -0 1 -.names cpu_est_2_.BLIF N_77.BLIF cpu_estse_1_un1_n -11 1 -.names cpu_est_ns_2__n.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n -11 1 -.names N_77.BLIF cpu_estse_2_un3_n -0 1 -.names cpu_est_3_reg.BLIF N_77.BLIF cpu_estse_2_un1_n -11 1 -.names N_149_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n -11 1 -.names N_30.BLIF as_030_000_sync_0_un3_n -0 1 -.names un1_DSACK1_INT_0_sqmuxa_3.BLIF N_30.BLIF as_030_000_sync_0_un1_n -11 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 -.names N_196.BLIF uds_000_int_0_un3_n -0 1 -.names state_machine_uds_000_int_7_n.BLIF N_196.BLIF uds_000_int_0_un1_n -11 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names N_196.BLIF lds_000_int_0_un3_n -0 1 -.names state_machine_lds_000_int_7_n.BLIF N_196.BLIF lds_000_int_0_un1_n -11 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names N_28.BLIF fpu_cs_int_0_un3_n -0 1 -.names AS_030_c.BLIF N_28.BLIF fpu_cs_int_0_un1_n -11 1 -.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n -11 1 -.names AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF avec_exp_0_un3_n -0 1 -.names inst_avec_expreg.BLIF AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \ +.names inst_avec_expreg.BLIF un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa.BLIF \ avec_exp_0_un1_n 11 1 -.names N_195_i.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un0_n +.names un1_bgack_030_int_d.BLIF avec_exp_0_un3_n.BLIF avec_exp_0_un0_n 11 1 .names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n 0 1 @@ -1031,24 +1147,46 @@ avec_exp_0_un1_n 11 1 .names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names N_193.BLIF as_000_int_0_un3_n +.names un1_AS_030_2.BLIF lds_000_int_0_un3_n 0 1 -.names N_67.BLIF N_193.BLIF as_000_int_0_un1_n +.names inst_LDS_000_INT.BLIF un1_AS_030_2.BLIF lds_000_int_0_un1_n 11 1 -.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +.names state_machine_lds_000_int_7_n.BLIF lds_000_int_0_un3_n.BLIF \ +lds_000_int_0_un0_n 11 1 -.names N_75.BLIF dsack1_int_0_un3_n +.names un1_AS_030_2.BLIF uds_000_int_0_un3_n 0 1 -.names N_114_i.BLIF N_75.BLIF dsack1_int_0_un1_n +.names inst_UDS_000_INT.BLIF un1_AS_030_2.BLIF uds_000_int_0_un1_n 11 1 -.names inst_DSACK1_INT.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF \ +uds_000_int_0_un0_n 11 1 -.names state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un3_n +.names RW_000_INT_0_sqmuxa_1.BLIF rw_000_int_0_un3_n 0 1 -.names state_machine_un10_clk_000_d0_n.BLIF \ -state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n +.names inst_RW_000_INT.BLIF RW_000_INT_0_sqmuxa_1.BLIF rw_000_int_0_un1_n 11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +.names state_machine_rw_000_int_7_iv_i_n.BLIF rw_000_int_0_un3_n.BLIF \ +rw_000_int_0_un0_n +11 1 +.names AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un3_n +0 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_1_sqmuxa.BLIF as_000_dma_0_un1_n +11 1 +.names state_machine_un8_bgack_030_int_i_n.BLIF as_000_dma_0_un3_n.BLIF \ +as_000_dma_0_un0_n +11 1 +.names DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un3_n +0 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_1_sqmuxa.BLIF ds_000_dma_0_un1_n +11 1 +.names state_machine_ds_000_dma_3_n.BLIF ds_000_dma_0_un3_n.BLIF \ +ds_000_dma_0_un0_n +11 1 +.names RST_c.BLIF clk_030_h_0_un3_n +0 1 +.names state_machine_clk_030_h_2_n.BLIF RST_c.BLIF clk_030_h_0_un1_n +11 1 +.names inst_CLK_030_H.BLIF clk_030_h_0_un3_n.BLIF clk_030_h_0_un0_n 11 1 .names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ 1 1 @@ -1095,7 +1233,7 @@ state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_220.BLIF CIIN +.names N_210.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -1104,12 +1242,6 @@ state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -0 0 -.names RST_i.BLIF cpu_est_0_.AR -1 1 -0 0 .names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 0 0 @@ -1128,16 +1260,13 @@ state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n .names RST_i.BLIF cpu_est_3_reg.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +.names cpu_estse.BLIF cpu_est_0_.D 1 1 0 0 -.names RST_i.BLIF SM_AMIGA_0_.AR +.names CLK_OSZI_c.BLIF cpu_est_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C -1 1 -0 0 -.names RST_i.BLIF SIZE_DMA_1_.AP +.names RST_i.BLIF cpu_est_0_.AR 1 1 0 0 .names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C @@ -1200,10 +1329,10 @@ state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n .names RST_i.BLIF SM_AMIGA_1_.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 0 0 -.names RST_i.BLIF inst_DSACK1_INT.AP +.names RST_i.BLIF SM_AMIGA_0_.AR 1 1 0 0 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C @@ -1233,6 +1362,12 @@ state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n .names RST_i.BLIF SIZE_DMA_0_.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names RST_i.BLIF SIZE_DMA_1_.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_LDS_000_INT.C 1 1 0 0 @@ -1275,6 +1410,12 @@ state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n .names RST_i.BLIF inst_AS_000_INT.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +1 1 +0 0 +.names RST_i.BLIF inst_DSACK1_INT.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_RW_000_INT.C 1 1 0 0 @@ -1329,15 +1470,6 @@ state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n .names RST_i.BLIF CLK_OUT_INTreg.AR 1 1 0 0 -.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C -1 1 -0 0 -.names RST_i.BLIF inst_CLK_000_D3.AP -1 1 -0 0 .names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D 1 1 0 0 @@ -1434,6 +1566,24 @@ state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n .names SIZE_DMA_0_.BLIF SIZE_0_ 1 1 0 0 +.names A_28_.BLIF a_c_28__n +1 1 +0 0 +.names A_29_.BLIF a_c_29__n +1 1 +0 0 +.names A_30_.BLIF a_c_30__n +1 1 +0 0 +.names A_31_.BLIF a_c_31__n +1 1 +0 0 +.names A0.PIN.BLIF A0_c +1 1 +0 0 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +0 0 .names BG_030.BLIF BG_030_c 1 1 0 0 @@ -1533,25 +1683,7 @@ state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n .names A_27_.BLIF a_c_27__n 1 1 0 0 -.names A_28_.BLIF a_c_28__n -1 1 -0 0 -.names A_29_.BLIF a_c_29__n -1 1 -0 0 -.names A_30_.BLIF a_c_30__n -1 1 -0 0 -.names A_31_.BLIF a_c_31__n -1 1 -0 0 -.names A0.PIN.BLIF A0_c -1 1 -0 0 -.names nEXP_SPACE.BLIF nEXP_SPACE_c -1 1 -0 0 -.names N_148.BLIF AS_030.OE +.names un3_dtack_i.BLIF AS_030.OE 1 1 0 0 .names inst_BGACK_030_INTreg.BLIF AS_000.OE @@ -1560,7 +1692,7 @@ state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n .names inst_BGACK_030_INTreg.BLIF RW_000.OE 1 1 0 0 -.names N_148.BLIF DS_030.OE +.names un3_dtack_i.BLIF DS_030.OE 1 1 0 0 .names inst_BGACK_030_INTreg.BLIF UDS_000.OE @@ -1569,19 +1701,19 @@ state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n .names inst_BGACK_030_INTreg.BLIF LDS_000.OE 1 1 0 0 -.names N_148.BLIF SIZE_0_.OE +.names un3_dtack_i.BLIF SIZE_0_.OE 1 1 0 0 -.names N_148.BLIF SIZE_1_.OE +.names un3_dtack_i.BLIF SIZE_1_.OE 1 1 0 0 -.names N_148.BLIF A0.OE +.names un3_dtack_i.BLIF A0.OE 1 1 0 0 .names nEXP_SPACE_c.BLIF DSACK1.OE 1 1 0 0 -.names N_148.BLIF DTACK.OE +.names un3_dtack_i.BLIF DTACK.OE 1 1 0 0 .names BGACK_030_INT_i.BLIF RW.OE @@ -1590,7 +1722,7 @@ state_machine_un12_clk_000_d0_n.BLIF vma_int_0_un1_n .names FPU_CS_INT_i.BLIF BERR.OE 1 1 0 0 -.names N_230.BLIF CIIN.OE +.names N_220.BLIF CIIN.OE 1 1 0 0 .names inst_CLK_OUT_PRE_25.BLIF state_machine_un3_clk_out_pre_50_n.BLIF \ @@ -1599,4 +1731,9 @@ CLK_OUT_PRE_25_0 10 1 11 0 00 0 +.names cpu_est_0_.BLIF state_machine_un3_clk_000_d1_n.BLIF cpu_estse +01 1 +10 1 +11 0 +00 0 .end diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index 54cd165..db3576b 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2014 6 1 1 3 19) + (timeStamp 2014 6 7 23 3 15) (author "Synopsys, Inc.") (program "Synplify Pro" (version "G-2012.09LC-SP1 , mapper maplat, Build 621R")) ) @@ -158,17 +158,13 @@ (port CIIN (direction OUTPUT)) ) (contents - (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) - ) (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) - ) - (instance (rename SIZE_DMA_1 "SIZE_DMA[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance (rename IPL_030DFFSH_0 "IPL_030DFFSH[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) ) @@ -190,7 +186,7 @@ ) (instance (rename SM_AMIGA_1 "SM_AMIGA[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance DSACK1_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance VMA_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) @@ -200,6 +196,8 @@ ) (instance (rename SIZE_DMA_0 "SIZE_DMA[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) ) + (instance (rename SIZE_DMA_1 "SIZE_DMA[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) (instance LDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance FPU_CS_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) @@ -214,6 +212,8 @@ ) (instance AS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) + (instance DSACK1_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) (instance RW_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance AS_030_000_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) @@ -230,8 +230,6 @@ ) (instance CLK_OUT_INT (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance CLK_000_D3 (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) (instance CLK_000_D1 (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance BGACK_030_INT_D (viewRef prim (cellRef DFFSH (libraryRef mach))) @@ -305,168 +303,309 @@ (instance AMIGA_BUS_DATA_DIR (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance RW_000_INT_0_sqmuxa_i_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_INT_0_sqmuxa_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_AS_030_2_i_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_AS_030_2_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_AS_030_2_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_AS_030_2_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bgack_030_int_d_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bgack_030_int_d_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un12_clk_000_d0_0_a3_1 "state_machine.un12_clk_000_d0_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un12_clk_000_d0_0_a3 "state_machine.un12_clk_000_d0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_AS_030_2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_1_4 "SM_AMIGA_ns_i_a2_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_4 "SM_AMIGA_ns_i_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un3_dtack_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un3_dtack_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_RW_000_INT_7_iv_0_a3_1 "state_machine.RW_000_INT_7_iv_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_RW_000_INT_7_iv_0_a3 "state_machine.RW_000_INT_7_iv_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_0_1_4 "SM_AMIGA_ns_i_a3_0_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_0_4 "SM_AMIGA_ns_i_a3_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_7_0_a3_1 "state_machine.LDS_000_INT_7_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_7_0_a3 "state_machine.LDS_000_INT_7_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_A0_DMA_2_0_a3_1 "state_machine.A0_DMA_2_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_A0_DMA_2_0_a3 "state_machine.A0_DMA_2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un12_clk_000_d0_0_a3_0 "state_machine.un12_clk_000_d0_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_1_5 "SM_AMIGA_ns_0_a3_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_2_5 "SM_AMIGA_ns_0_a3_2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_5 "SM_AMIGA_ns_0_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_RW_000_INT_7_iv_0_a3_0_1 "state_machine.RW_000_INT_7_iv_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_RW_000_INT_7_iv_0_a3_0 "state_machine.RW_000_INT_7_iv_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_1_2 "cpu_est_ns_0_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_2 "cpu_est_ns_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_1_sqmuxa_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_7_0_1 "state_machine.LDS_000_INT_7_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_7_0 "state_machine.LDS_000_INT_7_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_7_0_1 "state_machine.UDS_000_INT_7_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_7_0 "state_machine.UDS_000_INT_7_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_AS_030_2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_1_1 "cpu_est_ns_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_2_1 "cpu_est_ns_0_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_1 "cpu_est_ns_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_1_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_1_i_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_1_i_a3_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_1_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un10_bg_030_0_a3_1 "state_machine.un10_bg_030_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un10_bg_030_0_a3_2 "state_machine.un10_bg_030_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un10_bg_030_0_a3 "state_machine.un10_bg_030_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un12_clk_000_d0_0_a3_0_1 "state_machine.un12_clk_000_d0_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un12_clk_000_d0_0_a3_0_2 "state_machine.un12_clk_000_d0_0_a3_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bgack_030_int_d_i_o2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bgack_030_int_d_i_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_1_i_o2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_1_i_o2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_1_i_o2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_1_i_o2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_1_i_o2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_1_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un4_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un5_clk_000_d0_2 "state_machine.un5_clk_000_d0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un5_clk_000_d0 "state_machine.un5_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_d0_1 "state_machine.un10_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_d0_2 "state_machine.un10_clk_000_d0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_d0_3 "state_machine.un10_clk_000_d0_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_d0 "state_machine.un10_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_1_1 "cpu_est_ns_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_2_1 "cpu_est_ns_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_1 "cpu_est_ns_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un28_clk_000_d1_1 "state_machine.un28_clk_000_d1_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un28_clk_000_d1 "state_machine.un28_clk_000_d1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_bg_030 "state_machine.un8_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un57_clk_000_d0_1 "state_machine.un57_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un57_clk_000_d0 "state_machine.un57_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un49_clk_000_d0_1 "state_machine.un49_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un49_clk_000_d0 "state_machine.un49_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_0_sqmuxa_2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un28_clk_030_1 "state_machine.un28_clk_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un28_clk_030_2 "state_machine.un28_clk_030_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un28_clk_030_3 "state_machine.un28_clk_030_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un28_clk_030_4 "state_machine.un28_clk_030_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un28_clk_030_5 "state_machine.un28_clk_030_5") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un28_clk_030 "state_machine.un28_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un5_clk_000_d0_1 "state_machine.un5_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_a3_0_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_li_m_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_li_m (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_10_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_10_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_bgack_030_int_d_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_bgack_030_int_d (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_bg_030_1 "state_machine.un8_bg_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_bg_030_2 "state_machine.un8_bg_030_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un4_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un4_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_122_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_121_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_030_000_sync8_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_117_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_118_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_AS_030_2_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_116_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un8_ciin_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_93_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o3_i_1 "SM_AMIGA_ns_i_o3_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_DS_000_DMA_3_i "state_machine.DS_000_DMA_3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_CLK_030_H_2_f1_i "state_machine.CLK_030_H_2_f1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_92_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un3_dtack_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un3_dtack (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un25_clk_000_d0_1 "state_machine.un25_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un25_clk_000_d0 "state_machine.un25_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_1_2 "cpu_est_ns_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_2 "cpu_est_ns_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un4_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_7_i "state_machine.LDS_000_INT_7_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_SIZE_DMA_4_i_0 "state_machine.SIZE_DMA_4_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_SIZE_DMA_4_i_1 "state_machine.SIZE_DMA_4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_91_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_100_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_8_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_164_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_163_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_i_m_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_li_m_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un25_clk_000_d0_i_0 "state_machine.un25_clk_000_d0_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_90_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_94_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_5 "SM_AMIGA_ns_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_88_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_89_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0 "SM_AMIGA_ns_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_2_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_115_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un10_bg_030_0_i "state_machine.un10_bg_030_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_204_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un10_clk_000_d0_i "state_machine.un10_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un12_clk_000_d0_0_i "state_machine.un12_clk_000_d0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_145_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_146_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_147_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_i_2 "cpu_est_ns_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_144_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_DMA_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_138_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_172_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_129_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_128_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_i_0 "SM_AMIGA_ns_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_70_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_124_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_7_0_i "state_machine.LDS_000_INT_7_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_7_0_i "state_machine.UDS_000_INT_7_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_136_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_137_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_o2_i_1 "SM_AMIGA_ns_i_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_0_o2_i_2 "SM_AMIGA_ns_a2_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_169_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_168_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_DSACK1_INT_0_sqmuxa_3_0_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_i_0_o2_i_3 "cpu_est_ns_i_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_bgack_030_int_d_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_bgack_030_int_d_i_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_150_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_151_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_161_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_155_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_i_4 "SM_AMIGA_ns_i_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_0_i_4 "SM_AMIGA_ns_i_o2_0_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_1_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un3_clk_000_d1_0_o2_i "state_machine.un3_clk_000_d1_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_RW_000_INT_7_iv_0_o2_i "state_machine.RW_000_INT_7_iv_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_INT_0_sqmuxa_i_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_0_o2_i_6 "SM_AMIGA_ns_a2_0_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_CLK_030_H_2_f0_i_o2_i "state_machine.CLK_030_H_2_f0_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_i_1 "cpu_est_ns_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_167_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_170_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_SIZE_DMA_4_0_i_1 "state_machine.SIZE_DMA_4_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_131_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_133_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_134_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_i_5 "SM_AMIGA_ns_0_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_135_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_139_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_140_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_141_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_143_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_142_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_INT_0_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un6_bgack_000_0_i "state_machine.un6_bgack_000_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_DMA_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_119_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_120_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un8_bg_030_i "state_machine.un8_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un10_bg_030_i "state_machine.un10_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance RW_000_INT_0_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_DS_000_DMA_3_0_i "state_machine.DS_000_DMA_3_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_171_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un10_bgack_030_int_i "state_machine.un10_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_181_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance A0_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_7_i "state_machine.UDS_000_INT_7_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_12_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un3_clk_030_i_0 "state_machine.un3_clk_030_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un57_clk_000_d0_i "state_machine.un57_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un51_clk_000_d0_i "state_machine.un51_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un53_clk_000_d0_i "state_machine.un53_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un3_bgack_030_int_d_i "state_machine.un3_bgack_030_int_d_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_bgack_030_int_d_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_3_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_4_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_101_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_amiga_bus_enable_int5_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_97_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_96_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_95_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_o2_i_3 "cpu_est_ns_i_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_153_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_152_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_160_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_154_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_d0_2_i "state_machine.un10_clk_000_d0_2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_156_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_157_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_i_2 "cpu_est_ns_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_d0_i "state_machine.un10_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un12_clk_000_d0_i "state_machine.un12_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance FPU_CS_INT_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_as_030_000_sync8_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_0_sqmuxa_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_as_030_000_sync8_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un3_clk_000_d1_i "state_machine.un3_clk_000_d1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_bgack_000_i "state_machine.un6_bgack_000_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_i_1 "cpu_est_ns_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_159_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_158_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_a3_1 "cpu_est_ns_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_estse_2_r "cpu_estse_2.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_estse_2_m "cpu_estse_2.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_2_n "cpu_estse_2.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_2_p "cpu_estse_2.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_estse_1_r "cpu_estse_1.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_estse_1_m "cpu_estse_1.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_1_n "cpu_estse_1.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_1_p "cpu_estse_1.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_estse_0_r "cpu_estse_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_estse_0_m "cpu_estse_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_0_n "cpu_estse_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_estse_0_p "cpu_estse_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_143_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance cpu_estse (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_o2_3 "cpu_est_ns_i_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_3 "cpu_est_ns_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_a2_1 "cpu_est_ns_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_a3_0_3 "cpu_est_ns_i_a3_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_a3_3 "cpu_est_ns_i_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_a3_1_2 "cpu_est_ns_0_a3_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_a3_0_2 "cpu_est_ns_0_a3_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_a3_2 "cpu_est_ns_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_a3_1_1 "cpu_est_ns_0_a3_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_a3_0_1 "cpu_est_ns_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_0_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un3_clk_030 "state_machine.un3_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_151 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance FPU_CS_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_12 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_030_000_sync8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_030_000_sync8_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un28_clk_030_i "state_machine.un28_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un12_clk_000_d0 "state_machine.un12_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un3_clk_000_d1 "state_machine.un3_clk_000_d1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_r "FPU_CS_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_m "FPU_CS_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_n "FPU_CS_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_p "FPU_CS_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_p "DSACK1_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename state_machine_un5_clk_000_d0_i "state_machine.un5_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un51_clk_000_d0 "state_machine.un51_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un53_clk_000_d0 "state_machine.un53_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_0_5 "SM_AMIGA_ns_a2_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_6 "SM_AMIGA_ns_i_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_7 "SM_AMIGA_ns_a2[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_9_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0 "SM_AMIGA_ns[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_5 "SM_AMIGA_ns[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_6 "SM_AMIGA_ns_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_amiga_bus_enable_int5_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_10_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_4_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_99_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_INT_0_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename avec_exp_0_r "avec_exp_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename avec_exp_0_m "avec_exp_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename avec_exp_0_n "avec_exp_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename avec_exp_0_p "avec_exp_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename state_machine_un3_bgack_030_int_d "state_machine.un3_bgack_030_int_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BGACK_030_INT_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un5_bgack_030_int_d "state_machine.un5_bgack_030_int_d") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_3_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_bg_030 "state_machine.un10_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_0 "SM_AMIGA_ns_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_0_0 "SM_AMIGA_ns_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_5 "SM_AMIGA_ns_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un31_bgack_030_int_i "state_machine.un31_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_SIZE_DMA_4_0 "state_machine.SIZE_DMA_4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_7 "state_machine.LDS_000_INT_7") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_7 "state_machine.UDS_000_INT_7") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_AS_030_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un31_bgack_030_int "state_machine.un31_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_152 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_153 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un10_bgack_030_int "state_machine.un10_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_AS_030_2_94 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_RW_000_INT_7_iv "state_machine.RW_000_INT_7_iv") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_155 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_i_m (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_154 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_8_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_2 "SM_AMIGA_ns_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_8_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_2 "SM_AMIGA_ns_i_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_SIZE_DMA_4_1 "state_machine.SIZE_DMA_4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_bgack_030_int_i "state_machine.un8_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -479,118 +618,33 @@ (instance (rename CLK_030_H_0_m "CLK_030_H_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename CLK_030_H_0_n "CLK_030_H_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename CLK_030_H_0_p "CLK_030_H_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a3_7 "SM_AMIGA_ns_i_0_a3[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_0_5 "SM_AMIGA_ns_0_a3_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_4 "SM_AMIGA_ns_i_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a3_3 "SM_AMIGA_ns_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_0 "SM_AMIGA_ns_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_0_a3_6 "SM_AMIGA_ns_a2_0_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_SIZE_DMA_4_i_a3_0 "state_machine.SIZE_DMA_4_i_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_INT_0_sqmuxa_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_98_i_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_143 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_144 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_SIZE_DMA_4_0_a2_1 "state_machine.SIZE_DMA_4_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_142 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RW_000_INT_0_sqmuxa_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a2_0_4 "SM_AMIGA_ns_i_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_DMA_1_sqmuxa_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_CLK_030_H_2_f0_i_a3 "state_machine.CLK_030_H_2_f0_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_141 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un3_clk_000_d1_0_o2 "state_machine.un3_clk_000_d1_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_0_4 "SM_AMIGA_ns_i_o2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o2_4 "SM_AMIGA_ns_i_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_INT_0_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_RW_000_INT_7_iv_0 "state_machine.RW_000_INT_7_iv_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_CLK_030_H_2_f0_i "state_machine.CLK_030_H_2_f0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_7 "SM_AMIGA_ns_i_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_3 "SM_AMIGA_ns_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_SIZE_DMA_4_0_1 "state_machine.SIZE_DMA_4_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_DS_000_DMA_3_0 "state_machine.DS_000_DMA_3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_INT_0_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bgack_030_int_d_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_i_0_o2_3 "cpu_est_ns_i_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_DSACK1_INT_0_sqmuxa_3_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_o3_0 "SM_AMIGA_ns_0_o3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_0_o2_2 "SM_AMIGA_ns_a2_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_o2_1 "SM_AMIGA_ns_i_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_RW_000_INT_7_iv_0_a3_0_2 "state_machine.RW_000_INT_7_iv_0_a3_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_145 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_CLK_030_H_2_f0_i_o2 "state_machine.CLK_030_H_2_f0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_0_o2_6 "SM_AMIGA_ns_a2_0_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_INT_0_sqmuxa_i_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_RW_000_INT_7_iv_0_o2 "state_machine.RW_000_INT_7_iv_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_i_0_a2_3 "cpu_est_ns_i_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un12_clk_000_d0_0 "state_machine.un12_clk_000_d0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un10_bg_030_0 "state_machine.un10_bg_030_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_bgack_030_int_d_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_as_030_000_sync8_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_1 "SM_AMIGA_ns_i_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_i_0_3 "cpu_est_ns_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance cpu_estse_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_D2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_7_0_m3_r "state_machine.UDS_000_INT_7_0_m3.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_7_0_m3_m "state_machine.UDS_000_INT_7_0_m3.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_7_0_m3_n "state_machine.UDS_000_INT_7_0_m3.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_7_0_m3_p "state_machine.UDS_000_INT_7_0_m3.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_a3_2 "cpu_est_ns_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_a3_0_2 "cpu_est_ns_0_0_a3_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_a3_1_2 "cpu_est_ns_0_0_a3_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance cpu_estse_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance cpu_estse_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_a2_1 "cpu_est_ns_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_DSACK1_INT_0_sqmuxa_3_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a2_0 "SM_AMIGA_ns_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_a2_0_1 "cpu_est_ns_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o3_1 "SM_AMIGA_ns_i_o3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_4 "SM_AMIGA_ns[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_1 "SM_AMIGA_ns_i[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un49_clk_000_d0_i "state_machine.un49_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_0_4 "SM_AMIGA_ns_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a2_4 "SM_AMIGA_ns_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_1 "SM_AMIGA_ns_i_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_bgack_030_int "state_machine.un8_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_158 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_156 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance CLK_OUT_PRE_25_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance I_148 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_030_000_sync8_1_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_146 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_147 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a2_0_a3_2 "SM_AMIGA_ns_a2_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a3_1 "SM_AMIGA_ns_i_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_a3_1 "cpu_est_ns_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_a3_0_1 "cpu_est_ns_0_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_i_0_a3_3 "cpu_est_ns_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a2_3 "SM_AMIGA_ns_i_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_3 "SM_AMIGA_ns_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un24_bgack_030_int_i "state_machine.un24_bgack_030_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_CLK_030_H_2_f0 "state_machine.CLK_030_H_2_f0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_CLK_030_H_2_f1 "state_machine.CLK_030_H_2_f1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_DS_000_DMA_3 "state_machine.DS_000_DMA_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_A0_DMA_2 "state_machine.A0_DMA_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un24_bgack_030_int "state_machine.un24_bgack_030_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -598,79 +652,21 @@ (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_27 "A_i[27]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_125_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_estse_0_r "cpu_estse_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_estse_0_m "cpu_estse_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_estse_0_n "cpu_estse_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_estse_0_p "cpu_estse_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_estse_1_r "cpu_estse_1.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_estse_1_m "cpu_estse_1.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_estse_1_n "cpu_estse_1.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_estse_1_p "cpu_estse_1.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_estse_2_r "cpu_estse_2.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_estse_2_m "cpu_estse_2.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_estse_2_n "cpu_estse_2.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_estse_2_p "cpu_estse_2.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance CLK_OUT_PRE_50_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un3_clk_out_pre_50 "state_machine.un3_clk_out_pre_50") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance FPU_CS_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_r "FPU_CS_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_m "FPU_CS_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_n "FPU_CS_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_p "FPU_CS_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename avec_exp_0_r "avec_exp_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename avec_exp_0_m "avec_exp_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename avec_exp_0_n "avec_exp_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename avec_exp_0_p "avec_exp_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_114_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_p "DSACK1_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) - (portRef I0 (instanceRef un1_bgack_030_int_d_i)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1)) + (portRef I0 (instanceRef state_machine_un5_bgack_030_int_d)) (portRef I0 (instanceRef BGACK_030_INT_i)) + (portRef I0 (instanceRef state_machine_un3_bgack_030_int_d)) (portRef I0 (instanceRef BGACK_030_INT_0_n)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa_1)) (portRef OE (instanceRef AS_000)) (portRef I0 (instanceRef BGACK_030)) (portRef D (instanceRef BGACK_030_INT_D)) @@ -680,8 +676,8 @@ )) (net FPU_CS_INT (joined (portRef Q (instanceRef FPU_CS_INT)) - (portRef I0 (instanceRef FPU_CS_INT_0_n)) (portRef I0 (instanceRef FPU_CS_INT_i)) + (portRef I0 (instanceRef FPU_CS_INT_0_m)) (portRef I0 (instanceRef FPU_CS)) )) (net (rename avec_expZ0 "avec_exp") (joined @@ -698,24 +694,24 @@ )) (net AS_030_000_SYNC (joined (portRef Q (instanceRef AS_030_000_SYNC)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) (portRef I0 (instanceRef AS_030_000_SYNC_i)) )) (net BGACK_030_INT_D (joined (portRef Q (instanceRef BGACK_030_INT_D)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3_1)) - (portRef I1 (instanceRef un1_bgack_030_int_d_i_a3_1)) + (portRef I1 (instanceRef state_machine_un5_bgack_030_int_d)) + (portRef I0 (instanceRef BGACK_030_INT_D_i)) )) (net AS_000_DMA (joined (portRef Q (instanceRef AS_000_DMA)) (portRef I0 (instanceRef AS_000_DMA_i)) - (portRef I0 (instanceRef AS_000_DMA_0_n)) + (portRef I0 (instanceRef AS_000_DMA_0_m)) (portRef I0 (instanceRef AS_030)) )) (net VPA_D (joined (portRef Q (instanceRef VPA_D)) + (portRef I1 (instanceRef state_machine_un51_clk_000_d0)) (portRef I0 (instanceRef VPA_D_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_4)) )) (net CLK_OUT_PRE_50_D (joined (portRef Q (instanceRef CLK_OUT_PRE_50_D)) @@ -723,30 +719,24 @@ )) (net CLK_000_D0 (joined (portRef Q (instanceRef CLK_000_D0)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_a3_2)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_0_4)) - (portRef I0 (instanceRef state_machine_un3_clk_000_d1_0_o2)) - (portRef I0 (instanceRef N_98_i_i_a3)) - (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_a3)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_a3_6)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_2)) + (portRef I0 (instanceRef un1_SM_AMIGA_8_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_0)) + (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_6)) + (portRef I0 (instanceRef state_machine_un3_clk_000_d1)) (portRef I0 (instanceRef CLK_000_D0_i)) - (portRef I1 (instanceRef state_machine_un12_clk_000_d0_0_a3_0_1)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_0)) + (portRef I0 (instanceRef state_machine_un10_clk_000_d0_2)) (portRef D (instanceRef CLK_000_D1)) )) (net CLK_000_D1 (joined (portRef Q (instanceRef CLK_000_D1)) (portRef I0 (instanceRef CLK_000_D1_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_1_5)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_0_4)) + (portRef I1 (instanceRef state_machine_un49_clk_000_d0_1)) (portRef D (instanceRef CLK_000_D2)) )) - (net CLK_000_D2 (joined - (portRef Q (instanceRef CLK_000_D2)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i_o2)) - (portRef I0 (instanceRef CLK_000_D2_i)) - (portRef D (instanceRef CLK_000_D3)) - )) (net DTACK_D0 (joined (portRef Q (instanceRef DTACK_D0)) (portRef I0 (instanceRef DTACK_D0_i)) @@ -762,13 +752,10 @@ (portRef I0 (instanceRef CLK_OUT_PRE_25_0)) (portRef D (instanceRef CLK_OUT_INT)) )) - (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined - (portRef Q (instanceRef SM_AMIGA_7)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a2_0)) - (portRef I0 (instanceRef SM_AMIGA_i_7)) - (portRef I0 (instanceRef un1_bgack_030_int_d_i_o2)) - (portRef I0 (instanceRef state_machine_un10_bg_030_0_a3_2)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_2)) + (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined + (portRef Q (instanceRef SM_AMIGA_1)) + (portRef I1 (instanceRef un1_SM_AMIGA_9_i_a2)) + (portRef I0 (instanceRef SM_AMIGA_i_1)) )) (net VCC (joined (portRef I0 (instanceRef AMIGA_BUS_ENABLE_LOW)) @@ -778,82 +765,71 @@ (net GND (joined (portRef I0 (instanceRef BERR)) )) - (net (rename state_machine_un10_clk_000_d0 "state_machine.un10_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un12_clk_000_d0_0_a3_0)) - (portRef I0 (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef state_machine_un10_clk_000_d0_i)) - )) (net AS_000_INT (joined (portRef Q (instanceRef AS_000_INT)) - (portRef I0 (instanceRef AS_000_INT_0_n)) - (portRef I0 (instanceRef state_machine_un12_clk_000_d0_0_a3_0_1)) + (portRef I0 (instanceRef AS_000_INT_0_m)) + (portRef I1 (instanceRef state_machine_un10_clk_000_d0_1)) (portRef I0 (instanceRef AS_000)) )) (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined (portRef Q (instanceRef SM_AMIGA_6)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_o2_1)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_o3_1)) (portRef I0 (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef state_machine_RW_000_INT_7_iv_0_a3)) + (portRef I1 (instanceRef RW_000_INT_0_sqmuxa_i)) + (portRef I1 (instanceRef RW_li_m)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_2)) )) (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined (portRef Q (instanceRef SM_AMIGA_0)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_0)) (portRef I0 (instanceRef SM_AMIGA_i_0)) )) - (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined - (portRef Q (instanceRef SM_AMIGA_5)) - (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_i_o2)) - (portRef I0 (instanceRef SM_AMIGA_i_5)) - )) - (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined - (portRef Q (instanceRef SM_AMIGA_2)) - (portRef I1 (instanceRef N_98_i_i_a3)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_5)) - (portRef I0 (instanceRef SM_AMIGA_i_2)) + (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined + (portRef Q (instanceRef SM_AMIGA_7)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_0)) + (portRef I0 (instanceRef SM_AMIGA_i_7)) + (portRef I0 (instanceRef state_machine_un8_bg_030_2)) + (portRef I0 (instanceRef un1_SM_AMIGA_10_i_a3_1)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_sqmuxa_1)) )) (net RW_000_INT (joined (portRef Q (instanceRef RW_000_INT)) - (portRef I0 (instanceRef RW_000_INT_0_n)) + (portRef I0 (instanceRef RW_000_INT_0_m)) (portRef I0 (instanceRef RW)) (portRef I0 (instanceRef RW_000)) )) (net UDS_000_INT (joined (portRef Q (instanceRef UDS_000_INT)) - (portRef I0 (instanceRef UDS_000_INT_0_n)) + (portRef I0 (instanceRef UDS_000_INT_0_m)) (portRef I0 (instanceRef UDS_000)) )) (net LDS_000_INT (joined (portRef Q (instanceRef LDS_000_INT)) - (portRef I0 (instanceRef LDS_000_INT_0_n)) + (portRef I0 (instanceRef LDS_000_INT_0_m)) (portRef I0 (instanceRef LDS_000)) )) (net DSACK1_INT (joined (portRef Q (instanceRef DSACK1_INT)) - (portRef I0 (instanceRef DSACK1_INT_0_n)) + (portRef I0 (instanceRef DSACK1_INT_0_m)) (portRef I0 (instanceRef DSACK1)) )) (net (rename state_machine_un3_clk_out_pre_50 "state_machine.un3_clk_out_pre_50") (joined (portRef O (instanceRef state_machine_un3_clk_out_pre_50)) (portRef I1 (instanceRef CLK_OUT_PRE_25_0)) )) - (net CLK_000_D3 (joined - (portRef Q (instanceRef CLK_000_D3)) - (portRef I1 (instanceRef un1_bgack_030_int_d_i_o2_0)) + (net CLK_000_D2 (joined + (portRef Q (instanceRef CLK_000_D2)) + (portRef I0 (instanceRef state_machine_un28_clk_000_d1_1)) )) (net CLK_030_H (joined (portRef Q (instanceRef CLK_030_H)) - (portRef I0 (instanceRef CLK_030_H_i)) - (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_i_a3)) + (portRef I0 (instanceRef state_machine_un24_bgack_030_int)) (portRef I0 (instanceRef CLK_030_H_0_n)) - )) - (net (rename state_machine_un12_clk_000_d0 "state_machine.un12_clk_000_d0") (joined - (portRef O (instanceRef state_machine_un12_clk_000_d0_0_i)) - (portRef I1 (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_r)) + (portRef I0 (instanceRef CLK_030_H_i)) )) (net DS_000_DMA (joined (portRef Q (instanceRef DS_000_DMA)) - (portRef I0 (instanceRef DS_000_DMA_0_n)) + (portRef I0 (instanceRef DS_000_DMA_0_m)) (portRef I0 (instanceRef DS_030)) )) (net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined @@ -868,50 +844,38 @@ (portRef Q (instanceRef A0_DMA)) (portRef I0 (instanceRef A0)) )) - (net AMIGA_BUS_ENABLE_INT_2_sqmuxa (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3)) - (portRef I1 (instanceRef avec_exp_0_m)) - (portRef I0 (instanceRef avec_exp_0_r)) + (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined + (portRef Q (instanceRef SM_AMIGA_5)) + (portRef I0 (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_2)) )) (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined (portRef Q (instanceRef SM_AMIGA_4)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_0_4)) (portRef I0 (instanceRef SM_AMIGA_i_4)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_4)) )) (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined (portRef Q (instanceRef SM_AMIGA_3)) - (portRef I0 (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_2_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_5)) )) - (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined - (portRef Q (instanceRef SM_AMIGA_1)) - (portRef I0 (instanceRef SM_AMIGA_i_1)) - )) - (net un1_DSACK1_INT_0_sqmuxa_3 (joined - (portRef O (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_o3_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) + (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined + (portRef Q (instanceRef SM_AMIGA_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_5)) + (portRef I0 (instanceRef SM_AMIGA_i_2)) )) (net (rename state_machine_A0_DMA_2 "state_machine.A0_DMA_2") (joined - (portRef O (instanceRef state_machine_A0_DMA_2_0_a3)) + (portRef O (instanceRef state_machine_A0_DMA_2)) (portRef D (instanceRef A0_DMA)) )) + (net (rename state_machine_SIZE_DMA_4_0 "state_machine.SIZE_DMA_4[0]") (joined + (portRef O (instanceRef state_machine_SIZE_DMA_4_i_0)) + (portRef D (instanceRef SIZE_DMA_0)) + )) (net (rename state_machine_SIZE_DMA_4_1 "state_machine.SIZE_DMA_4[1]") (joined - (portRef O (instanceRef state_machine_SIZE_DMA_4_0_i_1)) + (portRef O (instanceRef state_machine_SIZE_DMA_4_i_1)) (portRef D (instanceRef SIZE_DMA_1)) )) - (net (rename state_machine_un10_bg_030 "state_machine.un10_bg_030") (joined - (portRef O (instanceRef state_machine_un10_bg_030_0_i)) - (portRef I1 (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_r)) - )) - (net (rename state_machine_LDS_000_INT_7 "state_machine.LDS_000_INT_7") (joined - (portRef O (instanceRef state_machine_LDS_000_INT_7_0_i)) - (portRef I0 (instanceRef LDS_000_INT_0_m)) - )) - (net (rename state_machine_UDS_000_INT_7 "state_machine.UDS_000_INT_7") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_7_0_i)) - (portRef I0 (instanceRef UDS_000_INT_0_m)) - )) (net N_1 (joined (portRef O (instanceRef RW_000_INT_0_p)) (portRef D (instanceRef RW_000_INT)) @@ -985,53 +949,57 @@ (portRef D (instanceRef IPL_030DFFSH_2)) )) (net (rename SM_AMIGA_ns_0 "SM_AMIGA_ns[0]") (joined - (portRef O (instanceRef SM_AMIGA_ns_0_i_0)) + (portRef O (instanceRef SM_AMIGA_ns_i_0)) (portRef D (instanceRef SM_AMIGA_7)) )) + (net (rename SM_AMIGA_ns_4 "SM_AMIGA_ns[4]") (joined + (portRef O (instanceRef SM_AMIGA_ns_i_4)) + (portRef D (instanceRef SM_AMIGA_3)) + )) (net (rename SM_AMIGA_ns_5 "SM_AMIGA_ns[5]") (joined - (portRef O (instanceRef SM_AMIGA_ns_0_i_5)) + (portRef O (instanceRef SM_AMIGA_ns_i_5)) (portRef D (instanceRef SM_AMIGA_2)) )) - (net (rename SM_AMIGA_ns_2 "SM_AMIGA_ns[2]") (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_0_a3_2)) - (portRef D (instanceRef SM_AMIGA_5)) - )) - (net (rename SM_AMIGA_ns_6 "SM_AMIGA_ns[6]") (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_0_a3_6)) - (portRef D (instanceRef SM_AMIGA_1)) + (net (rename SM_AMIGA_ns_7 "SM_AMIGA_ns[7]") (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_7)) + (portRef D (instanceRef SM_AMIGA_0)) )) (net (rename cpu_est_0 "cpu_est[0]") (joined (portRef Q (instanceRef cpu_est_0)) - (portRef I0 (instanceRef cpu_est_ns_0_0_a2_0_1)) + (portRef I0 (instanceRef cpu_est_ns_0_a3_1_1)) + (portRef I0 (instanceRef cpu_est_ns_0_a3_0_2)) (portRef I0 (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef cpu_estse_i_a3_0)) - (portRef I0 (instanceRef cpu_est_ns_0_0_a3_1_2)) + (portRef I0 (instanceRef cpu_estse)) + (portRef I0 (instanceRef state_machine_un5_clk_000_d0_2)) )) (net (rename cpu_est_1 "cpu_est[1]") (joined (portRef Q (instanceRef cpu_est_1)) - (portRef I0 (instanceRef cpu_estse_0_m)) (portRef I0 (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef cpu_est_ns_0_0_a2_1)) - (portRef I0 (instanceRef cpu_est_ns_0_0_a3_2)) + (portRef I0 (instanceRef cpu_est_ns_0_a3_2)) + (portRef I0 (instanceRef cpu_est_ns_0_a2_1)) + (portRef I0 (instanceRef cpu_estse_0_n)) )) (net (rename cpu_est_2 "cpu_est[2]") (joined (portRef Q (instanceRef cpu_est_2)) - (portRef I0 (instanceRef cpu_estse_1_m)) - (portRef I1 (instanceRef cpu_est_ns_i_0_a3_3)) (portRef I0 (instanceRef cpu_est_i_2)) - (portRef I0 (instanceRef cpu_est_ns_0_0_a3_1)) - (portRef I1 (instanceRef cpu_est_ns_0_0_a3_2)) - (portRef I1 (instanceRef state_machine_un12_clk_000_d0_0_a3_0_2)) + (portRef I0 (instanceRef cpu_est_ns_0_a3_0_1)) + (portRef I1 (instanceRef cpu_est_ns_0_a3_2)) + (portRef I1 (instanceRef cpu_est_ns_i_a3_3)) + (portRef I0 (instanceRef cpu_estse_1_n)) )) (net (rename cpu_est_3 "cpu_est[3]") (joined (portRef Q (instanceRef cpu_est_3)) - (portRef I0 (instanceRef cpu_estse_2_m)) - (portRef I1 (instanceRef cpu_est_ns_0_0_a3_1)) - (portRef I1 (instanceRef cpu_est_ns_0_0_a3_1_2)) - (portRef I0 (instanceRef cpu_est_ns_i_0_o2_3)) (portRef I0 (instanceRef cpu_est_i_3)) + (portRef I1 (instanceRef cpu_est_ns_0_a3_0_1)) + (portRef I1 (instanceRef cpu_est_ns_0_a3_0_2)) + (portRef I0 (instanceRef cpu_est_ns_i_o2_3)) + (portRef I0 (instanceRef cpu_estse_2_n)) (portRef I0 (instanceRef E)) )) + (net (rename cpu_est_ns_e_0 "cpu_est_ns_e[0]") (joined + (portRef O (instanceRef cpu_estse)) + (portRef D (instanceRef cpu_est_0)) + )) (net (rename cpu_est_ns_e_1 "cpu_est_ns_e[1]") (joined (portRef O (instanceRef cpu_estse_0_p)) (portRef D (instanceRef cpu_est_1)) @@ -1044,525 +1012,616 @@ (portRef O (instanceRef cpu_estse_2_p)) (portRef D (instanceRef cpu_est_3)) )) - (net (rename cpu_est_ns_1 "cpu_est_ns[1]") (joined - (portRef O (instanceRef cpu_est_ns_0_0_i_1)) - (portRef I0 (instanceRef cpu_estse_0_n)) + (net AS_000_DMA_0_sqmuxa (joined + (portRef O (instanceRef AS_000_DMA_0_sqmuxa)) + (portRef I0 (instanceRef RW_000_i_m)) + (portRef I0 (instanceRef AS_000_DMA_0_sqmuxa_i)) )) - (net (rename cpu_est_ns_2 "cpu_est_ns[2]") (joined - (portRef O (instanceRef cpu_est_ns_0_0_i_2)) - (portRef I0 (instanceRef cpu_estse_1_n)) + (net (rename state_machine_un8_bgack_030_int "state_machine.un8_bgack_030_int") (joined + (portRef O (instanceRef state_machine_un8_bgack_030_int)) + (portRef I1 (instanceRef AS_000_DMA_0_sqmuxa)) + (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa)) + (portRef I1 (instanceRef state_machine_A0_DMA_2)) + (portRef I1 (instanceRef state_machine_DS_000_DMA_3)) + (portRef I1 (instanceRef state_machine_CLK_030_H_2_f0)) + (portRef I0 (instanceRef state_machine_un8_bgack_030_int_i)) + (portRef I0 (instanceRef state_machine_SIZE_DMA_4_1)) + (portRef I0 (instanceRef state_machine_SIZE_DMA_4_0)) + (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_1)) )) - (net N_193 (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa_i_i)) - (portRef I1 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_r)) + (net N_92 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_3)) + (portRef I0 (instanceRef N_92_i)) )) - (net N_196 (joined - (portRef O (instanceRef un1_AS_030_2_i_i)) - (portRef I1 (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_r)) - (portRef I1 (instanceRef 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(instanceRef state_machine_SIZE_DMA_4_0)) + (portRef I0 (instanceRef state_machine_un31_bgack_030_int_i)) + )) + (net (rename state_machine_LDS_000_INT_7 "state_machine.LDS_000_INT_7") (joined + (portRef O (instanceRef state_machine_LDS_000_INT_7_i)) + (portRef I0 (instanceRef LDS_000_INT_0_n)) + )) + (net (rename state_machine_UDS_000_INT_7 "state_machine.UDS_000_INT_7") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_7_i)) + (portRef I0 (instanceRef UDS_000_INT_0_n)) + )) + (net RW_000_INT_0_sqmuxa_1 (joined + (portRef O (instanceRef RW_000_INT_0_sqmuxa_1)) + (portRef I1 (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_r)) + )) + (net un1_AS_030_2 (joined + (portRef O (instanceRef un1_AS_030_2)) + (portRef I1 (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_r)) + )) + (net N_59 (joined + (portRef O (instanceRef RW_000_INT_0_sqmuxa_i_i)) + (portRef I1 (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I0 (instanceRef AS_000_INT_0_n)) + )) + (net un1_bgack_030_int_d (joined + (portRef O (instanceRef un1_bgack_030_int_d_i)) + (portRef I0 (instanceRef avec_exp_0_n)) + )) + (net un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_i)) + (portRef I1 (instanceRef avec_exp_0_m)) + (portRef I0 (instanceRef avec_exp_0_r)) + )) + (net (rename state_machine_un10_bg_030 "state_machine.un10_bg_030") (joined + (portRef O (instanceRef state_machine_un10_bg_030_i)) + (portRef I1 (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_r)) + )) + (net (rename state_machine_un3_bgack_030_int_d "state_machine.un3_bgack_030_int_d") (joined + (portRef O (instanceRef state_machine_un3_bgack_030_int_d)) + (portRef I0 (instanceRef state_machine_un3_bgack_030_int_d_i)) + )) + (net AMIGA_BUS_ENABLE_INT_3_sqmuxa (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa_i)) + )) + (net N_86 (joined + (portRef O (instanceRef un1_SM_AMIGA_4_0_o2_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_7)) + )) + (net AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i)) + )) + (net N_84 (joined + (portRef O (instanceRef un1_amiga_bus_enable_int5_0_o2_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_0)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1)) + )) + (net AMIGA_BUS_ENABLE_INT_1_sqmuxa_2 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i)) + )) + (net (rename state_machine_un8_bg_030 "state_machine.un8_bg_030") (joined + (portRef O (instanceRef state_machine_un8_bg_030)) + (portRef I0 (instanceRef state_machine_un8_bg_030_i)) + )) + (net AMIGA_BUS_ENABLE_INT_2_sqmuxa (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_i)) + )) + (net N_89 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_0_0)) + (portRef I0 (instanceRef N_89_i)) + )) + (net N_95 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_5)) + (portRef I0 (instanceRef N_95_i)) + )) + (net N_96 (joined + (portRef O (instanceRef SM_AMIGA_ns_a2_0_5)) + (portRef I0 (instanceRef N_96_i)) + )) + (net N_97 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_a2_6)) + (portRef I0 (instanceRef N_97_i)) + )) + (net N_99 (joined + (portRef O (instanceRef un1_SM_AMIGA_9_i_a2)) + (portRef I0 (instanceRef N_99_i)) + )) + (net (rename state_machine_un28_clk_000_d1 "state_machine.un28_clk_000_d1") (joined + (portRef O (instanceRef state_machine_un28_clk_000_d1)) + (portRef I1 (instanceRef un1_amiga_bus_enable_int5_0_o2)) + (portRef I1 (instanceRef un1_SM_AMIGA_10_i_a3)) + )) + (net N_101 (joined + (portRef O (instanceRef un1_SM_AMIGA_10_i_a3)) + (portRef I0 (instanceRef N_101_i)) + )) + (net un1_SM_AMIGA_12 (joined + (portRef O (instanceRef un1_SM_AMIGA_12_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) + )) + (net AS_030_000_SYNC_1_sqmuxa (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) + )) + (net un1_as_030_000_sync8_1 (joined + (portRef O (instanceRef un1_as_030_000_sync8_1_i)) + (portRef I1 (instanceRef FPU_CS_INT_0_m)) + (portRef I0 (instanceRef FPU_CS_INT_0_r)) + )) + (net AS_000_INT_1_sqmuxa (joined + (portRef O (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I1 (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_r)) + )) + (net DSACK1_INT_1_sqmuxa (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa)) + (portRef I1 (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_0_r)) + )) + (net (rename state_machine_un10_clk_000_d0 "state_machine.un10_clk_000_d0") (joined + (portRef O (instanceRef state_machine_un10_clk_000_d0)) + (portRef I0 (instanceRef state_machine_un10_clk_000_d0_i)) + )) + (net (rename state_machine_un12_clk_000_d0 "state_machine.un12_clk_000_d0") (joined + (portRef O (instanceRef state_machine_un12_clk_000_d0_i)) + (portRef I1 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_r)) + )) + (net (rename state_machine_un51_clk_000_d0 "state_machine.un51_clk_000_d0") (joined + (portRef O (instanceRef state_machine_un51_clk_000_d0)) + (portRef I0 (instanceRef state_machine_un51_clk_000_d0_i)) + )) + (net (rename state_machine_un53_clk_000_d0 "state_machine.un53_clk_000_d0") (joined + (portRef O (instanceRef state_machine_un53_clk_000_d0_i)) + (portRef I1 (instanceRef state_machine_un49_clk_000_d0)) + )) + (net (rename state_machine_un57_clk_000_d0 "state_machine.un57_clk_000_d0") (joined + (portRef O (instanceRef state_machine_un57_clk_000_d0)) + (portRef I0 (instanceRef state_machine_un57_clk_000_d0_i)) + )) + (net AS_030_000_SYNC_0_sqmuxa_2 (joined + (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa_2)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa_2_i)) + )) + (net AS_030_000_SYNC_0_sqmuxa (joined + (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa_i)) + )) + (net (rename state_machine_un3_clk_030 "state_machine.un3_clk_030") (joined + (portRef O (instanceRef state_machine_un3_clk_030_i_0)) + (portRef I1 (instanceRef un1_as_030_000_sync8_1)) + (portRef I1 (instanceRef un1_as_030_000_sync8)) + )) + (net FPU_CS_INT_1_sqmuxa (joined + (portRef O (instanceRef FPU_CS_INT_1_sqmuxa)) + (portRef I0 (instanceRef FPU_CS_INT_1_sqmuxa_i)) + )) + (net (rename state_machine_un28_clk_030 "state_machine.un28_clk_030") (joined + (portRef O (instanceRef state_machine_un28_clk_030)) + (portRef I0 (instanceRef state_machine_un28_clk_030_i)) + )) + (net un1_as_030_000_sync8 (joined + (portRef O (instanceRef un1_as_030_000_sync8_i)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa)) + )) + (net N_150 (joined + (portRef O (instanceRef cpu_est_ns_i_o2_i_3)) + (portRef I0 (instanceRef cpu_est_ns_i_a3_3)) + )) + (net (rename state_machine_un5_clk_000_d0 "state_machine.un5_clk_000_d0") (joined + (portRef O (instanceRef state_machine_un5_clk_000_d0)) + (portRef I0 (instanceRef state_machine_un5_clk_000_d0_i)) + )) + (net (rename state_machine_un3_clk_000_d1 "state_machine.un3_clk_000_d1") (joined + (portRef O (instanceRef state_machine_un3_clk_000_d1)) + (portRef I1 (instanceRef cpu_estse)) + (portRef I1 (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef cpu_estse_0_m)) + (portRef I0 (instanceRef cpu_estse_0_r)) + (portRef I1 (instanceRef cpu_estse_1_m)) + (portRef I0 (instanceRef cpu_estse_1_r)) + (portRef I1 (instanceRef cpu_estse_2_m)) + (portRef I0 (instanceRef cpu_estse_2_r)) + (portRef I0 (instanceRef state_machine_un3_clk_000_d1_i)) + )) + (net (rename cpu_est_ns_2 "cpu_est_ns[2]") (joined + (portRef O (instanceRef cpu_est_ns_0_i_2)) + (portRef I0 (instanceRef cpu_estse_1_m)) + )) + (net N_157 (joined + (portRef O (instanceRef cpu_est_ns_0_a3_1_2)) + (portRef I0 (instanceRef N_157_i)) + )) + (net N_156 (joined + (portRef O (instanceRef cpu_est_ns_0_a3_0_2)) + (portRef I0 (instanceRef N_156_i)) + )) + (net (rename state_machine_un10_clk_000_d0_2 "state_machine.un10_clk_000_d0_2") (joined + (portRef O (instanceRef cpu_est_ns_0_a3_2)) + (portRef I0 (instanceRef state_machine_un10_clk_000_d0_2_i)) + (portRef I0 (instanceRef state_machine_un10_clk_000_d0_1)) + )) + (net N_154 (joined + (portRef O (instanceRef cpu_est_ns_0_a3_1_1)) + (portRef I0 (instanceRef N_154_i)) + )) + (net N_160 (joined + (portRef O (instanceRef cpu_est_ns_0_a2_1)) + (portRef I0 (instanceRef cpu_est_ns_i_a3_0_3)) + (portRef I0 (instanceRef N_160_i)) + )) + (net N_152 (joined + (portRef O (instanceRef cpu_est_ns_0_a3_1)) + (portRef I0 (instanceRef N_152_i)) + )) + (net N_153 (joined + (portRef O (instanceRef cpu_est_ns_0_a3_0_1)) + (portRef I0 (instanceRef N_153_i)) + )) + (net N_158 (joined + (portRef O (instanceRef cpu_est_ns_i_a3_3)) + (portRef I0 (instanceRef N_158_i)) + )) + (net N_159 (joined + (portRef O (instanceRef cpu_est_ns_i_a3_0_3)) + (portRef I0 (instanceRef N_159_i)) + )) + (net (rename cpu_est_ns_1 "cpu_est_ns[1]") (joined + (portRef O (instanceRef cpu_est_ns_0_i_1)) + (portRef I0 (instanceRef cpu_estse_0_m)) + )) (net (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (joined - (portRef O (instanceRef state_machine_un6_bgack_000_0_i)) + (portRef O (instanceRef state_machine_un6_bgack_000_i)) (portRef I1 (instanceRef BGACK_030_INT_0_m)) (portRef I0 (instanceRef BGACK_030_INT_0_r)) )) - (net N_143_2_i (joined - (portRef O (instanceRef N_143_2_i)) - (portRef I0 (instanceRef AS_000_DMA_0_m)) + (net AS_030_000_SYNC_i (joined + (portRef O (instanceRef AS_030_000_SYNC_i)) + (portRef I1 (instanceRef state_machine_un28_clk_000_d1_1)) )) - (net (rename A_i_18 "A_i[18]") (joined - (portRef O (instanceRef A_i_18)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_2)) - )) - (net (rename A_i_16 "A_i[16]") (joined - (portRef O (instanceRef A_i_16)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_2)) - )) - (net (rename A_i_19 "A_i[19]") (joined - (portRef O (instanceRef A_i_19)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_1)) - )) - (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined - (portRef O (instanceRef SM_AMIGA_i_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_3)) - )) - (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined - (portRef O (instanceRef SM_AMIGA_i_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_o2_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_3)) - )) - (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined - (portRef O (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_4)) - )) - (net CLK_000_D0_i (joined - (portRef O (instanceRef CLK_000_D0_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_3)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_7)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_1_5)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_0_1_4)) - (portRef I0 (instanceRef state_machine_un12_clk_000_d0_0_a3_1)) - )) - (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined - (portRef O (instanceRef SM_AMIGA_i_0)) - (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_o2_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_7)) - )) - (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined - (portRef O (instanceRef SM_AMIGA_i_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_o2_6)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_7)) - )) - (net RW_i (joined - (portRef O (instanceRef I_141)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3)) - (portRef I1 (instanceRef state_machine_RW_000_INT_7_iv_0_a3_1)) - (portRef I1 (instanceRef un1_AS_030_2_i_a3_0)) - )) - (net CLK_030_H_i (joined - (portRef O (instanceRef CLK_030_H_i)) - (portRef I0 (instanceRef state_machine_CLK_030_H_2_f0_i_a3)) - )) - (net CLK_030_i (joined - (portRef O (instanceRef CLK_030_i)) - (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv_0_o2)) - (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_i_a3)) - (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv_0_a3_0_1)) - (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_a3_0_1)) - )) - (net DTACK_D0_i (joined - (portRef O (instanceRef DTACK_D0_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_4)) - )) - (net BGACK_030_INT_i (joined - (portRef O (instanceRef BGACK_030_INT_i)) - (portRef I1 (instanceRef RW_000_INT_0_sqmuxa_i_a2)) - (portRef I1 (instanceRef un3_dtack_i_a3_1)) - (portRef OE (instanceRef RW)) - )) - (net AS_000_i (joined - (portRef O (instanceRef I_142)) - (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_a2)) - )) - (net UDS_000_i (joined - (portRef O (instanceRef I_143)) - (portRef I1 (instanceRef state_machine_SIZE_DMA_4_0_a2_1)) - )) - (net LDS_000_i (joined - (portRef O (instanceRef I_144)) - (portRef I0 (instanceRef state_machine_SIZE_DMA_4_0_a2_1)) - (portRef I1 (instanceRef state_machine_A0_DMA_2_0_a3_1)) - )) - (net RW_000_i (joined - (portRef O (instanceRef I_145)) - (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_i)) - (portRef I1 (instanceRef state_machine_RW_000_INT_7_iv_0_a3_0)) - )) - (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined - (portRef O (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef RW_000_INT_0_sqmuxa_i_o2_0)) - (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_o2_2)) + (net CLK_000_D1_i (joined + (portRef O (instanceRef CLK_000_D1_i)) + (portRef I1 (instanceRef state_machine_un3_clk_000_d1)) + (portRef I1 (instanceRef state_machine_un28_clk_000_d1)) )) (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined (portRef O (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef cpu_est_ns_0_0_a3_0_1)) - (portRef I1 (instanceRef cpu_est_ns_i_0_a2_3)) - )) - (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined - (portRef O (instanceRef SM_AMIGA_i_7)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_1)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3)) - )) - (net CLK_000_D2_i (joined - (portRef O (instanceRef CLK_000_D2_i)) - (portRef I0 (instanceRef un1_bgack_030_int_d_i_o2_0_1)) - )) - (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined - (portRef O (instanceRef cpu_est_i_1)) - (portRef I1 (instanceRef cpu_est_ns_0_0_a2_0_1)) - (portRef I1 (instanceRef cpu_est_ns_0_0_a3_0_2)) - (portRef I1 (instanceRef cpu_est_ns_i_0_o2_3)) - )) - (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined - (portRef O (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef cpu_est_ns_0_0_a2_1)) - (portRef I1 (instanceRef cpu_estse_i_a3)) - (portRef I0 (instanceRef cpu_est_ns_0_0_a3_0_2)) - )) - (net VMA_INT_i (joined - (portRef O (instanceRef VMA_INT_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_1_4)) - )) - (net VPA_D_i (joined - (portRef O (instanceRef VPA_D_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_4)) - (portRef I1 (instanceRef state_machine_un12_clk_000_d0_0_a3)) - )) - (net AS_000_DMA_i (joined - (portRef O (instanceRef AS_000_DMA_i)) - (portRef I0 (instanceRef state_machine_CLK_030_H_2_f0_i_o2)) - (portRef I0 (instanceRef state_machine_DS_000_DMA_3_0)) - (portRef I0 (instanceRef un3_dtack_i_a3_1)) - )) - (net nEXP_SPACE_i (joined - (portRef O (instanceRef nEXP_SPACE_i)) - (portRef I1 (instanceRef un1_bgack_030_int_d_i_o2)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0)) - (portRef I1 (instanceRef un3_dtack_i_a3)) + (portRef I1 (instanceRef cpu_est_ns_i_a3_0_3)) + (portRef I1 (instanceRef cpu_est_ns_0_a3_1)) + (portRef I1 (instanceRef state_machine_un10_clk_000_d0)) )) (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined (portRef O (instanceRef cpu_est_i_2)) - (portRef I0 (instanceRef cpu_est_ns_0_0_a3_0_1)) + (portRef I0 (instanceRef cpu_est_ns_0_a3_1)) )) - (net A0_i (joined - (portRef O (instanceRef I_146)) - (portRef I1 (instanceRef state_machine_UDS_000_INT_7_0_1)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_7_0_a3_1)) + (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined + (portRef O (instanceRef cpu_est_i_1)) + (portRef I1 (instanceRef cpu_est_ns_0_a3_1_1)) + (portRef I1 (instanceRef cpu_est_ns_0_a3_1_2)) + (portRef I1 (instanceRef cpu_est_ns_i_o2_3)) + (portRef I1 (instanceRef state_machine_un5_clk_000_d0_2)) )) - (net (rename SIZE_i_1 "SIZE_i[1]") (joined - (portRef O (instanceRef I_147)) - (portRef I1 (instanceRef state_machine_LDS_000_INT_7_0_a3)) + (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined + (portRef O (instanceRef cpu_est_i_0)) + (portRef I0 (instanceRef cpu_est_ns_0_a3_1_2)) + (portRef I1 (instanceRef cpu_est_ns_0_a2_1)) + (portRef I1 (instanceRef state_machine_un10_clk_000_d0_2)) + )) + (net VPA_D_i (joined + (portRef O (instanceRef VPA_D_i)) + (portRef I1 (instanceRef state_machine_un5_clk_000_d0_1)) + (portRef I0 (instanceRef state_machine_un57_clk_000_d0_1)) + )) + (net CLK_000_D0_i (joined + (portRef O (instanceRef CLK_000_D0_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_5)) + (portRef I0 (instanceRef un1_SM_AMIGA_9_i_a2)) + (portRef I0 (instanceRef SM_AMIGA_ns_a2_7)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_1)) + (portRef I0 (instanceRef state_machine_un5_clk_000_d0_1)) + (portRef I0 (instanceRef state_machine_un49_clk_000_d0_1)) + )) + (net (rename state_machine_un28_clk_030_i "state_machine.un28_clk_030_i") (joined + (portRef O (instanceRef state_machine_un28_clk_030_i)) + (portRef I1 (instanceRef FPU_CS_INT_1_sqmuxa)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_sqmuxa_2_0)) + )) + (net VMA_INT_i (joined + (portRef O (instanceRef VMA_INT_i)) + (portRef I1 (instanceRef state_machine_un57_clk_000_d0)) + )) + (net AS_030_i (joined + (portRef O (instanceRef I_151)) + (portRef I0 (instanceRef un1_AS_030_2)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa)) + (portRef I0 (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I0 (instanceRef un1_SM_AMIGA_12)) + (portRef I0 (instanceRef FPU_CS_INT_1_sqmuxa)) + (portRef I0 (instanceRef state_machine_un3_clk_030)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_sqmuxa_2)) + )) + (net AS_030_000_SYNC_0_sqmuxa_i (joined + (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa_2)) + )) + (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined + (portRef O (instanceRef SM_AMIGA_i_1)) + (portRef I1 (instanceRef un1_SM_AMIGA_4_0_o2)) + (portRef I1 (instanceRef un1_SM_AMIGA_10_i_o2)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_6)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa)) + (portRef I0 (instanceRef DSACK1_INT_0_n)) + )) + (net DTACK_D0_i (joined + (portRef O (instanceRef DTACK_D0_i)) + (portRef I0 (instanceRef state_machine_un51_clk_000_d0)) + )) + (net (rename A_i_19 "A_i[19]") (joined + (portRef O (instanceRef A_i_19)) + (portRef I1 (instanceRef state_machine_un28_clk_030_2)) + )) + (net (rename A_i_16 "A_i[16]") (joined + (portRef O (instanceRef A_i_16)) + (portRef I1 (instanceRef state_machine_un28_clk_030_1)) + )) + (net (rename A_i_18 "A_i[18]") (joined + (portRef O (instanceRef A_i_18)) + (portRef I0 (instanceRef state_machine_un28_clk_030_2)) + )) + (net (rename state_machine_un5_clk_000_d0_i_0 "state_machine.un5_clk_000_d0_i_0") (joined + (portRef O (instanceRef state_machine_un5_clk_000_d0_i)) + (portRef I0 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef state_machine_un12_clk_000_d0)) + )) + (net nEXP_SPACE_i (joined + (portRef O (instanceRef nEXP_SPACE_i)) + (portRef I0 (instanceRef un3_dtack_1)) + (portRef I1 (instanceRef un1_SM_AMIGA_10_i_a3_1)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0)) + )) + (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined + (portRef O (instanceRef SM_AMIGA_i_7)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_2)) + )) + (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined + (portRef O (instanceRef SM_AMIGA_i_0)) + (portRef I0 (instanceRef un1_SM_AMIGA_8_0_a2)) + (portRef I0 (instanceRef un1_SM_AMIGA_4_0_o2)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_1)) + )) + (net N_99_i (joined + (portRef O (instanceRef N_99_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_1)) + )) + (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined + (portRef O (instanceRef SM_AMIGA_i_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_6)) + )) + (net BGACK_030_INT_i (joined + (portRef O (instanceRef BGACK_030_INT_i)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1)) + (portRef I1 (instanceRef un3_dtack)) + (portRef OE (instanceRef RW)) + )) + (net BGACK_030_INT_D_i (joined + (portRef O (instanceRef BGACK_030_INT_D_i)) + (portRef I1 (instanceRef state_machine_un3_bgack_030_int_d)) + )) + (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined + (portRef O (instanceRef SM_AMIGA_i_6)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_2)) + (portRef I1 (instanceRef un1_SM_AMIGA_8_0_a2)) + )) + (net UDS_000_i (joined + (portRef O (instanceRef I_152)) + (portRef I1 (instanceRef state_machine_un31_bgack_030_int)) + )) + (net LDS_000_i (joined + (portRef O (instanceRef I_153)) + (portRef I0 (instanceRef state_machine_un31_bgack_030_int)) + )) + (net AS_000_DMA_0_sqmuxa_i (joined + (portRef O (instanceRef AS_000_DMA_0_sqmuxa_i)) + (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_1)) + (portRef I0 (instanceRef RW_li_m_1)) + )) + (net (rename state_machine_un8_bgack_030_int_i "state_machine.un8_bgack_030_int_i") (joined + (portRef O (instanceRef state_machine_un8_bgack_030_int_i)) + (portRef I0 (instanceRef AS_000_DMA_0_n)) + )) + (net (rename state_machine_un31_bgack_030_int_i "state_machine.un31_bgack_030_int_i") (joined + (portRef O (instanceRef state_machine_un31_bgack_030_int_i)) + (portRef I1 (instanceRef state_machine_SIZE_DMA_4_1)) + )) + (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined + (portRef O (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_2)) + )) + (net RW_i (joined + (portRef O (instanceRef I_154)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_2)) + (portRef I1 (instanceRef RW_li_m_1)) + )) + (net RW_000_i (joined + (portRef O (instanceRef I_155)) + (portRef I1 (instanceRef RW_000_i_m)) + (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_1)) + )) + (net UDS_000_INT_0_sqmuxa_i (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_i)) + (portRef I1 (instanceRef un1_AS_030_2_94)) + )) + (net UDS_000_INT_0_sqmuxa_1_i (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_i)) + (portRef I0 (instanceRef un1_AS_030_2_94)) + )) + (net AS_000_i (joined + (portRef O (instanceRef I_156)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1)) )) (net DS_030_i (joined - (portRef O (instanceRef I_148)) - (portRef I1 (instanceRef state_machine_UDS_000_INT_7_0)) - (portRef I1 (instanceRef state_machine_LDS_000_INT_7_0_1)) - (portRef I0 (instanceRef un1_AS_030_2_i_a3_1)) - (portRef I0 (instanceRef un1_AS_030_2_i_a3_0_1)) + (portRef O (instanceRef I_158)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_0)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_1)) )) - (net AS_030_000_SYNC_i (joined - (portRef O (instanceRef AS_030_000_SYNC_i)) - (portRef I1 (instanceRef un1_bgack_030_int_d_i_o2_0_1)) + (net (rename state_machine_un49_clk_000_d0_i "state_machine.un49_clk_000_d0_i") (joined + (portRef O (instanceRef state_machine_un49_clk_000_d0_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_4)) + )) + (net CLK_030_i (joined + (portRef O (instanceRef CLK_030_i)) + (portRef I1 (instanceRef state_machine_un24_bgack_030_int)) + (portRef I0 (instanceRef AS_000_DMA_0_sqmuxa)) + (portRef I1 (instanceRef state_machine_un3_clk_030)) + )) + (net (rename state_machine_un24_bgack_030_int_i "state_machine.un24_bgack_030_int_i") (joined + (portRef O (instanceRef state_machine_un24_bgack_030_int_i)) + (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa)) + )) + (net AS_000_DMA_i (joined + (portRef O (instanceRef AS_000_DMA_i)) + (portRef I0 (instanceRef state_machine_DS_000_DMA_3)) + (portRef I0 (instanceRef CLK_030_H_1_sqmuxa)) + (portRef I1 (instanceRef un3_dtack_1)) + )) + (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined + (portRef O (instanceRef SM_AMIGA_i_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_3)) )) (net (rename A_i_30 "A_i[30]") (joined (portRef O (instanceRef A_i_30)) @@ -1608,7 +1667,6 @@ (portRef S (instanceRef CLK_000_D0)) (portRef S (instanceRef CLK_000_D1)) (portRef S (instanceRef CLK_000_D2)) - (portRef S (instanceRef CLK_000_D3)) (portRef R (instanceRef CLK_OUT_INT)) (portRef R (instanceRef CLK_OUT_PRE_25)) (portRef R (instanceRef CLK_OUT_PRE_50)) @@ -1646,15 +1704,6 @@ (portRef O (instanceRef CLK_OUT_PRE_50_i)) (portRef D (instanceRef CLK_OUT_PRE_50)) )) - (net N_125_i (joined - (portRef O (instanceRef N_125_i)) - (portRef D (instanceRef SIZE_DMA_0)) - )) - (net N_114_i (joined - (portRef O (instanceRef N_114_i)) - (portRef I0 (instanceRef DSACK1_INT_0_m)) - (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_o3)) - )) (net FPU_CS_INT_i (joined (portRef O (instanceRef FPU_CS_INT_i)) (portRef OE (instanceRef BERR)) @@ -1665,9 +1714,9 @@ )) (net AS_030_c (joined (portRef O (instanceRef AS_030)) - (portRef I0 (instanceRef FPU_CS_INT_0_m)) - (portRef I0 (instanceRef AS_030_c_i)) - (portRef I0 (instanceRef state_machine_un10_bg_030_0_a3_1)) + (portRef I0 (instanceRef FPU_CS_INT_0_n)) + (portRef I0 (instanceRef I_151)) + (portRef I0 (instanceRef state_machine_un8_bg_030_1)) )) (net AS_030 (joined (portRef IO (instanceRef AS_030)) @@ -1675,7 +1724,7 @@ )) (net AS_000_c (joined (portRef O (instanceRef AS_000)) - (portRef I0 (instanceRef I_142)) + (portRef I0 (instanceRef I_156)) )) (net AS_000 (joined (portRef IO (instanceRef AS_000)) @@ -1683,7 +1732,7 @@ )) (net RW_000_c (joined (portRef O (instanceRef RW_000)) - (portRef I0 (instanceRef I_145)) + (portRef I0 (instanceRef I_155)) )) (net RW_000 (joined (portRef IO (instanceRef RW_000)) @@ -1691,7 +1740,7 @@ )) (net DS_030_c (joined (portRef O (instanceRef DS_030)) - (portRef I0 (instanceRef I_148)) + (portRef I0 (instanceRef I_158)) )) (net DS_030 (joined (portRef IO (instanceRef DS_030)) @@ -1699,9 +1748,9 @@ )) (net UDS_000_c (joined (portRef O (instanceRef UDS_000)) - (portRef I1 (instanceRef RW_000_INT_0_sqmuxa_i_o2)) - (portRef I0 (instanceRef I_143)) - (portRef I0 (instanceRef state_machine_A0_DMA_2_0_a3_1)) + (portRef I0 (instanceRef state_machine_A0_DMA_2)) + (portRef I1 (instanceRef state_machine_un10_bgack_030_int)) + (portRef I0 (instanceRef I_152)) )) (net UDS_000 (joined (portRef IO (instanceRef UDS_000)) @@ -1709,8 +1758,8 @@ )) (net LDS_000_c (joined (portRef O (instanceRef LDS_000)) - (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_o2)) - (portRef I0 (instanceRef I_144)) + (portRef I0 (instanceRef state_machine_un10_bgack_030_int)) + (portRef I0 (instanceRef I_153)) )) (net LDS_000 (joined (portRef IO (instanceRef LDS_000)) @@ -1718,7 +1767,7 @@ )) (net (rename SIZE_c_0 "SIZE_c[0]") (joined (portRef O (instanceRef SIZE_0)) - (portRef I1 (instanceRef state_machine_LDS_000_INT_7_0_a3_1)) + (portRef I0 (instanceRef state_machine_un25_clk_000_d0_1)) )) (net (rename SIZE_0 "SIZE[0]") (joined (portRef IO (instanceRef SIZE_0)) @@ -1726,7 +1775,7 @@ )) (net (rename SIZE_c_1 "SIZE_c[1]") (joined (portRef O (instanceRef SIZE_1)) - (portRef I0 (instanceRef I_147)) + (portRef I0 (instanceRef SIZE_c_i_1)) )) (net (rename SIZE_1 "SIZE[1]") (joined (portRef (member size 0)) @@ -1742,7 +1791,7 @@ )) (net (rename A_c_17 "A_c[17]") (joined (portRef O (instanceRef A_17)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_3)) + (portRef I0 (instanceRef state_machine_un28_clk_030_1)) )) (net (rename A_17 "A[17]") (joined (portRef (member a 14)) @@ -1862,7 +1911,7 @@ )) (net A0_c (joined (portRef O (instanceRef A0)) - (portRef I0 (instanceRef I_146)) + (portRef I0 (instanceRef A0_c_i)) )) (net A0 (joined (portRef IO (instanceRef A0)) @@ -1871,8 +1920,9 @@ (net nEXP_SPACE_c (joined (portRef O (instanceRef nEXP_SPACE)) (portRef I0 (instanceRef nEXP_SPACE_i)) - (portRef I1 (instanceRef state_machine_un10_bg_030_0_a3_2)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3)) + (portRef I0 (instanceRef un1_amiga_bus_enable_int5_0_o2)) + (portRef I1 (instanceRef state_machine_un8_bg_030_2)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa_2_0)) (portRef OE (instanceRef DSACK1)) )) (net nEXP_SPACE (joined @@ -1907,9 +1957,9 @@ )) (net BGACK_000_c (joined (portRef O (instanceRef BGACK_000)) - (portRef I0 (instanceRef state_machine_un6_bgack_000_0)) (portRef I0 (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_1)) + (portRef I0 (instanceRef state_machine_un6_bgack_000)) + (portRef I1 (instanceRef state_machine_un28_clk_030_3)) )) (net BGACK_000 (joined (portRef BGACK_000) @@ -1917,11 +1967,9 @@ )) (net CLK_030_c (joined (portRef O (instanceRef CLK_030)) - (portRef I0 (instanceRef un1_as_030_000_sync8_1_i_a3)) - (portRef I1 (instanceRef state_machine_CLK_030_H_2_f0_i_o2)) - (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i)) (portRef I0 (instanceRef CLK_030_i)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_1)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa)) + (portRef I1 (instanceRef CLK_030_H_1_sqmuxa)) )) (net CLK_030 (joined (portRef CLK_030) @@ -1929,7 +1977,7 @@ )) (net CLK_000_c (joined (portRef O (instanceRef CLK_000)) - (portRef I1 (instanceRef state_machine_un10_bg_030_0_a3_1)) + (portRef I1 (instanceRef state_machine_un8_bg_030_1)) (portRef D (instanceRef CLK_000_D0)) )) (net CLK_000 (joined @@ -1948,7 +1996,6 @@ (portRef CLK (instanceRef CLK_000_D0)) (portRef CLK (instanceRef CLK_000_D1)) (portRef CLK (instanceRef CLK_000_D2)) - (portRef CLK (instanceRef CLK_000_D3)) (portRef CLK (instanceRef CLK_030_H)) (portRef CLK (instanceRef CLK_OUT_INT)) (portRef CLK (instanceRef CLK_OUT_PRE_25)) @@ -2006,7 +2053,7 @@ )) (net (rename IPL_030_c_0 "IPL_030_c[0]") (joined (portRef Q (instanceRef IPL_030DFFSH_0)) - (portRef I0 (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__n)) (portRef I0 (instanceRef IPL_030_0)) )) (net (rename IPL_030_0 "IPL_030[0]") (joined @@ -2015,7 +2062,7 @@ )) (net (rename IPL_030_c_1 "IPL_030_c[1]") (joined (portRef Q (instanceRef IPL_030DFFSH_1)) - (portRef I0 (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__n)) (portRef I0 (instanceRef IPL_030_1)) )) (net (rename IPL_030_1 "IPL_030[1]") (joined @@ -2024,7 +2071,7 @@ )) (net (rename IPL_030_c_2 "IPL_030_c[2]") (joined (portRef Q (instanceRef IPL_030DFFSH_2)) - (portRef I0 (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__n)) (portRef I0 (instanceRef IPL_030_2)) )) (net (rename IPL_030_2 "IPL_030[2]") (joined @@ -2033,7 +2080,7 @@ )) (net (rename IPL_c_0 "IPL_c[0]") (joined (portRef O (instanceRef IPL_0)) - (portRef I0 (instanceRef IPL_030_0_0__n)) + (portRef I0 (instanceRef IPL_030_0_0__m)) )) (net (rename IPL_0 "IPL[0]") (joined (portRef (member ipl 2)) @@ -2041,7 +2088,7 @@ )) (net (rename IPL_c_1 "IPL_c[1]") (joined (portRef O (instanceRef IPL_1)) - (portRef I0 (instanceRef IPL_030_0_1__n)) + (portRef I0 (instanceRef IPL_030_0_1__m)) )) (net (rename IPL_1 "IPL[1]") (joined (portRef (member ipl 1)) @@ -2049,7 +2096,7 @@ )) (net (rename IPL_c_2 "IPL_c[2]") (joined (portRef O (instanceRef IPL_2)) - (portRef I0 (instanceRef IPL_030_0_2__n)) + (portRef I0 (instanceRef IPL_030_0_2__m)) )) (net (rename IPL_2 "IPL[2]") (joined (portRef (member ipl 0)) @@ -2115,11 +2162,9 @@ )) (net RW_c (joined (portRef O (instanceRef RW)) - (portRef I1 (instanceRef state_machine_UDS_000_INT_7_0_m3_m)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_7_0_m3_r)) - (portRef I0 (instanceRef I_141)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0_1)) - (portRef I1 (instanceRef un1_AS_030_2_i_a3)) + (portRef I0 (instanceRef I_154)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1_0)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_2)) )) (net RW (joined (portRef IO (instanceRef RW)) @@ -2127,7 +2172,7 @@ )) (net (rename FC_c_0 "FC_c[0]") (joined (portRef O (instanceRef FC_0)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_3)) + (portRef I1 (instanceRef state_machine_un28_clk_030_5)) )) (net (rename FC_0 "FC[0]") (joined (portRef (member fc 1)) @@ -2135,7 +2180,7 @@ )) (net (rename FC_c_1 "FC_c[1]") (joined (portRef O (instanceRef FC_1)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_5)) + (portRef I0 (instanceRef state_machine_un28_clk_030_3)) )) (net (rename FC_1 "FC[1]") (joined (portRef (member fc 0)) @@ -2146,7 +2191,7 @@ (portRef AMIGA_BUS_ENABLE) )) (net AMIGA_BUS_DATA_DIR_c (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_i)) + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_i)) (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR)) )) (net AMIGA_BUS_DATA_DIR (joined @@ -2161,696 +2206,508 @@ (portRef O (instanceRef CIIN)) (portRef CIIN) )) + (net (rename state_machine_un3_clk_000_d1_i "state_machine.un3_clk_000_d1_i") (joined + (portRef O (instanceRef state_machine_un3_clk_000_d1_i)) + (portRef I1 (instanceRef state_machine_un6_bgack_000)) + )) (net (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (joined - (portRef O (instanceRef state_machine_un6_bgack_000_0)) - (portRef I0 (instanceRef state_machine_un6_bgack_000_0_i)) - )) - (net N_194_0 (joined - (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i)) - (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_i)) - )) - (net N_119_i (joined - (portRef O (instanceRef N_119_i)) - (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i)) - )) - (net N_120_i (joined - (portRef O (instanceRef N_120_i)) - (portRef I1 (instanceRef RW_000_INT_0_sqmuxa_i)) - )) - (net N_197_0 (joined - (portRef O (instanceRef RW_000_INT_0_sqmuxa_i)) - (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_i)) - )) - (net (rename state_machine_DS_000_DMA_3_0 "state_machine.DS_000_DMA_3_0") (joined - (portRef O (instanceRef state_machine_DS_000_DMA_3_0)) - (portRef I0 (instanceRef state_machine_DS_000_DMA_3_0_i)) - )) - (net N_171_i (joined - (portRef O (instanceRef N_171_i)) - (portRef I1 (instanceRef state_machine_SIZE_DMA_4_0_1)) - )) - (net (rename state_machine_SIZE_DMA_4_0_1 "state_machine.SIZE_DMA_4_0[1]") (joined - (portRef O (instanceRef state_machine_SIZE_DMA_4_0_1)) - (portRef I0 (instanceRef state_machine_SIZE_DMA_4_0_i_1)) - )) - (net N_130_i (joined - (portRef O (instanceRef N_130_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_3)) - )) - (net N_68_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_0_3)) - (portRef D (instanceRef SM_AMIGA_4)) - )) - (net N_131_i (joined - (portRef O (instanceRef N_131_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_4)) - )) - (net N_132_i (joined - (portRef O (instanceRef N_132_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_4)) - )) - (net N_45_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_4)) - (portRef D (instanceRef SM_AMIGA_3)) - )) - (net N_133_i (joined - (portRef O (instanceRef N_133_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_5)) - )) - (net N_134_i (joined - (portRef O (instanceRef N_134_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_5)) - )) - (net (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (joined - (portRef O (instanceRef SM_AMIGA_ns_0_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_i_5)) - )) - (net N_135_i (joined - (portRef O (instanceRef N_135_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_7)) - )) - (net N_73_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_0_7)) - (portRef D (instanceRef SM_AMIGA_0)) - )) - (net N_139_i (joined - (portRef O (instanceRef N_139_i)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0)) - )) - (net N_140_i (joined - (portRef O (instanceRef N_140_i)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0)) - )) - (net AMIGA_BUS_DATA_DIR_c_0 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_i)) - )) - (net N_141_i (joined - (portRef O (instanceRef N_141_i)) - (portRef I0 (instanceRef state_machine_CLK_030_H_2_f0_i)) - )) - (net N_52_i (joined - (portRef O (instanceRef state_machine_CLK_030_H_2_f0_i)) - (portRef I0 (instanceRef CLK_030_H_0_m)) - )) - (net N_143_i (joined - (portRef O (instanceRef N_143_i)) - (portRef I1 (instanceRef state_machine_RW_000_INT_7_iv_0)) - )) - (net N_142_i (joined - (portRef O (instanceRef N_142_i)) - (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv_0)) - )) - (net (rename state_machine_RW_000_INT_7_iv_i "state_machine.RW_000_INT_7_iv_i") (joined - (portRef O (instanceRef state_machine_RW_000_INT_7_iv_0)) - (portRef I0 (instanceRef RW_000_INT_0_m)) - )) - (net N_62_0 (joined - (portRef O (instanceRef RW_000_INT_0_sqmuxa_i_o2)) - (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_o2_i)) - )) - (net N_161_i (joined - (portRef O (instanceRef N_161_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_4)) - )) - (net N_155_i (joined - (portRef O (instanceRef N_155_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_4)) - )) - (net N_63_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_4)) - )) - (net N_66_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o2_0_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_0_i_4)) - (portRef I1 (instanceRef un1_AS_030_2_i_a3_0_1)) - )) - (net N_76_i (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2)) - (portRef I1 (instanceRef un1_as_030_000_sync8_1_i_a3)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_i)) - )) - (net CLK_000_D1_i (joined - (portRef O (instanceRef CLK_000_D1_i)) - (portRef I1 (instanceRef state_machine_un3_clk_000_d1_0_o2)) - )) - (net N_77_i (joined - (portRef O (instanceRef state_machine_un3_clk_000_d1_0_o2)) - (portRef I0 (instanceRef cpu_estse_i_a3_0)) - (portRef I0 (instanceRef state_machine_un3_clk_000_d1_0_o2_i)) - )) - (net N_79_0 (joined - (portRef O (instanceRef state_machine_RW_000_INT_7_iv_0_o2)) - (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv_0_o2_i)) - )) - (net N_199_0 (joined - (portRef O (instanceRef RW_000_INT_0_sqmuxa_i_o2_0)) - (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_o2_0_i)) - )) - (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined - (portRef O (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_o2_6)) - )) - (net N_201_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_0_o2_6)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_o2_i_6)) - )) - (net N_203_0 (joined - (portRef O (instanceRef state_machine_CLK_030_H_2_f0_i_o2)) - (portRef I0 (instanceRef state_machine_CLK_030_H_2_f0_i_o2_i)) + (portRef O (instanceRef state_machine_un6_bgack_000)) + (portRef I0 (instanceRef state_machine_un6_bgack_000_i)) )) (net (rename cpu_est_ns_0_1 "cpu_est_ns_0[1]") (joined - (portRef O (instanceRef cpu_est_ns_0_0_1)) - (portRef I0 (instanceRef cpu_est_ns_0_0_i_1)) + (portRef O (instanceRef cpu_est_ns_0_1)) + (portRef I0 (instanceRef cpu_est_ns_0_i_1)) )) - (net N_167_i (joined - (portRef O (instanceRef N_167_i)) - (portRef I0 (instanceRef cpu_est_ns_0_0_2_1)) + (net N_159_i (joined + (portRef O (instanceRef N_159_i)) + (portRef I1 (instanceRef cpu_est_ns_i_3)) )) - (net N_170_i (joined - (portRef O (instanceRef N_170_i)) - (portRef I1 (instanceRef cpu_est_ns_0_0_2_1)) - )) - (net N_136_i (joined - (portRef O (instanceRef N_136_i)) - (portRef I0 (instanceRef cpu_est_ns_0_0_1_1)) - )) - (net N_137_i (joined - (portRef O (instanceRef N_137_i)) - (portRef I1 (instanceRef cpu_est_ns_0_0_1_1)) - )) - (net N_202_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_0_o2_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_i_1)) - )) - (net N_200_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_a2_0_o2_2)) - (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_o2_i_2)) - )) - (net N_169_i (joined - (portRef O (instanceRef N_169_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_o3_0)) - )) - (net N_198_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_0_o3_0)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_1)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_0)) - )) - (net N_168_i (joined - (portRef O (instanceRef N_168_i)) - (portRef I1 (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_o3)) - )) - (net un1_DSACK1_INT_0_sqmuxa_3_0 (joined - (portRef O (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_o3)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i)) - (portRef I0 (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_o3_i)) - )) - (net N_90_i (joined - (portRef O (instanceRef cpu_est_ns_i_0_o2_3)) - (portRef I0 (instanceRef cpu_est_ns_i_0_o2_i_3)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_1_4)) - )) - (net AS_030_c_i (joined - (portRef O (instanceRef AS_030_c_i)) - (portRef I0 (instanceRef un1_as_030_000_sync8_1_i)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_o3)) - (portRef I1 (instanceRef un1_AS_030_2_i_1)) - )) - (net N_75_i (joined - (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_o3)) - (portRef I0 (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_o3)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_o3_i)) - )) - (net N_71_i (joined - (portRef O (instanceRef un1_bgack_030_int_d_i_o2)) - (portRef I1 (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_a2)) - (portRef I0 (instanceRef un1_bgack_030_int_d_i_o2_i)) - )) - (net N_69_i (joined - (portRef O (instanceRef un1_bgack_030_int_d_i_o2_0)) - (portRef I0 (instanceRef un1_DSACK1_INT_0_sqmuxa_3_0_a2)) - (portRef I0 (instanceRef un1_bgack_030_int_d_i_o2_0_i)) - (portRef I1 (instanceRef un1_bgack_030_int_d_i_a3)) - )) - (net N_67_i (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa_i_o2)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i_o2_i)) - (portRef I1 (instanceRef un1_AS_030_2_i_a3_1)) - )) - (net N_150_i (joined - (portRef O (instanceRef N_150_i)) - (portRef I0 (instanceRef cpu_estse_i)) - )) - (net N_151_i (joined - (portRef O (instanceRef N_151_i)) - (portRef I1 (instanceRef cpu_estse_i)) - )) - (net N_60_i (joined - (portRef O (instanceRef cpu_estse_i)) - (portRef D (instanceRef cpu_est_0)) - )) - (net N_145_i (joined - (portRef O (instanceRef N_145_i)) - (portRef I1 (instanceRef cpu_est_ns_0_0_1_2)) - )) - (net N_146_i (joined - (portRef O (instanceRef N_146_i)) - (portRef I1 (instanceRef cpu_est_ns_0_0_2)) - )) - (net N_147_i (joined - (portRef O (instanceRef N_147_i)) - (portRef I0 (instanceRef cpu_est_ns_0_0_1_2)) - )) - (net (rename cpu_est_ns_0_2 "cpu_est_ns_0[2]") (joined - (portRef O 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(instanceRef cpu_est_ns_i_o2_3)) + (portRef I0 (instanceRef cpu_est_ns_i_o2_i_3)) + (portRef I1 (instanceRef state_machine_un57_clk_000_d0_1)) )) - (net N_65_i (joined - (portRef O (instanceRef SM_AMIGA_ns_i_0_1)) - (portRef D (instanceRef SM_AMIGA_6)) + (net N_153_i (joined + (portRef O (instanceRef N_153_i)) + (portRef I1 (instanceRef cpu_est_ns_0_1_1)) )) - (net N_128_i (joined - (portRef O (instanceRef N_128_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_0)) + (net N_152_i (joined + (portRef O (instanceRef N_152_i)) + (portRef I0 (instanceRef cpu_est_ns_0_1_1)) )) - (net (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (joined - (portRef O (instanceRef SM_AMIGA_ns_0_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_i_0)) + (net N_160_i (joined + (portRef O (instanceRef N_160_i)) + (portRef I1 (instanceRef cpu_est_ns_0_2_1)) )) - (net N_70_i (joined - (portRef O (instanceRef N_70_i)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_7_0_1)) - (portRef I1 (instanceRef state_machine_LDS_000_INT_7_0)) + (net N_154_i (joined + (portRef O (instanceRef N_154_i)) + (portRef I0 (instanceRef cpu_est_ns_0_2_1)) )) - (net N_124_i (joined - (portRef O (instanceRef N_124_i)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_7_0_1)) + (net (rename state_machine_un10_clk_000_d0_2_i "state_machine.un10_clk_000_d0_2_i") (joined + (portRef O (instanceRef state_machine_un10_clk_000_d0_2_i)) + (portRef I1 (instanceRef cpu_est_ns_0_2)) )) - (net (rename state_machine_LDS_000_INT_7_0 "state_machine.LDS_000_INT_7_0") (joined - (portRef O (instanceRef state_machine_LDS_000_INT_7_0)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_7_0_i)) + (net N_156_i (joined + (portRef O (instanceRef N_156_i)) + (portRef I1 (instanceRef cpu_est_ns_0_1_2)) )) - (net (rename state_machine_UDS_000_INT_7_0 "state_machine.UDS_000_INT_7_0") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_7_0)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_7_0_i)) + (net N_157_i (joined + (portRef O (instanceRef N_157_i)) + (portRef I0 (instanceRef cpu_est_ns_0_1_2)) )) - (net N_122_i (joined - (portRef O (instanceRef N_122_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i)) - )) - (net N_30_0 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_i)) - )) - (net N_121_i (joined - (portRef O (instanceRef N_121_i)) - (portRef I1 (instanceRef un1_as_030_000_sync8_1_i)) - )) - (net N_28_0 (joined - (portRef O (instanceRef un1_as_030_000_sync8_1_i)) - (portRef I0 (instanceRef un1_as_030_000_sync8_1_i_i)) - )) - (net N_117_i (joined - (portRef O (instanceRef N_117_i)) - (portRef I1 (instanceRef un1_AS_030_2_i)) - )) - (net N_118_i (joined - (portRef O (instanceRef N_118_i)) - (portRef I0 (instanceRef un1_AS_030_2_i_1)) - )) - (net N_196_0 (joined - (portRef O (instanceRef un1_AS_030_2_i)) - (portRef I0 (instanceRef un1_AS_030_2_i_i)) - )) - (net N_116_i (joined - (portRef O (instanceRef N_116_i)) - (portRef I1 (instanceRef un1_bgack_030_int_d_i)) - )) - (net N_195_i (joined - (portRef O (instanceRef un1_bgack_030_int_d_i)) - (portRef I0 (instanceRef avec_exp_0_n)) - )) - (net BG_030_c_i (joined - (portRef O (instanceRef BG_030_c_i)) - (portRef I0 (instanceRef state_machine_un10_bg_030_0)) - )) - (net N_115_i (joined - (portRef O (instanceRef N_115_i)) - (portRef I1 (instanceRef state_machine_un10_bg_030_0)) - )) - (net (rename state_machine_un10_bg_030_0 "state_machine.un10_bg_030_0") (joined - (portRef O (instanceRef state_machine_un10_bg_030_0)) - (portRef I0 (instanceRef state_machine_un10_bg_030_0_i)) - )) - (net N_193_0 (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa_i)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i_i)) - )) - (net N_204_i (joined - (portRef O (instanceRef N_204_i)) - (portRef I0 (instanceRef state_machine_un12_clk_000_d0_0)) + (net (rename cpu_est_ns_0_2 "cpu_est_ns_0[2]") (joined + (portRef O (instanceRef cpu_est_ns_0_2)) + (portRef I0 (instanceRef cpu_est_ns_0_i_2)) )) (net (rename state_machine_un10_clk_000_d0_i "state_machine.un10_clk_000_d0_i") (joined (portRef O (instanceRef state_machine_un10_clk_000_d0_i)) - (portRef I1 (instanceRef state_machine_un12_clk_000_d0_0)) + (portRef I1 (instanceRef state_machine_un12_clk_000_d0)) )) (net (rename state_machine_un12_clk_000_d0_0 "state_machine.un12_clk_000_d0_0") (joined - (portRef O (instanceRef state_machine_un12_clk_000_d0_0)) - (portRef I0 (instanceRef state_machine_un12_clk_000_d0_0_i)) + (portRef O (instanceRef state_machine_un12_clk_000_d0)) + (portRef I0 (instanceRef state_machine_un12_clk_000_d0_i)) )) - (net N_69_i_1 (joined - (portRef O (instanceRef un1_bgack_030_int_d_i_o2_0_1)) - (portRef I0 (instanceRef un1_bgack_030_int_d_i_o2_0)) + (net FPU_CS_INT_1_sqmuxa_i (joined + (portRef O (instanceRef FPU_CS_INT_1_sqmuxa_i)) + (portRef I0 (instanceRef un1_as_030_000_sync8_1)) )) - (net N_76_i_1 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_1)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_4)) + (net un1_as_030_000_sync8_1_0 (joined + (portRef O (instanceRef un1_as_030_000_sync8_1)) + (portRef I0 (instanceRef un1_as_030_000_sync8_1_i)) )) - (net N_76_i_2 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_2)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_4)) + (net AS_030_000_SYNC_0_sqmuxa_2_i (joined + (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa_2_i)) + (portRef I0 (instanceRef un1_as_030_000_sync8)) )) - (net N_76_i_3 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_3)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_5)) + (net un1_as_030_000_sync8_0 (joined + (portRef O (instanceRef un1_as_030_000_sync8)) + (portRef I0 (instanceRef un1_as_030_000_sync8_i)) )) - (net N_76_i_4 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_4)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2)) + (net un1_SM_AMIGA_12_0 (joined + (portRef O (instanceRef un1_SM_AMIGA_12)) + (portRef I0 (instanceRef un1_SM_AMIGA_12_i)) )) - (net N_76_i_5 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2_5)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_o2)) + (net (rename state_machine_un3_clk_030_i "state_machine.un3_clk_030_i") (joined + (portRef O (instanceRef state_machine_un3_clk_030)) + (portRef I0 (instanceRef state_machine_un3_clk_030_i_0)) )) - (net N_220_1 (joined + (net (rename state_machine_un57_clk_000_d0_i "state_machine.un57_clk_000_d0_i") (joined + (portRef O (instanceRef state_machine_un57_clk_000_d0_i)) + (portRef I1 (instanceRef state_machine_un53_clk_000_d0)) + )) + (net (rename state_machine_un51_clk_000_d0_i "state_machine.un51_clk_000_d0_i") (joined + (portRef O (instanceRef state_machine_un51_clk_000_d0_i)) + (portRef I0 (instanceRef state_machine_un53_clk_000_d0)) + )) + (net (rename state_machine_un53_clk_000_d0_0 "state_machine.un53_clk_000_d0_0") (joined + (portRef O (instanceRef state_machine_un53_clk_000_d0)) + (portRef I0 (instanceRef state_machine_un53_clk_000_d0_i)) + )) + (net (rename state_machine_un3_bgack_030_int_d_i "state_machine.un3_bgack_030_int_d_i") (joined + (portRef O (instanceRef state_machine_un3_bgack_030_int_d_i)) + (portRef I0 (instanceRef un1_bgack_030_int_d_1)) + )) + (net un1_bgack_030_int_d_0 (joined + (portRef O (instanceRef un1_bgack_030_int_d)) + (portRef I0 (instanceRef un1_bgack_030_int_d_i)) + )) + (net AMIGA_BUS_ENABLE_INT_3_sqmuxa_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa_i)) + (portRef I1 (instanceRef un1_bgack_030_int_d)) + )) + (net AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_i)) + (portRef I1 (instanceRef un1_bgack_030_int_d_1)) + )) + (net N_86_0 (joined + (portRef O (instanceRef un1_SM_AMIGA_4_0_o2)) + (portRef I0 (instanceRef un1_SM_AMIGA_4_0_o2_i)) + )) + (net N_101_i (joined + (portRef O (instanceRef N_101_i)) + (portRef I0 (instanceRef un1_SM_AMIGA_10_i_o2)) + )) + (net N_85_i (joined + (portRef O (instanceRef un1_SM_AMIGA_10_i_o2)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa)) + (portRef I1 (instanceRef un1_SM_AMIGA_12)) + )) + (net N_84_0 (joined + (portRef O (instanceRef un1_amiga_bus_enable_int5_0_o2)) + (portRef I0 (instanceRef un1_amiga_bus_enable_int5_0_o2_i)) + )) + (net N_97_i (joined + (portRef O (instanceRef N_97_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_6)) + )) + (net N_74_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_6)) + (portRef D (instanceRef SM_AMIGA_1)) + )) + (net N_96_i (joined + (portRef O (instanceRef N_96_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_5)) + )) + (net N_95_i (joined + (portRef O (instanceRef N_95_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_5)) + )) + (net (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (joined + (portRef O (instanceRef SM_AMIGA_ns_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_5)) + )) + (net N_88_i (joined + (portRef O (instanceRef N_88_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_0)) + )) + (net N_89_i (joined + (portRef O (instanceRef N_89_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0)) + )) + (net (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0)) + )) + (net AMIGA_BUS_ENABLE_INT_2_sqmuxa_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_i)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa)) + )) + (net AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_2_i)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa)) + )) + (net un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_0 (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_INT_2_sqmuxa_i)) + )) + (net BG_030_c_i (joined + (portRef O (instanceRef BG_030_c_i)) + (portRef I0 (instanceRef state_machine_un10_bg_030)) + )) + (net (rename state_machine_un8_bg_030_i "state_machine.un8_bg_030_i") (joined + (portRef O (instanceRef state_machine_un8_bg_030_i)) + (portRef I1 (instanceRef state_machine_un10_bg_030)) + )) + (net (rename state_machine_un10_bg_030_0 "state_machine.un10_bg_030_0") (joined + (portRef O (instanceRef state_machine_un10_bg_030)) + (portRef I0 (instanceRef state_machine_un10_bg_030_i)) + )) + (net (rename state_machine_un5_bgack_030_int_d_i "state_machine.un5_bgack_030_int_d_i") (joined + (portRef O (instanceRef state_machine_un5_bgack_030_int_d)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_3_sqmuxa)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_2)) + )) + (net N_59_0 (joined + (portRef O (instanceRef RW_000_INT_0_sqmuxa_i)) + (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_i)) + )) + (net (rename state_machine_un10_bgack_030_int_0 "state_machine.un10_bgack_030_int_0") (joined + (portRef O (instanceRef state_machine_un10_bgack_030_int)) + (portRef I0 (instanceRef state_machine_un10_bgack_030_int_i)) + )) + (net N_181_i (joined + (portRef O (instanceRef N_181_i)) + (portRef I1 (instanceRef state_machine_UDS_000_INT_7)) + (portRef I0 (instanceRef state_machine_LDS_000_INT_7)) + )) + (net A0_c_i (joined + (portRef O (instanceRef A0_c_i)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_7)) + (portRef I1 (instanceRef state_machine_un25_clk_000_d0_1)) + )) + (net (rename state_machine_UDS_000_INT_7_0 "state_machine.UDS_000_INT_7_0") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_7)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_7_i)) + )) + (net (rename state_machine_LDS_000_INT_7_0 "state_machine.LDS_000_INT_7_0") (joined + (portRef O (instanceRef state_machine_LDS_000_INT_7)) + (portRef I0 (instanceRef state_machine_LDS_000_INT_7_i)) + )) + (net (rename state_machine_SIZE_DMA_4_0_0 "state_machine.SIZE_DMA_4_0[0]") (joined + (portRef O (instanceRef state_machine_SIZE_DMA_4_0)) + (portRef I0 (instanceRef state_machine_SIZE_DMA_4_i_0)) + )) + (net (rename state_machine_SIZE_DMA_4_0_1 "state_machine.SIZE_DMA_4_0[1]") (joined + (portRef O (instanceRef state_machine_SIZE_DMA_4_1)) + (portRef I0 (instanceRef state_machine_SIZE_DMA_4_i_1)) + )) + (net N_91_i (joined + (portRef O (instanceRef N_91_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_2)) + )) + (net N_68_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_2)) + (portRef D (instanceRef SM_AMIGA_5)) + )) + (net N_100_i (joined + (portRef O (instanceRef N_100_i)) + (portRef I1 (instanceRef un1_SM_AMIGA_8_0)) + )) + (net un1_SM_AMIGA_8_0 (joined + (portRef O (instanceRef un1_SM_AMIGA_8_0)) + (portRef I0 (instanceRef un1_SM_AMIGA_8_0_i)) + )) + (net N_164_i (joined + (portRef O (instanceRef N_164_i)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0)) + )) + (net N_163_i (joined + (portRef O (instanceRef N_163_i)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0)) + )) + (net AMIGA_BUS_DATA_DIR_c_0 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_i)) + )) + (net RW_000_i_m_i (joined + (portRef O (instanceRef RW_000_i_m_i)) + (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv)) + )) + (net RW_li_m_i (joined + (portRef O (instanceRef RW_li_m_i)) + (portRef I1 (instanceRef state_machine_RW_000_INT_7_iv)) + )) + (net (rename state_machine_RW_000_INT_7_iv_i "state_machine.RW_000_INT_7_iv_i") (joined + (portRef O (instanceRef state_machine_RW_000_INT_7_iv)) + (portRef I0 (instanceRef RW_000_INT_0_n)) + )) + (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined + (portRef O (instanceRef SIZE_c_i_1)) + (portRef I1 (instanceRef state_machine_un25_clk_000_d0)) + )) + (net (rename state_machine_un25_clk_000_d0_i "state_machine.un25_clk_000_d0_i") (joined + (portRef O (instanceRef state_machine_un25_clk_000_d0)) + (portRef I0 (instanceRef state_machine_un25_clk_000_d0_i_0)) + )) + (net N_90_i (joined + (portRef O (instanceRef N_90_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_1)) + )) + (net N_66_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_1)) + (portRef D (instanceRef SM_AMIGA_6)) + )) + (net N_94_i (joined + (portRef O (instanceRef N_94_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_4)) + )) + (net N_93_i (joined + (portRef O (instanceRef N_93_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_4)) + )) + (net (rename SM_AMIGA_ns_0_4 "SM_AMIGA_ns_0[4]") (joined + (portRef O (instanceRef SM_AMIGA_ns_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_4)) + )) + (net N_87_0 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o3_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_i_1)) + )) + (net (rename state_machine_DS_000_DMA_3_0 "state_machine.DS_000_DMA_3_0") (joined + (portRef O (instanceRef state_machine_DS_000_DMA_3)) + (portRef I0 (instanceRef state_machine_DS_000_DMA_3_i)) + )) + (net CLK_030_H_i (joined + (portRef O (instanceRef CLK_030_H_i)) + (portRef I1 (instanceRef state_machine_CLK_030_H_2_f1)) + )) + (net CLK_030_H_1_sqmuxa_i (joined + (portRef O (instanceRef CLK_030_H_1_sqmuxa_i)) + (portRef I0 (instanceRef state_machine_CLK_030_H_2_f1)) + )) + (net (rename state_machine_CLK_030_H_2_f1_0 "state_machine.CLK_030_H_2_f1_0") (joined + (portRef O (instanceRef state_machine_CLK_030_H_2_f1)) + (portRef I0 (instanceRef state_machine_CLK_030_H_2_f1_i)) + )) + (net un3_dtack_i (joined + (portRef O (instanceRef un3_dtack)) + (portRef OE (instanceRef A0)) + (portRef OE (instanceRef AS_030)) + (portRef OE (instanceRef DS_030)) + (portRef OE (instanceRef DTACK)) + (portRef OE (instanceRef SIZE_0)) + (portRef OE (instanceRef SIZE_1)) + )) + (net N_92_i (joined + (portRef O (instanceRef N_92_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_3)) + )) + (net N_70_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_3)) + (portRef D (instanceRef SM_AMIGA_4)) + )) + (net un3_dtack_i_1 (joined + (portRef O (instanceRef un3_dtack_1)) + (portRef I0 (instanceRef un3_dtack)) + )) + (net (rename state_machine_un25_clk_000_d0_i_1 "state_machine.un25_clk_000_d0_i_1") (joined + (portRef O (instanceRef state_machine_un25_clk_000_d0_1)) + (portRef I0 (instanceRef state_machine_un25_clk_000_d0)) + )) + (net (rename cpu_est_ns_0_1_2 "cpu_est_ns_0_1[2]") (joined + (portRef O (instanceRef cpu_est_ns_0_1_2)) + (portRef I0 (instanceRef cpu_est_ns_0_2)) + )) + (net N_210_1 (joined (portRef O (instanceRef un4_ciin_1)) (portRef I0 (instanceRef un4_ciin)) )) - (net N_220_2 (joined + (net N_210_2 (joined (portRef O (instanceRef un4_ciin_2)) (portRef I1 (instanceRef un4_ciin)) )) - (net N_230_1 (joined + (net N_220_1 (joined (portRef O (instanceRef un8_ciin_1)) (portRef I0 (instanceRef un8_ciin_5)) )) - (net N_230_2 (joined + (net N_220_2 (joined (portRef O (instanceRef un8_ciin_2)) (portRef I1 (instanceRef un8_ciin_5)) )) - (net N_230_3 (joined + (net N_220_3 (joined (portRef O (instanceRef un8_ciin_3)) (portRef I0 (instanceRef un8_ciin_6)) )) - (net N_230_4 (joined + (net N_220_4 (joined (portRef O (instanceRef un8_ciin_4)) (portRef I1 (instanceRef un8_ciin_6)) )) - (net N_230_5 (joined + (net N_220_5 (joined (portRef O (instanceRef un8_ciin_5)) (portRef I0 (instanceRef un8_ciin)) )) - (net N_230_6 (joined + (net N_220_6 (joined (portRef O (instanceRef un8_ciin_6)) (portRef I1 (instanceRef un8_ciin)) )) - (net (rename cpu_est_ns_0_1_1 "cpu_est_ns_0_1[1]") (joined - (portRef O (instanceRef cpu_est_ns_0_0_1_1)) - (portRef I0 (instanceRef cpu_est_ns_0_0_1)) + (net DS_000_DMA_1_sqmuxa_1 (joined + (portRef O (instanceRef DS_000_DMA_1_sqmuxa_1)) + (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa)) )) - (net (rename cpu_est_ns_0_2_1 "cpu_est_ns_0_2[1]") (joined - (portRef O (instanceRef cpu_est_ns_0_0_2_1)) - (portRef I1 (instanceRef cpu_est_ns_0_0_1)) + (net UDS_000_INT_0_sqmuxa_1_1 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_1)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1)) )) - (net N_122_1 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_1)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_3)) + (net UDS_000_INT_0_sqmuxa_1_2 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_2)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1)) )) - (net N_122_2 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_2)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_3)) + (net UDS_000_INT_0_sqmuxa_1_0 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_0)) + (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa)) )) - (net N_122_3 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3_3)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_1_i_a3)) + (net UDS_000_INT_0_sqmuxa_2 (joined + (portRef O (instanceRef UDS_000_INT_0_sqmuxa_2)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa)) )) - (net N_115_1 (joined - (portRef O (instanceRef state_machine_un10_bg_030_0_a3_1)) - (portRef I0 (instanceRef state_machine_un10_bg_030_0_a3)) + (net N_164_1_0 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0_1_0)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_a3_0)) )) - (net N_115_2 (joined - (portRef O (instanceRef state_machine_un10_bg_030_0_a3_2)) - (portRef I1 (instanceRef state_machine_un10_bg_030_0_a3)) - )) - (net (rename state_machine_un10_clk_000_d0_1 "state_machine.un10_clk_000_d0_1") (joined - (portRef O (instanceRef state_machine_un12_clk_000_d0_0_a3_0_1)) - (portRef I0 (instanceRef state_machine_un12_clk_000_d0_0_a3_0)) - )) - (net (rename state_machine_un10_clk_000_d0_2 "state_machine.un10_clk_000_d0_2") (joined - (portRef O (instanceRef state_machine_un12_clk_000_d0_0_a3_0_2)) - (portRef I1 (instanceRef state_machine_un12_clk_000_d0_0_a3_0)) - )) - (net N_133_1 (joined - (portRef O (instanceRef SM_AMIGA_ns_0_a3_1_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_5)) - )) - (net N_133_2 (joined - (portRef O (instanceRef SM_AMIGA_ns_0_a3_2_5)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_5)) - )) - (net N_143_1 (joined - (portRef O (instanceRef state_machine_RW_000_INT_7_iv_0_a3_0_1)) - (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv_0_a3_0)) - )) - (net (rename cpu_est_ns_0_1_2 "cpu_est_ns_0_1[2]") (joined - (portRef O (instanceRef cpu_est_ns_0_0_1_2)) - (portRef I0 (instanceRef cpu_est_ns_0_0_2)) - )) - (net N_55_0_1 (joined - (portRef O (instanceRef DS_000_DMA_1_sqmuxa_i_1)) - (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_i)) - )) - (net (rename state_machine_LDS_000_INT_7_0_1 "state_machine.LDS_000_INT_7_0_1") (joined - (portRef O (instanceRef state_machine_LDS_000_INT_7_0_1)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_7_0)) - )) - (net (rename state_machine_UDS_000_INT_7_0_1 "state_machine.UDS_000_INT_7_0_1") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_7_0_1)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_7_0)) - )) - (net N_196_0_1 (joined - (portRef O (instanceRef un1_AS_030_2_i_1)) - (portRef I0 (instanceRef un1_AS_030_2_i)) - )) - (net N_155_1 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a2_1_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_4)) - )) - (net N_148_1 (joined - (portRef O (instanceRef un3_dtack_i_a3_1)) - (portRef I0 (instanceRef un3_dtack_i_a3)) - )) - (net N_142_1 (joined - (portRef O (instanceRef state_machine_RW_000_INT_7_iv_0_a3_1)) - (portRef I0 (instanceRef state_machine_RW_000_INT_7_iv_0_a3)) - )) - (net N_140_1 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0_1)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0)) - )) - (net N_132_1 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_a3_0_1_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_0_4)) - )) - (net N_124_1 (joined - (portRef O (instanceRef state_machine_LDS_000_INT_7_0_a3_1)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_7_0_a3)) - )) - (net (rename state_machine_A0_DMA_2_1 "state_machine.A0_DMA_2_1") (joined - (portRef O (instanceRef state_machine_A0_DMA_2_0_a3_1)) - (portRef I0 (instanceRef state_machine_A0_DMA_2_0_a3)) - )) - (net N_120_1 (joined - (portRef O (instanceRef RW_000_INT_0_sqmuxa_i_a3_0_1)) - (portRef I0 (instanceRef RW_000_INT_0_sqmuxa_i_a3_0)) - )) - (net N_118_1 (joined - (portRef O (instanceRef un1_AS_030_2_i_a3_0_1)) - (portRef I0 (instanceRef un1_AS_030_2_i_a3_0)) - )) - (net N_117_1 (joined - (portRef O (instanceRef un1_AS_030_2_i_a3_1)) - (portRef I0 (instanceRef un1_AS_030_2_i_a3)) - )) - (net N_116_1 (joined - (portRef O (instanceRef un1_bgack_030_int_d_i_a3_1)) - (portRef I0 (instanceRef un1_bgack_030_int_d_i_a3)) + (net RW_li_m_1 (joined + (portRef O (instanceRef RW_li_m_1)) + (portRef I0 (instanceRef RW_li_m)) )) (net AMIGA_BUS_ENABLE_INT_2_sqmuxa_1 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_0_a3)) + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa)) )) - (net N_204_1 (joined - (portRef O (instanceRef state_machine_un12_clk_000_d0_0_a3_1)) - (portRef I0 (instanceRef state_machine_un12_clk_000_d0_0_a3)) + (net AMIGA_BUS_ENABLE_INT_2_sqmuxa_2 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa_2)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_2_sqmuxa)) )) - (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined - (portRef O (instanceRef BGACK_030_INT_0_r)) - (portRef I1 (instanceRef BGACK_030_INT_0_n)) + (net N_101_1 (joined + (portRef O (instanceRef un1_SM_AMIGA_10_i_a3_1)) + (portRef I0 (instanceRef un1_SM_AMIGA_10_i_a3)) )) - (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined - (portRef O (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_p)) + (net un1_bgack_030_int_d_0_1 (joined + (portRef O (instanceRef un1_bgack_030_int_d_1)) + (portRef I0 (instanceRef un1_bgack_030_int_d)) )) - (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined - (portRef O (instanceRef BGACK_030_INT_0_n)) - (portRef I1 (instanceRef BGACK_030_INT_0_p)) + (net (rename state_machine_un8_bg_030_1 "state_machine.un8_bg_030_1") (joined + (portRef O (instanceRef state_machine_un8_bg_030_1)) + (portRef I0 (instanceRef state_machine_un8_bg_030)) )) - (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined - (portRef O (instanceRef AS_000_DMA_0_r)) - (portRef I1 (instanceRef AS_000_DMA_0_n)) + (net (rename state_machine_un8_bg_030_2 "state_machine.un8_bg_030_2") (joined + (portRef O (instanceRef state_machine_un8_bg_030_2)) + (portRef I1 (instanceRef state_machine_un8_bg_030)) )) - (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined - (portRef O (instanceRef AS_000_DMA_0_m)) - (portRef I0 (instanceRef AS_000_DMA_0_p)) + (net (rename state_machine_un57_clk_000_d0_1 "state_machine.un57_clk_000_d0_1") (joined + (portRef O (instanceRef state_machine_un57_clk_000_d0_1)) + (portRef I0 (instanceRef state_machine_un57_clk_000_d0)) )) - (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined - (portRef O (instanceRef AS_000_DMA_0_n)) - (portRef I1 (instanceRef AS_000_DMA_0_p)) + (net (rename state_machine_un49_clk_000_d0_1 "state_machine.un49_clk_000_d0_1") (joined + (portRef O (instanceRef state_machine_un49_clk_000_d0_1)) + (portRef I0 (instanceRef state_machine_un49_clk_000_d0)) )) - (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined - (portRef O (instanceRef DS_000_DMA_0_r)) - (portRef I1 (instanceRef DS_000_DMA_0_n)) + (net AS_030_000_SYNC_0_sqmuxa_1 (joined + (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_sqmuxa)) )) - (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined - (portRef O (instanceRef DS_000_DMA_0_m)) - (portRef I0 (instanceRef DS_000_DMA_0_p)) + (net AS_030_000_SYNC_0_sqmuxa_2_0 (joined + (portRef O (instanceRef AS_030_000_SYNC_0_sqmuxa_2_0)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_sqmuxa)) )) - (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined - (portRef O (instanceRef DS_000_DMA_0_n)) - (portRef I1 (instanceRef DS_000_DMA_0_p)) + (net (rename state_machine_un28_clk_030_1 "state_machine.un28_clk_030_1") (joined + (portRef O (instanceRef state_machine_un28_clk_030_1)) + (portRef I0 (instanceRef state_machine_un28_clk_030_4)) )) - (net (rename CLK_030_H_0_un3 "CLK_030_H_0.un3") (joined - (portRef O (instanceRef CLK_030_H_0_r)) - (portRef I1 (instanceRef CLK_030_H_0_n)) + (net (rename state_machine_un28_clk_030_2 "state_machine.un28_clk_030_2") (joined + (portRef O (instanceRef state_machine_un28_clk_030_2)) + (portRef I1 (instanceRef state_machine_un28_clk_030_4)) )) - (net (rename CLK_030_H_0_un1 "CLK_030_H_0.un1") (joined - (portRef O (instanceRef CLK_030_H_0_m)) - (portRef I0 (instanceRef CLK_030_H_0_p)) + (net (rename state_machine_un28_clk_030_3 "state_machine.un28_clk_030_3") (joined + (portRef O (instanceRef state_machine_un28_clk_030_3)) + (portRef I0 (instanceRef state_machine_un28_clk_030_5)) )) - (net (rename CLK_030_H_0_un0 "CLK_030_H_0.un0") (joined - (portRef O (instanceRef CLK_030_H_0_n)) - (portRef I1 (instanceRef CLK_030_H_0_p)) + (net (rename state_machine_un28_clk_030_4 "state_machine.un28_clk_030_4") (joined + (portRef O (instanceRef state_machine_un28_clk_030_4)) + (portRef I0 (instanceRef state_machine_un28_clk_030)) )) - (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined - (portRef O (instanceRef RW_000_INT_0_r)) - (portRef I1 (instanceRef RW_000_INT_0_n)) + (net (rename state_machine_un28_clk_030_5 "state_machine.un28_clk_030_5") (joined + (portRef O (instanceRef state_machine_un28_clk_030_5)) + (portRef I1 (instanceRef state_machine_un28_clk_030)) )) - (net (rename RW_000_INT_0_un1 "RW_000_INT_0.un1") (joined - (portRef O (instanceRef RW_000_INT_0_m)) - (portRef I0 (instanceRef RW_000_INT_0_p)) + (net (rename state_machine_un5_clk_000_d0_1 "state_machine.un5_clk_000_d0_1") (joined + (portRef O (instanceRef state_machine_un5_clk_000_d0_1)) + (portRef I0 (instanceRef state_machine_un5_clk_000_d0)) )) - (net (rename RW_000_INT_0_un0 "RW_000_INT_0.un0") (joined - (portRef O (instanceRef RW_000_INT_0_n)) - (portRef I1 (instanceRef RW_000_INT_0_p)) + (net (rename state_machine_un5_clk_000_d0_2 "state_machine.un5_clk_000_d0_2") (joined + (portRef O (instanceRef state_machine_un5_clk_000_d0_2)) + (portRef I1 (instanceRef state_machine_un5_clk_000_d0)) )) - (net (rename state_machine_UDS_000_INT_7_0_m3_un3 "state_machine.UDS_000_INT_7_0_m3.un3") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_7_0_m3_r)) - (portRef I1 (instanceRef state_machine_UDS_000_INT_7_0_m3_n)) + (net (rename state_machine_un10_clk_000_d0_1 "state_machine.un10_clk_000_d0_1") (joined + (portRef O (instanceRef state_machine_un10_clk_000_d0_1)) + (portRef I0 (instanceRef state_machine_un10_clk_000_d0_3)) )) - (net (rename state_machine_UDS_000_INT_7_0_m3_un1 "state_machine.UDS_000_INT_7_0_m3.un1") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_7_0_m3_m)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_7_0_m3_p)) + (net (rename state_machine_un10_clk_000_d0_2_0 "state_machine.un10_clk_000_d0_2_0") (joined + (portRef O (instanceRef state_machine_un10_clk_000_d0_2)) + (portRef I1 (instanceRef state_machine_un10_clk_000_d0_3)) )) - (net (rename state_machine_UDS_000_INT_7_0_m3_un0 "state_machine.UDS_000_INT_7_0_m3.un0") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_7_0_m3_n)) - (portRef I1 (instanceRef state_machine_UDS_000_INT_7_0_m3_p)) + (net (rename state_machine_un10_clk_000_d0_3 "state_machine.un10_clk_000_d0_3") (joined + (portRef O (instanceRef state_machine_un10_clk_000_d0_3)) + (portRef I0 (instanceRef state_machine_un10_clk_000_d0)) )) - (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined - (portRef O (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef IPL_030_0_0__n)) + (net (rename cpu_est_ns_0_1_1 "cpu_est_ns_0_1[1]") (joined + (portRef O (instanceRef cpu_est_ns_0_1_1)) + (portRef I0 (instanceRef cpu_est_ns_0_1)) )) - (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined - (portRef O (instanceRef IPL_030_0_0__m)) - (portRef I0 (instanceRef IPL_030_0_0__p)) + (net (rename cpu_est_ns_0_2_1 "cpu_est_ns_0_2[1]") (joined + (portRef O (instanceRef cpu_est_ns_0_2_1)) + (portRef I1 (instanceRef cpu_est_ns_0_1)) )) - (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined - (portRef O (instanceRef IPL_030_0_0__n)) - (portRef I1 (instanceRef IPL_030_0_0__p)) - )) - (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined - (portRef O (instanceRef IPL_030_0_1__r)) - (portRef I1 (instanceRef IPL_030_0_1__n)) - )) - (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined - (portRef O (instanceRef IPL_030_0_1__m)) - (portRef I0 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined - (portRef O (instanceRef IPL_030_0_1__n)) - (portRef I1 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined - (portRef O (instanceRef IPL_030_0_2__r)) - (portRef I1 (instanceRef IPL_030_0_2__n)) - )) - (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined - (portRef O (instanceRef IPL_030_0_2__m)) - (portRef I0 (instanceRef IPL_030_0_2__p)) - )) - (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined - (portRef O (instanceRef IPL_030_0_2__n)) - (portRef I1 (instanceRef IPL_030_0_2__p)) - )) - (net (rename cpu_estse_0_un3 "cpu_estse_0.un3") (joined - (portRef O (instanceRef cpu_estse_0_r)) - (portRef I1 (instanceRef cpu_estse_0_n)) - )) - (net (rename cpu_estse_0_un1 "cpu_estse_0.un1") (joined - (portRef O (instanceRef cpu_estse_0_m)) - (portRef I0 (instanceRef cpu_estse_0_p)) - )) - (net (rename cpu_estse_0_un0 "cpu_estse_0.un0") (joined - (portRef O (instanceRef cpu_estse_0_n)) - (portRef I1 (instanceRef cpu_estse_0_p)) - )) - (net (rename cpu_estse_1_un3 "cpu_estse_1.un3") (joined - (portRef O (instanceRef cpu_estse_1_r)) - (portRef I1 (instanceRef cpu_estse_1_n)) - )) - (net (rename cpu_estse_1_un1 "cpu_estse_1.un1") (joined - (portRef O (instanceRef cpu_estse_1_m)) - (portRef I0 (instanceRef cpu_estse_1_p)) - )) - (net (rename cpu_estse_1_un0 "cpu_estse_1.un0") (joined - (portRef O (instanceRef cpu_estse_1_n)) - (portRef I1 (instanceRef cpu_estse_1_p)) + (net (rename state_machine_un28_clk_000_d1_1 "state_machine.un28_clk_000_d1_1") (joined + (portRef O (instanceRef state_machine_un28_clk_000_d1_1)) + (portRef I0 (instanceRef state_machine_un28_clk_000_d1)) )) (net (rename cpu_estse_2_un3 "cpu_estse_2.un3") (joined (portRef O (instanceRef cpu_estse_2_r)) @@ -2864,6 +2721,78 @@ (portRef O (instanceRef cpu_estse_2_n)) (portRef I1 (instanceRef cpu_estse_2_p)) )) + (net (rename cpu_estse_1_un3 "cpu_estse_1.un3") (joined + (portRef O (instanceRef cpu_estse_1_r)) + (portRef I1 (instanceRef cpu_estse_1_n)) + )) + (net (rename cpu_estse_1_un1 "cpu_estse_1.un1") (joined + (portRef O (instanceRef cpu_estse_1_m)) + (portRef I0 (instanceRef cpu_estse_1_p)) + )) + (net (rename cpu_estse_1_un0 "cpu_estse_1.un0") (joined + (portRef O (instanceRef cpu_estse_1_n)) + (portRef I1 (instanceRef cpu_estse_1_p)) + )) + (net (rename cpu_estse_0_un3 "cpu_estse_0.un3") (joined + (portRef O (instanceRef cpu_estse_0_r)) + (portRef I1 (instanceRef cpu_estse_0_n)) + )) + (net (rename cpu_estse_0_un1 "cpu_estse_0.un1") (joined + (portRef O (instanceRef cpu_estse_0_m)) + (portRef I0 (instanceRef cpu_estse_0_p)) + )) + (net (rename cpu_estse_0_un0 "cpu_estse_0.un0") (joined + (portRef O (instanceRef cpu_estse_0_n)) + (portRef I1 (instanceRef cpu_estse_0_p)) + )) + (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined + (portRef O (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_2__n)) + )) + (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined + (portRef O (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__p)) + )) + (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined + (portRef O (instanceRef IPL_030_0_2__n)) + (portRef I1 (instanceRef IPL_030_0_2__p)) + )) + (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined + (portRef O (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_1__n)) + )) + (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined + (portRef O (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__p)) + )) + (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined + (portRef O (instanceRef IPL_030_0_1__n)) + (portRef I1 (instanceRef IPL_030_0_1__p)) + )) + (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined + (portRef O (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef IPL_030_0_0__n)) + )) + (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined + (portRef O (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__p)) + )) + (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined + (portRef O (instanceRef IPL_030_0_0__n)) + (portRef I1 (instanceRef IPL_030_0_0__p)) + )) + (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined + (portRef O (instanceRef BGACK_030_INT_0_r)) + (portRef I1 (instanceRef BGACK_030_INT_0_n)) + )) + (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined + (portRef O (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_p)) + )) + (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined + (portRef O (instanceRef BGACK_030_INT_0_n)) + (portRef I1 (instanceRef BGACK_030_INT_0_p)) + )) (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined (portRef O (instanceRef AS_030_000_SYNC_0_r)) (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) @@ -2876,30 +2805,6 @@ (portRef O (instanceRef AS_030_000_SYNC_0_n)) (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) )) - (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined - (portRef O (instanceRef UDS_000_INT_0_r)) - (portRef I1 (instanceRef UDS_000_INT_0_n)) - )) - (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined - (portRef O (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined - (portRef O (instanceRef UDS_000_INT_0_n)) - (portRef I1 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined - (portRef O (instanceRef LDS_000_INT_0_r)) - (portRef I1 (instanceRef LDS_000_INT_0_n)) - )) - (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined - (portRef O (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_p)) - )) - (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined - (portRef O (instanceRef LDS_000_INT_0_n)) - (portRef I1 (instanceRef LDS_000_INT_0_p)) - )) (net (rename FPU_CS_INT_0_un3 "FPU_CS_INT_0.un3") (joined (portRef O (instanceRef FPU_CS_INT_0_r)) (portRef I1 (instanceRef FPU_CS_INT_0_n)) @@ -2912,30 +2817,6 @@ (portRef O (instanceRef FPU_CS_INT_0_n)) (portRef I1 (instanceRef FPU_CS_INT_0_p)) )) - (net (rename avec_exp_0_un3 "avec_exp_0.un3") (joined - (portRef O (instanceRef avec_exp_0_r)) - (portRef I1 (instanceRef avec_exp_0_n)) - )) - (net (rename avec_exp_0_un1 "avec_exp_0.un1") (joined - (portRef O (instanceRef avec_exp_0_m)) - (portRef I0 (instanceRef avec_exp_0_p)) - )) - (net (rename avec_exp_0_un0 "avec_exp_0.un0") (joined - (portRef O (instanceRef avec_exp_0_n)) - (portRef I1 (instanceRef avec_exp_0_p)) - )) - (net (rename BG_000_0_un3 "BG_000_0.un3") (joined - (portRef O (instanceRef BG_000_0_r)) - (portRef I1 (instanceRef BG_000_0_n)) - )) - (net (rename BG_000_0_un1 "BG_000_0.un1") (joined - (portRef O (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_p)) - )) - (net (rename BG_000_0_un0 "BG_000_0.un0") (joined - (portRef O (instanceRef BG_000_0_n)) - (portRef I1 (instanceRef BG_000_0_p)) - )) (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined (portRef O (instanceRef AS_000_INT_0_r)) (portRef I1 (instanceRef AS_000_INT_0_n)) @@ -2972,6 +2853,102 @@ (portRef O (instanceRef VMA_INT_0_n)) (portRef I1 (instanceRef VMA_INT_0_p)) )) + (net (rename avec_exp_0_un3 "avec_exp_0.un3") (joined + (portRef O (instanceRef avec_exp_0_r)) + (portRef I1 (instanceRef avec_exp_0_n)) + )) + (net (rename avec_exp_0_un1 "avec_exp_0.un1") (joined + (portRef O (instanceRef avec_exp_0_m)) + (portRef I0 (instanceRef avec_exp_0_p)) + )) + (net (rename avec_exp_0_un0 "avec_exp_0.un0") (joined + (portRef O (instanceRef avec_exp_0_n)) + (portRef I1 (instanceRef avec_exp_0_p)) + )) + (net (rename BG_000_0_un3 "BG_000_0.un3") (joined + (portRef O (instanceRef BG_000_0_r)) + (portRef I1 (instanceRef BG_000_0_n)) + )) + (net (rename BG_000_0_un1 "BG_000_0.un1") (joined + (portRef O (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_p)) + )) + (net (rename BG_000_0_un0 "BG_000_0.un0") (joined + (portRef O (instanceRef BG_000_0_n)) + (portRef I1 (instanceRef BG_000_0_p)) + )) + (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined + (portRef O (instanceRef LDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_n)) + )) + (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined + (portRef O (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_p)) + )) + (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined + (portRef O (instanceRef LDS_000_INT_0_n)) + (portRef I1 (instanceRef LDS_000_INT_0_p)) + )) + (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined + (portRef O (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef UDS_000_INT_0_n)) + )) + (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined + (portRef O (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined + (portRef O (instanceRef UDS_000_INT_0_n)) + (portRef I1 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined + (portRef O (instanceRef RW_000_INT_0_r)) + (portRef I1 (instanceRef RW_000_INT_0_n)) + )) + (net (rename RW_000_INT_0_un1 "RW_000_INT_0.un1") (joined + (portRef O (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_p)) + )) + (net (rename RW_000_INT_0_un0 "RW_000_INT_0.un0") (joined + (portRef O (instanceRef RW_000_INT_0_n)) + (portRef I1 (instanceRef RW_000_INT_0_p)) + )) + (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined + (portRef O (instanceRef AS_000_DMA_0_r)) + (portRef I1 (instanceRef AS_000_DMA_0_n)) + )) + (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined + (portRef O (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_000_DMA_0_p)) + )) + (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined + (portRef O (instanceRef AS_000_DMA_0_n)) + (portRef I1 (instanceRef AS_000_DMA_0_p)) + )) + (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined + (portRef O (instanceRef DS_000_DMA_0_r)) + (portRef I1 (instanceRef DS_000_DMA_0_n)) + )) + (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined + (portRef O (instanceRef DS_000_DMA_0_m)) + (portRef I0 (instanceRef DS_000_DMA_0_p)) + )) + (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined + (portRef O (instanceRef DS_000_DMA_0_n)) + (portRef I1 (instanceRef DS_000_DMA_0_p)) + )) + (net (rename CLK_030_H_0_un3 "CLK_030_H_0.un3") (joined + (portRef O (instanceRef CLK_030_H_0_r)) + (portRef I1 (instanceRef CLK_030_H_0_n)) + )) + (net (rename CLK_030_H_0_un1 "CLK_030_H_0.un1") (joined + (portRef O (instanceRef CLK_030_H_0_m)) + (portRef I0 (instanceRef CLK_030_H_0_p)) + )) + (net (rename CLK_030_H_0_un0 "CLK_030_H_0.un0") (joined + (portRef O (instanceRef CLK_030_H_0_n)) + (portRef I1 (instanceRef CLK_030_H_0_p)) + )) ) (property orig_inst_of (string "BUS68030")) ) diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index e1cd2cd..60e4a44 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj -#-- Written on Sun Jun 01 01:03:18 2014 +#-- Written on Sat Jun 07 23:03:13 2014 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index 245e4b6..5810250 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -312,167 +312,125 @@ F@:@U64d:::6d.qj:vqQt_1Az_q hA_p pRmWqtvQqz_A1h_ q Ap_Wpm;H NR03sDs_FHNoMl"CRqtvQqz_A1h_ q Ap_Wpm"F; RU@@::6c4c:6:Bc:QRQhBhQQ;H NR03sDs_FHNoMl"CRBhQQ"o; -MMRk41_7q4Bi_aQh_#j_JGlkN;_d -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh.N; +M_Rh4N; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_ -d;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh;_c +.;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh;_d RNM3P#NCC_M0D_VN4o#Rn.6;M -oR6h_;M +oRch_;M NRN3#PMC_CV0_D#No46R.no; -M_RhnN; +M_Rh6N; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_ -(;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh;_U +n;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh;_( RNM3P#NCC_M0D_VN4o#Rn.6;M -oRgh_;M +oRUh_;M NRN3#PMC_CV0_D#No46R.no; -M_Rh4 -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh4_4;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh4 -.;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhd_4;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh4 -c;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh6_4;M 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RNH3Ds0_HFsolMNCOR"bCk_#;0" @@ -580,10 +532,10 @@ RNH3lV#_#0F0OR"bCk_#c0R"N; HVR3#0l_NCLD#"0RjjjjRjjjjjsj4jjRjs4jj4j4R4jj44sjjjjR4sjjj44jRjj444sj4jjR4s4jj444R4j44js444jRjs4j44j4R44j44s4j4jR4sjj4444R4444;s" RNH3lV#_HFsolMNCOR"bCk_#;0" RNH3lV#_N#00CCso;R4 -RNH3HFso#HM0lMNCOR'bCk_#j0r:94j's; +RNH3N#00lC_NHbbM"oRRjRRjjjjjjjjj-4R>jRjjMj\RjRRjjjjjjjj4-jR>jRj4Mj\RjRRjjjjj4jjj-jR>jRj4M4\RjRRjjjjjjj4j-jR>4RjjMj\RjRRjjjjjj4jj-jR>4RjjM4\RjRRjjjj4jjjj-jR>4Rj4Mj\RjRRj4jjjjjjj-jR>4Rj4M4\RjRRjjj4jjjjj-jR>jR44Mj\RjRRjj4jjjjjj-jR>jR44M4\RjRR4jjjjjjjj-jR>4R4jMj\R4RRjjjjjjjjj-jR>4R44M4\"s; RU@@:j4.::dc4:.jd4n+.b:Ok#_C0:rj4Rj9fjj:ROlNEwR7wR)]blsHRkOb_0C#r -.9SOT=bCk_#.0r97 -S=kOb_0C#__M#C9r. +49SOT=bCk_#40r97 +S=kOb_0C#__M#C9r4 pSBip=Bi1_mZOQ_ =S))_1aHN; HsR30_DC04FR;H @@ -596,9 +548,9 @@ NR#3VlF_0#"0RO_bkCR#0c NR#3Vls_FHNoMl"CRO_bkC"#0;H NR#3Vl0_#Ns0CC4oR;H NRs3FHMoH#N0Ml'CRO_bkCr#0jj:49 -';s@R@U.:4jc:d:j4.:+dn4O.:bCk_#j0r:94jR:fjjNRlO7ERw]w)RHbslbROk#_C09rd -=STO_bkCr#0dS9 -7b=Ok#_C0#_M_dCr9B +';s@R@U.:4jc:d:j4.:+dn4O.:bCk_#j0r:94jR:fjjNRlO7ERw]w)RHbslbROk#_C09r. +=STO_bkCr#0.S9 +7b=Ok#_C0#_M_.Cr9B SpBi=pmi_1_ZQO) S=a)1_ H;N3HRsC0D_R0F4N; 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+HVR3#0l_NCLD#"0RjjjjRjjjjjsj4jjRjs4jj4j4R4jj44sjjjjR4sjjj44jRjj444sj4jjR4s4jj444R4j44js444jRjs4j44j4R44j44s4j4jR4sjj4444R4444;s" +RNH3lV#_HFsolMNCOR"bCk_#;0" +RNH3lV#_N#00CCso;R4 +RNH3HFso#HM0lMNCOR'bCk_#j0r:94j's; +RU@@:.4j::dn4:j.d4U+.u:Qpd_jj:r.jf9RjR:jlENORw7w1b]RsRHlQ_upj7djw]w1r +j9SQT=ujp_dOj_r +j9Sh7=_ +4nSiBp=iBp_Zm1Q +_OS)1=1Ha_;H +NR03sDs_FHNoMl"CRQ_upj"dj;H +NRM3kVOsN_8HMCjGR;R +s@:@U4:j.d4n:jd.:U.+4:pQu_jjdrj.:9jRf:ljRNROE71ww]sRbHQlRujp_dwj7wr1]4S9 +Tu=Qpd_jjr_O4S9 +7_=h4S( +B=piB_pimQ1Z_SO +11=)a;_H +RNH3Ds0_HFsolMNCQR"ujp_d;j" +RNH3VkMs_NOHCM8G;R4 +@sR@4U:jd.:nj:4.U:d+:4.Q_upjrdj.9:jR:fjjNRlO7ERw]w1RHbsluRQpd_jjw7w1.]r9T +S=pQu_jjd_.Or97 +S=4h_UB SpBi=pmi_1_ZQO1 S=a)1_ H;N3HRs_0DFosHMCNlRu"Qpd_jj ";N3HRksMVNHO_MG8CR -j;s@R@Uj:4.n:d:.4j:+dU4Q.:ujp_d.jr:Rj9fjj:ROlNEwR7wR1]blsHRpQu_jjd71ww]9r4 -=STQ_upj_djO9r4 -=S7h(_4 -pSBip=Bi1_mZOQ_ -=S1)_1aHN; -HsR30FD_sMHoNRlC"pQu_jjd"N; -HkR3MNVsOM_H8RCG4s; -RU@@:.4j::dn4:j.d4U+.u:Qpd_jj:r.jf9RjR:jlENORw7w1b]RsRHlQ_upj7djw]w1r -.9SQT=ujp_dOj_r -.9Sh7=_ -4USiBp=iBp_Zm1Q -_OS)1=1Ha_;H -NR03sDs_FHNoMl"CRQ_upj"dj;H -NRM3kVOsN_8HMC.GR;R -s@:@U.:nc..(:ncc:c.+4:_1vqtvQq:rj(f9RjR:jlENORw7w1b]RsRHl1qv_vqQtr -(9S1T=vv_qQrtq(S9 -7v=1_QqvtMq_#9rj -pSBip=Bi1_mZOQ_ -=S1)_1aHN; -HsR30_DC04FR;H -NRM#$_lV#_RH8".(4g4d.."g4;H -NR03sDs_FHNoMl"CR1qv_vqQt"N; -HVR3#Vl_s#Fl01R"vv_qQRtqd -";N3HRV_#l00F#Rv"1_QqvtUqR"N; -HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N; -HVR3#Fl_sMHoNRlC"_1vqtvQq -";N3HRV_#l#00NCosCR -4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R -s@:@Ud:.cc.:dcg:4+:4.1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtqnS9 -Tv=1_Qqvtnqr97 -S=nh_6 -_HSiBp=iBp_Zm1Q -_OS))=1Ha_;H -NR03sD0C_F;R4 -RNH#_$MV_#lH"8R(g4.d..4g;4" -RNH3Ds0_HFsolMNC1R"vv_qQ"tq;H -NR#3Vls_VF0l#Rv"1_QqvtdqR"N; -HVR3#0l_FR#0"_1vqtvQq"RU;H -NR#3VlN_0L#DC0jR"j4jRjjjjjsjjjRj4jj4jjjjjsjj4R4jjjjjjj4sj4jRjjj4jj4jsjjjRj4jjjsjj4Rj4jjjjjj4jsj44Rjjjj4jjj4s44jRjjjjjj"4s;H -NR#3Vls_FHNoMl"CR1qv_vqQt"N; -HVR3##l_0CN0sRCo4N; -HFR3sHHoMM#0NRlC'_1vqtvQq:rj(;9' -@sR@dU:.cg::gd.:+.j41.:vv_qQrtqj9:(R:fjjNRlO7ERw]w)RHbslvR1_Qqvt6qr9T -S=_1vqtvQq9r6 -=S71qv_vqQt_rM#.S9 +.;s@R@Un:.c(:.:c.n:+cc41.:vv_qQrtqj9:(R:fjjNRlO7ERw]w1RHbslvR1_Qqvt(qr9T +S=_1vqtvQq9r( +=S71qv_vqQt_rM#jS9 B=piB_pimQ1Z_SO -)1=)a;_H +11=)a;_H RNH3Ds0CF_0R 4;N#HR$VM_#Hl_8(R"4d.g.g4.4 ";N3HRs_0DFosHMCNlRv"1_Qqvt;q" @@ -696,9 +628,9 @@ RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j RNH3lV#_HFsolMNC1R"vv_qQ"tq;H NR#3Vl0_#Ns0CC4oR;H NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9 -';s@R@U6:dj::cd:6j.4j+.v:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9rc +';s@R@U.:dc::cd:.c44g+.v:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9rn =ST1qv_vqQtr -c9Sh7=__nUHB +n9Sh7=__nnHB SpBi=pmi_1_ZQO) S=a)1_ H;N3HRsC0D_R0F4N; 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-R:fjjNRlOQERhbeRsRHlO_bkC##0C3_jsm -S=kOb_0C##jC_3dkM -jSQ=(h_(s; -R:fjjNRlOqERhR7.blsHRkOb_0C##jC_3Sl -mb=Ok#_C0_#CjM3k4Q -Sjb=Ok#_C09r4 -4SQ=(h_(s; -R:fjjNRlOqERhR7.blsHRkOb_0C##jC_3SM -mb=Ok#_C0_#CjM3kjQ -Sjb=Ok#_C0#_Mr -49S=Q4O_bkC##0C3_jk;Md -fsRjR:jlENOR.m)RHbslbROk#_C0_#Cj -3bSOm=bCk_#M0_#r_C4S9 -QOj=bCk_#C0#_kj3MS4 -QO4=bCk_#C0#_kj3M -j;sjRf:ljRNROEQRheblsHRkOb_0C##4C_3Ss -mb=Ok#_C0_#C4M3kdQ -Sj_=h( -(;sjRf:ljRNROEq.h7RHbslbROk#_C0_#C4 -3lSOm=bCk_#C0#_k43MS4 -QOj=bCk_#.0r9Q -S4_=h( -(;sjRf:ljRNROEq.h7RHbslbROk#_C0_#C4 -3MSOm=bCk_#C0#_k43MSj -QOj=bCk_#M0_#9r. -4SQ=kOb_0C##4C_3dkM;R -sfjj:ROlNE)Rm.sRbHOlRbCk_#C0#_b43 -=SmO_bkC_#0MC#_r -.9S=QjO_bkC##0C3_4k -M4S=Q4O_bkC##0C3_4k;Mj -fsRjR:jlENOReQhRHbslbROk#_C0_#C. -3sSOm=bCk_#C0#_k.3MSd -Qhj=_;(( -fsRjR:jlENOR7qh.sRbHOlRbCk_#C0#_l.3 -=SmO_bkC##0C3_.k -M4S=QjO_bkCr#0dS9 -Qh4=_;(( -fsRjR:jlENOR7qh.sRbHOlRbCk_#C0#_M.3 -=SmO_bkC##0C3_.k -MjS=Qjhc_4g -_HS=Q4O_bkC##0C3_.k;Md -fsRjR:jlENOR.m)RHbslbROk#_C0_#C. -3bSOm=bCk_#M0_#r_CdS9 -QOj=bCk_#C0#_k.3MS4 -QO4=bCk_#C0#_k.3M -j;sjRf:ljRNROEQRheblsHRiBp_amz_ u)__6j7 +fsRjR:jlENOReQhRHbsl_RqHgr.9m +S=Hq_r9.g +jSQ=Oq_r9.g;R +sfjj:ROlNEhRQesRbHqlR_dHrjS9 +m_=qHjrd9Q +Sj_=qOjrd9s; +R:fjjNRlOQERhbeRsRHlqr_Hd +49Sqm=_dHr4S9 +Qqj=_dOr4 +9;sjRf:ljRNROEQRheblsHRiBp_amz_ u)__6j7 _HSBm=pmi_zua_)6 _j__7HQ Sjp=Biz_ma)_u j_6_ 7;sjRf:ljRNROEq.h7RHbsl0R#N_0ClENOH\MC3dkM_ OD_0Fk_Cbs_ @@ -2304,144 +2408,7 @@ jSQ=iBp_amz_ u)_ 6jS=Q4B_pim_zau_) 67j__ H;sjRf:ljRNROEQRheblsHRzwu__B1Q_haHm S=zwu__B1Q_haHQ -Sju=wz1_B_aQh;R -sfjj:ROlNEhRQesRbHqlR1d_jjj_jjY_1hjB_3Ss -m1=q_jjd_jjj_h1YB3_jk -MdS=Qjhj_d;R -sfjj:ROlNEhRq7b.RsRHlqj1_djj_j1j_Y_hBj -3lSqm=1d_jjj_jjY_1hjB_34kM -jSQ=4kM_q71B_i4Q_hajJ_#lNkG_Sd -Qh4=_;dj -fsRjR:jlENOR7qh.sRbHqlR1d_jjj_jjY_1hjB_3SM -m1=q_jjd_jjj_h1YB3_jk -MjS=Qjqj1_djj_j1j_Y -hBS=Q4qj1_djj_j1j_Y_hBjM3kds; -R:fjjNRlOmER)b.RsRHlqj1_djj_j1j_Y_hBj -3bShm=_S. -Qqj=1d_jjj_jjY_1hjB_34kM -4SQ=_q1j_djj_jj1BYh_kj3M -j;sjRf:ljRNROEQRheblsHR1z7_jjj_aQh_sj3 -=Smz_71j_jjQ_hajM3kdQ -Sj_=h4;gn -fsRjR:jlENOR7qh.sRbHzlR7j1_jQj_hja_3Sl -m7=z1j_jjh_Qa3_jk -M4S=Qj#00NCN_lOMEHCz\37j1_jQj_h(a_ -4SQ=4h_g -n;sjRf:ljRNROEq.h7RHbsl7Rz1j_jjh_Qa3_jMm -S=1z7_jjj_aQh_kj3MSj -Qzj=7j1_jQj_hSa -Qz4=7j1_jQj_hja_3dkM;R -sfjj:ROlNE)Rm.sRbHzlR7j1_jQj_hja_3Sb -m_=hcQ -Sj7=z1j_jjh_Qa3_jk -M4S=Q4z_71j_jjQ_hajM3kjs; -R:fjjNRlOQERhbeRsRHlp_71j_jjQ_haj -3sSpm=7j1_jQj_hja_3dkM -jSQ=4h_g -n;sjRf:ljRNROEq.h7RHbsl7Rp1j_jjh_Qa3_jlm -S=1p7_jjj_aQh_kj3MS4 -Q#j=0CN0_OlNECHM\73p1j_jjh_Qa -_(S=Q4hg_4ns; -R:fjjNRlOqERhR7.blsHR1p7_jjj_aQh_Mj3 -=Smp_71j_jjQ_hajM3kjQ -Sj7=p1j_jjh_QaQ -S47=p1j_jjh_Qa3_jk;Md -fsRjR:jlENOR.m)RHbsl7Rp1j_jjh_Qa3_jbm -S=6h_ -jSQ=1p7_jjj_aQh_kj3MS4 -Qp4=7j1_jQj_hja_3jkM;R -sfjj:ROlNEhRQesRbHwlRuBz_1h_Qa3_jsm -S=zwu__B1Q_hajM3kdQ -Sj_=h. -U;sjRf:ljRNROEq.h7RHbsluRwz1_B_aQh_lj3 -=Smw_uzBQ1_hja_34kM -jSQ=_q1j_djOQ -S4_=h. -U;sjRf:ljRNROEq.h7RHbsluRwz1_B_aQh_Mj3 -=Smw_uzBQ1_hja_3jkM -jSQ=zwu__B1Q -haS=Q4w_uzBQ1_hja_3dkM;R -sfjj:ROlNE)Rm.sRbHwlRuBz_1h_Qa3_jbm -S=nh_ -jSQ=zwu__B1Q_hajM3k4Q -S4u=wz1_B_aQh_kj3M -j;sjRf:ljRNROEQRheblsHRCNPOG_Cb3_jsm -S=CNPOG_Cb3_jk -MdS=QjqtvQqz_A1h_ q Ap_aQh_#._JGlkNs; -R:fjjNRlOqERhR7.blsHRCNPOG_Cb3_jlm -S=CNPOG_Cb3_jk -M4S=QjNOPC_bCG -4SQ=QqvtAq_z 1_hpqA h_Qa__.#kJlG -N;sjRf:ljRNROEq.h7RHbslPRNCCO_Gjb_3SM -mP=NCCO_Gjb_3jkM -jSQ=4h_gH6_ -4SQ=CNPOG_Cb3_jk;Md -fsRjR:jlENOR.m)RHbslPRNCCO_Gjb_3Sb -m_=h(Q -SjP=NCCO_Gjb_34kM -4SQ=CNPOG_Cb3_jk;Mj -fsRjR:jlENOReQhRHbsltRA_jjj_sj3 -=SmAjt_jjj_3dkM -jSQ=N#00lC_NHOEM3C\kjM4__Loj;dj -fsRjR:jlENOR7qh.sRbHAlRtj_jj3_jlm -S=_Atj_jjjM3k4Q -Sjt=A_jjd_SO -Q#4=0CN0_OlNECHM\M3k4Lj_od_jjs; -R:fjjNRlOqERhR7.blsHR_Atj_jjj -3MSAm=tj_jj3_jk -MjS=QjAjt_jOj_ -4SQ=_Atj_jjjM3kds; -R:fjjNRlOmER)b.RsRHlAjt_jjj_3Sb -m_=hUQ -Sjt=A_jjj_kj3MS4 -QA4=tj_jj3_jk;Mj -fsRjR:jlENOReQhRHbsl1Rq_jjj_aQh_sj3 -=Smqj1_jQj_hja_3dkM -jSQ=4h_g -d;sjRf:ljRNROEq.h7RHbsl1Rq_jjj_aQh_lj3 -=Smqj1_jQj_hja_34kM -jSQ=nh_(Q -S4_=h4;gd -fsRjR:jlENOR7qh.sRbHqlR1j_jjh_Qa3_jMm -S=_q1j_jjQ_hajM3kjQ -Sj1=q_jjj_aQh -4SQ=_q1j_jjQ_hajM3kds; -R:fjjNRlOmER)b.RsRHlqj1_jQj_hja_3Sb -m_=h4S4 -Qqj=1j_jjh_Qa3_jk -M4S=Q4qj1_jQj_hja_3jkM;R -sfjj:ROlNEhRQesRbHhlR_c44_SH -m_=h4_4cHQ -Sj_=h4;4c -fsRjR:jlENOReQhRHbsl1R7q4Bi_aQh_sj3 -=Sm7B1qiQ4_hja_3dkM -jSQ=(h_6s; -R:fjjNRlOqERhR7.blsHRq71B_i4Q_haj -3lS7m=1iqB4h_Qa3_jk -M4S=Qjh4_4c -_HS=Q4h6_(;R -sfjj:ROlNEhRq7b.RsRHl7B1qiQ4_hja_3SM -m1=7q4Bi_aQh_kj3MSj -Q7j=1iqB4h_QaQ -S41=7q4Bi_aQh_kj3M -d;sjRf:ljRNROEmR).blsHRq71B_i4Q_haj -3bShm=_ -4.S=Qj7B1qiQ4_hja_34kM -4SQ=q71B_i4Q_hajM3kjs; -R:fjjNRlOQERhbeRsRHle_vqQ_haj -3sSem=vQq_hja_3dkM -jSQ=N#00lC_NHOEM3C\k.M4_ OD_jjj_;8j -fsRjR:jlENOR7qh.sRbHelRvQq_hja_3Sl -mv=eqh_Qa3_jk -M4S=Qj#00NCN_lOMEHCk\3M_4jO_D j_jj8Sj -Q#4=0CN0_OlNECHM\M3k4O._Dj _j8j_js; -R:fjjNRlOqERhR7.blsHRqev_aQh_Mj3 -=Sme_vqQ_hajM3kjQ -Sjv=eqh_QaQ -S4v=eqh_Qa3_jk;Md -fsRjR:jlENOR.m)RHbslvReqh_Qa3_jbm -S=4h_dQ -Sjv=eqh_Qa3_jk -M4S=Q4e_vqQ_hajM3kj -; +Sju=wz1_B_aQh; + + diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index 767bba0..97ebf54 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Sun Jun 01 01:03:18 2014 +#Sat Jun 07 23:03:13 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode @@ -23,6 +23,7 @@ Post processing for work.bus68030.behavioral @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:34:127:36|Pruning register CLK_000_D6 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_000_D5 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:34:125:36|Pruning register CLK_000_D4 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:34:124:36|Pruning register CLK_000_D3 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:38:117:40|Pruning register CLK_OUT_PRE_33 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_P(1 downto 0) @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:2:136:3|Pruning register CLK_CNT_N(1 downto 0) @@ -54,7 +55,7 @@ State machine has 11 reachable states with original encodings of: 1111 @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sun Jun 01 01:03:18 2014 +# Sat Jun 07 23:03:13 2014 ###########################################################] Map & Optimize Report @@ -91,16 +92,16 @@ Resource Usage Report Simple gate primitives: DFFRH 16 uses -DFFSH 27 uses +DFFSH 26 uses DFF 1 use BI_DIR 12 uses IBUF 29 uses BUFTH 2 uses OBUF 16 uses AND2 185 uses -INV 151 uses -OR2 21 uses -XOR2 1 use +INV 148 uses +OR2 20 uses +XOR2 2 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -110,6 +111,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sun Jun 01 01:03:19 2014 +# Sat Jun 07 23:03:15 2014 ###########################################################] diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs index fda9761..1ea6759 100644 Binary files a/Logic/BUS68030.srs and b/Logic/BUS68030.srs differ diff --git a/Logic/bus68030.exf b/Logic/bus68030.exf index 4a22d7b..07736e4 100644 --- a/Logic/bus68030.exf +++ b/Logic/bus68030.exf @@ -36,462 +36,520 @@ Section Member Rename Array-Notation Array Number Port FC_0_ FC[0] 3 1 End Section Cross Reference File -Design 'BUS68030' created Sun Jun 01 01:03:24 2014 +Design 'BUS68030' created Sat Jun 07 23:03:19 2014 Type New Name Original Name // ---------------------------------------------------------------------- - Inst i_z2O2O AS_030 - Inst i_z2P2P AS_000 - Inst i_z2Q2Q RW_000 - Inst i_z2R2R DS_030 - Inst i_z2S2S UDS_000 - Inst i_z2T2T LDS_000 - Inst i_z3G3G A0 - Inst i_z3I3I BERR - Inst i_z4343 DSACK1 - Inst i_z4444 DTACK - Inst i_z4C4C RW - Inst i_z4I4I CIIN - Inst cpu_est_ns_i_0_o2_i_3_ cpu_est_ns_i_0_o2_i[3] - Inst SM_AMIGA_ns_i_o2_i_4_ SM_AMIGA_ns_i_o2_i[4] - Inst SM_AMIGA_ns_i_o2_0_i_4_ SM_AMIGA_ns_i_o2_0_i[4] - Inst state_machine_un3_clk_000_d1_0_o2_i state_machine.un3_clk_000_d1_0_o2_i - Inst state_machine_RW_000_INT_7_iv_0_o2_i state_machine.RW_000_INT_7_iv_0_o2_i - Inst SM_AMIGA_i_2_ SM_AMIGA_i[2] - Inst SM_AMIGA_ns_a2_0_o2_i_6_ SM_AMIGA_ns_a2_0_o2_i[6] - Inst state_machine_CLK_030_H_2_f0_i_o2_i state_machine.CLK_030_H_2_f0_i_o2_i - Inst cpu_est_ns_0_0_i_1_ cpu_est_ns_0_0_i[1] - Inst state_machine_SIZE_DMA_4_0_i_1_ state_machine.SIZE_DMA_4_0_i[1] - Inst SM_AMIGA_ns_0_i_5_ SM_AMIGA_ns_0_i[5] - Inst state_machine_un6_bgack_000_0_i state_machine.un6_bgack_000_0_i - Inst state_machine_DS_000_DMA_3_0_i state_machine.DS_000_DMA_3_0_i - Inst cpu_est_0_ cpu_est[0] - Inst cpu_est_1_ cpu_est[1] - Inst A_i_19_ A_i[19] - Inst cpu_est_2_ cpu_est[2] - Inst A_i_18_ A_i[18] - Inst cpu_est_3_ cpu_est[3] - Inst A_i_16_ A_i[16] - Inst SM_AMIGA_0_ SM_AMIGA[0] - Inst BGACK_030_INT_0_r BGACK_030_INT_0.r - Inst SIZE_DMA_1_ SIZE_DMA[1] - Inst BGACK_030_INT_0_m BGACK_030_INT_0.m - Inst IPL_030DFFSH_0_ IPL_030DFFSH[0] - Inst BGACK_030_INT_0_n BGACK_030_INT_0.n - Inst IPL_030DFFSH_1_ IPL_030DFFSH[1] - Inst BGACK_030_INT_0_p BGACK_030_INT_0.p - Inst IPL_030DFFSH_2_ IPL_030DFFSH[2] - Inst SM_AMIGA_7_ SM_AMIGA[7] - Inst AS_000_DMA_0_r AS_000_DMA_0.r - Inst SM_AMIGA_6_ SM_AMIGA[6] - Inst AS_000_DMA_0_m AS_000_DMA_0.m - Inst SM_AMIGA_5_ SM_AMIGA[5] - Inst AS_000_DMA_0_n AS_000_DMA_0.n - Inst SM_AMIGA_4_ SM_AMIGA[4] - Inst AS_000_DMA_0_p AS_000_DMA_0.p - Inst SM_AMIGA_3_ SM_AMIGA[3] - Inst DS_000_DMA_0_r DS_000_DMA_0.r - Inst SM_AMIGA_2_ SM_AMIGA[2] - Inst DS_000_DMA_0_m DS_000_DMA_0.m - Inst SM_AMIGA_1_ SM_AMIGA[1] - Inst DS_000_DMA_0_n DS_000_DMA_0.n - Inst DS_000_DMA_0_p DS_000_DMA_0.p - Inst CLK_030_H_0_r CLK_030_H_0.r - Inst CLK_030_H_0_m CLK_030_H_0.m - Inst CLK_030_H_0_n CLK_030_H_0.n - Inst SIZE_DMA_0_ SIZE_DMA[0] - Inst CLK_030_H_0_p CLK_030_H_0.p - Inst RW_000_INT_0_r RW_000_INT_0.r - Inst RW_000_INT_0_m RW_000_INT_0.m - Inst RW_000_INT_0_n RW_000_INT_0.n - Inst RW_000_INT_0_p RW_000_INT_0.p - Inst SM_AMIGA_i_0_ SM_AMIGA_i[0] - Inst SM_AMIGA_i_1_ SM_AMIGA_i[1] - Inst SM_AMIGA_ns_i_0_a3_7_ SM_AMIGA_ns_i_0_a3[7] - Inst SM_AMIGA_ns_0_a3_0_5_ SM_AMIGA_ns_0_a3_0[5] - Inst SM_AMIGA_i_3_ SM_AMIGA_i[3] - Inst SM_AMIGA_ns_i_a3_4_ SM_AMIGA_ns_i_a3[4] - Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] - Inst SM_AMIGA_i_5_ SM_AMIGA_i[5] - Inst SM_AMIGA_ns_i_0_a3_3_ SM_AMIGA_ns_i_0_a3[3] - Inst SM_AMIGA_ns_0_a3_0_ SM_AMIGA_ns_0_a3[0] - Inst SM_AMIGA_ns_a2_0_a3_6_ SM_AMIGA_ns_a2_0_a3[6] - Inst state_machine_SIZE_DMA_4_i_a3_0_ state_machine.SIZE_DMA_4_i_a3[0] - Inst state_machine_un6_bgack_000_0 state_machine.un6_bgack_000_0 - Inst state_machine_SIZE_DMA_4_0_a2_1_ state_machine.SIZE_DMA_4_0_a2[1] - Inst SM_AMIGA_ns_i_a2_0_4_ SM_AMIGA_ns_i_a2_0[4] - Inst SIZE_0_ SIZE[0] - Inst SIZE_1_ SIZE[1] - Inst A_16_ A[16] - Inst state_machine_CLK_030_H_2_f0_i_a3 state_machine.CLK_030_H_2_f0_i_a3 - Inst A_17_ A[17] - Inst A_18_ A[18] - Inst A_19_ A[19] - Inst state_machine_un3_clk_000_d1_0_o2 state_machine.un3_clk_000_d1_0_o2 - Inst A_20_ A[20] - Inst SM_AMIGA_ns_i_o2_0_4_ SM_AMIGA_ns_i_o2_0[4] - Inst A_21_ A[21] - Inst SM_AMIGA_ns_i_o2_4_ SM_AMIGA_ns_i_o2[4] - Inst A_22_ A[22] - Inst A_23_ A[23] - Inst state_machine_RW_000_INT_7_iv_0 state_machine.RW_000_INT_7_iv_0 - Inst A_24_ A[24] - Inst state_machine_CLK_030_H_2_f0_i state_machine.CLK_030_H_2_f0_i - Inst A_25_ A[25] - Inst A_26_ A[26] - Inst SM_AMIGA_ns_i_0_7_ SM_AMIGA_ns_i_0[7] - Inst A_27_ A[27] - Inst SM_AMIGA_ns_0_5_ SM_AMIGA_ns_0[5] - Inst A_28_ A[28] - Inst SM_AMIGA_ns_i_4_ SM_AMIGA_ns_i[4] - Inst A_29_ A[29] - Inst SM_AMIGA_ns_i_0_3_ SM_AMIGA_ns_i_0[3] - Inst A_30_ A[30] - Inst state_machine_SIZE_DMA_4_0_1_ state_machine.SIZE_DMA_4_0[1] - Inst A_31_ A[31] - Inst state_machine_DS_000_DMA_3_0 state_machine.DS_000_DMA_3_0 - Inst cpu_est_i_3_ cpu_est_i[3] - Inst cpu_est_ns_i_0_o2_3_ cpu_est_ns_i_0_o2[3] - Inst SM_AMIGA_ns_0_o3_0_ SM_AMIGA_ns_0_o3[0] - Inst SM_AMIGA_ns_a2_0_o2_2_ SM_AMIGA_ns_a2_0_o2[2] - Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] - Inst SM_AMIGA_ns_i_0_o2_1_ SM_AMIGA_ns_i_0_o2[1] - Inst state_machine_RW_000_INT_7_iv_0_a3_0_2 state_machine.RW_000_INT_7_iv_0_a3_0_2 - Inst IPL_030_0_ IPL_030[0] - Inst state_machine_CLK_030_H_2_f0_i_o2 state_machine.CLK_030_H_2_f0_i_o2 - Inst IPL_030_1_ IPL_030[1] - Inst SM_AMIGA_ns_a2_0_o2_6_ SM_AMIGA_ns_a2_0_o2[6] - Inst IPL_030_2_ IPL_030[2] - Inst IPL_0_ IPL[0] - Inst state_machine_RW_000_INT_7_iv_0_o2 state_machine.RW_000_INT_7_iv_0_o2 - Inst IPL_1_ IPL[1] - Inst cpu_est_ns_i_0_a2_3_ cpu_est_ns_i_0_a2[3] - Inst IPL_2_ IPL[2] - Inst state_machine_un12_clk_000_d0_0 state_machine.un12_clk_000_d0_0 - Inst state_machine_un10_bg_030_0 state_machine.un10_bg_030_0 - Inst SM_AMIGA_ns_0_0_ SM_AMIGA_ns_0[0] - Inst SM_AMIGA_ns_i_0_1_ SM_AMIGA_ns_i_0[1] - Inst cpu_est_ns_i_0_3_ cpu_est_ns_i_0[3] - Inst FC_0_ FC[0] - Inst FC_1_ FC[1] - Inst state_machine_UDS_000_INT_7_0_m3_r state_machine.UDS_000_INT_7_0_m3.r - Inst state_machine_UDS_000_INT_7_0_m3_m state_machine.UDS_000_INT_7_0_m3.m - Inst state_machine_UDS_000_INT_7_0_m3_n state_machine.UDS_000_INT_7_0_m3.n - Inst state_machine_UDS_000_INT_7_0_m3_p state_machine.UDS_000_INT_7_0_m3.p - Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] - Inst cpu_est_ns_0_0_a3_2_ cpu_est_ns_0_0_a3[2] - Inst cpu_est_ns_0_0_a3_0_2_ cpu_est_ns_0_0_a3_0[2] - Inst cpu_est_ns_0_0_a3_1_2_ cpu_est_ns_0_0_a3_1[2] - Inst cpu_est_i_0_ cpu_est_i[0] - Inst state_machine_un12_clk_000_d0_0_a3_1 state_machine.un12_clk_000_d0_0_a3_1 - Inst cpu_est_ns_0_0_a2_1_ cpu_est_ns_0_0_a2[1] - Inst state_machine_un12_clk_000_d0_0_a3 state_machine.un12_clk_000_d0_0_a3 - Inst SM_AMIGA_ns_0_a2_0_ SM_AMIGA_ns_0_a2[0] - Inst SM_AMIGA_ns_i_a2_1_4_ SM_AMIGA_ns_i_a2_1[4] - Inst cpu_est_i_1_ cpu_est_i[1] - Inst SM_AMIGA_ns_i_a2_4_ SM_AMIGA_ns_i_a2[4] - Inst cpu_est_ns_0_0_a2_0_1_ cpu_est_ns_0_0_a2_0[1] - Inst A_i_29_ A_i[29] - Inst A_i_30_ A_i[30] - Inst state_machine_RW_000_INT_7_iv_0_a3_1 state_machine.RW_000_INT_7_iv_0_a3_1 - Inst A_i_31_ A_i[31] - Inst state_machine_RW_000_INT_7_iv_0_a3 state_machine.RW_000_INT_7_iv_0_a3 - Inst SM_AMIGA_ns_i_a3_0_1_4_ SM_AMIGA_ns_i_a3_0_1[4] - Inst SM_AMIGA_ns_i_a3_0_4_ SM_AMIGA_ns_i_a3_0[4] - Inst state_machine_LDS_000_INT_7_0_a3_1 state_machine.LDS_000_INT_7_0_a3_1 - Inst state_machine_LDS_000_INT_7_0_a3 state_machine.LDS_000_INT_7_0_a3 - Inst SM_AMIGA_ns_a2_0_a3_2_ SM_AMIGA_ns_a2_0_a3[2] - Inst state_machine_A0_DMA_2_0_a3_1 state_machine.A0_DMA_2_0_a3_1 - Inst SM_AMIGA_ns_i_0_a3_1_ SM_AMIGA_ns_i_0_a3[1] - Inst state_machine_A0_DMA_2_0_a3 state_machine.A0_DMA_2_0_a3 - Inst cpu_est_ns_0_0_a3_1_ cpu_est_ns_0_0_a3[1] - Inst state_machine_un12_clk_000_d0_0_a3_0 state_machine.un12_clk_000_d0_0_a3_0 - Inst cpu_est_i_2_ cpu_est_i[2] - Inst SM_AMIGA_ns_0_a3_1_5_ SM_AMIGA_ns_0_a3_1[5] - Inst cpu_est_ns_0_0_a3_0_1_ cpu_est_ns_0_0_a3_0[1] - Inst SM_AMIGA_ns_0_a3_2_5_ SM_AMIGA_ns_0_a3_2[5] - Inst cpu_est_ns_i_0_a3_3_ cpu_est_ns_i_0_a3[3] - Inst SM_AMIGA_ns_0_a3_5_ SM_AMIGA_ns_0_a3[5] - Inst state_machine_RW_000_INT_7_iv_0_a3_0_1 state_machine.RW_000_INT_7_iv_0_a3_0_1 - Inst state_machine_RW_000_INT_7_iv_0_a3_0 state_machine.RW_000_INT_7_iv_0_a3_0 - Inst A_i_24_ A_i[24] - Inst cpu_est_ns_0_0_1_2_ cpu_est_ns_0_0_1[2] - Inst A_i_25_ A_i[25] - Inst cpu_est_ns_0_0_2_ cpu_est_ns_0_0[2] - Inst A_i_26_ A_i[26] - Inst A_i_27_ A_i[27] - Inst A_i_28_ A_i[28] - Inst state_machine_LDS_000_INT_7_0_1 state_machine.LDS_000_INT_7_0_1 - Inst state_machine_LDS_000_INT_7_0 state_machine.LDS_000_INT_7_0 - Inst IPL_030_0_0__r IPL_030_0_0_.r - Inst state_machine_UDS_000_INT_7_0_1 state_machine.UDS_000_INT_7_0_1 - Inst IPL_030_0_0__m IPL_030_0_0_.m - Inst state_machine_UDS_000_INT_7_0 state_machine.UDS_000_INT_7_0 - Inst IPL_030_0_0__n IPL_030_0_0_.n - Inst IPL_030_0_0__p IPL_030_0_0_.p - Inst IPL_030_0_1__r IPL_030_0_1_.r - Inst IPL_030_0_1__m IPL_030_0_1_.m - Inst IPL_030_0_1__n IPL_030_0_1_.n - Inst cpu_est_ns_0_0_1_1_ cpu_est_ns_0_0_1[1] - Inst IPL_030_0_1__p IPL_030_0_1_.p - Inst cpu_est_ns_0_0_2_1_ cpu_est_ns_0_0_2[1] - Inst IPL_030_0_2__r IPL_030_0_2_.r - Inst cpu_est_ns_0_0_1_ cpu_est_ns_0_0[1] - Inst IPL_030_0_2__m IPL_030_0_2_.m - Inst IPL_030_0_2__n IPL_030_0_2_.n - Inst IPL_030_0_2__p IPL_030_0_2_.p - Inst cpu_estse_0_r cpu_estse_0.r - Inst cpu_estse_0_m cpu_estse_0.m - Inst state_machine_un10_bg_030_0_a3_1 state_machine.un10_bg_030_0_a3_1 - Inst cpu_estse_0_n cpu_estse_0.n - Inst state_machine_un10_bg_030_0_a3_2 state_machine.un10_bg_030_0_a3_2 - Inst cpu_estse_0_p cpu_estse_0.p - Inst state_machine_un10_bg_030_0_a3 state_machine.un10_bg_030_0_a3 - Inst cpu_estse_1_r cpu_estse_1.r - Inst state_machine_un12_clk_000_d0_0_a3_0_1 state_machine.un12_clk_000_d0_0_a3_0_1 - Inst cpu_estse_1_m cpu_estse_1.m - Inst state_machine_un12_clk_000_d0_0_a3_0_2 state_machine.un12_clk_000_d0_0_a3_0_2 - Inst cpu_estse_1_n cpu_estse_1.n - Inst cpu_estse_1_p cpu_estse_1.p + Inst i_z2N2N AS_030 + Inst i_z2O2O AS_000 + Inst i_z2P2P RW_000 + Inst i_z2Q2Q DS_030 + Inst i_z2R2R UDS_000 + Inst i_z2S2S LDS_000 + Inst i_z3F3F A0 + Inst i_z3H3H BERR + Inst i_z4242 DSACK1 + Inst i_z4343 DTACK + Inst i_z4B4B RW + Inst i_z4H4H CIIN + Inst cpu_est_ns_i_o2_i_3_ cpu_est_ns_i_o2_i[3] + Inst state_machine_un10_clk_000_d0_2_i state_machine.un10_clk_000_d0_2_i + Inst cpu_est_ns_0_i_2_ cpu_est_ns_0_i[2] + Inst state_machine_un10_clk_000_d0_i state_machine.un10_clk_000_d0_i + Inst state_machine_un12_clk_000_d0_i state_machine.un12_clk_000_d0_i + Inst state_machine_un3_clk_000_d1_i state_machine.un3_clk_000_d1_i + Inst state_machine_un6_bgack_000_i state_machine.un6_bgack_000_i + Inst cpu_est_ns_0_i_1_ cpu_est_ns_0_i[1] + Inst cpu_est_ns_0_a3_1_ cpu_est_ns_0_a3[1] + Inst state_machine_un6_bgack_000 state_machine.un6_bgack_000 Inst cpu_estse_2_r cpu_estse_2.r Inst cpu_estse_2_m cpu_estse_2.m Inst cpu_estse_2_n cpu_estse_2.n Inst cpu_estse_2_p cpu_estse_2.p - Inst state_machine_un3_clk_out_pre_50 state_machine.un3_clk_out_pre_50 + Inst cpu_estse_1_r cpu_estse_1.r + Inst cpu_estse_1_m cpu_estse_1.m + Inst cpu_estse_1_n cpu_estse_1.n + Inst cpu_estse_1_p cpu_estse_1.p + Inst cpu_estse_0_r cpu_estse_0.r + Inst cpu_estse_0_m cpu_estse_0.m + Inst cpu_estse_0_n cpu_estse_0.n + Inst cpu_estse_0_p cpu_estse_0.p + Inst IPL_030_0_2__r IPL_030_0_2_.r + Inst IPL_030_0_2__m IPL_030_0_2_.m + Inst cpu_est_1_ cpu_est[1] + Inst IPL_030_0_2__n IPL_030_0_2_.n + Inst cpu_est_2_ cpu_est[2] + Inst IPL_030_0_2__p IPL_030_0_2_.p + Inst cpu_est_3_ cpu_est[3] + Inst IPL_030_0_1__r IPL_030_0_1_.r + Inst cpu_est_0_ cpu_est[0] + Inst IPL_030_0_1__m IPL_030_0_1_.m + Inst IPL_030DFFSH_0_ IPL_030DFFSH[0] + Inst IPL_030_0_1__n IPL_030_0_1_.n + Inst IPL_030DFFSH_1_ IPL_030DFFSH[1] + Inst IPL_030_0_1__p IPL_030_0_1_.p + Inst IPL_030DFFSH_2_ IPL_030DFFSH[2] + Inst IPL_030_0_0__r IPL_030_0_0_.r + Inst SM_AMIGA_7_ SM_AMIGA[7] + Inst IPL_030_0_0__m IPL_030_0_0_.m + Inst SM_AMIGA_6_ SM_AMIGA[6] + Inst IPL_030_0_0__n IPL_030_0_0_.n + Inst SM_AMIGA_5_ SM_AMIGA[5] + Inst IPL_030_0_0__p IPL_030_0_0_.p + Inst SM_AMIGA_4_ SM_AMIGA[4] + Inst BGACK_030_INT_0_r BGACK_030_INT_0.r + Inst SM_AMIGA_3_ SM_AMIGA[3] + Inst BGACK_030_INT_0_m BGACK_030_INT_0.m + Inst SM_AMIGA_2_ SM_AMIGA[2] + Inst BGACK_030_INT_0_n BGACK_030_INT_0.n + Inst SM_AMIGA_1_ SM_AMIGA[1] + Inst BGACK_030_INT_0_p BGACK_030_INT_0.p + Inst SM_AMIGA_0_ SM_AMIGA[0] + Inst cpu_est_ns_i_o2_3_ cpu_est_ns_i_o2[3] + Inst cpu_est_ns_i_3_ cpu_est_ns_i[3] + Inst cpu_est_ns_0_a2_1_ cpu_est_ns_0_a2[1] + Inst SIZE_DMA_0_ SIZE_DMA[0] + Inst cpu_est_ns_i_a3_0_3_ cpu_est_ns_i_a3_0[3] + Inst SIZE_DMA_1_ SIZE_DMA[1] + Inst cpu_est_ns_i_a3_3_ cpu_est_ns_i_a3[3] + Inst cpu_est_i_0_ cpu_est_i[0] + Inst cpu_est_ns_0_a3_1_2_ cpu_est_ns_0_a3_1[2] + Inst cpu_est_ns_0_a3_0_2_ cpu_est_ns_0_a3_0[2] + Inst cpu_est_ns_0_a3_2_ cpu_est_ns_0_a3[2] + Inst cpu_est_i_1_ cpu_est_i[1] + Inst cpu_est_ns_0_a3_1_1_ cpu_est_ns_0_a3_1[1] + Inst cpu_est_ns_0_a3_0_1_ cpu_est_ns_0_a3_0[1] + Inst cpu_est_i_3_ cpu_est_i[3] + Inst cpu_est_i_2_ cpu_est_i[2] + Inst state_machine_un3_clk_030 state_machine.un3_clk_030 + Inst state_machine_un28_clk_030_i state_machine.un28_clk_030_i + Inst state_machine_un12_clk_000_d0 state_machine.un12_clk_000_d0 + Inst state_machine_un3_clk_000_d1 state_machine.un3_clk_000_d1 Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p - Inst UDS_000_INT_0_r UDS_000_INT_0.r - Inst UDS_000_INT_0_m UDS_000_INT_0.m - Inst UDS_000_INT_0_n UDS_000_INT_0.n - Inst UDS_000_INT_0_p UDS_000_INT_0.p - Inst LDS_000_INT_0_r LDS_000_INT_0.r - Inst LDS_000_INT_0_m LDS_000_INT_0.m - Inst LDS_000_INT_0_n LDS_000_INT_0.n - Inst LDS_000_INT_0_p LDS_000_INT_0.p Inst FPU_CS_INT_0_r FPU_CS_INT_0.r + Inst SIZE_0_ SIZE[0] Inst FPU_CS_INT_0_m FPU_CS_INT_0.m + Inst SIZE_1_ SIZE[1] Inst FPU_CS_INT_0_n FPU_CS_INT_0.n + Inst A_16_ A[16] Inst FPU_CS_INT_0_p FPU_CS_INT_0.p + Inst A_17_ A[17] + Inst AS_000_INT_0_r AS_000_INT_0.r + Inst A_18_ A[18] + Inst AS_000_INT_0_m AS_000_INT_0.m + Inst A_19_ A[19] + Inst AS_000_INT_0_n AS_000_INT_0.n + Inst A_20_ A[20] + Inst AS_000_INT_0_p AS_000_INT_0.p + Inst A_21_ A[21] + Inst DSACK1_INT_0_r DSACK1_INT_0.r + Inst A_22_ A[22] + Inst DSACK1_INT_0_m DSACK1_INT_0.m + Inst A_23_ A[23] + Inst DSACK1_INT_0_n DSACK1_INT_0.n + Inst A_24_ A[24] + Inst DSACK1_INT_0_p DSACK1_INT_0.p + Inst A_25_ A[25] + Inst state_machine_un5_clk_000_d0_i state_machine.un5_clk_000_d0_i + Inst A_26_ A[26] + Inst VMA_INT_0_r VMA_INT_0.r + Inst A_27_ A[27] + Inst VMA_INT_0_m VMA_INT_0.m + Inst A_28_ A[28] + Inst VMA_INT_0_n VMA_INT_0.n + Inst A_29_ A[29] + Inst VMA_INT_0_p VMA_INT_0.p + Inst A_30_ A[30] + Inst A_i_16_ A_i[16] + Inst A_31_ A[31] + Inst A_i_18_ A_i[18] + Inst A_i_19_ A_i[19] + Inst state_machine_un51_clk_000_d0 state_machine.un51_clk_000_d0 + Inst state_machine_un53_clk_000_d0 state_machine.un53_clk_000_d0 + Inst SM_AMIGA_i_1_ SM_AMIGA_i[1] + Inst SM_AMIGA_ns_a2_0_5_ SM_AMIGA_ns_a2_0[5] + Inst SM_AMIGA_i_2_ SM_AMIGA_i[2] + Inst SM_AMIGA_ns_i_a2_6_ SM_AMIGA_ns_i_a2[6] + Inst SM_AMIGA_ns_a2_7_ SM_AMIGA_ns_a2[7] + Inst SM_AMIGA_ns_0_ SM_AMIGA_ns[0] + Inst IPL_030_0_ IPL_030[0] + Inst SM_AMIGA_ns_5_ SM_AMIGA_ns[5] + Inst IPL_030_1_ IPL_030[1] + Inst SM_AMIGA_ns_i_6_ SM_AMIGA_ns_i[6] + Inst IPL_030_2_ IPL_030[2] + Inst IPL_0_ IPL[0] + Inst IPL_1_ IPL[1] + Inst IPL_2_ IPL[2] + Inst SM_AMIGA_i_0_ SM_AMIGA_i[0] + Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] Inst avec_exp_0_r avec_exp_0.r - Inst state_machine_un10_bg_030_0_i state_machine.un10_bg_030_0_i Inst avec_exp_0_m avec_exp_0.m Inst avec_exp_0_n avec_exp_0.n Inst avec_exp_0_p avec_exp_0.p - Inst state_machine_un10_clk_000_d0_i state_machine.un10_clk_000_d0_i Inst BG_000_0_r BG_000_0.r - Inst state_machine_un12_clk_000_d0_0_i state_machine.un12_clk_000_d0_0_i Inst BG_000_0_m BG_000_0.m + Inst FC_0_ FC[0] Inst BG_000_0_n BG_000_0.n + Inst FC_1_ FC[1] Inst BG_000_0_p BG_000_0.p - Inst AS_000_INT_0_r AS_000_INT_0.r - Inst cpu_est_ns_0_0_i_2_ cpu_est_ns_0_0_i[2] - Inst AS_000_INT_0_m AS_000_INT_0.m - Inst AS_000_INT_0_n AS_000_INT_0.n - Inst AS_000_INT_0_p AS_000_INT_0.p - Inst DSACK1_INT_0_r DSACK1_INT_0.r - Inst DSACK1_INT_0_m DSACK1_INT_0.m - Inst DSACK1_INT_0_n DSACK1_INT_0.n - Inst SM_AMIGA_ns_0_i_0_ SM_AMIGA_ns_0_i[0] - Inst DSACK1_INT_0_p DSACK1_INT_0.p - Inst VMA_INT_0_r VMA_INT_0.r - Inst VMA_INT_0_m VMA_INT_0.m - Inst state_machine_LDS_000_INT_7_0_i state_machine.LDS_000_INT_7_0_i - Inst VMA_INT_0_n VMA_INT_0.n - Inst state_machine_UDS_000_INT_7_0_i state_machine.UDS_000_INT_7_0_i - Inst VMA_INT_0_p VMA_INT_0.p - Inst SM_AMIGA_ns_i_0_o2_i_1_ SM_AMIGA_ns_i_0_o2_i[1] - Inst SM_AMIGA_ns_a2_0_o2_i_2_ SM_AMIGA_ns_a2_0_o2_i[2] + Inst state_machine_un3_bgack_030_int_d state_machine.un3_bgack_030_int_d + Inst state_machine_un5_bgack_030_int_d state_machine.un5_bgack_030_int_d + Inst state_machine_un5_clk_000_d0_2 state_machine.un5_clk_000_d0_2 + Inst state_machine_un5_clk_000_d0 state_machine.un5_clk_000_d0 + Inst state_machine_un10_clk_000_d0_1 state_machine.un10_clk_000_d0_1 + Inst state_machine_un10_clk_000_d0_2 state_machine.un10_clk_000_d0_2 + Inst state_machine_un10_bg_030 state_machine.un10_bg_030 + Inst state_machine_un10_clk_000_d0_3 state_machine.un10_clk_000_d0_3 + Inst state_machine_un10_clk_000_d0 state_machine.un10_clk_000_d0 + Inst SM_AMIGA_ns_a2_0_ SM_AMIGA_ns_a2[0] + Inst cpu_est_ns_0_1_1_ cpu_est_ns_0_1[1] + Inst SM_AMIGA_ns_a2_0_0_ SM_AMIGA_ns_a2_0[0] + Inst cpu_est_ns_0_2_1_ cpu_est_ns_0_2[1] + Inst SM_AMIGA_ns_a2_5_ SM_AMIGA_ns_a2[5] + Inst cpu_est_ns_0_1_ cpu_est_ns_0[1] + Inst state_machine_un31_bgack_030_int_i state_machine.un31_bgack_030_int_i + Inst state_machine_un28_clk_000_d1_1 state_machine.un28_clk_000_d1_1 + Inst state_machine_SIZE_DMA_4_0_ state_machine.SIZE_DMA_4[0] + Inst state_machine_un28_clk_000_d1 state_machine.un28_clk_000_d1 + Inst state_machine_LDS_000_INT_7 state_machine.LDS_000_INT_7 + Inst state_machine_un8_bg_030 state_machine.un8_bg_030 + Inst state_machine_UDS_000_INT_7 state_machine.UDS_000_INT_7 + Inst state_machine_un57_clk_000_d0_1 state_machine.un57_clk_000_d0_1 + Inst state_machine_un57_clk_000_d0 state_machine.un57_clk_000_d0 + Inst state_machine_un49_clk_000_d0_1 state_machine.un49_clk_000_d0_1 + Inst state_machine_un49_clk_000_d0 state_machine.un49_clk_000_d0 + Inst state_machine_un31_bgack_030_int state_machine.un31_bgack_030_int + Inst state_machine_un10_bgack_030_int state_machine.un10_bgack_030_int + Inst state_machine_un28_clk_030_1 state_machine.un28_clk_030_1 + Inst LDS_000_INT_0_r LDS_000_INT_0.r + Inst state_machine_un28_clk_030_2 state_machine.un28_clk_030_2 + Inst LDS_000_INT_0_m LDS_000_INT_0.m + Inst state_machine_un28_clk_030_3 state_machine.un28_clk_030_3 + Inst LDS_000_INT_0_n LDS_000_INT_0.n + Inst state_machine_un28_clk_030_4 state_machine.un28_clk_030_4 + Inst LDS_000_INT_0_p LDS_000_INT_0.p + Inst state_machine_un28_clk_030_5 state_machine.un28_clk_030_5 + Inst UDS_000_INT_0_r UDS_000_INT_0.r + Inst state_machine_un28_clk_030 state_machine.un28_clk_030 + Inst UDS_000_INT_0_m UDS_000_INT_0.m + Inst state_machine_un5_clk_000_d0_1 state_machine.un5_clk_000_d0_1 + Inst UDS_000_INT_0_n UDS_000_INT_0.n + Inst UDS_000_INT_0_p UDS_000_INT_0.p + Inst RW_000_INT_0_r RW_000_INT_0.r + Inst RW_000_INT_0_m RW_000_INT_0.m + Inst RW_000_INT_0_n RW_000_INT_0.n + Inst RW_000_INT_0_p RW_000_INT_0.p + Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] + Inst state_machine_RW_000_INT_7_iv state_machine.RW_000_INT_7_iv + Inst state_machine_un8_bg_030_1 state_machine.un8_bg_030_1 + Inst state_machine_un8_bg_030_2 state_machine.un8_bg_030_2 + Inst SM_AMIGA_ns_i_2_ SM_AMIGA_ns_i[2] + Inst SM_AMIGA_i_5_ SM_AMIGA_i[5] + Inst SM_AMIGA_ns_i_a2_2_ SM_AMIGA_ns_i_a2[2] + Inst state_machine_SIZE_DMA_4_1_ state_machine.SIZE_DMA_4[1] + Inst state_machine_un8_bgack_030_int_i state_machine.un8_bgack_030_int_i + Inst AS_000_DMA_0_r AS_000_DMA_0.r + Inst AS_000_DMA_0_m AS_000_DMA_0.m + Inst AS_000_DMA_0_n AS_000_DMA_0.n + Inst AS_000_DMA_0_p AS_000_DMA_0.p + Inst DS_000_DMA_0_r DS_000_DMA_0.r + Inst DS_000_DMA_0_m DS_000_DMA_0.m + Inst DS_000_DMA_0_n DS_000_DMA_0.n + Inst DS_000_DMA_0_p DS_000_DMA_0.p + Inst CLK_030_H_0_r CLK_030_H_0.r + Inst CLK_030_H_0_m CLK_030_H_0.m + Inst SM_AMIGA_ns_i_4_ SM_AMIGA_ns_i[4] + Inst CLK_030_H_0_n CLK_030_H_0.n + Inst SM_AMIGA_ns_i_o3_i_1_ SM_AMIGA_ns_i_o3_i[1] + Inst CLK_030_H_0_p CLK_030_H_0.p + Inst state_machine_DS_000_DMA_3_i state_machine.DS_000_DMA_3_i + Inst SM_AMIGA_ns_i_o3_1_ SM_AMIGA_ns_i_o3[1] + Inst SM_AMIGA_ns_4_ SM_AMIGA_ns[4] + Inst SM_AMIGA_ns_i_1_ SM_AMIGA_ns_i[1] + Inst state_machine_CLK_030_H_2_f1_i state_machine.CLK_030_H_2_f1_i + Inst state_machine_un49_clk_000_d0_i state_machine.un49_clk_000_d0_i + Inst SM_AMIGA_ns_a2_0_4_ SM_AMIGA_ns_a2_0[4] + Inst SM_AMIGA_ns_a2_4_ SM_AMIGA_ns_a2[4] + Inst SM_AMIGA_ns_i_a2_1_ SM_AMIGA_ns_i_a2[1] + Inst state_machine_un25_clk_000_d0_1 state_machine.un25_clk_000_d0_1 + Inst state_machine_un8_bgack_030_int state_machine.un8_bgack_030_int + Inst state_machine_un25_clk_000_d0 state_machine.un25_clk_000_d0 + Inst cpu_est_ns_0_1_2_ cpu_est_ns_0_1[2] + Inst cpu_est_ns_0_2_ cpu_est_ns_0[2] + Inst state_machine_LDS_000_INT_7_i state_machine.LDS_000_INT_7_i + Inst state_machine_SIZE_DMA_4_i_0_ state_machine.SIZE_DMA_4_i[0] + Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] + Inst state_machine_SIZE_DMA_4_i_1_ state_machine.SIZE_DMA_4_i[1] + Inst SM_AMIGA_ns_i_a2_3_ SM_AMIGA_ns_i_a2[3] + Inst SM_AMIGA_ns_i_3_ SM_AMIGA_ns_i[3] + Inst state_machine_un24_bgack_030_int_i state_machine.un24_bgack_030_int_i + Inst state_machine_CLK_030_H_2_f0 state_machine.CLK_030_H_2_f0 + Inst state_machine_CLK_030_H_2_f1 state_machine.CLK_030_H_2_f1 + Inst state_machine_DS_000_DMA_3 state_machine.DS_000_DMA_3 + Inst state_machine_A0_DMA_2 state_machine.A0_DMA_2 + Inst SIZE_c_i_1_ SIZE_c_i[1] + Inst state_machine_un25_clk_000_d0_i_0 state_machine.un25_clk_000_d0_i_0 + Inst state_machine_un24_bgack_030_int state_machine.un24_bgack_030_int + Inst SM_AMIGA_ns_i_5_ SM_AMIGA_ns_i[5] + Inst A_i_24_ A_i[24] + Inst SM_AMIGA_ns_i_0_ SM_AMIGA_ns_i[0] + Inst A_i_25_ A_i[25] + Inst A_i_26_ A_i[26] + Inst A_i_27_ A_i[27] + Inst A_i_28_ A_i[28] + Inst A_i_29_ A_i[29] + Inst state_machine_un8_bg_030_i state_machine.un8_bg_030_i + Inst A_i_30_ A_i[30] + Inst state_machine_un10_bg_030_i state_machine.un10_bg_030_i + Inst A_i_31_ A_i[31] + Inst state_machine_un10_bgack_030_int_i state_machine.un10_bgack_030_int_i + Inst state_machine_un3_clk_out_pre_50 state_machine.un3_clk_out_pre_50 + Inst state_machine_UDS_000_INT_7_i state_machine.UDS_000_INT_7_i + Inst state_machine_un3_clk_030_i_0 state_machine.un3_clk_030_i_0 + Inst state_machine_un57_clk_000_d0_i state_machine.un57_clk_000_d0_i + Inst state_machine_un51_clk_000_d0_i state_machine.un51_clk_000_d0_i + Inst state_machine_un53_clk_000_d0_i state_machine.un53_clk_000_d0_i + Inst state_machine_un3_bgack_030_int_d_i state_machine.un3_bgack_030_int_d_i + Net a_c_28__n A_c[28] + Net a_28__n A[28] + Net a_c_29__n A_c[29] + Net a_29__n A[29] + Net a_c_30__n A_c[30] + Net a_30__n A[30] + Net a_c_31__n A_c[31] + Net sm_amiga_1__n SM_AMIGA[1] + Net vcc_n_n VCC + Net gnd_n_n GND + Net sm_amiga_6__n SM_AMIGA[6] + Net sm_amiga_0__n SM_AMIGA[0] + Net sm_amiga_7__n SM_AMIGA[7] Net ipl_030_c_0__n IPL_030_c[0] + Net state_machine_un3_clk_out_pre_50_n state_machine.un3_clk_out_pre_50 Net ipl_030_0__n IPL_030[0] Net ipl_030_c_1__n IPL_030_c[1] - Net sm_amiga_7__n SM_AMIGA[7] Net ipl_030_1__n IPL_030[1] - Net vcc_n_n VCC Net ipl_030_c_2__n IPL_030_c[2] - Net gnd_n_n GND - Net state_machine_un10_clk_000_d0_n state_machine.un10_clk_000_d0 - Net ipl_c_0__n IPL_c[0] - Net ipl_0__n IPL[0] - Net sm_amiga_6__n SM_AMIGA[6] - Net ipl_c_1__n IPL_c[1] - Net sm_amiga_0__n SM_AMIGA[0] - Net ipl_1__n IPL[1] - Net sm_amiga_5__n SM_AMIGA[5] - Net ipl_c_2__n IPL_c[2] - Net sm_amiga_2__n SM_AMIGA[2] - Net state_machine_un3_clk_out_pre_50_n state_machine.un3_clk_out_pre_50 - Net state_machine_un12_clk_000_d0_n state_machine.un12_clk_000_d0 Net size_dma_0__n SIZE_DMA[0] Net size_dma_1__n SIZE_DMA[1] + Net ipl_c_0__n IPL_c[0] + Net ipl_0__n IPL[0] + Net sm_amiga_5__n SM_AMIGA[5] + Net ipl_c_1__n IPL_c[1] Net sm_amiga_4__n SM_AMIGA[4] + Net ipl_1__n IPL[1] Net sm_amiga_3__n SM_AMIGA[3] - Net sm_amiga_1__n SM_AMIGA[1] - Net fc_c_0__n FC_c[0] + Net ipl_c_2__n IPL_c[2] + Net sm_amiga_2__n SM_AMIGA[2] Net state_machine_a0_dma_2_n state_machine.A0_DMA_2 - Net fc_0__n FC[0] + Net state_machine_size_dma_4_0__n state_machine.SIZE_DMA_4[0] Net state_machine_size_dma_4_1__n state_machine.SIZE_DMA_4[1] + Net fc_c_0__n FC_c[0] + Net fc_0__n FC[0] Net fc_c_1__n FC_c[1] - Net state_machine_un10_bg_030_n state_machine.un10_bg_030 - Net state_machine_lds_000_int_7_n state_machine.LDS_000_INT_7 - Net state_machine_uds_000_int_7_n state_machine.UDS_000_INT_7 - Net state_machine_un6_bgack_000_0_n state_machine.un6_bgack_000_0 - Net state_machine_ds_000_dma_3_0_n state_machine.DS_000_DMA_3_0 - Net state_machine_size_dma_4_0_1__n state_machine.SIZE_DMA_4_0[1] Net sm_amiga_ns_0__n SM_AMIGA_ns[0] - Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5] + Net sm_amiga_ns_4__n SM_AMIGA_ns[4] Net sm_amiga_ns_5__n SM_AMIGA_ns[5] - Net sm_amiga_ns_2__n SM_AMIGA_ns[2] - Net sm_amiga_ns_6__n SM_AMIGA_ns[6] + Net sm_amiga_ns_7__n SM_AMIGA_ns[7] Net cpu_est_0__n cpu_est[0] + Net state_machine_un3_clk_000_d1_i_n state_machine.un3_clk_000_d1_i Net cpu_est_1__n cpu_est[1] + Net state_machine_un6_bgack_000_0_n state_machine.un6_bgack_000_0 Net cpu_est_2__n cpu_est[2] + Net cpu_est_ns_0_1__n cpu_est_ns_0[1] Net cpu_est_3__n cpu_est[3] + Net cpu_est_ns_e_0__n cpu_est_ns_e[0] Net cpu_est_ns_e_1__n cpu_est_ns_e[1] Net cpu_est_ns_e_2__n cpu_est_ns_e[2] Net cpu_est_ns_e_3__n cpu_est_ns_e[3] - Net state_machine_rw_000_int_7_iv_i_n state_machine.RW_000_INT_7_iv_i - Net cpu_est_ns_1__n cpu_est_ns[1] - Net cpu_est_ns_2__n cpu_est_ns[2] - Net sm_amiga_i_2__n SM_AMIGA_i[2] - Net cpu_est_ns_0_1__n cpu_est_ns_0[1] + Net state_machine_un8_bgack_030_int_n state_machine.un8_bgack_030_int + Net state_machine_un49_clk_000_d0_n state_machine.un49_clk_000_d0 + Net state_machine_un10_clk_000_d0_2_i_n state_machine.un10_clk_000_d0_2_i Net cpu_est_ns_0_2__n cpu_est_ns_0[2] - Net sm_amiga_ns_0_0__n SM_AMIGA_ns_0[0] - Net state_machine_lds_000_int_7_0_n state_machine.LDS_000_INT_7_0 - Net state_machine_uds_000_int_7_0_n state_machine.UDS_000_INT_7_0 - Net state_machine_un10_bg_030_0_n state_machine.un10_bg_030_0 Net state_machine_un10_clk_000_d0_i_n state_machine.un10_clk_000_d0_i Net state_machine_un12_clk_000_d0_0_n state_machine.un12_clk_000_d0_0 + Net state_machine_un24_bgack_030_int_n state_machine.un24_bgack_030_int + Net state_machine_clk_030_h_2_n state_machine.CLK_030_H_2 + Net state_machine_clk_030_h_2_f1_n state_machine.CLK_030_H_2_f1 Net state_machine_ds_000_dma_3_n state_machine.DS_000_DMA_3 - Net state_machine_un6_bgack_000_n state_machine.un6_bgack_000 - Net a_i_18__n A_i[18] - Net a_i_16__n A_i[16] - Net a_i_19__n A_i[19] - Net sm_amiga_i_4__n SM_AMIGA_i[4] - Net sm_amiga_i_5__n SM_AMIGA_i[5] - Net cpu_est_ns_0_1_1__n cpu_est_ns_0_1[1] - Net sm_amiga_i_3__n SM_AMIGA_i[3] - Net cpu_est_ns_0_2_1__n cpu_est_ns_0_2[1] - Net sm_amiga_i_0__n SM_AMIGA_i[0] - Net sm_amiga_i_1__n SM_AMIGA_i[1] - Net state_machine_un10_clk_000_d0_1_n state_machine.un10_clk_000_d0_1 - Net state_machine_un10_clk_000_d0_2_n state_machine.un10_clk_000_d0_2 + Net state_machine_un3_clk_030_i_n state_machine.un3_clk_030_i + Net state_machine_un57_clk_000_d0_i_n state_machine.un57_clk_000_d0_i + Net state_machine_un51_clk_000_d0_i_n state_machine.un51_clk_000_d0_i + Net state_machine_un53_clk_000_d0_0_n state_machine.un53_clk_000_d0_0 + Net state_machine_un3_bgack_030_int_d_i_n state_machine.un3_bgack_030_int_d_i + Net state_machine_un10_bgack_030_int_n state_machine.un10_bgack_030_int + Net state_machine_un25_clk_000_d0_n state_machine.un25_clk_000_d0 + Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5] + Net state_machine_un31_bgack_030_int_n state_machine.un31_bgack_030_int + Net state_machine_lds_000_int_7_n state_machine.LDS_000_INT_7 + Net state_machine_uds_000_int_7_n state_machine.UDS_000_INT_7 + Net sm_amiga_ns_0_0__n SM_AMIGA_ns_0[0] + Net state_machine_un8_bg_030_i_n state_machine.un8_bg_030_i + Net state_machine_un10_bg_030_n state_machine.un10_bg_030 + Net state_machine_un10_bg_030_0_n state_machine.un10_bg_030_0 + Net state_machine_un3_bgack_030_int_d_n state_machine.un3_bgack_030_int_d + Net state_machine_un5_bgack_030_int_d_i_n state_machine.un5_bgack_030_int_d_i + Net state_machine_un10_bgack_030_int_0_n state_machine.un10_bgack_030_int_0 + Net state_machine_uds_000_int_7_0_n state_machine.UDS_000_INT_7_0 + Net state_machine_un8_bg_030_n state_machine.un8_bg_030 + Net state_machine_lds_000_int_7_0_n state_machine.LDS_000_INT_7_0 + Net state_machine_size_dma_4_0_0__n state_machine.SIZE_DMA_4_0[0] + Net state_machine_size_dma_4_0_1__n state_machine.SIZE_DMA_4_0[1] + Net state_machine_un28_clk_000_d1_n state_machine.un28_clk_000_d1 + Net state_machine_rw_000_int_7_iv_i_n state_machine.RW_000_INT_7_iv_i + Net size_c_i_1__n SIZE_c_i[1] + Net state_machine_un10_clk_000_d0_n state_machine.un10_clk_000_d0 + Net state_machine_un25_clk_000_d0_i_n state_machine.un25_clk_000_d0_i + Net state_machine_un12_clk_000_d0_n state_machine.un12_clk_000_d0 + Net state_machine_un51_clk_000_d0_n state_machine.un51_clk_000_d0 + Net state_machine_un53_clk_000_d0_n state_machine.un53_clk_000_d0 + Net state_machine_un57_clk_000_d0_n state_machine.un57_clk_000_d0 + Net sm_amiga_ns_0_4__n SM_AMIGA_ns_0[4] + Net state_machine_un3_clk_030_n state_machine.un3_clk_030 + Net state_machine_ds_000_dma_3_0_n state_machine.DS_000_DMA_3_0 + Net state_machine_un28_clk_030_n state_machine.un28_clk_030 + Net state_machine_clk_030_h_2_f1_0_n state_machine.CLK_030_H_2_f1_0 + Net state_machine_un5_clk_000_d0_n state_machine.un5_clk_000_d0 + Net state_machine_un3_clk_000_d1_n state_machine.un3_clk_000_d1 + Net cpu_est_ns_2__n cpu_est_ns[2] + Net state_machine_un25_clk_000_d0_i_1_n state_machine.un25_clk_000_d0_i_1 Net cpu_est_ns_0_1_2__n cpu_est_ns_0_1[2] - Net sm_amiga_i_6__n SM_AMIGA_i[6] - Net state_machine_lds_000_int_7_0_1_n state_machine.LDS_000_INT_7_0_1 + Net state_machine_un10_clk_000_d0_2_n state_machine.un10_clk_000_d0_2 + Net cpu_est_ns_1__n cpu_est_ns[1] + Net state_machine_un6_bgack_000_n state_machine.un6_bgack_000 Net cpu_est_i_3__n cpu_est_i[3] - Net state_machine_uds_000_int_7_0_1_n state_machine.UDS_000_INT_7_0_1 - Net sm_amiga_i_7__n SM_AMIGA_i[7] + Net cpu_est_i_2__n cpu_est_i[2] Net cpu_est_i_1__n cpu_est_i[1] Net cpu_est_i_0__n cpu_est_i[0] - Net state_machine_a0_dma_2_1_n state_machine.A0_DMA_2_1 - Net cpu_est_i_2__n cpu_est_i[2] - Net size_i_1__n SIZE_i[1] - Net a_i_30__n A_i[30] - Net a_i_31__n A_i[31] - Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 - Net a_i_28__n A_i[28] - Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1 - Net a_i_29__n A_i[29] - Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0 - Net a_i_26__n A_i[26] - Net as_000_dma_0_un3_n AS_000_DMA_0.un3 - Net a_i_27__n A_i[27] - Net as_000_dma_0_un1_n AS_000_DMA_0.un1 - Net a_i_24__n A_i[24] - Net as_000_dma_0_un0_n AS_000_DMA_0.un0 - Net a_i_25__n A_i[25] - Net ds_000_dma_0_un3_n DS_000_DMA_0.un3 - Net ds_000_dma_0_un1_n DS_000_DMA_0.un1 - Net ds_000_dma_0_un0_n DS_000_DMA_0.un0 - Net clk_030_h_0_un3_n CLK_030_H_0.un3 - Net clk_030_h_0_un1_n CLK_030_H_0.un1 - Net clk_030_h_0_un0_n CLK_030_H_0.un0 - Net rw_000_int_0_un3_n RW_000_INT_0.un3 - Net rw_000_int_0_un1_n RW_000_INT_0.un1 - Net rw_000_int_0_un0_n RW_000_INT_0.un0 - Net state_machine_uds_000_int_7_0_m3_un3_n state_machine.UDS_000_INT_7_0_m3.un3 - Net state_machine_uds_000_int_7_0_m3_un1_n state_machine.UDS_000_INT_7_0_m3.un1 - Net state_machine_uds_000_int_7_0_m3_un0_n state_machine.UDS_000_INT_7_0_m3.un0 - Net ipl_030_0_0__un3_n IPL_030_0_0_.un3 - Net ipl_030_0_0__un1_n IPL_030_0_0_.un1 - Net ipl_030_0_0__un0_n IPL_030_0_0_.un0 - Net ipl_030_0_1__un3_n IPL_030_0_1_.un3 - Net ipl_030_0_1__un1_n IPL_030_0_1_.un1 - Net ipl_030_0_1__un0_n IPL_030_0_1_.un0 - Net ipl_030_0_2__un3_n IPL_030_0_2_.un3 - Net size_c_0__n SIZE_c[0] - Net ipl_030_0_2__un1_n IPL_030_0_2_.un1 - Net size_0__n SIZE[0] - Net ipl_030_0_2__un0_n IPL_030_0_2_.un0 - Net size_c_1__n SIZE_c[1] + Net state_machine_un28_clk_030_i_n state_machine.un28_clk_030_i + Net state_machine_un8_bg_030_1_n state_machine.un8_bg_030_1 + Net state_machine_un8_bg_030_2_n state_machine.un8_bg_030_2 + Net sm_amiga_i_1__n SM_AMIGA_i[1] + Net state_machine_un57_clk_000_d0_1_n state_machine.un57_clk_000_d0_1 + Net state_machine_un49_clk_000_d0_1_n state_machine.un49_clk_000_d0_1 + Net a_i_19__n A_i[19] + Net a_i_16__n A_i[16] + Net a_i_18__n A_i[18] + Net state_machine_un28_clk_030_1_n state_machine.un28_clk_030_1 + Net state_machine_un5_clk_000_d0_i_0_n state_machine.un5_clk_000_d0_i_0 + Net state_machine_un28_clk_030_2_n state_machine.un28_clk_030_2 + Net state_machine_un28_clk_030_3_n state_machine.un28_clk_030_3 + Net sm_amiga_i_7__n SM_AMIGA_i[7] + Net state_machine_un28_clk_030_4_n state_machine.un28_clk_030_4 + Net sm_amiga_i_0__n SM_AMIGA_i[0] + Net state_machine_un28_clk_030_5_n state_machine.un28_clk_030_5 + Net state_machine_un5_clk_000_d0_1_n state_machine.un5_clk_000_d0_1 + Net sm_amiga_i_2__n SM_AMIGA_i[2] + Net state_machine_un5_clk_000_d0_2_n state_machine.un5_clk_000_d0_2 + Net state_machine_un10_clk_000_d0_1_n state_machine.un10_clk_000_d0_1 + Net state_machine_un10_clk_000_d0_2_0_n state_machine.un10_clk_000_d0_2_0 + Net sm_amiga_i_6__n SM_AMIGA_i[6] + Net state_machine_un10_clk_000_d0_3_n state_machine.un10_clk_000_d0_3 + Net cpu_est_ns_0_1_1__n cpu_est_ns_0_1[1] + Net cpu_est_ns_0_2_1__n cpu_est_ns_0_2[1] + Net state_machine_un28_clk_000_d1_1_n state_machine.un28_clk_000_d1_1 + Net state_machine_un8_bgack_030_int_i_n state_machine.un8_bgack_030_int_i + Net cpu_estse_2_un3_n cpu_estse_2.un3 + Net state_machine_un31_bgack_030_int_i_n state_machine.un31_bgack_030_int_i + Net cpu_estse_2_un1_n cpu_estse_2.un1 + Net sm_amiga_i_5__n SM_AMIGA_i[5] + Net cpu_estse_2_un0_n cpu_estse_2.un0 + Net cpu_estse_1_un3_n cpu_estse_1.un3 + Net cpu_estse_1_un1_n cpu_estse_1.un1 + Net cpu_estse_1_un0_n cpu_estse_1.un0 Net cpu_estse_0_un3_n cpu_estse_0.un3 Net cpu_estse_0_un1_n cpu_estse_0.un1 - Net a_c_16__n A_c[16] Net cpu_estse_0_un0_n cpu_estse_0.un0 - Net a_16__n A[16] - Net cpu_estse_1_un3_n cpu_estse_1.un3 - Net a_c_17__n A_c[17] - Net cpu_estse_1_un1_n cpu_estse_1.un1 - Net a_17__n A[17] - Net cpu_estse_1_un0_n cpu_estse_1.un0 - Net a_c_18__n A_c[18] - Net cpu_estse_2_un3_n cpu_estse_2.un3 - Net a_18__n A[18] - Net cpu_estse_2_un1_n cpu_estse_2.un1 - Net a_c_19__n A_c[19] - Net cpu_estse_2_un0_n cpu_estse_2.un0 - Net a_19__n A[19] + Net state_machine_un49_clk_000_d0_i_n state_machine.un49_clk_000_d0_i + Net ipl_030_0_2__un3_n IPL_030_0_2_.un3 + Net ipl_030_0_2__un1_n IPL_030_0_2_.un1 + Net state_machine_un24_bgack_030_int_i_n state_machine.un24_bgack_030_int_i + Net ipl_030_0_2__un0_n IPL_030_0_2_.un0 + Net ipl_030_0_1__un3_n IPL_030_0_1_.un3 + Net sm_amiga_i_4__n SM_AMIGA_i[4] + Net ipl_030_0_1__un1_n IPL_030_0_1_.un1 + Net a_i_30__n A_i[30] + Net ipl_030_0_1__un0_n IPL_030_0_1_.un0 + Net a_i_31__n A_i[31] + Net ipl_030_0_0__un3_n IPL_030_0_0_.un3 + Net a_i_28__n A_i[28] + Net ipl_030_0_0__un1_n IPL_030_0_0_.un1 + Net a_i_29__n A_i[29] + Net ipl_030_0_0__un0_n IPL_030_0_0_.un0 + Net a_i_26__n A_i[26] + Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 + Net a_i_27__n A_i[27] + Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1 + Net a_i_24__n A_i[24] + Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0 + Net a_i_25__n A_i[25] Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3 - Net a_c_20__n A_c[20] Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1 - Net a_20__n A[20] Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0 - Net a_c_21__n A_c[21] - Net uds_000_int_0_un3_n UDS_000_INT_0.un3 - Net a_21__n A[21] - Net uds_000_int_0_un1_n UDS_000_INT_0.un1 - Net a_c_22__n A_c[22] - Net uds_000_int_0_un0_n UDS_000_INT_0.un0 - Net a_22__n A[22] - Net lds_000_int_0_un3_n LDS_000_INT_0.un3 - Net a_c_23__n A_c[23] - Net lds_000_int_0_un1_n LDS_000_INT_0.un1 - Net a_23__n A[23] - Net lds_000_int_0_un0_n LDS_000_INT_0.un0 - Net a_c_24__n A_c[24] Net fpu_cs_int_0_un3_n FPU_CS_INT_0.un3 - Net a_24__n A[24] Net fpu_cs_int_0_un1_n FPU_CS_INT_0.un1 - Net a_c_25__n A_c[25] Net fpu_cs_int_0_un0_n FPU_CS_INT_0.un0 - Net a_25__n A[25] - Net avec_exp_0_un3_n avec_exp_0.un3 - Net a_c_26__n A_c[26] - Net avec_exp_0_un1_n avec_exp_0.un1 - Net a_26__n A[26] - Net avec_exp_0_un0_n avec_exp_0.un0 - Net a_c_27__n A_c[27] - Net bg_000_0_un3_n BG_000_0.un3 - Net a_27__n A[27] - Net bg_000_0_un1_n BG_000_0.un1 - Net a_c_28__n A_c[28] - Net bg_000_0_un0_n BG_000_0.un0 - Net a_28__n A[28] Net as_000_int_0_un3_n AS_000_INT_0.un3 - Net a_c_29__n A_c[29] Net as_000_int_0_un1_n AS_000_INT_0.un1 - Net a_29__n A[29] Net as_000_int_0_un0_n AS_000_INT_0.un0 - Net a_c_30__n A_c[30] Net dsack1_int_0_un3_n DSACK1_INT_0.un3 - Net a_30__n A[30] Net dsack1_int_0_un1_n DSACK1_INT_0.un1 - Net a_c_31__n A_c[31] Net dsack1_int_0_un0_n DSACK1_INT_0.un0 Net vma_int_0_un3_n VMA_INT_0.un3 Net vma_int_0_un1_n VMA_INT_0.un1 Net vma_int_0_un0_n VMA_INT_0.un0 + Net avec_exp_0_un3_n avec_exp_0.un3 + Net avec_exp_0_un1_n avec_exp_0.un1 + Net size_c_0__n SIZE_c[0] + Net avec_exp_0_un0_n avec_exp_0.un0 + Net size_0__n SIZE[0] + Net bg_000_0_un3_n BG_000_0.un3 + Net size_c_1__n SIZE_c[1] + Net bg_000_0_un1_n BG_000_0.un1 + Net bg_000_0_un0_n BG_000_0.un0 + Net a_c_16__n A_c[16] + Net lds_000_int_0_un3_n LDS_000_INT_0.un3 + Net a_16__n A[16] + Net lds_000_int_0_un1_n LDS_000_INT_0.un1 + Net a_c_17__n A_c[17] + Net lds_000_int_0_un0_n LDS_000_INT_0.un0 + Net a_17__n A[17] + Net uds_000_int_0_un3_n UDS_000_INT_0.un3 + Net a_c_18__n A_c[18] + Net uds_000_int_0_un1_n UDS_000_INT_0.un1 + Net a_18__n A[18] + Net uds_000_int_0_un0_n UDS_000_INT_0.un0 + Net a_c_19__n A_c[19] + Net rw_000_int_0_un3_n RW_000_INT_0.un3 + Net a_19__n A[19] + Net rw_000_int_0_un1_n RW_000_INT_0.un1 + Net a_c_20__n A_c[20] + Net rw_000_int_0_un0_n RW_000_INT_0.un0 + Net a_20__n A[20] + Net as_000_dma_0_un3_n AS_000_DMA_0.un3 + Net a_c_21__n A_c[21] + Net as_000_dma_0_un1_n AS_000_DMA_0.un1 + Net a_21__n A[21] + Net as_000_dma_0_un0_n AS_000_DMA_0.un0 + Net a_c_22__n A_c[22] + Net ds_000_dma_0_un3_n DS_000_DMA_0.un3 + Net a_22__n A[22] + Net ds_000_dma_0_un1_n DS_000_DMA_0.un1 + Net a_c_23__n A_c[23] + Net ds_000_dma_0_un0_n DS_000_DMA_0.un0 + Net a_23__n A[23] + Net clk_030_h_0_un3_n CLK_030_H_0.un3 + Net a_c_24__n A_c[24] + Net clk_030_h_0_un1_n CLK_030_H_0.un1 + Net a_24__n A[24] + Net clk_030_h_0_un0_n CLK_030_H_0.un0 + Net a_c_25__n A_c[25] + Net a_25__n A[25] + Net a_c_26__n A_c[26] + Net a_26__n A[26] + Net a_c_27__n A_c[27] + Net a_27__n A[27] End Section Type Name // ---------------------------------------------------------------------- diff --git a/Logic/bus68030.srf b/Logic/bus68030.srf index 767bba0..97ebf54 100644 --- a/Logic/bus68030.srf +++ b/Logic/bus68030.srf @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Sun Jun 01 01:03:18 2014 +#Sat Jun 07 23:03:13 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode @@ -23,6 +23,7 @@ Post processing for work.bus68030.behavioral @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:34:127:36|Pruning register CLK_000_D6 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_000_D5 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:34:125:36|Pruning register CLK_000_D4 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:34:124:36|Pruning register CLK_000_D3 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:38:117:40|Pruning register CLK_OUT_PRE_33 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_P(1 downto 0) @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:2:136:3|Pruning register CLK_CNT_N(1 downto 0) @@ -54,7 +55,7 @@ State machine has 11 reachable states with original encodings of: 1111 @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sun Jun 01 01:03:18 2014 +# Sat Jun 07 23:03:13 2014 ###########################################################] Map & Optimize Report @@ -91,16 +92,16 @@ Resource Usage Report Simple gate primitives: DFFRH 16 uses -DFFSH 27 uses +DFFSH 26 uses DFF 1 use BI_DIR 12 uses IBUF 29 uses BUFTH 2 uses OBUF 16 uses AND2 185 uses -INV 151 uses -OR2 21 uses -XOR2 1 use +INV 148 uses +OR2 20 uses +XOR2 2 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -110,6 +111,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sun Jun 01 01:03:19 2014 +# Sat Jun 07 23:03:15 2014 ###########################################################] diff --git a/Logic/run_options.txt b/Logic/run_options.txt index 7467fad..17c2fbd 100644 --- a/Logic/run_options.txt +++ b/Logic/run_options.txt @@ -1,7 +1,7 @@ #-- Synopsys, Inc. #-- Version G-2012.09LC-SP1 #-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt -#-- Written on Sun Jun 01 01:03:18 2014 +#-- Written on Sat Jun 07 23:03:13 2014 #project files diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr index ff3d9f0..470684b 100644 --- a/Logic/synlog/bus68030_fpga_mapper.srr +++ b/Logic/synlog/bus68030_fpga_mapper.srr @@ -30,16 +30,16 @@ Resource Usage Report Simple gate primitives: DFFRH 16 uses -DFFSH 27 uses +DFFSH 26 uses DFF 1 use BI_DIR 12 uses IBUF 29 uses BUFTH 2 uses OBUF 16 uses AND2 185 uses -INV 151 uses -OR2 21 uses -XOR2 1 use +INV 148 uses +OR2 20 uses +XOR2 2 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -49,6 +49,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sun Jun 01 01:03:19 2014 +# Sat Jun 07 23:03:15 2014 ###########################################################] diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml index 03277cf..f6d1798 100644 --- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml +++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml @@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt - 7 + 8 C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt @@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t - - 1401577398 + 1402174993 \ No newline at end of file diff --git a/Logic/synlog/report/BUS68030_compiler_warnings.txt b/Logic/synlog/report/BUS68030_compiler_warnings.txt index 4692fd5..c6c0e97 100644 --- a/Logic/synlog/report/BUS68030_compiler_warnings.txt +++ b/Logic/synlog/report/BUS68030_compiler_warnings.txt @@ -2,6 +2,7 @@ @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:34:127:36|Pruning register CLK_000_D6 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_000_D5 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:34:125:36|Pruning register CLK_000_D4 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:34:124:36|Pruning register CLK_000_D3 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:38:117:40|Pruning register CLK_OUT_PRE_33 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_P(1 downto 0) @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:2:136:3|Pruning register CLK_CNT_N(1 downto 0) diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml index 7cf21a2..04fdaad 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml +++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml @@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the 95MB -1401577399 +1402174995 diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml index 040bf97..a6ed1e3 100644 --- a/Logic/syntmp/run_option.xml +++ b/Logic/syntmp/run_option.xml @@ -3,7 +3,7 @@ Synopsys, Inc. Version G-2012.09LC-SP1 Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml - Written on Sun Jun 01 01:03:18 2014 + Written on Sat Jun 07 23:03:13 2014 --> diff --git a/Logic/synwork/BUS68030_compiler.fdep b/Logic/synwork/BUS68030_compiler.fdep index 3067dfa..affdaa1 100644 --- a/Logic/synwork/BUS68030_compiler.fdep +++ b/Logic/synwork/BUS68030_compiler.fdep @@ -10,7 +10,7 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1401577392 +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1402174986 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) diff --git a/Logic/synwork/BUS68030_compiler.fdeporig b/Logic/synwork/BUS68030_compiler.fdeporig index 8b9175a..8e51ce7 100644 --- a/Logic/synwork/BUS68030_compiler.fdeporig +++ b/Logic/synwork/BUS68030_compiler.fdeporig @@ -10,7 +10,7 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1401577392 +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1402174986 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) diff --git a/Logic/synwork/BUS68030_compiler.srs b/Logic/synwork/BUS68030_compiler.srs index fda9761..1ea6759 100644 Binary files a/Logic/synwork/BUS68030_compiler.srs and b/Logic/synwork/BUS68030_compiler.srs differ diff --git a/Logic/synwork/BUS68030_compiler.tlg b/Logic/synwork/BUS68030_compiler.tlg index 7fd4607..0b54c1f 100644 --- a/Logic/synwork/BUS68030_compiler.tlg +++ b/Logic/synwork/BUS68030_compiler.tlg @@ -4,6 +4,7 @@ Post processing for work.bus68030.behavioral @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:34:127:36|Pruning register CLK_000_D6 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_000_D5 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:34:125:36|Pruning register CLK_000_D4 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:34:124:36|Pruning register CLK_000_D3 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:38:117:40|Pruning register CLK_OUT_PRE_33 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":149:2:149:3|Pruning register CLK_CNT_P(1 downto 0) @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":136:2:136:3|Pruning register CLK_CNT_N(1 downto 0)