diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index dc6d8c4..ed19dd2 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -186,7 +186,7 @@ begin AS_030_000_SYNC <= '1'; UDS_000_INT <= '1'; LDS_000_INT <= '1'; - CLK_REF <= "00"; + CLK_REF <= "01"; VMA_INT <= '1'; FPU_CS_INT <= '1'; BG_000 <= '1'; diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index 224f7dd..941e51c 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -132682,3 +132682,4045 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 05/18/14 21:01:40 ########### + +########## Tcl recorder starts at 05/21/14 19:55:50 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 19:55:50 ########### + + +########## Tcl recorder starts at 05/21/14 19:55:55 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 19:55:55 ########### + + +########## Tcl recorder starts at 05/21/14 19:57:36 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 19:57:36 ########### + + +########## Tcl recorder starts at 05/21/14 19:57:40 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 19:57:40 ########### + + +########## Tcl recorder starts at 05/21/14 19:58:45 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 19:58:45 ########### + + +########## Tcl recorder starts at 05/21/14 20:29:54 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:29:54 ########### + + +########## Tcl recorder starts at 05/21/14 20:29:57 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:29:57 ########### + + +########## Tcl recorder starts at 05/21/14 20:31:35 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:31:35 ########### + + +########## Tcl recorder starts at 05/21/14 20:31:45 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:31:45 ########### + + +########## Tcl recorder starts at 05/21/14 20:32:20 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:32:20 ########### + + +########## Tcl recorder starts at 05/21/14 20:32:23 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:32:23 ########### + + +########## Tcl recorder starts at 05/21/14 20:33:04 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:33:04 ########### + + +########## Tcl recorder starts at 05/21/14 20:33:07 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:33:07 ########### + + +########## Tcl recorder starts at 05/21/14 20:35:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:35:08 ########### + + +########## Tcl recorder starts at 05/21/14 20:35:14 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:35:14 ########### + + +########## Tcl recorder starts at 05/21/14 20:35:21 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:35:21 ########### + + +########## Tcl recorder starts at 05/21/14 20:35:35 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:35:35 ########### + + +########## Tcl recorder starts at 05/21/14 20:35:37 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:35:37 ########### + + +########## Tcl recorder starts at 05/21/14 20:36:44 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:36:44 ########### + + +########## Tcl recorder starts at 05/21/14 20:36:47 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:36:47 ########### + + +########## Tcl recorder starts at 05/21/14 20:45:03 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:45:03 ########### + + +########## Tcl recorder starts at 05/21/14 20:45:07 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:45:07 ########### + + +########## Tcl recorder starts at 05/21/14 20:50:27 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:50:27 ########### + + +########## Tcl recorder starts at 05/21/14 20:50:33 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 20:50:33 ########### + + +########## Tcl recorder starts at 05/21/14 21:11:37 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 21:11:37 ########### + + +########## Tcl recorder starts at 05/21/14 21:11:43 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 21:11:43 ########### + + +########## Tcl recorder starts at 05/21/14 21:16:14 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 21:16:14 ########### + + +########## Tcl recorder starts at 05/21/14 21:16:17 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 21:16:17 ########### + + +########## Tcl recorder starts at 05/21/14 21:18:01 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 21:18:01 ########### + + +########## Tcl recorder starts at 05/21/14 21:18:06 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 21:18:06 ########### + + +########## Tcl recorder starts at 05/21/14 21:44:30 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 21:44:30 ########### + + +########## Tcl recorder starts at 05/21/14 21:44:34 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 21:44:34 ########### + + +########## Tcl recorder starts at 05/21/14 21:46:53 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 21:46:53 ########### + + +########## Tcl recorder starts at 05/21/14 21:47:06 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 21:47:06 ########### + + +########## Tcl recorder starts at 05/21/14 21:48:40 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 21:48:40 ########### + + +########## Tcl recorder starts at 05/21/14 21:48:43 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 21:48:43 ########### + + +########## Tcl recorder starts at 05/21/14 21:52:13 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 21:52:13 ########### + + +########## Tcl recorder starts at 05/21/14 21:52:17 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/21/14 21:52:18 ########### + + +########## Tcl recorder starts at 05/22/14 14:26:55 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/22/14 14:26:55 ########### + + +########## Tcl recorder starts at 05/22/14 14:32:18 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/22/14 14:32:18 ########### + + +########## Tcl recorder starts at 05/22/14 14:32:23 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/22/14 14:32:23 ########### + + +########## Tcl recorder starts at 05/22/14 14:33:52 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/22/14 14:33:52 ########### + + +########## Tcl recorder starts at 05/22/14 14:33:55 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/22/14 14:33:55 ########### + + +########## Tcl recorder starts at 05/22/14 14:55:59 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/22/14 14:55:59 ########### + + +########## Tcl recorder starts at 05/22/14 14:56:03 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/22/14 14:56:03 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index 201fe70..d42a989 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,92 +1,92 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sun May 18 21:01:47 2014 +#$ DATE Thu May 22 14:56:10 2014 #$ MODULE 68030_tk #$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 \ -# SIZE_0_ LDS_000 A_30_ nEXP_SPACE A_29_ BERR A_28_ BG_030 A_27_ BG_000 A_26_ BGACK_030 \ -# A_25_ BGACK_000 A_24_ CLK_030 A_23_ CLK_000 A_22_ CLK_OSZI A_21_ CLK_DIV_OUT A_20_ \ -# CLK_EXP A_19_ FPU_CS A_18_ DTACK A_17_ AVEC A_16_ AVEC_EXP A_15_ E A_14_ VPA A_13_ VMA A_12_ \ -# RST A_11_ RESET A_10_ RW A_9_ AMIGA_BUS_ENABLE A_8_ AMIGA_BUS_DATA_DIR A_7_ \ -# AMIGA_BUS_ENABLE_LOW A_6_ CIIN A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ \ -# IPL_0_ DSACK_0_ FC_0_ -#$ NODES 369 BGACK_000_c CLK_030_c CLK_000_c CLK_OSZI_c inst_BGACK_030_INTreg \ -# inst_FPU_CS_INTreg cpu_est_3_reg CLK_OUT_INTreg inst_VMA_INTreg cpu_est_0_ \ -# cpu_est_1_ IPL_030DFFSH_0_reg inst_AS_000_INTreg inst_AS_030_000_SYNC \ -# IPL_030DFFSH_1_reg inst_DTACK_SYNC inst_VPA_D IPL_030DFFSH_2_reg inst_VPA_SYNC \ -# inst_CLK_000_D0 ipl_c_0__n inst_CLK_000_D1 inst_CLK_000_D2 ipl_c_1__n \ -# inst_CLK_OUT_PRE SM_AMIGA_6_ ipl_c_2__n vcc_n_n gnd_n_n cpu_est_2_ dsack_c_1__n \ -# CLK_REF_1_ SM_AMIGA_7_ DTACK_c inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ \ -# clk_un4_clk_000_d1_n SM_AMIGA_4_ SM_AMIGA_1_ inst_DTACK_DMA clk_clk_cnt_n RST_c \ -# CLK_CNT_0_ CLK_CNT_1_ RESETDFFreg state_machine_un14_as_000_int_n SM_AMIGA_3_ RW_c \ -# fc_c_0__n un1_as_030_4 SM_AMIGA_5_ fc_c_1__n SM_AMIGA_2_ SM_AMIGA_0_ \ -# AMIGA_BUS_ENABLEDFFreg state_machine_lds_000_int_7_n \ -# state_machine_uds_000_int_7_n N_101_i N_102_i N_103_i N_90_0 N_91_0 N_127_i N_128_i \ -# CLK_OUT_PRE_0 N_118_i N_125_i cpu_est_0_0_ N_123_i N_124_i N_126_i \ -# clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i N_129_i N_122_i N_121_i \ -# N_108_i G_86 sm_amiga_ns_0_7__n state_machine_un30_clk_000_d1_n \ -# state_machine_un8_clk_000_d0_i_n N_147 state_machine_un13_clk_000_d0_i_n N_96 \ -# state_machine_un15_clk_000_d0_0_n state_machine_un44_clk_000_d1_n \ -# state_machine_un23_clk_000_d0_i_n G_90 N_100_i N_89 sm_amiga_ns_0_2__n N_97 \ -# BG_030_c_i N_90 state_machine_un1_clk_030_0_n N_98 clk_un4_clk_000_d1_i_n N_99 \ -# state_machine_un6_bgack_000_0_n UDS_000_INT_0_sqmuxa \ -# state_machine_un17_clk_030_0_n UDS_000_INT_0_sqmuxa_1 un1_as_030_3_0 N_167 N_89_i \ -# N_170 AMIGA_BUS_ENABLE_i_m_i N_105 nEXP_SPACE_m_i N_92 \ -# state_machine_amiga_bus_enable_2_iv_i_n N_106 \ -# state_machine_as_030_000_sync_3_2_n N_107 N_94_i N_104 un1_bg_030_0 \ -# state_machine_un42_clk_030_n N_105_i un1_bg_030 N_104_i N_94 sm_amiga_ns_0_5__n \ -# state_machine_as_030_000_sync_3_n N_106_i AMIGA_BUS_ENABLE_i_m N_107_i \ -# nEXP_SPACE_m N_95 CLK_OUT_PRE_i un1_as_030_3 N_92_0 state_machine_un17_clk_030_n \ -# state_machine_un44_clk_000_d1_i_n state_machine_un6_bgack_000_n a_c_i_0__n \ -# state_machine_un1_clk_030_n size_c_i_1__n AS_000_INT_1_sqmuxa N_98_i \ -# DSACK_INT_1_sqmuxa N_99_i N_100 sm_amiga_ns_0_1__n state_machine_un23_clk_000_d0_n \ -# N_97_i DTACK_SYNC_1_sqmuxa DTACK_SYNC_1_sqmuxa_1 N_147_i VPA_SYNC_1_sqmuxa \ -# state_machine_lds_000_int_7_0_n VPA_SYNC_1_sqmuxa_1 \ -# state_machine_uds_000_int_7_0_n state_machine_un15_clk_000_d0_n un1_bg_030_0_1 \ -# clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n \ +# LDS_000 nEXP_SPACE BERR SIZE_0_ BG_030 A_30_ BG_000 A_29_ BGACK_030 A_28_ BGACK_000 A_27_ \ +# CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI A_24_ CLK_DIV_OUT A_23_ CLK_EXP A_22_ FPU_CS A_21_ \ +# DTACK A_20_ AVEC A_19_ AVEC_EXP A_18_ E A_17_ VPA A_16_ VMA A_15_ RST A_14_ RESET A_13_ RW \ +# A_12_ AMIGA_BUS_ENABLE A_11_ AMIGA_BUS_DATA_DIR A_10_ AMIGA_BUS_ENABLE_LOW A_9_ CIIN \ +# A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ DSACK_0_ \ +# FC_0_ +#$ NODES 372 BG_000DFFSHreg BGACK_000_c CLK_030_c inst_BGACK_030_INTreg CLK_000_c \ +# inst_FPU_CS_INTreg cpu_est_3_reg CLK_OSZI_c inst_VMA_INTreg cpu_est_0_ cpu_est_1_ \ +# CLK_OUT_INTreg inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC \ +# IPL_030DFFSH_0_reg inst_VPA_D inst_VPA_SYNC IPL_030DFFSH_1_reg inst_CLK_000_D0 \ +# inst_CLK_000_D1 IPL_030DFFSH_2_reg inst_CLK_000_D2 inst_CLK_OUT_PRE ipl_c_0__n \ +# SM_AMIGA_6_ vcc_n_n ipl_c_1__n gnd_n_n cpu_est_2_ ipl_c_2__n CLK_REF_0_ CLK_REF_1_ \ +# SM_AMIGA_7_ dsack_c_1__n inst_UDS_000_INTreg inst_LDS_000_INTreg DTACK_c \ +# DSACK_INT_1_ SM_AMIGA_4_ SM_AMIGA_1_ inst_DTACK_DMA clk_clk_cnt_n CLK_CNT_0_ \ +# CLK_CNT_1_ state_machine_un14_as_000_int_n RST_c SM_AMIGA_3_ RESETDFFreg \ +# SM_AMIGA_5_ RW_c SM_AMIGA_2_ SM_AMIGA_0_ fc_c_0__n fc_c_1__n AMIGA_BUS_ENABLEDFFreg \ +# N_101_i N_102_i N_103_i CLK_OUT_PRE_0 cpu_est_0_0_ N_91_0 N_125_i N_123_i N_124_i \ +# N_126_i clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i N_129_i N_122_i \ +# G_86 N_121_i G_87 N_127_i state_machine_un30_clk_000_d1_n N_128_i N_148 N_118_i \ +# DTACK_SYNC_1_sqmuxa state_machine_un8_clk_000_d0_i_n N_96 \ +# state_machine_un13_clk_000_d0_i_n G_91 state_machine_un15_clk_000_d0_0_n N_89 \ +# N_100_i N_97 sm_amiga_ns_0_2__n N_90 clk_un4_clk_000_d1_i_n N_98 \ +# state_machine_un6_bgack_000_0_n N_99 state_machine_un23_clk_000_d0_i_n N_108 \ +# BG_030_c_i UDS_000_INT_0_sqmuxa state_machine_un1_clk_030_0_n \ +# UDS_000_INT_0_sqmuxa_1 state_machine_un17_clk_030_0_n \ +# state_machine_un13_clk_000_d0_1_n un1_as_030_3_0 N_168 N_148_i N_171 a_c_i_0__n \ +# N_105 state_machine_uds_000_int_7_0_n N_92 state_machine_lds_000_int_7_0_n N_106 \ +# AMIGA_BUS_ENABLE_i_m_i N_107 nEXP_SPACE_m_i N_104 \ +# state_machine_amiga_bus_enable_2_iv_i_n state_machine_un42_clk_030_n \ +# state_machine_as_030_000_sync_3_2_n state_machine_un44_clk_000_d1_n N_94_i \ +# un1_bg_030 un1_bg_030_0 N_94 size_c_i_1__n state_machine_as_030_000_sync_3_n \ +# state_machine_un44_clk_000_d1_i_n AMIGA_BUS_ENABLE_i_m N_105_i nEXP_SPACE_m \ +# N_104_i N_95 sm_amiga_ns_0_5__n state_machine_lds_000_int_7_n N_106_i \ +# state_machine_uds_000_int_7_n N_107_i DTACK_SYNC_1_sqmuxa_1 un1_as_030_4 \ +# CLK_OUT_PRE_i un1_as_030_3 N_92_0 DSACK_INT_1_sqmuxa N_90_0 \ +# state_machine_un17_clk_030_n N_89_i state_machine_un1_clk_030_n N_108_i \ +# state_machine_un23_clk_000_d0_n sm_amiga_ns_0_7__n VPA_SYNC_1_sqmuxa N_98_i \ +# VPA_SYNC_1_sqmuxa_1 N_99_i AS_000_INT_1_sqmuxa sm_amiga_ns_0_1__n \ +# state_machine_un6_bgack_000_n N_97_i clk_un4_clk_000_d1_n N_100 \ +# state_machine_un44_clk_000_d1_i_1_n state_machine_un15_clk_000_d0_n \ +# un1_bg_030_0_1 clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n \ # state_machine_as_030_000_sync_3_2_1_n state_machine_un13_clk_000_d0_n \ # clk_cpu_est_11_0_1_1__n state_machine_un8_clk_000_d0_n clk_cpu_est_11_0_2_1__n \ -# N_108 N_167_1 state_machine_un13_clk_000_d0_1_n N_167_2 N_124 N_167_3 N_126 N_167_4 \ -# state_machine_un13_clk_000_d0_2_n N_167_5 N_129 N_167_6 N_122 N_170_1 N_130 N_170_2 \ -# N_121 UDS_000_INT_0_sqmuxa_1_1 N_131 UDS_000_INT_0_sqmuxa_1_2 N_127 \ -# UDS_000_INT_0_sqmuxa_1_3 clk_cpu_est_11_1__n UDS_000_INT_0_sqmuxa_1_0 N_128 \ -# state_machine_un44_clk_000_d1_i_1_n N_123 state_machine_un42_clk_030_1_n N_125 \ -# state_machine_un42_clk_030_2_n N_91 state_machine_un42_clk_030_3_n N_102 \ -# state_machine_un42_clk_030_4_n N_103 state_machine_un42_clk_030_5_n N_101 N_96_1 \ -# RW_i AMIGA_BUS_ENABLE_i_m_1 AS_000_INT_i N_131_1 dsack_i_1__n \ -# clk_cpu_est_11_0_1_3__n sm_amiga_i_4__n N_105_1 sm_amiga_i_5__n \ -# VPA_SYNC_1_sqmuxa_1_0 CLK_000_D0_i VPA_SYNC_1_sqmuxa_2 sm_amiga_i_3__n \ -# VPA_SYNC_1_sqmuxa_3 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_4 cpu_est_i_2__n \ -# VPA_SYNC_1_sqmuxa_5 state_machine_un13_clk_000_d0_2_i_n VPA_SYNC_1_sqmuxa_6 \ -# cpu_est_i_3__n DTACK_SYNC_1_sqmuxa_1_0 VPA_D_i DTACK_SYNC_1_sqmuxa_2 \ -# cpu_est_i_1__n state_machine_un8_clk_000_d0_1_n DTACK_i \ -# state_machine_un8_clk_000_d0_2_n VMA_INT_i state_machine_un8_clk_000_d0_3_n \ -# state_machine_un13_clk_000_d0_1_i_n state_machine_un8_clk_000_d0_4_n AS_030_i \ -# state_machine_un13_clk_000_d0_1_0_n DTACK_SYNC_1_sqmuxa_i \ -# state_machine_un13_clk_000_d0_2_0_n VPA_SYNC_1_sqmuxa_i N_127_1 CLK_000_D1_i \ -# N_128_1 N_95_i ipl_030_0_2__un3_n N_96_i ipl_030_0_2__un1_n a_i_18__n \ -# ipl_030_0_2__un0_n a_i_16__n ipl_030_0_1__un3_n a_i_19__n ipl_030_0_1__un1_n \ -# CLK_030_i ipl_030_0_1__un0_n CLK_000_D2_i ipl_030_0_0__un3_n \ -# state_machine_un42_clk_030_i_n ipl_030_0_0__un1_n sm_amiga_i_6__n \ -# ipl_030_0_0__un0_n sm_amiga_i_7__n cpu_est_0_2__un3_n AMIGA_BUS_ENABLE_i \ -# cpu_est_0_2__un1_n nEXP_SPACE_i cpu_est_0_2__un0_n sm_amiga_i_2__n \ -# cpu_est_0_1__un3_n sm_amiga_i_1__n cpu_est_0_1__un1_n DS_030_i cpu_est_0_1__un0_n \ -# AS_030_000_SYNC_i vpa_sync_0_un3_n UDS_000_INT_0_sqmuxa_1_i vpa_sync_0_un1_n \ -# UDS_000_INT_0_sqmuxa_i vpa_sync_0_un0_n clk_clk_cnt_i_n vma_int_0_un3_n \ -# clk_cnt_i_0__n vma_int_0_un1_n a_i_30__n vma_int_0_un0_n a_i_31__n \ -# cpu_est_0_3__un3_n a_i_28__n cpu_est_0_3__un1_n a_i_29__n cpu_est_0_3__un0_n \ -# a_i_26__n bgack_030_int_0_un3_n a_i_27__n bgack_030_int_0_un1_n a_i_24__n \ -# bgack_030_int_0_un0_n a_i_25__n bg_000_0_un3_n N_132_i bg_000_0_un1_n \ -# bg_000_0_un0_n RST_i amiga_bus_enable_0_un3_n FPU_CS_INT_i \ -# amiga_bus_enable_0_un1_n BGACK_030_INT_i amiga_bus_enable_0_un0_n AS_030_c \ -# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n DS_030_c \ -# fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n as_000_int_0_un3_n \ -# size_c_0__n as_000_int_0_un1_n as_000_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n \ -# dsack_int_0_1__un1_n a_c_0__n dsack_int_0_1__un0_n dtack_sync_0_un3_n \ -# dtack_sync_0_un1_n dtack_sync_0_un0_n uds_000_int_0_un3_n uds_000_int_0_un1_n \ -# uds_000_int_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n \ -# a_15__n a_14__n a_13__n a_12__n a_c_16__n a_11__n a_c_17__n a_10__n a_c_18__n a_9__n \ -# a_c_19__n a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n a_5__n a_c_23__n a_4__n \ -# a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n a_c_28__n a_c_29__n \ -# a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c BG_000DFFSHreg +# N_129 N_168_1 N_122 N_168_2 N_130 N_168_3 N_127 N_168_4 N_128 N_168_5 N_121 N_168_6 \ +# state_machine_un13_clk_000_d0_2_n N_171_1 N_131 N_171_2 clk_cpu_est_11_1__n \ +# UDS_000_INT_0_sqmuxa_1_1 N_126 UDS_000_INT_0_sqmuxa_1_2 N_124 \ +# UDS_000_INT_0_sqmuxa_1_3 N_123 UDS_000_INT_0_sqmuxa_1_0 N_125 N_96_1 N_91 \ +# state_machine_un42_clk_030_1_n N_102 state_machine_un42_clk_030_2_n N_103 \ +# state_machine_un42_clk_030_3_n N_101 state_machine_un42_clk_030_4_n RW_i \ +# state_machine_un42_clk_030_5_n AS_000_INT_i AMIGA_BUS_ENABLE_i_m_1 dsack_i_1__n \ +# VPA_SYNC_1_sqmuxa_1_0 sm_amiga_i_4__n VPA_SYNC_1_sqmuxa_2 sm_amiga_i_5__n \ +# VPA_SYNC_1_sqmuxa_3 CLK_000_D0_i VPA_SYNC_1_sqmuxa_4 sm_amiga_i_3__n \ +# VPA_SYNC_1_sqmuxa_5 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_6 cpu_est_i_3__n N_127_1 \ +# cpu_est_i_2__n N_128_1 VPA_D_i N_131_1 cpu_est_i_1__n clk_cpu_est_11_0_1_3__n \ +# DTACK_i N_105_1 VMA_INT_i DTACK_SYNC_1_sqmuxa_1_0 \ +# state_machine_un13_clk_000_d0_2_i_n DTACK_SYNC_1_sqmuxa_2 CLK_000_D1_i \ +# state_machine_un8_clk_000_d0_1_n VPA_SYNC_1_sqmuxa_i \ +# state_machine_un8_clk_000_d0_2_n AS_030_i state_machine_un8_clk_000_d0_3_n N_95_i \ +# state_machine_un8_clk_000_d0_4_n DTACK_SYNC_1_sqmuxa_i \ +# state_machine_un13_clk_000_d0_1_0_n N_96_i state_machine_un13_clk_000_d0_2_0_n \ +# a_i_18__n cpu_est_0_1__un3_n a_i_16__n cpu_est_0_1__un1_n a_i_19__n \ +# cpu_est_0_1__un0_n CLK_030_i cpu_est_0_3__un3_n state_machine_un42_clk_030_i_n \ +# cpu_est_0_3__un1_n sm_amiga_i_6__n cpu_est_0_3__un0_n sm_amiga_i_7__n \ +# ipl_030_0_0__un3_n AMIGA_BUS_ENABLE_i ipl_030_0_0__un1_n nEXP_SPACE_i \ +# ipl_030_0_0__un0_n sm_amiga_i_2__n ipl_030_0_1__un3_n sm_amiga_i_1__n \ +# ipl_030_0_1__un1_n DS_030_i ipl_030_0_1__un0_n AS_030_000_SYNC_i \ +# ipl_030_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i ipl_030_0_2__un1_n \ +# UDS_000_INT_0_sqmuxa_i ipl_030_0_2__un0_n state_machine_un13_clk_000_d0_1_i_n \ +# uds_000_int_0_un3_n clk_clk_cnt_i_n uds_000_int_0_un1_n clk_cnt_i_0__n \ +# uds_000_int_0_un0_n CLK_000_D2_i vpa_sync_0_un3_n a_i_30__n vpa_sync_0_un1_n \ +# a_i_31__n vpa_sync_0_un0_n a_i_28__n as_000_int_0_un3_n a_i_29__n \ +# as_000_int_0_un1_n a_i_26__n as_000_int_0_un0_n a_i_27__n bgack_030_int_0_un3_n \ +# a_i_24__n bgack_030_int_0_un1_n a_i_25__n bgack_030_int_0_un0_n N_132_i \ +# vma_int_0_un3_n N_133_i vma_int_0_un1_n vma_int_0_un0_n RST_i cpu_est_0_2__un3_n \ +# FPU_CS_INT_i cpu_est_0_2__un1_n BGACK_030_INT_i cpu_est_0_2__un0_n AS_030_c \ +# dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n DS_030_c \ +# bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n amiga_bus_enable_0_un3_n size_c_0__n \ +# amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n size_c_1__n \ +# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n a_c_0__n as_030_000_sync_0_un0_n \ +# fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n dtack_sync_0_un3_n \ +# dtack_sync_0_un1_n dtack_sync_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n \ +# lds_000_int_0_un0_n a_15__n a_14__n a_13__n a_12__n a_c_16__n a_11__n a_c_17__n \ +# a_10__n a_c_18__n a_9__n a_c_19__n a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n \ +# a_5__n a_c_23__n a_4__n a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n \ +# a_c_28__n a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ @@ -96,223 +96,230 @@ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF \ A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF \ A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF A_1_.BLIF \ A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF \ -DSACK_0_.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF CLK_000_c.BLIF CLK_OSZI_c.BLIF \ -inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF cpu_est_3_reg.BLIF \ -CLK_OUT_INTreg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ -IPL_030DFFSH_0_reg.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ -IPL_030DFFSH_1_reg.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF \ -IPL_030DFFSH_2_reg.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \ -ipl_c_0__n.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF ipl_c_1__n.BLIF \ -inst_CLK_OUT_PRE.BLIF SM_AMIGA_6_.BLIF ipl_c_2__n.BLIF vcc_n_n.BLIF \ -gnd_n_n.BLIF cpu_est_2_.BLIF dsack_c_1__n.BLIF CLK_REF_1_.BLIF \ -SM_AMIGA_7_.BLIF DTACK_c.BLIF inst_UDS_000_INTreg.BLIF \ -inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF clk_un4_clk_000_d1_n.BLIF \ -SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF clk_clk_cnt_n.BLIF \ -RST_c.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF RESETDFFreg.BLIF \ -state_machine_un14_as_000_int_n.BLIF SM_AMIGA_3_.BLIF RW_c.BLIF fc_c_0__n.BLIF \ -un1_as_030_4.BLIF SM_AMIGA_5_.BLIF fc_c_1__n.BLIF SM_AMIGA_2_.BLIF \ -SM_AMIGA_0_.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF \ -state_machine_lds_000_int_7_n.BLIF state_machine_uds_000_int_7_n.BLIF \ -N_101_i.BLIF N_102_i.BLIF N_103_i.BLIF N_90_0.BLIF N_91_0.BLIF N_127_i.BLIF \ -N_128_i.BLIF CLK_OUT_PRE_0.BLIF N_118_i.BLIF N_125_i.BLIF cpu_est_0_0_.BLIF \ -N_123_i.BLIF N_124_i.BLIF N_126_i.BLIF clk_cpu_est_11_0_1__n.BLIF N_131_i.BLIF \ -clk_cpu_est_11_0_3__n.BLIF N_130_i.BLIF N_129_i.BLIF N_122_i.BLIF N_121_i.BLIF \ -N_108_i.BLIF G_86.BLIF sm_amiga_ns_0_7__n.BLIF \ -state_machine_un30_clk_000_d1_n.BLIF state_machine_un8_clk_000_d0_i_n.BLIF \ -N_147.BLIF state_machine_un13_clk_000_d0_i_n.BLIF N_96.BLIF \ -state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un44_clk_000_d1_n.BLIF \ -state_machine_un23_clk_000_d0_i_n.BLIF G_90.BLIF N_100_i.BLIF N_89.BLIF \ -sm_amiga_ns_0_2__n.BLIF N_97.BLIF BG_030_c_i.BLIF N_90.BLIF \ -state_machine_un1_clk_030_0_n.BLIF N_98.BLIF clk_un4_clk_000_d1_i_n.BLIF \ -N_99.BLIF state_machine_un6_bgack_000_0_n.BLIF UDS_000_INT_0_sqmuxa.BLIF \ -state_machine_un17_clk_030_0_n.BLIF UDS_000_INT_0_sqmuxa_1.BLIF \ -un1_as_030_3_0.BLIF N_167.BLIF N_89_i.BLIF N_170.BLIF \ -AMIGA_BUS_ENABLE_i_m_i.BLIF N_105.BLIF nEXP_SPACE_m_i.BLIF N_92.BLIF \ -state_machine_amiga_bus_enable_2_iv_i_n.BLIF N_106.BLIF \ -state_machine_as_030_000_sync_3_2_n.BLIF N_107.BLIF N_94_i.BLIF N_104.BLIF \ -un1_bg_030_0.BLIF state_machine_un42_clk_030_n.BLIF N_105_i.BLIF \ -un1_bg_030.BLIF N_104_i.BLIF N_94.BLIF sm_amiga_ns_0_5__n.BLIF \ -state_machine_as_030_000_sync_3_n.BLIF N_106_i.BLIF AMIGA_BUS_ENABLE_i_m.BLIF \ -N_107_i.BLIF nEXP_SPACE_m.BLIF N_95.BLIF CLK_OUT_PRE_i.BLIF un1_as_030_3.BLIF \ -N_92_0.BLIF state_machine_un17_clk_030_n.BLIF \ -state_machine_un44_clk_000_d1_i_n.BLIF state_machine_un6_bgack_000_n.BLIF \ -a_c_i_0__n.BLIF state_machine_un1_clk_030_n.BLIF size_c_i_1__n.BLIF \ -AS_000_INT_1_sqmuxa.BLIF N_98_i.BLIF DSACK_INT_1_sqmuxa.BLIF N_99_i.BLIF \ -N_100.BLIF sm_amiga_ns_0_1__n.BLIF state_machine_un23_clk_000_d0_n.BLIF \ -N_97_i.BLIF DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF N_147_i.BLIF \ -VPA_SYNC_1_sqmuxa.BLIF state_machine_lds_000_int_7_0_n.BLIF \ -VPA_SYNC_1_sqmuxa_1.BLIF state_machine_uds_000_int_7_0_n.BLIF \ +DSACK_0_.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF \ +inst_BGACK_030_INTreg.BLIF CLK_000_c.BLIF inst_FPU_CS_INTreg.BLIF \ +cpu_est_3_reg.BLIF CLK_OSZI_c.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF CLK_OUT_INTreg.BLIF inst_AS_000_INTreg.BLIF \ +inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF \ +inst_VPA_D.BLIF inst_VPA_SYNC.BLIF IPL_030DFFSH_1_reg.BLIF \ +inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF IPL_030DFFSH_2_reg.BLIF \ +inst_CLK_000_D2.BLIF inst_CLK_OUT_PRE.BLIF ipl_c_0__n.BLIF SM_AMIGA_6_.BLIF \ +vcc_n_n.BLIF ipl_c_1__n.BLIF gnd_n_n.BLIF cpu_est_2_.BLIF ipl_c_2__n.BLIF \ +CLK_REF_0_.BLIF CLK_REF_1_.BLIF SM_AMIGA_7_.BLIF dsack_c_1__n.BLIF \ +inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DTACK_c.BLIF \ +DSACK_INT_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF \ +clk_clk_cnt_n.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \ +state_machine_un14_as_000_int_n.BLIF RST_c.BLIF SM_AMIGA_3_.BLIF \ +RESETDFFreg.BLIF SM_AMIGA_5_.BLIF RW_c.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF \ +fc_c_0__n.BLIF fc_c_1__n.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF N_101_i.BLIF \ +N_102_i.BLIF N_103_i.BLIF CLK_OUT_PRE_0.BLIF cpu_est_0_0_.BLIF N_91_0.BLIF \ +N_125_i.BLIF N_123_i.BLIF N_124_i.BLIF N_126_i.BLIF clk_cpu_est_11_0_1__n.BLIF \ +N_131_i.BLIF clk_cpu_est_11_0_3__n.BLIF N_130_i.BLIF N_129_i.BLIF N_122_i.BLIF \ +G_86.BLIF N_121_i.BLIF G_87.BLIF N_127_i.BLIF \ +state_machine_un30_clk_000_d1_n.BLIF N_128_i.BLIF N_148.BLIF N_118_i.BLIF \ +DTACK_SYNC_1_sqmuxa.BLIF state_machine_un8_clk_000_d0_i_n.BLIF N_96.BLIF \ +state_machine_un13_clk_000_d0_i_n.BLIF G_91.BLIF \ +state_machine_un15_clk_000_d0_0_n.BLIF N_89.BLIF N_100_i.BLIF N_97.BLIF \ +sm_amiga_ns_0_2__n.BLIF N_90.BLIF clk_un4_clk_000_d1_i_n.BLIF N_98.BLIF \ +state_machine_un6_bgack_000_0_n.BLIF N_99.BLIF \ +state_machine_un23_clk_000_d0_i_n.BLIF N_108.BLIF BG_030_c_i.BLIF \ +UDS_000_INT_0_sqmuxa.BLIF state_machine_un1_clk_030_0_n.BLIF \ +UDS_000_INT_0_sqmuxa_1.BLIF state_machine_un17_clk_030_0_n.BLIF \ +state_machine_un13_clk_000_d0_1_n.BLIF un1_as_030_3_0.BLIF N_168.BLIF \ +N_148_i.BLIF N_171.BLIF a_c_i_0__n.BLIF N_105.BLIF \ +state_machine_uds_000_int_7_0_n.BLIF N_92.BLIF \ +state_machine_lds_000_int_7_0_n.BLIF N_106.BLIF AMIGA_BUS_ENABLE_i_m_i.BLIF \ +N_107.BLIF nEXP_SPACE_m_i.BLIF N_104.BLIF \ +state_machine_amiga_bus_enable_2_iv_i_n.BLIF state_machine_un42_clk_030_n.BLIF \ +state_machine_as_030_000_sync_3_2_n.BLIF state_machine_un44_clk_000_d1_n.BLIF \ +N_94_i.BLIF un1_bg_030.BLIF un1_bg_030_0.BLIF N_94.BLIF size_c_i_1__n.BLIF \ +state_machine_as_030_000_sync_3_n.BLIF state_machine_un44_clk_000_d1_i_n.BLIF \ +AMIGA_BUS_ENABLE_i_m.BLIF N_105_i.BLIF nEXP_SPACE_m.BLIF N_104_i.BLIF \ +N_95.BLIF sm_amiga_ns_0_5__n.BLIF state_machine_lds_000_int_7_n.BLIF \ +N_106_i.BLIF state_machine_uds_000_int_7_n.BLIF N_107_i.BLIF \ +DTACK_SYNC_1_sqmuxa_1.BLIF un1_as_030_4.BLIF CLK_OUT_PRE_i.BLIF \ +un1_as_030_3.BLIF N_92_0.BLIF DSACK_INT_1_sqmuxa.BLIF N_90_0.BLIF \ +state_machine_un17_clk_030_n.BLIF N_89_i.BLIF state_machine_un1_clk_030_n.BLIF \ +N_108_i.BLIF state_machine_un23_clk_000_d0_n.BLIF sm_amiga_ns_0_7__n.BLIF \ +VPA_SYNC_1_sqmuxa.BLIF N_98_i.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_99_i.BLIF \ +AS_000_INT_1_sqmuxa.BLIF sm_amiga_ns_0_1__n.BLIF \ +state_machine_un6_bgack_000_n.BLIF N_97_i.BLIF clk_un4_clk_000_d1_n.BLIF \ +N_100.BLIF state_machine_un44_clk_000_d1_i_1_n.BLIF \ state_machine_un15_clk_000_d0_n.BLIF un1_bg_030_0_1.BLIF \ clk_cpu_est_11_3__n.BLIF un1_bg_030_0_2.BLIF state_machine_un2_clk_000_n.BLIF \ state_machine_as_030_000_sync_3_2_1_n.BLIF \ state_machine_un13_clk_000_d0_n.BLIF clk_cpu_est_11_0_1_1__n.BLIF \ -state_machine_un8_clk_000_d0_n.BLIF clk_cpu_est_11_0_2_1__n.BLIF N_108.BLIF \ -N_167_1.BLIF state_machine_un13_clk_000_d0_1_n.BLIF N_167_2.BLIF N_124.BLIF \ -N_167_3.BLIF N_126.BLIF N_167_4.BLIF state_machine_un13_clk_000_d0_2_n.BLIF \ -N_167_5.BLIF N_129.BLIF N_167_6.BLIF N_122.BLIF N_170_1.BLIF N_130.BLIF \ -N_170_2.BLIF N_121.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_131.BLIF \ -UDS_000_INT_0_sqmuxa_1_2.BLIF N_127.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \ -clk_cpu_est_11_1__n.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_128.BLIF \ -state_machine_un44_clk_000_d1_i_1_n.BLIF N_123.BLIF \ -state_machine_un42_clk_030_1_n.BLIF N_125.BLIF \ -state_machine_un42_clk_030_2_n.BLIF N_91.BLIF \ -state_machine_un42_clk_030_3_n.BLIF N_102.BLIF \ -state_machine_un42_clk_030_4_n.BLIF N_103.BLIF \ -state_machine_un42_clk_030_5_n.BLIF N_101.BLIF N_96_1.BLIF RW_i.BLIF \ -AMIGA_BUS_ENABLE_i_m_1.BLIF AS_000_INT_i.BLIF N_131_1.BLIF dsack_i_1__n.BLIF \ -clk_cpu_est_11_0_1_3__n.BLIF sm_amiga_i_4__n.BLIF N_105_1.BLIF \ -sm_amiga_i_5__n.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF CLK_000_D0_i.BLIF \ -VPA_SYNC_1_sqmuxa_2.BLIF sm_amiga_i_3__n.BLIF VPA_SYNC_1_sqmuxa_3.BLIF \ -cpu_est_i_0__n.BLIF VPA_SYNC_1_sqmuxa_4.BLIF cpu_est_i_2__n.BLIF \ -VPA_SYNC_1_sqmuxa_5.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF \ -VPA_SYNC_1_sqmuxa_6.BLIF cpu_est_i_3__n.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF \ -VPA_D_i.BLIF DTACK_SYNC_1_sqmuxa_2.BLIF cpu_est_i_1__n.BLIF \ -state_machine_un8_clk_000_d0_1_n.BLIF DTACK_i.BLIF \ -state_machine_un8_clk_000_d0_2_n.BLIF VMA_INT_i.BLIF \ -state_machine_un8_clk_000_d0_3_n.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF \ -state_machine_un8_clk_000_d0_4_n.BLIF AS_030_i.BLIF \ -state_machine_un13_clk_000_d0_1_0_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF \ -state_machine_un13_clk_000_d0_2_0_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF N_127_1.BLIF \ -CLK_000_D1_i.BLIF N_128_1.BLIF N_95_i.BLIF ipl_030_0_2__un3_n.BLIF N_96_i.BLIF \ -ipl_030_0_2__un1_n.BLIF a_i_18__n.BLIF ipl_030_0_2__un0_n.BLIF a_i_16__n.BLIF \ -ipl_030_0_1__un3_n.BLIF a_i_19__n.BLIF ipl_030_0_1__un1_n.BLIF CLK_030_i.BLIF \ -ipl_030_0_1__un0_n.BLIF CLK_000_D2_i.BLIF ipl_030_0_0__un3_n.BLIF \ -state_machine_un42_clk_030_i_n.BLIF ipl_030_0_0__un1_n.BLIF \ -sm_amiga_i_6__n.BLIF ipl_030_0_0__un0_n.BLIF sm_amiga_i_7__n.BLIF \ -cpu_est_0_2__un3_n.BLIF AMIGA_BUS_ENABLE_i.BLIF cpu_est_0_2__un1_n.BLIF \ -nEXP_SPACE_i.BLIF cpu_est_0_2__un0_n.BLIF sm_amiga_i_2__n.BLIF \ -cpu_est_0_1__un3_n.BLIF sm_amiga_i_1__n.BLIF cpu_est_0_1__un1_n.BLIF \ -DS_030_i.BLIF cpu_est_0_1__un0_n.BLIF AS_030_000_SYNC_i.BLIF \ -vpa_sync_0_un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF vpa_sync_0_un1_n.BLIF \ -UDS_000_INT_0_sqmuxa_i.BLIF vpa_sync_0_un0_n.BLIF clk_clk_cnt_i_n.BLIF \ -vma_int_0_un3_n.BLIF clk_cnt_i_0__n.BLIF vma_int_0_un1_n.BLIF a_i_30__n.BLIF \ -vma_int_0_un0_n.BLIF a_i_31__n.BLIF cpu_est_0_3__un3_n.BLIF a_i_28__n.BLIF \ -cpu_est_0_3__un1_n.BLIF a_i_29__n.BLIF cpu_est_0_3__un0_n.BLIF a_i_26__n.BLIF \ -bgack_030_int_0_un3_n.BLIF a_i_27__n.BLIF bgack_030_int_0_un1_n.BLIF \ -a_i_24__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_25__n.BLIF bg_000_0_un3_n.BLIF \ -N_132_i.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF RST_i.BLIF \ -amiga_bus_enable_0_un3_n.BLIF FPU_CS_INT_i.BLIF amiga_bus_enable_0_un1_n.BLIF \ -BGACK_030_INT_i.BLIF amiga_bus_enable_0_un0_n.BLIF AS_030_c.BLIF \ -as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF \ -as_030_000_sync_0_un0_n.BLIF DS_030_c.BLIF fpu_cs_int_0_un3_n.BLIF \ -fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF as_000_int_0_un3_n.BLIF \ -size_c_0__n.BLIF as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF \ -size_c_1__n.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF \ -a_c_0__n.BLIF dsack_int_0_1__un0_n.BLIF dtack_sync_0_un3_n.BLIF \ -dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF \ -lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_15__n.BLIF a_14__n.BLIF \ -a_13__n.BLIF a_12__n.BLIF a_c_16__n.BLIF a_11__n.BLIF a_c_17__n.BLIF \ -a_10__n.BLIF a_c_18__n.BLIF a_9__n.BLIF a_c_19__n.BLIF a_8__n.BLIF \ -a_c_20__n.BLIF a_7__n.BLIF a_c_21__n.BLIF a_6__n.BLIF a_c_22__n.BLIF \ -a_5__n.BLIF a_c_23__n.BLIF a_4__n.BLIF a_c_24__n.BLIF a_3__n.BLIF \ -a_c_25__n.BLIF a_2__n.BLIF a_c_26__n.BLIF a_1__n.BLIF a_c_27__n.BLIF \ -a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF nEXP_SPACE_c.BLIF \ -BG_030_c.BLIF BG_000DFFSHreg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +state_machine_un8_clk_000_d0_n.BLIF clk_cpu_est_11_0_2_1__n.BLIF N_129.BLIF \ +N_168_1.BLIF N_122.BLIF N_168_2.BLIF N_130.BLIF N_168_3.BLIF N_127.BLIF \ +N_168_4.BLIF N_128.BLIF N_168_5.BLIF N_121.BLIF N_168_6.BLIF \ +state_machine_un13_clk_000_d0_2_n.BLIF N_171_1.BLIF N_131.BLIF N_171_2.BLIF \ +clk_cpu_est_11_1__n.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_126.BLIF \ +UDS_000_INT_0_sqmuxa_1_2.BLIF N_124.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \ +N_123.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_125.BLIF N_96_1.BLIF N_91.BLIF \ +state_machine_un42_clk_030_1_n.BLIF N_102.BLIF \ +state_machine_un42_clk_030_2_n.BLIF N_103.BLIF \ +state_machine_un42_clk_030_3_n.BLIF N_101.BLIF \ +state_machine_un42_clk_030_4_n.BLIF RW_i.BLIF \ +state_machine_un42_clk_030_5_n.BLIF AS_000_INT_i.BLIF \ +AMIGA_BUS_ENABLE_i_m_1.BLIF dsack_i_1__n.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \ +sm_amiga_i_4__n.BLIF VPA_SYNC_1_sqmuxa_2.BLIF sm_amiga_i_5__n.BLIF \ +VPA_SYNC_1_sqmuxa_3.BLIF CLK_000_D0_i.BLIF VPA_SYNC_1_sqmuxa_4.BLIF \ +sm_amiga_i_3__n.BLIF VPA_SYNC_1_sqmuxa_5.BLIF cpu_est_i_0__n.BLIF \ +VPA_SYNC_1_sqmuxa_6.BLIF cpu_est_i_3__n.BLIF N_127_1.BLIF cpu_est_i_2__n.BLIF \ +N_128_1.BLIF VPA_D_i.BLIF N_131_1.BLIF cpu_est_i_1__n.BLIF \ +clk_cpu_est_11_0_1_3__n.BLIF DTACK_i.BLIF N_105_1.BLIF VMA_INT_i.BLIF \ +DTACK_SYNC_1_sqmuxa_1_0.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF \ +DTACK_SYNC_1_sqmuxa_2.BLIF CLK_000_D1_i.BLIF \ +state_machine_un8_clk_000_d0_1_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF \ +state_machine_un8_clk_000_d0_2_n.BLIF AS_030_i.BLIF \ +state_machine_un8_clk_000_d0_3_n.BLIF N_95_i.BLIF \ +state_machine_un8_clk_000_d0_4_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF \ +state_machine_un13_clk_000_d0_1_0_n.BLIF N_96_i.BLIF \ +state_machine_un13_clk_000_d0_2_0_n.BLIF a_i_18__n.BLIF \ +cpu_est_0_1__un3_n.BLIF a_i_16__n.BLIF cpu_est_0_1__un1_n.BLIF a_i_19__n.BLIF \ +cpu_est_0_1__un0_n.BLIF CLK_030_i.BLIF cpu_est_0_3__un3_n.BLIF \ +state_machine_un42_clk_030_i_n.BLIF cpu_est_0_3__un1_n.BLIF \ +sm_amiga_i_6__n.BLIF cpu_est_0_3__un0_n.BLIF sm_amiga_i_7__n.BLIF \ +ipl_030_0_0__un3_n.BLIF AMIGA_BUS_ENABLE_i.BLIF ipl_030_0_0__un1_n.BLIF \ +nEXP_SPACE_i.BLIF ipl_030_0_0__un0_n.BLIF sm_amiga_i_2__n.BLIF \ +ipl_030_0_1__un3_n.BLIF sm_amiga_i_1__n.BLIF ipl_030_0_1__un1_n.BLIF \ +DS_030_i.BLIF ipl_030_0_1__un0_n.BLIF AS_030_000_SYNC_i.BLIF \ +ipl_030_0_2__un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF ipl_030_0_2__un1_n.BLIF \ +UDS_000_INT_0_sqmuxa_i.BLIF ipl_030_0_2__un0_n.BLIF \ +state_machine_un13_clk_000_d0_1_i_n.BLIF uds_000_int_0_un3_n.BLIF \ +clk_clk_cnt_i_n.BLIF uds_000_int_0_un1_n.BLIF clk_cnt_i_0__n.BLIF \ +uds_000_int_0_un0_n.BLIF CLK_000_D2_i.BLIF vpa_sync_0_un3_n.BLIF \ +a_i_30__n.BLIF vpa_sync_0_un1_n.BLIF a_i_31__n.BLIF vpa_sync_0_un0_n.BLIF \ +a_i_28__n.BLIF as_000_int_0_un3_n.BLIF a_i_29__n.BLIF as_000_int_0_un1_n.BLIF \ +a_i_26__n.BLIF as_000_int_0_un0_n.BLIF a_i_27__n.BLIF \ +bgack_030_int_0_un3_n.BLIF a_i_24__n.BLIF bgack_030_int_0_un1_n.BLIF \ +a_i_25__n.BLIF bgack_030_int_0_un0_n.BLIF N_132_i.BLIF vma_int_0_un3_n.BLIF \ +N_133_i.BLIF vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF RST_i.BLIF \ +cpu_est_0_2__un3_n.BLIF FPU_CS_INT_i.BLIF cpu_est_0_2__un1_n.BLIF \ +BGACK_030_INT_i.BLIF cpu_est_0_2__un0_n.BLIF AS_030_c.BLIF \ +dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF \ +DS_030_c.BLIF bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF \ +amiga_bus_enable_0_un3_n.BLIF size_c_0__n.BLIF amiga_bus_enable_0_un1_n.BLIF \ +amiga_bus_enable_0_un0_n.BLIF size_c_1__n.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un1_n.BLIF a_c_0__n.BLIF as_030_000_sync_0_un0_n.BLIF \ +fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF \ +dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF \ +lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF \ +a_15__n.BLIF a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_c_16__n.BLIF \ +a_11__n.BLIF a_c_17__n.BLIF a_10__n.BLIF a_c_18__n.BLIF a_9__n.BLIF \ +a_c_19__n.BLIF a_8__n.BLIF a_c_20__n.BLIF a_7__n.BLIF a_c_21__n.BLIF \ +a_6__n.BLIF a_c_22__n.BLIF a_5__n.BLIF a_c_23__n.BLIF a_4__n.BLIF \ +a_c_24__n.BLIF a_3__n.BLIF a_c_25__n.BLIF a_2__n.BLIF a_c_26__n.BLIF \ +a_1__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF \ +a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF DSACK_1_.PIN.BLIF \ +DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_5_.D SM_AMIGA_5_.C \ -SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D \ -SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR \ -SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C \ -SM_AMIGA_0_.AR cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D \ +SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \ +SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_1_.D \ +cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D \ -SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ -inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP CLK_CNT_0_.D CLK_CNT_0_.C \ -CLK_CNT_1_.D CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ +SM_AMIGA_7_.C SM_AMIGA_7_.AP inst_VMA_INTreg.D inst_VMA_INTreg.C \ +inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ +inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C CLK_CNT_0_.D \ +CLK_CNT_0_.C CLK_CNT_1_.D CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C \ inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_FPU_CS_INTreg.D \ inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_030_000_SYNC.D \ inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_AS_000_INTreg.D \ inst_AS_000_INTreg.C inst_AS_000_INTreg.AP AMIGA_BUS_ENABLEDFFreg.D \ AMIGA_BUS_ENABLEDFFreg.C BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \ -DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_VMA_INTreg.D \ -inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_UDS_000_INTreg.D \ +DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_UDS_000_INTreg.D \ inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D \ inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D \ -inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_DTACK_DMA.D inst_DTACK_DMA.C \ -inst_DTACK_DMA.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_D2.D \ +inst_DTACK_SYNC.C inst_DTACK_SYNC.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ +inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_CLK_000_D2.D \ inst_CLK_000_D2.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D \ inst_CLK_000_D0.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_D1.D \ -inst_CLK_000_D1.C CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR DSACK_1_ DTACK \ -DSACK_0_ BGACK_000_c CLK_030_c CLK_000_c CLK_OSZI_c ipl_c_0__n ipl_c_1__n \ -ipl_c_2__n vcc_n_n gnd_n_n dsack_c_1__n DTACK_c clk_un4_clk_000_d1_n \ -clk_clk_cnt_n RST_c state_machine_un14_as_000_int_n RW_c fc_c_0__n \ -un1_as_030_4 fc_c_1__n state_machine_lds_000_int_7_n \ -state_machine_uds_000_int_7_n N_101_i N_102_i N_103_i N_90_0 N_91_0 N_127_i \ -N_128_i N_118_i N_125_i N_123_i N_124_i N_126_i clk_cpu_est_11_0_1__n N_131_i \ -clk_cpu_est_11_0_3__n N_130_i N_129_i N_122_i N_121_i N_108_i \ -sm_amiga_ns_0_7__n state_machine_un30_clk_000_d1_n \ -state_machine_un8_clk_000_d0_i_n N_147 state_machine_un13_clk_000_d0_i_n N_96 \ -state_machine_un15_clk_000_d0_0_n state_machine_un44_clk_000_d1_n \ -state_machine_un23_clk_000_d0_i_n N_100_i N_89 sm_amiga_ns_0_2__n N_97 \ -BG_030_c_i N_90 state_machine_un1_clk_030_0_n N_98 clk_un4_clk_000_d1_i_n N_99 \ -state_machine_un6_bgack_000_0_n UDS_000_INT_0_sqmuxa \ -state_machine_un17_clk_030_0_n UDS_000_INT_0_sqmuxa_1 un1_as_030_3_0 N_167 \ -N_89_i N_170 AMIGA_BUS_ENABLE_i_m_i N_105 nEXP_SPACE_m_i N_92 \ -state_machine_amiga_bus_enable_2_iv_i_n N_106 \ -state_machine_as_030_000_sync_3_2_n N_107 N_94_i N_104 un1_bg_030_0 \ -state_machine_un42_clk_030_n N_105_i un1_bg_030 N_104_i N_94 \ -sm_amiga_ns_0_5__n state_machine_as_030_000_sync_3_n N_106_i \ -AMIGA_BUS_ENABLE_i_m N_107_i nEXP_SPACE_m N_95 CLK_OUT_PRE_i un1_as_030_3 \ -N_92_0 state_machine_un17_clk_030_n state_machine_un44_clk_000_d1_i_n \ -state_machine_un6_bgack_000_n a_c_i_0__n state_machine_un1_clk_030_n \ -size_c_i_1__n AS_000_INT_1_sqmuxa N_98_i DSACK_INT_1_sqmuxa N_99_i N_100 \ -sm_amiga_ns_0_1__n state_machine_un23_clk_000_d0_n N_97_i DTACK_SYNC_1_sqmuxa \ -DTACK_SYNC_1_sqmuxa_1 N_147_i VPA_SYNC_1_sqmuxa \ -state_machine_lds_000_int_7_0_n VPA_SYNC_1_sqmuxa_1 \ -state_machine_uds_000_int_7_0_n state_machine_un15_clk_000_d0_n un1_bg_030_0_1 \ -clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n \ +inst_CLK_000_D1.C CLK_REF_0_.D CLK_REF_0_.LH CLK_REF_0_.AP CLK_REF_1_.D \ +CLK_REF_1_.LH CLK_REF_1_.AR DSACK_1_ DTACK DSACK_0_ BGACK_000_c CLK_030_c \ +CLK_000_c CLK_OSZI_c ipl_c_0__n vcc_n_n ipl_c_1__n gnd_n_n ipl_c_2__n \ +dsack_c_1__n DTACK_c clk_clk_cnt_n state_machine_un14_as_000_int_n RST_c RW_c \ +fc_c_0__n fc_c_1__n N_101_i N_102_i N_103_i N_91_0 N_125_i N_123_i N_124_i \ +N_126_i clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i N_129_i \ +N_122_i N_121_i N_127_i state_machine_un30_clk_000_d1_n N_128_i N_148 N_118_i \ +DTACK_SYNC_1_sqmuxa state_machine_un8_clk_000_d0_i_n N_96 \ +state_machine_un13_clk_000_d0_i_n state_machine_un15_clk_000_d0_0_n N_89 \ +N_100_i N_97 sm_amiga_ns_0_2__n N_90 clk_un4_clk_000_d1_i_n N_98 \ +state_machine_un6_bgack_000_0_n N_99 state_machine_un23_clk_000_d0_i_n N_108 \ +BG_030_c_i UDS_000_INT_0_sqmuxa state_machine_un1_clk_030_0_n \ +UDS_000_INT_0_sqmuxa_1 state_machine_un17_clk_030_0_n \ +state_machine_un13_clk_000_d0_1_n un1_as_030_3_0 N_168 N_148_i N_171 \ +a_c_i_0__n N_105 state_machine_uds_000_int_7_0_n N_92 \ +state_machine_lds_000_int_7_0_n N_106 AMIGA_BUS_ENABLE_i_m_i N_107 \ +nEXP_SPACE_m_i N_104 state_machine_amiga_bus_enable_2_iv_i_n \ +state_machine_un42_clk_030_n state_machine_as_030_000_sync_3_2_n \ +state_machine_un44_clk_000_d1_n N_94_i un1_bg_030 un1_bg_030_0 N_94 \ +size_c_i_1__n state_machine_as_030_000_sync_3_n \ +state_machine_un44_clk_000_d1_i_n AMIGA_BUS_ENABLE_i_m N_105_i nEXP_SPACE_m \ +N_104_i N_95 sm_amiga_ns_0_5__n state_machine_lds_000_int_7_n N_106_i \ +state_machine_uds_000_int_7_n N_107_i DTACK_SYNC_1_sqmuxa_1 un1_as_030_4 \ +CLK_OUT_PRE_i un1_as_030_3 N_92_0 DSACK_INT_1_sqmuxa N_90_0 \ +state_machine_un17_clk_030_n N_89_i state_machine_un1_clk_030_n N_108_i \ +state_machine_un23_clk_000_d0_n sm_amiga_ns_0_7__n VPA_SYNC_1_sqmuxa N_98_i \ +VPA_SYNC_1_sqmuxa_1 N_99_i AS_000_INT_1_sqmuxa sm_amiga_ns_0_1__n \ +state_machine_un6_bgack_000_n N_97_i clk_un4_clk_000_d1_n N_100 \ +state_machine_un44_clk_000_d1_i_1_n state_machine_un15_clk_000_d0_n \ +un1_bg_030_0_1 clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n \ state_machine_as_030_000_sync_3_2_1_n state_machine_un13_clk_000_d0_n \ clk_cpu_est_11_0_1_1__n state_machine_un8_clk_000_d0_n clk_cpu_est_11_0_2_1__n \ -N_108 N_167_1 state_machine_un13_clk_000_d0_1_n N_167_2 N_124 N_167_3 N_126 \ -N_167_4 state_machine_un13_clk_000_d0_2_n N_167_5 N_129 N_167_6 N_122 N_170_1 \ -N_130 N_170_2 N_121 UDS_000_INT_0_sqmuxa_1_1 N_131 UDS_000_INT_0_sqmuxa_1_2 \ -N_127 UDS_000_INT_0_sqmuxa_1_3 clk_cpu_est_11_1__n UDS_000_INT_0_sqmuxa_1_0 \ -N_128 state_machine_un44_clk_000_d1_i_1_n N_123 state_machine_un42_clk_030_1_n \ -N_125 state_machine_un42_clk_030_2_n N_91 state_machine_un42_clk_030_3_n N_102 \ -state_machine_un42_clk_030_4_n N_103 state_machine_un42_clk_030_5_n N_101 \ -N_96_1 RW_i AMIGA_BUS_ENABLE_i_m_1 AS_000_INT_i N_131_1 dsack_i_1__n \ -clk_cpu_est_11_0_1_3__n sm_amiga_i_4__n N_105_1 sm_amiga_i_5__n \ -VPA_SYNC_1_sqmuxa_1_0 CLK_000_D0_i VPA_SYNC_1_sqmuxa_2 sm_amiga_i_3__n \ -VPA_SYNC_1_sqmuxa_3 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_4 cpu_est_i_2__n \ -VPA_SYNC_1_sqmuxa_5 state_machine_un13_clk_000_d0_2_i_n VPA_SYNC_1_sqmuxa_6 \ -cpu_est_i_3__n DTACK_SYNC_1_sqmuxa_1_0 VPA_D_i DTACK_SYNC_1_sqmuxa_2 \ -cpu_est_i_1__n state_machine_un8_clk_000_d0_1_n DTACK_i \ -state_machine_un8_clk_000_d0_2_n VMA_INT_i state_machine_un8_clk_000_d0_3_n \ -state_machine_un13_clk_000_d0_1_i_n state_machine_un8_clk_000_d0_4_n AS_030_i \ -state_machine_un13_clk_000_d0_1_0_n DTACK_SYNC_1_sqmuxa_i \ -state_machine_un13_clk_000_d0_2_0_n VPA_SYNC_1_sqmuxa_i N_127_1 CLK_000_D1_i \ -N_128_1 N_95_i ipl_030_0_2__un3_n N_96_i ipl_030_0_2__un1_n a_i_18__n \ -ipl_030_0_2__un0_n a_i_16__n ipl_030_0_1__un3_n a_i_19__n ipl_030_0_1__un1_n \ -CLK_030_i ipl_030_0_1__un0_n CLK_000_D2_i ipl_030_0_0__un3_n \ -state_machine_un42_clk_030_i_n ipl_030_0_0__un1_n sm_amiga_i_6__n \ -ipl_030_0_0__un0_n sm_amiga_i_7__n cpu_est_0_2__un3_n AMIGA_BUS_ENABLE_i \ -cpu_est_0_2__un1_n nEXP_SPACE_i cpu_est_0_2__un0_n sm_amiga_i_2__n \ -cpu_est_0_1__un3_n sm_amiga_i_1__n cpu_est_0_1__un1_n DS_030_i \ -cpu_est_0_1__un0_n AS_030_000_SYNC_i vpa_sync_0_un3_n UDS_000_INT_0_sqmuxa_1_i \ -vpa_sync_0_un1_n UDS_000_INT_0_sqmuxa_i vpa_sync_0_un0_n clk_clk_cnt_i_n \ -vma_int_0_un3_n clk_cnt_i_0__n vma_int_0_un1_n a_i_30__n vma_int_0_un0_n \ -a_i_31__n cpu_est_0_3__un3_n a_i_28__n cpu_est_0_3__un1_n a_i_29__n \ -cpu_est_0_3__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n \ -bgack_030_int_0_un1_n a_i_24__n bgack_030_int_0_un0_n a_i_25__n bg_000_0_un3_n \ -N_132_i bg_000_0_un1_n bg_000_0_un0_n RST_i amiga_bus_enable_0_un3_n \ -FPU_CS_INT_i amiga_bus_enable_0_un1_n BGACK_030_INT_i amiga_bus_enable_0_un0_n \ -AS_030_c as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n \ -as_030_000_sync_0_un0_n DS_030_c fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n \ -fpu_cs_int_0_un0_n as_000_int_0_un3_n size_c_0__n as_000_int_0_un1_n \ -as_000_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n \ -a_c_0__n dsack_int_0_1__un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n \ -dtack_sync_0_un0_n uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n \ +N_129 N_168_1 N_122 N_168_2 N_130 N_168_3 N_127 N_168_4 N_128 N_168_5 N_121 \ +N_168_6 state_machine_un13_clk_000_d0_2_n N_171_1 N_131 N_171_2 \ +clk_cpu_est_11_1__n UDS_000_INT_0_sqmuxa_1_1 N_126 UDS_000_INT_0_sqmuxa_1_2 \ +N_124 UDS_000_INT_0_sqmuxa_1_3 N_123 UDS_000_INT_0_sqmuxa_1_0 N_125 N_96_1 \ +N_91 state_machine_un42_clk_030_1_n N_102 state_machine_un42_clk_030_2_n N_103 \ +state_machine_un42_clk_030_3_n N_101 state_machine_un42_clk_030_4_n RW_i \ +state_machine_un42_clk_030_5_n AS_000_INT_i AMIGA_BUS_ENABLE_i_m_1 \ +dsack_i_1__n VPA_SYNC_1_sqmuxa_1_0 sm_amiga_i_4__n VPA_SYNC_1_sqmuxa_2 \ +sm_amiga_i_5__n VPA_SYNC_1_sqmuxa_3 CLK_000_D0_i VPA_SYNC_1_sqmuxa_4 \ +sm_amiga_i_3__n VPA_SYNC_1_sqmuxa_5 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_6 \ +cpu_est_i_3__n N_127_1 cpu_est_i_2__n N_128_1 VPA_D_i N_131_1 cpu_est_i_1__n \ +clk_cpu_est_11_0_1_3__n DTACK_i N_105_1 VMA_INT_i DTACK_SYNC_1_sqmuxa_1_0 \ +state_machine_un13_clk_000_d0_2_i_n DTACK_SYNC_1_sqmuxa_2 CLK_000_D1_i \ +state_machine_un8_clk_000_d0_1_n VPA_SYNC_1_sqmuxa_i \ +state_machine_un8_clk_000_d0_2_n AS_030_i state_machine_un8_clk_000_d0_3_n \ +N_95_i state_machine_un8_clk_000_d0_4_n DTACK_SYNC_1_sqmuxa_i \ +state_machine_un13_clk_000_d0_1_0_n N_96_i state_machine_un13_clk_000_d0_2_0_n \ +a_i_18__n cpu_est_0_1__un3_n a_i_16__n cpu_est_0_1__un1_n a_i_19__n \ +cpu_est_0_1__un0_n CLK_030_i cpu_est_0_3__un3_n state_machine_un42_clk_030_i_n \ +cpu_est_0_3__un1_n sm_amiga_i_6__n cpu_est_0_3__un0_n sm_amiga_i_7__n \ +ipl_030_0_0__un3_n AMIGA_BUS_ENABLE_i ipl_030_0_0__un1_n nEXP_SPACE_i \ +ipl_030_0_0__un0_n sm_amiga_i_2__n ipl_030_0_1__un3_n sm_amiga_i_1__n \ +ipl_030_0_1__un1_n DS_030_i ipl_030_0_1__un0_n AS_030_000_SYNC_i \ +ipl_030_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i ipl_030_0_2__un1_n \ +UDS_000_INT_0_sqmuxa_i ipl_030_0_2__un0_n state_machine_un13_clk_000_d0_1_i_n \ +uds_000_int_0_un3_n clk_clk_cnt_i_n uds_000_int_0_un1_n clk_cnt_i_0__n \ +uds_000_int_0_un0_n CLK_000_D2_i vpa_sync_0_un3_n a_i_30__n vpa_sync_0_un1_n \ +a_i_31__n vpa_sync_0_un0_n a_i_28__n as_000_int_0_un3_n a_i_29__n \ +as_000_int_0_un1_n a_i_26__n as_000_int_0_un0_n a_i_27__n \ +bgack_030_int_0_un3_n a_i_24__n bgack_030_int_0_un1_n a_i_25__n \ +bgack_030_int_0_un0_n N_132_i vma_int_0_un3_n N_133_i vma_int_0_un1_n \ +vma_int_0_un0_n RST_i cpu_est_0_2__un3_n FPU_CS_INT_i cpu_est_0_2__un1_n \ +BGACK_030_INT_i cpu_est_0_2__un0_n AS_030_c dsack_int_0_1__un3_n \ +dsack_int_0_1__un1_n dsack_int_0_1__un0_n DS_030_c bg_000_0_un3_n \ +bg_000_0_un1_n bg_000_0_un0_n amiga_bus_enable_0_un3_n size_c_0__n \ +amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n size_c_1__n \ +as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n a_c_0__n \ +as_030_000_sync_0_un0_n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n \ +fpu_cs_int_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n \ lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n a_15__n a_14__n \ a_13__n a_12__n a_c_16__n a_11__n a_c_17__n a_10__n a_c_18__n a_9__n a_c_19__n \ a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n a_5__n a_c_23__n a_4__n \ a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n a_c_28__n \ a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c DSACK_1_.OE DTACK.OE \ AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE \ -CLK_OUT_PRE_0 cpu_est_0_0_ G_86 G_90 +CLK_OUT_PRE_0 cpu_est_0_0_ G_86 G_87 G_91 +.names sm_amiga_ns_0_1__n.BLIF SM_AMIGA_6_.D +0 1 .names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D 0 1 .names CLK_000_D0_i.BLIF N_101_i.BLIF SM_AMIGA_4_.D @@ -325,6 +332,9 @@ CLK_OUT_PRE_0 cpu_est_0_0_ G_86 G_90 11 1 .names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D 0 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 .names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D 1- 1 -1 1 @@ -342,19 +352,17 @@ CLK_OUT_PRE_0 cpu_est_0_0_ G_86 G_90 -1 1 .names inst_CLK_000_D0.BLIF N_97_i.BLIF SM_AMIGA_7_.D 11 1 -.names sm_amiga_ns_0_1__n.BLIF SM_AMIGA_6_.D -0 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +1- 1 +-1 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ inst_BGACK_030_INTreg.D 1- 1 -1 1 .names clk_cnt_i_0__n.BLIF clk_clk_cnt_i_n.BLIF CLK_CNT_0_.D 11 1 -.names clk_clk_cnt_i_n.BLIF G_90.BLIF CLK_CNT_1_.D +.names clk_clk_cnt_i_n.BLIF G_91.BLIF CLK_CNT_1_.D 11 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 .names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D 1- 1 -1 1 @@ -378,9 +386,6 @@ AMIGA_BUS_ENABLEDFFreg.D .names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D 1- 1 -1 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D -1- 1 --1 1 .names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D 1- 1 -1 1 @@ -395,34 +400,18 @@ AMIGA_BUS_ENABLEDFFreg.D .names vcc_n_n 1 .names gnd_n_n -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF clk_un4_clk_000_d1_n -11 1 -.names clk_cnt_i_0__n.BLIF N_132_i.BLIF clk_clk_cnt_n +.names N_132_i.BLIF N_133_i.BLIF clk_clk_cnt_n 11 1 .names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un14_as_000_int_n 11 1 -.names AS_030_i.BLIF N_147.BLIF un1_as_030_4 -11 1 -.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n -0 1 -.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n -0 1 .names N_101.BLIF N_101_i 0 1 .names N_102.BLIF N_102_i 0 1 .names N_103.BLIF N_103_i 0 1 -.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_90_0 -11 1 .names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_91_0 11 1 -.names N_127.BLIF N_127_i -0 1 -.names N_128.BLIF N_128_i -0 1 -.names N_127_i.BLIF N_128_i.BLIF N_118_i -11 1 .names N_125.BLIF N_125_i 0 1 .names N_123.BLIF N_123_i @@ -446,166 +435,189 @@ clk_cpu_est_11_0_1__n 11 1 .names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_121_i 11 1 -.names N_108.BLIF N_108_i +.names N_127.BLIF N_127_i 0 1 -.names N_96_i.BLIF N_108_i.BLIF sm_amiga_ns_0_7__n -11 1 .names inst_CLK_000_D1.BLIF CLK_000_D2_i.BLIF state_machine_un30_clk_000_d1_n 11 1 +.names N_128.BLIF N_128_i +0 1 +.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_148 +11 1 +.names N_127_i.BLIF N_128_i.BLIF N_118_i +11 1 +.names DTACK_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa_2.BLIF \ +DTACK_SYNC_1_sqmuxa +11 1 .names state_machine_un8_clk_000_d0_n.BLIF state_machine_un8_clk_000_d0_i_n 0 1 -.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_147 +.names N_96_1.BLIF SM_AMIGA_1_.BLIF N_96 11 1 .names state_machine_un13_clk_000_d0_n.BLIF state_machine_un13_clk_000_d0_i_n 0 1 -.names N_96_1.BLIF SM_AMIGA_1_.BLIF N_96 -11 1 .names state_machine_un8_clk_000_d0_i_n.BLIF \ state_machine_un13_clk_000_d0_i_n.BLIF state_machine_un15_clk_000_d0_0_n 11 1 -.names state_machine_un44_clk_000_d1_i_n.BLIF state_machine_un44_clk_000_d1_n -0 1 -.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ -state_machine_un23_clk_000_d0_i_n -11 1 -.names N_100.BLIF N_100_i -0 1 .names N_89_i.BLIF N_89 0 1 -.names N_95_i.BLIF N_100_i.BLIF sm_amiga_ns_0_2__n -11 1 +.names N_100.BLIF N_100_i +0 1 .names N_90.BLIF sm_amiga_i_7__n.BLIF N_97 11 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 +.names N_95_i.BLIF N_100_i.BLIF sm_amiga_ns_0_2__n +11 1 .names N_90_0.BLIF N_90 0 1 -.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n -11 1 -.names N_89.BLIF SM_AMIGA_6_.BLIF N_98 -11 1 .names clk_un4_clk_000_d1_n.BLIF clk_un4_clk_000_d1_i_n 0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_7_.BLIF N_99 +.names N_89.BLIF SM_AMIGA_6_.BLIF N_98 11 1 .names BGACK_000_c.BLIF clk_un4_clk_000_d1_i_n.BLIF \ state_machine_un6_bgack_000_0_n 11 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_7_.BLIF N_99 +11 1 +.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ +state_machine_un23_clk_000_d0_i_n +11 1 +.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF N_108 +11 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 .names UDS_000_INT_0_sqmuxa_1_0.BLIF RW_i.BLIF UDS_000_INT_0_sqmuxa 11 1 -.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n +.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n 11 1 .names UDS_000_INT_0_sqmuxa_1_3.BLIF state_machine_un30_clk_000_d1_n.BLIF \ UDS_000_INT_0_sqmuxa_1 11 1 +.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n +11 1 +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF \ +state_machine_un13_clk_000_d0_1_n +11 1 .names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_3_0 11 1 -.names N_167_5.BLIF N_167_6.BLIF N_167 +.names N_168_5.BLIF N_168_6.BLIF N_168 11 1 -.names AS_030_000_SYNC_i.BLIF state_machine_un30_clk_000_d1_n.BLIF N_89_i +.names N_148.BLIF N_148_i +0 1 +.names N_171_1.BLIF N_171_2.BLIF N_171 11 1 -.names N_170_1.BLIF N_170_2.BLIF N_170 -11 1 -.names AMIGA_BUS_ENABLE_i_m.BLIF AMIGA_BUS_ENABLE_i_m_i +.names a_c_0__n.BLIF a_c_i_0__n 0 1 .names N_105_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_105 11 1 -.names nEXP_SPACE_m.BLIF nEXP_SPACE_m_i -0 1 +.names a_c_i_0__n.BLIF N_148_i.BLIF state_machine_uds_000_int_7_0_n +11 1 .names N_92_0.BLIF N_92 0 1 -.names AMIGA_BUS_ENABLE_i_m_i.BLIF nEXP_SPACE_m_i.BLIF \ -state_machine_amiga_bus_enable_2_iv_i_n +.names N_148_i.BLIF state_machine_un44_clk_000_d1_n.BLIF \ +state_machine_lds_000_int_7_0_n 11 1 .names CLK_000_D0_i.BLIF N_92.BLIF N_106 11 1 -.names state_machine_as_030_000_sync_3_2_1_n.BLIF \ -state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n -11 1 +.names AMIGA_BUS_ENABLE_i_m.BLIF AMIGA_BUS_ENABLE_i_m_i +0 1 .names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_107 11 1 -.names N_94.BLIF N_94_i +.names nEXP_SPACE_m.BLIF nEXP_SPACE_m_i 0 1 .names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_104 11 1 -.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 +.names AMIGA_BUS_ENABLE_i_m_i.BLIF nEXP_SPACE_m_i.BLIF \ +state_machine_amiga_bus_enable_2_iv_i_n 11 1 .names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF \ state_machine_un42_clk_030_n 11 1 -.names N_105.BLIF N_105_i +.names state_machine_as_030_000_sync_3_2_1_n.BLIF \ +state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n +11 1 +.names state_machine_un44_clk_000_d1_i_n.BLIF state_machine_un44_clk_000_d1_n +0 1 +.names N_94.BLIF N_94_i 0 1 .names un1_bg_030_0.BLIF un1_bg_030 0 1 -.names N_104.BLIF N_104_i -0 1 +.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 +11 1 .names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_94 11 1 -.names N_104_i.BLIF N_105_i.BLIF sm_amiga_ns_0_5__n -11 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 .names state_machine_as_030_000_sync_3_2_n.BLIF \ state_machine_as_030_000_sync_3_n 0 1 -.names N_106.BLIF N_106_i -0 1 +.names state_machine_un44_clk_000_d1_i_1_n.BLIF size_c_i_1__n.BLIF \ +state_machine_un44_clk_000_d1_i_n +11 1 .names AMIGA_BUS_ENABLE_i_m_1.BLIF sm_amiga_i_6__n.BLIF AMIGA_BUS_ENABLE_i_m 11 1 -.names N_107.BLIF N_107_i +.names N_105.BLIF N_105_i 0 1 .names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF nEXP_SPACE_m 11 1 +.names N_104.BLIF N_104_i +0 1 .names N_89_i.BLIF SM_AMIGA_6_.BLIF N_95 11 1 +.names N_104_i.BLIF N_105_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n +0 1 +.names N_106.BLIF N_106_i +0 1 +.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n +0 1 +.names N_107.BLIF N_107_i +0 1 +.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 +11 1 +.names AS_030_i.BLIF N_148.BLIF un1_as_030_4 +11 1 .names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i 0 1 .names un1_as_030_3_0.BLIF un1_as_030_3 0 1 .names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_92_0 11 1 +.names AS_030_i.BLIF N_96_i.BLIF DSACK_INT_1_sqmuxa +11 1 +.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_90_0 +11 1 .names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n 0 1 -.names state_machine_un44_clk_000_d1_i_1_n.BLIF size_c_0__n.BLIF \ -state_machine_un44_clk_000_d1_i_n +.names AS_030_000_SYNC_i.BLIF state_machine_un30_clk_000_d1_n.BLIF N_89_i 11 1 -.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n -0 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 .names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n 0 1 -.names size_c_1__n.BLIF size_c_i_1__n +.names N_108.BLIF N_108_i 0 1 -.names AS_030_i.BLIF N_95_i.BLIF AS_000_INT_1_sqmuxa +.names state_machine_un23_clk_000_d0_i_n.BLIF state_machine_un23_clk_000_d0_n +0 1 +.names N_96_i.BLIF N_108_i.BLIF sm_amiga_ns_0_7__n +11 1 +.names VPA_SYNC_1_sqmuxa_5.BLIF VPA_SYNC_1_sqmuxa_6.BLIF VPA_SYNC_1_sqmuxa 11 1 .names N_98.BLIF N_98_i 0 1 -.names AS_030_i.BLIF N_96_i.BLIF DSACK_INT_1_sqmuxa +.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 11 1 .names N_99.BLIF N_99_i 0 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF N_100 +.names AS_030_i.BLIF N_95_i.BLIF AS_000_INT_1_sqmuxa 11 1 .names N_98_i.BLIF N_99_i.BLIF sm_amiga_ns_0_1__n 11 1 -.names state_machine_un23_clk_000_d0_i_n.BLIF state_machine_un23_clk_000_d0_n +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n 0 1 .names N_97.BLIF N_97_i 0 1 -.names DTACK_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa_2.BLIF \ -DTACK_SYNC_1_sqmuxa +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF clk_un4_clk_000_d1_n 11 1 -.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF N_100 11 1 -.names N_147.BLIF N_147_i -0 1 -.names VPA_SYNC_1_sqmuxa_5.BLIF VPA_SYNC_1_sqmuxa_6.BLIF VPA_SYNC_1_sqmuxa -11 1 -.names N_147_i.BLIF state_machine_un44_clk_000_d1_n.BLIF \ -state_machine_lds_000_int_7_0_n -11 1 -.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 -11 1 -.names a_c_i_0__n.BLIF N_147_i.BLIF state_machine_uds_000_int_7_0_n +.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un44_clk_000_d1_i_1_n 11 1 .names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n 0 1 @@ -629,304 +641,318 @@ state_machine_un8_clk_000_d0_3_n.BLIF state_machine_un8_clk_000_d0_n 11 1 .names N_123_i.BLIF N_125_i.BLIF clk_cpu_est_11_0_2_1__n 11 1 -.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF N_108 -11 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_167_1 -11 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF \ -state_machine_un13_clk_000_d0_1_n -11 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_167_2 -11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_124 -11 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_167_3 -11 1 -.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d0_2_n.BLIF N_126 -11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_167_4 -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d0_2_n -11 1 -.names N_167_1.BLIF N_167_2.BLIF N_167_5 -11 1 .names N_122.BLIF cpu_est_3_reg.BLIF N_129 11 1 -.names N_167_3.BLIF N_167_4.BLIF N_167_6 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_168_1 11 1 .names N_122_i.BLIF N_122 0 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_170_1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_168_2 11 1 .names N_122_i.BLIF cpu_est_i_2__n.BLIF N_130 11 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_170_2 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_168_3 +11 1 +.names N_127_1.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF N_127 +11 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_168_4 +11 1 +.names N_128_1.BLIF cpu_est_i_2__n.BLIF N_128 +11 1 +.names N_168_1.BLIF N_168_2.BLIF N_168_5 11 1 .names N_121_i.BLIF N_121 0 1 -.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 +.names N_168_3.BLIF N_168_4.BLIF N_168_6 +11 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d0_2_n +11 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_171_1 11 1 .names N_131_1.BLIF cpu_est_i_2__n.BLIF N_131 11 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_171_2 +11 1 +.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n +0 1 +.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 +11 1 +.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d0_2_n.BLIF N_126 +11 1 .names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2 11 1 -.names N_127_1.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF N_127 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_124 11 1 .names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ UDS_000_INT_0_sqmuxa_1_3 11 1 -.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n -0 1 -.names SM_AMIGA_4_.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 -11 1 -.names N_128_1.BLIF cpu_est_i_2__n.BLIF N_128 -11 1 -.names size_c_i_1__n.BLIF a_c_i_0__n.BLIF state_machine_un44_clk_000_d1_i_1_n -11 1 .names N_121.BLIF cpu_est_i_0__n.BLIF N_123 11 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n +.names SM_AMIGA_4_.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 11 1 .names N_121_i.BLIF cpu_est_0_.BLIF N_125 11 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n +.names CLK_000_D0_i.BLIF inst_CLK_OUT_PRE.BLIF N_96_1 11 1 .names N_91_0.BLIF N_91 0 1 -.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n +.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n 11 1 .names CLK_000_D0_i.BLIF N_91.BLIF N_102 11 1 +.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n +11 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_103 +11 1 +.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_101 +11 1 .names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF \ state_machine_un42_clk_030_4_n 11 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_103 -11 1 +.names RW_c.BLIF RW_i +0 1 .names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF \ state_machine_un42_clk_030_5_n 11 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_101 -11 1 -.names CLK_000_D0_i.BLIF inst_CLK_OUT_PRE.BLIF N_96_1 -11 1 -.names RW_c.BLIF RW_i +.names inst_AS_000_INTreg.BLIF AS_000_INT_i 0 1 .names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF AMIGA_BUS_ENABLE_i_m_1 11 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_131_1 -11 1 .names dsack_c_1__n.BLIF dsack_i_1__n 0 1 -.names N_131_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_1_3__n -11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_105_1 -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 .names SM_AMIGA_3_.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_1_0 11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n 0 1 .names VPA_D_i.BLIF cpu_est_2_.BLIF VPA_SYNC_1_sqmuxa_2 11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n 0 1 .names cpu_est_3_reg.BLIF cpu_est_i_0__n.BLIF VPA_SYNC_1_sqmuxa_3 11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n +.names inst_CLK_000_D0.BLIF CLK_000_D0_i 0 1 .names cpu_est_i_1__n.BLIF state_machine_un2_clk_000_n.BLIF \ VPA_SYNC_1_sqmuxa_4 11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 .names VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_5 11 1 -.names state_machine_un13_clk_000_d0_2_n.BLIF \ -state_machine_un13_clk_000_d0_2_i_n +.names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 .names VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_6 11 1 .names cpu_est_3_reg.BLIF cpu_est_i_3__n 0 1 -.names DTACK_i.BLIF SM_AMIGA_3_.BLIF DTACK_SYNC_1_sqmuxa_1_0 +.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_127_1 +11 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_128_1 11 1 .names inst_VPA_D.BLIF VPA_D_i 0 1 -.names inst_VPA_D.BLIF state_machine_un2_clk_000_n.BLIF DTACK_SYNC_1_sqmuxa_2 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_131_1 11 1 .names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 +.names N_131_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_1_3__n +11 1 +.names DTACK_c.BLIF DTACK_i +0 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_105_1 +11 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names DTACK_i.BLIF SM_AMIGA_3_.BLIF DTACK_SYNC_1_sqmuxa_1_0 +11 1 +.names state_machine_un13_clk_000_d0_2_n.BLIF \ +state_machine_un13_clk_000_d0_2_i_n +0 1 +.names inst_VPA_D.BLIF state_machine_un2_clk_000_n.BLIF DTACK_SYNC_1_sqmuxa_2 +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 .names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF \ state_machine_un8_clk_000_d0_1_n 11 1 -.names DTACK_c.BLIF DTACK_i +.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i 0 1 .names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d0_2_n 11 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i +.names AS_030_c.BLIF AS_030_i 0 1 .names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d0_3_n 11 1 -.names state_machine_un13_clk_000_d0_1_n.BLIF \ -state_machine_un13_clk_000_d0_1_i_n +.names N_95.BLIF N_95_i 0 1 .names state_machine_un8_clk_000_d0_1_n.BLIF \ state_machine_un8_clk_000_d0_2_n.BLIF state_machine_un8_clk_000_d0_4_n 11 1 -.names AS_030_c.BLIF AS_030_i +.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i 0 1 .names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF \ state_machine_un13_clk_000_d0_1_0_n 11 1 -.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i +.names N_96.BLIF N_96_i 0 1 .names state_machine_un13_clk_000_d0_1_n.BLIF \ state_machine_un13_clk_000_d0_2_n.BLIF state_machine_un13_clk_000_d0_2_0_n 11 1 -.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i -0 1 -.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_127_1 -11 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i -0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_128_1 -11 1 -.names N_95.BLIF N_95_i -0 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un3_n -0 1 -.names N_96.BLIF N_96_i -0 1 -.names ipl_c_2__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un1_n -11 1 .names a_c_18__n.BLIF a_i_18__n 0 1 -.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un3_n -0 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names ipl_c_1__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un1_n -11 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names inst_CLK_000_D2.BLIF CLK_000_D2_i -0 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un3_n -0 1 -.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n -0 1 -.names ipl_c_0__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un1_n -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un3_n -0 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i -0 1 -.names N_118_i.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un1_n -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 .names clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un3_n 0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +.names a_c_16__n.BLIF a_i_16__n 0 1 .names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un1_n 11 1 -.names DS_030_c.BLIF DS_030_i +.names a_c_19__n.BLIF a_i_19__n 0 1 .names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n -0 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i -0 1 -.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n -11 1 -.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i -0 1 -.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n -11 1 -.names clk_clk_cnt_n.BLIF clk_clk_cnt_i_n -0 1 -.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n -0 1 -.names CLK_CNT_0_.BLIF clk_cnt_i_0__n -0 1 -.names N_121.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n -11 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names a_c_31__n.BLIF a_i_31__n +.names CLK_030_c.BLIF CLK_030_i 0 1 .names clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un3_n 0 1 -.names a_c_28__n.BLIF a_i_28__n +.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n 0 1 .names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un1_n 11 1 -.names a_c_29__n.BLIF a_i_29__n +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n 0 1 .names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un3_n +0 1 +.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i +0 1 +.names ipl_c_0__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un1_n +11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un3_n +0 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names ipl_c_1__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un1_n +11 1 +.names DS_030_c.BLIF DS_030_i +0 1 +.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un3_n +0 1 +.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i +0 1 +.names ipl_c_2__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un1_n +11 1 +.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i +0 1 +.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names state_machine_un13_clk_000_d0_1_n.BLIF \ +state_machine_un13_clk_000_d0_1_i_n +0 1 +.names un1_as_030_4.BLIF uds_000_int_0_un3_n +0 1 +.names clk_clk_cnt_n.BLIF clk_clk_cnt_i_n +0 1 +.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n +11 1 +.names CLK_CNT_0_.BLIF clk_cnt_i_0__n +0 1 +.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF \ +uds_000_int_0_un0_n +11 1 +.names inst_CLK_000_D2.BLIF CLK_000_D2_i +0 1 +.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n +0 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n +11 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n +11 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +0 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +11 1 .names a_c_26__n.BLIF a_i_26__n 0 1 +.names N_95_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 .names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names a_c_27__n.BLIF a_i_27__n +.names a_c_24__n.BLIF a_i_24__n 0 1 .names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ bgack_030_int_0_un1_n 11 1 -.names a_c_24__n.BLIF a_i_24__n +.names a_c_25__n.BLIF a_i_25__n 0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n -0 1 .names G_86.BLIF N_132_i 0 1 +.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n +0 1 +.names G_87.BLIF N_133_i +0 1 +.names N_121.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +11 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names RST_c.BLIF RST_i +0 1 +.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un3_n +0 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +0 1 +.names N_118_i.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n +0 1 +.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n +11 1 +.names N_96_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n +11 1 +.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n +0 1 .names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n 11 1 .names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names RST_c.BLIF RST_i -0 1 .names RST_c.BLIF amiga_bus_enable_0_un3_n 0 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i -0 1 .names state_machine_amiga_bus_enable_2_iv_i_n.BLIF RST_c.BLIF \ amiga_bus_enable_0_un1_n 11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 .names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF \ amiga_bus_enable_0_un0_n 11 1 @@ -944,31 +970,12 @@ as_030_000_sync_0_un0_n 11 1 .names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n 11 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n -0 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n -11 1 -.names N_95_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 -.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n -0 1 -.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n -11 1 -.names N_96_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n -11 1 .names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n 0 1 .names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n 11 1 .names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n 11 1 -.names un1_as_030_4.BLIF uds_000_int_0_un3_n -0 1 -.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n -11 1 -.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un0_n -11 1 .names un1_as_030_4.BLIF lds_000_int_0_un3_n 0 1 .names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n @@ -986,12 +993,17 @@ lds_000_int_0_un0_n 10 1 11 0 00 0 -.names CLK_REF_1_.BLIF CLK_CNT_1_.BLIF G_86 +.names CLK_REF_0_.BLIF CLK_CNT_0_.BLIF G_86 01 1 10 1 11 0 00 0 -.names CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF G_90 +.names CLK_REF_1_.BLIF CLK_CNT_1_.BLIF G_87 +01 1 +10 1 +11 0 +00 0 +.names CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF G_91 01 1 10 1 11 0 @@ -1050,7 +1062,7 @@ lds_000_int_0_un0_n .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_170.BLIF CIIN +.names N_171.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -1059,6 +1071,12 @@ lds_000_int_0_un0_n .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_6_.AR +1 1 +0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 0 0 @@ -1095,6 +1113,9 @@ lds_000_int_0_un0_n .names RST_i.BLIF SM_AMIGA_0_.AR 1 1 0 0 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF cpu_est_2_.C 1 1 0 0 @@ -1125,16 +1146,10 @@ lds_000_int_0_un0_n .names RST_i.BLIF SM_AMIGA_7_.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 0 0 -.names RST_i.BLIF SM_AMIGA_6_.AR -1 1 -0 0 -.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +.names RST_i.BLIF inst_VMA_INTreg.AP 1 1 0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C @@ -1143,6 +1158,12 @@ lds_000_int_0_un0_n .names RST_i.BLIF inst_BGACK_030_INTreg.AP 1 1 0 0 +.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +1 1 +0 0 .names CLK_OSZI_c.BLIF CLK_CNT_0_.C 1 1 0 0 @@ -1155,9 +1176,6 @@ lds_000_int_0_un0_n .names CLK_OSZI_c.BLIF cpu_est_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_VPA_SYNC.C 1 1 0 0 @@ -1197,12 +1215,6 @@ lds_000_int_0_un0_n .names RST_i.BLIF DSACK_INT_1_.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_VMA_INTreg.AP -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C 1 1 0 0 @@ -1221,18 +1233,18 @@ lds_000_int_0_un0_n .names RST_i.BLIF inst_DTACK_SYNC.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_DTACK_DMA.C -1 1 -0 0 -.names RST_i.BLIF inst_DTACK_DMA.AP -1 1 -0 0 .names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D 1 1 0 0 .names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_DTACK_DMA.C +1 1 +0 0 +.names RST_i.BLIF inst_DTACK_DMA.AP +1 1 +0 0 .names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D 1 1 0 0 @@ -1263,6 +1275,15 @@ lds_000_int_0_un0_n .names CLK_OSZI_c.BLIF inst_CLK_000_D1.C 1 1 0 0 +.names gnd_n_n.BLIF CLK_REF_0_.D +1 1 +0 0 +.names gnd_n_n.BLIF CLK_REF_0_.LH +1 1 +0 0 +.names RST_i.BLIF CLK_REF_0_.AP +1 1 +0 0 .names gnd_n_n.BLIF CLK_REF_1_.D 1 1 0 0 @@ -1458,7 +1479,7 @@ lds_000_int_0_un0_n .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 0 0 -.names N_167.BLIF CIIN.OE +.names N_168.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index 6f3435c..cba30fb 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,70 +1,80 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sun May 18 21:01:47 2014 +#$ DATE Thu May 22 14:56:10 2014 #$ MODULE 68030_tk #$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 \ -# SIZE_0_ LDS_000 A_30_ nEXP_SPACE A_29_ BERR A_28_ BG_030 A_27_ BG_000 A_26_ BGACK_030 \ -# A_25_ BGACK_000 A_24_ CLK_030 A_23_ CLK_000 A_22_ CLK_OSZI A_21_ CLK_DIV_OUT A_20_ \ -# CLK_EXP A_19_ FPU_CS A_18_ DTACK A_17_ AVEC A_16_ AVEC_EXP E VPA VMA RST RESET RW \ -# AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_030_1_ \ -# IPL_030_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ -#$ NODES 38 inst_BGACK_030_INTreg inst_FPU_CS_INTreg cpu_est_3_reg CLK_OUT_INTreg \ -# inst_VMA_INTreg cpu_est_0_ cpu_est_1_ IPL_030DFFSH_0_reg inst_AS_000_INTreg \ -# inst_AS_030_000_SYNC IPL_030DFFSH_1_reg inst_DTACK_SYNC inst_VPA_D \ -# IPL_030DFFSH_2_reg inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 \ -# inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_1_ SM_AMIGA_7_ inst_UDS_000_INTreg \ -# inst_LDS_000_INTreg DSACK_INT_1_ SM_AMIGA_4_ SM_AMIGA_1_ inst_DTACK_DMA CLK_CNT_0_ \ -# CLK_CNT_1_ RESETDFFreg SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ \ -# AMIGA_BUS_ENABLEDFFreg BG_000DFFSHreg +# LDS_000 nEXP_SPACE BERR SIZE_0_ BG_030 A_30_ BG_000 A_29_ BGACK_030 A_28_ BGACK_000 A_27_ \ +# CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI A_24_ CLK_DIV_OUT A_23_ CLK_EXP A_22_ FPU_CS A_21_ \ +# DTACK A_20_ AVEC A_19_ AVEC_EXP A_18_ E A_17_ VPA A_16_ VMA RST RESET RW AMIGA_BUS_ENABLE \ +# AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ \ +# DSACK_0_ FC_0_ +#$ NODES 39 BG_000DFFSHreg inst_BGACK_030_INTreg inst_FPU_CS_INTreg cpu_est_3_reg \ +# inst_VMA_INTreg cpu_est_0_ cpu_est_1_ CLK_OUT_INTreg inst_AS_000_INTreg \ +# inst_AS_030_000_SYNC inst_DTACK_SYNC IPL_030DFFSH_0_reg inst_VPA_D inst_VPA_SYNC \ +# IPL_030DFFSH_1_reg inst_CLK_000_D0 inst_CLK_000_D1 IPL_030DFFSH_2_reg \ +# inst_CLK_000_D2 inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_0_ CLK_REF_1_ \ +# SM_AMIGA_7_ inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ SM_AMIGA_4_ \ +# SM_AMIGA_1_ inst_DTACK_DMA CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ RESETDFFreg SM_AMIGA_5_ \ +# SM_AMIGA_2_ SM_AMIGA_0_ AMIGA_BUS_ENABLEDFFreg .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \ A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_0_.BLIF \ -IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \ -inst_FPU_CS_INTreg.BLIF cpu_est_3_reg.BLIF CLK_OUT_INTreg.BLIF \ -inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF IPL_030DFFSH_0_reg.BLIF \ -inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF IPL_030DFFSH_1_reg.BLIF \ -inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF IPL_030DFFSH_2_reg.BLIF \ -inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ -inst_CLK_000_D2.BLIF inst_CLK_OUT_PRE.BLIF SM_AMIGA_6_.BLIF cpu_est_2_.BLIF \ -CLK_REF_1_.BLIF SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF \ -inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF \ -inst_DTACK_DMA.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF RESETDFFreg.BLIF \ -SM_AMIGA_3_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF \ -AMIGA_BUS_ENABLEDFFreg.BLIF BG_000DFFSHreg.BLIF DSACK_1_.PIN.BLIF \ -DTACK.PIN.BLIF +IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF BG_000DFFSHreg.BLIF \ +inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF cpu_est_3_reg.BLIF \ +inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF CLK_OUT_INTreg.BLIF \ +inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF \ +IPL_030DFFSH_0_reg.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF \ +IPL_030DFFSH_1_reg.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ +IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D2.BLIF inst_CLK_OUT_PRE.BLIF \ +SM_AMIGA_6_.BLIF cpu_est_2_.BLIF CLK_REF_0_.BLIF CLK_REF_1_.BLIF \ +SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF \ +DSACK_INT_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF \ +CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF SM_AMIGA_3_.BLIF RESETDFFreg.BLIF \ +SM_AMIGA_5_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF \ +DSACK_1_.PIN.BLIF DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_5_.D SM_AMIGA_5_.C \ -SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D \ -SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR \ -SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C \ -SM_AMIGA_0_.AR cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.C IPL_030DFFSH_0_reg.D \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D \ +SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \ +SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_1_.D \ +cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.C IPL_030DFFSH_0_reg.D \ IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ -SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR inst_CLK_OUT_PRE.C \ -inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \ +SM_AMIGA_7_.AP inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.C \ CLK_CNT_0_.D CLK_CNT_0_.C CLK_CNT_1_.D CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C \ -cpu_est_1_.D cpu_est_1_.C inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ -inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \ -inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ -inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP \ -AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C BG_000DFFSHreg.D \ -BG_000DFFSHreg.C BG_000DFFSHreg.AP DSACK_INT_1_.D DSACK_INT_1_.C \ -DSACK_INT_1_.AP inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_UDS_000_INTreg.D \ +inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_FPU_CS_INTreg.D \ +inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_030_000_SYNC.D \ +inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_AS_000_INTreg.D \ +inst_AS_000_INTreg.C inst_AS_000_INTreg.AP AMIGA_BUS_ENABLEDFFreg.D \ +AMIGA_BUS_ENABLEDFFreg.C BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \ +DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_UDS_000_INTreg.D \ inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D \ inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D \ -inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_DTACK_DMA.D inst_DTACK_DMA.C \ -inst_DTACK_DMA.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_D2.D \ +inst_DTACK_SYNC.C inst_DTACK_SYNC.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ +inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_CLK_000_D2.D \ inst_CLK_000_D2.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D \ inst_CLK_000_D0.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_D1.D \ -inst_CLK_000_D1.C CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR DSACK_1_ DTACK \ -DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE \ -DSACK_0_.OE AVEC_EXP.OE CIIN.OE cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 \ -inst_VMA_INTreg.D.X1 inst_VMA_INTreg.D.X2 inst_CLK_OUT_PRE.D.X1 \ -inst_CLK_OUT_PRE.D.X2 +inst_CLK_000_D1.C CLK_REF_0_.D CLK_REF_0_.LH CLK_REF_0_.AP CLK_REF_1_.D \ +CLK_REF_1_.LH CLK_REF_1_.AR DSACK_1_ DTACK DSACK_0_ DSACK_1_.OE DTACK.OE \ +AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE \ +cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 inst_VMA_INTreg.D.X1 \ +inst_VMA_INTreg.D.X2 inst_CLK_OUT_PRE.D.X1 inst_CLK_OUT_PRE.D.X2 +.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ +inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.D +---11- 1 +--0-1- 1 +1---1- 1 +-0---1 1 +0110-- 0 +0-10-0 0 +-1--0- 0 +----00 0 .names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_5_.D 0-101- 1 @@ -117,6 +127,21 @@ SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D --0-0 0 -1--0 0 .names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D0.BLIF \ +inst_CLK_000_D1.BLIF cpu_est_2_.BLIF cpu_est_1_.D +0--100 1 +01010- 1 +10-10- 1 +-01--- 1 +1-1--1 1 +--1-1- 1 +--10-- 1 +011101 0 +11-100 0 +000--1 0 +110--- 0 +--0-1- 0 +--00-- 0 +.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D0.BLIF \ inst_CLK_000_D1.BLIF cpu_est_2_.BLIF cpu_est_2_.D -0010- 1 11-10- 1 @@ -144,14 +169,14 @@ inst_CLK_000_D1.BLIF IPL_030DFFSH_1_reg.D 0-10 0 -00- 0 -0-1 0 -.names IPL_2_.BLIF IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF IPL_030DFFSH_2_reg.D -1-10 1 --10- 1 --1-1 1 -0-10 0 --00- 0 --0-1 0 +.names IPL_2_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ +IPL_030DFFSH_2_reg.BLIF IPL_030DFFSH_2_reg.D +110- 1 +--11 1 +-0-1 1 +010- 0 +--10 0 +-0-0 0 .names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF SM_AMIGA_7_.BLIF \ SM_AMIGA_0_.BLIF SM_AMIGA_7_.D -11- 1 @@ -159,16 +184,6 @@ SM_AMIGA_0_.BLIF SM_AMIGA_7_.D 0-0- 0 --00 0 -0-- 0 -.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ -inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.D ----11- 1 ---0-1- 1 -1---1- 1 --0---1 1 -0110-- 0 -0-10-0 0 --1--0- 0 -----00 0 .names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \ inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D 1-10 1 @@ -176,33 +191,24 @@ inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D -00- 0 0--- 0 -0-1 0 -.names CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF CLK_CNT_0_.D -100 1 -001 1 -0-0 0 -1-1 0 --1- 0 -.names CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF CLK_CNT_1_.D -001 1 --10 1 -1-1 0 --00 0 --11 0 -.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF cpu_est_2_.BLIF cpu_est_1_.D -0--100 1 -01010- 1 -10-10- 1 --01--- 1 -1-1--1 1 ---1-1- 1 ---10-- 1 -011101 0 -11-100 0 -000--1 0 -110--- 0 ---0-1- 0 ---00-- 0 +.names CLK_REF_0_.BLIF CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \ +CLK_CNT_0_.D +-100 1 +-001 1 +1-0- 1 +00-0 0 +01-1 0 +--1- 0 +.names CLK_REF_0_.BLIF CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \ +CLK_CNT_1_.D +-110 1 +0-10 1 +-001 1 +1-01 1 +10-0 0 +010- 0 +--00 0 +--11 0 .names AS_030.BLIF CLK_000.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF \ cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF \ inst_CLK_000_D0.BLIF cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_VPA_SYNC.D @@ -277,16 +283,16 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D -111- 0 0--00 0 --0-0 0 -.names AS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF CLK_030.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_7_.BLIF BG_000DFFSHreg.BLIF BG_000DFFSHreg.D ----000- 1 ----1--1 1 +.names AS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF CLK_030.BLIF \ +BG_000DFFSHreg.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF BG_000DFFSHreg.D +---11-- 1 +---0-00 1 -1-0--- 1 0--0--- 1 --1---- 1 1000-1- 0 -10001-- 0 ---01--0 0 +1000--1 0 +--010-- 0 .names AS_030.BLIF inst_CLK_000_D0.BLIF inst_CLK_OUT_PRE.BLIF \ DSACK_INT_1_.BLIF SM_AMIGA_1_.BLIF DSACK_INT_1_.D --01- 1 @@ -432,6 +438,12 @@ inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names RST.BLIF SM_AMIGA_6_.AR +0 1 +1 0 .names CLK_OSZI.BLIF SM_AMIGA_5_.C 1 1 0 0 @@ -468,6 +480,9 @@ inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D .names RST.BLIF SM_AMIGA_0_.AR 0 1 1 0 +.names CLK_OSZI.BLIF cpu_est_1_.C +1 1 +0 0 .names CLK_OSZI.BLIF cpu_est_2_.C 1 1 0 0 @@ -498,21 +513,21 @@ inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D .names RST.BLIF SM_AMIGA_7_.AP 0 1 1 0 -.names CLK_OSZI.BLIF SM_AMIGA_6_.C +.names CLK_OSZI.BLIF inst_VMA_INTreg.C 1 1 0 0 -.names RST.BLIF SM_AMIGA_6_.AR +.names RST.BLIF inst_VMA_INTreg.AP 0 1 1 0 -.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C -1 1 -0 0 .names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 .names RST.BLIF inst_BGACK_030_INTreg.AP 0 1 1 0 +.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C +1 1 +0 0 .names CLK_OSZI.BLIF CLK_CNT_0_.C 1 1 0 0 @@ -529,9 +544,6 @@ inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D .names CLK_OSZI.BLIF cpu_est_0_.C 1 1 0 0 -.names CLK_OSZI.BLIF cpu_est_1_.C -1 1 -0 0 .names CLK_OSZI.BLIF inst_VPA_SYNC.C 1 1 0 0 @@ -571,12 +583,6 @@ inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D .names RST.BLIF DSACK_INT_1_.AP 0 1 1 0 -.names CLK_OSZI.BLIF inst_VMA_INTreg.C -1 1 -0 0 -.names RST.BLIF inst_VMA_INTreg.AP -0 1 -1 0 .names CLK_OSZI.BLIF inst_UDS_000_INTreg.C 1 1 0 0 @@ -595,18 +601,18 @@ inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D .names RST.BLIF inst_DTACK_SYNC.AP 0 1 1 0 -.names CLK_OSZI.BLIF inst_DTACK_DMA.C -1 1 -0 0 -.names RST.BLIF inst_DTACK_DMA.AP -0 1 -1 0 .names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D 1 1 0 0 .names CLK_OSZI.BLIF CLK_OUT_INTreg.C 1 1 0 0 +.names CLK_OSZI.BLIF inst_DTACK_DMA.C +1 1 +0 0 +.names RST.BLIF inst_DTACK_DMA.AP +0 1 +1 0 .names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D 1 1 0 0 @@ -637,6 +643,13 @@ inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D .names CLK_OSZI.BLIF inst_CLK_000_D1.C 1 1 0 0 +.names CLK_REF_0_.D + 0 +.names CLK_REF_0_.LH + 0 +.names RST.BLIF CLK_REF_0_.AP +0 1 +1 0 .names CLK_REF_1_.D 0 .names CLK_REF_1_.LH @@ -727,13 +740,16 @@ inst_VMA_INTreg.D.X2 01---1-- 0 01----1- 0 .names inst_CLK_OUT_PRE.BLIF inst_CLK_OUT_PRE.D.X1 -1 1 -0 0 -.names inst_CLK_OUT_PRE.BLIF CLK_REF_1_.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \ -inst_CLK_OUT_PRE.D.X2 --000 1 --101 1 ---1- 0 --0-1 0 --1-0 0 +0 1 +1 0 +.names inst_CLK_OUT_PRE.BLIF CLK_REF_0_.BLIF CLK_REF_1_.BLIF CLK_CNT_0_.BLIF \ +CLK_CNT_1_.BLIF inst_CLK_OUT_PRE.D.X2 +-0-1- 1 +--0-1 1 +--1-0 1 +-1-0- 1 +-1111 0 +-0101 0 +-1010 0 +-0000 0 .end diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index e87bbd0..35a63e8 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 1.7.00.05.28.13 -// Design '68030_tk' created Sun May 18 21:01:47 2014 +// Design '68030_tk' created Thu May 22 14:56:10 2014 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index a2cc192..2f3700d 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,7 +2,7 @@ Copyright(C), 1992-2013, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Sun May 18 21:01:47 2014 +Design bus68030 created Thu May 22 14:56:10 2014 P-Terms Fan-in Fan-out Type Name (attributes) @@ -90,8 +90,7 @@ Design bus68030 created Sun May 18 21:01:47 2014 1 1 1 Node inst_CLK_000_D1.C 1 1 1 Node inst_CLK_000_D2.D 1 1 1 Node inst_CLK_000_D2.C - 3 3 1 NodeX1 inst_CLK_OUT_PRE.D.X1 - 1 2 1 NodeX2 inst_CLK_OUT_PRE.D.X2 + 4 4 1 Node inst_CLK_OUT_PRE.T 1 1 1 Node inst_CLK_OUT_PRE.C 1 1 1 Node SM_AMIGA_6_.AR 4 6 1 Node SM_AMIGA_6_.D @@ -99,6 +98,9 @@ Design bus68030 created Sun May 18 21:01:47 2014 3 6 1 NodeX1 cpu_est_2_.D.X1 1 1 1 NodeX2 cpu_est_2_.D.X2 1 1 1 Node cpu_est_2_.C + 0 0 1 Node CLK_REF_0_.D + 1 1 1 Node CLK_REF_0_.AP + 0 0 1 Node CLK_REF_0_.LH 1 1 1 Node CLK_REF_1_.AR 0 0 1 Node CLK_REF_1_.D 0 0 1 Node CLK_REF_1_.LH @@ -111,9 +113,9 @@ Design bus68030 created Sun May 18 21:01:47 2014 1 1 1 Node SM_AMIGA_1_.AR 3 4 1 Node SM_AMIGA_1_.D 1 1 1 Node SM_AMIGA_1_.C - 2 3 1 Node CLK_CNT_0_.D + 3 4 1 Node CLK_CNT_0_.D 1 1 1 Node CLK_CNT_0_.C - 2 3 1 Node CLK_CNT_1_.D + 4 4 1 Node CLK_CNT_1_.D 1 1 1 Node CLK_CNT_1_.C 1 1 1 Node SM_AMIGA_3_.AR 3 5 1 Node SM_AMIGA_3_.D @@ -128,9 +130,9 @@ Design bus68030 created Sun May 18 21:01:47 2014 3 5 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C ========= - 181 P-Term Total: 181 + 185 P-Term Total: 185 Total Pins: 59 - Total Nodes: 22 + Total Nodes: 23 Average P-Term/Output: 2 @@ -162,8 +164,8 @@ DSACK_0_ = (1); DSACK_0_.OE = (nEXP_SPACE); -IPL_030_2_.D = (IPL_030_2_.Q & !inst_CLK_000_D0.Q - # IPL_030_2_.Q & inst_CLK_000_D1.Q +IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q + # inst_CLK_000_D1.Q & IPL_030_2_.Q # IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); IPL_030_2_.AP = (!RST); @@ -347,11 +349,10 @@ inst_CLK_000_D2.D = (inst_CLK_000_D1.Q); inst_CLK_000_D2.C = (CLK_OSZI); -inst_CLK_OUT_PRE.D.X1 = (inst_CLK_OUT_PRE.Q & CLK_CNT_0_.Q - # inst_CLK_OUT_PRE.Q & CLK_CNT_1_.Q - # !inst_CLK_OUT_PRE.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); - -inst_CLK_OUT_PRE.D.X2 = (CLK_REF_1_.Q & !CLK_CNT_0_.Q); +inst_CLK_OUT_PRE.T = (CLK_REF_0_.Q & CLK_REF_1_.Q & CLK_CNT_0_.Q & CLK_CNT_1_.Q + # !CLK_REF_0_.Q & CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q + # CLK_REF_0_.Q & !CLK_REF_1_.Q & CLK_CNT_0_.Q & !CLK_CNT_1_.Q + # !CLK_REF_0_.Q & !CLK_REF_1_.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); inst_CLK_OUT_PRE.C = (CLK_OSZI); @@ -372,6 +373,12 @@ cpu_est_2_.D.X2 = (cpu_est_2_.Q); cpu_est_2_.C = (CLK_OSZI); +CLK_REF_0_.D = (0); + +CLK_REF_0_.AP = (!RST); + +CLK_REF_0_.LH = (0); + CLK_REF_1_.AR = (!RST); CLK_REF_1_.D = (0); @@ -400,13 +407,16 @@ SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q SM_AMIGA_1_.C = (CLK_OSZI); -CLK_CNT_0_.D = (!CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q +CLK_CNT_0_.D = (CLK_REF_0_.Q & !CLK_CNT_0_.Q + # !CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q # CLK_REF_1_.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); CLK_CNT_0_.C = (CLK_OSZI); -CLK_CNT_1_.D = (CLK_CNT_0_.Q & !CLK_CNT_1_.Q - # !CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q); +CLK_CNT_1_.D = (CLK_REF_0_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q + # !CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q + # !CLK_REF_0_.Q & CLK_CNT_0_.Q & !CLK_CNT_1_.Q + # CLK_REF_1_.Q & CLK_CNT_0_.Q & !CLK_CNT_1_.Q); CLK_CNT_1_.C = (CLK_OSZI); diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index 0f6eaff..8e517b1 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -35,12 +35,13 @@ DATA LOCATION BG_030:C_*_21 // INP DATA LOCATION CIIN:E_12_47 // OUT DATA LOCATION CLK_000:*_*_11 // INP DATA LOCATION CLK_030:*_*_64 // INP -DATA LOCATION CLK_CNT_0_:B_10 // NOD -DATA LOCATION CLK_CNT_1_:B_6 // NOD +DATA LOCATION CLK_CNT_0_:A_12 // NOD +DATA LOCATION CLK_CNT_1_:A_8 // NOD DATA LOCATION CLK_DIV_OUT:G_0_65 // OUT DATA LOCATION CLK_EXP:B_0_10 // OUT DATA LOCATION CLK_OSZI:*_*_61 // Cin -DATA LOCATION CLK_REF_1_:D_6 // NOD +DATA LOCATION CLK_REF_0_:D_6 // NOD +DATA LOCATION CLK_REF_1_:B_2 // NOD DATA LOCATION DSACK_0_:H_12_80 // OUT DATA LOCATION DSACK_1_:H_8_81 // IO {RN_DSACK_1_} DATA LOCATION DS_030:A_*_98 // INP @@ -74,28 +75,28 @@ DATA LOCATION RST:*_*_86 // INP DATA LOCATION RW:G_*_71 // INP DATA LOCATION SIZE_0_:G_*_70 // INP DATA LOCATION SIZE_1_:H_*_79 // INP -DATA LOCATION SM_AMIGA_0_:G_5 // NOD -DATA LOCATION SM_AMIGA_1_:H_5 // NOD -DATA LOCATION SM_AMIGA_2_:G_9 // NOD -DATA LOCATION SM_AMIGA_3_:G_2 // NOD -DATA LOCATION SM_AMIGA_4_:B_9 // NOD -DATA LOCATION SM_AMIGA_5_:B_2 // NOD -DATA LOCATION SM_AMIGA_6_:A_0 // NOD -DATA LOCATION SM_AMIGA_7_:B_13 // NOD +DATA LOCATION SM_AMIGA_0_:H_9 // NOD +DATA LOCATION SM_AMIGA_1_:B_13 // NOD +DATA LOCATION SM_AMIGA_2_:G_5 // NOD +DATA LOCATION SM_AMIGA_3_:G_9 // NOD +DATA LOCATION SM_AMIGA_4_:B_5 // NOD +DATA LOCATION SM_AMIGA_5_:G_2 // NOD +DATA LOCATION SM_AMIGA_6_:G_12 // NOD +DATA LOCATION SM_AMIGA_7_:H_5 // NOD DATA LOCATION UDS_000:D_12_32 // IO {RN_UDS_000} DATA LOCATION VMA:D_5_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP -DATA LOCATION cpu_est_0_:D_2 // NOD -DATA LOCATION cpu_est_1_:D_13 // NOD -DATA LOCATION cpu_est_2_:G_13 // NOD +DATA LOCATION cpu_est_0_:G_13 // NOD +DATA LOCATION cpu_est_1_:G_1 // NOD +DATA LOCATION cpu_est_2_:D_2 // NOD DATA LOCATION inst_AS_030_000_SYNC:H_1 // NOD -DATA LOCATION inst_CLK_000_D0:G_12 // NOD -DATA LOCATION inst_CLK_000_D1:G_8 // NOD -DATA LOCATION inst_CLK_000_D2:G_1 // NOD -DATA LOCATION inst_CLK_OUT_PRE:B_5 // NOD -DATA LOCATION inst_DTACK_SYNC:G_10 // NOD -DATA LOCATION inst_VPA_D:H_9 // NOD -DATA LOCATION inst_VPA_SYNC:G_6 // NOD +DATA LOCATION inst_CLK_000_D0:G_8 // NOD +DATA LOCATION inst_CLK_000_D1:D_13 // NOD +DATA LOCATION inst_CLK_000_D2:G_6 // NOD +DATA LOCATION inst_CLK_OUT_PRE:A_0 // NOD +DATA LOCATION inst_DTACK_SYNC:F_0 // NOD +DATA LOCATION inst_VPA_D:B_9 // NOD +DATA LOCATION inst_VPA_SYNC:G_10 // NOD DATA LOCATION nEXP_SPACE:*_*_14 // INP DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT DATA IO_DIR AMIGA_BUS_ENABLE:OUT @@ -169,55 +170,55 @@ DATA PW_LEVEL AS_030:0 DATA SLEW AS_030:0 DATA PW_LEVEL DS_030:0 DATA SLEW DS_030:0 -DATA PW_LEVEL SIZE_0_:0 -DATA SLEW SIZE_0_:0 -DATA PW_LEVEL A_30_:0 -DATA SLEW A_30_:0 DATA SLEW nEXP_SPACE:0 -DATA PW_LEVEL A_29_:0 -DATA SLEW A_29_:0 DATA PW_LEVEL BERR:0 DATA SLEW BERR:0 -DATA PW_LEVEL A_28_:0 -DATA SLEW A_28_:0 +DATA PW_LEVEL SIZE_0_:0 +DATA SLEW SIZE_0_:0 DATA PW_LEVEL BG_030:0 DATA SLEW BG_030:0 -DATA PW_LEVEL A_27_:0 -DATA SLEW A_27_:0 -DATA PW_LEVEL A_26_:0 -DATA SLEW A_26_:0 -DATA PW_LEVEL A_25_:0 -DATA SLEW A_25_:0 +DATA PW_LEVEL A_30_:0 +DATA SLEW A_30_:0 +DATA PW_LEVEL A_29_:0 +DATA SLEW A_29_:0 +DATA PW_LEVEL A_28_:0 +DATA SLEW A_28_:0 DATA PW_LEVEL BGACK_000:0 DATA SLEW BGACK_000:0 +DATA PW_LEVEL A_27_:0 +DATA SLEW A_27_:0 +DATA SLEW CLK_030:0 +DATA PW_LEVEL A_26_:0 +DATA SLEW A_26_:0 +DATA SLEW CLK_000:0 +DATA PW_LEVEL A_25_:0 +DATA SLEW A_25_:0 +DATA SLEW CLK_OSZI:0 DATA PW_LEVEL A_24_:0 DATA SLEW A_24_:0 -DATA SLEW CLK_030:0 -DATA PW_LEVEL A_23_:0 -DATA SLEW A_23_:0 -DATA SLEW CLK_000:0 -DATA PW_LEVEL A_22_:0 -DATA SLEW A_22_:0 -DATA SLEW CLK_OSZI:0 -DATA PW_LEVEL A_21_:0 -DATA SLEW A_21_:0 DATA PW_LEVEL CLK_DIV_OUT:0 DATA SLEW CLK_DIV_OUT:0 +DATA PW_LEVEL A_23_:0 +DATA SLEW A_23_:0 +DATA PW_LEVEL A_22_:0 +DATA SLEW A_22_:0 +DATA PW_LEVEL A_21_:0 +DATA SLEW A_21_:0 DATA PW_LEVEL A_20_:0 DATA SLEW A_20_:0 +DATA PW_LEVEL AVEC:0 +DATA SLEW AVEC:0 DATA PW_LEVEL A_19_:0 DATA SLEW A_19_:0 +DATA PW_LEVEL AVEC_EXP:0 +DATA SLEW AVEC_EXP:0 DATA PW_LEVEL A_18_:0 DATA SLEW A_18_:0 DATA PW_LEVEL A_17_:0 DATA SLEW A_17_:0 -DATA PW_LEVEL AVEC:0 -DATA SLEW AVEC:0 +DATA SLEW VPA:0 DATA PW_LEVEL A_16_:0 DATA SLEW A_16_:0 -DATA PW_LEVEL AVEC_EXP:0 -DATA SLEW AVEC_EXP:0 -DATA SLEW VPA:0 DATA SLEW RST:0 DATA PW_LEVEL RW:0 DATA SLEW RW:0 @@ -293,6 +294,8 @@ DATA PW_LEVEL SM_AMIGA_6_:0 DATA SLEW SM_AMIGA_6_:0 DATA PW_LEVEL cpu_est_2_:0 DATA SLEW cpu_est_2_:0 +DATA PW_LEVEL CLK_REF_0_:0 +DATA SLEW CLK_REF_0_:0 DATA PW_LEVEL CLK_REF_1_:0 DATA SLEW CLK_REF_1_:0 DATA PW_LEVEL SM_AMIGA_7_:0 diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index 804ef82..d34e1c4 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,15 +1,16 @@ -GROUP MACH_SEG_A SM_AMIGA_6_ AVEC -GROUP MACH_SEG_B SM_AMIGA_5_ SM_AMIGA_7_ IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ - RN_IPL_030_0_ IPL_030_2_ RN_IPL_030_2_ inst_CLK_OUT_PRE SM_AMIGA_4_ - CLK_CNT_0_ CLK_CNT_1_ CLK_EXP RESET +GROUP MACH_SEG_A inst_CLK_OUT_PRE CLK_CNT_0_ CLK_CNT_1_ AVEC +GROUP MACH_SEG_B SM_AMIGA_1_ IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ + IPL_030_2_ RN_IPL_030_2_ SM_AMIGA_4_ CLK_REF_1_ inst_VPA_D CLK_EXP + RESET GROUP MACH_SEG_C AVEC_EXP AMIGA_BUS_ENABLE_LOW GROUP MACH_SEG_D LDS_000 RN_LDS_000 UDS_000 RN_UDS_000 VMA RN_VMA BG_000 - RN_BG_000 AS_000 RN_AS_000 cpu_est_1_ AMIGA_BUS_ENABLE RN_AMIGA_BUS_ENABLE - DTACK cpu_est_0_ CLK_REF_1_ + RN_BG_000 AS_000 RN_AS_000 cpu_est_2_ AMIGA_BUS_ENABLE RN_AMIGA_BUS_ENABLE + DTACK CLK_REF_0_ inst_CLK_000_D1 GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR -GROUP MACH_SEG_G inst_VPA_SYNC inst_DTACK_SYNC E RN_E cpu_est_2_ SM_AMIGA_2_ - SM_AMIGA_3_ SM_AMIGA_0_ inst_CLK_000_D0 CLK_DIV_OUT inst_CLK_000_D2 - inst_CLK_000_D1 +GROUP MACH_SEG_F inst_DTACK_SYNC +GROUP MACH_SEG_G inst_VPA_SYNC SM_AMIGA_5_ SM_AMIGA_6_ E RN_E cpu_est_1_ + SM_AMIGA_2_ SM_AMIGA_3_ cpu_est_0_ inst_CLK_000_D0 CLK_DIV_OUT inst_CLK_000_D2 + GROUP MACH_SEG_H inst_AS_030_000_SYNC FPU_CS RN_FPU_CS DSACK_1_ RN_DSACK_1_ - SM_AMIGA_1_ BGACK_030 RN_BGACK_030 inst_VPA_D DSACK_0_ \ No newline at end of file + SM_AMIGA_0_ SM_AMIGA_7_ BGACK_030 RN_BGACK_030 DSACK_0_ \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index 76f5e1b..b80f688 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -715:716[ORb$ \ No newline at end of file +0610226pI?E^&ðS \ No newline at end of file diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index b70c97e..9531857 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Sun May 18 21:01:51 2014 +DATE: Thu May 22 14:56:14 2014 ABEL mach447a * @@ -32,47 +32,47 @@ NOTE Run Time Upper Bound in 15 minutes 0 * NOTE Zero Hold Time For Input Registers? Y * NOTE Table of pin names and numbers* NOTE PINS SIZE_1_:79 A_31_:4 IPL_2_:68 FC_1_:58 AS_030:82* -NOTE PINS DS_030:98 SIZE_0_:70 A_30_:5 nEXP_SPACE:14 A_29_:6* -NOTE PINS BERR:41 A_28_:15 BG_030:21 A_27_:16 A_26_:17 A_25_:18* -NOTE PINS BGACK_000:28 A_24_:19 CLK_030:64 A_23_:84 CLK_000:11* -NOTE PINS A_22_:85 CLK_OSZI:61 A_21_:94 CLK_DIV_OUT:65 A_20_:93* -NOTE PINS A_19_:97 A_18_:95 A_17_:59 AVEC:92 A_16_:96 AVEC_EXP:22* -NOTE PINS VPA:36 RST:86 RW:71 AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20* -NOTE PINS CIIN:47 A_0_:69 IPL_1_:56 IPL_0_:67 DSACK_0_:80* -NOTE PINS FC_0_:57 IPL_030_2_:9 DSACK_1_:81 AS_000:33 UDS_000:32* -NOTE PINS LDS_000:31 BG_000:29 BGACK_030:83 CLK_EXP:10 FPU_CS:78* -NOTE PINS DTACK:30 E:66 VMA:35 RESET:3 AMIGA_BUS_ENABLE:34* -NOTE PINS IPL_030_1_:7 IPL_030_0_:8 * +NOTE PINS DS_030:98 nEXP_SPACE:14 BERR:41 SIZE_0_:70 BG_030:21* +NOTE PINS A_30_:5 A_29_:6 A_28_:15 BGACK_000:28 A_27_:16* +NOTE PINS CLK_030:64 A_26_:17 CLK_000:11 A_25_:18 CLK_OSZI:61* +NOTE PINS A_24_:19 CLK_DIV_OUT:65 A_23_:84 A_22_:85 A_21_:94* +NOTE PINS A_20_:93 AVEC:92 A_19_:97 AVEC_EXP:22 A_18_:95* +NOTE PINS A_17_:59 VPA:36 A_16_:96 RST:86 RW:71 AMIGA_BUS_DATA_DIR:48* +NOTE PINS AMIGA_BUS_ENABLE_LOW:20 CIIN:47 A_0_:69 IPL_1_:56* +NOTE PINS IPL_0_:67 DSACK_0_:80 FC_0_:57 IPL_030_2_:9 DSACK_1_:81* +NOTE PINS AS_000:33 UDS_000:32 LDS_000:31 BG_000:29 BGACK_030:83* +NOTE PINS CLK_EXP:10 FPU_CS:78 DTACK:30 E:66 VMA:35 RESET:3* +NOTE PINS AMIGA_BUS_ENABLE:34 IPL_030_1_:7 IPL_030_0_:8 * NOTE Table of node names and numbers* NOTE NODES RN_IPL_030_2_:131 RN_DSACK_1_:281 RN_AS_000:187 * NOTE NODES RN_UDS_000:191 RN_LDS_000:185 RN_BG_000:175 RN_BGACK_030:275 * NOTE NODES RN_FPU_CS:269 RN_DTACK:173 RN_E:251 RN_VMA:181 * NOTE NODES RN_AMIGA_BUS_ENABLE:179 RN_IPL_030_1_:143 RN_IPL_030_0_:137 * -NOTE NODES cpu_est_0_:176 cpu_est_1_:193 inst_AS_030_000_SYNC:271 * -NOTE NODES inst_DTACK_SYNC:260 inst_VPA_D:283 inst_VPA_SYNC:254 * -NOTE NODES inst_CLK_000_D0:263 inst_CLK_000_D1:257 inst_CLK_000_D2:247 * -NOTE NODES inst_CLK_OUT_PRE:133 SM_AMIGA_6_:101 cpu_est_2_:265 * -NOTE NODES CLK_REF_1_:182 SM_AMIGA_7_:145 SM_AMIGA_4_:139 * -NOTE NODES SM_AMIGA_1_:277 CLK_CNT_0_:140 CLK_CNT_1_:134 * -NOTE NODES SM_AMIGA_3_:248 SM_AMIGA_5_:128 SM_AMIGA_2_:259 * -NOTE NODES SM_AMIGA_0_:253 * +NOTE NODES cpu_est_0_:265 cpu_est_1_:247 inst_AS_030_000_SYNC:271 * +NOTE NODES inst_DTACK_SYNC:221 inst_VPA_D:139 inst_VPA_SYNC:260 * +NOTE NODES inst_CLK_000_D0:257 inst_CLK_000_D1:193 inst_CLK_000_D2:254 * +NOTE NODES inst_CLK_OUT_PRE:101 SM_AMIGA_6_:263 cpu_est_2_:176 * +NOTE NODES CLK_REF_0_:182 CLK_REF_1_:128 SM_AMIGA_7_:277 * +NOTE NODES SM_AMIGA_4_:133 SM_AMIGA_1_:145 CLK_CNT_0_:119 * +NOTE NODES CLK_CNT_1_:113 SM_AMIGA_3_:259 SM_AMIGA_5_:248 * +NOTE NODES SM_AMIGA_2_:253 SM_AMIGA_0_:283 * NOTE BLOCK 0 * L000000 - 111111111111111011110111111111111111111111111111111111111111111111 - 111111111011111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111011111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111101111111111111111 111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 101111111111111111111111101111011111111111111111111111111111111111* + 111111111111111111110111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111011111111111111111111111111111111111111111111111 + 111111011111111111111111111111111111111111111111111111111111111111 + 111111110111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111* L000594 000000000000000000000000000000000000000000000000000000000000000000* -L000660 111111111111111111111111011111011111111111111111111111111111111111* -L000726 111111111111111111111111111011011111111111111111111111111111111111* -L000792 111111111111111111111111111111011111111111111111011111111111111111* -L000858 111111111111111011110111111111111111111111111111111111111111111111* +L000660 111111010111111111010111111111111111111111111111111111111111111111* +L000726 111111011011111111100111111111111111111111111111111111111111111111* +L000792 111111100111111111011011111111111111111111111111111111111111111111* +L000858 111111101011111111101011111111111111111111111111111111111111111111* L000924 000000000000000000000000000000000000000000000000000000000000000000* L000990 111111111111111111111111111111111111111111111111111111111111111111* L001056 111111111111111111111111111111111111111111111111111111111111111111* @@ -117,11 +117,11 @@ L003366 111111111111111111111111111111111111111111111111111111111111111111* L003432 111111111111111111111111111111111111111111111111111111111111111111* L003498 000000000000000000000000000000000000000000000000000000000000000000* -L003564 111111111111111111111111111111111111111111111111111111111111111111* -L003630 111111111111111111111111111111111111111111111111111111111111111111* -L003696 111111111111111111111111111111111111111111111111111111111111111111* -L003762 111111111111111111111111111111111111111111111111111111111111111111* -L003828 111111111111111111111111111111111111111111111111111111111111111111* +L003564 111111011111111111101011111111111111111111111111111111111111111111* +L003630 111111010111111111101111111111111111111111111111111111111111111111* +L003696 111111101011111111011111111111111111111111111111111111111111111111* +L003762 111111101111111111010111111111111111111111111111111111111111111111* +L003828 000000000000000000000000000000000000000000000000000000000000000000* L003894 111111111111111111111111111111111111111111111111111111111111111111* L003960 111111111111111111111111111111111111111111111111111111111111111111* L004026 111111111111111111111111111111111111111111111111111111111111111111* @@ -141,11 +141,11 @@ L004818 111111111111111111111111111111111111111111111111111111111111111111* L004884 111111111111111111111111111111111111111111111111111111111111111111* L004950 000000000000000000000000000000000000000000000000000000000000000000* -L005016 111111111111111111111111111111111111111111111111111111111111111111* -L005082 111111111111111111111111111111111111111111111111111111111111111111* -L005148 111111111111111111111111111111111111111111111111111111111111111111* -L005214 111111111111111111111111111111111111111111111111111111111111111111* -L005280 111111111111111111111111111111111111111111111111111111111111111111* +L005016 111111110111111111101111111111111111111111111111111111111111111111* +L005082 111111011111111111101011111111111111111111111111111111111111111111* +L005148 111111101111111111100111111111111111111111111111111111111111111111* +L005214 000000000000000000000000000000000000000000000000000000000000000000* +L005280 000000000000000000000000000000000000000000000000000000000000000000* L005346 111111111111111111111111111111111111111111111111111111111111111111* L005412 111111111111111111111111111111111111111111111111111111111111111111* L005478 111111111111111111111111111111111111111111111111111111111111111111* @@ -164,39 +164,39 @@ L006204 111111111111111111111111111111111111111111111111111111111111111111* L006270 111111111111111111111111111111111111111111111111111111111111111111* L006336 111111111111111111111111111111111111111111111111111111111111111111* L006402 - 101111111111111111111111111111111111111111111111111111111111111111 + 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L006534 0010* -L006538 10100110010000* +L006538 10100111010000* L006552 11011011111110* L006566 11110011110101* -L006580 11110111111111* -L006594 00110011111000* -L006608 11000111110011* -L006622 11110011110001* -L006636 11110111110011* -L006650 11110011110000* -L006664 11111011110011* -L006678 11110111110001* -L006692 11111111110011* -L006706 11110011110000* -L006720 11111011110011* -L006734 11110111110001* +L006580 11111111111111* +L006594 00111011111000* +L006608 11000011110011* +L006622 11110111110000* +L006636 11110011110010* +L006650 10100110010001* +L006664 11000111110011* +L006678 11111111110000* +L006692 11110011110011* +L006706 10100110010001* +L006720 11001011110011* +L006734 11110111110000* L006748 11111111110011* NOTE BLOCK 1 * L006762 - 110111111111111111111111111110111111111111111111111111110111111111 - 111101111111011111111111111111111111111111111111111111111110111111 - 111111101011111101111101111011111111111111111111111111111111110111 - 101111111111111111110111111111111111111111111011111111011111111111 - 111111111111111111111111111111111111111111111111101111111111111111 + 111111111111111111111111011111111111111111111111111111110111111111 + 111111111111111111111111111111111111111111111111111111111110111111 + 111111101011111101111111111011111111111111111111111111111111110111 + 101111111111111111111111111111111111111111111010111111011111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111110111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111110111111111111111111111111111111111 - 111111111111111111111111101111011111111111101111111111111111111111* + 110111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111110111111111011111111111101111111111111111111111* L007356 111111111111111111111111111111111111111111111111111111111111111111* -L007422 111111111111111111111111111111111111111111111111111111111111110111* +L007422 111111111111111111111111111111011111111111111111111111111111111111* L007488 111111111111111111111111111111111111111111111111111111111101111111* L007554 000000000000000000000000000000000000000000000000000000000000000000* L007620 000000000000000000000000000000000000000000000000000000000000000000* @@ -208,11 +208,11 @@ L007950 000000000000000000000000000000000000000000000000000000000000000000* L008016 000000000000000000000000000000000000000000000000000000000000000000* L008082 111111111111111111111111111111111111111111111111111111111111111111* -L008148 111111111111111111111111100111011111111111111111101111111111111111* -L008214 111111111111111111110111111101111111111111111111111111111111111111* -L008280 000000000000000000000000000000000000000000000000000000000000000000* -L008346 000000000000000000000000000000000000000000000000000000000000000000* -L008412 000000000000000000000000000000000000000000000000000000000000000000* +L008148 000000000000000000000000000000000000000000000000000000000000000000* +L008214 000000000000000000000000000000000000000000000000000000000000000000* +L008280 111111111111111111111111111111111111111111101111111111111111111111* +L008346 111111111111111111111111111111111111111111111111111111111111111111* +L008412 111111111111111111111111111111111111111111111111111111111111111111* L008478 111111111111111111111111111111111111111111111111111111111111111111* L008544 111111111111111111111111111111111111111111111111111111111111111111* L008610 111111111111111111111111111111111111111111111111111111111111111111* @@ -220,47 +220,47 @@ L008676 111111111111111111111111111111111111111111111111111111111111111111* L008742 111111111111111111111111111111111111111111111111111111111111111111* L008808 111111111111111111111111111111111111111111111111111111111111111111* -L008874 111111111111111111111111111110111111111111111111111111011111111111* -L008940 111111111111111111111111110111111111111111111111111111011111111111* -L009006 111111110111111111111111111001111111111111111111111111111111111111* +L008874 111011110111111111111111110111111111111111111111111111111111111111* +L008940 111111111111111111111111111011111111111111111111111111011111111111* +L009006 110111111111111111111111111111111111111111111111111111011111111111* L009072 000000000000000000000000000000000000000000000000000000000000000000* L009138 000000000000000000000000000000000000000000000000000000000000000000* -L009204 111110111111111111111111111111110111111111111111111111111111111111* -L009270 111111111111111111111111111111111111111111111111111111111101111111* +L009204 111111111111111111111111111011111111111111111111111111111111110111* +L009270 111111111111111111111111111011111111111111111101111111111111111111* L009336 000000000000000000000000000000000000000000000000000000000000000000* -L009402 111111111111111111111111111111111111111111111111111111111111111111* -L009468 111111111111111111111111111111111111111111111111111111111111111111* +L009402 000000000000000000000000000000000000000000000000000000000000000000* +L009468 000000000000000000000000000000000000000000000000000000000000000000* L009534 111111111111111111111111111111111111111111111111111111111111111111* -L009600 111110111111111111111101111111111011111111111111111111111111111111* -L009666 111111111111111111111111111111111111111111111111111111111101111111* -L009732 000000000000000000000000000000000000000000000000000000000000000000* -L009798 111101111111111111111110111111111111111111111111111111111111111111* -L009864 000000000000000000000000000000000000000000000000000000000000000000* -L009930 111101111111111111111111111111111111111111111111111111111111110111* -L009996 111111111111111111111101111111111111111111111111111111111111110111* -L010062 111110111111111111111110111111111111111111111111111111111111111011* -L010128 000000000000000000000000000000000000000000000000000000000000000000* -L010194 000000000000000000000000000000000000000000000000000000000000000000* +L009600 111111111111111111111111111111111111111111111111111111111111111111* +L009666 111111111111111111111111111111111111111111111111111111111111111111* +L009732 111111111111111111111111111111111111111111111111111111111111111111* +L009798 111111111111111111111111111111111111111111111111111111111111111111* +L009864 111111111111111111111111111111111111111111111111111111111111111111* +L009930 111111111111111111111111111111111111111111111111111111111111111111* +L009996 111111111111111111111111111111111111111111111111111111111111111111* +L010062 111111111111111111111111111111111111111111111111111111111111111111* +L010128 111111111111111111111111111111111111111111111111111111111111111111* +L010194 111111111111111111111111111111111111111111111111111111111111111111* L010260 000000000000000000000000000000000000000000000000000000000000000000* -L010326 111111111111111101111111111110111111111111111111111111111111111111* -L010392 111111111111111101111111110111111111111111111111111111111111111111* -L010458 011111111111111111111111111001111111111111111111111111111111111111* +L010326 111111111111111101111111111011111111111111111111111111111111111111* +L010392 110111111111111101111111111111111111111111111111111111111111111111* +L010458 011011111111111111111111110111111111111111111111111111111111111111* L010524 000000000000000000000000000000000000000000000000000000000000000000* L010590 000000000000000000000000000000000000000000000000000000000000000000* -L010656 111111111111011111111111111110111111111111111111111111111111111111* -L010722 111111111111111111110111111110111111111111111111111111111111111111* +L010656 111111111111111111110111111111111111111111111111111111111111111111* +L010722 111111111111111111111111111111111111111111111111111111111101111111* L010788 000000000000000000000000000000000000000000000000000000000000000000* -L010854 000000000000000000000000000000000000000000000000000000000000000000* -L010920 000000000000000000000000000000000000000000000000000000000000000000* +L010854 111111111111111111111111111111111111111111111111111111111111111111* +L010920 111111111111111111111111111111111111111111111111111111111111111111* L010986 000000000000000000000000000000000000000000000000000000000000000000* -L011052 111110111111111111111101111111111011111111111111111111111111111111* -L011118 111111111111111111111111111111111111111111111111111111111101111111* -L011184 000000000000000000000000000000000000000000000000000000000000000000* -L011250 111110111111111111111110111111110111111111111111111111111111111111* -L011316 000000000000000000000000000000000000000000000000000000000000000000* +L011052 111111111111111111111111111111111111111111111111111111111111111111* +L011118 111111111111111111111111111111111111111111111111111111111111111111* +L011184 111111111111111111111111111111111111111111111111111111111111111111* +L011250 111111111111111111111111111111111111111111111111111111111111111111* +L011316 111111111111111111111111111111111111111111111111111111111111111111* L011382 111111111111111111111111111111111111111111111111111111111111111111* L011448 111111111111111111111111111111111111111111111111111111111111111111* L011514 111111111111111111111111111111111111111111111111111111111111111111* @@ -268,14 +268,14 @@ L011580 111111111111111111111111111111111111111111111111111111111111111111* L011646 111111111111111111111111111111111111111111111111111111111111111111* L011712 000000000000000000000000000000000000000000000000000000000000000000* -L011778 110111111111111111111111111110111111111111111111111111111111111111* -L011844 110111111111111111111111110111111111111111111111111111111111111111* -L011910 111111011111111111111111111001111111111111111111111111111111111111* +L011778 111111111111111111111111011011111111111111111111111111111111111111* +L011844 110111111111111111111111011111111111111111111111111111111111111111* +L011910 111011011111111111111111110111111111111111111111111111111111111111* L011976 000000000000000000000000000000000000000000000000000000000000000000* L012042 000000000000000000000000000000000000000000000000000000000000000000* -L012108 111111111111111111111111111101111111111111111111111111110111111111* -L012174 111111111111110111111111111101111111111111110111111111111111111111* -L012240 000000000000000000000000000000000000000000000000000000000000000000* +L012108 111111111111111111111111110111111111111111111111111111110111111111* +L012174 111111111111111111111111110111111111111111110111111111111111111111* +L012240 111111111111111111111111111111101111111111111011111111110111111111* L012306 000000000000000000000000000000000000000000000000000000000000000000* L012372 000000000000000000000000000000000000000000000000000000000000000000* L012438 @@ -296,20 +296,20 @@ L013164 L013296 0010* L013300 00101110000000* L013314 00101110001110* -L013328 10100100010100* +L013328 00011110100100* L013342 11100011111111* L013356 10100110010011* -L013370 00001110001111* -L013384 10101110000110* -L013398 11001111111111* +L013370 10100100011111* +L013384 11011011110110* +L013398 11110011111111* L013412 10100110011001* -L013426 10100100010011* -L013440 10101110000000* -L013454 11101011110010* -L013468 10100110011000* -L013482 10100110010011* -L013496 11011111111100* -L013510 11110011111110* +L013426 00001110000011* +L013440 11011111110000* +L013454 11110011110010* +L013468 10100110011001* +L013482 10100100010011* +L013496 11011011111100* +L013510 11111111111111* NOTE BLOCK 2 * L013524 111111111111111111111111111111111111111111111111111111111111111111 @@ -439,15 +439,15 @@ L020258 11110111110101* L020272 11111111111111* NOTE BLOCK 3 * L020286 - 111111111111111011111111111111111111111110111111111011110111111111 - 111111111111111110111111111110011111111111110111111111111110110111 - 111111111111111111111111111011111111101111111111111111111111111111 - 111111111111111111111111111111111111111111101111111111111111111111 - 111111111101111111111111111111111111111111111111111111111111111110 + 111111111011111011111111111111111111111111111111111011111111111111 + 101111111101111110111111111111111111111111110111111111111110110111 + 111111111111111111111011111111101111111111111110111111110111111111 + 111110111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111011111111111111111111111111110 110111111111101111111101111111111111111111111111111111111111111111 - 111111111111111111111111011111110110111111111111111111101111111111 - 111111111111111111100111111111111111111111111110011111111111111111 - 101101010111111111111111111111111111111011111111111111111111111111* + 111111111111111111111111011111110110111111111111111111111111111111 + 111111111111111111101111111001111111111110111111011111111111111111 + 111111011111111111111111111111111111111011101111111111011111111111* L020880 111111111111111111111111111111111111111111111111111111111111111111* L020946 111111111111111111111111101111111110111111111111111111111111111111* @@ -455,90 +455,90 @@ L021012 000000000000000000000000000000000000000000000000000000000000000000* L021078 000000000000000000000000000000000000000000000000000000000000000000* L021144 000000000000000000000000000000000000000000000000000000000000000000* L021210 000000000000000000000000000000000000000000000000000000000000000000* -L021276 111111110111111111011111111111101111111110111011111111111111111111* -L021342 111111111111111111011111111111101111111110111011111111110111111111* -L021408 111110111111111111111111111111111111111101111011111111111111111111* +L021276 111111110111111111111111111111111111111111111011111111101111111111* +L021342 111111111010110111011111111111111111111111111011111111111111111111* +L021408 111111111010111111011111110111111111111111111011111111111111111111* L021474 000000000000000000000000000000000000000000000000000000000000000000* L021540 000000000000000000000000000000000000000000000000000000000000000000* L021606 111111111111111111111111111111111111111111111111111111111111111111* -L021672 111111011111111011111111111111111111111111111111111111111111111111* +L021672 111111011111111111111111111111111111111111111111111111111111111111* L021738 111111111111111111111111111111111111111111111111111111111101111111* L021804 000000000000000000000000000000000000000000000000000000000000000000* -L021870 111111011111111111111111110111111111111111111111111111111111111111* -L021936 111111101111110111111111111011111111111111111111111111111111111111* -L022002 111111111111111111111111111111111111111111111111111111111111111111* -L022068 111111111111111111111111111111111111111111111111111111111111111111* -L022134 111111111111111111111111111111111111111111111111111111111111111111* -L022200 111111111111111111111111111111111111111111111111111111111111111111* -L022266 111111111111111111111111111111111111111111111111111111111111111111* +L021870 111001101111111111110111111111111111111111111111110111111111111111* +L021936 111011101111111111110111111111111111111111111111111011111111111110* +L022002 111010011111111111110111111111111111111111111111110111111111111110* +L022068 000000000000000000000000000000000000000000000000000000000000000000* +L022134 000000000000000000000000000000000000000000000000000000000000000000* +L022200 000000000000000000000000000000000000000000000000000000000000000000* +L022266 000000000000000000000000000000000000000000000000000000000000000000* L022332 - 111111111111111111111111111111111111111111111101111111111111111111* -L022398 011111110111111111111111111111011111111111111111111111111111111111* + 111111111111111111111111111111111111111101111111111111111111111111* +L022398 111111111111111111111111111111111111111111111111111111111111111111* L022464 111111111111111111111111111111111111111111111111111111111101111111* L022530 000000000000000000000000000000000000000000000000000000000000000000* -L022596 101111111111111111111011111111111111111111111111111111111111111111* -L022662 111111111011111111101011111111111111111111111111111111111111111111* -L022728 110111101111110111111111011111111111111111101111100111111111111111* -L022794 111011011111111011111111111111111111111111101111010111101111111111* -L022860 000000000000000000000000000000000000000000000000000000000000000000* +L022596 111111111111111111111111111111111111111111111111111111111111111111* +L022662 111111111111111111111111111111111111111111111111111111111111111111* +L022728 111111111101110111111111111111111111111111011111111111111111111111* +L022794 111111111111111111111111111110111111111111101111111111111111111111* +L022860 111111111111111011101111111110111111111111111111111111111111111111* L022926 000000000000000000000000000000000000000000000000000000000000000000* L022992 000000000000000000000000000000000000000000000000000000000000000000* L023058 - 111111111111111111111111111111111111111111111101111111111111111111* + 111111111111111111111111111111111111111101111111111111111111111111* L023124 000000000000000000000000000000000000000000000000000000000000000000* L023190 000000000000000000000000000000000000000000000000000000000000000000* -L023256 101111111111111111111111111111111111111111111111111111111111111111* -L023322 111111111111111111111111111111111111111111111111111111111111111111* -L023388 111111111111111111111111111111111111111111111111111111111111111111* -L023454 111111110110011101111111110111111111111011111111111111111111111110* -L023520 111111110110111101111111110110111111111011111111111111111111111110* -L023586 111111110110111101111111110111111111011011111111111111111111111110* -L023652 111111111101111111101111111111111011111111111111111111111111111111* +L023256 111111111111111111111111111111111111111111101111111111111111111111* +L023322 111110011111111111110111011111111111111111111111101011111111111101* +L023388 111110011111111111111011111111111111111111111111010111111111111010* +L023454 110111111111010101111111111111111111101011111110111111111111111111* +L023520 100111111111110101111111111111111111101011111110111111111111111111* +L023586 110111111111110101111111111111011111101011111110111111111111111111* +L023652 111111111111111111101111111111111011011111111111111111111111111111* L023718 111111111111111101101111111111111011110111111111111111111111111111* L023784 - 111111111111111111111111111111111111111111111101111111111111111111* -L023850 111111111111111101101111111011111011111111111111111111111111111111* -L023916 111111111111111101101111111111111011111111111111111111111111111101* -L023982 111111111011111101101111111111111011111111111111111111111111111111* -L024048 111111111110011110111111111111111111111111111111111111111111110111* -L024114 111111111110111110111111111110111111111111111111111111111111110111* -L024180 111111111110111110111111111111111111011111111111111111111111110111* -L024246 111111111111111110101111111111111011111111111111111111111111111011* + 111111111111111111111111111111111111111101111111111111111111111111* +L023850 111011111111111101101111111111111011111111111111111111111111111111* +L023916 111111111111111101101111111111111011111111111101111111111111111111* +L023982 111111111111111001101111111111111011111111111111111111111111111111* +L024048 111111111111011110111111111111111111101111111111111111110111111111* +L024114 101111111111111110111111111111111111101111111111111111110111111111* +L024180 111111111111111110111111111111011111101111111111111111110111111111* +L024246 111111111111111110101111111111111011111111111111111111111011111111* L024312 000000000000000000000000000000000000000000000000000000000000000000* L024378 000000000000000000000000000000000000000000000000000000000000000000* L024444 000000000000000000000000000000000000000000000000000000000000000000* L024510 - 111111111111111111111111111111111111111111111110111111111111111111* + 111111111111111111111111111111111111111110111111111111111111111111* L024576 111111111111111111101111101111111111111111111111111111111111111111* -L024642 111111110111111111111111110111111111111011111111111111111111111110* +L024642 110111111111110111111111111111111111111011111110111111111111111111* L024708 000000000000000000000000000000000000000000000000000000000000000000* L024774 000000000000000000000000000000000000000000000000000000000000000000* L024840 000000000000000000000000000000000000000000000000000000000000000000* -L024906 111111111111111111111111111111111111111111111111111111111111111111* -L024972 111111111111111111111111111111111111111111111111111111111111111111* -L025038 111111111111111111111111111111111111111111111111111111111111111111* -L025104 111111111111111111111111111111111111111111111111111111111111111111* -L025170 111111111111111111111111111111111111111111111111111111111111111111* +L024906 110111111111110101111111111111101111101011111110111111111111111111* +L024972 111111111111111111101110111111111111011111111111111111111111111111* +L025038 111111111111111101101110111111111111110111111111111111111111111111* +L025104 111011111111111101101110111111111111111111111111111111111111111111* +L025170 111111111111111101101110111111111111111111111101111111111111111111* L025236 111111111111111111111111111111111111111111111111111111111111111111* -L025302 111111110110111101111111110111111111101011111111111111111111111110* -L025368 111111111101111111101110111111111111111111111111111111111111111111* -L025434 111111111111111101101110111111111111110111111111111111111111111111* -L025500 111111111111111101101110111011111111111111111111111111111111111111* -L025566 111111111111111101101110111111111111111111111111111111111111111101* -L025632 111111111011111101101110111111111111111111111111111111111111111111* +L025302 111111111111111001101110111111111111111111111111111111111111111111* +L025368 111111111111111110111111111111101111101111111111111111110111111111* +L025434 111111111111111110101110111111111111111111111111111111111011111111* +L025500 000000000000000000000000000000000000000000000000000000000000000000* +L025566 000000000000000000000000000000000000000000000000000000000000000000* +L025632 111111111111111111110111111111111111111111111111111111111111111111* L025698 111111111111111111111111111111111111111111111111111111111101111111* L025764 000000000000000000000000000000000000000000000000000000000000000000* -L025830 111111111110111110111111111111111111101111111111111111111111110111* -L025896 111111111111111110101110111111111111111111111111111111111111111011* +L025830 000000000000000000000000000000000000000000000000000000000000000000* +L025896 000000000000000000000000000000000000000000000000000000000000000000* L025962 000000000000000000000000000000000000000000000000000000000000000000* -L026028 111011101111110111111111111011111111111111011111111111111111111111* -L026094 111111011111110111111111111011111111111111101111110111111111111111* -L026160 110111011111110111111111111011111111111111011111111011111111111111* -L026226 111011111111110111111111111011111111111111101111111011111111111111* -L026292 000000000000000000000000000000000000000000000000000000000000000000* +L026028 111111111111111111111111111111111111111111111111111111111111111111* +L026094 111111111111111111111111111111111111111111111111111111111111111111* +L026160 111111111111111111111111111111111111111111111111111111111111111111* +L026226 111111111111111111111111111111111111111111111111111111111111111111* +L026292 111111111111111111111111111111111111111111111111111111111111111111* L026358 111111111111111111111111111111111111111111111111111111111111111111* L026424 111111111111111111111111111111111111111111111111111111111111111111* L026490 111111111111111111111111111111111111111111111111111111111111111111* @@ -546,23 +546,23 @@ L026556 111111111111111111111111111111111111111111111111111111111111111111* L026622 111111111111111111111111111111111111111111111111111111111111111111* L026688 000000000000000000000000000000000000000000000000000000000000000000 - 101111111111111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111111111111111111101111111111111111111111* L026820 0010* L026824 01100110011010* L026838 11100110011110* -L026852 10101110000100* -L026866 11100011111111* -L026880 11101110001011* -L026894 10100111011111* -L026908 00011110100110* +L026852 00101110000100* +L026866 11110011111111* +L026880 11111110001011* +L026894 10110111011111* +L026908 00111100100110* L026922 11011111111111* L026936 11100110010001* L026950 11110110011111* L026964 11111011110110* -L026978 11111111110010* +L026978 11011111110010* L026992 11100110011010* -L027006 10111111001111* -L027020 11110011110000* +L027006 00111110001111* +L027020 11010011110000* L027034 11111011110010* NOTE BLOCK 4 * L027048 @@ -693,22 +693,22 @@ L033782 11110111110101* L033796 11111111111111* NOTE BLOCK 5 * L033810 + 111111011111111111111111111111111111111111111111111111111111111111 + 111111111011011111111011111111111111111111111111111111111111111111 + 111111111111111111111111111011111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 + 111111111110111111111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111111111111111111101111111111111111111111111111111111111 + 111111111111111111101111111111111111111111111111111111111111111111 + 101111111111111111111111111111111111111111111111111111111111111111* L034404 000000000000000000000000000000000000000000000000000000000000000000* -L034470 111111111111111111111111111111111111111111111111111111111111111111* -L034536 111111111111111111111111111111111111111111111111111111111111111111* -L034602 111111111111111111111111111111111111111111111111111111111111111111* -L034668 111111111111111111111111111111111111111111111111111111111111111111* -L034734 111111111111111111111111111111111111111111111111111111111111111111* +L034470 111111111110111111101111111111111111111111111111111111111111111111* +L034536 111111011111011111110111110110111111111111111111111111111111111111* +L034602 000000000000000000000000000000000000000000000000000000000000000000* +L034668 000000000000000000000000000000000000000000000000000000000000000000* +L034734 000000000000000000000000000000000000000000000000000000000000000000* L034800 111111111111111111111111111111111111111111111111111111111111111111* L034866 111111111111111111111111111111111111111111111111111111111111111111* L034932 111111111111111111111111111111111111111111111111111111111111111111* @@ -800,10 +800,10 @@ L040080 111111111111111111111111111111111111111111111111111111111111111111* L040146 111111111111111111111111111111111111111111111111111111111111111111* L040212 000000000000000000000000000000000000000000000000000000000000000000 - 000000000000000000000000000000000000000000000000000000000000000000* -L040344 0000* -L040348 11010011111110* -L040362 11110111111111* + 101111111111111111111111111111111111111111111111111111111111111111* +L040344 0010* +L040348 11100110011110* +L040362 11011011111110* L040376 11110011111111* L040390 11110111110011* L040404 11110011111110* @@ -820,34 +820,34 @@ L040544 11110111111111* L040558 11111111111111* NOTE BLOCK 6 * L040572 - 111111011111111111111111101110111111111111111111111111111111111111 - 111111111110011111111011111111111111111111101111111111111111111111 - 111111111111111111111111111011111111111111111110111111110111111111 + 111111011111111111101111111110111111111111111111111111111111111111 + 111111111010011111111111101111111111111111111111111111111111111111 + 111111111111111111111011111111111111111111111110111111110111111111 111110111111111111111111111111111111111111111011111111111111111011 - 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111111111111101011111111111111 110111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111011110111111111111111111111111110111111111111111 - 111111111011110111111111111111111111111011111111111111111111111111 - 101111111111111111111111111111110111111111111111111111111111111111* + 111111111111111111111111111111111111111111111111111111111111111111 + 111111111111110111111111111011111111111111111111111111111111111110 + 101111111111111111111111111111010111111011111111111111111111111111* L041166 111111111111111111111111111111111111111111111111111111111111111111* -L041232 111111111111111111111111111111111111111111111111111111110111111111* +L041232 111111111111111111111111111111011111111111111111111111111111111111* L041298 000000000000000000000000000000000000000000000000000000000000000000* L041364 000000000000000000000000000000000000000000000000000000000000000000* L041430 000000000000000000000000000000000000000000000000000000000000000000* L041496 000000000000000000000000000000000000000000000000000000000000000000* -L041562 111111111111111111111111110111111111111111111111111111111111111111* -L041628 000000000000000000000000000000000000000000000000000000000000000000* -L041694 000000000000000000000000000000000000000000000000000000000000000000* -L041760 000000000000000000000000000000000000000000000000000000000000000000* +L041562 111001111111111111100111111111111111111111111111101111111111111111* +L041628 111010111111111111010111111111110111111111111111111111111111111111* +L041694 111001111111111111010111111111111011111111111111011111111111111111* +L041760 111010111111111111110111111111111011111111111111101111111111111111* L041826 000000000000000000000000000000000000000000000000000000000000000000* L041892 111111111111111111111111111111111111111111111111111111111111111111* -L041958 111111111111011111111111111101111111111111111111111111111111111111* -L042024 111111111111111111111111111111111111111111011111111111111111111111* +L041958 110111111111111111111111111101111111111011111110111111111111111111* +L042024 111111110111111111111111111111111111111111111111111111111111111111* L042090 101111111111111111111111111111111111111111111111111111111111111111* -L042156 111111111101111111111111111111111111111111111101111111111111110111* -L042222 111111111111111111111111111101111111111111111111111111111111110111* +L042156 111111111111111111110111111111111111111111111111111111111111110111* +L042222 000000000000000000000000000000000000000000000000000000000000000000* L042288 111111111111111111111111111111111111111111111111111111111111111111* L042354 111111111111111111111111111111111111111111111111111111111111111111* L042420 111111111111111111111111111111111111111111111111111111111111111111* @@ -855,23 +855,23 @@ L042486 111111111111111111111111111111111111111111111111111111111111111111* L042552 111111111111111111111111111111111111111111111111111111111111111111* L042618 000000000000000000000000000000000000000000000000000000000000000000* -L042684 110101111111111111111111011001110111111111111111111111111111111111* -L042750 110110111111111111111111101001110111111111111111111111111111111111* -L042816 111010111111111111111111101001111011111111111111111111111111111111* +L042684 111001111111111111010111111111110111111111111111011111111111111111* +L042750 111010111111111111010111111111111011111111111111011111111111111111* +L042816 111010111111111111100111111111111011111111111111101111111111111111* L042882 000000000000000000000000000000000000000000000000000000000000000000* L042948 000000000000000000000000000000000000000000000000000000000000000000* -L043014 111111110111111111111111111110111111111111111111111111110111111111* -L043080 111111111111111111111111111111111111111111011111111111111111111111* +L043014 111111111111111111111011011111111111111111111111111011111111111111* +L043080 111111110111111111111111111111111111111111111111111111111111111111* L043146 101111111111111111111111111111111111111111111111111111111111111111* -L043212 111111111111111111111111111111111111111111110111111011111111111111* -L043278 111111111111111111111111111110111111111111110111111111111111111111* +L043212 111111111110111111111011011111111111111111111111111111111111111111* +L043278 111111111111111111111011111111111111111111110111111111111111111111* L043344 000000000000000000000000000000000000000000000000000000000000000000* -L043410 111111111111111111111111111111111111111011111110111111111111111111* -L043476 111111111111111111111111111111111111111111011111111111111111111111* -L043542 101111111111111111111111111111111111111111111111111111111111111111* -L043608 111001011111111011111110011101111011111111111111111111111111110111* -L043674 000000000000000000000000000000000000000000000000000000000000000000* +L043410 110111111111111111111111111111111111111111111111111111111111111111* +L043476 111111111111111111111111111111111111111111111111111111111111111111* +L043542 111111111111111111111111111111111111111111111111111111111111111111* +L043608 111111111111111111111111111111111111111111111111111111111111111111* +L043674 111111111111111111111111111111111111111111111111111111111111111111* L043740 111111111111111111111111111111111111111111111111111111111111111111* L043806 111111111111111111111111111111111111111111111111111111111111111111* L043872 111111111111111111111111111111111111111111111111111111111111111111* @@ -879,22 +879,22 @@ L043938 111111111111111111111111111111111111111111111111111111111111111111* L044004 111111111111111111111111111111111111111111111111111111111111111111* L044070 000000000000000000000000000000000000000000000000000000000000000000* -L044136 111111111111111111111111111101111111111111111111111111111111111111* +L044136 111111011111111111111111111111111111111111111111111111111111111111* L044202 111111111111111111111111111111111111111111111111111111111111111111* L044268 111111111111111111111111111111111111111111111111111111111111111111* L044334 111111111111111111111111111111111111111111111111111111111111111111* L044400 111111111111111111111111111111111111111111111111111111111111111111* -L044466 111111111110111111111111111110111111111111111111111111111111110111* -L044532 111111111111111111111111111111111111111111011111111111111111111111* +L044466 111111111111111111110111111111111111111111111111111111110111111111* +L044532 111111110111111111111111111111111111111111111111111111111111111111* L044598 101111111111111111111111111111111111111111111111111111111111111111* -L044664 111111111111111111111111111110111111111111111110111111111111110111* -L044730 111111111111111111110111111110111111111111111111111111111111111111* +L044664 111111111101111111111111011111111111111111111111110111111111111111* +L044730 111111111111111111110111011111111111111111111111111111111111111111* L044796 000000000000000000000000000000000000000000000000000000000000000000* -L044862 111111111110111111111111111111111111111011111111111111111111111111* -L044928 111111111111111111111111111111111111111111011111111111111111111111* +L044862 111111111110111111111111111111111111111111111111111111111111111110* +L044928 111111110111111111111111111111111111111111111111111111111111111111* L044994 101111111111111111111111111111111111111111111111111111111111111111* -L045060 111111011111111111101101111101111111111111111111111111111111110111* +L045060 111101011111101011100111011111110111111111111111101111111111111111* L045126 000000000000000000000000000000000000000000000000000000000000000000* L045192 111111111111111111111111111111111111111111111111111111111111111111* L045258 111111111111111111111111111111111111111111111111111111111111111111* @@ -903,23 +903,23 @@ L045390 111111111111111111111111111111111111111111111111111111111111111111* L045456 111111111111111111111111111111111111111111111111111111111111111111* L045522 000000000000000000000000000000000000000000000000000000000000000000* -L045588 111111011111111111111111111111111111111111111111111111111111111111* -L045654 111111111111111111111111111111111111111111111111111111111111111111* -L045720 111111111111111111111111111111111111111111111111111111111111111111* -L045786 111111111111111111111111111111111111111111111111111111111111111111* -L045852 111111111111111111111111111111111111111111111111111111111111111111* -L045918 111111111111111111111111011111111111111111111111111111111111111111* -L045984 111101111111111111111111101001110111111111111111111111111111111111* -L046050 111011111111111111111111101001111011111111111111111111111111111111* -L046116 111010111111111111111111011001110111111111111111111111111111111111* +L045588 111111111111111111111111111101111111110111111111111111111111111111* +L045654 111111110111111111111111111111111111111111111111111111111111111111* +L045720 101111111111111111111111111111111111111111111111111111111111111111* +L045786 111011111111111111111111111101111111111111111111111111111111111111* +L045852 111111111111111111111111111101111111111111111101111111111111111111* +L045918 111111111111111111011011111111111111111111111111111111111111111111* +L045984 110111111111111111011111111111111111111111111111111111111111111111* +L046050 111011111111111111100111111111111111111111111111111111111111111111* +L046116 000000000000000000000000000000000000000000000000000000000000000000* L046182 000000000000000000000000000000000000000000000000000000000000000000* L046248 000000000000000000000000000000000000000000000000000000000000000000* -L046314 111111111111111111111111111111111111111111111111111111111111111111* -L046380 111111111111111111111111111111111111111111111111111111111111111111* -L046446 111111111111111111111111111111111111111111111111111111111111111111* -L046512 111111111111111111111111111111111111111111111111111111111111111111* -L046578 111111111111111111111111111111111111111111111111111111111111111111* +L046314 111111111111111111111011110111111111111111111111111111111111111111* +L046380 000000000000000000000000000000000000000000000000000000000000000000* +L046446 000000000000000000000000000000000000000000000000000000000000000000* +L046512 000000000000000000000000000000000000000000000000000000000000000000* +L046578 000000000000000000000000000000000000000000000000000000000000000000* L046644 111111111111111111111111111111111111111111111111111111111111111111* L046710 111111111111111111111111111111111111111111111111111111111111111111* L046776 111111111111111111111111111111111111111111111111111111111111111111* @@ -930,42 +930,42 @@ L046974 000000000000000000000000000000000000000000000000000000000000000000* L047106 0010* L047110 00100110010000* -L047124 00100110011110* +L047124 10100111011110* L047138 10101110000100* L047152 11100011111111* L047166 10100111011001* L047180 10101110000011* -L047194 11101100000000* +L047194 00010110010000* L047208 11101111110011* L047222 00110110010001* L047236 10101110000011* L047250 11101100000000* L047264 11101011110010* -L047278 00110110010000* -L047292 00100110010011* -L047306 11011111110000* +L047278 10101110000000* +L047292 10100110010011* +L047306 11001111110000* L047320 11110011111110* NOTE BLOCK 7 * L047334 - 111111111111111011111111111111111111111110111111111111111111111111 - 111111111101111111111111111111111111111111101111111111101111111111 - 111111111111101111111011111111111111111111111111111111110111111111 + 111111111111111111110111111111111111111110111111111111111111111111 + 111111111101111111111111111111111111111111111111111111111111111111 + 111111111111101111111111111111111111111111111111111111111011111111 111011111111111110111111111111111111111111111111111111111111111111 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111011111111111011111111111111111111111111111 - 111111101111111111111101111111111101111111111111111111111111111111 - 111111111011111111101111111111111111111111111110111111111111111111 - 101111111111111111111111110111111111111011111111111111111111101111* + 111111110111111111111111011111111111111111011111111111111111111111 + 111111101111110111111101111111111101111111111111111111101111111111 + 111111111111111111101111111011111111111111111110111111111111111111 + 101111111111111111111111111111011111111011111111111111111111101111* L047928 000000000000000000000000000000000000000000000000000000000000000000* -L047994 110111111111011101101110101111111110011101111111111111111111111111* +L047994 110111110111011101101110101111111110111101111111111111111111111111* L048060 111111111111111111101111111111111111111110111111111111111111101111* L048126 000000000000000000000000000000000000000000000000000000000000000000* L048192 000000000000000000000000000000000000000000000000000000000000000000* L048258 000000000000000000000000000000000000000000000000000000000000000000* L048324 111111111111111111011111111111111111111111111111111111111111111111* L048390 111111111110111111111111111111111111111101111111111111111111111111* -L048456 110111111111011101111110101111111110011101111111111111111111111111* +L048456 110111110111011101111110101111111110111101111111111111111111111111* L048522 111111111111111111111111111111111111110110111111111111111111111111* L048588 000000000000000000000000000000000000000000000000000000000000000000* L048654 @@ -982,14 +982,14 @@ L049248 111111111111111111111111111111111111111111111111111111111111111111* L049314 111111111111111111111111111111111111111111111111111111111111111111* L049380 111111111111111111111111111111111111111111111111111111111111111111* -L049446 111111111111111111111111111111111111011111111101111111111111111111* -L049512 111111111111110111111011111111111111011111111111111111111111111111* +L049446 111111110111111111111111111111111111111111111101111111111111111111* +L049512 111111110111111111111111111111111111111111101111111111110111111111* L049578 000000000000000000000000000000000000000000000000000000000000000000* L049644 000000000000000000000000000000000000000000000000000000000000000000* L049710 000000000000000000000000000000000000000000000000000000000000000000* -L049776 111111110111110111111111111111111111111111111111111111111111111111* -L049842 111111111111110111111111111111111111111111111111111111011111111111* -L049908 111111110111111111111111111111111111111111111111111111101011111111* +L049776 111111111111111111111111110111111111111111111111111111110111111111* +L049842 111111111111110111111111111111111111111111111111111111010111111111* +L049908 000000000000000000000000000000000000000000000000000000000000000000* L049974 000000000000000000000000000000000000000000000000000000000000000000* L050040 000000000000000000000000000000000000000000000000000000000000000000* L050106 @@ -1007,15 +1007,15 @@ L050766 111111111111111111111111111111111111111111111111111111111111111111* L050832 111111111101111111111111111111111111111111111111111111111111111111* L050898 111111101111111111101111111111111111111111111111111111111111111111* -L050964 111111110111111011111111111111111111111111111111111111110111111111* +L050964 111111111111111111110111111111011111111111111111111111111011111111* L051030 000000000000000000000000000000000000000000000000000000000000000000* L051096 000000000000000000000000000000000000000000000000000000000000000000* L051162 000000000000000000000000000000000000000000000000000000000000000000* -L051228 111111111111111111111111110111111111111111111111111111111111111111* -L051294 111111111111111111111111111111111111111111011111111111111111111111* -L051360 000000000000000000000000000000000000000000000000000000000000000000* -L051426 111111111111111111111111111111111111111111111111111111111111111111* -L051492 111111111111111111111111111111111111111111111111111111111111111111* +L051228 111111111111111111110111111111011111111111111111111111111011111111* +L051294 111111111111111011111111111111111111111111111111111111011111111111* +L051360 111111111111111111111111111111111111111111111111111111011011111111* +L051426 000000000000000000000000000000000000000000000000000000000000000000* +L051492 000000000000000000000000000000000000000000000000000000000000000000* L051558 111111111101111111111111111111111111111111111111111111111111111111* L051624 111111111111111111111111111111111111111111111111111111111111111111* @@ -1061,17 +1061,17 @@ L053886 10100110010010* L053900 11011111110000* L053914 11111011110011* L053928 10100110010000* -L053942 10100100011110* +L053942 10100110011110* L053956 11011111110001* L053970 11111011110011* L053984 11100110010000* -L053998 00001110000010* +L053998 10100100010010* L054012 11010011110100* L054026 11111011111111* L054040 00111111111000* L054054 11000011110010* L054068 11111011110101* -L054082 11110111111111* +L054082 11111111111111* E1 0 00000000 @@ -1091,6 +1091,6 @@ E1 00000000 1 * -C9018* +C52A9* U00000000000000000000000000000000* -B9C5 +BBAB diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index ca16c3f..3f381a2 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; -DATE = 5/18/14; -TIME = 21:01:51; +DATE = 5/22/14; +TIME = 14:56:14; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -82,33 +82,33 @@ IPL_2_ = pin,68,-,G,-; FC_1_ = pin,58,-,F,-; AS_030 = pin,82,-,H,-; DS_030 = pin,98,-,A,-; -SIZE_0_ = pin,70,-,G,-; -A_30_ = pin,5,-,B,-; nEXP_SPACE = pin,14,-,-,-; -A_29_ = pin,6,-,B,-; BERR = pin,41,-,E,-; -A_28_ = pin,15,-,C,-; +SIZE_0_ = pin,70,-,G,-; BG_030 = pin,21,-,C,-; -A_27_ = pin,16,-,C,-; -A_26_ = pin,17,-,C,-; -A_25_ = pin,18,-,C,-; +A_30_ = pin,5,-,B,-; +A_29_ = pin,6,-,B,-; +A_28_ = pin,15,-,C,-; BGACK_000 = pin,28,-,D,-; -A_24_ = pin,19,-,C,-; +A_27_ = pin,16,-,C,-; CLK_030 = pin,64,-,-,-; -A_23_ = pin,84,-,H,-; +A_26_ = pin,17,-,C,-; CLK_000 = pin,11,-,-,-; -A_22_ = pin,85,-,H,-; +A_25_ = pin,18,-,C,-; CLK_OSZI = pin,61,-,-,-; -A_21_ = pin,94,-,A,-; +A_24_ = pin,19,-,C,-; CLK_DIV_OUT = pin,65,-,G,-; +A_23_ = pin,84,-,H,-; +A_22_ = pin,85,-,H,-; +A_21_ = pin,94,-,A,-; A_20_ = pin,93,-,A,-; +AVEC = pin,92,-,A,-; A_19_ = pin,97,-,A,-; +AVEC_EXP = pin,22,-,C,-; A_18_ = pin,95,-,A,-; A_17_ = pin,59,-,F,-; -AVEC = pin,92,-,A,-; -A_16_ = pin,96,-,A,-; -AVEC_EXP = pin,22,-,C,-; VPA = pin,36,-,-,-; +A_16_ = pin,96,-,A,-; RST = pin,86,-,-,-; RW = pin,71,-,G,-; AMIGA_BUS_DATA_DIR = pin,48,-,E,-; @@ -135,28 +135,29 @@ RESET = pin,3,-,B,-; AMIGA_BUS_ENABLE = pin,34,-,D,-; IPL_030_1_ = pin,7,-,B,-; IPL_030_0_ = pin,8,-,B,-; -cpu_est_0_ = node,-,-,D,2; -cpu_est_1_ = node,-,-,D,13; +cpu_est_0_ = node,-,-,G,13; +cpu_est_1_ = node,-,-,G,1; inst_AS_030_000_SYNC = node,-,-,H,1; -inst_DTACK_SYNC = node,-,-,G,10; -inst_VPA_D = node,-,-,H,9; -inst_VPA_SYNC = node,-,-,G,6; -inst_CLK_000_D0 = node,-,-,G,12; -inst_CLK_000_D1 = node,-,-,G,8; -inst_CLK_000_D2 = node,-,-,G,1; -inst_CLK_OUT_PRE = node,-,-,B,5; -SM_AMIGA_6_ = node,-,-,A,0; -cpu_est_2_ = node,-,-,G,13; -CLK_REF_1_ = node,-,-,D,6; -SM_AMIGA_7_ = node,-,-,B,13; -SM_AMIGA_4_ = node,-,-,B,9; -SM_AMIGA_1_ = node,-,-,H,5; -CLK_CNT_0_ = node,-,-,B,10; -CLK_CNT_1_ = node,-,-,B,6; -SM_AMIGA_3_ = node,-,-,G,2; -SM_AMIGA_5_ = node,-,-,B,2; -SM_AMIGA_2_ = node,-,-,G,9; -SM_AMIGA_0_ = node,-,-,G,5; +inst_DTACK_SYNC = node,-,-,F,0; +inst_VPA_D = node,-,-,B,9; +inst_VPA_SYNC = node,-,-,G,10; +inst_CLK_000_D0 = node,-,-,G,8; +inst_CLK_000_D1 = node,-,-,D,13; +inst_CLK_000_D2 = node,-,-,G,6; +inst_CLK_OUT_PRE = node,-,-,A,0; +SM_AMIGA_6_ = node,-,-,G,12; +cpu_est_2_ = node,-,-,D,2; +CLK_REF_0_ = node,-,-,D,6; +CLK_REF_1_ = node,-,-,B,2; +SM_AMIGA_7_ = node,-,-,H,5; +SM_AMIGA_4_ = node,-,-,B,5; +SM_AMIGA_1_ = node,-,-,B,13; +CLK_CNT_0_ = node,-,-,A,12; +CLK_CNT_1_ = node,-,-,A,8; +SM_AMIGA_3_ = node,-,-,G,9; +SM_AMIGA_5_ = node,-,-,G,2; +SM_AMIGA_2_ = node,-,-,G,5; +SM_AMIGA_0_ = node,-,-,H,9; [GROUP ASSIGNMENTS] Layer = OFF; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index 220684f..55004bf 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -55563,4 +55563,1817 @@ 5 A_29_ 1 -1 -1 1 4 5 -1 4 A_30_ 1 -1 -1 1 4 4 -1 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +94 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 320 3 0 30 -1 12 0 21 + 31 UDS_000 5 319 3 0 31 -1 8 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 321 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 322 7 0 82 -1 2 0 21 + 77 FPU_CS 5 323 7 0 77 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 318 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 3 4 0 1 3 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 3 0 3 7 -1 -1 4 0 21 + 309 SM_AMIGA_1_ 3 -1 6 3 1 6 7 -1 -1 3 0 20 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 1 3 1 3 6 -1 -1 3 0 20 + 323 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 304 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 318 RN_AS_000 3 32 3 2 1 3 32 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 0 2 0 6 -1 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 307 SM_AMIGA_7_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 3 2 0 3 -1 -1 1 0 20 + 298 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21 + 320 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 319 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 315 SM_AMIGA_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 314 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 306 CLK_REF_1_ 3 -1 7 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 10 CLK_000 1 -1 -1 3 1 6 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +98 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 12 0 21 + 31 UDS_000 5 323 3 0 31 -1 8 0 21 + 65 E 5 328 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 330 3 0 33 -1 3 0 20 + 28 BG_000 5 325 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 332 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 331 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 0 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20 + 297 inst_AS_030_000_SYNC 3 -1 7 3 1 3 7 -1 -1 4 0 21 + 313 SM_AMIGA_1_ 3 -1 6 3 1 6 7 -1 -1 3 0 20 + 304 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 302 inst_CLK_000_D1 3 -1 3 3 1 3 7 -1 -1 1 0 20 + 299 inst_VPA_D 3 -1 1 3 0 3 6 -1 -1 1 0 20 + 305 SM_AMIGA_6_ 3 -1 3 2 1 3 -1 -1 4 0 21 + 316 SM_AMIGA_3_ 3 -1 6 2 0 6 -1 -1 3 0 20 + 309 cpu_est_2_ 3 -1 6 2 6 7 -1 -1 3 1 21 + 307 cpu_est_0_ 3 -1 7 2 6 7 -1 -1 3 0 20 + 329 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 326 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 322 RN_AS_000 3 32 3 2 1 3 32 -1 2 0 21 + 317 SM_AMIGA_5_ 3 -1 1 2 1 6 -1 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 311 SM_AMIGA_7_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 300 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 306 cpu_est_d_2_ 3 -1 7 2 0 3 -1 -1 1 0 20 + 303 inst_CLK_000_D2 3 -1 3 2 1 3 -1 -1 1 0 20 + 296 cpu_est_d_3_ 3 -1 6 2 0 3 -1 -1 1 0 21 + 295 cpu_est_d_1_ 3 -1 6 2 0 3 -1 -1 1 0 21 + 294 cpu_est_d_0_ 3 -1 7 2 0 3 -1 -1 1 0 20 + 324 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 308 cpu_est_1_ 3 -1 6 1 6 -1 -1 4 0 21 + 332 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 331 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 328 RN_E 3 65 6 1 6 65 -1 3 0 21 + 325 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 SM_AMIGA_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 318 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 315 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 314 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 298 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 310 CLK_REF_1_ 3 -1 7 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 6 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 6 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +98 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 12 0 21 + 31 UDS_000 5 323 3 0 31 -1 8 0 21 + 65 E 5 328 6 0 65 -1 4 0 21 + 33 AMIGA_BUS_ENABLE 5 330 3 0 33 -1 3 0 20 + 28 BG_000 5 325 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 332 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 331 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 0 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D0 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 20 + 302 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 297 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 304 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 299 inst_VPA_D 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 328 RN_E 3 65 6 2 6 7 65 -1 4 0 21 + 307 cpu_est_1_ 3 -1 7 2 6 7 -1 -1 4 0 20 + 305 SM_AMIGA_6_ 3 -1 6 2 3 6 -1 -1 4 0 20 + 318 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 316 SM_AMIGA_3_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 312 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 308 cpu_est_2_ 3 -1 7 2 6 7 -1 -1 3 0 20 + 329 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 326 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 322 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21 + 317 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 2 0 20 + 311 SM_AMIGA_4_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 310 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 300 inst_VPA_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21 + 313 cpu_est_d0_2_ 3 -1 6 2 0 3 -1 -1 1 0 21 + 306 cpu_est_0_ 3 -1 7 2 6 7 -1 -1 1 0 20 + 303 inst_CLK_000_D2 3 -1 3 2 3 6 -1 -1 1 0 20 + 296 cpu_est_d0_3_ 3 -1 7 2 0 3 -1 -1 1 0 20 + 295 cpu_est_d0_1_ 3 -1 7 2 0 3 -1 -1 1 0 20 + 294 cpu_est_d0_0_ 3 -1 7 2 0 3 -1 -1 1 0 20 + 324 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 332 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 331 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 325 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 3 0 20 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 315 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 314 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 298 inst_DTACK_SYNC 3 -1 1 1 1 -1 -1 2 0 21 + 309 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 1 3 6 7 60 -1 + 10 CLK_000 9 -1 2 0 1 10 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +98 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 12 0 21 + 31 UDS_000 5 323 3 0 31 -1 8 0 21 + 65 E 5 328 6 0 65 -1 4 0 21 + 33 AMIGA_BUS_ENABLE 5 330 3 0 33 -1 3 0 20 + 28 BG_000 5 325 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 332 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 331 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 0 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20 + 302 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 297 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 316 SM_AMIGA_3_ 3 -1 1 3 0 1 6 -1 -1 3 0 21 + 313 cpu_est_d0_2_ 3 -1 7 3 0 3 7 -1 -1 3 0 20 + 304 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 296 cpu_est_d0_3_ 3 -1 1 3 0 1 3 -1 -1 3 0 20 + 295 cpu_est_d0_1_ 3 -1 1 3 0 1 3 -1 -1 3 0 20 + 294 cpu_est_d0_0_ 3 -1 7 3 0 3 7 -1 -1 3 0 20 + 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 299 inst_VPA_D 3 -1 7 3 0 3 6 -1 -1 1 0 20 + 328 RN_E 3 65 6 2 1 6 65 -1 4 0 21 + 307 cpu_est_1_ 3 -1 6 2 1 6 -1 -1 4 0 21 + 305 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 318 SM_AMIGA_2_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 312 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 + 308 cpu_est_2_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 329 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 326 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 322 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21 + 317 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 2 0 20 + 311 SM_AMIGA_4_ 3 -1 1 2 1 3 -1 -1 2 0 21 + 310 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 300 inst_VPA_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21 + 298 inst_DTACK_SYNC 3 -1 6 2 1 6 -1 -1 2 0 20 + 306 cpu_est_0_ 3 -1 7 2 6 7 -1 -1 1 0 20 + 303 inst_CLK_000_D2 3 -1 3 2 3 6 -1 -1 1 0 20 + 324 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 332 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 331 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 325 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 3 0 20 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 315 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 314 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 309 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 1 3 6 7 60 -1 + 10 CLK_000 9 -1 3 0 6 7 10 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +98 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 321 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 1 29 -1 1 0 21 + 30 LDS_000 5 324 3 0 30 -1 12 0 21 + 31 UDS_000 5 323 3 0 31 -1 8 0 21 + 65 E 5 328 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 330 3 0 33 -1 3 0 20 + 28 BG_000 5 325 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 320 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 332 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 331 1 0 6 -1 3 0 21 + 82 BGACK_030 5 326 7 0 82 -1 2 0 21 + 77 FPU_CS 5 327 7 0 77 -1 2 0 21 + 34 VMA 5 329 3 0 34 -1 2 0 21 + 32 AS_000 5 322 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20 + 302 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 308 cpu_est_1_ 3 -1 7 3 1 6 7 -1 -1 4 0 20 + 297 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 316 SM_AMIGA_3_ 3 -1 6 3 0 1 6 -1 -1 3 0 20 + 304 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 3 1 21 + 327 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 299 inst_VPA_D 3 -1 1 3 0 1 3 -1 -1 1 0 20 + 305 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 4 0 21 + 328 RN_E 3 65 6 2 6 7 65 -1 3 0 21 + 313 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 309 cpu_est_2_ 3 -1 7 2 6 7 -1 -1 3 1 20 + 307 cpu_est_0_ 3 -1 7 2 6 7 -1 -1 3 0 20 + 329 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21 + 326 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 322 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21 + 312 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 311 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20 + 300 inst_VPA_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21 + 298 inst_DTACK_SYNC 3 -1 1 2 1 6 -1 -1 2 0 21 + 306 cpu_est_d0_2_ 3 -1 6 2 0 3 -1 -1 1 0 21 + 303 inst_CLK_000_D2 3 -1 7 2 3 6 -1 -1 1 0 20 + 296 cpu_est_d0_3_ 3 -1 6 2 0 3 -1 -1 1 0 21 + 295 cpu_est_d0_1_ 3 -1 1 2 0 3 -1 -1 1 0 20 + 294 cpu_est_d0_0_ 3 -1 7 2 0 3 -1 -1 1 0 20 + 324 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 323 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 332 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 331 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 330 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 325 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 320 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 319 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 3 0 20 + 318 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 321 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 317 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20 + 315 CLK_CNT_1_ 3 -1 6 1 6 -1 -1 2 0 21 + 314 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 310 CLK_REF_1_ 3 -1 3 1 6 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 4 0 1 3 7 81 -1 + 10 CLK_000 1 -1 -1 3 0 1 7 10 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +94 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 320 3 0 30 -1 12 0 21 + 31 UDS_000 5 319 3 0 31 -1 8 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 321 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 322 7 0 82 -1 2 0 21 + 77 FPU_CS 5 323 7 0 77 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 318 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 1 3 7 -1 -1 4 0 21 + 304 SM_AMIGA_6_ 3 -1 0 3 0 1 3 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 323 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 318 RN_AS_000 3 32 3 3 1 3 6 32 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 315 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 309 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20 + 320 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 319 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 306 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 327 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 328 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 5 1 3 5 6 7 -1 -1 1 0 21 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 303 inst_CLK_OUT_PRE 3 -1 0 3 1 6 7 -1 -1 4 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 308 SM_AMIGA_7_ 3 -1 7 3 3 6 7 -1 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 3 5 6 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 6 2 3 6 -1 -1 4 0 20 + 295 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 315 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 313 SM_AMIGA_3_ 3 -1 6 2 5 6 -1 -1 3 0 20 + 310 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 + 326 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 319 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 312 CLK_CNT_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21 + 311 CLK_CNT_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 307 CLK_REF_1_ 3 -1 1 1 0 -1 -1 1 0 20 + 306 CLK_REF_0_ 3 -1 3 1 0 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 1 3 5 6 60 -1 + 85 RST 1 -1 -1 5 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 3 5 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 10 CLK_000 1 -1 -1 2 5 6 10 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +94 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 320 3 0 30 -1 12 0 21 + 31 UDS_000 5 319 3 0 31 -1 8 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 321 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 322 7 0 82 -1 2 0 21 + 77 FPU_CS 5 323 7 0 77 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 318 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 1 3 7 -1 -1 4 0 21 + 304 SM_AMIGA_6_ 3 -1 0 3 0 1 3 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 323 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 318 RN_AS_000 3 32 3 3 1 3 6 32 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 315 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 309 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20 + 320 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 319 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 306 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +93 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 320 3 0 30 -1 12 0 21 + 31 UDS_000 5 319 3 0 31 -1 8 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 321 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 322 7 0 82 -1 2 0 21 + 77 FPU_CS 5 323 7 0 77 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 318 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 1 3 7 -1 -1 4 0 21 + 304 SM_AMIGA_6_ 3 -1 0 3 0 1 3 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 318 RN_AS_000 3 32 3 3 1 3 6 32 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 315 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 309 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 323 RN_FPU_CS 3 77 7 2 2 7 77 -1 2 0 21 + 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20 + 320 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 319 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 306 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +94 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 320 3 0 30 -1 12 0 21 + 31 UDS_000 5 319 3 0 31 -1 8 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 321 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 322 7 0 82 -1 2 0 21 + 77 FPU_CS 5 323 7 0 77 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 318 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 1 3 7 -1 -1 4 0 21 + 304 SM_AMIGA_6_ 3 -1 0 3 0 1 3 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 323 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 318 RN_AS_000 3 32 3 3 1 3 6 32 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 315 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 309 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20 + 320 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 319 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 306 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +93 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 320 3 0 30 -1 12 0 21 + 31 UDS_000 5 319 3 0 31 -1 8 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 321 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 322 7 0 82 -1 2 0 21 + 77 FPU_CS 5 323 7 0 77 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 318 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 1 3 7 -1 -1 4 0 21 + 304 SM_AMIGA_6_ 3 -1 0 3 0 1 3 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 318 RN_AS_000 3 32 3 3 1 3 6 32 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 315 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 309 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 323 RN_FPU_CS 3 77 7 2 2 7 77 -1 2 0 21 + 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20 + 320 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 319 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 306 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +93 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 1 5 0 1 3 6 7 -1 -1 1 0 20 + 296 inst_AS_030_000_SYNC 3 -1 7 4 1 3 6 7 -1 -1 4 0 21 + 301 inst_CLK_000_D1 3 -1 6 4 1 3 6 7 -1 -1 1 0 21 + 304 SM_AMIGA_6_ 3 -1 6 3 1 3 6 -1 -1 4 0 20 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 309 SM_AMIGA_4_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 308 SM_AMIGA_7_ 3 -1 7 3 3 6 7 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 3 1 3 6 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 313 SM_AMIGA_3_ 3 -1 0 2 0 6 -1 -1 3 0 21 + 310 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 306 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 319 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 305 inst_FPU_CS_INT 3 -1 7 2 2 7 -1 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 6 2 0 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 2 0 6 -1 -1 2 0 20 + 298 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21 + 315 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 312 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 311 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 307 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 0 1 3 6 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 10 CLK_000 1 -1 -1 2 1 6 10 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +93 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 320 3 0 30 -1 12 0 21 + 31 UDS_000 5 319 3 0 31 -1 8 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 321 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 322 7 0 82 -1 2 0 21 + 77 FPU_CS 5 323 7 0 77 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 318 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 1 3 7 -1 -1 4 0 21 + 304 SM_AMIGA_6_ 3 -1 0 3 0 1 3 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 318 RN_AS_000 3 32 3 3 1 3 6 32 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 315 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 309 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 323 RN_FPU_CS 3 77 7 2 2 7 77 -1 2 0 21 + 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20 + 320 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 319 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 306 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +94 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 320 3 0 30 -1 12 0 21 + 31 UDS_000 5 319 3 0 31 -1 8 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 321 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 322 7 0 82 -1 2 0 21 + 77 FPU_CS 5 323 7 0 77 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 318 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 1 3 7 -1 -1 4 0 21 + 304 SM_AMIGA_6_ 3 -1 0 3 0 1 3 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 323 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 318 RN_AS_000 3 32 3 3 1 3 6 32 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 315 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 309 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20 + 320 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 319 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 306 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +94 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 320 3 0 30 -1 12 0 21 + 31 UDS_000 5 319 3 0 31 -1 8 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 321 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 322 7 0 82 -1 2 0 21 + 77 FPU_CS 5 323 7 0 77 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 318 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 1 3 7 -1 -1 4 0 21 + 304 SM_AMIGA_6_ 3 -1 0 3 0 1 3 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 323 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 318 RN_AS_000 3 32 3 3 1 3 6 32 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 315 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 309 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20 + 320 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 319 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 306 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +93 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 320 3 0 30 -1 12 0 21 + 31 UDS_000 5 319 3 0 31 -1 8 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 321 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 322 7 0 82 -1 2 0 21 + 77 FPU_CS 5 323 7 0 77 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 318 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 1 3 7 -1 -1 4 0 21 + 304 SM_AMIGA_6_ 3 -1 0 3 0 1 3 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 318 RN_AS_000 3 32 3 3 1 3 6 32 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 315 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 309 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 323 RN_FPU_CS 3 77 7 2 2 7 77 -1 2 0 21 + 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20 + 320 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 319 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 306 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +94 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 6 29 -1 1 0 21 + 30 LDS_000 5 320 3 0 30 -1 12 0 21 + 31 UDS_000 5 319 3 0 31 -1 8 0 21 + 65 E 5 324 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 326 3 0 33 -1 3 0 20 + 28 BG_000 5 321 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 328 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 327 1 0 6 -1 3 0 21 + 82 BGACK_030 5 322 7 0 82 -1 2 0 21 + 77 FPU_CS 5 323 7 0 77 -1 2 0 21 + 34 VMA 5 325 3 0 34 -1 2 0 21 + 32 AS_000 5 318 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 301 inst_CLK_000_D1 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 300 inst_CLK_000_D0 3 -1 6 5 0 1 3 6 7 -1 -1 1 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 4 0 1 3 7 -1 -1 4 0 21 + 304 SM_AMIGA_6_ 3 -1 0 3 0 1 3 -1 -1 4 0 21 + 303 inst_CLK_OUT_PRE 3 -1 1 3 1 6 7 -1 -1 3 1 20 + 323 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 318 RN_AS_000 3 32 3 3 1 3 6 32 -1 2 0 21 + 308 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 307 SM_AMIGA_7_ 3 -1 1 3 0 1 3 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 3 0 1 3 -1 -1 1 0 21 + 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20 + 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 315 SM_AMIGA_0_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 314 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20 + 309 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 6 2 3 6 -1 -1 3 1 21 + 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20 + 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20 + 320 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 319 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 328 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 327 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 326 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 312 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20 + 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 313 SM_AMIGA_5_ 3 -1 1 1 1 -1 -1 2 0 21 + 311 CLK_CNT_1_ 3 -1 1 1 1 -1 -1 2 0 20 + 310 CLK_CNT_0_ 3 -1 1 1 1 -1 -1 2 0 20 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 306 CLK_REF_1_ 3 -1 3 1 1 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1 + 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1 + 81 AS_030 1 -1 -1 3 3 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 + 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 +95 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21 + 29 DTACK 5 -1 3 1 5 29 -1 1 0 21 + 30 LDS_000 5 321 3 0 30 -1 12 0 21 + 31 UDS_000 5 320 3 0 31 -1 8 0 21 + 65 E 5 325 6 0 65 -1 3 0 21 + 33 AMIGA_BUS_ENABLE 5 327 3 0 33 -1 3 0 20 + 28 BG_000 5 322 3 0 28 -1 3 0 21 + 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21 + 7 IPL_030_0_ 5 329 1 0 7 -1 3 0 21 + 6 IPL_030_1_ 5 328 1 0 6 -1 3 0 21 + 82 BGACK_030 5 323 7 0 82 -1 2 0 21 + 77 FPU_CS 5 324 7 0 77 -1 2 0 21 + 34 VMA 5 326 3 0 34 -1 2 0 21 + 32 AS_000 5 319 3 0 32 -1 2 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 79 DSACK_0_ 0 7 0 79 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 40 BERR 0 4 0 40 -1 1 0 21 + 21 AVEC_EXP 0 2 0 21 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 20 + 2 RESET 0 1 0 2 -1 1 0 20 + 300 inst_CLK_000_D0 3 -1 6 5 1 3 5 6 7 -1 -1 1 0 21 + 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20 + 303 inst_CLK_OUT_PRE 3 -1 0 3 1 6 7 -1 -1 4 0 21 + 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21 + 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21 + 309 SM_AMIGA_4_ 3 -1 1 3 1 3 6 -1 -1 2 0 21 + 308 SM_AMIGA_7_ 3 -1 7 3 3 6 7 -1 -1 2 0 21 + 298 inst_VPA_D 3 -1 1 3 3 5 6 -1 -1 1 0 20 + 304 SM_AMIGA_6_ 3 -1 6 2 3 6 -1 -1 4 0 20 + 295 cpu_est_1_ 3 -1 6 2 3 6 -1 -1 4 0 21 + 325 RN_E 3 65 6 2 3 6 65 -1 3 0 21 + 315 SM_AMIGA_2_ 3 -1 6 2 1 6 -1 -1 3 0 20 + 313 SM_AMIGA_3_ 3 -1 6 2 5 6 -1 -1 3 0 20 + 310 SM_AMIGA_1_ 3 -1 1 2 1 7 -1 -1 3 0 21 + 305 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20 + 294 cpu_est_0_ 3 -1 6 2 3 6 -1 -1 3 0 21 + 326 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21 + 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21 + 319 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21 + 314 SM_AMIGA_5_ 3 -1 6 2 1 6 -1 -1 2 0 20 + 297 inst_DTACK_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21 + 302 inst_CLK_000_D2 3 -1 6 2 3 6 -1 -1 1 0 21 + 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21 + 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21 + 312 CLK_CNT_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 329 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21 + 328 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21 + 327 RN_AMIGA_BUS_ENABLE 3 33 3 1 3 33 -1 3 0 20 + 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21 + 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21 + 316 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21 + 311 CLK_CNT_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21 + 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20 + 307 CLK_REF_1_ 3 -1 1 1 0 -1 -1 1 0 20 + 306 CLK_REF_0_ 3 -1 3 1 0 -1 -1 1 0 20 + 60 CLK_OSZI 9 -1 4 1 3 5 6 60 -1 + 85 RST 1 -1 -1 5 1 3 5 6 7 85 -1 + 81 AS_030 1 -1 -1 4 3 5 6 7 81 -1 + 70 RW 1 -1 -1 2 3 4 70 -1 + 63 CLK_030 1 -1 -1 2 3 7 63 -1 + 10 CLK_000 1 -1 -1 2 5 6 10 -1 + 97 DS_030 1 -1 -1 1 3 97 -1 + 96 A_19_ 1 -1 -1 1 7 96 -1 + 95 A_16_ 1 -1 -1 1 7 95 -1 + 94 A_18_ 1 -1 -1 1 7 94 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_22_ 1 -1 -1 1 4 84 -1 + 83 A_23_ 1 -1 -1 1 4 83 -1 + 78 SIZE_1_ 1 -1 -1 1 3 78 -1 + 69 SIZE_0_ 1 -1 -1 1 3 69 -1 + 68 A_0_ 1 -1 -1 1 3 68 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 58 A_17_ 1 -1 -1 1 7 58 -1 + 57 FC_1_ 1 -1 -1 1 7 57 -1 + 56 FC_0_ 1 -1 -1 1 7 56 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 27 BGACK_000 1 -1 -1 1 7 27 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1 \ No newline at end of file diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index 67068bb..aa25424 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,7 +8,7 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Sun May 18 21:01:51 2014 +; DATE Thu May 22 14:56:14 2014 Pin 79 SIZE_1_ @@ -17,33 +17,33 @@ Pin 68 IPL_2_ Pin 58 FC_1_ Pin 82 AS_030 Pin 98 DS_030 -Pin 70 SIZE_0_ -Pin 5 A_30_ Pin 14 nEXP_SPACE -Pin 6 A_29_ Pin 41 BERR Comb ; S6=1 S9=1 Pair 203 -Pin 15 A_28_ +Pin 70 SIZE_0_ Pin 21 BG_030 -Pin 16 A_27_ -Pin 17 A_26_ -Pin 18 A_25_ +Pin 5 A_30_ +Pin 6 A_29_ +Pin 15 A_28_ Pin 28 BGACK_000 -Pin 19 A_24_ +Pin 16 A_27_ Pin 64 CLK_030 -Pin 84 A_23_ +Pin 17 A_26_ Pin 11 CLK_000 -Pin 85 A_22_ +Pin 18 A_25_ Pin 61 CLK_OSZI -Pin 94 A_21_ +Pin 19 A_24_ Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 245 +Pin 84 A_23_ +Pin 85 A_22_ +Pin 94 A_21_ Pin 93 A_20_ +Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 Pin 97 A_19_ +Pin 22 AVEC_EXP Comb ; S6=1 S9=1 Pair 149 Pin 95 A_18_ Pin 59 A_17_ -Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 -Pin 96 A_16_ -Pin 22 AVEC_EXP Comb ; S6=1 S9=1 Pair 149 Pin 36 VPA +Pin 96 A_16_ Pin 86 RST Pin 71 RW Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 197 @@ -84,27 +84,28 @@ Node 181 RN_VMA Reg ; S6=1 S9=1 Node 179 RN_AMIGA_BUS_ENABLE Reg ; S6=1 S9=0 Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1 Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1 -Node 176 cpu_est_0_ Reg ; S6=1 S9=0 -Node 193 cpu_est_1_ Reg ; S6=1 S9=0 +Node 265 cpu_est_0_ Reg ; S6=1 S9=1 +Node 247 cpu_est_1_ Reg ; S6=1 S9=1 Node 271 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 -Node 260 inst_DTACK_SYNC Reg ; S6=0 S9=0 -Node 283 inst_VPA_D Reg ; S6=1 S9=0 -Node 254 inst_VPA_SYNC Reg ; S6=0 S9=0 -Node 263 inst_CLK_000_D0 Reg ; S6=1 S9=1 -Node 257 inst_CLK_000_D1 Reg ; S6=1 S9=1 -Node 247 inst_CLK_000_D2 Reg ; S6=1 S9=1 -Node 133 inst_CLK_OUT_PRE Reg ; S6=1 S9=0 -Node 101 SM_AMIGA_6_ Reg ; S6=1 S9=1 -Node 265 cpu_est_2_ Reg ; S6=1 S9=1 -Node 182 CLK_REF_1_ Lat ; S6=1 S9=0 -Node 145 SM_AMIGA_7_ Reg ; S6=1 S9=1 -Node 139 SM_AMIGA_4_ Reg ; S6=0 S9=1 -Node 277 SM_AMIGA_1_ Reg ; S6=0 S9=1 -Node 140 CLK_CNT_0_ Reg ; S6=1 S9=0 -Node 134 CLK_CNT_1_ Reg ; S6=1 S9=0 -Node 248 SM_AMIGA_3_ Reg ; S6=1 S9=0 -Node 128 SM_AMIGA_5_ Reg ; S6=0 S9=1 -Node 259 SM_AMIGA_2_ Reg ; S6=1 S9=0 -Node 253 SM_AMIGA_0_ Reg ; S6=1 S9=0 +Node 221 inst_DTACK_SYNC Reg ; S6=1 S9=1 +Node 139 inst_VPA_D Reg ; S6=1 S9=0 +Node 260 inst_VPA_SYNC Reg ; S6=0 S9=0 +Node 257 inst_CLK_000_D0 Reg ; S6=1 S9=1 +Node 193 inst_CLK_000_D1 Reg ; S6=1 S9=0 +Node 254 inst_CLK_000_D2 Reg ; S6=1 S9=1 +Node 101 inst_CLK_OUT_PRE Reg ; S6=1 S9=1 +Node 263 SM_AMIGA_6_ Reg ; S6=1 S9=0 +Node 176 cpu_est_2_ Reg ; S6=1 S9=0 +Node 182 CLK_REF_0_ Lat ; S6=0 S9=0 +Node 128 CLK_REF_1_ Lat ; S6=1 S9=0 +Node 277 SM_AMIGA_7_ Reg ; S6=1 S9=1 +Node 133 SM_AMIGA_4_ Reg ; S6=0 S9=1 +Node 145 SM_AMIGA_1_ Reg ; S6=0 S9=1 +Node 119 CLK_CNT_0_ Reg ; S6=1 S9=1 +Node 113 CLK_CNT_1_ Reg ; S6=1 S9=1 +Node 259 SM_AMIGA_3_ Reg ; S6=1 S9=0 +Node 248 SM_AMIGA_5_ Reg ; S6=1 S9=0 +Node 253 SM_AMIGA_2_ Reg ; S6=1 S9=0 +Node 283 SM_AMIGA_0_ Reg ; S6=0 S9=1 ; Unused Pins & Nodes ; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index ef3832d..12cedad 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Sun May 18 21:01:51 2014 -End : Sun May 18 21:01:51 2014 $$$ Elapsed time: 00:00:00 +Start: Thu May 22 14:56:14 2014 +End : Thu May 22 14:56:14 2014 $$$ Elapsed time: 00:00:00 =========================================================================== Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] @@ -21,16 +21,16 @@ Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030 | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 2 | 2 => 100% | 8 | 7 => 87% | 33 | 8 => 24% - 1 | 16 | 11 | 11 => 100% | 8 | 8 => 100% | 33 | 22 => 66% + 0 | 16 | 4 | 4 => 100% | 8 | 7 => 87% | 33 | 4 => 12% + 1 | 16 | 9 | 9 => 100% | 8 | 8 => 100% | 33 | 16 => 48% 2 | 16 | 2 | 2 => 100% | 8 | 8 => 100% | 33 | 1 => 3% 3 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 31 => 93% 4 | 16 | 3 | 3 => 100% | 8 | 3 => 37% | 33 | 14 => 42% - 5 | 16 | 0 | 0 => n/a | 8 | 4 => 50% | 33 | 0 => 0% - 6 | 16 | 11 | 11 => 100% | 8 | 7 => 87% | 33 | 22 => 66% + 5 | 16 | 1 | 1 => 100% | 8 | 4 => 50% | 33 | 9 => 27% + 6 | 16 | 11 | 11 => 100% | 8 | 7 => 87% | 33 | 23 => 69% 7 | 16 | 7 | 7 => 100% | 8 | 8 => 100% | 33 | 22 => 66% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 17.14 => 51% + | Avg number of array inputs in used blocks : 15.00 => 45% * Input/Clock Signal count: 35 -> placed: 35 = 100% @@ -40,14 +40,14 @@ _|____|____|____|_______________|____|_____________|___|________________ I/O Pins : 64 53 => 82% Clock Only Pins : 0 0 => 0% Clock/Input Pins : 4 4 => 100% - Logic Blocks : 8 7 => 87% - Macrocells : 128 46 => 35% - PT Clusters : 128 33 => 25% - - Single PT Clusters : 128 16 => 12% + Logic Blocks : 8 8 => 100% + Macrocells : 128 47 => 36% + PT Clusters : 128 36 => 28% + - Single PT Clusters : 128 17 => 13% Input Registers : 0 * Routing Completion: 100% -* Attempts: Place [ 94] Route [ 0] +* Attempts: Place [ 95] Route [ 0] =========================================================================== Signal Fanout Table =========================================================================== @@ -63,7 +63,7 @@ ___|__|__|____|____________________________________________________________ 3| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW 4| 3| IO| 33|=> ....|....| AS_000 |=> Paired w/: RN_AS_000 - 5| 7|INP| 82|=> ...3|..67| AS_030 + 5| 7|INP| 82|=> ...3|.567| AS_030 6| 0|OUT| 92|=> ....|....| AVEC 7| 2|OUT| 22|=> ....|....| AVEC_EXP 8| 6|INP| 69|=> ...3|....| A_0_ @@ -91,92 +91,93 @@ ___|__|__|____|____________________________________________________________ |=> Paired w/: RN_BG_000 29| 2|INP| 21|=> ...3|....| BG_030 30| 4|OUT| 47|=> ....|....| CIIN - 31| +|INP| 11|=> ....|..6.| CLK_000 + 31| +|INP| 11|=> ....|.56.| CLK_000 32| +|INP| 64|=> ...3|...7| CLK_030 - 33| 1|NOD| . |=> .1..|....| CLK_CNT_0_ - 34| 1|NOD| . |=> .1..|....| CLK_CNT_1_ + 33| 0|NOD| . |=> 0...|....| CLK_CNT_0_ + 34| 0|NOD| . |=> 0...|....| CLK_CNT_1_ 35| 6|OUT| 65|=> ....|....| CLK_DIV_OUT 36| 1|OUT| 10|=> ....|....| CLK_EXP - 37| +|Cin| 61|=> 01.3|..67| CLK_OSZI - 38| 3|NOD| . |=> .1..|....| CLK_REF_1_ - 39| 7|OUT| 80|=> ....|....| DSACK_0_ - 40| 7| IO| 81|=> ...3|....| DSACK_1_ + 37| +|Cin| 61|=> .1.3|.56.| CLK_OSZI + 38| 3|NOD| . |=> 0...|....| CLK_REF_0_ + 39| 1|NOD| . |=> 0...|....| CLK_REF_1_ + 40| 7|OUT| 80|=> ....|....| DSACK_0_ + 41| 7| IO| 81|=> ...3|....| DSACK_1_ |=> Paired w/: RN_DSACK_1_ - 41| 0|INP| 98|=> ...3|....| DS_030 - 42| 3| IO| 30|=> ....|..6.| DTACK - 43| 6| IO| 66|=> ....|....| E + 42| 0|INP| 98|=> ...3|....| DS_030 + 43| 3| IO| 30|=> ....|.5..| DTACK + 44| 6| IO| 66|=> ....|....| E |=> Paired w/: RN_E - 44| 5|INP| 57|=> ....|...7| FC_0_ - 45| 5|INP| 58|=> ....|...7| FC_1_ - 46| 7| IO| 78|=> ....|....| FPU_CS + 45| 5|INP| 57|=> ....|...7| FC_0_ + 46| 5|INP| 58|=> ....|...7| FC_1_ + 47| 7| IO| 78|=> ....|....| FPU_CS |=> Paired w/: RN_FPU_CS - 47| 1| IO| 8|=> ....|....| IPL_030_0_ + 48| 1| IO| 8|=> ....|....| IPL_030_0_ |=> Paired w/: RN_IPL_030_0_ - 48| 1| IO| 7|=> ....|....| IPL_030_1_ + 49| 1| IO| 7|=> ....|....| IPL_030_1_ |=> Paired w/: RN_IPL_030_1_ - 49| 1| IO| 9|=> ....|....| IPL_030_2_ + 50| 1| IO| 9|=> ....|....| IPL_030_2_ |=> Paired w/: RN_IPL_030_2_ - 50| 6|INP| 67|=> .1..|....| IPL_0_ - 51| 5|INP| 56|=> .1..|....| IPL_1_ - 52| 6|INP| 68|=> .1..|....| IPL_2_ - 53| 3| IO| 31|=> ....|....| LDS_000 + 51| 6|INP| 67|=> .1..|....| IPL_0_ + 52| 5|INP| 56|=> .1..|....| IPL_1_ + 53| 6|INP| 68|=> .1..|....| IPL_2_ + 54| 3| IO| 31|=> ....|....| LDS_000 |=> Paired w/: RN_LDS_000 - 54| 1|OUT| 3|=> ....|....| RESET - 55| 3|NOD| . |=> ...3|....| RN_AMIGA_BUS_ENABLE + 55| 1|OUT| 3|=> ....|....| RESET + 56| 3|NOD| . |=> ...3|....| RN_AMIGA_BUS_ENABLE |=> Paired w/: AMIGA_BUS_ENABLE - 56| 3|NOD| . |=> .1.3|..6.| RN_AS_000 + 57| 3|NOD| . |=> ...3|...7| RN_AS_000 |=> Paired w/: AS_000 - 57| 7|NOD| . |=> ...3|...7| RN_BGACK_030 + 58| 7|NOD| . |=> ...3|...7| RN_BGACK_030 |=> Paired w/: BGACK_030 - 58| 3|NOD| . |=> ...3|....| RN_BG_000 + 59| 3|NOD| . |=> ...3|....| RN_BG_000 |=> Paired w/: BG_000 - 59| 7|NOD| . |=> ....|...7| RN_DSACK_1_ + 60| 7|NOD| . |=> ....|...7| RN_DSACK_1_ |=> Paired w/: DSACK_1_ - 60| 6|NOD| . |=> ...3|..6.| RN_E + 61| 6|NOD| . |=> ...3|..6.| RN_E |=> Paired w/: E - 61| 7|NOD| . |=> ..2.|4..7| RN_FPU_CS + 62| 7|NOD| . |=> ..2.|4..7| RN_FPU_CS |=> Paired w/: FPU_CS - 62| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + 63| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ |=> Paired w/: IPL_030_0_ - 63| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + 64| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ |=> Paired w/: IPL_030_1_ - 64| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + 65| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ |=> Paired w/: IPL_030_2_ - 65| 3|NOD| . |=> ...3|....| RN_LDS_000 + 66| 3|NOD| . |=> ...3|....| RN_LDS_000 |=> Paired w/: LDS_000 - 66| 3|NOD| . |=> ...3|....| RN_UDS_000 + 67| 3|NOD| . |=> ...3|....| RN_UDS_000 |=> Paired w/: UDS_000 - 67| 3|NOD| . |=> ...3|..6.| RN_VMA + 68| 3|NOD| . |=> ...3|..6.| RN_VMA |=> Paired w/: VMA - 68| +|INP| 86|=> 01.3|..67| RST - 69| 6|INP| 71|=> ...3|4...| RW - 70| 6|INP| 70|=> ...3|....| SIZE_0_ - 71| 7|INP| 79|=> ...3|....| SIZE_1_ - 72| 6|NOD| . |=> .1..|..6.| SM_AMIGA_0_ - 73| 7|NOD| . |=> ....|..67| SM_AMIGA_1_ - 74| 6|NOD| . |=> ....|..67| SM_AMIGA_2_ - 75| 6|NOD| . |=> ....|..6.| SM_AMIGA_3_ - 76| 1|NOD| . |=> .1.3|..6.| SM_AMIGA_4_ - 77| 1|NOD| . |=> .1..|....| SM_AMIGA_5_ - 78| 0|NOD| . |=> 01.3|....| SM_AMIGA_6_ - 79| 1|NOD| . |=> 01.3|....| SM_AMIGA_7_ - 80| 3| IO| 32|=> ....|....| UDS_000 + 69| +|INP| 86|=> .1.3|.567| RST + 70| 6|INP| 71|=> ...3|4...| RW + 71| 6|INP| 70|=> ...3|....| SIZE_0_ + 72| 7|INP| 79|=> ...3|....| SIZE_1_ + 73| 7|NOD| . |=> ....|...7| SM_AMIGA_0_ + 74| 1|NOD| . |=> .1..|...7| SM_AMIGA_1_ + 75| 6|NOD| . |=> .1..|..6.| SM_AMIGA_2_ + 76| 6|NOD| . |=> ....|.56.| SM_AMIGA_3_ + 77| 1|NOD| . |=> .1.3|..6.| SM_AMIGA_4_ + 78| 6|NOD| . |=> .1..|..6.| SM_AMIGA_5_ + 79| 6|NOD| . |=> ...3|..6.| SM_AMIGA_6_ + 80| 7|NOD| . |=> ...3|..67| SM_AMIGA_7_ + 81| 3| IO| 32|=> ....|....| UDS_000 |=> Paired w/: RN_UDS_000 - 81| 3| IO| 35|=> ....|....| VMA + 82| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 82| +|INP| 36|=> ....|...7| VPA - 83| 3|NOD| . |=> ...3|..6.| cpu_est_0_ - 84| 3|NOD| . |=> ...3|..6.| cpu_est_1_ - 85| 6|NOD| . |=> ...3|..6.| cpu_est_2_ - 86| 7|NOD| . |=> 01.3|...7| inst_AS_030_000_SYNC - 87| 6|NOD| . |=> 01.3|..67| inst_CLK_000_D0 - 88| 6|NOD| . |=> 01.3|..67| inst_CLK_000_D1 - 89| 6|NOD| . |=> 01.3|....| inst_CLK_000_D2 - 90| 1|NOD| . |=> .1..|..67| inst_CLK_OUT_PRE - 91| 6|NOD| . |=> ....|..6.| inst_DTACK_SYNC - 92| 7|NOD| . |=> ...3|..6.| inst_VPA_D - 93| 6|NOD| . |=> ....|..6.| inst_VPA_SYNC - 94| +|INP| 14|=> ...3|...7| nEXP_SPACE + 83| +|INP| 36|=> .1..|....| VPA + 84| 6|NOD| . |=> ...3|..6.| cpu_est_0_ + 85| 6|NOD| . |=> ...3|..6.| cpu_est_1_ + 86| 3|NOD| . |=> ...3|..6.| cpu_est_2_ + 87| 7|NOD| . |=> ...3|..67| inst_AS_030_000_SYNC + 88| 6|NOD| . |=> .1.3|.567| inst_CLK_000_D0 + 89| 3|NOD| . |=> .1.3|..67| inst_CLK_000_D1 + 90| 6|NOD| . |=> ...3|..6.| inst_CLK_000_D2 + 91| 0|NOD| . |=> .1..|..67| inst_CLK_OUT_PRE + 92| 5|NOD| . |=> ....|.56.| inst_DTACK_SYNC + 93| 1|NOD| . |=> ...3|.56.| inst_VPA_D + 94| 6|NOD| . |=> ....|..6.| inst_VPA_SYNC + 95| +|INP| 14|=> ...3|...7| nEXP_SPACE --------------------------------------------------------------------------- =========================================================================== < C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments > @@ -296,7 +297,7 @@ ____|_____|_________|______________________________________________________ | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| SM_AMIGA_6_|NOD| | S | 4 | 4 to [ 0]| 1 XOR free + 0|inst_CLK_OUT_PRE|NOD| | S | 4 | 4 to [ 0]| 1 XOR free 1| | ? | | S | | 4 free | 1 XOR free 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free @@ -304,11 +305,11 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 5| | ? | | S | | 4 free | 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| | ? | | S | | 4 free | 1 XOR free + 8| CLK_CNT_1_|NOD| | S | 4 | 4 to [ 8]| 1 XOR free 9| | ? | | S | | 4 free | 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| | ? | | S | | 4 free | 1 XOR free +12| CLK_CNT_0_|NOD| | S | 3 | 4 to [12]| 1 XOR free 13| | ? | | S | | 4 free | 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free @@ -323,20 +324,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| SM_AMIGA_6_|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) + 0|inst_CLK_OUT_PRE|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) 1| | ? | | S | |=> can support up to [ 15] logic PT(s) 2| | ? | | S | |=> can support up to [ 19] logic PT(s) 3| | ? | | S | |=> can support up to [ 19] logic PT(s) 4| AVEC|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) 5| | ? | | S | |=> can support up to [ 19] logic PT(s) - 6| | ? | | S | |=> can support up to [ 20] logic PT(s) - 7| | ? | | S | |=> can support up to [ 20] logic PT(s) - 8| | ? | | S | |=> can support up to [ 20] logic PT(s) - 9| | ? | | S | |=> can support up to [ 20] logic PT(s) -10| | ? | | S | |=> can support up to [ 20] logic PT(s) -11| | ? | | S | |=> can support up to [ 20] logic PT(s) -12| | ? | | S | |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 20] logic PT(s) + 6| | ? | | S | |=> can support up to [ 15] logic PT(s) + 7| | ? | | S | |=> can support up to [ 15] logic PT(s) + 8| CLK_CNT_1_|NOD| | S | 4 |=> can support up to [ 20] logic PT(s) + 9| | ? | | S | |=> can support up to [ 15] logic PT(s) +10| | ? | | S | |=> can support up to [ 15] logic PT(s) +11| | ? | | S | |=> can support up to [ 15] logic PT(s) +12| CLK_CNT_0_|NOD| | S | 3 |=> can support up to [ 20] logic PT(s) +13| | ? | | S | |=> can support up to [ 15] logic PT(s) 14| | ? | | S | |=> can support up to [ 15] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- @@ -348,7 +349,7 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 0] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| SM_AMIGA_6_|NOD| | => | 5 6 7 0 | 96 97 98 91 + 0|inst_CLK_OUT_PRE|NOD| | => | 5 6 7 0 | 96 97 98 91 1| | | | => | 5 6 7 0 | 96 97 98 91 2| | | | => | 6 7 0 1 | 97 98 91 92 3| | | | => | 6 7 0 1 | 97 98 91 92 @@ -356,11 +357,11 @@ _|_________________|__|_____|____________________|________________________ 5| | | | => | 7 0 1 2 | 98 91 92 93 6| | | | => | 0 1 2 3 | 91 92 93 94 7| | | | => | 0 1 2 3 | 91 92 93 94 - 8| | | | => | 1 2 3 4 | 92 93 94 95 + 8| CLK_CNT_1_|NOD| | => | 1 2 3 4 | 92 93 94 95 9| | | | => | 1 2 3 4 | 92 93 94 95 10| | | | => | 2 3 4 5 | 93 94 95 96 11| | | | => | 2 3 4 5 | 93 94 95 96 -12| | | | => | 3 4 5 6 | 94 95 96 97 +12| CLK_CNT_0_|NOD| | => | 3 4 5 6 | 94 95 96 97 13| | | | => | 3 4 5 6 | 94 95 96 97 14| | | | => | 4 5 6 7 | 95 96 97 98 15| | | | => | 4 5 6 7 | 95 96 97 98 @@ -412,7 +413,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 91| -| | ] [RegIn 0 |102| -| | ] - [MCell 0 |101|NOD SM_AMIGA_6_| |*] + [MCell 0 |101|NOD inst_CLK_OUT_PRE| |*] [MCell 1 |103| -| | ] 1 [IOpin 1 | 92|OUT AVEC|*| ] @@ -432,7 +433,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 95|INP A_18_|*|*] [RegIn 4 |114| -| | ] - [MCell 8 |113| -| | ] + [MCell 8 |113|NOD CLK_CNT_1_| |*] [MCell 9 |115| -| | ] 5 [IOpin 5 | 96|INP A_16_|*|*] @@ -442,7 +443,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 97|INP A_19_|*|*] [RegIn 6 |120| -| | ] - [MCell 12 |119| -| | ] + [MCell 12 |119|NOD CLK_CNT_0_| |*] [MCell 13 |121| -| | ] 7 [IOpin 7 | 98|INP DS_030|*|*] @@ -456,22 +457,22 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST +Mux00| ... | ... Mux01| ... | ... Mux02| ... | ... -Mux03| ... | ... -Mux04| Input Pin ( 61)| CLK_OSZI +Mux03| Mcel 0 8 ( 113)| CLK_CNT_1_ +Mux04| Mcel 3 6 ( 182)| CLK_REF_0_ Mux05| ... | ... Mux06| ... | ... -Mux07| Mcel 6 12 ( 263)| inst_CLK_000_D0 +Mux07| ... | ... Mux08| ... | ... -Mux09| ... | ... -Mux10| Mcel 1 13 ( 145)| SM_AMIGA_7_ +Mux09| Mcel 0 12 ( 119)| CLK_CNT_0_ +Mux10| Mcel 1 2 ( 128)| CLK_REF_1_ Mux11| ... | ... -Mux12| Mcel 7 1 ( 271)| inst_AS_030_000_SYNC -Mux13| Mcel 6 8 ( 257)| inst_CLK_000_D1 +Mux12| ... | ... +Mux13| ... | ... Mux14| ... | ... -Mux15| Mcel 0 0 ( 101)| SM_AMIGA_6_ +Mux15| ... | ... Mux16| ... | ... Mux17| ... | ... Mux18| ... | ... @@ -480,7 +481,7 @@ Mux20| ... | ... Mux21| ... | ... Mux22| ... | ... Mux23| ... | ... -Mux24| Mcel 6 1 ( 247)| inst_CLK_000_D2 +Mux24| ... | ... Mux25| ... | ... Mux26| ... | ... Mux27| ... | ... @@ -502,18 +503,18 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| CLK_EXP|OUT| | A | 1 | 2 free | 1 XOR to [ 0] for 1 PT sig 1| RESET|OUT| | A | 1 | 2 free | 1 XOR to [ 1] for 1 PT sig - 2| SM_AMIGA_5_|NOD| | S | 2 | 4 to [ 2]| 1 XOR free + 2| CLK_REF_1_|NOD| | A | 1 | 2 free | 1 XOR to [ 2] for 1 PT sig 3| | ? | | S | | 4 free | 1 XOR free 4| IPL_030_2_| IO| | S | 3 | 4 to [ 4]| 1 XOR free - 5|inst_CLK_OUT_PRE|NOD| | A | 3 :+: 1| 2 free | 1 XOR to [ 5] - 6| CLK_CNT_1_|NOD| | A | 2 | 2 to [ 6]| 1 XOR free - 7| | ? | | S | | 4 to [ 5]| 1 XOR free + 5| SM_AMIGA_4_|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 6| | ? | | S | | 4 free | 1 XOR free + 7| | ? | | S | | 4 free | 1 XOR free 8| IPL_030_0_| IO| | S | 3 | 4 to [ 8]| 1 XOR free - 9| SM_AMIGA_4_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free -10| CLK_CNT_0_|NOD| | A | 2 | 2 to [10]| 1 XOR free + 9| inst_VPA_D|NOD| | A | 1 | 2 free | 1 XOR to [ 9] for 1 PT sig +10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| IPL_030_1_| IO| | S | 3 | 4 to [12]| 1 XOR free -13| SM_AMIGA_7_|NOD| | S | 2 | 4 to [13]| 1 XOR free +13| SM_AMIGA_1_|NOD| | S | 3 | 4 to [13]| 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -527,20 +528,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| CLK_EXP|OUT| | A | 1 |=> can support up to [ 5] logic PT(s) - 1| RESET|OUT| | A | 1 |=> can support up to [ 10] logic PT(s) - 2| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 12] logic PT(s) + 0| CLK_EXP|OUT| | A | 1 |=> can support up to [ 7] logic PT(s) + 1| RESET|OUT| | A | 1 |=> can support up to [ 12] logic PT(s) + 2| CLK_REF_1_|NOD| | A | 1 |=> can support up to [ 10] logic PT(s) 3| | ? | | S | |=> can support up to [ 7] logic PT(s) - 4| IPL_030_2_| IO| | S | 3 |=> can support up to [ 12] logic PT(s) - 5|inst_CLK_OUT_PRE|NOD| | A | 3 :+: 1|=> can support up to [ 7] logic PT(s) - 6| CLK_CNT_1_|NOD| | A | 2 |=> can support up to [ 5] logic PT(s) - 7| | ? | | S | |=> can support up to [ 1] logic PT(s) - 8| IPL_030_0_| IO| | S | 3 |=> can support up to [ 5] logic PT(s) - 9| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) -10| CLK_CNT_0_|NOD| | A | 2 |=> can support up to [ 8] logic PT(s) -11| | ? | | S | |=> can support up to [ 5] logic PT(s) + 4| IPL_030_2_| IO| | S | 3 |=> can support up to [ 15] logic PT(s) + 5| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) + 6| | ? | | S | |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 12] logic PT(s) + 8| IPL_030_0_| IO| | S | 3 |=> can support up to [ 17] logic PT(s) + 9| inst_VPA_D|NOD| | A | 1 |=> can support up to [ 13] logic PT(s) +10| | ? | | S | |=> can support up to [ 12] logic PT(s) +11| | ? | | S | |=> can support up to [ 10] logic PT(s) 12| IPL_030_1_| IO| | S | 3 |=> can support up to [ 15] logic PT(s) -13| SM_AMIGA_7_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) +13| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) 14| | ? | | S | |=> can support up to [ 10] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- @@ -554,18 +555,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) 1| RESET|OUT| | => | 5 6 ( 7) 0 | 5 4 ( 3) 10 - 2| SM_AMIGA_5_|NOD| | => | 6 7 0 1 | 4 3 10 9 + 2| CLK_REF_1_|NOD| | => | 6 7 0 1 | 4 3 10 9 3| | | | => | 6 7 0 1 | 4 3 10 9 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 - 5|inst_CLK_OUT_PRE|NOD| | => | 7 0 1 2 | 3 10 9 8 - 6| CLK_CNT_1_|NOD| | => | 0 1 2 3 | 10 9 8 7 + 5| SM_AMIGA_4_|NOD| | => | 7 0 1 2 | 3 10 9 8 + 6| | | | => | 0 1 2 3 | 10 9 8 7 7| | | | => | 0 1 2 3 | 10 9 8 7 8| IPL_030_0_| IO| | => | 1 ( 2) 3 4 | 9 ( 8) 7 6 - 9| SM_AMIGA_4_|NOD| | => | 1 2 3 4 | 9 8 7 6 -10| CLK_CNT_0_|NOD| | => | 2 3 4 5 | 8 7 6 5 + 9| inst_VPA_D|NOD| | => | 1 2 3 4 | 9 8 7 6 +10| | | | => | 2 3 4 5 | 8 7 6 5 11| | | | => | 2 3 4 5 | 8 7 6 5 12| IPL_030_1_| IO| | => |( 3) 4 5 6 |( 7) 6 5 4 -13| SM_AMIGA_7_|NOD| | => | 3 4 5 6 | 7 6 5 4 +13| SM_AMIGA_1_|NOD| | => | 3 4 5 6 | 7 6 5 4 14| | | | => | 4 5 6 7 | 6 5 4 3 15| | | | => | 4 5 6 7 | 6 5 4 3 --------------------------------------------------------------------------- @@ -624,33 +625,33 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_] [RegIn 1 |129| -| | ] - [MCell 2 |128|NOD SM_AMIGA_5_| |*] + [MCell 2 |128|NOD CLK_REF_1_| |*] [MCell 3 |130| -| | ] 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] [RegIn 2 |132| -| | ] [MCell 4 |131|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] - [MCell 5 |133|NOD inst_CLK_OUT_PRE| |*] + [MCell 5 |133|NOD SM_AMIGA_4_| |*] 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] - [MCell 6 |134|NOD CLK_CNT_1_| |*] + [MCell 6 |134| -| | ] [MCell 7 |136| -| | ] 4 [IOpin 4 | 6|INP A_29_|*|*] [RegIn 4 |138| -| | ] [MCell 8 |137|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] - [MCell 9 |139|NOD SM_AMIGA_4_| |*] + [MCell 9 |139|NOD inst_VPA_D| |*] 5 [IOpin 5 | 5|INP A_30_|*|*] [RegIn 5 |141| -| | ] - [MCell 10 |140|NOD CLK_CNT_0_| |*] + [MCell 10 |140| -| | ] [MCell 11 |142| -| | ] 6 [IOpin 6 | 4|INP A_31_|*|*] [RegIn 6 |144| -| | ] [MCell 12 |143|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] - [MCell 13 |145|NOD SM_AMIGA_7_| |*] + [MCell 13 |145|NOD SM_AMIGA_1_| |*] 7 [IOpin 7 | 3|OUT RESET|*| ] [RegIn 7 |147| -| | ] @@ -664,37 +665,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| IOPin 6 2 ( 67)| IPL_0_ -Mux01| Mcel 1 12 ( 143)| RN_IPL_030_1_ -Mux02| Mcel 1 10 ( 140)| CLK_CNT_0_ +Mux01| Mcel 3 13 ( 193)| inst_CLK_000_D1 +Mux02| ... | ... Mux03| IOPin 5 4 ( 56)| IPL_1_ Mux04| IOPin 6 3 ( 68)| IPL_2_ Mux05| ... | ... -Mux06| Mcel 1 9 ( 139)| SM_AMIGA_4_ -Mux07| Mcel 3 9 ( 187)| RN_AS_000 +Mux06| ... | ... +Mux07| ... | ... Mux08| Mcel 1 8 ( 137)| RN_IPL_030_0_ Mux09| ... | ... -Mux10| Mcel 1 2 ( 128)| SM_AMIGA_5_ -Mux11| Mcel 1 6 ( 134)| CLK_CNT_1_ -Mux12| Mcel 7 1 ( 271)| inst_AS_030_000_SYNC -Mux13| Mcel 6 8 ( 257)| inst_CLK_000_D1 -Mux14| Mcel 6 12 ( 263)| inst_CLK_000_D0 -Mux15| Mcel 0 0 ( 101)| SM_AMIGA_6_ -Mux16| Mcel 3 6 ( 182)| CLK_REF_1_ +Mux10| Input Pin ( 36)| VPA +Mux11| ... | ... +Mux12| Mcel 1 12 ( 143)| RN_IPL_030_1_ +Mux13| Mcel 6 8 ( 257)| inst_CLK_000_D0 +Mux14| ... | ... +Mux15| Mcel 0 0 ( 101)| inst_CLK_OUT_PRE +Mux16| ... | ... Mux17| ... | ... Mux18| ... | ... Mux19| ... | ... Mux20| ... | ... Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 5 ( 253)| SM_AMIGA_0_ -Mux23| ... | ... -Mux24| Mcel 6 1 ( 247)| inst_CLK_000_D2 +Mux22| Mcel 6 5 ( 253)| SM_AMIGA_2_ +Mux23| Mcel 6 2 ( 248)| SM_AMIGA_5_ +Mux24| ... | ... Mux25| ... | ... Mux26| ... | ... Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ -Mux28| Mcel 1 13 ( 145)| SM_AMIGA_7_ +Mux28| Mcel 1 13 ( 145)| SM_AMIGA_1_ Mux29| Input Pin ( 61)| CLK_OSZI Mux30| ... | ... -Mux31| Mcel 1 5 ( 133)| inst_CLK_OUT_PRE +Mux31| Mcel 1 5 ( 133)| SM_AMIGA_4_ Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -913,19 +914,19 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| DTACK| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| BG_000| IO| | S | 3 | 4 to [ 1]| 1 XOR free - 2| cpu_est_0_|NOD| | A | 3 | 2 to [ 2]| 1 XOR to [ 2] as logic PT - 3| | ? | | S | | 4 free | 1 XOR free - 4|AMIGA_BUS_ENABLE| IO| | A | 3 | 2 to [ 4]| 1 XOR to [ 4] as logic PT - 5| VMA| IO| | S | 2 | 4 to [ 5]| 1 XOR free - 6| CLK_REF_1_|NOD| | A | 1 | 2 free | 1 XOR to [ 6] for 1 PT sig + 2| cpu_est_2_|NOD| | A | 3 :+: 1| 2 to [ 2]| 1 XOR to [ 2] + 3| | ? | | S | | 4 to [ 2]| 1 XOR free + 4|AMIGA_BUS_ENABLE| IO| | A | 3 | 2 free | 1 XOR free + 5| VMA| IO| | S | 2 | 4 to [ 4]| 1 XOR free + 6| CLK_REF_0_|NOD| | A | 1 | 2 to [ 5]| 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 to [ 8]| 1 XOR free 8| LDS_000| IO| | S |12 | 4 to [ 8]| 1 XOR to [ 8] as logic PT 9| AS_000| IO| | S | 2 | 4 to [ 8]| 1 XOR to [ 8] as logic PT 10| | ? | | S | | 4 to [ 9]| 1 XOR free -11| | ? | | S | | 4 free | 1 XOR free +11| | ? | | S | | 4 to [12]| 1 XOR free 12| UDS_000| IO| | S | 8 | 4 to [12]| 1 XOR to [12] as logic PT -13| cpu_est_1_|NOD| | A | 4 | 2 to [12]| 1 XOR to [12] as logic PT -14| | ? | | S | | 4 to [13]| 1 XOR free +13|inst_CLK_000_D1|NOD| | A | 1 | 2 to [12]| 1 XOR to [13] for 1 PT sig +14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -939,21 +940,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| DTACK| IO| | S | 1 |=> can support up to [ 5] logic PT(s) - 1| BG_000| IO| | S | 3 |=> can support up to [ 14] logic PT(s) - 2| cpu_est_0_|NOD| | A | 3 |=> can support up to [ 8] logic PT(s) - 3| | ? | | S | |=> can support up to [ 5] logic PT(s) - 4|AMIGA_BUS_ENABLE| IO| | A | 3 |=> can support up to [ 10] logic PT(s) - 5| VMA| IO| | S | 2 |=> can support up to [ 7] logic PT(s) - 6| CLK_REF_1_|NOD| | A | 1 |=> can support up to [ 3] logic PT(s) - 7| | ? | | S | |=> can support up to [ 3] logic PT(s) + 1| BG_000| IO| | S | 3 |=> can support up to [ 9] logic PT(s) + 2| cpu_est_2_|NOD| | A | 3 :+: 1|=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 4] logic PT(s) + 4|AMIGA_BUS_ENABLE| IO| | A | 3 |=> can support up to [ 8] logic PT(s) + 5| VMA| IO| | S | 2 |=> can support up to [ 5] logic PT(s) + 6| CLK_REF_0_|NOD| | A | 1 |=> can support up to [ 1] logic PT(s) + 7| | ? | | S | |=> can support up to [ 1] logic PT(s) 8| LDS_000| IO| | S |12 |=> can support up to [ 15] logic PT(s) - 9| AS_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) -10| | ? | | S | |=> can support up to [ 6] logic PT(s) -11| | ? | | S | |=> can support up to [ 5] logic PT(s) -12| UDS_000| IO| | S | 8 |=> can support up to [ 13] logic PT(s) -13| cpu_est_1_|NOD| | A | 4 |=> can support up to [ 10] logic PT(s) -14| | ? | | S | |=> can support up to [ 6] logic PT(s) -15| | ? | | S | |=> can support up to [ 5] logic PT(s) + 9| AS_000| IO| | S | 2 |=> can support up to [ 5] logic PT(s) +10| | ? | | S | |=> can support up to [ 1] logic PT(s) +11| | ? | | S | |=> can support up to [ 1] logic PT(s) +12| UDS_000| IO| | S | 8 |=> can support up to [ 17] logic PT(s) +13|inst_CLK_000_D1|NOD| | A | 1 |=> can support up to [ 11] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Node-Pin Assignments @@ -965,18 +966,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| DTACK| IO| | => |( 5) 6 7 0 |( 30) 29 28 35 1| BG_000| IO| | => | 5 ( 6) 7 0 | 30 ( 29) 28 35 - 2| cpu_est_0_|NOD| | => | 6 7 0 1 | 29 28 35 34 + 2| cpu_est_2_|NOD| | => | 6 7 0 1 | 29 28 35 34 3| | | | => | 6 7 0 1 | 29 28 35 34 4|AMIGA_BUS_ENABLE| IO| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 5| VMA| IO| | => | 7 ( 0) 1 2 | 28 ( 35) 34 33 - 6| CLK_REF_1_|NOD| | => | 0 1 2 3 | 35 34 33 32 + 6| CLK_REF_0_|NOD| | => | 0 1 2 3 | 35 34 33 32 7| | | | => | 0 1 2 3 | 35 34 33 32 8| LDS_000| IO| | => | 1 2 3 ( 4)| 34 33 32 ( 31) 9| AS_000| IO| | => | 1 ( 2) 3 4 | 34 ( 33) 32 31 10| | | | => | 2 3 4 5 | 33 32 31 30 11| | | | => | 2 3 4 5 | 33 32 31 30 12| UDS_000| IO| | => |( 3) 4 5 6 |( 32) 31 30 29 -13| cpu_est_1_|NOD| | => | 3 4 5 6 | 32 31 30 29 +13|inst_CLK_000_D1|NOD| | => | 3 4 5 6 | 32 31 30 29 14| | | | => | 4 5 6 7 | 31 30 29 28 15| | | | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- @@ -1038,7 +1039,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 34| IO AMIGA_BUS_ENABLE|*| ] paired w/[RN_AMIGA_BUS_ENABLE] [RegIn 1 |177| -| | ] - [MCell 2 |176|NOD cpu_est_0_| |*] + [MCell 2 |176|NOD cpu_est_2_| |*] [MCell 3 |178| -| | ] 2 [IOpin 2 | 33| IO AS_000|*| ] paired w/[ RN_AS_000] @@ -1048,7 +1049,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 32| IO UDS_000|*| ] paired w/[ RN_UDS_000] [RegIn 3 |183| -| | ] - [MCell 6 |182|NOD CLK_REF_1_| |*] + [MCell 6 |182|NOD CLK_REF_0_| |*] [MCell 7 |184| -| | ] 4 [IOpin 4 | 31| IO LDS_000|*| ] paired w/[ RN_LDS_000] @@ -1064,7 +1065,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] [RegIn 6 |192| -| | ] [MCell 12 |191|NOD RN_UDS_000| |*] paired w/[ UDS_000] - [MCell 13 |193|NOD cpu_est_1_| |*] + [MCell 13 |193|NOD inst_CLK_000_D1| |*] 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] @@ -1077,39 +1078,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST -Mux01| Mcel 3 13 ( 193)| cpu_est_1_ -Mux02| Mcel 3 1 ( 175)| RN_BG_000 -Mux03| Mcel 3 2 ( 176)| cpu_est_0_ -Mux04| Mcel 0 0 ( 101)| SM_AMIGA_6_ -Mux05| IOPin 0 7 ( 98)| DS_030 +Mux00| IOPin 6 5 ( 70)| SIZE_0_ +Mux01| Mcel 3 13 ( 193)| inst_CLK_000_D1 +Mux02| Mcel 6 4 ( 251)| RN_E +Mux03| Mcel 3 2 ( 176)| cpu_est_2_ +Mux04| Input Pin ( 64)| CLK_030 +Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| IOPin 7 6 ( 79)| SIZE_1_ -Mux07| Mcel 6 12 ( 263)| inst_CLK_000_D0 +Mux07| Mcel 6 12 ( 263)| SM_AMIGA_6_ Mux08| IOPin 6 6 ( 71)| RW Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 3 4 ( 179)| RN_AMIGA_BUS_ENABLE +Mux10| Mcel 6 8 ( 257)| inst_CLK_000_D0 Mux11| Mcel 3 12 ( 191)| RN_UDS_000 Mux12| Mcel 3 9 ( 187)| RN_AS_000 -Mux13| Mcel 6 8 ( 257)| inst_CLK_000_D1 -Mux14| IOPin 6 5 ( 70)| SIZE_0_ -Mux15| Input Pin ( 14)| nEXP_SPACE +Mux13| Mcel 7 5 ( 277)| SM_AMIGA_7_ +Mux14| Mcel 3 4 ( 179)| RN_AMIGA_BUS_ENABLE +Mux15| IOPin 6 4 ( 69)| A_0_ Mux16| Mcel 3 8 ( 185)| RN_LDS_000 Mux17| IOPin 7 4 ( 81)| DSACK_1_ -Mux18| IOPin 6 4 ( 69)| A_0_ +Mux18| IOPin 0 7 ( 98)| DS_030 Mux19| Mcel 7 1 ( 271)| inst_AS_030_000_SYNC -Mux20| Input Pin ( 64)| CLK_030 -Mux21| Mcel 6 4 ( 251)| RN_E +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| Input Pin ( 86)| RST Mux22| IOPin 2 6 ( 21)| BG_030 -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux23| Mcel 6 6 ( 254)| inst_CLK_000_D2 Mux24| Mcel 3 5 ( 181)| RN_VMA -Mux25| Mcel 6 13 ( 265)| cpu_est_2_ +Mux25| Mcel 6 13 ( 265)| cpu_est_0_ Mux26| ... | ... -Mux27| Mcel 7 9 ( 283)| inst_VPA_D -Mux28| Mcel 1 13 ( 145)| SM_AMIGA_7_ +Mux27| Mcel 3 1 ( 175)| RN_BG_000 +Mux28| Mcel 1 5 ( 133)| SM_AMIGA_4_ Mux29| Input Pin ( 61)| CLK_OSZI Mux30| ... | ... -Mux31| Mcel 1 9 ( 139)| SM_AMIGA_4_ -Mux32| Mcel 6 1 ( 247)| inst_CLK_000_D2 +Mux31| Mcel 1 9 ( 139)| inst_VPA_D +Mux32| Mcel 6 1 ( 247)| cpu_est_1_ --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > Macrocell (MCell) Cluster Assignments @@ -1315,6 +1316,85 @@ Mux30| ... | ... Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0|inst_DTACK_SYNC|NOD| | S | 2 | 4 to [ 0]| 1 XOR free + 1| | ? | | S | | 4 free | 1 XOR free + 2| | ? | | S | | 4 free | 1 XOR free + 3| | ? | | S | | 4 free | 1 XOR free + 4| | ? | | S | | 4 free | 1 XOR free + 5| | ? | | S | | 4 free | 1 XOR free + 6| | ? | | S | | 4 free | 1 XOR free + 7| | ? | | S | | 4 free | 1 XOR free + 8| | ? | | S | | 4 free | 1 XOR free + 9| | ? | | S | | 4 free | 1 XOR free +10| | ? | | S | | 4 free | 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free +12| | ? | | S | | 4 free | 1 XOR free +13| | ? | | S | | 4 free | 1 XOR free +14| | ? | | S | | 4 free | 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0|inst_DTACK_SYNC|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) + 1| | ? | | S | |=> can support up to [ 15] logic PT(s) + 2| | ? | | S | |=> can support up to [ 20] logic PT(s) + 3| | ? | | S | |=> can support up to [ 20] logic PT(s) + 4| | ? | | S | |=> can support up to [ 20] logic PT(s) + 5| | ? | | S | |=> can support up to [ 20] logic PT(s) + 6| | ? | | S | |=> can support up to [ 20] logic PT(s) + 7| | ? | | S | |=> can support up to [ 20] logic PT(s) + 8| | ? | | S | |=> can support up to [ 20] logic PT(s) + 9| | ? | | S | |=> can support up to [ 20] logic PT(s) +10| | ? | | S | |=> can support up to [ 20] logic PT(s) +11| | ? | | S | |=> can support up to [ 20] logic PT(s) +12| | ? | | S | |=> can support up to [ 20] logic PT(s) +13| | ? | | S | |=> can support up to [ 20] logic PT(s) +14| | ? | | S | |=> can support up to [ 15] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0|inst_DTACK_SYNC|NOD| | => | 5 6 7 0 | 55 54 53 60 + 1| | | | => | 5 6 7 0 | 55 54 53 60 + 2| | | | => | 6 7 0 1 | 54 53 60 59 + 3| | | | => | 6 7 0 1 | 54 53 60 59 + 4| | | | => | 7 0 1 2 | 53 60 59 58 + 5| | | | => | 7 0 1 2 | 53 60 59 58 + 6| | | | => | 0 1 2 3 | 60 59 58 57 + 7| | | | => | 0 1 2 3 | 60 59 58 57 + 8| | | | => | 1 2 3 4 | 59 58 57 56 + 9| | | | => | 1 2 3 4 | 59 58 57 56 +10| | | | => | 2 3 4 5 | 58 57 56 55 +11| | | | => | 2 3 4 5 | 58 57 56 55 +12| | | | => | 3 4 5 6 | 57 56 55 54 +13| | | | => | 3 4 5 6 | 57 56 55 54 +14| | | | => | 4 5 6 7 | 56 55 54 53 +15| | | | => | 4 5 6 7 | 56 55 54 53 +--------------------------------------------------------------------------- =========================================================================== < Block [ 5] > IO-to-Node Pin Mapping =========================================================================== @@ -1362,7 +1442,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 60| -| | ] [RegIn 0 |222| -| | ] - [MCell 0 |221| -| | ] + [MCell 0 |221|NOD inst_DTACK_SYNC| |*] [MCell 1 |223| -| | ] 1 [IOpin 1 | 59|INP A_17_|*|*] @@ -1400,6 +1480,46 @@ IMX No. | +---- Block IO Pin or Macrocell Number [MCell 14 |242| -| | ] [MCell 15 |244| -| | ] --------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Input Pin ( 86)| RST +Mux01| ... | ... +Mux02| ... | ... +Mux03| Input Pin ( 11)| CLK_000 +Mux04| Input Pin ( 61)| CLK_OSZI +Mux05| Mcel 5 0 ( 221)| inst_DTACK_SYNC +Mux06| Mcel 1 9 ( 139)| inst_VPA_D +Mux07| ... | ... +Mux08| ... | ... +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 6 9 ( 259)| SM_AMIGA_3_ +Mux11| ... | ... +Mux12| ... | ... +Mux13| Mcel 6 8 ( 257)| inst_CLK_000_D0 +Mux14| IOPin 3 5 ( 30)| DTACK +Mux15| ... | ... +Mux16| ... | ... +Mux17| ... | ... +Mux18| ... | ... +Mux19| ... | ... +Mux20| ... | ... +Mux21| ... | ... +Mux22| ... | ... +Mux23| ... | ... +Mux24| ... | ... +Mux25| ... | ... +Mux26| ... | ... +Mux27| ... | ... +Mux28| ... | ... +Mux29| ... | ... +Mux30| ... | ... +Mux31| ... | ... +Mux32| ... | ... +--------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Macrocell (MCell) Cluster Assignments =========================================================================== @@ -1411,20 +1531,20 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1|inst_CLK_000_D2|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| SM_AMIGA_3_|NOD| | A | 3 | 2 to [ 2]| 1 XOR to [ 2] as logic PT + 1| cpu_est_1_|NOD| | S | 4 | 4 to [ 1]| 1 XOR free + 2| SM_AMIGA_5_|NOD| | A | 2 | 2 to [ 2]| 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| E| IO| | S | 3 | 4 to [ 4]| 1 XOR free - 5| SM_AMIGA_0_|NOD| | A | 3 | 2 to [ 5]| 1 XOR to [ 5] as logic PT - 6| inst_VPA_SYNC|NOD| | A | 2 | 2 to [ 6]| 1 XOR free + 5| SM_AMIGA_2_|NOD| | A | 3 | 2 to [ 5]| 1 XOR to [ 5] as logic PT + 6|inst_CLK_000_D2|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig 7| | ? | | S | | 4 free | 1 XOR free - 8|inst_CLK_000_D1|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9| SM_AMIGA_2_|NOD| | A | 3 | 2 to [ 9]| 1 XOR to [ 9] as logic PT -10|inst_DTACK_SYNC|NOD| | A | 2 | 2 to [10]| 1 XOR free + 8|inst_CLK_000_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9| SM_AMIGA_3_|NOD| | A | 3 | 2 to [ 9]| 1 XOR to [ 9] as logic PT +10| inst_VPA_SYNC|NOD| | A | 2 | 2 to [10]| 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12|inst_CLK_000_D0|NOD| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| cpu_est_2_|NOD| | S | 3 :+: 1| 4 to [13]| 1 XOR to [13] -14| | ? | | S | | 4 free | 1 XOR free +12| SM_AMIGA_6_|NOD| | A | 4 | 2 to [12]| 1 XOR to [12] as logic PT +13| cpu_est_0_|NOD| | S | 3 | 4 to [13]| 1 XOR free +14| | ? | | S | | 4 to [12]| 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -1437,22 +1557,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 1|inst_CLK_000_D2|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 2| SM_AMIGA_3_|NOD| | A | 3 |=> can support up to [ 12] logic PT(s) + 0| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) + 1| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) + 2| SM_AMIGA_5_|NOD| | A | 2 |=> can support up to [ 8] logic PT(s) 3| | ? | | S | |=> can support up to [ 5] logic PT(s) - 4| E| IO| | S | 3 |=> can support up to [ 10] logic PT(s) - 5| SM_AMIGA_0_|NOD| | A | 3 |=> can support up to [ 8] logic PT(s) - 6| inst_VPA_SYNC|NOD| | A | 2 |=> can support up to [ 12] logic PT(s) - 7| | ? | | S | |=> can support up to [ 9] logic PT(s) - 8|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) - 9| SM_AMIGA_2_|NOD| | A | 3 |=> can support up to [ 12] logic PT(s) -10|inst_DTACK_SYNC|NOD| | A | 2 |=> can support up to [ 12] logic PT(s) -11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) -13| cpu_est_2_|NOD| | S | 3 :+: 1|=> can support up to [ 18] logic PT(s) -14| | ? | | S | |=> can support up to [ 10] logic PT(s) -15| | ? | | S | |=> can support up to [ 10] logic PT(s) + 4| E| IO| | S | 3 |=> can support up to [ 14] logic PT(s) + 5| SM_AMIGA_2_|NOD| | A | 3 |=> can support up to [ 12] logic PT(s) + 6|inst_CLK_000_D2|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 7| | ? | | S | |=> can support up to [ 13] logic PT(s) + 8|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 9| SM_AMIGA_3_|NOD| | A | 3 |=> can support up to [ 12] logic PT(s) +10| inst_VPA_SYNC|NOD| | A | 2 |=> can support up to [ 8] logic PT(s) +11| | ? | | S | |=> can support up to [ 5] logic PT(s) +12| SM_AMIGA_6_|NOD| | A | 4 |=> can support up to [ 13] logic PT(s) +13| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) +14| | ? | | S | |=> can support up to [ 6] logic PT(s) +15| | ? | | S | |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Node-Pin Assignments @@ -1463,19 +1583,19 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) - 1|inst_CLK_000_D2|NOD| | => | 5 6 7 0 | 70 71 72 65 - 2| SM_AMIGA_3_|NOD| | => | 6 7 0 1 | 71 72 65 66 + 1| cpu_est_1_|NOD| | => | 5 6 7 0 | 70 71 72 65 + 2| SM_AMIGA_5_|NOD| | => | 6 7 0 1 | 71 72 65 66 3| | | | => | 6 7 0 1 | 71 72 65 66 4| E| IO| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 - 5| SM_AMIGA_0_|NOD| | => | 7 0 1 2 | 72 65 66 67 - 6| inst_VPA_SYNC|NOD| | => | 0 1 2 3 | 65 66 67 68 + 5| SM_AMIGA_2_|NOD| | => | 7 0 1 2 | 72 65 66 67 + 6|inst_CLK_000_D2|NOD| | => | 0 1 2 3 | 65 66 67 68 7| | | | => | 0 1 2 3 | 65 66 67 68 - 8|inst_CLK_000_D1|NOD| | => | 1 2 3 4 | 66 67 68 69 - 9| SM_AMIGA_2_|NOD| | => | 1 2 3 4 | 66 67 68 69 -10|inst_DTACK_SYNC|NOD| | => | 2 3 4 5 | 67 68 69 70 + 8|inst_CLK_000_D0|NOD| | => | 1 2 3 4 | 66 67 68 69 + 9| SM_AMIGA_3_|NOD| | => | 1 2 3 4 | 66 67 68 69 +10| inst_VPA_SYNC|NOD| | => | 2 3 4 5 | 67 68 69 70 11| | | | => | 2 3 4 5 | 67 68 69 70 -12|inst_CLK_000_D0|NOD| | => | 3 4 5 6 | 68 69 70 71 -13| cpu_est_2_|NOD| | => | 3 4 5 6 | 68 69 70 71 +12| SM_AMIGA_6_|NOD| | => | 3 4 5 6 | 68 69 70 71 +13| cpu_est_0_|NOD| | => | 3 4 5 6 | 68 69 70 71 14| | | | => | 4 5 6 7 | 69 70 71 72 15| | | | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- @@ -1528,37 +1648,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 65|OUT CLK_DIV_OUT|*| ] [RegIn 0 |246| -| | ] [MCell 0 |245|OUT CLK_DIV_OUT| | ] - [MCell 1 |247|NOD inst_CLK_000_D2| |*] + [MCell 1 |247|NOD cpu_est_1_| |*] 1 [IOpin 1 | 66| IO E|*| ] paired w/[ RN_E] [RegIn 1 |249| -| | ] - [MCell 2 |248|NOD SM_AMIGA_3_| |*] + [MCell 2 |248|NOD SM_AMIGA_5_| |*] [MCell 3 |250| -| | ] 2 [IOpin 2 | 67|INP IPL_0_|*|*] [RegIn 2 |252| -| | ] [MCell 4 |251|NOD RN_E| |*] paired w/[ E] - [MCell 5 |253|NOD SM_AMIGA_0_| |*] + [MCell 5 |253|NOD SM_AMIGA_2_| |*] 3 [IOpin 3 | 68|INP IPL_2_|*|*] [RegIn 3 |255| -| | ] - [MCell 6 |254|NOD inst_VPA_SYNC| |*] + [MCell 6 |254|NOD inst_CLK_000_D2| |*] [MCell 7 |256| -| | ] 4 [IOpin 4 | 69|INP A_0_|*|*] [RegIn 4 |258| -| | ] - [MCell 8 |257|NOD inst_CLK_000_D1| |*] - [MCell 9 |259|NOD SM_AMIGA_2_| |*] + [MCell 8 |257|NOD inst_CLK_000_D0| |*] + [MCell 9 |259|NOD SM_AMIGA_3_| |*] 5 [IOpin 5 | 70|INP SIZE_0_|*|*] [RegIn 5 |261| -| | ] - [MCell 10 |260|NOD inst_DTACK_SYNC| |*] + [MCell 10 |260|NOD inst_VPA_SYNC| |*] [MCell 11 |262| -| | ] 6 [IOpin 6 | 71|INP RW|*|*] [RegIn 6 |264| -| | ] - [MCell 12 |263|NOD inst_CLK_000_D0| |*] - [MCell 13 |265|NOD cpu_est_2_| |*] + [MCell 12 |263|NOD SM_AMIGA_6_| |*] + [MCell 13 |265|NOD cpu_est_0_| |*] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] @@ -1572,38 +1692,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST -Mux01| Mcel 3 13 ( 193)| cpu_est_1_ +Mux01| Mcel 3 13 ( 193)| inst_CLK_000_D1 Mux02| Mcel 6 4 ( 251)| RN_E Mux03| Input Pin ( 11)| CLK_000 -Mux04| Mcel 7 5 ( 277)| SM_AMIGA_1_ -Mux05| Mcel 6 10 ( 260)| inst_DTACK_SYNC -Mux06| Mcel 1 9 ( 139)| SM_AMIGA_4_ +Mux04| Input Pin ( 61)| CLK_OSZI +Mux05| Mcel 6 10 ( 260)| inst_VPA_SYNC +Mux06| Mcel 1 9 ( 139)| inst_VPA_D Mux07| Mcel 3 5 ( 181)| RN_VMA Mux08| ... | ... -Mux09| IOPin 3 5 ( 30)| DTACK -Mux10| Mcel 6 9 ( 259)| SM_AMIGA_2_ -Mux11| Mcel 7 9 ( 283)| inst_VPA_D -Mux12| Mcel 6 13 ( 265)| cpu_est_2_ -Mux13| Mcel 6 8 ( 257)| inst_CLK_000_D1 -Mux14| Mcel 6 12 ( 263)| inst_CLK_000_D0 -Mux15| ... | ... -Mux16| Mcel 3 2 ( 176)| cpu_est_0_ +Mux09| Mcel 6 13 ( 265)| cpu_est_0_ +Mux10| Mcel 6 8 ( 257)| inst_CLK_000_D0 +Mux11| ... | ... +Mux12| Mcel 6 9 ( 259)| SM_AMIGA_3_ +Mux13| Mcel 7 5 ( 277)| SM_AMIGA_7_ +Mux14| Mcel 6 12 ( 263)| SM_AMIGA_6_ +Mux15| Mcel 0 0 ( 101)| inst_CLK_OUT_PRE +Mux16| Mcel 3 2 ( 176)| cpu_est_2_ Mux17| ... | ... Mux18| ... | ... -Mux19| IOPin 7 3 ( 82)| AS_030 +Mux19| Mcel 7 1 ( 271)| inst_AS_030_000_SYNC Mux20| ... | ... -Mux21| Input Pin ( 61)| CLK_OSZI -Mux22| Mcel 6 5 ( 253)| SM_AMIGA_0_ -Mux23| Mcel 6 6 ( 254)| inst_VPA_SYNC -Mux24| ... | ... -Mux25| Mcel 3 9 ( 187)| RN_AS_000 +Mux21| ... | ... +Mux22| Mcel 6 5 ( 253)| SM_AMIGA_2_ +Mux23| Mcel 6 6 ( 254)| inst_CLK_000_D2 +Mux24| Mcel 6 1 ( 247)| cpu_est_1_ +Mux25| Mcel 5 0 ( 221)| inst_DTACK_SYNC Mux26| ... | ... Mux27| ... | ... -Mux28| Mcel 1 5 ( 133)| inst_CLK_OUT_PRE +Mux28| Mcel 1 5 ( 133)| SM_AMIGA_4_ Mux29| ... | ... Mux30| ... | ... -Mux31| Mcel 6 2 ( 248)| SM_AMIGA_3_ -Mux32| ... | ... +Mux31| Mcel 6 2 ( 248)| SM_AMIGA_5_ +Mux32| IOPin 7 3 ( 82)| AS_030 --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Macrocell (MCell) Cluster Assignments @@ -1620,11 +1740,11 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| BGACK_030| IO| | S | 2 | 4 to [ 4]| 1 XOR free - 5| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free + 5| SM_AMIGA_7_|NOD| | S | 2 | 4 to [ 5]| 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| DSACK_1_| IO| | S | 2 | 4 to [ 8]| 1 XOR free - 9| inst_VPA_D|NOD| | A | 1 | 2 free | 1 XOR to [ 9] for 1 PT sig + 9| SM_AMIGA_0_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| DSACK_0_|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig @@ -1647,12 +1767,12 @@ _|_________________|__|__|___|_____|_______________________________________ 2| | ? | | S | |=> can support up to [ 10] logic PT(s) 3| | ? | | S | |=> can support up to [ 10] logic PT(s) 4| BGACK_030| IO| | S | 2 |=> can support up to [ 15] logic PT(s) - 5| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) + 5| SM_AMIGA_7_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) 6| | ? | | S | |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 12] logic PT(s) - 8| DSACK_1_| IO| | S | 2 |=> can support up to [ 17] logic PT(s) - 9| inst_VPA_D|NOD| | A | 1 |=> can support up to [ 13] logic PT(s) -10| | ? | | S | |=> can support up to [ 16] logic PT(s) + 7| | ? | | S | |=> can support up to [ 10] logic PT(s) + 8| DSACK_1_| IO| | S | 2 |=> can support up to [ 15] logic PT(s) + 9| SM_AMIGA_0_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) 11| | ? | | S | |=> can support up to [ 19] logic PT(s) 12| DSACK_0_|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) 13| | ? | | S | |=> can support up to [ 19] logic PT(s) @@ -1672,11 +1792,11 @@ _|_________________|__|_____|____________________|________________________ 2| | | | => | 6 7 0 1 | 79 78 85 84 3| | | | => | 6 7 0 1 | 79 78 85 84 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) - 5| SM_AMIGA_1_|NOD| | => | 7 0 1 2 | 78 85 84 83 + 5| SM_AMIGA_7_|NOD| | => | 7 0 1 2 | 78 85 84 83 6| | | | => | 0 1 2 3 | 85 84 83 82 7| | | | => | 0 1 2 3 | 85 84 83 82 8| DSACK_1_| IO| | => | 1 2 3 ( 4)| 84 83 82 ( 81) - 9| inst_VPA_D|NOD| | => | 1 2 3 4 | 84 83 82 81 + 9| SM_AMIGA_0_|NOD| | => | 1 2 3 4 | 84 83 82 81 10| | | | => | 2 3 4 5 | 83 82 81 80 11| | | | => | 2 3 4 5 | 83 82 81 80 12| DSACK_0_|OUT| | => | 3 4 ( 5) 6 | 82 81 ( 80) 79 @@ -1745,7 +1865,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] [RegIn 2 |276| -| | ] [MCell 4 |275|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] - [MCell 5 |277|NOD SM_AMIGA_1_| |*] + [MCell 5 |277|NOD SM_AMIGA_7_| |*] 3 [IOpin 3 | 82|INP AS_030|*|*] [RegIn 3 |279| -| | ] @@ -1755,7 +1875,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 81| IO DSACK_1_|*|*] paired w/[ RN_DSACK_1_] [RegIn 4 |282| -| | ] [MCell 8 |281|NOD RN_DSACK_1_| |*] paired w/[ DSACK_1_] - [MCell 9 |283|NOD inst_VPA_D| |*] + [MCell 9 |283|NOD SM_AMIGA_0_| |*] 5 [IOpin 5 | 80|OUT DSACK_0_|*| ] [RegIn 5 |285| -| | ] @@ -1782,31 +1902,31 @@ Mux00| Input Pin ( 86)| RST Mux01| IOPin 5 2 ( 58)| FC_1_ Mux02| ... | ... Mux03| Mcel 7 8 ( 281)| RN_DSACK_1_ -Mux04| Mcel 7 5 ( 277)| SM_AMIGA_1_ +Mux04| IOPin 3 7 ( 28)| BGACK_000 Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| IOPin 5 3 ( 57)| FC_0_ -Mux07| Mcel 6 12 ( 263)| inst_CLK_000_D0 +Mux07| Mcel 3 9 ( 187)| RN_AS_000 Mux08| IOPin 5 1 ( 59)| A_17_ Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 6 8 ( 257)| inst_CLK_000_D1 +Mux10| Mcel 1 13 ( 145)| SM_AMIGA_1_ Mux11| IOPin 0 5 ( 96)| A_16_ Mux12| IOPin 0 6 ( 97)| A_19_ -Mux13| Input Pin ( 36)| VPA +Mux13| Mcel 7 5 ( 277)| SM_AMIGA_7_ Mux14| ... | ... -Mux15| ... | ... +Mux15| Mcel 0 0 ( 101)| inst_CLK_OUT_PRE Mux16| ... | ... Mux17| IOPin 0 4 ( 95)| A_18_ -Mux18| IOPin 3 7 ( 28)| BGACK_000 +Mux18| ... | ... Mux19| Mcel 7 1 ( 271)| inst_AS_030_000_SYNC Mux20| Input Pin ( 64)| CLK_030 -Mux21| Input Pin ( 61)| CLK_OSZI +Mux21| Mcel 3 13 ( 193)| inst_CLK_000_D1 Mux22| ... | ... Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 Mux24| ... | ... Mux25| ... | ... Mux26| ... | ... -Mux27| Mcel 6 9 ( 259)| SM_AMIGA_2_ -Mux28| Mcel 1 5 ( 133)| inst_CLK_OUT_PRE +Mux27| Mcel 7 9 ( 283)| SM_AMIGA_0_ +Mux28| Mcel 6 8 ( 257)| inst_CLK_000_D0 Mux29| ... | ... Mux30| Mcel 7 0 ( 269)| RN_FPU_CS Mux31| ... | ... diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index 22bf1c7..9623a68 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic -Project Fitted on : Sun May 18 21:01:51 2014 +Project Fitted on : Thu May 22 14:56:14 2014 Device : M4A5-128/64 Package : 100TQFP @@ -40,8 +40,8 @@ Design_Summary Total Input Pins : 35 Total Output Pins : 22 Total Bidir I/O Pins : 2 - Total Flip-Flops : 39 - Total Product Terms : 111 + Total Flip-Flops : 40 + Total Product Terms : 116 Total Reserved Pins : 0 Total Reserved Blocks : 0 @@ -54,13 +54,13 @@ Dedicated Pins Input-Only Pins 2 2 0 --> 100% Clock/Input Pins 4 4 0 --> 100% I/O Pins 64 53 11 --> 82% -Logic Macrocells 128 46 82 --> 35% +Logic Macrocells 128 47 81 --> 36% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 0 .. CSM Outputs/Total Block Inputs 264 120 144 --> 45% -Logical Product Terms 640 113 527 --> 17% -Product Term Clusters 128 39 89 --> 30% +Logical Product Terms 640 117 523 --> 18% +Product Term Clusters 128 41 87 --> 32%  Blocks_Resource_Summary @@ -71,14 +71,14 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 8 7 0 2 0 14 5 15 Hi -Block B 22 8 0 11 0 5 25 7 Hi +Block A 4 7 0 4 0 12 12 13 Hi +Block B 16 8 0 9 0 7 18 11 Hi Block C 1 8 0 2 0 14 2 16 Hi -Block D 31 8 0 10 0 6 39 5 Hi +Block D 31 8 0 10 0 6 37 4 Hi Block E 14 3 0 3 0 13 3 16 Hi -Block F 0 4 0 0 0 16 0 16 Hi -Block G 22 7 0 11 0 5 24 9 Hi -Block H 22 8 0 7 0 9 15 11 Hi +Block F 9 4 0 1 0 15 2 15 Hi +Block G 23 7 0 11 0 5 27 7 Hi +Block H 22 8 0 7 0 9 16 10 Hi --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. @@ -287,7 +287,7 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 82 H . I/O ---D--GH Hi Fast AS_030 + 82 H . I/O ---D-FGH Hi Fast AS_030 69 G . I/O ---D---- Hi Fast A_0_ 96 A . I/O -------H Hi Fast A_16_ 59 F . I/O -------H Hi Fast A_17_ @@ -316,12 +316,12 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 71 G . I/O ---DE--- Hi Fast RW 70 G . I/O ---D---- Hi Fast SIZE_0_ 79 H . I/O ---D---- Hi Fast SIZE_1_ - 11 . . Ck/I ------G- - Fast CLK_000 + 11 . . Ck/I -----FG- - Fast CLK_000 14 . . Ck/I ---D---H - Fast nEXP_SPACE - 36 . . Ded -------H - Fast VPA - 61 . . Ck/I AB-D--GH - Fast CLK_OSZI + 36 . . Ded -B------ - Fast VPA + 61 . . Ck/I AB-D-FGH - Fast CLK_OSZI 64 . . Ck/I ---D---H - Fast CLK_030 - 86 . . Ded AB-D--GH - Fast RST + 86 . . Ded -B-D-FGH - Fast RST ---------------------------------------------------------------------- Power : Hi = High @@ -375,7 +375,7 @@ Bidir_Signal_List Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- 81 H 2 DFF * * ---D---- Hi Fast DSACK_1_ - 30 D 1 DFF * * ------G- Hi Fast DTACK + 30 D 1 DFF * * -----F-- Hi Fast DTACK ---------------------------------------------------------------------- Power : Hi = High @@ -391,11 +391,12 @@ Buried_Signal_List Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - B10 B 2 DFF * * -B------ Hi Fast CLK_CNT_0_ - B6 B 2 DFF * * -B------ Hi Fast CLK_CNT_1_ - D6 D 1 LAT * * -B------ Hi Fast CLK_REF_1_ + A12 A 3 DFF * * A------- Hi Fast CLK_CNT_0_ + A8 A 4 DFF * * A------- Hi Fast CLK_CNT_1_ + D6 D 1 LAT * * A------- Hi Fast CLK_REF_0_ + B2 B 1 LAT * * A------- Hi Fast CLK_REF_1_ D4 D 3 DFF * * ---D---- Hi - RN_AMIGA_BUS_ENABLE --> AMIGA_BUS_ENABLE - D9 D 2 DFF * * -B-D--G- Hi - RN_AS_000 --> AS_000 + D9 D 2 DFF * * ---D---H Hi - RN_AS_000 --> AS_000 H4 H 2 DFF * * ---D---H Hi - RN_BGACK_030 --> BGACK_030 D1 D 3 DFF * * ---D---- Hi - RN_BG_000 --> BG_000 H8 H 2 DFF * * -------H Hi - RN_DSACK_1_ --> DSACK_1_ @@ -407,25 +408,25 @@ Buried_Signal_List D8 D 12 DFF * * ---D---- Hi - RN_LDS_000 --> LDS_000 D12 D 8 DFF * * ---D---- Hi - RN_UDS_000 --> UDS_000 D5 D 2 TFF * * ---D--G- Hi - RN_VMA --> VMA - G5 G 3 DFF * * -B----G- Hi Fast SM_AMIGA_0_ - H5 H 3 DFF * * ------GH Hi Fast SM_AMIGA_1_ - G9 G 3 DFF * * ------GH Hi Fast SM_AMIGA_2_ - G2 G 3 DFF * * ------G- Hi Fast SM_AMIGA_3_ - B9 B 2 DFF * * -B-D--G- Hi Fast SM_AMIGA_4_ - B2 B 2 DFF * * -B------ Hi Fast SM_AMIGA_5_ - A0 A 4 DFF * * AB-D---- Hi Fast SM_AMIGA_6_ - B13 B 2 DFF * * AB-D---- Hi Fast SM_AMIGA_7_ - D2 D 3 DFF * * ---D--G- Hi Fast cpu_est_0_ - D13 D 4 TFF * * ---D--G- Hi Fast cpu_est_1_ - G13 G 3 DFF * * ---D--G- Hi Fast cpu_est_2_ - H1 H 4 DFF * * AB-D---H Hi Fast inst_AS_030_000_SYNC - G12 G 1 DFF * * AB-D--GH Hi Fast inst_CLK_000_D0 - G8 G 1 DFF * * AB-D--GH Hi Fast inst_CLK_000_D1 - G1 G 1 DFF * * AB-D---- Hi Fast inst_CLK_000_D2 - B5 B 3 DFF * * -B----GH Hi Fast inst_CLK_OUT_PRE - G10 G 2 DFF * * ------G- Hi Fast inst_DTACK_SYNC - H9 H 1 DFF * * ---D--G- Hi Fast inst_VPA_D - G6 G 2 DFF * * ------G- Hi Fast inst_VPA_SYNC + H9 H 3 DFF * * -------H Hi Fast SM_AMIGA_0_ + B13 B 3 DFF * * -B-----H Hi Fast SM_AMIGA_1_ + G5 G 3 DFF * * -B----G- Hi Fast SM_AMIGA_2_ + G9 G 3 DFF * * -----FG- Hi Fast SM_AMIGA_3_ + B5 B 2 DFF * * -B-D--G- Hi Fast SM_AMIGA_4_ + G2 G 2 DFF * * -B----G- Hi Fast SM_AMIGA_5_ + G12 G 4 DFF * * ---D--G- Hi Fast SM_AMIGA_6_ + H5 H 2 DFF * * ---D--GH Hi Fast SM_AMIGA_7_ + G13 G 3 DFF * * ---D--G- Hi Fast cpu_est_0_ + G1 G 4 TFF * * ---D--G- Hi Fast cpu_est_1_ + D2 D 3 DFF * * ---D--G- Hi Fast cpu_est_2_ + H1 H 4 DFF * * ---D--GH Hi Fast inst_AS_030_000_SYNC + G8 G 1 DFF * * -B-D-FGH Hi Fast inst_CLK_000_D0 + D13 D 1 DFF * * -B-D--GH Hi Fast inst_CLK_000_D1 + G6 G 1 DFF * * ---D--G- Hi Fast inst_CLK_000_D2 + A0 A 4 TFF * * -B----GH Hi Fast inst_CLK_OUT_PRE + F0 F 2 DFF * * -----FG- Hi Fast inst_DTACK_SYNC + B9 B 1 DFF * * ---D-FG- Hi Fast inst_VPA_D + G10 G 2 DFF * * ------G- Hi Fast inst_VPA_SYNC ---------------------------------------------------------------------- Power : Hi = High @@ -446,41 +447,41 @@ Signal Source : Fanout List FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} AS_030{ I}: DSACK_1_{ H} AS_000{ D} UDS_000{ D} : LDS_000{ D} BG_000{ D} FPU_CS{ H} - :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ G} + :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ F} : inst_VPA_SYNC{ G} DS_030{ B}: UDS_000{ D} LDS_000{ D} - SIZE_0_{ H}: LDS_000{ D} - A_30_{ C}: CIIN{ E} nEXP_SPACE{. }: DSACK_0_{ H} DSACK_1_{ H} BG_000{ D} :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} + SIZE_0_{ H}: LDS_000{ D} + BG_030{ D}: BG_000{ D} + A_30_{ C}: CIIN{ E} A_29_{ C}: CIIN{ E} A_28_{ D}: CIIN{ E} - BG_030{ D}: BG_000{ D} - A_27_{ D}: CIIN{ E} - A_26_{ D}: CIIN{ E} - A_25_{ D}: CIIN{ E} BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ H} - A_24_{ D}: CIIN{ E} + A_27_{ D}: CIIN{ E} CLK_030{. }: BG_000{ D} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_26_{ D}: CIIN{ E} + CLK_000{. }:inst_DTACK_SYNC{ F} inst_VPA_SYNC{ G}inst_CLK_000_D0{ G} + A_25_{ D}: CIIN{ E} + A_24_{ D}: CIIN{ E} A_23_{ I}: CIIN{ E} - CLK_000{. }:inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G}inst_CLK_000_D0{ G} A_22_{ I}: CIIN{ E} A_21_{ B}: CIIN{ E} A_20_{ B}: CIIN{ E} A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + VPA{. }: inst_VPA_D{ B} A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - VPA{. }: inst_VPA_D{ H} RST{. }: IPL_030_2_{ B} DSACK_1_{ H} AS_000{ D} : UDS_000{ D} LDS_000{ D} BG_000{ D} : BGACK_030{ H} FPU_CS{ H} DTACK{ D} : VMA{ D} RESET{ B}AMIGA_BUS_ENABLE{ D} : IPL_030_1_{ B} IPL_030_0_{ B}inst_AS_030_000_SYNC{ H} - :inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G} SM_AMIGA_6_{ A} - : CLK_REF_1_{ D} SM_AMIGA_7_{ B} SM_AMIGA_4_{ B} - : SM_AMIGA_1_{ H} SM_AMIGA_3_{ G} SM_AMIGA_5_{ B} - : SM_AMIGA_2_{ G} SM_AMIGA_0_{ G} + :inst_DTACK_SYNC{ F} inst_VPA_SYNC{ G} SM_AMIGA_6_{ G} + : CLK_REF_0_{ D} CLK_REF_1_{ B} SM_AMIGA_7_{ H} + : SM_AMIGA_4_{ B} SM_AMIGA_1_{ B} SM_AMIGA_3_{ G} + : SM_AMIGA_5_{ G} SM_AMIGA_2_{ G} SM_AMIGA_0_{ H} RW{ H}:AMIGA_BUS_DATA_DIR{ E} UDS_000{ D} LDS_000{ D} A_0_{ H}: UDS_000{ D} LDS_000{ D} IPL_1_{ G}: IPL_030_1_{ B} @@ -490,62 +491,63 @@ RN_IPL_030_2_{ C}: IPL_030_2_{ B} DSACK_1_{ I}: DTACK{ D} RN_DSACK_1_{ I}: DSACK_1_{ H} RN_AS_000{ E}: AS_000{ D} DTACK{ D} VMA{ D} - : SM_AMIGA_7_{ B} SM_AMIGA_0_{ G} + : SM_AMIGA_7_{ H} SM_AMIGA_0_{ H} RN_UDS_000{ E}: UDS_000{ D} RN_LDS_000{ E}: LDS_000{ D} RN_BG_000{ E}: BG_000{ D} RN_BGACK_030{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} : BGACK_030{ H} DTACK{ D} RN_FPU_CS{ I}: BERR{ E} AVEC_EXP{ C} FPU_CS{ H} - DTACK{ E}:inst_DTACK_SYNC{ G} - RN_E{ H}: E{ G} VMA{ D} cpu_est_1_{ D} - : inst_VPA_SYNC{ G} cpu_est_2_{ G} + DTACK{ E}:inst_DTACK_SYNC{ F} + RN_E{ H}: E{ G} VMA{ D} cpu_est_1_{ G} + : inst_VPA_SYNC{ G} cpu_est_2_{ D} RN_VMA{ E}: VMA{ D} inst_VPA_SYNC{ G} RN_AMIGA_BUS_ENABLE{ E}:AMIGA_BUS_ENABLE{ D} RN_IPL_030_1_{ C}: IPL_030_1_{ B} RN_IPL_030_0_{ C}: IPL_030_0_{ B} - cpu_est_0_{ E}: E{ G} VMA{ D} cpu_est_0_{ D} - : cpu_est_1_{ D} inst_VPA_SYNC{ G} cpu_est_2_{ G} - cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} - : inst_VPA_SYNC{ G} cpu_est_2_{ G} + cpu_est_0_{ H}: E{ G} VMA{ D} cpu_est_0_{ G} + : cpu_est_1_{ G} inst_VPA_SYNC{ G} cpu_est_2_{ D} + cpu_est_1_{ H}: E{ G} VMA{ D} cpu_est_1_{ G} + : inst_VPA_SYNC{ G} cpu_est_2_{ D} inst_AS_030_000_SYNC{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} - :inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ A} SM_AMIGA_5_{ B} -inst_DTACK_SYNC{ H}:inst_DTACK_SYNC{ G} SM_AMIGA_3_{ G} SM_AMIGA_2_{ G} - inst_VPA_D{ I}: VMA{ D}inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G} + :inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ G} SM_AMIGA_5_{ G} +inst_DTACK_SYNC{ G}:inst_DTACK_SYNC{ F} SM_AMIGA_3_{ G} SM_AMIGA_2_{ G} + inst_VPA_D{ C}: VMA{ D}inst_DTACK_SYNC{ F} inst_VPA_SYNC{ G} inst_VPA_SYNC{ H}: inst_VPA_SYNC{ G} SM_AMIGA_3_{ G} SM_AMIGA_2_{ G} inst_CLK_000_D0{ H}: IPL_030_2_{ B} DSACK_1_{ H} BGACK_030{ H} : E{ G} VMA{ D} IPL_030_1_{ B} - : IPL_030_0_{ B} cpu_est_0_{ D} cpu_est_1_{ D} - :inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G}inst_CLK_000_D1{ G} - : SM_AMIGA_6_{ A} cpu_est_2_{ G} SM_AMIGA_7_{ B} - : SM_AMIGA_4_{ B} SM_AMIGA_1_{ H} SM_AMIGA_3_{ G} - : SM_AMIGA_5_{ B} SM_AMIGA_2_{ G} SM_AMIGA_0_{ G} -inst_CLK_000_D1{ H}: IPL_030_2_{ B} AS_000{ D} UDS_000{ D} + : IPL_030_0_{ B} cpu_est_0_{ G} cpu_est_1_{ G} + :inst_DTACK_SYNC{ F} inst_VPA_SYNC{ G}inst_CLK_000_D1{ D} + : SM_AMIGA_6_{ G} cpu_est_2_{ D} SM_AMIGA_7_{ H} + : SM_AMIGA_4_{ B} SM_AMIGA_1_{ B} SM_AMIGA_3_{ G} + : SM_AMIGA_5_{ G} SM_AMIGA_2_{ G} SM_AMIGA_0_{ H} +inst_CLK_000_D1{ E}: IPL_030_2_{ B} AS_000{ D} UDS_000{ D} : LDS_000{ D} BGACK_030{ H} E{ G} - : IPL_030_1_{ B} IPL_030_0_{ B} cpu_est_0_{ D} - : cpu_est_1_{ D}inst_CLK_000_D2{ G} SM_AMIGA_6_{ A} - : cpu_est_2_{ G} SM_AMIGA_5_{ B} + : IPL_030_1_{ B} IPL_030_0_{ B} cpu_est_0_{ G} + : cpu_est_1_{ G}inst_CLK_000_D2{ G} SM_AMIGA_6_{ G} + : cpu_est_2_{ D} SM_AMIGA_5_{ G} inst_CLK_000_D2{ H}: AS_000{ D} UDS_000{ D} LDS_000{ D} - : SM_AMIGA_6_{ A} SM_AMIGA_5_{ B} -inst_CLK_OUT_PRE{ C}: CLK_DIV_OUT{ G} DSACK_1_{ H} CLK_EXP{ B} - :inst_CLK_OUT_PRE{ B} SM_AMIGA_1_{ H} SM_AMIGA_0_{ G} -SM_AMIGA_6_{ B}: AS_000{ D} UDS_000{ D} LDS_000{ D} - : BG_000{ D}AMIGA_BUS_ENABLE{ D} SM_AMIGA_6_{ A} - : SM_AMIGA_5_{ B} - cpu_est_2_{ H}: E{ G} VMA{ D} cpu_est_1_{ D} - : inst_VPA_SYNC{ G} cpu_est_2_{ G} - CLK_REF_1_{ E}:inst_CLK_OUT_PRE{ B} CLK_CNT_0_{ B} CLK_CNT_1_{ B} -SM_AMIGA_7_{ C}: BG_000{ D} SM_AMIGA_6_{ A} SM_AMIGA_7_{ B} + : SM_AMIGA_6_{ G} SM_AMIGA_5_{ G} +inst_CLK_OUT_PRE{ B}: CLK_DIV_OUT{ G} DSACK_1_{ H} CLK_EXP{ B} + : SM_AMIGA_1_{ B} SM_AMIGA_0_{ H} +SM_AMIGA_6_{ H}: AS_000{ D} UDS_000{ D} LDS_000{ D} + : BG_000{ D}AMIGA_BUS_ENABLE{ D} SM_AMIGA_6_{ G} + : SM_AMIGA_5_{ G} + cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ G} + : inst_VPA_SYNC{ G} cpu_est_2_{ D} + CLK_REF_0_{ E}:inst_CLK_OUT_PRE{ A} CLK_CNT_0_{ A} CLK_CNT_1_{ A} + CLK_REF_1_{ C}:inst_CLK_OUT_PRE{ A} CLK_CNT_0_{ A} CLK_CNT_1_{ A} +SM_AMIGA_7_{ I}: BG_000{ D} SM_AMIGA_6_{ G} SM_AMIGA_7_{ H} SM_AMIGA_4_{ C}: UDS_000{ D} LDS_000{ D} SM_AMIGA_4_{ B} : SM_AMIGA_3_{ G} -SM_AMIGA_1_{ I}: DSACK_1_{ H} SM_AMIGA_1_{ H} SM_AMIGA_0_{ G} - CLK_CNT_0_{ C}:inst_CLK_OUT_PRE{ B} CLK_CNT_0_{ B} CLK_CNT_1_{ B} - CLK_CNT_1_{ C}:inst_CLK_OUT_PRE{ B} CLK_CNT_0_{ B} CLK_CNT_1_{ B} -SM_AMIGA_3_{ H}:inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G} SM_AMIGA_3_{ G} +SM_AMIGA_1_{ C}: DSACK_1_{ H} SM_AMIGA_1_{ B} SM_AMIGA_0_{ H} + CLK_CNT_0_{ B}:inst_CLK_OUT_PRE{ A} CLK_CNT_0_{ A} CLK_CNT_1_{ A} + CLK_CNT_1_{ B}:inst_CLK_OUT_PRE{ A} CLK_CNT_0_{ A} CLK_CNT_1_{ A} +SM_AMIGA_3_{ H}:inst_DTACK_SYNC{ F} inst_VPA_SYNC{ G} SM_AMIGA_3_{ G} : SM_AMIGA_2_{ G} -SM_AMIGA_5_{ C}: SM_AMIGA_4_{ B} SM_AMIGA_5_{ B} -SM_AMIGA_2_{ H}: SM_AMIGA_1_{ H} SM_AMIGA_2_{ G} -SM_AMIGA_0_{ H}: SM_AMIGA_7_{ B} SM_AMIGA_0_{ G} +SM_AMIGA_5_{ H}: SM_AMIGA_4_{ B} SM_AMIGA_5_{ G} +SM_AMIGA_2_{ H}: SM_AMIGA_1_{ B} SM_AMIGA_2_{ G} +SM_AMIGA_0_{ I}: SM_AMIGA_7_{ H} SM_AMIGA_0_{ H} ----------------------------------------------------------------------------- {.} : Indicates block location of signal @@ -556,13 +558,15 @@ Set_Reset_Summary Block A block level set pt : GND -block level reset pt : !RST +block level reset pt : GND Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | | | | | AVEC -| * | S | BS | BR | SM_AMIGA_6_ +| * | S | BS | BR | inst_CLK_OUT_PRE +| * | S | BS | BR | CLK_CNT_1_ +| * | S | BS | BR | CLK_CNT_0_ | | | | | DS_030 | | | | | A_19_ | | | | | A_16_ @@ -583,15 +587,13 @@ Equations : | * | S | BS | BR | IPL_030_1_ | * | A | | | CLK_EXP | * | A | | | RESET -| * | A | | | inst_CLK_OUT_PRE | * | S | BR | BS | SM_AMIGA_4_ -| * | S | BS | BR | SM_AMIGA_7_ +| * | A | | | inst_VPA_D +| * | S | BR | BS | SM_AMIGA_1_ | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ | * | S | BS | BR | RN_IPL_030_2_ -| * | S | BR | BS | SM_AMIGA_5_ -| * | A | | | CLK_CNT_1_ -| * | A | | | CLK_CNT_0_ +| * | A | | | CLK_REF_1_ | | | | | A_29_ | | | | | A_30_ | | | | | A_31_ @@ -628,15 +630,15 @@ Equations : | * | S | BS | BR | BG_000 | * | S | BS | BR | VMA | * | S | BS | BR | AS_000 -| * | S | BS | BR | RN_AS_000 -| * | A | | | cpu_est_1_ -| * | A | | | cpu_est_0_ +| * | A | | | inst_CLK_000_D1 +| * | A | | | cpu_est_2_ | * | S | BS | BR | RN_VMA +| * | S | BS | BR | RN_AS_000 | * | S | BS | BR | RN_LDS_000 | * | S | BS | BR | RN_UDS_000 | * | A | | | RN_AMIGA_BUS_ENABLE | * | S | BS | BR | RN_BG_000 -| * | A | | | CLK_REF_1_ +| * | A | | | CLK_REF_0_ | | | | | BGACK_000 @@ -653,12 +655,13 @@ Equations : Block F -block level set pt : -block level reset pt : +block level set pt : !RST +block level reset pt : GND Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ +| * | S | BS | BR | inst_DTACK_SYNC | | | | | A_17_ | | | | | FC_1_ | | | | | FC_0_ @@ -674,16 +677,16 @@ Equations : +-----+-----+-----+-----+------------------------ | * | S | BS | BR | E | * | S | BS | BR | CLK_DIV_OUT -| * | S | BS | BR | inst_CLK_000_D1 | * | S | BS | BR | inst_CLK_000_D0 -| * | S | BS | BR | inst_CLK_000_D2 +| * | A | | | SM_AMIGA_6_ +| * | S | BS | BR | cpu_est_1_ | * | S | BS | BR | RN_E -| * | A | | | SM_AMIGA_0_ | * | A | | | SM_AMIGA_2_ -| * | S | BS | BR | cpu_est_2_ | * | A | | | SM_AMIGA_3_ +| * | S | BS | BR | cpu_est_0_ +| * | A | | | SM_AMIGA_5_ +| * | S | BS | BR | inst_CLK_000_D2 | * | A | | | inst_VPA_SYNC -| * | A | | | inst_DTACK_SYNC | | | | | RW | | | | | SIZE_0_ | | | | | A_0_ @@ -704,9 +707,9 @@ Equations : | | | | | DSACK_0_ | * | S | BS | BR | inst_AS_030_000_SYNC | * | S | BS | BR | RN_FPU_CS -| * | S | BR | BS | SM_AMIGA_1_ +| * | S | BS | BR | SM_AMIGA_7_ | * | S | BS | BR | RN_BGACK_030 -| * | A | | | inst_VPA_D +| * | S | BR | BS | SM_AMIGA_0_ | * | S | BS | BR | RN_DSACK_1_ | | | | | AS_030 | | | | | A_22_ @@ -728,22 +731,22 @@ BLOCK_A_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx A0 RST pin 86 mx A17 ... ... +mx A0 ... ... mx A17 ... ... mx A1 ... ... mx A18 ... ... mx A2 ... ... mx A19 ... ... -mx A3 ... ... mx A20 ... ... -mx A4 CLK_OSZI pin 61 mx A21 ... ... +mx A3 CLK_CNT_1_ mcell A8 mx A20 ... ... +mx A4 CLK_REF_0_ mcell D6 mx A21 ... ... mx A5 ... ... mx A22 ... ... mx A6 ... ... mx A23 ... ... -mx A7 inst_CLK_000_D0 mcell G12 mx A24 inst_CLK_000_D2 mcell G1 +mx A7 ... ... mx A24 ... ... mx A8 ... ... mx A25 ... ... -mx A9 ... ... mx A26 ... ... -mx A10 SM_AMIGA_7_ mcell B13 mx A27 ... ... +mx A9 CLK_CNT_0_ mcell A12 mx A26 ... ... +mx A10 CLK_REF_1_ mcell B2 mx A27 ... ... mx A11 ... ... mx A28 ... ... -mx A12inst_AS_030_000_SYNC mcell H1 mx A29 ... ... -mx A13 inst_CLK_000_D1 mcell G8 mx A30 ... ... +mx A12 ... ... mx A29 ... ... +mx A13 ... ... mx A30 ... ... mx A14 ... ... mx A31 ... ... -mx A15 SM_AMIGA_6_ mcell A0 mx A32 ... ... +mx A15 ... ... mx A32 ... ... mx A16 ... ... ---------------------------------------------------------------------------- @@ -753,22 +756,22 @@ BLOCK_B_LOGIC_ARRAY_FANIN CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx B0 IPL_0_ pin 67 mx B17 ... ... -mx B1 RN_IPL_030_1_ mcell B12 mx B18 ... ... -mx B2 CLK_CNT_0_ mcell B10 mx B19 ... ... +mx B1 inst_CLK_000_D1 mcell D13 mx B18 ... ... +mx B2 ... ... mx B19 ... ... mx B3 IPL_1_ pin 56 mx B20 ... ... mx B4 IPL_2_ pin 68 mx B21 RST pin 86 -mx B5 ... ... mx B22 SM_AMIGA_0_ mcell G5 -mx B6 SM_AMIGA_4_ mcell B9 mx B23 ... ... -mx B7 RN_AS_000 mcell D9 mx B24 inst_CLK_000_D2 mcell G1 +mx B5 ... ... mx B22 SM_AMIGA_2_ mcell G5 +mx B6 ... ... mx B23 SM_AMIGA_5_ mcell G2 +mx B7 ... ... mx B24 ... ... mx B8 RN_IPL_030_0_ mcell B8 mx B25 ... ... mx B9 ... ... mx B26 ... ... -mx B10 SM_AMIGA_5_ mcell B2 mx B27 RN_IPL_030_2_ mcell B4 -mx B11 CLK_CNT_1_ mcell B6 mx B28 SM_AMIGA_7_ mcell B13 -mx B12inst_AS_030_000_SYNC mcell H1 mx B29 CLK_OSZI pin 61 -mx B13 inst_CLK_000_D1 mcell G8 mx B30 ... ... -mx B14 inst_CLK_000_D0 mcell G12 mx B31inst_CLK_OUT_PRE mcell B5 -mx B15 SM_AMIGA_6_ mcell A0 mx B32 ... ... -mx B16 CLK_REF_1_ mcell D6 +mx B10 VPA pin 36 mx B27 RN_IPL_030_2_ mcell B4 +mx B11 ... ... mx B28 SM_AMIGA_1_ mcell B13 +mx B12 RN_IPL_030_1_ mcell B12 mx B29 CLK_OSZI pin 61 +mx B13 inst_CLK_000_D0 mcell G8 mx B30 ... ... +mx B14 ... ... mx B31 SM_AMIGA_4_ mcell B5 +mx B15inst_CLK_OUT_PRE mcell A0 mx B32 ... ... +mx B16 ... ... ---------------------------------------------------------------------------- @@ -800,22 +803,22 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 RST pin 86 mx D17 DSACK_1_ pin 81 -mx D1 cpu_est_1_ mcell D13 mx D18 A_0_ pin 69 -mx D2 RN_BG_000 mcell D1 mx D19inst_AS_030_000_SYNC mcell H1 -mx D3 cpu_est_0_ mcell D2 mx D20 CLK_030 pin 64 -mx D4 SM_AMIGA_6_ mcell A0 mx D21 RN_E mcell G4 -mx D5 DS_030 pin 98 mx D22 BG_030 pin 21 -mx D6 SIZE_1_ pin 79 mx D23 RN_BGACK_030 mcell H4 -mx D7 inst_CLK_000_D0 mcell G12 mx D24 RN_VMA mcell D5 -mx D8 RW pin 71 mx D25 cpu_est_2_ mcell G13 +mx D0 SIZE_0_ pin 70 mx D17 DSACK_1_ pin 81 +mx D1 inst_CLK_000_D1 mcell D13 mx D18 DS_030 pin 98 +mx D2 RN_E mcell G4 mx D19inst_AS_030_000_SYNC mcell H1 +mx D3 cpu_est_2_ mcell D2 mx D20 RN_BGACK_030 mcell H4 +mx D4 CLK_030 pin 64 mx D21 RST pin 86 +mx D5 nEXP_SPACE pin 14 mx D22 BG_030 pin 21 +mx D6 SIZE_1_ pin 79 mx D23 inst_CLK_000_D2 mcell G6 +mx D7 SM_AMIGA_6_ mcell G12 mx D24 RN_VMA mcell D5 +mx D8 RW pin 71 mx D25 cpu_est_0_ mcell G13 mx D9 AS_030 pin 82 mx D26 ... ... -mx D10RN_AMIGA_BUS_ENABLE mcell D4 mx D27 inst_VPA_D mcell H9 -mx D11 RN_UDS_000 mcell D12 mx D28 SM_AMIGA_7_ mcell B13 +mx D10 inst_CLK_000_D0 mcell G8 mx D27 RN_BG_000 mcell D1 +mx D11 RN_UDS_000 mcell D12 mx D28 SM_AMIGA_4_ mcell B5 mx D12 RN_AS_000 mcell D9 mx D29 CLK_OSZI pin 61 -mx D13 inst_CLK_000_D1 mcell G8 mx D30 ... ... -mx D14 SIZE_0_ pin 70 mx D31 SM_AMIGA_4_ mcell B9 -mx D15 nEXP_SPACE pin 14 mx D32 inst_CLK_000_D2 mcell G1 +mx D13 SM_AMIGA_7_ mcell H5 mx D30 ... ... +mx D14RN_AMIGA_BUS_ENABLE mcell D4 mx D31 inst_VPA_D mcell B9 +mx D15 A_0_ pin 69 mx D32 cpu_est_1_ mcell G1 mx D16 RN_LDS_000 mcell D8 ---------------------------------------------------------------------------- @@ -844,27 +847,51 @@ mx E16 ... ... ---------------------------------------------------------------------------- +BLOCK_F_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx F0 RST pin 86 mx F17 ... ... +mx F1 ... ... mx F18 ... ... +mx F2 ... ... mx F19 ... ... +mx F3 CLK_000 pin 11 mx F20 ... ... +mx F4 CLK_OSZI pin 61 mx F21 ... ... +mx F5 inst_DTACK_SYNC mcell F0 mx F22 ... ... +mx F6 inst_VPA_D mcell B9 mx F23 ... ... +mx F7 ... ... mx F24 ... ... +mx F8 ... ... mx F25 ... ... +mx F9 AS_030 pin 82 mx F26 ... ... +mx F10 SM_AMIGA_3_ mcell G9 mx F27 ... ... +mx F11 ... ... mx F28 ... ... +mx F12 ... ... mx F29 ... ... +mx F13 inst_CLK_000_D0 mcell G8 mx F30 ... ... +mx F14 DTACK pin 30 mx F31 ... ... +mx F15 ... ... mx F32 ... ... +mx F16 ... ... +---------------------------------------------------------------------------- + + BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx G0 RST pin 86 mx G17 ... ... -mx G1 cpu_est_1_ mcell D13 mx G18 ... ... -mx G2 RN_E mcell G4 mx G19 AS_030 pin 82 +mx G1 inst_CLK_000_D1 mcell D13 mx G18 ... ... +mx G2 RN_E mcell G4 mx G19inst_AS_030_000_SYNC mcell H1 mx G3 CLK_000 pin 11 mx G20 ... ... -mx G4 SM_AMIGA_1_ mcell H5 mx G21 CLK_OSZI pin 61 -mx G5 inst_DTACK_SYNC mcell G10 mx G22 SM_AMIGA_0_ mcell G5 -mx G6 SM_AMIGA_4_ mcell B9 mx G23 inst_VPA_SYNC mcell G6 -mx G7 RN_VMA mcell D5 mx G24 ... ... -mx G8 ... ... mx G25 RN_AS_000 mcell D9 -mx G9 DTACK pin 30 mx G26 ... ... -mx G10 SM_AMIGA_2_ mcell G9 mx G27 ... ... -mx G11 inst_VPA_D mcell H9 mx G28inst_CLK_OUT_PRE mcell B5 -mx G12 cpu_est_2_ mcell G13 mx G29 ... ... -mx G13 inst_CLK_000_D1 mcell G8 mx G30 ... ... -mx G14 inst_CLK_000_D0 mcell G12 mx G31 SM_AMIGA_3_ mcell G2 -mx G15 ... ... mx G32 ... ... -mx G16 cpu_est_0_ mcell D2 +mx G4 CLK_OSZI pin 61 mx G21 ... ... +mx G5 inst_VPA_SYNC mcell G10 mx G22 SM_AMIGA_2_ mcell G5 +mx G6 inst_VPA_D mcell B9 mx G23 inst_CLK_000_D2 mcell G6 +mx G7 RN_VMA mcell D5 mx G24 cpu_est_1_ mcell G1 +mx G8 ... ... mx G25 inst_DTACK_SYNC mcell F0 +mx G9 cpu_est_0_ mcell G13 mx G26 ... ... +mx G10 inst_CLK_000_D0 mcell G8 mx G27 ... ... +mx G11 ... ... mx G28 SM_AMIGA_4_ mcell B5 +mx G12 SM_AMIGA_3_ mcell G9 mx G29 ... ... +mx G13 SM_AMIGA_7_ mcell H5 mx G30 ... ... +mx G14 SM_AMIGA_6_ mcell G12 mx G31 SM_AMIGA_5_ mcell G2 +mx G15inst_CLK_OUT_PRE mcell A0 mx G32 AS_030 pin 82 +mx G16 cpu_est_2_ mcell D2 ---------------------------------------------------------------------------- @@ -873,21 +900,21 @@ BLOCK_H_LOGIC_ARRAY_FANIN CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ mx H0 RST pin 86 mx H17 A_18_ pin 95 -mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28 +mx H1 FC_1_ pin 58 mx H18 ... ... mx H2 ... ... mx H19inst_AS_030_000_SYNC mcell H1 mx H3 RN_DSACK_1_ mcell H8 mx H20 CLK_030 pin 64 -mx H4 SM_AMIGA_1_ mcell H5 mx H21 CLK_OSZI pin 61 +mx H4 BGACK_000 pin 28 mx H21 inst_CLK_000_D1 mcell D13 mx H5 nEXP_SPACE pin 14 mx H22 ... ... mx H6 FC_0_ pin 57 mx H23 RN_BGACK_030 mcell H4 -mx H7 inst_CLK_000_D0 mcell G12 mx H24 ... ... +mx H7 RN_AS_000 mcell D9 mx H24 ... ... mx H8 A_17_ pin 59 mx H25 ... ... mx H9 AS_030 pin 82 mx H26 ... ... -mx H10 inst_CLK_000_D1 mcell G8 mx H27 SM_AMIGA_2_ mcell G9 -mx H11 A_16_ pin 96 mx H28inst_CLK_OUT_PRE mcell B5 +mx H10 SM_AMIGA_1_ mcell B13 mx H27 SM_AMIGA_0_ mcell H9 +mx H11 A_16_ pin 96 mx H28 inst_CLK_000_D0 mcell G8 mx H12 A_19_ pin 97 mx H29 ... ... -mx H13 VPA pin 36 mx H30 RN_FPU_CS mcell H0 +mx H13 SM_AMIGA_7_ mcell H5 mx H30 RN_FPU_CS mcell H0 mx H14 ... ... mx H31 ... ... -mx H15 ... ... mx H32 ... ... +mx H15inst_CLK_OUT_PRE mcell A0 mx H32 ... ... mx H16 ... ... ---------------------------------------------------------------------------- @@ -986,8 +1013,7 @@ PostFit_Equations 1 1 1 Node inst_CLK_000_D1.C 1 1 1 Node inst_CLK_000_D2.D 1 1 1 Node inst_CLK_000_D2.C - 3 3 1 NodeX1 inst_CLK_OUT_PRE.D.X1 - 1 2 1 NodeX2 inst_CLK_OUT_PRE.D.X2 + 4 4 1 Node inst_CLK_OUT_PRE.T 1 1 1 Node inst_CLK_OUT_PRE.C 1 1 1 Node SM_AMIGA_6_.AR 4 6 1 Node SM_AMIGA_6_.D @@ -995,6 +1021,9 @@ PostFit_Equations 3 6 1 NodeX1 cpu_est_2_.D.X1 1 1 1 NodeX2 cpu_est_2_.D.X2 1 1 1 Node cpu_est_2_.C + 0 0 1 Node CLK_REF_0_.D + 1 1 1 Node CLK_REF_0_.AP + 0 0 1 Node CLK_REF_0_.LH 1 1 1 Node CLK_REF_1_.AR 0 0 1 Node CLK_REF_1_.D 0 0 1 Node CLK_REF_1_.LH @@ -1007,9 +1036,9 @@ PostFit_Equations 1 1 1 Node SM_AMIGA_1_.AR 3 4 1 Node SM_AMIGA_1_.D 1 1 1 Node SM_AMIGA_1_.C - 2 3 1 Node CLK_CNT_0_.D + 3 4 1 Node CLK_CNT_0_.D 1 1 1 Node CLK_CNT_0_.C - 2 3 1 Node CLK_CNT_1_.D + 4 4 1 Node CLK_CNT_1_.D 1 1 1 Node CLK_CNT_1_.C 1 1 1 Node SM_AMIGA_3_.AR 3 5 1 Node SM_AMIGA_3_.D @@ -1024,9 +1053,9 @@ PostFit_Equations 3 5 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C ========= - 181 P-Term Total: 181 + 185 P-Term Total: 185 Total Pins: 59 - Total Nodes: 22 + Total Nodes: 23 Average P-Term/Output: 2 @@ -1058,8 +1087,8 @@ DSACK_0_ = (1); DSACK_0_.OE = (nEXP_SPACE); -IPL_030_2_.D = (IPL_030_2_.Q & !inst_CLK_000_D0.Q - # IPL_030_2_.Q & inst_CLK_000_D1.Q +IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q + # inst_CLK_000_D1.Q & IPL_030_2_.Q # IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); IPL_030_2_.AP = (!RST); @@ -1243,11 +1272,10 @@ inst_CLK_000_D2.D = (inst_CLK_000_D1.Q); inst_CLK_000_D2.C = (CLK_OSZI); -inst_CLK_OUT_PRE.D.X1 = (inst_CLK_OUT_PRE.Q & CLK_CNT_0_.Q - # inst_CLK_OUT_PRE.Q & CLK_CNT_1_.Q - # !inst_CLK_OUT_PRE.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); - -inst_CLK_OUT_PRE.D.X2 = (CLK_REF_1_.Q & !CLK_CNT_0_.Q); +inst_CLK_OUT_PRE.T = (CLK_REF_0_.Q & CLK_REF_1_.Q & CLK_CNT_0_.Q & CLK_CNT_1_.Q + # !CLK_REF_0_.Q & CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q + # CLK_REF_0_.Q & !CLK_REF_1_.Q & CLK_CNT_0_.Q & !CLK_CNT_1_.Q + # !CLK_REF_0_.Q & !CLK_REF_1_.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); inst_CLK_OUT_PRE.C = (CLK_OSZI); @@ -1268,6 +1296,12 @@ cpu_est_2_.D.X2 = (cpu_est_2_.Q); cpu_est_2_.C = (CLK_OSZI); +CLK_REF_0_.D = (0); + +CLK_REF_0_.AP = (!RST); + +CLK_REF_0_.LH = (0); + CLK_REF_1_.AR = (!RST); CLK_REF_1_.D = (0); @@ -1296,13 +1330,16 @@ SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q SM_AMIGA_1_.C = (CLK_OSZI); -CLK_CNT_0_.D = (!CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q +CLK_CNT_0_.D = (CLK_REF_0_.Q & !CLK_CNT_0_.Q + # !CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q # CLK_REF_1_.Q & !CLK_CNT_0_.Q & !CLK_CNT_1_.Q); CLK_CNT_0_.C = (CLK_OSZI); -CLK_CNT_1_.D = (CLK_CNT_0_.Q & !CLK_CNT_1_.Q - # !CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q); +CLK_CNT_1_.D = (CLK_REF_0_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q + # !CLK_REF_1_.Q & !CLK_CNT_0_.Q & CLK_CNT_1_.Q + # !CLK_REF_0_.Q & CLK_CNT_0_.Q & !CLK_CNT_1_.Q + # CLK_REF_1_.Q & CLK_CNT_0_.Q & !CLK_CNT_1_.Q); CLK_CNT_1_.C = (CLK_OSZI); diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index 36bd9c2..c9e8378 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -74,6 +74,7 @@ inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1 inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1 SM_AMIGA_6_ .. .. .. .. .. .. 1 1 cpu_est_2_ .. .. .. .. .. .. 1 1 + CLK_REF_0_ .. .. .. .. .. .. 1 1 CLK_REF_1_ .. .. .. .. .. .. 1 1 SM_AMIGA_7_ .. .. .. .. .. .. 1 1 SM_AMIGA_4_ .. .. .. .. .. .. 1 1 diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index e67db52..0b0c01d 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,317 +1,320 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sun May 18 21:01:47 2014 +#$ DATE Thu May 22 14:56:10 2014 #$ MODULE 68030_tk -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 SIZE_0_ A_30_ nEXP_SPACE A_29_ BERR A_28_ BG_030 A_27_ A_26_ A_25_ BGACK_000 A_24_ CLK_030 A_23_ CLK_000 A_22_ CLK_OSZI A_21_ CLK_DIV_OUT A_20_ A_19_ A_18_ A_17_ AVEC A_16_ AVEC_EXP VPA RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 22 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_1_ SM_AMIGA_7_ SM_AMIGA_4_ SM_AMIGA_1_ CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ +#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR SIZE_0_ BG_030 A_30_ A_29_ A_28_ BGACK_000 A_27_ CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI A_24_ CLK_DIV_OUT A_23_ A_22_ A_21_ A_20_ AVEC A_19_ AVEC_EXP A_18_ A_17_ VPA A_16_ RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ +#$ NODES 23 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_0_ CLK_REF_1_ SM_AMIGA_7_ SM_AMIGA_4_ SM_AMIGA_1_ CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ .type fr -.i 72 -.o 118 -.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q IPL_030_0_.Q AS_000.Q inst_AS_030_000_SYNC.Q IPL_030_1_.Q inst_DTACK_SYNC.Q inst_VPA_D.Q IPL_030_2_.Q inst_VPA_SYNC.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q cpu_est_2_.Q CLK_REF_1_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q CLK_CNT_0_.Q CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q AMIGA_BUS_ENABLE.Q BG_000.Q DSACK_1_.PIN DTACK.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_2_.C E.C IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR inst_CLK_OUT_PRE.C BGACK_030.C BGACK_030.AP CLK_CNT_0_.C CLK_CNT_1_.C cpu_est_0_.C cpu_est_1_.C inst_VPA_SYNC.C inst_VPA_SYNC.AP FPU_CS.C FPU_CS.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP AS_000.C AS_000.AP AMIGA_BUS_ENABLE.C BG_000.C BG_000.AP DSACK_1_.C DSACK_1_.AP VMA.C VMA.AP UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP DTACK.C DTACK.AP CLK_EXP.C inst_CLK_000_D2.C inst_VPA_D.C inst_CLK_000_D0.C RESET.C inst_CLK_000_D1.C CLK_REF_1_.LH CLK_REF_1_.AR DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D FPU_CS.D E.T CLK_EXP.D VMA.T cpu_est_0_.D cpu_est_1_.T IPL_030_0_.D AS_000.D inst_AS_030_000_SYNC.D IPL_030_1_.D inst_DTACK_SYNC.D inst_VPA_D.D IPL_030_2_.D inst_VPA_SYNC.D inst_CLK_000_D0.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_CLK_OUT_PRE.D SM_AMIGA_6_.D cpu_est_2_.D CLK_REF_1_.D SM_AMIGA_7_.D UDS_000.D LDS_000.D DSACK_1_.D SM_AMIGA_4_.D SM_AMIGA_1_.D DTACK.D CLK_CNT_0_.D CLK_CNT_1_.D RESET.D SM_AMIGA_3_.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D AMIGA_BUS_ENABLE.D BG_000.D -.p 305 ------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----11------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~ -------1----------------------------------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1--------------------1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----10---11-----------------0010---1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----0--------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------01-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------01------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ------0--------0----------------1----------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ ------0--------0----------------0----------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----0---------0------------------------------------------0--0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----0---------0-------------------------------------------0-0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ --------------------------------------------------0--1--------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ ---------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ -----------------------------------------------------0---------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------1-------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~ -----------------------------------------------------0--0-------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------11-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -----------------------------------------------------1--1------01-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------0--1-------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------0-------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ---------------------------------------------------------------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -----------------------------------------------------1--0------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ -----------1--------------------------1000-----0--1----1---------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------0--------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------------------------0---0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------------------------------------1---------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ---------------------------------------------------0--------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ----------------------------------------------------1-------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ------------------------------------------------------0-----------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ -------------------------------------------------------------0----0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ --------------------------------------------------0----------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ----------------------------------------------1--1-----------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ --------------------------------------------------------------0----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----------------------------------------------------------------0-0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ --------------------------------------------------1-----------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ -----------------------------------------------------0--------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ---------------------------------------------------------0----------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ --------------------------------------------------------------0-----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ --------------0------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----0------------------------------------------------0--------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ --------0-1-----------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -------------------------------------------0---------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -----------1-----------------------------------1--1--------------1------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +.i 73 +.o 121 +.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q IPL_030_0_.Q inst_VPA_D.Q inst_VPA_SYNC.Q IPL_030_1_.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q IPL_030_2_.Q inst_CLK_000_D2.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q cpu_est_2_.Q CLK_REF_0_.Q CLK_REF_1_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q CLK_CNT_0_.Q CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q AMIGA_BUS_ENABLE.Q DSACK_1_.PIN DTACK.PIN +.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_1_.C cpu_est_2_.C E.C IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C CLK_CNT_0_.C CLK_CNT_1_.C cpu_est_0_.C inst_VPA_SYNC.C inst_VPA_SYNC.AP FPU_CS.C FPU_CS.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP AS_000.C AS_000.AP AMIGA_BUS_ENABLE.C BG_000.C BG_000.AP DSACK_1_.C DSACK_1_.AP UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP CLK_EXP.C DTACK.C DTACK.AP inst_CLK_000_D2.C inst_VPA_D.C inst_CLK_000_D0.C RESET.C inst_CLK_000_D1.C CLK_REF_0_.LH CLK_REF_0_.AP CLK_REF_1_.LH CLK_REF_1_.AR DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BG_000.D BGACK_030.D FPU_CS.D E.T VMA.T cpu_est_0_.D cpu_est_1_.T CLK_EXP.D AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D IPL_030_0_.D inst_VPA_D.D inst_VPA_SYNC.D IPL_030_1_.D inst_CLK_000_D0.D inst_CLK_000_D1.D IPL_030_2_.D inst_CLK_000_D2.D inst_CLK_OUT_PRE.T SM_AMIGA_6_.D cpu_est_2_.D CLK_REF_0_.D CLK_REF_1_.D SM_AMIGA_7_.D UDS_000.D LDS_000.D DSACK_1_.D SM_AMIGA_4_.D SM_AMIGA_1_.D DTACK.D CLK_CNT_0_.D CLK_CNT_1_.D SM_AMIGA_3_.D RESET.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D AMIGA_BUS_ENABLE.D +.p 308 +------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----11------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ +------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0-----1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0--1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------01--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----0--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1--0--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +----1-----0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------------------------------------- ~~~~~~1~1~1~1~1~1~1~1111~1~1~1~1~1~11111~1~1~1~11~1~1~1~1~11~11111~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-------------0----------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~~~~1~1~1~1~1~1~~~~~1~1~1~1~~1~1~1~1~1~~1~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------0---------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-0--------------0000000-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1111---------------------------------------------- ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-----------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------1-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-------------------0------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1--------------------1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1----11-----------------0010---1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1---------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0---------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------0---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +----1--------------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0---------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1----------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ +------------------------------------------11----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0---------------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1-0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1-------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1-----1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------11------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +----1--------------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1--------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1----0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1---0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1-0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------10----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1---------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1----1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1-----------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ +------------------------------------------1-------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--1----------------------------------------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +--------1----------------------------------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1----------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1---------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-1--------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +----------------------------------------0--------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------00-------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +--------------------------------------1-00-------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0-1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------11--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1-------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ +------------------------------------------1---------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +------0------1----------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-------------------------------------------1----------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +--------------------------------------------------0---1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +----------------------------------------------------1-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +-------------------------------------------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-----0--------1----------------1-----------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +0----0--------11---------------0-----------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +----1-------------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1--------1----------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +----1---------1---------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ +------------------------------------------1-----------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +--------------------------------------00011------1-----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0-----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +--------------------------------------0110----0--0-----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +--------------------------------------0-1--------10----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-11-------10----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1-------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-11-------10----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-11-------10----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--0-------10----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-00-------10----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1--------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-------------------------------------------------0--------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +---------0--------------------------------------------0---0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1-----------------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------1----------------------------1---------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------1-----------------------------------0--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------1-------------------------------------1------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------1---------------------------------------0----1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +-----1------------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------1----------------------------1----------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------1-----------------------------------0---------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------1-------------------------------------1-------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------1---------------------------------------0-----1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-------------------------------------------------1-----------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +-----------------------------------------------------0-------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +-----0--------0----------------1------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +0----0--------01---------------0------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-------------------------------------------------1------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +-------------------------------------------------0------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +----1---------0-----------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ +--------------0--------------------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------0---------------------------------------------1-0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-------------------------------------------------1-------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +-------------------------------------------------0---1---------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----1----------------------------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +-------------------------------------------------------------1-0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +--------------------------------------------------------1-------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +--------------------------------------------------------11------11------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------1-------01------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +--------------------------------------------------------01------01------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------0------01------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~ +--------------------------------------------------------0-------10------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +---------------------------------------------------------1------10------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +--------------------------------------------------------10------10------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------1------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +--------------------------------------------------------00------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1--1------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +-------------------------------------------------1----------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------------0----0----------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-----------------------------------------------0-0----------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----1-------------------------------------------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1---------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1-----------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-------------------------------------------------0-----------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +-------------------------------------------------1------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +-------------------------------------------------0------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-----------------------------------------------------0---------1----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +------------------------------------------0--------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +------------------------------------------1------1-------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-------------------------------------------------0-------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +-------------0--------------------------------------------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +------------------------------------------------------0---------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-----------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +----1-------------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1---------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------------- 0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~~~~~ +-1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---00-1--1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1-01--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ +-----------0------------------------------------------------------------- ~~~~~~0~0~0~0~0~0~0~0000~0~0~0~0~0~00000~0~0~0~00~0~0~0~0~00~00000~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1----------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~~~~0~0~0~0~0~0~~~~~0~0~0~0~~0~0~0~0~0~~0~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------0----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ +--------------1---------------------------------------------------------- ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------1-------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------1--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------0------------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------0------------------------------------------------ ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------0----------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------0---------------------------------------------- ~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-----------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------1-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1-------------------0------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1--------------------1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---10---11-----------------0010---1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-1--1------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------0-1-------------------------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----0---------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------01-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------01------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------10------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-10------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------00------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0-------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----0---------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0---------------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0------------------------------------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~0~~ +---------------------------------------1---------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------1------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +------------------------------------------0------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~0~~~~~~~0~~~~~~~~~~~~~~ +------------------------------------0------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------0--------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1-------0----------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +------------------------------------------------00----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0-------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------0---------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------0----1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------0-1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ +--0----------------------------------------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +--------------------------------0----------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------0---------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1--------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-10-------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +-------------------------------------------------00---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +-------------------------------------------------0-0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------10--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0--1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +-------------------------------------------0-----11-0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0---1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +-----------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-00-0--------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1------1----------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +-------------------------------------------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +1----0--------1----------------------------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +-----0--------10---------------------------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +-----0--------1----------------1-----------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +-----0--------1----------------0-----------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +-------------------------------------------------1----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0----0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +--------------------------------------0----------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------0--------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-0--------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1--1-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1----------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--1-------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +----------------------------------------01-------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +-------------------------------------------------0-----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +--------------------------------------------------1----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +----1-00-0------------------------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------0---------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +-------------------------------------------0------1-0-----0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +------------------------------------------------------0---0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +----01-----------------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +----0---------1----------------------------1---------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +----0---------1-----------------------------------0--------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +----0---------1-------------------------------------1------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +----0---------1---------------------------------------0----0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +----01------------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +----0---------1----------------------------1----------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +----0---------1-----------------------------------0---------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +----0---------1-------------------------------------1-------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +----0---------1---------------------------------------0-----0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +----0--------------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ +1----0--------0-----------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +-----0--------00----------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +-----0--------0----------------1------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +-----0--------0----------------0------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +----0---------0--------------------------------------------0--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +----0---------0---------------------------------------------0-0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +-------------------------------------------------0---1---------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ +----------------------------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +--------------------------------------------------------0-------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------1-------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------01------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +--------------------------------------------------------01-------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +---------------------------------------------------------0-------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------11------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +---------------------------------------------------------1-------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------10-------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +--------------------------------------------------------00-------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ +----------------------------------------------------------------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +----------1---------------------------1000----0--1-----1----------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0----------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +--------------------------------------------------------------0---0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +-------------------------------------------1-----------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +--------------------------------------------------0----------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +----------------------------------------------------1--------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +------------------------------------------------------0------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +--------------------------------------------------------------0----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +-------------------------------------------------0------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +--------------------------------------------1--1--------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +---------------------------------------------------------------0----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +------------------------------------------------------------------0-0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +-------------------------------------------------1-------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +-----------------------------------------------------0---------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +----------------------------------------------------------0----------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +---------------------------------------------------------------0-----0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +-------------0--------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +----0-------------------------------------------------0---------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +------------------------------------------0----------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +----------1-----------------------------------1--1----------------1-----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index 53afa0c..1b9eb18 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,317 +1,320 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sun May 18 21:01:47 2014 +#$ DATE Thu May 22 14:56:10 2014 #$ MODULE 68030_tk -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 SIZE_0_ A_30_ nEXP_SPACE A_29_ BERR A_28_ BG_030 A_27_ A_26_ A_25_ BGACK_000 A_24_ CLK_030 A_23_ CLK_000 A_22_ CLK_OSZI A_21_ CLK_DIV_OUT A_20_ A_19_ A_18_ A_17_ AVEC A_16_ AVEC_EXP VPA RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 22 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_1_ SM_AMIGA_7_ SM_AMIGA_4_ SM_AMIGA_1_ CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ +#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR SIZE_0_ BG_030 A_30_ A_29_ A_28_ BGACK_000 A_27_ CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI A_24_ CLK_DIV_OUT A_23_ A_22_ A_21_ A_20_ AVEC A_19_ AVEC_EXP A_18_ A_17_ VPA A_16_ RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ +#$ NODES 23 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_0_ CLK_REF_1_ SM_AMIGA_7_ SM_AMIGA_4_ SM_AMIGA_1_ CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ .type fr -.i 72 -.o 118 -.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q IPL_030_0_.Q AS_000.Q inst_AS_030_000_SYNC.Q IPL_030_1_.Q inst_DTACK_SYNC.Q inst_VPA_D.Q IPL_030_2_.Q inst_VPA_SYNC.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q cpu_est_2_.Q CLK_REF_1_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q CLK_CNT_0_.Q CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q AMIGA_BUS_ENABLE.Q BG_000.Q DSACK_1_.PIN DTACK.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_2_.C E.C IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR inst_CLK_OUT_PRE.C BGACK_030.C BGACK_030.AP CLK_CNT_0_.C CLK_CNT_1_.C cpu_est_0_.C cpu_est_1_.C inst_VPA_SYNC.C inst_VPA_SYNC.AP FPU_CS.C FPU_CS.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP AS_000.C AS_000.AP AMIGA_BUS_ENABLE.C BG_000.C BG_000.AP DSACK_1_.C DSACK_1_.AP VMA.C VMA.AP UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP DTACK.C DTACK.AP CLK_EXP.C inst_CLK_000_D2.C inst_VPA_D.C inst_CLK_000_D0.C RESET.C inst_CLK_000_D1.C CLK_REF_1_.LH CLK_REF_1_.AR DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D FPU_CS.D E.T CLK_EXP.D VMA.T cpu_est_0_.D cpu_est_1_.T IPL_030_0_.D AS_000.D inst_AS_030_000_SYNC.D IPL_030_1_.D inst_DTACK_SYNC.D inst_VPA_D.D IPL_030_2_.D inst_VPA_SYNC.D inst_CLK_000_D0.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_CLK_OUT_PRE.D SM_AMIGA_6_.D cpu_est_2_.D CLK_REF_1_.D SM_AMIGA_7_.D UDS_000.D LDS_000.D DSACK_1_.D SM_AMIGA_4_.D SM_AMIGA_1_.D DTACK.D CLK_CNT_0_.D CLK_CNT_1_.D RESET.D SM_AMIGA_3_.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D AMIGA_BUS_ENABLE.D BG_000.D -.p 305 ------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----11------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~ -------1----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 ----0-----1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0--1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------01-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0----0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 -------1--0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 -----------1------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ -----1-----0------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~ ------------1------------------------------------------------------------ ~~~~~~1~1~1~1~1~1~111~1~1~1~1~11~11111~1~1~1~11~1~1~1~1~1~1~111111~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ --------------0---------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~~~1~1~1~1~1~~1~~~~~1~1~1~1~~1~1~1~1~1~1~1~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------0--------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --0--------------0000000------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------1111--------------------------------------------- ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1-----------------1-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1------------------1------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1-------------------0------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1--------------------1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----1----11-----------------0010---1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------1------------------------0------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------1--------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------0--------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1--------------------------------0---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ -----1---------------------------------1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ -----1----------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ -----1-----------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ -----1--------------------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------0---------------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1---------1----------------------------1---------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------1----------------10--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------1---------------10--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------1-1---------10--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ ----------------------------------------0---------10--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------00--------10--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ --------------------------------------1-00--------10--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1----------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1---------1------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~ -------------------------------------------1--------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------1------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----0---------1-----------------------------------0------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----0---------1------------------------------------1-----0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----0---------1--------------------------------------0---0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ -----01----------------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----0---------1----------------------------1--------------0------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------------------11-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -----------------------------------------------------1--1------01-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ -----------------------------------------------------0--1-------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------0-------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ---------------------------------------------------------------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -----------------------------------------------------1--0------00-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ -----------1--------------------------1000-----0--1----1---------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------0--------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------------------------0---0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------------------------------------1---------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ---------------------------------------------------0--------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ----------------------------------------------------1-------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ------------------------------------------------------0-----------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ -------------------------------------------------------------0----0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ --------------------------------------------------0----------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ----------------------------------------------1--1-----------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ --------------------------------------------------------------0----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----------------------------------------------------------------0-0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ --------------------------------------------------1-----------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ -----------------------------------------------------0--------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ---------------------------------------------------------0----------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ --------------------------------------------------------------0-----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ --------------0------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----0------------------------------------------------0--------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ --------0-1-----------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 -------------------------------------------0---------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -----------1-----------------------------------1--1--------------1------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +.i 73 +.o 121 +.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q IPL_030_0_.Q inst_VPA_D.Q inst_VPA_SYNC.Q IPL_030_1_.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q IPL_030_2_.Q inst_CLK_000_D2.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q cpu_est_2_.Q CLK_REF_0_.Q CLK_REF_1_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q CLK_CNT_0_.Q CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q AMIGA_BUS_ENABLE.Q DSACK_1_.PIN DTACK.PIN +.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_1_.C cpu_est_2_.C E.C IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C CLK_CNT_0_.C CLK_CNT_1_.C cpu_est_0_.C inst_VPA_SYNC.C inst_VPA_SYNC.AP FPU_CS.C FPU_CS.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP AS_000.C AS_000.AP AMIGA_BUS_ENABLE.C BG_000.C BG_000.AP DSACK_1_.C DSACK_1_.AP UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP CLK_EXP.C DTACK.C DTACK.AP inst_CLK_000_D2.C inst_VPA_D.C inst_CLK_000_D0.C RESET.C inst_CLK_000_D1.C CLK_REF_0_.LH CLK_REF_0_.AP CLK_REF_1_.LH CLK_REF_1_.AR DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BG_000.D BGACK_030.D FPU_CS.D E.T VMA.T cpu_est_0_.D cpu_est_1_.T CLK_EXP.D AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D IPL_030_0_.D inst_VPA_D.D inst_VPA_SYNC.D IPL_030_1_.D inst_CLK_000_D0.D inst_CLK_000_D1.D IPL_030_2_.D inst_CLK_000_D2.D inst_CLK_OUT_PRE.T SM_AMIGA_6_.D cpu_est_2_.D CLK_REF_0_.D CLK_REF_1_.D SM_AMIGA_7_.D UDS_000.D LDS_000.D DSACK_1_.D SM_AMIGA_4_.D SM_AMIGA_1_.D DTACK.D CLK_CNT_0_.D CLK_CNT_1_.D SM_AMIGA_3_.D RESET.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D AMIGA_BUS_ENABLE.D +.p 308 +------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----11------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ +------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0-----1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0--1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------01--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----0----0--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1--0--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +----1-----0-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------------------------------------- ~~~~~~1~1~1~1~1~1~1~1111~1~1~1~1~1~11111~1~1~1~11~1~1~1~1~11~11111~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------1----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-------------0----------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~~~~1~1~1~1~1~1~~~~~1~1~1~1~~1~1~1~1~1~~1~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------0---------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-0--------------0000000-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1111---------------------------------------------- ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-----------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------1-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-------------------0------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1--------------------1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1----11-----------------0010---1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-------------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1---------------------------1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0---------------------------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------0----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------0---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +----1--------------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0---------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1----------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ +------------------------------------------11----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0---------------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1-0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--------1------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +----1--------------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1--------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1----0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1---0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1-0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------10----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1---------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1----1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------1-1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1-----------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ +------------------------------------------1-------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--1----------------------------------------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +--------1----------------------------------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1----------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1---------------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-1--------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +----------------------------------------0--------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------00-------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +--------------------------------------1-00-------10---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0-1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------11--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +----1-----------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1---------1-------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ +------------------------------------------1---------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +------0------1----------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-------------------------------------------1----------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +--------------------------------------------------0---1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +----------------------------------------------------1-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +-------------------------------------------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-----0--------1----------------1-----------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +0----0--------11---------------0-----------0------1-0-1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +----1-------------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1--------1----------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +----1---------1---------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ +------------------------------------------1-----------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1-------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +--------------------------------------00011------1-----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0-----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +--------------------------------------0110----0--0-----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +--------------------------------------0-1--------10----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-11-------10----1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1--------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1-------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-11-------10----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-11-------10----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--0-------10----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-00-------10----0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1--------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-------------------------------------------------0--------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +---------0--------------------------------------------0---0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1-----------------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------1----------------------------1---------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------1-----------------------------------0--------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------1-------------------------------------1------1------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +--------------1---------------------------------------0-----1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-------------------------------------------------1-----------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +-----------------------------------------------------0-------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +-----0--------0----------------1------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +0----0--------01---------------0------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-------------------------------------------------1------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +-------------------------------------------------0------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +----1---------0-----------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~ +--------------0--------------------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +--------------0---------------------------------------------1-0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-------------------------------------------------1-------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +-------------------------------------------------0---1---------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +----1----------------------------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +-------------------------------------------------------------1-0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +--------------------------------------------------------1-------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +--------------------------------------------------------11------11------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------1-------01------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +--------------------------------------------------------01------01------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------0------01------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~ +--------------------------------------------------------0-------10------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +---------------------------------------------------------1------10------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +--------------------------------------------------------10------10------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------1------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +--------------------------------------------------------00------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1--1------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +-------------------------------------------------1----------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +--------------------------------------------0----0----------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-----------------------------------------------0-0----------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----1-------------------------------------------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1---------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1-----------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +-------------------------------------------------0-----------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +-------------------------------------------------1------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +-------------------------------------------------0------------------1---- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +-----0--------00----------------------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +-----0--------0----------------1------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ +-----0--------0----------------0------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +----0---------0--------------------------------------------0--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ +----0---------0---------------------------------------------0-0---------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +-------------------------------------------1-----------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +--------------------------------------------------0----------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +----------------------------------------------------1--------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +------------------------------------------------------0------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ +--------------------------------------------------------------0----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +-------------------------------------------------0------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +--------------------------------------------1--1--------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +---------------------------------------------------------------0----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ +------------------------------------------------------------------0-0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ +-------------------------------------------------1-------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +-----------------------------------------------------0---------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +----------------------------------------------------------0----------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ +---------------------------------------------------------------0-----0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ +-------------0--------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +----0-------------------------------------------------0---------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 +------------------------------------------0----------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ +----------1-----------------------------------1--1----------------1-----0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index 08dad3a..529ccb0 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,30 +1,30 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sun May 18 21:01:47 2014 +#$ DATE Thu May 22 14:56:10 2014 #$ MODULE BUS68030 -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 SIZE_0_ A_30_ nEXP_SPACE - A_29_ BERR A_28_ BG_030 A_27_ A_26_ A_25_ BGACK_000 A_24_ CLK_030 A_23_ CLK_000 - A_22_ CLK_OSZI A_21_ CLK_DIV_OUT A_20_ A_19_ A_18_ A_17_ AVEC A_16_ AVEC_EXP VPA - RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ - FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS - DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 22 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC +#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR SIZE_0_ + BG_030 A_30_ A_29_ A_28_ BGACK_000 A_27_ CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI + A_24_ CLK_DIV_OUT A_23_ A_22_ A_21_ A_20_ AVEC A_19_ AVEC_EXP A_18_ A_17_ VPA + A_16_ RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ + DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 + CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ +#$ NODES 23 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 - inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_1_ SM_AMIGA_7_ SM_AMIGA_4_ - SM_AMIGA_1_ CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ - SM_AMIGA_0_ + inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_0_ CLK_REF_1_ SM_AMIGA_7_ + SM_AMIGA_4_ SM_AMIGA_1_ CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_5_ + SM_AMIGA_2_ SM_AMIGA_0_ .type f -.i 72 -.o 120 +.i 73 +.o 122 .ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ - BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q IPL_030_0_.Q AS_000.Q - inst_AS_030_000_SYNC.Q IPL_030_1_.Q inst_DTACK_SYNC.Q inst_VPA_D.Q IPL_030_2_.Q - inst_VPA_SYNC.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q - inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q cpu_est_2_.Q CLK_REF_1_.Q SM_AMIGA_7_.Q - UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q CLK_CNT_0_.Q - CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q - AMIGA_BUS_ENABLE.Q BG_000.Q DSACK_1_.PIN DTACK.PIN + BG_000.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q + inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q IPL_030_0_.Q inst_VPA_D.Q + inst_VPA_SYNC.Q IPL_030_1_.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q IPL_030_2_.Q + inst_CLK_000_D2.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q cpu_est_2_.Q CLK_REF_0_.Q + CLK_REF_1_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_4_.Q + SM_AMIGA_1_.Q CLK_CNT_0_.Q CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q + SM_AMIGA_2_.Q SM_AMIGA_0_.Q AMIGA_BUS_ENABLE.Q DSACK_1_.PIN DTACK.PIN .ob BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AVEC AVEC_EXP AVEC_EXP.OE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE DSACK_0_ DSACK_0_.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D% DSACK_1_.C DSACK_1_.AP @@ -39,125 +39,128 @@ inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_SYNC.D% inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D0.D inst_CLK_000_D0.C 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00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 +-------------------------------------------------1----------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 +-------------------------------------------------1-----------------1----- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 +--------------------------------------------0----0----------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +-----------------------------------------------0-0----------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +-------------------------------------------------0------------------1---- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +------------------------------------------0--------------------------1--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +-------------------------------------------------0-------------------1--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index 35fb4e4..4f9d020 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,30 +1,30 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sun May 18 21:01:47 2014 +#$ DATE Thu May 22 14:56:10 2014 #$ MODULE BUS68030 -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 SIZE_0_ A_30_ nEXP_SPACE - A_29_ BERR A_28_ BG_030 A_27_ A_26_ A_25_ BGACK_000 A_24_ CLK_030 A_23_ CLK_000 - A_22_ CLK_OSZI A_21_ CLK_DIV_OUT A_20_ A_19_ A_18_ A_17_ AVEC A_16_ AVEC_EXP VPA - RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ - FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS - DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 22 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC +#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BERR SIZE_0_ + BG_030 A_30_ A_29_ A_28_ BGACK_000 A_27_ CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI + A_24_ CLK_DIV_OUT A_23_ A_22_ A_21_ A_20_ AVEC A_19_ AVEC_EXP A_18_ A_17_ VPA + A_16_ RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ + DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 + CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ +#$ NODES 23 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 - inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_1_ SM_AMIGA_7_ SM_AMIGA_4_ - SM_AMIGA_1_ CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ - SM_AMIGA_0_ + inst_CLK_OUT_PRE SM_AMIGA_6_ cpu_est_2_ CLK_REF_0_ CLK_REF_1_ SM_AMIGA_7_ + SM_AMIGA_4_ SM_AMIGA_1_ CLK_CNT_0_ CLK_CNT_1_ SM_AMIGA_3_ SM_AMIGA_5_ + SM_AMIGA_2_ SM_AMIGA_0_ .type f -.i 72 -.o 120 +.i 73 +.o 122 .ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ - BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q IPL_030_0_.Q AS_000.Q - inst_AS_030_000_SYNC.Q IPL_030_1_.Q inst_DTACK_SYNC.Q inst_VPA_D.Q IPL_030_2_.Q - inst_VPA_SYNC.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q - inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q cpu_est_2_.Q CLK_REF_1_.Q SM_AMIGA_7_.Q - UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_1_.Q CLK_CNT_0_.Q - CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q - AMIGA_BUS_ENABLE.Q BG_000.Q DSACK_1_.PIN DTACK.PIN + BG_000.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q + inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q IPL_030_0_.Q inst_VPA_D.Q + inst_VPA_SYNC.Q IPL_030_1_.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q IPL_030_2_.Q + inst_CLK_000_D2.Q inst_CLK_OUT_PRE.Q SM_AMIGA_6_.Q cpu_est_2_.Q CLK_REF_0_.Q + CLK_REF_1_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_4_.Q + SM_AMIGA_1_.Q CLK_CNT_0_.Q CLK_CNT_1_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q + SM_AMIGA_2_.Q SM_AMIGA_0_.Q AMIGA_BUS_ENABLE.Q DSACK_1_.PIN DTACK.PIN .ob BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AVEC AVEC_EXP AVEC_EXP.OE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE DSACK_0_ DSACK_0_.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D- DSACK_1_.C DSACK_1_.AP @@ -39,125 +39,128 @@ inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_SYNC.D- inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D0.D inst_CLK_000_D0.C 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00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000 +--------------------------------------------------------1-------01------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000 +--------------------------------------------------------0-------10------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000 +---------------------------------------------------------1------10------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000 +-------------------------------------------------1------------1---------- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 +--------------------------------------------1--1------------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 +-------------------------------------------------1----------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 +-------------------------------------------------1-----------------1----- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 +--------------------------------------------0----0----------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +-----------------------------------------------0-0----------------1------ 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +-------------------------------------------------0------------------1---- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 +------------------------------------------0--------------------------1--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +-------------------------------------------------0-------------------1--- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index adc8366..4e4b052 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 5/18/14; -TIME = 21:01:51; +DATE = 5/22/14; +TIME = 14:56:14; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -155,39 +155,40 @@ AVEC_EXP = OUTPUT,22,2,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-; CLK_EXP = OUTPUT,10,1,-; RESET = OUTPUT,3,1,-; -inst_CLK_000_D1 = NODE,*,6,-; inst_CLK_000_D0 = NODE,*,6,-; +inst_CLK_000_D1 = NODE,*,3,-; +inst_CLK_OUT_PRE = NODE,*,0,-; inst_AS_030_000_SYNC = NODE,*,7,-; -SM_AMIGA_6_ = NODE,*,0,-; -inst_CLK_OUT_PRE = NODE,*,1,-; RN_FPU_CS = NODE,-1,7,-; -RN_AS_000 = NODE,-1,3,-; SM_AMIGA_4_ = NODE,*,1,-; -SM_AMIGA_7_ = NODE,*,1,-; -inst_CLK_000_D2 = NODE,*,6,-; -cpu_est_1_ = NODE,*,3,-; +SM_AMIGA_7_ = NODE,*,7,-; +inst_VPA_D = NODE,*,1,-; +SM_AMIGA_6_ = NODE,*,6,-; +cpu_est_1_ = NODE,*,6,-; RN_E = NODE,-1,6,-; -SM_AMIGA_0_ = NODE,*,6,-; SM_AMIGA_2_ = NODE,*,6,-; -SM_AMIGA_1_ = NODE,*,7,-; -cpu_est_2_ = NODE,*,6,-; -cpu_est_0_ = NODE,*,3,-; +SM_AMIGA_3_ = NODE,*,6,-; +SM_AMIGA_1_ = NODE,*,1,-; +cpu_est_2_ = NODE,*,3,-; +cpu_est_0_ = NODE,*,6,-; RN_VMA = NODE,-1,3,-; RN_BGACK_030 = NODE,-1,7,-; -inst_VPA_D = NODE,*,7,-; +RN_AS_000 = NODE,-1,3,-; +SM_AMIGA_5_ = NODE,*,6,-; +inst_DTACK_SYNC = NODE,*,5,-; +inst_CLK_000_D2 = NODE,*,6,-; RN_LDS_000 = NODE,-1,3,-; RN_UDS_000 = NODE,-1,3,-; +CLK_CNT_1_ = NODE,*,0,-; RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; RN_AMIGA_BUS_ENABLE = NODE,-1,3,-; RN_BG_000 = NODE,-1,3,-; RN_IPL_030_2_ = NODE,-1,1,-; -SM_AMIGA_3_ = NODE,*,6,-; +SM_AMIGA_0_ = NODE,*,7,-; +CLK_CNT_0_ = NODE,*,0,-; RN_DSACK_1_ = NODE,-1,7,-; -SM_AMIGA_5_ = NODE,*,1,-; -CLK_CNT_1_ = NODE,*,1,-; -CLK_CNT_0_ = NODE,*,1,-; inst_VPA_SYNC = NODE,*,6,-; -inst_DTACK_SYNC = NODE,*,6,-; -CLK_REF_1_ = NODE,*,3,-; +CLK_REF_1_ = NODE,*,1,-; +CLK_REF_0_ = NODE,*,3,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index cd2c1d4..18e40ae 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 5/18/14; -TIME = 21:01:51; +DATE = 5/22/14; +TIME = 14:56:14; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -137,33 +137,33 @@ IPL_2_ = INPUT,68, G,-; FC_1_ = INPUT,58, F,-; AS_030 = INPUT,82, H,-; DS_030 = INPUT,98, A,-; -SIZE_0_ = INPUT,70, G,-; -A_30_ = INPUT,5, B,-; nEXP_SPACE = INPUT,14,-,-; -A_29_ = INPUT,6, B,-; BERR = OUTPUT,41, E,-; -A_28_ = INPUT,15, C,-; +SIZE_0_ = INPUT,70, G,-; BG_030 = INPUT,21, C,-; -A_27_ = INPUT,16, C,-; -A_26_ = INPUT,17, C,-; -A_25_ = INPUT,18, C,-; +A_30_ = INPUT,5, B,-; +A_29_ = INPUT,6, B,-; +A_28_ = INPUT,15, C,-; BGACK_000 = INPUT,28, D,-; -A_24_ = INPUT,19, C,-; +A_27_ = INPUT,16, C,-; CLK_030 = INPUT,64,-,-; -A_23_ = INPUT,84, H,-; +A_26_ = INPUT,17, C,-; CLK_000 = INPUT,11,-,-; -A_22_ = INPUT,85, H,-; +A_25_ = INPUT,18, C,-; CLK_OSZI = INPUT,61,-,-; -A_21_ = INPUT,94, A,-; +A_24_ = INPUT,19, C,-; CLK_DIV_OUT = OUTPUT,65, G,-; +A_23_ = INPUT,84, H,-; +A_22_ = INPUT,85, H,-; +A_21_ = INPUT,94, A,-; A_20_ = INPUT,93, A,-; +AVEC = OUTPUT,92, A,-; A_19_ = INPUT,97, A,-; +AVEC_EXP = OUTPUT,22, C,-; A_18_ = INPUT,95, A,-; A_17_ = INPUT,59, F,-; -AVEC = OUTPUT,92, A,-; -A_16_ = INPUT,96, A,-; -AVEC_EXP = OUTPUT,22, C,-; VPA = INPUT,36,-,-; +A_16_ = INPUT,96, A,-; RST = INPUT,86,-,-; RW = INPUT,71, G,-; AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; @@ -190,25 +190,26 @@ RESET = OUTPUT,3, B,-; AMIGA_BUS_ENABLE = OUTPUT,34, D,-; IPL_030_1_ = OUTPUT,7, B,-; IPL_030_0_ = OUTPUT,8, B,-; -cpu_est_0_ = NODE,2, D,-; -cpu_est_1_ = NODE,13, D,-; +cpu_est_0_ = NODE,13, G,-; +cpu_est_1_ = NODE,1, G,-; inst_AS_030_000_SYNC = NODE,1, H,-; -inst_DTACK_SYNC = NODE,10, G,-; -inst_VPA_D = NODE,9, H,-; -inst_VPA_SYNC = NODE,6, G,-; -inst_CLK_000_D0 = NODE,12, G,-; -inst_CLK_000_D1 = NODE,8, G,-; -inst_CLK_000_D2 = NODE,1, G,-; -inst_CLK_OUT_PRE = NODE,5, B,-; -SM_AMIGA_6_ = NODE,0, A,-; -cpu_est_2_ = NODE,13, G,-; -CLK_REF_1_ = NODE,6, D,-; -SM_AMIGA_7_ = NODE,13, B,-; -SM_AMIGA_4_ = NODE,9, B,-; -SM_AMIGA_1_ = NODE,5, H,-; -CLK_CNT_0_ = NODE,10, B,-; -CLK_CNT_1_ = NODE,6, B,-; -SM_AMIGA_3_ = NODE,2, G,-; -SM_AMIGA_5_ = NODE,2, B,-; -SM_AMIGA_2_ = NODE,9, G,-; -SM_AMIGA_0_ = NODE,5, G,-; +inst_DTACK_SYNC = NODE,0, F,-; +inst_VPA_D = NODE,9, B,-; +inst_VPA_SYNC = NODE,10, G,-; +inst_CLK_000_D0 = NODE,8, G,-; +inst_CLK_000_D1 = NODE,13, D,-; +inst_CLK_000_D2 = NODE,6, G,-; +inst_CLK_OUT_PRE = NODE,0, A,-; +SM_AMIGA_6_ = NODE,12, G,-; +cpu_est_2_ = NODE,2, D,-; +CLK_REF_0_ = NODE,6, D,-; +CLK_REF_1_ = NODE,2, B,-; +SM_AMIGA_7_ = NODE,5, H,-; +SM_AMIGA_4_ = NODE,5, B,-; +SM_AMIGA_1_ = NODE,13, B,-; +CLK_CNT_0_ = NODE,12, A,-; +CLK_CNT_1_ = NODE,8, A,-; +SM_AMIGA_3_ = NODE,9, G,-; +SM_AMIGA_5_ = NODE,2, G,-; +SM_AMIGA_2_ = NODE,5, G,-; +SM_AMIGA_0_ = NODE,9, H,-; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index b58e03a..4d4e2b8 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 1.7.00.05.28.13 -Design '68030_tk' created Sun May 18 21:01:47 2014 +Design '68030_tk' created Thu May 22 14:56:10 2014 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index e92f3ce..213d74b 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,135 +1,137 @@ -#$ DATE Sun May 18 21:01:47 2014 +#$ DATE Thu May 22 14:56:10 2014 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 SIZE_0_ LDS_000 A_30_ nEXP_SPACE A_29_ BERR A_28_ BG_030 A_27_ BG_000 A_26_ BGACK_030 A_25_ BGACK_000 A_24_ CLK_030 A_23_ CLK_000 A_22_ CLK_OSZI A_21_ CLK_DIV_OUT A_20_ CLK_EXP A_19_ FPU_CS A_18_ DTACK A_17_ AVEC A_16_ AVEC_EXP A_15_ E A_14_ VPA A_13_ VMA A_12_ RST A_11_ RESET A_10_ RW A_9_ AMIGA_BUS_ENABLE A_8_ AMIGA_BUS_DATA_DIR A_7_ AMIGA_BUS_ENABLE_LOW A_6_ CIIN A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ -#$ NODES 369 BGACK_000_c CLK_030_c CLK_000_c CLK_OSZI_c inst_BGACK_030_INTreg inst_FPU_CS_INTreg cpu_est_3_reg CLK_OUT_INTreg inst_VMA_INTreg cpu_est_0_ \ -# cpu_est_1_ IPL_030DFFSH_0_reg inst_AS_000_INTreg inst_AS_030_000_SYNC IPL_030DFFSH_1_reg inst_DTACK_SYNC inst_VPA_D IPL_030DFFSH_2_reg inst_VPA_SYNC inst_CLK_000_D0 \ -# ipl_c_0__n inst_CLK_000_D1 inst_CLK_000_D2 ipl_c_1__n inst_CLK_OUT_PRE SM_AMIGA_6_ ipl_c_2__n vcc_n_n gnd_n_n cpu_est_2_ \ -# dsack_c_1__n CLK_REF_1_ SM_AMIGA_7_ DTACK_c inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ clk_un4_clk_000_d1_n SM_AMIGA_4_ SM_AMIGA_1_ \ -# inst_DTACK_DMA clk_clk_cnt_n RST_c CLK_CNT_0_ CLK_CNT_1_ RESETDFFreg state_machine_un14_as_000_int_n SM_AMIGA_3_ RW_c fc_c_0__n \ -# un1_as_030_4 SM_AMIGA_5_ fc_c_1__n SM_AMIGA_2_ SM_AMIGA_0_ AMIGA_BUS_ENABLEDFFreg state_machine_lds_000_int_7_n state_machine_uds_000_int_7_n N_101_i N_102_i \ -# N_103_i N_90_0 N_91_0 N_127_i N_128_i CLK_OUT_PRE_0 N_118_i N_125_i cpu_est_0_0_ N_123_i \ -# N_124_i N_126_i clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i N_129_i N_122_i N_121_i N_108_i \ -# G_86 sm_amiga_ns_0_7__n state_machine_un30_clk_000_d1_n state_machine_un8_clk_000_d0_i_n N_147 state_machine_un13_clk_000_d0_i_n N_96 state_machine_un15_clk_000_d0_0_n state_machine_un44_clk_000_d1_n state_machine_un23_clk_000_d0_i_n \ -# G_90 N_100_i N_89 sm_amiga_ns_0_2__n N_97 BG_030_c_i N_90 state_machine_un1_clk_030_0_n N_98 clk_un4_clk_000_d1_i_n \ -# N_99 state_machine_un6_bgack_000_0_n UDS_000_INT_0_sqmuxa state_machine_un17_clk_030_0_n UDS_000_INT_0_sqmuxa_1 un1_as_030_3_0 N_167 N_89_i N_170 AMIGA_BUS_ENABLE_i_m_i \ -# N_105 nEXP_SPACE_m_i N_92 state_machine_amiga_bus_enable_2_iv_i_n N_106 state_machine_as_030_000_sync_3_2_n N_107 N_94_i N_104 un1_bg_030_0 \ -# state_machine_un42_clk_030_n N_105_i un1_bg_030 N_104_i N_94 sm_amiga_ns_0_5__n state_machine_as_030_000_sync_3_n N_106_i AMIGA_BUS_ENABLE_i_m N_107_i \ -# nEXP_SPACE_m N_95 CLK_OUT_PRE_i un1_as_030_3 N_92_0 state_machine_un17_clk_030_n state_machine_un44_clk_000_d1_i_n state_machine_un6_bgack_000_n a_c_i_0__n state_machine_un1_clk_030_n \ -# size_c_i_1__n AS_000_INT_1_sqmuxa N_98_i DSACK_INT_1_sqmuxa N_99_i N_100 sm_amiga_ns_0_1__n state_machine_un23_clk_000_d0_n N_97_i DTACK_SYNC_1_sqmuxa \ -# DTACK_SYNC_1_sqmuxa_1 N_147_i VPA_SYNC_1_sqmuxa state_machine_lds_000_int_7_0_n VPA_SYNC_1_sqmuxa_1 state_machine_uds_000_int_7_0_n state_machine_un15_clk_000_d0_n un1_bg_030_0_1 clk_cpu_est_11_3__n un1_bg_030_0_2 \ -# state_machine_un2_clk_000_n state_machine_as_030_000_sync_3_2_1_n state_machine_un13_clk_000_d0_n clk_cpu_est_11_0_1_1__n state_machine_un8_clk_000_d0_n clk_cpu_est_11_0_2_1__n N_108 N_167_1 state_machine_un13_clk_000_d0_1_n N_167_2 \ -# N_124 N_167_3 N_126 N_167_4 state_machine_un13_clk_000_d0_2_n N_167_5 N_129 N_167_6 N_122 N_170_1 \ -# N_130 N_170_2 N_121 UDS_000_INT_0_sqmuxa_1_1 N_131 UDS_000_INT_0_sqmuxa_1_2 N_127 UDS_000_INT_0_sqmuxa_1_3 clk_cpu_est_11_1__n UDS_000_INT_0_sqmuxa_1_0 \ -# N_128 state_machine_un44_clk_000_d1_i_1_n N_123 state_machine_un42_clk_030_1_n N_125 state_machine_un42_clk_030_2_n N_91 state_machine_un42_clk_030_3_n N_102 state_machine_un42_clk_030_4_n \ -# N_103 state_machine_un42_clk_030_5_n N_101 N_96_1 RW_i AMIGA_BUS_ENABLE_i_m_1 AS_000_INT_i N_131_1 dsack_i_1__n clk_cpu_est_11_0_1_3__n \ -# sm_amiga_i_4__n N_105_1 sm_amiga_i_5__n VPA_SYNC_1_sqmuxa_1_0 CLK_000_D0_i VPA_SYNC_1_sqmuxa_2 sm_amiga_i_3__n VPA_SYNC_1_sqmuxa_3 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_4 \ -# cpu_est_i_2__n VPA_SYNC_1_sqmuxa_5 state_machine_un13_clk_000_d0_2_i_n VPA_SYNC_1_sqmuxa_6 cpu_est_i_3__n DTACK_SYNC_1_sqmuxa_1_0 VPA_D_i DTACK_SYNC_1_sqmuxa_2 cpu_est_i_1__n state_machine_un8_clk_000_d0_1_n \ -# DTACK_i state_machine_un8_clk_000_d0_2_n VMA_INT_i state_machine_un8_clk_000_d0_3_n state_machine_un13_clk_000_d0_1_i_n state_machine_un8_clk_000_d0_4_n AS_030_i state_machine_un13_clk_000_d0_1_0_n DTACK_SYNC_1_sqmuxa_i state_machine_un13_clk_000_d0_2_0_n \ -# VPA_SYNC_1_sqmuxa_i N_127_1 CLK_000_D1_i N_128_1 N_95_i ipl_030_0_2__un3_n N_96_i ipl_030_0_2__un1_n a_i_18__n ipl_030_0_2__un0_n \ -# a_i_16__n ipl_030_0_1__un3_n a_i_19__n ipl_030_0_1__un1_n CLK_030_i ipl_030_0_1__un0_n CLK_000_D2_i ipl_030_0_0__un3_n state_machine_un42_clk_030_i_n ipl_030_0_0__un1_n \ -# sm_amiga_i_6__n ipl_030_0_0__un0_n sm_amiga_i_7__n cpu_est_0_2__un3_n AMIGA_BUS_ENABLE_i cpu_est_0_2__un1_n nEXP_SPACE_i cpu_est_0_2__un0_n sm_amiga_i_2__n cpu_est_0_1__un3_n \ -# sm_amiga_i_1__n cpu_est_0_1__un1_n DS_030_i cpu_est_0_1__un0_n AS_030_000_SYNC_i vpa_sync_0_un3_n UDS_000_INT_0_sqmuxa_1_i vpa_sync_0_un1_n UDS_000_INT_0_sqmuxa_i vpa_sync_0_un0_n \ -# clk_clk_cnt_i_n vma_int_0_un3_n clk_cnt_i_0__n vma_int_0_un1_n a_i_30__n vma_int_0_un0_n a_i_31__n cpu_est_0_3__un3_n a_i_28__n cpu_est_0_3__un1_n \ -# a_i_29__n cpu_est_0_3__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n bgack_030_int_0_un1_n a_i_24__n bgack_030_int_0_un0_n a_i_25__n bg_000_0_un3_n \ -# N_132_i bg_000_0_un1_n bg_000_0_un0_n RST_i amiga_bus_enable_0_un3_n FPU_CS_INT_i amiga_bus_enable_0_un1_n BGACK_030_INT_i amiga_bus_enable_0_un0_n AS_030_c \ -# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n DS_030_c fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n as_000_int_0_un3_n size_c_0__n as_000_int_0_un1_n \ -# as_000_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n a_c_0__n dsack_int_0_1__un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n uds_000_int_0_un3_n \ -# uds_000_int_0_un1_n uds_000_int_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n a_15__n a_14__n a_13__n a_12__n a_c_16__n \ -# a_11__n a_c_17__n a_10__n a_c_18__n a_9__n a_c_19__n a_8__n a_c_20__n a_7__n a_c_21__n \ -# a_6__n a_c_22__n a_5__n a_c_23__n a_4__n a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n \ -# a_1__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c BG_000DFFSHreg +#$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR SIZE_0_ BG_030 A_30_ BG_000 A_29_ BGACK_030 A_28_ BGACK_000 A_27_ CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI A_24_ CLK_DIV_OUT A_23_ CLK_EXP A_22_ FPU_CS A_21_ DTACK A_20_ AVEC A_19_ AVEC_EXP A_18_ E A_17_ VPA A_16_ VMA A_15_ RST A_14_ RESET A_13_ RW A_12_ AMIGA_BUS_ENABLE A_11_ AMIGA_BUS_DATA_DIR A_10_ AMIGA_BUS_ENABLE_LOW A_9_ CIIN A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ +#$ NODES 372 BG_000DFFSHreg BGACK_000_c CLK_030_c inst_BGACK_030_INTreg CLK_000_c inst_FPU_CS_INTreg cpu_est_3_reg CLK_OSZI_c inst_VMA_INTreg cpu_est_0_ \ +# cpu_est_1_ CLK_OUT_INTreg inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC IPL_030DFFSH_0_reg inst_VPA_D inst_VPA_SYNC IPL_030DFFSH_1_reg inst_CLK_000_D0 \ +# inst_CLK_000_D1 IPL_030DFFSH_2_reg inst_CLK_000_D2 inst_CLK_OUT_PRE ipl_c_0__n SM_AMIGA_6_ vcc_n_n ipl_c_1__n gnd_n_n cpu_est_2_ \ +# ipl_c_2__n CLK_REF_0_ CLK_REF_1_ SM_AMIGA_7_ dsack_c_1__n inst_UDS_000_INTreg inst_LDS_000_INTreg DTACK_c DSACK_INT_1_ SM_AMIGA_4_ \ +# SM_AMIGA_1_ inst_DTACK_DMA clk_clk_cnt_n CLK_CNT_0_ CLK_CNT_1_ state_machine_un14_as_000_int_n RST_c SM_AMIGA_3_ RESETDFFreg SM_AMIGA_5_ \ +# RW_c SM_AMIGA_2_ SM_AMIGA_0_ fc_c_0__n fc_c_1__n AMIGA_BUS_ENABLEDFFreg N_101_i N_102_i N_103_i CLK_OUT_PRE_0 \ +# cpu_est_0_0_ N_91_0 N_125_i N_123_i N_124_i N_126_i clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i \ +# N_129_i N_122_i G_86 N_121_i G_87 N_127_i state_machine_un30_clk_000_d1_n N_128_i N_148 N_118_i \ +# DTACK_SYNC_1_sqmuxa state_machine_un8_clk_000_d0_i_n N_96 state_machine_un13_clk_000_d0_i_n G_91 state_machine_un15_clk_000_d0_0_n N_89 N_100_i N_97 sm_amiga_ns_0_2__n \ +# N_90 clk_un4_clk_000_d1_i_n N_98 state_machine_un6_bgack_000_0_n N_99 state_machine_un23_clk_000_d0_i_n N_108 BG_030_c_i UDS_000_INT_0_sqmuxa state_machine_un1_clk_030_0_n \ +# UDS_000_INT_0_sqmuxa_1 state_machine_un17_clk_030_0_n state_machine_un13_clk_000_d0_1_n un1_as_030_3_0 N_168 N_148_i N_171 a_c_i_0__n N_105 state_machine_uds_000_int_7_0_n \ +# N_92 state_machine_lds_000_int_7_0_n N_106 AMIGA_BUS_ENABLE_i_m_i N_107 nEXP_SPACE_m_i N_104 state_machine_amiga_bus_enable_2_iv_i_n state_machine_un42_clk_030_n state_machine_as_030_000_sync_3_2_n \ +# state_machine_un44_clk_000_d1_n N_94_i un1_bg_030 un1_bg_030_0 N_94 size_c_i_1__n state_machine_as_030_000_sync_3_n state_machine_un44_clk_000_d1_i_n AMIGA_BUS_ENABLE_i_m N_105_i \ +# nEXP_SPACE_m N_104_i N_95 sm_amiga_ns_0_5__n state_machine_lds_000_int_7_n N_106_i state_machine_uds_000_int_7_n N_107_i DTACK_SYNC_1_sqmuxa_1 un1_as_030_4 \ +# CLK_OUT_PRE_i un1_as_030_3 N_92_0 DSACK_INT_1_sqmuxa N_90_0 state_machine_un17_clk_030_n N_89_i state_machine_un1_clk_030_n N_108_i state_machine_un23_clk_000_d0_n \ +# sm_amiga_ns_0_7__n VPA_SYNC_1_sqmuxa N_98_i VPA_SYNC_1_sqmuxa_1 N_99_i AS_000_INT_1_sqmuxa sm_amiga_ns_0_1__n state_machine_un6_bgack_000_n N_97_i clk_un4_clk_000_d1_n \ +# N_100 state_machine_un44_clk_000_d1_i_1_n state_machine_un15_clk_000_d0_n un1_bg_030_0_1 clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n state_machine_as_030_000_sync_3_2_1_n state_machine_un13_clk_000_d0_n clk_cpu_est_11_0_1_1__n \ +# state_machine_un8_clk_000_d0_n clk_cpu_est_11_0_2_1__n N_129 N_168_1 N_122 N_168_2 N_130 N_168_3 N_127 N_168_4 \ +# N_128 N_168_5 N_121 N_168_6 state_machine_un13_clk_000_d0_2_n N_171_1 N_131 N_171_2 clk_cpu_est_11_1__n UDS_000_INT_0_sqmuxa_1_1 \ +# N_126 UDS_000_INT_0_sqmuxa_1_2 N_124 UDS_000_INT_0_sqmuxa_1_3 N_123 UDS_000_INT_0_sqmuxa_1_0 N_125 N_96_1 N_91 state_machine_un42_clk_030_1_n \ +# N_102 state_machine_un42_clk_030_2_n N_103 state_machine_un42_clk_030_3_n N_101 state_machine_un42_clk_030_4_n RW_i state_machine_un42_clk_030_5_n AS_000_INT_i AMIGA_BUS_ENABLE_i_m_1 \ +# dsack_i_1__n VPA_SYNC_1_sqmuxa_1_0 sm_amiga_i_4__n VPA_SYNC_1_sqmuxa_2 sm_amiga_i_5__n VPA_SYNC_1_sqmuxa_3 CLK_000_D0_i VPA_SYNC_1_sqmuxa_4 sm_amiga_i_3__n VPA_SYNC_1_sqmuxa_5 \ +# cpu_est_i_0__n VPA_SYNC_1_sqmuxa_6 cpu_est_i_3__n N_127_1 cpu_est_i_2__n N_128_1 VPA_D_i N_131_1 cpu_est_i_1__n clk_cpu_est_11_0_1_3__n \ +# DTACK_i N_105_1 VMA_INT_i DTACK_SYNC_1_sqmuxa_1_0 state_machine_un13_clk_000_d0_2_i_n DTACK_SYNC_1_sqmuxa_2 CLK_000_D1_i state_machine_un8_clk_000_d0_1_n VPA_SYNC_1_sqmuxa_i state_machine_un8_clk_000_d0_2_n \ +# AS_030_i state_machine_un8_clk_000_d0_3_n N_95_i state_machine_un8_clk_000_d0_4_n DTACK_SYNC_1_sqmuxa_i state_machine_un13_clk_000_d0_1_0_n N_96_i state_machine_un13_clk_000_d0_2_0_n a_i_18__n cpu_est_0_1__un3_n \ +# a_i_16__n cpu_est_0_1__un1_n a_i_19__n cpu_est_0_1__un0_n CLK_030_i cpu_est_0_3__un3_n state_machine_un42_clk_030_i_n cpu_est_0_3__un1_n sm_amiga_i_6__n cpu_est_0_3__un0_n \ +# sm_amiga_i_7__n ipl_030_0_0__un3_n AMIGA_BUS_ENABLE_i ipl_030_0_0__un1_n nEXP_SPACE_i ipl_030_0_0__un0_n sm_amiga_i_2__n ipl_030_0_1__un3_n sm_amiga_i_1__n ipl_030_0_1__un1_n \ +# DS_030_i ipl_030_0_1__un0_n AS_030_000_SYNC_i ipl_030_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i ipl_030_0_2__un1_n UDS_000_INT_0_sqmuxa_i ipl_030_0_2__un0_n state_machine_un13_clk_000_d0_1_i_n uds_000_int_0_un3_n \ +# clk_clk_cnt_i_n uds_000_int_0_un1_n clk_cnt_i_0__n uds_000_int_0_un0_n CLK_000_D2_i vpa_sync_0_un3_n a_i_30__n vpa_sync_0_un1_n a_i_31__n vpa_sync_0_un0_n \ +# a_i_28__n as_000_int_0_un3_n a_i_29__n as_000_int_0_un1_n a_i_26__n as_000_int_0_un0_n a_i_27__n bgack_030_int_0_un3_n a_i_24__n bgack_030_int_0_un1_n \ +# a_i_25__n bgack_030_int_0_un0_n N_132_i vma_int_0_un3_n N_133_i vma_int_0_un1_n vma_int_0_un0_n RST_i cpu_est_0_2__un3_n FPU_CS_INT_i \ +# cpu_est_0_2__un1_n BGACK_030_INT_i cpu_est_0_2__un0_n AS_030_c dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n DS_030_c bg_000_0_un3_n bg_000_0_un1_n \ +# bg_000_0_un0_n amiga_bus_enable_0_un3_n size_c_0__n amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n size_c_1__n as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n a_c_0__n as_030_000_sync_0_un0_n \ +# fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n a_15__n \ +# a_14__n a_13__n a_12__n a_c_16__n a_11__n a_c_17__n a_10__n a_c_18__n a_9__n a_c_19__n \ +# a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n a_5__n a_c_23__n a_4__n a_c_24__n \ +# a_3__n a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n \ +# nEXP_SPACE_c BG_030_c .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF \ CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \ A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF \ A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF \ - A_1_.BLIF A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF DSACK_0_.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF CLK_000_c.BLIF CLK_OSZI_c.BLIF \ - inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF cpu_est_3_reg.BLIF CLK_OUT_INTreg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF IPL_030DFFSH_0_reg.BLIF inst_AS_000_INTreg.BLIF \ - inst_AS_030_000_SYNC.BLIF IPL_030DFFSH_1_reg.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF IPL_030DFFSH_2_reg.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF ipl_c_0__n.BLIF inst_CLK_000_D1.BLIF \ - inst_CLK_000_D2.BLIF ipl_c_1__n.BLIF inst_CLK_OUT_PRE.BLIF SM_AMIGA_6_.BLIF ipl_c_2__n.BLIF vcc_n_n.BLIF gnd_n_n.BLIF cpu_est_2_.BLIF dsack_c_1__n.BLIF \ - CLK_REF_1_.BLIF SM_AMIGA_7_.BLIF DTACK_c.BLIF inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF clk_un4_clk_000_d1_n.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF \ - inst_DTACK_DMA.BLIF clk_clk_cnt_n.BLIF RST_c.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF RESETDFFreg.BLIF state_machine_un14_as_000_int_n.BLIF SM_AMIGA_3_.BLIF RW_c.BLIF \ - fc_c_0__n.BLIF un1_as_030_4.BLIF SM_AMIGA_5_.BLIF fc_c_1__n.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF state_machine_lds_000_int_7_n.BLIF state_machine_uds_000_int_7_n.BLIF \ - N_101_i.BLIF N_102_i.BLIF N_103_i.BLIF N_90_0.BLIF N_91_0.BLIF N_127_i.BLIF N_128_i.BLIF CLK_OUT_PRE_0.BLIF N_118_i.BLIF \ - N_125_i.BLIF cpu_est_0_0_.BLIF N_123_i.BLIF N_124_i.BLIF N_126_i.BLIF clk_cpu_est_11_0_1__n.BLIF N_131_i.BLIF clk_cpu_est_11_0_3__n.BLIF N_130_i.BLIF \ - N_129_i.BLIF N_122_i.BLIF N_121_i.BLIF N_108_i.BLIF G_86.BLIF sm_amiga_ns_0_7__n.BLIF state_machine_un30_clk_000_d1_n.BLIF state_machine_un8_clk_000_d0_i_n.BLIF N_147.BLIF \ - state_machine_un13_clk_000_d0_i_n.BLIF N_96.BLIF state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un44_clk_000_d1_n.BLIF state_machine_un23_clk_000_d0_i_n.BLIF G_90.BLIF N_100_i.BLIF N_89.BLIF sm_amiga_ns_0_2__n.BLIF \ - N_97.BLIF BG_030_c_i.BLIF N_90.BLIF state_machine_un1_clk_030_0_n.BLIF N_98.BLIF clk_un4_clk_000_d1_i_n.BLIF N_99.BLIF state_machine_un6_bgack_000_0_n.BLIF UDS_000_INT_0_sqmuxa.BLIF \ - state_machine_un17_clk_030_0_n.BLIF UDS_000_INT_0_sqmuxa_1.BLIF un1_as_030_3_0.BLIF N_167.BLIF N_89_i.BLIF N_170.BLIF AMIGA_BUS_ENABLE_i_m_i.BLIF N_105.BLIF nEXP_SPACE_m_i.BLIF \ - N_92.BLIF state_machine_amiga_bus_enable_2_iv_i_n.BLIF N_106.BLIF state_machine_as_030_000_sync_3_2_n.BLIF N_107.BLIF N_94_i.BLIF N_104.BLIF un1_bg_030_0.BLIF state_machine_un42_clk_030_n.BLIF \ - N_105_i.BLIF un1_bg_030.BLIF N_104_i.BLIF N_94.BLIF sm_amiga_ns_0_5__n.BLIF state_machine_as_030_000_sync_3_n.BLIF N_106_i.BLIF AMIGA_BUS_ENABLE_i_m.BLIF N_107_i.BLIF \ - nEXP_SPACE_m.BLIF N_95.BLIF CLK_OUT_PRE_i.BLIF un1_as_030_3.BLIF N_92_0.BLIF state_machine_un17_clk_030_n.BLIF state_machine_un44_clk_000_d1_i_n.BLIF state_machine_un6_bgack_000_n.BLIF a_c_i_0__n.BLIF \ - state_machine_un1_clk_030_n.BLIF size_c_i_1__n.BLIF AS_000_INT_1_sqmuxa.BLIF N_98_i.BLIF DSACK_INT_1_sqmuxa.BLIF N_99_i.BLIF N_100.BLIF sm_amiga_ns_0_1__n.BLIF state_machine_un23_clk_000_d0_n.BLIF \ - N_97_i.BLIF DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF N_147_i.BLIF VPA_SYNC_1_sqmuxa.BLIF state_machine_lds_000_int_7_0_n.BLIF VPA_SYNC_1_sqmuxa_1.BLIF state_machine_uds_000_int_7_0_n.BLIF state_machine_un15_clk_000_d0_n.BLIF \ - un1_bg_030_0_1.BLIF clk_cpu_est_11_3__n.BLIF un1_bg_030_0_2.BLIF state_machine_un2_clk_000_n.BLIF state_machine_as_030_000_sync_3_2_1_n.BLIF state_machine_un13_clk_000_d0_n.BLIF clk_cpu_est_11_0_1_1__n.BLIF state_machine_un8_clk_000_d0_n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \ - N_108.BLIF N_167_1.BLIF state_machine_un13_clk_000_d0_1_n.BLIF N_167_2.BLIF N_124.BLIF N_167_3.BLIF N_126.BLIF N_167_4.BLIF state_machine_un13_clk_000_d0_2_n.BLIF \ - N_167_5.BLIF N_129.BLIF N_167_6.BLIF N_122.BLIF N_170_1.BLIF N_130.BLIF N_170_2.BLIF N_121.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF \ - N_131.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF N_127.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF clk_cpu_est_11_1__n.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_128.BLIF state_machine_un44_clk_000_d1_i_1_n.BLIF N_123.BLIF \ - state_machine_un42_clk_030_1_n.BLIF N_125.BLIF state_machine_un42_clk_030_2_n.BLIF N_91.BLIF state_machine_un42_clk_030_3_n.BLIF N_102.BLIF state_machine_un42_clk_030_4_n.BLIF N_103.BLIF state_machine_un42_clk_030_5_n.BLIF \ - N_101.BLIF N_96_1.BLIF RW_i.BLIF AMIGA_BUS_ENABLE_i_m_1.BLIF AS_000_INT_i.BLIF N_131_1.BLIF dsack_i_1__n.BLIF clk_cpu_est_11_0_1_3__n.BLIF sm_amiga_i_4__n.BLIF \ - N_105_1.BLIF sm_amiga_i_5__n.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF CLK_000_D0_i.BLIF VPA_SYNC_1_sqmuxa_2.BLIF sm_amiga_i_3__n.BLIF VPA_SYNC_1_sqmuxa_3.BLIF cpu_est_i_0__n.BLIF VPA_SYNC_1_sqmuxa_4.BLIF \ - cpu_est_i_2__n.BLIF VPA_SYNC_1_sqmuxa_5.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF VPA_SYNC_1_sqmuxa_6.BLIF cpu_est_i_3__n.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_D_i.BLIF DTACK_SYNC_1_sqmuxa_2.BLIF cpu_est_i_1__n.BLIF \ - state_machine_un8_clk_000_d0_1_n.BLIF DTACK_i.BLIF state_machine_un8_clk_000_d0_2_n.BLIF VMA_INT_i.BLIF state_machine_un8_clk_000_d0_3_n.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF state_machine_un8_clk_000_d0_4_n.BLIF AS_030_i.BLIF state_machine_un13_clk_000_d0_1_0_n.BLIF \ - DTACK_SYNC_1_sqmuxa_i.BLIF state_machine_un13_clk_000_d0_2_0_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF N_127_1.BLIF CLK_000_D1_i.BLIF N_128_1.BLIF N_95_i.BLIF ipl_030_0_2__un3_n.BLIF N_96_i.BLIF \ - ipl_030_0_2__un1_n.BLIF a_i_18__n.BLIF ipl_030_0_2__un0_n.BLIF a_i_16__n.BLIF ipl_030_0_1__un3_n.BLIF a_i_19__n.BLIF ipl_030_0_1__un1_n.BLIF CLK_030_i.BLIF ipl_030_0_1__un0_n.BLIF \ - CLK_000_D2_i.BLIF ipl_030_0_0__un3_n.BLIF state_machine_un42_clk_030_i_n.BLIF ipl_030_0_0__un1_n.BLIF sm_amiga_i_6__n.BLIF ipl_030_0_0__un0_n.BLIF sm_amiga_i_7__n.BLIF cpu_est_0_2__un3_n.BLIF AMIGA_BUS_ENABLE_i.BLIF \ - cpu_est_0_2__un1_n.BLIF nEXP_SPACE_i.BLIF cpu_est_0_2__un0_n.BLIF sm_amiga_i_2__n.BLIF cpu_est_0_1__un3_n.BLIF sm_amiga_i_1__n.BLIF cpu_est_0_1__un1_n.BLIF DS_030_i.BLIF cpu_est_0_1__un0_n.BLIF \ - AS_030_000_SYNC_i.BLIF vpa_sync_0_un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF vpa_sync_0_un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF vpa_sync_0_un0_n.BLIF clk_clk_cnt_i_n.BLIF vma_int_0_un3_n.BLIF clk_cnt_i_0__n.BLIF \ - vma_int_0_un1_n.BLIF a_i_30__n.BLIF vma_int_0_un0_n.BLIF a_i_31__n.BLIF cpu_est_0_3__un3_n.BLIF a_i_28__n.BLIF cpu_est_0_3__un1_n.BLIF a_i_29__n.BLIF cpu_est_0_3__un0_n.BLIF \ - a_i_26__n.BLIF bgack_030_int_0_un3_n.BLIF a_i_27__n.BLIF bgack_030_int_0_un1_n.BLIF a_i_24__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_25__n.BLIF bg_000_0_un3_n.BLIF N_132_i.BLIF \ - bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF RST_i.BLIF amiga_bus_enable_0_un3_n.BLIF FPU_CS_INT_i.BLIF amiga_bus_enable_0_un1_n.BLIF BGACK_030_INT_i.BLIF amiga_bus_enable_0_un0_n.BLIF AS_030_c.BLIF \ - as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF DS_030_c.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF as_000_int_0_un3_n.BLIF size_c_0__n.BLIF \ - as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF size_c_1__n.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF a_c_0__n.BLIF dsack_int_0_1__un0_n.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF \ - dtack_sync_0_un0_n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_15__n.BLIF a_14__n.BLIF \ - a_13__n.BLIF a_12__n.BLIF a_c_16__n.BLIF a_11__n.BLIF a_c_17__n.BLIF a_10__n.BLIF a_c_18__n.BLIF a_9__n.BLIF a_c_19__n.BLIF \ - a_8__n.BLIF a_c_20__n.BLIF a_7__n.BLIF a_c_21__n.BLIF a_6__n.BLIF a_c_22__n.BLIF a_5__n.BLIF a_c_23__n.BLIF a_4__n.BLIF \ - a_c_24__n.BLIF a_3__n.BLIF a_c_25__n.BLIF a_2__n.BLIF a_c_26__n.BLIF a_1__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF \ - a_c_30__n.BLIF a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF DSACK_1_.PIN DTACK.PIN + A_1_.BLIF A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF DSACK_0_.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF inst_BGACK_030_INTreg.BLIF \ + CLK_000_c.BLIF inst_FPU_CS_INTreg.BLIF cpu_est_3_reg.BLIF CLK_OSZI_c.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF CLK_OUT_INTreg.BLIF inst_AS_000_INTreg.BLIF \ + inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF IPL_030DFFSH_2_reg.BLIF \ + inst_CLK_000_D2.BLIF inst_CLK_OUT_PRE.BLIF ipl_c_0__n.BLIF SM_AMIGA_6_.BLIF vcc_n_n.BLIF ipl_c_1__n.BLIF gnd_n_n.BLIF cpu_est_2_.BLIF ipl_c_2__n.BLIF \ + CLK_REF_0_.BLIF CLK_REF_1_.BLIF SM_AMIGA_7_.BLIF dsack_c_1__n.BLIF inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DTACK_c.BLIF DSACK_INT_1_.BLIF SM_AMIGA_4_.BLIF \ + SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF clk_clk_cnt_n.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF state_machine_un14_as_000_int_n.BLIF RST_c.BLIF SM_AMIGA_3_.BLIF RESETDFFreg.BLIF \ + SM_AMIGA_5_.BLIF RW_c.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF fc_c_0__n.BLIF fc_c_1__n.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF N_101_i.BLIF N_102_i.BLIF \ + N_103_i.BLIF CLK_OUT_PRE_0.BLIF cpu_est_0_0_.BLIF N_91_0.BLIF N_125_i.BLIF N_123_i.BLIF N_124_i.BLIF N_126_i.BLIF clk_cpu_est_11_0_1__n.BLIF \ + N_131_i.BLIF clk_cpu_est_11_0_3__n.BLIF N_130_i.BLIF N_129_i.BLIF N_122_i.BLIF G_86.BLIF N_121_i.BLIF G_87.BLIF N_127_i.BLIF \ + state_machine_un30_clk_000_d1_n.BLIF N_128_i.BLIF N_148.BLIF N_118_i.BLIF DTACK_SYNC_1_sqmuxa.BLIF state_machine_un8_clk_000_d0_i_n.BLIF N_96.BLIF state_machine_un13_clk_000_d0_i_n.BLIF G_91.BLIF \ + state_machine_un15_clk_000_d0_0_n.BLIF N_89.BLIF N_100_i.BLIF N_97.BLIF sm_amiga_ns_0_2__n.BLIF N_90.BLIF clk_un4_clk_000_d1_i_n.BLIF N_98.BLIF state_machine_un6_bgack_000_0_n.BLIF \ + N_99.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_108.BLIF BG_030_c_i.BLIF UDS_000_INT_0_sqmuxa.BLIF state_machine_un1_clk_030_0_n.BLIF UDS_000_INT_0_sqmuxa_1.BLIF state_machine_un17_clk_030_0_n.BLIF state_machine_un13_clk_000_d0_1_n.BLIF \ + un1_as_030_3_0.BLIF N_168.BLIF N_148_i.BLIF N_171.BLIF a_c_i_0__n.BLIF N_105.BLIF state_machine_uds_000_int_7_0_n.BLIF N_92.BLIF state_machine_lds_000_int_7_0_n.BLIF \ + N_106.BLIF AMIGA_BUS_ENABLE_i_m_i.BLIF N_107.BLIF nEXP_SPACE_m_i.BLIF N_104.BLIF state_machine_amiga_bus_enable_2_iv_i_n.BLIF state_machine_un42_clk_030_n.BLIF state_machine_as_030_000_sync_3_2_n.BLIF state_machine_un44_clk_000_d1_n.BLIF \ + N_94_i.BLIF un1_bg_030.BLIF un1_bg_030_0.BLIF N_94.BLIF size_c_i_1__n.BLIF state_machine_as_030_000_sync_3_n.BLIF state_machine_un44_clk_000_d1_i_n.BLIF AMIGA_BUS_ENABLE_i_m.BLIF N_105_i.BLIF \ + nEXP_SPACE_m.BLIF N_104_i.BLIF N_95.BLIF sm_amiga_ns_0_5__n.BLIF state_machine_lds_000_int_7_n.BLIF N_106_i.BLIF state_machine_uds_000_int_7_n.BLIF N_107_i.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF \ + un1_as_030_4.BLIF CLK_OUT_PRE_i.BLIF un1_as_030_3.BLIF N_92_0.BLIF DSACK_INT_1_sqmuxa.BLIF N_90_0.BLIF state_machine_un17_clk_030_n.BLIF N_89_i.BLIF state_machine_un1_clk_030_n.BLIF \ + N_108_i.BLIF state_machine_un23_clk_000_d0_n.BLIF sm_amiga_ns_0_7__n.BLIF VPA_SYNC_1_sqmuxa.BLIF N_98_i.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_99_i.BLIF AS_000_INT_1_sqmuxa.BLIF sm_amiga_ns_0_1__n.BLIF \ + state_machine_un6_bgack_000_n.BLIF N_97_i.BLIF clk_un4_clk_000_d1_n.BLIF N_100.BLIF state_machine_un44_clk_000_d1_i_1_n.BLIF state_machine_un15_clk_000_d0_n.BLIF un1_bg_030_0_1.BLIF clk_cpu_est_11_3__n.BLIF un1_bg_030_0_2.BLIF \ + state_machine_un2_clk_000_n.BLIF state_machine_as_030_000_sync_3_2_1_n.BLIF state_machine_un13_clk_000_d0_n.BLIF clk_cpu_est_11_0_1_1__n.BLIF state_machine_un8_clk_000_d0_n.BLIF clk_cpu_est_11_0_2_1__n.BLIF N_129.BLIF N_168_1.BLIF N_122.BLIF \ + N_168_2.BLIF N_130.BLIF N_168_3.BLIF N_127.BLIF N_168_4.BLIF N_128.BLIF N_168_5.BLIF N_121.BLIF N_168_6.BLIF \ + state_machine_un13_clk_000_d0_2_n.BLIF N_171_1.BLIF N_131.BLIF N_171_2.BLIF clk_cpu_est_11_1__n.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_126.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF N_124.BLIF \ + UDS_000_INT_0_sqmuxa_1_3.BLIF N_123.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_125.BLIF N_96_1.BLIF N_91.BLIF state_machine_un42_clk_030_1_n.BLIF N_102.BLIF state_machine_un42_clk_030_2_n.BLIF \ + N_103.BLIF state_machine_un42_clk_030_3_n.BLIF N_101.BLIF state_machine_un42_clk_030_4_n.BLIF RW_i.BLIF state_machine_un42_clk_030_5_n.BLIF AS_000_INT_i.BLIF AMIGA_BUS_ENABLE_i_m_1.BLIF dsack_i_1__n.BLIF \ + VPA_SYNC_1_sqmuxa_1_0.BLIF sm_amiga_i_4__n.BLIF VPA_SYNC_1_sqmuxa_2.BLIF sm_amiga_i_5__n.BLIF VPA_SYNC_1_sqmuxa_3.BLIF CLK_000_D0_i.BLIF VPA_SYNC_1_sqmuxa_4.BLIF sm_amiga_i_3__n.BLIF VPA_SYNC_1_sqmuxa_5.BLIF \ + cpu_est_i_0__n.BLIF VPA_SYNC_1_sqmuxa_6.BLIF cpu_est_i_3__n.BLIF N_127_1.BLIF cpu_est_i_2__n.BLIF N_128_1.BLIF VPA_D_i.BLIF N_131_1.BLIF cpu_est_i_1__n.BLIF \ + clk_cpu_est_11_0_1_3__n.BLIF DTACK_i.BLIF N_105_1.BLIF VMA_INT_i.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF DTACK_SYNC_1_sqmuxa_2.BLIF CLK_000_D1_i.BLIF state_machine_un8_clk_000_d0_1_n.BLIF \ + VPA_SYNC_1_sqmuxa_i.BLIF state_machine_un8_clk_000_d0_2_n.BLIF AS_030_i.BLIF state_machine_un8_clk_000_d0_3_n.BLIF N_95_i.BLIF state_machine_un8_clk_000_d0_4_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF state_machine_un13_clk_000_d0_1_0_n.BLIF N_96_i.BLIF \ + state_machine_un13_clk_000_d0_2_0_n.BLIF a_i_18__n.BLIF cpu_est_0_1__un3_n.BLIF a_i_16__n.BLIF cpu_est_0_1__un1_n.BLIF a_i_19__n.BLIF cpu_est_0_1__un0_n.BLIF CLK_030_i.BLIF cpu_est_0_3__un3_n.BLIF \ + state_machine_un42_clk_030_i_n.BLIF cpu_est_0_3__un1_n.BLIF sm_amiga_i_6__n.BLIF cpu_est_0_3__un0_n.BLIF sm_amiga_i_7__n.BLIF ipl_030_0_0__un3_n.BLIF AMIGA_BUS_ENABLE_i.BLIF ipl_030_0_0__un1_n.BLIF nEXP_SPACE_i.BLIF \ + ipl_030_0_0__un0_n.BLIF sm_amiga_i_2__n.BLIF ipl_030_0_1__un3_n.BLIF sm_amiga_i_1__n.BLIF ipl_030_0_1__un1_n.BLIF DS_030_i.BLIF ipl_030_0_1__un0_n.BLIF AS_030_000_SYNC_i.BLIF ipl_030_0_2__un3_n.BLIF \ + UDS_000_INT_0_sqmuxa_1_i.BLIF ipl_030_0_2__un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF ipl_030_0_2__un0_n.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF uds_000_int_0_un3_n.BLIF clk_clk_cnt_i_n.BLIF uds_000_int_0_un1_n.BLIF clk_cnt_i_0__n.BLIF \ + uds_000_int_0_un0_n.BLIF CLK_000_D2_i.BLIF vpa_sync_0_un3_n.BLIF a_i_30__n.BLIF vpa_sync_0_un1_n.BLIF a_i_31__n.BLIF vpa_sync_0_un0_n.BLIF a_i_28__n.BLIF as_000_int_0_un3_n.BLIF \ + a_i_29__n.BLIF as_000_int_0_un1_n.BLIF a_i_26__n.BLIF as_000_int_0_un0_n.BLIF a_i_27__n.BLIF bgack_030_int_0_un3_n.BLIF a_i_24__n.BLIF bgack_030_int_0_un1_n.BLIF a_i_25__n.BLIF \ + bgack_030_int_0_un0_n.BLIF N_132_i.BLIF vma_int_0_un3_n.BLIF N_133_i.BLIF vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF RST_i.BLIF cpu_est_0_2__un3_n.BLIF FPU_CS_INT_i.BLIF \ + cpu_est_0_2__un1_n.BLIF BGACK_030_INT_i.BLIF cpu_est_0_2__un0_n.BLIF AS_030_c.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DS_030_c.BLIF bg_000_0_un3_n.BLIF \ + bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF amiga_bus_enable_0_un3_n.BLIF size_c_0__n.BLIF amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF size_c_1__n.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF \ + a_c_0__n.BLIF as_030_000_sync_0_un0_n.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF \ + lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_15__n.BLIF a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_c_16__n.BLIF a_11__n.BLIF a_c_17__n.BLIF \ + a_10__n.BLIF a_c_18__n.BLIF a_9__n.BLIF a_c_19__n.BLIF a_8__n.BLIF a_c_20__n.BLIF a_7__n.BLIF a_c_21__n.BLIF a_6__n.BLIF \ + a_c_22__n.BLIF a_5__n.BLIF a_c_23__n.BLIF a_4__n.BLIF a_c_24__n.BLIF a_3__n.BLIF a_c_25__n.BLIF a_2__n.BLIF a_c_26__n.BLIF \ + a_1__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF DSACK_1_.PIN \ + DTACK.PIN .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ - AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_5_.D \ - SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR \ - SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C IPL_030DFFSH_0_reg.D \ - IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP \ - SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP CLK_CNT_0_.D CLK_CNT_0_.C CLK_CNT_1_.D \ - CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \ - inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \ - DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C \ - inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_D2.D inst_CLK_000_D2.C \ - inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR \ - cpu_est_0_0_.X1 cpu_est_0_0_.X2 G_90.X1 G_90.X2 G_86.X1 G_86.X2 CLK_OUT_PRE_0.X1 CLK_OUT_PRE_0.X2 DSACK_1_ DTACK DSACK_0_ BGACK_000_c CLK_030_c CLK_000_c \ - CLK_OSZI_c ipl_c_0__n ipl_c_1__n ipl_c_2__n vcc_n_n gnd_n_n dsack_c_1__n DTACK_c clk_un4_clk_000_d1_n clk_clk_cnt_n RST_c \ - state_machine_un14_as_000_int_n RW_c fc_c_0__n un1_as_030_4 fc_c_1__n state_machine_lds_000_int_7_n state_machine_uds_000_int_7_n N_101_i N_102_i N_103_i N_90_0 \ - N_91_0 N_127_i N_128_i N_118_i N_125_i N_123_i N_124_i N_126_i clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n \ - N_130_i N_129_i N_122_i N_121_i N_108_i sm_amiga_ns_0_7__n state_machine_un30_clk_000_d1_n state_machine_un8_clk_000_d0_i_n N_147 state_machine_un13_clk_000_d0_i_n N_96 \ - state_machine_un15_clk_000_d0_0_n state_machine_un44_clk_000_d1_n state_machine_un23_clk_000_d0_i_n N_100_i N_89 sm_amiga_ns_0_2__n N_97 BG_030_c_i N_90 state_machine_un1_clk_030_0_n N_98 \ - clk_un4_clk_000_d1_i_n N_99 state_machine_un6_bgack_000_0_n UDS_000_INT_0_sqmuxa state_machine_un17_clk_030_0_n UDS_000_INT_0_sqmuxa_1 un1_as_030_3_0 N_167 N_89_i N_170 AMIGA_BUS_ENABLE_i_m_i \ - N_105 nEXP_SPACE_m_i N_92 state_machine_amiga_bus_enable_2_iv_i_n N_106 state_machine_as_030_000_sync_3_2_n N_107 N_94_i N_104 un1_bg_030_0 state_machine_un42_clk_030_n \ - N_105_i un1_bg_030 N_104_i N_94 sm_amiga_ns_0_5__n state_machine_as_030_000_sync_3_n N_106_i AMIGA_BUS_ENABLE_i_m N_107_i nEXP_SPACE_m N_95 \ - CLK_OUT_PRE_i un1_as_030_3 N_92_0 state_machine_un17_clk_030_n state_machine_un44_clk_000_d1_i_n state_machine_un6_bgack_000_n a_c_i_0__n state_machine_un1_clk_030_n size_c_i_1__n AS_000_INT_1_sqmuxa N_98_i \ - DSACK_INT_1_sqmuxa N_99_i N_100 sm_amiga_ns_0_1__n state_machine_un23_clk_000_d0_n N_97_i DTACK_SYNC_1_sqmuxa DTACK_SYNC_1_sqmuxa_1 N_147_i VPA_SYNC_1_sqmuxa state_machine_lds_000_int_7_0_n \ - VPA_SYNC_1_sqmuxa_1 state_machine_uds_000_int_7_0_n state_machine_un15_clk_000_d0_n un1_bg_030_0_1 clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n state_machine_as_030_000_sync_3_2_1_n state_machine_un13_clk_000_d0_n clk_cpu_est_11_0_1_1__n state_machine_un8_clk_000_d0_n \ - clk_cpu_est_11_0_2_1__n N_108 N_167_1 state_machine_un13_clk_000_d0_1_n N_167_2 N_124 N_167_3 N_126 N_167_4 state_machine_un13_clk_000_d0_2_n N_167_5 \ - N_129 N_167_6 N_122 N_170_1 N_130 N_170_2 N_121 UDS_000_INT_0_sqmuxa_1_1 N_131 UDS_000_INT_0_sqmuxa_1_2 N_127 \ - UDS_000_INT_0_sqmuxa_1_3 clk_cpu_est_11_1__n UDS_000_INT_0_sqmuxa_1_0 N_128 state_machine_un44_clk_000_d1_i_1_n N_123 state_machine_un42_clk_030_1_n N_125 state_machine_un42_clk_030_2_n N_91 state_machine_un42_clk_030_3_n \ - N_102 state_machine_un42_clk_030_4_n N_103 state_machine_un42_clk_030_5_n N_101 N_96_1 RW_i AMIGA_BUS_ENABLE_i_m_1 AS_000_INT_i N_131_1 dsack_i_1__n \ - clk_cpu_est_11_0_1_3__n sm_amiga_i_4__n N_105_1 sm_amiga_i_5__n VPA_SYNC_1_sqmuxa_1_0 CLK_000_D0_i VPA_SYNC_1_sqmuxa_2 sm_amiga_i_3__n VPA_SYNC_1_sqmuxa_3 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_4 \ - cpu_est_i_2__n VPA_SYNC_1_sqmuxa_5 state_machine_un13_clk_000_d0_2_i_n VPA_SYNC_1_sqmuxa_6 cpu_est_i_3__n DTACK_SYNC_1_sqmuxa_1_0 VPA_D_i DTACK_SYNC_1_sqmuxa_2 cpu_est_i_1__n state_machine_un8_clk_000_d0_1_n DTACK_i \ - state_machine_un8_clk_000_d0_2_n VMA_INT_i state_machine_un8_clk_000_d0_3_n state_machine_un13_clk_000_d0_1_i_n state_machine_un8_clk_000_d0_4_n AS_030_i state_machine_un13_clk_000_d0_1_0_n DTACK_SYNC_1_sqmuxa_i state_machine_un13_clk_000_d0_2_0_n VPA_SYNC_1_sqmuxa_i N_127_1 \ - CLK_000_D1_i N_128_1 N_95_i ipl_030_0_2__un3_n N_96_i ipl_030_0_2__un1_n a_i_18__n ipl_030_0_2__un0_n a_i_16__n ipl_030_0_1__un3_n a_i_19__n \ - ipl_030_0_1__un1_n CLK_030_i ipl_030_0_1__un0_n CLK_000_D2_i ipl_030_0_0__un3_n state_machine_un42_clk_030_i_n ipl_030_0_0__un1_n sm_amiga_i_6__n ipl_030_0_0__un0_n sm_amiga_i_7__n cpu_est_0_2__un3_n \ - AMIGA_BUS_ENABLE_i cpu_est_0_2__un1_n nEXP_SPACE_i cpu_est_0_2__un0_n sm_amiga_i_2__n cpu_est_0_1__un3_n sm_amiga_i_1__n cpu_est_0_1__un1_n DS_030_i cpu_est_0_1__un0_n AS_030_000_SYNC_i \ - vpa_sync_0_un3_n UDS_000_INT_0_sqmuxa_1_i vpa_sync_0_un1_n UDS_000_INT_0_sqmuxa_i vpa_sync_0_un0_n clk_clk_cnt_i_n vma_int_0_un3_n clk_cnt_i_0__n vma_int_0_un1_n a_i_30__n vma_int_0_un0_n \ - a_i_31__n cpu_est_0_3__un3_n a_i_28__n cpu_est_0_3__un1_n a_i_29__n cpu_est_0_3__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n bgack_030_int_0_un1_n a_i_24__n \ - bgack_030_int_0_un0_n a_i_25__n bg_000_0_un3_n N_132_i bg_000_0_un1_n bg_000_0_un0_n RST_i amiga_bus_enable_0_un3_n FPU_CS_INT_i amiga_bus_enable_0_un1_n BGACK_030_INT_i \ - amiga_bus_enable_0_un0_n AS_030_c as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n DS_030_c fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n as_000_int_0_un3_n size_c_0__n \ - as_000_int_0_un1_n as_000_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n a_c_0__n dsack_int_0_1__un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n uds_000_int_0_un3_n \ - uds_000_int_0_un1_n uds_000_int_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n a_15__n a_14__n a_13__n a_12__n a_c_16__n a_11__n \ - a_c_17__n a_10__n a_c_18__n a_9__n a_c_19__n a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n \ - a_5__n a_c_23__n a_4__n a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n a_c_28__n \ - a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE \ - LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE + AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D \ + SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \ + SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_1_.D cpu_est_1_.C \ + cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ + IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \ + inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C CLK_CNT_0_.D CLK_CNT_0_.C CLK_CNT_1_.D CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ + inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C \ + BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C \ + inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_CLK_000_D2.D inst_CLK_000_D2.C \ + inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_REF_0_.D CLK_REF_0_.LH CLK_REF_0_.AP \ + CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR cpu_est_0_0_.X1 cpu_est_0_0_.X2 CLK_OUT_PRE_0.X1 CLK_OUT_PRE_0.X2 G_91.X1 G_91.X2 G_87.X1 G_87.X2 \ + G_86.X1 G_86.X2 DSACK_1_ DTACK DSACK_0_ BGACK_000_c CLK_030_c CLK_000_c CLK_OSZI_c ipl_c_0__n vcc_n_n ipl_c_1__n gnd_n_n ipl_c_2__n \ + dsack_c_1__n DTACK_c clk_clk_cnt_n state_machine_un14_as_000_int_n RST_c RW_c fc_c_0__n fc_c_1__n N_101_i N_102_i N_103_i \ + N_91_0 N_125_i N_123_i N_124_i N_126_i clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i N_129_i N_122_i \ + N_121_i N_127_i state_machine_un30_clk_000_d1_n N_128_i N_148 N_118_i DTACK_SYNC_1_sqmuxa state_machine_un8_clk_000_d0_i_n N_96 state_machine_un13_clk_000_d0_i_n state_machine_un15_clk_000_d0_0_n \ + N_89 N_100_i N_97 sm_amiga_ns_0_2__n N_90 clk_un4_clk_000_d1_i_n N_98 state_machine_un6_bgack_000_0_n N_99 state_machine_un23_clk_000_d0_i_n N_108 \ + BG_030_c_i UDS_000_INT_0_sqmuxa state_machine_un1_clk_030_0_n UDS_000_INT_0_sqmuxa_1 state_machine_un17_clk_030_0_n state_machine_un13_clk_000_d0_1_n un1_as_030_3_0 N_168 N_148_i N_171 a_c_i_0__n \ + N_105 state_machine_uds_000_int_7_0_n N_92 state_machine_lds_000_int_7_0_n N_106 AMIGA_BUS_ENABLE_i_m_i N_107 nEXP_SPACE_m_i N_104 state_machine_amiga_bus_enable_2_iv_i_n state_machine_un42_clk_030_n \ + state_machine_as_030_000_sync_3_2_n state_machine_un44_clk_000_d1_n N_94_i un1_bg_030 un1_bg_030_0 N_94 size_c_i_1__n state_machine_as_030_000_sync_3_n state_machine_un44_clk_000_d1_i_n AMIGA_BUS_ENABLE_i_m N_105_i \ + nEXP_SPACE_m N_104_i N_95 sm_amiga_ns_0_5__n state_machine_lds_000_int_7_n N_106_i state_machine_uds_000_int_7_n N_107_i DTACK_SYNC_1_sqmuxa_1 un1_as_030_4 CLK_OUT_PRE_i \ + un1_as_030_3 N_92_0 DSACK_INT_1_sqmuxa N_90_0 state_machine_un17_clk_030_n N_89_i state_machine_un1_clk_030_n N_108_i state_machine_un23_clk_000_d0_n sm_amiga_ns_0_7__n VPA_SYNC_1_sqmuxa \ + N_98_i VPA_SYNC_1_sqmuxa_1 N_99_i AS_000_INT_1_sqmuxa sm_amiga_ns_0_1__n state_machine_un6_bgack_000_n N_97_i clk_un4_clk_000_d1_n N_100 state_machine_un44_clk_000_d1_i_1_n state_machine_un15_clk_000_d0_n \ + un1_bg_030_0_1 clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n state_machine_as_030_000_sync_3_2_1_n state_machine_un13_clk_000_d0_n clk_cpu_est_11_0_1_1__n state_machine_un8_clk_000_d0_n clk_cpu_est_11_0_2_1__n N_129 N_168_1 \ + N_122 N_168_2 N_130 N_168_3 N_127 N_168_4 N_128 N_168_5 N_121 N_168_6 state_machine_un13_clk_000_d0_2_n \ + N_171_1 N_131 N_171_2 clk_cpu_est_11_1__n UDS_000_INT_0_sqmuxa_1_1 N_126 UDS_000_INT_0_sqmuxa_1_2 N_124 UDS_000_INT_0_sqmuxa_1_3 N_123 UDS_000_INT_0_sqmuxa_1_0 \ + N_125 N_96_1 N_91 state_machine_un42_clk_030_1_n N_102 state_machine_un42_clk_030_2_n N_103 state_machine_un42_clk_030_3_n N_101 state_machine_un42_clk_030_4_n RW_i \ + state_machine_un42_clk_030_5_n AS_000_INT_i AMIGA_BUS_ENABLE_i_m_1 dsack_i_1__n VPA_SYNC_1_sqmuxa_1_0 sm_amiga_i_4__n VPA_SYNC_1_sqmuxa_2 sm_amiga_i_5__n VPA_SYNC_1_sqmuxa_3 CLK_000_D0_i VPA_SYNC_1_sqmuxa_4 \ + sm_amiga_i_3__n VPA_SYNC_1_sqmuxa_5 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_6 cpu_est_i_3__n N_127_1 cpu_est_i_2__n N_128_1 VPA_D_i N_131_1 cpu_est_i_1__n \ + clk_cpu_est_11_0_1_3__n DTACK_i N_105_1 VMA_INT_i DTACK_SYNC_1_sqmuxa_1_0 state_machine_un13_clk_000_d0_2_i_n DTACK_SYNC_1_sqmuxa_2 CLK_000_D1_i state_machine_un8_clk_000_d0_1_n VPA_SYNC_1_sqmuxa_i state_machine_un8_clk_000_d0_2_n \ + AS_030_i state_machine_un8_clk_000_d0_3_n N_95_i state_machine_un8_clk_000_d0_4_n DTACK_SYNC_1_sqmuxa_i state_machine_un13_clk_000_d0_1_0_n N_96_i state_machine_un13_clk_000_d0_2_0_n a_i_18__n cpu_est_0_1__un3_n a_i_16__n \ + cpu_est_0_1__un1_n a_i_19__n cpu_est_0_1__un0_n CLK_030_i cpu_est_0_3__un3_n state_machine_un42_clk_030_i_n cpu_est_0_3__un1_n sm_amiga_i_6__n cpu_est_0_3__un0_n sm_amiga_i_7__n ipl_030_0_0__un3_n \ + AMIGA_BUS_ENABLE_i ipl_030_0_0__un1_n nEXP_SPACE_i ipl_030_0_0__un0_n sm_amiga_i_2__n ipl_030_0_1__un3_n sm_amiga_i_1__n ipl_030_0_1__un1_n DS_030_i ipl_030_0_1__un0_n AS_030_000_SYNC_i \ + ipl_030_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i ipl_030_0_2__un1_n UDS_000_INT_0_sqmuxa_i ipl_030_0_2__un0_n state_machine_un13_clk_000_d0_1_i_n uds_000_int_0_un3_n clk_clk_cnt_i_n uds_000_int_0_un1_n clk_cnt_i_0__n uds_000_int_0_un0_n \ + CLK_000_D2_i vpa_sync_0_un3_n a_i_30__n vpa_sync_0_un1_n a_i_31__n vpa_sync_0_un0_n a_i_28__n as_000_int_0_un3_n a_i_29__n as_000_int_0_un1_n a_i_26__n \ + as_000_int_0_un0_n a_i_27__n bgack_030_int_0_un3_n a_i_24__n bgack_030_int_0_un1_n a_i_25__n bgack_030_int_0_un0_n N_132_i vma_int_0_un3_n N_133_i vma_int_0_un1_n \ + vma_int_0_un0_n RST_i cpu_est_0_2__un3_n FPU_CS_INT_i cpu_est_0_2__un1_n BGACK_030_INT_i cpu_est_0_2__un0_n AS_030_c dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n \ + DS_030_c bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n amiga_bus_enable_0_un3_n size_c_0__n amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n size_c_1__n as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n \ + a_c_0__n as_030_000_sync_0_un0_n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n \ + a_15__n a_14__n a_13__n a_12__n a_c_16__n a_11__n a_c_17__n a_10__n a_c_18__n a_9__n a_c_19__n \ + a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n a_5__n a_c_23__n a_4__n a_c_24__n a_3__n \ + a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c \ + DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE .names DSACK_INT_1_.BLIF DSACK_1_ 1 1 .names DSACK_1_.PIN dsack_c_1__n @@ -166,26 +168,132 @@ 1 1 .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 -.names N_170.BLIF CIIN +.names N_171.BLIF CIIN 1 1 -.names N_167.BLIF CIIN.OE +.names N_168.BLIF CIIN.OE 1 1 -.names N_91_0.BLIF N_91 +.names N_102.BLIF N_102_i 0 1 -.names N_127.BLIF N_127_i +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +.names N_103.BLIF N_103_i 0 1 +.names CLK_000_D0_i.BLIF N_101_i.BLIF SM_AMIGA_4_.D +11 1 +.names RST_i.BLIF SM_AMIGA_5_.AR +1 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_103 +11 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names CLK_000_D0_i.BLIF N_91.BLIF N_102 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +1 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names RST_i.BLIF SM_AMIGA_4_.AR +1 1 .names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_101 11 1 .names inst_AS_000_INTreg.BLIF AS_000_INT_i 0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 .names dsack_c_1__n.BLIF dsack_i_1__n 0 1 .names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un14_as_000_int_n 11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un3_n +0 1 +.names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un1_n +11 1 .names RST_i.BLIF SM_AMIGA_3_.AR 1 1 +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +11 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names RW_c.BLIF RW_i +0 1 +.names DTACK_c.BLIF DTACK_i +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names RST_i.BLIF SM_AMIGA_2_.AR +1 1 +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF state_machine_un13_clk_000_d0_1_n +11 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d0_2_n +11 1 +.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d0_2_n.BLIF N_126 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +.names N_121_i.BLIF cpu_est_0_.BLIF N_125 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names RST_i.BLIF SM_AMIGA_1_.AR +1 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_124 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names N_121.BLIF cpu_est_i_0__n.BLIF N_123 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 +.names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_91_0 +11 1 +.names N_102_i.BLIF N_103_i.BLIF SM_AMIGA_3_.D +11 1 +.names RST_i.BLIF SM_AMIGA_0_.AR +1 1 +.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un3_n +0 1 +.names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un1_n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un3_n +0 1 +.names ipl_c_0__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un1_n +11 1 +.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un3_n +0 1 +.names ipl_c_1__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un1_n +11 1 +.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF cpu_est_3_reg.C +1 1 .names clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un3_n 0 1 .names ipl_c_2__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un1_n @@ -195,849 +303,765 @@ .names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D 1- 1 -1 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C -1 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un3_n -0 1 -.names ipl_c_1__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un1_n -11 1 -.names RST_i.BLIF SM_AMIGA_2_.AR -1 1 -.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D -1- 1 --1 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un3_n -0 1 -.names ipl_c_0__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un1_n -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 -.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D -1- 1 --1 1 -.names RST_i.BLIF SM_AMIGA_1_.AR -1 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un3_n -0 1 -.names N_118_i.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un1_n -11 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un3_n -0 1 -.names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un1_n -11 1 -.names RST_i.BLIF SM_AMIGA_0_.AR -1 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n -11 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 -.names RW_c.BLIF RW_i -0 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -.names N_127_i.BLIF N_128_i.BLIF N_118_i -11 1 -.names N_121_i.BLIF cpu_est_0_.BLIF N_125 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names N_121.BLIF cpu_est_i_0__n.BLIF N_123 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_3_reg.C -1 1 -.names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_91_0 -11 1 -.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_90_0 -11 1 -.names N_102_i.BLIF N_103_i.BLIF SM_AMIGA_3_.D -11 1 -.names CLK_000_D0_i.BLIF N_101_i.BLIF SM_AMIGA_4_.D -11 1 .names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C 1 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_103 +.names inst_CLK_000_D0.BLIF CLK_000_c.BLIF state_machine_un2_clk_000_n 11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 .names RST_i.BLIF IPL_030DFFSH_0_reg.AP 1 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names CLK_000_D0_i.BLIF N_91.BLIF N_102 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF clk_un4_clk_000_d1_n 11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C -1 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_124 +.names state_machine_un8_clk_000_d0_i_n.BLIF state_machine_un13_clk_000_d0_i_n.BLIF state_machine_un15_clk_000_d0_0_n 11 1 -.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d0_2_n.BLIF N_126 -11 1 -.names RST_i.BLIF IPL_030DFFSH_1_reg.AP -1 1 .names N_122.BLIF cpu_est_3_reg.BLIF N_129 11 1 .names N_122_i.BLIF cpu_est_i_2__n.BLIF N_130 11 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +1 1 +.names N_127_i.BLIF N_128_i.BLIF N_118_i +11 1 .names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_121_i 11 1 +.names RST_i.BLIF IPL_030DFFSH_1_reg.AP +1 1 .names cpu_est_0_.BLIF cpu_est_1_.BLIF N_122_i 11 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C -1 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names DTACK_c.BLIF DTACK_i -0 1 -.names RST_i.BLIF IPL_030DFFSH_2_reg.AP -1 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF state_machine_un13_clk_000_d0_1_n -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d0_2_n -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C -1 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names RST_i.BLIF SM_AMIGA_7_.AP -1 1 .names state_machine_un13_clk_000_d0_2_n.BLIF state_machine_un13_clk_000_d0_2_i_n 0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names un1_as_030_4.BLIF uds_000_int_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C +1 1 +.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n +11 1 +.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names RST_i.BLIF IPL_030DFFSH_2_reg.AP +1 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D +1- 1 +-1 1 +.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF state_machine_un23_clk_000_d0_i_n +11 1 .names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n 0 1 .names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n 11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C +1 1 .names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n 11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 .names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D 1- 1 -1 1 -.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n -0 1 -.names RST_i.BLIF SM_AMIGA_6_.AR -1 1 -.names N_121.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n -11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D -1- 1 --1 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C -1 1 -.names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un1_n -11 1 -.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D -1- 1 --1 1 -.names inst_CLK_000_D0.BLIF CLK_000_c.BLIF state_machine_un2_clk_000_n -11 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF clk_un4_clk_000_d1_n -11 1 -.names RST_i.BLIF inst_BGACK_030_INTreg.AP -1 1 -.names state_machine_un8_clk_000_d0_i_n.BLIF state_machine_un13_clk_000_d0_i_n.BLIF state_machine_un15_clk_000_d0_0_n -11 1 -.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i -0 1 -.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names CLK_OSZI_c.BLIF CLK_CNT_0_.C -1 1 -.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i -0 1 -.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 -11 1 -.names state_machine_un13_clk_000_d0_1_n.BLIF state_machine_un13_clk_000_d0_1_i_n -0 1 -.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF N_108 -11 1 -.names CLK_OSZI_c.BLIF CLK_CNT_1_.C -1 1 -.names AS_030.BLIF AS_030_c -1 1 -.names N_96_i.BLIF N_108_i.BLIF sm_amiga_ns_0_7__n -11 1 -.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names DS_030.BLIF DS_030_c -1 1 -.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n -11 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D -1- 1 --1 1 -.names SIZE_0_.BLIF size_c_0__n -1 1 -.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n -0 1 -.names SIZE_1_.BLIF size_c_1__n -1 1 -.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n -11 1 -.names A_0_.BLIF a_c_0__n -1 1 -.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -.names A_16_.BLIF a_c_16__n -1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D -1- 1 --1 1 -.names A_17_.BLIF a_c_17__n -1 1 -.names RST_c.BLIF amiga_bus_enable_0_un3_n -0 1 -.names A_18_.BLIF a_c_18__n -1 1 -.names state_machine_amiga_bus_enable_2_iv_i_n.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n -11 1 -.names A_19_.BLIF a_c_19__n -1 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF amiga_bus_enable_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C -1 1 -.names A_20_.BLIF a_c_20__n -1 1 -.names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF AMIGA_BUS_ENABLEDFFreg.D -1- 1 --1 1 -.names A_21_.BLIF a_c_21__n -1 1 -.names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n -0 1 -.names RST_i.BLIF inst_VPA_SYNC.AP -1 1 -.names A_22_.BLIF a_c_22__n -1 1 -.names state_machine_as_030_000_sync_3_n.BLIF state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n -11 1 -.names A_23_.BLIF a_c_23__n -1 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n -11 1 -.names A_24_.BLIF a_c_24__n -1 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D -1- 1 --1 1 -.names A_25_.BLIF a_c_25__n -1 1 -.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C -1 1 -.names A_26_.BLIF a_c_26__n -1 1 -.names un1_as_030_3.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n -11 1 -.names A_27_.BLIF a_c_27__n -1 1 -.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n -11 1 -.names RST_i.BLIF inst_FPU_CS_INTreg.AP -1 1 -.names A_28_.BLIF a_c_28__n -1 1 -.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D -1- 1 --1 1 -.names A_29_.BLIF a_c_29__n +.names RST_i.BLIF SM_AMIGA_7_.AP 1 1 .names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 -.names A_30_.BLIF a_c_30__n -1 1 .names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names A_31_.BLIF a_c_31__n -1 1 .names N_95_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -.names nEXP_SPACE.BLIF nEXP_SPACE_c -1 1 .names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D 1- 1 -1 1 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +11 1 +.names RST_i.BLIF inst_VMA_INTreg.AP +1 1 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +11 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D +1- 1 +-1 1 +.names BGACK_000_c.BLIF clk_un4_clk_000_d1_i_n.BLIF state_machine_un6_bgack_000_0_n +11 1 +.names N_95.BLIF N_95_i +0 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +.names AS_030_i.BLIF N_95_i.BLIF AS_000_INT_1_sqmuxa +11 1 +.names AS_030.BLIF AS_030_c +1 1 +.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i +0 1 +.names RST_i.BLIF inst_BGACK_030_INTreg.AP +1 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names DS_030.BLIF DS_030_c +1 1 +.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 +11 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF N_100 +11 1 +.names N_95_i.BLIF N_100_i.BLIF sm_amiga_ns_0_2__n +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +1 1 +.names SIZE_0_.BLIF size_c_0__n +1 1 +.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n +0 1 +.names SIZE_1_.BLIF size_c_1__n +1 1 +.names N_121.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +11 1 +.names A_0_.BLIF a_c_0__n +1 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names A_16_.BLIF a_c_16__n +1 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF CLK_CNT_0_.C +1 1 +.names A_17_.BLIF a_c_17__n +1 1 +.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un3_n +0 1 +.names A_18_.BLIF a_c_18__n +1 1 +.names N_118_i.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un1_n +11 1 +.names A_19_.BLIF a_c_19__n +1 1 +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names A_20_.BLIF a_c_20__n +1 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF CLK_CNT_1_.C +1 1 +.names A_21_.BLIF a_c_21__n +1 1 +.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n +11 1 +.names A_22_.BLIF a_c_22__n +1 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names A_23_.BLIF a_c_23__n +1 1 +.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n +11 1 +.names A_24_.BLIF a_c_24__n +1 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +.names A_25_.BLIF a_c_25__n +1 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names A_26_.BLIF a_c_26__n +1 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names A_27_.BLIF a_c_27__n +1 1 +.names N_96.BLIF N_96_i +0 1 +.names A_28_.BLIF a_c_28__n +1 1 .names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n 0 1 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP +.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C 1 1 -.names BG_030.BLIF BG_030_c +.names A_29_.BLIF a_c_29__n 1 1 .names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n 11 1 -.names BG_000DFFSHreg.BLIF BG_000 +.names A_30_.BLIF a_c_30__n 1 1 .names N_96_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n 11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030 +.names RST_i.BLIF inst_VPA_SYNC.AP +1 1 +.names A_31_.BLIF a_c_31__n 1 1 .names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D 1- 1 -1 1 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n +0 1 +.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n +11 1 +.names BG_030.BLIF BG_030_c +1 1 +.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C +1 1 +.names BG_000DFFSHreg.BLIF BG_000 +1 1 +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +1- 1 +-1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names RST_c.BLIF amiga_bus_enable_0_un3_n +0 1 +.names RST_i.BLIF inst_FPU_CS_INTreg.AP +1 1 .names BGACK_000.BLIF BGACK_000_c 1 1 -.names N_96.BLIF N_96_i -0 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C -1 1 +.names state_machine_amiga_bus_enable_2_iv_i_n.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n +11 1 .names CLK_030.BLIF CLK_030_c 1 1 -.names AS_030_i.BLIF N_96_i.BLIF DSACK_INT_1_sqmuxa +.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF amiga_bus_enable_0_un0_n 11 1 .names CLK_000.BLIF CLK_000_c 1 1 -.names N_95.BLIF N_95_i -0 1 -.names RST_i.BLIF inst_AS_000_INTreg.AP -1 1 +.names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF AMIGA_BUS_ENABLEDFFreg.D +1- 1 +-1 1 .names CLK_OSZI.BLIF CLK_OSZI_c 1 1 -.names AS_030_i.BLIF N_95_i.BLIF AS_000_INT_1_sqmuxa -11 1 +.names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 .names CLK_OUT_INTreg.BLIF CLK_DIV_OUT 1 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF N_100 +.names state_machine_as_030_000_sync_3_n.BLIF state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n 11 1 .names CLK_OUT_INTreg.BLIF CLK_EXP 1 1 -.names N_95_i.BLIF N_100_i.BLIF sm_amiga_ns_0_2__n +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n 11 1 +.names RST_i.BLIF inst_AS_030_000_SYNC.AP +1 1 .names inst_FPU_CS_INTreg.BLIF FPU_CS 1 1 -.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF state_machine_un23_clk_000_d0_i_n -11 1 -.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C -1 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D +1- 1 +-1 1 .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 -.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n +.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n 0 1 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ 1 1 -.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n +.names un1_as_030_3.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n 11 1 .names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ 1 1 -.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n +.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n 11 1 +.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C +1 1 .names IPL_0_.BLIF ipl_c_0__n 1 1 +.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D +1- 1 +-1 1 +.names IPL_1_.BLIF ipl_c_1__n +1 1 +.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i +0 1 +.names RST_i.BLIF inst_AS_000_INTreg.AP +1 1 +.names IPL_2_.BLIF ipl_c_2__n +1 1 +.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n +0 1 +.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n +11 1 +.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n +11 1 .names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D 1- 1 -1 1 +.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C +1 1 +.names vcc_n_n.BLIF AVEC +1 1 +.names un1_as_030_4.BLIF lds_000_int_0_un3_n +0 1 +.names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n +11 1 +.names cpu_est_3_reg.BLIF E +1 1 +.names state_machine_lds_000_int_7_n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names VPA.BLIF inst_VPA_D.D +1 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D +1- 1 +-1 1 .names CLK_OSZI_c.BLIF BG_000DFFSHreg.C 1 1 -.names IPL_1_.BLIF ipl_c_1__n +.names inst_VMA_INTreg.BLIF VMA 1 1 -.names N_89_i.BLIF SM_AMIGA_6_.BLIF N_95 -11 1 -.names IPL_2_.BLIF ipl_c_2__n +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names RST.BLIF RST_c 1 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i 0 1 .names RST_i.BLIF BG_000DFFSHreg.AP 1 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_94 -11 1 -.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n -0 1 -.names vcc_n_n.BLIF AVEC +.names RESETDFFreg.BLIF RESET 1 1 -.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_3_0 +.names AMIGA_BUS_ENABLE_i_m_i.BLIF nEXP_SPACE_m_i.BLIF state_machine_amiga_bus_enable_2_iv_i_n 11 1 +.names RW.BLIF RW_c +1 1 +.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF nEXP_SPACE_m +11 1 +.names FC_0_.BLIF fc_c_0__n +1 1 +.names N_89_i.BLIF SM_AMIGA_6_.BLIF N_95 +11 1 +.names FC_1_.BLIF fc_c_1__n +1 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 .names CLK_OSZI_c.BLIF DSACK_INT_1_.C 1 1 -.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n -11 1 -.names cpu_est_3_reg.BLIF E +.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE 1 1 -.names BGACK_000_c.BLIF clk_un4_clk_000_d1_i_n.BLIF state_machine_un6_bgack_000_0_n +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names RW_i.BLIF AMIGA_BUS_DATA_DIR +1 1 +.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_94 11 1 .names RST_i.BLIF DSACK_INT_1_.AP 1 1 -.names VPA.BLIF inst_VPA_D.D -1 1 -.names inst_CLK_000_D2.BLIF CLK_000_D2_i -0 1 -.names inst_VMA_INTreg.BLIF VMA -1 1 -.names inst_CLK_000_D1.BLIF CLK_000_D2_i.BLIF state_machine_un30_clk_000_d1_n -11 1 -.names RST.BLIF RST_c -1 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names RESETDFFreg.BLIF RESET -1 1 -.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n -11 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -.names RW.BLIF RW_c -1 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names FC_0_.BLIF fc_c_0__n -1 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names RST_i.BLIF inst_VMA_INTreg.AP -1 1 -.names FC_1_.BLIF fc_c_1__n -1 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE -1 1 -.names RW_i.BLIF AMIGA_BUS_DATA_DIR -1 1 .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 -.names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_92_0 +.names N_148_i.BLIF state_machine_un44_clk_000_d1_n.BLIF state_machine_lds_000_int_7_0_n +11 1 +.names a_c_i_0__n.BLIF N_148_i.BLIF state_machine_uds_000_int_7_0_n +11 1 +.names DTACK_i.BLIF SM_AMIGA_3_.BLIF DTACK_SYNC_1_sqmuxa_1_0 +11 1 +.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 +11 1 +.names inst_VPA_D.BLIF state_machine_un2_clk_000_n.BLIF DTACK_SYNC_1_sqmuxa_2 +11 1 +.names AS_030_i.BLIF N_148.BLIF un1_as_030_4 11 1 .names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C 1 1 -.names N_106_i.BLIF N_107_i.BLIF SM_AMIGA_1_.D +.names DTACK_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa_2.BLIF DTACK_SYNC_1_sqmuxa 11 1 -.names state_machine_un8_clk_000_d0_4_n.BLIF state_machine_un8_clk_000_d0_3_n.BLIF state_machine_un8_clk_000_d0_n +.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n +0 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF state_machine_un8_clk_000_d0_1_n 11 1 -.names N_104_i.BLIF N_105_i.BLIF sm_amiga_ns_0_5__n +.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_3_0 11 1 .names RST_i.BLIF inst_UDS_000_INTreg.AP 1 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF state_machine_un13_clk_000_d0_1_0_n +.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d0_2_n 11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +.names AS_030_i.BLIF N_96_i.BLIF DSACK_INT_1_sqmuxa +11 1 +.names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d0_3_n +11 1 +.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_148 +11 1 +.names state_machine_un8_clk_000_d0_1_n.BLIF state_machine_un8_clk_000_d0_2_n.BLIF state_machine_un8_clk_000_d0_4_n +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i 0 1 -.names state_machine_un13_clk_000_d0_1_n.BLIF state_machine_un13_clk_000_d0_2_n.BLIF state_machine_un13_clk_000_d0_2_0_n +.names state_machine_un8_clk_000_d0_4_n.BLIF state_machine_un8_clk_000_d0_3_n.BLIF state_machine_un8_clk_000_d0_n 11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +.names DS_030_c.BLIF DS_030_i 0 1 -.names state_machine_un13_clk_000_d0_1_0_n.BLIF state_machine_un13_clk_000_d0_2_0_n.BLIF state_machine_un13_clk_000_d0_n -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_107 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_127_1 -11 1 -.names CLK_000_D0_i.BLIF N_92.BLIF N_106 -11 1 .names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C 1 1 -.names N_127_1.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF N_127 +.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF state_machine_un13_clk_000_d0_1_0_n 11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_104 +.names state_machine_un13_clk_000_d0_1_n.BLIF state_machine_un13_clk_000_d0_2_n.BLIF state_machine_un13_clk_000_d0_2_0_n 11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_128_1 -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 .names RST_i.BLIF inst_LDS_000_INTreg.AP 1 1 -.names N_128_1.BLIF cpu_est_i_2__n.BLIF N_128 +.names state_machine_un13_clk_000_d0_1_0_n.BLIF state_machine_un13_clk_000_d0_2_0_n.BLIF state_machine_un13_clk_000_d0_n 11 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i -0 1 -.names N_105_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_105 +.names cpu_est_3_reg.BLIF cpu_est_i_0__n.BLIF VPA_SYNC_1_sqmuxa_3 11 1 -.names AMIGA_BUS_ENABLE_i_m_i.BLIF nEXP_SPACE_m_i.BLIF state_machine_amiga_bus_enable_2_iv_i_n +.names cpu_est_i_1__n.BLIF state_machine_un2_clk_000_n.BLIF VPA_SYNC_1_sqmuxa_4 11 1 -.names SM_AMIGA_3_.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_1_0 +.names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_92_0 11 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF nEXP_SPACE_m +.names VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_5 11 1 -.names VPA_D_i.BLIF cpu_est_2_.BLIF VPA_SYNC_1_sqmuxa_2 -11 1 -.names AS_030_000_SYNC_i.BLIF state_machine_un30_clk_000_d1_n.BLIF N_89_i +.names N_106_i.BLIF N_107_i.BLIF SM_AMIGA_1_.D 11 1 .names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C 1 1 -.names cpu_est_3_reg.BLIF cpu_est_i_0__n.BLIF VPA_SYNC_1_sqmuxa_3 -11 1 -.names CLK_CNT_0_.BLIF clk_cnt_i_0__n -0 1 -.names cpu_est_i_1__n.BLIF state_machine_un2_clk_000_n.BLIF VPA_SYNC_1_sqmuxa_4 -11 1 -.names clk_cnt_i_0__n.BLIF clk_clk_cnt_i_n.BLIF CLK_CNT_0_.D -11 1 -.names RST_i.BLIF inst_DTACK_SYNC.AP -1 1 -.names VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_5 -11 1 -.names clk_clk_cnt_n.BLIF clk_clk_cnt_i_n -0 1 .names VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_6 11 1 -.names clk_clk_cnt_i_n.BLIF G_90.BLIF CLK_CNT_1_.D +.names N_104_i.BLIF N_105_i.BLIF sm_amiga_ns_0_5__n 11 1 .names VPA_SYNC_1_sqmuxa_5.BLIF VPA_SYNC_1_sqmuxa_6.BLIF VPA_SYNC_1_sqmuxa 11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names RST_i.BLIF inst_DTACK_SYNC.AP +1 1 +.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_127_1 +11 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_127_1.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF N_127 +11 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_107 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_128_1 +11 1 +.names CLK_000_D0_i.BLIF N_92.BLIF N_106 +11 1 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +1 1 +.names N_128_1.BLIF cpu_est_i_2__n.BLIF N_128 +11 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_104 +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_131_1 +11 1 +.names clk_cnt_i_0__n.BLIF clk_clk_cnt_i_n.BLIF CLK_CNT_0_.D +11 1 +.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +1 1 +.names N_131_1.BLIF cpu_est_i_2__n.BLIF N_131 +11 1 +.names clk_clk_cnt_n.BLIF clk_clk_cnt_i_n +0 1 +.names N_131_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_1_3__n +11 1 +.names clk_clk_cnt_i_n.BLIF G_91.BLIF CLK_CNT_1_.D +11 1 +.names clk_cpu_est_11_0_1_3__n.BLIF N_130_i.BLIF clk_cpu_est_11_0_3__n +11 1 .names N_90.BLIF sm_amiga_i_7__n.BLIF N_97 11 1 -.names DTACK_i.BLIF SM_AMIGA_3_.BLIF DTACK_SYNC_1_sqmuxa_1_0 +.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_105_1 11 1 .names N_89.BLIF SM_AMIGA_6_.BLIF N_98 11 1 .names CLK_OSZI_c.BLIF inst_DTACK_DMA.C 1 1 -.names inst_VPA_D.BLIF state_machine_un2_clk_000_n.BLIF DTACK_SYNC_1_sqmuxa_2 +.names N_105_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_105 11 1 .names CLK_000_D0_i.BLIF SM_AMIGA_7_.BLIF N_99 11 1 -.names DTACK_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa_2.BLIF DTACK_SYNC_1_sqmuxa -11 1 -.names inst_CLK_000_D0.BLIF N_97_i.BLIF SM_AMIGA_7_.D -11 1 -.names RST_i.BLIF inst_DTACK_DMA.AP -1 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF state_machine_un8_clk_000_d0_1_n -11 1 -.names N_98_i.BLIF N_99_i.BLIF sm_amiga_ns_0_1__n -11 1 -.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d0_2_n -11 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i -0 1 -.names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d0_3_n -11 1 -.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i -0 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D -1 1 -.names state_machine_un8_clk_000_d0_1_n.BLIF state_machine_un8_clk_000_d0_2_n.BLIF state_machine_un8_clk_000_d0_4_n -11 1 -.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_147 -11 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n -11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C -1 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n -11 1 -.names DS_030_c.BLIF DS_030_i -0 1 -.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n -11 1 -.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF state_machine_un42_clk_030_4_n -11 1 -.names G_86.BLIF N_132_i -0 1 -.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D -1 1 -.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF state_machine_un42_clk_030_5_n -11 1 -.names clk_cnt_i_0__n.BLIF N_132_i.BLIF clk_clk_cnt_n -11 1 -.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF state_machine_un42_clk_030_n -11 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C -1 1 -.names CLK_000_D0_i.BLIF inst_CLK_OUT_PRE.BLIF N_96_1 -11 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names N_96_1.BLIF SM_AMIGA_1_.BLIF N_96 -11 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF AMIGA_BUS_ENABLE_i_m_1 -11 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names AMIGA_BUS_ENABLE_i_m_1.BLIF sm_amiga_i_6__n.BLIF AMIGA_BUS_ENABLE_i_m -11 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names CLK_OSZI_c.BLIF inst_VPA_D.C -1 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_131_1 -11 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names N_131_1.BLIF cpu_est_i_2__n.BLIF N_131 -11 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names N_131_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_1_3__n -11 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names CLK_000_c.BLIF inst_CLK_000_D0.D -1 1 -.names clk_cpu_est_11_0_1_3__n.BLIF N_130_i.BLIF clk_cpu_est_11_0_3__n -11 1 -.names AS_030_i.BLIF N_147.BLIF un1_as_030_4 -11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_105_1 -11 1 -.names a_c_i_0__n.BLIF N_147_i.BLIF state_machine_uds_000_int_7_0_n -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C -1 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_167_4 -11 1 -.names N_147_i.BLIF state_machine_un44_clk_000_d1_n.BLIF state_machine_lds_000_int_7_0_n -11 1 -.names N_167_1.BLIF N_167_2.BLIF N_167_5 -11 1 -.names state_machine_un14_as_000_int_n.BLIF inst_DTACK_DMA.D -0 1 -.names N_167_3.BLIF N_167_4.BLIF N_167_6 -11 1 -.names RST_c.BLIF RST_i -0 1 -.names RST_c.BLIF RESETDFFreg.D -1 1 -.names N_167_5.BLIF N_167_6.BLIF N_167 -11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_170_1 -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names CLK_OSZI_c.BLIF RESETDFFreg.C -1 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_170_2 -11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i -0 1 -.names N_170_1.BLIF N_170_2.BLIF N_170 -11 1 -.names un1_as_030_4.BLIF uds_000_int_0_un3_n -0 1 -.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 -11 1 -.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n -11 1 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D -1 1 -.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2 -11 1 -.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF UDS_000_INT_0_sqmuxa_1_3 -11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D -1- 1 --1 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C -1 1 .names UDS_000_INT_0_sqmuxa_1_3.BLIF state_machine_un30_clk_000_d1_n.BLIF UDS_000_INT_0_sqmuxa_1 11 1 -.names un1_as_030_4.BLIF lds_000_int_0_un3_n +.names state_machine_un13_clk_000_d0_1_n.BLIF state_machine_un13_clk_000_d0_1_i_n 0 1 +.names RST_i.BLIF inst_DTACK_DMA.AP +1 1 .names SM_AMIGA_4_.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 11 1 -.names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n +.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF N_108 11 1 .names UDS_000_INT_0_sqmuxa_1_0.BLIF RW_i.BLIF UDS_000_INT_0_sqmuxa 11 1 -.names state_machine_lds_000_int_7_n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +.names inst_CLK_000_D0.BLIF N_97_i.BLIF SM_AMIGA_7_.D 11 1 -.names gnd_n_n.BLIF CLK_REF_1_.D +.names CLK_000_D0_i.BLIF inst_CLK_OUT_PRE.BLIF N_96_1 +11 1 +.names N_98_i.BLIF N_99_i.BLIF sm_amiga_ns_0_1__n +11 1 +.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D 1 1 -.names size_c_i_1__n.BLIF a_c_i_0__n.BLIF state_machine_un44_clk_000_d1_i_1_n +.names N_96_1.BLIF SM_AMIGA_1_.BLIF N_96 11 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D -1- 1 --1 1 -.names state_machine_un44_clk_000_d1_i_1_n.BLIF size_c_0__n.BLIF state_machine_un44_clk_000_d1_i_n +.names N_96_i.BLIF N_108_i.BLIF sm_amiga_ns_0_7__n 11 1 -.names vcc_n_n -1 -.names gnd_n_n.BLIF CLK_REF_1_.LH +.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n +11 1 +.names AS_030_000_SYNC_i.BLIF state_machine_un30_clk_000_d1_n.BLIF N_89_i +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C 1 1 -.names N_97.BLIF N_97_i +.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n +11 1 +.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_90_0 +11 1 +.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n +11 1 +.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i 0 1 -.names gnd_n_n -.names N_147.BLIF N_147_i +.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF state_machine_un42_clk_030_4_n +11 1 +.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i 0 1 -.names A_15_.BLIF a_15__n -1 1 -.names RST_i.BLIF CLK_REF_1_.AR -1 1 -.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n +.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF state_machine_un42_clk_030_5_n +11 1 +.names G_86.BLIF N_132_i 0 1 -.names A_14_.BLIF a_14__n +.names CLK_OSZI_c.BLIF inst_VPA_D.C 1 1 -.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n +.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF state_machine_un42_clk_030_n +11 1 +.names G_87.BLIF N_133_i 0 1 -.names A_13_.BLIF a_13__n -1 1 -.names BG_030_c_i.BLIF N_94_i.BLIF un1_bg_030_0_1 +.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF AMIGA_BUS_ENABLE_i_m_1 11 1 -.names A_12_.BLIF a_12__n -1 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_0_.X1 -1 1 -.names AS_030_c.BLIF nEXP_SPACE_i.BLIF un1_bg_030_0_2 +.names N_132_i.BLIF N_133_i.BLIF clk_clk_cnt_n 11 1 -.names A_11_.BLIF a_11__n -1 1 -.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 +.names AMIGA_BUS_ENABLE_i_m_1.BLIF sm_amiga_i_6__n.BLIF AMIGA_BUS_ENABLE_i_m 11 1 -.names A_10_.BLIF a_10__n +.names a_c_24__n.BLIF a_i_24__n +0 1 +.names CLK_000_c.BLIF inst_CLK_000_D0.D 1 1 -.names cpu_est_0_.BLIF cpu_est_0_0_.X2 -1 1 -.names AS_030_i.BLIF nEXP_SPACE_c.BLIF state_machine_as_030_000_sync_3_2_1_n +.names SM_AMIGA_3_.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_1_0 11 1 -.names A_9_.BLIF a_9__n -1 1 -.names state_machine_as_030_000_sync_3_2_1_n.BLIF state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names VPA_D_i.BLIF cpu_est_2_.BLIF VPA_SYNC_1_sqmuxa_2 11 1 -.names A_8_.BLIF a_8__n -1 1 -.names N_126_i.BLIF N_124_i.BLIF clk_cpu_est_11_0_1_1__n -11 1 -.names A_7_.BLIF a_7__n -1 1 -.names CLK_CNT_0_.BLIF G_90.X1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C 1 1 .names N_123_i.BLIF N_125_i.BLIF clk_cpu_est_11_0_2_1__n 11 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 +.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF clk_cpu_est_11_0_1__n +11 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_168_1 +11 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names RST_c.BLIF RESETDFFreg.D +1 1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_168_2 +11 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_168_3 +11 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names CLK_OSZI_c.BLIF RESETDFFreg.C +1 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_168_4 +11 1 +.names inst_CLK_000_D2.BLIF CLK_000_D2_i +0 1 +.names N_168_1.BLIF N_168_2.BLIF N_168_5 +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D2_i.BLIF state_machine_un30_clk_000_d1_n +11 1 +.names N_168_3.BLIF N_168_4.BLIF N_168_6 +11 1 +.names CLK_CNT_0_.BLIF clk_cnt_i_0__n +0 1 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D +1 1 +.names N_168_5.BLIF N_168_6.BLIF N_168 +11 1 +.names state_machine_un14_as_000_int_n.BLIF inst_DTACK_DMA.D +0 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_171_1 +11 1 +.names RST_c.BLIF RST_i +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C +1 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_171_2 +11 1 +.names N_171_1.BLIF N_171_2.BLIF N_171 +11 1 +.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names gnd_n_n.BLIF CLK_REF_0_.D +1 1 +.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2 +11 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +0 1 +.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF UDS_000_INT_0_sqmuxa_1_3 +11 1 +.names vcc_n_n +1 +.names gnd_n_n.BLIF CLK_REF_0_.LH +1 1 +.names N_89_i.BLIF N_89 +0 1 +.names gnd_n_n +.names N_108.BLIF N_108_i +0 1 +.names A_15_.BLIF a_15__n +1 1 +.names RST_i.BLIF CLK_REF_0_.AP +1 1 +.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D +0 1 +.names A_14_.BLIF a_14__n +1 1 +.names N_98.BLIF N_98_i +0 1 +.names A_13_.BLIF a_13__n +1 1 +.names N_99.BLIF N_99_i +0 1 +.names A_12_.BLIF a_12__n +1 1 +.names gnd_n_n.BLIF CLK_REF_1_.D +1 1 +.names sm_amiga_ns_0_1__n.BLIF SM_AMIGA_6_.D +0 1 +.names A_11_.BLIF a_11__n +1 1 +.names N_97.BLIF N_97_i +0 1 +.names A_10_.BLIF a_10__n +1 1 +.names gnd_n_n.BLIF CLK_REF_1_.LH +1 1 +.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un44_clk_000_d1_i_1_n +11 1 +.names A_9_.BLIF a_9__n +1 1 +.names state_machine_un44_clk_000_d1_i_1_n.BLIF size_c_i_1__n.BLIF state_machine_un44_clk_000_d1_i_n +11 1 +.names A_8_.BLIF a_8__n +1 1 +.names RST_i.BLIF CLK_REF_1_.AR +1 1 +.names BG_030_c_i.BLIF N_94_i.BLIF un1_bg_030_0_1 +11 1 +.names A_7_.BLIF a_7__n +1 1 +.names AS_030_c.BLIF nEXP_SPACE_i.BLIF un1_bg_030_0_2 +11 1 .names A_6_.BLIF a_6__n 1 1 -.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF clk_cpu_est_11_0_1__n +.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 11 1 .names A_5_.BLIF a_5__n 1 1 -.names CLK_CNT_1_.BLIF G_90.X2 +.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_0_.X1 1 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_167_1 +.names AS_030_i.BLIF nEXP_SPACE_c.BLIF state_machine_as_030_000_sync_3_2_1_n 11 1 .names A_4_.BLIF a_4__n 1 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_167_2 +.names state_machine_as_030_000_sync_3_2_1_n.BLIF state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n 11 1 .names A_3_.BLIF a_3__n 1 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_167_3 +.names cpu_est_0_.BLIF cpu_est_0_0_.X2 +1 1 +.names N_126_i.BLIF N_124_i.BLIF clk_cpu_est_11_0_1_1__n 11 1 .names A_2_.BLIF a_2__n 1 1 -.names CLK_CNT_1_.BLIF G_86.X1 -1 1 -.names N_94.BLIF N_94_i +.names AMIGA_BUS_ENABLE_i_m.BLIF AMIGA_BUS_ENABLE_i_m_i 0 1 .names A_1_.BLIF a_1__n 1 1 +.names nEXP_SPACE_m.BLIF nEXP_SPACE_m_i +0 1 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_0.X1 +1 1 +.names state_machine_as_030_000_sync_3_2_n.BLIF state_machine_as_030_000_sync_3_n +0 1 +.names N_94.BLIF N_94_i +0 1 +.names clk_clk_cnt_n.BLIF CLK_OUT_PRE_0.X2 +1 1 .names un1_bg_030_0.BLIF un1_bg_030 0 1 -.names CLK_REF_1_.BLIF G_86.X2 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names state_machine_un44_clk_000_d1_i_n.BLIF state_machine_un44_clk_000_d1_n +0 1 +.names CLK_CNT_0_.BLIF G_91.X1 1 1 .names N_105.BLIF N_105_i 0 1 .names N_104.BLIF N_104_i 0 1 +.names CLK_CNT_1_.BLIF G_91.X2 +1 1 .names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D 0 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_0.X1 -1 1 .names N_106.BLIF N_106_i 0 1 .names N_107.BLIF N_107_i 0 1 -.names clk_clk_cnt_n.BLIF CLK_OUT_PRE_0.X2 +.names CLK_CNT_1_.BLIF G_87.X1 1 1 .names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i 0 1 .names N_92_0.BLIF N_92 0 1 -.names state_machine_un44_clk_000_d1_i_n.BLIF state_machine_un44_clk_000_d1_n -0 1 -.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D +.names CLK_REF_1_.BLIF G_87.X2 1 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 -.names cpu_est_0_0_.BLIF cpu_est_0_.D -1 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names N_98.BLIF N_98_i -0 1 -.names N_99.BLIF N_99_i -0 1 -.names sm_amiga_ns_0_1__n.BLIF SM_AMIGA_6_.D +.names N_90_0.BLIF N_90 0 1 .names state_machine_un13_clk_000_d0_n.BLIF state_machine_un13_clk_000_d0_i_n 0 1 .names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n 0 1 -.names state_machine_un23_clk_000_d0_i_n.BLIF state_machine_un23_clk_000_d0_n -0 1 +.names CLK_CNT_0_.BLIF G_86.X1 +1 1 .names N_100.BLIF N_100_i 0 1 .names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D 0 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n -0 1 +.names CLK_REF_0_.BLIF G_86.X2 +1 1 .names clk_un4_clk_000_d1_n.BLIF clk_un4_clk_000_d1_i_n 0 1 .names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n 0 1 +.names state_machine_un23_clk_000_d0_i_n.BLIF state_machine_un23_clk_000_d0_n +0 1 +.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D +1 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names cpu_est_0_0_.BLIF cpu_est_0_.D +1 1 +.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n +0 1 .names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n 0 1 .names un1_as_030_3_0.BLIF un1_as_030_3 0 1 -.names N_89_i.BLIF N_89 +.names N_148.BLIF N_148_i 0 1 -.names AMIGA_BUS_ENABLE_i_m.BLIF AMIGA_BUS_ENABLE_i_m_i +.names a_c_0__n.BLIF a_c_i_0__n 0 1 -.names nEXP_SPACE_m.BLIF nEXP_SPACE_m_i +.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n 0 1 -.names state_machine_as_030_000_sync_3_2_n.BLIF state_machine_as_030_000_sync_3_n +.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n 0 1 -.names N_128.BLIF N_128_i +.names N_91_0.BLIF N_91 0 1 .names N_125.BLIF N_125_i 0 1 @@ -1059,28 +1083,18 @@ 0 1 .names N_122_i.BLIF N_122 0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 .names N_121_i.BLIF N_121 0 1 -.names N_108.BLIF N_108_i +.names N_127.BLIF N_127_i 0 1 -.names RST_i.BLIF SM_AMIGA_5_.AR +.names RST_i.BLIF SM_AMIGA_6_.AR 1 1 -.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D +.names N_128.BLIF N_128_i 0 1 .names state_machine_un8_clk_000_d0_n.BLIF state_machine_un8_clk_000_d0_i_n 0 1 .names N_101.BLIF N_101_i 0 1 -.names N_102.BLIF N_102_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C -1 1 -.names N_103.BLIF N_103_i -0 1 -.names N_90_0.BLIF N_90 -0 1 -.names RST_i.BLIF SM_AMIGA_4_.AR -1 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index 503f953..52b9523 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,92 +1,92 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sun May 18 21:01:47 2014 +#$ DATE Thu May 22 14:56:10 2014 #$ MODULE bus68030 #$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 \ -# SIZE_0_ LDS_000 A_30_ nEXP_SPACE A_29_ BERR A_28_ BG_030 A_27_ BG_000 A_26_ BGACK_030 \ -# A_25_ BGACK_000 A_24_ CLK_030 A_23_ CLK_000 A_22_ CLK_OSZI A_21_ CLK_DIV_OUT A_20_ \ -# CLK_EXP A_19_ FPU_CS A_18_ DTACK A_17_ AVEC A_16_ AVEC_EXP A_15_ E A_14_ VPA A_13_ VMA A_12_ \ -# RST A_11_ RESET A_10_ RW A_9_ AMIGA_BUS_ENABLE A_8_ AMIGA_BUS_DATA_DIR A_7_ \ -# AMIGA_BUS_ENABLE_LOW A_6_ CIIN A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ \ -# IPL_0_ DSACK_0_ FC_0_ -#$ NODES 369 BGACK_000_c CLK_030_c CLK_000_c CLK_OSZI_c inst_BGACK_030_INTreg \ -# inst_FPU_CS_INTreg cpu_est_3_reg CLK_OUT_INTreg inst_VMA_INTreg cpu_est_0_ \ -# cpu_est_1_ IPL_030DFFSH_0_reg inst_AS_000_INTreg inst_AS_030_000_SYNC \ -# IPL_030DFFSH_1_reg inst_DTACK_SYNC inst_VPA_D IPL_030DFFSH_2_reg inst_VPA_SYNC \ -# inst_CLK_000_D0 ipl_c_0__n inst_CLK_000_D1 inst_CLK_000_D2 ipl_c_1__n \ -# inst_CLK_OUT_PRE SM_AMIGA_6_ ipl_c_2__n vcc_n_n gnd_n_n cpu_est_2_ dsack_c_1__n \ -# CLK_REF_1_ SM_AMIGA_7_ DTACK_c inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ \ -# clk_un4_clk_000_d1_n SM_AMIGA_4_ SM_AMIGA_1_ inst_DTACK_DMA clk_clk_cnt_n RST_c \ -# CLK_CNT_0_ CLK_CNT_1_ RESETDFFreg state_machine_un14_as_000_int_n SM_AMIGA_3_ RW_c \ -# fc_c_0__n un1_as_030_4 SM_AMIGA_5_ fc_c_1__n SM_AMIGA_2_ SM_AMIGA_0_ \ -# AMIGA_BUS_ENABLEDFFreg state_machine_lds_000_int_7_n \ -# state_machine_uds_000_int_7_n N_101_i N_102_i N_103_i N_90_0 N_91_0 N_127_i N_128_i \ -# CLK_OUT_PRE_0 N_118_i N_125_i cpu_est_0_0_ N_123_i N_124_i N_126_i \ -# clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i N_129_i N_122_i N_121_i \ -# N_108_i G_86 sm_amiga_ns_0_7__n state_machine_un30_clk_000_d1_n \ -# state_machine_un8_clk_000_d0_i_n N_147 state_machine_un13_clk_000_d0_i_n N_96 \ -# state_machine_un15_clk_000_d0_0_n state_machine_un44_clk_000_d1_n \ -# state_machine_un23_clk_000_d0_i_n G_90 N_100_i N_89 sm_amiga_ns_0_2__n N_97 \ -# BG_030_c_i N_90 state_machine_un1_clk_030_0_n N_98 clk_un4_clk_000_d1_i_n N_99 \ -# state_machine_un6_bgack_000_0_n UDS_000_INT_0_sqmuxa \ -# state_machine_un17_clk_030_0_n UDS_000_INT_0_sqmuxa_1 un1_as_030_3_0 N_167 N_89_i \ -# N_170 AMIGA_BUS_ENABLE_i_m_i N_105 nEXP_SPACE_m_i N_92 \ -# state_machine_amiga_bus_enable_2_iv_i_n N_106 \ -# state_machine_as_030_000_sync_3_2_n N_107 N_94_i N_104 un1_bg_030_0 \ -# state_machine_un42_clk_030_n N_105_i un1_bg_030 N_104_i N_94 sm_amiga_ns_0_5__n \ -# state_machine_as_030_000_sync_3_n N_106_i AMIGA_BUS_ENABLE_i_m N_107_i \ -# nEXP_SPACE_m N_95 CLK_OUT_PRE_i un1_as_030_3 N_92_0 state_machine_un17_clk_030_n \ -# state_machine_un44_clk_000_d1_i_n state_machine_un6_bgack_000_n a_c_i_0__n \ -# state_machine_un1_clk_030_n size_c_i_1__n AS_000_INT_1_sqmuxa N_98_i \ -# DSACK_INT_1_sqmuxa N_99_i N_100 sm_amiga_ns_0_1__n state_machine_un23_clk_000_d0_n \ -# N_97_i DTACK_SYNC_1_sqmuxa DTACK_SYNC_1_sqmuxa_1 N_147_i VPA_SYNC_1_sqmuxa \ -# state_machine_lds_000_int_7_0_n VPA_SYNC_1_sqmuxa_1 \ -# state_machine_uds_000_int_7_0_n state_machine_un15_clk_000_d0_n un1_bg_030_0_1 \ -# clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n \ +# LDS_000 nEXP_SPACE BERR SIZE_0_ BG_030 A_30_ BG_000 A_29_ BGACK_030 A_28_ BGACK_000 A_27_ \ +# CLK_030 A_26_ CLK_000 A_25_ CLK_OSZI A_24_ CLK_DIV_OUT A_23_ CLK_EXP A_22_ FPU_CS A_21_ \ +# DTACK A_20_ AVEC A_19_ AVEC_EXP A_18_ E A_17_ VPA A_16_ VMA A_15_ RST A_14_ RESET A_13_ RW \ +# A_12_ AMIGA_BUS_ENABLE A_11_ AMIGA_BUS_DATA_DIR A_10_ AMIGA_BUS_ENABLE_LOW A_9_ CIIN \ +# A_8_ A_7_ A_6_ A_5_ A_4_ A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ DSACK_0_ \ +# FC_0_ +#$ NODES 372 BG_000DFFSHreg BGACK_000_c CLK_030_c inst_BGACK_030_INTreg CLK_000_c \ +# inst_FPU_CS_INTreg cpu_est_3_reg CLK_OSZI_c inst_VMA_INTreg cpu_est_0_ cpu_est_1_ \ +# CLK_OUT_INTreg inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC \ +# IPL_030DFFSH_0_reg inst_VPA_D inst_VPA_SYNC IPL_030DFFSH_1_reg inst_CLK_000_D0 \ +# inst_CLK_000_D1 IPL_030DFFSH_2_reg inst_CLK_000_D2 inst_CLK_OUT_PRE ipl_c_0__n \ +# SM_AMIGA_6_ vcc_n_n ipl_c_1__n gnd_n_n cpu_est_2_ ipl_c_2__n CLK_REF_0_ CLK_REF_1_ \ +# SM_AMIGA_7_ dsack_c_1__n inst_UDS_000_INTreg inst_LDS_000_INTreg DTACK_c \ +# DSACK_INT_1_ SM_AMIGA_4_ SM_AMIGA_1_ inst_DTACK_DMA clk_clk_cnt_n CLK_CNT_0_ \ +# CLK_CNT_1_ state_machine_un14_as_000_int_n RST_c SM_AMIGA_3_ RESETDFFreg \ +# SM_AMIGA_5_ RW_c SM_AMIGA_2_ SM_AMIGA_0_ fc_c_0__n fc_c_1__n AMIGA_BUS_ENABLEDFFreg \ +# N_101_i N_102_i N_103_i CLK_OUT_PRE_0 cpu_est_0_0_ N_91_0 N_125_i N_123_i N_124_i \ +# N_126_i clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i N_129_i N_122_i \ +# G_86 N_121_i G_87 N_127_i state_machine_un30_clk_000_d1_n N_128_i N_148 N_118_i \ +# DTACK_SYNC_1_sqmuxa state_machine_un8_clk_000_d0_i_n N_96 \ +# state_machine_un13_clk_000_d0_i_n G_91 state_machine_un15_clk_000_d0_0_n N_89 \ +# N_100_i N_97 sm_amiga_ns_0_2__n N_90 clk_un4_clk_000_d1_i_n N_98 \ +# state_machine_un6_bgack_000_0_n N_99 state_machine_un23_clk_000_d0_i_n N_108 \ +# BG_030_c_i UDS_000_INT_0_sqmuxa state_machine_un1_clk_030_0_n \ +# UDS_000_INT_0_sqmuxa_1 state_machine_un17_clk_030_0_n \ +# state_machine_un13_clk_000_d0_1_n un1_as_030_3_0 N_168 N_148_i N_171 a_c_i_0__n \ +# N_105 state_machine_uds_000_int_7_0_n N_92 state_machine_lds_000_int_7_0_n N_106 \ +# AMIGA_BUS_ENABLE_i_m_i N_107 nEXP_SPACE_m_i N_104 \ +# state_machine_amiga_bus_enable_2_iv_i_n state_machine_un42_clk_030_n \ +# state_machine_as_030_000_sync_3_2_n state_machine_un44_clk_000_d1_n N_94_i \ +# un1_bg_030 un1_bg_030_0 N_94 size_c_i_1__n state_machine_as_030_000_sync_3_n \ +# state_machine_un44_clk_000_d1_i_n AMIGA_BUS_ENABLE_i_m N_105_i nEXP_SPACE_m \ +# N_104_i N_95 sm_amiga_ns_0_5__n state_machine_lds_000_int_7_n N_106_i \ +# state_machine_uds_000_int_7_n N_107_i DTACK_SYNC_1_sqmuxa_1 un1_as_030_4 \ +# CLK_OUT_PRE_i un1_as_030_3 N_92_0 DSACK_INT_1_sqmuxa N_90_0 \ +# state_machine_un17_clk_030_n N_89_i state_machine_un1_clk_030_n N_108_i \ +# state_machine_un23_clk_000_d0_n sm_amiga_ns_0_7__n VPA_SYNC_1_sqmuxa N_98_i \ +# VPA_SYNC_1_sqmuxa_1 N_99_i AS_000_INT_1_sqmuxa sm_amiga_ns_0_1__n \ +# state_machine_un6_bgack_000_n N_97_i clk_un4_clk_000_d1_n N_100 \ +# state_machine_un44_clk_000_d1_i_1_n state_machine_un15_clk_000_d0_n \ +# un1_bg_030_0_1 clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n \ # state_machine_as_030_000_sync_3_2_1_n state_machine_un13_clk_000_d0_n \ # clk_cpu_est_11_0_1_1__n state_machine_un8_clk_000_d0_n clk_cpu_est_11_0_2_1__n \ -# N_108 N_167_1 state_machine_un13_clk_000_d0_1_n N_167_2 N_124 N_167_3 N_126 N_167_4 \ -# state_machine_un13_clk_000_d0_2_n N_167_5 N_129 N_167_6 N_122 N_170_1 N_130 N_170_2 \ -# N_121 UDS_000_INT_0_sqmuxa_1_1 N_131 UDS_000_INT_0_sqmuxa_1_2 N_127 \ -# UDS_000_INT_0_sqmuxa_1_3 clk_cpu_est_11_1__n UDS_000_INT_0_sqmuxa_1_0 N_128 \ -# state_machine_un44_clk_000_d1_i_1_n N_123 state_machine_un42_clk_030_1_n N_125 \ -# state_machine_un42_clk_030_2_n N_91 state_machine_un42_clk_030_3_n N_102 \ -# state_machine_un42_clk_030_4_n N_103 state_machine_un42_clk_030_5_n N_101 N_96_1 \ -# RW_i AMIGA_BUS_ENABLE_i_m_1 AS_000_INT_i N_131_1 dsack_i_1__n \ -# clk_cpu_est_11_0_1_3__n sm_amiga_i_4__n N_105_1 sm_amiga_i_5__n \ -# VPA_SYNC_1_sqmuxa_1_0 CLK_000_D0_i VPA_SYNC_1_sqmuxa_2 sm_amiga_i_3__n \ -# VPA_SYNC_1_sqmuxa_3 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_4 cpu_est_i_2__n \ -# VPA_SYNC_1_sqmuxa_5 state_machine_un13_clk_000_d0_2_i_n VPA_SYNC_1_sqmuxa_6 \ -# cpu_est_i_3__n DTACK_SYNC_1_sqmuxa_1_0 VPA_D_i DTACK_SYNC_1_sqmuxa_2 \ -# cpu_est_i_1__n state_machine_un8_clk_000_d0_1_n DTACK_i \ -# state_machine_un8_clk_000_d0_2_n VMA_INT_i state_machine_un8_clk_000_d0_3_n \ -# state_machine_un13_clk_000_d0_1_i_n state_machine_un8_clk_000_d0_4_n AS_030_i \ -# state_machine_un13_clk_000_d0_1_0_n DTACK_SYNC_1_sqmuxa_i \ -# state_machine_un13_clk_000_d0_2_0_n VPA_SYNC_1_sqmuxa_i N_127_1 CLK_000_D1_i \ -# N_128_1 N_95_i ipl_030_0_2__un3_n N_96_i ipl_030_0_2__un1_n a_i_18__n \ -# ipl_030_0_2__un0_n a_i_16__n ipl_030_0_1__un3_n a_i_19__n ipl_030_0_1__un1_n \ -# CLK_030_i ipl_030_0_1__un0_n CLK_000_D2_i ipl_030_0_0__un3_n \ -# state_machine_un42_clk_030_i_n ipl_030_0_0__un1_n sm_amiga_i_6__n \ -# ipl_030_0_0__un0_n sm_amiga_i_7__n cpu_est_0_2__un3_n AMIGA_BUS_ENABLE_i \ -# cpu_est_0_2__un1_n nEXP_SPACE_i cpu_est_0_2__un0_n sm_amiga_i_2__n \ -# cpu_est_0_1__un3_n sm_amiga_i_1__n cpu_est_0_1__un1_n DS_030_i cpu_est_0_1__un0_n \ -# AS_030_000_SYNC_i vpa_sync_0_un3_n UDS_000_INT_0_sqmuxa_1_i vpa_sync_0_un1_n \ -# UDS_000_INT_0_sqmuxa_i vpa_sync_0_un0_n clk_clk_cnt_i_n vma_int_0_un3_n \ -# clk_cnt_i_0__n vma_int_0_un1_n a_i_30__n vma_int_0_un0_n a_i_31__n \ -# cpu_est_0_3__un3_n a_i_28__n cpu_est_0_3__un1_n a_i_29__n cpu_est_0_3__un0_n \ -# a_i_26__n bgack_030_int_0_un3_n a_i_27__n bgack_030_int_0_un1_n a_i_24__n \ -# bgack_030_int_0_un0_n a_i_25__n bg_000_0_un3_n N_132_i bg_000_0_un1_n \ -# bg_000_0_un0_n RST_i amiga_bus_enable_0_un3_n FPU_CS_INT_i \ -# amiga_bus_enable_0_un1_n BGACK_030_INT_i amiga_bus_enable_0_un0_n AS_030_c \ -# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n DS_030_c \ -# fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n as_000_int_0_un3_n \ -# size_c_0__n as_000_int_0_un1_n as_000_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n \ -# dsack_int_0_1__un1_n a_c_0__n dsack_int_0_1__un0_n dtack_sync_0_un3_n \ -# dtack_sync_0_un1_n dtack_sync_0_un0_n uds_000_int_0_un3_n uds_000_int_0_un1_n \ -# uds_000_int_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n \ -# a_15__n a_14__n a_13__n a_12__n a_c_16__n a_11__n a_c_17__n a_10__n a_c_18__n a_9__n \ -# a_c_19__n a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n a_5__n a_c_23__n a_4__n \ -# a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n a_c_28__n a_c_29__n \ -# a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c BG_000DFFSHreg +# N_129 N_168_1 N_122 N_168_2 N_130 N_168_3 N_127 N_168_4 N_128 N_168_5 N_121 N_168_6 \ +# state_machine_un13_clk_000_d0_2_n N_171_1 N_131 N_171_2 clk_cpu_est_11_1__n \ +# UDS_000_INT_0_sqmuxa_1_1 N_126 UDS_000_INT_0_sqmuxa_1_2 N_124 \ +# UDS_000_INT_0_sqmuxa_1_3 N_123 UDS_000_INT_0_sqmuxa_1_0 N_125 N_96_1 N_91 \ +# state_machine_un42_clk_030_1_n N_102 state_machine_un42_clk_030_2_n N_103 \ +# state_machine_un42_clk_030_3_n N_101 state_machine_un42_clk_030_4_n RW_i \ +# state_machine_un42_clk_030_5_n AS_000_INT_i AMIGA_BUS_ENABLE_i_m_1 dsack_i_1__n \ +# VPA_SYNC_1_sqmuxa_1_0 sm_amiga_i_4__n VPA_SYNC_1_sqmuxa_2 sm_amiga_i_5__n \ +# VPA_SYNC_1_sqmuxa_3 CLK_000_D0_i VPA_SYNC_1_sqmuxa_4 sm_amiga_i_3__n \ +# VPA_SYNC_1_sqmuxa_5 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_6 cpu_est_i_3__n N_127_1 \ +# cpu_est_i_2__n N_128_1 VPA_D_i N_131_1 cpu_est_i_1__n clk_cpu_est_11_0_1_3__n \ +# DTACK_i N_105_1 VMA_INT_i DTACK_SYNC_1_sqmuxa_1_0 \ +# state_machine_un13_clk_000_d0_2_i_n DTACK_SYNC_1_sqmuxa_2 CLK_000_D1_i \ +# state_machine_un8_clk_000_d0_1_n VPA_SYNC_1_sqmuxa_i \ +# state_machine_un8_clk_000_d0_2_n AS_030_i state_machine_un8_clk_000_d0_3_n N_95_i \ +# state_machine_un8_clk_000_d0_4_n DTACK_SYNC_1_sqmuxa_i \ +# state_machine_un13_clk_000_d0_1_0_n N_96_i state_machine_un13_clk_000_d0_2_0_n \ +# a_i_18__n cpu_est_0_1__un3_n a_i_16__n cpu_est_0_1__un1_n a_i_19__n \ +# cpu_est_0_1__un0_n CLK_030_i cpu_est_0_3__un3_n state_machine_un42_clk_030_i_n \ +# cpu_est_0_3__un1_n sm_amiga_i_6__n cpu_est_0_3__un0_n sm_amiga_i_7__n \ +# ipl_030_0_0__un3_n AMIGA_BUS_ENABLE_i ipl_030_0_0__un1_n nEXP_SPACE_i \ +# ipl_030_0_0__un0_n sm_amiga_i_2__n ipl_030_0_1__un3_n sm_amiga_i_1__n \ +# ipl_030_0_1__un1_n DS_030_i ipl_030_0_1__un0_n AS_030_000_SYNC_i \ +# ipl_030_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i ipl_030_0_2__un1_n \ +# UDS_000_INT_0_sqmuxa_i ipl_030_0_2__un0_n state_machine_un13_clk_000_d0_1_i_n \ +# uds_000_int_0_un3_n clk_clk_cnt_i_n uds_000_int_0_un1_n clk_cnt_i_0__n \ +# uds_000_int_0_un0_n CLK_000_D2_i vpa_sync_0_un3_n a_i_30__n vpa_sync_0_un1_n \ +# a_i_31__n vpa_sync_0_un0_n a_i_28__n as_000_int_0_un3_n a_i_29__n \ +# as_000_int_0_un1_n a_i_26__n as_000_int_0_un0_n a_i_27__n bgack_030_int_0_un3_n \ +# a_i_24__n bgack_030_int_0_un1_n a_i_25__n bgack_030_int_0_un0_n N_132_i \ +# vma_int_0_un3_n N_133_i vma_int_0_un1_n vma_int_0_un0_n RST_i cpu_est_0_2__un3_n \ +# FPU_CS_INT_i cpu_est_0_2__un1_n BGACK_030_INT_i cpu_est_0_2__un0_n AS_030_c \ +# dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n DS_030_c \ +# bg_000_0_un3_n bg_000_0_un1_n bg_000_0_un0_n amiga_bus_enable_0_un3_n size_c_0__n \ +# amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n size_c_1__n \ +# as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n a_c_0__n as_030_000_sync_0_un0_n \ +# fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n dtack_sync_0_un3_n \ +# dtack_sync_0_un1_n dtack_sync_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n \ +# lds_000_int_0_un0_n a_15__n a_14__n a_13__n a_12__n a_c_16__n a_11__n a_c_17__n \ +# a_10__n a_c_18__n a_9__n a_c_19__n a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n \ +# a_5__n a_c_23__n a_4__n a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n \ +# a_c_28__n a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c .model bus68030 .inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ @@ -96,223 +96,230 @@ A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF \ A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF \ A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF A_1_.BLIF \ A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF \ -DSACK_0_.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF CLK_000_c.BLIF CLK_OSZI_c.BLIF \ -inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF cpu_est_3_reg.BLIF \ -CLK_OUT_INTreg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ -IPL_030DFFSH_0_reg.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ -IPL_030DFFSH_1_reg.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF \ -IPL_030DFFSH_2_reg.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \ -ipl_c_0__n.BLIF inst_CLK_000_D1.BLIF inst_CLK_000_D2.BLIF ipl_c_1__n.BLIF \ -inst_CLK_OUT_PRE.BLIF SM_AMIGA_6_.BLIF ipl_c_2__n.BLIF vcc_n_n.BLIF \ -gnd_n_n.BLIF cpu_est_2_.BLIF dsack_c_1__n.BLIF CLK_REF_1_.BLIF \ -SM_AMIGA_7_.BLIF DTACK_c.BLIF inst_UDS_000_INTreg.BLIF \ -inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF clk_un4_clk_000_d1_n.BLIF \ -SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF clk_clk_cnt_n.BLIF \ -RST_c.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF RESETDFFreg.BLIF \ -state_machine_un14_as_000_int_n.BLIF SM_AMIGA_3_.BLIF RW_c.BLIF fc_c_0__n.BLIF \ -un1_as_030_4.BLIF SM_AMIGA_5_.BLIF fc_c_1__n.BLIF SM_AMIGA_2_.BLIF \ -SM_AMIGA_0_.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF \ -state_machine_lds_000_int_7_n.BLIF state_machine_uds_000_int_7_n.BLIF \ -N_101_i.BLIF N_102_i.BLIF N_103_i.BLIF N_90_0.BLIF N_91_0.BLIF N_127_i.BLIF \ -N_128_i.BLIF CLK_OUT_PRE_0.BLIF N_118_i.BLIF N_125_i.BLIF cpu_est_0_0_.BLIF \ -N_123_i.BLIF N_124_i.BLIF N_126_i.BLIF clk_cpu_est_11_0_1__n.BLIF N_131_i.BLIF \ -clk_cpu_est_11_0_3__n.BLIF N_130_i.BLIF N_129_i.BLIF N_122_i.BLIF N_121_i.BLIF \ -N_108_i.BLIF G_86.BLIF sm_amiga_ns_0_7__n.BLIF \ -state_machine_un30_clk_000_d1_n.BLIF state_machine_un8_clk_000_d0_i_n.BLIF \ -N_147.BLIF state_machine_un13_clk_000_d0_i_n.BLIF N_96.BLIF \ -state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un44_clk_000_d1_n.BLIF \ -state_machine_un23_clk_000_d0_i_n.BLIF G_90.BLIF N_100_i.BLIF N_89.BLIF \ -sm_amiga_ns_0_2__n.BLIF N_97.BLIF BG_030_c_i.BLIF N_90.BLIF \ -state_machine_un1_clk_030_0_n.BLIF N_98.BLIF clk_un4_clk_000_d1_i_n.BLIF \ -N_99.BLIF state_machine_un6_bgack_000_0_n.BLIF UDS_000_INT_0_sqmuxa.BLIF \ -state_machine_un17_clk_030_0_n.BLIF UDS_000_INT_0_sqmuxa_1.BLIF \ -un1_as_030_3_0.BLIF N_167.BLIF N_89_i.BLIF N_170.BLIF \ -AMIGA_BUS_ENABLE_i_m_i.BLIF N_105.BLIF nEXP_SPACE_m_i.BLIF N_92.BLIF \ -state_machine_amiga_bus_enable_2_iv_i_n.BLIF N_106.BLIF \ -state_machine_as_030_000_sync_3_2_n.BLIF N_107.BLIF N_94_i.BLIF N_104.BLIF \ -un1_bg_030_0.BLIF state_machine_un42_clk_030_n.BLIF N_105_i.BLIF \ -un1_bg_030.BLIF N_104_i.BLIF N_94.BLIF sm_amiga_ns_0_5__n.BLIF \ -state_machine_as_030_000_sync_3_n.BLIF N_106_i.BLIF AMIGA_BUS_ENABLE_i_m.BLIF \ -N_107_i.BLIF nEXP_SPACE_m.BLIF N_95.BLIF CLK_OUT_PRE_i.BLIF un1_as_030_3.BLIF \ -N_92_0.BLIF state_machine_un17_clk_030_n.BLIF \ -state_machine_un44_clk_000_d1_i_n.BLIF state_machine_un6_bgack_000_n.BLIF \ -a_c_i_0__n.BLIF state_machine_un1_clk_030_n.BLIF size_c_i_1__n.BLIF \ -AS_000_INT_1_sqmuxa.BLIF N_98_i.BLIF DSACK_INT_1_sqmuxa.BLIF N_99_i.BLIF \ -N_100.BLIF sm_amiga_ns_0_1__n.BLIF state_machine_un23_clk_000_d0_n.BLIF \ -N_97_i.BLIF DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF N_147_i.BLIF \ -VPA_SYNC_1_sqmuxa.BLIF state_machine_lds_000_int_7_0_n.BLIF \ -VPA_SYNC_1_sqmuxa_1.BLIF state_machine_uds_000_int_7_0_n.BLIF \ +DSACK_0_.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF \ +inst_BGACK_030_INTreg.BLIF CLK_000_c.BLIF inst_FPU_CS_INTreg.BLIF \ +cpu_est_3_reg.BLIF CLK_OSZI_c.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF CLK_OUT_INTreg.BLIF inst_AS_000_INTreg.BLIF \ +inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF IPL_030DFFSH_0_reg.BLIF \ +inst_VPA_D.BLIF inst_VPA_SYNC.BLIF IPL_030DFFSH_1_reg.BLIF \ +inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF IPL_030DFFSH_2_reg.BLIF \ +inst_CLK_000_D2.BLIF inst_CLK_OUT_PRE.BLIF ipl_c_0__n.BLIF SM_AMIGA_6_.BLIF \ +vcc_n_n.BLIF ipl_c_1__n.BLIF gnd_n_n.BLIF cpu_est_2_.BLIF ipl_c_2__n.BLIF \ +CLK_REF_0_.BLIF CLK_REF_1_.BLIF SM_AMIGA_7_.BLIF dsack_c_1__n.BLIF \ +inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DTACK_c.BLIF \ +DSACK_INT_1_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF \ +clk_clk_cnt_n.BLIF CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF \ +state_machine_un14_as_000_int_n.BLIF RST_c.BLIF SM_AMIGA_3_.BLIF \ +RESETDFFreg.BLIF SM_AMIGA_5_.BLIF RW_c.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF \ +fc_c_0__n.BLIF fc_c_1__n.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF N_101_i.BLIF \ +N_102_i.BLIF N_103_i.BLIF CLK_OUT_PRE_0.BLIF cpu_est_0_0_.BLIF N_91_0.BLIF \ +N_125_i.BLIF N_123_i.BLIF N_124_i.BLIF N_126_i.BLIF clk_cpu_est_11_0_1__n.BLIF \ +N_131_i.BLIF clk_cpu_est_11_0_3__n.BLIF N_130_i.BLIF N_129_i.BLIF N_122_i.BLIF \ +G_86.BLIF N_121_i.BLIF G_87.BLIF N_127_i.BLIF \ +state_machine_un30_clk_000_d1_n.BLIF N_128_i.BLIF N_148.BLIF N_118_i.BLIF \ +DTACK_SYNC_1_sqmuxa.BLIF state_machine_un8_clk_000_d0_i_n.BLIF N_96.BLIF \ +state_machine_un13_clk_000_d0_i_n.BLIF G_91.BLIF \ +state_machine_un15_clk_000_d0_0_n.BLIF N_89.BLIF N_100_i.BLIF N_97.BLIF \ +sm_amiga_ns_0_2__n.BLIF N_90.BLIF clk_un4_clk_000_d1_i_n.BLIF N_98.BLIF \ +state_machine_un6_bgack_000_0_n.BLIF N_99.BLIF \ +state_machine_un23_clk_000_d0_i_n.BLIF N_108.BLIF BG_030_c_i.BLIF \ +UDS_000_INT_0_sqmuxa.BLIF state_machine_un1_clk_030_0_n.BLIF \ +UDS_000_INT_0_sqmuxa_1.BLIF state_machine_un17_clk_030_0_n.BLIF \ +state_machine_un13_clk_000_d0_1_n.BLIF un1_as_030_3_0.BLIF N_168.BLIF \ +N_148_i.BLIF N_171.BLIF a_c_i_0__n.BLIF N_105.BLIF \ +state_machine_uds_000_int_7_0_n.BLIF N_92.BLIF \ +state_machine_lds_000_int_7_0_n.BLIF N_106.BLIF AMIGA_BUS_ENABLE_i_m_i.BLIF \ +N_107.BLIF nEXP_SPACE_m_i.BLIF N_104.BLIF \ +state_machine_amiga_bus_enable_2_iv_i_n.BLIF state_machine_un42_clk_030_n.BLIF \ +state_machine_as_030_000_sync_3_2_n.BLIF state_machine_un44_clk_000_d1_n.BLIF \ +N_94_i.BLIF un1_bg_030.BLIF un1_bg_030_0.BLIF N_94.BLIF size_c_i_1__n.BLIF \ +state_machine_as_030_000_sync_3_n.BLIF state_machine_un44_clk_000_d1_i_n.BLIF \ +AMIGA_BUS_ENABLE_i_m.BLIF N_105_i.BLIF nEXP_SPACE_m.BLIF N_104_i.BLIF \ +N_95.BLIF sm_amiga_ns_0_5__n.BLIF state_machine_lds_000_int_7_n.BLIF \ +N_106_i.BLIF state_machine_uds_000_int_7_n.BLIF N_107_i.BLIF \ +DTACK_SYNC_1_sqmuxa_1.BLIF un1_as_030_4.BLIF CLK_OUT_PRE_i.BLIF \ +un1_as_030_3.BLIF N_92_0.BLIF DSACK_INT_1_sqmuxa.BLIF N_90_0.BLIF \ +state_machine_un17_clk_030_n.BLIF N_89_i.BLIF state_machine_un1_clk_030_n.BLIF \ +N_108_i.BLIF state_machine_un23_clk_000_d0_n.BLIF sm_amiga_ns_0_7__n.BLIF \ +VPA_SYNC_1_sqmuxa.BLIF N_98_i.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_99_i.BLIF \ +AS_000_INT_1_sqmuxa.BLIF sm_amiga_ns_0_1__n.BLIF \ +state_machine_un6_bgack_000_n.BLIF N_97_i.BLIF clk_un4_clk_000_d1_n.BLIF \ +N_100.BLIF state_machine_un44_clk_000_d1_i_1_n.BLIF \ state_machine_un15_clk_000_d0_n.BLIF un1_bg_030_0_1.BLIF \ clk_cpu_est_11_3__n.BLIF un1_bg_030_0_2.BLIF state_machine_un2_clk_000_n.BLIF \ state_machine_as_030_000_sync_3_2_1_n.BLIF \ state_machine_un13_clk_000_d0_n.BLIF clk_cpu_est_11_0_1_1__n.BLIF \ -state_machine_un8_clk_000_d0_n.BLIF clk_cpu_est_11_0_2_1__n.BLIF N_108.BLIF \ -N_167_1.BLIF state_machine_un13_clk_000_d0_1_n.BLIF N_167_2.BLIF N_124.BLIF \ -N_167_3.BLIF N_126.BLIF N_167_4.BLIF state_machine_un13_clk_000_d0_2_n.BLIF \ -N_167_5.BLIF N_129.BLIF N_167_6.BLIF N_122.BLIF N_170_1.BLIF N_130.BLIF \ -N_170_2.BLIF N_121.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_131.BLIF \ -UDS_000_INT_0_sqmuxa_1_2.BLIF N_127.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \ -clk_cpu_est_11_1__n.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_128.BLIF \ -state_machine_un44_clk_000_d1_i_1_n.BLIF N_123.BLIF \ -state_machine_un42_clk_030_1_n.BLIF N_125.BLIF \ -state_machine_un42_clk_030_2_n.BLIF N_91.BLIF \ -state_machine_un42_clk_030_3_n.BLIF N_102.BLIF \ -state_machine_un42_clk_030_4_n.BLIF N_103.BLIF \ -state_machine_un42_clk_030_5_n.BLIF N_101.BLIF N_96_1.BLIF RW_i.BLIF \ -AMIGA_BUS_ENABLE_i_m_1.BLIF AS_000_INT_i.BLIF N_131_1.BLIF dsack_i_1__n.BLIF \ -clk_cpu_est_11_0_1_3__n.BLIF sm_amiga_i_4__n.BLIF N_105_1.BLIF \ -sm_amiga_i_5__n.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF CLK_000_D0_i.BLIF \ -VPA_SYNC_1_sqmuxa_2.BLIF sm_amiga_i_3__n.BLIF VPA_SYNC_1_sqmuxa_3.BLIF \ -cpu_est_i_0__n.BLIF VPA_SYNC_1_sqmuxa_4.BLIF cpu_est_i_2__n.BLIF \ -VPA_SYNC_1_sqmuxa_5.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF \ -VPA_SYNC_1_sqmuxa_6.BLIF cpu_est_i_3__n.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF \ -VPA_D_i.BLIF DTACK_SYNC_1_sqmuxa_2.BLIF cpu_est_i_1__n.BLIF \ -state_machine_un8_clk_000_d0_1_n.BLIF DTACK_i.BLIF \ -state_machine_un8_clk_000_d0_2_n.BLIF VMA_INT_i.BLIF \ -state_machine_un8_clk_000_d0_3_n.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF \ -state_machine_un8_clk_000_d0_4_n.BLIF AS_030_i.BLIF \ -state_machine_un13_clk_000_d0_1_0_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF \ -state_machine_un13_clk_000_d0_2_0_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF N_127_1.BLIF \ -CLK_000_D1_i.BLIF N_128_1.BLIF N_95_i.BLIF ipl_030_0_2__un3_n.BLIF N_96_i.BLIF \ -ipl_030_0_2__un1_n.BLIF a_i_18__n.BLIF ipl_030_0_2__un0_n.BLIF a_i_16__n.BLIF \ -ipl_030_0_1__un3_n.BLIF a_i_19__n.BLIF ipl_030_0_1__un1_n.BLIF CLK_030_i.BLIF \ -ipl_030_0_1__un0_n.BLIF CLK_000_D2_i.BLIF ipl_030_0_0__un3_n.BLIF \ -state_machine_un42_clk_030_i_n.BLIF ipl_030_0_0__un1_n.BLIF \ -sm_amiga_i_6__n.BLIF ipl_030_0_0__un0_n.BLIF sm_amiga_i_7__n.BLIF \ -cpu_est_0_2__un3_n.BLIF AMIGA_BUS_ENABLE_i.BLIF cpu_est_0_2__un1_n.BLIF \ -nEXP_SPACE_i.BLIF cpu_est_0_2__un0_n.BLIF sm_amiga_i_2__n.BLIF \ -cpu_est_0_1__un3_n.BLIF sm_amiga_i_1__n.BLIF cpu_est_0_1__un1_n.BLIF \ -DS_030_i.BLIF cpu_est_0_1__un0_n.BLIF AS_030_000_SYNC_i.BLIF \ -vpa_sync_0_un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF vpa_sync_0_un1_n.BLIF \ -UDS_000_INT_0_sqmuxa_i.BLIF vpa_sync_0_un0_n.BLIF clk_clk_cnt_i_n.BLIF \ -vma_int_0_un3_n.BLIF clk_cnt_i_0__n.BLIF vma_int_0_un1_n.BLIF a_i_30__n.BLIF \ -vma_int_0_un0_n.BLIF a_i_31__n.BLIF cpu_est_0_3__un3_n.BLIF a_i_28__n.BLIF \ -cpu_est_0_3__un1_n.BLIF a_i_29__n.BLIF cpu_est_0_3__un0_n.BLIF a_i_26__n.BLIF \ -bgack_030_int_0_un3_n.BLIF a_i_27__n.BLIF bgack_030_int_0_un1_n.BLIF \ -a_i_24__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_25__n.BLIF bg_000_0_un3_n.BLIF \ -N_132_i.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF RST_i.BLIF \ -amiga_bus_enable_0_un3_n.BLIF FPU_CS_INT_i.BLIF amiga_bus_enable_0_un1_n.BLIF \ -BGACK_030_INT_i.BLIF amiga_bus_enable_0_un0_n.BLIF AS_030_c.BLIF \ -as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un1_n.BLIF \ -as_030_000_sync_0_un0_n.BLIF DS_030_c.BLIF fpu_cs_int_0_un3_n.BLIF \ -fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF as_000_int_0_un3_n.BLIF \ -size_c_0__n.BLIF as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF \ -size_c_1__n.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF \ -a_c_0__n.BLIF dsack_int_0_1__un0_n.BLIF dtack_sync_0_un3_n.BLIF \ -dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF \ -lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_15__n.BLIF a_14__n.BLIF \ -a_13__n.BLIF a_12__n.BLIF a_c_16__n.BLIF a_11__n.BLIF a_c_17__n.BLIF \ -a_10__n.BLIF a_c_18__n.BLIF a_9__n.BLIF a_c_19__n.BLIF a_8__n.BLIF \ -a_c_20__n.BLIF a_7__n.BLIF a_c_21__n.BLIF a_6__n.BLIF a_c_22__n.BLIF \ -a_5__n.BLIF a_c_23__n.BLIF a_4__n.BLIF a_c_24__n.BLIF a_3__n.BLIF \ -a_c_25__n.BLIF a_2__n.BLIF a_c_26__n.BLIF a_1__n.BLIF a_c_27__n.BLIF \ -a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF nEXP_SPACE_c.BLIF \ -BG_030_c.BLIF BG_000DFFSHreg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +state_machine_un8_clk_000_d0_n.BLIF clk_cpu_est_11_0_2_1__n.BLIF N_129.BLIF \ +N_168_1.BLIF N_122.BLIF N_168_2.BLIF N_130.BLIF N_168_3.BLIF N_127.BLIF \ +N_168_4.BLIF N_128.BLIF N_168_5.BLIF N_121.BLIF N_168_6.BLIF \ +state_machine_un13_clk_000_d0_2_n.BLIF N_171_1.BLIF N_131.BLIF N_171_2.BLIF \ +clk_cpu_est_11_1__n.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_126.BLIF \ +UDS_000_INT_0_sqmuxa_1_2.BLIF N_124.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \ +N_123.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_125.BLIF N_96_1.BLIF N_91.BLIF \ +state_machine_un42_clk_030_1_n.BLIF N_102.BLIF \ +state_machine_un42_clk_030_2_n.BLIF N_103.BLIF \ +state_machine_un42_clk_030_3_n.BLIF N_101.BLIF \ +state_machine_un42_clk_030_4_n.BLIF RW_i.BLIF \ +state_machine_un42_clk_030_5_n.BLIF AS_000_INT_i.BLIF \ +AMIGA_BUS_ENABLE_i_m_1.BLIF dsack_i_1__n.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \ +sm_amiga_i_4__n.BLIF VPA_SYNC_1_sqmuxa_2.BLIF sm_amiga_i_5__n.BLIF \ +VPA_SYNC_1_sqmuxa_3.BLIF CLK_000_D0_i.BLIF VPA_SYNC_1_sqmuxa_4.BLIF \ +sm_amiga_i_3__n.BLIF VPA_SYNC_1_sqmuxa_5.BLIF cpu_est_i_0__n.BLIF \ +VPA_SYNC_1_sqmuxa_6.BLIF cpu_est_i_3__n.BLIF N_127_1.BLIF cpu_est_i_2__n.BLIF \ +N_128_1.BLIF VPA_D_i.BLIF N_131_1.BLIF cpu_est_i_1__n.BLIF \ +clk_cpu_est_11_0_1_3__n.BLIF DTACK_i.BLIF N_105_1.BLIF VMA_INT_i.BLIF \ +DTACK_SYNC_1_sqmuxa_1_0.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF \ +DTACK_SYNC_1_sqmuxa_2.BLIF CLK_000_D1_i.BLIF \ +state_machine_un8_clk_000_d0_1_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF \ +state_machine_un8_clk_000_d0_2_n.BLIF AS_030_i.BLIF \ +state_machine_un8_clk_000_d0_3_n.BLIF N_95_i.BLIF \ +state_machine_un8_clk_000_d0_4_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF \ +state_machine_un13_clk_000_d0_1_0_n.BLIF N_96_i.BLIF \ +state_machine_un13_clk_000_d0_2_0_n.BLIF a_i_18__n.BLIF \ +cpu_est_0_1__un3_n.BLIF a_i_16__n.BLIF cpu_est_0_1__un1_n.BLIF a_i_19__n.BLIF \ +cpu_est_0_1__un0_n.BLIF CLK_030_i.BLIF cpu_est_0_3__un3_n.BLIF \ +state_machine_un42_clk_030_i_n.BLIF cpu_est_0_3__un1_n.BLIF \ +sm_amiga_i_6__n.BLIF cpu_est_0_3__un0_n.BLIF sm_amiga_i_7__n.BLIF \ +ipl_030_0_0__un3_n.BLIF AMIGA_BUS_ENABLE_i.BLIF ipl_030_0_0__un1_n.BLIF \ +nEXP_SPACE_i.BLIF ipl_030_0_0__un0_n.BLIF sm_amiga_i_2__n.BLIF \ +ipl_030_0_1__un3_n.BLIF sm_amiga_i_1__n.BLIF ipl_030_0_1__un1_n.BLIF \ +DS_030_i.BLIF ipl_030_0_1__un0_n.BLIF AS_030_000_SYNC_i.BLIF \ +ipl_030_0_2__un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF ipl_030_0_2__un1_n.BLIF \ +UDS_000_INT_0_sqmuxa_i.BLIF ipl_030_0_2__un0_n.BLIF \ +state_machine_un13_clk_000_d0_1_i_n.BLIF uds_000_int_0_un3_n.BLIF \ +clk_clk_cnt_i_n.BLIF uds_000_int_0_un1_n.BLIF clk_cnt_i_0__n.BLIF \ +uds_000_int_0_un0_n.BLIF CLK_000_D2_i.BLIF vpa_sync_0_un3_n.BLIF \ +a_i_30__n.BLIF vpa_sync_0_un1_n.BLIF a_i_31__n.BLIF vpa_sync_0_un0_n.BLIF \ +a_i_28__n.BLIF as_000_int_0_un3_n.BLIF a_i_29__n.BLIF as_000_int_0_un1_n.BLIF \ +a_i_26__n.BLIF as_000_int_0_un0_n.BLIF a_i_27__n.BLIF \ +bgack_030_int_0_un3_n.BLIF a_i_24__n.BLIF bgack_030_int_0_un1_n.BLIF \ +a_i_25__n.BLIF bgack_030_int_0_un0_n.BLIF N_132_i.BLIF vma_int_0_un3_n.BLIF \ +N_133_i.BLIF vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF RST_i.BLIF \ +cpu_est_0_2__un3_n.BLIF FPU_CS_INT_i.BLIF cpu_est_0_2__un1_n.BLIF \ +BGACK_030_INT_i.BLIF cpu_est_0_2__un0_n.BLIF AS_030_c.BLIF \ +dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF \ +DS_030_c.BLIF bg_000_0_un3_n.BLIF bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF \ +amiga_bus_enable_0_un3_n.BLIF size_c_0__n.BLIF amiga_bus_enable_0_un1_n.BLIF \ +amiga_bus_enable_0_un0_n.BLIF size_c_1__n.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un1_n.BLIF a_c_0__n.BLIF as_030_000_sync_0_un0_n.BLIF \ +fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF \ +dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF \ +lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF \ +a_15__n.BLIF a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_c_16__n.BLIF \ +a_11__n.BLIF a_c_17__n.BLIF a_10__n.BLIF a_c_18__n.BLIF a_9__n.BLIF \ +a_c_19__n.BLIF a_8__n.BLIF a_c_20__n.BLIF a_7__n.BLIF a_c_21__n.BLIF \ +a_6__n.BLIF a_c_22__n.BLIF a_5__n.BLIF a_c_23__n.BLIF a_4__n.BLIF \ +a_c_24__n.BLIF a_3__n.BLIF a_c_25__n.BLIF a_2__n.BLIF a_c_26__n.BLIF \ +a_1__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF \ +a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF DSACK_1_.PIN.BLIF \ +DTACK.PIN.BLIF .outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_5_.D SM_AMIGA_5_.C \ -SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D \ -SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR \ -SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C \ -SM_AMIGA_0_.AR cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ +AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_6_.D SM_AMIGA_6_.C \ +SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D \ +SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \ +SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR cpu_est_1_.D \ +cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C \ IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D \ -SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ -inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP CLK_CNT_0_.D CLK_CNT_0_.C \ -CLK_CNT_1_.D CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ +SM_AMIGA_7_.C SM_AMIGA_7_.AP inst_VMA_INTreg.D inst_VMA_INTreg.C \ +inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ +inst_BGACK_030_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C CLK_CNT_0_.D \ +CLK_CNT_0_.C CLK_CNT_1_.D CLK_CNT_1_.C cpu_est_0_.D cpu_est_0_.C \ inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_FPU_CS_INTreg.D \ inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_030_000_SYNC.D \ inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_AS_000_INTreg.D \ inst_AS_000_INTreg.C inst_AS_000_INTreg.AP AMIGA_BUS_ENABLEDFFreg.D \ AMIGA_BUS_ENABLEDFFreg.C BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \ -DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_VMA_INTreg.D \ -inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_UDS_000_INTreg.D \ +DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP inst_UDS_000_INTreg.D \ inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D \ inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D \ -inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_DTACK_DMA.D inst_DTACK_DMA.C \ -inst_DTACK_DMA.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_D2.D \ +inst_DTACK_SYNC.C inst_DTACK_SYNC.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ +inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_CLK_000_D2.D \ inst_CLK_000_D2.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D \ inst_CLK_000_D0.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_D1.D \ -inst_CLK_000_D1.C CLK_REF_1_.D CLK_REF_1_.LH CLK_REF_1_.AR DSACK_1_ DTACK \ -DSACK_0_ BGACK_000_c CLK_030_c CLK_000_c CLK_OSZI_c ipl_c_0__n ipl_c_1__n \ -ipl_c_2__n vcc_n_n gnd_n_n dsack_c_1__n DTACK_c clk_un4_clk_000_d1_n \ -clk_clk_cnt_n RST_c state_machine_un14_as_000_int_n RW_c fc_c_0__n \ -un1_as_030_4 fc_c_1__n state_machine_lds_000_int_7_n \ -state_machine_uds_000_int_7_n N_101_i N_102_i N_103_i N_90_0 N_91_0 N_127_i \ -N_128_i N_118_i N_125_i N_123_i N_124_i N_126_i clk_cpu_est_11_0_1__n N_131_i \ -clk_cpu_est_11_0_3__n N_130_i N_129_i N_122_i N_121_i N_108_i \ -sm_amiga_ns_0_7__n state_machine_un30_clk_000_d1_n \ -state_machine_un8_clk_000_d0_i_n N_147 state_machine_un13_clk_000_d0_i_n N_96 \ -state_machine_un15_clk_000_d0_0_n state_machine_un44_clk_000_d1_n \ -state_machine_un23_clk_000_d0_i_n N_100_i N_89 sm_amiga_ns_0_2__n N_97 \ -BG_030_c_i N_90 state_machine_un1_clk_030_0_n N_98 clk_un4_clk_000_d1_i_n N_99 \ -state_machine_un6_bgack_000_0_n UDS_000_INT_0_sqmuxa \ -state_machine_un17_clk_030_0_n UDS_000_INT_0_sqmuxa_1 un1_as_030_3_0 N_167 \ -N_89_i N_170 AMIGA_BUS_ENABLE_i_m_i N_105 nEXP_SPACE_m_i N_92 \ -state_machine_amiga_bus_enable_2_iv_i_n N_106 \ -state_machine_as_030_000_sync_3_2_n N_107 N_94_i N_104 un1_bg_030_0 \ -state_machine_un42_clk_030_n N_105_i un1_bg_030 N_104_i N_94 \ -sm_amiga_ns_0_5__n state_machine_as_030_000_sync_3_n N_106_i \ -AMIGA_BUS_ENABLE_i_m N_107_i nEXP_SPACE_m N_95 CLK_OUT_PRE_i un1_as_030_3 \ -N_92_0 state_machine_un17_clk_030_n state_machine_un44_clk_000_d1_i_n \ -state_machine_un6_bgack_000_n a_c_i_0__n state_machine_un1_clk_030_n \ -size_c_i_1__n AS_000_INT_1_sqmuxa N_98_i DSACK_INT_1_sqmuxa N_99_i N_100 \ -sm_amiga_ns_0_1__n state_machine_un23_clk_000_d0_n N_97_i DTACK_SYNC_1_sqmuxa \ -DTACK_SYNC_1_sqmuxa_1 N_147_i VPA_SYNC_1_sqmuxa \ -state_machine_lds_000_int_7_0_n VPA_SYNC_1_sqmuxa_1 \ -state_machine_uds_000_int_7_0_n state_machine_un15_clk_000_d0_n un1_bg_030_0_1 \ -clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n \ +inst_CLK_000_D1.C CLK_REF_0_.D CLK_REF_0_.LH CLK_REF_0_.AP CLK_REF_1_.D \ +CLK_REF_1_.LH CLK_REF_1_.AR DSACK_1_ DTACK DSACK_0_ BGACK_000_c CLK_030_c \ +CLK_000_c CLK_OSZI_c ipl_c_0__n vcc_n_n ipl_c_1__n gnd_n_n ipl_c_2__n \ +dsack_c_1__n DTACK_c clk_clk_cnt_n state_machine_un14_as_000_int_n RST_c RW_c \ +fc_c_0__n fc_c_1__n N_101_i N_102_i N_103_i N_91_0 N_125_i N_123_i N_124_i \ +N_126_i clk_cpu_est_11_0_1__n N_131_i clk_cpu_est_11_0_3__n N_130_i N_129_i \ +N_122_i N_121_i N_127_i state_machine_un30_clk_000_d1_n N_128_i N_148 N_118_i \ +DTACK_SYNC_1_sqmuxa state_machine_un8_clk_000_d0_i_n N_96 \ +state_machine_un13_clk_000_d0_i_n state_machine_un15_clk_000_d0_0_n N_89 \ +N_100_i N_97 sm_amiga_ns_0_2__n N_90 clk_un4_clk_000_d1_i_n N_98 \ +state_machine_un6_bgack_000_0_n N_99 state_machine_un23_clk_000_d0_i_n N_108 \ +BG_030_c_i UDS_000_INT_0_sqmuxa state_machine_un1_clk_030_0_n \ +UDS_000_INT_0_sqmuxa_1 state_machine_un17_clk_030_0_n \ +state_machine_un13_clk_000_d0_1_n un1_as_030_3_0 N_168 N_148_i N_171 \ +a_c_i_0__n N_105 state_machine_uds_000_int_7_0_n N_92 \ +state_machine_lds_000_int_7_0_n N_106 AMIGA_BUS_ENABLE_i_m_i N_107 \ +nEXP_SPACE_m_i N_104 state_machine_amiga_bus_enable_2_iv_i_n \ +state_machine_un42_clk_030_n state_machine_as_030_000_sync_3_2_n \ +state_machine_un44_clk_000_d1_n N_94_i un1_bg_030 un1_bg_030_0 N_94 \ +size_c_i_1__n state_machine_as_030_000_sync_3_n \ +state_machine_un44_clk_000_d1_i_n AMIGA_BUS_ENABLE_i_m N_105_i nEXP_SPACE_m \ +N_104_i N_95 sm_amiga_ns_0_5__n state_machine_lds_000_int_7_n N_106_i \ +state_machine_uds_000_int_7_n N_107_i DTACK_SYNC_1_sqmuxa_1 un1_as_030_4 \ +CLK_OUT_PRE_i un1_as_030_3 N_92_0 DSACK_INT_1_sqmuxa N_90_0 \ +state_machine_un17_clk_030_n N_89_i state_machine_un1_clk_030_n N_108_i \ +state_machine_un23_clk_000_d0_n sm_amiga_ns_0_7__n VPA_SYNC_1_sqmuxa N_98_i \ +VPA_SYNC_1_sqmuxa_1 N_99_i AS_000_INT_1_sqmuxa sm_amiga_ns_0_1__n \ +state_machine_un6_bgack_000_n N_97_i clk_un4_clk_000_d1_n N_100 \ +state_machine_un44_clk_000_d1_i_1_n state_machine_un15_clk_000_d0_n \ +un1_bg_030_0_1 clk_cpu_est_11_3__n un1_bg_030_0_2 state_machine_un2_clk_000_n \ state_machine_as_030_000_sync_3_2_1_n state_machine_un13_clk_000_d0_n \ clk_cpu_est_11_0_1_1__n state_machine_un8_clk_000_d0_n clk_cpu_est_11_0_2_1__n \ -N_108 N_167_1 state_machine_un13_clk_000_d0_1_n N_167_2 N_124 N_167_3 N_126 \ -N_167_4 state_machine_un13_clk_000_d0_2_n N_167_5 N_129 N_167_6 N_122 N_170_1 \ -N_130 N_170_2 N_121 UDS_000_INT_0_sqmuxa_1_1 N_131 UDS_000_INT_0_sqmuxa_1_2 \ -N_127 UDS_000_INT_0_sqmuxa_1_3 clk_cpu_est_11_1__n UDS_000_INT_0_sqmuxa_1_0 \ -N_128 state_machine_un44_clk_000_d1_i_1_n N_123 state_machine_un42_clk_030_1_n \ -N_125 state_machine_un42_clk_030_2_n N_91 state_machine_un42_clk_030_3_n N_102 \ -state_machine_un42_clk_030_4_n N_103 state_machine_un42_clk_030_5_n N_101 \ -N_96_1 RW_i AMIGA_BUS_ENABLE_i_m_1 AS_000_INT_i N_131_1 dsack_i_1__n \ -clk_cpu_est_11_0_1_3__n sm_amiga_i_4__n N_105_1 sm_amiga_i_5__n \ -VPA_SYNC_1_sqmuxa_1_0 CLK_000_D0_i VPA_SYNC_1_sqmuxa_2 sm_amiga_i_3__n \ -VPA_SYNC_1_sqmuxa_3 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_4 cpu_est_i_2__n \ -VPA_SYNC_1_sqmuxa_5 state_machine_un13_clk_000_d0_2_i_n VPA_SYNC_1_sqmuxa_6 \ -cpu_est_i_3__n DTACK_SYNC_1_sqmuxa_1_0 VPA_D_i DTACK_SYNC_1_sqmuxa_2 \ -cpu_est_i_1__n state_machine_un8_clk_000_d0_1_n DTACK_i \ -state_machine_un8_clk_000_d0_2_n VMA_INT_i state_machine_un8_clk_000_d0_3_n \ -state_machine_un13_clk_000_d0_1_i_n state_machine_un8_clk_000_d0_4_n AS_030_i \ -state_machine_un13_clk_000_d0_1_0_n DTACK_SYNC_1_sqmuxa_i \ -state_machine_un13_clk_000_d0_2_0_n VPA_SYNC_1_sqmuxa_i N_127_1 CLK_000_D1_i \ -N_128_1 N_95_i ipl_030_0_2__un3_n N_96_i ipl_030_0_2__un1_n a_i_18__n \ -ipl_030_0_2__un0_n a_i_16__n ipl_030_0_1__un3_n a_i_19__n ipl_030_0_1__un1_n \ -CLK_030_i ipl_030_0_1__un0_n CLK_000_D2_i ipl_030_0_0__un3_n \ -state_machine_un42_clk_030_i_n ipl_030_0_0__un1_n sm_amiga_i_6__n \ -ipl_030_0_0__un0_n sm_amiga_i_7__n cpu_est_0_2__un3_n AMIGA_BUS_ENABLE_i \ -cpu_est_0_2__un1_n nEXP_SPACE_i cpu_est_0_2__un0_n sm_amiga_i_2__n \ -cpu_est_0_1__un3_n sm_amiga_i_1__n cpu_est_0_1__un1_n DS_030_i \ -cpu_est_0_1__un0_n AS_030_000_SYNC_i vpa_sync_0_un3_n UDS_000_INT_0_sqmuxa_1_i \ -vpa_sync_0_un1_n UDS_000_INT_0_sqmuxa_i vpa_sync_0_un0_n clk_clk_cnt_i_n \ -vma_int_0_un3_n clk_cnt_i_0__n vma_int_0_un1_n a_i_30__n vma_int_0_un0_n \ -a_i_31__n cpu_est_0_3__un3_n a_i_28__n cpu_est_0_3__un1_n a_i_29__n \ -cpu_est_0_3__un0_n a_i_26__n bgack_030_int_0_un3_n a_i_27__n \ -bgack_030_int_0_un1_n a_i_24__n bgack_030_int_0_un0_n a_i_25__n bg_000_0_un3_n \ -N_132_i bg_000_0_un1_n bg_000_0_un0_n RST_i amiga_bus_enable_0_un3_n \ -FPU_CS_INT_i amiga_bus_enable_0_un1_n BGACK_030_INT_i amiga_bus_enable_0_un0_n \ -AS_030_c as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n \ -as_030_000_sync_0_un0_n DS_030_c fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n \ -fpu_cs_int_0_un0_n as_000_int_0_un3_n size_c_0__n as_000_int_0_un1_n \ -as_000_int_0_un0_n size_c_1__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n \ -a_c_0__n dsack_int_0_1__un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n \ -dtack_sync_0_un0_n uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n \ +N_129 N_168_1 N_122 N_168_2 N_130 N_168_3 N_127 N_168_4 N_128 N_168_5 N_121 \ +N_168_6 state_machine_un13_clk_000_d0_2_n N_171_1 N_131 N_171_2 \ +clk_cpu_est_11_1__n UDS_000_INT_0_sqmuxa_1_1 N_126 UDS_000_INT_0_sqmuxa_1_2 \ +N_124 UDS_000_INT_0_sqmuxa_1_3 N_123 UDS_000_INT_0_sqmuxa_1_0 N_125 N_96_1 \ +N_91 state_machine_un42_clk_030_1_n N_102 state_machine_un42_clk_030_2_n N_103 \ +state_machine_un42_clk_030_3_n N_101 state_machine_un42_clk_030_4_n RW_i \ +state_machine_un42_clk_030_5_n AS_000_INT_i AMIGA_BUS_ENABLE_i_m_1 \ +dsack_i_1__n VPA_SYNC_1_sqmuxa_1_0 sm_amiga_i_4__n VPA_SYNC_1_sqmuxa_2 \ +sm_amiga_i_5__n VPA_SYNC_1_sqmuxa_3 CLK_000_D0_i VPA_SYNC_1_sqmuxa_4 \ +sm_amiga_i_3__n VPA_SYNC_1_sqmuxa_5 cpu_est_i_0__n VPA_SYNC_1_sqmuxa_6 \ +cpu_est_i_3__n N_127_1 cpu_est_i_2__n N_128_1 VPA_D_i N_131_1 cpu_est_i_1__n \ +clk_cpu_est_11_0_1_3__n DTACK_i N_105_1 VMA_INT_i DTACK_SYNC_1_sqmuxa_1_0 \ +state_machine_un13_clk_000_d0_2_i_n DTACK_SYNC_1_sqmuxa_2 CLK_000_D1_i \ +state_machine_un8_clk_000_d0_1_n VPA_SYNC_1_sqmuxa_i \ +state_machine_un8_clk_000_d0_2_n AS_030_i state_machine_un8_clk_000_d0_3_n \ +N_95_i state_machine_un8_clk_000_d0_4_n DTACK_SYNC_1_sqmuxa_i \ +state_machine_un13_clk_000_d0_1_0_n N_96_i state_machine_un13_clk_000_d0_2_0_n \ +a_i_18__n cpu_est_0_1__un3_n a_i_16__n cpu_est_0_1__un1_n a_i_19__n \ +cpu_est_0_1__un0_n CLK_030_i cpu_est_0_3__un3_n state_machine_un42_clk_030_i_n \ +cpu_est_0_3__un1_n sm_amiga_i_6__n cpu_est_0_3__un0_n sm_amiga_i_7__n \ +ipl_030_0_0__un3_n AMIGA_BUS_ENABLE_i ipl_030_0_0__un1_n nEXP_SPACE_i \ +ipl_030_0_0__un0_n sm_amiga_i_2__n ipl_030_0_1__un3_n sm_amiga_i_1__n \ +ipl_030_0_1__un1_n DS_030_i ipl_030_0_1__un0_n AS_030_000_SYNC_i \ +ipl_030_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i ipl_030_0_2__un1_n \ +UDS_000_INT_0_sqmuxa_i ipl_030_0_2__un0_n state_machine_un13_clk_000_d0_1_i_n \ +uds_000_int_0_un3_n clk_clk_cnt_i_n uds_000_int_0_un1_n clk_cnt_i_0__n \ +uds_000_int_0_un0_n CLK_000_D2_i vpa_sync_0_un3_n a_i_30__n vpa_sync_0_un1_n \ +a_i_31__n vpa_sync_0_un0_n a_i_28__n as_000_int_0_un3_n a_i_29__n \ +as_000_int_0_un1_n a_i_26__n as_000_int_0_un0_n a_i_27__n \ +bgack_030_int_0_un3_n a_i_24__n bgack_030_int_0_un1_n a_i_25__n \ +bgack_030_int_0_un0_n N_132_i vma_int_0_un3_n N_133_i vma_int_0_un1_n \ +vma_int_0_un0_n RST_i cpu_est_0_2__un3_n FPU_CS_INT_i cpu_est_0_2__un1_n \ +BGACK_030_INT_i cpu_est_0_2__un0_n AS_030_c dsack_int_0_1__un3_n \ +dsack_int_0_1__un1_n dsack_int_0_1__un0_n DS_030_c bg_000_0_un3_n \ +bg_000_0_un1_n bg_000_0_un0_n amiga_bus_enable_0_un3_n size_c_0__n \ +amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n size_c_1__n \ +as_030_000_sync_0_un3_n as_030_000_sync_0_un1_n a_c_0__n \ +as_030_000_sync_0_un0_n fpu_cs_int_0_un3_n fpu_cs_int_0_un1_n \ +fpu_cs_int_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n dtack_sync_0_un0_n \ lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n a_15__n a_14__n \ a_13__n a_12__n a_c_16__n a_11__n a_c_17__n a_10__n a_c_18__n a_9__n a_c_19__n \ a_8__n a_c_20__n a_7__n a_c_21__n a_6__n a_c_22__n a_5__n a_c_23__n a_4__n \ a_c_24__n a_3__n a_c_25__n a_2__n a_c_26__n a_1__n a_c_27__n a_c_28__n \ a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c DSACK_1_.OE DTACK.OE \ AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE \ -CLK_OUT_PRE_0 cpu_est_0_0_ G_86 G_90 +CLK_OUT_PRE_0 cpu_est_0_0_ G_86 G_87 G_91 +.names sm_amiga_ns_0_1__n.BLIF SM_AMIGA_6_.D +0 1 .names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D 0 1 .names CLK_000_D0_i.BLIF N_101_i.BLIF SM_AMIGA_4_.D @@ -325,6 +332,9 @@ CLK_OUT_PRE_0 cpu_est_0_0_ G_86 G_90 11 1 .names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D 0 1 +.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 .names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D 1- 1 -1 1 @@ -342,19 +352,17 @@ CLK_OUT_PRE_0 cpu_est_0_0_ G_86 G_90 -1 1 .names inst_CLK_000_D0.BLIF N_97_i.BLIF SM_AMIGA_7_.D 11 1 -.names sm_amiga_ns_0_1__n.BLIF SM_AMIGA_6_.D -0 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +1- 1 +-1 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ inst_BGACK_030_INTreg.D 1- 1 -1 1 .names clk_cnt_i_0__n.BLIF clk_clk_cnt_i_n.BLIF CLK_CNT_0_.D 11 1 -.names clk_clk_cnt_i_n.BLIF G_90.BLIF CLK_CNT_1_.D +.names clk_clk_cnt_i_n.BLIF G_91.BLIF CLK_CNT_1_.D 11 1 -.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D -1- 1 --1 1 .names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D 1- 1 -1 1 @@ -378,9 +386,6 @@ AMIGA_BUS_ENABLEDFFreg.D .names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D 1- 1 -1 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D -1- 1 --1 1 .names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D 1- 1 -1 1 @@ -395,34 +400,18 @@ AMIGA_BUS_ENABLEDFFreg.D .names vcc_n_n 1 .names gnd_n_n -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF clk_un4_clk_000_d1_n -11 1 -.names clk_cnt_i_0__n.BLIF N_132_i.BLIF clk_clk_cnt_n +.names N_132_i.BLIF N_133_i.BLIF clk_clk_cnt_n 11 1 .names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un14_as_000_int_n 11 1 -.names AS_030_i.BLIF N_147.BLIF un1_as_030_4 -11 1 -.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n -0 1 -.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n -0 1 .names N_101.BLIF N_101_i 0 1 .names N_102.BLIF N_102_i 0 1 .names N_103.BLIF N_103_i 0 1 -.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_90_0 -11 1 .names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_i_n.BLIF N_91_0 11 1 -.names N_127.BLIF N_127_i -0 1 -.names N_128.BLIF N_128_i -0 1 -.names N_127_i.BLIF N_128_i.BLIF N_118_i -11 1 .names N_125.BLIF N_125_i 0 1 .names N_123.BLIF N_123_i @@ -446,166 +435,189 @@ clk_cpu_est_11_0_1__n 11 1 .names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_121_i 11 1 -.names N_108.BLIF N_108_i +.names N_127.BLIF N_127_i 0 1 -.names N_96_i.BLIF N_108_i.BLIF sm_amiga_ns_0_7__n -11 1 .names inst_CLK_000_D1.BLIF CLK_000_D2_i.BLIF state_machine_un30_clk_000_d1_n 11 1 +.names N_128.BLIF N_128_i +0 1 +.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_148 +11 1 +.names N_127_i.BLIF N_128_i.BLIF N_118_i +11 1 +.names DTACK_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa_2.BLIF \ +DTACK_SYNC_1_sqmuxa +11 1 .names state_machine_un8_clk_000_d0_n.BLIF state_machine_un8_clk_000_d0_i_n 0 1 -.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_147 +.names N_96_1.BLIF SM_AMIGA_1_.BLIF N_96 11 1 .names state_machine_un13_clk_000_d0_n.BLIF state_machine_un13_clk_000_d0_i_n 0 1 -.names N_96_1.BLIF SM_AMIGA_1_.BLIF N_96 -11 1 .names state_machine_un8_clk_000_d0_i_n.BLIF \ state_machine_un13_clk_000_d0_i_n.BLIF state_machine_un15_clk_000_d0_0_n 11 1 -.names state_machine_un44_clk_000_d1_i_n.BLIF state_machine_un44_clk_000_d1_n -0 1 -.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ -state_machine_un23_clk_000_d0_i_n -11 1 -.names N_100.BLIF N_100_i -0 1 .names N_89_i.BLIF N_89 0 1 -.names N_95_i.BLIF N_100_i.BLIF sm_amiga_ns_0_2__n -11 1 +.names N_100.BLIF N_100_i +0 1 .names N_90.BLIF sm_amiga_i_7__n.BLIF N_97 11 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 +.names N_95_i.BLIF N_100_i.BLIF sm_amiga_ns_0_2__n +11 1 .names N_90_0.BLIF N_90 0 1 -.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n -11 1 -.names N_89.BLIF SM_AMIGA_6_.BLIF N_98 -11 1 .names clk_un4_clk_000_d1_n.BLIF clk_un4_clk_000_d1_i_n 0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_7_.BLIF N_99 +.names N_89.BLIF SM_AMIGA_6_.BLIF N_98 11 1 .names BGACK_000_c.BLIF clk_un4_clk_000_d1_i_n.BLIF \ state_machine_un6_bgack_000_0_n 11 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_7_.BLIF N_99 +11 1 +.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ +state_machine_un23_clk_000_d0_i_n +11 1 +.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF N_108 +11 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 .names UDS_000_INT_0_sqmuxa_1_0.BLIF RW_i.BLIF UDS_000_INT_0_sqmuxa 11 1 -.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n +.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n 11 1 .names UDS_000_INT_0_sqmuxa_1_3.BLIF state_machine_un30_clk_000_d1_n.BLIF \ UDS_000_INT_0_sqmuxa_1 11 1 +.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n +11 1 +.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF \ +state_machine_un13_clk_000_d0_1_n +11 1 .names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_3_0 11 1 -.names N_167_5.BLIF N_167_6.BLIF N_167 +.names N_168_5.BLIF N_168_6.BLIF N_168 11 1 -.names AS_030_000_SYNC_i.BLIF state_machine_un30_clk_000_d1_n.BLIF N_89_i +.names N_148.BLIF N_148_i +0 1 +.names N_171_1.BLIF N_171_2.BLIF N_171 11 1 -.names N_170_1.BLIF N_170_2.BLIF N_170 -11 1 -.names AMIGA_BUS_ENABLE_i_m.BLIF AMIGA_BUS_ENABLE_i_m_i +.names a_c_0__n.BLIF a_c_i_0__n 0 1 .names N_105_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_105 11 1 -.names nEXP_SPACE_m.BLIF nEXP_SPACE_m_i -0 1 +.names a_c_i_0__n.BLIF N_148_i.BLIF state_machine_uds_000_int_7_0_n +11 1 .names N_92_0.BLIF N_92 0 1 -.names AMIGA_BUS_ENABLE_i_m_i.BLIF nEXP_SPACE_m_i.BLIF \ -state_machine_amiga_bus_enable_2_iv_i_n +.names N_148_i.BLIF state_machine_un44_clk_000_d1_n.BLIF \ +state_machine_lds_000_int_7_0_n 11 1 .names CLK_000_D0_i.BLIF N_92.BLIF N_106 11 1 -.names state_machine_as_030_000_sync_3_2_1_n.BLIF \ -state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n -11 1 +.names AMIGA_BUS_ENABLE_i_m.BLIF AMIGA_BUS_ENABLE_i_m_i +0 1 .names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_107 11 1 -.names N_94.BLIF N_94_i +.names nEXP_SPACE_m.BLIF nEXP_SPACE_m_i 0 1 .names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_104 11 1 -.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 +.names AMIGA_BUS_ENABLE_i_m_i.BLIF nEXP_SPACE_m_i.BLIF \ +state_machine_amiga_bus_enable_2_iv_i_n 11 1 .names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF \ state_machine_un42_clk_030_n 11 1 -.names N_105.BLIF N_105_i +.names state_machine_as_030_000_sync_3_2_1_n.BLIF \ +state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n +11 1 +.names state_machine_un44_clk_000_d1_i_n.BLIF state_machine_un44_clk_000_d1_n +0 1 +.names N_94.BLIF N_94_i 0 1 .names un1_bg_030_0.BLIF un1_bg_030 0 1 -.names N_104.BLIF N_104_i -0 1 +.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0 +11 1 .names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_94 11 1 -.names N_104_i.BLIF N_105_i.BLIF sm_amiga_ns_0_5__n -11 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 .names state_machine_as_030_000_sync_3_2_n.BLIF \ state_machine_as_030_000_sync_3_n 0 1 -.names N_106.BLIF N_106_i -0 1 +.names state_machine_un44_clk_000_d1_i_1_n.BLIF size_c_i_1__n.BLIF \ +state_machine_un44_clk_000_d1_i_n +11 1 .names AMIGA_BUS_ENABLE_i_m_1.BLIF sm_amiga_i_6__n.BLIF AMIGA_BUS_ENABLE_i_m 11 1 -.names N_107.BLIF N_107_i +.names N_105.BLIF N_105_i 0 1 .names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF nEXP_SPACE_m 11 1 +.names N_104.BLIF N_104_i +0 1 .names N_89_i.BLIF SM_AMIGA_6_.BLIF N_95 11 1 +.names N_104_i.BLIF N_105_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names state_machine_lds_000_int_7_0_n.BLIF state_machine_lds_000_int_7_n +0 1 +.names N_106.BLIF N_106_i +0 1 +.names state_machine_uds_000_int_7_0_n.BLIF state_machine_uds_000_int_7_n +0 1 +.names N_107.BLIF N_107_i +0 1 +.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 +11 1 +.names AS_030_i.BLIF N_148.BLIF un1_as_030_4 +11 1 .names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i 0 1 .names un1_as_030_3_0.BLIF un1_as_030_3 0 1 .names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_92_0 11 1 +.names AS_030_i.BLIF N_96_i.BLIF DSACK_INT_1_sqmuxa +11 1 +.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_90_0 +11 1 .names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n 0 1 -.names state_machine_un44_clk_000_d1_i_1_n.BLIF size_c_0__n.BLIF \ -state_machine_un44_clk_000_d1_i_n +.names AS_030_000_SYNC_i.BLIF state_machine_un30_clk_000_d1_n.BLIF N_89_i 11 1 -.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n -0 1 -.names a_c_0__n.BLIF a_c_i_0__n -0 1 .names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n 0 1 -.names size_c_1__n.BLIF size_c_i_1__n +.names N_108.BLIF N_108_i 0 1 -.names AS_030_i.BLIF N_95_i.BLIF AS_000_INT_1_sqmuxa +.names state_machine_un23_clk_000_d0_i_n.BLIF state_machine_un23_clk_000_d0_n +0 1 +.names N_96_i.BLIF N_108_i.BLIF sm_amiga_ns_0_7__n +11 1 +.names VPA_SYNC_1_sqmuxa_5.BLIF VPA_SYNC_1_sqmuxa_6.BLIF VPA_SYNC_1_sqmuxa 11 1 .names N_98.BLIF N_98_i 0 1 -.names AS_030_i.BLIF N_96_i.BLIF DSACK_INT_1_sqmuxa +.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 11 1 .names N_99.BLIF N_99_i 0 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF N_100 +.names AS_030_i.BLIF N_95_i.BLIF AS_000_INT_1_sqmuxa 11 1 .names N_98_i.BLIF N_99_i.BLIF sm_amiga_ns_0_1__n 11 1 -.names state_machine_un23_clk_000_d0_i_n.BLIF state_machine_un23_clk_000_d0_n +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n 0 1 .names N_97.BLIF N_97_i 0 1 -.names DTACK_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa_2.BLIF \ -DTACK_SYNC_1_sqmuxa +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF clk_un4_clk_000_d1_n 11 1 -.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF N_100 11 1 -.names N_147.BLIF N_147_i -0 1 -.names VPA_SYNC_1_sqmuxa_5.BLIF VPA_SYNC_1_sqmuxa_6.BLIF VPA_SYNC_1_sqmuxa -11 1 -.names N_147_i.BLIF state_machine_un44_clk_000_d1_n.BLIF \ -state_machine_lds_000_int_7_0_n -11 1 -.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1 -11 1 -.names a_c_i_0__n.BLIF N_147_i.BLIF state_machine_uds_000_int_7_0_n +.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un44_clk_000_d1_i_1_n 11 1 .names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n 0 1 @@ -629,304 +641,318 @@ state_machine_un8_clk_000_d0_3_n.BLIF state_machine_un8_clk_000_d0_n 11 1 .names N_123_i.BLIF N_125_i.BLIF clk_cpu_est_11_0_2_1__n 11 1 -.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF N_108 -11 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_167_1 -11 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF \ -state_machine_un13_clk_000_d0_1_n -11 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_167_2 -11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_124 -11 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_167_3 -11 1 -.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d0_2_n.BLIF N_126 -11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_167_4 -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d0_2_n -11 1 -.names N_167_1.BLIF N_167_2.BLIF N_167_5 -11 1 .names N_122.BLIF cpu_est_3_reg.BLIF N_129 11 1 -.names N_167_3.BLIF N_167_4.BLIF N_167_6 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_168_1 11 1 .names N_122_i.BLIF N_122 0 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_170_1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_168_2 11 1 .names N_122_i.BLIF cpu_est_i_2__n.BLIF N_130 11 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_170_2 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_168_3 +11 1 +.names N_127_1.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF N_127 +11 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_168_4 +11 1 +.names N_128_1.BLIF cpu_est_i_2__n.BLIF N_128 +11 1 +.names N_168_1.BLIF N_168_2.BLIF N_168_5 11 1 .names N_121_i.BLIF N_121 0 1 -.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 +.names N_168_3.BLIF N_168_4.BLIF N_168_6 +11 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d0_2_n +11 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_171_1 11 1 .names N_131_1.BLIF cpu_est_i_2__n.BLIF N_131 11 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_171_2 +11 1 +.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n +0 1 +.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1 +11 1 +.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d0_2_n.BLIF N_126 +11 1 .names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2 11 1 -.names N_127_1.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF N_127 +.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_124 11 1 .names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \ UDS_000_INT_0_sqmuxa_1_3 11 1 -.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n -0 1 -.names SM_AMIGA_4_.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 -11 1 -.names N_128_1.BLIF cpu_est_i_2__n.BLIF N_128 -11 1 -.names size_c_i_1__n.BLIF a_c_i_0__n.BLIF state_machine_un44_clk_000_d1_i_1_n -11 1 .names N_121.BLIF cpu_est_i_0__n.BLIF N_123 11 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n +.names SM_AMIGA_4_.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0 11 1 .names N_121_i.BLIF cpu_est_0_.BLIF N_125 11 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n +.names CLK_000_D0_i.BLIF inst_CLK_OUT_PRE.BLIF N_96_1 11 1 .names N_91_0.BLIF N_91 0 1 -.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n +.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n 11 1 .names CLK_000_D0_i.BLIF N_91.BLIF N_102 11 1 +.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n +11 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_103 +11 1 +.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_101 +11 1 .names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF \ state_machine_un42_clk_030_4_n 11 1 -.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_103 -11 1 +.names RW_c.BLIF RW_i +0 1 .names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF \ state_machine_un42_clk_030_5_n 11 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_101 -11 1 -.names CLK_000_D0_i.BLIF inst_CLK_OUT_PRE.BLIF N_96_1 -11 1 -.names RW_c.BLIF RW_i +.names inst_AS_000_INTreg.BLIF AS_000_INT_i 0 1 .names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF AMIGA_BUS_ENABLE_i_m_1 11 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_131_1 -11 1 .names dsack_c_1__n.BLIF dsack_i_1__n 0 1 -.names N_131_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_1_3__n -11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_105_1 -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 .names SM_AMIGA_3_.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_1_0 11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n 0 1 .names VPA_D_i.BLIF cpu_est_2_.BLIF VPA_SYNC_1_sqmuxa_2 11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n 0 1 .names cpu_est_3_reg.BLIF cpu_est_i_0__n.BLIF VPA_SYNC_1_sqmuxa_3 11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n +.names inst_CLK_000_D0.BLIF CLK_000_D0_i 0 1 .names cpu_est_i_1__n.BLIF state_machine_un2_clk_000_n.BLIF \ VPA_SYNC_1_sqmuxa_4 11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 .names VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_5 11 1 -.names state_machine_un13_clk_000_d0_2_n.BLIF \ -state_machine_un13_clk_000_d0_2_i_n +.names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 .names VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_6 11 1 .names cpu_est_3_reg.BLIF cpu_est_i_3__n 0 1 -.names DTACK_i.BLIF SM_AMIGA_3_.BLIF DTACK_SYNC_1_sqmuxa_1_0 +.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_127_1 +11 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_128_1 11 1 .names inst_VPA_D.BLIF VPA_D_i 0 1 -.names inst_VPA_D.BLIF state_machine_un2_clk_000_n.BLIF DTACK_SYNC_1_sqmuxa_2 +.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_131_1 11 1 .names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 +.names N_131_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_1_3__n +11 1 +.names DTACK_c.BLIF DTACK_i +0 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_105_1 +11 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names DTACK_i.BLIF SM_AMIGA_3_.BLIF DTACK_SYNC_1_sqmuxa_1_0 +11 1 +.names state_machine_un13_clk_000_d0_2_n.BLIF \ +state_machine_un13_clk_000_d0_2_i_n +0 1 +.names inst_VPA_D.BLIF state_machine_un2_clk_000_n.BLIF DTACK_SYNC_1_sqmuxa_2 +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 .names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF \ state_machine_un8_clk_000_d0_1_n 11 1 -.names DTACK_c.BLIF DTACK_i +.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i 0 1 .names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d0_2_n 11 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i +.names AS_030_c.BLIF AS_030_i 0 1 .names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d0_3_n 11 1 -.names state_machine_un13_clk_000_d0_1_n.BLIF \ -state_machine_un13_clk_000_d0_1_i_n +.names N_95.BLIF N_95_i 0 1 .names state_machine_un8_clk_000_d0_1_n.BLIF \ state_machine_un8_clk_000_d0_2_n.BLIF state_machine_un8_clk_000_d0_4_n 11 1 -.names AS_030_c.BLIF AS_030_i +.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i 0 1 .names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF \ state_machine_un13_clk_000_d0_1_0_n 11 1 -.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i +.names N_96.BLIF N_96_i 0 1 .names state_machine_un13_clk_000_d0_1_n.BLIF \ state_machine_un13_clk_000_d0_2_n.BLIF state_machine_un13_clk_000_d0_2_0_n 11 1 -.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i -0 1 -.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_127_1 -11 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i -0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_128_1 -11 1 -.names N_95.BLIF N_95_i -0 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un3_n -0 1 -.names N_96.BLIF N_96_i -0 1 -.names ipl_c_2__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un1_n -11 1 .names a_c_18__n.BLIF a_i_18__n 0 1 -.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un3_n -0 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names ipl_c_1__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un1_n -11 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names inst_CLK_000_D2.BLIF CLK_000_D2_i -0 1 -.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un3_n -0 1 -.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n -0 1 -.names ipl_c_0__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un1_n -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un3_n -0 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i -0 1 -.names N_118_i.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un1_n -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 .names clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un3_n 0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +.names a_c_16__n.BLIF a_i_16__n 0 1 .names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un1_n 11 1 -.names DS_030_c.BLIF DS_030_i +.names a_c_19__n.BLIF a_i_19__n 0 1 .names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n -0 1 -.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i -0 1 -.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n -11 1 -.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i -0 1 -.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n -11 1 -.names clk_clk_cnt_n.BLIF clk_clk_cnt_i_n -0 1 -.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n -0 1 -.names CLK_CNT_0_.BLIF clk_cnt_i_0__n -0 1 -.names N_121.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n -11 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names a_c_31__n.BLIF a_i_31__n +.names CLK_030_c.BLIF CLK_030_i 0 1 .names clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un3_n 0 1 -.names a_c_28__n.BLIF a_i_28__n +.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n 0 1 .names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un1_n 11 1 -.names a_c_29__n.BLIF a_i_29__n +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n 0 1 .names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un3_n +0 1 +.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i +0 1 +.names ipl_c_0__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un1_n +11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un3_n +0 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names ipl_c_1__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un1_n +11 1 +.names DS_030_c.BLIF DS_030_i +0 1 +.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un3_n +0 1 +.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i +0 1 +.names ipl_c_2__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un1_n +11 1 +.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i +0 1 +.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names state_machine_un13_clk_000_d0_1_n.BLIF \ +state_machine_un13_clk_000_d0_1_i_n +0 1 +.names un1_as_030_4.BLIF uds_000_int_0_un3_n +0 1 +.names clk_clk_cnt_n.BLIF clk_clk_cnt_i_n +0 1 +.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n +11 1 +.names CLK_CNT_0_.BLIF clk_cnt_i_0__n +0 1 +.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF \ +uds_000_int_0_un0_n +11 1 +.names inst_CLK_000_D2.BLIF CLK_000_D2_i +0 1 +.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n +0 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n +11 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n +11 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +0 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +11 1 .names a_c_26__n.BLIF a_i_26__n 0 1 +.names N_95_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 .names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names a_c_27__n.BLIF a_i_27__n +.names a_c_24__n.BLIF a_i_24__n 0 1 .names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ bgack_030_int_0_un1_n 11 1 -.names a_c_24__n.BLIF a_i_24__n +.names a_c_25__n.BLIF a_i_25__n 0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n -0 1 .names G_86.BLIF N_132_i 0 1 +.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n +0 1 +.names G_87.BLIF N_133_i +0 1 +.names N_121.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +11 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names RST_c.BLIF RST_i +0 1 +.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un3_n +0 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +0 1 +.names N_118_i.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n +0 1 +.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n +11 1 +.names N_96_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n +11 1 +.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n +0 1 .names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n 11 1 .names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names RST_c.BLIF RST_i -0 1 .names RST_c.BLIF amiga_bus_enable_0_un3_n 0 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i -0 1 .names state_machine_amiga_bus_enable_2_iv_i_n.BLIF RST_c.BLIF \ amiga_bus_enable_0_un1_n 11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 .names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF \ amiga_bus_enable_0_un0_n 11 1 @@ -944,31 +970,12 @@ as_030_000_sync_0_un0_n 11 1 .names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n 11 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n -0 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n -11 1 -.names N_95_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 -.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n -0 1 -.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n -11 1 -.names N_96_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n -11 1 .names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n 0 1 .names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n 11 1 .names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n 11 1 -.names un1_as_030_4.BLIF uds_000_int_0_un3_n -0 1 -.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n -11 1 -.names state_machine_uds_000_int_7_n.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un0_n -11 1 .names un1_as_030_4.BLIF lds_000_int_0_un3_n 0 1 .names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n @@ -1030,7 +1037,7 @@ lds_000_int_0_un0_n .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_170.BLIF CIIN +.names N_171.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -1039,6 +1046,12 @@ lds_000_int_0_un0_n .names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names RST_i.BLIF SM_AMIGA_6_.AR +1 1 +0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 0 0 @@ -1075,6 +1088,9 @@ lds_000_int_0_un0_n .names RST_i.BLIF SM_AMIGA_0_.AR 1 1 0 0 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF cpu_est_2_.C 1 1 0 0 @@ -1105,16 +1121,10 @@ lds_000_int_0_un0_n .names RST_i.BLIF SM_AMIGA_7_.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 0 0 -.names RST_i.BLIF SM_AMIGA_6_.AR -1 1 -0 0 -.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +.names RST_i.BLIF inst_VMA_INTreg.AP 1 1 0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C @@ -1123,6 +1133,12 @@ lds_000_int_0_un0_n .names RST_i.BLIF inst_BGACK_030_INTreg.AP 1 1 0 0 +.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +1 1 +0 0 .names CLK_OSZI_c.BLIF CLK_CNT_0_.C 1 1 0 0 @@ -1135,9 +1151,6 @@ lds_000_int_0_un0_n .names CLK_OSZI_c.BLIF cpu_est_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_VPA_SYNC.C 1 1 0 0 @@ -1177,12 +1190,6 @@ lds_000_int_0_un0_n .names RST_i.BLIF DSACK_INT_1_.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_VMA_INTreg.AP -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C 1 1 0 0 @@ -1201,18 +1208,18 @@ lds_000_int_0_un0_n .names RST_i.BLIF inst_DTACK_SYNC.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_DTACK_DMA.C -1 1 -0 0 -.names RST_i.BLIF inst_DTACK_DMA.AP -1 1 -0 0 .names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D 1 1 0 0 .names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_DTACK_DMA.C +1 1 +0 0 +.names RST_i.BLIF inst_DTACK_DMA.AP +1 1 +0 0 .names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D 1 1 0 0 @@ -1243,6 +1250,15 @@ lds_000_int_0_un0_n .names CLK_OSZI_c.BLIF inst_CLK_000_D1.C 1 1 0 0 +.names gnd_n_n.BLIF CLK_REF_0_.D +1 1 +0 0 +.names gnd_n_n.BLIF CLK_REF_0_.LH +1 1 +0 0 +.names RST_i.BLIF CLK_REF_0_.AP +1 1 +0 0 .names gnd_n_n.BLIF CLK_REF_1_.D 1 1 0 0 @@ -1438,7 +1454,7 @@ lds_000_int_0_un0_n .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 0 0 -.names N_167.BLIF CIIN.OE +.names N_168.BLIF CIIN.OE 1 1 0 0 .names inst_CLK_OUT_PRE.BLIF clk_clk_cnt_n.BLIF CLK_OUT_PRE_0 @@ -1451,12 +1467,17 @@ lds_000_int_0_un0_n 10 1 11 0 00 0 -.names CLK_REF_1_.BLIF CLK_CNT_1_.BLIF G_86 +.names CLK_REF_0_.BLIF CLK_CNT_0_.BLIF G_86 01 1 10 1 11 0 00 0 -.names CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF G_90 +.names CLK_REF_1_.BLIF CLK_CNT_1_.BLIF G_87 +01 1 +10 1 +11 0 +00 0 +.names CLK_CNT_0_.BLIF CLK_CNT_1_.BLIF G_91 01 1 10 1 11 0 diff --git a/Logic/BUS68030.cmd b/Logic/BUS68030.cmd new file mode 100644 index 0000000..e7c37a0 --- /dev/null +++ b/Logic/BUS68030.cmd @@ -0,0 +1,8 @@ +STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: "c:/users/matze/documents/github/68030tk/logic" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index 7f3061f..cd73471 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2014 5 18 21 1 42) + (timeStamp 2014 5 22 14 56 5) (author "Synopsys, Inc.") (program "Synplify Pro" (version "G-2012.09LC-SP1 , mapper maplat, Build 621R")) ) @@ -79,6 +79,16 @@ ) ) ) + (cell DLATSH (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port Q (direction OUTPUT)) + (port D (direction INPUT)) + (port LAT (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) (cell IBUF (cellType GENERIC) (view prim (viewType NETLIST) (interface @@ -166,6 +176,8 @@ (port CIIN (direction OUTPUT)) ) (contents + (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFFRH (libraryRef mach))) @@ -178,6 +190,8 @@ ) (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) + (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -190,20 +204,18 @@ ) (instance (rename SM_AMIGA_7 "SM_AMIGA[7]") (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFFRH (libraryRef mach))) - ) - (instance CLK_OUT_PRE (viewRef prim (cellRef DFF (libraryRef mach))) + (instance VMA_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance BGACK_030_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) + (instance CLK_OUT_PRE (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename CLK_CNT_0 "CLK_CNT[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_CNT_1 "CLK_CNT[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance VPA_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance FPU_CS_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) @@ -218,18 +230,16 @@ ) (instance (rename DSACK_INT_1 "DSACK_INT[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance VMA_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) (instance UDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance LDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance DTACK_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance DTACK_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) (instance CLK_OUT_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance DTACK_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) (instance CLK_000_D2 (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance VPA_D (viewRef prim (cellRef DFF (libraryRef mach))) @@ -299,22 +309,6 @@ (instance AMIGA_BUS_DATA_DIR (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d0 "state_machine.un8_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d0_1_0 "state_machine.un13_clk_000_d0_1_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d0_2_0 "state_machine.un13_clk_000_d0_2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d0 "state_machine.un13_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_a4_1_2 "clk.cpu_est_11_i_a4_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_a4_2 "clk.cpu_est_11_i_a4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_a4_0_1_2 "clk.cpu_est_11_i_a4_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_a4_0_2 "clk.cpu_est_11_i_a4_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_0_5 "SM_AMIGA_ns_a3_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DTACK_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DTACK_SYNC_1_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DTACK_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -322,21 +316,45 @@ (instance (rename state_machine_un8_clk_000_d0_2 "state_machine.un8_clk_000_d0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un8_clk_000_d0_3 "state_machine.un8_clk_000_d0_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un8_clk_000_d0_4 "state_machine.un8_clk_000_d0_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d0 "state_machine.un8_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d0_1_0 "state_machine.un13_clk_000_d0_1_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d0_2_0 "state_machine.un13_clk_000_d0_2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d0 "state_machine.un13_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_a4_1_2 "clk.cpu_est_11_i_a4_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_a4_2 "clk.cpu_est_11_i_a4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_a4_0_1_2 "clk.cpu_est_11_i_a4_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_a4_0_2 "clk.cpu_est_11_i_a4_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_1_1_3 "clk.cpu_est_11_0_a4_1_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_1_3 "clk.cpu_est_11_0_a4_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a3_0_1_5 "SM_AMIGA_ns_a3_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a3_0_5 "SM_AMIGA_ns_a3_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DSACK_INT_0_sqmuxa_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DSACK_INT_0_sqmuxa_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_1 "state_machine.un42_clk_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_2 "state_machine.un42_clk_030_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_3 "state_machine.un42_clk_030_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_4 "state_machine.un42_clk_030_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_5 "state_machine.un42_clk_030_5") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030 "state_machine.un42_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_DSACK_INT_0_sqmuxa_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_DSACK_INT_0_sqmuxa_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_i_m_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_i_m (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1_1_3 "clk.cpu_est_11_0_a4_1_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1_3 "clk.cpu_est_11_0_a4_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_0_1_5 "SM_AMIGA_ns_a3_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_2_1 "clk.cpu_est_11_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -347,28 +365,28 @@ (instance UDS_000_INT_0_sqmuxa_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance UDS_000_INT_0_sqmuxa_1_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance UDS_000_INT_0_sqmuxa_1_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_o3_i_1 "SM_AMIGA_ns_o3_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_108_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_7 "SM_AMIGA_ns_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_98_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_99_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_1 "SM_AMIGA_ns_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_97_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un44_clk_000_d1_1 "state_machine.un44_clk_000_d1_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un44_clk_000_d1 "state_machine.un44_clk_000_d1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_97_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_147_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_7_i "state_machine.LDS_000_INT_7_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_7_i "state_machine.UDS_000_INT_7_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un1_bg_030_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_bg_030_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_bg_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_AS_030_000_SYNC_3_1 "state_machine.AS_030_000_SYNC_3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_AS_030_000_SYNC_3 "state_machine.AS_030_000_SYNC_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename clk_cpu_est_11_0_1_1 "clk.cpu_est_11_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_2_1 "clk.cpu_est_11_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_i_m_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance nEXP_SPACE_m_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_AS_030_000_SYNC_3_i "state_machine.AS_030_000_SYNC_3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_94_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un1_bg_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un44_clk_000_d1_i_0 "state_machine.un44_clk_000_d1_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_105_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_104_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_5 "SM_AMIGA_ns_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -376,28 +394,23 @@ (instance N_107_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance CLK_OUT_PRE_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_o3_i_6 "SM_AMIGA_ns_i_o3_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un44_clk_000_d1_i_0 "state_machine.un44_clk_000_d1_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_98_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_99_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_1 "SM_AMIGA_ns_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o3_i_0 "SM_AMIGA_ns_i_o3_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un13_clk_000_d0_i "state_machine.un13_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un15_clk_000_d0_i "state_machine.un15_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un23_clk_000_d0_i_0 "state_machine.un23_clk_000_d0_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_100_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_2 "SM_AMIGA_ns_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un1_clk_030_i "state_machine.un1_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename clk_un4_clk_000_d1_i "clk.un4_clk_000_d1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un6_bgack_000_i "state_machine.un6_bgack_000_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un23_clk_000_d0_i_0 "state_machine.un23_clk_000_d0_i_0") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un1_clk_030_i "state_machine.un1_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un17_clk_030_i "state_machine.un17_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un1_as_030_3_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_o3_i_1 "SM_AMIGA_ns_o3_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_i_m_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance nEXP_SPACE_m_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_AS_030_000_SYNC_3_i "state_machine.AS_030_000_SYNC_3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_128_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_148_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_7_i "state_machine.UDS_000_INT_7_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_7_i "state_machine.LDS_000_INT_7_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o3_i_4 "SM_AMIGA_ns_i_o3_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_125_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_123_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_124_i (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -409,48 +422,12 @@ (instance N_129_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename clk_cpu_est_11_0_o4_i_3 "clk.cpu_est_11_0_o4_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename clk_cpu_est_11_0_o4_i_1 "clk.cpu_est_11_0_o4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_108_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_7 "SM_AMIGA_ns_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_127_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_128_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un8_clk_000_d0_i "state_machine.un8_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_101_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_102_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_103_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o3_i_0 "SM_AMIGA_ns_i_o3_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o3_i_4 "SM_AMIGA_ns_i_o3_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_127_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_a3_3 "SM_AMIGA_ns_i_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_108 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un14_as_000_int "state_machine.un14_as_000_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance RW_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_i_2 "clk.cpu_est_11_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1_1 "clk.cpu_est_11_0_a4_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_1 "clk.cpu_est_11_0_a4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o3_4 "SM_AMIGA_ns_i_o3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_o3_0 "SM_AMIGA_ns_i_o3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_3 "SM_AMIGA_ns_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_a3_0_4 "SM_AMIGA_ns_i_a3_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -458,49 +435,101 @@ (instance (rename SM_AMIGA_ns_i_a3_4 "SM_AMIGA_ns_i_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_0_1 "clk.cpu_est_11_0_a4_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_2_1 "clk.cpu_est_11_0_a4_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_3 "clk.cpu_est_11_0_a4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_a4_0_3 "clk.cpu_est_11_0_a4_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_o4_1 "clk.cpu_est_11_0_o4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_cpu_est_11_0_o4_3 "clk.cpu_est_11_0_o4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_a3_3 "SM_AMIGA_ns_i_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance I_109 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un14_as_000_int "state_machine.un14_as_000_int") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance RW_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_110 (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un13_clk_000_d0_1 "state_machine.un13_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un13_clk_000_d0_2 "state_machine.un13_clk_000_d0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_0 "cpu_est_0[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_2_1 "clk.cpu_est_11_0_a4_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_1_1 "clk.cpu_est_11_0_a4_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d0_2_i "state_machine.un13_clk_000_d0_2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_r "VPA_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_m "VPA_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_n "VPA_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_p "VPA_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_0_1 "clk.cpu_est_11_0_a4_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_1 "clk.cpu_est_11_0_a4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o3_4 "SM_AMIGA_ns_i_o3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename state_machine_un2_clk_000 "state_machine.un2_clk_000") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename clk_un4_clk_000_d1 "clk.un4_clk_000_d1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un15_clk_000_d0 "state_machine.un15_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un13_clk_000_d0_1_i "state_machine.un13_clk_000_d0_1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_7 "SM_AMIGA_ns_a3[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_7 "SM_AMIGA_ns[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_3 "clk.cpu_est_11_0_a4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_a4_0_3 "clk.cpu_est_11_0_a4_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_i_2 "clk.cpu_est_11_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_o4_1 "clk.cpu_est_11_0_o4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_cpu_est_11_0_o4_3 "clk.cpu_est_11_0_o4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d0_2_i "state_machine.un13_clk_000_d0_2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename state_machine_un23_clk_000_d0 "state_machine.un23_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_r "VPA_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_m "VPA_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_n "VPA_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_p "VPA_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_95_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a3_2 "SM_AMIGA_ns_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_2 "SM_AMIGA_ns[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename state_machine_un17_clk_030 "state_machine.un17_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un1_clk_030 "state_machine.un1_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_96_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__r "DSACK_INT_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__m "DSACK_INT_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__n "DSACK_INT_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK_INT_0_1__p "DSACK_INT_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -517,41 +546,36 @@ (instance (rename FPU_CS_INT_0_m "FPU_CS_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename FPU_CS_INT_0_n "FPU_CS_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename FPU_CS_INT_0_p "FPU_CS_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__r "DSACK_INT_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__m "DSACK_INT_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__n "DSACK_INT_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__p "DSACK_INT_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_96_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_95_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_a3_2 "SM_AMIGA_ns_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_2 "SM_AMIGA_ns[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un23_clk_000_d0 "state_machine.un23_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_r "DTACK_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_m "DTACK_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_n "DTACK_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename DTACK_SYNC_0_p "DTACK_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_AMIGA_BUS_ENABLE_2_iv "state_machine.AMIGA_BUS_ENABLE_2_iv") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance nEXP_SPACE_m (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_SM_AMIGA_0_sqmuxa_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un5_clk_030_i_a3 "state_machine.un5_clk_030_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_7 "state_machine.LDS_000_INT_7") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_7 "state_machine.UDS_000_INT_7") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_030_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_un42_clk_030_i "state_machine.un42_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un1_as_030_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un17_clk_030 "state_machine.un17_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_D2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un30_clk_000_d1 "state_machine.un30_clk_000_d1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un1_clk_030 "state_machine.un1_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_90 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance DSACK_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_030_4_96 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_OUT_PRE_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_91 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_87 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) (instance G_86 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_o3_6 "SM_AMIGA_ns_i_o3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_6 "SM_AMIGA_ns_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -561,28 +585,24 @@ (instance (rename SM_AMIGA_ns_i_a3_0_6 "SM_AMIGA_ns_i_a3_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_a3_6 "SM_AMIGA_ns_i_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_a3_5 "SM_AMIGA_ns_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_AMIGA_BUS_ENABLE_2_iv "state_machine.AMIGA_BUS_ENABLE_2_iv") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance nEXP_SPACE_m (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_o3_1 "SM_AMIGA_ns_o3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CLK_CNT_i_0 "CLK_CNT_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename clk_CLK_CNT_3_0 "clk.CLK_CNT_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename clk_clk_cnt_i "clk.clk_cnt_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename clk_CLK_CNT_3_1 "clk.CLK_CNT_3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_a3_0 "SM_AMIGA_ns_i_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_a3_1 "SM_AMIGA_ns_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_a3_0_1 "SM_AMIGA_ns_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un13_clk_000_d0_1_i "state_machine.un13_clk_000_d0_1_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_a3_7 "SM_AMIGA_ns_a3[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_0 "SM_AMIGA_ns_i[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_1 "SM_AMIGA_ns[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_7 "SM_AMIGA_ns[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_o3_1 "SM_AMIGA_ns_o3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_o3_0 "SM_AMIGA_ns_i_o3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance UDS_000_INT_0_sqmuxa_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance UDS_000_INT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_030_4_95 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_OUT_PRE_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_87 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_133_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_88 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -591,22 +611,15 @@ (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_030_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_7 "state_machine.UDS_000_INT_7") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_7 "state_machine.LDS_000_INT_7") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_D2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un30_clk_000_d1 "state_machine.un30_clk_000_d1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_CNT_i_0 "CLK_CNT_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_un14_as_000_int_i "state_machine.un14_as_000_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename CLK_REF_0 "CLK_REF[0]") (viewRef prim (cellRef DLATSH (libraryRef mach))) ) (instance (rename CLK_REF_1 "CLK_REF[1]") (viewRef prim (cellRef DLATRH (libraryRef mach))) ) (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance FPU_CS_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) (portRef I0 (instanceRef BGACK_030_INT_i)) @@ -624,9 +637,9 @@ )) (net (rename cpu_est_3 "cpu_est[3]") (joined (portRef Q (instanceRef cpu_est_3)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_3)) (portRef I0 (instanceRef cpu_est_0_3__n)) (portRef I0 (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_3)) (portRef I0 (instanceRef clk_cpu_est_11_0_a4_2_1)) (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_3)) (portRef I0 (instanceRef E)) @@ -639,26 +652,26 @@ )) (net (rename cpu_est_0 "cpu_est[0]") (joined (portRef Q (instanceRef cpu_est_0)) - (portRef I1 (instanceRef cpu_est_0_0)) (portRef I0 (instanceRef clk_cpu_est_11_0_o4_3)) (portRef I0 (instanceRef cpu_est_i_0)) (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_1)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d0_3)) + (portRef I1 (instanceRef cpu_est_0_0)) (portRef I0 (instanceRef clk_cpu_est_11_i_a4_1_2)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d0_3)) )) (net (rename cpu_est_1 "cpu_est[1]") (joined (portRef Q (instanceRef cpu_est_1)) + (portRef I1 (instanceRef clk_cpu_est_11_0_o4_3)) (portRef I0 (instanceRef state_machine_un13_clk_000_d0_2)) (portRef I0 (instanceRef cpu_est_i_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_o4_3)) (portRef I0 (instanceRef cpu_est_0_1__n)) (portRef I0 (instanceRef clk_cpu_est_11_i_a4_0_1_2)) )) (net AS_000_INT (joined (portRef Q (instanceRef AS_000_INT)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_0)) (portRef I0 (instanceRef AS_000_INT_0_m)) (portRef I0 (instanceRef state_machine_un13_clk_000_d0_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_0)) (portRef I0 (instanceRef AS_000_INT_i)) (portRef I0 (instanceRef AS_000)) )) @@ -679,8 +692,8 @@ )) (net VPA_SYNC (joined (portRef Q (instanceRef VPA_SYNC)) - (portRef I1 (instanceRef state_machine_un23_clk_000_d0)) (portRef I0 (instanceRef VPA_SYNC_0_m)) + (portRef I1 (instanceRef state_machine_un23_clk_000_d0)) )) (net CLK_000_D0 (joined (portRef Q (instanceRef CLK_000_D0)) @@ -712,9 +725,9 @@ (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined (portRef Q (instanceRef SM_AMIGA_6)) (portRef I1 (instanceRef SM_AMIGA_ns_a3_1)) - (portRef I0 (instanceRef nEXP_SPACE_m)) (portRef I0 (instanceRef SM_AMIGA_i_6)) (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_i_a3)) + (portRef I0 (instanceRef nEXP_SPACE_m)) (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_2)) )) (net VCC (joined @@ -725,20 +738,26 @@ (net GND (joined (portRef LAT (instanceRef CLK_REF_1)) (portRef D (instanceRef CLK_REF_1)) + (portRef LAT (instanceRef CLK_REF_0)) + (portRef D (instanceRef CLK_REF_0)) (portRef I0 (instanceRef AVEC_EXP)) (portRef I0 (instanceRef BERR)) )) (net (rename cpu_est_2 "cpu_est[2]") (joined (portRef Q (instanceRef cpu_est_2)) - (portRef I1 (instanceRef state_machine_un13_clk_000_d0_2)) - (portRef I0 (instanceRef cpu_est_i_2)) (portRef I0 (instanceRef cpu_est_0_2__n)) - (portRef I1 (instanceRef state_machine_un8_clk_000_d0_3)) + (portRef I0 (instanceRef cpu_est_i_2)) + (portRef I1 (instanceRef state_machine_un13_clk_000_d0_2)) (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_2)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d0_3)) + )) + (net (rename CLK_REF_0 "CLK_REF[0]") (joined + (portRef Q (instanceRef CLK_REF_0)) + (portRef I1 (instanceRef G_86)) )) (net (rename CLK_REF_1 "CLK_REF[1]") (joined (portRef Q (instanceRef CLK_REF_1)) - (portRef I1 (instanceRef G_86)) + (portRef I1 (instanceRef G_87)) )) (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined (portRef Q (instanceRef SM_AMIGA_7)) @@ -760,23 +779,6 @@ (portRef I0 (instanceRef DSACK_INT_0_1__m)) (portRef I0 (instanceRef DSACK_1)) )) - (net (rename clk_un4_clk_000_d1 "clk.un4_clk_000_d1") (joined - (portRef O (instanceRef clk_un4_clk_000_d1)) - (portRef I1 (instanceRef cpu_est_0_3__m)) - (portRef I0 (instanceRef cpu_est_0_3__r)) - (portRef I0 (instanceRef cpu_est_0_0)) - (portRef I1 (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__r)) - (portRef I1 (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef IPL_030_0_0__m)) - (portRef I0 (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef IPL_030_0_1__m)) - (portRef I0 (instanceRef IPL_030_0_1__r)) - (portRef I1 (instanceRef IPL_030_0_2__m)) - (portRef I0 (instanceRef IPL_030_0_2__r)) - (portRef I0 (instanceRef clk_un4_clk_000_d1_i)) - )) (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined (portRef Q (instanceRef SM_AMIGA_4)) (portRef I0 (instanceRef SM_AMIGA_i_4)) @@ -792,19 +794,20 @@ (portRef I0 (instanceRef DTACK)) )) (net (rename clk_clk_cnt "clk.clk_cnt") (joined - (portRef O (instanceRef G_87)) - (portRef I1 (instanceRef CLK_OUT_PRE_0)) + (portRef O (instanceRef G_88)) (portRef I0 (instanceRef clk_clk_cnt_i)) + (portRef I1 (instanceRef CLK_OUT_PRE_0)) )) (net (rename CLK_CNT_0 "CLK_CNT[0]") (joined (portRef Q (instanceRef CLK_CNT_0)) (portRef I0 (instanceRef CLK_CNT_i_0)) - (portRef I0 (instanceRef G_90)) + (portRef I0 (instanceRef G_86)) + (portRef I0 (instanceRef G_91)) )) (net (rename CLK_CNT_1 "CLK_CNT[1]") (joined (portRef Q (instanceRef CLK_CNT_1)) - (portRef I0 (instanceRef G_86)) - (portRef I1 (instanceRef G_90)) + (portRef I0 (instanceRef G_87)) + (portRef I1 (instanceRef G_91)) )) (net (rename state_machine_un14_as_000_int "state_machine.un14_as_000_int") (joined (portRef O (instanceRef state_machine_un14_as_000_int)) @@ -812,11 +815,11 @@ )) (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined (portRef Q (instanceRef SM_AMIGA_3)) - (portRef I0 (instanceRef SM_AMIGA_i_3)) (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_4)) + (portRef I0 (instanceRef SM_AMIGA_i_3)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_0)) (portRef I1 (instanceRef SM_AMIGA_ns_a3_0_1_5)) (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_0)) )) (net (rename clk_CLK_CNT_3_0 "clk.CLK_CNT_3[0]") (joined (portRef O (instanceRef clk_CLK_CNT_3_0)) @@ -826,13 +829,6 @@ (portRef O (instanceRef clk_CLK_CNT_3_1)) (portRef D (instanceRef CLK_CNT_1)) )) - (net un1_as_030_4 (joined - (portRef O (instanceRef un1_as_030_4)) - (portRef I1 (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_r)) - (portRef I1 (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_r)) - )) (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined (portRef Q (instanceRef SM_AMIGA_5)) (portRef I1 (instanceRef SM_AMIGA_ns_a3_2)) @@ -845,16 +841,8 @@ )) (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined (portRef Q (instanceRef SM_AMIGA_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_7)) (portRef I1 (instanceRef SM_AMIGA_ns_i_o3_0)) - )) - (net (rename state_machine_LDS_000_INT_7 "state_machine.LDS_000_INT_7") (joined - (portRef O (instanceRef state_machine_LDS_000_INT_7_i)) - (portRef I0 (instanceRef LDS_000_INT_0_n)) - )) - (net (rename state_machine_UDS_000_INT_7 "state_machine.UDS_000_INT_7") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_7_i)) - (portRef I0 (instanceRef UDS_000_INT_0_n)) + (portRef I0 (instanceRef SM_AMIGA_ns_a3_7)) )) (net N_1 (joined (portRef O (instanceRef UDS_000_INT_0_p)) @@ -901,13 +889,13 @@ (portRef D (instanceRef VMA_INT)) )) (net N_12 (joined - (portRef O (instanceRef CLK_OUT_PRE_0)) - (portRef D (instanceRef CLK_OUT_PRE)) - )) - (net N_13 (joined (portRef O (instanceRef BGACK_030_INT_0_p)) (portRef D (instanceRef BGACK_030_INT)) )) + (net N_13 (joined + (portRef O (instanceRef CLK_OUT_PRE_0)) + (portRef D (instanceRef CLK_OUT_PRE)) + )) (net N_14 (joined (portRef O (instanceRef cpu_est_0_0)) (portRef D (instanceRef cpu_est_0)) @@ -956,26 +944,30 @@ (portRef O (instanceRef G_86)) (portRef I0 (instanceRef N_132_i)) )) + (net N_133 (joined + (portRef O (instanceRef G_87)) + (portRef I0 (instanceRef N_133_i)) + )) (net (rename state_machine_un30_clk_000_d1 "state_machine.un30_clk_000_d1") (joined (portRef O (instanceRef state_machine_un30_clk_000_d1)) (portRef I1 (instanceRef SM_AMIGA_ns_o3_1)) (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1)) )) - (net N_147 (joined - (portRef O (instanceRef un1_as_030_4_95)) + (net N_148 (joined + (portRef O (instanceRef un1_as_030_4_96)) (portRef I1 (instanceRef un1_as_030_4)) - (portRef I0 (instanceRef N_147_i)) + (portRef I0 (instanceRef N_148_i)) + )) + (net DTACK_SYNC_1_sqmuxa (joined + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_i)) )) (net N_96 (joined (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_a3)) (portRef I0 (instanceRef N_96_i)) )) - (net (rename state_machine_un44_clk_000_d1 "state_machine.un44_clk_000_d1") (joined - (portRef O (instanceRef state_machine_un44_clk_000_d1_i_0)) - (portRef I1 (instanceRef state_machine_LDS_000_INT_7)) - )) (net (rename un3_clk_cnt_1 "un3_clk_cnt[1]") (joined - (portRef O (instanceRef G_90)) + (portRef O (instanceRef G_91)) (portRef I1 (instanceRef clk_CLK_CNT_3_1)) )) (net N_89 (joined @@ -998,6 +990,10 @@ (portRef O (instanceRef SM_AMIGA_ns_a3_0_1)) (portRef I0 (instanceRef N_99_i)) )) + (net N_108 (joined + (portRef O (instanceRef SM_AMIGA_ns_a3_7)) + (portRef I0 (instanceRef N_108_i)) + )) (net UDS_000_INT_0_sqmuxa (joined (portRef O (instanceRef UDS_000_INT_0_sqmuxa)) (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_i)) @@ -1006,11 +1002,16 @@ (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1)) (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_i)) )) - (net N_167 (joined + (net (rename state_machine_un13_clk_000_d0_1 "state_machine.un13_clk_000_d0_1") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d0_1)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d0_1_i)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d0_2_0)) + )) + (net N_168 (joined (portRef O (instanceRef un8_ciin)) (portRef OE (instanceRef CIIN)) )) - (net N_170 (joined + (net N_171 (joined (portRef O (instanceRef un4_ciin)) (portRef I0 (instanceRef CIIN)) )) @@ -1039,6 +1040,10 @@ (portRef I1 (instanceRef un1_as_030_3)) (portRef I0 (instanceRef state_machine_un42_clk_030_i)) )) + (net (rename state_machine_un44_clk_000_d1 "state_machine.un44_clk_000_d1") (joined + (portRef O (instanceRef state_machine_un44_clk_000_d1_i_0)) + (portRef I1 (instanceRef state_machine_LDS_000_INT_7)) + )) (net un1_bg_030 (joined (portRef O (instanceRef un1_bg_030_i)) (portRef I0 (instanceRef BG_000_0_m)) @@ -1063,10 +1068,35 @@ (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_i_a3)) (portRef I0 (instanceRef N_95_i)) )) + (net (rename state_machine_LDS_000_INT_7 "state_machine.LDS_000_INT_7") (joined + (portRef O (instanceRef state_machine_LDS_000_INT_7_i)) + (portRef I0 (instanceRef LDS_000_INT_0_n)) + )) + (net (rename state_machine_UDS_000_INT_7 "state_machine.UDS_000_INT_7") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_7_i)) + (portRef I0 (instanceRef UDS_000_INT_0_n)) + )) + (net DTACK_SYNC_1_sqmuxa_1 (joined + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1)) + (portRef I1 (instanceRef DTACK_SYNC_0_m)) + (portRef I0 (instanceRef DTACK_SYNC_0_r)) + )) + (net un1_as_030_4 (joined + (portRef O (instanceRef un1_as_030_4)) + (portRef I1 (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_r)) + (portRef I1 (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_r)) + )) (net un1_as_030_3 (joined (portRef O (instanceRef un1_as_030_3_i)) (portRef I0 (instanceRef FPU_CS_INT_0_m)) )) + (net DSACK_INT_1_sqmuxa (joined + (portRef O (instanceRef DSACK_INT_1_sqmuxa)) + (portRef I1 (instanceRef DSACK_INT_0_1__m)) + (portRef I0 (instanceRef DSACK_INT_0_1__r)) + )) (net (rename state_machine_un17_clk_030 "state_machine.un17_clk_030") (joined (portRef O (instanceRef state_machine_un17_clk_030_i)) (portRef I1 (instanceRef FPU_CS_INT_0_m)) @@ -1074,43 +1104,15 @@ (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) )) - (net (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (joined - (portRef O (instanceRef state_machine_un6_bgack_000_i)) - (portRef I1 (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_r)) - )) (net (rename state_machine_un1_clk_030 "state_machine.un1_clk_030") (joined (portRef O (instanceRef state_machine_un1_clk_030_i)) (portRef I1 (instanceRef BG_000_0_m)) (portRef I0 (instanceRef BG_000_0_r)) )) - (net AS_000_INT_1_sqmuxa (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa)) - (portRef I1 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_r)) - )) - (net DSACK_INT_1_sqmuxa (joined - (portRef O (instanceRef DSACK_INT_1_sqmuxa)) - (portRef I1 (instanceRef DSACK_INT_0_1__m)) - (portRef I0 (instanceRef DSACK_INT_0_1__r)) - )) - (net N_100 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_2)) - (portRef I0 (instanceRef N_100_i)) - )) (net (rename state_machine_un23_clk_000_d0 "state_machine.un23_clk_000_d0") (joined (portRef O (instanceRef state_machine_un23_clk_000_d0_i_0)) (portRef I1 (instanceRef SM_AMIGA_ns_a3_0_5)) )) - (net DTACK_SYNC_1_sqmuxa (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_i)) - )) - (net DTACK_SYNC_1_sqmuxa_1 (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1)) - (portRef I1 (instanceRef DTACK_SYNC_0_m)) - (portRef I0 (instanceRef DTACK_SYNC_0_r)) - )) (net VPA_SYNC_1_sqmuxa (joined (portRef O (instanceRef VPA_SYNC_1_sqmuxa)) (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_i)) @@ -1120,6 +1122,37 @@ (portRef I1 (instanceRef VPA_SYNC_0_m)) (portRef I0 (instanceRef VPA_SYNC_0_r)) )) + (net AS_000_INT_1_sqmuxa (joined + (portRef O (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I1 (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_r)) + )) + (net (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (joined + (portRef O (instanceRef state_machine_un6_bgack_000_i)) + (portRef I1 (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_r)) + )) + (net (rename clk_un4_clk_000_d1 "clk.un4_clk_000_d1") (joined + (portRef O (instanceRef clk_un4_clk_000_d1)) + (portRef I1 (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_0_3__r)) + (portRef I0 (instanceRef cpu_est_0_0)) + (portRef I1 (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__r)) + (portRef I0 (instanceRef clk_un4_clk_000_d1_i)) + )) + (net N_100 (joined + (portRef O (instanceRef SM_AMIGA_ns_a3_2)) + (portRef I0 (instanceRef N_100_i)) + )) (net (rename state_machine_un15_clk_000_d0 "state_machine.un15_clk_000_d0") (joined (portRef O (instanceRef state_machine_un15_clk_000_d0_i)) (portRef I1 (instanceRef VMA_INT_0_m)) @@ -1131,8 +1164,8 @@ )) (net (rename state_machine_un2_clk_000 "state_machine.un2_clk_000") (joined (portRef O (instanceRef state_machine_un2_clk_000)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_2)) (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_4)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_2)) )) (net (rename state_machine_un13_clk_000_d0 "state_machine.un13_clk_000_d0") (joined (portRef O (instanceRef state_machine_un13_clk_000_d0)) @@ -1142,29 +1175,6 @@ (portRef O (instanceRef state_machine_un8_clk_000_d0)) (portRef I0 (instanceRef state_machine_un8_clk_000_d0_i)) )) - (net N_108 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_7)) - (portRef I0 (instanceRef N_108_i)) - )) - (net (rename state_machine_un13_clk_000_d0_1 "state_machine.un13_clk_000_d0_1") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d0_1)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d0_1_i)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d0_2_0)) - )) - (net N_124 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_0_1)) - (portRef I0 (instanceRef N_124_i)) - )) - (net N_126 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_2_1)) - (portRef I0 (instanceRef N_126_i)) - )) - (net (rename state_machine_un13_clk_000_d0_2 "state_machine.un13_clk_000_d0_2") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d0_2)) - (portRef I0 (instanceRef state_machine_un13_clk_000_d0_2_i)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_2_1)) - (portRef I1 (instanceRef state_machine_un13_clk_000_d0_2_0)) - )) (net N_129 (joined (portRef O (instanceRef clk_cpu_est_11_0_a4_3)) (portRef I0 (instanceRef N_129_i)) @@ -1177,26 +1187,40 @@ (portRef O (instanceRef clk_cpu_est_11_0_a4_0_3)) (portRef I0 (instanceRef N_130_i)) )) + (net N_127 (joined + (portRef O (instanceRef clk_cpu_est_11_i_a4_2)) + (portRef I0 (instanceRef N_127_i)) + )) + (net N_128 (joined + (portRef O (instanceRef clk_cpu_est_11_i_a4_0_2)) + (portRef I0 (instanceRef N_128_i)) + )) (net N_121 (joined (portRef O (instanceRef clk_cpu_est_11_0_o4_i_1)) (portRef I0 (instanceRef VMA_INT_0_m)) (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1)) )) + (net (rename state_machine_un13_clk_000_d0_2 "state_machine.un13_clk_000_d0_2") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d0_2)) + (portRef I0 (instanceRef state_machine_un13_clk_000_d0_2_i)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_2_1)) + (portRef I1 (instanceRef state_machine_un13_clk_000_d0_2_0)) + )) (net N_131 (joined (portRef O (instanceRef clk_cpu_est_11_0_a4_1_3)) (portRef I0 (instanceRef N_131_i)) )) - (net N_127 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_2)) - (portRef I0 (instanceRef N_127_i)) - )) (net (rename clk_cpu_est_11_1 "clk.cpu_est_11[1]") (joined (portRef O (instanceRef clk_cpu_est_11_0_i_1)) (portRef I0 (instanceRef cpu_est_0_1__m)) )) - (net N_128 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_0_2)) - (portRef I0 (instanceRef N_128_i)) + (net N_126 (joined + (portRef O (instanceRef clk_cpu_est_11_0_a4_2_1)) + (portRef I0 (instanceRef N_126_i)) + )) + (net N_124 (joined + (portRef O (instanceRef clk_cpu_est_11_0_a4_0_1)) + (portRef I0 (instanceRef N_124_i)) )) (net N_123 (joined (portRef O (instanceRef clk_cpu_est_11_0_a4_1)) @@ -1232,13 +1256,13 @@ (portRef I0 (instanceRef state_machine_un14_as_000_int)) )) (net (rename DSACK_i_1 "DSACK_i[1]") (joined - (portRef O (instanceRef I_108)) + (portRef O (instanceRef I_109)) (portRef I1 (instanceRef state_machine_un14_as_000_int)) )) (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined (portRef O (instanceRef SM_AMIGA_i_4)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_0_4)) (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_3)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_a3_0_4)) )) (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined (portRef O (instanceRef SM_AMIGA_i_5)) @@ -1251,8 +1275,8 @@ (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_6)) (portRef I0 (instanceRef SM_AMIGA_ns_i_a3_4)) (portRef I0 (instanceRef SM_AMIGA_ns_i_3)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_0_1_5)) (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a3_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_a3_0_1_5)) (portRef I0 (instanceRef state_machine_un8_clk_000_d0_2)) )) (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined @@ -1263,10 +1287,18 @@ (portRef O (instanceRef cpu_est_i_0)) (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1)) (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_1_3)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_3)) (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_1_2)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_3)) (portRef I0 (instanceRef state_machine_un13_clk_000_d0_1_0)) )) + (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined + (portRef O (instanceRef cpu_est_i_3)) + (portRef I1 (instanceRef clk_cpu_est_11_0_o4_1)) + (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_1)) + (portRef I1 (instanceRef clk_cpu_est_11_i_a4_1_2)) + (portRef I1 (instanceRef state_machine_un13_clk_000_d0_1_0)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d0_1)) + )) (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined (portRef O (instanceRef cpu_est_i_2)) (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_3)) @@ -1274,67 +1306,50 @@ (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_3)) (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_2)) )) - (net (rename state_machine_un13_clk_000_d0_2_i "state_machine.un13_clk_000_d0_2_i") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d0_2_i)) - (portRef I1 (instanceRef clk_cpu_est_11_i_a4_2)) - )) - (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined - (portRef O (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef clk_cpu_est_11_0_o4_1)) - (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_1)) - (portRef I1 (instanceRef state_machine_un8_clk_000_d0_1)) - (portRef I1 (instanceRef clk_cpu_est_11_i_a4_1_2)) - (portRef I1 (instanceRef state_machine_un13_clk_000_d0_1_0)) - )) (net VPA_D_i (joined (portRef O (instanceRef VPA_D_i)) - (portRef I1 (instanceRef state_machine_un8_clk_000_d0_2)) (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_2)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d0_2)) )) (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined (portRef O (instanceRef cpu_est_i_1)) (portRef I0 (instanceRef clk_cpu_est_11_0_o4_1)) (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_1_3)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d0_1)) (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_4)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d0_1)) )) (net DTACK_i (joined - (portRef O (instanceRef I_109)) + (portRef O (instanceRef I_110)) (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) )) (net VMA_INT_i (joined (portRef O (instanceRef VMA_INT_i)) (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_0)) )) - (net (rename state_machine_un13_clk_000_d0_1_i "state_machine.un13_clk_000_d0_1_i") (joined - (portRef O (instanceRef state_machine_un13_clk_000_d0_1_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_a3_7)) + (net (rename state_machine_un13_clk_000_d0_2_i "state_machine.un13_clk_000_d0_2_i") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d0_2_i)) + (portRef I1 (instanceRef clk_cpu_est_11_i_a4_2)) )) - (net AS_030_i (joined - (portRef O (instanceRef AS_030_i)) - (portRef I0 (instanceRef un1_as_030_4)) - (portRef I0 (instanceRef state_machine_un17_clk_030)) - (portRef I0 (instanceRef un1_as_030_3)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa)) - (portRef I0 (instanceRef DSACK_INT_1_sqmuxa)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1)) - (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3_1)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_i_m_1)) - )) - (net DTACK_SYNC_1_sqmuxa_i (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_i)) - (portRef I0 (instanceRef DTACK_SYNC_0_n)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1)) + (net CLK_000_D1_i (joined + (portRef O (instanceRef CLK_000_D1_i)) + (portRef I1 (instanceRef clk_un4_clk_000_d1)) )) (net VPA_SYNC_1_sqmuxa_i (joined (portRef O (instanceRef VPA_SYNC_1_sqmuxa_i)) (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1)) (portRef I0 (instanceRef VPA_SYNC_0_n)) )) - (net CLK_000_D1_i (joined - (portRef O (instanceRef CLK_000_D1_i)) - (portRef I1 (instanceRef clk_un4_clk_000_d1)) + (net AS_030_i (joined + (portRef O (instanceRef AS_030_i)) + (portRef I0 (instanceRef DSACK_INT_1_sqmuxa)) + (portRef I0 (instanceRef un1_as_030_3)) + (portRef I0 (instanceRef un1_as_030_4)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1)) + (portRef I0 (instanceRef state_machine_un17_clk_030)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1)) + (portRef I0 (instanceRef AS_000_INT_1_sqmuxa)) + (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3_1)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_i_m_1)) )) (net N_95_i (joined (portRef O (instanceRef N_95_i)) @@ -1342,11 +1357,16 @@ (portRef I1 (instanceRef AS_000_INT_1_sqmuxa)) (portRef I0 (instanceRef AS_000_INT_0_n)) )) + (net DTACK_SYNC_1_sqmuxa_i (joined + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_i)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1)) + (portRef I0 (instanceRef DTACK_SYNC_0_n)) + )) (net N_96_i (joined (portRef O (instanceRef N_96_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_7)) (portRef I1 (instanceRef DSACK_INT_1_sqmuxa)) (portRef I0 (instanceRef DSACK_INT_0_1__n)) - (portRef I0 (instanceRef SM_AMIGA_ns_7)) )) (net (rename A_i_18 "A_i[18]") (joined (portRef O (instanceRef A_i_18)) @@ -1364,10 +1384,6 @@ (portRef O (instanceRef CLK_030_i)) (portRef I1 (instanceRef state_machine_un17_clk_030)) )) - (net CLK_000_D2_i (joined - (portRef O (instanceRef CLK_000_D2_i)) - (portRef I1 (instanceRef state_machine_un30_clk_000_d1)) - )) (net (rename state_machine_un42_clk_030_i "state_machine.un42_clk_030_i") (joined (portRef O (instanceRef state_machine_un42_clk_030_i)) (portRef I1 (instanceRef state_machine_AS_030_000_SYNC_3)) @@ -1401,8 +1417,8 @@ )) (net DS_030_i (joined (portRef O (instanceRef DS_030_i)) - (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_0)) (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_1)) + (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_0)) )) (net AS_030_000_SYNC_i (joined (portRef O (instanceRef AS_030_000_SYNC_i)) @@ -1411,11 +1427,15 @@ )) (net UDS_000_INT_0_sqmuxa_1_i (joined (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_i)) - (portRef I0 (instanceRef un1_as_030_4_95)) + (portRef I0 (instanceRef un1_as_030_4_96)) )) (net UDS_000_INT_0_sqmuxa_i (joined (portRef O (instanceRef UDS_000_INT_0_sqmuxa_i)) - (portRef I1 (instanceRef un1_as_030_4_95)) + (portRef I1 (instanceRef un1_as_030_4_96)) + )) + (net (rename state_machine_un13_clk_000_d0_1_i "state_machine.un13_clk_000_d0_1_i") (joined + (portRef O (instanceRef state_machine_un13_clk_000_d0_1_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_a3_7)) )) (net (rename clk_clk_cnt_i "clk.clk_cnt_i") (joined (portRef O (instanceRef clk_clk_cnt_i)) @@ -1424,9 +1444,12 @@ )) (net (rename CLK_CNT_i_0 "CLK_CNT_i[0]") (joined (portRef O (instanceRef CLK_CNT_i_0)) - (portRef I0 (instanceRef G_87)) (portRef I0 (instanceRef clk_CLK_CNT_3_0)) )) + (net CLK_000_D2_i (joined + (portRef O (instanceRef CLK_000_D2_i)) + (portRef I1 (instanceRef state_machine_un30_clk_000_d1)) + )) (net (rename A_i_30 "A_i[30]") (joined (portRef O (instanceRef A_i_30)) (portRef I0 (instanceRef un8_ciin_4)) @@ -1461,7 +1484,11 @@ )) (net N_132_i (joined (portRef O (instanceRef N_132_i)) - (portRef I1 (instanceRef G_87)) + (portRef I0 (instanceRef G_88)) + )) + (net N_133_i (joined + (portRef O (instanceRef N_133_i)) + (portRef I1 (instanceRef G_88)) )) (net (rename state_machine_un14_as_000_int_i "state_machine.un14_as_000_int_i") (joined (portRef O (instanceRef state_machine_un14_as_000_int_i)) @@ -1470,6 +1497,7 @@ (net RST_i (joined (portRef O (instanceRef RST_i)) (portRef R (instanceRef CLK_REF_1)) + (portRef S (instanceRef CLK_REF_0)) (portRef S (instanceRef AS_000_INT)) (portRef S (instanceRef AS_030_000_SYNC)) (portRef S (instanceRef BGACK_030_INT)) @@ -1534,7 +1562,7 @@ )) (net (rename SIZE_c_0 "SIZE_c[0]") (joined (portRef O (instanceRef SIZE_0)) - (portRef I1 (instanceRef state_machine_un44_clk_000_d1)) + (portRef I0 (instanceRef state_machine_un44_clk_000_d1_1)) )) (net (rename SIZE_0 "SIZE[0]") (joined (portRef (member size 1)) @@ -1912,7 +1940,7 @@ )) (net (rename DSACK_c_1 "DSACK_c[1]") (joined (portRef O (instanceRef DSACK_1)) - (portRef I0 (instanceRef I_108)) + (portRef I0 (instanceRef I_109)) )) (net (rename DSACK_1 "DSACK[1]") (joined (portRef (member dsack 0)) @@ -1920,7 +1948,7 @@ )) (net DTACK_c (joined (portRef O (instanceRef DTACK)) - (portRef I0 (instanceRef I_109)) + (portRef I0 (instanceRef I_110)) )) (net DTACK (joined (portRef IO (instanceRef DTACK)) @@ -2036,26 +2064,10 @@ (portRef O (instanceRef SM_AMIGA_ns_i_4)) (portRef D (instanceRef SM_AMIGA_3)) )) - (net N_90_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_o3_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_i_0)) - )) (net N_91_0 (joined (portRef O (instanceRef SM_AMIGA_ns_i_o3_4)) (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_i_4)) )) - (net N_127_i (joined - (portRef O (instanceRef N_127_i)) - (portRef I0 (instanceRef clk_cpu_est_11_i_2)) - )) - (net N_128_i (joined - (portRef O (instanceRef N_128_i)) - (portRef I1 (instanceRef clk_cpu_est_11_i_2)) - )) - (net N_118_i (joined - (portRef O (instanceRef clk_cpu_est_11_i_2)) - (portRef I0 (instanceRef cpu_est_0_2__m)) - )) (net N_125_i (joined (portRef O (instanceRef N_125_i)) (portRef I1 (instanceRef clk_cpu_est_11_0_2_1)) @@ -2102,13 +2114,17 @@ (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_1)) (portRef I0 (instanceRef clk_cpu_est_11_0_o4_i_1)) )) - (net N_108_i (joined - (portRef O (instanceRef N_108_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_7)) + (net N_127_i (joined + (portRef O (instanceRef N_127_i)) + (portRef I0 (instanceRef clk_cpu_est_11_i_2)) )) - (net (rename SM_AMIGA_ns_0_7 "SM_AMIGA_ns_0[7]") (joined - (portRef O (instanceRef SM_AMIGA_ns_7)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_7)) + (net N_128_i (joined + (portRef O (instanceRef N_128_i)) + (portRef I1 (instanceRef clk_cpu_est_11_i_2)) + )) + (net N_118_i (joined + (portRef O (instanceRef clk_cpu_est_11_i_2)) + (portRef I0 (instanceRef cpu_est_0_2__m)) )) (net (rename state_machine_un8_clk_000_d0_i "state_machine.un8_clk_000_d0_i") (joined (portRef O (instanceRef state_machine_un8_clk_000_d0_i)) @@ -2122,11 +2138,6 @@ (portRef O (instanceRef state_machine_un15_clk_000_d0)) (portRef I0 (instanceRef state_machine_un15_clk_000_d0_i)) )) - (net (rename state_machine_un23_clk_000_d0_i "state_machine.un23_clk_000_d0_i") (joined - (portRef O (instanceRef state_machine_un23_clk_000_d0)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_o3_4)) - (portRef I0 (instanceRef state_machine_un23_clk_000_d0_i_0)) - )) (net N_100_i (joined (portRef O (instanceRef N_100_i)) (portRef I1 (instanceRef SM_AMIGA_ns_2)) @@ -2135,6 +2146,19 @@ (portRef O (instanceRef SM_AMIGA_ns_2)) (portRef I0 (instanceRef SM_AMIGA_ns_i_2)) )) + (net (rename clk_un4_clk_000_d1_i "clk.un4_clk_000_d1_i") (joined + (portRef O (instanceRef clk_un4_clk_000_d1_i)) + (portRef I1 (instanceRef state_machine_un6_bgack_000)) + )) + (net (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (joined + (portRef O (instanceRef state_machine_un6_bgack_000)) + (portRef I0 (instanceRef state_machine_un6_bgack_000_i)) + )) + (net (rename state_machine_un23_clk_000_d0_i "state_machine.un23_clk_000_d0_i") (joined + (portRef O (instanceRef state_machine_un23_clk_000_d0)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_o3_4)) + (portRef I0 (instanceRef state_machine_un23_clk_000_d0_i_0)) + )) (net BG_030_c_i (joined (portRef O (instanceRef BG_030_c_i)) (portRef I0 (instanceRef state_machine_un1_clk_030)) @@ -2144,14 +2168,6 @@ (portRef O (instanceRef state_machine_un1_clk_030)) (portRef I0 (instanceRef state_machine_un1_clk_030_i)) )) - (net (rename clk_un4_clk_000_d1_i "clk.un4_clk_000_d1_i") (joined - (portRef O (instanceRef clk_un4_clk_000_d1_i)) - (portRef I1 (instanceRef state_machine_un6_bgack_000)) - )) - (net (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (joined - (portRef O (instanceRef state_machine_un6_bgack_000)) - (portRef I0 (instanceRef state_machine_un6_bgack_000_i)) - )) (net (rename state_machine_un17_clk_030_0 "state_machine.un17_clk_030_0") (joined (portRef O (instanceRef state_machine_un17_clk_030)) (portRef I0 (instanceRef state_machine_un17_clk_030_i)) @@ -2160,10 +2176,23 @@ (portRef O (instanceRef un1_as_030_3)) (portRef I0 (instanceRef un1_as_030_3_i)) )) - (net N_89_i (joined - (portRef O (instanceRef SM_AMIGA_ns_o3_1)) - (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_i_a3)) - (portRef I0 (instanceRef SM_AMIGA_ns_o3_i_1)) + (net N_148_i (joined + (portRef O (instanceRef N_148_i)) + (portRef I1 (instanceRef state_machine_UDS_000_INT_7)) + (portRef I0 (instanceRef state_machine_LDS_000_INT_7)) + )) + (net (rename A_c_i_0 "A_c_i[0]") (joined + (portRef O (instanceRef A_c_i_0)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_7)) + (portRef I1 (instanceRef state_machine_un44_clk_000_d1_1)) + )) + (net (rename state_machine_UDS_000_INT_7_0 "state_machine.UDS_000_INT_7_0") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_7)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_7_i)) + )) + (net (rename state_machine_LDS_000_INT_7_0 "state_machine.LDS_000_INT_7_0") (joined + (portRef O (instanceRef state_machine_LDS_000_INT_7)) + (portRef I0 (instanceRef state_machine_LDS_000_INT_7_i)) )) (net AMIGA_BUS_ENABLE_i_m_i (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_i_m_i)) @@ -2189,6 +2218,14 @@ (portRef O (instanceRef un1_bg_030)) (portRef I0 (instanceRef un1_bg_030_i)) )) + (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined + (portRef O (instanceRef SIZE_c_i_1)) + (portRef I1 (instanceRef state_machine_un44_clk_000_d1)) + )) + (net (rename state_machine_un44_clk_000_d1_i "state_machine.un44_clk_000_d1_i") (joined + (portRef O (instanceRef state_machine_un44_clk_000_d1)) + (portRef I0 (instanceRef state_machine_un44_clk_000_d1_i_0)) + )) (net N_105_i (joined (portRef O (instanceRef N_105_i)) (portRef I1 (instanceRef SM_AMIGA_ns_5)) @@ -2221,18 +2258,22 @@ (portRef O (instanceRef SM_AMIGA_ns_i_o3_6)) (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_i_6)) )) - (net (rename state_machine_un44_clk_000_d1_i "state_machine.un44_clk_000_d1_i") (joined - (portRef O (instanceRef state_machine_un44_clk_000_d1)) - (portRef I0 (instanceRef state_machine_un44_clk_000_d1_i_0)) + (net N_90_0 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_o3_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_o3_i_0)) )) - (net (rename A_c_i_0 "A_c_i[0]") (joined - (portRef O (instanceRef A_c_i_0)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_7)) - (portRef I1 (instanceRef state_machine_un44_clk_000_d1_1)) + (net N_89_i (joined + (portRef O (instanceRef SM_AMIGA_ns_o3_1)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_i_a3)) + (portRef I0 (instanceRef SM_AMIGA_ns_o3_i_1)) )) - (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined - (portRef O (instanceRef SIZE_c_i_1)) - (portRef I0 (instanceRef state_machine_un44_clk_000_d1_1)) + (net N_108_i (joined + (portRef O (instanceRef N_108_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_7)) + )) + (net (rename SM_AMIGA_ns_0_7 "SM_AMIGA_ns_0[7]") (joined + (portRef O (instanceRef SM_AMIGA_ns_7)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_7)) )) (net N_98_i (joined (portRef O (instanceRef N_98_i)) @@ -2254,18 +2295,9 @@ (portRef O (instanceRef SM_AMIGA_ns_i_0)) (portRef D (instanceRef SM_AMIGA_7)) )) - (net N_147_i (joined - (portRef O (instanceRef N_147_i)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_7)) - (portRef I1 (instanceRef state_machine_UDS_000_INT_7)) - )) - (net (rename state_machine_LDS_000_INT_7_0 "state_machine.LDS_000_INT_7_0") (joined - (portRef O (instanceRef state_machine_LDS_000_INT_7)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_7_i)) - )) - (net (rename state_machine_UDS_000_INT_7_0 "state_machine.UDS_000_INT_7_0") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_7)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_7_i)) + (net (rename state_machine_un44_clk_000_d1_i_1 "state_machine.un44_clk_000_d1_i_1") (joined + (portRef O (instanceRef state_machine_un44_clk_000_d1_1)) + (portRef I0 (instanceRef state_machine_un44_clk_000_d1)) )) (net un1_bg_030_0_1 (joined (portRef O (instanceRef un1_bg_030_1)) @@ -2287,35 +2319,35 @@ (portRef O (instanceRef clk_cpu_est_11_0_2_1)) (portRef I1 (instanceRef clk_cpu_est_11_0_1)) )) - (net N_167_1 (joined + (net N_168_1 (joined (portRef O (instanceRef un8_ciin_1)) (portRef I0 (instanceRef un8_ciin_5)) )) - (net N_167_2 (joined + (net N_168_2 (joined (portRef O (instanceRef un8_ciin_2)) (portRef I1 (instanceRef un8_ciin_5)) )) - (net N_167_3 (joined + (net N_168_3 (joined (portRef O (instanceRef un8_ciin_3)) (portRef I0 (instanceRef un8_ciin_6)) )) - (net N_167_4 (joined + (net N_168_4 (joined (portRef O (instanceRef un8_ciin_4)) (portRef I1 (instanceRef un8_ciin_6)) )) - (net N_167_5 (joined + (net N_168_5 (joined (portRef O (instanceRef un8_ciin_5)) (portRef I0 (instanceRef un8_ciin)) )) - (net N_167_6 (joined + (net N_168_6 (joined (portRef O (instanceRef un8_ciin_6)) (portRef I1 (instanceRef un8_ciin)) )) - (net N_170_1 (joined + (net N_171_1 (joined (portRef O (instanceRef un4_ciin_1)) (portRef I0 (instanceRef un4_ciin)) )) - (net N_170_2 (joined + (net N_171_2 (joined (portRef O (instanceRef un4_ciin_2)) (portRef I1 (instanceRef un4_ciin)) )) @@ -2335,9 +2367,9 @@ (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_0)) (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa)) )) - (net (rename state_machine_un44_clk_000_d1_i_1 "state_machine.un44_clk_000_d1_i_1") (joined - (portRef O (instanceRef state_machine_un44_clk_000_d1_1)) - (portRef I0 (instanceRef state_machine_un44_clk_000_d1)) + (net N_96_1 (joined + (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_a3_1)) + (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a3)) )) (net (rename state_machine_un42_clk_030_1 "state_machine.un42_clk_030_1") (joined (portRef O (instanceRef state_machine_un42_clk_030_1)) @@ -2359,26 +2391,10 @@ (portRef O (instanceRef state_machine_un42_clk_030_5)) (portRef I1 (instanceRef state_machine_un42_clk_030)) )) - (net N_96_1 (joined - (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_a3_1)) - (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a3)) - )) (net AMIGA_BUS_ENABLE_i_m_1 (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_i_m_1)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_i_m)) )) - (net N_131_1 (joined - (portRef O (instanceRef clk_cpu_est_11_0_a4_1_1_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_3)) - )) - (net (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (joined - (portRef O (instanceRef clk_cpu_est_11_0_1_3)) - (portRef I0 (instanceRef clk_cpu_est_11_0_3)) - )) - (net N_105_1 (joined - (portRef O (instanceRef SM_AMIGA_ns_a3_0_1_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_a3_0_5)) - )) (net VPA_SYNC_1_sqmuxa_1_0 (joined (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_0)) (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_5)) @@ -2403,6 +2419,26 @@ (portRef O (instanceRef VPA_SYNC_1_sqmuxa_6)) (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa)) )) + (net N_127_1 (joined + (portRef O (instanceRef clk_cpu_est_11_i_a4_1_2)) + (portRef I0 (instanceRef clk_cpu_est_11_i_a4_2)) + )) + (net N_128_1 (joined + (portRef O (instanceRef clk_cpu_est_11_i_a4_0_1_2)) + (portRef I0 (instanceRef clk_cpu_est_11_i_a4_0_2)) + )) + (net N_131_1 (joined + (portRef O (instanceRef clk_cpu_est_11_0_a4_1_1_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_3)) + )) + (net (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (joined + (portRef O (instanceRef clk_cpu_est_11_0_1_3)) + (portRef I0 (instanceRef clk_cpu_est_11_0_3)) + )) + (net N_105_1 (joined + (portRef O (instanceRef SM_AMIGA_ns_a3_0_1_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_a3_0_5)) + )) (net DTACK_SYNC_1_sqmuxa_1_0 (joined (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_0)) (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa)) @@ -2435,62 +2471,6 @@ (portRef O (instanceRef state_machine_un13_clk_000_d0_2_0)) (portRef I1 (instanceRef state_machine_un13_clk_000_d0)) )) - (net N_127_1 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_1_2)) - (portRef I0 (instanceRef clk_cpu_est_11_i_a4_2)) - )) - (net N_128_1 (joined - (portRef O (instanceRef clk_cpu_est_11_i_a4_0_1_2)) - (portRef I0 (instanceRef clk_cpu_est_11_i_a4_0_2)) - )) - (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined - (portRef O (instanceRef IPL_030_0_2__r)) - (portRef I1 (instanceRef IPL_030_0_2__n)) - )) - (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined - (portRef O (instanceRef IPL_030_0_2__m)) - (portRef I0 (instanceRef IPL_030_0_2__p)) - )) - (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined - (portRef O (instanceRef IPL_030_0_2__n)) - (portRef I1 (instanceRef IPL_030_0_2__p)) - )) - (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined - (portRef O (instanceRef IPL_030_0_1__r)) - (portRef I1 (instanceRef IPL_030_0_1__n)) - )) - (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined - (portRef O (instanceRef IPL_030_0_1__m)) - (portRef I0 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined - (portRef O (instanceRef IPL_030_0_1__n)) - (portRef I1 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined - (portRef O (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef IPL_030_0_0__n)) - )) - (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined - (portRef O (instanceRef IPL_030_0_0__m)) - (portRef I0 (instanceRef IPL_030_0_0__p)) - )) - (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined - (portRef O (instanceRef IPL_030_0_0__n)) - (portRef I1 (instanceRef IPL_030_0_0__p)) - )) - (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined - (portRef O (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef cpu_est_0_2__n)) - )) - (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined - (portRef O (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__p)) - )) - (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined - (portRef O (instanceRef cpu_est_0_2__n)) - (portRef I1 (instanceRef cpu_est_0_2__p)) - )) (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined (portRef O (instanceRef cpu_est_0_1__r)) (portRef I1 (instanceRef cpu_est_0_1__n)) @@ -2503,30 +2483,6 @@ (portRef O (instanceRef cpu_est_0_1__n)) (portRef I1 (instanceRef cpu_est_0_1__p)) )) - (net (rename VPA_SYNC_0_un3 "VPA_SYNC_0.un3") (joined - (portRef O (instanceRef VPA_SYNC_0_r)) - (portRef I1 (instanceRef VPA_SYNC_0_n)) - )) - (net (rename VPA_SYNC_0_un1 "VPA_SYNC_0.un1") (joined - (portRef O (instanceRef VPA_SYNC_0_m)) - (portRef I0 (instanceRef VPA_SYNC_0_p)) - )) - (net (rename VPA_SYNC_0_un0 "VPA_SYNC_0.un0") (joined - (portRef O (instanceRef VPA_SYNC_0_n)) - (portRef I1 (instanceRef VPA_SYNC_0_p)) - )) - (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined - (portRef O (instanceRef VMA_INT_0_r)) - (portRef I1 (instanceRef VMA_INT_0_n)) - )) - (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined - (portRef O (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_p)) - )) - (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined - (portRef O (instanceRef VMA_INT_0_n)) - (portRef I1 (instanceRef VMA_INT_0_p)) - )) (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined (portRef O (instanceRef cpu_est_0_3__r)) (portRef I1 (instanceRef cpu_est_0_3__n)) @@ -2539,6 +2495,78 @@ (portRef O (instanceRef cpu_est_0_3__n)) (portRef I1 (instanceRef cpu_est_0_3__p)) )) + (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined + (portRef O (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef IPL_030_0_0__n)) + )) + (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined + (portRef O (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__p)) + )) + (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined + (portRef O (instanceRef IPL_030_0_0__n)) + (portRef I1 (instanceRef IPL_030_0_0__p)) + )) + (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined + (portRef O (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_1__n)) + )) + (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined + (portRef O (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__p)) + )) + (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined + (portRef O (instanceRef IPL_030_0_1__n)) + (portRef I1 (instanceRef IPL_030_0_1__p)) + )) + (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined + (portRef O (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_2__n)) + )) + (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined + (portRef O (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__p)) + )) + (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined + (portRef O (instanceRef IPL_030_0_2__n)) + (portRef I1 (instanceRef IPL_030_0_2__p)) + )) + (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined + (portRef O (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef UDS_000_INT_0_n)) + )) + (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined + (portRef O (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined + (portRef O (instanceRef UDS_000_INT_0_n)) + (portRef I1 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename VPA_SYNC_0_un3 "VPA_SYNC_0.un3") (joined + (portRef O (instanceRef VPA_SYNC_0_r)) + (portRef I1 (instanceRef VPA_SYNC_0_n)) + )) + (net (rename VPA_SYNC_0_un1 "VPA_SYNC_0.un1") (joined + (portRef O (instanceRef VPA_SYNC_0_m)) + (portRef I0 (instanceRef VPA_SYNC_0_p)) + )) + (net (rename VPA_SYNC_0_un0 "VPA_SYNC_0.un0") (joined + (portRef O (instanceRef VPA_SYNC_0_n)) + (portRef I1 (instanceRef VPA_SYNC_0_p)) + )) + (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined + (portRef O (instanceRef AS_000_INT_0_r)) + (portRef I1 (instanceRef AS_000_INT_0_n)) + )) + (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined + (portRef O (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_p)) + )) + (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined + (portRef O (instanceRef AS_000_INT_0_n)) + (portRef I1 (instanceRef AS_000_INT_0_p)) + )) (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined (portRef O (instanceRef BGACK_030_INT_0_r)) (portRef I1 (instanceRef BGACK_030_INT_0_n)) @@ -2551,6 +2579,42 @@ (portRef O (instanceRef BGACK_030_INT_0_n)) (portRef I1 (instanceRef BGACK_030_INT_0_p)) )) + (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined + (portRef O (instanceRef VMA_INT_0_r)) + (portRef I1 (instanceRef VMA_INT_0_n)) + )) + (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined + (portRef O (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_p)) + )) + (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined + (portRef O (instanceRef VMA_INT_0_n)) + (portRef I1 (instanceRef VMA_INT_0_p)) + )) + (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined + (portRef O (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_2__n)) + )) + (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined + (portRef O (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__p)) + )) + (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined + (portRef O (instanceRef cpu_est_0_2__n)) + (portRef I1 (instanceRef cpu_est_0_2__p)) + )) + (net (rename DSACK_INT_0_1__un3 "DSACK_INT_0_1_.un3") (joined + (portRef O (instanceRef DSACK_INT_0_1__r)) + (portRef I1 (instanceRef DSACK_INT_0_1__n)) + )) + (net (rename DSACK_INT_0_1__un1 "DSACK_INT_0_1_.un1") (joined + (portRef O (instanceRef DSACK_INT_0_1__m)) + (portRef I0 (instanceRef DSACK_INT_0_1__p)) + )) + (net (rename DSACK_INT_0_1__un0 "DSACK_INT_0_1_.un0") (joined + (portRef O (instanceRef DSACK_INT_0_1__n)) + (portRef I1 (instanceRef DSACK_INT_0_1__p)) + )) (net (rename BG_000_0_un3 "BG_000_0.un3") (joined (portRef O (instanceRef BG_000_0_r)) (portRef I1 (instanceRef BG_000_0_n)) @@ -2599,30 +2663,6 @@ (portRef O (instanceRef FPU_CS_INT_0_n)) (portRef I1 (instanceRef FPU_CS_INT_0_p)) )) - (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined - (portRef O (instanceRef AS_000_INT_0_r)) - (portRef I1 (instanceRef AS_000_INT_0_n)) - )) - (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined - (portRef O (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_p)) - )) - (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined - (portRef O (instanceRef AS_000_INT_0_n)) - (portRef I1 (instanceRef AS_000_INT_0_p)) - )) - (net (rename DSACK_INT_0_1__un3 "DSACK_INT_0_1_.un3") (joined - (portRef O (instanceRef DSACK_INT_0_1__r)) - (portRef I1 (instanceRef DSACK_INT_0_1__n)) - )) - (net (rename DSACK_INT_0_1__un1 "DSACK_INT_0_1_.un1") (joined - (portRef O (instanceRef DSACK_INT_0_1__m)) - (portRef I0 (instanceRef DSACK_INT_0_1__p)) - )) - (net (rename DSACK_INT_0_1__un0 "DSACK_INT_0_1_.un0") (joined - (portRef O (instanceRef DSACK_INT_0_1__n)) - (portRef I1 (instanceRef DSACK_INT_0_1__p)) - )) (net (rename DTACK_SYNC_0_un3 "DTACK_SYNC_0.un3") (joined (portRef O (instanceRef DTACK_SYNC_0_r)) (portRef I1 (instanceRef DTACK_SYNC_0_n)) @@ -2635,18 +2675,6 @@ (portRef O (instanceRef DTACK_SYNC_0_n)) (portRef I1 (instanceRef DTACK_SYNC_0_p)) )) - (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined - (portRef O (instanceRef UDS_000_INT_0_r)) - (portRef I1 (instanceRef UDS_000_INT_0_n)) - )) - (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined - (portRef O (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined - (portRef O (instanceRef UDS_000_INT_0_n)) - (portRef I1 (instanceRef UDS_000_INT_0_p)) - )) (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined (portRef O (instanceRef LDS_000_INT_0_r)) (portRef I1 (instanceRef LDS_000_INT_0_n)) diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index 0d4b762..6306612 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj -#-- Written on Sun May 18 21:01:40 2014 +#-- Written on Thu May 22 14:56:03 2014 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index 247c835..6ad2b62 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -45,8 +45,9 @@ VNAME 'mach.INV.prim'; # view id 9 VNAME 'mach.OR2.prim'; # view id 10 VNAME 'mach.XOR2.prim'; # view id 11 VNAME 'mach.MACH_LATCH.prim'; # view id 12 -VNAME 'mach.DLATRH.prim'; # view id 13 -VNAME 'work.BUS68030.behavioral'; # view id 14 +VNAME 'mach.DLATSH.prim'; # view id 13 +VNAME 'mach.DLATRH.prim'; # view id 14 +VNAME 'work.BUS68030.behavioral'; # view id 15 @ERMRlENORBvq]w_7wsRbH l;N3ORCV8HMCF8V;R4 RNP3#8H#PFDCRlC4N; @@ -214,12 +215,12 @@ fbRjR:jHRMPkRM4kRM4)b; R:fjjsR0k0CRsRkCe;BB fbRjR:jV#NDCNRVDR#Ct;h7 fbRjR:jDsN0#RRTTRR7pRqakRM4k;Mj -RMRlENORq7paR)]blsH;P +RMRlENORq7paR1]blsH;P NR#3HblsHR 4;FRRTk;Mj 7HR;R Hp;qa -)HR;M +1HR;M oRjkM;M NRN3#PMC_CV0_D#No46R.no; MMRk4N; @@ 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+c9S=Qjqr_O.;c9 +fsRjR:jlENOReQhRHbsl_RqH6r.9m +S=Hq_r9.6 +jSQ=Oq_r9.6;R +sfjj:ROlNEhRQesRbHqlR_.HrnS9 +m_=qHnr.9Q +Sj_=qOnr.9s; R:fjjNRlOQERhbeRsRHlqr_H. -U9Sqm=_.HrUS9 -Qqj=_.OrU -9;sjRf:ljRNROEQRheblsHRHq_r9.g +(9Sqm=_.Hr(S9 +Qqj=_.Or( +9;sjRf:ljRNROEQRheblsHRHq_r9.U =Smqr_H. -g9S=Qjqr_O.;g9 -fsRjR:jlENOReQhRHbsl_RqHjrd9m -S=Hq_r9dj -jSQ=Oq_r9dj;R -sfjj:ROlNEhRQesRbHqlR_dHr4S9 -m_=qH4rd9Q -Sj_=qO4rd9s; -R:fjjNRlOqERhR7.blsHR4kM__N#j_djcm -S=4kM__N#j_djcQ -Sj1=q_jjd_SH -Qh4=_(4c;R -sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCz\37j1_jQj_h(a_ -=Sm#00NCN_lOMEHCz\37j1_jQj_h(a__Sj -Qqj=_HO_r -j9S=Q4hc_4(;_H -fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\73p1j_jjh_Qa -_(S#m=0CN0_OlNECHM\73p1j_jjh_Qa__(jQ -Sj_=h4_c(HQ -S40=#N_0ClENOH\MC3ckMcD_O j_jj4_8;R -sfjj:ROlNEhRQesRbH#lR0CN0_OlNECHM\M3k4Nc_#j_jjM_H0 -_HS#m=0CN0_OlNECHM\M3k4Nc_#j_jjM_H0 -_HS=Qj#00NCN_lOMEHCk\3M_4cNj#_jHj_M -0;sjRf:ljRNROEQRheblsHRa)1_SH -m1=)a -_HS=Qj)_1aOs; -R:fjjNRlO7ERp)qa]sRbHBlRp)i_ 4wr9T -S=iBp_w) r -49St7=hS7 -p=qat -h7S))=1Ha_;R -sfjj:ROlNEhRQesRbHAlRtiqB_jjd_aQh_SH -mt=Aq_Bij_djQ_haHQ -Sjt=Aq_Bij_djQ;ha -fsRjR:jlENOReQhRHbsluRwz1_B_aQh_SH -mu=wz1_B_aQh_SH -Qwj=uBz_1h_Qas; -R:fjjNRlOQERhbeRsRHlz_71j_jjQ_haj -3sSzm=7j1_jQj_hja_3dkM -jSQ=4kM__N#j_djcs; -R:fjjNRlOqERhR7.blsHR1z7_jjj_aQh_lj3 -=Smz_71j_jjQ_hajM3k4Q -Sj7=z1j_jjh_QaQ -S4M=k4#_N_jjd_ -c;sjRf:ljRNROEq.h7RHbsl7Rz1j_jjh_Qa3_jMm -S=1z7_jjj_aQh_kj3MSj -Q#j=0CN0_OlNECHM\73z1j_jjh_Qa -_(S=Q4z_71j_jjQ_hajM3kds; -R:fjjNRlOmER)b.RsRHlz_71j_jjQ_haj -3bShm=_S4 -Qzj=7j1_jQj_hja_34kM -4SQ=1z7_jjj_aQh_kj3M -j;sjRf:ljRNROEQRheblsHR1p7_jjj_aQh_sj3 -=Smp_71j_jjQ_hajM3kdQ -SjM=k4#_N_jjd_ -c;sjRf:ljRNROEq.h7RHbsl7Rp1j_jjh_Qa3_jlm -S=1p7_jjj_aQh_kj3MS4 -Qpj=7j1_jQj_hSa -Qk4=MN4_#d_jj;_c -fsRjR:jlENOR7qh.sRbHplR7j1_jQj_hja_3SM -m7=p1j_jjh_Qa3_jk -MjS=Qj#00NCN_lOMEHCp\37j1_jQj_h(a_ -4SQ=1p7_jjj_aQh_kj3M -d;sjRf:ljRNROEmR).blsHR1p7_jjj_aQh_bj3 -=Smh -_.S=Qjp_71j_jjQ_hajM3k4Q -S47=p1j_jjh_Qa3_jk;Mj +U9S=Qjqr_O.;U9 +fsRjR:jlENOReQhRHbsl_RqHgr.9m +S=Hq_r9.g +jSQ=Oq_r9.g;R +sfjj:ROlNEhRQesRbHqlR_dHrjS9 +m_=qHjrd9Q +Sj_=qOjrd9s; +R:fjjNRlOQERhbeRsRHlqr_Hd +49Sqm=_dHr4S9 +Qqj=_dOr4 +9;sjRf:ljRNROEQRheblsHRiBp_jjj__7.Hm +S=iBp_jjj__7.HQ +Sjp=Bij_jj._7;R +sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3M_djO_D j_jj8S4 +m0=#N_0ClENOH\MC3dkMjD_O j_jj4_8 +jSQ=iBp_jjj_ +74S=Q4B_pij_jj7H._;R +sfjj:ROlNEhRQesRbHBlRpBi_hHa_r +j9SBm=pBi_hHa_r +j9S=QjB_piBrhaj +9;sjRf:ljRNROEQRheblsHRN#00lC_NHOEM3C\kcM4__N#j_jjH_M0Hm +S=N#00lC_NHOEM3C\kcM4__N#j_jjH_M0HQ +Sj0=#N_0ClENOH\MC34kMc#_N_jjj_0HM;R +sfjj:ROlNEhRQesRbH)lR1Ha_ +=Sm)_1aHQ +Sj1=)a;_O +fsRjR:jlENORq7paR1]blsHRiBp_w) r +j9SBT=p)i_ jwr97 +S=7th +qSpah=t71 +S=a)1_ +H;sjRf:ljRNROE7apq)b]RsRHlB_pi)r w4S9 +Tp=Bi _)w9r4 +=S7t +h7Sapq=7th +=S))_1aHs; +R:fjjNRlOQERhbeRsRHlABtqid_jjh_Qa +_HSAm=tiqB_jjd_aQh_SH +QAj=tiqB_jjd_aQh;R +sfjj:ROlNEhRQesRbHwlRuBz_1h_Qa +_HSwm=uBz_1h_Qa +_HS=Qjw_uzBQ1_h +a; diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index d4247bf..1fc62ae 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Sun May 18 21:01:41 2014 +#Thu May 22 14:56:04 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode @@ -25,7 +25,6 @@ Post processing for work.bus68030.behavioral @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":116:32:116:34|Pruning register CLK_000_D4 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":115:32:115:34|Pruning register CLK_000_D3 @A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Feedback mux created for signal AMIGA_BUS_ENABLE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. -@W: CL111 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|All reachable assignments to CLK_REF(0) assign '0'; register removed by optimization @W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|Latch generated from process for signal CLK_REF(1 downto 0); possible missing assignment in an if or case statement. @W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Optimizing register bit DSACK_INT(0) to a constant 1 @W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Pruning register bit 0 of DSACK_INT(1 downto 0) @@ -44,7 +43,7 @@ State machine has 8 reachable states with original encodings of: @W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|Initial value is not supported on state machine SM_AMIGA @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sun May 18 21:01:41 2014 +# Thu May 22 14:56:04 2014 ###########################################################] Map & Optimize Report @@ -76,9 +75,10 @@ BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses AND2 159 uses -INV 126 uses +INV 127 uses OR2 18 uses -XOR2 4 uses +XOR2 5 uses +DLATSH 1 use DLATRH 1 use @@ -89,6 +89,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sun May 18 21:01:42 2014 +# Thu May 22 14:56:05 2014 ###########################################################] diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs index 3ff0f39..7cc84e0 100644 Binary files a/Logic/BUS68030.srs and b/Logic/BUS68030.srs differ diff --git a/Logic/bus68030.exf b/Logic/bus68030.exf index 6757e21..7b8fdd2 100644 --- a/Logic/bus68030.exf +++ b/Logic/bus68030.exf @@ -55,7 +55,7 @@ Section Member Rename Array-Notation Array Number Port FC_0_ FC[0] 4 1 End Section Cross Reference File -Design 'BUS68030' created Sun May 18 21:01:47 2014 +Design 'BUS68030' created Thu May 22 14:56:10 2014 Type New Name Original Name // ---------------------------------------------------------------------- Inst i_z2H2H AS_000 @@ -65,200 +65,212 @@ Design 'BUS68030' created Sun May 18 21:01:47 2014 Inst i_z3S3S DTACK Inst i_z3U3U AVEC_EXP Inst i_z4A4A CIIN - Inst SM_AMIGA_ns_i_o3_i_4_ SM_AMIGA_ns_i_o3_i[4] - Inst SM_AMIGA_ns_i_a3_3_ SM_AMIGA_ns_i_a3[3] - Inst state_machine_un14_as_000_int state_machine.un14_as_000_int - Inst IPL_030_0_2__r IPL_030_0_2_.r - Inst IPL_030_0_2__m IPL_030_0_2_.m - Inst IPL_030_0_2__n IPL_030_0_2_.n - Inst IPL_030_0_2__p IPL_030_0_2_.p - Inst IPL_030_0_1__r IPL_030_0_1_.r - Inst IPL_030_0_1__m IPL_030_0_1_.m - Inst IPL_030_0_1__n IPL_030_0_1_.n - Inst IPL_030_0_1__p IPL_030_0_1_.p - Inst IPL_030_0_0__r IPL_030_0_0_.r - Inst IPL_030_0_0__m IPL_030_0_0_.m - Inst IPL_030_0_0__n IPL_030_0_0_.n - Inst IPL_030_0_0__p IPL_030_0_0_.p - Inst cpu_est_0_2__r cpu_est_0_2_.r - Inst cpu_est_0_2__m cpu_est_0_2_.m - Inst cpu_est_0_2__n cpu_est_0_2_.n - Inst cpu_est_0_2__p cpu_est_0_2_.p - Inst cpu_est_0_1__r cpu_est_0_1_.r - Inst cpu_est_0_1__m cpu_est_0_1_.m - Inst cpu_est_0_1__n cpu_est_0_1_.n - Inst cpu_est_0_1__p cpu_est_0_1_.p - Inst cpu_est_i_2_ cpu_est_i[2] - Inst clk_cpu_est_11_i_2_ clk.cpu_est_11_i[2] - Inst clk_cpu_est_11_0_a4_1_1_ clk.cpu_est_11_0_a4_1[1] - Inst cpu_est_i_0_ cpu_est_i[0] - Inst clk_cpu_est_11_0_a4_1_ clk.cpu_est_11_0_a4[1] - Inst SM_AMIGA_ns_i_o3_4_ SM_AMIGA_ns_i_o3[4] - Inst SM_AMIGA_ns_i_o3_0_ SM_AMIGA_ns_i_o3[0] - Inst SM_AMIGA_ns_i_4_ SM_AMIGA_ns_i[4] Inst SM_AMIGA_ns_i_3_ SM_AMIGA_ns_i[3] Inst SM_AMIGA_i_3_ SM_AMIGA_i[3] Inst SM_AMIGA_ns_i_a3_0_4_ SM_AMIGA_ns_i_a3_0[4] Inst SM_AMIGA_ns_i_a3_4_ SM_AMIGA_ns_i_a3[4] Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] Inst SM_AMIGA_i_5_ SM_AMIGA_i[5] - Inst clk_cpu_est_11_0_a4_0_1_ clk.cpu_est_11_0_a4_0[1] - Inst SM_AMIGA_5_ SM_AMIGA[5] - Inst clk_cpu_est_11_0_a4_2_1_ clk.cpu_est_11_0_a4_2[1] - Inst SM_AMIGA_4_ SM_AMIGA[4] - Inst clk_cpu_est_11_0_a4_3_ clk.cpu_est_11_0_a4[3] - Inst SM_AMIGA_3_ SM_AMIGA[3] - Inst clk_cpu_est_11_0_a4_0_3_ clk.cpu_est_11_0_a4_0[3] - Inst SM_AMIGA_2_ SM_AMIGA[2] - Inst clk_cpu_est_11_0_o4_1_ clk.cpu_est_11_0_o4[1] - Inst SM_AMIGA_1_ SM_AMIGA[1] - Inst clk_cpu_est_11_0_o4_3_ clk.cpu_est_11_0_o4[3] - Inst SM_AMIGA_0_ SM_AMIGA[0] - Inst cpu_est_2_ cpu_est[2] - Inst cpu_est_3_ cpu_est[3] + Inst SM_AMIGA_ns_i_a3_3_ SM_AMIGA_ns_i_a3[3] + Inst state_machine_un14_as_000_int state_machine.un14_as_000_int + Inst cpu_est_0_1__r cpu_est_0_1_.r + Inst cpu_est_0_1__m cpu_est_0_1_.m + Inst cpu_est_0_1__n cpu_est_0_1_.n + Inst cpu_est_0_1__p cpu_est_0_1_.p Inst cpu_est_i_1_ cpu_est_i[1] - Inst IPL_030DFFSH_0_ IPL_030DFFSH[0] - Inst IPL_030DFFSH_1_ IPL_030DFFSH[1] Inst state_machine_un13_clk_000_d0_1 state_machine.un13_clk_000_d0_1 - Inst IPL_030DFFSH_2_ IPL_030DFFSH[2] Inst state_machine_un13_clk_000_d0_2 state_machine.un13_clk_000_d0_2 - Inst SM_AMIGA_7_ SM_AMIGA[7] Inst cpu_est_0_0_ cpu_est_0[0] - Inst SM_AMIGA_6_ SM_AMIGA[6] + Inst clk_cpu_est_11_0_a4_2_1_ clk.cpu_est_11_0_a4_2[1] + Inst clk_cpu_est_11_0_a4_1_1_ clk.cpu_est_11_0_a4_1[1] Inst cpu_est_i_3_ cpu_est_i[3] - Inst state_machine_un13_clk_000_d0_2_i state_machine.un13_clk_000_d0_2_i - Inst VPA_SYNC_0_r VPA_SYNC_0.r - Inst CLK_CNT_0_ CLK_CNT[0] - Inst VPA_SYNC_0_m VPA_SYNC_0.m - Inst CLK_CNT_1_ CLK_CNT[1] - Inst VPA_SYNC_0_n VPA_SYNC_0.n - Inst cpu_est_0_ cpu_est[0] - Inst VPA_SYNC_0_p VPA_SYNC_0.p - Inst cpu_est_1_ cpu_est[1] - Inst VMA_INT_0_r VMA_INT_0.r - Inst VMA_INT_0_m VMA_INT_0.m - Inst VMA_INT_0_n VMA_INT_0.n - Inst VMA_INT_0_p VMA_INT_0.p + Inst cpu_est_i_2_ cpu_est_i[2] + Inst clk_cpu_est_11_0_a4_0_1_ clk.cpu_est_11_0_a4_0[1] + Inst cpu_est_i_0_ cpu_est_i[0] + Inst clk_cpu_est_11_0_a4_1_ clk.cpu_est_11_0_a4[1] + Inst SM_AMIGA_ns_i_o3_4_ SM_AMIGA_ns_i_o3[4] + Inst SM_AMIGA_ns_i_4_ SM_AMIGA_ns_i[4] Inst cpu_est_0_3__r cpu_est_0_3_.r Inst cpu_est_0_3__m cpu_est_0_3_.m Inst cpu_est_0_3__n cpu_est_0_3_.n - Inst DSACK_INT_1_ DSACK_INT[1] Inst cpu_est_0_3__p cpu_est_0_3_.p + Inst IPL_030_0_0__r IPL_030_0_0_.r + Inst IPL_030_0_0__m IPL_030_0_0_.m + Inst IPL_030_0_0__n IPL_030_0_0_.n + Inst IPL_030_0_0__p IPL_030_0_0_.p + Inst IPL_030_0_1__r IPL_030_0_1_.r + Inst IPL_030_0_1__m IPL_030_0_1_.m + Inst SM_AMIGA_6_ SM_AMIGA[6] + Inst IPL_030_0_1__n IPL_030_0_1_.n + Inst SM_AMIGA_5_ SM_AMIGA[5] + Inst IPL_030_0_1__p IPL_030_0_1_.p + Inst SM_AMIGA_4_ SM_AMIGA[4] + Inst IPL_030_0_2__r IPL_030_0_2_.r + Inst SM_AMIGA_3_ SM_AMIGA[3] + Inst IPL_030_0_2__m IPL_030_0_2_.m + Inst SM_AMIGA_2_ SM_AMIGA[2] + Inst IPL_030_0_2__n IPL_030_0_2_.n + Inst SM_AMIGA_1_ SM_AMIGA[1] + Inst IPL_030_0_2__p IPL_030_0_2_.p + Inst SM_AMIGA_0_ SM_AMIGA[0] Inst state_machine_un2_clk_000 state_machine.un2_clk_000 + Inst cpu_est_1_ cpu_est[1] + Inst cpu_est_2_ cpu_est[2] Inst clk_un4_clk_000_d1 clk.un4_clk_000_d1 + Inst cpu_est_3_ cpu_est[3] Inst state_machine_un15_clk_000_d0 state_machine.un15_clk_000_d0 - Inst state_machine_un13_clk_000_d0_1_i state_machine.un13_clk_000_d0_1_i - Inst SM_AMIGA_ns_a3_7_ SM_AMIGA_ns_a3[7] - Inst SM_AMIGA_ns_7_ SM_AMIGA_ns[7] + Inst IPL_030DFFSH_0_ IPL_030DFFSH[0] + Inst clk_cpu_est_11_0_a4_3_ clk.cpu_est_11_0_a4[3] + Inst IPL_030DFFSH_1_ IPL_030DFFSH[1] + Inst clk_cpu_est_11_0_a4_0_3_ clk.cpu_est_11_0_a4_0[3] + Inst IPL_030DFFSH_2_ IPL_030DFFSH[2] + Inst clk_cpu_est_11_i_2_ clk.cpu_est_11_i[2] + Inst SM_AMIGA_7_ SM_AMIGA[7] + Inst clk_cpu_est_11_0_o4_1_ clk.cpu_est_11_0_o4[1] + Inst clk_cpu_est_11_0_o4_3_ clk.cpu_est_11_0_o4[3] + Inst state_machine_un13_clk_000_d0_2_i state_machine.un13_clk_000_d0_2_i + Inst CLK_CNT_0_ CLK_CNT[0] + Inst UDS_000_INT_0_r UDS_000_INT_0.r + Inst CLK_CNT_1_ CLK_CNT[1] + Inst UDS_000_INT_0_m UDS_000_INT_0.m + Inst cpu_est_0_ cpu_est[0] + Inst UDS_000_INT_0_n UDS_000_INT_0.n + Inst UDS_000_INT_0_p UDS_000_INT_0.p + Inst state_machine_un23_clk_000_d0 state_machine.un23_clk_000_d0 + Inst VPA_SYNC_0_r VPA_SYNC_0.r + Inst VPA_SYNC_0_m VPA_SYNC_0.m + Inst VPA_SYNC_0_n VPA_SYNC_0.n + Inst VPA_SYNC_0_p VPA_SYNC_0.p + Inst DSACK_INT_1_ DSACK_INT[1] + Inst AS_000_INT_0_r AS_000_INT_0.r + Inst AS_000_INT_0_m AS_000_INT_0.m + Inst AS_000_INT_0_n AS_000_INT_0.n + Inst AS_000_INT_0_p AS_000_INT_0.p Inst BGACK_030_INT_0_r BGACK_030_INT_0.r Inst BGACK_030_INT_0_m BGACK_030_INT_0.m Inst BGACK_030_INT_0_n BGACK_030_INT_0.n Inst BGACK_030_INT_0_p BGACK_030_INT_0.p - Inst SIZE_0_ SIZE[0] - Inst BG_000_0_r BG_000_0.r - Inst SIZE_1_ SIZE[1] - Inst BG_000_0_m BG_000_0.m - Inst A_0_ A[0] - Inst BG_000_0_n BG_000_0.n - Inst A_16_ A[16] - Inst BG_000_0_p BG_000_0.p - Inst A_17_ A[17] - Inst AMIGA_BUS_ENABLE_0_r AMIGA_BUS_ENABLE_0.r - Inst A_18_ A[18] - Inst AMIGA_BUS_ENABLE_0_m AMIGA_BUS_ENABLE_0.m - Inst A_19_ A[19] - Inst AMIGA_BUS_ENABLE_0_n AMIGA_BUS_ENABLE_0.n - Inst A_20_ A[20] - Inst AMIGA_BUS_ENABLE_0_p AMIGA_BUS_ENABLE_0.p - Inst A_21_ A[21] - Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r - Inst A_22_ A[22] - Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m - Inst A_23_ A[23] - Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n - Inst A_24_ A[24] - Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p - Inst A_25_ A[25] - Inst FPU_CS_INT_0_r FPU_CS_INT_0.r - Inst A_26_ A[26] - Inst FPU_CS_INT_0_m FPU_CS_INT_0.m - Inst A_27_ A[27] - Inst FPU_CS_INT_0_n FPU_CS_INT_0.n - Inst A_28_ A[28] - Inst FPU_CS_INT_0_p FPU_CS_INT_0.p - Inst A_29_ A[29] - Inst AS_000_INT_0_r AS_000_INT_0.r - Inst A_30_ A[30] - Inst AS_000_INT_0_m AS_000_INT_0.m - Inst A_31_ A[31] - Inst AS_000_INT_0_n AS_000_INT_0.n - Inst AS_000_INT_0_p AS_000_INT_0.p - Inst DSACK_INT_0_1__r DSACK_INT_0_1_.r - Inst DSACK_INT_0_1__m DSACK_INT_0_1_.m - Inst DSACK_INT_0_1__n DSACK_INT_0_1_.n - Inst DSACK_INT_0_1__p DSACK_INT_0_1_.p + Inst state_machine_un6_bgack_000 state_machine.un6_bgack_000 Inst SM_AMIGA_ns_a3_2_ SM_AMIGA_ns_a3[2] Inst SM_AMIGA_ns_2_ SM_AMIGA_ns[2] - Inst state_machine_un23_clk_000_d0 state_machine.un23_clk_000_d0 + Inst SIZE_0_ SIZE[0] + Inst VMA_INT_0_r VMA_INT_0.r + Inst SIZE_1_ SIZE[1] + Inst VMA_INT_0_m VMA_INT_0.m + Inst A_0_ A[0] + Inst VMA_INT_0_n VMA_INT_0.n + Inst A_16_ A[16] + Inst VMA_INT_0_p VMA_INT_0.p + Inst A_17_ A[17] + Inst cpu_est_0_2__r cpu_est_0_2_.r + Inst A_18_ A[18] + Inst cpu_est_0_2__m cpu_est_0_2_.m + Inst A_19_ A[19] + Inst cpu_est_0_2__n cpu_est_0_2_.n + Inst A_20_ A[20] + Inst cpu_est_0_2__p cpu_est_0_2_.p + Inst A_21_ A[21] + Inst state_machine_un17_clk_030 state_machine.un17_clk_030 + Inst A_22_ A[22] + Inst A_23_ A[23] + Inst state_machine_un1_clk_030 state_machine.un1_clk_030 + Inst A_24_ A[24] + Inst A_i_19_ A_i[19] + Inst A_25_ A[25] + Inst A_i_18_ A_i[18] + Inst A_26_ A[26] + Inst A_i_16_ A_i[16] + Inst A_27_ A[27] + Inst A_28_ A[28] + Inst DSACK_INT_0_1__r DSACK_INT_0_1_.r + Inst A_29_ A[29] + Inst DSACK_INT_0_1__m DSACK_INT_0_1_.m + Inst A_30_ A[30] + Inst DSACK_INT_0_1__n DSACK_INT_0_1_.n + Inst A_31_ A[31] + Inst DSACK_INT_0_1__p DSACK_INT_0_1_.p + Inst BG_000_0_r BG_000_0.r + Inst BG_000_0_m BG_000_0.m + Inst BG_000_0_n BG_000_0.n + Inst BG_000_0_p BG_000_0.p + Inst AMIGA_BUS_ENABLE_0_r AMIGA_BUS_ENABLE_0.r + Inst AMIGA_BUS_ENABLE_0_m AMIGA_BUS_ENABLE_0.m + Inst AMIGA_BUS_ENABLE_0_n AMIGA_BUS_ENABLE_0.n + Inst AMIGA_BUS_ENABLE_0_p AMIGA_BUS_ENABLE_0.p + Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r + Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m + Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n + Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p Inst IPL_030_0_ IPL_030[0] - Inst DTACK_SYNC_0_r DTACK_SYNC_0.r + Inst FPU_CS_INT_0_r FPU_CS_INT_0.r Inst IPL_030_1_ IPL_030[1] - Inst DTACK_SYNC_0_m DTACK_SYNC_0.m + Inst FPU_CS_INT_0_m FPU_CS_INT_0.m Inst IPL_030_2_ IPL_030[2] - Inst DTACK_SYNC_0_n DTACK_SYNC_0.n + Inst FPU_CS_INT_0_n FPU_CS_INT_0.n Inst IPL_0_ IPL[0] - Inst DTACK_SYNC_0_p DTACK_SYNC_0.p + Inst FPU_CS_INT_0_p FPU_CS_INT_0.p Inst IPL_1_ IPL[1] Inst IPL_2_ IPL[2] - Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] + Inst DTACK_SYNC_0_r DTACK_SYNC_0.r Inst DSACK_0_ DSACK[0] - Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] + Inst DTACK_SYNC_0_m DTACK_SYNC_0.m Inst DSACK_1_ DSACK[1] - Inst state_machine_un5_clk_030_i_a3 state_machine.un5_clk_030_i_a3 - Inst state_machine_un42_clk_030_i state_machine.un42_clk_030_i - Inst state_machine_un17_clk_030 state_machine.un17_clk_030 - Inst state_machine_un6_bgack_000 state_machine.un6_bgack_000 - Inst state_machine_un30_clk_000_d1 state_machine.un30_clk_000_d1 - Inst state_machine_un1_clk_030 state_machine.un1_clk_030 - Inst A_i_19_ A_i[19] - Inst FC_0_ FC[0] - Inst A_i_18_ A_i[18] - Inst FC_1_ FC[1] - Inst A_i_16_ A_i[16] - Inst SM_AMIGA_ns_i_o3_6_ SM_AMIGA_ns_i_o3[6] - Inst SM_AMIGA_ns_i_6_ SM_AMIGA_ns_i[6] - Inst state_machine_un8_clk_000_d0 state_machine.un8_clk_000_d0 - Inst SM_AMIGA_ns_5_ SM_AMIGA_ns[5] - Inst state_machine_un13_clk_000_d0_1_0 state_machine.un13_clk_000_d0_1_0 - Inst SM_AMIGA_i_2_ SM_AMIGA_i[2] - Inst state_machine_un13_clk_000_d0_2_0 state_machine.un13_clk_000_d0_2_0 - Inst SM_AMIGA_i_1_ SM_AMIGA_i[1] - Inst state_machine_un13_clk_000_d0 state_machine.un13_clk_000_d0 - Inst SM_AMIGA_ns_i_a3_0_6_ SM_AMIGA_ns_i_a3_0[6] - Inst clk_cpu_est_11_i_a4_1_2_ clk.cpu_est_11_i_a4_1[2] - Inst SM_AMIGA_ns_i_a3_6_ SM_AMIGA_ns_i_a3[6] - Inst clk_cpu_est_11_i_a4_2_ clk.cpu_est_11_i_a4[2] - Inst SM_AMIGA_ns_a3_5_ SM_AMIGA_ns_a3[5] - Inst clk_cpu_est_11_i_a4_0_1_2_ clk.cpu_est_11_i_a4_0_1[2] - Inst clk_cpu_est_11_i_a4_0_2_ clk.cpu_est_11_i_a4_0[2] - Inst SM_AMIGA_ns_a3_0_5_ SM_AMIGA_ns_a3_0[5] + Inst DTACK_SYNC_0_n DTACK_SYNC_0.n + Inst DTACK_SYNC_0_p DTACK_SYNC_0.p + Inst LDS_000_INT_0_r LDS_000_INT_0.r + Inst LDS_000_INT_0_m LDS_000_INT_0.m + Inst LDS_000_INT_0_n LDS_000_INT_0.n + Inst LDS_000_INT_0_p LDS_000_INT_0.p Inst state_machine_AMIGA_BUS_ENABLE_2_iv state_machine.AMIGA_BUS_ENABLE_2_iv - Inst SM_AMIGA_ns_o3_1_ SM_AMIGA_ns_o3[1] - Inst CLK_CNT_i_0_ CLK_CNT_i[0] - Inst clk_CLK_CNT_3_0_ clk.CLK_CNT_3[0] - Inst clk_clk_cnt_i clk.clk_cnt_i - Inst clk_CLK_CNT_3_1_ clk.CLK_CNT_3[1] - Inst SM_AMIGA_ns_i_a3_0_ SM_AMIGA_ns_i_a3[0] - Inst SM_AMIGA_ns_a3_1_ SM_AMIGA_ns_a3[1] - Inst SM_AMIGA_ns_a3_0_1_ SM_AMIGA_ns_a3_0[1] - Inst SM_AMIGA_ns_i_0_ SM_AMIGA_ns_i[0] + Inst FC_0_ FC[0] + Inst FC_1_ FC[1] + Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] + Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] + Inst state_machine_un5_clk_030_i_a3 state_machine.un5_clk_030_i_a3 + Inst state_machine_LDS_000_INT_7 state_machine.LDS_000_INT_7 + Inst state_machine_UDS_000_INT_7 state_machine.UDS_000_INT_7 + Inst state_machine_un42_clk_030_i state_machine.un42_clk_030_i Inst state_machine_un8_clk_000_d0_1 state_machine.un8_clk_000_d0_1 - Inst SM_AMIGA_ns_1_ SM_AMIGA_ns[1] Inst state_machine_un8_clk_000_d0_2 state_machine.un8_clk_000_d0_2 Inst state_machine_un8_clk_000_d0_3 state_machine.un8_clk_000_d0_3 Inst state_machine_un8_clk_000_d0_4 state_machine.un8_clk_000_d0_4 + Inst state_machine_un8_clk_000_d0 state_machine.un8_clk_000_d0 + Inst state_machine_un13_clk_000_d0_1_0 state_machine.un13_clk_000_d0_1_0 + Inst state_machine_un13_clk_000_d0_2_0 state_machine.un13_clk_000_d0_2_0 + Inst state_machine_un13_clk_000_d0 state_machine.un13_clk_000_d0 + Inst SM_AMIGA_ns_i_o3_6_ SM_AMIGA_ns_i_o3[6] + Inst SM_AMIGA_ns_i_6_ SM_AMIGA_ns_i[6] + Inst SM_AMIGA_ns_5_ SM_AMIGA_ns[5] + Inst SM_AMIGA_i_2_ SM_AMIGA_i[2] + Inst clk_cpu_est_11_i_a4_1_2_ clk.cpu_est_11_i_a4_1[2] + Inst SM_AMIGA_i_1_ SM_AMIGA_i[1] + Inst clk_cpu_est_11_i_a4_2_ clk.cpu_est_11_i_a4[2] + Inst SM_AMIGA_ns_i_a3_0_6_ SM_AMIGA_ns_i_a3_0[6] + Inst clk_cpu_est_11_i_a4_0_1_2_ clk.cpu_est_11_i_a4_0_1[2] + Inst SM_AMIGA_ns_i_a3_6_ SM_AMIGA_ns_i_a3[6] + Inst clk_cpu_est_11_i_a4_0_2_ clk.cpu_est_11_i_a4_0[2] + Inst SM_AMIGA_ns_a3_5_ SM_AMIGA_ns_a3[5] + Inst clk_cpu_est_11_0_a4_1_1_3_ clk.cpu_est_11_0_a4_1_1[3] + Inst clk_CLK_CNT_3_0_ clk.CLK_CNT_3[0] + Inst clk_cpu_est_11_0_a4_1_3_ clk.cpu_est_11_0_a4_1[3] + Inst clk_clk_cnt_i clk.clk_cnt_i + Inst clk_cpu_est_11_0_1_3_ clk.cpu_est_11_0_1[3] + Inst clk_CLK_CNT_3_1_ clk.CLK_CNT_3[1] + Inst clk_cpu_est_11_0_3_ clk.cpu_est_11_0[3] + Inst SM_AMIGA_ns_i_a3_0_ SM_AMIGA_ns_i_a3[0] + Inst SM_AMIGA_ns_a3_0_1_5_ SM_AMIGA_ns_a3_0_1[5] + Inst SM_AMIGA_ns_a3_1_ SM_AMIGA_ns_a3[1] + Inst SM_AMIGA_ns_a3_0_5_ SM_AMIGA_ns_a3_0[5] + Inst SM_AMIGA_ns_a3_0_1_ SM_AMIGA_ns_a3_0[1] + Inst state_machine_un13_clk_000_d0_1_i state_machine.un13_clk_000_d0_1_i + Inst SM_AMIGA_ns_a3_7_ SM_AMIGA_ns_a3[7] + Inst SM_AMIGA_ns_i_0_ SM_AMIGA_ns_i[0] + Inst SM_AMIGA_ns_1_ SM_AMIGA_ns[1] + Inst SM_AMIGA_ns_7_ SM_AMIGA_ns[7] Inst state_machine_un42_clk_030_1 state_machine.un42_clk_030_1 + Inst SM_AMIGA_ns_o3_1_ SM_AMIGA_ns_o3[1] Inst state_machine_un42_clk_030_2 state_machine.un42_clk_030_2 + Inst SM_AMIGA_ns_i_o3_0_ SM_AMIGA_ns_i_o3[0] Inst state_machine_un42_clk_030_3 state_machine.un42_clk_030_3 Inst state_machine_un42_clk_030_4 state_machine.un42_clk_030_4 Inst state_machine_un42_clk_030_5 state_machine.un42_clk_030_5 @@ -266,60 +278,49 @@ Design 'BUS68030' created Sun May 18 21:01:47 2014 Inst A_i_24_ A_i[24] Inst A_i_25_ A_i[25] Inst A_i_26_ A_i[26] + Inst clk_cpu_est_11_0_2_1_ clk.cpu_est_11_0_2[1] Inst A_i_27_ A_i[27] + Inst clk_cpu_est_11_0_1_ clk.cpu_est_11_0[1] Inst A_i_28_ A_i[28] - Inst clk_cpu_est_11_0_a4_1_1_3_ clk.cpu_est_11_0_a4_1_1[3] Inst A_i_29_ A_i[29] - Inst clk_cpu_est_11_0_a4_1_3_ clk.cpu_est_11_0_a4_1[3] Inst A_i_30_ A_i[30] - Inst clk_cpu_est_11_0_1_3_ clk.cpu_est_11_0_1[3] Inst A_i_31_ A_i[31] - Inst clk_cpu_est_11_0_3_ clk.cpu_est_11_0[3] - Inst SM_AMIGA_ns_a3_0_1_5_ SM_AMIGA_ns_a3_0_1[5] - Inst state_machine_UDS_000_INT_7 state_machine.UDS_000_INT_7 - Inst state_machine_LDS_000_INT_7 state_machine.LDS_000_INT_7 + Inst state_machine_un30_clk_000_d1 state_machine.un30_clk_000_d1 + Inst CLK_CNT_i_0_ CLK_CNT_i[0] Inst state_machine_un14_as_000_int_i state_machine.un14_as_000_int_i + Inst CLK_REF_0_ CLK_REF[0] Inst CLK_REF_1_ CLK_REF[1] - Inst UDS_000_INT_0_r UDS_000_INT_0.r - Inst UDS_000_INT_0_m UDS_000_INT_0.m - Inst UDS_000_INT_0_n UDS_000_INT_0.n - Inst UDS_000_INT_0_p UDS_000_INT_0.p - Inst LDS_000_INT_0_r LDS_000_INT_0.r - Inst LDS_000_INT_0_m LDS_000_INT_0.m - Inst LDS_000_INT_0_n LDS_000_INT_0.n + Inst SM_AMIGA_ns_o3_i_1_ SM_AMIGA_ns_o3_i[1] + Inst SM_AMIGA_ns_i_7_ SM_AMIGA_ns_i[7] + Inst SM_AMIGA_ns_i_1_ SM_AMIGA_ns_i[1] Inst state_machine_un44_clk_000_d1_1 state_machine.un44_clk_000_d1_1 - Inst LDS_000_INT_0_p LDS_000_INT_0.p Inst state_machine_un44_clk_000_d1 state_machine.un44_clk_000_d1 - Inst state_machine_LDS_000_INT_7_i state_machine.LDS_000_INT_7_i - Inst state_machine_UDS_000_INT_7_i state_machine.UDS_000_INT_7_i Inst state_machine_AS_030_000_SYNC_3_1 state_machine.AS_030_000_SYNC_3_1 Inst state_machine_AS_030_000_SYNC_3 state_machine.AS_030_000_SYNC_3 Inst clk_cpu_est_11_0_1_1_ clk.cpu_est_11_0_1[1] - Inst clk_cpu_est_11_0_2_1_ clk.cpu_est_11_0_2[1] - Inst clk_cpu_est_11_0_1_ clk.cpu_est_11_0[1] + Inst state_machine_AS_030_000_SYNC_3_i state_machine.AS_030_000_SYNC_3_i + Inst SIZE_c_i_1_ SIZE_c_i[1] + Inst state_machine_un44_clk_000_d1_i_0 state_machine.un44_clk_000_d1_i_0 Inst SM_AMIGA_ns_i_5_ SM_AMIGA_ns_i[5] Inst SM_AMIGA_ns_i_o3_i_6_ SM_AMIGA_ns_i_o3_i[6] - Inst state_machine_un44_clk_000_d1_i_0 state_machine.un44_clk_000_d1_i_0 - Inst A_c_i_0_ A_c_i[0] - Inst SIZE_c_i_1_ SIZE_c_i[1] - Inst SM_AMIGA_ns_i_1_ SM_AMIGA_ns_i[1] + Inst SM_AMIGA_ns_i_o3_i_0_ SM_AMIGA_ns_i_o3_i[0] Inst state_machine_un13_clk_000_d0_i state_machine.un13_clk_000_d0_i Inst state_machine_un15_clk_000_d0_i state_machine.un15_clk_000_d0_i - Inst state_machine_un23_clk_000_d0_i_0 state_machine.un23_clk_000_d0_i_0 Inst SM_AMIGA_ns_i_2_ SM_AMIGA_ns_i[2] - Inst state_machine_un1_clk_030_i state_machine.un1_clk_030_i Inst clk_un4_clk_000_d1_i clk.un4_clk_000_d1_i Inst state_machine_un6_bgack_000_i state_machine.un6_bgack_000_i + Inst state_machine_un23_clk_000_d0_i_0 state_machine.un23_clk_000_d0_i_0 + Inst state_machine_un1_clk_030_i state_machine.un1_clk_030_i Inst state_machine_un17_clk_030_i state_machine.un17_clk_030_i - Inst SM_AMIGA_ns_o3_i_1_ SM_AMIGA_ns_o3_i[1] - Inst state_machine_AS_030_000_SYNC_3_i state_machine.AS_030_000_SYNC_3_i + Inst A_c_i_0_ A_c_i[0] + Inst state_machine_UDS_000_INT_7_i state_machine.UDS_000_INT_7_i + Inst state_machine_LDS_000_INT_7_i state_machine.LDS_000_INT_7_i + Inst SM_AMIGA_ns_i_o3_i_4_ SM_AMIGA_ns_i_o3_i[4] Inst clk_cpu_est_11_0_i_1_ clk.cpu_est_11_0_i[1] Inst clk_cpu_est_11_0_i_3_ clk.cpu_est_11_0_i[3] Inst clk_cpu_est_11_0_o4_i_3_ clk.cpu_est_11_0_o4_i[3] Inst clk_cpu_est_11_0_o4_i_1_ clk.cpu_est_11_0_o4_i[1] - Inst SM_AMIGA_ns_i_7_ SM_AMIGA_ns_i[7] Inst state_machine_un8_clk_000_d0_i state_machine.un8_clk_000_d0_i - Inst SM_AMIGA_ns_i_o3_i_0_ SM_AMIGA_ns_i_o3_i[0] Net cpu_est_3__n cpu_est[3] Net cpu_est_0__n cpu_est[0] Net cpu_est_1__n cpu_est[1] @@ -329,20 +330,20 @@ Design 'BUS68030' created Sun May 18 21:01:47 2014 Net ipl_030_1__n IPL_030[1] Net ipl_030_c_2__n IPL_030_c[2] Net ipl_c_0__n IPL_c[0] - Net ipl_0__n IPL[0] - Net ipl_c_1__n IPL_c[1] - Net ipl_1__n IPL[1] Net sm_amiga_6__n SM_AMIGA[6] - Net ipl_c_2__n IPL_c[2] + Net ipl_0__n IPL[0] Net vcc_n_n VCC + Net ipl_c_1__n IPL_c[1] Net gnd_n_n GND - Net dsack_0__n DSACK[0] + Net ipl_1__n IPL[1] Net cpu_est_2__n cpu_est[2] - Net dsack_c_1__n DSACK_c[1] + Net ipl_c_2__n IPL_c[2] + Net clk_ref_0__n CLK_REF[0] Net clk_ref_1__n CLK_REF[1] + Net dsack_0__n DSACK[0] Net sm_amiga_7__n SM_AMIGA[7] + Net dsack_c_1__n DSACK_c[1] Net dsack_int_1__n DSACK_INT[1] - Net clk_un4_clk_000_d1_n clk.un4_clk_000_d1 Net sm_amiga_4__n SM_AMIGA[4] Net sm_amiga_1__n SM_AMIGA[1] Net clk_clk_cnt_n clk.clk_cnt @@ -352,48 +353,51 @@ Design 'BUS68030' created Sun May 18 21:01:47 2014 Net sm_amiga_3__n SM_AMIGA[3] Net clk_clk_cnt_3_0__n clk.CLK_CNT_3[0] Net clk_clk_cnt_3_1__n clk.CLK_CNT_3[1] - Net fc_c_0__n FC_c[0] - Net fc_0__n FC[0] Net sm_amiga_5__n SM_AMIGA[5] - Net fc_c_1__n FC_c[1] Net sm_amiga_2__n SM_AMIGA[2] Net sm_amiga_0__n SM_AMIGA[0] - Net state_machine_lds_000_int_7_n state_machine.LDS_000_INT_7 - Net state_machine_uds_000_int_7_n state_machine.UDS_000_INT_7 + Net fc_c_0__n FC_c[0] + Net fc_0__n FC[0] + Net fc_c_1__n FC_c[1] Net clk_cpu_est_11_0_1__n clk.cpu_est_11_0[1] - Net clk_cpu_est_11_0_3__n clk.cpu_est_11_0[3] Net sm_amiga_ns_1__n SM_AMIGA_ns[1] + Net clk_cpu_est_11_0_3__n clk.cpu_est_11_0[3] Net sm_amiga_ns_2__n SM_AMIGA_ns[2] Net sm_amiga_ns_5__n SM_AMIGA_ns[5] Net sm_amiga_ns_7__n SM_AMIGA_ns[7] - Net sm_amiga_ns_0_7__n SM_AMIGA_ns_0[7] Net state_machine_un30_clk_000_d1_n state_machine.un30_clk_000_d1 Net state_machine_un8_clk_000_d0_i_n state_machine.un8_clk_000_d0_i Net state_machine_un13_clk_000_d0_i_n state_machine.un13_clk_000_d0_i - Net state_machine_un15_clk_000_d0_0_n state_machine.un15_clk_000_d0_0 - Net state_machine_un44_clk_000_d1_n state_machine.un44_clk_000_d1 - Net state_machine_un23_clk_000_d0_i_n state_machine.un23_clk_000_d0_i Net un3_clk_cnt_1__n un3_clk_cnt[1] + Net state_machine_un15_clk_000_d0_0_n state_machine.un15_clk_000_d0_0 Net sm_amiga_ns_0_2__n SM_AMIGA_ns_0[2] - Net state_machine_un1_clk_030_0_n state_machine.un1_clk_030_0 Net clk_un4_clk_000_d1_i_n clk.un4_clk_000_d1_i Net state_machine_un6_bgack_000_0_n state_machine.un6_bgack_000_0 + Net state_machine_un23_clk_000_d0_i_n state_machine.un23_clk_000_d0_i + Net state_machine_un1_clk_030_0_n state_machine.un1_clk_030_0 Net state_machine_un17_clk_030_0_n state_machine.un17_clk_030_0 - Net state_machine_amiga_bus_enable_2_iv_i_n state_machine.AMIGA_BUS_ENABLE_2_iv_i - Net state_machine_as_030_000_sync_3_2_n state_machine.AS_030_000_SYNC_3_2 - Net state_machine_un42_clk_030_n state_machine.un42_clk_030 - Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5] - Net state_machine_as_030_000_sync_3_n state_machine.AS_030_000_SYNC_3 - Net state_machine_un17_clk_030_n state_machine.un17_clk_030 - Net state_machine_un44_clk_000_d1_i_n state_machine.un44_clk_000_d1_i - Net state_machine_un6_bgack_000_n state_machine.un6_bgack_000 + Net state_machine_un13_clk_000_d0_1_n state_machine.un13_clk_000_d0_1 Net a_c_i_0__n A_c_i[0] - Net state_machine_un1_clk_030_n state_machine.un1_clk_030 - Net size_c_i_1__n SIZE_c_i[1] - Net sm_amiga_ns_0_1__n SM_AMIGA_ns_0[1] - Net state_machine_un23_clk_000_d0_n state_machine.un23_clk_000_d0 - Net state_machine_lds_000_int_7_0_n state_machine.LDS_000_INT_7_0 Net state_machine_uds_000_int_7_0_n state_machine.UDS_000_INT_7_0 + Net state_machine_lds_000_int_7_0_n state_machine.LDS_000_INT_7_0 + Net state_machine_amiga_bus_enable_2_iv_i_n state_machine.AMIGA_BUS_ENABLE_2_iv_i + Net state_machine_un42_clk_030_n state_machine.un42_clk_030 + Net state_machine_as_030_000_sync_3_2_n state_machine.AS_030_000_SYNC_3_2 + Net state_machine_un44_clk_000_d1_n state_machine.un44_clk_000_d1 + Net size_c_i_1__n SIZE_c_i[1] + Net state_machine_as_030_000_sync_3_n state_machine.AS_030_000_SYNC_3 + Net state_machine_un44_clk_000_d1_i_n state_machine.un44_clk_000_d1_i + Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5] + Net state_machine_lds_000_int_7_n state_machine.LDS_000_INT_7 + Net state_machine_uds_000_int_7_n state_machine.UDS_000_INT_7 + Net state_machine_un17_clk_030_n state_machine.un17_clk_030 + Net state_machine_un1_clk_030_n state_machine.un1_clk_030 + Net state_machine_un23_clk_000_d0_n state_machine.un23_clk_000_d0 + Net sm_amiga_ns_0_7__n SM_AMIGA_ns_0[7] + Net sm_amiga_ns_0_1__n SM_AMIGA_ns_0[1] + Net state_machine_un6_bgack_000_n state_machine.un6_bgack_000 + Net clk_un4_clk_000_d1_n clk.un4_clk_000_d1 + Net state_machine_un44_clk_000_d1_i_1_n state_machine.un44_clk_000_d1_i_1 Net state_machine_un15_clk_000_d0_n state_machine.un15_clk_000_d0 Net clk_cpu_est_11_3__n clk.cpu_est_11[3] Net state_machine_un2_clk_000_n state_machine.un2_clk_000 @@ -402,107 +406,105 @@ Design 'BUS68030' created Sun May 18 21:01:47 2014 Net clk_cpu_est_11_0_1_1__n clk.cpu_est_11_0_1[1] Net state_machine_un8_clk_000_d0_n state_machine.un8_clk_000_d0 Net clk_cpu_est_11_0_2_1__n clk.cpu_est_11_0_2[1] - Net state_machine_un13_clk_000_d0_1_n state_machine.un13_clk_000_d0_1 Net state_machine_un13_clk_000_d0_2_n state_machine.un13_clk_000_d0_2 Net clk_cpu_est_11_1__n clk.cpu_est_11[1] - Net state_machine_un44_clk_000_d1_i_1_n state_machine.un44_clk_000_d1_i_1 Net state_machine_un42_clk_030_1_n state_machine.un42_clk_030_1 Net state_machine_un42_clk_030_2_n state_machine.un42_clk_030_2 Net state_machine_un42_clk_030_3_n state_machine.un42_clk_030_3 Net state_machine_un42_clk_030_4_n state_machine.un42_clk_030_4 Net state_machine_un42_clk_030_5_n state_machine.un42_clk_030_5 Net dsack_i_1__n DSACK_i[1] - Net clk_cpu_est_11_0_1_3__n clk.cpu_est_11_0_1[3] Net sm_amiga_i_4__n SM_AMIGA_i[4] Net sm_amiga_i_5__n SM_AMIGA_i[5] Net sm_amiga_i_3__n SM_AMIGA_i[3] Net cpu_est_i_0__n cpu_est_i[0] - Net cpu_est_i_2__n cpu_est_i[2] - Net state_machine_un13_clk_000_d0_2_i_n state_machine.un13_clk_000_d0_2_i Net cpu_est_i_3__n cpu_est_i[3] + Net cpu_est_i_2__n cpu_est_i[2] Net cpu_est_i_1__n cpu_est_i[1] + Net clk_cpu_est_11_0_1_3__n clk.cpu_est_11_0_1[3] + Net state_machine_un13_clk_000_d0_2_i_n state_machine.un13_clk_000_d0_2_i Net state_machine_un8_clk_000_d0_1_n state_machine.un8_clk_000_d0_1 Net state_machine_un8_clk_000_d0_2_n state_machine.un8_clk_000_d0_2 Net state_machine_un8_clk_000_d0_3_n state_machine.un8_clk_000_d0_3 - Net state_machine_un13_clk_000_d0_1_i_n state_machine.un13_clk_000_d0_1_i Net state_machine_un8_clk_000_d0_4_n state_machine.un8_clk_000_d0_4 Net state_machine_un13_clk_000_d0_1_0_n state_machine.un13_clk_000_d0_1_0 Net state_machine_un13_clk_000_d0_2_0_n state_machine.un13_clk_000_d0_2_0 - Net ipl_030_0_2__un3_n IPL_030_0_2_.un3 - Net ipl_030_0_2__un1_n IPL_030_0_2_.un1 Net a_i_18__n A_i[18] - Net ipl_030_0_2__un0_n IPL_030_0_2_.un0 + Net cpu_est_0_1__un3_n cpu_est_0_1_.un3 Net a_i_16__n A_i[16] - Net ipl_030_0_1__un3_n IPL_030_0_1_.un3 + Net cpu_est_0_1__un1_n cpu_est_0_1_.un1 Net a_i_19__n A_i[19] + Net cpu_est_0_1__un0_n cpu_est_0_1_.un0 + Net cpu_est_0_3__un3_n cpu_est_0_3_.un3 + Net state_machine_un42_clk_030_i_n state_machine.un42_clk_030_i + Net cpu_est_0_3__un1_n cpu_est_0_3_.un1 + Net sm_amiga_i_6__n SM_AMIGA_i[6] + Net cpu_est_0_3__un0_n cpu_est_0_3_.un0 + Net sm_amiga_i_7__n SM_AMIGA_i[7] + Net ipl_030_0_0__un3_n IPL_030_0_0_.un3 + Net ipl_030_0_0__un1_n IPL_030_0_0_.un1 + Net ipl_030_0_0__un0_n IPL_030_0_0_.un0 + Net sm_amiga_i_2__n SM_AMIGA_i[2] + Net ipl_030_0_1__un3_n IPL_030_0_1_.un3 + Net sm_amiga_i_1__n SM_AMIGA_i[1] Net ipl_030_0_1__un1_n IPL_030_0_1_.un1 Net ipl_030_0_1__un0_n IPL_030_0_1_.un0 - Net ipl_030_0_0__un3_n IPL_030_0_0_.un3 - Net state_machine_un42_clk_030_i_n state_machine.un42_clk_030_i - Net ipl_030_0_0__un1_n IPL_030_0_0_.un1 - Net sm_amiga_i_6__n SM_AMIGA_i[6] - Net ipl_030_0_0__un0_n IPL_030_0_0_.un0 - Net sm_amiga_i_7__n SM_AMIGA_i[7] + Net ipl_030_0_2__un3_n IPL_030_0_2_.un3 + Net ipl_030_0_2__un1_n IPL_030_0_2_.un1 + Net ipl_030_0_2__un0_n IPL_030_0_2_.un0 + Net state_machine_un13_clk_000_d0_1_i_n state_machine.un13_clk_000_d0_1_i + Net uds_000_int_0_un3_n UDS_000_INT_0.un3 + Net clk_clk_cnt_i_n clk.clk_cnt_i + Net uds_000_int_0_un1_n UDS_000_INT_0.un1 + Net clk_cnt_i_0__n CLK_CNT_i[0] + Net uds_000_int_0_un0_n UDS_000_INT_0.un0 + Net vpa_sync_0_un3_n VPA_SYNC_0.un3 + Net a_i_30__n A_i[30] + Net vpa_sync_0_un1_n VPA_SYNC_0.un1 + Net a_i_31__n A_i[31] + Net vpa_sync_0_un0_n VPA_SYNC_0.un0 + Net a_i_28__n A_i[28] + Net as_000_int_0_un3_n AS_000_INT_0.un3 + Net a_i_29__n A_i[29] + Net as_000_int_0_un1_n AS_000_INT_0.un1 + Net a_i_26__n A_i[26] + Net as_000_int_0_un0_n AS_000_INT_0.un0 + Net a_i_27__n A_i[27] + Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 + Net a_i_24__n A_i[24] + Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1 + Net a_i_25__n A_i[25] + Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0 + Net vma_int_0_un3_n VMA_INT_0.un3 + Net vma_int_0_un1_n VMA_INT_0.un1 + Net state_machine_un14_as_000_int_i_n state_machine.un14_as_000_int_i + Net vma_int_0_un0_n VMA_INT_0.un0 Net cpu_est_0_2__un3_n cpu_est_0_2_.un3 Net cpu_est_0_2__un1_n cpu_est_0_2_.un1 Net cpu_est_0_2__un0_n cpu_est_0_2_.un0 - Net sm_amiga_i_2__n SM_AMIGA_i[2] - Net cpu_est_0_1__un3_n cpu_est_0_1_.un3 - Net sm_amiga_i_1__n SM_AMIGA_i[1] - Net cpu_est_0_1__un1_n cpu_est_0_1_.un1 - Net cpu_est_0_1__un0_n cpu_est_0_1_.un0 - Net vpa_sync_0_un3_n VPA_SYNC_0.un3 - Net vpa_sync_0_un1_n VPA_SYNC_0.un1 - Net vpa_sync_0_un0_n VPA_SYNC_0.un0 - Net clk_clk_cnt_i_n clk.clk_cnt_i - Net vma_int_0_un3_n VMA_INT_0.un3 - Net clk_cnt_i_0__n CLK_CNT_i[0] - Net vma_int_0_un1_n VMA_INT_0.un1 - Net a_i_30__n A_i[30] - Net vma_int_0_un0_n VMA_INT_0.un0 - Net a_i_31__n A_i[31] - Net cpu_est_0_3__un3_n cpu_est_0_3_.un3 - Net a_i_28__n A_i[28] - Net cpu_est_0_3__un1_n cpu_est_0_3_.un1 - Net a_i_29__n A_i[29] - Net cpu_est_0_3__un0_n cpu_est_0_3_.un0 - Net a_i_26__n A_i[26] - Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 - Net a_i_27__n A_i[27] - Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1 - Net a_i_24__n A_i[24] - Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0 - Net a_i_25__n A_i[25] + Net dsack_int_0_1__un3_n DSACK_INT_0_1_.un3 + Net dsack_int_0_1__un1_n DSACK_INT_0_1_.un1 + Net dsack_int_0_1__un0_n DSACK_INT_0_1_.un0 Net bg_000_0_un3_n BG_000_0.un3 Net bg_000_0_un1_n BG_000_0.un1 - Net state_machine_un14_as_000_int_i_n state_machine.un14_as_000_int_i Net bg_000_0_un0_n BG_000_0.un0 Net amiga_bus_enable_0_un3_n AMIGA_BUS_ENABLE_0.un3 + Net size_c_0__n SIZE_c[0] Net amiga_bus_enable_0_un1_n AMIGA_BUS_ENABLE_0.un1 + Net size_0__n SIZE[0] Net amiga_bus_enable_0_un0_n AMIGA_BUS_ENABLE_0.un0 + Net size_c_1__n SIZE_c[1] Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3 Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1 + Net a_c_0__n A_c[0] Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0 + Net a_0__n A[0] Net fpu_cs_int_0_un3_n FPU_CS_INT_0.un3 Net fpu_cs_int_0_un1_n FPU_CS_INT_0.un1 Net fpu_cs_int_0_un0_n FPU_CS_INT_0.un0 - Net as_000_int_0_un3_n AS_000_INT_0.un3 - Net size_c_0__n SIZE_c[0] - Net as_000_int_0_un1_n AS_000_INT_0.un1 - Net size_0__n SIZE[0] - Net as_000_int_0_un0_n AS_000_INT_0.un0 - Net size_c_1__n SIZE_c[1] - Net dsack_int_0_1__un3_n DSACK_INT_0_1_.un3 - Net dsack_int_0_1__un1_n DSACK_INT_0_1_.un1 - Net a_c_0__n A_c[0] - Net dsack_int_0_1__un0_n DSACK_INT_0_1_.un0 - Net a_0__n A[0] Net dtack_sync_0_un3_n DTACK_SYNC_0.un3 Net dtack_sync_0_un1_n DTACK_SYNC_0.un1 Net dtack_sync_0_un0_n DTACK_SYNC_0.un0 - Net uds_000_int_0_un3_n UDS_000_INT_0.un3 - Net uds_000_int_0_un1_n UDS_000_INT_0.un1 - Net uds_000_int_0_un0_n UDS_000_INT_0.un0 Net lds_000_int_0_un3_n LDS_000_INT_0.un3 Net lds_000_int_0_un1_n LDS_000_INT_0.un1 Net lds_000_int_0_un0_n LDS_000_INT_0.un0 diff --git a/Logic/bus68030.srf b/Logic/bus68030.srf index d4247bf..1fc62ae 100644 --- a/Logic/bus68030.srf +++ b/Logic/bus68030.srf @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Sun May 18 21:01:41 2014 +#Thu May 22 14:56:04 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode @@ -25,7 +25,6 @@ Post processing for work.bus68030.behavioral @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":116:32:116:34|Pruning register CLK_000_D4 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":115:32:115:34|Pruning register CLK_000_D3 @A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Feedback mux created for signal AMIGA_BUS_ENABLE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. -@W: CL111 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|All reachable assignments to CLK_REF(0) assign '0'; register removed by optimization @W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|Latch generated from process for signal CLK_REF(1 downto 0); possible missing assignment in an if or case statement. @W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Optimizing register bit DSACK_INT(0) to a constant 1 @W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Pruning register bit 0 of DSACK_INT(1 downto 0) @@ -44,7 +43,7 @@ State machine has 8 reachable states with original encodings of: @W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|Initial value is not supported on state machine SM_AMIGA @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sun May 18 21:01:41 2014 +# Thu May 22 14:56:04 2014 ###########################################################] Map & Optimize Report @@ -76,9 +75,10 @@ BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses AND2 159 uses -INV 126 uses +INV 127 uses OR2 18 uses -XOR2 4 uses +XOR2 5 uses +DLATSH 1 use DLATRH 1 use @@ -89,6 +89,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sun May 18 21:01:42 2014 +# Thu May 22 14:56:05 2014 ###########################################################] diff --git a/Logic/dm/BUS68030_compiler.xdm b/Logic/dm/BUS68030_compiler.xdm index 6cb1414..446166e 100644 --- a/Logic/dm/BUS68030_compiler.xdm +++ b/Logic/dm/BUS68030_compiler.xdm @@ -26,10 +26,10 @@ S7RCVMI="F3s Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S> SRSqS SRSqS"/ -S -S +/>SqSSqS"/ + + /S<7>CV ]sC diff --git a/Logic/run_options.txt b/Logic/run_options.txt index 99779a1..371813f 100644 --- a/Logic/run_options.txt +++ b/Logic/run_options.txt @@ -1,7 +1,7 @@ #-- Synopsys, Inc. #-- Version G-2012.09LC-SP1 #-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt -#-- Written on Sun May 18 21:01:41 2014 +#-- Written on Thu May 22 14:56:04 2014 #project files diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr index 2703791..99f269a 100644 --- a/Logic/synlog/bus68030_fpga_mapper.srr +++ b/Logic/synlog/bus68030_fpga_mapper.srr @@ -25,9 +25,10 @@ BUFTH 7 uses OBUF 15 uses BI_DIR 2 uses AND2 159 uses -INV 126 uses +INV 127 uses OR2 18 uses -XOR2 4 uses +XOR2 5 uses +DLATSH 1 use DLATRH 1 use @@ -38,6 +39,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sun May 18 21:01:42 2014 +# Thu May 22 14:56:05 2014 ###########################################################] diff --git a/Logic/synlog/report/BUS68030_compiler_errors.txt b/Logic/synlog/report/BUS68030_compiler_errors.txt index bf42ac0..42a0fbf 100644 --- a/Logic/synlog/report/BUS68030_compiler_errors.txt +++ b/Logic/synlog/report/BUS68030_compiler_errors.txt @@ -1,3 +1,3 @@ -@E: CD199 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":314:5:314:10|elseif should probably be elsif +@E: CD204 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":151:49:151:49|Expecting sequential statement @E|Parse errors encountered - exiting diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml index ed27042..838e05e 100644 --- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml +++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml @@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt - 10 + 9 C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt @@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t - - 1400439701 + 1400763364 \ No newline at end of file diff --git a/Logic/synlog/report/BUS68030_compiler_warnings.txt b/Logic/synlog/report/BUS68030_compiler_warnings.txt index 10c373f..a2e1070 100644 --- a/Logic/synlog/report/BUS68030_compiler_warnings.txt +++ b/Logic/synlog/report/BUS68030_compiler_warnings.txt @@ -3,7 +3,6 @@ @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:32:117:34|Pruning register CLK_000_D5 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":116:32:116:34|Pruning register CLK_000_D4 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":115:32:115:34|Pruning register CLK_000_D3 -@W: CL111 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|All reachable assignments to CLK_REF(0) assign '0'; register removed by optimization @W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|Latch generated from process for signal CLK_REF(1 downto 0); possible missing assignment in an if or case statement. @W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Optimizing register bit DSACK_INT(0) to a constant 1 @W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Pruning register bit 0 of DSACK_INT(1 downto 0) diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml index f3cb549..df171d3 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml +++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml @@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the 95MB -1400439702 +1400763365 diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml index fa9e311..9ab0a9c 100644 --- a/Logic/syntmp/run_option.xml +++ b/Logic/syntmp/run_option.xml @@ -3,7 +3,7 @@ Synopsys, Inc. Version G-2012.09LC-SP1 Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml - Written on Sun May 18 21:01:41 2014 + Written on Thu May 22 14:56:04 2014 --> diff --git a/Logic/synwork/BUS68030_compiler.fdep b/Logic/synwork/BUS68030_compiler.fdep index 901192c..b8e42ee 100644 --- a/Logic/synwork/BUS68030_compiler.fdep +++ b/Logic/synwork/BUS68030_compiler.fdep @@ -10,7 +10,7 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400439696 +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400763359 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) diff --git a/Logic/synwork/BUS68030_compiler.fdeporig b/Logic/synwork/BUS68030_compiler.fdeporig index fdffd29..e97ab28 100644 --- a/Logic/synwork/BUS68030_compiler.fdeporig +++ b/Logic/synwork/BUS68030_compiler.fdeporig @@ -10,7 +10,7 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400439696 +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400763359 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) diff --git a/Logic/synwork/BUS68030_compiler.srs b/Logic/synwork/BUS68030_compiler.srs index 3ff0f39..7cc84e0 100644 Binary files a/Logic/synwork/BUS68030_compiler.srs and b/Logic/synwork/BUS68030_compiler.srs differ diff --git a/Logic/synwork/BUS68030_compiler.tlg b/Logic/synwork/BUS68030_compiler.tlg index f4c01d0..b2e7b9c 100644 --- a/Logic/synwork/BUS68030_compiler.tlg +++ b/Logic/synwork/BUS68030_compiler.tlg @@ -6,7 +6,6 @@ Post processing for work.bus68030.behavioral @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":116:32:116:34|Pruning register CLK_000_D4 @W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":115:32:115:34|Pruning register CLK_000_D3 @A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Feedback mux created for signal AMIGA_BUS_ENABLE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. -@W: CL111 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|All reachable assignments to CLK_REF(0) assign '0'; register removed by optimization @W: CL117 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":183:2:183:3|Latch generated from process for signal CLK_REF(1 downto 0); possible missing assignment in an if or case statement. @W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Optimizing register bit DSACK_INT(0) to a constant 1 @W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:52:109:55|Pruning register bit 0 of DSACK_INT(1 downto 0)