From 23323633f907a34a36a5996e168a1b0cba691638 Mon Sep 17 00:00:00 2001 From: MHeinrichs Date: Fri, 19 Aug 2016 00:22:24 +0200 Subject: [PATCH] Clarified some thing Timing can be adjusted with constants --- Logic/68030-68000-bus.vhd | 98 +- Logic/68030_TK.STY | 6 +- Logic/68030_TK.cmi | 8 +- Logic/68030_TK.lci | 22 +- Logic/68030_TK.lct | 22 +- Logic/68030_TK.syn | 2 +- Logic/68030_TK.tcl | 13975 ++++++++++++++++ Logic/68030_tk.bl2 | 3247 ++-- Logic/68030_tk.bl3 | 1264 +- Logic/68030_tk.crf | 2 +- Logic/68030_tk.eq3 | 414 +- Logic/68030_tk.fti | 386 +- Logic/68030_tk.grp | 48 +- Logic/68030_tk.ipr | 2 +- Logic/68030_tk.jed | 1217 +- Logic/68030_tk.lco | 190 +- Logic/68030_tk.out | 8674 +++++++++- Logic/68030_tk.plc | 216 +- Logic/68030_tk.prd | 1692 +- Logic/68030_tk.rpt | 1388 +- Logic/68030_tk.tal | 46 +- Logic/68030_tk.tt2 | 1146 +- Logic/68030_tk.tt3 | 1146 +- Logic/68030_tk.tt4 | 606 +- Logic/68030_tk.tte | 606 +- Logic/68030_tk.vcl | 124 +- Logic/68030_tk.vco | 190 +- Logic/68030_tk.vct | 22 +- Logic/68030_tk.xrf | 2 +- Logic/BUS68030.bl0 | 3220 ++-- Logic/BUS68030.bl1 | 3247 ++-- Logic/BUS68030.edi | 5923 +++---- Logic/BUS68030.fse | 20 +- Logic/BUS68030.naf | 64 +- Logic/BUS68030.prj | 2 +- Logic/BUS68030.srm | 6493 +++---- Logic/BUS68030.srr | 49 +- Logic/BUS68030.srs | Bin 13161 -> 13588 bytes Logic/bus68030.exf | 1308 +- Logic/bus68030.srf | 77 +- Logic/run_options.txt | 2 +- Logic/synlog/BUS68030_multi_srs_gen.srr | 2 +- Logic/synlog/bus68030_fpga_mapper.srr | 14 +- .../report/BUS68030_compiler_errors.txt | 2 +- .../synlog/report/BUS68030_compiler_notes.txt | 8 +- .../report/BUS68030_compiler_runstatus.xml | 4 +- .../report/BUS68030_compiler_warnings.txt | 19 +- .../report/BUS68030_fpga_mapper_runstatus.xml | 2 +- Logic/syntmp/BUS68030_srr.htm | 65 +- Logic/syntmp/BUS68030_toc.htm | 2 +- Logic/syntmp/run_option.xml | 2 +- Logic/syntmp/statusReport.html | 8 +- Logic/synwork/BUS68030_comp.fdep | 2 +- Logic/synwork/BUS68030_comp.fdeporig | 2 +- Logic/synwork/BUS68030_comp.srs | Bin 12568 -> 13047 bytes Logic/synwork/BUS68030_comp.tlg | 27 +- Logic/synwork/BUS68030_mult.srs | Bin 13161 -> 13588 bytes Logic/synwork/BUS68030_mult_srs/skeleton.srs | Bin 1121 -> 1222 bytes Logic/synwork/BUS68030_s.srs | Bin 12568 -> 13047 bytes 59 files changed, 40637 insertions(+), 16688 deletions(-) diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index 8a2bafb..acc9e3b 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -20,9 +20,11 @@ port( UDS_000: inout std_logic; LDS_000: inout std_logic; SIZE: inout std_logic_vector ( 1 downto 0 ); - A: in std_logic_vector ( 31 downto 2 ); - A0: inout std_logic; - A1: in std_logic; + AHIGH: inout std_logic_vector ( 31 downto 24 ); + A_DECODE: in std_logic_vector ( 23 downto 2 ); + A: inout std_logic_vector ( 1 downto 0 ); + --A0: inout std_logic; + --A1: in std_logic; nEXP_SPACE: in std_logic ; BERR: inout std_logic ; BG_030: in std_logic ; @@ -59,6 +61,10 @@ end BUS68030; architecture Behavioral of BUS68030 is +-- values are determined empiracally for 7.09 MHz Clock with a base clock of 100Mhz +constant PE_CLK : integer := 10; +constant NE_CLK : integer := 12; +constant DS_SAMPLE : integer := 12; @@ -96,7 +102,6 @@ signal SM_AMIGA : SM_68000; --signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000"; signal AS_000_INT:STD_LOGIC := '1'; signal RW_000_INT:STD_LOGIC := '1'; -signal AMIGA_BUS_ENABLE_INT:STD_LOGIC := '1'; signal AMIGA_BUS_ENABLE_DMA_HIGH:STD_LOGIC := '1'; signal AMIGA_BUS_ENABLE_DMA_LOW:STD_LOGIC := '1'; signal AS_030_D0:STD_LOGIC := '1'; @@ -126,9 +131,9 @@ signal CLK_OUT_PRE_D: STD_LOGIC := '1'; signal CLK_OUT_INT: STD_LOGIC := '1'; signal CLK_OUT_EXP_INT: STD_LOGIC := '1'; signal CLK_030_H: STD_LOGIC := '1'; -signal CLK_000_D: STD_LOGIC_VECTOR ( 7 downto 0 ) := "00000000"; -signal CLK_000_P_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000"; -signal CLK_000_N_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) := "0000000000000"; +signal CLK_000_D: STD_LOGIC_VECTOR ( DS_SAMPLE downto 0 ); +signal CLK_000_P_SYNC: STD_LOGIC_VECTOR ( PE_CLK downto 0 ); +signal CLK_000_N_SYNC: STD_LOGIC_VECTOR ( NE_CLK downto 0 ); signal CLK_000_PE: STD_LOGIC := '0'; signal CLK_000_NE: STD_LOGIC := '0'; signal CLK_000_NE_D0: STD_LOGIC := '0'; @@ -139,8 +144,15 @@ signal CLK_030_D0: STD_LOGIC := '0'; signal RST_DLY: STD_LOGIC_VECTOR ( 2 downto 0 ) := "000"; --signal RST_DLY_AMIGA: STD_LOGIC_VECTOR ( 7 downto 0 ) := "00000000"; --signal RESET_OUT_AMIGA: STD_LOGIC := '0'; + begin + CLK_000_PE <= CLK_000_P_SYNC(PE_CLK); + CLK_000_NE <= CLK_000_N_SYNC(NE_CLK); + --CLK_000_PE <= CLK_000_D(0) AND NOT CLK_000_D(1); + --CLK_000_NE <= NOT CLK_000_D(0) AND CLK_000_D(1) AND CLK_000_D(2); + + --pos edge clock process --no ansynchronious reset! the reset is sampled synchroniously --this mut be because of the e-clock: The E-Clock has to run CONSTANTLY @@ -166,20 +178,14 @@ begin CLK_OUT_EXP_INT <= CLK_OUT_PRE_50; --delayed Clocks and signals for edge detection CLK_000_D(0) <= CLK_000; - CLK_000_D(7 downto 1) <= CLK_000_D(6 downto 0); + CLK_000_D(DS_SAMPLE downto 1) <= CLK_000_D((DS_SAMPLE-1) downto 0); --shift registers for edge detection - CLK_000_P_SYNC( 12 downto 1 ) <= CLK_000_P_SYNC( 11 downto 0 ); + CLK_000_P_SYNC( PE_CLK downto 1 ) <= CLK_000_P_SYNC( (PE_CLK-1) downto 0 ); CLK_000_P_SYNC(0) <= CLK_000_D(0) AND NOT CLK_000_D(1); - CLK_000_N_SYNC( 12 downto 1 ) <= CLK_000_N_SYNC( 11 downto 0 ); + CLK_000_N_SYNC( NE_CLK downto 1 ) <= CLK_000_N_SYNC( (NE_CLK-1) downto 0 ); CLK_000_N_SYNC(0) <= NOT CLK_000_D(0) AND CLK_000_D(1); - -- values are determined empiracally for 7.09 MHz Clock - -- since the clock is not symmetrically these values differ! - CLK_000_PE <= CLK_000_P_SYNC(9); - CLK_000_NE <= CLK_000_N_SYNC(11); - --CLK_000_PE <= CLK_000_D(0) AND NOT CLK_000_D(1) AND NOT CLK_000_D(2); - --CLK_000_NE <= NOT CLK_000_D(0) AND CLK_000_D(1) AND CLK_000_D(2); CLK_000_NE_D0 <= CLK_000_NE; -- e-clock is changed on the FALLING edge! @@ -237,7 +243,6 @@ begin DS_000_DMA <= '1'; SIZE_DMA <= "11"; A0_DMA <= '1'; - AMIGA_BUS_ENABLE_INT <= '1'; AMIGA_BUS_ENABLE_DMA_HIGH <= '1'; AMIGA_BUS_ENABLE_DMA_LOW <= '1'; AS_030_D0 <= '1'; @@ -285,7 +290,7 @@ begin if(BG_030= '1')then BG_000 <= '1'; elsif( BG_030= '0' --AND (SM_AMIGA = IDLE_P) - and nEXP_SPACE_D0 = '1' and AS_030_D0='1' + and nEXP_SPACE = '1' and AS_030_D0='1' and CLK_000_D(0)='1' ) then --bus granted no local access and no AS_030 running! BG_000 <= '0'; @@ -313,8 +318,8 @@ begin AS_030_D0 = '0' AND --as set BGACK_030_INT='1' AND BGACK_030_INT_D='1' AND --no dma -cycle - NOT (FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0') AND --FPU-Select - nEXP_SPACE_D0 ='1' and --not an expansion space cycle + NOT (FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0') AND --FPU-Select + nEXP_SPACE ='1' and --not an expansion space cycle SM_AMIGA = IDLE_P --last amiga cycle terminated ) then AS_030_000_SYNC <= '0'; @@ -330,12 +335,12 @@ begin --uds/lds precalculation if (SM_AMIGA = IDLE_N) then --DS: set udl/lds - if(A0='0') then + if(A(0)='0') then UDS_000_INT <= '0'; else UDS_000_INT <= '1'; end if; - if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then + if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then LDS_000_INT <= '0'; else LDS_000_INT <= '1'; @@ -352,12 +357,10 @@ begin case (SM_AMIGA) is when IDLE_P => --68000:S0 wait for a falling edge RW_000_INT <= '1'; - AMIGA_BUS_ENABLE_INT <= CLK_000_D(1); - if( CLK_000_D(0)='0' and CLK_000_D(1)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE_D0 ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle! + if( CLK_000_D(1)='0' and CLK_000_D(2)= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle! SM_AMIGA<=IDLE_N; --go to s1 end if; when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe - AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga if(CLK_000_PE='1')then --go to s2 SM_AMIGA <= AS_SET_P; --as for amiga set! end if; @@ -392,8 +395,8 @@ begin end if; when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus! DS_000_ENABLE <= '1'; - if( (CLK_000_N_SYNC( 9)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR - (CLK_000_N_SYNC(10)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge + if( (CLK_000_D(DS_SAMPLE-2)='0' AND CLK_000_D((DS_SAMPLE-1))='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR + (CLK_000_D(DS_SAMPLE-1)='0' AND CLK_000_D((DS_SAMPLE-0))='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge DSACK1_INT <='0'; end if; if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge @@ -403,14 +406,11 @@ begin if(CLK_000_PE='1')then --go to s0 SM_AMIGA<=IDLE_P; RW_000_INT <= '1'; - --AMIGA_BUS_ENABLE_INT <= '1'; end if; end case; --dma stuff if(BGACK_030_INT='0')then - --switch amiga bus on for DMA-Cycles - AMIGA_BUS_ENABLE_INT <= '0' ; --set some signals NOT linked to AS_000='0' RW_000_DMA <= RW_000; -- now determine the size: if both uds and lds is set its 16 bit else 8 bit! @@ -427,11 +427,10 @@ begin A0_DMA <= UDS_000; --A1 is set by the amiga side --here we determine the upper or lower half of the databus - AMIGA_BUS_ENABLE_DMA_HIGH <= A1; - AMIGA_BUS_ENABLE_DMA_LOW <= not A1; + AMIGA_BUS_ENABLE_DMA_HIGH <= A(1); + AMIGA_BUS_ENABLE_DMA_LOW <= not A(1); elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then - AMIGA_BUS_ENABLE_INT <= '1' ; RW_000_DMA <= '1'; SIZE_DMA <= "00"; A0_DMA <= '0'; @@ -496,9 +495,8 @@ begin --RESET <= RESET_OUT; -- bus drivers - --AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT; AMIGA_ADDR_ENABLE <= '0'; - AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and not (SM_AMIGA = IDLE_P) ELSE + AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and not (SM_AMIGA = IDLE_P or (SM_AMIGA = END_CYCLE_N and CLK_000 = '1')) ELSE '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE '1'; AMIGA_BUS_ENABLE_LOW <= '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' ELSE @@ -507,26 +505,26 @@ begin AMIGA_BUS_DATA_DIR <= '1' WHEN (RW_000='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE '0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ - '1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE_D0 = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space + '1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space '0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space '0'; --Point towarts TK --dma stuff - DTACK <= 'Z'; - --DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else - -- '0' when DSACK1 ='0' else - -- '1'; - AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' or RESET_OUT ='0' else + DTACK <= 'Z'; --DTACK will be generated by GARY! + + AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else '0' when AS_000_DMA ='0' and AS_000 ='0' else '1'; - DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' or RESET_OUT ='0' else + DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else '0' when DS_000_DMA ='0' and AS_000 ='0' else '1'; - A0 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' or RESET_OUT ='0' else + A(0) <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else '0' when A0_DMA ='0' else '1'; - SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else + A(1) <= 'Z'; + AHIGH <= "ZZZZZZZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' or RESET_OUT ='0' else x"00"; + SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else "10" when SIZE_DMA ="10" else "01" when SIZE_DMA ="01" else "00"; @@ -538,19 +536,17 @@ begin BGACK_030 <= BGACK_030_INT; --fpu - FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='0' + FPU_CS <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0' AND BGACK_000='1' AND FPU_SENSE ='0' else '1'; --if no copro is installed: - BERR <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='1' + BERR <= '0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A_DECODE(19)='0' and A_DECODE(18)='0' and A_DECODE(17)='1' and A_DECODE(16)='0' AND BGACK_000='1' AND FPU_SENSE ='1' else 'Z'; - --BERR <= 'Z'; - --cache inhibit: Tristate for expansion (it decides) and off for the Amiga - CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom - 'Z' WHEN nEXP_SPACE_D0 = '0' ELSE --Tristate for expansion (it decides) + CIIN <= '1' WHEN AHIGH(31 downto 24) = x"00" and A_DECODE(23 downto 20) = x"F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom + 'Z' WHEN nEXP_SPACE = '0' ELSE --Tristate for expansion (it decides) '0'; --off for the Amiga --e and VMA @@ -584,7 +580,7 @@ begin '1'; --dsack - DSACK1 <= 'Z' when nEXP_SPACE_D0 = '0' else -- output on amiga cycle + DSACK1 <= 'Z' when nEXP_SPACE = '0' else -- output on amiga cycle '0' when DSACK1_INT ='0' else '1'; diff --git a/Logic/68030_TK.STY b/Logic/68030_TK.STY index b15bf23..4ec41bd 100644 --- a/Logic/68030_TK.STY +++ b/Logic/68030_TK.STY @@ -1,4 +1,6 @@ -[STRATEGY-LIST] -Normal=True, 1412327082 [synthesis-type] tool=Synplify +[STRATEGY-LIST] +Normal=True, 1412327082 +[TOUCHED-REPORT] +Design.tt4File=1471555574 diff --git a/Logic/68030_TK.cmi b/Logic/68030_TK.cmi index 22dd140..c90aea8 100644 --- a/Logic/68030_TK.cmi +++ b/Logic/68030_TK.cmi @@ -1,15 +1,15 @@ [WINDOWS] -MAIN_WINDOW_POSITION=2,26,1922,1041 -LEFT_PANE_WIDTH=634 +MAIN_WINDOW_POSITION=-7,0,967,1167 +LEFT_PANE_WIDTH=245 CHILD_FRAME_STATE=Maximal -CHILD_WINDOW_SIZE=1920,789 +CHILD_WINDOW_SIZE=974,941 CHILD_WINDOW_POS=-8,-31 [GUI SETTING] Remember_Setting=1 Open_PV_Opt=2 Open_PV=0 PV_IS_ACTIVE=0 -ACTIVE_SHEET=Global Constraints +ACTIVE_SHEET=Pin Attributes Show_Def_Opt=2 Show_Def_Val=1 Expand_All_Column=0 diff --git a/Logic/68030_TK.lci b/Logic/68030_TK.lci index f3888af..80fd337 100644 --- a/Logic/68030_TK.lci +++ b/Logic/68030_TK.lci @@ -12,8 +12,8 @@ EN_PinMacrocell = Yes; [Revision] Parent = m4a5.lci; -DATE = 03/16/2015; -TIME = 21:53:52; +DATE = 08/18/2016; +TIME = 23:26:14; Source_Format = Pure_VHDL; Synthesis = Synplify; @@ -100,6 +100,24 @@ FPU_SENSE = Pin, 91, -, A, -; A1 = Pin, 60, -, F, -; A_3_ = Pin, 44, -, E, -; A_2_ = Pin, 43, -, E, -; +AHIGH_24_ = Pin, 19, -, C, -; +AHIGH_25_ = Pin, 18, -, C, -; +AHIGH_26_ = Pin, 17, -, C, -; +AHIGH_27_ = Pin, 16, -, C, -; +AHIGH_28_ = Pin, 15, -, C, -; +AHIGH_29_ = Pin, 6, -, B, -; +AHIGH_30_ = Pin, 5, -, B, -; +AHIGH_31_ = Pin, 4, -, B, -; +A_1_ = Pin, 60, -, F, -; +A_0_ = Pin, 69, -, G, -; +A_DECODE_16_ = Pin, 96, -, A, -; +A_DECODE_17_ = Pin, 59, -, F, -; +A_DECODE_18_ = Pin, 95, -, A, -; +A_DECODE_19_ = Pin, 97, -, A, -; +A_DECODE_20_ = Pin, 93, -, A, -; +A_DECODE_21_ = Pin, 94, -, A, -; +A_DECODE_22_ = Pin, 84, -, H, -; +A_DECODE_23_ = Pin, 85, -, H, -; [Group Assignments] layer = OFF; diff --git a/Logic/68030_TK.lct b/Logic/68030_TK.lct index f3888af..80fd337 100644 --- a/Logic/68030_TK.lct +++ b/Logic/68030_TK.lct @@ -12,8 +12,8 @@ EN_PinMacrocell = Yes; [Revision] Parent = m4a5.lci; -DATE = 03/16/2015; -TIME = 21:53:52; +DATE = 08/18/2016; +TIME = 23:26:14; Source_Format = Pure_VHDL; Synthesis = Synplify; @@ -100,6 +100,24 @@ FPU_SENSE = Pin, 91, -, A, -; A1 = Pin, 60, -, F, -; A_3_ = Pin, 44, -, E, -; A_2_ = Pin, 43, -, E, -; +AHIGH_24_ = Pin, 19, -, C, -; +AHIGH_25_ = Pin, 18, -, C, -; +AHIGH_26_ = Pin, 17, -, C, -; +AHIGH_27_ = Pin, 16, -, C, -; +AHIGH_28_ = Pin, 15, -, C, -; +AHIGH_29_ = Pin, 6, -, B, -; +AHIGH_30_ = Pin, 5, -, B, -; +AHIGH_31_ = Pin, 4, -, B, -; +A_1_ = Pin, 60, -, F, -; +A_0_ = Pin, 69, -, G, -; +A_DECODE_16_ = Pin, 96, -, A, -; +A_DECODE_17_ = Pin, 59, -, F, -; +A_DECODE_18_ = Pin, 95, -, A, -; +A_DECODE_19_ = Pin, 97, -, A, -; +A_DECODE_20_ = Pin, 93, -, A, -; +A_DECODE_21_ = Pin, 94, -, A, -; +A_DECODE_22_ = Pin, 84, -, H, -; +A_DECODE_23_ = Pin, 85, -, H, -; [Group Assignments] layer = OFF; diff --git a/Logic/68030_TK.syn b/Logic/68030_TK.syn index 69ddd58..6342952 100644 --- a/Logic/68030_TK.syn +++ b/Logic/68030_TK.syn @@ -1,5 +1,5 @@ JDF B -// Created by Version 1.8 +// Created by Version 2.0 PROJECT 68030_TK DESIGN 68030_tk Normal DEVKIT M4A5-128/64-10VC diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index 46c9ad9..cec1bdd 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -355289,3 +355289,13978 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 08/17/16 17:45:34 ########### + +########## Tcl recorder starts at 08/18/16 22:11:43 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:11:43 ########### + + +########## Tcl recorder starts at 08/18/16 22:11:47 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:11:47 ########### + + +########## Tcl recorder starts at 08/18/16 22:13:05 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:13:05 ########### + + +########## Tcl recorder starts at 08/18/16 22:13:09 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:13:09 ########### + + +########## Tcl recorder starts at 08/18/16 22:13:42 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:13:42 ########### + + +########## Tcl recorder starts at 08/18/16 22:13:46 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:13:46 ########### + + +########## Tcl recorder starts at 08/18/16 22:14:56 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:14:56 ########### + + +########## Tcl recorder starts at 08/18/16 22:14:59 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:14:59 ########### + + +########## Tcl recorder starts at 08/18/16 22:16:24 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:16:24 ########### + + +########## Tcl recorder starts at 08/18/16 22:16:34 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:16:34 ########### + + +########## Tcl recorder starts at 08/18/16 22:17:38 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:17:38 ########### + + +########## Tcl recorder starts at 08/18/16 22:17:41 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:17:41 ########### + + +########## Tcl recorder starts at 08/18/16 22:18:37 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:18:37 ########### + + +########## Tcl recorder starts at 08/18/16 22:18:40 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:18:40 ########### + + +########## Tcl recorder starts at 08/18/16 22:20:07 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:20:07 ########### + + +########## Tcl recorder starts at 08/18/16 22:20:10 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:20:10 ########### + + +########## Tcl recorder starts at 08/18/16 22:21:33 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:21:33 ########### + + +########## Tcl recorder starts at 08/18/16 22:21:37 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:21:37 ########### + + +########## Tcl recorder starts at 08/18/16 22:22:48 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:22:48 ########### + + +########## Tcl recorder starts at 08/18/16 22:22:56 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:22:56 ########### + + +########## Tcl recorder starts at 08/18/16 22:23:53 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:23:53 ########### + + +########## Tcl recorder starts at 08/18/16 22:23:55 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:23:55 ########### + + +########## Tcl recorder starts at 08/18/16 22:24:43 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:24:43 ########### + + +########## Tcl recorder starts at 08/18/16 22:24:45 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:24:45 ########### + + +########## Tcl recorder starts at 08/18/16 22:25:40 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:25:40 ########### + + +########## Tcl recorder starts at 08/18/16 22:25:43 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:25:43 ########### + + +########## Tcl recorder starts at 08/18/16 22:27:16 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:27:16 ########### + + +########## Tcl recorder starts at 08/18/16 22:27:24 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:27:24 ########### + + +########## Tcl recorder starts at 08/18/16 22:32:12 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:32:12 ########### + + +########## Tcl recorder starts at 08/18/16 22:32:14 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:32:14 ########### + + +########## Tcl recorder starts at 08/18/16 22:33:51 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:33:51 ########### + + +########## Tcl recorder starts at 08/18/16 22:33:54 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:33:54 ########### + + +########## Tcl recorder starts at 08/18/16 22:34:39 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:34:39 ########### + + +########## Tcl recorder starts at 08/18/16 22:34:43 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:34:43 ########### + + +########## Tcl recorder starts at 08/18/16 22:36:01 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:36:01 ########### + + +########## Tcl recorder starts at 08/18/16 22:36:03 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:36:03 ########### + + +########## Tcl recorder starts at 08/18/16 22:37:03 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:37:03 ########### + + +########## Tcl recorder starts at 08/18/16 22:37:10 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:37:10 ########### + + +########## Tcl recorder starts at 08/18/16 22:38:03 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:38:03 ########### + + +########## Tcl recorder starts at 08/18/16 22:38:33 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:38:33 ########### + + +########## Tcl recorder starts at 08/18/16 22:38:35 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:38:35 ########### + + +########## Tcl recorder starts at 08/18/16 22:39:50 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:39:50 ########### + + +########## Tcl recorder starts at 08/18/16 22:39:55 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:39:55 ########### + + +########## Tcl recorder starts at 08/18/16 22:40:44 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:40:44 ########### + + +########## Tcl recorder starts at 08/18/16 22:40:57 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:40:57 ########### + + +########## Tcl recorder starts at 08/18/16 22:41:54 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:41:54 ########### + + +########## Tcl recorder starts at 08/18/16 22:41:59 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:41:59 ########### + + +########## Tcl recorder starts at 08/18/16 22:42:50 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:42:50 ########### + + +########## Tcl recorder starts at 08/18/16 22:42:52 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:42:52 ########### + + +########## Tcl recorder starts at 08/18/16 22:43:37 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:43:37 ########### + + +########## Tcl recorder starts at 08/18/16 22:43:40 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:43:40 ########### + + +########## Tcl recorder starts at 08/18/16 22:45:51 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:45:51 ########### + + +########## Tcl recorder starts at 08/18/16 22:45:55 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:45:55 ########### + + +########## Tcl recorder starts at 08/18/16 22:46:35 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:46:35 ########### + + +########## Tcl recorder starts at 08/18/16 22:46:36 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:46:36 ########### + + +########## Tcl recorder starts at 08/18/16 22:47:50 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:47:51 ########### + + +########## Tcl recorder starts at 08/18/16 22:47:54 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:47:54 ########### + + +########## Tcl recorder starts at 08/18/16 22:53:32 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:53:32 ########### + + +########## Tcl recorder starts at 08/18/16 22:53:33 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:53:33 ########### + + +########## Tcl recorder starts at 08/18/16 22:55:52 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:55:52 ########### + + +########## Tcl recorder starts at 08/18/16 22:55:52 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:55:52 ########### + + +########## Tcl recorder starts at 08/18/16 22:56:48 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:56:48 ########### + + +########## Tcl recorder starts at 08/18/16 22:56:48 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:56:48 ########### + + +########## Tcl recorder starts at 08/18/16 22:57:03 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:57:03 ########### + + +########## Tcl recorder starts at 08/18/16 22:57:03 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 22:57:03 ########### + + +########## Tcl recorder starts at 08/18/16 23:02:04 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:02:04 ########### + + +########## Tcl recorder starts at 08/18/16 23:02:05 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:02:05 ########### + + +########## Tcl recorder starts at 08/18/16 23:03:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:03:08 ########### + + +########## Tcl recorder starts at 08/18/16 23:03:09 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:03:09 ########### + + +########## Tcl recorder starts at 08/18/16 23:04:43 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:04:43 ########### + + +########## Tcl recorder starts at 08/18/16 23:04:43 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:04:43 ########### + + +########## Tcl recorder starts at 08/18/16 23:06:39 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:06:39 ########### + + +########## Tcl recorder starts at 08/18/16 23:06:39 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:06:39 ########### + + +########## Tcl recorder starts at 08/18/16 23:07:14 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:07:14 ########### + + +########## Tcl recorder starts at 08/18/16 23:07:14 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:07:14 ########### + + +########## Tcl recorder starts at 08/18/16 23:08:00 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:08:00 ########### + + +########## Tcl recorder starts at 08/18/16 23:08:01 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:08:01 ########### + + +########## Tcl recorder starts at 08/18/16 23:08:36 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:08:36 ########### + + +########## Tcl recorder starts at 08/18/16 23:08:36 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:08:36 ########### + + +########## Tcl recorder starts at 08/18/16 23:10:52 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:10:52 ########### + + +########## Tcl recorder starts at 08/18/16 23:10:52 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:10:52 ########### + + +########## Tcl recorder starts at 08/18/16 23:11:22 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:11:22 ########### + + +########## Tcl recorder starts at 08/18/16 23:11:22 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:11:22 ########### + + +########## Tcl recorder starts at 08/18/16 23:12:36 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:12:36 ########### + + +########## Tcl recorder starts at 08/18/16 23:12:37 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:12:37 ########### + + +########## Tcl recorder starts at 08/18/16 23:14:35 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:14:35 ########### + + +########## Tcl recorder starts at 08/18/16 23:14:35 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:14:35 ########### + + +########## Tcl recorder starts at 08/18/16 23:16:10 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:16:10 ########### + + +########## Tcl recorder starts at 08/18/16 23:16:10 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:16:10 ########### + + +########## Tcl recorder starts at 08/18/16 23:20:13 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:20:13 ########### + + +########## Tcl recorder starts at 08/18/16 23:20:13 ########## + +# Commands to make the Process: +# Constraint Editor +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:20:13 ########### + + +########## Tcl recorder starts at 08/18/16 23:21:13 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:21:13 ########### + + +########## Tcl recorder starts at 08/18/16 23:21:14 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:21:14 ########### + + +########## Tcl recorder starts at 08/18/16 23:21:40 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:21:40 ########### + + +########## Tcl recorder starts at 08/18/16 23:26:18 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:26:18 ########### + + +########## Tcl recorder starts at 08/18/16 23:33:07 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:33:07 ########### + + +########## Tcl recorder starts at 08/18/16 23:33:07 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:33:07 ########### + + +########## Tcl recorder starts at 08/18/16 23:33:37 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:33:37 ########### + + +########## Tcl recorder starts at 08/18/16 23:33:37 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:33:37 ########### + + +########## Tcl recorder starts at 08/18/16 23:34:47 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:34:47 ########### + + +########## Tcl recorder starts at 08/18/16 23:34:47 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:34:47 ########### + + +########## Tcl recorder starts at 08/18/16 23:36:16 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:36:16 ########### + + +########## Tcl recorder starts at 08/18/16 23:36:16 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:36:16 ########### + + +########## Tcl recorder starts at 08/18/16 23:36:58 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:36:58 ########### + + +########## Tcl recorder starts at 08/18/16 23:36:58 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:36:58 ########### + + +########## Tcl recorder starts at 08/18/16 23:37:45 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:37:45 ########### + + +########## Tcl recorder starts at 08/18/16 23:37:45 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:37:45 ########### + + +########## Tcl recorder starts at 08/18/16 23:38:46 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:38:46 ########### + + +########## Tcl recorder starts at 08/18/16 23:38:47 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:38:47 ########### + + +########## Tcl recorder starts at 08/18/16 23:39:39 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:39:39 ########### + + +########## Tcl recorder starts at 08/18/16 23:39:39 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:39:39 ########### + + +########## Tcl recorder starts at 08/18/16 23:40:33 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:40:33 ########### + + +########## Tcl recorder starts at 08/18/16 23:40:33 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:40:33 ########### + + +########## Tcl recorder starts at 08/18/16 23:41:48 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:41:48 ########### + + +########## Tcl recorder starts at 08/18/16 23:41:49 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:41:49 ########### + + +########## Tcl recorder starts at 08/18/16 23:42:40 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:42:40 ########### + + +########## Tcl recorder starts at 08/18/16 23:42:41 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:42:41 ########### + + +########## Tcl recorder starts at 08/18/16 23:43:29 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:43:29 ########### + + +########## Tcl recorder starts at 08/18/16 23:43:29 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:43:29 ########### + + +########## Tcl recorder starts at 08/18/16 23:45:16 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:45:16 ########### + + +########## Tcl recorder starts at 08/18/16 23:45:16 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:45:16 ########### + + +########## Tcl recorder starts at 08/18/16 23:51:40 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:51:40 ########### + + +########## Tcl recorder starts at 08/18/16 23:51:40 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:51:40 ########### + + +########## Tcl recorder starts at 08/18/16 23:52:16 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:52:16 ########### + + +########## Tcl recorder starts at 08/18/16 23:52:17 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:52:17 ########### + + +########## Tcl recorder starts at 08/18/16 23:52:52 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:52:52 ########### + + +########## Tcl recorder starts at 08/18/16 23:52:52 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:52:52 ########### + + +########## Tcl recorder starts at 08/18/16 23:53:56 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:53:56 ########### + + +########## Tcl recorder starts at 08/18/16 23:53:56 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:53:56 ########### + + +########## Tcl recorder starts at 08/18/16 23:55:26 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:55:26 ########### + + +########## Tcl recorder starts at 08/18/16 23:55:26 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:55:26 ########### + + +########## Tcl recorder starts at 08/18/16 23:57:48 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:57:48 ########### + + +########## Tcl recorder starts at 08/18/16 23:57:49 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:57:49 ########### + + +########## Tcl recorder starts at 08/18/16 23:59:06 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:59:06 ########### + + +########## Tcl recorder starts at 08/18/16 23:59:06 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:59:06 ########### + + +########## Tcl recorder starts at 08/18/16 23:59:57 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:59:57 ########### + + +########## Tcl recorder starts at 08/18/16 23:59:57 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/18/16 23:59:57 ########### + + +########## Tcl recorder starts at 08/19/16 00:02:14 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:02:14 ########### + + +########## Tcl recorder starts at 08/19/16 00:02:14 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:02:14 ########### + + +########## Tcl recorder starts at 08/19/16 00:04:18 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:04:18 ########### + + +########## Tcl recorder starts at 08/19/16 00:04:18 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:04:18 ########### + + +########## Tcl recorder starts at 08/19/16 00:10:53 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:10:53 ########### + + +########## Tcl recorder starts at 08/19/16 00:10:54 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:10:54 ########### + + +########## Tcl recorder starts at 08/19/16 00:11:24 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:11:24 ########### + + +########## Tcl recorder starts at 08/19/16 00:11:24 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:11:24 ########### + + +########## Tcl recorder starts at 08/19/16 00:11:51 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:11:51 ########### + + +########## Tcl recorder starts at 08/19/16 00:11:51 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:11:51 ########### + + +########## Tcl recorder starts at 08/19/16 00:12:54 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:12:54 ########### + + +########## Tcl recorder starts at 08/19/16 00:12:54 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:12:54 ########### + + +########## Tcl recorder starts at 08/19/16 00:16:45 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:16:45 ########### + + +########## Tcl recorder starts at 08/19/16 00:16:45 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:16:45 ########### + + +########## Tcl recorder starts at 08/19/16 00:18:22 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:18:22 ########### + + +########## Tcl recorder starts at 08/19/16 00:18:22 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:18:22 ########### + + +########## Tcl recorder starts at 08/19/16 00:20:26 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:20:26 ########### + + +########## Tcl recorder starts at 08/19/16 00:20:27 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 08/19/16 00:20:27 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index 3c31eee..362f1eb 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,440 +1,500 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Wed Aug 17 17:45:46 2016 +#$ DATE Fri Aug 19 00:20:41 2016 #$ MODULE 68030_tk -#$ PINS 75 A_8_ A_7_ SIZE_1_ A_6_ A_5_ A_31_ A_4_ A_3_ IPL_030_2_ A_2_ IPL_030_1_ IPL_2_ \ -# IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 \ -# nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT \ -# CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE SIZE_0_ \ -# AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN \ -# A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_15_ A_14_ A_13_ \ -# A_12_ A_11_ A_10_ A_9_ -#$ NODES 680 N_280 N_210_0 cpu_est_0_1__un0_n N_279 N_289_0 cpu_est_0_2__un3_n N_271 \ -# N_218_0 cpu_est_0_2__un1_n N_272 cpu_est_0_2__un0_n N_276 N_242_i cpu_est_0_3__un3_n \ -# DS_000_ENABLE_1_sqmuxa_1 N_246_i cpu_est_0_3__un1_n inst_BGACK_030_INTreg N_4 \ -# N_240_i cpu_est_0_3__un0_n vcc_n_n N_5 N_241_i ipl_030_0_0__un3_n inst_VMA_INTreg N_7 \ -# ipl_030_0_0__un1_n gnd_n_n N_10 N_266_i ipl_030_0_0__un0_n un1_amiga_bus_enable_low \ -# N_18 N_267_i ipl_030_0_1__un3_n un3_size N_24 N_254_i ipl_030_0_1__un1_n un4_size N_6 \ -# N_317_i ipl_030_0_1__un0_n un4_uds_000 un1_amiga_bus_enable_low_i \ -# ipl_030_0_2__un3_n un4_lds_000 un21_fpu_cs_i N_313_i ipl_030_0_2__un1_n un5_ciin \ -# BGACK_030_INT_i N_316_i ipl_030_0_2__un0_n un4_as_000 AMIGA_BUS_ENABLE_DMA_LOW_i \ -# N_312_i a0_dma_0_un3_n un21_fpu_cs UDS_000_INT_i a0_dma_0_un1_n un22_berr \ -# LDS_000_INT_i N_347_i a0_dma_0_un0_n un6_ds_030 N_236_i N_323_i uds_000_int_0_un3_n \ -# cpu_est_2_ sm_amiga_i_5__n N_324_i uds_000_int_0_un1_n cpu_est_3_ \ -# DS_000_ENABLE_1_sqmuxa_i N_222_i uds_000_int_0_un0_n cpu_est_0_ N_276_i \ -# AS_000_DMA_i vma_int_0_un3_n cpu_est_1_ RST_i N_221_0 vma_int_0_un1_n \ -# inst_AS_000_INT a_i_19__n N_220_0 vma_int_0_un0_n SM_AMIGA_5_ a_i_18__n N_219_0 \ -# amiga_bus_enable_dma_high_0_un3_n inst_AMIGA_BUS_ENABLE_DMA_LOW size_dma_i_1__n \ -# N_216_0 amiga_bus_enable_dma_high_0_un1_n inst_AS_030_D0 size_dma_i_0__n N_290_0 \ -# amiga_bus_enable_dma_high_0_un0_n inst_nEXP_SPACE_D0reg RW_i N_212_0 \ -# bg_000_0_un3_n inst_AS_030_000_SYNC CLK_000_PE_i N_211_0 bg_000_0_un1_n \ -# inst_BGACK_030_INT_D a_i_16__n N_204_0 bg_000_0_un0_n inst_AS_000_DMA RESET_OUT_i \ -# N_351_i ds_000_dma_0_un3_n inst_DS_000_DMA BERR_i N_353_i ds_000_dma_0_un1_n \ -# CYCLE_DMA_0_ sm_amiga_i_i_7__n N_201_i ds_000_dma_0_un0_n CYCLE_DMA_1_ \ -# nEXP_SPACE_D0_i VMA_INT_i as_000_dma_0_un3_n SIZE_DMA_0_ sm_amiga_i_4__n N_197_i \ -# as_000_dma_0_un1_n SIZE_DMA_1_ FPU_SENSE_i N_196_i as_000_dma_0_un0_n inst_VPA_D \ -# AS_030_i N_193_i lds_000_int_0_un3_n inst_UDS_000_INT AS_030_D0_i N_192_0 \ -# lds_000_int_0_un1_n inst_LDS_000_INT a_i_24__n clk_000_n_sync_i_10__n \ -# lds_000_int_0_un0_n inst_CLK_OUT_PRE_D sm_amiga_i_3__n N_350_i rw_000_dma_0_un3_n \ -# inst_DTACK_D0 cpu_est_i_0__n N_188_0 rw_000_dma_0_un1_n inst_RESET_OUT \ -# cpu_est_i_3__n N_187_i rw_000_dma_0_un0_n inst_CLK_OUT_PRE_50 cpu_est_i_2__n \ -# N_185_i a_15__n CLK_000_D_1_ cpu_est_i_1__n N_182_i CLK_000_D_0_ VPA_D_i N_181_i \ -# a_14__n inst_CLK_000_PE CLK_000_NE_i CLK_OUT_PRE_D_i CLK_000_P_SYNC_9_ \ -# sm_amiga_i_1__n N_175_0 a_13__n inst_CLK_000_NE rst_dly_i_2__n N_168_i \ -# CLK_000_N_SYNC_11_ CLK_030_i AS_030_000_SYNC_i a_12__n IPL_D0_0_ rst_dly_i_0__n \ -# N_158_i IPL_D0_1_ rst_dly_i_1__n clk_000_d_i_0__n a_11__n IPL_D0_2_ clk_000_d_i_1__n \ -# N_148_i inst_CLK_000_NE_D0 DTACK_D0_i N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i \ -# N_344_i SM_AMIGA_0_ CLK_030_H_i N_144_0 a_9__n inst_AMIGA_BUS_ENABLE_DMA_HIGH \ -# sm_amiga_i_6__n N_138_0 inst_DSACK1_INTreg sm_amiga_i_2__n a_8__n AS_000_i N_342_i \ -# pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n SM_AMIGA_4_ A1_i N_124_0 \ -# inst_DS_000_ENABLE a_i_31__n N_341_i a_6__n RST_DLY_0_ a_i_29__n N_119_0 RST_DLY_1_ \ -# a_i_30__n N_340_i a_5__n RST_DLY_2_ a_i_27__n N_361_i pos_clk_un9_bg_030_n a_i_28__n \ -# cpu_est_2_0_2__n a_4__n CLK_000_P_SYNC_0_ a_i_25__n N_338_i CLK_000_P_SYNC_1_ \ -# a_i_26__n N_339_i a_3__n CLK_000_P_SYNC_2_ N_213_i cpu_est_2_0_1__n \ -# CLK_000_P_SYNC_3_ N_214_i N_332_i a_2__n CLK_000_P_SYNC_4_ N_215_i N_336_i \ -# CLK_000_P_SYNC_5_ pos_clk_un7_clk_000_pe_0_n CLK_000_P_SYNC_6_ N_275_i N_99_0 \ -# CLK_000_P_SYNC_7_ un6_ds_030_i N_331_i CLK_000_P_SYNC_8_ DS_000_DMA_i N_96_0 \ -# CLK_000_N_SYNC_0_ un4_as_000_i N_330_i CLK_000_N_SYNC_1_ AS_000_INT_i N_90_0 \ -# CLK_000_N_SYNC_2_ un4_lds_000_i N_328_i CLK_000_N_SYNC_3_ un4_uds_000_i \ -# CLK_000_N_SYNC_4_ AS_030_c N_80_0 CLK_000_N_SYNC_5_ N_325_i CLK_000_N_SYNC_6_ \ -# AS_000_c N_326_i CLK_000_N_SYNC_7_ N_258_0 CLK_000_N_SYNC_8_ RW_000_c N_217_i \ -# CLK_000_N_SYNC_9_ N_321_i CLK_000_N_SYNC_10_ N_322_i inst_RW_000_INT UDS_000_c \ -# inst_RW_000_DMA N_320_i pos_clk_un7_clk_000_pe_n LDS_000_c inst_A0_DMA un5_ciin_i \ -# pos_clk_a0_dma_3_n size_c_0__n N_61_0 SM_AMIGA_6_ N_310_i inst_CLK_030_H size_c_1__n \ -# SM_AMIGA_1_ N_305_i SM_AMIGA_3_ N_307_i SM_AMIGA_2_ N_3 N_303_i N_8 N_304_i N_283_0 \ -# N_301_i N_300_i N_123_0 N_17 N_278_i N_19 N_297_i N_20 AMIGA_BUS_DATA_DIR_c_0 N_21 \ -# N_277_i N_22 N_25 N_26 pos_clk_un8_sm_amiga_i_n N_27 A0_c_i N_28 size_c_i_1__n N_29 \ -# N_29_i N_32_0 N_28_i N_31_0 N_27_i N_30_0 ipl_c_i_2__n N_53_0 ipl_c_i_1__n N_52_0 \ -# a_c_16__n ipl_c_i_0__n N_51_0 a_c_17__n DTACK_c_i N_56_0 a_c_18__n VPA_c_i N_55_0 \ -# a_c_19__n nEXP_SPACE_c_i N_54_0 a_c_20__n N_3_i N_49_0 a_c_21__n N_8_i N_45_0 a_c_22__n \ -# N_17_i N_42_0 a_c_23__n N_19_i N_40_0 SM_AMIGA_i_7_ a_c_24__n N_20_i N_123 N_39_0 \ -# cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i G_134 \ -# N_37_0 G_135 a_c_27__n N_25_i G_136 N_34_0 N_217 a_c_28__n N_26_i N_33_0 N_61 a_c_29__n \ -# BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 \ -# N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \ -# pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c N_351_2 N_124 N_168_i_1 N_138 \ -# nEXP_SPACE_c N_192_0_1 N_144 N_192_0_2 N_158 BERR_c N_137_i_1 N_168 N_137_i_2 N_175 \ -# BG_030_c N_145_i_1 N_182 N_145_i_2 N_185 BG_000DFFreg N_145_i_3 N_187 N_260_i_1 N_188 \ -# N_260_i_2 N_192 BGACK_000_c N_259_i_1 N_193 N_259_i_2 N_197 CLK_030_c N_336_1 N_201 \ -# N_336_2 N_204 N_332_1 N_206 N_332_2 N_207 CLK_OSZI_c N_332_3 N_317_1 N_211 N_317_2 N_212 \ -# CLK_OUT_INTreg N_317_3 N_290 N_304_1 N_216 N_304_2 N_219 FPU_SENSE_c un5_ciin_1 N_220 \ -# un5_ciin_2 N_221 IPL_030DFF_0_reg un5_ciin_3 N_227 un5_ciin_4 N_229 IPL_030DFF_1_reg \ -# un5_ciin_5 N_230 un5_ciin_6 N_236 IPL_030DFF_2_reg un5_ciin_7 N_240 un5_ciin_8 N_241 \ -# ipl_c_0__n un5_ciin_9 N_242 un5_ciin_10 N_246 ipl_c_1__n un5_ciin_11 N_254 \ -# un22_berr_1_0 N_266 ipl_c_2__n un21_fpu_cs_1 N_267 N_375_1 N_275 N_375_2 N_277 DTACK_c \ -# N_375_3 N_278 N_375_4 N_297 N_134_i_1 N_300 N_96_0_1 N_301 VPA_c N_83_i_1 N_303 N_261_i_1 \ -# N_304 N_141_i_1 N_305 RST_c N_139_i_1 N_307 N_133_i_1 N_310 N_123_0_1 N_312 RW_c \ -# N_282_i_1 N_313 N_343_1 N_316 fc_c_0__n N_339_1 N_317 pos_clk_un6_bg_030_1_n N_320 \ -# fc_c_1__n N_326_1 N_321 N_325_1 N_322 N_324_1 N_323 AMIGA_BUS_DATA_DIR_c N_316_1 N_324 \ -# N_313_1 N_325 N_303_1 N_326 N_297_1 N_328 N_266_1 N_330 N_24_i N_240_1 N_331 N_35_0 \ -# pos_clk_ipl_1_n N_332 N_18_i amiga_bus_enable_dma_low_0_un3_n N_336 N_41_0 \ -# amiga_bus_enable_dma_low_0_un1_n N_338 N_10_i amiga_bus_enable_dma_low_0_un0_n \ -# N_339 N_43_0 rw_000_int_0_un3_n N_340 N_7_i rw_000_int_0_un1_n N_341 N_46_0 \ -# rw_000_int_0_un0_n N_342 N_5_i bgack_030_int_0_un3_n N_343 N_47_0 \ -# bgack_030_int_0_un1_n N_344 N_4_i bgack_030_int_0_un0_n N_345 N_48_0 \ -# as_030_000_sync_0_un3_n N_347 N_272_i as_030_000_sync_0_un1_n N_350 N_271_i \ -# as_030_000_sync_0_un0_n N_351 N_279_0 ds_000_enable_0_un3_n N_353 N_280_0 \ -# ds_000_enable_0_un1_n N_361 N_281_0 ds_000_enable_0_un0_n \ -# pos_clk_un23_bgack_030_int_i_i_a4_i_x2 N_298_i as_000_int_0_un3_n \ -# pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_size_dma_6_0_0__n as_000_int_0_un1_n \ -# cpu_est_0_0_x2_0_ N_299_i as_000_int_0_un0_n pos_clk_CYCLE_DMA_5_1_i_x2 \ -# pos_clk_size_dma_6_0_1__n dsack1_int_0_un3_n un22_berr_1 un1_as_000_i \ -# dsack1_int_0_un1_n N_375 N_358_i dsack1_int_0_un0_n N_218 pos_clk_un6_bgack_000_0_n \ -# size_dma_0_1__un3_n N_156 N_284_i size_dma_0_1__un1_n N_289 N_285_i \ -# size_dma_0_1__un0_n N_354 N_286_0 size_dma_0_0__un3_n N_205 N_88_0 \ -# size_dma_0_0__un1_n un1_SM_AMIGA_5 pos_clk_un3_as_030_d0_i_n size_dma_0_0__un0_n \ -# DS_000_ENABLE_1_sqmuxa N_156_i sm_amiga_srsts_i_0_m2_1__un3_n N_349 N_349_i \ -# sm_amiga_srsts_i_0_m2_1__un1_n pos_clk_un3_as_030_d0_n N_194_i \ -# sm_amiga_srsts_i_0_m2_1__un0_n N_286 un1_SM_AMIGA_5_i \ -# un1_amiga_bus_enable_dma_high_i_m2_0__un3_n pos_clk_un6_bgack_000_n UDS_000_c_i \ -# un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_358 LDS_000_c_i \ -# un1_amiga_bus_enable_dma_high_i_m2_0__un0_n pos_clk_size_dma_6_1__n N_205_i \ -# sm_amiga_srsts_i_0_m2_5__un3_n N_299 N_206_0 sm_amiga_srsts_i_0_m2_5__un1_n \ -# pos_clk_size_dma_6_0__n N_207_0 sm_amiga_srsts_i_0_m2_5__un0_n N_298 N_354_i \ -# cpu_est_0_1__un3_n N_281 N_208_0 cpu_est_0_1__un1_n +#$ PINS 75 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ AHIGH_31_ \ +# A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ A_DECODE_15_ A_DECODE_14_ \ +# A_DECODE_13_ IPL_030_2_ A_DECODE_12_ A_DECODE_11_ IPL_2_ A_DECODE_10_ A_DECODE_9_ \ +# FC_1_ A_DECODE_8_ AS_030 A_DECODE_7_ AS_000 A_DECODE_6_ RW_000 A_DECODE_5_ DS_030 \ +# A_DECODE_4_ UDS_000 A_DECODE_3_ LDS_000 A_DECODE_2_ nEXP_SPACE A_0_ BERR IPL_030_1_ \ +# BG_030 IPL_030_0_ BG_000 IPL_1_ BGACK_030 IPL_0_ BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 \ +# CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW \ +# AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH \ +# CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ +#$ NODES 694 N_166 N_32_0 cpu_est_0_3__un0_n N_141 a_c_i_0__n cpu_est_0_2__un3_n \ +# N_226 size_c_i_1__n cpu_est_0_2__un1_n N_357 pos_clk_un10_sm_amiga_i_n \ +# cpu_est_0_2__un0_n N_219 N_258_0 sm_amiga_srsts_i_0_m2_1__un3_n N_217 N_357_i \ +# sm_amiga_srsts_i_0_m2_1__un1_n N_221 N_254_i sm_amiga_srsts_i_0_m2_1__un0_n N_220 \ +# cpu_est_2_0_2__n vma_int_0_un3_n inst_BGACK_030_INTreg N_223 N_315_i \ +# vma_int_0_un1_n vcc_n_n N_343 N_291_0 vma_int_0_un0_n inst_VMA_INTreg N_192 \ +# AS_030_000_SYNC_i cpu_est_0_1__un3_n gnd_n_n N_164 N_146_0 cpu_est_0_1__un1_n \ +# un1_amiga_bus_enable_dma_high_0__n N_291 N_149_i cpu_est_0_1__un0_n \ +# un1_amiga_bus_enable_low N_315 N_164_i sm_amiga_srsts_i_0_0_m2_5__un3_n un6_as_030 \ +# cpu_est_2_2__n N_166_i sm_amiga_srsts_i_0_0_m2_5__un1_n un3_size N_254 N_172_i \ +# sm_amiga_srsts_i_0_0_m2_5__un0_n un4_size N_258 N_176_i rw_000_int_0_un3_n \ +# un4_uds_000 N_29 N_186_0 rw_000_int_0_un1_n un4_lds_000 N_28 N_192_0 \ +# rw_000_int_0_un0_n un4_as_000 N_27 N_228_i bgack_030_int_0_un3_n un10_ciin N_4 \ +# N_227_i bgack_030_int_0_un1_n un21_fpu_cs N_17 N_343_i bgack_030_int_0_un0_n \ +# un22_berr N_21 as_000_int_0_un3_n un6_ds_030 N_26 N_223_i as_000_int_0_un1_n \ +# cpu_est_2_ pos_clk_un9_bg_030_n N_225_i as_000_int_0_un0_n cpu_est_3_ \ +# un1_amiga_bus_enable_low_i N_224_i ds_000_enable_0_un3_n cpu_est_0_ un21_fpu_cs_i \ +# N_226_i ds_000_enable_0_un1_n cpu_est_1_ N_275_i ds_000_enable_0_un0_n \ +# inst_AS_000_INT clk_000_n_sync_i_12__n N_220_i as_030_000_sync_0_un3_n \ +# inst_AMIGA_BUS_ENABLE_DMA_LOW rst_dly_i_2__n N_221_i as_030_000_sync_0_un1_n \ +# inst_AS_030_D0 rst_dly_i_1__n N_222_i as_030_000_sync_0_un0_n inst_AS_030_000_SYNC \ +# BERR_i un1_amiga_bus_enable_dma_high_0_m2_0__un3_n inst_BGACK_030_INT_D \ +# cpu_est_i_2__n N_217_i un1_amiga_bus_enable_dma_high_0_m2_0__un1_n \ +# inst_AS_000_DMA nEXP_SPACE_i N_215_i un1_amiga_bus_enable_dma_high_0_m2_0__un0_n \ +# inst_DS_000_DMA rst_dly_i_0__n N_219_i amiga_bus_enable_dma_low_0_un3_n \ +# CYCLE_DMA_0_ cpu_est_i_1__n amiga_bus_enable_dma_low_0_un1_n CYCLE_DMA_1_ \ +# cpu_est_i_0__n N_200_i amiga_bus_enable_dma_low_0_un0_n SIZE_DMA_0_ VPA_D_i N_195_0 \ +# amiga_bus_enable_dma_high_0_un3_n SIZE_DMA_1_ sm_amiga_i_3__n N_190_0 \ +# amiga_bus_enable_dma_high_0_un1_n inst_VPA_D sm_amiga_i_0__n N_157_i \ +# amiga_bus_enable_dma_high_0_un0_n inst_UDS_000_INT cpu_est_i_3__n N_154_i \ +# size_dma_0_0__un3_n inst_LDS_000_INT sm_amiga_i_1__n N_340_i size_dma_0_0__un1_n \ +# inst_CLK_OUT_PRE_D RESET_OUT_i N_141_0 size_dma_0_0__un0_n CLK_000_D_10_ \ +# BGACK_030_INT_i un3_as_030_i size_dma_0_1__un3_n CLK_000_D_11_ sm_amiga_i_2__n \ +# N_216_i size_dma_0_1__un1_n inst_DTACK_D0 sm_amiga_i_4__n N_337_i \ +# size_dma_0_1__un0_n inst_RESET_OUT clk_000_p_sync_i_10__n ds_000_dma_0_un3_n \ +# inst_CLK_OUT_PRE_50 sm_amiga_i_5__n un10_ciin_i ds_000_dma_0_un1_n CLK_000_D_1_ \ +# sm_amiga_i_i_7__n N_296_0 ds_000_dma_0_un0_n CLK_000_D_0_ clk_000_d_i_11__n \ +# un1_as_000_i as_000_dma_0_un3_n CLK_000_P_SYNC_10_ sm_amiga_i_6__n N_284_i \ +# as_000_dma_0_un1_n SM_AMIGA_5_ RW_i N_285_i as_000_dma_0_un0_n IPL_D0_0_ \ +# DS_000_ENABLE_1_sqmuxa_i N_292_0 rw_000_dma_0_un3_n IPL_D0_1_ LDS_000_INT_i N_280_i \ +# rw_000_dma_0_un1_n IPL_D0_2_ UDS_000_INT_i N_277_i rw_000_dma_0_un0_n CLK_000_D_2_ \ +# AS_030_i N_257_0 a0_dma_0_un3_n CLK_000_D_3_ AS_000_INT_i N_235_i a0_dma_0_un1_n \ +# CLK_000_D_4_ a_decode_i_19__n N_236_i a0_dma_0_un0_n CLK_000_D_5_ a_decode_i_18__n \ +# cpu_est_2_0_1__n a_decode_15__n CLK_000_D_6_ a_decode_i_16__n N_231_i CLK_000_D_7_ \ +# AS_000_i N_230_i a_decode_14__n CLK_000_D_8_ FPU_SENSE_i pos_clk_un4_clk_000_pe_0_n \ +# CLK_000_D_9_ AMIGA_BUS_ENABLE_DMA_HIGH_i N_22_i a_decode_13__n CLK_000_D_12_ \ +# CLK_030_i N_37_0 pos_clk_un6_bg_030_n DTACK_D0_i a_decode_12__n SM_AMIGA_0_ \ +# clk_000_d_i_10__n N_334_i inst_DSACK1_INTreg RW_000_i N_335_i a_decode_11__n \ +# a_i_1__n N_194_0 CLK_030_H_i N_191_0 a_decode_10__n pos_clk_ipl_n AS_000_DMA_i \ +# un1_SM_AMIGA_5_i CLK_000_N_SYNC_0_ clk_000_d_i_0__n N_346_i a_decode_9__n \ +# SM_AMIGA_4_ clk_000_d_i_1__n N_163_i inst_DS_000_ENABLE AS_030_D0_i N_345_i \ +# a_decode_8__n CLK_000_N_SYNC_12_ size_dma_i_0__n N_344_i RST_DLY_0_ size_dma_i_1__n \ +# N_153_0 a_decode_7__n RST_DLY_1_ ahigh_i_30__n pos_clk_un3_as_030_d0_i_n RST_DLY_2_ \ +# ahigh_i_31__n N_293_0 a_decode_6__n CLK_000_P_SYNC_0_ ahigh_i_28__n N_233_i \ +# CLK_000_P_SYNC_1_ ahigh_i_29__n N_232_i a_decode_5__n CLK_000_P_SYNC_2_ \ +# ahigh_i_26__n N_290_0 CLK_000_P_SYNC_3_ ahigh_i_27__n VPA_c_i a_decode_4__n \ +# CLK_000_P_SYNC_4_ ahigh_i_24__n N_54_0 CLK_000_P_SYNC_5_ ahigh_i_25__n N_5_i \ +# a_decode_3__n CLK_000_P_SYNC_6_ N_212_i N_47_0 CLK_000_P_SYNC_7_ N_213_i N_7_i \ +# a_decode_2__n CLK_000_P_SYNC_8_ N_214_i N_46_0 CLK_000_P_SYNC_9_ N_18_i \ +# CLK_000_N_SYNC_1_ N_41_0 CLK_000_N_SYNC_2_ N_321_i N_10_i CLK_000_N_SYNC_3_ N_322_i \ +# N_43_0 CLK_000_N_SYNC_4_ un6_ds_030_i DTACK_c_i CLK_000_N_SYNC_5_ DS_000_DMA_i \ +# N_55_0 CLK_000_N_SYNC_6_ un4_as_000_i pos_clk_un6_bgack_000_0_n CLK_000_N_SYNC_7_ \ +# un6_as_030_i N_137_i CLK_000_N_SYNC_8_ un4_lds_000_i N_184_0 CLK_000_N_SYNC_9_ \ +# un4_uds_000_i N_349_i CLK_000_N_SYNC_10_ AMIGA_BUS_ENABLE_DMA_LOW_i N_185_i \ +# CLK_000_N_SYNC_11_ AS_030_c N_187_0 pos_clk_un5_bgack_030_int_d_n N_203_i \ +# inst_RW_000_INT AS_000_c N_324_i inst_RW_000_DMA inst_CLK_000_NE_D0 RW_000_c N_199_0 \ +# inst_AMIGA_BUS_ENABLE_DMA_HIGH N_197_0 inst_A0_DMA N_196_0 pos_clk_a0_dma_3_n \ +# UDS_000_c LDS_000_c_i SM_AMIGA_6_ UDS_000_c_i inst_CLK_030_H LDS_000_c N_181_i \ +# SM_AMIGA_1_ N_347_i SM_AMIGA_3_ size_c_0__n N_348_i SM_AMIGA_2_ N_178_i \ +# pos_clk_ds_000_dma_4_n size_c_1__n VMA_INT_i N_3 pos_clk_un5_bgack_030_int_d_i_n \ +# N_8 ahigh_c_24__n pos_clk_un23_bgack_030_int_i_1_0_n CLK_OUT_PRE_D_i ahigh_c_25__n \ +# N_148_0 N_341_i ahigh_c_26__n N_338_i N_339_i N_19 ahigh_c_27__n N_20 N_336_i N_24 \ +# ahigh_c_28__n N_122_0 N_25 N_211_i ahigh_c_29__n N_332_i ahigh_c_30__n N_331_i N_120_0 \ +# ahigh_c_31__n N_330_i pos_clk_ds_000_dma_4_0_n N_329_i pos_clk_size_dma_6_0_1__n \ +# N_328_i pos_clk_size_dma_6_0_0__n N_325_i N_327_i AMIGA_BUS_DATA_DIR_c_0 N_320_i \ +# N_298_0 N_295_0 N_294_0 N_319_i un1_amiga_bus_enable_dma_high_0_0__n N_206_i N_283_i \ +# SM_AMIGA_i_7_ N_122 N_281_i pos_clk_size_dma_6_0__n N_282_i pos_clk_size_dma_6_1__n \ +# G_134 N_3_i G_135 N_49_0 G_136 N_8_i N_45_0 pos_clk_un23_bgack_030_int_i_1_n N_19_i \ +# N_292 N_40_0 N_294 a_decode_c_16__n N_20_i N_295 N_39_0 N_296 a_decode_c_17__n N_24_i \ +# N_298 N_35_0 N_120 a_decode_c_18__n N_25_i N_148 N_34_0 N_149 a_decode_c_19__n \ +# N_194_0_1 N_157 N_237_i_1 N_172 a_decode_c_20__n N_237_i_2 N_176 N_238_i_1 N_178 \ +# a_decode_c_21__n N_238_i_2 N_181 N_144_i_1 N_184 a_decode_c_22__n N_144_i_2 N_144_i_3 \ +# N_196 a_decode_c_23__n N_136_i_1 N_197 N_136_i_2 N_206 a_c_0__n N_176_i_1 N_207 \ +# N_146_0_1 N_211 a_c_1__n pos_clk_un10_sm_amiga_i_1_n N_215 un10_ciin_1 N_222 \ +# nEXP_SPACE_c un10_ciin_2 N_224 un10_ciin_3 N_225 BERR_c un10_ciin_4 N_227 un10_ciin_5 \ +# N_228 BG_030_c un10_ciin_6 N_236 un10_ciin_7 N_277 BG_000DFFreg un10_ciin_8 N_281 \ +# un10_ciin_9 N_282 un10_ciin_10 N_283 BGACK_000_c un10_ciin_11 N_285 N_347_1 N_318 \ +# CLK_030_c N_347_2 N_319 pos_clk_un23_bgack_030_int_i_1_0_1_n N_320 CLK_000_c \ +# pos_clk_un23_bgack_030_int_i_1_0_2_n N_321 un21_fpu_cs_1 N_322 CLK_OSZI_c \ +# un22_berr_1_0 N_323 N_366_1 N_325 N_366_2 N_327 CLK_OUT_INTreg N_366_3 N_328 N_366_4 \ +# N_329 un1_SM_AMIGA_5_i_1 N_330 FPU_SENSE_c un1_SM_AMIGA_5_i_2 N_331 N_142_i_1 N_332 \ +# IPL_030DFF_0_reg N_142_i_2 N_336 N_339_1 N_338 IPL_030DFF_1_reg N_280_1 N_339 N_280_2 \ +# N_341 IPL_030DFF_2_reg N_231_1 N_344 N_231_2 N_347 ipl_c_0__n N_230_1 N_348 N_230_2 \ +# pos_clk_un23_bgack_030_int_i_0_x2 ipl_c_1__n N_230_3 cpu_est_0_0_x2_0_x2_0_ \ +# N_226_1 pos_clk_CYCLE_DMA_5_0_i_x2 ipl_c_2__n N_226_2 pos_clk_CYCLE_DMA_5_1_i_x2 \ +# N_226_3 N_199 N_239_i_1 N_324 DTACK_c N_122_0_1 un22_berr_1 N_132_i_1 N_366 N_120_0_1 \ +# N_335 N_106_i_1 N_208 VPA_c N_103_i_1 N_203 N_92_i_1 N_187 N_140_i_1 N_137 RST_c \ +# N_138_i_1 N_349 N_344_1 pos_clk_un6_bgack_000_n pos_clk_un6_bg_030_1_n N_10 RW_c \ +# N_327_1 N_5 N_319_1 N_293 fc_c_0__n N_285_1 N_6 N_277_1 un1_SM_AMIGA_5 fc_c_1__n N_236_1 \ +# DS_000_ENABLE_1_sqmuxa_1 N_228_1 N_7 N_225_1 pos_clk_un3_as_030_d0_n \ +# AMIGA_BUS_DATA_DIR_c N_224_1 N_290 N_222_1 N_18 N_215_1 DS_000_ENABLE_1_sqmuxa \ +# pos_clk_ipl_1_n N_232 bg_000_0_un3_n N_194 BG_030_c_i bg_000_0_un1_n N_233 \ +# pos_clk_un6_bg_030_i_n bg_000_0_un0_n N_275 pos_clk_un9_bg_030_0_n \ +# uds_000_int_0_un3_n N_153 N_26_i uds_000_int_0_un1_n N_191 N_33_0 \ +# uds_000_int_0_un0_n N_334 N_21_i lds_000_int_0_un3_n N_146 N_38_0 \ +# lds_000_int_0_un1_n N_345 N_17_i lds_000_int_0_un0_n N_346 N_42_0 dsack1_int_0_un3_n \ +# N_163 N_4_i dsack1_int_0_un1_n N_22 N_48_0 dsack1_int_0_un0_n \ +# pos_clk_un4_clk_000_pe_n ipl_c_i_0__n ipl_030_0_2__un3_n cpu_est_2_1__n N_51_0 \ +# ipl_030_0_2__un1_n N_235 ipl_c_i_1__n ipl_030_0_2__un0_n N_284 N_52_0 \ +# ipl_030_0_1__un3_n N_190 ipl_c_i_2__n ipl_030_0_1__un1_n N_337 N_53_0 \ +# ipl_030_0_1__un0_n N_195 N_27_i ipl_030_0_0__un3_n N_340 N_30_0 ipl_030_0_0__un1_n \ +# N_231 N_28_i ipl_030_0_0__un0_n N_230 N_31_0 cpu_est_0_3__un3_n N_280 N_29_i \ +# cpu_est_0_3__un1_n .model bus68030 -.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ +.inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ -DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \ -A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ -A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF \ -A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF \ -A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \ -SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF \ -A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_280.BLIF N_210_0.BLIF \ -cpu_est_0_1__un0_n.BLIF N_279.BLIF N_289_0.BLIF cpu_est_0_2__un3_n.BLIF \ -N_271.BLIF N_218_0.BLIF cpu_est_0_2__un1_n.BLIF N_272.BLIF \ -cpu_est_0_2__un0_n.BLIF N_276.BLIF N_242_i.BLIF cpu_est_0_3__un3_n.BLIF \ -DS_000_ENABLE_1_sqmuxa_1.BLIF N_246_i.BLIF cpu_est_0_3__un1_n.BLIF \ -inst_BGACK_030_INTreg.BLIF N_4.BLIF N_240_i.BLIF cpu_est_0_3__un0_n.BLIF \ -vcc_n_n.BLIF N_5.BLIF N_241_i.BLIF ipl_030_0_0__un3_n.BLIF \ -inst_VMA_INTreg.BLIF N_7.BLIF ipl_030_0_0__un1_n.BLIF gnd_n_n.BLIF N_10.BLIF \ -N_266_i.BLIF ipl_030_0_0__un0_n.BLIF un1_amiga_bus_enable_low.BLIF N_18.BLIF \ -N_267_i.BLIF ipl_030_0_1__un3_n.BLIF un3_size.BLIF N_24.BLIF N_254_i.BLIF \ -ipl_030_0_1__un1_n.BLIF un4_size.BLIF N_6.BLIF N_317_i.BLIF \ -ipl_030_0_1__un0_n.BLIF un4_uds_000.BLIF un1_amiga_bus_enable_low_i.BLIF \ -ipl_030_0_2__un3_n.BLIF un4_lds_000.BLIF un21_fpu_cs_i.BLIF N_313_i.BLIF \ -ipl_030_0_2__un1_n.BLIF un5_ciin.BLIF BGACK_030_INT_i.BLIF N_316_i.BLIF \ -ipl_030_0_2__un0_n.BLIF un4_as_000.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF \ -N_312_i.BLIF a0_dma_0_un3_n.BLIF un21_fpu_cs.BLIF UDS_000_INT_i.BLIF \ -a0_dma_0_un1_n.BLIF un22_berr.BLIF LDS_000_INT_i.BLIF N_347_i.BLIF \ -a0_dma_0_un0_n.BLIF un6_ds_030.BLIF N_236_i.BLIF N_323_i.BLIF \ -uds_000_int_0_un3_n.BLIF cpu_est_2_.BLIF sm_amiga_i_5__n.BLIF N_324_i.BLIF \ -uds_000_int_0_un1_n.BLIF cpu_est_3_.BLIF DS_000_ENABLE_1_sqmuxa_i.BLIF \ -N_222_i.BLIF uds_000_int_0_un0_n.BLIF cpu_est_0_.BLIF N_276_i.BLIF \ -AS_000_DMA_i.BLIF vma_int_0_un3_n.BLIF cpu_est_1_.BLIF RST_i.BLIF N_221_0.BLIF \ -vma_int_0_un1_n.BLIF inst_AS_000_INT.BLIF a_i_19__n.BLIF N_220_0.BLIF \ -vma_int_0_un0_n.BLIF SM_AMIGA_5_.BLIF a_i_18__n.BLIF N_219_0.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ -size_dma_i_1__n.BLIF N_216_0.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF \ -inst_AS_030_D0.BLIF size_dma_i_0__n.BLIF N_290_0.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF inst_nEXP_SPACE_D0reg.BLIF RW_i.BLIF \ -N_212_0.BLIF bg_000_0_un3_n.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_PE_i.BLIF \ -N_211_0.BLIF bg_000_0_un1_n.BLIF inst_BGACK_030_INT_D.BLIF a_i_16__n.BLIF \ -N_204_0.BLIF bg_000_0_un0_n.BLIF inst_AS_000_DMA.BLIF RESET_OUT_i.BLIF \ -N_351_i.BLIF ds_000_dma_0_un3_n.BLIF inst_DS_000_DMA.BLIF BERR_i.BLIF \ -N_353_i.BLIF ds_000_dma_0_un1_n.BLIF CYCLE_DMA_0_.BLIF sm_amiga_i_i_7__n.BLIF \ -N_201_i.BLIF ds_000_dma_0_un0_n.BLIF CYCLE_DMA_1_.BLIF nEXP_SPACE_D0_i.BLIF \ -VMA_INT_i.BLIF as_000_dma_0_un3_n.BLIF SIZE_DMA_0_.BLIF sm_amiga_i_4__n.BLIF \ -N_197_i.BLIF as_000_dma_0_un1_n.BLIF SIZE_DMA_1_.BLIF FPU_SENSE_i.BLIF \ -N_196_i.BLIF as_000_dma_0_un0_n.BLIF inst_VPA_D.BLIF AS_030_i.BLIF \ -N_193_i.BLIF lds_000_int_0_un3_n.BLIF inst_UDS_000_INT.BLIF AS_030_D0_i.BLIF \ -N_192_0.BLIF lds_000_int_0_un1_n.BLIF inst_LDS_000_INT.BLIF a_i_24__n.BLIF \ -clk_000_n_sync_i_10__n.BLIF lds_000_int_0_un0_n.BLIF inst_CLK_OUT_PRE_D.BLIF \ -sm_amiga_i_3__n.BLIF N_350_i.BLIF rw_000_dma_0_un3_n.BLIF inst_DTACK_D0.BLIF \ -cpu_est_i_0__n.BLIF N_188_0.BLIF rw_000_dma_0_un1_n.BLIF inst_RESET_OUT.BLIF \ -cpu_est_i_3__n.BLIF N_187_i.BLIF rw_000_dma_0_un0_n.BLIF \ -inst_CLK_OUT_PRE_50.BLIF cpu_est_i_2__n.BLIF N_185_i.BLIF a_15__n.BLIF \ -CLK_000_D_1_.BLIF cpu_est_i_1__n.BLIF N_182_i.BLIF CLK_000_D_0_.BLIF \ -VPA_D_i.BLIF N_181_i.BLIF a_14__n.BLIF inst_CLK_000_PE.BLIF CLK_000_NE_i.BLIF \ -CLK_OUT_PRE_D_i.BLIF CLK_000_P_SYNC_9_.BLIF sm_amiga_i_1__n.BLIF N_175_0.BLIF \ -a_13__n.BLIF inst_CLK_000_NE.BLIF rst_dly_i_2__n.BLIF N_168_i.BLIF \ -CLK_000_N_SYNC_11_.BLIF CLK_030_i.BLIF AS_030_000_SYNC_i.BLIF a_12__n.BLIF \ -IPL_D0_0_.BLIF rst_dly_i_0__n.BLIF N_158_i.BLIF IPL_D0_1_.BLIF \ -rst_dly_i_1__n.BLIF clk_000_d_i_0__n.BLIF a_11__n.BLIF IPL_D0_2_.BLIF \ -clk_000_d_i_1__n.BLIF N_148_i.BLIF inst_CLK_000_NE_D0.BLIF DTACK_D0_i.BLIF \ -N_345_i.BLIF a_10__n.BLIF pos_clk_un6_bg_030_n.BLIF RW_000_i.BLIF N_344_i.BLIF \ -SM_AMIGA_0_.BLIF CLK_030_H_i.BLIF N_144_0.BLIF a_9__n.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF sm_amiga_i_6__n.BLIF N_138_0.BLIF \ -inst_DSACK1_INTreg.BLIF sm_amiga_i_2__n.BLIF a_8__n.BLIF AS_000_i.BLIF \ -N_342_i.BLIF pos_clk_ipl_n.BLIF sm_amiga_i_0__n.BLIF N_343_i.BLIF a_7__n.BLIF \ -SM_AMIGA_4_.BLIF A1_i.BLIF N_124_0.BLIF inst_DS_000_ENABLE.BLIF a_i_31__n.BLIF \ -N_341_i.BLIF a_6__n.BLIF RST_DLY_0_.BLIF a_i_29__n.BLIF N_119_0.BLIF \ -RST_DLY_1_.BLIF a_i_30__n.BLIF N_340_i.BLIF a_5__n.BLIF RST_DLY_2_.BLIF \ -a_i_27__n.BLIF N_361_i.BLIF pos_clk_un9_bg_030_n.BLIF a_i_28__n.BLIF \ -cpu_est_2_0_2__n.BLIF a_4__n.BLIF CLK_000_P_SYNC_0_.BLIF a_i_25__n.BLIF \ -N_338_i.BLIF CLK_000_P_SYNC_1_.BLIF a_i_26__n.BLIF N_339_i.BLIF a_3__n.BLIF \ -CLK_000_P_SYNC_2_.BLIF N_213_i.BLIF cpu_est_2_0_1__n.BLIF \ -CLK_000_P_SYNC_3_.BLIF N_214_i.BLIF N_332_i.BLIF a_2__n.BLIF \ -CLK_000_P_SYNC_4_.BLIF N_215_i.BLIF N_336_i.BLIF CLK_000_P_SYNC_5_.BLIF \ -pos_clk_un7_clk_000_pe_0_n.BLIF CLK_000_P_SYNC_6_.BLIF N_275_i.BLIF \ -N_99_0.BLIF CLK_000_P_SYNC_7_.BLIF un6_ds_030_i.BLIF N_331_i.BLIF \ -CLK_000_P_SYNC_8_.BLIF DS_000_DMA_i.BLIF N_96_0.BLIF CLK_000_N_SYNC_0_.BLIF \ -un4_as_000_i.BLIF N_330_i.BLIF CLK_000_N_SYNC_1_.BLIF AS_000_INT_i.BLIF \ -N_90_0.BLIF CLK_000_N_SYNC_2_.BLIF un4_lds_000_i.BLIF N_328_i.BLIF \ -CLK_000_N_SYNC_3_.BLIF un4_uds_000_i.BLIF CLK_000_N_SYNC_4_.BLIF AS_030_c.BLIF \ -N_80_0.BLIF CLK_000_N_SYNC_5_.BLIF N_325_i.BLIF CLK_000_N_SYNC_6_.BLIF \ -AS_000_c.BLIF N_326_i.BLIF CLK_000_N_SYNC_7_.BLIF N_258_0.BLIF \ -CLK_000_N_SYNC_8_.BLIF RW_000_c.BLIF N_217_i.BLIF CLK_000_N_SYNC_9_.BLIF \ -N_321_i.BLIF CLK_000_N_SYNC_10_.BLIF N_322_i.BLIF inst_RW_000_INT.BLIF \ -UDS_000_c.BLIF inst_RW_000_DMA.BLIF N_320_i.BLIF pos_clk_un7_clk_000_pe_n.BLIF \ -LDS_000_c.BLIF inst_A0_DMA.BLIF un5_ciin_i.BLIF pos_clk_a0_dma_3_n.BLIF \ -size_c_0__n.BLIF N_61_0.BLIF SM_AMIGA_6_.BLIF N_310_i.BLIF inst_CLK_030_H.BLIF \ -size_c_1__n.BLIF SM_AMIGA_1_.BLIF N_305_i.BLIF SM_AMIGA_3_.BLIF N_307_i.BLIF \ -SM_AMIGA_2_.BLIF N_3.BLIF N_303_i.BLIF N_8.BLIF N_304_i.BLIF N_283_0.BLIF \ -N_301_i.BLIF N_300_i.BLIF N_123_0.BLIF N_17.BLIF N_278_i.BLIF N_19.BLIF \ -N_297_i.BLIF N_20.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_21.BLIF N_277_i.BLIF \ -N_22.BLIF N_25.BLIF N_26.BLIF pos_clk_un8_sm_amiga_i_n.BLIF N_27.BLIF \ -A0_c_i.BLIF N_28.BLIF size_c_i_1__n.BLIF N_29.BLIF N_29_i.BLIF N_32_0.BLIF \ -N_28_i.BLIF N_31_0.BLIF N_27_i.BLIF N_30_0.BLIF ipl_c_i_2__n.BLIF N_53_0.BLIF \ -ipl_c_i_1__n.BLIF N_52_0.BLIF a_c_16__n.BLIF ipl_c_i_0__n.BLIF N_51_0.BLIF \ -a_c_17__n.BLIF DTACK_c_i.BLIF N_56_0.BLIF a_c_18__n.BLIF VPA_c_i.BLIF \ -N_55_0.BLIF a_c_19__n.BLIF nEXP_SPACE_c_i.BLIF N_54_0.BLIF a_c_20__n.BLIF \ -N_3_i.BLIF N_49_0.BLIF a_c_21__n.BLIF N_8_i.BLIF N_45_0.BLIF a_c_22__n.BLIF \ -N_17_i.BLIF N_42_0.BLIF a_c_23__n.BLIF N_19_i.BLIF N_40_0.BLIF \ -SM_AMIGA_i_7_.BLIF a_c_24__n.BLIF N_20_i.BLIF N_123.BLIF N_39_0.BLIF \ -cpu_est_2_1__n.BLIF a_c_25__n.BLIF N_21_i.BLIF cpu_est_2_2__n.BLIF N_38_0.BLIF \ -N_209.BLIF a_c_26__n.BLIF N_22_i.BLIF G_134.BLIF N_37_0.BLIF G_135.BLIF \ -a_c_27__n.BLIF N_25_i.BLIF G_136.BLIF N_34_0.BLIF N_217.BLIF a_c_28__n.BLIF \ -N_26_i.BLIF N_33_0.BLIF N_61.BLIF a_c_29__n.BLIF BG_030_c_i.BLIF N_127.BLIF \ -pos_clk_un6_bg_030_i_n.BLIF a_c_30__n.BLIF pos_clk_un9_bg_030_0_n.BLIF \ -N_80.BLIF N_289_0_1.BLIF a_c_31__n.BLIF un1_SM_AMIGA_5_i_1.BLIF N_90.BLIF \ -un1_SM_AMIGA_5_i_2.BLIF N_96.BLIF A0_c.BLIF pos_clk_un8_sm_amiga_i_1_n.BLIF \ -N_99.BLIF N_351_1.BLIF N_119.BLIF A1_c.BLIF N_351_2.BLIF N_124.BLIF \ -N_168_i_1.BLIF N_138.BLIF nEXP_SPACE_c.BLIF N_192_0_1.BLIF N_144.BLIF \ -N_192_0_2.BLIF N_158.BLIF BERR_c.BLIF N_137_i_1.BLIF N_168.BLIF N_137_i_2.BLIF \ -N_175.BLIF BG_030_c.BLIF N_145_i_1.BLIF N_182.BLIF N_145_i_2.BLIF N_185.BLIF \ -BG_000DFFreg.BLIF N_145_i_3.BLIF N_187.BLIF N_260_i_1.BLIF N_188.BLIF \ -N_260_i_2.BLIF N_192.BLIF BGACK_000_c.BLIF N_259_i_1.BLIF N_193.BLIF \ -N_259_i_2.BLIF N_197.BLIF CLK_030_c.BLIF N_336_1.BLIF N_201.BLIF N_336_2.BLIF \ -N_204.BLIF N_332_1.BLIF N_206.BLIF N_332_2.BLIF N_207.BLIF CLK_OSZI_c.BLIF \ -N_332_3.BLIF N_317_1.BLIF N_211.BLIF N_317_2.BLIF N_212.BLIF \ -CLK_OUT_INTreg.BLIF N_317_3.BLIF N_290.BLIF N_304_1.BLIF N_216.BLIF \ -N_304_2.BLIF N_219.BLIF FPU_SENSE_c.BLIF un5_ciin_1.BLIF N_220.BLIF \ -un5_ciin_2.BLIF N_221.BLIF IPL_030DFF_0_reg.BLIF un5_ciin_3.BLIF N_227.BLIF \ -un5_ciin_4.BLIF N_229.BLIF IPL_030DFF_1_reg.BLIF un5_ciin_5.BLIF N_230.BLIF \ -un5_ciin_6.BLIF N_236.BLIF IPL_030DFF_2_reg.BLIF un5_ciin_7.BLIF N_240.BLIF \ -un5_ciin_8.BLIF N_241.BLIF ipl_c_0__n.BLIF un5_ciin_9.BLIF N_242.BLIF \ -un5_ciin_10.BLIF N_246.BLIF ipl_c_1__n.BLIF un5_ciin_11.BLIF N_254.BLIF \ -un22_berr_1_0.BLIF N_266.BLIF ipl_c_2__n.BLIF un21_fpu_cs_1.BLIF N_267.BLIF \ -N_375_1.BLIF N_275.BLIF N_375_2.BLIF N_277.BLIF DTACK_c.BLIF N_375_3.BLIF \ -N_278.BLIF N_375_4.BLIF N_297.BLIF N_134_i_1.BLIF N_300.BLIF N_96_0_1.BLIF \ -N_301.BLIF VPA_c.BLIF N_83_i_1.BLIF N_303.BLIF N_261_i_1.BLIF N_304.BLIF \ -N_141_i_1.BLIF N_305.BLIF RST_c.BLIF N_139_i_1.BLIF N_307.BLIF N_133_i_1.BLIF \ -N_310.BLIF N_123_0_1.BLIF N_312.BLIF RW_c.BLIF N_282_i_1.BLIF N_313.BLIF \ -N_343_1.BLIF N_316.BLIF fc_c_0__n.BLIF N_339_1.BLIF N_317.BLIF \ -pos_clk_un6_bg_030_1_n.BLIF N_320.BLIF fc_c_1__n.BLIF N_326_1.BLIF N_321.BLIF \ -N_325_1.BLIF N_322.BLIF N_324_1.BLIF N_323.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ -N_316_1.BLIF N_324.BLIF N_313_1.BLIF N_325.BLIF N_303_1.BLIF N_326.BLIF \ -N_297_1.BLIF N_328.BLIF N_266_1.BLIF N_330.BLIF N_24_i.BLIF N_240_1.BLIF \ -N_331.BLIF N_35_0.BLIF pos_clk_ipl_1_n.BLIF N_332.BLIF N_18_i.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF N_336.BLIF N_41_0.BLIF \ -amiga_bus_enable_dma_low_0_un1_n.BLIF N_338.BLIF N_10_i.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_339.BLIF N_43_0.BLIF \ -rw_000_int_0_un3_n.BLIF N_340.BLIF N_7_i.BLIF rw_000_int_0_un1_n.BLIF \ -N_341.BLIF N_46_0.BLIF rw_000_int_0_un0_n.BLIF N_342.BLIF N_5_i.BLIF \ -bgack_030_int_0_un3_n.BLIF N_343.BLIF N_47_0.BLIF bgack_030_int_0_un1_n.BLIF \ -N_344.BLIF N_4_i.BLIF bgack_030_int_0_un0_n.BLIF N_345.BLIF N_48_0.BLIF \ -as_030_000_sync_0_un3_n.BLIF N_347.BLIF N_272_i.BLIF \ -as_030_000_sync_0_un1_n.BLIF N_350.BLIF N_271_i.BLIF \ -as_030_000_sync_0_un0_n.BLIF N_351.BLIF N_279_0.BLIF \ -ds_000_enable_0_un3_n.BLIF N_353.BLIF N_280_0.BLIF ds_000_enable_0_un1_n.BLIF \ -N_361.BLIF N_281_0.BLIF ds_000_enable_0_un0_n.BLIF \ -pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_298_i.BLIF \ -as_000_int_0_un3_n.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF \ -pos_clk_size_dma_6_0_0__n.BLIF as_000_int_0_un1_n.BLIF cpu_est_0_0_x2_0_.BLIF \ -N_299_i.BLIF as_000_int_0_un0_n.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF \ -pos_clk_size_dma_6_0_1__n.BLIF dsack1_int_0_un3_n.BLIF un22_berr_1.BLIF \ -un1_as_000_i.BLIF dsack1_int_0_un1_n.BLIF N_375.BLIF N_358_i.BLIF \ -dsack1_int_0_un0_n.BLIF N_218.BLIF pos_clk_un6_bgack_000_0_n.BLIF \ -size_dma_0_1__un3_n.BLIF N_156.BLIF N_284_i.BLIF size_dma_0_1__un1_n.BLIF \ -N_289.BLIF N_285_i.BLIF size_dma_0_1__un0_n.BLIF N_354.BLIF N_286_0.BLIF \ -size_dma_0_0__un3_n.BLIF N_205.BLIF N_88_0.BLIF size_dma_0_0__un1_n.BLIF \ -un1_SM_AMIGA_5.BLIF pos_clk_un3_as_030_d0_i_n.BLIF size_dma_0_0__un0_n.BLIF \ -DS_000_ENABLE_1_sqmuxa.BLIF N_156_i.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF \ -N_349.BLIF N_349_i.BLIF sm_amiga_srsts_i_0_m2_1__un1_n.BLIF \ -pos_clk_un3_as_030_d0_n.BLIF N_194_i.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF \ -N_286.BLIF un1_SM_AMIGA_5_i.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF pos_clk_un6_bgack_000_n.BLIF \ -UDS_000_c_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF N_358.BLIF \ -LDS_000_c_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF \ -pos_clk_size_dma_6_1__n.BLIF N_205_i.BLIF sm_amiga_srsts_i_0_m2_5__un3_n.BLIF \ -N_299.BLIF N_206_0.BLIF sm_amiga_srsts_i_0_m2_5__un1_n.BLIF \ -pos_clk_size_dma_6_0__n.BLIF N_207_0.BLIF sm_amiga_srsts_i_0_m2_5__un0_n.BLIF \ -N_298.BLIF N_354_i.BLIF cpu_est_0_1__un3_n.BLIF N_281.BLIF N_208_0.BLIF \ -cpu_est_0_1__un1_n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \ -UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ -A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF +DTACK.BLIF VPA.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \ +A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF A_DECODE_17_.BLIF \ +A_DECODE_16_.BLIF A_DECODE_15_.BLIF A_DECODE_14_.BLIF A_DECODE_13_.BLIF \ +A_DECODE_12_.BLIF A_DECODE_11_.BLIF A_DECODE_10_.BLIF A_DECODE_9_.BLIF \ +A_DECODE_8_.BLIF A_DECODE_7_.BLIF A_DECODE_6_.BLIF A_DECODE_5_.BLIF \ +A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ +FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF \ +RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF \ +AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF \ +AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_166.BLIF N_32_0.BLIF \ +cpu_est_0_3__un0_n.BLIF N_141.BLIF a_c_i_0__n.BLIF cpu_est_0_2__un3_n.BLIF \ +N_226.BLIF size_c_i_1__n.BLIF cpu_est_0_2__un1_n.BLIF N_357.BLIF \ +pos_clk_un10_sm_amiga_i_n.BLIF cpu_est_0_2__un0_n.BLIF N_219.BLIF N_258_0.BLIF \ +sm_amiga_srsts_i_0_m2_1__un3_n.BLIF N_217.BLIF N_357_i.BLIF \ +sm_amiga_srsts_i_0_m2_1__un1_n.BLIF N_221.BLIF N_254_i.BLIF \ +sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_220.BLIF cpu_est_2_0_2__n.BLIF \ +vma_int_0_un3_n.BLIF inst_BGACK_030_INTreg.BLIF N_223.BLIF N_315_i.BLIF \ +vma_int_0_un1_n.BLIF vcc_n_n.BLIF N_343.BLIF N_291_0.BLIF vma_int_0_un0_n.BLIF \ +inst_VMA_INTreg.BLIF N_192.BLIF AS_030_000_SYNC_i.BLIF cpu_est_0_1__un3_n.BLIF \ +gnd_n_n.BLIF N_164.BLIF N_146_0.BLIF cpu_est_0_1__un1_n.BLIF \ +un1_amiga_bus_enable_dma_high_0__n.BLIF N_291.BLIF N_149_i.BLIF \ +cpu_est_0_1__un0_n.BLIF un1_amiga_bus_enable_low.BLIF N_315.BLIF N_164_i.BLIF \ +sm_amiga_srsts_i_0_0_m2_5__un3_n.BLIF un6_as_030.BLIF cpu_est_2_2__n.BLIF \ +N_166_i.BLIF sm_amiga_srsts_i_0_0_m2_5__un1_n.BLIF un3_size.BLIF N_254.BLIF \ +N_172_i.BLIF sm_amiga_srsts_i_0_0_m2_5__un0_n.BLIF un4_size.BLIF N_258.BLIF \ +N_176_i.BLIF rw_000_int_0_un3_n.BLIF un4_uds_000.BLIF N_29.BLIF N_186_0.BLIF \ +rw_000_int_0_un1_n.BLIF un4_lds_000.BLIF N_28.BLIF N_192_0.BLIF \ +rw_000_int_0_un0_n.BLIF un4_as_000.BLIF N_27.BLIF N_228_i.BLIF \ +bgack_030_int_0_un3_n.BLIF un10_ciin.BLIF N_4.BLIF N_227_i.BLIF \ +bgack_030_int_0_un1_n.BLIF un21_fpu_cs.BLIF N_17.BLIF N_343_i.BLIF \ +bgack_030_int_0_un0_n.BLIF un22_berr.BLIF N_21.BLIF as_000_int_0_un3_n.BLIF \ +un6_ds_030.BLIF N_26.BLIF N_223_i.BLIF as_000_int_0_un1_n.BLIF cpu_est_2_.BLIF \ +pos_clk_un9_bg_030_n.BLIF N_225_i.BLIF as_000_int_0_un0_n.BLIF cpu_est_3_.BLIF \ +un1_amiga_bus_enable_low_i.BLIF N_224_i.BLIF ds_000_enable_0_un3_n.BLIF \ +cpu_est_0_.BLIF un21_fpu_cs_i.BLIF N_226_i.BLIF ds_000_enable_0_un1_n.BLIF \ +cpu_est_1_.BLIF N_275_i.BLIF ds_000_enable_0_un0_n.BLIF inst_AS_000_INT.BLIF \ +clk_000_n_sync_i_12__n.BLIF N_220_i.BLIF as_030_000_sync_0_un3_n.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF rst_dly_i_2__n.BLIF N_221_i.BLIF \ +as_030_000_sync_0_un1_n.BLIF inst_AS_030_D0.BLIF rst_dly_i_1__n.BLIF \ +N_222_i.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF \ +BERR_i.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF \ +inst_BGACK_030_INT_D.BLIF cpu_est_i_2__n.BLIF N_217_i.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF inst_AS_000_DMA.BLIF \ +nEXP_SPACE_i.BLIF N_215_i.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF inst_DS_000_DMA.BLIF \ +rst_dly_i_0__n.BLIF N_219_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF \ +CYCLE_DMA_0_.BLIF cpu_est_i_1__n.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF \ +CYCLE_DMA_1_.BLIF cpu_est_i_0__n.BLIF N_200_i.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF SIZE_DMA_0_.BLIF VPA_D_i.BLIF \ +N_195_0.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF SIZE_DMA_1_.BLIF \ +sm_amiga_i_3__n.BLIF N_190_0.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF \ +inst_VPA_D.BLIF sm_amiga_i_0__n.BLIF N_157_i.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF inst_UDS_000_INT.BLIF \ +cpu_est_i_3__n.BLIF N_154_i.BLIF size_dma_0_0__un3_n.BLIF \ +inst_LDS_000_INT.BLIF sm_amiga_i_1__n.BLIF N_340_i.BLIF \ +size_dma_0_0__un1_n.BLIF inst_CLK_OUT_PRE_D.BLIF RESET_OUT_i.BLIF N_141_0.BLIF \ +size_dma_0_0__un0_n.BLIF CLK_000_D_10_.BLIF BGACK_030_INT_i.BLIF \ +un3_as_030_i.BLIF size_dma_0_1__un3_n.BLIF CLK_000_D_11_.BLIF \ +sm_amiga_i_2__n.BLIF N_216_i.BLIF size_dma_0_1__un1_n.BLIF inst_DTACK_D0.BLIF \ +sm_amiga_i_4__n.BLIF N_337_i.BLIF size_dma_0_1__un0_n.BLIF inst_RESET_OUT.BLIF \ +clk_000_p_sync_i_10__n.BLIF ds_000_dma_0_un3_n.BLIF inst_CLK_OUT_PRE_50.BLIF \ +sm_amiga_i_5__n.BLIF un10_ciin_i.BLIF ds_000_dma_0_un1_n.BLIF \ +CLK_000_D_1_.BLIF sm_amiga_i_i_7__n.BLIF N_296_0.BLIF ds_000_dma_0_un0_n.BLIF \ +CLK_000_D_0_.BLIF clk_000_d_i_11__n.BLIF un1_as_000_i.BLIF \ +as_000_dma_0_un3_n.BLIF CLK_000_P_SYNC_10_.BLIF sm_amiga_i_6__n.BLIF \ +N_284_i.BLIF as_000_dma_0_un1_n.BLIF SM_AMIGA_5_.BLIF RW_i.BLIF N_285_i.BLIF \ +as_000_dma_0_un0_n.BLIF IPL_D0_0_.BLIF DS_000_ENABLE_1_sqmuxa_i.BLIF \ +N_292_0.BLIF rw_000_dma_0_un3_n.BLIF IPL_D0_1_.BLIF LDS_000_INT_i.BLIF \ +N_280_i.BLIF rw_000_dma_0_un1_n.BLIF IPL_D0_2_.BLIF UDS_000_INT_i.BLIF \ +N_277_i.BLIF rw_000_dma_0_un0_n.BLIF CLK_000_D_2_.BLIF AS_030_i.BLIF \ +N_257_0.BLIF a0_dma_0_un3_n.BLIF CLK_000_D_3_.BLIF AS_000_INT_i.BLIF \ +N_235_i.BLIF a0_dma_0_un1_n.BLIF CLK_000_D_4_.BLIF a_decode_i_19__n.BLIF \ +N_236_i.BLIF a0_dma_0_un0_n.BLIF CLK_000_D_5_.BLIF a_decode_i_18__n.BLIF \ +cpu_est_2_0_1__n.BLIF a_decode_15__n.BLIF CLK_000_D_6_.BLIF \ +a_decode_i_16__n.BLIF N_231_i.BLIF CLK_000_D_7_.BLIF AS_000_i.BLIF \ +N_230_i.BLIF a_decode_14__n.BLIF CLK_000_D_8_.BLIF FPU_SENSE_i.BLIF \ +pos_clk_un4_clk_000_pe_0_n.BLIF CLK_000_D_9_.BLIF \ +AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_22_i.BLIF a_decode_13__n.BLIF \ +CLK_000_D_12_.BLIF CLK_030_i.BLIF N_37_0.BLIF pos_clk_un6_bg_030_n.BLIF \ +DTACK_D0_i.BLIF a_decode_12__n.BLIF SM_AMIGA_0_.BLIF clk_000_d_i_10__n.BLIF \ +N_334_i.BLIF inst_DSACK1_INTreg.BLIF RW_000_i.BLIF N_335_i.BLIF \ +a_decode_11__n.BLIF a_i_1__n.BLIF N_194_0.BLIF CLK_030_H_i.BLIF N_191_0.BLIF \ +a_decode_10__n.BLIF pos_clk_ipl_n.BLIF AS_000_DMA_i.BLIF un1_SM_AMIGA_5_i.BLIF \ +CLK_000_N_SYNC_0_.BLIF clk_000_d_i_0__n.BLIF N_346_i.BLIF a_decode_9__n.BLIF \ +SM_AMIGA_4_.BLIF clk_000_d_i_1__n.BLIF N_163_i.BLIF inst_DS_000_ENABLE.BLIF \ +AS_030_D0_i.BLIF N_345_i.BLIF a_decode_8__n.BLIF CLK_000_N_SYNC_12_.BLIF \ +size_dma_i_0__n.BLIF N_344_i.BLIF RST_DLY_0_.BLIF size_dma_i_1__n.BLIF \ +N_153_0.BLIF a_decode_7__n.BLIF RST_DLY_1_.BLIF ahigh_i_30__n.BLIF \ +pos_clk_un3_as_030_d0_i_n.BLIF RST_DLY_2_.BLIF ahigh_i_31__n.BLIF N_293_0.BLIF \ +a_decode_6__n.BLIF CLK_000_P_SYNC_0_.BLIF ahigh_i_28__n.BLIF N_233_i.BLIF \ +CLK_000_P_SYNC_1_.BLIF ahigh_i_29__n.BLIF N_232_i.BLIF a_decode_5__n.BLIF \ +CLK_000_P_SYNC_2_.BLIF ahigh_i_26__n.BLIF N_290_0.BLIF CLK_000_P_SYNC_3_.BLIF \ +ahigh_i_27__n.BLIF VPA_c_i.BLIF a_decode_4__n.BLIF CLK_000_P_SYNC_4_.BLIF \ +ahigh_i_24__n.BLIF N_54_0.BLIF CLK_000_P_SYNC_5_.BLIF ahigh_i_25__n.BLIF \ +N_5_i.BLIF a_decode_3__n.BLIF CLK_000_P_SYNC_6_.BLIF N_212_i.BLIF N_47_0.BLIF \ +CLK_000_P_SYNC_7_.BLIF N_213_i.BLIF N_7_i.BLIF a_decode_2__n.BLIF \ +CLK_000_P_SYNC_8_.BLIF N_214_i.BLIF N_46_0.BLIF CLK_000_P_SYNC_9_.BLIF \ +N_18_i.BLIF CLK_000_N_SYNC_1_.BLIF N_41_0.BLIF CLK_000_N_SYNC_2_.BLIF \ +N_321_i.BLIF N_10_i.BLIF CLK_000_N_SYNC_3_.BLIF N_322_i.BLIF N_43_0.BLIF \ +CLK_000_N_SYNC_4_.BLIF un6_ds_030_i.BLIF DTACK_c_i.BLIF CLK_000_N_SYNC_5_.BLIF \ +DS_000_DMA_i.BLIF N_55_0.BLIF CLK_000_N_SYNC_6_.BLIF un4_as_000_i.BLIF \ +pos_clk_un6_bgack_000_0_n.BLIF CLK_000_N_SYNC_7_.BLIF un6_as_030_i.BLIF \ +N_137_i.BLIF CLK_000_N_SYNC_8_.BLIF un4_lds_000_i.BLIF N_184_0.BLIF \ +CLK_000_N_SYNC_9_.BLIF un4_uds_000_i.BLIF N_349_i.BLIF CLK_000_N_SYNC_10_.BLIF \ +AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_185_i.BLIF CLK_000_N_SYNC_11_.BLIF \ +AS_030_c.BLIF N_187_0.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF N_203_i.BLIF \ +inst_RW_000_INT.BLIF AS_000_c.BLIF N_324_i.BLIF inst_RW_000_DMA.BLIF \ +inst_CLK_000_NE_D0.BLIF RW_000_c.BLIF N_199_0.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_197_0.BLIF inst_A0_DMA.BLIF N_196_0.BLIF \ +pos_clk_a0_dma_3_n.BLIF UDS_000_c.BLIF LDS_000_c_i.BLIF SM_AMIGA_6_.BLIF \ +UDS_000_c_i.BLIF inst_CLK_030_H.BLIF LDS_000_c.BLIF N_181_i.BLIF \ +SM_AMIGA_1_.BLIF N_347_i.BLIF SM_AMIGA_3_.BLIF size_c_0__n.BLIF N_348_i.BLIF \ +SM_AMIGA_2_.BLIF N_178_i.BLIF pos_clk_ds_000_dma_4_n.BLIF size_c_1__n.BLIF \ +VMA_INT_i.BLIF N_3.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_8.BLIF \ +ahigh_c_24__n.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF \ +CLK_OUT_PRE_D_i.BLIF ahigh_c_25__n.BLIF N_148_0.BLIF N_341_i.BLIF \ +ahigh_c_26__n.BLIF N_338_i.BLIF N_339_i.BLIF N_19.BLIF ahigh_c_27__n.BLIF \ +N_20.BLIF N_336_i.BLIF N_24.BLIF ahigh_c_28__n.BLIF N_122_0.BLIF N_25.BLIF \ +N_211_i.BLIF ahigh_c_29__n.BLIF N_332_i.BLIF ahigh_c_30__n.BLIF N_331_i.BLIF \ +N_120_0.BLIF ahigh_c_31__n.BLIF N_330_i.BLIF pos_clk_ds_000_dma_4_0_n.BLIF \ +N_329_i.BLIF pos_clk_size_dma_6_0_1__n.BLIF N_328_i.BLIF \ +pos_clk_size_dma_6_0_0__n.BLIF N_325_i.BLIF N_327_i.BLIF \ +AMIGA_BUS_DATA_DIR_c_0.BLIF N_320_i.BLIF N_298_0.BLIF N_295_0.BLIF \ +N_294_0.BLIF N_319_i.BLIF un1_amiga_bus_enable_dma_high_0_0__n.BLIF \ +N_206_i.BLIF N_283_i.BLIF SM_AMIGA_i_7_.BLIF N_122.BLIF N_281_i.BLIF \ +pos_clk_size_dma_6_0__n.BLIF N_282_i.BLIF pos_clk_size_dma_6_1__n.BLIF \ +G_134.BLIF N_3_i.BLIF G_135.BLIF N_49_0.BLIF G_136.BLIF N_8_i.BLIF N_45_0.BLIF \ +pos_clk_un23_bgack_030_int_i_1_n.BLIF N_19_i.BLIF N_292.BLIF N_40_0.BLIF \ +N_294.BLIF a_decode_c_16__n.BLIF N_20_i.BLIF N_295.BLIF N_39_0.BLIF N_296.BLIF \ +a_decode_c_17__n.BLIF N_24_i.BLIF N_298.BLIF N_35_0.BLIF N_120.BLIF \ +a_decode_c_18__n.BLIF N_25_i.BLIF N_148.BLIF N_34_0.BLIF N_149.BLIF \ +a_decode_c_19__n.BLIF N_194_0_1.BLIF N_157.BLIF N_237_i_1.BLIF N_172.BLIF \ +a_decode_c_20__n.BLIF N_237_i_2.BLIF N_176.BLIF N_238_i_1.BLIF N_178.BLIF \ +a_decode_c_21__n.BLIF N_238_i_2.BLIF N_181.BLIF N_144_i_1.BLIF N_184.BLIF \ +a_decode_c_22__n.BLIF N_144_i_2.BLIF N_144_i_3.BLIF N_196.BLIF \ +a_decode_c_23__n.BLIF N_136_i_1.BLIF N_197.BLIF N_136_i_2.BLIF N_206.BLIF \ +a_c_0__n.BLIF N_176_i_1.BLIF N_207.BLIF N_146_0_1.BLIF N_211.BLIF \ +a_c_1__n.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF N_215.BLIF un10_ciin_1.BLIF \ +N_222.BLIF nEXP_SPACE_c.BLIF un10_ciin_2.BLIF N_224.BLIF un10_ciin_3.BLIF \ +N_225.BLIF BERR_c.BLIF un10_ciin_4.BLIF N_227.BLIF un10_ciin_5.BLIF N_228.BLIF \ +BG_030_c.BLIF un10_ciin_6.BLIF N_236.BLIF un10_ciin_7.BLIF N_277.BLIF \ +BG_000DFFreg.BLIF un10_ciin_8.BLIF N_281.BLIF un10_ciin_9.BLIF N_282.BLIF \ +un10_ciin_10.BLIF N_283.BLIF BGACK_000_c.BLIF un10_ciin_11.BLIF N_285.BLIF \ +N_347_1.BLIF N_318.BLIF CLK_030_c.BLIF N_347_2.BLIF N_319.BLIF \ +pos_clk_un23_bgack_030_int_i_1_0_1_n.BLIF N_320.BLIF CLK_000_c.BLIF \ +pos_clk_un23_bgack_030_int_i_1_0_2_n.BLIF N_321.BLIF un21_fpu_cs_1.BLIF \ +N_322.BLIF CLK_OSZI_c.BLIF un22_berr_1_0.BLIF N_323.BLIF N_366_1.BLIF \ +N_325.BLIF N_366_2.BLIF N_327.BLIF CLK_OUT_INTreg.BLIF N_366_3.BLIF N_328.BLIF \ +N_366_4.BLIF N_329.BLIF un1_SM_AMIGA_5_i_1.BLIF N_330.BLIF FPU_SENSE_c.BLIF \ +un1_SM_AMIGA_5_i_2.BLIF N_331.BLIF N_142_i_1.BLIF N_332.BLIF \ +IPL_030DFF_0_reg.BLIF N_142_i_2.BLIF N_336.BLIF N_339_1.BLIF N_338.BLIF \ +IPL_030DFF_1_reg.BLIF N_280_1.BLIF N_339.BLIF N_280_2.BLIF N_341.BLIF \ +IPL_030DFF_2_reg.BLIF N_231_1.BLIF N_344.BLIF N_231_2.BLIF N_347.BLIF \ +ipl_c_0__n.BLIF N_230_1.BLIF N_348.BLIF N_230_2.BLIF \ +pos_clk_un23_bgack_030_int_i_0_x2.BLIF ipl_c_1__n.BLIF N_230_3.BLIF \ +cpu_est_0_0_x2_0_x2_0_.BLIF N_226_1.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF \ +ipl_c_2__n.BLIF N_226_2.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_226_3.BLIF \ +N_199.BLIF N_239_i_1.BLIF N_324.BLIF DTACK_c.BLIF N_122_0_1.BLIF \ +un22_berr_1.BLIF N_132_i_1.BLIF N_366.BLIF N_120_0_1.BLIF N_335.BLIF \ +N_106_i_1.BLIF N_208.BLIF VPA_c.BLIF N_103_i_1.BLIF N_203.BLIF N_92_i_1.BLIF \ +N_187.BLIF N_140_i_1.BLIF N_137.BLIF RST_c.BLIF N_138_i_1.BLIF N_349.BLIF \ +N_344_1.BLIF pos_clk_un6_bgack_000_n.BLIF pos_clk_un6_bg_030_1_n.BLIF \ +N_10.BLIF RW_c.BLIF N_327_1.BLIF N_5.BLIF N_319_1.BLIF N_293.BLIF \ +fc_c_0__n.BLIF N_285_1.BLIF N_6.BLIF N_277_1.BLIF un1_SM_AMIGA_5.BLIF \ +fc_c_1__n.BLIF N_236_1.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF N_228_1.BLIF \ +N_7.BLIF N_225_1.BLIF pos_clk_un3_as_030_d0_n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ +N_224_1.BLIF N_290.BLIF N_222_1.BLIF N_18.BLIF N_215_1.BLIF \ +DS_000_ENABLE_1_sqmuxa.BLIF pos_clk_ipl_1_n.BLIF N_232.BLIF \ +bg_000_0_un3_n.BLIF N_194.BLIF BG_030_c_i.BLIF bg_000_0_un1_n.BLIF N_233.BLIF \ +pos_clk_un6_bg_030_i_n.BLIF bg_000_0_un0_n.BLIF N_275.BLIF \ +pos_clk_un9_bg_030_0_n.BLIF uds_000_int_0_un3_n.BLIF N_153.BLIF N_26_i.BLIF \ +uds_000_int_0_un1_n.BLIF N_191.BLIF N_33_0.BLIF uds_000_int_0_un0_n.BLIF \ +N_334.BLIF N_21_i.BLIF lds_000_int_0_un3_n.BLIF N_146.BLIF N_38_0.BLIF \ +lds_000_int_0_un1_n.BLIF N_345.BLIF N_17_i.BLIF lds_000_int_0_un0_n.BLIF \ +N_346.BLIF N_42_0.BLIF dsack1_int_0_un3_n.BLIF N_163.BLIF N_4_i.BLIF \ +dsack1_int_0_un1_n.BLIF N_22.BLIF N_48_0.BLIF dsack1_int_0_un0_n.BLIF \ +pos_clk_un4_clk_000_pe_n.BLIF ipl_c_i_0__n.BLIF ipl_030_0_2__un3_n.BLIF \ +cpu_est_2_1__n.BLIF N_51_0.BLIF ipl_030_0_2__un1_n.BLIF N_235.BLIF \ +ipl_c_i_1__n.BLIF ipl_030_0_2__un0_n.BLIF N_284.BLIF N_52_0.BLIF \ +ipl_030_0_1__un3_n.BLIF N_190.BLIF ipl_c_i_2__n.BLIF ipl_030_0_1__un1_n.BLIF \ +N_337.BLIF N_53_0.BLIF ipl_030_0_1__un0_n.BLIF N_195.BLIF N_27_i.BLIF \ +ipl_030_0_0__un3_n.BLIF N_340.BLIF N_30_0.BLIF ipl_030_0_0__un1_n.BLIF \ +N_231.BLIF N_28_i.BLIF ipl_030_0_0__un0_n.BLIF N_230.BLIF N_31_0.BLIF \ +cpu_est_0_3__un3_n.BLIF N_280.BLIF N_29_i.BLIF cpu_est_0_3__un1_n.BLIF \ +AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF \ +LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF \ +AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF \ +AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF \ +BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ -SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D \ -SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \ +SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \ +SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D \ +SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \ +cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D \ IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ -IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ -SM_AMIGA_5_.D SM_AMIGA_5_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \ -CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ +IPL_D0_2_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D \ +CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C \ +CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \ +CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C \ +CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ -SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \ -cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C \ -CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D \ -CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \ -CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D \ -CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C \ -CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D \ -CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C \ -CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \ -CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \ -CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \ -CLK_000_N_SYNC_9_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ -CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \ -CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \ -CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C \ -CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D \ -CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_INT.D \ -inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \ -inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \ -inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ -inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D \ -inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ +SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ +CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D \ +CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C \ +CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ +CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \ +CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \ +CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_10_.D CLK_000_P_SYNC_10_.C \ +CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D \ +CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C \ +CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D \ +CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_D_0_.D \ +CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C \ +CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D \ +CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C \ +CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_10_.D \ +CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C CLK_000_D_12_.D \ +CLK_000_D_12_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \ +CLK_000_P_SYNC_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \ +RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D \ +inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_VMA_INTreg.D \ +inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D \ +inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D \ +inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ +inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \ +inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ +inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \ +inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C BG_000DFFreg.D \ BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ -inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \ -inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \ -inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C \ -inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D \ -inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ -inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ -inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C \ -inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 RW_000 \ -UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_280 N_210_0 cpu_est_0_1__un0_n N_279 \ -N_289_0 cpu_est_0_2__un3_n N_271 N_218_0 cpu_est_0_2__un1_n N_272 \ -cpu_est_0_2__un0_n N_276 N_242_i cpu_est_0_3__un3_n DS_000_ENABLE_1_sqmuxa_1 \ -N_246_i cpu_est_0_3__un1_n N_4 N_240_i cpu_est_0_3__un0_n vcc_n_n N_5 N_241_i \ -ipl_030_0_0__un3_n N_7 ipl_030_0_0__un1_n gnd_n_n N_10 N_266_i \ -ipl_030_0_0__un0_n un1_amiga_bus_enable_low N_18 N_267_i ipl_030_0_1__un3_n \ -un3_size N_24 N_254_i ipl_030_0_1__un1_n un4_size N_6 N_317_i \ -ipl_030_0_1__un0_n un4_uds_000 un1_amiga_bus_enable_low_i ipl_030_0_2__un3_n \ -un4_lds_000 un21_fpu_cs_i N_313_i ipl_030_0_2__un1_n un5_ciin BGACK_030_INT_i \ -N_316_i ipl_030_0_2__un0_n un4_as_000 AMIGA_BUS_ENABLE_DMA_LOW_i N_312_i \ -a0_dma_0_un3_n un21_fpu_cs UDS_000_INT_i a0_dma_0_un1_n un22_berr \ -LDS_000_INT_i N_347_i a0_dma_0_un0_n un6_ds_030 N_236_i N_323_i \ -uds_000_int_0_un3_n sm_amiga_i_5__n N_324_i uds_000_int_0_un1_n \ -DS_000_ENABLE_1_sqmuxa_i N_222_i uds_000_int_0_un0_n N_276_i AS_000_DMA_i \ -vma_int_0_un3_n RST_i N_221_0 vma_int_0_un1_n a_i_19__n N_220_0 \ -vma_int_0_un0_n a_i_18__n N_219_0 amiga_bus_enable_dma_high_0_un3_n \ -size_dma_i_1__n N_216_0 amiga_bus_enable_dma_high_0_un1_n size_dma_i_0__n \ -N_290_0 amiga_bus_enable_dma_high_0_un0_n RW_i N_212_0 bg_000_0_un3_n \ -CLK_000_PE_i N_211_0 bg_000_0_un1_n a_i_16__n N_204_0 bg_000_0_un0_n \ -RESET_OUT_i N_351_i ds_000_dma_0_un3_n BERR_i N_353_i ds_000_dma_0_un1_n \ -sm_amiga_i_i_7__n N_201_i ds_000_dma_0_un0_n nEXP_SPACE_D0_i VMA_INT_i \ -as_000_dma_0_un3_n sm_amiga_i_4__n N_197_i as_000_dma_0_un1_n FPU_SENSE_i \ -N_196_i as_000_dma_0_un0_n AS_030_i N_193_i lds_000_int_0_un3_n AS_030_D0_i \ -N_192_0 lds_000_int_0_un1_n a_i_24__n clk_000_n_sync_i_10__n \ -lds_000_int_0_un0_n sm_amiga_i_3__n N_350_i rw_000_dma_0_un3_n cpu_est_i_0__n \ -N_188_0 rw_000_dma_0_un1_n cpu_est_i_3__n N_187_i rw_000_dma_0_un0_n \ -cpu_est_i_2__n N_185_i a_15__n cpu_est_i_1__n N_182_i VPA_D_i N_181_i a_14__n \ -CLK_000_NE_i CLK_OUT_PRE_D_i sm_amiga_i_1__n N_175_0 a_13__n rst_dly_i_2__n \ -N_168_i CLK_030_i AS_030_000_SYNC_i a_12__n rst_dly_i_0__n N_158_i \ -rst_dly_i_1__n clk_000_d_i_0__n a_11__n clk_000_d_i_1__n N_148_i DTACK_D0_i \ -N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i CLK_030_H_i N_144_0 \ -a_9__n sm_amiga_i_6__n N_138_0 sm_amiga_i_2__n a_8__n AS_000_i N_342_i \ -pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n A1_i N_124_0 a_i_31__n N_341_i \ -a_6__n a_i_29__n N_119_0 a_i_30__n N_340_i a_5__n a_i_27__n N_361_i \ -pos_clk_un9_bg_030_n a_i_28__n cpu_est_2_0_2__n a_4__n a_i_25__n N_338_i \ -a_i_26__n N_339_i a_3__n N_213_i cpu_est_2_0_1__n N_214_i N_332_i a_2__n \ -N_215_i N_336_i pos_clk_un7_clk_000_pe_0_n N_275_i N_99_0 un6_ds_030_i N_331_i \ -DS_000_DMA_i N_96_0 un4_as_000_i N_330_i AS_000_INT_i N_90_0 un4_lds_000_i \ -N_328_i un4_uds_000_i AS_030_c N_80_0 N_325_i AS_000_c N_326_i N_258_0 \ -RW_000_c N_217_i N_321_i N_322_i UDS_000_c N_320_i pos_clk_un7_clk_000_pe_n \ -LDS_000_c un5_ciin_i pos_clk_a0_dma_3_n size_c_0__n N_61_0 N_310_i size_c_1__n \ -N_305_i N_307_i N_3 N_303_i N_8 N_304_i N_283_0 N_301_i N_300_i N_123_0 N_17 \ -N_278_i N_19 N_297_i N_20 AMIGA_BUS_DATA_DIR_c_0 N_21 N_277_i N_22 N_25 N_26 \ -pos_clk_un8_sm_amiga_i_n N_27 A0_c_i N_28 size_c_i_1__n N_29 N_29_i N_32_0 \ -N_28_i N_31_0 N_27_i N_30_0 ipl_c_i_2__n N_53_0 ipl_c_i_1__n N_52_0 a_c_16__n \ -ipl_c_i_0__n N_51_0 a_c_17__n DTACK_c_i N_56_0 a_c_18__n VPA_c_i N_55_0 \ -a_c_19__n nEXP_SPACE_c_i N_54_0 a_c_20__n N_3_i N_49_0 a_c_21__n N_8_i N_45_0 \ -a_c_22__n N_17_i N_42_0 a_c_23__n N_19_i N_40_0 a_c_24__n N_20_i N_123 N_39_0 \ -cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i \ -N_37_0 a_c_27__n N_25_i N_34_0 N_217 a_c_28__n N_26_i N_33_0 N_61 a_c_29__n \ -BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 \ -N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \ -pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c N_351_2 N_124 N_168_i_1 \ -N_138 nEXP_SPACE_c N_192_0_1 N_144 N_192_0_2 N_158 BERR_c N_137_i_1 N_168 \ -N_137_i_2 N_175 BG_030_c N_145_i_1 N_182 N_145_i_2 N_185 N_145_i_3 N_187 \ -N_260_i_1 N_188 N_260_i_2 N_192 BGACK_000_c N_259_i_1 N_193 N_259_i_2 N_197 \ -CLK_030_c N_336_1 N_201 N_336_2 N_204 N_332_1 N_206 N_332_2 N_207 CLK_OSZI_c \ -N_332_3 N_317_1 N_211 N_317_2 N_212 N_317_3 N_290 N_304_1 N_216 N_304_2 N_219 \ -FPU_SENSE_c un5_ciin_1 N_220 un5_ciin_2 N_221 un5_ciin_3 N_227 un5_ciin_4 \ -N_229 un5_ciin_5 N_230 un5_ciin_6 N_236 un5_ciin_7 N_240 un5_ciin_8 N_241 \ -ipl_c_0__n un5_ciin_9 N_242 un5_ciin_10 N_246 ipl_c_1__n un5_ciin_11 N_254 \ -un22_berr_1_0 N_266 ipl_c_2__n un21_fpu_cs_1 N_267 N_375_1 N_275 N_375_2 N_277 \ -DTACK_c N_375_3 N_278 N_375_4 N_297 N_134_i_1 N_300 N_96_0_1 N_301 VPA_c \ -N_83_i_1 N_303 N_261_i_1 N_304 N_141_i_1 N_305 RST_c N_139_i_1 N_307 N_133_i_1 \ -N_310 N_123_0_1 N_312 RW_c N_282_i_1 N_313 N_343_1 N_316 fc_c_0__n N_339_1 \ -N_317 pos_clk_un6_bg_030_1_n N_320 fc_c_1__n N_326_1 N_321 N_325_1 N_322 \ -N_324_1 N_323 AMIGA_BUS_DATA_DIR_c N_316_1 N_324 N_313_1 N_325 N_303_1 N_326 \ -N_297_1 N_328 N_266_1 N_330 N_24_i N_240_1 N_331 N_35_0 pos_clk_ipl_1_n N_332 \ -N_18_i amiga_bus_enable_dma_low_0_un3_n N_336 N_41_0 \ -amiga_bus_enable_dma_low_0_un1_n N_338 N_10_i amiga_bus_enable_dma_low_0_un0_n \ -N_339 N_43_0 rw_000_int_0_un3_n N_340 N_7_i rw_000_int_0_un1_n N_341 N_46_0 \ -rw_000_int_0_un0_n N_342 N_5_i bgack_030_int_0_un3_n N_343 N_47_0 \ -bgack_030_int_0_un1_n N_344 N_4_i bgack_030_int_0_un0_n N_345 N_48_0 \ -as_030_000_sync_0_un3_n N_347 N_272_i as_030_000_sync_0_un1_n N_350 N_271_i \ -as_030_000_sync_0_un0_n N_351 N_279_0 ds_000_enable_0_un3_n N_353 N_280_0 \ -ds_000_enable_0_un1_n N_361 N_281_0 ds_000_enable_0_un0_n N_298_i \ -as_000_int_0_un3_n pos_clk_size_dma_6_0_0__n as_000_int_0_un1_n N_299_i \ -as_000_int_0_un0_n pos_clk_size_dma_6_0_1__n dsack1_int_0_un3_n un22_berr_1 \ -un1_as_000_i dsack1_int_0_un1_n N_375 N_358_i dsack1_int_0_un0_n N_218 \ -pos_clk_un6_bgack_000_0_n size_dma_0_1__un3_n N_156 N_284_i \ -size_dma_0_1__un1_n N_289 N_285_i size_dma_0_1__un0_n N_354 N_286_0 \ -size_dma_0_0__un3_n N_205 N_88_0 size_dma_0_0__un1_n un1_SM_AMIGA_5 \ -pos_clk_un3_as_030_d0_i_n size_dma_0_0__un0_n DS_000_ENABLE_1_sqmuxa N_156_i \ -sm_amiga_srsts_i_0_m2_1__un3_n N_349 N_349_i sm_amiga_srsts_i_0_m2_1__un1_n \ -pos_clk_un3_as_030_d0_n N_194_i sm_amiga_srsts_i_0_m2_1__un0_n N_286 \ -un1_SM_AMIGA_5_i un1_amiga_bus_enable_dma_high_i_m2_0__un3_n \ -pos_clk_un6_bgack_000_n UDS_000_c_i \ -un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_358 LDS_000_c_i \ -un1_amiga_bus_enable_dma_high_i_m2_0__un0_n pos_clk_size_dma_6_1__n N_205_i \ -sm_amiga_srsts_i_0_m2_5__un3_n N_299 N_206_0 sm_amiga_srsts_i_0_m2_5__un1_n \ -pos_clk_size_dma_6_0__n N_207_0 sm_amiga_srsts_i_0_m2_5__un0_n N_298 N_354_i \ -cpu_est_0_1__un3_n N_281 N_208_0 cpu_est_0_1__un1_n AS_030.OE AS_000.OE \ -RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE \ -DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_134 G_135 G_136 \ -pos_clk_un23_bgack_030_int_i_i_a4_i_x2 pos_clk_CYCLE_DMA_5_0_i_x2 \ -cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 -.names N_139_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ +inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D \ +inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D \ +inst_CLK_OUT_PRE_50.C SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 \ +BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ \ +AHIGH_24_ A_0_ N_166 N_32_0 cpu_est_0_3__un0_n N_141 a_c_i_0__n \ +cpu_est_0_2__un3_n N_226 size_c_i_1__n cpu_est_0_2__un1_n N_357 \ +pos_clk_un10_sm_amiga_i_n cpu_est_0_2__un0_n N_219 N_258_0 \ +sm_amiga_srsts_i_0_m2_1__un3_n N_217 N_357_i sm_amiga_srsts_i_0_m2_1__un1_n \ +N_221 N_254_i sm_amiga_srsts_i_0_m2_1__un0_n N_220 cpu_est_2_0_2__n \ +vma_int_0_un3_n N_223 N_315_i vma_int_0_un1_n vcc_n_n N_343 N_291_0 \ +vma_int_0_un0_n N_192 AS_030_000_SYNC_i cpu_est_0_1__un3_n gnd_n_n N_164 \ +N_146_0 cpu_est_0_1__un1_n un1_amiga_bus_enable_dma_high_0__n N_291 N_149_i \ +cpu_est_0_1__un0_n un1_amiga_bus_enable_low N_315 N_164_i \ +sm_amiga_srsts_i_0_0_m2_5__un3_n un6_as_030 cpu_est_2_2__n N_166_i \ +sm_amiga_srsts_i_0_0_m2_5__un1_n un3_size N_254 N_172_i \ +sm_amiga_srsts_i_0_0_m2_5__un0_n un4_size N_258 N_176_i rw_000_int_0_un3_n \ +un4_uds_000 N_29 N_186_0 rw_000_int_0_un1_n un4_lds_000 N_28 N_192_0 \ +rw_000_int_0_un0_n un4_as_000 N_27 N_228_i bgack_030_int_0_un3_n un10_ciin N_4 \ +N_227_i bgack_030_int_0_un1_n un21_fpu_cs N_17 N_343_i bgack_030_int_0_un0_n \ +un22_berr N_21 as_000_int_0_un3_n un6_ds_030 N_26 N_223_i as_000_int_0_un1_n \ +pos_clk_un9_bg_030_n N_225_i as_000_int_0_un0_n un1_amiga_bus_enable_low_i \ +N_224_i ds_000_enable_0_un3_n un21_fpu_cs_i N_226_i ds_000_enable_0_un1_n \ +N_275_i ds_000_enable_0_un0_n clk_000_n_sync_i_12__n N_220_i \ +as_030_000_sync_0_un3_n rst_dly_i_2__n N_221_i as_030_000_sync_0_un1_n \ +rst_dly_i_1__n N_222_i as_030_000_sync_0_un0_n BERR_i \ +un1_amiga_bus_enable_dma_high_0_m2_0__un3_n cpu_est_i_2__n N_217_i \ +un1_amiga_bus_enable_dma_high_0_m2_0__un1_n nEXP_SPACE_i N_215_i \ +un1_amiga_bus_enable_dma_high_0_m2_0__un0_n rst_dly_i_0__n N_219_i \ +amiga_bus_enable_dma_low_0_un3_n cpu_est_i_1__n \ +amiga_bus_enable_dma_low_0_un1_n cpu_est_i_0__n N_200_i \ +amiga_bus_enable_dma_low_0_un0_n VPA_D_i N_195_0 \ +amiga_bus_enable_dma_high_0_un3_n sm_amiga_i_3__n N_190_0 \ +amiga_bus_enable_dma_high_0_un1_n sm_amiga_i_0__n N_157_i \ +amiga_bus_enable_dma_high_0_un0_n cpu_est_i_3__n N_154_i size_dma_0_0__un3_n \ +sm_amiga_i_1__n N_340_i size_dma_0_0__un1_n RESET_OUT_i N_141_0 \ +size_dma_0_0__un0_n BGACK_030_INT_i un3_as_030_i size_dma_0_1__un3_n \ +sm_amiga_i_2__n N_216_i size_dma_0_1__un1_n sm_amiga_i_4__n N_337_i \ +size_dma_0_1__un0_n clk_000_p_sync_i_10__n ds_000_dma_0_un3_n sm_amiga_i_5__n \ +un10_ciin_i ds_000_dma_0_un1_n sm_amiga_i_i_7__n N_296_0 ds_000_dma_0_un0_n \ +clk_000_d_i_11__n un1_as_000_i as_000_dma_0_un3_n sm_amiga_i_6__n N_284_i \ +as_000_dma_0_un1_n RW_i N_285_i as_000_dma_0_un0_n DS_000_ENABLE_1_sqmuxa_i \ +N_292_0 rw_000_dma_0_un3_n LDS_000_INT_i N_280_i rw_000_dma_0_un1_n \ +UDS_000_INT_i N_277_i rw_000_dma_0_un0_n AS_030_i N_257_0 a0_dma_0_un3_n \ +AS_000_INT_i N_235_i a0_dma_0_un1_n a_decode_i_19__n N_236_i a0_dma_0_un0_n \ +a_decode_i_18__n cpu_est_2_0_1__n a_decode_15__n a_decode_i_16__n N_231_i \ +AS_000_i N_230_i a_decode_14__n FPU_SENSE_i pos_clk_un4_clk_000_pe_0_n \ +AMIGA_BUS_ENABLE_DMA_HIGH_i N_22_i a_decode_13__n CLK_030_i N_37_0 \ +pos_clk_un6_bg_030_n DTACK_D0_i a_decode_12__n clk_000_d_i_10__n N_334_i \ +RW_000_i N_335_i a_decode_11__n a_i_1__n N_194_0 CLK_030_H_i N_191_0 \ +a_decode_10__n pos_clk_ipl_n AS_000_DMA_i un1_SM_AMIGA_5_i clk_000_d_i_0__n \ +N_346_i a_decode_9__n clk_000_d_i_1__n N_163_i AS_030_D0_i N_345_i \ +a_decode_8__n size_dma_i_0__n N_344_i size_dma_i_1__n N_153_0 a_decode_7__n \ +ahigh_i_30__n pos_clk_un3_as_030_d0_i_n ahigh_i_31__n N_293_0 a_decode_6__n \ +ahigh_i_28__n N_233_i ahigh_i_29__n N_232_i a_decode_5__n ahigh_i_26__n \ +N_290_0 ahigh_i_27__n VPA_c_i a_decode_4__n ahigh_i_24__n N_54_0 ahigh_i_25__n \ +N_5_i a_decode_3__n N_212_i N_47_0 N_213_i N_7_i a_decode_2__n N_214_i N_46_0 \ +N_18_i N_41_0 N_321_i N_10_i N_322_i N_43_0 un6_ds_030_i DTACK_c_i \ +DS_000_DMA_i N_55_0 un4_as_000_i pos_clk_un6_bgack_000_0_n un6_as_030_i \ +N_137_i un4_lds_000_i N_184_0 un4_uds_000_i N_349_i AMIGA_BUS_ENABLE_DMA_LOW_i \ +N_185_i AS_030_c N_187_0 pos_clk_un5_bgack_030_int_d_n N_203_i AS_000_c \ +N_324_i RW_000_c N_199_0 N_197_0 N_196_0 pos_clk_a0_dma_3_n UDS_000_c \ +LDS_000_c_i UDS_000_c_i LDS_000_c N_181_i N_347_i size_c_0__n N_348_i N_178_i \ +pos_clk_ds_000_dma_4_n size_c_1__n VMA_INT_i N_3 \ +pos_clk_un5_bgack_030_int_d_i_n N_8 ahigh_c_24__n \ +pos_clk_un23_bgack_030_int_i_1_0_n CLK_OUT_PRE_D_i ahigh_c_25__n N_148_0 \ +N_341_i ahigh_c_26__n N_338_i N_339_i N_19 ahigh_c_27__n N_20 N_336_i N_24 \ +ahigh_c_28__n N_122_0 N_25 N_211_i ahigh_c_29__n N_332_i ahigh_c_30__n N_331_i \ +N_120_0 ahigh_c_31__n N_330_i pos_clk_ds_000_dma_4_0_n N_329_i \ +pos_clk_size_dma_6_0_1__n N_328_i pos_clk_size_dma_6_0_0__n N_325_i N_327_i \ +AMIGA_BUS_DATA_DIR_c_0 N_320_i N_298_0 N_295_0 N_294_0 N_319_i \ +un1_amiga_bus_enable_dma_high_0_0__n N_206_i N_283_i N_122 N_281_i \ +pos_clk_size_dma_6_0__n N_282_i pos_clk_size_dma_6_1__n N_3_i N_49_0 N_8_i \ +N_45_0 pos_clk_un23_bgack_030_int_i_1_n N_19_i N_292 N_40_0 N_294 \ +a_decode_c_16__n N_20_i N_295 N_39_0 N_296 a_decode_c_17__n N_24_i N_298 \ +N_35_0 N_120 a_decode_c_18__n N_25_i N_148 N_34_0 N_149 a_decode_c_19__n \ +N_194_0_1 N_157 N_237_i_1 N_172 a_decode_c_20__n N_237_i_2 N_176 N_238_i_1 \ +N_178 a_decode_c_21__n N_238_i_2 N_181 N_144_i_1 N_184 a_decode_c_22__n \ +N_144_i_2 N_144_i_3 N_196 a_decode_c_23__n N_136_i_1 N_197 N_136_i_2 N_206 \ +a_c_0__n N_176_i_1 N_207 N_146_0_1 N_211 a_c_1__n pos_clk_un10_sm_amiga_i_1_n \ +N_215 un10_ciin_1 N_222 nEXP_SPACE_c un10_ciin_2 N_224 un10_ciin_3 N_225 \ +BERR_c un10_ciin_4 N_227 un10_ciin_5 N_228 BG_030_c un10_ciin_6 N_236 \ +un10_ciin_7 N_277 un10_ciin_8 N_281 un10_ciin_9 N_282 un10_ciin_10 N_283 \ +BGACK_000_c un10_ciin_11 N_285 N_347_1 N_318 CLK_030_c N_347_2 N_319 \ +pos_clk_un23_bgack_030_int_i_1_0_1_n N_320 CLK_000_c \ +pos_clk_un23_bgack_030_int_i_1_0_2_n N_321 un21_fpu_cs_1 N_322 CLK_OSZI_c \ +un22_berr_1_0 N_323 N_366_1 N_325 N_366_2 N_327 N_366_3 N_328 N_366_4 N_329 \ +un1_SM_AMIGA_5_i_1 N_330 FPU_SENSE_c un1_SM_AMIGA_5_i_2 N_331 N_142_i_1 N_332 \ +N_142_i_2 N_336 N_339_1 N_338 N_280_1 N_339 N_280_2 N_341 N_231_1 N_344 \ +N_231_2 N_347 ipl_c_0__n N_230_1 N_348 N_230_2 ipl_c_1__n N_230_3 N_226_1 \ +ipl_c_2__n N_226_2 N_226_3 N_199 N_239_i_1 N_324 DTACK_c N_122_0_1 un22_berr_1 \ +N_132_i_1 N_366 N_120_0_1 N_335 N_106_i_1 N_208 VPA_c N_103_i_1 N_203 N_92_i_1 \ +N_187 N_140_i_1 N_137 RST_c N_138_i_1 N_349 N_344_1 pos_clk_un6_bgack_000_n \ +pos_clk_un6_bg_030_1_n N_10 RW_c N_327_1 N_5 N_319_1 N_293 fc_c_0__n N_285_1 \ +N_6 N_277_1 un1_SM_AMIGA_5 fc_c_1__n N_236_1 DS_000_ENABLE_1_sqmuxa_1 N_228_1 \ +N_7 N_225_1 pos_clk_un3_as_030_d0_n AMIGA_BUS_DATA_DIR_c N_224_1 N_290 N_222_1 \ +N_18 N_215_1 DS_000_ENABLE_1_sqmuxa pos_clk_ipl_1_n N_232 bg_000_0_un3_n N_194 \ +BG_030_c_i bg_000_0_un1_n N_233 pos_clk_un6_bg_030_i_n bg_000_0_un0_n N_275 \ +pos_clk_un9_bg_030_0_n uds_000_int_0_un3_n N_153 N_26_i uds_000_int_0_un1_n \ +N_191 N_33_0 uds_000_int_0_un0_n N_334 N_21_i lds_000_int_0_un3_n N_146 N_38_0 \ +lds_000_int_0_un1_n N_345 N_17_i lds_000_int_0_un0_n N_346 N_42_0 \ +dsack1_int_0_un3_n N_163 N_4_i dsack1_int_0_un1_n N_22 N_48_0 \ +dsack1_int_0_un0_n pos_clk_un4_clk_000_pe_n ipl_c_i_0__n ipl_030_0_2__un3_n \ +cpu_est_2_1__n N_51_0 ipl_030_0_2__un1_n N_235 ipl_c_i_1__n ipl_030_0_2__un0_n \ +N_284 N_52_0 ipl_030_0_1__un3_n N_190 ipl_c_i_2__n ipl_030_0_1__un1_n N_337 \ +N_53_0 ipl_030_0_1__un0_n N_195 N_27_i ipl_030_0_0__un3_n N_340 N_30_0 \ +ipl_030_0_0__un1_n N_231 N_28_i ipl_030_0_0__un0_n N_230 N_31_0 \ +cpu_est_0_3__un3_n N_280 N_29_i cpu_est_0_3__un1_n AS_030.OE AS_000.OE \ +RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE \ +AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE \ +AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_134 \ +G_135 G_136 pos_clk_un23_bgack_030_int_i_0_x2 cpu_est_0_0_x2_0_x2_0_ \ +pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_CYCLE_DMA_5_1_i_x2 +.names N_144_i_3.BLIF N_226_i.BLIF SM_AMIGA_i_7_.D 11 1 -.names N_137_i_1.BLIF N_137_i_2.BLIF SM_AMIGA_3_.D +.names N_142_i_1.BLIF N_142_i_2.BLIF SM_AMIGA_6_.D 11 1 -.names N_283_0.BLIF SM_AMIGA_2_.D +.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D +11 1 +.names N_138_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +11 1 +.names N_136_i_1.BLIF N_136_i_2.BLIF SM_AMIGA_3_.D +11 1 +.names N_257_0.BLIF SM_AMIGA_2_.D 0 1 -.names N_133_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D +.names N_132_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D 11 1 -.names N_208_0.BLIF N_277_i.BLIF SM_AMIGA_0_.D +.names N_185_i.BLIF N_324_i.BLIF SM_AMIGA_0_.D 11 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D +1- 1 +-1 1 .names N_30_0.BLIF IPL_030DFF_0_reg.D 0 1 .names N_31_0.BLIF IPL_030DFF_1_reg.D @@ -447,15 +507,9 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 0 1 .names N_53_0.BLIF IPL_D0_2_.D 0 1 -.names N_145_i_3.BLIF N_317_i.BLIF SM_AMIGA_i_7_.D +.names N_92_i_1.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF CYCLE_DMA_0_.D 11 1 -.names N_258_0.BLIF SM_AMIGA_6_.D -0 1 -.names N_141_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D -11 1 -.names N_282_i_1.BLIF N_210_0.BLIF CYCLE_DMA_0_.D -11 1 -.names N_134_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF CYCLE_DMA_1_.D +.names N_103_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF CYCLE_DMA_1_.D 11 1 .names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D 1- 1 @@ -466,46 +520,22 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D -1- 1 --1 1 -.names N_260_i_1.BLIF N_260_i_2.BLIF RST_DLY_1_.D -11 1 -.names N_259_i_1.BLIF N_259_i_2.BLIF RST_DLY_2_.D +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF CLK_000_N_SYNC_0_.D 11 1 .names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF CLK_000_P_SYNC_0_.D 11 1 -.names N_261_i_1.BLIF N_322_i.BLIF RST_DLY_0_.D +.names N_239_i_1.BLIF RST_c.BLIF RST_DLY_0_.D 11 1 -.names N_47_0.BLIF inst_AS_000_INT.D -0 1 -.names N_48_0.BLIF inst_DSACK1_INTreg.D -0 1 -.names N_49_0.BLIF inst_DS_000_DMA.D -0 1 -.names N_88_0.BLIF inst_AS_030_D0.D -0 1 -.names N_54_0.BLIF inst_nEXP_SPACE_D0reg.D -0 1 -.names N_55_0.BLIF inst_VPA_D.D -0 1 -.names N_56_0.BLIF inst_DTACK_D0.D -0 1 -.names N_83_i_1.BLIF RST_c.BLIF inst_CLK_030_H.D +.names N_238_i_1.BLIF N_238_i_2.BLIF RST_DLY_1_.D 11 1 -.names N_320_i.BLIF RST_c.BLIF inst_RESET_OUT.D +.names N_237_i_1.BLIF N_237_i_2.BLIF RST_DLY_2_.D +11 1 +.names N_106_i_1.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF inst_CLK_030_H.D +11 1 +.names N_337_i.BLIF RST_c.BLIF inst_RESET_OUT.D 11 1 .names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D 11 1 -.names N_33_0.BLIF BG_000DFFreg.D -0 1 -.names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D -0 1 -.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 .names N_37_0.BLIF inst_VMA_INTreg.D 0 1 .names N_38_0.BLIF inst_UDS_000_INT.D @@ -524,568 +554,695 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 0 1 .names N_46_0.BLIF inst_AS_030_000_SYNC.D 0 1 -.names N_210_0.BLIF inst_BGACK_030_INT_D.D +.names N_47_0.BLIF inst_AS_000_INT.D +0 1 +.names N_48_0.BLIF inst_DSACK1_INTreg.D +0 1 +.names N_49_0.BLIF inst_DS_000_DMA.D +0 1 +.names N_323.BLIF inst_AS_030_D0.D +0 1 +.names N_54_0.BLIF inst_VPA_D.D +0 1 +.names N_55_0.BLIF inst_DTACK_D0.D +0 1 +.names N_33_0.BLIF BG_000DFFreg.D +0 1 +.names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names N_186_0.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names N_280_0.BLIF N_280 +.names N_166_i.BLIF N_166 0 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_210_0 +.names N_29_i.BLIF RST_c.BLIF N_32_0 11 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +.names cpu_est_3_.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 -.names N_279_0.BLIF N_279 +.names N_141_0.BLIF N_141 +0 1 +.names a_c_0__n.BLIF a_c_i_0__n 0 1 -.names N_289_0_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_289_0 -11 1 .names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n 0 1 -.names N_289.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_271 -11 1 -.names N_156_i.BLIF SM_AMIGA_4_.BLIF N_218_0 +.names N_226_3.BLIF sm_amiga_i_3__n.BLIF N_226 11 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 .names cpu_est_2_2__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n 11 1 -.names N_375.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_272 +.names N_164_i.BLIF cpu_est_i_2__n.BLIF N_357 +11 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ +pos_clk_un10_sm_amiga_i_n 11 1 .names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n 11 1 -.names A1_c.BLIF BGACK_030_INT_i.BLIF N_276 +.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_2__n.BLIF N_219 11 1 -.names N_242.BLIF N_242_i -0 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n -0 1 -.names pos_clk_un3_as_030_d0_i_n.BLIF un1_SM_AMIGA_5.BLIF \ -DS_000_ENABLE_1_sqmuxa_1 +.names N_275_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_258_0 11 1 -.names N_246.BLIF N_246_i +.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n 0 1 -.names N_119.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n +.names N_141.BLIF N_166_i.BLIF N_217 11 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_4 -1- 1 --1 1 -.names N_240.BLIF N_240_i +.names N_357.BLIF N_357_i 0 1 -.names cpu_est_3_.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n +11 1 +.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_1__n.BLIF N_221 +11 1 +.names N_254.BLIF N_254_i +0 1 +.names clk_000_p_sync_i_10__n.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF \ +sm_amiga_srsts_i_0_m2_1__un0_n +11 1 +.names N_149_i.BLIF N_340.BLIF N_220 +11 1 +.names N_254_i.BLIF N_357_i.BLIF cpu_est_2_0_2__n +11 1 +.names pos_clk_un4_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 +.names N_192.BLIF N_343.BLIF N_223 +11 1 +.names N_315.BLIF N_315_i +0 1 +.names cpu_est_i_1__n.BLIF pos_clk_un4_clk_000_pe_n.BLIF vma_int_0_un1_n 11 1 .names vcc_n_n 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_5 -1- 1 --1 1 -.names N_241.BLIF N_241_i -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_7 -1- 1 --1 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_343 11 1 -.names gnd_n_n -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_10 -1- 1 --1 1 -.names N_266.BLIF N_266_i +.names N_157.BLIF N_315_i.BLIF N_291_0 +11 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names N_192_0.BLIF N_192 0 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n +0 1 +.names gnd_n_n +.names N_164_i.BLIF N_164 +0 1 +.names N_146_0_1.BLIF nEXP_SPACE_c.BLIF N_146_0 +11 1 +.names cpu_est_2_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n +11 1 +.names un1_amiga_bus_enable_dma_high_0_0__n.BLIF \ +un1_amiga_bus_enable_dma_high_0__n +0 1 +.names N_291_0.BLIF N_291 +0 1 +.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_149_i +11 1 +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 .names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ un1_amiga_bus_enable_low 11 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_18 -1- 1 --1 1 -.names N_267.BLIF N_267_i +.names N_164_i.BLIF cpu_est_2_.BLIF N_315 +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_164_i +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m2_5__un3_n 0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 +11 1 +.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n 0 1 +.names N_149_i.BLIF RST_DLY_2_.BLIF N_166_i +11 1 +.names BERR_i.BLIF SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m2_5__un1_n +11 1 .names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size 11 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_24 -1- 1 --1 1 -.names N_254.BLIF N_254_i -0 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +.names N_164.BLIF cpu_est_2_.BLIF N_254 +11 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_172_i +11 1 +.names clk_000_p_sync_i_10__n.BLIF sm_amiga_srsts_i_0_0_m2_5__un3_n.BLIF \ +sm_amiga_srsts_i_0_0_m2_5__un0_n 11 1 .names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size 11 1 -.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6 -1- 1 --1 1 -.names N_317.BLIF N_317_i +.names N_258_0.BLIF N_258 0 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +.names N_176_i_1.BLIF sm_amiga_i_2__n.BLIF N_176_i 11 1 +.names N_122.BLIF rw_000_int_0_un3_n +0 1 .names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un4_uds_000 11 1 -.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n -0 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 +1- 1 +-1 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_186_0 +11 1 +.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_122.BLIF rw_000_int_0_un1_n +11 1 .names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un4_lds_000 11 1 -.names un21_fpu_cs.BLIF un21_fpu_cs_i -0 1 -.names N_313.BLIF N_313_i -0 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28 +1- 1 +-1 1 +.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_192_0 11 1 -.names un5_ciin_10.BLIF un5_ciin_11.BLIF un5_ciin -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names N_316.BLIF N_316_i -0 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 .names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names N_312.BLIF N_312_i -0 1 -.names N_193.BLIF a0_dma_0_un3_n -0 1 -.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs -11 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names pos_clk_a0_dma_3_n.BLIF N_193.BLIF a0_dma_0_un1_n -11 1 -.names un22_berr_1_0.BLIF N_375.BLIF un22_berr -11 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i -0 1 -.names N_347.BLIF N_347_i -0 1 -.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n -11 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 -11 1 -.names N_236.BLIF N_236_i -0 1 -.names N_323.BLIF N_323_i -0 1 -.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n -0 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names N_324.BLIF N_324_i -0 1 -.names A0_c.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n -11 1 -.names DS_000_ENABLE_1_sqmuxa.BLIF DS_000_ENABLE_1_sqmuxa_i -0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF N_222_i -11 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names N_276.BLIF N_276_i -0 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n -0 1 -.names RST_c.BLIF RST_i -0 1 -.names AS_000_DMA_i.BLIF CLK_030_i.BLIF N_221_0 -11 1 -.names cpu_est_i_1__n.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n -11 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names inst_CLK_000_PE.BLIF SM_AMIGA_4_.BLIF N_220_0 -11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_219_0 -11 1 -.names N_193.BLIF amiga_bus_enable_dma_high_0_un3_n -0 1 -.names SIZE_DMA_1_.BLIF size_dma_i_1__n -0 1 -.names inst_CLK_000_NE.BLIF N_187_i.BLIF N_216_0 -11 1 -.names N_275_i.BLIF N_193.BLIF amiga_bus_enable_dma_high_0_un1_n -11 1 -.names SIZE_DMA_0_.BLIF size_dma_i_0__n -0 1 -.names inst_CLK_000_NE_D0.BLIF N_201.BLIF N_290_0 -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n -11 1 -.names RW_c.BLIF RW_i -0 1 -.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_212_0 -11 1 -.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n -0 1 -.names inst_CLK_000_PE.BLIF CLK_000_PE_i -0 1 -.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_211_0 -11 1 -.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n -11 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names N_196_i.BLIF sm_amiga_i_6__n.BLIF N_204_0 -11 1 -.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names inst_RESET_OUT.BLIF RESET_OUT_i -0 1 -.names N_351.BLIF N_351_i -0 1 -.names N_96.BLIF ds_000_dma_0_un3_n -0 1 -.names BERR_c.BLIF BERR_i -0 1 -.names N_353.BLIF N_353_i -0 1 -.names N_90.BLIF N_96.BLIF ds_000_dma_0_un1_n -11 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names N_351_i.BLIF N_353_i.BLIF N_201_i -11 1 -.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names N_99.BLIF as_000_dma_0_un3_n -0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_197_i -11 1 -.names N_192.BLIF N_99.BLIF as_000_dma_0_un1_n -11 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names sm_amiga_i_2__n.BLIF sm_amiga_i_4__n.BLIF N_196_i -11 1 -.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_193_i -11 1 -.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names N_192_0_1.BLIF N_192_0_2.BLIF N_192_0 -11 1 -.names pos_clk_un8_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n -11 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n -0 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_350.BLIF N_350_i -0 1 -.names N_193.BLIF rw_000_dma_0_un3_n -0 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names clk_000_n_sync_i_10__n.BLIF N_350_i.BLIF N_188_0 -11 1 -.names N_80.BLIF N_193.BLIF rw_000_dma_0_un1_n -11 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names N_158_i.BLIF RST_DLY_2_.BLIF N_187_i -11 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_185_i -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names N_181_i.BLIF cpu_est_i_0__n.BLIF N_182_i -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names cpu_est_3_.BLIF cpu_est_i_2__n.BLIF N_181_i -11 1 -.names inst_CLK_000_NE.BLIF CLK_000_NE_i -0 1 -.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_175_0 -11 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n -0 1 -.names N_168_i_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_168_i -11 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n -0 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_158_i -11 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_148_i -11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names N_345.BLIF N_345_i -0 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n -11 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_344.BLIF N_344_i -0 1 -.names inst_CLK_030_H.BLIF CLK_030_H_i -0 1 -.names N_344_i.BLIF RST_c.BLIF N_144_0 -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF N_138_0 -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names N_342.BLIF N_342_i -0 1 -.names pos_clk_ipl_1_n.BLIF N_214_i.BLIF pos_clk_ipl_n -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names N_343.BLIF N_343_i -0 1 -.names A1_c.BLIF A1_i -0 1 -.names N_342_i.BLIF N_343_i.BLIF N_124_0 -11 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names N_341.BLIF N_341_i -0 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names N_182.BLIF N_341_i.BLIF N_119_0 -11 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names N_340.BLIF N_340_i -0 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names N_361.BLIF N_361_i -0 1 -.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n -0 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names N_340_i.BLIF N_361_i.BLIF cpu_est_2_0_2__n -11 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names N_338.BLIF N_338_i -0 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names N_339.BLIF N_339_i -0 1 -.names G_134.BLIF N_213_i -0 1 -.names N_338_i.BLIF N_339_i.BLIF cpu_est_2_0_1__n -11 1 -.names G_135.BLIF N_214_i -0 1 -.names N_332.BLIF N_332_i -0 1 -.names G_136.BLIF N_215_i -0 1 -.names N_336.BLIF N_336_i -0 1 -.names N_332_i.BLIF N_336_i.BLIF pos_clk_un7_clk_000_pe_0_n -11 1 -.names N_275.BLIF N_275_i -0 1 -.names CLK_030_i.BLIF N_192_0.BLIF N_99_0 -11 1 -.names un6_ds_030.BLIF un6_ds_030_i -0 1 -.names N_331.BLIF N_331_i -0 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i -0 1 -.names N_96_0_1.BLIF RW_000_i.BLIF N_96_0 -11 1 -.names un4_as_000.BLIF un4_as_000_i -0 1 -.names N_330.BLIF N_330_i -0 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names N_192_0.BLIF N_330_i.BLIF N_90_0 -11 1 -.names un4_lds_000.BLIF un4_lds_000_i -0 1 -.names N_328.BLIF N_328_i -0 1 -.names un4_uds_000.BLIF un4_uds_000_i -0 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_80_0 -11 1 -.names N_325.BLIF N_325_i -0 1 -.names N_326.BLIF N_326_i -0 1 -.names N_325_i.BLIF N_326_i.BLIF N_258_0 -11 1 -.names N_187.BLIF RST_c.BLIF N_217_i -11 1 -.names N_321.BLIF N_321_i -0 1 -.names N_322.BLIF N_322_i -0 1 -.names N_320.BLIF N_320_i -0 1 -.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n -0 1 -.names un5_ciin.BLIF un5_ciin_i -0 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n -11 1 -.names nEXP_SPACE_D0_i.BLIF un5_ciin_i.BLIF N_61_0 -11 1 -.names N_310.BLIF N_310_i -0 1 -.names N_305.BLIF N_305_i -0 1 -.names N_307.BLIF N_307_i -0 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names N_303.BLIF N_303_i -0 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_8 -1- 1 --1 1 -.names N_304.BLIF N_304_i -0 1 -.names N_303_i.BLIF N_304_i.BLIF N_283_0 -11 1 -.names N_301.BLIF N_301_i -0 1 -.names N_300.BLIF N_300_i -0 1 -.names N_123_0_1.BLIF SM_AMIGA_i_7_.BLIF N_123_0 -11 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_17 -1- 1 --1 1 -.names N_278.BLIF N_278_i -0 1 -.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 -1- 1 --1 1 -.names N_297.BLIF N_297_i -0 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 -1- 1 --1 1 -.names N_278_i.BLIF N_297_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 -1- 1 --1 1 -.names N_277.BLIF N_277_i -0 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_22 -1- 1 --1 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF N_25 -1- 1 --1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26 -1- 1 --1 1 -.names pos_clk_un8_sm_amiga_i_1_n.BLIF size_c_0__n.BLIF \ -pos_clk_un8_sm_amiga_i_n -11 1 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27 1- 1 -1 1 -.names A0_c.BLIF A0_c_i +.names N_228.BLIF N_228_i 0 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28 +.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin +11 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_4 1- 1 -1 1 -.names size_c_1__n.BLIF size_c_i_1__n +.names N_227.BLIF N_227_i 0 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 +.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +11 1 +.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs +11 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_17 1- 1 -1 1 -.names N_29.BLIF N_29_i +.names N_343.BLIF N_343_i 0 1 -.names N_29_i.BLIF RST_c.BLIF N_32_0 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ +bgack_030_int_0_un0_n 11 1 -.names N_28.BLIF N_28_i +.names un22_berr_1_0.BLIF N_366.BLIF un22_berr +11 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names N_293.BLIF as_000_int_0_un3_n 0 1 -.names N_28_i.BLIF RST_c.BLIF N_31_0 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 11 1 -.names N_27.BLIF N_27_i +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26 +1- 1 +-1 1 +.names N_223.BLIF N_223_i 0 1 -.names N_27_i.BLIF RST_c.BLIF N_30_0 +.names sm_amiga_i_5__n.BLIF N_293.BLIF as_000_int_0_un1_n 11 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n 0 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_53_0 -11 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n +.names N_225.BLIF N_225_i 0 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_52_0 +.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i 0 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_51_0 -11 1 -.names DTACK_c.BLIF DTACK_c_i +.names N_224.BLIF N_224_i 0 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_56_0 +.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n +0 1 +.names un21_fpu_cs.BLIF un21_fpu_cs_i +0 1 +.names N_226.BLIF N_226_i +0 1 +.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF \ +ds_000_enable_0_un1_n 11 1 +.names N_275.BLIF N_275_i +0 1 +.names un1_SM_AMIGA_5_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n +11 1 +.names CLK_000_N_SYNC_12_.BLIF clk_000_n_sync_i_12__n +0 1 +.names N_220.BLIF N_220_i +0 1 +.names N_290.BLIF as_030_000_sync_0_un3_n +0 1 +.names RST_DLY_2_.BLIF rst_dly_i_2__n +0 1 +.names N_221.BLIF N_221_i +0 1 +.names inst_AS_030_000_SYNC.BLIF N_290.BLIF as_030_000_sync_0_un1_n +11 1 +.names RST_DLY_1_.BLIF rst_dly_i_1__n +0 1 +.names N_222.BLIF N_222_i +0 1 +.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un0_n +11 1 +.names BERR_c.BLIF BERR_i +0 1 +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names N_217.BLIF N_217_i +0 1 +.names SM_AMIGA_i_7_.BLIF inst_BGACK_030_INTreg.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un1_n +11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names N_215.BLIF N_215_i +0 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un0_n +11 1 +.names RST_DLY_0_.BLIF rst_dly_i_0__n +0 1 +.names N_219.BLIF N_219_i +0 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names N_322_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +amiga_bus_enable_dma_low_0_un1_n +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_200_i +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ +amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n +11 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names CLK_000_N_SYNC_12_.BLIF N_166_i.BLIF N_195_0 +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n +0 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names clk_000_n_sync_i_12__n.BLIF SM_AMIGA_1_.BLIF N_190_0 +11 1 +.names N_321_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +amiga_bus_enable_dma_high_0_un1_n +11 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names N_154_i.BLIF cpu_est_i_0__n.BLIF N_157_i +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +11 1 +.names cpu_est_3_.BLIF cpu_est_i_3__n +0 1 +.names cpu_est_3_.BLIF cpu_est_i_2__n.BLIF N_154_i +11 1 +.names N_294.BLIF size_dma_0_0__un3_n +0 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_340.BLIF N_340_i +0 1 +.names pos_clk_size_dma_6_0__n.BLIF N_294.BLIF size_dma_0_0__un1_n +11 1 +.names inst_RESET_OUT.BLIF RESET_OUT_i +0 1 +.names N_340_i.BLIF RST_c.BLIF N_141_0 +11 1 +.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names N_200_i.BLIF inst_RESET_OUT.BLIF un3_as_030_i +11 1 +.names N_294.BLIF size_dma_0_1__un3_n +0 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names N_166.BLIF RST_c.BLIF N_216_i +11 1 +.names pos_clk_size_dma_6_1__n.BLIF N_294.BLIF size_dma_0_1__un1_n +11 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names N_337.BLIF N_337_i +0 1 +.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n +11 1 +.names CLK_000_P_SYNC_10_.BLIF clk_000_p_sync_i_10__n +0 1 +.names N_120.BLIF ds_000_dma_0_un3_n +0 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names un10_ciin.BLIF un10_ciin_i +0 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_120.BLIF ds_000_dma_0_un1_n +11 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_296_0 +11 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names CLK_000_D_11_.BLIF clk_000_d_i_11__n +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i +11 1 +.names N_298.BLIF as_000_dma_0_un3_n +0 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names N_284.BLIF N_284_i +0 1 +.names pos_clk_un23_bgack_030_int_i_1_n.BLIF N_298.BLIF as_000_dma_0_un1_n +11 1 +.names RW_c.BLIF RW_i +0 1 +.names N_285.BLIF N_285_i +0 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names DS_000_ENABLE_1_sqmuxa.BLIF DS_000_ENABLE_1_sqmuxa_i +0 1 +.names N_284_i.BLIF N_285_i.BLIF N_292_0 +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n +0 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names N_280.BLIF N_280_i +0 1 +.names N_295.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n +11 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names N_277.BLIF N_277_i +0 1 +.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_277_i.BLIF N_280_i.BLIF N_257_0 +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_235.BLIF N_235_i +0 1 +.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +a0_dma_0_un1_n +11 1 +.names a_decode_c_19__n.BLIF a_decode_i_19__n +0 1 +.names N_236.BLIF N_236_i +0 1 +.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +11 1 +.names a_decode_c_18__n.BLIF a_decode_i_18__n +0 1 +.names N_235_i.BLIF N_236_i.BLIF cpu_est_2_0_1__n +11 1 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names N_231.BLIF N_231_i +0 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names N_230.BLIF N_230_i +0 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names N_230_i.BLIF N_231_i.BLIF pos_clk_un4_clk_000_pe_0_n +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i +0 1 +.names N_22.BLIF N_22_i +0 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names N_22_i.BLIF RST_c.BLIF N_37_0 +11 1 +.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n +11 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names CLK_000_D_10_.BLIF clk_000_d_i_10__n +0 1 +.names N_334.BLIF N_334_i +0 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names N_335.BLIF N_335_i +0 1 +.names a_c_1__n.BLIF a_i_1__n +0 1 +.names N_194_0_1.BLIF nEXP_SPACE_c.BLIF N_194_0 +11 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names clk_000_n_sync_i_12__n.BLIF SM_AMIGA_5_.BLIF N_191_0 +11 1 +.names pos_clk_ipl_1_n.BLIF N_213_i.BLIF pos_clk_ipl_n +11 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names un1_SM_AMIGA_5_i_1.BLIF un1_SM_AMIGA_5_i_2.BLIF un1_SM_AMIGA_5_i +11 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names N_346.BLIF N_346_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names sm_amiga_i_6__n.BLIF SM_AMIGA_i_7_.BLIF N_163_i +11 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names N_345.BLIF N_345_i +0 1 +.names SIZE_DMA_0_.BLIF size_dma_i_0__n +0 1 +.names N_344.BLIF N_344_i +0 1 +.names SIZE_DMA_1_.BLIF size_dma_i_1__n +0 1 +.names N_344_i.BLIF N_345_i.BLIF N_153_0 +11 1 +.names ahigh_c_30__n.BLIF ahigh_i_30__n +0 1 +.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n +11 1 +.names ahigh_c_31__n.BLIF ahigh_i_31__n +0 1 +.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_293_0 +11 1 +.names ahigh_c_28__n.BLIF ahigh_i_28__n +0 1 +.names N_233.BLIF N_233_i +0 1 +.names ahigh_c_29__n.BLIF ahigh_i_29__n +0 1 +.names N_232.BLIF N_232_i +0 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names N_232_i.BLIF N_233_i.BLIF N_290_0 +11 1 +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 .names VPA_c.BLIF VPA_c_i 0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_55_0 -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i +.names ahigh_c_24__n.BLIF ahigh_i_24__n 0 1 -.names RST_c.BLIF nEXP_SPACE_c_i.BLIF N_54_0 +.names RST_c.BLIF VPA_c_i.BLIF N_54_0 11 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 +.names N_5.BLIF N_5_i +0 1 +.names G_134.BLIF N_212_i +0 1 +.names N_5_i.BLIF RST_c.BLIF N_47_0 +11 1 +.names G_135.BLIF N_213_i +0 1 +.names N_7.BLIF N_7_i +0 1 +.names G_136.BLIF N_214_i +0 1 +.names N_7_i.BLIF RST_c.BLIF N_46_0 +11 1 +.names N_18.BLIF N_18_i +0 1 +.names N_18_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names N_321.BLIF N_321_i +0 1 +.names N_10.BLIF N_10_i +0 1 +.names N_322.BLIF N_322_i +0 1 +.names N_10_i.BLIF RST_c.BLIF N_43_0 +11 1 +.names un6_ds_030.BLIF un6_ds_030_i +0 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names DTACK_c_i.BLIF RST_c.BLIF N_55_0 +11 1 +.names un4_as_000.BLIF un4_as_000_i +0 1 +.names BGACK_000_c.BLIF N_203.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names un6_as_030.BLIF un6_as_030_i +0 1 +.names BERR_c.BLIF clk_000_p_sync_i_10__n.BLIF N_137_i +11 1 +.names un4_lds_000.BLIF un4_lds_000_i +0 1 +.names N_137.BLIF sm_amiga_i_3__n.BLIF N_184_0 +11 1 +.names un4_uds_000.BLIF un4_uds_000_i +0 1 +.names N_349.BLIF N_349_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names N_349_i.BLIF RST_c.BLIF N_185_i +11 1 +.names N_137_i.BLIF SM_AMIGA_4_.BLIF N_187_0 +11 1 +.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n +0 1 +.names AS_000_c.BLIF CLK_000_P_SYNC_10_.BLIF N_203_i +11 1 +.names N_324.BLIF N_324_i +0 1 +.names CLK_000_N_SYNC_12_.BLIF SM_AMIGA_1_.BLIF N_199_0 +11 1 +.names AS_000_DMA_i.BLIF CLK_030_i.BLIF N_197_0 +11 1 +.names CLK_000_P_SYNC_10_.BLIF SM_AMIGA_4_.BLIF N_196_0 +11 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +11 1 +.names LDS_000_c.BLIF LDS_000_c_i +0 1 +.names UDS_000_c.BLIF UDS_000_c_i +0 1 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_181_i +11 1 +.names N_347.BLIF N_347_i +0 1 +.names N_348.BLIF N_348_i +0 1 +.names N_347_i.BLIF N_348_i.BLIF N_178_i +11 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 +1- 1 +-1 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +pos_clk_un5_bgack_030_int_d_i_n +11 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_8 +1- 1 +-1 1 +.names pos_clk_un23_bgack_030_int_i_1_0_1_n.BLIF \ +pos_clk_un23_bgack_030_int_i_1_0_2_n.BLIF pos_clk_un23_bgack_030_int_i_1_0_n +11 1 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i +0 1 +.names CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_148_0 +11 1 +.names N_341.BLIF N_341_i +0 1 +.names N_338.BLIF N_338_i +0 1 +.names N_339.BLIF N_339_i +0 1 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 +1- 1 +-1 1 +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 +1- 1 +-1 1 +.names N_336.BLIF N_336_i +0 1 +.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF N_24 +1- 1 +-1 1 +.names N_122_0_1.BLIF SM_AMIGA_i_7_.BLIF N_122_0 +11 1 +.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF N_25 +1- 1 +-1 1 +.names N_211.BLIF N_211_i +0 1 +.names N_332.BLIF N_332_i +0 1 +.names N_331.BLIF N_331_i +0 1 +.names N_120_0_1.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF N_120_0 +11 1 +.names N_330.BLIF N_330_i +0 1 +.names N_330_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF \ +pos_clk_ds_000_dma_4_0_n +11 1 +.names N_329.BLIF N_329_i +0 1 +.names N_329_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names N_328.BLIF N_328_i +0 1 +.names N_328_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names N_325.BLIF N_325_i +0 1 +.names N_327.BLIF N_327_i +0 1 +.names N_325_i.BLIF N_327_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names N_320.BLIF N_320_i +0 1 +.names CLK_030_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF N_298_0 +11 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_295_0 +11 1 +.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_294_0 +11 1 +.names N_319.BLIF N_319_i +0 1 +.names N_207.BLIF N_319_i.BLIF un1_amiga_bus_enable_dma_high_0_0__n +11 1 +.names N_206.BLIF N_206_i +0 1 +.names N_283.BLIF N_283_i +0 1 +.names N_122_0.BLIF N_122 +0 1 +.names N_281.BLIF N_281_i +0 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 +.names N_282.BLIF N_282_i +0 1 +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +0 1 .names N_3.BLIF N_3_i 0 1 .names N_3_i.BLIF RST_c.BLIF N_49_0 @@ -1094,558 +1251,464 @@ pos_clk_un8_sm_amiga_i_n 0 1 .names N_8_i.BLIF RST_c.BLIF N_45_0 11 1 -.names N_17.BLIF N_17_i +.names pos_clk_un23_bgack_030_int_i_1_0_n.BLIF \ +pos_clk_un23_bgack_030_int_i_1_n 0 1 -.names N_17_i.BLIF RST_c.BLIF N_42_0 -11 1 .names N_19.BLIF N_19_i 0 1 +.names N_292_0.BLIF N_292 +0 1 .names N_19_i.BLIF RST_c.BLIF N_40_0 11 1 +.names N_294_0.BLIF N_294 +0 1 .names N_20.BLIF N_20_i 0 1 -.names N_123_0.BLIF N_123 +.names N_295_0.BLIF N_295 0 1 .names N_20_i.BLIF RST_c.BLIF N_39_0 11 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n +.names N_296_0.BLIF N_296 0 1 -.names N_21.BLIF N_21_i +.names N_24.BLIF N_24_i 0 1 -.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n +.names N_298_0.BLIF N_298 0 1 -.names N_21_i.BLIF RST_c.BLIF N_38_0 +.names N_24_i.BLIF RST_c.BLIF N_35_0 11 1 -.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_209 -11 1 -.names N_22.BLIF N_22_i +.names N_120_0.BLIF N_120 0 1 -.names N_22_i.BLIF RST_c.BLIF N_37_0 -11 1 .names N_25.BLIF N_25_i 0 1 +.names N_148_0.BLIF N_148 +0 1 .names N_25_i.BLIF RST_c.BLIF N_34_0 11 1 -.names N_217_i.BLIF N_217 +.names N_149_i.BLIF N_149 0 1 -.names N_26.BLIF N_26_i +.names sm_amiga_i_i_7__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_194_0_1 +11 1 +.names N_157_i.BLIF N_157 0 1 -.names N_26_i.BLIF RST_c.BLIF N_33_0 +.names N_215_i.BLIF N_217_i.BLIF N_237_i_1 11 1 -.names N_61_0.BLIF N_61 +.names N_172_i.BLIF N_172 0 1 -.names BG_030_c.BLIF BG_030_c_i +.names N_219_i.BLIF RST_c.BLIF N_237_i_2 +11 1 +.names N_176_i.BLIF N_176 0 1 -.names CLK_000_NE_i.BLIF RST_c.BLIF N_127 +.names N_220_i.BLIF RST_c.BLIF N_238_i_1 11 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +.names N_178_i.BLIF N_178 0 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n +.names N_221_i.BLIF N_222_i.BLIF N_238_i_2 11 1 -.names N_80_0.BLIF N_80 +.names N_181_i.BLIF N_181 0 1 -.names N_193_i.BLIF sm_amiga_i_i_7__n.BLIF N_289_0_1 +.names N_185_i.BLIF N_223_i.BLIF N_144_i_1 11 1 -.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_349_i.BLIF un1_SM_AMIGA_5_i_1 -11 1 -.names N_90_0.BLIF N_90 +.names N_184_0.BLIF N_184 0 1 -.names N_194_i.BLIF SM_AMIGA_i_7_.BLIF un1_SM_AMIGA_5_i_2 +.names N_224_i.BLIF N_225_i.BLIF N_144_i_2 11 1 -.names N_96_0.BLIF N_96 +.names N_144_i_1.BLIF N_144_i_2.BLIF N_144_i_3 +11 1 +.names N_196_0.BLIF N_196 0 1 -.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un8_sm_amiga_i_1_n +.names N_227_i.BLIF N_228_i.BLIF N_136_i_1 11 1 -.names N_99_0.BLIF N_99 +.names N_197_0.BLIF N_197 0 1 -.names N_182_i.BLIF VMA_INT_i.BLIF N_351_1 +.names N_343_i.BLIF RST_c.BLIF N_136_i_2 11 1 -.names N_119_0.BLIF N_119 -0 1 -.names VPA_D_i.BLIF cpu_est_i_1__n.BLIF N_351_2 -11 1 -.names N_124_0.BLIF N_124 -0 1 -.names AS_030_000_SYNC_i.BLIF N_148_i.BLIF N_168_i_1 -11 1 -.names N_138_0.BLIF N_138 -0 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_192_0_1 -11 1 -.names N_144_0.BLIF N_144 -0 1 -.names pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_345_i.BLIF N_192_0_2 -11 1 -.names N_158_i.BLIF N_158 -0 1 -.names N_323_i.BLIF N_324_i.BLIF N_137_i_1 -11 1 -.names N_168_i.BLIF N_168 -0 1 -.names N_347_i.BLIF RST_c.BLIF N_137_i_2 -11 1 -.names N_175_0.BLIF N_175 -0 1 -.names N_208_0.BLIF N_312_i.BLIF N_145_i_1 -11 1 -.names N_182_i.BLIF N_182 -0 1 -.names N_313_i.BLIF N_316_i.BLIF N_145_i_2 -11 1 -.names N_185_i.BLIF N_185 -0 1 -.names N_145_i_1.BLIF N_145_i_2.BLIF N_145_i_3 -11 1 -.names N_187_i.BLIF N_187 -0 1 -.names N_242_i.BLIF N_254_i.BLIF N_260_i_1 -11 1 -.names N_188_0.BLIF N_188 -0 1 -.names N_266_i.BLIF N_267_i.BLIF N_260_i_2 -11 1 -.names N_192_0.BLIF N_192 -0 1 -.names N_240_i.BLIF N_241_i.BLIF N_259_i_1 -11 1 -.names N_193_i.BLIF N_193 -0 1 -.names N_242_i.BLIF N_246_i.BLIF N_259_i_2 -11 1 -.names N_197_i.BLIF N_197 -0 1 -.names inst_CLK_000_NE.BLIF N_361.BLIF N_336_1 -11 1 -.names N_201_i.BLIF N_201 -0 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_336_2 -11 1 -.names N_204_0.BLIF N_204 -0 1 -.names inst_CLK_000_PE.BLIF cpu_est_i_0__n.BLIF N_332_1 -11 1 -.names N_206_0.BLIF N_206 -0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_332_2 -11 1 -.names N_207_0.BLIF N_207 -0 1 -.names N_332_1.BLIF N_332_2.BLIF N_332_3 -11 1 -.names N_168.BLIF N_194_i.BLIF N_317_1 -11 1 -.names N_211_0.BLIF N_211 -0 1 -.names N_196_i.BLIF N_197_i.BLIF N_317_2 -11 1 -.names N_212_0.BLIF N_212 -0 1 -.names N_317_1.BLIF N_317_2.BLIF N_317_3 -11 1 -.names N_290_0.BLIF N_290 -0 1 -.names inst_CLK_000_NE_D0.BLIF N_201.BLIF N_304_1 -11 1 -.names N_216_0.BLIF N_216 -0 1 -.names RST_c.BLIF SM_AMIGA_3_.BLIF N_304_2 -11 1 -.names N_219_0.BLIF N_219 -0 1 -.names AS_030_D0_i.BLIF a_c_20__n.BLIF un5_ciin_1 -11 1 -.names N_220_0.BLIF N_220 -0 1 -.names a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2 -11 1 -.names N_221_0.BLIF N_221 -0 1 -.names a_c_23__n.BLIF a_i_24__n.BLIF un5_ciin_3 -11 1 -.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_227 +.names sm_amiga_srsts_i_0_0_m2_5__un1_n.BLIF \ +sm_amiga_srsts_i_0_0_m2_5__un0_n.BLIF N_206 1- 1 -1 1 -.names a_i_25__n.BLIF a_i_26__n.BLIF un5_ciin_4 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_176_i_1 +11 1 +.names un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF N_207 +1- 1 +-1 1 +.names AS_030_000_SYNC_i.BLIF CLK_000_N_SYNC_0_.BLIF N_146_0_1 11 1 .names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF \ -N_229 +N_211 1- 1 -1 1 -.names a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5 +.names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n 11 1 -.names sm_amiga_srsts_i_0_m2_5__un1_n.BLIF sm_amiga_srsts_i_0_m2_5__un0_n.BLIF \ -N_230 -1- 1 --1 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6 +.names N_215_1.BLIF rst_dly_i_2__n.BLIF N_215 11 1 -.names N_188.BLIF SM_AMIGA_1_.BLIF N_236 +.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 11 1 -.names un5_ciin_1.BLIF un5_ciin_2.BLIF un5_ciin_7 +.names N_222_1.BLIF rst_dly_i_1__n.BLIF N_222 11 1 -.names N_240_1.BLIF rst_dly_i_2__n.BLIF N_240 +.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 11 1 -.names un5_ciin_3.BLIF un5_ciin_4.BLIF un5_ciin_8 +.names N_224_1.BLIF clk_000_p_sync_i_10__n.BLIF N_224 11 1 -.names N_144.BLIF N_187_i.BLIF N_241 +.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 11 1 -.names un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9 +.names N_225_1.BLIF clk_000_n_sync_i_12__n.BLIF N_225 11 1 -.names N_217.BLIF RST_i.BLIF N_242 +.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 11 1 -.names un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10 +.names N_196.BLIF sm_amiga_i_3__n.BLIF N_227 11 1 -.names N_127.BLIF rst_dly_i_2__n.BLIF N_246 +.names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 11 1 -.names un5_ciin_9.BLIF a_i_30__n.BLIF un5_ciin_11 +.names N_228_1.BLIF sm_amiga_i_4__n.BLIF N_228 11 1 -.names N_144.BLIF N_158_i.BLIF N_254 +.names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 +11 1 +.names N_236_1.BLIF cpu_est_i_3__n.BLIF N_236 +11 1 +.names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 +11 1 +.names N_277_1.BLIF SM_AMIGA_2_.BLIF N_277 +11 1 +.names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 +11 1 +.names N_187.BLIF sm_amiga_i_5__n.BLIF N_281 +11 1 +.names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 +11 1 +.names clk_000_n_sync_i_12__n.BLIF sm_amiga_i_4__n.BLIF N_282 +11 1 +.names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 +11 1 +.names N_191.BLIF sm_amiga_i_6__n.BLIF N_283 +11 1 +.names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 +11 1 +.names N_285_1.BLIF cpu_est_i_3__n.BLIF N_285 +11 1 +.names N_157_i.BLIF VMA_INT_i.BLIF N_347_1 +11 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_318 +11 1 +.names VPA_D_i.BLIF cpu_est_i_1__n.BLIF N_347_2 +11 1 +.names N_319_1.BLIF SM_AMIGA_0_.BLIF N_319 +11 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_1_n +11 1 +.names CLK_030_H_i.BLIF N_197.BLIF N_320 +11 1 +.names pos_clk_un23_bgack_030_int_i_0_x2.BLIF N_341_i.BLIF \ +pos_clk_un23_bgack_030_int_i_1_0_2_n +11 1 +.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_321 +11 1 +.names FPU_SENSE_i.BLIF N_366.BLIF un21_fpu_cs_1 +11 1 +.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_322 11 1 .names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 11 1 -.names N_266_1.BLIF rst_dly_i_1__n.BLIF N_266 +.names AS_030_i.BLIF RST_c.BLIF N_323 11 1 -.names FPU_SENSE_i.BLIF N_375.BLIF un21_fpu_cs_1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_366_1 11 1 -.names N_127.BLIF rst_dly_i_1__n.BLIF N_267 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_325 11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_375_1 +.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_366_2 11 1 -.names A1_i.BLIF BGACK_030_INT_i.BLIF N_275 +.names N_327_1.BLIF RW_000_c.BLIF N_327 11 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF N_375_2 +.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_366_3 11 1 -.names N_219.BLIF sm_amiga_i_0__n.BLIF N_277 +.names BGACK_030_INT_i.BLIF N_181.BLIF N_328 11 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF N_375_3 +.names N_366_1.BLIF N_366_2.BLIF N_366_4 11 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_278 +.names BGACK_030_INT_i.BLIF N_181_i.BLIF N_329 11 1 -.names N_375_1.BLIF N_375_2.BLIF N_375_4 -11 1 -.names N_297_1.BLIF RW_000_c.BLIF N_297 -11 1 -.names AS_000_i.BLIF N_210_0.BLIF N_134_i_1 -11 1 -.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_300 -11 1 -.names N_192_0.BLIF N_331_i.BLIF N_96_0_1 -11 1 -.names N_212.BLIF sm_amiga_i_2__n.BLIF N_301 -11 1 -.names N_192_0.BLIF N_328_i.BLIF N_83_i_1 -11 1 -.names N_303_1.BLIF SM_AMIGA_2_.BLIF N_303 -11 1 -.names N_242_i.BLIF N_321_i.BLIF N_261_i_1 -11 1 -.names N_304_1.BLIF N_304_2.BLIF N_304 -11 1 -.names N_230.BLIF N_310_i.BLIF N_141_i_1 -11 1 -.names N_218.BLIF sm_amiga_i_5__n.BLIF N_305 -11 1 -.names N_305_i.BLIF N_307_i.BLIF N_139_i_1 -11 1 -.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_307 -11 1 -.names N_229.BLIF N_301_i.BLIF N_133_i_1 -11 1 -.names N_211.BLIF sm_amiga_i_6__n.BLIF N_310 -11 1 -.names N_300_i.BLIF sm_amiga_i_5__n.BLIF N_123_0_1 -11 1 -.names N_290.BLIF N_347.BLIF N_312 -11 1 -.names pos_clk_CYCLE_DMA_5_0_i_x2.BLIF AS_000_i.BLIF N_282_i_1 -11 1 -.names N_313_1.BLIF CLK_000_PE_i.BLIF N_313 -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_343_1 -11 1 -.names N_316_1.BLIF CLK_000_NE_i.BLIF N_316 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_339_1 -11 1 -.names N_317_3.BLIF sm_amiga_i_3__n.BLIF N_317 -11 1 -.names inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n -11 1 -.names N_216.BLIF RESET_OUT_i.BLIF N_320 -11 1 -.names N_168_i.BLIF RST_c.BLIF N_326_1 -11 1 -.names N_144.BLIF RST_DLY_0_.BLIF N_321 -11 1 -.names N_206.BLIF RST_c.BLIF N_325_1 -11 1 -.names N_127.BLIF rst_dly_i_0__n.BLIF N_322 -11 1 -.names inst_CLK_000_NE_D0.BLIF N_201.BLIF N_324_1 -11 1 -.names N_220.BLIF sm_amiga_i_3__n.BLIF N_323 -11 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names N_197.BLIF BERR_i.BLIF N_316_1 -11 1 -.names N_324_1.BLIF sm_amiga_i_4__n.BLIF N_324 -11 1 -.names N_204.BLIF BERR_i.BLIF N_313_1 -11 1 -.names N_325_1.BLIF SM_AMIGA_6_.BLIF N_325 -11 1 -.names N_207.BLIF RST_c.BLIF N_303_1 -11 1 -.names N_326_1.BLIF sm_amiga_i_i_7__n.BLIF N_326 -11 1 -.names AS_000_i.BLIF N_222_i.BLIF N_297_1 -11 1 -.names CLK_030_H_i.BLIF N_221.BLIF N_328 -11 1 -.names N_217_i.BLIF rst_dly_i_0__n.BLIF N_266_1 +.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_163_i.BLIF un1_SM_AMIGA_5_i_1 11 1 .names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_330 11 1 -.names N_24.BLIF N_24_i -0 1 -.names N_158.BLIF N_217_i.BLIF N_240_1 +.names N_346_i.BLIF sm_amiga_i_0__n.BLIF un1_SM_AMIGA_5_i_2 11 1 .names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_331 11 1 -.names N_24_i.BLIF RST_c.BLIF N_35_0 +.names N_163.BLIF N_334_i.BLIF N_142_i_1 11 1 -.names N_215_i.BLIF N_213_i.BLIF pos_clk_ipl_1_n +.names N_190.BLIF sm_amiga_i_2__n.BLIF N_332 11 1 -.names N_332_3.BLIF cpu_est_i_3__n.BLIF N_332 +.names N_335_i.BLIF RST_c.BLIF N_142_i_2 11 1 -.names N_18.BLIF N_18_i +.names CLK_000_P_SYNC_10_.BLIF SM_AMIGA_0_.BLIF N_336 +11 1 +.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_0__n.BLIF N_339_1 +11 1 +.names N_141.BLIF RST_DLY_0_.BLIF N_338 +11 1 +.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_280_1 +11 1 +.names N_339_1.BLIF RST_c.BLIF N_339 +11 1 +.names RST_c.BLIF SM_AMIGA_3_.BLIF N_280_2 +11 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_341 +11 1 +.names CLK_000_N_SYNC_12_.BLIF N_357.BLIF N_231_1 +11 1 +.names N_344_1.BLIF clk_000_d_i_10__n.BLIF N_344 +11 1 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_231_2 +11 1 +.names N_347_1.BLIF N_347_2.BLIF N_347 +11 1 +.names CLK_000_P_SYNC_10_.BLIF cpu_est_i_0__n.BLIF N_230_1 +11 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_348 +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_230_2 +11 1 +.names N_230_1.BLIF N_230_2.BLIF N_230_3 +11 1 +.names N_146.BLIF N_172_i.BLIF N_226_1 +11 1 +.names N_176_i.BLIF sm_amiga_i_0__n.BLIF N_226_2 +11 1 +.names N_226_1.BLIF N_226_2.BLIF N_226_3 +11 1 +.names N_199_0.BLIF N_199 0 1 -.names N_193.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names N_336_1.BLIF N_336_2.BLIF N_336 +.names N_338_i.BLIF N_339_i.BLIF N_239_i_1 11 1 -.names N_18_i.BLIF RST_c.BLIF N_41_0 +.names N_199.BLIF sm_amiga_i_0__n.BLIF N_324 11 1 -.names N_276_i.BLIF N_193.BLIF amiga_bus_enable_dma_low_0_un1_n +.names N_336_i.BLIF sm_amiga_i_5__n.BLIF N_122_0_1 11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_338 -11 1 -.names N_10.BLIF N_10_i -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names N_339_1.BLIF cpu_est_i_3__n.BLIF N_339 -11 1 -.names N_10_i.BLIF RST_c.BLIF N_43_0 -11 1 -.names N_123.BLIF rw_000_int_0_un3_n -0 1 -.names N_185.BLIF cpu_est_2_.BLIF N_340 -11 1 -.names N_7.BLIF N_7_i -0 1 -.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_123.BLIF rw_000_int_0_un1_n -11 1 -.names N_185_i.BLIF cpu_est_2_.BLIF N_341 -11 1 -.names N_7_i.BLIF RST_c.BLIF N_46_0 -11 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n -11 1 -.names N_181_i.BLIF cpu_est_i_1__n.BLIF N_342 -11 1 -.names N_5.BLIF N_5_i -0 1 -.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names N_343_1.BLIF cpu_est_i_3__n.BLIF N_343 -11 1 -.names N_5_i.BLIF RST_c.BLIF N_47_0 -11 1 -.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n -11 1 -.names inst_CLK_000_NE.BLIF N_217_i.BLIF N_344 -11 1 -.names N_4.BLIF N_4_i -0 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ -bgack_030_int_0_un0_n -11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_345 -11 1 -.names N_4_i.BLIF RST_c.BLIF N_48_0 -11 1 -.names N_279.BLIF as_030_000_sync_0_un3_n -0 1 -.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_347 -11 1 -.names N_272.BLIF N_272_i -0 1 -.names inst_AS_030_000_SYNC.BLIF N_279.BLIF as_030_000_sync_0_un1_n -11 1 -.names CLK_000_N_SYNC_9_.BLIF N_175.BLIF N_350 -11 1 -.names N_271.BLIF N_271_i -0 1 -.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 -.names N_351_1.BLIF N_351_2.BLIF N_351 -11 1 -.names N_271_i.BLIF N_272_i.BLIF N_279_0 -11 1 -.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n -0 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_353 -11 1 -.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_280_0 -11 1 -.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF \ -ds_000_enable_0_un1_n -11 1 -.names N_185_i.BLIF cpu_est_i_2__n.BLIF N_361 -11 1 -.names N_236_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_281_0 -11 1 -.names un1_SM_AMIGA_5_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n -11 1 -.names N_298.BLIF N_298_i -0 1 -.names N_280.BLIF as_000_int_0_un3_n -0 1 -.names N_298_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n -11 1 -.names sm_amiga_i_5__n.BLIF N_280.BLIF as_000_int_0_un1_n -11 1 -.names N_299.BLIF N_299_i -0 1 -.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 -.names N_299_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n -11 1 -.names N_281.BLIF dsack1_int_0_un3_n -0 1 .names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 11 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i +.names N_211_i.BLIF N_332_i.BLIF N_132_i_1 11 1 -.names N_236_i.BLIF N_281.BLIF dsack1_int_0_un1_n +.names N_366_4.BLIF N_366_3.BLIF N_366 11 1 -.names N_375_4.BLIF N_375_3.BLIF N_375 +.names N_331_i.BLIF RW_000_i.BLIF N_120_0_1 11 1 -.names N_358.BLIF N_358_i +.names N_137.BLIF SM_AMIGA_i_7_.BLIF N_335 +11 1 +.names N_320_i.BLIF RST_c.BLIF N_106_i_1 +11 1 +.names CLK_000_P_SYNC_10_.BLIF CYCLE_DMA_0_.BLIF N_208 +11 1 +.names AS_000_i.BLIF N_186_0.BLIF N_103_i_1 +11 1 +.names N_203_i.BLIF N_203 0 1 -.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +.names AS_000_i.BLIF N_186_0.BLIF N_92_i_1 11 1 -.names N_218_0.BLIF N_218 +.names N_187_0.BLIF N_187 0 1 -.names BGACK_000_c.BLIF N_358_i.BLIF pos_clk_un6_bgack_000_0_n +.names N_206_i.BLIF N_283_i.BLIF N_140_i_1 11 1 -.names N_286.BLIF size_dma_0_1__un3_n +.names N_137_i.BLIF N_137 0 1 -.names N_156_i.BLIF N_156 +.names N_281_i.BLIF N_282_i.BLIF N_138_i_1 +11 1 +.names N_137.BLIF SM_AMIGA_0_.BLIF N_349 +11 1 +.names N_148.BLIF CLK_000_D_11_.BLIF N_344_1 +11 1 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n 0 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_284_i +.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n 11 1 -.names pos_clk_size_dma_6_1__n.BLIF N_286.BLIF size_dma_0_1__un1_n +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_10 +1- 1 +-1 1 +.names AS_000_i.BLIF N_200_i.BLIF N_327_1 11 1 -.names N_289_0.BLIF N_289 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_5 +1- 1 +-1 1 +.names inst_BGACK_030_INTreg.BLIF CLK_000_c.BLIF N_319_1 +11 1 +.names N_293_0.BLIF N_293 0 1 -.names N_222_i.BLIF inst_RESET_OUT.BLIF N_285_i +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_285_1 11 1 -.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n -11 1 -.names N_156.BLIF SM_AMIGA_0_.BLIF N_354 -11 1 -.names N_193_i.BLIF RST_c.BLIF N_286_0 -11 1 -.names N_286.BLIF size_dma_0_0__un3_n -0 1 -.names N_205_i.BLIF N_205 -0 1 -.names AS_030_i.BLIF RST_c.BLIF N_88_0 -11 1 -.names pos_clk_size_dma_6_0__n.BLIF N_286.BLIF size_dma_0_0__un1_n +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6 +1- 1 +-1 1 +.names N_184.BLIF RST_c.BLIF N_277_1 11 1 .names un1_SM_AMIGA_5_i.BLIF un1_SM_AMIGA_5 0 1 -.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_236_1 11 1 -.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +.names pos_clk_un3_as_030_d0_i_n.BLIF un1_SM_AMIGA_5.BLIF \ +DS_000_ENABLE_1_sqmuxa_1 11 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa +.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_228_1 11 1 -.names BERR_c.BLIF CLK_000_PE_i.BLIF N_156_i -11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n -0 1 -.names CLK_000_PE_i.BLIF SM_AMIGA_4_.BLIF N_349 -11 1 -.names N_349.BLIF N_349_i -0 1 -.names BERR_c.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_7 +1- 1 +-1 1 +.names N_172.BLIF BERR_i.BLIF N_225_1 11 1 .names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n 0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_194_i -11 1 -.names inst_CLK_000_PE.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF \ -sm_amiga_srsts_i_0_m2_1__un0_n -11 1 -.names N_286_0.BLIF N_286 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c 0 1 -.names un1_SM_AMIGA_5_i_1.BLIF un1_SM_AMIGA_5_i_2.BLIF un1_SM_AMIGA_5_i +.names N_176.BLIF BERR_i.BLIF N_224_1 11 1 -.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n +.names N_290_0.BLIF N_290 0 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +.names N_216_i.BLIF rst_dly_i_0__n.BLIF N_222_1 +11 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_18 +1- 1 +-1 1 +.names N_149.BLIF N_216_i.BLIF N_215_1 +11 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa +11 1 +.names N_214_i.BLIF N_212_i.BLIF pos_clk_ipl_1_n +11 1 +.names N_194.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_232 +11 1 +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n 0 1 -.names UDS_000_c.BLIF UDS_000_c_i +.names N_194_0.BLIF N_194 0 1 -.names sm_amiga_i_i_7__n.BLIF inst_BGACK_030_INTreg.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un1_n -11 1 -.names AS_000_c.BLIF inst_CLK_000_PE.BLIF N_358 -11 1 -.names LDS_000_c.BLIF LDS_000_c_i +.names BG_030_c.BLIF BG_030_c_i 0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un0_n +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n 11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +.names N_366.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_233 +11 1 +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n 0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_205_i +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_m2_5__un3_n +.names N_153.BLIF SM_AMIGA_1_.BLIF N_275 +11 1 +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n +11 1 +.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n 0 1 -.names BGACK_030_INT_i.BLIF N_205_i.BLIF N_299 -11 1 -.names N_156.BLIF SM_AMIGA_i_7_.BLIF N_206_0 -11 1 -.names BERR_c.BLIF SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_m2_5__un1_n -11 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +.names N_153_0.BLIF N_153 0 1 -.names N_156.BLIF sm_amiga_i_3__n.BLIF N_207_0 -11 1 -.names inst_CLK_000_PE.BLIF sm_amiga_srsts_i_0_m2_5__un3_n.BLIF \ -sm_amiga_srsts_i_0_m2_5__un0_n -11 1 -.names BGACK_030_INT_i.BLIF N_205.BLIF N_298 -11 1 -.names N_354.BLIF N_354_i +.names N_26.BLIF N_26_i 0 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n -0 1 -.names N_281_0.BLIF N_281 -0 1 -.names N_354_i.BLIF RST_c.BLIF N_208_0 +.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n 11 1 -.names cpu_est_2_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n +.names N_191_0.BLIF N_191 +0 1 +.names N_26_i.BLIF RST_c.BLIF N_33_0 +11 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names N_146.BLIF sm_amiga_i_6__n.BLIF N_334 +11 1 +.names N_21.BLIF N_21_i +0 1 +.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n +0 1 +.names N_146_0.BLIF N_146 +0 1 +.names N_21_i.BLIF RST_c.BLIF N_38_0 +11 1 +.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n +11 1 +.names CLK_000_D_12_.BLIF clk_000_d_i_11__n.BLIF N_345 +11 1 +.names N_17.BLIF N_17_i +0 1 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names clk_000_p_sync_i_10__n.BLIF SM_AMIGA_4_.BLIF N_346 +11 1 +.names N_17_i.BLIF RST_c.BLIF N_42_0 +11 1 +.names N_258.BLIF dsack1_int_0_un3_n +0 1 +.names N_163_i.BLIF N_163 +0 1 +.names N_4.BLIF N_4_i +0 1 +.names N_275_i.BLIF N_258.BLIF dsack1_int_0_un1_n +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_22 +1- 1 +-1 1 +.names N_4_i.BLIF RST_c.BLIF N_48_0 +11 1 +.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +11 1 +.names pos_clk_un4_clk_000_pe_0_n.BLIF pos_clk_un4_clk_000_pe_n +0 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n +0 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_51_0 +11 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +11 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_235 +11 1 +.names ipl_c_1__n.BLIF ipl_c_i_1__n +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names N_154_i.BLIF cpu_est_i_1__n.BLIF N_284 +11 1 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_52_0 +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names N_190_0.BLIF N_190 +0 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n +0 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names N_195.BLIF RESET_OUT_i.BLIF N_337 +11 1 +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_53_0 +11 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names N_195_0.BLIF N_195 +0 1 +.names N_27.BLIF N_27_i +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names CLK_000_N_SYNC_12_.BLIF N_166.BLIF N_340 +11 1 +.names N_27_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names N_231_1.BLIF N_231_2.BLIF N_231 +11 1 +.names N_28.BLIF N_28_i +0 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names N_230_3.BLIF cpu_est_i_3__n.BLIF N_230 +11 1 +.names N_28_i.BLIF RST_c.BLIF N_31_0 +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n +0 1 +.names N_280_1.BLIF N_280_2.BLIF N_280 +11 1 +.names N_29.BLIF N_29_i +0 1 +.names N_291.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n 11 1 .names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_134 01 1 @@ -1662,23 +1725,22 @@ sm_amiga_srsts_i_0_m2_5__un0_n 10 1 11 0 00 0 -.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ -pos_clk_un23_bgack_030_int_i_i_a4_i_x2 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF pos_clk_un23_bgack_030_int_i_0_x2 01 1 10 1 11 0 00 0 -.names CYCLE_DMA_0_.BLIF inst_CLK_000_PE.BLIF pos_clk_CYCLE_DMA_5_0_i_x2 +.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_x2_0_ 01 1 10 1 11 0 00 0 -.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_ +.names CYCLE_DMA_0_.BLIF CLK_000_P_SYNC_10_.BLIF pos_clk_CYCLE_DMA_5_0_i_x2 01 1 10 1 11 0 00 0 -.names CYCLE_DMA_1_.BLIF N_209.BLIF pos_clk_CYCLE_DMA_5_1_i_x2 +.names CYCLE_DMA_1_.BLIF N_208.BLIF pos_clk_CYCLE_DMA_5_1_i_x2 01 1 10 1 11 0 @@ -1710,7 +1772,7 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names vcc_n_n.BLIF AVEC 1 1 0 0 -.names N_124.BLIF E +.names N_292.BLIF E 1 1 0 0 .names inst_VMA_INTreg.BLIF VMA @@ -1728,10 +1790,10 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_227.BLIF AMIGA_BUS_ENABLE_HIGH +.names un1_amiga_bus_enable_dma_high_0__n.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 0 0 -.names un5_ciin.BLIF CIIN +.names un10_ciin.BLIF CIIN 1 1 0 0 .names IPL_030DFF_1_reg.BLIF IPL_030_1_ @@ -1740,6 +1802,15 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -1755,6 +1826,12 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 0 0 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_3_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C 1 1 0 0 @@ -1773,13 +1850,28 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF IPL_D0_2_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C +1 1 +0 0 +.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C +1 1 +0 0 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C 1 1 0 0 .names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D @@ -1794,6 +1886,12 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C 1 1 0 0 +.names CLK_000_N_SYNC_11_.BLIF CLK_000_N_SYNC_12_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_12_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C 1 1 0 0 @@ -1806,7 +1904,7 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF SIZE_DMA_1_.C 1 1 0 0 -.names cpu_est_0_0_x2_0_.BLIF cpu_est_0_.D +.names cpu_est_0_0_x2_0_x2_0_.BLIF cpu_est_0_.D 1 1 0 0 .names CLK_OSZI_c.BLIF cpu_est_0_.C @@ -1815,10 +1913,22 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_2_.C +.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_3_.C +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C +1 1 +0 0 +.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C +1 1 +0 0 +.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C 1 1 0 0 .names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D @@ -1851,7 +1961,10 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C 1 1 0 0 -.names N_148_i.BLIF CLK_000_N_SYNC_0_.D +.names CLK_000_P_SYNC_9_.BLIF CLK_000_P_SYNC_10_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_10_.C 1 1 0 0 .names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C @@ -1887,37 +2000,7 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C 1 1 0 0 -.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C -1 1 -0 0 -.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C -1 1 -0 0 -.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C -1 1 -0 0 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF RST_DLY_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF RST_DLY_2_.C -1 1 -0 0 -.names CLK_000.BLIF CLK_000_D_0_.D +.names CLK_000_c.BLIF CLK_000_D_0_.D 1 1 0 0 .names CLK_OSZI_c.BLIF CLK_000_D_0_.C @@ -1929,6 +2012,72 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF CLK_000_D_1_.C 1 1 0 0 +.names CLK_000_D_1_.BLIF CLK_000_D_2_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_2_.C +1 1 +0 0 +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_3_.C +1 1 +0 0 +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_4_.C +1 1 +0 0 +.names CLK_000_D_4_.BLIF CLK_000_D_5_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_5_.C +1 1 +0 0 +.names CLK_000_D_5_.BLIF CLK_000_D_6_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_6_.C +1 1 +0 0 +.names CLK_000_D_6_.BLIF CLK_000_D_7_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_7_.C +1 1 +0 0 +.names CLK_000_D_7_.BLIF CLK_000_D_8_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_8_.C +1 1 +0 0 +.names CLK_000_D_8_.BLIF CLK_000_D_9_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_9_.C +1 1 +0 0 +.names CLK_000_D_9_.BLIF CLK_000_D_10_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_10_.C +1 1 +0 0 +.names CLK_000_D_10_.BLIF CLK_000_D_11_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_11_.C +1 1 +0 0 +.names CLK_000_D_11_.BLIF CLK_000_D_12_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_12_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C 1 1 0 0 @@ -1938,46 +2087,13 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C 1 1 0 0 -.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C -1 1 -0 0 -.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C -1 1 -0 0 -.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF RST_DLY_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +.names CLK_OSZI_c.BLIF RST_DLY_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_D0.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_nEXP_SPACE_D0reg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_VPA_D.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +.names CLK_OSZI_c.BLIF RST_DLY_2_.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_030_H.C @@ -1989,15 +2105,6 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C 1 1 0 0 -.names CLK_OSZI_c.BLIF BG_000DFFreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 0 0 @@ -2025,15 +2132,42 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C 1 1 0 0 -.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D +.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF BG_000DFFreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 +0 0 +.names CLK_000_N_SYNC_12_.BLIF inst_CLK_000_NE_D0.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C +1 1 +0 0 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D 1 1 0 0 @@ -2046,25 +2180,16 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 0 0 -.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_000_PE.C -1 1 -0 0 -.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C 1 1 0 0 .names un3_size.BLIF SIZE_1_ 1 1 0 0 -.names N_138.BLIF AS_030 +.names gnd_n_n.BLIF AHIGH_31_ +1 1 +0 0 +.names un6_as_030_i.BLIF AS_030 1 1 0 0 .names un4_as_000_i.BLIF AS_000 @@ -2079,9 +2204,6 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names un4_lds_000_i.BLIF LDS_000 1 1 0 0 -.names inst_A0_DMA.BLIF A0 -1 1 -0 0 .names gnd_n_n.BLIF BERR 1 1 0 0 @@ -2091,46 +2213,70 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names un4_size.BLIF SIZE_0_ 1 1 0 0 -.names A_15_.BLIF a_15__n +.names gnd_n_n.BLIF AHIGH_30_ 1 1 0 0 -.names A_14_.BLIF a_14__n +.names gnd_n_n.BLIF AHIGH_29_ 1 1 0 0 -.names A_13_.BLIF a_13__n +.names gnd_n_n.BLIF AHIGH_28_ 1 1 0 0 -.names A_12_.BLIF a_12__n +.names gnd_n_n.BLIF AHIGH_27_ 1 1 0 0 -.names A_11_.BLIF a_11__n +.names gnd_n_n.BLIF AHIGH_26_ 1 1 0 0 -.names A_10_.BLIF a_10__n +.names gnd_n_n.BLIF AHIGH_25_ 1 1 0 0 -.names A_9_.BLIF a_9__n +.names gnd_n_n.BLIF AHIGH_24_ 1 1 0 0 -.names A_8_.BLIF a_8__n +.names inst_A0_DMA.BLIF A_0_ 1 1 0 0 -.names A_7_.BLIF a_7__n +.names A_DECODE_15_.BLIF a_decode_15__n 1 1 0 0 -.names A_6_.BLIF a_6__n +.names A_DECODE_14_.BLIF a_decode_14__n 1 1 0 0 -.names A_5_.BLIF a_5__n +.names A_DECODE_13_.BLIF a_decode_13__n 1 1 0 0 -.names A_4_.BLIF a_4__n +.names A_DECODE_12_.BLIF a_decode_12__n 1 1 0 0 -.names A_3_.BLIF a_3__n +.names A_DECODE_11_.BLIF a_decode_11__n 1 1 0 0 -.names A_2_.BLIF a_2__n +.names A_DECODE_10_.BLIF a_decode_10__n +1 1 +0 0 +.names A_DECODE_9_.BLIF a_decode_9__n +1 1 +0 0 +.names A_DECODE_8_.BLIF a_decode_8__n +1 1 +0 0 +.names A_DECODE_7_.BLIF a_decode_7__n +1 1 +0 0 +.names A_DECODE_6_.BLIF a_decode_6__n +1 1 +0 0 +.names A_DECODE_5_.BLIF a_decode_5__n +1 1 +0 0 +.names A_DECODE_4_.BLIF a_decode_4__n +1 1 +0 0 +.names A_DECODE_3_.BLIF a_decode_3__n +1 1 +0 0 +.names A_DECODE_2_.BLIF a_decode_2__n 1 1 0 0 .names AS_030.PIN.BLIF AS_030_c @@ -2154,58 +2300,58 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names SIZE_1_.PIN.BLIF size_c_1__n 1 1 0 0 -.names A_16_.BLIF a_c_16__n +.names AHIGH_24_.PIN.BLIF ahigh_c_24__n 1 1 0 0 -.names A_17_.BLIF a_c_17__n +.names AHIGH_25_.PIN.BLIF ahigh_c_25__n 1 1 0 0 -.names A_18_.BLIF a_c_18__n +.names AHIGH_26_.PIN.BLIF ahigh_c_26__n 1 1 0 0 -.names A_19_.BLIF a_c_19__n +.names AHIGH_27_.PIN.BLIF ahigh_c_27__n 1 1 0 0 -.names A_20_.BLIF a_c_20__n +.names AHIGH_28_.PIN.BLIF ahigh_c_28__n 1 1 0 0 -.names A_21_.BLIF a_c_21__n +.names AHIGH_29_.PIN.BLIF ahigh_c_29__n 1 1 0 0 -.names A_22_.BLIF a_c_22__n +.names AHIGH_30_.PIN.BLIF ahigh_c_30__n 1 1 0 0 -.names A_23_.BLIF a_c_23__n +.names AHIGH_31_.PIN.BLIF ahigh_c_31__n 1 1 0 0 -.names A_24_.BLIF a_c_24__n +.names A_DECODE_16_.BLIF a_decode_c_16__n 1 1 0 0 -.names A_25_.BLIF a_c_25__n +.names A_DECODE_17_.BLIF a_decode_c_17__n 1 1 0 0 -.names A_26_.BLIF a_c_26__n +.names A_DECODE_18_.BLIF a_decode_c_18__n 1 1 0 0 -.names A_27_.BLIF a_c_27__n +.names A_DECODE_19_.BLIF a_decode_c_19__n 1 1 0 0 -.names A_28_.BLIF a_c_28__n +.names A_DECODE_20_.BLIF a_decode_c_20__n 1 1 0 0 -.names A_29_.BLIF a_c_29__n +.names A_DECODE_21_.BLIF a_decode_c_21__n 1 1 0 0 -.names A_30_.BLIF a_c_30__n +.names A_DECODE_22_.BLIF a_decode_c_22__n 1 1 0 0 -.names A_31_.BLIF a_c_31__n +.names A_DECODE_23_.BLIF a_decode_c_23__n 1 1 0 0 -.names A0.PIN.BLIF A0_c +.names A_0_.PIN.BLIF a_c_0__n 1 1 0 0 -.names A1.BLIF A1_c +.names A_1_.BLIF a_c_1__n 1 1 0 0 .names nEXP_SPACE.BLIF nEXP_SPACE_c @@ -2223,6 +2369,9 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names CLK_030.BLIF CLK_030_c 1 1 0 0 +.names CLK_000.BLIF CLK_000_c +1 1 +0 0 .names CLK_OSZI.BLIF CLK_OSZI_c 1 1 0 0 @@ -2256,7 +2405,7 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names FC_1_.BLIF fc_c_1__n 1 1 0 0 -.names N_285_i.BLIF AS_030.OE +.names un3_as_030_i.BLIF AS_030.OE 1 1 0 0 .names un1_as_000_i.BLIF AS_000.OE @@ -2271,31 +2420,55 @@ pos_clk_un23_bgack_030_int_i_i_a4_i_x2 .names un1_as_000_i.BLIF LDS_000.OE 1 1 0 0 -.names N_222_i.BLIF SIZE_0_.OE +.names N_200_i.BLIF SIZE_0_.OE 1 1 0 0 -.names N_222_i.BLIF SIZE_1_.OE +.names N_200_i.BLIF SIZE_1_.OE 1 1 0 0 -.names N_285_i.BLIF A0.OE +.names un3_as_030_i.BLIF AHIGH_24_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF AHIGH_25_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF AHIGH_26_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF AHIGH_27_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF AHIGH_28_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF AHIGH_29_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF AHIGH_30_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF AHIGH_31_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF A_0_.OE 1 1 0 0 .names un22_berr.BLIF BERR.OE 1 1 0 0 -.names N_284_i.BLIF RW.OE +.names N_318.BLIF RW.OE 1 1 0 0 -.names N_285_i.BLIF DS_030.OE +.names un3_as_030_i.BLIF DS_030.OE 1 1 0 0 -.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE +.names nEXP_SPACE_c.BLIF DSACK1.OE 1 1 0 0 .names RESET_OUT_i.BLIF RESET.OE 1 1 0 0 -.names N_61.BLIF CIIN.OE +.names N_296.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index a115e41..520efcc 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,123 +1,197 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Wed Aug 17 17:45:46 2016 +#$ DATE Fri Aug 19 00:20:41 2016 #$ MODULE 68030_tk -#$ PINS 61 SIZE_1_ A_31_ IPL_030_2_ IPL_030_1_ IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ \ -# AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 nEXP_SPACE BERR BG_030 BG_000 \ -# BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE \ -# DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE SIZE_0_ AMIGA_BUS_DATA_DIR \ -# A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ \ -# A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ -#$ NODES 79 inst_BGACK_030_INTreg inst_VMA_INTreg N_317_i cpu_est_2_ cpu_est_3_ \ -# cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW \ -# inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D \ -# inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ \ -# inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 \ -# inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE \ -# CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ \ -# inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg \ -# SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ \ +#$ PINS 61 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ AHIGH_31_ \ +# A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ IPL_030_2_ IPL_2_ FC_1_ AS_030 \ +# AS_000 RW_000 DS_030 UDS_000 LDS_000 nEXP_SPACE A_0_ BERR IPL_030_1_ BG_030 IPL_030_0_ \ +# BG_000 IPL_1_ BGACK_030 IPL_0_ BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT \ +# CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE \ +# AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ \ +# AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ +#$ NODES 89 N_226 inst_BGACK_030_INTreg inst_VMA_INTreg cpu_est_2_ cpu_est_3_ \ +# cpu_est_0_ cpu_est_1_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 \ +# inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA \ +# CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT \ +# inst_LDS_000_INT inst_CLK_OUT_PRE_D CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 \ +# inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ CLK_000_P_SYNC_10_ \ +# SM_AMIGA_5_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ \ +# CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ \ +# SM_AMIGA_0_ inst_DSACK1_INTreg CLK_000_N_SYNC_0_ SM_AMIGA_4_ inst_DS_000_ENABLE \ +# CLK_000_N_SYNC_12_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ \ # CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ \ # CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ \ -# CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ \ +# CLK_000_P_SYNC_9_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ \ # CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ \ -# CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_RW_000_INT \ -# inst_RW_000_DMA inst_A0_DMA SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ \ -# SM_AMIGA_2_ SM_AMIGA_i_7_ BG_000DFFreg CLK_OUT_INTreg IPL_030DFF_0_reg \ -# IPL_030DFF_1_reg IPL_030DFF_2_reg +# CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_N_SYNC_11_ \ +# inst_RW_000_INT inst_RW_000_DMA inst_CLK_000_NE_D0 inst_AMIGA_BUS_ENABLE_DMA_HIGH \ +# inst_A0_DMA SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ \ +# SM_AMIGA_i_7_ BG_000DFFreg CLK_OUT_INTreg IPL_030DFF_0_reg IPL_030DFF_1_reg \ +# IPL_030DFF_2_reg .model bus68030 -.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ +.inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ -DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \ -A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ -A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \ -inst_BGACK_030_INTreg.BLIF inst_VMA_INTreg.BLIF N_317_i.BLIF cpu_est_2_.BLIF \ +DTACK.BLIF VPA.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \ +A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF A_DECODE_17_.BLIF \ +A_DECODE_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF A_1_.BLIF N_226.BLIF \ +inst_BGACK_030_INTreg.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF \ cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INT.BLIF \ -SM_AMIGA_5_.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \ -inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ -SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF inst_VPA_D.BLIF inst_UDS_000_INT.BLIF \ -inst_LDS_000_INT.BLIF inst_CLK_OUT_PRE_D.BLIF inst_DTACK_D0.BLIF \ -inst_RESET_OUT.BLIF inst_CLK_OUT_PRE_50.BLIF CLK_000_D_1_.BLIF \ -CLK_000_D_0_.BLIF inst_CLK_000_PE.BLIF CLK_000_P_SYNC_9_.BLIF \ -inst_CLK_000_NE.BLIF CLK_000_N_SYNC_11_.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF \ -IPL_D0_2_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_DSACK1_INTreg.BLIF SM_AMIGA_4_.BLIF \ -inst_DS_000_ENABLE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF \ -CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF \ -CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.BLIF \ -CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF \ -CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF \ -CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.BLIF \ -CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.BLIF \ -CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF inst_RW_000_INT.BLIF \ -inst_RW_000_DMA.BLIF inst_A0_DMA.BLIF SM_AMIGA_6_.BLIF inst_CLK_030_H.BLIF \ -SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF \ -BG_000DFFreg.BLIF CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_AS_030_D0.BLIF \ +inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF \ +inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF SIZE_DMA_0_.BLIF \ +SIZE_DMA_1_.BLIF inst_VPA_D.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \ +inst_CLK_OUT_PRE_D.BLIF CLK_000_D_10_.BLIF CLK_000_D_11_.BLIF \ +inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF inst_CLK_OUT_PRE_50.BLIF \ +CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF \ +IPL_D0_0_.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF CLK_000_D_2_.BLIF \ +CLK_000_D_3_.BLIF CLK_000_D_4_.BLIF CLK_000_D_5_.BLIF CLK_000_D_6_.BLIF \ +CLK_000_D_7_.BLIF CLK_000_D_8_.BLIF CLK_000_D_9_.BLIF CLK_000_D_12_.BLIF \ +SM_AMIGA_0_.BLIF inst_DSACK1_INTreg.BLIF CLK_000_N_SYNC_0_.BLIF \ +SM_AMIGA_4_.BLIF inst_DS_000_ENABLE.BLIF CLK_000_N_SYNC_12_.BLIF \ +RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF CLK_000_P_SYNC_0_.BLIF \ +CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.BLIF \ +CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.BLIF \ +CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.BLIF \ +CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.BLIF \ +CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.BLIF \ +CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.BLIF \ +CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.BLIF inst_RW_000_INT.BLIF \ +inst_RW_000_DMA.BLIF inst_CLK_000_NE_D0.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_A0_DMA.BLIF SM_AMIGA_6_.BLIF \ +inst_CLK_030_H.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \ +SM_AMIGA_i_7_.BLIF BG_000DFFreg.BLIF CLK_OUT_INTreg.BLIF IPL_030DFF_0_reg.BLIF \ IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ -SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF +SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \ +AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \ +AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ -SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ -SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \ +SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \ +SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C \ +SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_2_.D \ +cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \ IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \ IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \ -SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D \ -SM_AMIGA_5_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D \ -CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D \ -CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C \ -cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C \ -cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C \ -CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D \ -CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \ -CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D \ -CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C \ -CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D \ -CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C \ -CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \ -CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \ -CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \ -CLK_000_N_SYNC_9_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ -CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \ -CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \ -CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C \ -CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D \ -CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_INT.D \ +CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D \ +CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C \ +CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \ +CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C \ +CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ +CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ +SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ +CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D \ +CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C \ +CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ +CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \ +CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \ +CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_10_.D CLK_000_P_SYNC_10_.C \ +CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D \ +CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C \ +CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D \ +CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_D_0_.D \ +CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C \ +CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D \ +CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C \ +CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_10_.D \ +CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C CLK_000_D_12_.D \ +CLK_000_D_12_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \ +CLK_000_P_SYNC_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \ +RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C \ +inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ +inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \ +inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \ +inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C \ +inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_000_INT.D \ inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \ -inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \ -inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ -inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C \ -inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C \ +inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D inst_VPA_D.C \ +inst_DTACK_D0.D inst_DTACK_D0.C BG_000DFFreg.D BG_000DFFreg.C \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C \ inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ -inst_VMA_INTreg.D inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C \ -inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C \ -inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ -inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \ -inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ -inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.D \ -inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \ -CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_PE.D inst_CLK_000_PE.C \ -inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D \ -inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 LDS_000 A0 BERR RW \ -SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ -SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE \ -inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 -.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \ -SM_AMIGA_4_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D -1-0-11 1 -11-1-- 1 -11--1- 1 ----00- 0 --01--- 0 --0--0- 0 +inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C inst_BGACK_030_INT_D.D \ +inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C \ +CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \ +SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ \ +AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ \ +N_226 AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ +SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE \ +AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE \ +DSACK1.OE RESET.OE CIIN.OE inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 \ +SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2 +.names RST.BLIF N_226.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF \ +cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF \ +inst_DTACK_D0.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_0_.BLIF \ +SM_AMIGA_4_.BLIF CLK_000_N_SYNC_12_.BLIF inst_CLK_000_NE_D0.BLIF \ +SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \ +BERR.PIN.BLIF SM_AMIGA_i_7_.D +10001000--000-100-0- 1 +10001000---00110--0- 1 +10001000-100--1-0--- 1 +10001000-1-0-11----- 1 +10-----10-000-100-0- 1 +10-----10--00110--0- 1 +10--------000--0000- 1 +10-----10100--1-0--- 1 +10---------001-0-00- 1 +10-----101-0-11----- 1 +10-------100----00-- 1 +10-------1-0-1---0-- 1 +10-------0---------1 1 +10---------0-------1 1 +-------11--------1-0 0 +---------1-1-------- 0 +------10---------1-0 0 +-----1-0---------1-0 0 +----0--0---------1-0 0 +---1---0---------1-0 0 +--1----0---------1-0 0 +-------------0--1--0 0 +----------1--0-----0 0 +---------0--------10 0 +---------0-----1---0 0 +---------0--1------0 0 +--------------0--1-0 0 +-1------------------ 0 +0------------------- 0 +-----------1-------0 0 +.names nEXP_SPACE.BLIF RST.BLIF inst_AS_030_000_SYNC.BLIF \ +CLK_000_P_SYNC_10_.BLIF CLK_000_N_SYNC_0_.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D +110-1-0- 1 +-1-0-1-1 1 +-1---10- 1 +---1--1- 0 +----00-- 0 +--1--0-- 0 +0----0-- 0 +-----01- 0 +-0------ 0 +------10 0 +.names RST.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF \ +CLK_000_N_SYNC_12_.BLIF SM_AMIGA_6_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D +110-1- 1 +1-10-1 1 +1-1-11 1 +---10- 0 +-00--- 0 +--0-0- 0 +--1--0 0 0----- 0 --0---0 0 +.names RST.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.BLIF \ +CLK_000_N_SYNC_12_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D +10-1-1 1 +1-1-1- 1 +1-11-- 1 +---00- 0 +-10--- 0 +--00-- 0 +0----- 0 +--0--0 0 .names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \ -inst_CLK_000_PE.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \ -BERR.PIN.BLIF SM_AMIGA_2_.D +CLK_000_P_SYNC_10_.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_3_.BLIF \ +SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_2_.D 1001000--11-- 1 1-----10-11-- 1 1-------0--11 1 @@ -133,8 +207,8 @@ BERR.PIN.BLIF SM_AMIGA_2_.D ----------00- 0 0------------ 0 ----------0-0 0 -.names RST.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF \ -SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_1_.D +.names RST.BLIF CLK_000_P_SYNC_10_.BLIF CLK_000_N_SYNC_12_.BLIF \ +SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_1_.D 11-01- 1 1-01-1 1 1--111 1 @@ -143,15 +217,35 @@ SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_1_.D ---00- 0 ---1-0 0 0----- 0 -.names RST.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_0_.BLIF \ -SM_AMIGA_1_.BLIF BERR.PIN.BLIF SM_AMIGA_0_.D -1-101- 1 -10-1-1 1 --1-1-- 0 ----00- 0 +.names RST.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_0_.BLIF \ +CLK_000_N_SYNC_12_.BLIF SM_AMIGA_1_.BLIF BERR.PIN.BLIF SM_AMIGA_0_.D +1-011- 1 +101--1 1 +-11--- 0 +--0-0- 0 --00-- 0 ----1-0 0 +--1--0 0 0----- 0 +.names cpu_est_2_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_NE_D0.BLIF \ +cpu_est_2_.D +0111 1 +1-0- 1 +10-- 1 +1--0 1 +1111 0 +0-0- 0 +00-- 0 +0--0 0 +.names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ +inst_CLK_000_NE_D0.BLIF cpu_est_3_.D +1-111 1 +010-- 1 +-1--0 1 +--101 0 +00--- 0 +1-0-1 0 +0-1-1 0 +-0--0 0 .names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D 0-01100- 1 @@ -233,68 +327,8 @@ IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D 1- 1 -0 1 01 0 -.names RST.BLIF inst_VMA_INTreg.BLIF N_317_i.BLIF cpu_est_2_.BLIF \ -cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF SM_AMIGA_5_.BLIF \ -inst_VPA_D.BLIF inst_DTACK_D0.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \ -inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF \ -SM_AMIGA_i_7_.D -101010000---10000-0- 1 -1010100-0--11000--0- 1 -101010000-1-10--0--- 1 -1010100-0-1110------ 1 -1-1----010--10000-0- 1 -1-1-----10-11000--0- 1 -1-1----0-----000000- 1 -1-1----0101-10--0--- 1 -1-1--------1-000-00- 1 -1-1-----101110------ 1 -1-1----0--1--0--00-- 1 -1-1-------11-0---0-- 1 -1-1-------0--------1 1 -1-1----------0-----1 1 ---------11-------1-0 0 -----------1--1------ 0 -------1-0--------1-0 0 ------1--0--------1-0 0 -----0---0--------1-0 0 ----1----0--------1-0 0 --1------0--------1-0 0 ------------0----1--0 0 --------1---0-------0 0 -----------0-------10 0 -----------0----1---0 0 -----------0---1----0 0 -------------0----1-0 0 ---0----------------- 0 -0------------------- 0 --------------1-----0 0 -.names RST.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \ -CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D -11010--0- 1 -1----01-1 1 -1-----10- 1 ------1-1- 0 -----1-0-- 0 ----0--0-- 0 ---1---0-- 0 --0----0-- 0 -------01- 0 -0-------- 0 --------10 0 -.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \ -SM_AMIGA_6_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D -101-1- 1 -11-0-1 1 -11--11 1 ----10- 0 --00--- 0 --0--0- 0 --1---0 0 -0----- 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF \ -inst_CLK_000_PE.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D +CLK_000_P_SYNC_10_.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D 10100 1 10010 1 --00- 0 @@ -303,7 +337,7 @@ inst_CLK_000_PE.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D 0---- 0 ----1 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ -inst_CLK_000_PE.BLIF AS_000.PIN.BLIF CYCLE_DMA_1_.D +CLK_000_P_SYNC_10_.BLIF AS_000.PIN.BLIF CYCLE_DMA_1_.D 101010 1 10-100 1 1001-0 1 @@ -340,27 +374,24 @@ cpu_est_1_.D -111 0 -00- 0 --00 0 -.names cpu_est_2_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_NE_D0.BLIF \ -cpu_est_2_.D -0111 1 -1-0- 1 -10-- 1 -1--0 1 -1111 0 -0-0- 0 -00-- 0 -0--0 0 -.names cpu_est_2_.BLIF cpu_est_3_.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ -inst_CLK_000_NE_D0.BLIF cpu_est_3_.D +.names CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_N_SYNC_0_.D +10 1 +0- 0 +-1 0 +.names CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_P_SYNC_0_.D +01 1 +1- 0 +-0 0 +.names RST.BLIF CLK_000_N_SYNC_12_.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ +RST_DLY_2_.BLIF RST_DLY_0_.D 1-111 1 -010-- 1 --1--0 1 ---101 0 -00--- 0 -1-0-1 0 -0-1-1 0 --0--0 0 -.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ +110-- 1 +101-- 1 +-110- 0 +-00-- 0 +-11-0 0 +0---- 0 +.names RST.BLIF CLK_000_N_SYNC_12_.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ RST_DLY_2_.BLIF RST_DLY_1_.D 1--11 1 1110- 1 @@ -370,7 +401,7 @@ RST_DLY_2_.BLIF RST_DLY_1_.D --00- 0 -0-0- 0 0---- 0 -.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ +.names RST.BLIF CLK_000_N_SYNC_12_.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ RST_DLY_2_.BLIF RST_DLY_2_.D 1111- 1 1---1 1 @@ -378,44 +409,171 @@ RST_DLY_2_.BLIF RST_DLY_2_.D ---00 0 --0-0 0 -0--0 0 -.names CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_P_SYNC_0_.D -01 1 -1- 0 --0 0 -.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \ -RST_DLY_2_.BLIF RST_DLY_0_.D -1-111 1 -110-- 1 -101-- 1 --110- 0 --00-- 0 --11-0 0 -0---- 0 -.names RST.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF \ -BERR.PIN.BLIF inst_AS_000_INT.D --10-- 1 ---01- 1 +.names RST.BLIF inst_RESET_OUT.BLIF CLK_000_N_SYNC_12_.BLIF RST_DLY_0_.BLIF \ +RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D +1-1111 1 +11---- 1 +-0--0- 0 +-0-0-- 0 +-00--- 0 +0----- 0 +-0---0 0 +.names RST.BLIF inst_AS_030_D0.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF \ +SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D +1--000-01-- 1 +1-100--01-- 1 +10----1--1- 1 +1---00-01-1 1 +1-1-0--01-1 1 +--0--1---0- 0 +--0--10---- 0 +-10--1----- 0 +---1-----00 0 +---1--0---0 0 +-1-1------0 0 +--------00- 0 +-------1-0- 0 +----1----0- 0 +------0-0-- 0 +-1------0-- 0 +------01--- 0 +-1-----1--- 0 +----1-0---- 0 +-1--1------ 0 +0---------- 0 +.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ +cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF CLK_000_P_SYNC_10_.BLIF \ +CLK_000_N_SYNC_12_.BLIF inst_VMA_INTreg.D +--0000-1- 1 +-1----1-- 1 +-1---0--- 1 +-1--0---- 1 +-1------0 1 +0-------- 1 +-1-1----- 1 +-11------ 1 +1-00110-1 0 +10-----0- 0 +10-1----- 0 +101------ 0 +10---1--- 0 +10--1---- 0 +.names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A_0_.PIN.BLIF \ +inst_UDS_000_INT.D +-10- 1 +0--- 1 +--11 1 +100- 0 +1-10 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D +-111- 1 0---- 1 ---0-0 1 -10-01 0 -1-1-- 0 -.names CLK_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_CLK_OUT_PRE_D.BLIF \ -inst_DSACK1_INTreg.BLIF CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF \ -SM_AMIGA_1_.BLIF BERR.PIN.BLIF inst_DSACK1_INTreg.D -1--01-0-- 1 -----100-- 1 -1-10--0-- 1 -1--0--0-0 1 -----1--0- 1 ---1--00-- 1 ------00-0 1 ---1----0- 1 +-0--1 1 +11-0- 0 +110-- 0 +10--0 0 +.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D +-1-1- 1 +-10-- 1 +0---- 1 +-0--1 1 +1110- 0 +10--0 0 +.names RST.BLIF CLK_000_P_SYNC_10_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_0_.BLIF \ +inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D +--0-1-- 1 +-101--- 1 +--0--0- 1 +0------ 1 +--1---1 1 +1-0001- 0 +100-01- 0 +1-1---0 0 +.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \ +SIZE_1_.PIN.BLIF A_0_.PIN.BLIF inst_LDS_000_INT.D +--1100 1 +-10--- 1 +0----- 1 +100--- 0 +1-1-1- 0 +1-10-- 0 +1-1--1 0 +.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF \ +CLK_000_P_SYNC_10_.BLIF AS_000.PIN.BLIF inst_BGACK_030_INTreg.D +1-1-- 1 +1--11 1 +-0--- 1 +-100- 0 +-10-0 0 +01--- 0 +.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ +CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ +LDS_000.PIN.BLIF inst_AS_000_DMA.D +----00--- 1 +----11--- 1 +0--1----- 1 +------1-- 1 +--1------ 1 -0------- 1 --------00 1 --10-0---1 0 --1-1-1-1- 0 -01---1-1- 0 --1----11- 0 +-------11 1 +-1001000- 0 +110-1000- 0 +-1000100- 0 +110-0100- 0 +-100100-0 0 +110-100-0 0 +-100010-0 0 +110-010-0 0 +.names FC_1_.BLIF nEXP_SPACE.BLIF RST.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF \ +A_DECODE_17_.BLIF A_DECODE_16_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_AS_030_D0.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \ +SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D +1--00101--1--- 1 +----------1-1- 1 +----------10-- 1 +--------0-1--- 1 +-0--------1--- 1 +---------1---- 1 +--0----------- 1 +-------------0 1 +-11----010-101 0 +-11---1-10-101 0 +-11--0--10-101 0 +-11-1---10-101 0 +-111----10-101 0 +011-----10-101 0 +--1------00--1 0 +.names RST.BLIF inst_AS_000_INT.BLIF inst_AS_030_D0.BLIF SM_AMIGA_5_.BLIF \ +BERR.PIN.BLIF inst_AS_000_INT.D +-1-0- 1 +--10- 1 +0---- 1 +---00 1 +100-1 0 +1--1- 0 +.names CLK_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_CLK_OUT_PRE_D.BLIF \ +CLK_000_D_10_.BLIF CLK_000_D_11_.BLIF CLK_000_D_12_.BLIF \ +inst_DSACK1_INTreg.BLIF SM_AMIGA_1_.BLIF BERR.PIN.BLIF inst_DSACK1_INTreg.D +1--0-1-1-- 1 +-----001-- 1 +----11-1-- 1 +1-10-1---- 1 +1--0-1---0 1 +-------10- 1 +--1--00--- 1 +--1-11---- 1 +-----00--0 1 +----11---0 1 +--1-----0- 1 +-0-------- 1 +--------00 1 +-1-101--1- 0 +01--01--1- 0 +-1---01-1- 0 +-10----0-1 0 .names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF \ AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ @@ -449,10 +607,6 @@ inst_DS_000_DMA.D 0- 1 -1 1 10 0 -.names nEXP_SPACE.BLIF RST.BLIF inst_nEXP_SPACE_D0reg.D -1- 1 --0 1 -01 0 .names VPA.BLIF RST.BLIF inst_VPA_D.D 1- 1 -0 1 @@ -461,169 +615,32 @@ inst_DS_000_DMA.D 1- 1 -0 1 01 0 -.names RST.BLIF inst_RESET_OUT.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF \ -RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D -1-1111 1 -11---- 1 --0--0- 0 --0-0-- 0 --00--- 0 -0----- 0 --0---0 0 -.names RST.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF inst_CLK_000_PE.BLIF \ -SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF \ -SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D -10--00-01-- 1 -10-10--01-- 1 -1-0---1--1- 1 -1---00-01-1 1 -1--10--01-1 1 ----0-1---0- 0 ----0-10---- 0 ---10-1----- 0 --1-------00 0 --1----0---0 0 --11-------0 0 ---------00- 0 --------1-0- 0 -----1----0- 0 -------0-0-- 0 ---1-----0-- 0 -------01--- 0 ---1----1--- 0 -----1-0---- 0 ---1-1------ 0 -0---------- 0 -.names BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF \ +.names nEXP_SPACE.BLIF BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF \ CLK_000_D_0_.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D ----01 1 ---0-1 1 ---0--1 1 --0---- 1 -1----- 1 -01111- 0 -01---0 0 -.names A1.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +0----1 1 +--0--- 1 +-1---- 1 +10111- 0 +-01--0 0 +.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D --1-1 1 -1-0-- 1 +-10-- 1 --10- 1 --0--- 1 --1110 0 -010-- 0 -.names A1.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF \ +0---- 1 +1-110 0 +100-- 0 +.names RST.BLIF A_1_.BLIF inst_BGACK_030_INTreg.BLIF \ inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_BGACK_030_INT_D.BLIF \ inst_AMIGA_BUS_ENABLE_DMA_LOW.D --11- 1 -0-0-- 1 +-00-- 1 --1-0 1 --0--- 1 --1101 0 -110-- 0 -.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ -cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_CLK_000_PE.BLIF \ -inst_CLK_000_NE.BLIF inst_VMA_INTreg.D ---0000-1- 1 --1----1-- 1 --1---0--- 1 --1--0---- 1 --1------0 1 -0-------- 1 --1-1----- 1 --11------ 1 -1-00110-1 0 -10-----0- 0 -10-1----- 0 -101------ 0 -10---1--- 0 -10--1---- 0 -.names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A0.PIN.BLIF \ -inst_UDS_000_INT.D --10- 1 -0--- 1 ---11 1 -100- 0 -1-10 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D --111- 1 0---- 1 --0--1 1 -11-0- 0 +1-101 0 110-- 0 -10--0 0 -.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ -inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D --1-1- 1 --10-- 1 -0---- 1 --0--1 1 -1110- 0 -10--0 0 -.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF \ -inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D --0--1-- 1 --011--- 1 --0---0- 1 -0------ 1 --1----1 1 -10-001- 0 -100-01- 0 -11----0 0 -.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \ -SIZE_1_.PIN.BLIF A0.PIN.BLIF inst_LDS_000_INT.D ---1100 1 --10--- 1 -0----- 1 -100--- 0 -1-1-1- 0 -1-10-- 0 -1-1--1 0 -.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_PE.BLIF \ -AS_000.PIN.BLIF inst_BGACK_030_INTreg.D -1-1-- 1 -1--11 1 --0--- 1 --100- 0 --10-0 0 -01--- 0 -.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \ -CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \ -LDS_000.PIN.BLIF inst_AS_000_DMA.D -----00--- 1 -----11--- 1 -0--1----- 1 -------1-- 1 ---1------ 1 --0------- 1 --------11 1 --1001000- 0 -110-1000- 0 --1000100- 0 -110-0100- 0 --100100-0 0 -110-100-0 0 --100010-0 0 -110-010-0 0 -.names FC_1_.BLIF RST.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \ -FC_0_.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_030_D0.BLIF \ -inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \ -SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D -1-00101---1--- 1 -----------1-1- 1 -----------10-- 1 ----------01--- 1 --------0--1--- 1 ---------1----- 1 --0------------ 1 --------------0 1 --1----0101-101 0 --1---1-101-101 0 --1--0--101-101 0 --1-1---101-101 0 --11----101-101 0 -01-----101-101 0 --1------0-0--1 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D 0- 1 -1 1 @@ -631,21 +648,20 @@ SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 1 0 -.names SM_AMIGA_5_.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \ -CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF \ -SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF N_317_i --1010------ 1 ----------1- 1 ---------1-- 1 --------1--- 1 -------1---- 1 ------1----- 1 -1---------- 1 -----------1 1 -0---1000000 0 -0--0-000000 0 -0-1--000000 0 -00---000000 0 +.names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF SM_AMIGA_5_.BLIF \ +SM_AMIGA_0_.BLIF CLK_000_N_SYNC_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_6_.BLIF \ +SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF N_226 +--00000000 1 +-100-00000 1 +0-00-00000 1 +10--1----- 0 +--------1- 0 +-------1-- 0 +------1--- 0 +-----1---- 0 +---1------ 0 +--1------- 0 +---------1 0 .names IPL_030DFF_2_reg.BLIF IPL_030_2_ 1 1 0 0 @@ -665,8 +681,9 @@ SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF N_317_i .names CLK_OUT_INTreg.BLIF CLK_EXP 1 1 0 0 -.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_19_.BLIF A_18_.BLIF \ -A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF FPU_CS +.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_DECODE_19_.BLIF \ +A_DECODE_18_.BLIF A_DECODE_17_.BLIF A_DECODE_16_.BLIF FC_0_.BLIF \ +AS_030.PIN.BLIF FPU_CS -------0- 1 ------1-- 1 -----0--- 1 @@ -695,41 +712,44 @@ A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF FPU_CS 0 .names AMIGA_ADDR_ENABLE 0 -.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF AS_000.PIN.BLIF \ +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF AS_000.PIN.BLIF \ RW_000.PIN.BLIF AMIGA_BUS_DATA_DIR 0001 1 -1--0 1 --1-1 0 ---11 0 -0--0 0 +-1-0 1 1--1 0 +--11 0 +-0-0 0 +-1-1 0 .names inst_BGACK_030_INTreg.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ AMIGA_BUS_ENABLE_LOW 1- 1 -1 1 00 0 -.names inst_BGACK_030_INTreg.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH -01- 1 -1-0 1 -00- 0 -1-1 0 -.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \ -A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ -inst_AS_030_D0.BLIF CIIN -0000000011110 1 ------------0- 0 -----------0-- 0 ----------0--- 0 ---------0---- 0 +.names CLK_000.BLIF inst_BGACK_030_INTreg.BLIF SM_AMIGA_0_.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH +111-- 1 +-0-1- 1 +-1--0 1 +-0-0- 0 +-10-1 0 +01--1 0 +.names A_DECODE_23_.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF \ +inst_AS_030_D0.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF \ +AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF \ +AHIGH_31_.PIN.BLIF CIIN +1111000000000 1 +-----------1- 0 +----------1-- 0 +---------1--- 0 +--------1---- 0 -------1----- 0 ------1------ 0 -----1------- 0 ----1-------- 0 ----1--------- 0 ---1---------- 0 --1----------- 0 -1------------ 0 +---0--------- 0 +--0---------- 0 +-0----------- 0 +0------------ 0 ------------1 0 .names IPL_030DFF_1_reg.BLIF IPL_030_1_ 1 1 @@ -737,6 +757,15 @@ inst_AS_030_D0.BLIF CIIN .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI.BLIF SM_AMIGA_5_.C +1 1 +0 0 .names CLK_OSZI.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -752,6 +781,12 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF SM_AMIGA_0_.C 1 1 0 0 +.names CLK_OSZI.BLIF cpu_est_2_.C +1 1 +0 0 +.names CLK_OSZI.BLIF cpu_est_3_.C +1 1 +0 0 .names CLK_OSZI.BLIF IPL_030DFF_0_reg.C 1 1 0 0 @@ -770,13 +805,28 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF IPL_D0_2_.C 1 1 0 0 -.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C +.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D 1 1 0 0 -.names CLK_OSZI.BLIF SM_AMIGA_6_.C +.names CLK_OSZI.BLIF CLK_000_N_SYNC_6_.C 1 1 0 0 -.names CLK_OSZI.BLIF SM_AMIGA_5_.C +.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_7_.C +1 1 +0 0 +.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C +1 1 +0 0 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C 1 1 0 0 .names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D @@ -791,6 +841,12 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF CLK_000_N_SYNC_11_.C 1 1 0 0 +.names CLK_000_N_SYNC_11_.BLIF CLK_000_N_SYNC_12_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_N_SYNC_12_.C +1 1 +0 0 .names CLK_OSZI.BLIF CYCLE_DMA_0_.C 1 1 0 0 @@ -814,10 +870,22 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF cpu_est_1_.C 1 1 0 0 -.names CLK_OSZI.BLIF cpu_est_2_.C +.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D 1 1 0 0 -.names CLK_OSZI.BLIF cpu_est_3_.C +.names CLK_OSZI.BLIF CLK_000_P_SYNC_2_.C +1 1 +0 0 +.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_3_.C +1 1 +0 0 +.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_4_.C 1 1 0 0 .names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D @@ -850,10 +918,12 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF CLK_000_P_SYNC_9_.C 1 1 0 0 -.names CLK_000_D_1_.BLIF CLK_000_D_0_.BLIF CLK_000_N_SYNC_0_.D -10 1 -0- 0 --1 0 +.names CLK_000_P_SYNC_9_.BLIF CLK_000_P_SYNC_10_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_P_SYNC_10_.C +1 1 +0 0 .names CLK_OSZI.BLIF CLK_000_N_SYNC_0_.C 1 1 0 0 @@ -887,36 +957,6 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF CLK_000_N_SYNC_5_.C 1 1 0 0 -.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_6_.C -1 1 -0 0 -.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_7_.C -1 1 -0 0 -.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C -1 1 -0 0 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C -1 1 -0 0 -.names CLK_OSZI.BLIF RST_DLY_1_.C -1 1 -0 0 -.names CLK_OSZI.BLIF RST_DLY_2_.C -1 1 -0 0 .names CLK_000.BLIF CLK_000_D_0_.D 1 1 0 0 @@ -929,6 +969,72 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF CLK_000_D_1_.C 1 1 0 0 +.names CLK_000_D_1_.BLIF CLK_000_D_2_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_2_.C +1 1 +0 0 +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_3_.C +1 1 +0 0 +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_4_.C +1 1 +0 0 +.names CLK_000_D_4_.BLIF CLK_000_D_5_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_5_.C +1 1 +0 0 +.names CLK_000_D_5_.BLIF CLK_000_D_6_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_6_.C +1 1 +0 0 +.names CLK_000_D_6_.BLIF CLK_000_D_7_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_7_.C +1 1 +0 0 +.names CLK_000_D_7_.BLIF CLK_000_D_8_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_8_.C +1 1 +0 0 +.names CLK_000_D_8_.BLIF CLK_000_D_9_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_9_.C +1 1 +0 0 +.names CLK_000_D_9_.BLIF CLK_000_D_10_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_10_.C +1 1 +0 0 +.names CLK_000_D_10_.BLIF CLK_000_D_11_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_11_.C +1 1 +0 0 +.names CLK_000_D_11_.BLIF CLK_000_D_12_.D +1 1 +0 0 +.names CLK_OSZI.BLIF CLK_000_D_12_.C +1 1 +0 0 .names CLK_OSZI.BLIF CLK_000_P_SYNC_0_.C 1 1 0 0 @@ -938,46 +1044,13 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF CLK_000_P_SYNC_1_.C 1 1 0 0 -.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_2_.C -1 1 -0 0 -.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_3_.C -1 1 -0 0 -.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_000_P_SYNC_4_.C -1 1 -0 0 .names CLK_OSZI.BLIF RST_DLY_0_.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_AS_000_INT.C +.names CLK_OSZI.BLIF RST_DLY_1_.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_DSACK1_INTreg.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_DS_000_DMA.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AS_030_D0.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_nEXP_SPACE_D0reg.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_VPA_D.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_DTACK_D0.C +.names CLK_OSZI.BLIF RST_DLY_2_.C 1 1 0 0 .names CLK_OSZI.BLIF inst_CLK_030_H.C @@ -989,15 +1062,6 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF inst_DS_000_ENABLE.C 1 1 0 0 -.names CLK_OSZI.BLIF BG_000DFFreg.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -0 0 .names CLK_OSZI.BLIF inst_VMA_INTreg.C 1 1 0 0 @@ -1025,15 +1089,42 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 -.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C +.names CLK_OSZI.BLIF inst_AS_000_INT.C 1 1 0 0 -.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D +.names CLK_OSZI.BLIF inst_DSACK1_INTreg.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_DS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AS_030_D0.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_VPA_D.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_DTACK_D0.C +1 1 +0 0 +.names CLK_OSZI.BLIF BG_000DFFreg.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 +0 0 +.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 +0 0 +.names CLK_000_N_SYNC_12_.BLIF inst_CLK_000_NE_D0.D 1 1 0 0 .names CLK_OSZI.BLIF inst_CLK_000_NE_D0.C 1 1 0 0 +.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C +1 1 +0 0 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D 1 1 0 0 @@ -1046,18 +1137,6 @@ inst_AS_030_D0.BLIF CIIN .names CLK_OSZI.BLIF CLK_OUT_INTreg.C 1 1 0 0 -.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D -1 1 -0 0 -.names CLK_OSZI.BLIF inst_CLK_000_PE.C -1 1 -0 0 -.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D -1 1 -0 0 -.names CLK_OSZI.BLIF inst_CLK_000_NE.C -1 1 -0 0 .names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C 1 1 0 0 @@ -1065,6 +1144,8 @@ inst_AS_030_D0.BLIF CIIN 01 1 1- 0 -0 0 +.names AHIGH_31_ + 0 .names inst_AS_000_DMA.BLIF AS_000.PIN.BLIF AS_030 1- 1 -1 1 @@ -1084,9 +1165,6 @@ inst_AS_030_D0.BLIF CIIN 1- 1 -0 1 01 0 -.names inst_A0_DMA.BLIF A0 -1 1 -0 0 .names BERR 0 .names inst_RW_000_DMA.BLIF RW @@ -1096,8 +1174,25 @@ inst_AS_030_D0.BLIF CIIN 10 1 0- 0 -1 0 -.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF \ -inst_RESET_OUT.BLIF AS_030.OE +.names AHIGH_30_ + 0 +.names AHIGH_29_ + 0 +.names AHIGH_28_ + 0 +.names AHIGH_27_ + 0 +.names AHIGH_26_ + 0 +.names AHIGH_25_ + 0 +.names AHIGH_24_ + 0 +.names inst_A0_DMA.BLIF A_0_ +1 1 +0 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \ +AS_030.OE 001 1 -1- 0 1-- 0 @@ -1118,22 +1213,70 @@ inst_RESET_OUT.BLIF AS_030.OE 11 1 0- 0 -0 0 -.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF SIZE_0_.OE +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF SIZE_0_.OE 00 1 1- 0 -1 0 -.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF SIZE_1_.OE +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF SIZE_1_.OE 00 1 1- 0 -1 0 -.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF \ -inst_RESET_OUT.BLIF A0.OE +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \ +AHIGH_24_.OE 001 1 -1- 0 1-- 0 --0 0 -.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_19_.BLIF A_18_.BLIF \ -A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF BERR.OE +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \ +AHIGH_25_.OE +001 1 +-1- 0 +1-- 0 +--0 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \ +AHIGH_26_.OE +001 1 +-1- 0 +1-- 0 +--0 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \ +AHIGH_27_.OE +001 1 +-1- 0 +1-- 0 +--0 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \ +AHIGH_28_.OE +001 1 +-1- 0 +1-- 0 +--0 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \ +AHIGH_29_.OE +001 1 +-1- 0 +1-- 0 +--0 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \ +AHIGH_30_.OE +001 1 +-1- 0 +1-- 0 +--0 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \ +AHIGH_31_.OE +001 1 +-1- 0 +1-- 0 +--0 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF A_0_.OE +001 1 +-1- 0 +1-- 0 +--0 0 +.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_DECODE_19_.BLIF \ +A_DECODE_18_.BLIF A_DECODE_17_.BLIF A_DECODE_16_.BLIF FC_0_.BLIF \ +AS_030.PIN.BLIF BERR.OE 111001010 1 -------0- 0 ------1-- 0 @@ -1148,36 +1291,37 @@ A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF BERR.OE 01 1 1- 0 -0 0 -.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF \ -inst_RESET_OUT.BLIF DS_030.OE +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF \ +DS_030.OE 001 1 -1- 0 1-- 0 --0 0 -.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE +.names nEXP_SPACE.BLIF DSACK1.OE 1 1 0 0 .names inst_RESET_OUT.BLIF RESET.OE 0 1 1 0 -.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \ -A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ -inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF CIIN.OE -0000000011110- 1 --------------1 1 -------------10 0 ------------0-0 0 -----------0--0 0 ----------0---0 0 ---------0----0 0 --------1-----0 0 -------1------0 0 ------1-------0 0 -----1--------0 0 ----1---------0 0 ---1----------0 0 --1-----------0 0 -1------------0 0 +.names A_DECODE_23_.BLIF nEXP_SPACE.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \ +A_DECODE_20_.BLIF inst_AS_030_D0.BLIF AHIGH_24_.PIN.BLIF AHIGH_25_.PIN.BLIF \ +AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF AHIGH_29_.PIN.BLIF \ +AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF CIIN.OE +1-111000000000 1 +-1------------ 1 +-0----------1- 0 +-0---------1-- 0 +-0--------1--- 0 +-0-------1---- 0 +-0------1----- 0 +-0-----1------ 0 +-0----1------- 0 +-0---1-------- 0 +-0--0--------- 0 +-0-0---------- 0 +-00----------- 0 +00------------ 0 +-0-----------1 0 .names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_030_H.D.X1 10 1 0- 0 @@ -1207,17 +1351,17 @@ UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_CLK_030_H.D.X2 -0 0 .names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \ cpu_est_0_.BLIF cpu_est_1_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \ -inst_CLK_000_PE.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \ -BERR.PIN.BLIF SM_AMIGA_3_.D.X2 -1-------1-10- 1 +CLK_000_P_SYNC_10_.BLIF SM_AMIGA_4_.BLIF inst_CLK_000_NE_D0.BLIF \ +SM_AMIGA_3_.BLIF BERR.PIN.BLIF SM_AMIGA_3_.D.X2 +1-------11-0- 1 1----------10 1 -1001000--101- 1 -1-----10-101- 1 +1001000--011- 1 +1-----10-011- 1 0------------ 0 --------0--0- 0 -----------00- 0 ----------0-11 0 -----------111 0 +---------0-0- 0 +---------1-11 0 +----------011 0 -1----0----11 0 --1---0----11 0 ---0--0----11 0 diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index 0f15e10..f4156fc 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 2.0.00.17.20.15 -// Design '68030_tk' created Wed Aug 17 17:45:46 2016 +// Design '68030_tk' created Fri Aug 19 00:20:41 2016 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index c40f95f..221b8d3 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,13 +2,15 @@ Copyright(C), 1992-2015, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Wed Aug 17 17:45:46 2016 +Design bus68030 created Fri Aug 19 00:20:41 2016 P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- 1 2 1 Pin SIZE_1_ 1 2 1 Pin SIZE_1_.OE + 0 0 1 Pin AHIGH_31_ + 1 3 1 Pin AHIGH_31_.OE 1 2 1 Pin AS_030- 1 3 1 Pin AS_030.OE 1 2 1 Pin AS_000- @@ -29,25 +31,39 @@ Design bus68030 created Wed Aug 17 17:45:46 2016 0 0 1 Pin RESET 1 1 1 Pin RESET.OE 0 0 1 Pin AMIGA_ADDR_ENABLE - 1 2 1 Pin SIZE_0_ - 1 2 1 Pin SIZE_0_.OE 2 4 1 Pin AMIGA_BUS_DATA_DIR 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- - 2 3 1 Pin AMIGA_BUS_ENABLE_HIGH + 3 5 1 Pin AMIGA_BUS_ENABLE_HIGH 1 13 1 Pin CIIN 1 1 1 Pin CIIN.OE + 1 2 1 Pin SIZE_0_ + 1 2 1 Pin SIZE_0_.OE + 0 0 1 Pin AHIGH_30_ + 1 3 1 Pin AHIGH_30_.OE + 0 0 1 Pin AHIGH_29_ + 1 3 1 Pin AHIGH_29_.OE + 0 0 1 Pin AHIGH_28_ + 1 3 1 Pin AHIGH_28_.OE + 0 0 1 Pin AHIGH_27_ + 1 3 1 Pin AHIGH_27_.OE + 0 0 1 Pin AHIGH_26_ + 1 3 1 Pin AHIGH_26_.OE + 0 0 1 Pin AHIGH_25_ + 1 3 1 Pin AHIGH_25_.OE + 0 0 1 Pin AHIGH_24_ + 1 3 1 Pin AHIGH_24_.OE 10 8 1 Pin IPL_030_2_.D- 1 1 1 Pin IPL_030_2_.C + 1 2 1 Pin RW_000.OE + 3 7 1 Pin RW_000.D- + 1 1 1 Pin RW_000.C + 1 3 1 Pin A_0_.OE + 3 5 1 Pin A_0_.D + 1 1 1 Pin A_0_.C 10 8 1 Pin IPL_030_1_.D- 1 1 1 Pin IPL_030_1_.C 10 8 1 Pin IPL_030_0_.D- 1 1 1 Pin IPL_030_0_.C - 1 2 1 Pin RW_000.OE - 3 7 1 Pin RW_000.D- - 1 1 1 Pin RW_000.C - 1 3 1 Pin A0.OE - 3 5 1 Pin A0.D - 1 1 1 Pin A0.C 2 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.C 3 5 1 Pin BGACK_030.D @@ -55,14 +71,14 @@ Design bus68030 created Wed Aug 17 17:45:46 2016 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C 1 1 1 Pin DSACK1.OE - 4 9 1 Pin DSACK1.D- + 4 10 1 Pin DSACK1.D- 1 1 1 Pin DSACK1.C 3 9 1 Pin VMA.T 1 1 1 Pin VMA.C 1 2 1 Pin RW.OE 2 5 1 Pin RW.D- 1 1 1 Pin RW.C - 4 11 1 Node N_317_i- + 3 10 1 Node N_226 4 4 1 Node cpu_est_2_.D 1 1 1 Node cpu_est_2_.C 3 5 1 Node cpu_est_3_.D @@ -73,14 +89,10 @@ Design bus68030 created Wed Aug 17 17:45:46 2016 1 1 1 Node cpu_est_1_.C 2 5 1 Node inst_AS_000_INT.D- 1 1 1 Node inst_AS_000_INT.C - 3 6 1 Node SM_AMIGA_5_.D - 1 1 1 Node SM_AMIGA_5_.C 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 2 1 Node inst_AS_030_D0.D- 1 1 1 Node inst_AS_030_D0.C - 1 2 1 Node inst_nEXP_SPACE_D0reg.D- - 1 1 1 Node inst_nEXP_SPACE_D0reg.C 7 14 1 Node inst_AS_030_000_SYNC.D- 1 1 1 Node inst_AS_030_000_SYNC.C 1 2 1 Node inst_BGACK_030_INT_D.D- @@ -105,6 +117,10 @@ Design bus68030 created Wed Aug 17 17:45:46 2016 1 1 1 Node inst_LDS_000_INT.C 1 1 1 Node inst_CLK_OUT_PRE_D.D 1 1 1 Node inst_CLK_OUT_PRE_D.C + 1 1 1 Node CLK_000_D_10_.D + 1 1 1 Node CLK_000_D_10_.C + 1 1 1 Node CLK_000_D_11_.D + 1 1 1 Node CLK_000_D_11_.C 1 2 1 Node inst_DTACK_D0.D- 1 1 1 Node inst_DTACK_D0.C 2 6 1 Node inst_RESET_OUT.D @@ -115,30 +131,44 @@ Design bus68030 created Wed Aug 17 17:45:46 2016 1 1 1 Node CLK_000_D_1_.C 1 1 1 Node CLK_000_D_0_.D 1 1 1 Node CLK_000_D_0_.C - 1 1 1 Node inst_CLK_000_PE.D - 1 1 1 Node inst_CLK_000_PE.C - 1 1 1 Node CLK_000_P_SYNC_9_.D - 1 1 1 Node CLK_000_P_SYNC_9_.C - 1 1 1 Node inst_CLK_000_NE.D - 1 1 1 Node inst_CLK_000_NE.C - 1 1 1 Node CLK_000_N_SYNC_11_.D - 1 1 1 Node CLK_000_N_SYNC_11_.C + 1 1 1 Node CLK_000_P_SYNC_10_.D + 1 1 1 Node CLK_000_P_SYNC_10_.C + 3 6 1 Node SM_AMIGA_5_.D + 1 1 1 Node SM_AMIGA_5_.C 1 2 1 Node IPL_D0_0_.D- 1 1 1 Node IPL_D0_0_.C 1 2 1 Node IPL_D0_1_.D- 1 1 1 Node IPL_D0_1_.C 1 2 1 Node IPL_D0_2_.D- 1 1 1 Node IPL_D0_2_.C - 1 1 1 Node inst_CLK_000_NE_D0.D - 1 1 1 Node inst_CLK_000_NE_D0.C + 1 1 1 Node CLK_000_D_2_.D + 1 1 1 Node CLK_000_D_2_.C + 1 1 1 Node CLK_000_D_3_.D + 1 1 1 Node CLK_000_D_3_.C + 1 1 1 Node CLK_000_D_4_.D + 1 1 1 Node CLK_000_D_4_.C + 1 1 1 Node CLK_000_D_5_.D + 1 1 1 Node CLK_000_D_5_.C + 1 1 1 Node CLK_000_D_6_.D + 1 1 1 Node CLK_000_D_6_.C + 1 1 1 Node CLK_000_D_7_.D + 1 1 1 Node CLK_000_D_7_.C + 1 1 1 Node CLK_000_D_8_.D + 1 1 1 Node CLK_000_D_8_.C + 1 1 1 Node CLK_000_D_9_.D + 1 1 1 Node CLK_000_D_9_.C + 1 1 1 Node CLK_000_D_12_.D + 1 1 1 Node CLK_000_D_12_.C 2 6 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C - 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- - 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C + 1 2 1 Node CLK_000_N_SYNC_0_.D + 1 1 1 Node CLK_000_N_SYNC_0_.C 3 6 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C 5 11 1 Node inst_DS_000_ENABLE.D 1 1 1 Node inst_DS_000_ENABLE.C + 1 1 1 Node CLK_000_N_SYNC_12_.D + 1 1 1 Node CLK_000_N_SYNC_12_.C 3 5 1 Node RST_DLY_0_.D 1 1 1 Node RST_DLY_0_.C 4 5 1 Node RST_DLY_1_.D @@ -163,8 +193,8 @@ Design bus68030 created Wed Aug 17 17:45:46 2016 1 1 1 Node CLK_000_P_SYNC_7_.C 1 1 1 Node CLK_000_P_SYNC_8_.D 1 1 1 Node CLK_000_P_SYNC_8_.C - 1 2 1 Node CLK_000_N_SYNC_0_.D - 1 1 1 Node CLK_000_N_SYNC_0_.C + 1 1 1 Node CLK_000_P_SYNC_9_.D + 1 1 1 Node CLK_000_P_SYNC_9_.C 1 1 1 Node CLK_000_N_SYNC_1_.D 1 1 1 Node CLK_000_N_SYNC_1_.C 1 1 1 Node CLK_000_N_SYNC_2_.D @@ -185,7 +215,13 @@ Design bus68030 created Wed Aug 17 17:45:46 2016 1 1 1 Node CLK_000_N_SYNC_9_.C 1 1 1 Node CLK_000_N_SYNC_10_.D 1 1 1 Node CLK_000_N_SYNC_10_.C - 3 9 1 Node SM_AMIGA_6_.D + 1 1 1 Node CLK_000_N_SYNC_11_.D + 1 1 1 Node CLK_000_N_SYNC_11_.C + 1 1 1 Node inst_CLK_000_NE_D0.D + 1 1 1 Node inst_CLK_000_NE_D0.C + 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- + 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C + 3 8 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C 8 10 1 Node inst_CLK_030_H.D 1 1 1 Node inst_CLK_030_H.C @@ -199,9 +235,9 @@ Design bus68030 created Wed Aug 17 17:45:46 2016 1 1 1 Node SM_AMIGA_i_7_.C 2 14 1 Node CIIN_0 ========= - 323 P-Term Total: 323 + 351 P-Term Total: 351 Total Pins: 61 - Total Nodes: 69 + Total Nodes: 79 Average P-Term/Output: 2 @@ -209,11 +245,15 @@ Equations: SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q); -SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q); +SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q); + +AHIGH_31_ = (0); + +AHIGH_31_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); !AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN); -AS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q); +AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); !AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN); @@ -221,7 +261,7 @@ AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); !DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN); -DS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q); +DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); !UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q); @@ -233,13 +273,13 @@ LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); BERR = (0); -BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); +BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); CLK_DIV_OUT.C = (CLK_OSZI); -!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); +!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); AVEC = (1); @@ -252,22 +292,51 @@ RESET.OE = (!inst_RESET_OUT.Q); AMIGA_ADDR_ENABLE = (0); -SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); - -SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q); - AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN - # !BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & !AS_000.PIN & RW_000.PIN); + # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW_000.PIN); !AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q); AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q - # BGACK_030.Q & !SM_AMIGA_i_7_.Q); + # BGACK_030.Q & !SM_AMIGA_i_7_.Q + # CLK_000 & BGACK_030.Q & SM_AMIGA_0_.Q); -CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q); +CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); CIIN.OE = (CIIN_0); +SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); + +SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); + +AHIGH_30_ = (0); + +AHIGH_30_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + +AHIGH_29_ = (0); + +AHIGH_29_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + +AHIGH_28_ = (0); + +AHIGH_28_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + +AHIGH_27_ = (0); + +AHIGH_27_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + +AHIGH_26_ = (0); + +AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + +AHIGH_25_ = (0); + +AHIGH_25_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + +AHIGH_24_ = (0); + +AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + !IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q @@ -281,6 +350,22 @@ CIIN.OE = (CIIN_0); IPL_030_2_.C = (CLK_OSZI); +RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); + +!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN + # RST & !CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q + # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q); + +RW_000.C = (CLK_OSZI); + +A_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + +A_0_.D = (!RST + # !BGACK_030.Q & UDS_000.PIN + # BGACK_030.Q & inst_BGACK_030_INT_D.Q & A_0_.Q); + +A_0_.C = (CLK_OSZI); + !IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q # RST & !IPL_D0_1_.Q & !IPL_030_1_.Q # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q @@ -307,30 +392,14 @@ IPL_030_1_.C = (CLK_OSZI); IPL_030_0_.C = (CLK_OSZI); -RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); - -!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN - # RST & !SM_AMIGA_5_.Q & !inst_CLK_000_PE.Q & !RW_000.Q & SM_AMIGA_i_7_.Q - # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q); - -RW_000.C = (CLK_OSZI); - -A0.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q); - -A0.D = (!RST - # !BGACK_030.Q & UDS_000.PIN - # BGACK_030.Q & inst_BGACK_030_INT_D.Q & A0.Q); - -A0.C = (CLK_OSZI); - !BG_000.D = (!BG_030 & RST & !BG_000.Q - # !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & CLK_000_D_0_.Q); + # nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q); BG_000.C = (CLK_OSZI); BGACK_030.D = (!RST # BGACK_000 & BGACK_030.Q - # BGACK_000 & inst_CLK_000_PE.Q & AS_000.PIN); + # BGACK_000 & CLK_000_P_SYNC_10_.Q & AS_000.PIN); BGACK_030.C = (CLK_OSZI); @@ -338,18 +407,18 @@ CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q); CLK_EXP.C = (CLK_OSZI); -DSACK1.OE = (inst_nEXP_SPACE_D0reg.Q); +DSACK1.OE = (nEXP_SPACE); -!DSACK1.D = (RST & CLK_000_N_SYNC_10_.Q & SM_AMIGA_1_.Q - # !CLK_030 & RST & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q - # RST & inst_CLK_OUT_PRE_D.Q & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q - # RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN); +!DSACK1.D = (RST & !CLK_000_D_11_.Q & CLK_000_D_12_.Q & SM_AMIGA_1_.Q + # RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN + # !CLK_030 & RST & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q + # RST & inst_CLK_OUT_PRE_D.Q & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q); DSACK1.C = (CLK_OSZI); VMA.T = (!RST & !VMA.Q - # !VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_PE.Q - # RST & VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q); + # !VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & CLK_000_P_SYNC_10_.Q + # RST & VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_N_SYNC_12_.Q); VMA.C = (CLK_OSZI); @@ -360,10 +429,9 @@ RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q); RW.C = (CLK_OSZI); -!N_317_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & !CLK_000_D_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & CLK_000_D_0_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q); +N_226 = (!nEXP_SPACE & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q + # inst_AS_030_000_SYNC.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !CLK_000_N_SYNC_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q); cpu_est_2_.D = (cpu_est_2_.Q & !cpu_est_0_.Q # cpu_est_2_.Q & !cpu_est_1_.Q @@ -394,13 +462,7 @@ cpu_est_1_.C = (CLK_OSZI); inst_AS_000_INT.C = (CLK_OSZI); -SM_AMIGA_5_.D = (RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & SM_AMIGA_6_.Q - # RST & SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & BERR.PIN - # RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN); - -SM_AMIGA_5_.C = (CLK_OSZI); - -!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (A1 & RST & !BGACK_030.Q +!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q); inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); @@ -409,17 +471,13 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); inst_AS_030_D0.C = (CLK_OSZI); -!inst_nEXP_SPACE_D0reg.D = (!nEXP_SPACE & RST); - -inst_nEXP_SPACE_D0reg.C = (CLK_OSZI); - !inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_D0.Q & !inst_AS_030_000_SYNC.Q & BERR.PIN - # !FC_1_ & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN - # RST & A_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN - # RST & A_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN - # RST & !A_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN - # RST & A_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN - # RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN); + # !FC_1_ & nEXP_SPACE & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # nEXP_SPACE & RST & A_DECODE_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # nEXP_SPACE & RST & A_DECODE_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # nEXP_SPACE & RST & !A_DECODE_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # nEXP_SPACE & RST & A_DECODE_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # nEXP_SPACE & RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN); inst_AS_030_000_SYNC.C = (CLK_OSZI); @@ -449,14 +507,14 @@ inst_DS_000_DMA.D = (!RST inst_DS_000_DMA.C = (CLK_OSZI); -CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & inst_CLK_000_PE.Q & !AS_000.PIN - # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN); +CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CLK_000_P_SYNC_10_.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CLK_000_P_SYNC_10_.Q & !AS_000.PIN); CYCLE_DMA_0_.C = (CLK_OSZI); CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN - # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN - # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_000_PE.Q & !AS_000.PIN); + # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !CLK_000_P_SYNC_10_.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & CLK_000_P_SYNC_10_.Q & !AS_000.PIN); CYCLE_DMA_1_.C = (CLK_OSZI); @@ -477,13 +535,13 @@ SIZE_DMA_1_.C = (CLK_OSZI); inst_VPA_D.C = (CLK_OSZI); !inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q - # RST & SM_AMIGA_6_.Q & !A0.PIN); + # RST & SM_AMIGA_6_.Q & !A_0_.PIN); inst_UDS_000_INT.C = (CLK_OSZI); inst_LDS_000_INT.D = (!RST # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q - # SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN); + # SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN); inst_LDS_000_INT.C = (CLK_OSZI); @@ -491,12 +549,20 @@ inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_D.C = (CLK_OSZI); +CLK_000_D_10_.D = (CLK_000_D_9_.Q); + +CLK_000_D_10_.C = (CLK_OSZI); + +CLK_000_D_11_.D = (CLK_000_D_10_.Q); + +CLK_000_D_11_.C = (CLK_OSZI); + !inst_DTACK_D0.D = (!DTACK & RST); inst_DTACK_D0.C = (CLK_OSZI); inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q - # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); + # RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); inst_RESET_OUT.C = (CLK_OSZI); @@ -512,21 +578,15 @@ CLK_000_D_0_.D = (CLK_000); CLK_000_D_0_.C = (CLK_OSZI); -inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q); +CLK_000_P_SYNC_10_.D = (CLK_000_P_SYNC_9_.Q); -inst_CLK_000_PE.C = (CLK_OSZI); +CLK_000_P_SYNC_10_.C = (CLK_OSZI); -CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q); +SM_AMIGA_5_.D = (RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_6_.Q + # RST & SM_AMIGA_5_.Q & !CLK_000_N_SYNC_12_.Q & BERR.PIN + # RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN); -CLK_000_P_SYNC_9_.C = (CLK_OSZI); - -inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q); - -inst_CLK_000_NE.C = (CLK_OSZI); - -CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q); - -CLK_000_N_SYNC_11_.C = (CLK_OSZI); +SM_AMIGA_5_.C = (CLK_OSZI); !IPL_D0_0_.D = (RST & !IPL_0_); @@ -540,49 +600,84 @@ IPL_D0_1_.C = (CLK_OSZI); IPL_D0_2_.C = (CLK_OSZI); -inst_CLK_000_NE_D0.D = (inst_CLK_000_NE.Q); +CLK_000_D_2_.D = (CLK_000_D_1_.Q); -inst_CLK_000_NE_D0.C = (CLK_OSZI); +CLK_000_D_2_.C = (CLK_OSZI); -SM_AMIGA_0_.D = (RST & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & SM_AMIGA_1_.Q - # RST & !inst_CLK_000_PE.Q & SM_AMIGA_0_.Q & BERR.PIN); +CLK_000_D_3_.D = (CLK_000_D_2_.Q); + +CLK_000_D_3_.C = (CLK_OSZI); + +CLK_000_D_4_.D = (CLK_000_D_3_.Q); + +CLK_000_D_4_.C = (CLK_OSZI); + +CLK_000_D_5_.D = (CLK_000_D_4_.Q); + +CLK_000_D_5_.C = (CLK_OSZI); + +CLK_000_D_6_.D = (CLK_000_D_5_.Q); + +CLK_000_D_6_.C = (CLK_OSZI); + +CLK_000_D_7_.D = (CLK_000_D_6_.Q); + +CLK_000_D_7_.C = (CLK_OSZI); + +CLK_000_D_8_.D = (CLK_000_D_7_.Q); + +CLK_000_D_8_.C = (CLK_OSZI); + +CLK_000_D_9_.D = (CLK_000_D_8_.Q); + +CLK_000_D_9_.C = (CLK_OSZI); + +CLK_000_D_12_.D = (CLK_000_D_11_.Q); + +CLK_000_D_12_.C = (CLK_OSZI); + +SM_AMIGA_0_.D = (RST & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & SM_AMIGA_1_.Q + # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_0_.Q & BERR.PIN); SM_AMIGA_0_.C = (CLK_OSZI); -!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (!A1 & RST & !BGACK_030.Q - # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); +CLK_000_N_SYNC_0_.D = (CLK_000_D_1_.Q & !CLK_000_D_0_.Q); -inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); +CLK_000_N_SYNC_0_.C = (CLK_OSZI); -SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & inst_CLK_000_NE.Q - # RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q - # RST & !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & BERR.PIN); +SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q + # RST & SM_AMIGA_5_.Q & CLK_000_N_SYNC_12_.Q + # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_4_.Q & BERR.PIN); SM_AMIGA_4_.C = (CLK_OSZI); inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN - # RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q + # RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q - # RST & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN + # RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN # RST & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN); inst_DS_000_ENABLE.C = (CLK_OSZI); -RST_DLY_0_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_0_.Q - # RST & inst_CLK_000_NE.Q & !RST_DLY_0_.Q +CLK_000_N_SYNC_12_.D = (CLK_000_N_SYNC_11_.Q); + +CLK_000_N_SYNC_12_.C = (CLK_OSZI); + +RST_DLY_0_.D = (RST & !CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q + # RST & CLK_000_N_SYNC_12_.Q & !RST_DLY_0_.Q # RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); RST_DLY_0_.C = (CLK_OSZI); -RST_DLY_1_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_1_.Q +RST_DLY_1_.D = (RST & !CLK_000_N_SYNC_12_.Q & RST_DLY_1_.Q # RST & !RST_DLY_0_.Q & RST_DLY_1_.Q # RST & RST_DLY_1_.Q & RST_DLY_2_.Q - # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q); + # RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q); RST_DLY_1_.C = (CLK_OSZI); RST_DLY_2_.D = (RST & RST_DLY_2_.Q - # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q); + # RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q); RST_DLY_2_.C = (CLK_OSZI); @@ -622,9 +717,9 @@ CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q); CLK_000_P_SYNC_8_.C = (CLK_OSZI); -CLK_000_N_SYNC_0_.D = (CLK_000_D_1_.Q & !CLK_000_D_0_.Q); +CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q); -CLK_000_N_SYNC_0_.C = (CLK_OSZI); +CLK_000_P_SYNC_9_.C = (CLK_OSZI); CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q); @@ -666,9 +761,22 @@ CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q); CLK_000_N_SYNC_10_.C = (CLK_OSZI); +CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q); + +CLK_000_N_SYNC_11_.C = (CLK_OSZI); + +inst_CLK_000_NE_D0.D = (CLK_000_N_SYNC_12_.Q); + +inst_CLK_000_NE_D0.C = (CLK_OSZI); + +!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q + # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); + +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); + SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q - # RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN - # RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_i_7_.Q); + # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_6_.Q & BERR.PIN + # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & CLK_000_N_SYNC_0_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_6_.C = (CLK_OSZI); @@ -683,46 +791,46 @@ inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst inst_CLK_030_H.C = (CLK_OSZI); -SM_AMIGA_1_.D = (RST & inst_CLK_000_PE.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q - # RST & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & BERR.PIN +SM_AMIGA_1_.D = (RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q + # RST & !CLK_000_N_SYNC_12_.Q & SM_AMIGA_1_.Q & BERR.PIN # RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q & BERR.PIN); SM_AMIGA_1_.C = (CLK_OSZI); SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q # SM_AMIGA_3_.Q & !BERR.PIN - # RST & inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q - # inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q - # !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q); + # RST & CLK_000_P_SYNC_10_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q + # inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q + # !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q); SM_AMIGA_3_.C = (CLK_OSZI); SM_AMIGA_2_.D = (RST & SM_AMIGA_3_.Q & SM_AMIGA_2_.Q - # RST & !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN + # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_2_.Q & BERR.PIN # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q # RST & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q); SM_AMIGA_2_.C = (CLK_OSZI); -SM_AMIGA_i_7_.D = (RST & N_317_i & !inst_CLK_000_PE.Q & BERR.PIN - # RST & N_317_i & !SM_AMIGA_0_.Q & BERR.PIN - # RST & N_317_i & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_3_.Q - # RST & N_317_i & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q - # RST & N_317_i & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q - # RST & N_317_i & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # RST & N_317_i & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q - # RST & N_317_i & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # RST & N_317_i & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q - # RST & N_317_i & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q - # RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q - # RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q - # RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q - # RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q); +SM_AMIGA_i_7_.D = (RST & !N_226 & !CLK_000_P_SYNC_10_.Q & BERR.PIN + # RST & !N_226 & !SM_AMIGA_0_.Q & BERR.PIN + # RST & !N_226 & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & !SM_AMIGA_3_.Q + # RST & !N_226 & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q + # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q + # RST & !N_226 & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q + # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_1_.Q + # RST & !N_226 & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q + # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q + # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q + # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q + # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_1_.Q + # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q + # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q); SM_AMIGA_i_7_.C = (CLK_OSZI); -CIIN_0 = (inst_nEXP_SPACE_D0reg.Q - # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q); +CIIN_0 = (nEXP_SPACE + # A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); Reverse-Polarity Equations: diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index 3dd1e3a..b7a3320 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -1,150 +1,166 @@ #PLAFILE 68030_tk.tt4 -#DATE 03/16/2015 +#DATE 08/18/2016 #DESIGN #DEVICE mach447a -DATA LOCATION A0:G_8_69 // IO {RN_A0} -DATA LOCATION A1:F_*_60 // INP +DATA LOCATION AHIGH_24_:C_8_19 // IO +DATA LOCATION AHIGH_25_:C_12_18 // IO +DATA LOCATION AHIGH_26_:C_5_17 // IO +DATA LOCATION AHIGH_27_:C_4_16 // IO +DATA LOCATION AHIGH_28_:C_0_15 // IO +DATA LOCATION AHIGH_29_:B_13_6 // IO +DATA LOCATION AHIGH_30_:B_0_5 // IO +DATA LOCATION AHIGH_31_:B_12_4 // IO DATA LOCATION AMIGA_ADDR_ENABLE:D_5_33 // OUT DATA LOCATION AMIGA_BUS_DATA_DIR:E_1_48 // OUT DATA LOCATION AMIGA_BUS_ENABLE_HIGH:D_4_34 // OUT -DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_0_20 // OUT +DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_1_20 // OUT DATA LOCATION AS_000:E_4_42 // IO DATA LOCATION AS_030:H_8_82 // IO DATA LOCATION AVEC:A_4_92 // OUT -DATA LOCATION A_16_:A_*_96 // INP -DATA LOCATION A_17_:F_*_59 // INP -DATA LOCATION A_18_:A_*_95 // INP -DATA LOCATION A_19_:A_*_97 // INP -DATA LOCATION A_20_:A_*_93 // INP -DATA LOCATION A_21_:A_*_94 // INP -DATA LOCATION A_22_:H_*_84 // INP -DATA LOCATION A_23_:H_*_85 // INP -DATA LOCATION A_24_:C_*_19 // INP -DATA LOCATION A_25_:C_*_18 // INP -DATA LOCATION A_26_:C_*_17 // INP -DATA LOCATION A_27_:C_*_16 // INP -DATA LOCATION A_28_:C_*_15 // INP -DATA LOCATION A_29_:B_*_6 // INP -DATA LOCATION A_30_:B_*_5 // INP -DATA LOCATION A_31_:B_*_4 // INP +DATA LOCATION A_0_:G_8_69 // IO {RN_A_0_} +DATA LOCATION A_1_:F_*_60 // INP +DATA LOCATION A_DECODE_16_:A_*_96 // INP +DATA LOCATION A_DECODE_17_:F_*_59 // INP +DATA LOCATION A_DECODE_18_:A_*_95 // INP +DATA LOCATION A_DECODE_19_:A_*_97 // INP +DATA LOCATION A_DECODE_20_:A_*_93 // INP +DATA LOCATION A_DECODE_21_:A_*_94 // INP +DATA LOCATION A_DECODE_22_:H_*_84 // INP +DATA LOCATION A_DECODE_23_:H_*_85 // INP DATA LOCATION BERR:E_0_41 // IO DATA LOCATION BGACK_000:D_*_28 // INP -DATA LOCATION BGACK_030:H_4_83 // IO {RN_BGACK_030} +DATA LOCATION BGACK_030:H_6_83 // IO {RN_BGACK_030} DATA LOCATION BG_000:D_1_29 // IO {RN_BG_000} DATA LOCATION BG_030:C_*_21 // INP DATA LOCATION CIIN:E_12_47 // OUT -DATA LOCATION CIIN_0:E_5 // NOD +DATA LOCATION CIIN_0:E_10 // NOD DATA LOCATION CLK_000:*_*_11 // INP -DATA LOCATION CLK_000_D_0_:B_9 // NOD -DATA LOCATION CLK_000_D_1_:E_8 // NOD -DATA LOCATION CLK_000_N_SYNC_0_:E_9 // NOD -DATA LOCATION CLK_000_N_SYNC_10_:H_2 // NOD -DATA LOCATION CLK_000_N_SYNC_11_:H_6 // NOD -DATA LOCATION CLK_000_N_SYNC_1_:A_14 // NOD -DATA LOCATION CLK_000_N_SYNC_2_:B_14 // NOD -DATA LOCATION CLK_000_N_SYNC_3_:B_10 // NOD -DATA LOCATION CLK_000_N_SYNC_4_:B_6 // NOD -DATA LOCATION CLK_000_N_SYNC_5_:D_11 // NOD -DATA LOCATION CLK_000_N_SYNC_6_:G_6 // NOD -DATA LOCATION CLK_000_N_SYNC_7_:F_3 // NOD -DATA LOCATION CLK_000_N_SYNC_8_:A_10 // NOD -DATA LOCATION CLK_000_N_SYNC_9_:A_6 // NOD -DATA LOCATION CLK_000_P_SYNC_0_:E_2 // NOD -DATA LOCATION CLK_000_P_SYNC_1_:B_7 // NOD -DATA LOCATION CLK_000_P_SYNC_2_:G_7 // NOD -DATA LOCATION CLK_000_P_SYNC_3_:E_13 // NOD -DATA LOCATION CLK_000_P_SYNC_4_:G_3 // NOD +DATA LOCATION CLK_000_D_0_:G_13 // NOD +DATA LOCATION CLK_000_D_10_:G_15 // NOD +DATA LOCATION CLK_000_D_11_:H_10 // NOD +DATA LOCATION CLK_000_D_12_:H_2 // NOD +DATA LOCATION CLK_000_D_1_:C_6 // NOD +DATA LOCATION CLK_000_D_2_:G_11 // NOD +DATA LOCATION CLK_000_D_3_:G_7 // NOD +DATA LOCATION CLK_000_D_4_:C_11 // NOD +DATA LOCATION CLK_000_D_5_:E_13 // NOD +DATA LOCATION CLK_000_D_6_:B_11 // NOD +DATA LOCATION CLK_000_D_7_:G_3 // NOD +DATA LOCATION CLK_000_D_8_:B_7 // NOD +DATA LOCATION CLK_000_D_9_:D_11 // NOD +DATA LOCATION CLK_000_N_SYNC_0_:D_2 // NOD +DATA LOCATION CLK_000_N_SYNC_10_:C_14 // NOD +DATA LOCATION CLK_000_N_SYNC_11_:C_10 // NOD +DATA LOCATION CLK_000_N_SYNC_12_:D_13 // NOD +DATA LOCATION CLK_000_N_SYNC_1_:E_9 // NOD +DATA LOCATION CLK_000_N_SYNC_2_:A_3 // NOD +DATA LOCATION CLK_000_N_SYNC_3_:F_7 // NOD +DATA LOCATION CLK_000_N_SYNC_4_:A_14 // NOD +DATA LOCATION CLK_000_N_SYNC_5_:A_6 // NOD +DATA LOCATION CLK_000_N_SYNC_6_:B_3 // NOD +DATA LOCATION CLK_000_N_SYNC_7_:G_6 // NOD +DATA LOCATION CLK_000_N_SYNC_8_:B_14 // NOD +DATA LOCATION CLK_000_N_SYNC_9_:F_3 // NOD +DATA LOCATION CLK_000_P_SYNC_0_:D_7 // NOD +DATA LOCATION CLK_000_P_SYNC_10_:A_8 // NOD +DATA LOCATION CLK_000_P_SYNC_1_:A_15 // NOD +DATA LOCATION CLK_000_P_SYNC_2_:F_11 // NOD +DATA LOCATION CLK_000_P_SYNC_3_:C_7 // NOD +DATA LOCATION CLK_000_P_SYNC_4_:A_11 // NOD DATA LOCATION CLK_000_P_SYNC_5_:G_14 // NOD -DATA LOCATION CLK_000_P_SYNC_6_:A_3 // NOD -DATA LOCATION CLK_000_P_SYNC_7_:B_3 // NOD -DATA LOCATION CLK_000_P_SYNC_8_:G_10 // NOD -DATA LOCATION CLK_000_P_SYNC_9_:G_15 // NOD +DATA LOCATION CLK_000_P_SYNC_6_:G_10 // NOD +DATA LOCATION CLK_000_P_SYNC_7_:D_3 // NOD +DATA LOCATION CLK_000_P_SYNC_8_:A_7 // NOD +DATA LOCATION CLK_000_P_SYNC_9_:C_3 // NOD DATA LOCATION CLK_030:*_*_64 // INP DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT -DATA LOCATION CLK_EXP:B_0_10 // OUT +DATA LOCATION CLK_EXP:B_1_10 // OUT DATA LOCATION CLK_OSZI:*_*_61 // Cin -DATA LOCATION CYCLE_DMA_0_:B_5 // NOD -DATA LOCATION CYCLE_DMA_1_:C_12 // NOD +DATA LOCATION CYCLE_DMA_0_:A_10 // NOD +DATA LOCATION CYCLE_DMA_1_:A_2 // NOD DATA LOCATION DSACK1:H_9_81 // IO {RN_DSACK1} DATA LOCATION DS_030:A_0_98 // OUT DATA LOCATION DTACK:D_*_30 // INP DATA LOCATION E:G_4_66 // OUT DATA LOCATION FC_0_:F_*_57 // INP DATA LOCATION FC_1_:F_*_58 // INP -DATA LOCATION FPU_CS:H_1_78 // OUT +DATA LOCATION FPU_CS:H_4_78 // OUT DATA LOCATION FPU_SENSE:A_*_91 // INP DATA LOCATION IPL_030_0_:B_8_8 // IO {RN_IPL_030_0_} -DATA LOCATION IPL_030_1_:B_12_7 // IO {RN_IPL_030_1_} +DATA LOCATION IPL_030_1_:B_9_7 // IO {RN_IPL_030_1_} DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_} DATA LOCATION IPL_0_:G_*_67 // INP DATA LOCATION IPL_1_:F_*_56 // INP DATA LOCATION IPL_2_:G_*_68 // INP -DATA LOCATION IPL_D0_0_:G_11 // NOD -DATA LOCATION IPL_D0_1_:D_15 // NOD -DATA LOCATION IPL_D0_2_:B_11 // NOD +DATA LOCATION IPL_D0_0_:D_15 // NOD +DATA LOCATION IPL_D0_1_:F_15 // NOD +DATA LOCATION IPL_D0_2_:B_15 // NOD DATA LOCATION LDS_000:D_12_31 // IO -DATA LOCATION N_317_i:F_14 // NOD -DATA LOCATION RESET:B_1_3 // OUT -DATA LOCATION RN_A0:G_8 // NOD {A0} -DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030} +DATA LOCATION N_226:F_14 // NOD +DATA LOCATION RESET:B_5_3 // OUT +DATA LOCATION RN_A_0_:G_8 // NOD {A_0_} +DATA LOCATION RN_BGACK_030:H_6 // NOD {BGACK_030} DATA LOCATION RN_BG_000:D_1 // NOD {BG_000} DATA LOCATION RN_DSACK1:H_9 // NOD {DSACK1} DATA LOCATION RN_IPL_030_0_:B_8 // NOD {IPL_030_0_} -DATA LOCATION RN_IPL_030_1_:B_12 // NOD {IPL_030_1_} +DATA LOCATION RN_IPL_030_1_:B_9 // NOD {IPL_030_1_} DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_} DATA LOCATION RN_RW:G_0 // NOD {RW} DATA LOCATION RN_RW_000:H_0 // NOD {RW_000} DATA LOCATION RN_VMA:D_0 // NOD {VMA} DATA LOCATION RST:*_*_86 // INP -DATA LOCATION RST_DLY_0_:D_3 // NOD -DATA LOCATION RST_DLY_1_:D_14 // NOD -DATA LOCATION RST_DLY_2_:D_7 // NOD +DATA LOCATION RST_DLY_0_:D_10 // NOD +DATA LOCATION RST_DLY_1_:D_6 // NOD +DATA LOCATION RST_DLY_2_:D_14 // NOD DATA LOCATION RW:G_0_71 // IO {RN_RW} DATA LOCATION RW_000:H_0_80 // IO {RN_RW_000} DATA LOCATION SIZE_0_:G_12_70 // IO DATA LOCATION SIZE_1_:H_12_79 // IO -DATA LOCATION SIZE_DMA_0_:G_13 // NOD -DATA LOCATION SIZE_DMA_1_:G_9 // NOD -DATA LOCATION SM_AMIGA_0_:F_1 // NOD -DATA LOCATION SM_AMIGA_1_:F_5 // NOD -DATA LOCATION SM_AMIGA_2_:F_10 // NOD -DATA LOCATION SM_AMIGA_3_:F_6 // NOD -DATA LOCATION SM_AMIGA_4_:F_9 // NOD +DATA LOCATION SIZE_DMA_0_:G_9 // NOD +DATA LOCATION SIZE_DMA_1_:G_5 // NOD +DATA LOCATION SM_AMIGA_0_:F_5 // NOD +DATA LOCATION SM_AMIGA_1_:F_13 // NOD +DATA LOCATION SM_AMIGA_2_:F_6 // NOD +DATA LOCATION SM_AMIGA_3_:F_2 // NOD +DATA LOCATION SM_AMIGA_4_:F_10 // NOD DATA LOCATION SM_AMIGA_5_:F_8 // NOD -DATA LOCATION SM_AMIGA_6_:F_4 // NOD +DATA LOCATION SM_AMIGA_6_:C_9 // NOD DATA LOCATION SM_AMIGA_i_7_:F_0 // NOD DATA LOCATION UDS_000:D_8_32 // IO DATA LOCATION VMA:D_0_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP -DATA LOCATION cpu_est_0_:D_6 // NOD -DATA LOCATION cpu_est_1_:D_2 // NOD -DATA LOCATION cpu_est_2_:D_13 // NOD -DATA LOCATION cpu_est_3_:F_12 // NOD -DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:B_13 // NOD -DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:B_2 // NOD -DATA LOCATION inst_AS_000_DMA:A_1 // NOD -DATA LOCATION inst_AS_000_INT:C_1 // NOD -DATA LOCATION inst_AS_030_000_SYNC:C_4 // NOD -DATA LOCATION inst_AS_030_D0:H_3 // NOD +DATA LOCATION cpu_est_0_:B_2 // NOD +DATA LOCATION cpu_est_1_:F_12 // NOD +DATA LOCATION cpu_est_2_:F_4 // NOD +DATA LOCATION cpu_est_3_:F_1 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:C_2 // NOD +DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:B_10 // NOD +DATA LOCATION inst_AS_000_DMA:A_12 // NOD +DATA LOCATION inst_AS_000_INT:G_2 // NOD +DATA LOCATION inst_AS_030_000_SYNC:C_13 // NOD +DATA LOCATION inst_AS_030_D0:H_1 // NOD DATA LOCATION inst_BGACK_030_INT_D:H_13 // NOD -DATA LOCATION inst_CLK_000_NE:G_2 // NOD -DATA LOCATION inst_CLK_000_NE_D0:D_10 // NOD -DATA LOCATION inst_CLK_000_PE:G_5 // NOD -DATA LOCATION inst_CLK_030_H:A_2 // NOD -DATA LOCATION inst_CLK_OUT_PRE_50:F_13 // NOD -DATA LOCATION inst_CLK_OUT_PRE_D:A_12 // NOD -DATA LOCATION inst_DS_000_DMA:A_13 // NOD -DATA LOCATION inst_DS_000_ENABLE:C_8 // NOD -DATA LOCATION inst_DTACK_D0:B_15 // NOD -DATA LOCATION inst_LDS_000_INT:A_5 // NOD +DATA LOCATION inst_CLK_000_NE_D0:E_5 // NOD +DATA LOCATION inst_CLK_030_H:A_13 // NOD +DATA LOCATION inst_CLK_OUT_PRE_50:E_2 // NOD +DATA LOCATION inst_CLK_OUT_PRE_D:E_8 // NOD +DATA LOCATION inst_DS_000_DMA:A_9 // NOD +DATA LOCATION inst_DS_000_ENABLE:F_9 // NOD +DATA LOCATION inst_DTACK_D0:C_15 // NOD +DATA LOCATION inst_LDS_000_INT:A_1 // NOD DATA LOCATION inst_RESET_OUT:D_9 // NOD -DATA LOCATION inst_UDS_000_INT:A_9 // NOD -DATA LOCATION inst_VPA_D:F_2 // NOD -DATA LOCATION inst_nEXP_SPACE_D0reg:A_8 // NOD +DATA LOCATION inst_UDS_000_INT:B_6 // NOD +DATA LOCATION inst_VPA_D:A_5 // NOD DATA LOCATION nEXP_SPACE:*_*_14 // INP -DATA IO_DIR A0:BI -DATA IO_DIR A1:IN +DATA IO_DIR AHIGH_24_:BI +DATA IO_DIR AHIGH_25_:BI +DATA IO_DIR AHIGH_26_:BI +DATA IO_DIR AHIGH_27_:BI +DATA IO_DIR AHIGH_28_:BI +DATA IO_DIR AHIGH_29_:BI +DATA IO_DIR AHIGH_30_:BI +DATA IO_DIR AHIGH_31_:BI DATA IO_DIR AMIGA_ADDR_ENABLE:OUT DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT DATA IO_DIR AMIGA_BUS_ENABLE_HIGH:OUT @@ -152,22 +168,16 @@ DATA IO_DIR AMIGA_BUS_ENABLE_LOW:OUT DATA IO_DIR AS_000:BI DATA IO_DIR AS_030:BI DATA IO_DIR AVEC:OUT -DATA IO_DIR A_16_:IN -DATA IO_DIR A_17_:IN -DATA IO_DIR A_18_:IN -DATA IO_DIR A_19_:IN -DATA IO_DIR A_20_:IN -DATA IO_DIR A_21_:IN -DATA IO_DIR A_22_:IN -DATA IO_DIR A_23_:IN -DATA IO_DIR A_24_:IN -DATA IO_DIR A_25_:IN -DATA IO_DIR A_26_:IN -DATA IO_DIR A_27_:IN -DATA IO_DIR A_28_:IN -DATA IO_DIR A_29_:IN -DATA IO_DIR A_30_:IN -DATA IO_DIR A_31_:IN +DATA IO_DIR A_0_:BI +DATA IO_DIR A_1_:IN +DATA IO_DIR A_DECODE_16_:IN +DATA IO_DIR A_DECODE_17_:IN +DATA IO_DIR A_DECODE_18_:IN +DATA IO_DIR A_DECODE_19_:IN +DATA IO_DIR A_DECODE_20_:IN +DATA IO_DIR A_DECODE_21_:IN +DATA IO_DIR A_DECODE_22_:IN +DATA IO_DIR A_DECODE_23_:IN DATA IO_DIR BERR:BI DATA IO_DIR BGACK_000:IN DATA IO_DIR BGACK_030:OUT @@ -205,22 +215,32 @@ DATA IO_DIR VMA:OUT DATA IO_DIR VPA:IN DATA IO_DIR nEXP_SPACE:IN DATA GLB_CLOCK CLK_OSZI +DATA PW_LEVEL A_DECODE_22_:1 +DATA SLEW A_DECODE_22_:1 +DATA PW_LEVEL A_DECODE_21_:1 +DATA SLEW A_DECODE_21_:1 DATA PW_LEVEL SIZE_1_:1 DATA SLEW SIZE_1_:1 -DATA PW_LEVEL A_31_:1 -DATA SLEW A_31_:1 +DATA PW_LEVEL A_DECODE_20_:1 +DATA SLEW A_DECODE_20_:1 +DATA PW_LEVEL A_DECODE_19_:1 +DATA SLEW A_DECODE_19_:1 +DATA PW_LEVEL AHIGH_31_:1 +DATA SLEW AHIGH_31_:1 +DATA PW_LEVEL A_DECODE_18_:1 +DATA SLEW A_DECODE_18_:1 +DATA PW_LEVEL A_DECODE_17_:1 +DATA SLEW A_DECODE_17_:1 +DATA PW_LEVEL A_DECODE_23_:1 +DATA SLEW A_DECODE_23_:1 +DATA PW_LEVEL A_DECODE_16_:1 +DATA SLEW A_DECODE_16_:1 DATA PW_LEVEL IPL_2_:1 DATA SLEW IPL_2_:1 -DATA PW_LEVEL IPL_1_:1 -DATA SLEW IPL_1_:1 DATA PW_LEVEL FC_1_:1 DATA SLEW FC_1_:1 -DATA PW_LEVEL IPL_0_:1 -DATA SLEW IPL_0_:1 DATA PW_LEVEL AS_030:1 DATA SLEW AS_030:1 -DATA PW_LEVEL FC_0_:1 -DATA SLEW FC_0_:1 DATA PW_LEVEL AS_000:1 DATA SLEW AS_000:1 DATA PW_LEVEL DS_030:1 @@ -229,16 +249,22 @@ DATA PW_LEVEL UDS_000:1 DATA SLEW UDS_000:1 DATA PW_LEVEL LDS_000:1 DATA SLEW LDS_000:1 -DATA PW_LEVEL A1:1 -DATA SLEW A1:1 DATA SLEW nEXP_SPACE:1 DATA PW_LEVEL BERR:1 DATA SLEW BERR:1 DATA PW_LEVEL BG_030:1 DATA SLEW BG_030:1 +DATA PW_LEVEL IPL_1_:1 +DATA SLEW IPL_1_:1 +DATA PW_LEVEL IPL_0_:1 +DATA SLEW IPL_0_:1 DATA PW_LEVEL BGACK_000:1 DATA SLEW BGACK_000:1 +DATA PW_LEVEL FC_0_:1 +DATA SLEW FC_0_:1 DATA SLEW CLK_030:1 +DATA PW_LEVEL A_1_:1 +DATA SLEW A_1_:1 DATA SLEW CLK_000:1 DATA SLEW CLK_OSZI:1 DATA PW_LEVEL CLK_DIV_OUT:1 @@ -259,56 +285,40 @@ DATA PW_LEVEL RESET:1 DATA SLEW RESET:1 DATA PW_LEVEL AMIGA_ADDR_ENABLE:1 DATA SLEW AMIGA_ADDR_ENABLE:0 -DATA PW_LEVEL SIZE_0_:1 -DATA SLEW SIZE_0_:1 DATA PW_LEVEL AMIGA_BUS_DATA_DIR:1 DATA SLEW AMIGA_BUS_DATA_DIR:0 -DATA PW_LEVEL A_30_:1 -DATA SLEW A_30_:1 DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:1 DATA SLEW AMIGA_BUS_ENABLE_LOW:0 -DATA PW_LEVEL A_29_:1 -DATA SLEW A_29_:1 DATA PW_LEVEL AMIGA_BUS_ENABLE_HIGH:1 DATA SLEW AMIGA_BUS_ENABLE_HIGH:0 -DATA PW_LEVEL A_28_:1 -DATA SLEW A_28_:1 DATA PW_LEVEL CIIN:1 DATA SLEW CIIN:1 -DATA PW_LEVEL A_27_:1 -DATA SLEW A_27_:1 -DATA PW_LEVEL A_26_:1 -DATA SLEW A_26_:1 -DATA PW_LEVEL A_25_:1 -DATA SLEW A_25_:1 -DATA PW_LEVEL A_24_:1 -DATA SLEW A_24_:1 -DATA PW_LEVEL A_23_:1 -DATA SLEW A_23_:1 -DATA PW_LEVEL A_22_:1 -DATA SLEW A_22_:1 -DATA PW_LEVEL A_21_:1 -DATA SLEW A_21_:1 -DATA PW_LEVEL A_20_:1 -DATA SLEW A_20_:1 -DATA PW_LEVEL A_19_:1 -DATA SLEW A_19_:1 -DATA PW_LEVEL A_18_:1 -DATA SLEW A_18_:1 -DATA PW_LEVEL A_17_:1 -DATA SLEW A_17_:1 -DATA PW_LEVEL A_16_:1 -DATA SLEW A_16_:1 +DATA PW_LEVEL SIZE_0_:1 +DATA SLEW SIZE_0_:1 +DATA PW_LEVEL AHIGH_30_:1 +DATA SLEW AHIGH_30_:1 +DATA PW_LEVEL AHIGH_29_:1 +DATA SLEW AHIGH_29_:1 +DATA PW_LEVEL AHIGH_28_:1 +DATA SLEW AHIGH_28_:1 +DATA PW_LEVEL AHIGH_27_:1 +DATA SLEW AHIGH_27_:1 +DATA PW_LEVEL AHIGH_26_:1 +DATA SLEW AHIGH_26_:1 +DATA PW_LEVEL AHIGH_25_:1 +DATA SLEW AHIGH_25_:1 +DATA PW_LEVEL AHIGH_24_:1 +DATA SLEW AHIGH_24_:1 DATA PW_LEVEL IPL_030_2_:1 DATA SLEW IPL_030_2_:1 +DATA PW_LEVEL RW_000:1 +DATA SLEW RW_000:1 +DATA PW_LEVEL A_0_:1 +DATA SLEW A_0_:1 DATA PW_LEVEL IPL_030_1_:1 DATA SLEW IPL_030_1_:1 DATA PW_LEVEL IPL_030_0_:1 DATA SLEW IPL_030_0_:1 -DATA PW_LEVEL RW_000:1 -DATA SLEW RW_000:1 -DATA PW_LEVEL A0:1 -DATA SLEW A0:1 DATA PW_LEVEL BG_000:1 DATA SLEW BG_000:1 DATA PW_LEVEL BGACK_030:1 @@ -321,8 +331,8 @@ DATA PW_LEVEL VMA:1 DATA SLEW VMA:1 DATA PW_LEVEL RW:1 DATA SLEW RW:1 -DATA PW_LEVEL N_317_i:1 -DATA SLEW N_317_i:1 +DATA PW_LEVEL N_226:1 +DATA SLEW N_226:1 DATA PW_LEVEL cpu_est_2_:1 DATA SLEW cpu_est_2_:1 DATA PW_LEVEL cpu_est_3_:1 @@ -333,14 +343,10 @@ DATA PW_LEVEL cpu_est_1_:1 DATA SLEW cpu_est_1_:1 DATA PW_LEVEL inst_AS_000_INT:1 DATA SLEW inst_AS_000_INT:1 -DATA PW_LEVEL SM_AMIGA_5_:1 -DATA SLEW SM_AMIGA_5_:1 DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_LOW:1 DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_LOW:1 DATA PW_LEVEL inst_AS_030_D0:1 DATA SLEW inst_AS_030_D0:1 -DATA PW_LEVEL inst_nEXP_SPACE_D0reg:1 -DATA SLEW inst_nEXP_SPACE_D0reg:1 DATA PW_LEVEL inst_AS_030_000_SYNC:1 DATA SLEW inst_AS_030_000_SYNC:1 DATA PW_LEVEL inst_BGACK_030_INT_D:1 @@ -365,6 +371,10 @@ DATA PW_LEVEL inst_LDS_000_INT:1 DATA SLEW inst_LDS_000_INT:1 DATA PW_LEVEL inst_CLK_OUT_PRE_D:1 DATA SLEW inst_CLK_OUT_PRE_D:1 +DATA PW_LEVEL CLK_000_D_10_:1 +DATA SLEW CLK_000_D_10_:1 +DATA PW_LEVEL CLK_000_D_11_:1 +DATA SLEW CLK_000_D_11_:1 DATA PW_LEVEL inst_DTACK_D0:1 DATA SLEW inst_DTACK_D0:1 DATA PW_LEVEL inst_RESET_OUT:1 @@ -375,30 +385,44 @@ DATA PW_LEVEL CLK_000_D_1_:1 DATA SLEW CLK_000_D_1_:1 DATA PW_LEVEL CLK_000_D_0_:1 DATA SLEW CLK_000_D_0_:1 -DATA PW_LEVEL inst_CLK_000_PE:1 -DATA SLEW inst_CLK_000_PE:1 -DATA PW_LEVEL CLK_000_P_SYNC_9_:1 -DATA SLEW CLK_000_P_SYNC_9_:1 -DATA PW_LEVEL inst_CLK_000_NE:1 -DATA SLEW inst_CLK_000_NE:1 -DATA PW_LEVEL CLK_000_N_SYNC_11_:1 -DATA SLEW CLK_000_N_SYNC_11_:1 +DATA PW_LEVEL CLK_000_P_SYNC_10_:1 +DATA SLEW CLK_000_P_SYNC_10_:1 +DATA PW_LEVEL SM_AMIGA_5_:1 +DATA SLEW SM_AMIGA_5_:1 DATA PW_LEVEL IPL_D0_0_:1 DATA SLEW IPL_D0_0_:1 DATA PW_LEVEL IPL_D0_1_:1 DATA SLEW IPL_D0_1_:1 DATA PW_LEVEL IPL_D0_2_:1 DATA SLEW IPL_D0_2_:1 -DATA PW_LEVEL inst_CLK_000_NE_D0:1 -DATA SLEW inst_CLK_000_NE_D0:1 +DATA PW_LEVEL CLK_000_D_2_:1 +DATA SLEW CLK_000_D_2_:1 +DATA PW_LEVEL CLK_000_D_3_:1 +DATA SLEW CLK_000_D_3_:1 +DATA PW_LEVEL CLK_000_D_4_:1 +DATA SLEW CLK_000_D_4_:1 +DATA PW_LEVEL CLK_000_D_5_:1 +DATA SLEW CLK_000_D_5_:1 +DATA PW_LEVEL CLK_000_D_6_:1 +DATA SLEW CLK_000_D_6_:1 +DATA PW_LEVEL CLK_000_D_7_:1 +DATA SLEW CLK_000_D_7_:1 +DATA PW_LEVEL CLK_000_D_8_:1 +DATA SLEW CLK_000_D_8_:1 +DATA PW_LEVEL CLK_000_D_9_:1 +DATA SLEW CLK_000_D_9_:1 +DATA PW_LEVEL CLK_000_D_12_:1 +DATA SLEW CLK_000_D_12_:1 DATA PW_LEVEL SM_AMIGA_0_:1 DATA SLEW SM_AMIGA_0_:1 -DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 -DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 +DATA PW_LEVEL CLK_000_N_SYNC_0_:1 +DATA SLEW CLK_000_N_SYNC_0_:1 DATA PW_LEVEL SM_AMIGA_4_:1 DATA SLEW SM_AMIGA_4_:1 DATA PW_LEVEL inst_DS_000_ENABLE:1 DATA SLEW inst_DS_000_ENABLE:1 +DATA PW_LEVEL CLK_000_N_SYNC_12_:1 +DATA SLEW CLK_000_N_SYNC_12_:1 DATA PW_LEVEL RST_DLY_0_:1 DATA SLEW RST_DLY_0_:1 DATA PW_LEVEL RST_DLY_1_:1 @@ -423,8 +447,8 @@ DATA PW_LEVEL CLK_000_P_SYNC_7_:1 DATA SLEW CLK_000_P_SYNC_7_:1 DATA PW_LEVEL CLK_000_P_SYNC_8_:1 DATA SLEW CLK_000_P_SYNC_8_:1 -DATA PW_LEVEL CLK_000_N_SYNC_0_:1 -DATA SLEW CLK_000_N_SYNC_0_:1 +DATA PW_LEVEL CLK_000_P_SYNC_9_:1 +DATA SLEW CLK_000_P_SYNC_9_:1 DATA PW_LEVEL CLK_000_N_SYNC_1_:1 DATA SLEW CLK_000_N_SYNC_1_:1 DATA PW_LEVEL CLK_000_N_SYNC_2_:1 @@ -445,6 +469,12 @@ DATA PW_LEVEL CLK_000_N_SYNC_9_:1 DATA SLEW CLK_000_N_SYNC_9_:1 DATA PW_LEVEL CLK_000_N_SYNC_10_:1 DATA SLEW CLK_000_N_SYNC_10_:1 +DATA PW_LEVEL CLK_000_N_SYNC_11_:1 +DATA SLEW CLK_000_N_SYNC_11_:1 +DATA PW_LEVEL inst_CLK_000_NE_D0:1 +DATA SLEW inst_CLK_000_NE_D0:1 +DATA PW_LEVEL inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 +DATA SLEW inst_AMIGA_BUS_ENABLE_DMA_HIGH:1 DATA PW_LEVEL SM_AMIGA_6_:1 DATA SLEW SM_AMIGA_6_:1 DATA PW_LEVEL inst_CLK_030_H:1 @@ -460,10 +490,10 @@ DATA SLEW SM_AMIGA_i_7_:1 DATA PW_LEVEL CIIN_0:1 DATA SLEW CIIN_0:1 DATA PW_LEVEL RN_IPL_030_2_:1 +DATA PW_LEVEL RN_RW_000:1 +DATA PW_LEVEL RN_A_0_:1 DATA PW_LEVEL RN_IPL_030_1_:1 DATA PW_LEVEL RN_IPL_030_0_:1 -DATA PW_LEVEL RN_RW_000:1 -DATA PW_LEVEL RN_A0:1 DATA PW_LEVEL RN_BG_000:1 DATA PW_LEVEL RN_BGACK_030:1 DATA PW_LEVEL RN_DSACK1:1 diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index f7c6278..6161d0d 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,28 +1,30 @@ GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA inst_LDS_000_INT - inst_UDS_000_INT inst_nEXP_SPACE_D0reg CLK_000_P_SYNC_6_ CLK_000_N_SYNC_1_ - CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ inst_CLK_OUT_PRE_D DS_030 AVEC - + CYCLE_DMA_1_ CYCLE_DMA_0_ inst_VPA_D CLK_000_P_SYNC_10_ CLK_000_P_SYNC_1_ + CLK_000_P_SYNC_4_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_4_ + CLK_000_N_SYNC_5_ DS_030 AVEC GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ - RN_IPL_030_2_ CLK_EXP inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AMIGA_BUS_ENABLE_DMA_HIGH - CYCLE_DMA_0_ inst_DTACK_D0 IPL_D0_2_ CLK_000_D_0_ CLK_000_P_SYNC_1_ - CLK_000_P_SYNC_7_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ - RESET -GROUP MACH_SEG_C inst_AS_030_000_SYNC inst_DS_000_ENABLE CYCLE_DMA_1_ inst_AS_000_INT - AMIGA_BUS_ENABLE_LOW + RN_IPL_030_2_ CLK_EXP inst_AMIGA_BUS_ENABLE_DMA_LOW inst_UDS_000_INT + cpu_est_0_ IPL_D0_2_ CLK_000_D_6_ CLK_000_D_8_ CLK_000_N_SYNC_6_ + CLK_000_N_SYNC_8_ AHIGH_31_ AHIGH_30_ AHIGH_29_ RESET +GROUP MACH_SEG_C inst_AS_030_000_SYNC SM_AMIGA_6_ inst_AMIGA_BUS_ENABLE_DMA_HIGH + inst_DTACK_D0 CLK_000_D_4_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_9_ CLK_000_N_SYNC_10_ + CLK_000_N_SYNC_11_ CLK_000_D_1_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ + AHIGH_24_ AMIGA_BUS_ENABLE_LOW GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 inst_RESET_OUT RST_DLY_0_ - RST_DLY_1_ RST_DLY_2_ cpu_est_2_ cpu_est_1_ cpu_est_0_ IPL_D0_1_ - CLK_000_N_SYNC_5_ inst_CLK_000_NE_D0 LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH - AMIGA_ADDR_ENABLE -GROUP MACH_SEG_E CLK_000_P_SYNC_0_ CLK_000_N_SYNC_0_ CLK_000_P_SYNC_3_ - CLK_000_D_1_ CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 -GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ SM_AMIGA_6_ SM_AMIGA_1_ - SM_AMIGA_0_ SM_AMIGA_4_ SM_AMIGA_5_ cpu_est_3_ inst_VPA_D CLK_000_N_SYNC_7_ - inst_CLK_OUT_PRE_50 N_317_i -GROUP MACH_SEG_G A0 RN_A0 RW RN_RW CLK_DIV_OUT SIZE_DMA_0_ SIZE_DMA_1_ - IPL_D0_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_P_SYNC_2_ - CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_6_ - SIZE_0_ E + RST_DLY_1_ RST_DLY_2_ CLK_000_N_SYNC_0_ CLK_000_P_SYNC_0_ IPL_D0_0_ + CLK_000_D_9_ CLK_000_N_SYNC_12_ CLK_000_P_SYNC_7_ AMIGA_BUS_ENABLE_HIGH + LDS_000 UDS_000 AMIGA_ADDR_ENABLE +GROUP MACH_SEG_E CLK_000_D_5_ inst_CLK_OUT_PRE_D inst_CLK_OUT_PRE_50 CLK_000_N_SYNC_1_ + inst_CLK_000_NE_D0 CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 +GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ inst_DS_000_ENABLE + SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_4_ SM_AMIGA_5_ cpu_est_3_ cpu_est_2_ + cpu_est_1_ IPL_D0_1_ CLK_000_P_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_9_ + N_226 +GROUP MACH_SEG_G A_0_ RN_A_0_ RW RN_RW CLK_DIV_OUT SIZE_DMA_0_ SIZE_DMA_1_ + inst_AS_000_INT CLK_000_D_10_ CLK_000_D_3_ CLK_000_D_7_ CLK_000_P_SYNC_5_ + CLK_000_P_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_D_0_ CLK_000_D_2_ SIZE_0_ + E GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 BGACK_030 RN_BGACK_030 - inst_AS_030_D0 inst_BGACK_030_INT_D CLK_000_N_SYNC_11_ CLK_000_N_SYNC_10_ - FPU_CS AS_030 SIZE_1_ \ No newline at end of file + inst_AS_030_D0 inst_BGACK_030_INT_D CLK_000_D_11_ CLK_000_D_12_ FPU_CS + AS_030 SIZE_1_ \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index fd30cdc..35e5b62 100644 --- a/Logic/68030_tk.ipr +++ b/Logic/68030_tk.ipr @@ -1 +1 @@ -755;017}nxñA.c \ No newline at end of file +15:;107B74eO \ No newline at end of file diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed index ef3d250..a3cc5af 100644 --- a/Logic/68030_tk.jed +++ b/Logic/68030_tk.jed @@ -10,7 +10,7 @@ AUTHOR: PATTERN: COMPANY: REVISION: -DATE: Wed Aug 17 17:45:51 2016 +DATE: Fri Aug 19 00:20:46 2016 ABEL mach447a * @@ -31,83 +31,90 @@ NOTE Spread Placement? Y * NOTE Run Time Upper Bound in 15 minutes 0 * NOTE Zero Hold Time For Input Registers? Y * NOTE Table of pin names and numbers* -NOTE PINS SIZE_1_:79 A_31_:4 IPL_2_:68 IPL_1_:56 FC_1_:58* -NOTE PINS IPL_0_:67 AS_030:82 FC_0_:57 AS_000:42 DS_030:98* -NOTE PINS UDS_000:32 LDS_000:31 A1:60 nEXP_SPACE:14 BERR:41* -NOTE PINS BG_030:21 BGACK_000:28 CLK_030:64 CLK_000:11 CLK_OSZI:61* -NOTE PINS CLK_DIV_OUT:65 FPU_CS:78 FPU_SENSE:91 DTACK:30* -NOTE PINS AVEC:92 E:66 VPA:36 RST:86 RESET:3 AMIGA_ADDR_ENABLE:33* -NOTE PINS SIZE_0_:70 AMIGA_BUS_DATA_DIR:48 A_30_:5 AMIGA_BUS_ENABLE_LOW:20* -NOTE PINS A_29_:6 AMIGA_BUS_ENABLE_HIGH:34 A_28_:15 CIIN:47* -NOTE PINS A_27_:16 A_26_:17 A_25_:18 A_24_:19 A_23_:85 A_22_:84* -NOTE PINS A_21_:94 A_20_:93 A_19_:97 A_18_:95 A_17_:59 A_16_:96* -NOTE PINS IPL_030_2_:9 IPL_030_1_:7 IPL_030_0_:8 RW_000:80* -NOTE PINS A0:69 BG_000:29 BGACK_030:83 CLK_EXP:10 DSACK1:81* -NOTE PINS VMA:35 RW:71 * +NOTE PINS A_DECODE_22_:84 A_DECODE_21_:94 SIZE_1_:79 A_DECODE_20_:93* +NOTE PINS A_DECODE_19_:97 AHIGH_31_:4 A_DECODE_18_:95 A_DECODE_17_:59* +NOTE PINS A_DECODE_23_:85 A_DECODE_16_:96 IPL_2_:68 FC_1_:58* +NOTE PINS AS_030:82 AS_000:42 DS_030:98 UDS_000:32 LDS_000:31* +NOTE PINS nEXP_SPACE:14 BERR:41 BG_030:21 IPL_1_:56 IPL_0_:67* +NOTE PINS BGACK_000:28 FC_0_:57 CLK_030:64 A_1_:60 CLK_000:11* +NOTE PINS CLK_OSZI:61 CLK_DIV_OUT:65 FPU_CS:78 FPU_SENSE:91* +NOTE PINS DTACK:30 AVEC:92 E:66 VPA:36 RST:86 RESET:3 AMIGA_ADDR_ENABLE:33* +NOTE PINS AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20 AMIGA_BUS_ENABLE_HIGH:34* +NOTE PINS CIIN:47 SIZE_0_:70 AHIGH_30_:5 AHIGH_29_:6 AHIGH_28_:15* +NOTE PINS AHIGH_27_:16 AHIGH_26_:17 AHIGH_25_:18 AHIGH_24_:19* +NOTE PINS IPL_030_2_:9 RW_000:80 A_0_:69 IPL_030_1_:7 IPL_030_0_:8* +NOTE PINS BG_000:29 BGACK_030:83 CLK_EXP:10 DSACK1:81 VMA:35* +NOTE PINS RW:71 * NOTE Table of node names and numbers* -NOTE NODES RN_SIZE_1_:287 RN_AS_030:281 RN_AS_000:203 RN_UDS_000:185 * -NOTE NODES RN_LDS_000:191 RN_BERR:197 RN_SIZE_0_:263 RN_IPL_030_2_:131 * -NOTE NODES RN_IPL_030_1_:143 RN_IPL_030_0_:137 RN_RW_000:269 * -NOTE NODES RN_A0:257 RN_BG_000:175 RN_BGACK_030:275 RN_DSACK1:283 * -NOTE NODES RN_VMA:173 RN_RW:245 N_317_i:242 cpu_est_2_:193 * -NOTE NODES cpu_est_3_:239 cpu_est_0_:182 cpu_est_1_:176 * -NOTE NODES inst_AS_000_INT:151 SM_AMIGA_5_:233 inst_AMIGA_BUS_ENABLE_DMA_LOW:128 * -NOTE NODES inst_AS_030_D0:274 inst_nEXP_SPACE_D0reg:113 * -NOTE NODES inst_AS_030_000_SYNC:155 inst_BGACK_030_INT_D:289 * -NOTE NODES inst_AS_000_DMA:103 inst_DS_000_DMA:121 CYCLE_DMA_0_:133 * -NOTE NODES CYCLE_DMA_1_:167 SIZE_DMA_0_:265 SIZE_DMA_1_:259 * -NOTE NODES inst_VPA_D:224 inst_UDS_000_INT:115 inst_LDS_000_INT:109 * -NOTE NODES inst_CLK_OUT_PRE_D:119 inst_DTACK_D0:148 inst_RESET_OUT:187 * -NOTE NODES inst_CLK_OUT_PRE_50:241 CLK_000_D_1_:209 CLK_000_D_0_:139 * -NOTE NODES inst_CLK_000_PE:253 CLK_000_P_SYNC_9_:268 inst_CLK_000_NE:248 * -NOTE NODES CLK_000_N_SYNC_11_:278 IPL_D0_0_:262 IPL_D0_1_:196 * -NOTE NODES IPL_D0_2_:142 inst_CLK_000_NE_D0:188 SM_AMIGA_0_:223 * -NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_HIGH:145 SM_AMIGA_4_:235 * -NOTE NODES inst_DS_000_ENABLE:161 RST_DLY_0_:178 RST_DLY_1_:194 * -NOTE NODES RST_DLY_2_:184 CLK_000_P_SYNC_0_:200 CLK_000_P_SYNC_1_:136 * -NOTE NODES CLK_000_P_SYNC_2_:256 CLK_000_P_SYNC_3_:217 CLK_000_P_SYNC_4_:250 * -NOTE NODES CLK_000_P_SYNC_5_:266 CLK_000_P_SYNC_6_:106 CLK_000_P_SYNC_7_:130 * -NOTE NODES CLK_000_P_SYNC_8_:260 CLK_000_N_SYNC_0_:211 CLK_000_N_SYNC_1_:122 * -NOTE NODES CLK_000_N_SYNC_2_:146 CLK_000_N_SYNC_3_:140 CLK_000_N_SYNC_4_:134 * -NOTE NODES CLK_000_N_SYNC_5_:190 CLK_000_N_SYNC_6_:254 CLK_000_N_SYNC_7_:226 * -NOTE NODES CLK_000_N_SYNC_8_:116 CLK_000_N_SYNC_9_:110 CLK_000_N_SYNC_10_:272 * -NOTE NODES SM_AMIGA_6_:227 inst_CLK_030_H:104 SM_AMIGA_1_:229 * -NOTE NODES SM_AMIGA_3_:230 SM_AMIGA_2_:236 SM_AMIGA_i_7_:221 * -NOTE NODES CIIN_0:205 * +NOTE NODES RN_SIZE_1_:287 RN_AHIGH_31_:143 RN_AS_030:281 * +NOTE NODES RN_AS_000:203 RN_UDS_000:185 RN_LDS_000:191 RN_BERR:197 * +NOTE NODES RN_SIZE_0_:263 RN_AHIGH_30_:125 RN_AHIGH_29_:145 * +NOTE NODES RN_AHIGH_28_:149 RN_AHIGH_27_:155 RN_AHIGH_26_:157 * +NOTE NODES RN_AHIGH_25_:167 RN_AHIGH_24_:161 RN_IPL_030_2_:131 * +NOTE NODES RN_RW_000:269 RN_A_0_:257 RN_IPL_030_1_:139 RN_IPL_030_0_:137 * +NOTE NODES RN_BG_000:175 RN_BGACK_030:278 RN_DSACK1:283 * +NOTE NODES RN_VMA:173 RN_RW:245 N_226:242 cpu_est_2_:227 * +NOTE NODES cpu_est_3_:223 cpu_est_0_:128 cpu_est_1_:239 * +NOTE NODES inst_AS_000_INT:248 inst_AMIGA_BUS_ENABLE_DMA_LOW:140 * +NOTE NODES inst_AS_030_D0:271 inst_AS_030_000_SYNC:169 inst_BGACK_030_INT_D:289 * +NOTE NODES inst_AS_000_DMA:119 inst_DS_000_DMA:115 CYCLE_DMA_0_:116 * +NOTE NODES CYCLE_DMA_1_:104 SIZE_DMA_0_:259 SIZE_DMA_1_:253 * +NOTE NODES inst_VPA_D:109 inst_UDS_000_INT:134 inst_LDS_000_INT:103 * +NOTE NODES inst_CLK_OUT_PRE_D:209 CLK_000_D_10_:268 CLK_000_D_11_:284 * +NOTE NODES inst_DTACK_D0:172 inst_RESET_OUT:187 inst_CLK_OUT_PRE_50:200 * +NOTE NODES CLK_000_D_1_:158 CLK_000_D_0_:265 CLK_000_P_SYNC_10_:113 * +NOTE NODES SM_AMIGA_5_:233 IPL_D0_0_:196 IPL_D0_1_:244 IPL_D0_2_:148 * +NOTE NODES CLK_000_D_2_:262 CLK_000_D_3_:256 CLK_000_D_4_:166 * +NOTE NODES CLK_000_D_5_:217 CLK_000_D_6_:142 CLK_000_D_7_:250 * +NOTE NODES CLK_000_D_8_:136 CLK_000_D_9_:190 CLK_000_D_12_:272 * +NOTE NODES SM_AMIGA_0_:229 CLK_000_N_SYNC_0_:176 SM_AMIGA_4_:236 * +NOTE NODES inst_DS_000_ENABLE:235 CLK_000_N_SYNC_12_:193 * +NOTE NODES RST_DLY_0_:188 RST_DLY_1_:182 RST_DLY_2_:194 * +NOTE NODES CLK_000_P_SYNC_0_:184 CLK_000_P_SYNC_1_:124 CLK_000_P_SYNC_2_:238 * +NOTE NODES CLK_000_P_SYNC_3_:160 CLK_000_P_SYNC_4_:118 CLK_000_P_SYNC_5_:266 * +NOTE NODES CLK_000_P_SYNC_6_:260 CLK_000_P_SYNC_7_:178 CLK_000_P_SYNC_8_:112 * +NOTE NODES CLK_000_P_SYNC_9_:154 CLK_000_N_SYNC_1_:211 CLK_000_N_SYNC_2_:106 * +NOTE NODES CLK_000_N_SYNC_3_:232 CLK_000_N_SYNC_4_:122 CLK_000_N_SYNC_5_:110 * +NOTE NODES CLK_000_N_SYNC_6_:130 CLK_000_N_SYNC_7_:254 CLK_000_N_SYNC_8_:146 * +NOTE NODES CLK_000_N_SYNC_9_:226 CLK_000_N_SYNC_10_:170 * +NOTE NODES CLK_000_N_SYNC_11_:164 inst_CLK_000_NE_D0:205 * +NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_HIGH:152 SM_AMIGA_6_:163 * +NOTE NODES inst_CLK_030_H:121 SM_AMIGA_1_:241 SM_AMIGA_3_:224 * +NOTE NODES SM_AMIGA_2_:230 SM_AMIGA_i_7_:221 CIIN_0:212 * NOTE BLOCK 0 * L000000 - 111111110111111111111110111111101111111110111111111111111111111111 - 111111111101111111111111111111111110111111111111111111111111111111 - 101111111111111111111111111111111111111111111111111111110111111111 - 111111111111111011111011111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111111111 - 111111111111111111111111111101111111111111111111110111101111111111 - 111110011111101111111111011111111111110111111111011111111111111111 - 111111111111111101111111111111111111011111111110111111111111111111 - 111111111111111111011111111111111011111111100111111111111111111111* + 111111111011111111111111111111111111111111111111111111111111111111 + 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111111110111111111111111111111111111111111111111111111110111111111* -L000990 111111111011111111111111111111111111111111111111111111111011111111* -L001056 111111111111111111111111111111110111111111111111111111111111111111* -L001122 111111111111111101111111111111111111111111111111011111111111111111* +L000660 111111111111111111111111111111111111111011111111111110111111111111* +L000726 000000000000000000000000000000000000000000000000000000000000000000* +L000792 000000000000000000000000000000000000000000000000000000000000000000* +L000858 000000000000000000000000000000000000000000000000000000000000000000* +L000924 000000000000000000000000000000000000000000000000000000000000000000* +L000990 111111111111111111111111111111111111111111111111101111111111111111* +L001056 111111111111111111111111111111111111111111011110111111111111111111* +L001122 101111111111111111111111111111111101111110111101111111111111111111* L001188 000000000000000000000000000000000000000000000000000000000000000000* L001254 000000000000000000000000000000000000000000000000000000000000000000* L001320 111111111111111111111111111111111111111111111111111111111111111111* -L001386 111111110111111110101111111111111011111110011110111111111011111111* -L001452 111111111011111110101111111111111011111110011110111111110111111111* -L001518 111111110111111110111111111111111011111111010110111111111011111111* -L001584 111111111011111110111111111111111011111111010110111111110111111111* -L001650 111111110111111111101111111111111011111110011110101111111011111111* -L001716 111111111111111111111101111111111111111111111111111111111111111111* -L001782 111111111011111111101111111111111011111110011110101111110111111111* -L001848 111111110111111111111111111111111011111111010110101111111011111111* -L001914 111111111011111111111111111111111011111111010110101111110111111111* +L001386 111111111111111111111111111110111111111111110111011110111111101111* +L001452 111111111111111111111111111101111111011111111011011110111111101111* +L001518 111111111111111111111111111111111111101111110111011110111111101111* +L001584 000000000000000000000000000000000000000000000000000000000000000000* +L001650 000000000000000000000000000000000000000000000000000000000000000000* +L001716 111101111111111111111111111111111111111111111111111111111111111111* +L001782 000000000000000000000000000000000000000000000000000000000000000000* +L001848 000000000000000000000000000000000000000000000000000000000000000000* +L001914 000000000000000000000000000000000000000000000000000000000000000000* L001980 000000000000000000000000000000000000000000000000000000000000000000* L002046 000000000000000000000000000000000000000000000000000000000000000000* @@ -116,385 +123,385 @@ L002178 000000000000000000000000000000000000000000000000000000000000000000* L002244 000000000000000000000000000000000000000000000000000000000000000000* L002310 000000000000000000000000000000000000000000000000000000000000000000* L002376 000000000000000000000000000000000000000000000000000000000000000000* -L002442 111111111111111111111111111111111111111111101111111111111111111111* -L002508 111111111111111111111011111111111111011111111111111111111111111111* -L002574 101111111111111111110111111111111101111111111111111111101111111111* +L002442 111111111111111111111011111111111111111111111111011111111111111111* +L002508 000000000000000000000000000000000000000000000000000000000000000000* +L002574 000000000000000000000000000000000000000000000000000000000000000000* L002640 000000000000000000000000000000000000000000000000000000000000000000* L002706 000000000000000000000000000000000000000000000000000000000000000000* L002772 000000000000000000000000000000000000000000000000000000000000000000* -L002838 111111111111111111111111111101111111111111111111111111111111111111* -L002904 111111111111111111111111111111111111111111111111111111111111111111* -L002970 111111111111111111111111111111111111111111111111111111111111111111* -L003036 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000000000000000000000000000000000000000000000000000000000000000000* -L004158 000000000000000000000000000000000000000000000000000000000000000000* +L003564 111111111111111111111111011111111111111111111111111111111111111111* +L003630 000000000000000000000000000000000000000000000000000000000000000000* +L003696 000000000000000000000000000000000000000000000000000000000000000000* +L003762 000000000000000000000000000000000000000000000000000000000000000000* +L003828 000000000000000000000000000000000000000000000000000000000000000000* +L003894 111111111111111111111111111111111111111111111111101111111111111111* +L003960 111111111111111111111111111111111111111111111111111111111111011111* +L004026 111111111111111111111111111101111111111111110111111111111111111111* +L004092 111111111111111111111111111110111111111111111011111111111111111111* +L004158 111111111111111111111111111111111111111111111111111101111111111111* L004224 000000000000000000000000000000000000000000000000000000000000000000* -L004290 111111111111110111111111111111111111111111111111111111111111111111* -L004356 111111111111111111111111111111111111111111111111111111111111111111* -L004422 111111111111111111111111111111111111111111111111111111111111111111* -L004488 111111111111111111111111111111111111111111111111111111111111111111* -L004554 111111111111111111111111111111111111111111111111111111111111111111* -L004620 111111111111111111111111111111111111111111111111111111111111111111* -L004686 111111111111111111111111111111111111111111111111111111111111111111* -L004752 111111111111111111111111111111111111111111111111111111111111111111* -L004818 111111111111111111111111111111111111111111111111111111111111111111* -L004884 111111111111111111111111111111111111111111111111111111111111111111* +L004290 111111111111111111111111111110111111011111111111011110111111101111* +L004356 111111111111111111111111111101111111101111111111011110111111101111* +L004422 000000000000000000000000000000000000000000000000000000000000000000* +L004488 000000000000000000000000000000000000000000000000000000000000000000* +L004554 000000000000000000000000000000000000000000000000000000000000000000* +L004620 111111111111011111111111111111111111111111111111111111111111111111* +L004686 111111111111111101111111111111111111111111111111111111011111111111* +L004752 111111111011111111111111111111111111110111111111111111111011111111* +L004818 111111110111111111111111111111011111111111111111110111111011111111* +L004884 111111111111111111111111111111111111110111111111111011111011111111* L004950 000000000000000000000000000000000000000000000000000000000000000000* -L005016 111111111111111111111111111111011111111111111111111111111111111111* -L005082 111111111111111111111111111111111111111111101111111111111111111111* -L005148 111111111111111111111111111111111111111111111101111111111111111111* -L005214 111111110111111111111111111111111111111111111111111111110111111111* -L005280 111111111011111111111111111111111111111111111111111111111011111111* -L005346 111111111111111111111111111111110111111111111111111111111111111111* -L005412 111111111111111101111111111111111111111111111111011111111111111111* -L005478 111111111111101111111111111111111111111110111111110111111111111111* -L005544 111111111111101111011111111111111111111101110111111111111111111111* -L005610 111111111111101111111111111111111111111111111011110111111111111111* +L005016 111111111111111111111111111111111111111111111111101111111111111111* +L005082 111111111111111111111111111111111111111111111111111111111111011111* +L005148 111111111011111111111111111111011111111111111111111111111111111111* +L005214 111111111111111111111111111101111111111111110111111111111111111111* +L005280 111111111111111111111111111110111111111111111011111111111111111111* +L005346 111111111111111111111111111111111111111111111111111101111111111111* +L005412 111111111111111101111111111111111111111111111111111111011111111111* +L005478 000000000000000000000000000000000000000000000000000000000000000000* +L005544 000000000000000000000000000000000000000000000000000000000000000000* +L005610 000000000000000000000000000000000000000000000000000000000000000000* L005676 - 111111101111111111111111011111111111111111111110111111111111111111* -L005742 111101111111111111111111111111111111111111111111111111111111111111* -L005808 111111111111111111111111111111111111111111111111111111111111111111* -L005874 111111111111111111111111111111111111111111111111111111111111111111* -L005940 111111111111111111111111111111111111111111111111111111111111111111* -L006006 111111111111111111111111111111111111111111111111111111111111111111* -L006072 111111111111111111111111111111111111111111111111111111111111111111* -L006138 111111111111111111111111111111111111111111111111111111111111111111* -L006204 111111111111111111111111111111111111111111111111111111111111111111* -L006270 111111111111111111111111111111111111111111111111111111111111111111* -L006336 111111111111111111111111111111111111111111111111111111111111111111* + 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-L006538 01010011111000* +L006538 01100011111000* L006552 10100110010011* L006566 10100110010101* -L006580 00110110011111* +L006580 00100110011111* L006594 00101111111000* -L006608 10100110010010* -L006622 00010110010000* -L006636 11100011110011* -L006650 01110110010000* -L006664 11100110010010* -L006678 00010110010000* -L006692 11101111110011* -L006706 00010110010001* -L006720 10100110010011* -L006734 00010110010100* -L006748 11100011111111* +L006608 01100110010010* +L006622 00100110010000* +L006636 00100110010011* +L006650 00100110010000* +L006664 10100110010010* +L006678 10100110010000* +L006692 00000110010011* +L006706 10100110010001* +L006720 10110110010011* +L006734 00110110010100* +L006748 00000110011110* NOTE BLOCK 1 * L006762 - 110111011111111111111111111111111111111111111111111111110101111111 - 111111111111110111111111011011111111111111111111111111111111111111 - 111111111011111101111111111111111111111111101111111111111111110111 - 101111111111111111110111111111111111111111111011111111011111111111 - 111101111111111111111110111111111111111101111111111111111111111111 - 111111111111111111011111111111111111111011111111111111111111111111 - 111111111111111111111111111101111111111111111111110111111111111111 - 111111111111011111111111111111111111111111111110111111111111111111 - 111111111111111111111111111111101011111111111111101111111111111111* + 111111111111111101111111111111111111111011111111111111111111111111 + 111111011111011111111111011111011111111111111111111111111111111111 + 111111111010111111111101111111111101101111111111111111111111111011 + 101111111111111111110111111111111111111111111111101111011111111111 + 111101111111111111111111111111111111111111111110111111111111111111 + 111111111111111011111111111011111111111111111111111111111111111111 + 111111111111111111111111111111111011111111110111110111111111111111 + 111111111111111111111111111110111111111111111111111111111111101111 + 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000000000000000000000000000000000000000000000000000000000000000000* L008082 111111111111111111111111111111111111111111111111111111111111111111* -L008148 111111111111111111111101111111111111111111111110011111111111111111* -L008214 111111111111111111111011111111111111110111111101011111111111111111* +L008148 111111111111111111111011111101111111111111111111111111111111111111* +L008214 111111111111111111110111111110111111111111111111111111111111111111* L008280 000000000000000000000000000000000000000000000000000000000000000000* L008346 000000000000000000000000000000000000000000000000000000000000000000* L008412 000000000000000000000000000000000000000000000000000000000000000000* -L008478 111111111111011111111111111111111111111111111111111111111111111111* -L008544 000000000000000000000000000000000000000000000000000000000000000000* -L008610 000000000000000000000000000000000000000000000000000000000000000000* -L008676 000000000000000000000000000000000000000000000000000000000000000000* -L008742 000000000000000000000000000000000000000000000000000000000000000000* +L008478 111111111111111111111111111111111111111111110111111111111111111111* +L008544 011101111011111110111111111111111111110111011111111111111111110111* +L008610 101110111011111110111111111111111111110111011111111111111111110111* +L008676 011101111011111110111111111111111111111011011111111111111111111011* +L008742 101110111011111110111111111111111111111011011111111111111111111011* L008808 111111111111111111111111111111111111111111111111111111111111111111* -L008874 011101111011111011111111110111111111111111011111011111111111111111* -L008940 101101111011111011111111111011111111111111011111011111111111111111* -L009006 011110111011111011111111110111111111111111101111011111111111111111* -L009072 101110111011111011111111111011111111111111101111011111111111111111* -L009138 111111111011111111111111111111111111111111111111011111101111111111* -L009204 101111111111111111111111110111111111111111111111011111101111111111* -L009270 011111111111111111111111111011111111111111111111011111101111111111* -L009336 111101111111111111111111111111111111111111101111011111101111111111* -L009402 111110111111111111111111111111111111111111011111011111101111111111* -L009468 111111111111111011111111111111111111111111111111011111101111111111* +L008874 111111111011111111111111111111111111111111011111111111101111111111* +L008940 101101111111111111111111111111111111111111011111111111101111111111* +L009006 011110111111111111111111111111111111111111011111111111101111111111* +L009072 111111111111111111111111111111111111110111011111111111101111111011* +L009138 111111111111111111111111111111111111111011011111111111101111110111* +L009204 000000000000000000000000000000000000000000000000000000000000000000* +L009270 111111111111111110111111111111111111111111011111111111101111111111* +L009336 000000000000000000000000000000000000000000000000000000000000000000* +L009402 000000000000000000000000000000000000000000000000000000000000000000* +L009468 000000000000000000000000000000000000000000000000000000000000000000* L009534 111111111111111111111111111111111111111111111111111111111111111111* -L009600 111111111111111111111111011111111111111111111111111111111111111111* -L009666 000000000000000000000000000000000000000000000000000000000000000000* +L009600 111111101111111111111110111111111111111111011111111111111111111111* +L009666 111111011111111111111111111111111111101111011111111111111111111111* L009732 000000000000000000000000000000000000000000000000000000000000000000* L009798 000000000000000000000000000000000000000000000000000000000000000000* L009864 000000000000000000000000000000000000000000000000000000000000000000* -L009930 111111111111111111111111111111011111111111111111111111111111111111* -L009996 111111111111111111111111111111111011111111110110011111111111111011* -L010062 111111111111111111111111111111111011111111111010011111111111110111* +L009930 111111111111111111111111111111111111111111111111011111111111111111* +L009996 000000000000000000000000000000000000000000000000000000000000000000* +L010062 000000000000000000000000000000000000000000000000000000000000000000* L010128 000000000000000000000000000000000000000000000000000000000000000000* L010194 000000000000000000000000000000000000000000000000000000000000000000* L010260 - 000000000000000000000000000000000000000000000000000000000000000000* -L010326 101101111011111011111111111011111111111111011111011111111111111111* -L010392 101110111011111011111111111011111111111111101111011111111111111111* -L010458 101110110111110111111111111011111111111111101111011111111111111111* -L010524 101101110111110111111111111011111111111111011111011111111111111111* -L010590 101111111111111110111111111111111111111111111111011111111111111111* -L010656 111111011111111111111111111111111111111111111111111111111111111111* -L010722 111111111111111110111111111011111111111111111111011111111111111111* -L010788 111101111111111110111111111111111111111111101111011111111111111111* -L010854 111110111111111110111111111111111111111111011111011111111111111111* -L010920 111111111011110110111111111111111111111111111111011111111111111111* + 111111111111111111111111111111101111111111111111110111111111101111* +L010326 101110111011111110111111111111111111110111011111111111111111110111* +L010392 101110111011111110111111111111111111111011011111111111111111111011* +L010458 101110110111111101111111111111111111111011011111111111111111111011* +L010524 101110110111111101111111111111111111110111011111111111111111110111* +L010590 101111111111111111111111111111111110111111011111111111111111111111* +L010656 111110111111111111111111111111111110111111011111111111111111111111* +L010722 111111111111111111111111111111111110110111011111111111111111111011* +L010788 111111111111111111111111111111111110111011011111111111111111110111* +L010854 111111111011111101111111111111111110111111011111111111111111111111* +L010920 111111110111111110111111111111111110111111011111111111111111111111* L010986 - 000000000000000000000000000000000000000000000000000000000000000000* -L011052 111111111111111111111111111111111111111111111111111111111101111111* -L011118 111111110111111010111111111111111111111111111111011111111111111111* -L011184 000000000000000000000000000000000000000000000000000000000000000000* -L011250 000000000000000000000000000000000000000000000000000000000000000000* -L011316 000000000000000000000000000000000000000000000000000000000000000000* -L011382 111111111011111111111111111111111111111111111111011111111111111111* -L011448 000000000000000000000000000000000000000000000000000000000000000000* -L011514 000000000000000000000000000000000000000000000000000000000000000000* -L011580 000000000000000000000000000000000000000000000000000000000000000000* -L011646 000000000000000000000000000000000000000000000000000000000000000000* + 111111111111111111111111111111101111111111111111110111111111101111* +L011052 011101111011111110111111111111111111111011011111111111111111111011* +L011118 101110111011111110111111111111111111111011011111111111111111111011* +L011184 011101110111111101111111111111111111111011011111111111111111111011* +L011250 101110110111111101111111111111111111111011011111111111111111111011* +L011316 111111111111101111111111111111111111111111011111111111111111111011* +L011382 101101111111101111111111111111111111111111011111111111111111111111* +L011448 011110111111101111111111111111111111111111011111111111111111111111* +L011514 111111111111101111111111111111111111111011011111111111111111111111* +L011580 111111111011101101111111111111111111111111011111111111111111111111* +L011646 111111110111101110111111111111111111111111011111111111111111111111* L011712 - 000000000000000000000000000000000000000000000000000000000000000000* -L011778 011110111011111011111111110111111111111111101111011111111111111111* -L011844 101110111011111011111111111011111111111111101111011111111111111111* -L011910 011110110111110111111111110111111111111111101111011111111111111111* -L011976 101110110111110111111111111011111111111111101111011111111111111111* -L012042 111011111111111111111111111111111111111111101111011111111111111111* -L012108 101011111111111111111111110111111111111111111111011111111111111111* -L012174 011011111111111111111111111011111111111111111111011111111111111111* -L012240 111010111111111111111111111111111111111111111111011111111111111111* -L012306 111011111011110111111111111111111111111111111111011111111111111111* -L012372 111011110111111011111111111111111111111111111111011111111111111111* + 111111111111111111111111111111101111111111111111110111111111101111* +L011778 000000000000000000000000000000000000000000000000000000000000000000* +L011844 111111111111111111111111111111111111111111011101111111111111101111* +L011910 111111111111110111111111101111111111111111011111111111111111011111* +L011976 000000000000000000000000000000000000000000000000000000000000000000* +L012042 000000000000000000000000000000000000000000000000000000000000000000* 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-L012900 111111111111111111111110111111111111111111111110011111111111111111* -L012966 111111111111111111111111111111111111110111111101011111111011111111* +L012834 111111111011111111111111111111111111111111011111111111111111111111* +L012900 000000000000000000000000000000000000000000000000000000000000000000* +L012966 000000000000000000000000000000000000000000000000000000000000000000* L013032 000000000000000000000000000000000000000000000000000000000000000000* L013098 000000000000000000000000000000000000000000000000000000000000000000* L013164 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L013296 0010* -L013300 00100110010000* -L013314 00101011111110* -L013328 11100110010101* -L013342 00100110011111* +L013300 00100011111000* +L013314 00100110011111* +L013328 10100110010101* +L013342 00010110011111* L013356 11100110010010* -L013370 10110110011110* -L013384 00100110010110* -L013398 00000110011111* -L013412 11100110011001* -L013426 00110110010011* -L013440 00000110010000* -L013454 01100110010010* -L013468 11100110011000* -L013482 11110110010011* -L013496 00100110011101* -L013510 01000110011111* +L013370 00110011111110* +L013384 11100110011100* +L013398 00100110011111* +L013412 11100110011011* +L013426 11110110010011* +L013440 11110110010110* +L013454 10000110010011* +L013468 00001011110001* +L013482 00001111110011* +L013496 00100110011110* +L013510 01100110011110* NOTE BLOCK 2 * L013524 - 111111111111111111111111111111011111111111111111111111111111111111 - 111111111111111110111111111111111111101111111111111111111111111111 - 111110111111110111111111111111111110111111111111111111110111111111 - 111111111111111111110111111001111111111110111011111111111110111111 - 110111111110111111111111111111111111111111111111111111111111101111 - 111111111111111111111111011111111111111011111111111111111111111111 - 111111010111011111111111111111111111111111111111111111111111111111 - 101111111111111111111110111111111111111111111111111111111111111111 - 111111111111111111111111111111111011111111101111111011111111111111* + 111111111111111111111111111111111111111111111111111011111111010111 + 111101111111111111111111110111011111111110111111111111111111111111 + 111111111111101111111111111111111111111111111111111110111111111111 + 111111111111111110111111101111111110111111110111111111111111111111 + 111111101110111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111111111111111011111111111111011111111111 + 111111110111110111011101111111111111011111111111111111110111111111 + 111111111111111111111111111111111111111111101111111111111111111111 + 101011111111111111111011111111110111111111111111111111111111111111* L014118 - 000000000000000000000000000000000000000000000000000000000000000000* -L014184 101111111111111111111011111111111111111111111111111111111111111111* + 111111111111110111111111111111101111111111101111111111111111111111* +L014184 000000000000000000000000000000000000000000000000000000000000000000* L014250 000000000000000000000000000000000000000000000000000000000000000000* L014316 000000000000000000000000000000000000000000000000000000000000000000* L014382 000000000000000000000000000000000000000000000000000000000000000000* L014448 000000000000000000000000000000000000000000000000000000000000000000* -L014514 111101111111111111111111111111111111111111011111111111111111111111* -L014580 111011111111111111111110111111111111111111011111110111111111111111* +L014514 111110111111111111111111111111111111111111101111111111111111111111* +L014580 000000000000000000000000000000000000000000000000000000000000000000* L014646 000000000000000000000000000000000000000000000000000000000000000000* L014712 000000000000000000000000000000000000000000000000000000000000000000* L014778 000000000000000000000000000000000000000000000000000000000000000000* L014844 - 000000000000000000000000000000000000000000000000000000000000000000* -L014910 111111111111111111111111111111111111111111111111111111111111111111* -L014976 111111111111111111111111111111111111111111111111111111111111111111* -L015042 111111111111111111111111111111111111111111111111111111111111111111* -L015108 111111111111111111111111111111111111111111111111111111111111111111* -L015174 111111111111111111111111111111111111111111111111111111111111111111* -L015240 111111111111111111111111111111111111111111111111111111111111111111* -L015306 111111111111111111111111111111111111111111111111111111111111111111* -L015372 111111111111111111111111111111111111111111111111111111111111111111* -L015438 111111111111111111111111111111111111111111111111111111111111111111* -L015504 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111110111111111111111101111111111101111111111111111111111* +L014910 011111101111111111111111111111111111111111101111111111111111111111* +L014976 011111111111111111111111111111111111110111011011111111111111111111* +L015042 000000000000000000000000000000000000000000000000000000000000000000* +L015108 000000000000000000000000000000000000000000000000000000000000000000* +L015174 000000000000000000000000000000000000000000000000000000000000000000* +L015240 111111111111111111111111111111111111111111111111111111110111111111* +L015306 000000000000000000000000000000000000000000000000000000000000000000* +L015372 000000000000000000000000000000000000000000000000000000000000000000* +L015438 000000000000000000000000000000000000000000000000000000000000000000* +L015504 000000000000000000000000000000000000000000000000000000000000000000* L015570 - 000000000000000000000000000000000000000000000000000000000000000000* -L015636 111111111111111111111110111110111111111111011111110111111111111111* -L015702 011111011110111111111110111111111111110110011111110111111111111111* -L015768 011111011110111111111110011111111111110111011111110111111111111111* -L015834 011111010110111111111110111111111111110111011111110111111111111111* -L015900 011111011110111111111110111011111111110111011111110111111111111111* -L015966 011111011110011111111110111111111111110111011111110111111111111111* -L016032 011111011110111111111110111111111110110111011111110111111111111111* + 111111111111110111111111111111101111111111101111111111111111111111* +L015636 000000000000000000000000000000000000000000000000000000000000000000* +L015702 000000000000000000000000000000000000000000000000000000000000000000* +L015768 000000000000000000000000000000000000000000000000000000000000000000* +L015834 000000000000000000000000000000000000000000000000000000000000000000* +L015900 000000000000000000000000000000000000000000000000000000000000000000* +L015966 000000000000000000000000000000000000000000000000000000000000000000* +L016032 000000000000000000000000000000000000000000000000000000000000000000* L016098 000000000000000000000000000000000000000000000000000000000000000000* L016164 000000000000000000000000000000000000000000000000000000000000000000* L016230 000000000000000000000000000000000000000000000000000000000000000000* L016296 - 000000000000000000000000000000000000000000000000000000000000000000* -L016362 111111111111111111111111111111111111111111111111111111111111111111* -L016428 111111111111111111111111111111111111111111111111111111111111111111* -L016494 111111111111111111111111111111111111111111111111111111111111111111* -L016560 111111111111111111111111111111111111111111111111111111111111111111* -L016626 111111111111111111111111111111111111111111111111111111111111111111* -L016692 111111111111111111111111111111111111111111111111111111111111111111* -L016758 111111111111111111111111111111111111111111111111111111111111111111* -L016824 111111111111111111111111111111111111111111111111111111111111111111* -L016890 111111111111111111111111111111111111111111111111111111111111111111* -L016956 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111110111111111111111101111111111101111111111111111111111* +L016362 111111111111111111111111111111111111111111111111110111111111111111* +L016428 000000000000000000000000000000000000000000000000000000000000000000* +L016494 000000000000000000000000000000000000000000000000000000000000000000* +L016560 000000000000000000000000000000000000000000000000000000000000000000* +L016626 000000000000000000000000000000000000000000000000000000000000000000* +L016692 111111111111111111111111111111111111111101111111111111111111111111* +L016758 000000000000000000000000000000000000000000000000000000000000000000* +L016824 000000000000000000000000000000000000000000000000000000000000000000* +L016890 000000000000000000000000000000000000000000000000000000000000000000* +L016956 000000000000000000000000000000000000000000000000000000000000000000* L017022 - 000000000000000000000000000000000000000000000000000000000000000000* -L017088 111110111101111111111111111111111111111111010111111111111110101111* -L017154 111110111101111111111111111111111111101111011111111111111110101111* -L017220 111111111111110111111110111111111111111111011111110111111111111111* -L017286 111111111101111101111111111111111111111111010111111111111110101111* -L017352 111111111101111101111111111111111111101111011111111111111110101111* -L017418 111111111111111111111111111111111111111111111111111111111111111111* -L017484 111111111111111111111111111111111111111111111111111111111111111111* -L017550 111111111111111111111111111111111111111111111111111111111111111111* -L017616 111111111111111111111111111111111111111111111111111111111111111111* -L017682 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111110111111111111111101111111111101111111111111111111111* +L017088 000000000000000000000000000000000000000000000000000000000000000000* +L017154 000000000000000000000000000000000000000000000000000000000000000000* +L017220 000000000000000000000000000000000000000000000000000000000000000000* +L017286 000000000000000000000000000000000000000000000000000000000000000000* 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-L018210 111111111111111111111111111111111111111111111111111111111111111111* -L018276 111111111111111111111111111111111111111111111111111111111111111111* -L018342 111111111111111111111111111111111111111111111111111111111111111111* -L018408 111111111111111111111111111111111111111111111111111111111111111111* +L017814 111111111111111111111111111111111111111111111111111111111111110111* +L017880 000000000000000000000000000000000000000000000000000000000000000000* +L017946 000000000000000000000000000000000000000000000000000000000000000000* +L018012 000000000000000000000000000000000000000000000000000000000000000000* +L018078 000000000000000000000000000000000000000000000000000000000000000000* +L018144 111111111111111111111111111111111111111111111111111101111111111111* +L018210 000000000000000000000000000000000000000000000000000000000000000000* +L018276 000000000000000000000000000000000000000000000000000000000000000000* +L018342 000000000000000000000000000000000000000000000000000000000000000000* +L018408 000000000000000000000000000000000000000000000000000000000000000000* L018474 000000000000000000000000000000000000000000000000000000000000000000* -L018540 101111111111111111111111111111011011111111011111111111111011111111* -L018606 101111111111111111111111111111101011111111010111111111110111111111* -L018672 101111111111111111111111111111011011111111011011111111111111111111* +L018540 000000000000000000000000000000000000000000000000000000000000000000* +L018606 000000000000000000000000000000000000000000000000000000000000000000* +L018672 000000000000000000000000000000000000000000000000000000000000000000* L018738 000000000000000000000000000000000000000000000000000000000000000000* L018804 000000000000000000000000000000000000000000000000000000000000000000* -L018870 111111111111111111111111111111111111111111111111111111111111111111* -L018936 111111111111111111111111111111111111111111111111111111111111111111* -L019002 111111111111111111111111111111111111111111111111111111111111111111* -L019068 111111111111111111111111111111111111111111111111111111111111111111* -L019134 111111111111111111111111111111111111111111111111111111111111111111* +L018870 010111111111111111111011111111111111111111111111111111111111101111* +L018936 010111111110111111111011101111011111110111011111111111111111111111* +L019002 010111111110111111111011111111011111110111011111111111011111111111* +L019068 010111110110111111111011111111011111110111011111111111111111111111* +L019134 010111111110111110111011111111011111110111011111111111111111111111* L019200 000000000000000000000000000000000000000000000000000000000000000000* -L019266 111111111111111111111111111111111111111111111111111111111111111111* -L019332 111111111111111111111111111111111111111111111111111111111111111111* -L019398 111111111111111111111111111111111111111111111111111111111111111111* -L019464 111111111111111111111111111111111111111111111111111111111111111111* -L019530 111111111111111111111111111111111111111111111111111111111111111111* -L019596 111111111111111111111111111111111111111111111111111111111111111111* -L019662 111111111111111111111111111111111111111111111111111111111111111111* -L019728 111111111111111111111111111111111111111111111111111111111111111111* -L019794 111111111111111111111111111111111111111111111111111111111111111111* -L019860 111111111111111111111111111111111111111111111111111111111111111111* +L019266 111111111111111111111111111111111101111111111111111111111111111111* +L019332 010111111110111111111001111111011111110111011111111111111111111111* +L019398 010111111110101111111011111111011111110111011111111111111111111111* +L019464 000000000000000000000000000000000000000000000000000000000000000000* +L019530 000000000000000000000000000000000000000000000000000000000000000000* +L019596 011111111111111111101111111111111111111111111111111111111111111111* +L019662 000000000000000000000000000000000000000000000000000000000000000000* +L019728 000000000000000000000000000000000000000000000000000000000000000000* +L019794 000000000000000000000000000000000000000000000000000000000000000000* +L019860 000000000000000000000000000000000000000000000000000000000000000000* L019926 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L020058 0010* -L020062 01100011111000* -L020076 11100110010011* -L020090 11010011110001* -L020104 11111111110011* -L020118 11100110010000* -L020132 11111111110011* -L020146 11111011110000* -L020160 11110011110010* -L020174 10100110010000* -L020188 11000111110011* -L020202 11111111110110* -L020216 11110011111110* -L020230 10100110010001* -L020244 11001011110011* -L020258 11110111110000* -L020272 11111111111111* +L020062 00100011110000* +L020076 01101111110011* +L020090 11100110010100* +L020104 00100110010010* +L020118 00100011111000* +L020132 00101111110011* +L020146 00100110010111* +L020160 00100110010011* +L020174 00100011110000* +L020188 10100110010011* +L020202 00100110011110* +L020216 00100110011110* +L020230 00101011111000* +L020244 11100110011011* +L020258 00110110010001* +L020272 01100110011111* NOTE BLOCK 3 * L020286 - 111011111111111111110111111111111111111111111111111111111111111111 - 111111110111011111111111111111111111111111111111111111111111111111 - 111111111111110111111101111111111111111111111111111111111111111011 - 111111111111111111111111111111101111111111111010111111111111111111 - 111111111110111111111111111111111101111111111111111111111111111111 + 111111011111111111111111111111111111111111111101111011111111111011 + 111011111111111101111111111111111111111111011111111111111011111111 + 111111111111111111111101111111111111011111111111111111101111111101 + 111111111111111111110111111110111011111111110111111111111111111111 + 111111111110111111111111111111101111111111111111011111111111111111 111111111111111111111111111111111111111101111111111111111101111111 - 111111111111111101111111011111111111110111111111111111111111011111 - 101111111111111111011111111111110111101111111111111111110111111111 - 111101011111111111111111111111111111111111101111111101111111111111* + 111111111111111111111111011111111111111111111111111111111111011111 + 111101110111111011111111111111111111111111111111111111111111111111 + 101111111111111111011111111111111101111011111111111101111111111111* L020880 111111111111111111111111111111111111111111111111111111111111111111* -L020946 111111111111111111111111111111111111111111101111111110111111111111* -L021012 111011101111111111111111111111111011111111110111111110111110111111* -L021078 111011011111111111111111111111100111111111011101111101111110111111* +L020946 101111111111111111111111111111111111111111111111111110111111111111* +L021012 111111111111111111111011111110101111111111111111111110111111011011* +L021078 011110111111111111110111111110101111111111111111111101111101110111* L021144 000000000000000000000000000000000000000000000000000000000000000000* L021210 000000000000000000000000000000000000000000000000000000000000000000* -L021276 111111111011011111111111111111111111011111011111111111111111011111* -L021342 111110111011111111111111111111111111111111011111111111111111111111* +L021276 011111111111111111111111111111111111110111011110110111111111111111* +L021342 011111111111111111111111111111111110111111111110111111111111111111* L021408 000000000000000000000000000000000000000000000000000000000000000000* L021474 000000000000000000000000000000000000000000000000000000000000000000* L021540 000000000000000000000000000000000000000000000000000000000000000000* L021606 111111111111111111111111111111111111111111111111111111111111111111* -L021672 111111011111111111111111111111111011111111111111111111111111111111* -L021738 111011101111111111111111111111110111111101111111111111111111111111* -L021804 111111011111111111111111111111111111111110111111111111111111111111* +L021672 111111111111111111111111111111111111011111111111111011111111111111* +L021738 000000000000000000000000000000000000000000000000000000000000000000* +L021804 000000000000000000000000000000000000000000000000000000000000000000* L021870 000000000000000000000000000000000000000000000000000000000000000000* L021936 000000000000000000000000000000000000000000000000000000000000000000* -L022002 111111111111111111011111111111111111111111011110111111111111111111* -L022068 111111111111111111101111111111111111111111011101111111111111111111* -L022134 111111111111111101011111111111111101111111011111111111111111111111* +L022002 111111111111111111111111111111111111111111111111111111110111111111* +L022068 000000000000000000000000000000000000000000000000000000000000000000* +L022134 000000000000000000000000000000000000000000000000000000000000000000* L022200 000000000000000000000000000000000000000000000000000000000000000000* L022266 000000000000000000000000000000000000000000000000000000000000000000* L022332 111111111111111111111111111111111111111111111111111111111111111111* -L022398 101111111111111111110111111111111111111111111111111111111111111111* -L022464 011111111110111111111111111111111111111111111111111111111111111111* -L022530 000000000000000000000000000000000000000000000000000000000000000000* +L022398 111111011111110111111111111111111111111111111111111111011111111111* +L022464 111111111111111011111111111111111111111111110111111111111111111111* +L022530 111111111110110111111111111111111111111111111111111111111111111111* L022596 000000000000000000000000000000000000000000000000000000000000000000* L022662 000000000000000000000000000000000000000000000000000000000000000000* L022728 000000000000000000000000000000000000000000000000000000000000000000* @@ -503,61 +510,61 @@ L022860 000000000000000000000000000000000000000000000000000000000000000000* L022926 000000000000000000000000000000000000000000000000000000000000000000* L022992 000000000000000000000000000000000000000000000000000000000000000000* L023058 - 011111111111111111111111011111111111111111111111111111111111111111* -L023124 111111111111111111111111111111111011111101111111111111111111111111* -L023190 111111111111111111111111111111110111111110111111111111111111111111* -L023256 000000000000000000000000000000000000000000000000000000000000000000* -L023322 000000000000000000000000000000000000000000000000000000000000000000* + 111111111111110111111111011111111111111111111111111111111111111111* +L023124 011111110111111111111111111111111111111111111111111111111110111111* +L023190 011111110111111111111111111111111111111110111111111111111111111111* +L023256 011111111011111111111111111111111111111101111111111111111101111111* +L023322 011111110111111111111111111111111111111111111111011111111111111111* L023388 000000000000000000000000000000000000000000000000000000000000000000* -L023454 111111111111111111011111111111111101111111011101111111111111111111* -L023520 111111111111111101111111111111111111111111011111111111111111111111* +L023454 111111111111111111111111111111111111101111111111110111111111111111* +L023520 000000000000000000000000000000000000000000000000000000000000000000* L023586 000000000000000000000000000000000000000000000000000000000000000000* L023652 000000000000000000000000000000000000000000000000000000000000000000* L023718 000000000000000000000000000000000000000000000000000000000000000000* L023784 - 011111111111111111111111011111111111111111111111111111111111111111* -L023850 111111111111110111111111111111111111111011111111111111111111111111* + 111111111111110111111111011111111111111111111111111111111111111111* +L023850 110111111111111111111110111111111111111111111111111111111111111111* L023916 000000000000000000000000000000000000000000000000000000000000000000* L023982 000000000000000000000000000000000000000000000000000000000000000000* L024048 000000000000000000000000000000000000000000000000000000000000000000* L024114 000000000000000000000000000000000000000000000000000000000000000000* -L024180 111111111111111111111111011111111111111111011111111111111111111111* -L024246 111111111111111101011111111111111101111111011101111111111111111111* +L024180 011111111111111111111111011111111111111111111111111111111111111111* +L024246 011111110111111111111111111111111111111101111111011111111101111111* L024312 000000000000000000000000000000000000000000000000000000000000000000* L024378 000000000000000000000000000000000000000000000000000000000000000000* L024444 000000000000000000000000000000000000000000000000000000000000000000* L024510 000000000000000000000000000000000000000000000000000000000000000000* -L024576 111111111111111111111111111111111111111111111101111111111111111111* -L024642 000000000000000000000000000000000000000000000000000000000000000000* -L024708 000000000000000000000000000000000000000000000000000000000000000000* +L024576 011111111111111111111111111111111111111101111111111111111110111111* +L024642 011111111111111111111111111111111111111110111111111111111101111111* +L024708 011111110111111111111111111111111111111101111111011111111111111111* L024774 000000000000000000000000000000000000000000000000000000000000000000* L024840 000000000000000000000000000000000000000000000000000000000000000000* -L024906 111111111111111111111101111111111111111111111111111111111111111111* +L024906 111111111111111111111111111111111111111111111111111111111111111101* L024972 000000000000000000000000000000000000000000000000000000000000000000* L025038 000000000000000000000000000000000000000000000000000000000000000000* L025104 000000000000000000000000000000000000000000000000000000000000000000* L025170 000000000000000000000000000000000000000000000000000000000000000000* L025236 111111111111111111111111111111111111111111111111111111111111111111* -L025302 111111111111110111111111111111111111111111111111111111111011111111* +L025302 110111111111111111101111111111111111111111111111111111111111111111* L025368 000000000000000000000000000000000000000000000000000000000000000000* L025434 000000000000000000000000000000000000000000000000000000000000000000* L025500 000000000000000000000000000000000000000000000000000000000000000000* L025566 000000000000000000000000000000000000000000000000000000000000000000* -L025632 111111111111111111111111111111111011111111111111111111111101111111* -L025698 111111101111111111111111111111111111111111111111111111111101111111* -L025764 111111011111111111111111111111110111111101111111111111111110111111* -L025830 111111111111111111111111111111111111111110111111111111111101111111* +L025632 111111111111111101111111111111111111111111111111111111111111111111* +L025698 000000000000000000000000000000000000000000000000000000000000000000* +L025764 000000000000000000000000000000000000000000000000000000000000000000* +L025830 000000000000000000000000000000000000000000000000000000000000000000* L025896 000000000000000000000000000000000000000000000000000000000000000000* L025962 000000000000000000000000000000000000000000000000000000000000000000* -L026028 111111111111111111111111111111111101111111011110111111111111111111* -L026094 111111111111111111101111111111111101111111011111111111111111111111* -L026160 111111111111111111011111111111111110111111011101111111111111111111* -L026226 111111111111111101111111111111111101111111011111111111111111111111* +L026028 011111110111111111111111111111111111111101111111111111111101111111* +L026094 011111111111111111111111111111111111111111111111011111111111111111* +L026160 000000000000000000000000000000000000000000000000000000000000000000* +L026226 000000000000000000000000000000000000000000000000000000000000000000* L026292 000000000000000000000000000000000000000000000000000000000000000000* -L026358 111111111111111111111111111111111111111111011111111111111111111011* +L026358 011111111111111111111111111111111011111111111111111111111111111111* L026424 000000000000000000000000000000000000000000000000000000000000000000* L026490 000000000000000000000000000000000000000000000000000000000000000000* L026556 000000000000000000000000000000000000000000000000000000000000000000* @@ -568,46 +575,46 @@ L026688 L026820 0010* L026824 10100111010000* L026838 11100110011110* -L026852 10100110010100* -L026866 10100110011111* +L026852 00100110010100* +L026866 00100110011111* L026880 10101011111001* L026894 00100011111111* L026908 10100110010100* -L026922 10100110010010* +L026922 00100110010010* L026936 01101011110011* L026950 10100110010011* -L026964 00100110010000* +L026964 10100110010000* L026978 00100110010011* L026992 01101111111011* -L027006 10100110011111* +L027006 00100110011111* L027020 10100110010000* L027034 01100110010010* NOTE BLOCK 4 * L027048 111111111111111111111111111111111111111111111111111111111111111111 - 110111111111011111111111111111111111110111111111111111111111111111 - 111111011101111110111111110111111111111111111111101111111111111111 - 111111111111111111111111111111111101111110011111111111101111111111 - 111111111111110111111111111111111111111111110111111111111111111111 - 111111110111111111111111011111111111111111111111111111111111111111 - 111111111111111111111111111111111011111111111111110101111011010111 - 101111111111111111111011111110011111111111111111111111111101111110 - 111110111111111111101101111111111111101111111111111111111111111111* + 011111111111111111111111111111011111111111111111110111110111111111 + 111111110101111111111111111111111111111111110111101111111111111111 + 111011111111111111011101111011111111111111111110111111111111111111 + 111111111111111111111111111101111111111111111111111111111111111111 + 111111111111011111111111101111111111111111111111111111111101111101 + 111111111111110111111111111111111101111111101111111101111111111111 + 111111011111111111111111111111111111111011111111111111111111100111 + 111110111111111101111011111111110111101110111111111111101111111111* L027642 - 111111110111111111111101101111111111111101111111011110011111111010* + 110111111111101101111111110111111110111011111111011110111111111101* L027708 000000000000000000000000000000000000000000000000000000000000000000* L027774 000000000000000000000000000000000000000000000000000000000000000000* L027840 000000000000000000000000000000000000000000000000000000000000000000* L027906 000000000000000000000000000000000000000000000000000000000000000000* L027972 000000000000000000000000000000000000000000000000000000000000000000* -L028038 101110111111111111111111111111111111111111111111111111110111101111* -L028104 011111111111111111111111111111111111111111111111111111111011111111* +L028038 111110111111111111111111111111101111111111011111111111111111101111* +L028104 111111111111111111111111111111111111111111101111111111111111011111* L028170 000000000000000000000000000000000000000000000000000000000000000000* L028236 000000000000000000000000000000000000000000000000000000000000000000* L028302 000000000000000000000000000000000000000000000000000000000000000000* L028368 - 011111111111111111111111111111111111111111111111110111111111111111* -L028434 111111111111011111111111111111111011111111111111111111111111111111* + 111111111111110111111111111111111111111111111111111111111111011111* +L028434 111111111111111111111111111111111111111111111111111111101111111111* L028500 111111111111111111111111111111111111111111111111111111111111111111* L028566 111111111111111111111111111111111111111111111111111111111111111111* L028632 111111111111111111111111111111111111111111111111111111111111111111* @@ -619,16 +626,16 @@ L028962 111111111111111111111111111111111111111111111111111111111111111111* L029028 111111111111111111111111111111111111111111111111111111111111111111* L029094 000000000000000000000000000000000000000000000000000000000000000000* -L029160 111111111111111111111111111111111111111111111011111111111111111110* +L029160 111111111111111111111111111111111111111011111110111111111111111111* L029226 111111111111111111111111111111111111111111111111111111111111111111* L029292 111111111111111111111111111111111111111111111111111111111111111111* L029358 111111111111111111111111111111111111111111111111111111111111111111* L029424 111111111111111111111111111111111111111111111111111111111111111111* -L029490 111011101110111011011011111011011110011011101111111111111101111111* -L029556 111111111111111111111111111111111111111111111111111111111111011111* -L029622 000000000000000000000000000000000000000000000000000000000000000000* -L029688 000000000000000000000000000000000000000000000000000000000000000000* -L029754 000000000000000000000000000000000000000000000000000000000000000000* +L029490 111111111111111111111111111111111111111111111111111111111101111111* +L029556 111111111111111111111111111111111111111111111111111111111111111111* +L029622 111111111111111111111111111111111111111111111111111111111111111111* +L029688 111111111111111111111111111111111111111111111111111111111111111111* +L029754 111111111111111111111111111111111111111111111111111111111111111111* L029820 000000000000000000000000000000000000000000000000000000000000000000* L029886 111111111111111111111111111111111111111111111111111111111111111111* @@ -643,36 +650,36 @@ L030414 111111111111111111111111111111111111111111111111111111111111111111* L030480 111111111111111111111111111111111111111111111111111111111111111111* L030546 000000000000000000000000000000000000000000000000000000000000000000* -L030612 111111111111011111111111111111111111111111111111111111111111111111* +L030612 111111111111111111111111111111111111111111111111111111011111111111* L030678 111111111111111111111111111111111111111111111111111111111111111111* L030744 111111111111111111111111111111111111111111111111111111111111111111* L030810 111111111111111111111111111111111111111111111111111111111111111111* L030876 111111111111111111111111111111111111111111111111111111111111111111* -L030942 111111111111101111111111111111110111111111111111111111111111111111* +L030942 111111111111111111111111111111110111111111111111111111111111111111* L031008 111111111111111111111111111111111111111111111111111111111111111111* L031074 111111111111111111111111111111111111111111111111111111111111111111* L031140 111111111111111111111111111111111111111111111111111111111111111111* L031206 111111111111111111111111111111111111111111111111111111111111111111* L031272 000000000000000000000000000000000000000000000000000000000000000000* -L031338 111111111111111111111111111111111111111111111111111111111111111111* -L031404 111111111111111111111111111111111111111111111111111111111111111111* -L031470 111111111111111111111111111111111111111111111111111111111111111111* -L031536 111111111111111111111111111111111111111111111111111111111111111111* -L031602 111111111111111111111111111111111111111111111111111111111111111111* +L031338 111111011010111111101010111110111111011101111011111011111011110111* +L031404 111111111111111111111111111111011111111111111111111111111111111111* +L031470 000000000000000000000000000000000000000000000000000000000000000000* +L031536 000000000000000000000000000000000000000000000000000000000000000000* +L031602 000000000000000000000000000000000000000000000000000000000000000000* L031668 111111111111111111111111111111111111111111111111111111111111111111* L031734 111111111111111111111111111111111111111111111111111111111111111111* L031800 111111111111111111111111111111111111111111111111111111111111111111* L031866 111111111111111111111111111111111111111111111111111111111111111111* L031932 111111111111111111111111111111111111111111111111111111111111111111* L031998 - 111111111111111111111111111101111111111111111111111111111111111111* -L032064 111011101110111011011011111011011110011011101111111111111101111111* + 111111111111111111111111011111111111111111111111111111111111111111* +L032064 111111011010111111101010111110111111011101111011111011111011110111* L032130 111111111111111111111111111111111111111111111111111111111111111111* L032196 111111111111111111111111111111111111111111111111111111111111111111* L032262 111111111111111111111111111111111111111111111111111111111111111111* L032328 111111111111111111111111111111111111111111111111111111111111111111* -L032394 111111111111111101111111111111111111111111111111111111111111111111* +L032394 011111111111111111111111111111111111111111111111111111111111111111* L032460 111111111111111111111111111111111111111111111111111111111111111111* L032526 111111111111111111111111111111111111111111111111111111111111111111* L032592 111111111111111111111111111111111111111111111111111111111111111111* @@ -698,247 +705,247 @@ L033600 10101111110011* L033614 00010110010100* L033628 11101111110010* L033642 01111011111000* -L033656 10100011111111* -L033670 11011111110000* -L033684 11111011111110* +L033656 00000110011111* +L033670 11011011110000* +L033684 11110011111110* L033698 00110110010001* L033712 00000110011111* -L033726 11011111110000* -L033740 11110011111111* -L033754 00111011110000* -L033768 00000110011110* -L033782 11010111111101* -L033796 11111111111110* +L033726 10101111110000* +L033740 11100011111110* +L033754 00111011110001* +L033768 00000110011111* +L033782 11010111111100* +L033796 11111111111111* NOTE BLOCK 5 * L033810 - 111111111111101111111111111111111110110111111111101111111111111111 - 111110111111111111111111111111111111101111111111111111111111110111 - 111111111110111111111110111110111111111111111111111111111111111110 - 111111111011111111101011111111111111111111111011111111111101111111 - 111111111111111111111111111111101111111111111111111011111111111111 - 111111111111111111111111111111111111111101011111111111111111111111 - 111111011111111110111111111111111111111111111111111111111111111111 - 111111111111111111111111111111111111111111111111111111111111011111 - 101011111111111111111111110111110111111111111111111101111111111111* + 011111111111101111111111111111111110111101110111101111111111111111 + 111111111111111110111111111111011111111011111101111111111111111110 + 111110111111111111111110111111111111111111111111111111101111111011 + 111111111111111111101011111111111111011111111111111111111111111111 + 111111111110111111111111110111111111111111111111111111111111101111 + 111111111111111111111111111111111111111111111111111111111101111111 + 111111011111111111111111111111111111111111111111111111111111111111 + 111111111111111111111111111110111111111111111111110111110111111111 + 111011111111111111111111101111110111111111101111111101111111111111* L034404 000000000000000000000000000000000000000000000000000000000000000000* -L034470 011111110111111111101111111111101001111101100111011110111111101111* -L034536 011111110111111111011111111111101111111001110111011111111111111111* -L034602 011111111111111111101111111110101001111101100111011110111111101110* -L034668 011111111111111111011111111110101111111001110111011111111111111110* -L034734 011111110111111111111110111111101111111111110111011111111111111111* -L034800 011111111111111111111110111110101111111111110111011111111111111110* -L034866 011110110111111111101011111111101001101101101111011110111111101111* -L034932 011110110111111111011011111111101111101001111111011111111111111111* -L034998 011110111111111111101011111110101001101101101111011110111111101110* -L035064 011110111111111111011011111110101111101001111111011111111111111110* +L034470 111111011111111111111011111101111110101111011111101110101001011111* +L034536 111111011111111111111111111101111111111111011011101111100101111111* +L034602 111110011111101111111011111101111110101111011111101110101011011111* +L034668 111110011111101111111111111101111111111111011011101111100111111111* +L034734 111111011111111111101111111111111111111111011111101111101101111111* +L034800 111110011111101111101111111111111111111111011111101111101111111111* +L034866 111111111111111111111010111101111110101011011110101110101001011111* +L034932 111111111111111111111110111101111111111011011010101111100101111111* +L034998 111110111111101111111010111101111110101011011110101110101011011111* +L035064 111110111111101111111110111101111111111011011010101111100111111111* L035130 000000000000000000000000000000000000000000000000000000000000000000* -L035196 011111111111111111111111111011111111111111111111111111111111111111* -L035262 011110110111111111111010111111101111101111111111011111111111111111* -L035328 011110111111111111111010111110101111101111111111011111111111111110* -L035394 010111111111111111111111111111111111111111111011011111111111111111* -L035460 010111111111111111111111111111101111111111111111011111111111111111* -L035526 111111111101111111111111111111111111111111111111111111111111111111* -L035592 011111110111111111111111111101101111111111111111111111111111111111* -L035658 010111111111111111111111111111011111111111111011111111111111111111* -L035724 000000000000000000000000000000000000000000000000000000000000000000* +L035196 111111111111111111101110111111111111111011011110101111101101111111* +L035262 111110111111101111101110111111111111111011011110101111101111111111* +L035328 110111101111111111111111111111111111111111011111101111111111111111* +L035394 110111111111111111111111111111111111111111011111101111101111111111* +L035460 000000000000000000000000000000000000000000000000000000000000000000* +L035526 111111111111111111111111111111111111111101111111111111111111111111* +L035592 111111111111111111111011111111111111101111111111111111111111011111* +L035658 111111111111111111110111111101111101011111111111111111111111111111* +L035724 111111111111111111111111111110111111111111111111111111111111011111* L035790 000000000000000000000000000000000000000000000000000000000000000000* L035856 000000000000000000000000000000000000000000000000000000000000000000* -L035922 011111011111111101111111111111111111111111111111111011111110111011* -L035988 011111111111111111110111111111111111111111111111111011111111111111* -L036054 010111111111111111110111111111111111111111111011111111111111111111* -L036120 000000000000000000000000000000000000000000000000000000000000000000* -L036186 000000000000000000000000000000000000000000000000000000000000000000* -L036252 011101111111111111111111111110111111111111110111111111111111111111* -L036318 010111111011111111111111111101111111111111111111111111111111111111* -L036384 010101111111111111111111111101111111111111111111111111111111111111* -L036450 000000000000000000000000000000000000000000000000000000000000000000* +L035922 111111111111111111011111111111111111111111101111111111111111111111* +L035988 111111111111111111011011111101111110101011111111111110111011011111* +L036054 111111111111111111011111111101111111111011111011111111110111111111* +L036120 111111011111111111101111111111111111110111011111111111111111111111* +L036186 111011111111111111011111111111111111111111111111111111111111111111* +L036252 111111111111111111110111111111111111101111111111111111111111111111* +L036318 111111111111111111110111111111111110111111111111111111111111111111* +L036384 111111111111111111111011111101111101011111111111111111111111111111* +L036450 111111111111111111110111111110111111111111111111111111111111111111* L036516 000000000000000000000000000000000000000000000000000000000000000000* L036582 000000000000000000000000000000000000000000000000000000000000000000* -L036648 101111111111111111111101111111111111111111111111111111111111111111* -L036714 111111111111111111101101111111111001101101101111111110111111101111* -L036780 111111111111111111011101111111111111101001111111111111111111111111* -L036846 011111111111111111111110111111111111011111110111111111111111111111* -L036912 111011111111111111111101111111111111111111111111111111111111111111* -L036978 111111111111111111111111111111111111111111111111111111111111111111* -L037044 111111111111111111111111111111111111111111111111111111111111111111* -L037110 111111111111111111111111111111111111111111111111111111111111111111* -L037176 111111111111111111111111111111111111111111111111111111111111111111* -L037242 111111111111111111111111111111111111111111111111111111111111111111* +L036648 111111111111111111011011111101111110101111011111111110111011011111* +L036714 111111111111111111011111111101111111111111011011111111110111111111* +L036780 111111111111111111011101111111111111111111011111111111111111111111* +L036846 110111101111111111111101111111111111111111011111111111111111111111* +L036912 000000000000000000000000000000000000000000000000000000000000000000* +L036978 111111111111111111111111111111111111111111111111110111111111111111* +L037044 111111111111011111111111111111111111111111011111111111101101111111* +L037110 110111101111111111111111111111111111111111011111111111011111111111* +L037176 000000000000000000000000000000000000000000000000000000000000000000* +L037242 000000000000000000000000000000000000000000000000000000000000000000* L037308 000000000000000000000000000000000000000000000000000000000000000000* -L037374 011111111111111111110111111111111111111111110111111111111111111110* -L037440 010111111011111111111111111111111111111111111111111111111111111101* -L037506 010111111111111111110111111111111111111111111111111111111111111101* +L037374 111110011111111111111111111111111111111111011101111111111111111111* +L037440 110101111111111111111111111111111111111111011111111111111110111111* +L037506 110101111111111111111111111111111111111111011101111111111111111111* L037572 000000000000000000000000000000000000000000000000000000000000000000* L037638 000000000000000000000000000000000000000000000000000000000000000000* -L037704 011111110111111111111111111111111111111111111111111111111111111101* -L037770 011111111111111111111111111111111111011111111111111111111111111101* -L037836 010111111111111111111111111111111111011111111011111111111111111111* -L037902 000000000000000000000000000000000000000000000000000000000000000000* -L037968 000000000000000000000000000000000000000000000000000000000000000000* +L037704 111110011101111111111111111111111111111111011110111111101111111111* +L037770 111110111101111111111111111111111111111011011110111111101111111111* +L037836 110111111111111111111111101111111111111111011111111111111111111101* +L037902 111111011101111101111111111111111111111111011110111111101111111111* +L037968 111111111101111101111111111111111111111011011110111111101111111111* L038034 000000000000000000000000000000000000000000000000000000000000000000* -L038100 011111111111111111101101111111111001111101101111111110111111101111* -L038166 011111111111111111011101111111111111111001111111111111111111111111* -L038232 011101111111111111111101111111111111111111111111111111111111111111* -L038298 010101111111111111111111111111111111111111111011111111111111111111* +L038100 111101111111111111111111111111111111110111011111111111111111111111* +L038166 111101111111111111111111111111111111111111011111111111111101111111* +L038232 110111101111111111111111111111111111110111011111111111111111111111* +L038298 000000000000000000000000000000000000000000000000000000000000000000* L038364 000000000000000000000000000000000000000000000000000000000000000000* -L038430 111111111111111111111111111111111111111111111111111111111111111111* -L038496 111111111111111111111111111111111111111111111111111111111111111111* -L038562 111111111111111111111111111111111111111111111111111111111111111111* -L038628 111111111111111111111111111111111111111111111111111111111111111111* -L038694 111111111111111111111111111111111111111111111111111111111111111111* +L038430 111111111111111111111111110111111111111111111111111111111111111111* +L038496 000000000000000000000000000000000000000000000000000000000000000000* +L038562 000000000000000000000000000000000000000000000000000000000000000000* +L038628 000000000000000000000000000000000000000000000000000000000000000000* +L038694 000000000000000000000000000000000000000000000000000000000000000000* L038760 000000000000000000000000000000000000000000000000000000000000000000* -L038826 111111111111111111111111111111111101111111101111111111111111101111* -L038892 111111111111111111111111111111110111111101011111111111111111011111* -L038958 111111111111111111111111111111111101111110111111111111111111111111* +L038826 111111111111111111111111111111111101101111111111111111111111111111* +L038892 111111111111111111111111111101111110011111111111111111111111101111* +L038958 111111111111111111111111111110111101111111111111111111111111111111* L039024 000000000000000000000000000000000000000000000000000000000000000000* L039090 000000000000000000000000000000000000000000000000000000000000000000* -L039156 111111111111101111111111111111111111111111111111111111111111111111* -L039222 111111111111111111111111111111111111111111111111111111111111111111* -L039288 111111111111111111111111111111111111111111111111111111111111111111* -L039354 111111111111111111111111111111111111111111111111111111111111111111* -L039420 111111111111111111111111111111111111111111111111111111111111111111* +L039156 111111011111101111111101111111111111111111011111111111111111111111* +L039222 110111111111011111111111111111111111111111011111111111111110111111* +L039288 110111111111011111111101111111111111111111011111111111111111111111* +L039354 000000000000000000000000000000000000000000000000000000000000000000* +L039420 000000000000000000000000000000000000000000000000000000000000000000* L039486 000000000000000000000000000000000000000000000000000000000000000000* -L039552 111110101111111111111010111110101111101111111111111111111111111110* -L039618 111110111111111111111010111110101111101111111111111111111101111110* -L039684 111110111111111110111010111110101111101111111111111111111111111110* -L039750 111110111111111111111010111110101111101111111111111111111111110110* +L039552 111110111111101111101110111111101111111011111110111111101111111111* +L039618 011110111111101111101110111111111111111011111110111111101111111111* +L039684 111110111111101111101110111111111011111011111110111111101111111111* +L039750 000000000000000000000000000000000000000000000000000000000000000000* L039816 000000000000000000000000000000000000000000000000000000000000000000* -L039882 111111111111111111111111111111111111111111111111111111111111111111* -L039948 111111111111111111111111111111111111111111111111111111111111111111* -L040014 111111111111111111111111111111111111111111111111111111111111111111* -L040080 111111111111111111111111111111111111111111111111111111111111111111* -L040146 111111111111111111111111111111111111111111111111111111111111111111* +L039882 111111111111111111111111111111111111111111011111111111111111111011* +L039948 000000000000000000000000000000000000000000000000000000000000000000* +L040014 000000000000000000000000000000000000000000000000000000000000000000* +L040080 000000000000000000000000000000000000000000000000000000000000000000* +L040146 000000000000000000000000000000000000000000000000000000000000000000* L040212 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L040344 0010* L040348 10100110011110* L040362 10110110010010* -L040376 01000110011110* +L040376 10000111011110* L040390 00000110010011* -L040404 10100110011111* -L040418 10100110010011* -L040432 10100111011110* -L040446 11101011110010* +L040404 10000110011111* +L040418 10110110010011* +L040432 10100110011110* +L040446 00000110010010* L040460 10100110011110* L040474 10100110010011* L040488 10100110011111* -L040502 11100011111111* +L040502 00100110011111* L040516 10100110011110* -L040530 00000110011110* -L040544 11101011111111* -L040558 11101111111111* +L040530 10100110011110* +L040544 10101111111110* +L040558 01100110011111* NOTE BLOCK 6 * L040572 - 111110111111111111101111111111111111111111111111111111111111111011 - 111111111111111111111111101111111111111111111011111111111111111111 - 110111111111111111111011111111111111111111111111111111111111111111 - 101111111110111111111111111111111111110111111111111111111111111111 - 111111111111111111111111111111111110111111111111111111111111111111 - 111111011111111111111111111011011111111111111111111111111001111111 - 111111111111101111111111111111111111011111111111010111111111111111 - 111111111111111001111111111111111111111110111111111111111111111111 - 111111111111111111111111111111110111111111101111111111111111111111* + 111111111111111111111110111101111110111111111111111111111111111111 + 111111111111110111101111111111011111111111111111111111101111111111 + 111110111111111111111111111111111111011111111111111111111011111111 + 111111111001111111111111111111111111111111111011111111111110111111 + 101111111111111111111011111111111111111111111111111111111111111111 + 111111011111111111111111110111111111111011111111111111111111111111 + 111111111111101110111111111111111111111111111111010111111111111111 + 111111111111111111111111111111111111111101111111111111111111101111 + 111011111111111111111111101111111111111111101111111111111111111111* L041166 111111111111111111111111111111111111111111111111111111111111111111* -L041232 111111111111111111111111111111111110111101011111111111110111111111* -L041298 111111111111101111111111111111111111111110011111111111111111111111* +L041232 101111111111111111111111111111111111110111011111111111111111011111* +L041298 111111111111101111111111111111111111111111011111111111111111101111* L041364 000000000000000000000000000000000000000000000000000000000000000000* L041430 000000000000000000000000000000000000000000000000000000000000000000* L041496 000000000000000000000000000000000000000000000000000000000000000000* -L041562 111111111111111111111111111111011111111111111111111111111111111111* +L041562 111111111111111101111111111111111111111111111111111111111111111111* L041628 000000000000000000000000000000000000000000000000000000000000000000* L041694 000000000000000000000000000000000000000000000000000000000000000000* L041760 000000000000000000000000000000000000000000000000000000000000000000* L041826 000000000000000000000000000000000000000000000000000000000000000000* L041892 111111111111111111111111111111111111111111111111111111111111111111* -L041958 111111111111110111111111111111111111111111111111111111111111111111* -L042024 000000000000000000000000000000000000000000000000000000000000000000* +L041958 111101111111111111111111111111111111111111011111111111111111111111* +L042024 110111111011111111111111101111111111111111011111111111111111111111* L042090 000000000000000000000000000000000000000000000000000000000000000000* L042156 000000000000000000000000000000000000000000000000000000000000000000* L042222 000000000000000000000000000000000000000000000000000000000000000000* -L042288 111111111111111111111111110111111111111111111111111111111111111111* +L042288 111111111111110111111111111111111111111111111111111111111111111111* L042354 000000000000000000000000000000000000000000000000000000000000000000* L042420 000000000000000000000000000000000000000000000000000000000000000000* L042486 000000000000000000000000000000000000000000000000000000000000000000* L042552 000000000000000000000000000000000000000000000000000000000000000000* L042618 000000000000000000000000000000000000000000000000000000000000000000* -L042684 111111111111111111111111111111110111111111111111111111111101111011* -L042750 111111111111111111111111111111111011111111111111111111111110110111* +L042684 111111111111111111111011111111111101111111111111111111111101111111* +L042750 111111111111111111110111111111111110111111111111111111111110111111* L042816 000000000000000000000000000000000000000000000000000000000000000000* L042882 000000000000000000000000000000000000000000000000000000000000000000* L042948 000000000000000000000000000000000000000000000000000000000000000000* -L043014 111101111111111111111111111111111111111111111111111111111111111111* -L043080 000000000000000000000000000000000000000000000000000000000000000000* -L043146 000000000000000000000000000000000000000000000000000000000000000000* +L043014 111111111111111111111111111111111111111111101111111111111111111111* +L043080 111111111111111111111111111111111111110111110111111111111111011111* +L043146 111111111111111111111111111111111111111110111111101111111111101111* L043212 000000000000000000000000000000000000000000000000000000000000000000* L043278 000000000000000000000000000000000000000000000000000000000000000000* L043344 000000000000000000000000000000000000000000000000000000000000000000* -L043410 111111011111111111111111111111111111111111111111111111111111111111* +L043410 111111111101111111111111111111111111111111111111111111111111111111* L043476 000000000000000000000000000000000000000000000000000000000000000000* L043542 000000000000000000000000000000000000000000000000000000000000000000* L043608 000000000000000000000000000000000000000000000000000000000000000000* L043674 000000000000000000000000000000000000000000000000000000000000000000* -L043740 110111111111111111111111111111111111111111111111111111111111111111* +L043740 111111111111111111011111111111111111111111111111111111111111111111* L043806 000000000000000000000000000000000000000000000000000000000000000000* L043872 000000000000000000000000000000000000000000000000000000000000000000* L043938 000000000000000000000000000000000000000000000000000000000000000000* L044004 000000000000000000000000000000000000000000000000000000000000000000* L044070 - 111111111111111111111111111111111111101110111111110111111111111111* + 111111111111111111111111111111101111111111111111110111111111101111* L044136 111111111111111111111111111111111111111111101111111111111111111111* -L044202 111111111111111111110111111111111111111101111111111111110111111111* -L044268 111111111111111101111111111111111111111110111111111111111111111111* +L044202 111111111111111111111111111111111111110111111111111111110111011111* +L044268 111111111111111111111111111111111111111101111111111111111111101111* L044334 000000000000000000000000000000000000000000000000000000000000000000* L044400 000000000000000000000000000000000000000000000000000000000000000000* -L044466 111111111111111111111111111111111111111111101111111111111111111111* -L044532 111111111111111111111111011111111111111101111111111111110111111111* -L044598 111111111111111110111111111111111111111110111111101111111111111111* +L044466 111111111111111111111111111111111111111011011111111111111111011111* +L044532 111111111111111111111111111111111111111111011111111111101111011111* +L044598 111111111111111111111111111111111111111110011111101111111111101111* L044664 000000000000000000000000000000000000000000000000000000000000000000* L044730 000000000000000000000000000000000000000000000000000000000000000000* L044796 - 111111111111111111111111111111111111101110111111111111111111111111* -L044862 111111111111111111111111111111111111110111111111111111111111111111* + 111111111111111111111111111111101111111111111111111111111111101111* +L044862 111111111111111111111101111111111111111111111111111111111111111111* L044928 000000000000000000000000000000000000000000000000000000000000000000* L044994 000000000000000000000000000000000000000000000000000000000000000000* L045060 000000000000000000000000000000000000000000000000000000000000000000* L045126 000000000000000000000000000000000000000000000000000000000000000000* -L045192 101111111111111111111111111111111111111111011111111111111111111111* +L045192 111111111111111111111111111111111111011111111111111111111111111111* L045258 000000000000000000000000000000000000000000000000000000000000000000* L045324 000000000000000000000000000000000000000000000000000000000000000000* L045390 000000000000000000000000000000000000000000000000000000000000000000* L045456 000000000000000000000000000000000000000000000000000000000000000000* L045522 - 111111111111111111111111111111111111111110111111110111111111111111* -L045588 111111111111111111011111101111111111111111111111111111111111111111* + 111111111111111111111111111111111111111111111111110111111111101111* +L045588 111111111111111111111111111111111111111111111011111111011111111111* L045654 000000000000000000000000000000000000000000000000000000000000000000* L045720 000000000000000000000000000000000000000000000000000000000000000000* L045786 000000000000000000000000000000000000000000000000000000000000000000* L045852 000000000000000000000000000000000000000000000000000000000000000000* -L045918 111111111111111111111111111111111111111101011111111111111011111111* -L045984 111111111111111111101111111111111111111101011111111111111111111111* -L046050 111111111111111110111111111111111111111110011111101111111111111111* +L045918 111111111111111111111111111101111111111111111111111111111111111111* +L045984 000000000000000000000000000000000000000000000000000000000000000000* +L046050 000000000000000000000000000000000000000000000000000000000000000000* L046116 000000000000000000000000000000000000000000000000000000000000000000* L046182 000000000000000000000000000000000000000000000000000000000000000000* L046248 000000000000000000000000000000000000000000000000000000000000000000* -L046314 111111111101111111111111111111111111111111111111111111111111111111* +L046314 111111111111111111111111110111111111111111111111111111111111111111* L046380 000000000000000000000000000000000000000000000000000000000000000000* L046446 000000000000000000000000000000000000000000000000000000000000000000* L046512 000000000000000000000000000000000000000000000000000000000000000000* L046578 000000000000000000000000000000000000000000000000000000000000000000* -L046644 111111111111111111111111111111111111111111110111111111111111111111* +L046644 111111011111111111111111111111111111111111111111111111111111111111* L046710 000000000000000000000000000000000000000000000000000000000000000000* L046776 000000000000000000000000000000000000000000000000000000000000000000* L046842 000000000000000000000000000000000000000000000000000000000000000000* @@ -949,94 +956,94 @@ L046974 L047106 0010* L047110 11100110011000* L047124 00100110011110* -L047138 00100110010100* +L047138 11100110010100* L047152 00100110011111* L047166 10101011111001* -L047180 00100110010011* +L047180 10100110010011* L047194 00100110010000* L047208 00100110010010* L047222 10100110010001* -L047236 10100110010011* +L047236 11100110010011* L047250 00100110010100* -L047264 01100110010010* +L047264 00100110010010* L047278 00100011110010* -L047292 11100110010011* +L047292 00100110010011* L047306 00100110010001* L047320 00100110011111* NOTE BLOCK 7 * L047334 - 111111111111111111111111111111111111111110111111111011111111111111 - 111111111111111110111011111111111111111111111111111111111111111111 - 111110111111101111111111111110111111111111111111111111111111111111 + 111111111111111111111111111111101111111111111111111111111011101111 + 111111111101111111111011111111111111111111111111111011111111111111 + 111111111111101111111111111110111111111110111111111111111111111111 111111111111111111111111101011111111111111111011111111111111111111 - 111111111110111111111111111111111111111111111111111111111111101111 - 111111110111111111111111111111111111111111111111011111011111111111 - 111111011111110111111110111111011101111111111111111101111111111111 - 101111111111111111111111111111111111101111111111111111111111111110 - 111011111111111111011111111111111011110111101110111111111011111111* + 111111111111111111111111111111111111111111111111111111111111111011 + 111111111111111111111111111111111111101111111111011111011111111101 + 111111011111110111111110111111111001111111111111111101111111111111 + 111111111111111111101111111111111111111111101111111111111111111111 + 101010111011111101111111111111111111111011111110111111111111111111* L047928 000000000000000000000000000000000000000000000000000000000000000000* -L047994 111110111101111111111111111111111111111111011010111111111111111111* -L048060 111110111101111111111111111111111111111111011110111111111111101111* -L048126 111101111111111110111111111111111111111111011111111111111111111111* +L047994 011111101111111111111111111111111111111110111110111111111111110111* +L048060 011111111111111111111111111110111111111110111110111111111111110111* +L048126 011111111111111111111111111111111111111101111111111011111111111111* L048192 000000000000000000000000000000000000000000000000000000000000000000* L048258 000000000000000000000000000000000000000000000000000000000000000000* -L048324 111111110111011111111111010111111110111011111111111110101111111110* +L048324 011111111111111111101111111111111111111111111111111111111111111111* L048390 000000000000000000000000000000000000000000000000000000000000000000* L048456 000000000000000000000000000000000000000000000000000000000000000000* L048522 000000000000000000000000000000000000000000000000000000000000000000* L048588 000000000000000000000000000000000000000000000000000000000000000000* L048654 000000000000000000000000000000000000000000000000000000000000000000* -L048720 111111111111111111111111111111011111111111111111111111111111111111* -L048786 000000000000000000000000000000000000000000000000000000000000000000* -L048852 000000000000000000000000000000000000000000000000000000000000000000* -L048918 000000000000000000000000000000000000000000000000000000000000000000* -L048984 000000000000000000000000000000000000000000000000000000000000000000* -L049050 111111111111111111111111111111111111111111011111111111111111111110* -L049116 000000000000000000000000000000000000000000000000000000000000000000* -L049182 000000000000000000000000000000000000000000000000000000000000000000* -L049248 000000000000000000000000000000000000000000000000000000000000000000* -L049314 000000000000000000000000000000000000000000000000000000000000000000* +L048720 111111111111111111111111111111111111011111111111111111111111111111* +L048786 111111111111111111111111111111111111111111111111111111111111111111* +L048852 111111111111111111111111111111111111111111111111111111111111111111* +L048918 111111111111111111111111111111111111111111111111111111111111111111* +L048984 111111111111111111111111111111111111111111111111111111111111111111* +L049050 111111111111111111111111111111111111111111111111111111111111111111* +L049116 111111111111111111111111111111111111111111111111111111111111111111* +L049182 111111111111111111111111111111111111111111111111111111111111111111* +L049248 111111111111111111111111111111111111111111111111111111111111111111* +L049314 111111111111111111111111111111111111111111111111111111111111111111* L049380 111111111111111111111111111111111111111111111111111111111111111111* -L049446 111111111111111111111111111111111111111111101111111111111111111111* -L049512 011111110111111111111111111111111111111111111111111111111111111111* -L049578 111111110111111111111111111111110111111111110111111111111111111111* -L049644 000000000000000000000000000000000000000000000000000000000000000000* -L049710 000000000000000000000000000000000000000000000000000000000000000000* +L049446 111111111111011110101111010111111110111111111111111110101111111101* +L049512 111111111111111111111111111111111111111111111111111111111111111111* +L049578 111111111111111111111111111111111111111111111111111111111111111111* +L049644 111111111111111111111111111111111111111111111111111111111111111111* +L049710 111111111111111111111111111111111111111111111111111111111111111111* L049776 111111111111111111111111111111111111111111111111111111111111111111* L049842 111111111111111111111111111111111111111111111111111111111111111111* L049908 111111111111111111111111111111111111111111111111111111111111111111* L049974 111111111111111111111111111111111111111111111111111111111111111111* L050040 111111111111111111111111111111111111111111111111111111111111111111* L050106 - 101111101111110111111111111111111111111111111111111111111111111111* -L050172 111111111111111111111111111111111111111111111111111111110111111111* -L050238 111111111111111111111111111111111111111111111111111111111111111111* -L050304 111111111111111111111111111111111111111111111111111111111111111111* -L050370 111111111111111111111111111111111111111111111111111111111111111111* -L050436 111111111111111111111111111111111111111111111111111111111111111111* + 111111111110110111111111111111111111111111101111111111111111111111* +L050172 101111111111111111111111111111111111111111111111111111111111111111* +L050238 111111111111111111111111111111111111111111011111111111111111111101* +L050304 111101011111111111111111111111111111111111111111111111111111111101* +L050370 000000000000000000000000000000000000000000000000000000000000000000* +L050436 000000000000000000000000000000000000000000000000000000000000000000* L050502 111111111111111111111111111111111111111111111111111111111111111111* L050568 111111111111111111111111111111111111111111111111111111111111111111* L050634 111111111111111111111111111111111111111111111111111111111111111111* L050700 111111111111111111111111111111111111111111111111111111111111111111* L050766 111111111111111111111111111111111111111111111111111111111111111111* L050832 - 111111011111111111111111111111111111111111111111111111111111111111* -L050898 111111111111111111101111111111111011111111111111111111111111111111* + 111111111101111111111111111111111111111111111111111111111111111111* +L050898 111110111111111111111111111111111111111111111111101111111111111111* L050964 111111111111111111111111111111111111111111111111111111111111111111* L051030 111111111111111111111111111111111111111111111111111111111111111111* L051096 111111111111111111111111111111111111111111111111111111111111111111* L051162 111111111111111111111111111111111111111111111111111111111111111111* -L051228 111111111111111111111111111101011111111110011111111111111111111111* -L051294 111111111111111111111111111101011111111111011111011111111111111111* -L051360 111111111111111111111111111101111111111111011111111111110111111111* -L051426 110111111111111111111110111111111111101111011111111111111111111111* +L051228 011111111111111111111111111111011111011111111111111111111011101111* +L051294 011111111111111111111111111111010111011111111111111111111111101111* +L051360 011111110111111111111111111111011111101111111111111111111111111111* +L051426 010111111111111111111110111111111111111011111111111111111111111111* L051492 000000000000000000000000000000000000000000000000000000000000000000* L051558 - 011111111111110111111111111111111111111111111111111111111111111111* -L051624 111111111111111111111111111111111111111111111111111111111111111111* + 111111111111110111111111111111111111111111011111111111111111111111* +L051624 111111111111111111111111111111111111111111111111111111111111011111* L051690 111111111111111111111111111111111111111111111111111111111111111111* L051756 111111111111111111111111111111111111111111111111111111111111111111* L051822 111111111111111111111111111111111111111111111111111111111111111111* @@ -1047,13 +1054,13 @@ L052086 111111111111111111111111111111111111111111111111111111111111111111* L052152 111111111111111111111111111111111111111111111111111111111111111111* L052218 111111111111111111111111111111111111111111111111111111111111111111* L052284 - 101111101111111111111111111111111111111111111111111111111111111111* -L052350 111111111111111111110111111111111111111111111111111011111111111111* + 111111111110111111111111111111111111111111101111111111111111111111* +L052350 111111111111111111111011111111111111111111110111111111111111111111* L052416 111111111111111111111111111111111111111111111111111111111111111111* L052482 111111111111111111111111111111111111111111111111111111111111111111* L052548 111111111111111111111111111111111111111111111111111111111111111111* L052614 111111111111111111111111111111111111111111111111111111111111111111* -L052680 101111111111111111111111111111111111111111011111111111111111111111* +L052680 011111111111111111111111111111111111111111101111111111111111111111* L052746 111111111111111111111111111111111111111111111111111111111111111111* L052812 111111111111111111111111111111111111111111111111111111111111111111* L052878 111111111111111111111111111111111111111111111111111111111111111111* @@ -1074,21 +1081,21 @@ L053736 000000000000000000000000000000000000000000000000000000000000000000 000000000000000000000000000000000000000000000000000000000000000000* L053868 0010* -L053872 11100110011100* -L053886 01101011110010* -L053900 00100110010001* -L053914 01100110010011* -L053928 10100110010000* -L053942 11100011111110* -L053956 00110110010100* -L053970 11000011110011* -L053984 01111111111001* -L053998 11100110011111* -L054012 11010011110110* -L054026 11111011110011* -L054040 00111111110001* -L054054 01000110010011* -L054068 11010011111100* +L053872 11100110011000* +L053886 01100110010010* +L053900 00010110010000* +L053914 11100011110011* +L053928 01111111110101* +L053942 11001011111111* +L053956 10100110010100* +L053970 11001011110011* +L053984 01110011111000* +L053998 11100110011110* +L054012 00010110010111* +L054026 11101011110011* +L054040 00111111110000* +L054054 01000110010010* +L054068 11010011110111* L054082 11111011111111* E1 1 @@ -1102,13 +1109,13 @@ E1 1 01011001 1 -00000000 +00011111 1 -10001110 +11111110 1 10000010 1 * -C2728* +CB4EF* U00000000000000000000000000000000* -ECEB +5630 diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco index 4f33ac0..10aa91b 100644 --- a/Logic/68030_tk.lco +++ b/Logic/68030_tk.lco @@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; Design = 68030_tk.tt4; -DATE = 8/17/16; -TIME = 17:45:51; +DATE = 8/19/16; +TIME = 00:20:46; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -76,24 +76,32 @@ Usercode_Format = Hex; [LOCATION ASSIGNMENTS] Layer = OFF; +A_DECODE_22_ = pin,84,-,H,-; +A_DECODE_21_ = pin,94,-,A,-; SIZE_1_ = pin,79,-,H,-; -A_31_ = pin,4,-,B,-; +A_DECODE_20_ = pin,93,-,A,-; +A_DECODE_19_ = pin,97,-,A,-; +AHIGH_31_ = pin,4,-,B,-; +A_DECODE_18_ = pin,95,-,A,-; +A_DECODE_17_ = pin,59,-,F,-; +A_DECODE_23_ = pin,85,-,H,-; +A_DECODE_16_ = pin,96,-,A,-; IPL_2_ = pin,68,-,G,-; -IPL_1_ = pin,56,-,F,-; FC_1_ = pin,58,-,F,-; -IPL_0_ = pin,67,-,G,-; AS_030 = pin,82,-,H,-; -FC_0_ = pin,57,-,F,-; AS_000 = pin,42,-,E,-; DS_030 = pin,98,-,A,-; UDS_000 = pin,32,-,D,-; LDS_000 = pin,31,-,D,-; -A1 = pin,60,-,F,-; nEXP_SPACE = pin,14,-,-,-; BERR = pin,41,-,E,-; BG_030 = pin,21,-,C,-; +IPL_1_ = pin,56,-,F,-; +IPL_0_ = pin,67,-,G,-; BGACK_000 = pin,28,-,D,-; +FC_0_ = pin,57,-,F,-; CLK_030 = pin,64,-,-,-; +A_1_ = pin,60,-,F,-; CLK_000 = pin,11,-,-,-; CLK_OSZI = pin,61,-,-,-; CLK_DIV_OUT = pin,65,-,G,-; @@ -106,106 +114,108 @@ VPA = pin,36,-,-,-; RST = pin,86,-,-,-; RESET = pin,3,-,B,-; AMIGA_ADDR_ENABLE = pin,33,-,D,-; -SIZE_0_ = pin,70,-,G,-; AMIGA_BUS_DATA_DIR = pin,48,-,E,-; -A_30_ = pin,5,-,B,-; AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; -A_29_ = pin,6,-,B,-; AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-; -A_28_ = pin,15,-,C,-; CIIN = pin,47,-,E,-; -A_27_ = pin,16,-,C,-; -A_26_ = pin,17,-,C,-; -A_25_ = pin,18,-,C,-; -A_24_ = pin,19,-,C,-; -A_23_ = pin,85,-,H,-; -A_22_ = pin,84,-,H,-; -A_21_ = pin,94,-,A,-; -A_20_ = pin,93,-,A,-; -A_19_ = pin,97,-,A,-; -A_18_ = pin,95,-,A,-; -A_17_ = pin,59,-,F,-; -A_16_ = pin,96,-,A,-; +SIZE_0_ = pin,70,-,G,-; +AHIGH_30_ = pin,5,-,B,-; +AHIGH_29_ = pin,6,-,B,-; +AHIGH_28_ = pin,15,-,C,-; +AHIGH_27_ = pin,16,-,C,-; +AHIGH_26_ = pin,17,-,C,-; +AHIGH_25_ = pin,18,-,C,-; +AHIGH_24_ = pin,19,-,C,-; IPL_030_2_ = pin,9,-,B,-; +RW_000 = pin,80,-,H,-; +A_0_ = pin,69,-,G,-; IPL_030_1_ = pin,7,-,B,-; IPL_030_0_ = pin,8,-,B,-; -RW_000 = pin,80,-,H,-; -A0 = pin,69,-,G,-; BG_000 = pin,29,-,D,-; BGACK_030 = pin,83,-,H,-; CLK_EXP = pin,10,-,B,-; DSACK1 = pin,81,-,H,-; VMA = pin,35,-,D,-; RW = pin,71,-,G,-; -N_317_i = node,-,-,F,14; -cpu_est_2_ = node,-,-,D,13; -cpu_est_3_ = node,-,-,F,12; -cpu_est_0_ = node,-,-,D,6; -cpu_est_1_ = node,-,-,D,2; -inst_AS_000_INT = node,-,-,C,1; -SM_AMIGA_5_ = node,-,-,F,8; -inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,B,2; -inst_AS_030_D0 = node,-,-,H,3; -inst_nEXP_SPACE_D0reg = node,-,-,A,8; -inst_AS_030_000_SYNC = node,-,-,C,4; +N_226 = node,-,-,F,14; +cpu_est_2_ = node,-,-,F,4; +cpu_est_3_ = node,-,-,F,1; +cpu_est_0_ = node,-,-,B,2; +cpu_est_1_ = node,-,-,F,12; +inst_AS_000_INT = node,-,-,G,2; +inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,B,10; +inst_AS_030_D0 = node,-,-,H,1; +inst_AS_030_000_SYNC = node,-,-,C,13; inst_BGACK_030_INT_D = node,-,-,H,13; -inst_AS_000_DMA = node,-,-,A,1; -inst_DS_000_DMA = node,-,-,A,13; -CYCLE_DMA_0_ = node,-,-,B,5; -CYCLE_DMA_1_ = node,-,-,C,12; -SIZE_DMA_0_ = node,-,-,G,13; -SIZE_DMA_1_ = node,-,-,G,9; -inst_VPA_D = node,-,-,F,2; -inst_UDS_000_INT = node,-,-,A,9; -inst_LDS_000_INT = node,-,-,A,5; -inst_CLK_OUT_PRE_D = node,-,-,A,12; -inst_DTACK_D0 = node,-,-,B,15; +inst_AS_000_DMA = node,-,-,A,12; +inst_DS_000_DMA = node,-,-,A,9; +CYCLE_DMA_0_ = node,-,-,A,10; +CYCLE_DMA_1_ = node,-,-,A,2; +SIZE_DMA_0_ = node,-,-,G,9; +SIZE_DMA_1_ = node,-,-,G,5; +inst_VPA_D = node,-,-,A,5; +inst_UDS_000_INT = node,-,-,B,6; +inst_LDS_000_INT = node,-,-,A,1; +inst_CLK_OUT_PRE_D = node,-,-,E,8; +CLK_000_D_10_ = node,-,-,G,15; +CLK_000_D_11_ = node,-,-,H,10; +inst_DTACK_D0 = node,-,-,C,15; inst_RESET_OUT = node,-,-,D,9; -inst_CLK_OUT_PRE_50 = node,-,-,F,13; -CLK_000_D_1_ = node,-,-,E,8; -CLK_000_D_0_ = node,-,-,B,9; -inst_CLK_000_PE = node,-,-,G,5; -CLK_000_P_SYNC_9_ = node,-,-,G,15; -inst_CLK_000_NE = node,-,-,G,2; -CLK_000_N_SYNC_11_ = node,-,-,H,6; -IPL_D0_0_ = node,-,-,G,11; -IPL_D0_1_ = node,-,-,D,15; -IPL_D0_2_ = node,-,-,B,11; -inst_CLK_000_NE_D0 = node,-,-,D,10; -SM_AMIGA_0_ = node,-,-,F,1; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,B,13; -SM_AMIGA_4_ = node,-,-,F,9; -inst_DS_000_ENABLE = node,-,-,C,8; -RST_DLY_0_ = node,-,-,D,3; -RST_DLY_1_ = node,-,-,D,14; -RST_DLY_2_ = node,-,-,D,7; -CLK_000_P_SYNC_0_ = node,-,-,E,2; -CLK_000_P_SYNC_1_ = node,-,-,B,7; -CLK_000_P_SYNC_2_ = node,-,-,G,7; -CLK_000_P_SYNC_3_ = node,-,-,E,13; -CLK_000_P_SYNC_4_ = node,-,-,G,3; +inst_CLK_OUT_PRE_50 = node,-,-,E,2; +CLK_000_D_1_ = node,-,-,C,6; +CLK_000_D_0_ = node,-,-,G,13; +CLK_000_P_SYNC_10_ = node,-,-,A,8; +SM_AMIGA_5_ = node,-,-,F,8; +IPL_D0_0_ = node,-,-,D,15; +IPL_D0_1_ = node,-,-,F,15; +IPL_D0_2_ = node,-,-,B,15; +CLK_000_D_2_ = node,-,-,G,11; +CLK_000_D_3_ = node,-,-,G,7; +CLK_000_D_4_ = node,-,-,C,11; +CLK_000_D_5_ = node,-,-,E,13; +CLK_000_D_6_ = node,-,-,B,11; +CLK_000_D_7_ = node,-,-,G,3; +CLK_000_D_8_ = node,-,-,B,7; +CLK_000_D_9_ = node,-,-,D,11; +CLK_000_D_12_ = node,-,-,H,2; +SM_AMIGA_0_ = node,-,-,F,5; +CLK_000_N_SYNC_0_ = node,-,-,D,2; +SM_AMIGA_4_ = node,-,-,F,10; +inst_DS_000_ENABLE = node,-,-,F,9; +CLK_000_N_SYNC_12_ = node,-,-,D,13; +RST_DLY_0_ = node,-,-,D,10; +RST_DLY_1_ = node,-,-,D,6; +RST_DLY_2_ = node,-,-,D,14; +CLK_000_P_SYNC_0_ = node,-,-,D,7; +CLK_000_P_SYNC_1_ = node,-,-,A,15; +CLK_000_P_SYNC_2_ = node,-,-,F,11; +CLK_000_P_SYNC_3_ = node,-,-,C,7; +CLK_000_P_SYNC_4_ = node,-,-,A,11; CLK_000_P_SYNC_5_ = node,-,-,G,14; -CLK_000_P_SYNC_6_ = node,-,-,A,3; -CLK_000_P_SYNC_7_ = node,-,-,B,3; -CLK_000_P_SYNC_8_ = node,-,-,G,10; -CLK_000_N_SYNC_0_ = node,-,-,E,9; -CLK_000_N_SYNC_1_ = node,-,-,A,14; -CLK_000_N_SYNC_2_ = node,-,-,B,14; -CLK_000_N_SYNC_3_ = node,-,-,B,10; -CLK_000_N_SYNC_4_ = node,-,-,B,6; -CLK_000_N_SYNC_5_ = node,-,-,D,11; -CLK_000_N_SYNC_6_ = node,-,-,G,6; -CLK_000_N_SYNC_7_ = node,-,-,F,3; -CLK_000_N_SYNC_8_ = node,-,-,A,10; -CLK_000_N_SYNC_9_ = node,-,-,A,6; -CLK_000_N_SYNC_10_ = node,-,-,H,2; -SM_AMIGA_6_ = node,-,-,F,4; -inst_CLK_030_H = node,-,-,A,2; -SM_AMIGA_1_ = node,-,-,F,5; -SM_AMIGA_3_ = node,-,-,F,6; -SM_AMIGA_2_ = node,-,-,F,10; +CLK_000_P_SYNC_6_ = node,-,-,G,10; +CLK_000_P_SYNC_7_ = node,-,-,D,3; +CLK_000_P_SYNC_8_ = node,-,-,A,7; +CLK_000_P_SYNC_9_ = node,-,-,C,3; +CLK_000_N_SYNC_1_ = node,-,-,E,9; +CLK_000_N_SYNC_2_ = node,-,-,A,3; +CLK_000_N_SYNC_3_ = node,-,-,F,7; +CLK_000_N_SYNC_4_ = node,-,-,A,14; +CLK_000_N_SYNC_5_ = node,-,-,A,6; +CLK_000_N_SYNC_6_ = node,-,-,B,3; +CLK_000_N_SYNC_7_ = node,-,-,G,6; +CLK_000_N_SYNC_8_ = node,-,-,B,14; +CLK_000_N_SYNC_9_ = node,-,-,F,3; +CLK_000_N_SYNC_10_ = node,-,-,C,14; +CLK_000_N_SYNC_11_ = node,-,-,C,10; +inst_CLK_000_NE_D0 = node,-,-,E,5; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,C,2; +SM_AMIGA_6_ = node,-,-,C,9; +inst_CLK_030_H = node,-,-,A,13; +SM_AMIGA_1_ = node,-,-,F,13; +SM_AMIGA_3_ = node,-,-,F,2; +SM_AMIGA_2_ = node,-,-,F,6; SM_AMIGA_i_7_ = node,-,-,F,0; -CIIN_0 = node,-,-,E,5; +CIIN_0 = node,-,-,E,10; [GROUP ASSIGNMENTS] Layer = OFF; diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out index 9dbe4bb..6905586 100644 --- a/Logic/68030_tk.out +++ b/Logic/68030_tk.out @@ -4155,4 +4155,8676 @@ 10 CLK_000 1 -1 -1 1 1 10 -1 5 A_29_ 1 -1 -1 1 4 5 -1 4 A_30_ 1 -1 -1 1 4 4 -1 - 3 A_31_ 1 -1 -1 1 4 3 -1 \ No newline at end of file + 3 A_31_ 1 -1 -1 1 4 3 -1 +131 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 + 79 RW_000 5 354 7 3 0 4 6 79 -1 3 0 21 + 40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21 + 68 A0 5 355 6 2 1 3 68 -1 3 0 21 + 70 RW 5 360 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 353 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 362 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 361 1 0 6 -1 10 0 21 + 80 DSACK1 5 358 7 0 80 -1 4 0 21 + 82 BGACK_030 5 357 7 0 82 -1 3 0 21 + 34 VMA 5 359 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 356 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 357 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 1 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 315 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 320 inst_CLK_000_PE 3 -1 0 6 0 1 2 3 5 7 -1 -1 1 0 21 + 322 inst_CLK_000_NE 3 -1 3 5 1 2 3 5 6 -1 -1 1 0 21 + 350 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 345 SM_AMIGA_6_ 3 -1 5 4 1 2 3 5 -1 -1 3 0 21 + 318 CLK_000_D_0_ 3 -1 0 4 0 3 4 5 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 347 SM_AMIGA_1_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 + 298 SM_AMIGA_5_ 3 -1 2 3 2 5 7 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 293 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 326 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 2 0 21 + 317 CLK_000_D_1_ 3 -1 4 3 0 4 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 329 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 331 RST_DLY_1_ 3 -1 6 2 1 6 -1 -1 4 0 21 + 359 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 330 RST_DLY_0_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 328 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 332 RST_DLY_2_ 3 -1 1 2 1 6 -1 -1 2 0 21 + 327 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 342 CLK_000_N_SYNC_9_ 3 -1 5 2 6 7 -1 -1 1 0 21 + 321 inst_CLK_000_NE_D0 3 -1 1 2 3 5 -1 -1 1 0 21 + 316 inst_CLK_OUT_PRE_50 3 -1 6 2 3 6 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21 + 362 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 361 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 353 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 346 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 348 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 358 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 351 N_232 3 -1 5 1 5 -1 -1 4 0 21 + 349 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 355 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 354 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 360 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 356 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 352 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 344 CLK_000_N_SYNC_11_ 3 -1 7 1 3 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_10_ 3 -1 6 1 7 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_8_ 3 -1 2 1 5 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_7_ 3 -1 0 1 2 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_6_ 3 -1 7 1 0 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_5_ 3 -1 4 1 7 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_4_ 3 -1 2 1 4 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_3_ 3 -1 0 1 2 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_2_ 3 -1 6 1 0 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_1_ 3 -1 0 1 6 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21 + 325 IPL_D0_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 324 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 323 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 319 CLK_000_D_2_ 3 -1 4 1 0 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 3 67 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 59 A1 1 -1 -1 2 0 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 1 13 -1 + 10 CLK_000 1 -1 -1 1 0 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +130 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 353 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 359 6 2 1 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 354 6 1 6 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21 + 8 IPL_030_2_ 5 352 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 361 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 360 1 0 6 -1 10 0 21 + 80 DSACK1 5 357 7 0 80 -1 4 0 21 + 82 BGACK_030 5 356 7 0 82 -1 3 0 21 + 34 VMA 5 358 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 355 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 356 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 320 inst_CLK_000_PE 3 -1 5 6 0 1 2 3 5 7 -1 -1 1 0 21 + 322 inst_CLK_000_NE 3 -1 0 5 0 1 2 3 5 -1 -1 1 0 21 + 301 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21 + 350 SM_AMIGA_i_7_ 3 -1 2 4 1 3 5 7 -1 -1 15 0 21 + 347 SM_AMIGA_1_ 3 -1 1 4 0 1 2 7 -1 -1 3 0 21 + 345 SM_AMIGA_6_ 3 -1 5 4 1 2 5 6 -1 -1 3 0 21 + 299 SM_AMIGA_5_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 + 326 SM_AMIGA_0_ 3 -1 0 4 0 1 2 7 -1 -1 2 0 21 + 294 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 309 SIZE_DMA_0_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 319 CLK_000_D_0_ 3 -1 0 3 2 3 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 3 0 5 6 -1 -1 1 0 21 + 305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 303 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21 + 329 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21 + 349 SM_AMIGA_2_ 3 -1 2 2 1 2 -1 -1 4 0 21 + 358 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 328 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 327 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 2 2 2 3 -1 -1 2 0 21 + 318 CLK_000_D_1_ 3 -1 5 2 2 5 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 6 2 2 3 -1 -1 1 0 21 + 361 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 360 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 352 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 346 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 348 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 357 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 331 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 354 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 353 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 330 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 359 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 355 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 351 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 332 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 307 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 344 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_9_ 3 -1 1 1 7 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_8_ 3 -1 5 1 1 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_7_ 3 -1 1 1 5 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_6_ 3 -1 6 1 1 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_5_ 3 -1 5 1 6 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_4_ 3 -1 4 1 5 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_3_ 3 -1 3 1 4 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_2_ 3 -1 3 1 3 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_1_ 3 -1 6 1 3 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_0_ 3 -1 2 1 6 -1 -1 1 0 21 + 325 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 324 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 + 323 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 inst_CLK_000_NE_D0 3 -1 5 1 2 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 6 1 2 -1 -1 1 0 21 + 293 N_348_i 3 -1 2 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 59 A1 1 -1 -1 2 0 5 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 0 5 10 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 5 13 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +130 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 2 3 5 7 40 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 353 7 3 2 4 6 79 -1 5 0 21 + 70 RW 5 359 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 68 A0 5 354 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 352 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 361 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 360 1 0 6 -1 10 0 21 + 80 DSACK1 5 357 7 0 80 -1 4 0 21 + 82 BGACK_030 5 356 7 0 82 -1 3 0 21 + 34 VMA 5 358 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 355 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 356 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 3 6 0 3 4 5 6 7 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21 + 317 CLK_000_D_0_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21 + 301 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21 + 344 SM_AMIGA_6_ 3 -1 3 4 0 1 3 5 -1 -1 3 1 21 + 299 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21 + 303 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21 + 323 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 4 0 21 + 297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 349 SM_AMIGA_i_7_ 3 -1 5 3 0 3 7 -1 -1 2 0 21 + 326 CLK_000_N_SYNC_12_ 3 -1 5 3 1 3 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 306 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 305 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 325 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21 + 358 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 346 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 342 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 1 21 + 313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 343 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_10_ 3 -1 7 2 1 7 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 2 0 6 -1 -1 1 0 21 + 351 SM_AMIGA_i_7__0 3 -1 5 1 5 -1 -1 15 0 21 + 361 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 360 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 352 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 345 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 353 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 348 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 + 347 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 357 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 328 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 307 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 4 0 21 + 293 N_230_i 3 -1 5 1 5 -1 -1 4 0 21 + 354 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 327 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 359 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 355 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 350 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 329 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 + 341 CLK_000_N_SYNC_11_ 3 -1 1 1 5 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_7_ 3 -1 6 1 6 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_6_ 3 -1 2 1 6 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_4_ 3 -1 2 1 6 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_3_ 3 -1 5 1 2 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_2_ 3 -1 2 1 5 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_1_ 3 -1 4 1 2 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_0_ 3 -1 3 1 4 -1 -1 1 0 21 + 322 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 320 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 + 308 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 1 1 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 10 CLK_000 1 -1 -1 5 0 2 3 5 7 10 -1 + 96 A_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 3 13 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 + 79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21 + 40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21 + 70 RW 5 371 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 366 6 1 0 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21 + 80 DSACK1 5 369 7 0 80 -1 4 0 21 + 82 BGACK_030 5 368 7 0 82 -1 3 0 21 + 34 VMA 5 370 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 367 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 320 CLK_000_P_SYNC_10_ 3 -1 6 5 1 2 3 5 7 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 355 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21 + 299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 324 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 307 CYCLE_DMA_0_ 3 -1 1 3 0 1 2 -1 -1 2 0 21 + 319 CLK_000_D_0_ 3 -1 1 3 3 4 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 327 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 326 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 CYCLE_DMA_1_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 354 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_12_ 3 -1 6 2 3 5 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 4 2 4 5 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 5 2 0 5 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 + 364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 330 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21 + 366 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 329 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 371 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 331 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 353 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_8_ 3 -1 0 1 0 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_6_ 3 -1 6 1 5 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_7_ 3 -1 0 1 1 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_4_ 3 -1 4 1 6 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_3_ 3 -1 6 1 4 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_2_ 3 -1 1 1 6 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_0_ 3 -1 4 1 6 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +138 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 363 7 2 4 6 79 -1 3 0 21 + 70 RW 5 369 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 68 A0 5 364 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 31 UDS_000 5 -1 3 1 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 1 6 30 -1 1 0 21 + 8 IPL_030_2_ 5 360 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 362 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 361 1 0 6 -1 10 0 21 + 80 DSACK1 5 367 7 0 80 -1 4 0 21 + 82 BGACK_030 5 366 7 0 82 -1 3 0 21 + 34 VMA 5 368 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 365 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 366 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 316 inst_RESET_OUT 3 -1 0 6 0 1 3 4 6 7 -1 -1 2 0 21 + 320 CLK_000_P_SYNC_10_ 3 -1 2 5 0 3 5 6 7 -1 -1 1 0 21 + 301 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21 + 358 SM_AMIGA_i_7_ 3 -1 5 4 0 2 3 7 -1 -1 14 0 21 + 299 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 2 1 21 + 303 inst_AS_030_000_SYNC 3 -1 2 3 0 2 5 -1 -1 7 0 21 + 295 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 353 SM_AMIGA_6_ 3 -1 0 3 0 1 5 -1 -1 3 0 21 + 296 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 324 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 2 0 21 + 319 CLK_000_D_0_ 3 -1 3 3 0 3 5 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 0 3 0 3 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 3 3 1 2 6 -1 -1 1 0 21 + 306 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 + 305 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21 + 327 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21 + 368 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 326 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 355 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 1 21 + 325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 297 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 328 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21 + 362 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 361 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 360 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 354 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21 + 356 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 367 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 357 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 293 N_212_i 3 -1 5 1 5 -1 -1 4 0 21 + 364 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 363 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 351 RST_DLY_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 350 RST_DLY_0_ 3 -1 0 1 0 -1 -1 3 1 21 + 308 CYCLE_DMA_1_ 3 -1 6 1 6 -1 -1 3 0 21 + 369 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 365 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 359 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 352 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 307 CYCLE_DMA_0_ 3 -1 6 1 6 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 349 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_9_ 3 -1 5 1 7 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_8_ 3 -1 6 1 5 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_7_ 3 -1 1 1 6 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_6_ 3 -1 4 1 1 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_5_ 3 -1 3 1 4 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_4_ 3 -1 2 1 3 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_3_ 3 -1 7 1 2 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_2_ 3 -1 1 1 7 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_1_ 3 -1 4 1 1 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_0_ 3 -1 5 1 4 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_9_ 3 -1 2 1 2 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_8_ 3 -1 5 1 2 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_7_ 3 -1 3 1 5 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_6_ 3 -1 6 1 3 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_5_ 3 -1 0 1 6 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_4_ 3 -1 2 1 0 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_3_ 3 -1 3 1 2 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_2_ 3 -1 2 1 3 -1 -1 1 0 21 + 330 CLK_000_P_SYNC_1_ 3 -1 0 1 2 -1 -1 1 0 21 + 329 CLK_000_P_SYNC_0_ 3 -1 0 1 0 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 10 CLK_000 1 -1 -1 3 0 3 5 10 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 63 CLK_030 1 -1 -1 2 6 7 63 -1 + 59 A1 1 -1 -1 2 1 2 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +139 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 362 7 3 0 4 6 79 -1 3 0 21 + 70 RW 5 370 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 365 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 361 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21 + 80 DSACK1 5 368 7 0 80 -1 4 0 21 + 82 BGACK_030 5 367 7 0 82 -1 3 0 21 + 34 VMA 5 369 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 366 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 367 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 315 inst_RESET_OUT 3 -1 0 6 0 1 3 4 6 7 -1 -1 2 0 21 + 319 CLK_000_P_SYNC_10_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 5 1 2 3 4 7 -1 -1 1 0 21 + 358 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 13 0 21 + 298 SM_AMIGA_5_ 3 -1 5 4 1 2 5 7 -1 -1 2 1 21 + 293 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 353 SM_AMIGA_6_ 3 -1 5 3 1 2 5 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 324 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 323 CLK_000_D_2_ 3 -1 5 3 0 3 5 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 3 3 0 3 5 -1 -1 1 0 21 + 316 CLK_000_D_0_ 3 -1 3 3 0 3 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 327 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 369 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 355 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 1 21 + 326 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 2 0 21 + 325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 6 2 0 6 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 349 inst_CLK_000_NE_D0 3 -1 5 2 3 5 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 2 2 2 6 -1 -1 1 0 21 + 364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 361 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 354 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 359 N_160_i_3 3 -1 5 1 5 -1 -1 6 0 21 + 356 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 368 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 357 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 365 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 362 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 351 RST_DLY_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 350 RST_DLY_0_ 3 -1 0 1 0 -1 -1 3 1 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 370 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 366 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 360 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 352 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 348 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_9_ 3 -1 0 1 7 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_8_ 3 -1 3 1 0 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_7_ 3 -1 3 1 3 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_6_ 3 -1 1 1 3 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_5_ 3 -1 0 1 1 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_3_ 3 -1 1 1 6 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_1_ 3 -1 6 1 5 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_0_ 3 -1 3 1 6 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_9_ 3 -1 3 1 0 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_8_ 3 -1 7 1 3 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_7_ 3 -1 1 1 7 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_6_ 3 -1 4 1 1 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_5_ 3 -1 4 1 4 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_4_ 3 -1 0 1 4 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_3_ 3 -1 0 1 0 -1 -1 1 0 21 + 330 CLK_000_P_SYNC_2_ 3 -1 0 1 0 -1 -1 1 0 21 + 329 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21 + 328 CLK_000_P_SYNC_0_ 3 -1 3 1 6 -1 -1 1 0 21 + 322 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 321 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 320 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 59 A1 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +131 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 354 7 3 2 4 6 79 -1 5 0 21 + 81 AS_030 5 -1 7 3 3 4 7 81 -1 1 0 21 + 70 RW 5 360 6 2 0 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 68 A0 5 355 6 1 6 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21 + 8 IPL_030_2_ 5 353 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 362 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 361 1 0 6 -1 10 0 21 + 80 DSACK1 5 358 7 0 80 -1 4 0 21 + 82 BGACK_030 5 357 7 0 82 -1 3 0 21 + 34 VMA 5 359 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 356 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 357 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 315 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 319 CLK_000_D_0_ 3 -1 1 5 0 2 3 5 7 -1 -1 1 0 21 + 317 CLK_000_D_2_ 3 -1 2 5 0 2 3 5 7 -1 -1 1 0 21 + 316 CLK_000_D_1_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 3 5 0 1 3 4 7 -1 -1 1 0 21 + 345 SM_AMIGA_6_ 3 -1 2 4 0 2 5 6 -1 -1 4 0 21 + 324 SM_AMIGA_0_ 3 -1 5 4 0 1 5 7 -1 -1 4 0 21 + 350 SM_AMIGA_i_7_ 3 -1 1 4 0 2 3 7 -1 -1 2 0 21 + 298 SM_AMIGA_5_ 3 -1 5 4 0 1 5 7 -1 -1 2 0 21 + 302 inst_AS_030_000_SYNC 3 -1 0 3 0 2 5 -1 -1 7 0 21 + 293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 2 3 2 3 5 -1 -1 2 0 21 + 343 inst_CLK_000_NE_D0 3 -1 5 3 2 3 5 -1 -1 1 0 21 + 327 CLK_000_N_SYNC_12_ 3 -1 6 3 1 3 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21 + 305 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 304 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 326 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21 + 344 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 4 0 21 + 322 N_202_i 3 -1 5 2 1 5 -1 -1 4 0 21 + 359 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 347 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 0 21 + 325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 310 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21 + 352 SM_AMIGA_i_7__0 3 -1 5 1 1 -1 -1 15 0 21 + 362 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 361 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 353 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 348 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21 + 346 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 354 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 358 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 329 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 306 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 4 0 21 + 355 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 349 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 3 1 21 + 328 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 360 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 356 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 351 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 342 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_9_ 3 -1 1 1 7 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_8_ 3 -1 2 1 1 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_7_ 3 -1 1 1 2 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_6_ 3 -1 3 1 1 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_5_ 3 -1 2 1 3 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_4_ 3 -1 5 1 2 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_3_ 3 -1 6 1 5 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_2_ 3 -1 3 1 6 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_1_ 3 -1 4 1 3 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_0_ 3 -1 7 1 4 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 321 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 + 320 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 + 307 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 1 1 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 59 A1 1 -1 -1 2 2 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +130 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 2 3 5 7 40 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 353 7 3 2 4 6 79 -1 5 0 21 + 70 RW 5 359 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 68 A0 5 354 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 352 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 361 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 360 1 0 6 -1 10 0 21 + 80 DSACK1 5 357 7 0 80 -1 4 0 21 + 82 BGACK_030 5 356 7 0 82 -1 3 0 21 + 34 VMA 5 358 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 355 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 356 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 3 6 0 3 4 5 6 7 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21 + 317 CLK_000_D_0_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21 + 301 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21 + 344 SM_AMIGA_6_ 3 -1 3 4 0 1 3 5 -1 -1 3 1 21 + 299 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21 + 303 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21 + 323 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 4 0 21 + 297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 349 SM_AMIGA_i_7_ 3 -1 5 3 0 3 7 -1 -1 2 0 21 + 326 CLK_000_N_SYNC_12_ 3 -1 5 3 1 3 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 306 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 305 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 325 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21 + 358 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 346 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 342 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 1 21 + 313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 343 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_10_ 3 -1 7 2 1 7 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 2 0 6 -1 -1 1 0 21 + 351 SM_AMIGA_i_7__0 3 -1 5 1 5 -1 -1 15 0 21 + 361 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 360 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 352 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 345 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 353 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 348 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 + 347 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 357 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 328 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 307 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 4 0 21 + 293 N_230_i 3 -1 5 1 5 -1 -1 4 0 21 + 354 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 327 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 359 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 355 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 350 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 329 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 + 341 CLK_000_N_SYNC_11_ 3 -1 1 1 5 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_7_ 3 -1 6 1 6 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_6_ 3 -1 2 1 6 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_4_ 3 -1 2 1 6 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_3_ 3 -1 5 1 2 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_2_ 3 -1 2 1 5 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_1_ 3 -1 4 1 2 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_0_ 3 -1 3 1 4 -1 -1 1 0 21 + 322 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 320 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 + 308 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 1 1 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 10 CLK_000 1 -1 -1 5 0 2 3 5 7 10 -1 + 96 A_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 3 13 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +129 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 352 7 3 2 4 6 79 -1 5 0 21 + 70 RW 5 358 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 68 A0 5 353 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 351 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 360 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 359 1 0 6 -1 10 0 21 + 80 DSACK1 5 356 7 0 80 -1 4 0 21 + 82 BGACK_030 5 355 7 0 82 -1 3 0 21 + 34 VMA 5 357 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 354 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 355 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 348 CLK_000_D_0_ 3 -1 7 6 0 2 3 5 6 7 -1 -1 1 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 1 6 0 3 4 5 6 7 -1 -1 1 0 21 + 317 CLK_000_D_1_ 3 -1 6 5 0 2 3 5 7 -1 -1 1 0 21 + 301 inst_AS_030_D0 3 -1 7 5 0 1 3 4 7 -1 -1 1 0 21 + 299 SM_AMIGA_5_ 3 -1 5 4 0 1 5 7 -1 -1 3 0 21 + 347 SM_AMIGA_i_7_ 3 -1 2 4 0 3 5 7 -1 -1 2 0 21 + 322 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 4 0 21 + 297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 342 SM_AMIGA_6_ 3 -1 5 3 0 1 5 -1 -1 3 1 21 + 296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 325 CLK_000_N_SYNC_11_ 3 -1 7 3 3 4 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 1 3 1 6 7 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21 + 306 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 305 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 303 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21 + 324 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21 + 293 N_225_i 3 -1 5 2 2 5 -1 -1 4 0 21 + 357 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 344 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 340 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 1 21 + 313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 323 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 341 inst_CLK_000_NE_D0 3 -1 4 2 3 5 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_9_ 3 -1 6 2 6 7 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 2 1 4 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 + 350 SM_AMIGA_i_7__0 3 -1 5 1 2 -1 -1 15 0 21 + 360 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 359 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 351 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 343 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 352 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 346 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 + 345 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 356 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 327 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 307 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 4 0 21 + 353 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 326 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 358 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 354 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 349 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 328 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 339 CLK_000_N_SYNC_10_ 3 -1 6 1 7 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_8_ 3 -1 2 1 6 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_7_ 3 -1 1 1 2 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_6_ 3 -1 2 1 1 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_5_ 3 -1 1 1 2 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_4_ 3 -1 6 1 1 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_3_ 3 -1 3 1 6 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_2_ 3 -1 4 1 3 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_1_ 3 -1 1 1 4 -1 -1 1 0 21 + 329 CLK_000_N_SYNC_0_ 3 -1 7 1 1 -1 -1 1 0 21 + 321 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 320 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 319 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 5 1 5 -1 -1 1 0 21 + 308 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 1 1 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 10 CLK_000 1 -1 -1 5 0 2 3 5 7 10 -1 + 96 A_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 59 A1 1 -1 -1 2 2 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 5 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 1 13 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +138 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 363 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 369 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 364 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 361 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 362 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 360 1 0 6 -1 10 0 21 + 80 DSACK1 5 367 7 0 80 -1 4 0 21 + 82 BGACK_030 5 366 7 0 82 -1 3 0 21 + 34 VMA 5 368 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 365 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 366 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 320 CLK_000_P_SYNC_9_ 3 -1 4 6 0 2 3 5 6 7 -1 -1 1 0 21 + 301 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21 + 358 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 324 SM_AMIGA_0_ 3 -1 6 4 2 5 6 7 -1 -1 2 0 21 + 294 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 4 0 21 + 355 SM_AMIGA_1_ 3 -1 5 3 5 6 7 -1 -1 3 0 21 + 353 SM_AMIGA_6_ 3 -1 5 3 1 2 5 -1 -1 3 0 21 + 299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 296 cpu_est_0_ 3 -1 5 3 3 5 6 -1 -1 2 0 21 + 352 inst_CLK_000_NE_D0 3 -1 6 3 3 5 6 -1 -1 1 0 21 + 328 CLK_000_N_SYNC_11_ 3 -1 7 3 3 5 6 -1 -1 1 0 21 + 319 CLK_000_D_0_ 3 -1 1 3 1 3 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21 + 305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 327 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 368 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 326 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 350 CLK_000_N_SYNC_9_ 3 -1 1 2 6 7 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 5 2 1 5 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21 + 362 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 361 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 360 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 354 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 356 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 367 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 357 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 330 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21 + 364 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 363 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 329 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 369 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 365 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 359 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 331 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 307 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 351 CLK_000_N_SYNC_10_ 3 -1 6 1 7 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_8_ 3 -1 3 1 1 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_7_ 3 -1 6 1 3 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_6_ 3 -1 6 1 6 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_3_ 3 -1 7 1 1 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_2_ 3 -1 0 1 7 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_1_ 3 -1 4 1 0 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_0_ 3 -1 5 1 4 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_8_ 3 -1 3 1 4 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_7_ 3 -1 2 1 3 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_6_ 3 -1 1 1 2 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_5_ 3 -1 6 1 1 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_4_ 3 -1 0 1 6 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_3_ 3 -1 6 1 0 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_2_ 3 -1 0 1 6 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_1_ 3 -1 1 1 0 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A1 1 -1 -1 1 0 59 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +139 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 79 RW_000 5 364 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21 + 70 RW 5 370 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 365 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 361 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 363 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 362 1 0 6 -1 10 0 21 + 80 DSACK1 5 368 7 0 80 -1 4 0 21 + 82 BGACK_030 5 367 7 0 82 -1 3 0 21 + 34 VMA 5 369 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 366 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 367 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 320 CLK_000_P_SYNC_10_ 3 -1 0 5 0 2 3 5 7 -1 -1 1 0 21 + 359 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 354 SM_AMIGA_6_ 3 -1 5 3 1 2 5 -1 -1 3 0 21 + 299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 324 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 328 CLK_000_N_SYNC_11_ 3 -1 7 3 1 3 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21 + 305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 327 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 369 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 356 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 326 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 353 inst_CLK_000_NE_D0 3 -1 5 2 3 5 -1 -1 1 0 21 + 319 CLK_000_D_0_ 3 -1 1 2 3 5 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21 + 363 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 361 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 357 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 368 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 358 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 330 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21 + 365 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 364 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 329 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 370 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 366 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 360 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 331 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 + 307 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 352 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_8_ 3 -1 4 1 6 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_7_ 3 -1 0 1 4 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_4_ 3 -1 6 1 3 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_2_ 3 -1 3 1 0 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_1_ 3 -1 3 1 3 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_0_ 3 -1 5 1 3 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_9_ 3 -1 5 1 0 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_8_ 3 -1 3 1 5 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_7_ 3 -1 6 1 3 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_6_ 3 -1 0 1 6 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_5_ 3 -1 0 1 0 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_3_ 3 -1 1 1 6 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_2_ 3 -1 4 1 1 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_1_ 3 -1 3 1 4 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_0_ 3 -1 5 1 3 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 3 1 5 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 0 59 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +139 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 79 RW_000 5 364 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21 + 70 RW 5 370 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 365 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 361 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 363 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 362 1 0 6 -1 10 0 21 + 80 DSACK1 5 368 7 0 80 -1 4 0 21 + 82 BGACK_030 5 367 7 0 82 -1 3 0 21 + 34 VMA 5 369 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 366 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 367 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 320 CLK_000_P_SYNC_9_ 3 -1 0 5 0 2 3 5 7 -1 -1 1 0 21 + 359 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 301 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 354 SM_AMIGA_6_ 3 -1 5 3 1 2 5 -1 -1 3 0 21 + 299 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 324 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 328 CLK_000_N_SYNC_12_ 3 -1 3 3 1 3 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21 + 305 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 327 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 369 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 356 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 326 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 353 inst_CLK_000_NE_D0 3 -1 5 2 3 5 -1 -1 1 0 21 + 319 CLK_000_D_0_ 3 -1 1 2 3 5 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21 + 363 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 361 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 306 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 357 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 368 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 358 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 330 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 293 N_317_i 3 -1 5 1 5 -1 -1 4 0 21 + 365 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 364 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 329 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 308 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 370 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 366 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 360 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 331 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 + 307 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 352 CLK_000_N_SYNC_11_ 3 -1 7 1 3 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_8_ 3 -1 4 1 6 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_7_ 3 -1 0 1 4 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_4_ 3 -1 6 1 3 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_2_ 3 -1 3 1 0 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_1_ 3 -1 3 1 3 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_0_ 3 -1 5 1 3 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_8_ 3 -1 5 1 0 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_7_ 3 -1 3 1 5 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_6_ 3 -1 6 1 3 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_5_ 3 -1 0 1 6 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_3_ 3 -1 6 1 0 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_2_ 3 -1 1 1 6 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_1_ 3 -1 4 1 1 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_0_ 3 -1 5 1 4 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 3 1 5 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 0 59 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +130 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 2 3 5 7 40 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 353 7 3 2 4 6 79 -1 5 0 21 + 70 RW 5 359 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 68 A0 5 354 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 352 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 361 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 360 1 0 6 -1 10 0 21 + 80 DSACK1 5 357 7 0 80 -1 4 0 21 + 82 BGACK_030 5 356 7 0 82 -1 3 0 21 + 34 VMA 5 358 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 355 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 356 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 3 6 0 3 4 5 6 7 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21 + 317 CLK_000_D_0_ 3 -1 7 5 0 2 3 5 7 -1 -1 1 0 21 + 301 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21 + 344 SM_AMIGA_6_ 3 -1 3 4 0 1 3 5 -1 -1 3 1 21 + 299 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21 + 303 inst_AS_030_000_SYNC 3 -1 0 3 0 3 5 -1 -1 7 0 21 + 323 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 4 0 21 + 297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 349 SM_AMIGA_i_7_ 3 -1 5 3 0 3 7 -1 -1 2 0 21 + 326 CLK_000_N_SYNC_12_ 3 -1 5 3 1 3 5 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 306 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 305 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 325 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21 + 358 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 346 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 342 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 1 21 + 313 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 310 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 343 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_10_ 3 -1 7 2 1 7 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 2 0 6 -1 -1 1 0 21 + 351 SM_AMIGA_i_7__0 3 -1 5 1 5 -1 -1 15 0 21 + 361 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 360 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 352 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 345 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 353 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 348 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 + 347 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 357 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 328 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 307 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 4 0 21 + 293 N_230_i 3 -1 5 1 5 -1 -1 4 0 21 + 354 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 327 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 359 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 355 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 350 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 329 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 + 341 CLK_000_N_SYNC_11_ 3 -1 1 1 5 -1 -1 1 0 21 + 339 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21 + 338 CLK_000_N_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_7_ 3 -1 6 1 6 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_6_ 3 -1 2 1 6 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21 + 334 CLK_000_N_SYNC_4_ 3 -1 2 1 6 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_3_ 3 -1 5 1 2 -1 -1 1 0 21 + 332 CLK_000_N_SYNC_2_ 3 -1 2 1 5 -1 -1 1 0 21 + 331 CLK_000_N_SYNC_1_ 3 -1 4 1 2 -1 -1 1 0 21 + 330 CLK_000_N_SYNC_0_ 3 -1 3 1 4 -1 -1 1 0 21 + 322 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 320 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 + 308 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 1 1 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 10 CLK_000 1 -1 -1 5 0 2 3 5 7 10 -1 + 96 A_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 3 13 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A0 5 366 6 2 0 6 68 -1 3 0 21 + 70 RW 5 371 6 2 1 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 363 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 362 1 0 6 -1 10 0 21 + 80 DSACK1 5 369 7 0 80 -1 4 0 21 + 82 BGACK_030 5 368 7 0 82 -1 3 0 21 + 34 VMA 5 370 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 367 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 368 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 300 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 314 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 359 SM_AMIGA_i_7_ 3 -1 2 5 1 2 3 5 7 -1 -1 15 0 21 + 318 CLK_000_P_SYNC_10_ 3 -1 5 5 0 1 2 3 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21 + 354 SM_AMIGA_6_ 3 -1 2 4 0 1 2 6 -1 -1 3 0 21 + 323 SM_AMIGA_0_ 3 -1 0 4 0 1 2 7 -1 -1 2 0 21 + 327 CLK_000_N_SYNC_12_ 3 -1 0 4 0 1 2 3 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 356 SM_AMIGA_1_ 3 -1 2 3 0 2 7 -1 -1 3 0 21 + 319 SM_AMIGA_5_ 3 -1 2 3 1 2 7 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21 + 317 CLK_000_D_0_ 3 -1 6 3 2 3 5 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 6 3 1 6 7 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21 + 326 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21 + 370 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 325 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 353 inst_CLK_000_NE_D0 3 -1 2 2 2 6 -1 -1 1 0 21 + 316 CLK_000_D_1_ 3 -1 3 2 2 5 -1 -1 1 0 21 + 315 inst_CLK_OUT_PRE_50 3 -1 2 2 2 6 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21 + 364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 357 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 358 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21 + 329 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 366 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 328 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 371 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 360 N_319 3 -1 3 1 2 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_9_ 3 -1 4 1 7 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_8_ 3 -1 6 1 4 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_7_ 3 -1 5 1 6 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_6_ 3 -1 4 1 5 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_5_ 3 -1 0 1 4 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_3_ 3 -1 5 1 6 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_2_ 3 -1 0 1 5 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_1_ 3 -1 5 1 0 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_0_ 3 -1 5 1 5 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_9_ 3 -1 4 1 5 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_8_ 3 -1 3 1 4 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_7_ 3 -1 1 1 3 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_5_ 3 -1 5 1 0 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_4_ 3 -1 1 1 5 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_3_ 3 -1 3 1 1 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_2_ 3 -1 3 1 3 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_1_ 3 -1 3 1 3 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_0_ 3 -1 2 1 3 -1 -1 1 0 21 + 322 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 321 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 320 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 313 inst_DTACK_D0 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 59 A1 1 -1 -1 1 5 59 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 5 13 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +146 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 371 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A0 5 372 6 2 0 1 68 -1 3 0 21 + 70 RW 5 377 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 368 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 370 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 369 1 0 6 -1 10 0 21 + 80 DSACK1 5 375 7 0 80 -1 4 0 21 + 82 BGACK_030 5 374 7 0 82 -1 3 0 21 + 34 VMA 5 376 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 373 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 374 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 315 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 319 CLK_000_P_SYNC_10_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 5 6 0 3 4 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21 + 366 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 15 0 21 + 361 SM_AMIGA_6_ 3 -1 5 4 0 1 2 5 -1 -1 3 0 21 + 330 SM_AMIGA_0_ 3 -1 6 4 2 5 6 7 -1 -1 2 0 21 + 334 CLK_000_N_SYNC_12_ 3 -1 1 4 1 3 5 6 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 363 SM_AMIGA_1_ 3 -1 5 3 5 6 7 -1 -1 3 0 21 + 320 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 360 inst_CLK_000_NE_D0 3 -1 5 3 2 3 5 -1 -1 1 0 21 + 318 CLK_000_D_0_ 3 -1 6 3 1 3 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 3 3 2 3 5 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 364 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21 + 333 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 365 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 376 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 332 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 331 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 2 2 2 3 -1 -1 2 0 21 + 317 CLK_000_D_1_ 3 -1 5 2 1 5 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 3 2 2 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21 + 370 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 369 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 368 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 362 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 302 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21 + 375 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 336 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 372 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 371 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 335 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 377 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 373 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 367 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 337 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 359 CLK_000_N_SYNC_11_ 3 -1 3 1 1 -1 -1 1 0 21 + 358 CLK_000_N_SYNC_10_ 3 -1 3 1 3 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_9_ 3 -1 2 1 3 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_8_ 3 -1 6 1 2 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_7_ 3 -1 4 1 6 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_6_ 3 -1 4 1 4 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_5_ 3 -1 3 1 4 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_4_ 3 -1 2 1 3 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_3_ 3 -1 3 1 2 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_2_ 3 -1 1 1 3 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_9_ 3 -1 1 1 0 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_8_ 3 -1 0 1 1 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_7_ 3 -1 2 1 0 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_6_ 3 -1 2 1 2 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_5_ 3 -1 2 1 2 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_3_ 3 -1 1 1 0 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_0_ 3 -1 1 1 6 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 7 1 7 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 4 1 7 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 5 1 4 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 6 1 5 -1 -1 1 0 21 + 325 CLK_000_D_3_ 3 -1 3 1 6 -1 -1 1 0 21 + 324 CLK_000_D_2_ 3 -1 5 1 3 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 316 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21 + 293 N_319 3 -1 2 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 59 A1 1 -1 -1 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 5 13 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +145 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 369 7 3 0 4 6 79 -1 3 0 21 + 68 A0 5 371 6 2 3 6 68 -1 3 0 21 + 70 RW 5 376 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21 + 8 IPL_030_2_ 5 367 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 370 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 368 1 0 6 -1 10 0 21 + 80 DSACK1 5 374 7 0 80 -1 4 0 21 + 82 BGACK_030 5 373 7 0 82 -1 3 0 21 + 34 VMA 5 375 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 372 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 373 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 300 inst_nEXP_SPACE_D0reg 3 -1 2 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 315 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 319 CLK_000_P_SYNC_10_ 3 -1 1 6 0 1 2 3 5 7 -1 -1 1 0 21 + 333 CLK_000_N_SYNC_12_ 3 -1 0 5 0 1 3 5 7 -1 -1 1 0 21 + 365 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 360 SM_AMIGA_6_ 3 -1 5 4 2 3 5 6 -1 -1 3 0 21 + 320 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21 + 299 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 331 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 329 SM_AMIGA_0_ 3 -1 7 3 2 5 7 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 332 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 335 RST_DLY_1_ 3 -1 1 2 0 1 -1 -1 4 0 21 + 375 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 362 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 334 RST_DLY_0_ 3 -1 0 2 0 1 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 336 RST_DLY_2_ 3 -1 0 2 0 1 -1 -1 2 0 21 + 330 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 359 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 6 2 6 7 -1 -1 1 0 21 + 318 CLK_000_D_0_ 3 -1 3 2 3 5 -1 -1 1 0 21 + 317 CLK_000_D_1_ 3 -1 5 2 3 5 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 5 2 3 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21 + 370 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 368 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 367 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 361 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 363 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 374 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 364 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 302 N_263_i 3 -1 5 1 5 -1 -1 4 0 21 + 371 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 369 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 376 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 372 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 366 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 3 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 358 CLK_000_N_SYNC_11_ 3 -1 3 1 0 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_10_ 3 -1 0 1 3 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_8_ 3 -1 0 1 6 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_7_ 3 -1 0 1 0 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_6_ 3 -1 4 1 0 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_5_ 3 -1 6 1 4 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_4_ 3 -1 4 1 6 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_3_ 3 -1 6 1 4 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_2_ 3 -1 1 1 6 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_0_ 3 -1 3 1 3 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_9_ 3 -1 0 1 1 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_7_ 3 -1 6 1 2 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_6_ 3 -1 0 1 6 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_5_ 3 -1 1 1 0 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_4_ 3 -1 1 1 1 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_3_ 3 -1 1 1 1 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_1_ 3 -1 5 1 6 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_0_ 3 -1 3 1 5 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 6 1 7 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 1 1 6 -1 -1 1 0 21 + 325 CLK_000_D_3_ 3 -1 5 1 1 -1 -1 1 0 21 + 324 CLK_000_D_2_ 3 -1 5 1 5 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A1 1 -1 -1 1 2 59 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 2 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +147 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 79 RW_000 5 371 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21 + 68 A0 5 373 6 2 0 1 68 -1 3 0 21 + 70 RW 5 378 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 369 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 372 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 370 1 0 6 -1 10 0 21 + 80 DSACK1 5 376 7 0 80 -1 4 0 21 + 82 BGACK_030 5 375 7 0 82 -1 3 0 21 + 34 VMA 5 377 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 374 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 375 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 315 inst_RESET_OUT 3 -1 6 6 0 1 3 4 6 7 -1 -1 2 0 21 + 319 CLK_000_P_SYNC_10_ 3 -1 6 5 0 2 3 5 7 -1 -1 1 0 21 + 362 SM_AMIGA_6_ 3 -1 5 4 0 1 2 5 -1 -1 3 0 21 + 335 CLK_000_N_SYNC_12_ 3 -1 4 4 2 3 5 6 -1 -1 1 0 21 + 318 CLK_000_D_0_ 3 -1 3 4 0 2 3 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 4 0 1 5 6 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 4 3 4 5 7 -1 -1 1 0 21 + 367 SM_AMIGA_i_7_ 3 -1 2 3 3 5 7 -1 -1 15 0 21 + 294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 364 SM_AMIGA_1_ 3 -1 2 3 2 5 7 -1 -1 3 0 21 + 320 SM_AMIGA_5_ 3 -1 2 3 2 5 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 331 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21 + 334 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 377 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 333 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 332 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 2 2 2 3 -1 -1 2 0 21 + 361 inst_CLK_000_NE_D0 3 -1 5 2 2 3 -1 -1 1 0 21 + 317 CLK_000_D_1_ 3 -1 0 2 2 5 -1 -1 1 0 21 + 316 inst_CLK_OUT_PRE_50 3 -1 4 2 3 4 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 2 2 2 3 -1 -1 1 0 21 + 372 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 370 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 369 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 363 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 365 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 376 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 366 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21 + 337 RST_DLY_1_ 3 -1 6 1 6 -1 -1 4 0 21 + 373 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 371 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 336 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 378 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 374 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 368 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 338 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 360 CLK_000_N_SYNC_11_ 3 -1 0 1 4 -1 -1 1 0 21 + 359 CLK_000_N_SYNC_10_ 3 -1 0 1 0 -1 -1 1 0 21 + 358 CLK_000_N_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_8_ 3 -1 3 1 6 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_7_ 3 -1 3 1 3 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_6_ 3 -1 2 1 3 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_5_ 3 -1 1 1 2 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_4_ 3 -1 0 1 1 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_3_ 3 -1 1 1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_1_ 3 -1 6 1 0 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_0_ 3 -1 2 1 6 -1 -1 1 0 21 + 348 CLK_000_P_SYNC_9_ 3 -1 1 1 6 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_8_ 3 -1 5 1 1 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_7_ 3 -1 4 1 5 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_6_ 3 -1 1 1 4 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_5_ 3 -1 5 1 1 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_4_ 3 -1 1 1 5 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_3_ 3 -1 6 1 1 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_2_ 3 -1 6 1 6 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_1_ 3 -1 3 1 6 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_0_ 3 -1 5 1 3 -1 -1 1 0 21 + 330 CLK_000_D_8_ 3 -1 7 1 7 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 3 1 7 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 0 1 3 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 3 1 0 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 2 1 3 -1 -1 1 0 21 + 325 CLK_000_D_3_ 3 -1 1 1 2 -1 -1 1 0 21 + 324 CLK_000_D_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 5 1 2 -1 -1 1 0 21 + 293 N_319 3 -1 2 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A1 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 5 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +148 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 373 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 379 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 374 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 370 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 372 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 371 1 0 6 -1 10 0 21 + 80 DSACK1 5 377 7 0 80 -1 4 0 21 + 82 BGACK_030 5 376 7 0 82 -1 3 0 21 + 34 VMA 5 378 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 375 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 376 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 315 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 1 6 0 3 4 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 4 6 2 3 4 5 6 7 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_10_ 3 -1 1 5 0 2 3 5 7 -1 -1 1 0 21 + 368 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 15 0 21 + 320 SM_AMIGA_5_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21 + 294 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 363 SM_AMIGA_6_ 3 -1 5 3 1 2 5 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 + 332 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21 + 362 inst_CLK_000_NE_D0 3 -1 3 3 2 5 6 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_12_ 3 -1 0 3 1 3 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 2 3 1 6 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 0 3 2 3 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 3 0 5 6 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 366 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21 + 335 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 367 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 338 RST_DLY_1_ 3 -1 1 2 1 3 -1 -1 4 0 21 + 378 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 365 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 337 RST_DLY_0_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 334 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 339 RST_DLY_2_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 333 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 318 CLK_000_D_0_ 3 -1 3 2 3 5 -1 -1 1 0 21 + 317 CLK_000_D_1_ 3 -1 5 2 5 6 -1 -1 1 0 21 + 316 inst_CLK_OUT_PRE_50 3 -1 6 2 2 6 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 6 2 2 5 -1 -1 1 0 21 + 372 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 371 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 370 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 364 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 302 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21 + 377 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 374 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 373 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 379 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 375 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 369 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 361 CLK_000_N_SYNC_11_ 3 -1 6 1 0 -1 -1 1 0 21 + 360 CLK_000_N_SYNC_10_ 3 -1 1 1 6 -1 -1 1 0 21 + 359 CLK_000_N_SYNC_9_ 3 -1 6 1 1 -1 -1 1 0 21 + 358 CLK_000_N_SYNC_8_ 3 -1 5 1 6 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_7_ 3 -1 1 1 5 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_6_ 3 -1 1 1 1 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_5_ 3 -1 2 1 1 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_3_ 3 -1 2 1 0 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_2_ 3 -1 1 1 2 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_0_ 3 -1 5 1 6 -1 -1 1 0 21 + 349 CLK_000_P_SYNC_9_ 3 -1 2 1 1 -1 -1 1 0 21 + 348 CLK_000_P_SYNC_8_ 3 -1 2 1 2 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_7_ 3 -1 4 1 2 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_6_ 3 -1 0 1 4 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_5_ 3 -1 3 1 0 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_4_ 3 -1 3 1 3 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_3_ 3 -1 4 1 3 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_2_ 3 -1 0 1 4 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_1_ 3 -1 0 1 0 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 331 CLK_000_D_9_ 3 -1 7 1 7 -1 -1 1 0 21 + 330 CLK_000_D_8_ 3 -1 5 1 7 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 2 1 5 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 7 1 2 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 6 1 7 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 3 1 6 -1 -1 1 0 21 + 325 CLK_000_D_3_ 3 -1 3 1 3 -1 -1 1 0 21 + 324 CLK_000_D_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 293 N_377_i 3 -1 3 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 0 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 1 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +149 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 79 RW_000 5 372 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 3 2 5 7 40 -1 1 0 21 + 70 RW 5 380 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 375 6 1 0 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 371 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 374 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 373 1 0 6 -1 10 0 21 + 80 DSACK1 5 378 7 0 80 -1 4 0 21 + 82 BGACK_030 5 377 7 0 82 -1 3 0 21 + 34 VMA 5 379 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 376 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 377 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 300 inst_nEXP_SPACE_D0reg 3 -1 0 6 0 3 4 5 6 7 -1 -1 1 0 21 + 321 CLK_000_P_SYNC_10_ 3 -1 2 5 0 2 3 5 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21 + 369 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 15 0 21 + 337 CLK_000_N_SYNC_12_ 3 -1 1 4 1 3 4 5 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 364 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21 + 322 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 293 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 333 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 363 inst_CLK_000_NE_D0 3 -1 4 3 2 3 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 3 3 2 3 5 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 367 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21 + 336 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 368 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 379 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 366 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 335 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21 + 320 CLK_000_D_0_ 3 -1 1 2 3 5 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 0 2 2 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21 + 374 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 373 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 371 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 365 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21 + 378 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 339 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 375 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 372 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 338 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 380 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 376 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 370 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 340 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 362 CLK_000_N_SYNC_11_ 3 -1 6 1 1 -1 -1 1 0 21 + 361 CLK_000_N_SYNC_10_ 3 -1 5 1 6 -1 -1 1 0 21 + 360 CLK_000_N_SYNC_9_ 3 -1 0 1 5 -1 -1 1 0 21 + 359 CLK_000_N_SYNC_8_ 3 -1 6 1 0 -1 -1 1 0 21 + 358 CLK_000_N_SYNC_7_ 3 -1 3 1 6 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_6_ 3 -1 1 1 3 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_5_ 3 -1 2 1 1 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_4_ 3 -1 2 1 2 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_3_ 3 -1 3 1 2 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_2_ 3 -1 3 1 3 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_1_ 3 -1 3 1 3 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_0_ 3 -1 5 1 3 -1 -1 1 0 21 + 350 CLK_000_P_SYNC_9_ 3 -1 6 1 2 -1 -1 1 0 21 + 349 CLK_000_P_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21 + 348 CLK_000_P_SYNC_7_ 3 -1 0 1 1 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_6_ 3 -1 0 1 0 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_5_ 3 -1 1 1 0 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_4_ 3 -1 3 1 1 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_2_ 3 -1 6 1 6 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_1_ 3 -1 0 1 6 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_0_ 3 -1 5 1 0 -1 -1 1 0 21 + 332 CLK_000_D_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 331 CLK_000_D_7_ 3 -1 6 1 0 -1 -1 1 0 21 + 330 CLK_000_D_6_ 3 -1 1 1 6 -1 -1 1 0 21 + 329 CLK_000_D_5_ 3 -1 3 1 1 -1 -1 1 0 21 + 328 CLK_000_D_4_ 3 -1 2 1 3 -1 -1 1 0 21 + 327 CLK_000_D_3_ 3 -1 1 1 2 -1 -1 1 0 21 + 326 CLK_000_D_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 325 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 324 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 323 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 319 CLK_000_D_1_ 3 -1 5 1 5 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 CLK_000_D_9_ 3 -1 7 1 7 -1 -1 1 0 21 + 314 CLK_000_D_8_ 3 -1 0 1 7 -1 -1 1 0 21 + 302 N_343_i 3 -1 2 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 59 A1 1 -1 -1 1 6 59 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +148 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 371 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 379 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 374 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 370 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 373 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 372 1 0 6 -1 10 0 21 + 80 DSACK1 5 377 7 0 80 -1 4 0 21 + 82 BGACK_030 5 376 7 0 82 -1 3 0 21 + 34 VMA 5 378 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 375 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 376 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 300 inst_nEXP_SPACE_D0reg 3 -1 0 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 317 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 321 CLK_000_P_SYNC_10_ 3 -1 5 5 0 2 3 5 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21 + 368 SM_AMIGA_i_7_ 3 -1 2 4 2 3 5 7 -1 -1 15 0 21 + 322 SM_AMIGA_5_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 + 294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 363 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 293 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 332 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 2 0 21 + 336 CLK_000_N_SYNC_12_ 3 -1 2 3 2 3 5 -1 -1 1 0 21 + 320 CLK_000_D_0_ 3 -1 3 3 2 3 6 -1 -1 1 0 21 + 319 CLK_000_D_1_ 3 -1 2 3 2 5 6 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 3 0 5 6 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21 + 335 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 378 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 365 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21 + 334 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 333 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21 + 362 inst_CLK_000_NE_D0 3 -1 2 2 2 3 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 1 2 2 3 -1 -1 1 0 21 + 373 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 372 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 370 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 364 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 366 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 377 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 367 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21 + 338 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 374 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 371 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 337 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 379 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 375 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 369 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 339 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 361 CLK_000_N_SYNC_11_ 3 -1 6 1 2 -1 -1 1 0 21 + 360 CLK_000_N_SYNC_10_ 3 -1 6 1 6 -1 -1 1 0 21 + 359 CLK_000_N_SYNC_9_ 3 -1 1 1 6 -1 -1 1 0 21 + 358 CLK_000_N_SYNC_8_ 3 -1 6 1 1 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_7_ 3 -1 5 1 6 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_6_ 3 -1 1 1 5 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_5_ 3 -1 0 1 1 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_2_ 3 -1 1 1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_0_ 3 -1 6 1 6 -1 -1 1 0 21 + 349 CLK_000_P_SYNC_9_ 3 -1 1 1 5 -1 -1 1 0 21 + 348 CLK_000_P_SYNC_8_ 3 -1 0 1 1 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_6_ 3 -1 2 1 5 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_4_ 3 -1 0 1 6 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_3_ 3 -1 4 1 0 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_2_ 3 -1 3 1 4 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_1_ 3 -1 6 1 3 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_0_ 3 -1 2 1 6 -1 -1 1 0 21 + 331 CLK_000_D_9_ 3 -1 7 1 7 -1 -1 1 0 21 + 330 CLK_000_D_6_ 3 -1 5 1 6 -1 -1 1 0 21 + 329 CLK_000_D_5_ 3 -1 5 1 5 -1 -1 1 0 21 + 328 CLK_000_D_4_ 3 -1 1 1 5 -1 -1 1 0 21 + 327 CLK_000_D_3_ 3 -1 0 1 1 -1 -1 1 0 21 + 326 CLK_000_D_2_ 3 -1 5 1 0 -1 -1 1 0 21 + 325 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 324 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 0 1 2 -1 -1 1 0 21 + 315 CLK_000_D_8_ 3 -1 7 1 7 -1 -1 1 0 21 + 314 CLK_000_D_7_ 3 -1 6 1 7 -1 -1 1 0 21 + 301 N_343_i 3 -1 2 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A1 1 -1 -1 1 0 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +148 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 371 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A0 5 372 6 2 1 2 68 -1 3 0 21 + 70 RW 5 379 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 370 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 374 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 373 1 0 6 -1 10 0 21 + 80 DSACK1 5 377 7 0 80 -1 4 0 21 + 82 BGACK_030 5 376 7 0 82 -1 3 0 21 + 34 VMA 5 378 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 375 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 376 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 1 6 0 3 4 5 6 7 -1 -1 1 0 21 + 367 SM_AMIGA_i_7_ 3 -1 5 5 0 2 3 5 7 -1 -1 14 0 21 + 321 CLK_000_P_SYNC_10_ 3 -1 3 5 0 2 3 5 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 362 SM_AMIGA_6_ 3 -1 5 3 1 2 5 -1 -1 3 0 21 + 322 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 297 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 332 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 368 CLK_000_N_SYNC_12_ 3 -1 3 3 1 3 5 -1 -1 1 0 21 + 320 CLK_000_D_0_ 3 -1 1 3 0 3 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21 + 335 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 378 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 364 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 334 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 333 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 319 CLK_000_D_1_ 3 -1 3 2 0 5 -1 -1 1 0 21 + 314 CLK_000_D_6_ 3 -1 2 2 1 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 2 0 6 -1 -1 1 0 21 + 374 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 373 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 370 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 363 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 365 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 377 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 366 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 337 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 293 N_202_i 3 -1 5 1 5 -1 -1 4 0 21 + 372 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 371 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 336 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 379 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 375 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 369 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 338 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 361 inst_CLK_000_NE_D0 3 -1 3 1 5 -1 -1 1 0 21 + 360 CLK_000_N_SYNC_11_ 3 -1 2 1 3 -1 -1 1 0 21 + 359 CLK_000_N_SYNC_10_ 3 -1 0 1 2 -1 -1 1 0 21 + 358 CLK_000_N_SYNC_9_ 3 -1 3 1 0 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_8_ 3 -1 6 1 3 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_7_ 3 -1 3 1 6 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_6_ 3 -1 6 1 3 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_5_ 3 -1 2 1 6 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_4_ 3 -1 1 1 2 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_3_ 3 -1 2 1 1 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_2_ 3 -1 4 1 2 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_1_ 3 -1 2 1 4 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_0_ 3 -1 0 1 2 -1 -1 1 0 21 + 348 CLK_000_P_SYNC_9_ 3 -1 0 1 3 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_7_ 3 -1 3 1 2 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_6_ 3 -1 2 1 3 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_4_ 3 -1 6 1 6 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_3_ 3 -1 6 1 6 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_2_ 3 -1 1 1 6 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_0_ 3 -1 0 1 3 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 7 1 7 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 1 1 7 -1 -1 1 0 21 + 329 CLK_000_D_5_ 3 -1 2 1 2 -1 -1 1 0 21 + 328 CLK_000_D_4_ 3 -1 1 1 2 -1 -1 1 0 21 + 327 CLK_000_D_3_ 3 -1 6 1 1 -1 -1 1 0 21 + 326 CLK_000_D_2_ 3 -1 0 1 6 -1 -1 1 0 21 + 325 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 324 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 + 323 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 + 315 CLK_000_D_9_ 3 -1 7 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 59 A1 1 -1 -1 1 6 59 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 1 13 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +146 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 371 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A0 5 372 6 2 0 6 68 -1 3 0 21 + 70 RW 5 377 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 368 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 370 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 369 1 0 6 -1 10 0 21 + 80 DSACK1 5 375 7 0 80 -1 4 0 21 + 82 BGACK_030 5 374 7 0 82 -1 3 0 21 + 34 VMA 5 376 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 373 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 374 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 321 CLK_000_P_SYNC_10_ 3 -1 0 6 0 2 3 5 6 7 -1 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 5 6 0 3 4 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21 + 366 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 15 0 21 + 361 SM_AMIGA_6_ 3 -1 5 4 0 2 5 6 -1 -1 3 0 21 + 330 SM_AMIGA_0_ 3 -1 6 4 2 5 6 7 -1 -1 2 0 21 + 334 CLK_000_N_SYNC_12_ 3 -1 1 4 1 3 5 6 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 363 SM_AMIGA_1_ 3 -1 5 3 5 6 7 -1 -1 3 0 21 + 322 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 293 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 360 inst_CLK_000_NE_D0 3 -1 6 3 2 3 5 -1 -1 1 0 21 + 320 CLK_000_D_0_ 3 -1 5 3 3 4 5 -1 -1 1 0 21 + 319 CLK_000_D_1_ 3 -1 4 3 0 3 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 5 3 1 6 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 3 3 2 3 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 2 3 1 5 6 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 364 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 5 0 21 + 333 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 365 SM_AMIGA_2_ 3 -1 2 2 2 5 -1 -1 4 0 21 + 376 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 332 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 331 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 7 2 0 7 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21 + 316 inst_DTACK_D0 3 -1 0 2 2 5 -1 -1 1 0 21 + 370 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 369 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 368 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 362 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 302 inst_AS_030_000_SYNC 3 -1 5 1 5 -1 -1 7 0 21 + 375 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 336 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 372 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 371 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 335 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 377 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 373 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 367 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 337 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 + 359 CLK_000_N_SYNC_11_ 3 -1 1 1 1 -1 -1 1 0 21 + 358 CLK_000_N_SYNC_10_ 3 -1 0 1 1 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_7_ 3 -1 4 1 1 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_6_ 3 -1 1 1 4 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_5_ 3 -1 3 1 1 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_4_ 3 -1 0 1 3 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_3_ 3 -1 4 1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_2_ 3 -1 6 1 4 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_1_ 3 -1 2 1 6 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_0_ 3 -1 5 1 2 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_7_ 3 -1 6 1 6 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_6_ 3 -1 3 1 6 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_5_ 3 -1 3 1 3 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_4_ 3 -1 0 1 3 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_3_ 3 -1 0 1 0 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_2_ 3 -1 1 1 0 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_1_ 3 -1 2 1 1 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_0_ 3 -1 3 1 2 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 7 1 7 -1 -1 1 0 21 + 328 CLK_000_D_4_ 3 -1 6 1 3 -1 -1 1 0 21 + 327 CLK_000_D_3_ 3 -1 2 1 6 -1 -1 1 0 21 + 326 CLK_000_D_2_ 3 -1 0 1 2 -1 -1 1 0 21 + 325 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 324 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 323 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 5 1 5 -1 -1 1 0 21 + 315 CLK_000_D_6_ 3 -1 7 1 7 -1 -1 1 0 21 + 314 CLK_000_D_5_ 3 -1 3 1 7 -1 -1 1 0 21 + 299 N_343_i 3 -1 2 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 59 A1 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 5 13 -1 + 10 CLK_000 1 -1 -1 1 5 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +146 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 371 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A0 5 372 6 2 0 6 68 -1 3 0 21 + 70 RW 5 377 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 370 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 369 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 368 1 0 6 -1 10 0 21 + 82 BGACK_030 5 374 7 0 82 -1 3 0 21 + 34 VMA 5 376 3 0 34 -1 3 0 21 + 80 DSACK1 5 375 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 373 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 374 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 315 inst_RESET_OUT 3 -1 5 7 0 1 3 4 5 6 7 -1 -1 2 0 21 + 319 CLK_000_P_SYNC_10_ 3 -1 5 6 0 2 3 5 6 7 -1 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 0 6 0 2 3 4 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 5 1 2 3 4 7 -1 -1 1 0 21 + 361 SM_AMIGA_6_ 3 -1 2 4 0 2 5 6 -1 -1 3 0 21 + 333 SM_AMIGA_1_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21 + 320 SM_AMIGA_5_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 + 330 SM_AMIGA_0_ 3 -1 6 4 2 5 6 7 -1 -1 2 0 21 + 366 CLK_000_N_SYNC_12_ 3 -1 5 4 2 3 5 6 -1 -1 1 0 21 + 365 SM_AMIGA_i_7_ 3 -1 5 3 2 3 7 -1 -1 14 0 21 + 294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 318 CLK_000_D_0_ 3 -1 6 3 2 3 6 -1 -1 1 0 21 + 317 CLK_000_D_1_ 3 -1 6 3 2 3 6 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 363 SM_AMIGA_3_ 3 -1 5 2 2 5 -1 -1 5 0 21 + 334 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 364 SM_AMIGA_2_ 3 -1 5 2 2 5 -1 -1 4 0 21 + 376 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 332 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 331 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 360 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 321 inst_CLK_OUT_PRE_D 3 -1 4 2 1 6 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 7 2 3 5 -1 -1 1 0 21 + 370 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 369 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 368 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 362 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 302 inst_AS_030_000_SYNC 3 -1 2 1 2 -1 -1 7 0 21 + 336 RST_DLY_1_ 3 -1 5 1 5 -1 -1 4 0 21 + 293 N_201_i 3 -1 2 1 5 -1 -1 4 0 21 + 372 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 371 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 335 RST_DLY_0_ 3 -1 5 1 5 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 377 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 375 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 373 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 367 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 337 RST_DLY_2_ 3 -1 5 1 5 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 359 CLK_000_N_SYNC_11_ 3 -1 4 1 5 -1 -1 1 0 21 + 358 CLK_000_N_SYNC_10_ 3 -1 2 1 4 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_9_ 3 -1 6 1 2 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_7_ 3 -1 0 1 6 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_6_ 3 -1 4 1 0 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_5_ 3 -1 1 1 4 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_4_ 3 -1 0 1 1 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_3_ 3 -1 0 1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_2_ 3 -1 5 1 0 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_9_ 3 -1 6 1 5 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_8_ 3 -1 0 1 6 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_7_ 3 -1 1 1 0 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_6_ 3 -1 1 1 1 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_5_ 3 -1 1 1 1 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_4_ 3 -1 3 1 1 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_3_ 3 -1 5 1 3 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_2_ 3 -1 7 1 5 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_1_ 3 -1 1 1 7 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 7 1 7 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 0 1 5 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 1 1 0 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 3 1 1 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 6 1 3 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 + 313 CLK_000_D_6_ 3 -1 5 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 59 A1 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 7 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +147 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 372 7 3 0 4 6 79 -1 3 0 21 + 70 RW 5 378 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A0 5 373 6 1 0 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 371 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 370 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 369 1 0 6 -1 10 0 21 + 82 BGACK_030 5 375 7 0 82 -1 3 0 21 + 34 VMA 5 377 3 0 34 -1 3 0 21 + 80 DSACK1 5 376 7 0 80 -1 2 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 374 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 375 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 315 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 6 6 0 2 3 4 6 7 -1 -1 1 0 21 + 319 CLK_000_P_SYNC_10_ 3 -1 5 5 1 2 3 5 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 5 2 3 4 6 7 -1 -1 1 0 21 + 320 SM_AMIGA_5_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21 + 367 CLK_000_N_SYNC_12_ 3 -1 6 4 0 2 3 5 -1 -1 1 0 21 + 366 SM_AMIGA_i_7_ 3 -1 5 3 2 3 7 -1 -1 14 0 21 + 294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 362 SM_AMIGA_6_ 3 -1 2 3 0 2 5 -1 -1 3 0 21 + 334 SM_AMIGA_1_ 3 -1 2 3 2 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 331 SM_AMIGA_0_ 3 -1 2 3 2 5 7 -1 -1 2 0 21 + 318 CLK_000_D_0_ 3 -1 3 3 2 3 4 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 364 SM_AMIGA_3_ 3 -1 5 2 2 5 -1 -1 5 0 21 + 335 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 365 SM_AMIGA_2_ 3 -1 5 2 2 5 -1 -1 4 0 21 + 377 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 333 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 1 2 0 1 -1 -1 3 0 21 + 332 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 1 2 0 1 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 361 inst_CLK_000_NE_D0 3 -1 0 2 3 5 -1 -1 1 0 21 + 321 inst_CLK_OUT_PRE_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 317 CLK_000_D_1_ 3 -1 2 2 2 4 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 + 371 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 370 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 369 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 363 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 302 inst_AS_030_000_SYNC 3 -1 2 1 2 -1 -1 7 0 21 + 337 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 293 N_201_i 3 -1 2 1 5 -1 -1 4 0 21 + 373 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 372 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 336 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 378 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 376 RN_DSACK1 3 80 7 1 7 80 -1 2 0 21 + 374 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 368 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 338 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 360 CLK_000_N_SYNC_11_ 3 -1 3 1 6 -1 -1 1 0 21 + 359 CLK_000_N_SYNC_10_ 3 -1 5 1 3 -1 -1 1 0 21 + 358 CLK_000_N_SYNC_9_ 3 -1 0 1 5 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_8_ 3 -1 4 1 0 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_7_ 3 -1 0 1 4 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_6_ 3 -1 5 1 0 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_5_ 3 -1 5 1 5 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_4_ 3 -1 0 1 5 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_3_ 3 -1 3 1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_2_ 3 -1 1 1 3 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21 + 348 CLK_000_P_SYNC_9_ 3 -1 6 1 5 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_7_ 3 -1 5 1 6 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_6_ 3 -1 1 1 5 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_5_ 3 -1 1 1 1 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_4_ 3 -1 1 1 1 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_3_ 3 -1 5 1 1 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_2_ 3 -1 6 1 5 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_1_ 3 -1 6 1 6 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_0_ 3 -1 4 1 6 -1 -1 1 0 21 + 330 CLK_000_D_8_ 3 -1 7 1 7 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 5 1 2 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 0 1 5 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 1 1 0 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 5 1 1 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 4 1 5 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 inst_CLK_OUT_PRE_50 3 -1 7 1 7 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 313 CLK_000_D_7_ 3 -1 2 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 59 A1 1 -1 -1 2 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 63 CLK_030 1 -1 -1 1 0 63 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A0 5 366 6 2 0 6 68 -1 3 0 21 + 70 RW 5 371 6 2 1 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 363 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 362 1 0 6 -1 10 0 21 + 80 DSACK1 5 369 7 0 80 -1 4 0 21 + 82 BGACK_030 5 368 7 0 82 -1 3 0 21 + 34 VMA 5 370 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 367 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 368 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 300 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 314 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 359 SM_AMIGA_i_7_ 3 -1 2 5 1 2 3 5 7 -1 -1 15 0 21 + 318 CLK_000_P_SYNC_10_ 3 -1 5 5 0 1 2 3 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21 + 354 SM_AMIGA_6_ 3 -1 2 4 0 1 2 6 -1 -1 3 0 21 + 323 SM_AMIGA_0_ 3 -1 0 4 0 1 2 7 -1 -1 2 0 21 + 327 CLK_000_N_SYNC_12_ 3 -1 0 4 0 1 2 3 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 356 SM_AMIGA_1_ 3 -1 2 3 0 2 7 -1 -1 3 0 21 + 319 SM_AMIGA_5_ 3 -1 2 3 1 2 7 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21 + 317 CLK_000_D_0_ 3 -1 6 3 2 3 5 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 6 3 1 6 7 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21 + 326 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21 + 370 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 325 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 353 inst_CLK_000_NE_D0 3 -1 2 2 2 6 -1 -1 1 0 21 + 316 CLK_000_D_1_ 3 -1 3 2 2 5 -1 -1 1 0 21 + 315 inst_CLK_OUT_PRE_50 3 -1 2 2 2 6 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21 + 364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 357 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 358 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21 + 329 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 366 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 328 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 371 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 360 N_319 3 -1 3 1 2 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_9_ 3 -1 4 1 7 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_8_ 3 -1 6 1 4 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_7_ 3 -1 5 1 6 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_6_ 3 -1 4 1 5 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_5_ 3 -1 0 1 4 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_3_ 3 -1 5 1 6 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_2_ 3 -1 0 1 5 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_1_ 3 -1 5 1 0 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_0_ 3 -1 5 1 5 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_9_ 3 -1 4 1 5 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_8_ 3 -1 3 1 4 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_7_ 3 -1 1 1 3 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_5_ 3 -1 5 1 0 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_4_ 3 -1 1 1 5 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_3_ 3 -1 3 1 1 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_2_ 3 -1 3 1 3 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_1_ 3 -1 3 1 3 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_0_ 3 -1 2 1 3 -1 -1 1 0 21 + 322 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 321 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 320 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 313 inst_DTACK_D0 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 59 A1 1 -1 -1 1 5 59 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 5 13 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 365 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A0 5 366 6 2 0 6 68 -1 3 0 21 + 70 RW 5 371 6 2 1 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 363 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 362 1 0 6 -1 10 0 21 + 80 DSACK1 5 369 7 0 80 -1 4 0 21 + 82 BGACK_030 5 368 7 0 82 -1 3 0 21 + 34 VMA 5 370 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 367 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 368 RN_BGACK_030 3 82 7 7 0 2 3 4 5 6 7 82 -1 3 0 21 + 300 inst_nEXP_SPACE_D0reg 3 -1 5 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 314 inst_RESET_OUT 3 -1 1 6 0 1 3 4 6 7 -1 -1 2 0 21 + 359 SM_AMIGA_i_7_ 3 -1 2 5 1 2 3 5 7 -1 -1 15 0 21 + 318 CLK_000_P_SYNC_10_ 3 -1 5 5 0 1 2 3 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21 + 354 SM_AMIGA_6_ 3 -1 2 4 0 1 2 6 -1 -1 3 0 21 + 323 SM_AMIGA_0_ 3 -1 0 4 0 1 2 7 -1 -1 2 0 21 + 327 CLK_000_N_SYNC_12_ 3 -1 0 4 0 1 2 3 -1 -1 1 0 21 + 293 cpu_est_2_ 3 -1 2 3 2 3 6 -1 -1 4 0 21 + 356 SM_AMIGA_1_ 3 -1 2 3 0 2 7 -1 -1 3 0 21 + 319 SM_AMIGA_5_ 3 -1 2 3 1 2 7 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 6 3 2 3 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 2 3 2 3 6 -1 -1 2 0 21 + 317 CLK_000_D_0_ 3 -1 6 3 2 3 5 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 6 3 1 6 7 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21 + 326 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21 + 370 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 325 SM_AMIGA_4_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 324 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 5 2 3 5 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 353 inst_CLK_000_NE_D0 3 -1 2 2 2 6 -1 -1 1 0 21 + 316 CLK_000_D_1_ 3 -1 3 2 2 5 -1 -1 1 0 21 + 315 inst_CLK_OUT_PRE_50 3 -1 2 2 2 6 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 5 2 2 3 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 2 5 6 -1 -1 1 0 21 + 364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 357 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 5 0 21 + 369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 358 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 4 0 21 + 329 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 366 RN_A0 3 68 6 1 6 68 -1 3 0 21 + 365 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 328 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 371 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 330 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 360 N_319 3 -1 3 1 2 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_9_ 3 -1 4 1 7 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_8_ 3 -1 6 1 4 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_7_ 3 -1 5 1 6 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_6_ 3 -1 4 1 5 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_5_ 3 -1 0 1 4 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_4_ 3 -1 6 1 0 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_3_ 3 -1 5 1 6 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_2_ 3 -1 0 1 5 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_1_ 3 -1 5 1 0 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_0_ 3 -1 5 1 5 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_9_ 3 -1 4 1 5 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_8_ 3 -1 3 1 4 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_7_ 3 -1 1 1 3 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_5_ 3 -1 5 1 0 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_4_ 3 -1 1 1 5 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_3_ 3 -1 3 1 1 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_2_ 3 -1 3 1 3 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_1_ 3 -1 3 1 3 -1 -1 1 0 21 + 331 CLK_000_P_SYNC_0_ 3 -1 2 1 3 -1 -1 1 0 21 + 322 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 321 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 320 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 313 inst_DTACK_D0 3 -1 3 1 2 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_21_ 1 -1 -1 1 4 93 -1 + 92 A_20_ 1 -1 -1 1 4 92 -1 + 84 A_23_ 1 -1 -1 1 4 84 -1 + 83 A_22_ 1 -1 -1 1 4 83 -1 + 59 A1 1 -1 -1 1 5 59 -1 + 35 VPA 1 -1 -1 1 5 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 18 A_24_ 1 -1 -1 1 4 18 -1 + 17 A_25_ 1 -1 -1 1 4 17 -1 + 16 A_26_ 1 -1 -1 1 4 16 -1 + 15 A_27_ 1 -1 -1 1 4 15 -1 + 14 A_28_ 1 -1 -1 1 4 14 -1 + 13 nEXP_SPACE 1 -1 -1 1 5 13 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 + 5 A_29_ 1 -1 -1 1 4 5 -1 + 4 A_30_ 1 -1 -1 1 4 4 -1 + 3 A_31_ 1 -1 -1 1 4 3 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 381 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 310 A_0_ 5 384 6 2 1 6 -1 -1 3 0 21 + 70 RW 5 389 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 380 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 386 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 385 1 0 6 -1 10 0 21 + 80 DSACK1 5 387 7 0 80 -1 4 0 21 + 82 BGACK_030 5 383 7 0 82 -1 3 0 21 + 34 VMA 5 388 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 382 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 318 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 383 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 332 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 336 CLK_000_P_SYNC_10_ 3 -1 6 5 0 2 3 5 7 -1 -1 1 0 21 + 317 inst_AS_030_D0 3 -1 7 5 1 2 3 4 7 -1 -1 1 0 21 + 377 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 372 SM_AMIGA_6_ 3 -1 5 4 1 2 5 6 -1 -1 3 0 21 + 337 SM_AMIGA_5_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 + 311 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 314 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 312 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 341 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 335 CLK_000_D_0_ 3 -1 0 3 3 5 6 -1 -1 1 0 21 + 330 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 321 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 319 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 344 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 388 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 374 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 343 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 329 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 326 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 325 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 342 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 328 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 315 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 313 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 371 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_12_ 3 -1 0 2 3 5 -1 -1 1 0 21 + 334 CLK_000_D_1_ 3 -1 6 2 3 5 -1 -1 1 0 21 + 333 inst_CLK_OUT_PRE_50 3 -1 1 2 1 4 -1 -1 1 0 21 + 327 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 + 320 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21 + 386 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 385 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 380 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 322 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 373 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 375 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 387 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 378 N_104 3 -1 5 1 5 -1 -1 4 0 21 + 376 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 347 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 384 RN_A_0_ 3 310 6 1 6 -1 -1 3 0 21 + 381 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 346 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 324 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 389 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 382 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 379 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 348 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 323 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 316 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 370 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21 + 369 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 368 CLK_000_N_SYNC_9_ 3 -1 1 1 7 -1 -1 1 0 21 + 367 CLK_000_N_SYNC_8_ 3 -1 1 1 1 -1 -1 1 0 21 + 366 CLK_000_N_SYNC_7_ 3 -1 6 1 1 -1 -1 1 0 21 + 365 CLK_000_N_SYNC_6_ 3 -1 0 1 6 -1 -1 1 0 21 + 364 CLK_000_N_SYNC_5_ 3 -1 0 1 0 -1 -1 1 0 21 + 363 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21 + 362 CLK_000_N_SYNC_3_ 3 -1 1 1 0 -1 -1 1 0 21 + 361 CLK_000_N_SYNC_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 360 CLK_000_N_SYNC_1_ 3 -1 4 1 6 -1 -1 1 0 21 + 359 CLK_000_N_SYNC_0_ 3 -1 3 1 4 -1 -1 1 0 21 + 358 CLK_000_P_SYNC_9_ 3 -1 1 1 6 -1 -1 1 0 21 + 357 CLK_000_P_SYNC_8_ 3 -1 0 1 1 -1 -1 1 0 21 + 356 CLK_000_P_SYNC_7_ 3 -1 0 1 0 -1 -1 1 0 21 + 355 CLK_000_P_SYNC_6_ 3 -1 4 1 0 -1 -1 1 0 21 + 354 CLK_000_P_SYNC_5_ 3 -1 1 1 4 -1 -1 1 0 21 + 353 CLK_000_P_SYNC_4_ 3 -1 2 1 1 -1 -1 1 0 21 + 352 CLK_000_P_SYNC_3_ 3 -1 6 1 2 -1 -1 1 0 21 + 351 CLK_000_P_SYNC_2_ 3 -1 3 1 6 -1 -1 1 0 21 + 350 CLK_000_P_SYNC_1_ 3 -1 0 1 3 -1 -1 1 0 21 + 349 CLK_000_P_SYNC_0_ 3 -1 3 1 0 -1 -1 1 0 21 + 340 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 339 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 338 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 331 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 0 10 -1 + 308 AHIGH_16_ 1 -1 -1 3 2 4 7 -1 -1 + 307 AHIGH_17_ 1 -1 -1 3 2 4 7 -1 -1 + 306 AHIGH_18_ 1 -1 -1 3 2 4 7 -1 -1 + 305 AHIGH_19_ 1 -1 -1 3 2 4 7 -1 -1 + 309 A_1_ 1 -1 -1 1 2 -1 -1 + 304 AHIGH_20_ 1 -1 -1 1 4 -1 -1 + 303 AHIGH_21_ 1 -1 -1 1 4 -1 -1 + 302 AHIGH_22_ 1 -1 -1 1 4 -1 -1 + 301 AHIGH_23_ 1 -1 -1 1 4 -1 -1 + 300 AHIGH_24_ 1 -1 -1 1 4 -1 -1 + 299 AHIGH_25_ 1 -1 -1 1 4 -1 -1 + 298 AHIGH_26_ 1 -1 -1 1 4 -1 -1 + 297 AHIGH_27_ 1 -1 -1 1 4 -1 -1 + 296 AHIGH_28_ 1 -1 -1 1 4 -1 -1 + 295 AHIGH_29_ 1 -1 -1 1 4 -1 -1 + 294 AHIGH_30_ 1 -1 -1 1 4 -1 -1 + 293 AHIGH_31_ 1 -1 -1 1 4 -1 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 381 7 3 1 4 6 79 -1 3 0 21 + 310 A_0_ 5 384 6 2 0 6 -1 -1 3 0 21 + 70 RW 5 389 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21 + 300 AHIGH_24_ 5 -1 4 1 4 -1 -1 1 0 21 + 299 AHIGH_25_ 5 -1 4 1 4 -1 -1 1 0 21 + 298 AHIGH_26_ 5 -1 0 1 4 -1 -1 1 0 21 + 297 AHIGH_27_ 5 -1 4 1 4 -1 -1 1 0 21 + 296 AHIGH_28_ 5 -1 7 1 4 -1 -1 1 0 21 + 295 AHIGH_29_ 5 -1 7 1 4 -1 -1 1 0 21 + 294 AHIGH_30_ 5 -1 4 1 4 -1 -1 1 0 21 + 293 AHIGH_31_ 5 -1 0 1 4 -1 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 380 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 386 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 385 1 0 6 -1 10 0 21 + 80 DSACK1 5 387 7 0 80 -1 4 0 21 + 82 BGACK_030 5 383 7 0 82 -1 3 0 21 + 34 VMA 5 388 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 382 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 383 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 318 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 332 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 336 CLK_000_P_SYNC_10_ 3 -1 0 6 0 1 2 3 5 7 -1 -1 1 0 21 + 378 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 10 0 21 + 372 SM_AMIGA_6_ 3 -1 5 4 0 2 5 6 -1 -1 3 0 21 + 337 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21 + 317 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21 + 314 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 374 SM_AMIGA_1_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 + 343 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 + 313 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 311 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 341 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 345 CLK_000_N_SYNC_12_ 3 -1 0 3 0 3 5 -1 -1 1 0 21 + 330 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 322 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 + 321 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 + 319 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 344 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 376 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 4 0 21 + 347 RST_DLY_1_ 3 -1 0 2 0 3 -1 -1 4 0 21 + 388 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 346 RST_DLY_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 329 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 326 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 325 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 348 RST_DLY_2_ 3 -1 3 2 0 3 -1 -1 2 0 21 + 342 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 328 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 315 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 312 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 371 inst_CLK_000_NE_D0 3 -1 5 2 3 5 -1 -1 1 0 21 + 335 CLK_000_D_0_ 3 -1 5 2 3 5 -1 -1 1 0 21 + 334 CLK_000_D_1_ 3 -1 3 2 3 5 -1 -1 1 0 21 + 327 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21 + 320 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21 + 386 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 385 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 380 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 373 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 + 377 N_145_i_2 3 -1 0 1 5 -1 -1 5 0 21 + 375 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 387 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 384 RN_A_0_ 3 310 6 1 6 -1 -1 3 0 21 + 381 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 324 CYCLE_DMA_1_ 3 -1 1 1 1 -1 -1 3 0 21 + 389 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 382 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 379 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 323 CYCLE_DMA_0_ 3 -1 1 1 1 -1 -1 2 0 21 + 316 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 370 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21 + 369 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 368 CLK_000_N_SYNC_9_ 3 -1 2 1 7 -1 -1 1 0 21 + 367 CLK_000_N_SYNC_8_ 3 -1 0 1 2 -1 -1 1 0 21 + 366 CLK_000_N_SYNC_7_ 3 -1 0 1 0 -1 -1 1 0 21 + 365 CLK_000_N_SYNC_6_ 3 -1 2 1 0 -1 -1 1 0 21 + 364 CLK_000_N_SYNC_5_ 3 -1 0 1 2 -1 -1 1 0 21 + 363 CLK_000_N_SYNC_4_ 3 -1 1 1 0 -1 -1 1 0 21 + 362 CLK_000_N_SYNC_3_ 3 -1 5 1 1 -1 -1 1 0 21 + 361 CLK_000_N_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21 + 360 CLK_000_N_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21 + 359 CLK_000_N_SYNC_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 358 CLK_000_P_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21 + 357 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 356 CLK_000_P_SYNC_7_ 3 -1 0 1 6 -1 -1 1 0 21 + 355 CLK_000_P_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21 + 354 CLK_000_P_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21 + 353 CLK_000_P_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21 + 352 CLK_000_P_SYNC_3_ 3 -1 5 1 1 -1 -1 1 0 21 + 351 CLK_000_P_SYNC_2_ 3 -1 4 1 5 -1 -1 1 0 21 + 350 CLK_000_P_SYNC_1_ 3 -1 1 1 4 -1 -1 1 0 21 + 349 CLK_000_P_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 340 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 339 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 338 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 333 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 331 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 1 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 5 10 -1 + 309 AHIGH_16_ 1 -1 -1 3 2 4 7 -1 -1 + 308 AHIGH_17_ 1 -1 -1 3 2 4 7 -1 -1 + 307 AHIGH_18_ 1 -1 -1 3 2 4 7 -1 -1 + 306 AHIGH_19_ 1 -1 -1 3 2 4 7 -1 -1 + 301 A_1_ 1 -1 -1 2 2 6 -1 -1 + 305 AHIGH_20_ 1 -1 -1 1 4 -1 -1 + 304 AHIGH_21_ 1 -1 -1 1 4 -1 -1 + 303 AHIGH_22_ 1 -1 -1 1 4 -1 -1 + 302 AHIGH_23_ 1 -1 -1 1 4 -1 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 381 7 3 1 4 6 79 -1 3 0 21 + 310 A_0_ 5 384 6 2 0 6 -1 -1 3 0 21 + 70 RW 5 389 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21 + 300 AHIGH_24_ 5 -1 4 1 4 -1 -1 1 0 21 + 299 AHIGH_25_ 5 -1 4 1 4 -1 -1 1 0 21 + 298 AHIGH_26_ 5 -1 0 1 4 -1 -1 1 0 21 + 297 AHIGH_27_ 5 -1 4 1 4 -1 -1 1 0 21 + 296 AHIGH_28_ 5 -1 7 1 4 -1 -1 1 0 21 + 295 AHIGH_29_ 5 -1 7 1 4 -1 -1 1 0 21 + 294 AHIGH_30_ 5 -1 4 1 4 -1 -1 1 0 21 + 293 AHIGH_31_ 5 -1 0 1 4 -1 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 8 IPL_030_2_ 5 380 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 386 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 385 1 0 6 -1 10 0 21 + 80 DSACK1 5 387 7 0 80 -1 4 0 21 + 82 BGACK_030 5 383 7 0 82 -1 3 0 21 + 34 VMA 5 388 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 382 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 383 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 318 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 332 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 336 CLK_000_P_SYNC_10_ 3 -1 0 6 0 1 2 3 5 7 -1 -1 1 0 21 + 378 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 10 0 21 + 372 SM_AMIGA_6_ 3 -1 5 4 0 2 5 6 -1 -1 3 0 21 + 337 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21 + 317 inst_AS_030_D0 3 -1 7 4 2 3 4 7 -1 -1 1 0 21 + 314 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 374 SM_AMIGA_1_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 + 343 SM_AMIGA_4_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 + 313 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 311 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 341 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 345 CLK_000_N_SYNC_12_ 3 -1 0 3 0 3 5 -1 -1 1 0 21 + 330 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 322 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 + 321 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 + 319 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 344 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 376 SM_AMIGA_2_ 3 -1 5 2 0 5 -1 -1 4 0 21 + 347 RST_DLY_1_ 3 -1 0 2 0 3 -1 -1 4 0 21 + 388 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 346 RST_DLY_0_ 3 -1 3 2 0 3 -1 -1 3 0 21 + 329 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 326 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 325 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 348 RST_DLY_2_ 3 -1 3 2 0 3 -1 -1 2 0 21 + 342 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 328 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 315 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 312 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 371 inst_CLK_000_NE_D0 3 -1 5 2 3 5 -1 -1 1 0 21 + 335 CLK_000_D_0_ 3 -1 5 2 3 5 -1 -1 1 0 21 + 334 CLK_000_D_1_ 3 -1 3 2 3 5 -1 -1 1 0 21 + 327 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21 + 320 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21 + 386 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 385 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 380 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 373 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 + 377 N_145_i_2 3 -1 0 1 5 -1 -1 5 0 21 + 375 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 387 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 384 RN_A_0_ 3 310 6 1 6 -1 -1 3 0 21 + 381 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 324 CYCLE_DMA_1_ 3 -1 1 1 1 -1 -1 3 0 21 + 389 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 382 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 379 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 323 CYCLE_DMA_0_ 3 -1 1 1 1 -1 -1 2 0 21 + 316 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 370 CLK_000_N_SYNC_11_ 3 -1 7 1 0 -1 -1 1 0 21 + 369 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 368 CLK_000_N_SYNC_9_ 3 -1 2 1 7 -1 -1 1 0 21 + 367 CLK_000_N_SYNC_8_ 3 -1 0 1 2 -1 -1 1 0 21 + 366 CLK_000_N_SYNC_7_ 3 -1 0 1 0 -1 -1 1 0 21 + 365 CLK_000_N_SYNC_6_ 3 -1 2 1 0 -1 -1 1 0 21 + 364 CLK_000_N_SYNC_5_ 3 -1 0 1 2 -1 -1 1 0 21 + 363 CLK_000_N_SYNC_4_ 3 -1 1 1 0 -1 -1 1 0 21 + 362 CLK_000_N_SYNC_3_ 3 -1 5 1 1 -1 -1 1 0 21 + 361 CLK_000_N_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21 + 360 CLK_000_N_SYNC_1_ 3 -1 1 1 5 -1 -1 1 0 21 + 359 CLK_000_N_SYNC_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 358 CLK_000_P_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21 + 357 CLK_000_P_SYNC_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 356 CLK_000_P_SYNC_7_ 3 -1 0 1 6 -1 -1 1 0 21 + 355 CLK_000_P_SYNC_6_ 3 -1 6 1 0 -1 -1 1 0 21 + 354 CLK_000_P_SYNC_5_ 3 -1 3 1 6 -1 -1 1 0 21 + 353 CLK_000_P_SYNC_4_ 3 -1 1 1 3 -1 -1 1 0 21 + 352 CLK_000_P_SYNC_3_ 3 -1 5 1 1 -1 -1 1 0 21 + 351 CLK_000_P_SYNC_2_ 3 -1 4 1 5 -1 -1 1 0 21 + 350 CLK_000_P_SYNC_1_ 3 -1 1 1 4 -1 -1 1 0 21 + 349 CLK_000_P_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 340 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 339 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 338 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 333 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 331 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 1 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 5 10 -1 + 309 AHIGH_16_ 1 -1 -1 3 2 4 7 -1 -1 + 308 AHIGH_17_ 1 -1 -1 3 2 4 7 -1 -1 + 307 AHIGH_18_ 1 -1 -1 3 2 4 7 -1 -1 + 306 AHIGH_19_ 1 -1 -1 3 2 4 7 -1 -1 + 301 A_1_ 1 -1 -1 2 2 6 -1 -1 + 305 AHIGH_20_ 1 -1 -1 1 4 -1 -1 + 304 AHIGH_21_ 1 -1 -1 1 4 -1 -1 + 303 AHIGH_22_ 1 -1 -1 1 4 -1 -1 + 302 AHIGH_23_ 1 -1 -1 1 4 -1 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 384 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 389 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 310 A_0_ 5 380 0 1 1 -1 -1 3 0 21 + 302 AHIGH_24_ 5 -1 4 1 4 -1 -1 1 0 21 + 301 AHIGH_25_ 5 -1 7 1 4 -1 -1 1 0 21 + 300 AHIGH_26_ 5 -1 4 1 4 -1 -1 1 0 21 + 299 AHIGH_27_ 5 -1 4 1 4 -1 -1 1 0 21 + 298 AHIGH_28_ 5 -1 7 1 4 -1 -1 1 0 21 + 297 AHIGH_29_ 5 -1 4 1 4 -1 -1 1 0 21 + 296 AHIGH_30_ 5 -1 6 1 4 -1 -1 1 0 21 + 293 AHIGH_31_ 5 -1 6 1 4 -1 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 8 IPL_030_2_ 5 383 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 382 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 381 1 0 6 -1 10 0 21 + 80 DSACK1 5 387 7 0 80 -1 4 0 21 + 82 BGACK_030 5 386 7 0 82 -1 3 0 21 + 34 VMA 5 388 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 385 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 386 RN_BGACK_030 3 82 7 6 0 2 3 4 6 7 82 -1 3 0 21 + 333 inst_RESET_OUT 3 -1 3 6 0 1 3 4 6 7 -1 -1 2 0 21 + 319 inst_nEXP_SPACE_D0reg 3 -1 2 6 0 2 3 4 6 7 -1 -1 1 0 21 + 318 inst_AS_030_D0 3 -1 7 6 2 3 4 5 6 7 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_10_ 3 -1 6 5 0 2 3 5 7 -1 -1 1 0 21 + 378 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 338 SM_AMIGA_5_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21 + 315 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 375 SM_AMIGA_1_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 373 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 3 0 21 + 314 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 311 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 342 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 336 CLK_000_D_0_ 3 -1 5 3 2 3 6 -1 -1 1 0 21 + 331 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 321 inst_BGACK_030_INT_D 3 -1 7 3 0 2 6 -1 -1 1 0 21 + 322 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 376 SM_AMIGA_3_ 3 -1 5 2 2 5 -1 -1 5 0 21 + 345 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 377 SM_AMIGA_2_ 3 -1 5 2 2 5 -1 -1 4 0 21 + 388 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 344 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 330 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 327 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 326 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 343 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 0 2 0 3 -1 -1 2 0 21 + 329 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 317 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 316 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 312 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 372 inst_CLK_000_NE_D0 3 -1 5 2 3 5 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_12_ 3 -1 4 2 3 5 -1 -1 1 0 21 + 335 CLK_000_D_1_ 3 -1 3 2 2 6 -1 -1 1 0 21 + 328 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 + 383 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 382 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 381 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 323 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 374 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 320 inst_AS_030_000_SYNC 3 -1 2 1 2 -1 -1 7 0 21 + 387 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 348 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 313 N_195_i 3 -1 2 1 5 -1 -1 4 0 21 + 384 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 380 RN_A_0_ 3 310 0 1 0 -1 -1 3 0 21 + 347 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 325 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 389 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 385 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 379 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 349 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 324 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 371 CLK_000_N_SYNC_11_ 3 -1 7 1 4 -1 -1 1 0 21 + 370 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 369 CLK_000_N_SYNC_9_ 3 -1 1 1 7 -1 -1 1 0 21 + 368 CLK_000_N_SYNC_8_ 3 -1 0 1 1 -1 -1 1 0 21 + 367 CLK_000_N_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 366 CLK_000_N_SYNC_6_ 3 -1 1 1 5 -1 -1 1 0 21 + 365 CLK_000_N_SYNC_5_ 3 -1 1 1 1 -1 -1 1 0 21 + 364 CLK_000_N_SYNC_4_ 3 -1 3 1 1 -1 -1 1 0 21 + 363 CLK_000_N_SYNC_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 362 CLK_000_N_SYNC_2_ 3 -1 1 1 6 -1 -1 1 0 21 + 361 CLK_000_N_SYNC_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 360 CLK_000_N_SYNC_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 359 CLK_000_P_SYNC_9_ 3 -1 1 1 6 -1 -1 1 0 21 + 358 CLK_000_P_SYNC_8_ 3 -1 5 1 1 -1 -1 1 0 21 + 357 CLK_000_P_SYNC_7_ 3 -1 0 1 5 -1 -1 1 0 21 + 356 CLK_000_P_SYNC_6_ 3 -1 2 1 0 -1 -1 1 0 21 + 355 CLK_000_P_SYNC_5_ 3 -1 6 1 2 -1 -1 1 0 21 + 354 CLK_000_P_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21 + 353 CLK_000_P_SYNC_3_ 3 -1 3 1 1 -1 -1 1 0 21 + 352 CLK_000_P_SYNC_2_ 3 -1 0 1 3 -1 -1 1 0 21 + 351 CLK_000_P_SYNC_1_ 3 -1 0 1 0 -1 -1 1 0 21 + 350 CLK_000_P_SYNC_0_ 3 -1 2 1 0 -1 -1 1 0 21 + 341 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 340 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 339 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 334 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 332 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 2 13 -1 + 10 CLK_000 1 -1 -1 1 5 10 -1 + 309 A_DECODE_16_ 1 -1 -1 3 2 4 7 -1 -1 + 308 A_DECODE_17_ 1 -1 -1 3 2 4 7 -1 -1 + 307 A_DECODE_18_ 1 -1 -1 3 2 4 7 -1 -1 + 306 A_DECODE_19_ 1 -1 -1 3 2 4 7 -1 -1 + 305 A_DECODE_20_ 1 -1 -1 1 4 -1 -1 + 304 A_DECODE_21_ 1 -1 -1 1 4 -1 -1 + 303 A_DECODE_22_ 1 -1 -1 1 4 -1 -1 + 295 A_1_ 1 -1 -1 1 0 -1 -1 + 294 A_DECODE_23_ 1 -1 -1 1 4 -1 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 366 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 371 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A_0_ 5 362 6 1 0 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 365 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21 + 80 DSACK1 5 369 7 0 80 -1 4 0 21 + 82 BGACK_030 5 368 7 0 82 -1 3 0 21 + 34 VMA 5 370 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 367 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 2 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 315 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 319 CLK_000_P_SYNC_10_ 3 -1 1 5 0 1 3 5 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 320 SM_AMIGA_5_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 + 297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 293 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 328 CLK_000_N_SYNC_12_ 3 -1 6 3 1 3 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 327 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 355 SM_AMIGA_6_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 326 SM_AMIGA_4_ 3 -1 1 2 1 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 325 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 324 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 354 inst_CLK_000_NE_D0 3 -1 5 2 3 5 -1 -1 1 0 21 + 318 CLK_000_D_0_ 3 -1 2 2 3 5 -1 -1 1 0 21 + 317 CLK_000_D_1_ 3 -1 5 2 3 5 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21 + 365 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 330 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 295 N_195_i 3 -1 5 1 5 -1 -1 4 0 21 + 366 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 362 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 329 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 371 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 331 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 353 CLK_000_N_SYNC_11_ 3 -1 7 1 6 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_9_ 3 -1 6 1 7 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_8_ 3 -1 2 1 6 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_7_ 3 -1 4 1 2 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_6_ 3 -1 6 1 4 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_5_ 3 -1 2 1 6 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_4_ 3 -1 4 1 2 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_3_ 3 -1 2 1 4 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_2_ 3 -1 1 1 2 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 341 CLK_000_P_SYNC_9_ 3 -1 0 1 1 -1 -1 1 0 21 + 340 CLK_000_P_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21 + 339 CLK_000_P_SYNC_7_ 3 -1 0 1 2 -1 -1 1 0 21 + 338 CLK_000_P_SYNC_6_ 3 -1 0 1 0 -1 -1 1 0 21 + 337 CLK_000_P_SYNC_5_ 3 -1 2 1 0 -1 -1 1 0 21 + 336 CLK_000_P_SYNC_4_ 3 -1 3 1 2 -1 -1 1 0 21 + 335 CLK_000_P_SYNC_3_ 3 -1 6 1 3 -1 -1 1 0 21 + 334 CLK_000_P_SYNC_2_ 3 -1 2 1 6 -1 -1 1 0 21 + 333 CLK_000_P_SYNC_1_ 3 -1 6 1 2 -1 -1 1 0 21 + 332 CLK_000_P_SYNC_0_ 3 -1 3 1 6 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 314 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 59 A_1_ 1 -1 -1 2 1 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 2 13 -1 + 10 CLK_000 1 -1 -1 1 2 10 -1 +150 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 374 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 373 6 2 1 6 68 -1 3 0 21 + 70 RW 5 381 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 372 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 376 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 375 1 0 6 -1 10 0 21 + 80 DSACK1 5 379 7 0 80 -1 4 0 21 + 82 BGACK_030 5 378 7 0 82 -1 3 0 21 + 34 VMA 5 380 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 377 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 7 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 378 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 300 inst_AS_030_D0 3 -1 7 6 0 2 3 4 5 7 -1 -1 1 0 21 + 370 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 321 CLK_000_P_SYNC_10_ 3 -1 6 4 0 3 5 7 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 365 SM_AMIGA_6_ 3 -1 5 3 1 5 6 -1 -1 3 0 21 + 322 SM_AMIGA_5_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 296 cpu_est_0_ 3 -1 2 3 2 3 5 -1 -1 2 0 21 + 338 CLK_000_N_SYNC_12_ 3 -1 6 3 2 3 5 -1 -1 1 0 21 + 320 CLK_000_D_0_ 3 -1 2 3 3 4 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 337 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 380 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 367 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 334 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 364 inst_CLK_000_NE_D0 3 -1 2 2 2 5 -1 -1 1 0 21 + 319 CLK_000_D_1_ 3 -1 4 2 4 5 -1 -1 1 0 21 + 314 CLK_000_D_9_ 3 -1 3 2 2 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21 + 376 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 375 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 372 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 366 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 368 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 379 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 369 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 340 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 293 N_205_i 3 -1 5 1 5 -1 -1 4 0 21 + 374 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 373 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 339 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 336 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 381 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 377 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 371 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 341 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 363 CLK_000_N_SYNC_11_ 3 -1 3 1 6 -1 -1 1 0 21 + 362 CLK_000_N_SYNC_10_ 3 -1 2 1 3 -1 -1 1 0 21 + 361 CLK_000_N_SYNC_9_ 3 -1 1 1 2 -1 -1 1 0 21 + 360 CLK_000_N_SYNC_8_ 3 -1 2 1 1 -1 -1 1 0 21 + 359 CLK_000_N_SYNC_7_ 3 -1 4 1 2 -1 -1 1 0 21 + 358 CLK_000_N_SYNC_6_ 3 -1 6 1 4 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_5_ 3 -1 0 1 6 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_4_ 3 -1 2 1 0 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_3_ 3 -1 6 1 2 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_2_ 3 -1 0 1 6 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_1_ 3 -1 1 1 0 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_0_ 3 -1 4 1 1 -1 -1 1 0 21 + 351 CLK_000_P_SYNC_9_ 3 -1 6 1 6 -1 -1 1 0 21 + 350 CLK_000_P_SYNC_8_ 3 -1 1 1 6 -1 -1 1 0 21 + 349 CLK_000_P_SYNC_7_ 3 -1 1 1 1 -1 -1 1 0 21 + 348 CLK_000_P_SYNC_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_5_ 3 -1 2 1 0 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_4_ 3 -1 6 1 2 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_3_ 3 -1 5 1 6 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_2_ 3 -1 5 1 5 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_1_ 3 -1 2 1 5 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_0_ 3 -1 4 1 2 -1 -1 1 0 21 + 333 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21 + 332 CLK_000_D_8_ 3 -1 3 1 3 -1 -1 1 0 21 + 331 CLK_000_D_7_ 3 -1 3 1 3 -1 -1 1 0 21 + 330 CLK_000_D_6_ 3 -1 3 1 3 -1 -1 1 0 21 + 329 CLK_000_D_5_ 3 -1 3 1 3 -1 -1 1 0 21 + 328 CLK_000_D_4_ 3 -1 6 1 3 -1 -1 1 0 21 + 327 CLK_000_D_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 326 CLK_000_D_2_ 3 -1 4 1 0 -1 -1 1 0 21 + 325 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 324 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 323 IPL_D0_0_ 3 -1 5 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21 + 315 CLK_000_D_10_ 3 -1 2 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 5 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 59 A_1_ 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 7 13 -1 + 10 CLK_000 1 -1 -1 1 2 10 -1 +151 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 374 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 375 6 2 0 6 68 -1 3 0 21 + 70 RW 5 382 6 2 1 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 373 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 377 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 376 1 0 6 -1 10 0 21 + 80 DSACK1 5 380 7 0 80 -1 4 0 21 + 82 BGACK_030 5 379 7 0 82 -1 3 0 21 + 34 VMA 5 381 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 378 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 6 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 379 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 321 CLK_000_P_SYNC_10_ 3 -1 3 6 0 1 3 5 6 7 -1 -1 1 0 21 + 371 SM_AMIGA_i_7_ 3 -1 5 5 1 2 3 5 7 -1 -1 14 0 21 + 300 inst_AS_030_D0 3 -1 7 5 1 2 3 4 7 -1 -1 1 0 21 + 366 SM_AMIGA_6_ 3 -1 5 4 0 1 5 6 -1 -1 3 0 21 + 322 SM_AMIGA_5_ 3 -1 5 4 1 2 5 7 -1 -1 3 0 21 + 335 SM_AMIGA_0_ 3 -1 6 4 1 5 6 7 -1 -1 2 0 21 + 339 CLK_000_N_SYNC_12_ 3 -1 0 4 1 3 5 6 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 368 SM_AMIGA_1_ 3 -1 5 3 5 6 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 320 CLK_000_D_0_ 3 -1 5 3 3 5 6 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 338 inst_DS_000_ENABLE 3 -1 1 2 1 3 -1 -1 5 0 21 + 381 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 337 SM_AMIGA_4_ 3 -1 5 2 1 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 336 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 365 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 319 CLK_000_D_1_ 3 -1 5 2 5 6 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 2 2 3 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21 + 377 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 376 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 373 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 367 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 369 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 380 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 370 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 341 RST_DLY_1_ 3 -1 1 1 1 -1 -1 4 0 21 + 293 N_205_i 3 -1 5 1 5 -1 -1 4 0 21 + 375 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 374 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 340 RST_DLY_0_ 3 -1 1 1 1 -1 -1 3 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 382 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 378 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 372 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 342 RST_DLY_2_ 3 -1 1 1 1 -1 -1 2 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 364 CLK_000_N_SYNC_11_ 3 -1 0 1 0 -1 -1 1 0 21 + 363 CLK_000_N_SYNC_10_ 3 -1 6 1 0 -1 -1 1 0 21 + 362 CLK_000_N_SYNC_9_ 3 -1 4 1 6 -1 -1 1 0 21 + 361 CLK_000_N_SYNC_8_ 3 -1 3 1 4 -1 -1 1 0 21 + 360 CLK_000_N_SYNC_7_ 3 -1 5 1 3 -1 -1 1 0 21 + 359 CLK_000_N_SYNC_6_ 3 -1 2 1 5 -1 -1 1 0 21 + 358 CLK_000_N_SYNC_5_ 3 -1 4 1 2 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_4_ 3 -1 6 1 4 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_2_ 3 -1 3 1 0 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_1_ 3 -1 0 1 3 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_0_ 3 -1 6 1 0 -1 -1 1 0 21 + 352 CLK_000_P_SYNC_9_ 3 -1 6 1 3 -1 -1 1 0 21 + 351 CLK_000_P_SYNC_8_ 3 -1 0 1 6 -1 -1 1 0 21 + 350 CLK_000_P_SYNC_7_ 3 -1 5 1 0 -1 -1 1 0 21 + 349 CLK_000_P_SYNC_6_ 3 -1 7 1 5 -1 -1 1 0 21 + 348 CLK_000_P_SYNC_5_ 3 -1 3 1 7 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_4_ 3 -1 4 1 3 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_3_ 3 -1 6 1 4 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_2_ 3 -1 2 1 6 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_1_ 3 -1 2 1 2 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_0_ 3 -1 5 1 2 -1 -1 1 0 21 + 334 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 333 CLK_000_D_9_ 3 -1 1 1 3 -1 -1 1 0 21 + 332 CLK_000_D_8_ 3 -1 2 1 1 -1 -1 1 0 21 + 331 CLK_000_D_7_ 3 -1 1 1 2 -1 -1 1 0 21 + 330 CLK_000_D_6_ 3 -1 0 1 1 -1 -1 1 0 21 + 329 CLK_000_D_5_ 3 -1 3 1 0 -1 -1 1 0 21 + 328 CLK_000_D_4_ 3 -1 1 1 3 -1 -1 1 0 21 + 327 CLK_000_D_3_ 3 -1 2 1 1 -1 -1 1 0 21 + 326 CLK_000_D_2_ 3 -1 5 1 2 -1 -1 1 0 21 + 325 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 324 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 323 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21 + 315 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21 + 314 CLK_000_D_10_ 3 -1 3 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 59 A_1_ 1 -1 -1 2 2 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 35 VPA 1 -1 -1 1 2 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 5 10 -1 +128 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 79 RW_000 5 352 7 2 4 6 79 -1 5 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 70 RW 5 357 6 1 7 70 -1 2 0 21 + 40 BERR 5 -1 4 1 7 40 -1 1 0 21 + 31 UDS_000 5 -1 3 1 6 31 -1 1 0 21 + 18 AHIGH_24_ 5 -1 -1 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 -1 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 -1 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 -1 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 -1 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 -1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 -1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 -1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 0 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 10 0 21 + 80 DSACK1 0 7 0 80 -1 4 0 21 + 82 BGACK_030 0 7 0 82 -1 3 0 21 + 68 A_0_ 5 358 6 0 68 -1 3 0 21 + 34 VMA 0 3 0 34 -1 3 0 21 + 65 E 0 -1 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 -1 0 33 -1 2 0 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 78 SIZE_1_ 0 -1 0 78 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 69 SIZE_0_ 0 6 0 69 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 -1 0 32 -1 1 0 21 + 30 LDS_000 0 3 0 30 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 -1 0 2 -1 1 0 21 + 354 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 3 0 21 + 318 inst_RESET_OUT 3 -1 -1 5 0 3 4 6 7 -1 -1 2 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 -1 5 0 3 4 6 7 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 -1 3 1 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 -1 3 3 4 7 -1 -1 1 0 21 + 319 CLK_000_D_1_ 3 -1 -1 2 3 7 -1 -1 1 0 21 + 314 CLK_000_D_0_ 3 -1 -1 2 3 7 -1 -1 1 0 21 + 359 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 351 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 350 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 -1 1 0 -1 -1 9 0 21 + 304 inst_AS_000_DMA 3 -1 -1 1 7 -1 -1 7 0 21 + 352 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 336 inst_DS_000_ENABLE 3 -1 -1 1 3 -1 -1 5 0 21 + 355 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 344 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 4 0 21 + 334 SM_AMIGA_0_ 3 -1 -1 1 7 -1 -1 4 0 21 + 321 SM_AMIGA_5_ 3 -1 -1 1 7 -1 -1 4 0 21 + 295 cpu_est_2_ 3 -1 -1 1 3 -1 -1 4 0 21 + 358 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 356 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 -1 1 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 -1 1 6 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 -1 1 6 -1 -1 3 0 21 + 296 cpu_est_3_ 3 -1 -1 1 3 -1 -1 3 0 21 + 294 cpu_est_1_ 3 -1 -1 1 3 -1 -1 3 0 21 + 357 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 353 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 348 CIIN_0 3 -1 -1 1 4 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 -1 1 3 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 -1 1 4 -1 -1 2 0 21 + 297 cpu_est_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 347 SM_AMIGA_i_7_ 3 -1 -1 1 7 -1 -1 1 0 21 + 333 CLK_000_D_12_ 3 -1 -1 1 7 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 -1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 -1 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 -1 1 1 -1 -1 1 0 21 + 316 CLK_000_D_11_ 3 -1 -1 1 7 -1 -1 1 0 21 + 315 CLK_000_D_10_ 3 -1 -1 1 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 -1 1 6 -1 -1 1 0 21 + 349 SM_AMIGA_i_7__0 3 -1 -1 0 -1 -1 11 1 21 + 345 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 8 0 21 + 343 inst_CLK_030_H 3 -1 -1 0 -1 -1 8 0 21 + 302 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 7 0 21 + 346 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 5 0 21 + 342 SM_AMIGA_6_ 3 -1 -1 0 -1 -1 4 0 21 + 338 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 4 0 21 + 306 CYCLE_DMA_0_ 3 -1 -1 0 -1 -1 4 0 21 + 340 RST_DLY_1_ 3 -1 -1 0 -1 -1 3 0 21 + 339 RST_DLY_0_ 3 -1 -1 0 -1 -1 3 1 21 + 341 RST_DLY_2_ 3 -1 -1 0 -1 -1 2 0 21 + 335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 -1 0 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 -1 0 -1 -1 2 0 21 + 293 N_199_i 3 -1 -1 0 -1 -1 2 0 21 + 337 inst_CLK_000_NE_D0 3 -1 -1 0 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 -1 0 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 -1 0 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 -1 0 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 -1 0 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 -1 0 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 -1 0 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 -1 0 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 -1 0 -1 -1 1 0 21 + 320 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 317 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 307 CYCLE_DMA_1_ 3 -1 -1 0 -1 -1 1 1 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 7 10 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 63 CLK_030 1 -1 -1 1 7 63 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 59 A_1_ 1 -1 -1 0 59 -1 + 35 VPA 1 -1 -1 0 35 -1 + 29 DTACK 1 -1 -1 0 29 -1 + 13 nEXP_SPACE 1 -1 -1 0 13 -1 +128 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 79 RW_000 5 352 7 2 4 6 79 -1 5 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 70 RW 5 357 6 1 7 70 -1 2 0 21 + 40 BERR 5 -1 4 1 7 40 -1 1 0 21 + 31 UDS_000 5 -1 3 1 6 31 -1 1 0 21 + 18 AHIGH_24_ 5 -1 -1 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 -1 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 -1 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 -1 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 -1 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 -1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 -1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 -1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 0 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 10 0 21 + 80 DSACK1 0 7 0 80 -1 4 0 21 + 82 BGACK_030 0 7 0 82 -1 3 0 21 + 68 A_0_ 5 358 6 0 68 -1 3 0 21 + 34 VMA 0 3 0 34 -1 3 0 21 + 65 E 0 -1 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 -1 0 33 -1 2 0 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 78 SIZE_1_ 0 -1 0 78 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 69 SIZE_0_ 0 6 0 69 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 -1 0 32 -1 1 0 21 + 30 LDS_000 0 3 0 30 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 -1 0 2 -1 1 0 21 + 354 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 3 0 21 + 318 inst_RESET_OUT 3 -1 -1 5 0 3 4 6 7 -1 -1 2 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 -1 5 0 3 4 6 7 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 -1 3 1 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 -1 3 3 4 7 -1 -1 1 0 21 + 319 CLK_000_D_1_ 3 -1 -1 2 3 7 -1 -1 1 0 21 + 314 CLK_000_D_0_ 3 -1 -1 2 3 7 -1 -1 1 0 21 + 359 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 351 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 350 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 -1 1 0 -1 -1 9 0 21 + 304 inst_AS_000_DMA 3 -1 -1 1 7 -1 -1 7 0 21 + 352 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 336 inst_DS_000_ENABLE 3 -1 -1 1 3 -1 -1 5 0 21 + 355 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 344 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 4 0 21 + 334 SM_AMIGA_0_ 3 -1 -1 1 7 -1 -1 4 0 21 + 321 SM_AMIGA_5_ 3 -1 -1 1 7 -1 -1 4 0 21 + 295 cpu_est_2_ 3 -1 -1 1 3 -1 -1 4 0 21 + 358 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 356 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 -1 1 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 -1 1 6 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 -1 1 6 -1 -1 3 0 21 + 296 cpu_est_3_ 3 -1 -1 1 3 -1 -1 3 0 21 + 294 cpu_est_1_ 3 -1 -1 1 3 -1 -1 3 0 21 + 357 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 353 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 348 CIIN_0 3 -1 -1 1 4 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 -1 1 3 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 -1 1 4 -1 -1 2 0 21 + 297 cpu_est_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 347 SM_AMIGA_i_7_ 3 -1 -1 1 7 -1 -1 1 0 21 + 333 CLK_000_D_12_ 3 -1 -1 1 7 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 -1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 -1 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 -1 1 1 -1 -1 1 0 21 + 316 CLK_000_D_11_ 3 -1 -1 1 7 -1 -1 1 0 21 + 315 CLK_000_D_10_ 3 -1 -1 1 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 -1 1 6 -1 -1 1 0 21 + 349 SM_AMIGA_i_7__0 3 -1 -1 0 -1 -1 11 1 21 + 345 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 8 0 21 + 343 inst_CLK_030_H 3 -1 -1 0 -1 -1 8 0 21 + 302 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 7 0 21 + 346 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 5 0 21 + 342 SM_AMIGA_6_ 3 -1 -1 0 -1 -1 4 0 21 + 338 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 4 0 21 + 306 CYCLE_DMA_0_ 3 -1 -1 0 -1 -1 4 0 21 + 340 RST_DLY_1_ 3 -1 -1 0 -1 -1 3 0 21 + 339 RST_DLY_0_ 3 -1 -1 0 -1 -1 3 1 21 + 341 RST_DLY_2_ 3 -1 -1 0 -1 -1 2 0 21 + 335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 -1 0 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 -1 0 -1 -1 2 0 21 + 293 N_199_i 3 -1 -1 0 -1 -1 2 0 21 + 337 inst_CLK_000_NE_D0 3 -1 -1 0 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 -1 0 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 -1 0 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 -1 0 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 -1 0 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 -1 0 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 -1 0 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 -1 0 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 -1 0 -1 -1 1 0 21 + 320 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 317 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 307 CYCLE_DMA_1_ 3 -1 -1 0 -1 -1 1 1 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 7 10 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 63 CLK_030 1 -1 -1 1 7 63 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 59 A_1_ 1 -1 -1 0 59 -1 + 35 VPA 1 -1 -1 0 35 -1 + 29 DTACK 1 -1 -1 0 29 -1 + 13 nEXP_SPACE 1 -1 -1 0 13 -1 +129 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 2 3 5 7 40 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 1 4 7 41 -1 1 0 21 + 79 RW_000 5 355 7 3 1 4 6 79 -1 4 0 21 + 31 UDS_000 5 -1 3 3 1 2 6 31 -1 1 0 21 + 68 A_0_ 5 351 6 2 2 6 68 -1 3 0 21 + 70 RW 5 360 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 30 LDS_000 5 -1 3 2 1 2 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 6 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 6 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 354 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 353 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 352 1 0 6 -1 10 0 21 + 80 DSACK1 5 358 7 0 80 -1 4 0 21 + 82 BGACK_030 5 357 7 0 82 -1 3 0 21 + 34 VMA 5 359 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 356 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 302 inst_nEXP_SPACE_D0reg 3 -1 1 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 357 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 319 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 301 inst_AS_030_D0 3 -1 4 5 2 3 4 5 7 -1 -1 1 0 21 + 348 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 11 0 21 + 343 SM_AMIGA_6_ 3 -1 5 4 2 3 5 6 -1 -1 3 0 21 + 315 CLK_000_D_0_ 3 -1 7 4 0 3 5 7 -1 -1 1 0 21 + 321 SM_AMIGA_5_ 3 -1 3 3 3 5 7 -1 -1 4 0 21 + 295 cpu_est_2_ 3 -1 6 3 0 3 6 -1 -1 4 0 21 + 310 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 309 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 298 cpu_est_1_ 3 -1 6 3 0 3 6 -1 -1 3 0 21 + 296 cpu_est_3_ 3 -1 0 3 0 3 6 -1 -1 3 0 21 + 297 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 2 0 21 + 338 inst_CLK_000_NE_D0 3 -1 7 3 0 3 6 -1 -1 1 0 21 + 314 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 306 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 + 346 SM_AMIGA_3_ 3 -1 0 2 0 5 -1 -1 8 0 21 + 305 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 + 303 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 337 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 347 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 4 0 21 + 345 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 4 0 21 + 340 RST_DLY_0_ 3 -1 5 2 0 5 -1 -1 4 0 21 + 308 CYCLE_DMA_1_ 3 -1 0 2 0 1 -1 -1 4 0 21 + 359 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 339 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 335 SM_AMIGA_0_ 3 -1 7 2 5 7 -1 -1 3 0 21 + 313 inst_LDS_000_INT 3 -1 6 2 3 6 -1 -1 3 0 21 + 307 CYCLE_DMA_0_ 3 -1 0 2 0 1 -1 -1 3 0 21 + 342 RST_DLY_2_ 3 -1 0 2 0 5 -1 -1 2 0 21 + 341 RST_DLY_1_ 3 -1 0 2 0 5 -1 -1 2 1 21 + 336 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 312 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 299 inst_AS_000_INT 3 -1 5 2 4 5 -1 -1 2 0 21 + 325 CLK_000_D_1_ 3 -1 5 2 3 5 -1 -1 1 0 21 + 317 CLK_000_D_11_ 3 -1 7 2 3 7 -1 -1 1 0 21 + 311 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 + 304 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21 + 354 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 344 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 + 358 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 355 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 350 SM_AMIGA_i_7__0 3 -1 5 1 5 -1 -1 4 0 21 + 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 360 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 356 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 349 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 293 N_146_i 3 -1 0 1 5 -1 -1 2 0 21 + 334 CLK_000_D_12_ 3 -1 3 1 7 -1 -1 1 0 21 + 333 CLK_000_D_9_ 3 -1 5 1 0 -1 -1 1 0 21 + 332 CLK_000_D_8_ 3 -1 6 1 5 -1 -1 1 0 21 + 331 CLK_000_D_7_ 3 -1 4 1 6 -1 -1 1 0 21 + 330 CLK_000_D_6_ 3 -1 6 1 4 -1 -1 1 0 21 + 329 CLK_000_D_5_ 3 -1 6 1 6 -1 -1 1 0 21 + 328 CLK_000_D_4_ 3 -1 6 1 6 -1 -1 1 0 21 + 327 CLK_000_D_3_ 3 -1 3 1 6 -1 -1 1 0 21 + 326 CLK_000_D_2_ 3 -1 3 1 3 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 4 1 1 -1 -1 1 0 21 + 320 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 318 inst_DTACK_D0 3 -1 0 1 0 -1 -1 1 0 21 + 316 CLK_000_D_10_ 3 -1 0 1 7 -1 -1 1 0 21 + 294 N_132_i 3 -1 3 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 10 CLK_000 1 -1 -1 4 0 3 5 7 10 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 4 66 -1 + 63 CLK_030 1 -1 -1 2 1 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 59 A_1_ 1 -1 -1 1 2 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 1 13 -1 +127 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 5 0 1 3 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 5 0 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 351 7 3 1 4 6 79 -1 4 0 21 + 70 RW 5 356 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 1 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 1 6 30 -1 1 0 21 + 68 A_0_ 5 357 6 1 5 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 350 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 349 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 358 1 0 6 -1 10 0 21 + 80 DSACK1 5 354 7 0 80 -1 4 0 21 + 82 BGACK_030 5 353 7 0 82 -1 3 0 21 + 34 VMA 5 355 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 352 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 3 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 353 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 300 inst_AS_030_D0 3 -1 7 6 0 3 4 5 6 7 -1 -1 1 0 21 + 319 CLK_000_D_0_ 3 -1 3 5 0 2 3 5 7 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 0 5 0 2 3 5 7 -1 -1 1 0 21 + 347 SM_AMIGA_i_7_ 3 -1 2 4 0 3 5 7 -1 -1 12 0 21 + 344 SM_AMIGA_1_ 3 -1 0 4 0 2 5 7 -1 -1 3 0 21 + 321 SM_AMIGA_5_ 3 -1 5 4 2 5 6 7 -1 -1 3 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 4 0 1 2 6 -1 -1 1 0 21 + 346 SM_AMIGA_2_ 3 -1 2 3 0 2 5 -1 -1 5 0 21 + 297 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 334 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 1 3 1 6 7 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 305 inst_DS_000_DMA 3 -1 1 2 0 1 -1 -1 9 0 21 + 345 SM_AMIGA_3_ 3 -1 2 2 2 5 -1 -1 8 0 21 + 304 inst_AS_000_DMA 3 -1 1 2 1 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21 + 336 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 307 CYCLE_DMA_1_ 3 -1 3 2 1 3 -1 -1 4 0 21 + 355 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 342 SM_AMIGA_6_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 338 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 CYCLE_DMA_0_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 3 2 2 3 -1 -1 2 0 21 + 337 inst_CLK_000_NE_D0 3 -1 5 2 2 3 -1 -1 1 0 21 + 314 CLK_000_D_10_ 3 -1 5 2 0 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 0 2 2 3 -1 -1 1 0 21 + 358 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 350 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 349 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 343 inst_CLK_030_H 3 -1 1 1 1 -1 -1 8 0 21 + 354 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 351 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 339 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 293 N_206_i 3 -1 5 1 2 -1 -1 4 0 21 + 357 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 356 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 352 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 348 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 341 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 340 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 333 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 6 1 5 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 4 1 6 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 0 1 4 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 4 1 0 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 2 1 4 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 5 1 2 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 0 1 5 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 3 1 0 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 320 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 3 1 2 -1 -1 1 0 21 + 315 CLK_000_D_11_ 3 -1 0 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 63 CLK_030 1 -1 -1 2 1 7 63 -1 + 59 A_1_ 1 -1 -1 2 2 6 59 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 3 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +126 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 352 7 3 2 4 6 79 -1 4 0 21 + 68 A_0_ 5 348 6 2 0 2 68 -1 3 0 21 + 70 RW 5 357 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 30 LDS_000 5 -1 3 1 2 30 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 351 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 350 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 349 1 0 6 -1 10 0 21 + 80 DSACK1 5 355 7 0 80 -1 4 0 21 + 82 BGACK_030 5 354 7 0 82 -1 3 0 21 + 34 VMA 5 356 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 353 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 3 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 354 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 319 CLK_000_D_0_ 3 -1 0 6 0 1 3 4 5 7 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 7 6 0 1 3 4 5 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 6 2 3 4 5 6 7 -1 -1 1 0 21 + 346 SM_AMIGA_i_7_ 3 -1 5 5 1 3 5 6 7 -1 -1 12 0 21 + 341 SM_AMIGA_6_ 3 -1 1 4 0 1 2 5 -1 -1 3 0 21 + 303 inst_BGACK_030_INT_D 3 -1 4 4 0 2 3 6 -1 -1 1 0 21 + 302 inst_AS_030_000_SYNC 3 -1 6 3 1 5 6 -1 -1 7 0 21 + 297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 321 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 305 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 304 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 335 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 2 0 2 -1 -1 4 0 21 + 356 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 343 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 333 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 3 0 21 + 311 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 0 2 0 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 336 inst_CLK_000_NE_D0 3 -1 4 2 3 5 -1 -1 1 0 21 + 315 CLK_000_D_10_ 3 -1 6 2 3 7 -1 -1 1 0 21 + 314 CLK_000_D_9_ 3 -1 1 2 6 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21 + 351 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 350 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 349 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 344 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21 + 342 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 345 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 + 355 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 352 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 338 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 293 N_229_i 3 -1 5 1 5 -1 -1 4 0 21 + 348 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 337 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 + 357 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 353 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 347 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 340 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 339 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 + 334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21 + 332 CLK_000_D_11_ 3 -1 3 1 7 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 1 1 1 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 6 1 1 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 3 1 6 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 1 1 3 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 2 1 1 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 3 1 2 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 7 1 3 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 320 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 6 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 6 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 6 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 6 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 6 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 6 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 59 A_1_ 1 -1 -1 2 0 3 59 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 3 13 -1 + 10 CLK_000 1 -1 -1 1 0 10 -1 +128 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 0 5 6 7 40 -1 1 0 21 + 79 RW_000 5 353 7 3 2 4 6 79 -1 4 0 21 + 70 RW 5 358 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 68 A_0_ 5 359 6 1 2 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 352 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 351 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 350 1 0 6 -1 10 0 21 + 80 DSACK1 5 356 7 0 80 -1 4 0 21 + 82 BGACK_030 5 355 7 0 82 -1 3 0 21 + 34 VMA 5 357 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 354 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 355 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 3 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 317 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 318 CLK_000_D_1_ 3 -1 3 6 0 2 3 4 5 7 -1 -1 1 0 21 + 348 SM_AMIGA_i_7_ 3 -1 5 5 0 3 5 6 7 -1 -1 12 0 21 + 319 CLK_000_D_0_ 3 -1 2 5 0 2 3 5 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 4 5 0 3 4 6 7 -1 -1 1 0 21 + 297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 343 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21 + 335 SM_AMIGA_0_ 3 -1 7 3 0 5 7 -1 -1 3 0 21 + 321 SM_AMIGA_5_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_0_ 3 -1 1 3 1 3 5 -1 -1 2 0 21 + 338 inst_CLK_000_NE_D0 3 -1 7 3 1 3 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21 + 305 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 304 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 6 2 5 6 -1 -1 7 0 21 + 337 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21 + 357 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 345 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 339 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 336 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 320 inst_CLK_OUT_PRE_50 3 -1 4 2 3 4 -1 -1 1 0 21 + 315 CLK_000_D_12_ 3 -1 7 2 1 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 5 2 1 6 -1 -1 1 0 21 + 352 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 351 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 350 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 346 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21 + 344 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 347 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 + 356 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 353 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 340 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 307 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 + 293 N_206_i 3 -1 5 1 5 -1 -1 4 0 21 + 359 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 306 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21 + 358 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 354 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 349 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 342 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 341 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 + 334 CLK_000_D_13_ 3 -1 1 1 7 -1 -1 1 0 21 + 333 CLK_000_D_10_ 3 -1 3 1 4 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 0 1 3 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 2 1 0 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 5 1 2 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 0 1 5 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 0 1 0 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 3 1 0 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 3 1 3 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 4 1 3 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21 + 314 CLK_000_D_11_ 3 -1 4 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 6 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 6 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 6 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 6 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 6 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 6 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A_1_ 1 -1 -1 1 1 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 3 13 -1 + 10 CLK_000 1 -1 -1 1 2 10 -1 +128 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 2 5 6 7 40 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 351 7 3 2 4 6 79 -1 4 0 21 + 68 A_0_ 5 352 6 2 1 5 68 -1 3 0 21 + 70 RW 5 359 6 2 6 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 350 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 354 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 353 1 0 6 -1 10 0 21 + 80 DSACK1 5 357 7 0 80 -1 4 0 21 + 82 BGACK_030 5 356 7 0 82 -1 3 0 21 + 34 VMA 5 358 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 355 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 1 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 356 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 318 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 319 CLK_000_D_0_ 3 -1 3 7 0 2 3 4 5 6 7 -1 -1 1 0 21 + 314 CLK_000_D_1_ 3 -1 4 6 0 2 3 5 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 6 0 2 3 4 6 7 -1 -1 1 0 21 + 348 SM_AMIGA_i_7_ 3 -1 5 5 0 3 5 6 7 -1 -1 12 0 21 + 321 SM_AMIGA_5_ 3 -1 6 4 2 5 6 7 -1 -1 3 0 21 + 303 inst_BGACK_030_INT_D 3 -1 0 4 0 1 3 6 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 343 SM_AMIGA_6_ 3 -1 5 3 1 5 6 -1 -1 3 0 21 + 335 SM_AMIGA_0_ 3 -1 7 3 5 6 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 305 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 304 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21 + 337 inst_DS_000_ENABLE 3 -1 6 2 3 6 -1 -1 5 0 21 + 358 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 345 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 339 SM_AMIGA_4_ 3 -1 5 2 5 6 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 311 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 338 inst_CLK_000_NE_D0 3 -1 7 2 3 5 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 5 2 3 5 -1 -1 1 0 21 + 316 CLK_000_D_12_ 3 -1 4 2 3 7 -1 -1 1 0 21 + 315 CLK_000_D_11_ 3 -1 3 2 4 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 + 354 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 353 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 350 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 346 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21 + 344 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 347 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 + 357 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 351 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 340 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 307 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 + 293 N_331 3 -1 5 1 5 -1 -1 4 0 21 + 352 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 306 CYCLE_DMA_0_ 3 -1 2 1 2 -1 -1 3 0 21 + 359 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 355 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 349 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 342 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 341 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 + 336 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 3 1 3 -1 -1 2 0 21 + 334 CLK_000_D_13_ 3 -1 3 1 7 -1 -1 1 0 21 + 333 CLK_000_D_10_ 3 -1 0 1 3 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 1 1 0 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 2 1 1 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 5 1 2 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 5 1 5 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 1 1 5 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 2 1 1 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 3 1 2 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 0 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 320 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 317 inst_DTACK_D0 3 -1 1 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 59 A_1_ 1 -1 -1 2 1 3 59 -1 + 55 IPL_1_ 1 -1 -1 2 0 1 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 1 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 1 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +127 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 350 7 2 4 6 79 -1 4 0 21 + 70 RW 5 358 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A_0_ 5 351 6 1 0 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 349 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 353 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 352 1 0 6 -1 10 0 21 + 80 DSACK1 5 356 7 0 80 -1 4 0 21 + 82 BGACK_030 5 355 7 0 82 -1 3 0 21 + 34 VMA 5 357 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 354 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 2 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 355 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 318 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 314 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 + 347 SM_AMIGA_i_7_ 3 -1 5 5 1 2 3 5 7 -1 -1 12 0 21 + 319 CLK_000_D_0_ 3 -1 3 5 0 2 3 5 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 4 5 1 2 3 4 7 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 3 0 6 7 -1 -1 7 0 21 + 294 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 342 SM_AMIGA_6_ 3 -1 5 3 0 2 5 -1 -1 3 0 21 + 334 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 321 SM_AMIGA_5_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 305 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 + 343 inst_CLK_030_H 3 -1 0 2 0 6 -1 -1 8 0 21 + 302 inst_AS_030_000_SYNC 3 -1 1 2 1 5 -1 -1 7 0 21 + 336 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 2 0 6 -1 -1 4 0 21 + 357 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 344 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 338 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 3 0 21 + 335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 337 inst_CLK_000_NE_D0 3 -1 2 2 3 5 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 1 2 4 5 -1 -1 1 0 21 + 320 inst_CLK_OUT_PRE_50 3 -1 1 2 1 3 -1 -1 1 0 21 + 315 CLK_000_D_10_ 3 -1 4 2 2 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 + 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 345 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21 + 346 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 + 356 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 339 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 293 N_331 3 -1 5 1 5 -1 -1 4 0 21 + 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 358 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 354 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 348 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 341 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 340 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 333 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 4 1 4 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 5 1 4 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 2 1 5 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 5 1 2 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 6 1 5 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 3 1 6 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 4 1 3 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 317 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 + 316 CLK_000_D_11_ 3 -1 2 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A_1_ 1 -1 -1 1 2 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 2 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +127 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 5 0 1 4 6 7 41 -1 1 0 21 + 40 BERR 5 -1 4 5 0 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 350 7 2 4 6 79 -1 4 0 21 + 70 RW 5 358 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 68 A_0_ 5 351 6 1 5 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 31 UDS_000 5 -1 3 1 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 1 6 30 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 349 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 353 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 352 1 0 6 -1 10 0 21 + 80 DSACK1 5 356 7 0 80 -1 4 0 21 + 82 BGACK_030 5 355 7 0 82 -1 3 0 21 + 34 VMA 5 357 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 354 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 355 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 5 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 318 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 300 inst_AS_030_D0 3 -1 7 6 0 3 4 5 6 7 -1 -1 1 0 21 + 319 CLK_000_D_0_ 3 -1 2 5 0 1 2 3 7 -1 -1 1 0 21 + 314 CLK_000_D_1_ 3 -1 7 5 0 1 2 3 7 -1 -1 1 0 21 + 347 SM_AMIGA_i_7_ 3 -1 2 4 0 3 5 7 -1 -1 12 0 21 + 321 SM_AMIGA_5_ 3 -1 2 4 0 2 6 7 -1 -1 3 0 21 + 302 inst_AS_030_000_SYNC 3 -1 5 3 0 2 5 -1 -1 7 0 21 + 294 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 4 0 21 + 342 SM_AMIGA_6_ 3 -1 0 3 0 2 5 -1 -1 3 0 21 + 334 SM_AMIGA_0_ 3 -1 7 3 0 2 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 2 3 2 3 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 3 3 2 3 6 -1 -1 3 0 21 + 325 CLK_000_D_2_ 3 -1 7 3 0 2 3 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 3 3 1 6 7 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 5 3 1 5 6 -1 -1 1 0 21 + 305 inst_DS_000_DMA 3 -1 6 2 0 6 -1 -1 9 0 21 + 304 inst_AS_000_DMA 3 -1 6 2 6 7 -1 -1 7 0 21 + 336 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21 + 339 RST_DLY_0_ 3 -1 1 2 0 1 -1 -1 4 0 21 + 307 CYCLE_DMA_1_ 3 -1 1 2 1 6 -1 -1 4 0 21 + 357 RN_VMA 3 34 3 2 2 3 34 -1 3 0 21 + 344 SM_AMIGA_1_ 3 -1 2 2 2 7 -1 -1 3 0 21 + 338 SM_AMIGA_4_ 3 -1 2 2 0 2 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 CYCLE_DMA_0_ 3 -1 1 2 1 6 -1 -1 3 0 21 + 341 RST_DLY_2_ 3 -1 0 2 0 1 -1 -1 2 0 21 + 340 RST_DLY_1_ 3 -1 1 2 0 1 -1 -1 2 1 21 + 335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 5 2 3 5 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 5 2 2 5 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 2 2 2 3 -1 -1 2 0 21 + 337 inst_CLK_000_NE_D0 3 -1 7 2 2 3 -1 -1 1 0 21 + 316 CLK_000_D_11_ 3 -1 7 2 0 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 3 2 2 3 -1 -1 1 0 21 + 353 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 352 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 349 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 345 SM_AMIGA_3_ 3 -1 2 1 2 -1 -1 8 0 21 + 343 inst_CLK_030_H 3 -1 6 1 6 -1 -1 8 0 21 + 346 SM_AMIGA_2_ 3 -1 2 1 2 -1 -1 5 0 21 + 356 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 293 N_331 3 -1 2 1 2 -1 -1 4 0 21 + 351 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 358 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 354 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 348 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 333 CLK_000_D_12_ 3 -1 0 1 7 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 3 1 0 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 0 1 3 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 1 1 0 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 5 1 1 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 3 1 5 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 5 1 3 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 3 1 5 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 320 inst_CLK_OUT_PRE_50 3 -1 3 1 3 -1 -1 1 0 21 + 317 inst_DTACK_D0 3 -1 3 1 2 -1 -1 1 0 21 + 315 CLK_000_D_10_ 3 -1 0 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 63 CLK_030 1 -1 -1 2 6 7 63 -1 + 59 A_1_ 1 -1 -1 2 1 5 59 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 5 13 -1 + 10 CLK_000 1 -1 -1 1 2 10 -1 +126 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 350 7 3 0 4 6 79 -1 4 0 21 + 81 AS_030 5 -1 7 3 1 4 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 357 6 2 2 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A_0_ 5 349 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 348 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 352 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 351 1 0 6 -1 10 0 21 + 80 DSACK1 5 355 7 0 80 -1 4 0 21 + 82 BGACK_030 5 354 7 0 82 -1 3 0 21 + 34 VMA 5 356 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 353 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 354 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 2 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 318 inst_RESET_OUT 3 -1 0 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 319 CLK_000_D_0_ 3 -1 3 6 0 2 3 5 6 7 -1 -1 1 0 21 + 314 CLK_000_D_1_ 3 -1 6 6 0 2 3 4 5 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 1 5 2 3 4 6 7 -1 -1 1 0 21 + 346 SM_AMIGA_i_7_ 3 -1 5 4 2 3 6 7 -1 -1 12 0 21 + 341 SM_AMIGA_6_ 3 -1 2 4 0 1 2 5 -1 -1 3 0 21 + 321 SM_AMIGA_5_ 3 -1 0 4 0 2 5 7 -1 -1 3 0 21 + 302 inst_AS_030_000_SYNC 3 -1 6 3 2 5 6 -1 -1 7 0 21 + 294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 333 SM_AMIGA_0_ 3 -1 7 3 2 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 335 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 356 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 343 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 337 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 336 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 4 2 2 5 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 5 2 2 6 -1 -1 1 0 21 + 352 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 351 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 348 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 344 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21 + 342 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 345 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 5 0 21 + 355 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 350 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 338 RST_DLY_0_ 3 -1 0 1 0 -1 -1 4 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 293 N_331 3 -1 5 1 5 -1 -1 4 0 21 + 349 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 357 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 353 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 347 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 340 RST_DLY_2_ 3 -1 0 1 0 -1 -1 2 0 21 + 339 RST_DLY_1_ 3 -1 0 1 0 -1 -1 2 1 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 332 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 3 1 3 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 5 1 3 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 5 1 5 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 1 1 5 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 4 1 1 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 5 1 4 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 320 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 317 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21 + 316 CLK_000_D_10_ 3 -1 7 1 7 -1 -1 1 0 21 + 315 CLK_000_D_9_ 3 -1 3 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 6 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 6 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 6 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 6 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 6 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 6 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A_1_ 1 -1 -1 1 2 59 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 2 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +151 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 374 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 382 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A_0_ 5 375 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 373 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 377 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 376 1 0 6 -1 10 0 21 + 80 DSACK1 5 380 7 0 80 -1 4 0 21 + 82 BGACK_030 5 379 7 0 82 -1 3 0 21 + 34 VMA 5 381 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 378 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 300 inst_nEXP_SPACE_D0reg 3 -1 6 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 379 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 320 CLK_000_P_SYNC_10_ 3 -1 6 5 0 2 3 5 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21 + 321 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 3 0 21 + 371 SM_AMIGA_i_7_ 3 -1 5 3 2 3 7 -1 -1 14 0 21 + 293 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 366 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 334 SM_AMIGA_0_ 3 -1 7 3 2 5 7 -1 -1 2 0 21 + 339 CLK_000_N_SYNC_12_ 3 -1 3 3 3 5 7 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 5 3 1 6 7 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 2 3 1 2 6 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 338 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 381 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 368 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 337 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 365 inst_CLK_000_NE_D0 3 -1 7 2 3 5 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_0_ 3 -1 4 2 2 5 -1 -1 1 0 21 + 319 CLK_000_D_0_ 3 -1 3 2 3 4 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 1 2 3 5 -1 -1 1 0 21 + 377 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 376 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 373 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 367 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 369 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 380 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 370 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 341 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 375 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 374 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 343 N_194_i 3 -1 5 1 5 -1 -1 3 0 21 + 340 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 382 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 378 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 372 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 342 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 364 CLK_000_N_SYNC_11_ 3 -1 2 1 3 -1 -1 1 0 21 + 363 CLK_000_N_SYNC_10_ 3 -1 1 1 2 -1 -1 1 0 21 + 362 CLK_000_N_SYNC_9_ 3 -1 6 1 1 -1 -1 1 0 21 + 361 CLK_000_N_SYNC_8_ 3 -1 3 1 6 -1 -1 1 0 21 + 360 CLK_000_N_SYNC_7_ 3 -1 2 1 3 -1 -1 1 0 21 + 359 CLK_000_N_SYNC_6_ 3 -1 3 1 2 -1 -1 1 0 21 + 358 CLK_000_N_SYNC_5_ 3 -1 2 1 3 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_4_ 3 -1 0 1 2 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_3_ 3 -1 1 1 0 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_1_ 3 -1 5 1 0 -1 -1 1 0 21 + 353 CLK_000_P_SYNC_9_ 3 -1 5 1 6 -1 -1 1 0 21 + 352 CLK_000_P_SYNC_8_ 3 -1 4 1 5 -1 -1 1 0 21 + 351 CLK_000_P_SYNC_7_ 3 -1 0 1 4 -1 -1 1 0 21 + 350 CLK_000_P_SYNC_6_ 3 -1 0 1 0 -1 -1 1 0 21 + 349 CLK_000_P_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21 + 348 CLK_000_P_SYNC_4_ 3 -1 0 1 6 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_3_ 3 -1 6 1 0 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_2_ 3 -1 5 1 6 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_1_ 3 -1 0 1 5 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_0_ 3 -1 4 1 0 -1 -1 1 0 21 + 333 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 2 1 1 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 1 1 2 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 5 1 1 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 6 1 5 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 6 1 6 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 2 1 6 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 5 1 2 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 4 1 5 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 4 1 4 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 5 1 5 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 0 1 5 -1 -1 1 0 21 + 314 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21 + 313 CLK_000_D_10_ 3 -1 1 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 59 A_1_ 1 -1 -1 2 1 2 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 35 VPA 1 -1 -1 1 1 35 -1 + 29 DTACK 1 -1 -1 1 0 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 6 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +141 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 79 RW_000 5 367 7 2 4 6 79 -1 5 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 70 RW 5 372 6 1 7 70 -1 2 0 21 + 40 BERR 5 -1 4 1 7 40 -1 1 0 21 + 31 UDS_000 5 -1 3 1 6 31 -1 1 0 21 + 18 AHIGH_24_ 5 -1 -1 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 -1 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 -1 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 -1 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 -1 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 -1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 -1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 -1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 0 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 10 0 21 + 80 DSACK1 0 7 0 80 -1 4 0 21 + 82 BGACK_030 0 7 0 82 -1 3 0 21 + 68 A_0_ 5 364 6 0 68 -1 3 0 21 + 34 VMA 0 3 0 34 -1 3 0 21 + 65 E 0 -1 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 -1 0 33 -1 2 0 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 78 SIZE_1_ 0 -1 0 78 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 69 SIZE_0_ 0 6 0 69 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 -1 0 32 -1 1 0 21 + 30 LDS_000 0 3 0 30 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 -1 0 2 -1 1 0 21 + 369 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 -1 5 0 3 4 6 7 -1 -1 2 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 -1 5 0 3 4 6 7 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 -1 3 1 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 -1 3 3 4 7 -1 -1 1 0 21 + 319 CLK_000_D_1_ 3 -1 -1 2 3 7 -1 -1 1 0 21 + 318 CLK_000_D_0_ 3 -1 -1 2 3 7 -1 -1 1 0 21 + 366 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 365 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 -1 1 0 -1 -1 9 0 21 + 304 inst_AS_000_DMA 3 -1 -1 1 7 -1 -1 7 0 21 + 367 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 337 inst_DS_000_ENABLE 3 -1 -1 1 3 -1 -1 5 0 21 + 370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 334 SM_AMIGA_0_ 3 -1 -1 1 7 -1 -1 4 0 21 + 297 cpu_est_2_ 3 -1 -1 1 3 -1 -1 4 0 21 + 371 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 364 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 357 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 3 0 21 + 321 SM_AMIGA_5_ 3 -1 -1 1 7 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 -1 1 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 -1 1 6 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 -1 1 6 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 -1 1 3 -1 -1 3 0 21 + 293 cpu_est_3_ 3 -1 -1 1 3 -1 -1 3 0 21 + 372 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 -1 1 4 -1 -1 2 0 21 + 360 SM_AMIGA_i_7_ 3 -1 -1 1 7 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 -1 1 3 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 -1 1 4 -1 -1 2 0 21 + 294 cpu_est_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 338 CLK_000_N_SYNC_12_ 3 -1 -1 1 3 -1 -1 1 0 21 + 333 CLK_000_D_12_ 3 -1 -1 1 7 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 -1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 -1 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 -1 1 1 -1 -1 1 0 21 + 315 CLK_000_D_11_ 3 -1 -1 1 7 -1 -1 1 0 21 + 314 CLK_000_D_10_ 3 -1 -1 1 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 -1 1 6 -1 -1 1 0 21 + 362 SM_AMIGA_i_7__0 3 -1 -1 0 -1 -1 15 0 21 + 356 inst_CLK_030_H 3 -1 -1 0 -1 -1 8 0 21 + 302 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 7 0 21 + 359 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 5 0 21 + 358 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 5 0 21 + 340 RST_DLY_1_ 3 -1 -1 0 -1 -1 4 0 21 + 306 CYCLE_DMA_0_ 3 -1 -1 0 -1 -1 4 0 21 + 355 SM_AMIGA_6_ 3 -1 -1 0 -1 -1 3 1 21 + 353 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 3 1 21 + 339 RST_DLY_0_ 3 -1 -1 0 -1 -1 3 0 21 + 295 N_208_i 3 -1 -1 0 -1 -1 3 0 21 + 341 RST_DLY_2_ 3 -1 -1 0 -1 -1 2 0 21 + 335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 -1 0 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 -1 0 -1 -1 2 0 21 + 354 inst_CLK_000_NE_D0 3 -1 -1 0 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_11_ 3 -1 -1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_10_ 3 -1 -1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_9_ 3 -1 -1 0 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_8_ 3 -1 -1 0 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_7_ 3 -1 -1 0 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_6_ 3 -1 -1 0 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_5_ 3 -1 -1 0 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_4_ 3 -1 -1 0 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_3_ 3 -1 -1 0 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_2_ 3 -1 -1 0 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_1_ 3 -1 -1 0 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_0_ 3 -1 -1 0 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 -1 0 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 -1 0 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 -1 0 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 -1 0 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 -1 0 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 -1 0 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 -1 0 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 -1 0 -1 -1 1 0 21 + 320 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 307 CYCLE_DMA_1_ 3 -1 -1 0 -1 -1 1 1 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 7 10 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 63 CLK_030 1 -1 -1 1 7 63 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 59 A_1_ 1 -1 -1 0 59 -1 + 35 VPA 1 -1 -1 0 35 -1 + 29 DTACK 1 -1 -1 0 29 -1 + 13 nEXP_SPACE 1 -1 -1 0 13 -1 +141 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 79 RW_000 5 367 7 2 4 6 79 -1 5 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 70 RW 5 372 6 1 7 70 -1 2 0 21 + 40 BERR 5 -1 4 1 7 40 -1 1 0 21 + 31 UDS_000 5 -1 3 1 6 31 -1 1 0 21 + 18 AHIGH_24_ 5 -1 -1 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 -1 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 -1 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 -1 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 -1 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 -1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 -1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 -1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 0 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 10 0 21 + 80 DSACK1 0 7 0 80 -1 4 0 21 + 82 BGACK_030 0 7 0 82 -1 3 0 21 + 68 A_0_ 5 364 6 0 68 -1 3 0 21 + 34 VMA 0 3 0 34 -1 3 0 21 + 65 E 0 -1 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 -1 0 33 -1 2 0 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 78 SIZE_1_ 0 -1 0 78 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 69 SIZE_0_ 0 6 0 69 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 -1 0 32 -1 1 0 21 + 30 LDS_000 0 3 0 30 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 -1 0 2 -1 1 0 21 + 369 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 -1 5 0 3 4 6 7 -1 -1 2 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 -1 5 0 3 4 6 7 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 -1 3 1 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 -1 3 3 4 7 -1 -1 1 0 21 + 319 CLK_000_D_1_ 3 -1 -1 2 3 7 -1 -1 1 0 21 + 318 CLK_000_D_0_ 3 -1 -1 2 3 7 -1 -1 1 0 21 + 366 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 365 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 -1 1 0 -1 -1 9 0 21 + 304 inst_AS_000_DMA 3 -1 -1 1 7 -1 -1 7 0 21 + 367 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 337 inst_DS_000_ENABLE 3 -1 -1 1 3 -1 -1 5 0 21 + 370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 334 SM_AMIGA_0_ 3 -1 -1 1 7 -1 -1 4 0 21 + 297 cpu_est_2_ 3 -1 -1 1 3 -1 -1 4 0 21 + 371 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 364 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 357 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 3 0 21 + 321 SM_AMIGA_5_ 3 -1 -1 1 7 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 -1 1 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 -1 1 6 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 -1 1 6 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 -1 1 3 -1 -1 3 0 21 + 293 cpu_est_3_ 3 -1 -1 1 3 -1 -1 3 0 21 + 372 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 -1 1 4 -1 -1 2 0 21 + 360 SM_AMIGA_i_7_ 3 -1 -1 1 7 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 -1 1 3 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 -1 1 4 -1 -1 2 0 21 + 294 cpu_est_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 338 CLK_000_N_SYNC_12_ 3 -1 -1 1 3 -1 -1 1 0 21 + 333 CLK_000_D_12_ 3 -1 -1 1 7 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 -1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 -1 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 -1 1 1 -1 -1 1 0 21 + 315 CLK_000_D_11_ 3 -1 -1 1 7 -1 -1 1 0 21 + 314 CLK_000_D_10_ 3 -1 -1 1 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 -1 1 6 -1 -1 1 0 21 + 362 SM_AMIGA_i_7__0 3 -1 -1 0 -1 -1 15 0 21 + 356 inst_CLK_030_H 3 -1 -1 0 -1 -1 8 0 21 + 302 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 7 0 21 + 359 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 5 0 21 + 358 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 5 0 21 + 340 RST_DLY_1_ 3 -1 -1 0 -1 -1 4 0 21 + 306 CYCLE_DMA_0_ 3 -1 -1 0 -1 -1 4 0 21 + 355 SM_AMIGA_6_ 3 -1 -1 0 -1 -1 3 1 21 + 353 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 3 1 21 + 339 RST_DLY_0_ 3 -1 -1 0 -1 -1 3 0 21 + 295 N_208_i 3 -1 -1 0 -1 -1 3 0 21 + 341 RST_DLY_2_ 3 -1 -1 0 -1 -1 2 0 21 + 335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 -1 0 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 -1 0 -1 -1 2 0 21 + 354 inst_CLK_000_NE_D0 3 -1 -1 0 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_11_ 3 -1 -1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_10_ 3 -1 -1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_9_ 3 -1 -1 0 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_8_ 3 -1 -1 0 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_7_ 3 -1 -1 0 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_6_ 3 -1 -1 0 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_5_ 3 -1 -1 0 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_4_ 3 -1 -1 0 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_3_ 3 -1 -1 0 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_2_ 3 -1 -1 0 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_1_ 3 -1 -1 0 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_0_ 3 -1 -1 0 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 -1 0 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 -1 0 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 -1 0 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 -1 0 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 -1 0 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 -1 0 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 -1 0 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 -1 0 -1 -1 1 0 21 + 320 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 307 CYCLE_DMA_1_ 3 -1 -1 0 -1 -1 1 1 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 7 10 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 63 CLK_030 1 -1 -1 1 7 63 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 59 A_1_ 1 -1 -1 0 59 -1 + 35 VPA 1 -1 -1 0 35 -1 + 29 DTACK 1 -1 -1 0 29 -1 + 13 nEXP_SPACE 1 -1 -1 0 13 -1 +141 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 367 7 3 2 4 6 79 -1 4 0 21 + 70 RW 5 372 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 68 A_0_ 5 363 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 366 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 365 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 364 1 0 6 -1 10 0 21 + 80 DSACK1 5 370 7 0 80 -1 4 0 21 + 82 BGACK_030 5 369 7 0 82 -1 3 0 21 + 34 VMA 5 371 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 368 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 369 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 300 inst_nEXP_SPACE_D0reg 3 -1 0 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 316 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 317 CLK_000_D_0_ 3 -1 4 6 0 2 3 4 5 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 11 0 21 + 354 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 4 0 21 + 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 356 SM_AMIGA_1_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 + 319 SM_AMIGA_5_ 3 -1 5 3 1 5 7 -1 -1 3 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 3 0 21 + 293 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 3 0 21 + 353 inst_CLK_000_NE_D0 3 -1 5 3 0 3 5 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_12_ 3 -1 0 3 0 3 5 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_0_ 3 -1 5 3 2 4 5 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21 + 304 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 303 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21 + 358 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 + 357 SM_AMIGA_3_ 3 -1 0 2 0 5 -1 -1 5 0 21 + 336 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 352 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 4 0 21 + 371 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 333 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 3 0 21 + 334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 2 0 21 + 309 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 3 2 5 6 -1 -1 1 0 21 + 366 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 365 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 364 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 355 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 367 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 339 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 306 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 + 363 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 362 SM_AMIGA_i_7__0 3 -1 5 1 5 -1 -1 3 0 21 + 338 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 372 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 359 N_162_i 3 -1 0 1 5 -1 -1 2 0 21 + 340 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 351 CLK_000_N_SYNC_11_ 3 -1 1 1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_10_ 3 -1 0 1 1 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_8_ 3 -1 2 1 6 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_7_ 3 -1 0 1 2 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_6_ 3 -1 1 1 0 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_5_ 3 -1 3 1 1 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_4_ 3 -1 6 1 3 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_3_ 3 -1 5 1 6 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_2_ 3 -1 2 1 5 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_1_ 3 -1 4 1 2 -1 -1 1 0 21 + 332 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 331 CLK_000_D_9_ 3 -1 1 1 0 -1 -1 1 0 21 + 330 CLK_000_D_8_ 3 -1 2 1 1 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 4 1 2 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 3 1 4 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 6 1 3 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 6 1 6 -1 -1 1 0 21 + 325 CLK_000_D_3_ 3 -1 1 1 6 -1 -1 1 0 21 + 324 CLK_000_D_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 323 CLK_000_D_1_ 3 -1 4 1 5 -1 -1 1 0 21 + 322 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 320 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21 + 314 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21 + 313 CLK_000_D_10_ 3 -1 0 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 10 CLK_000 1 -1 -1 6 0 2 3 4 5 7 10 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 0 1 5 7 40 -1 1 0 21 + 79 RW_000 5 363 7 3 2 4 6 79 -1 4 0 21 + 68 A_0_ 5 369 6 2 2 6 68 -1 3 0 21 + 70 RW 5 368 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 371 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 370 1 0 6 -1 10 0 21 + 80 DSACK1 5 366 7 0 80 -1 4 0 21 + 82 BGACK_030 5 365 7 0 82 -1 3 0 21 + 34 VMA 5 367 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 364 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 0 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 365 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 320 CLK_000_D_0_ 3 -1 3 6 0 1 2 3 5 7 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 4 0 3 5 7 -1 -1 15 0 21 + 355 SM_AMIGA_6_ 3 -1 5 4 0 2 5 6 -1 -1 3 0 21 + 338 CLK_000_N_SYNC_12_ 3 -1 6 4 0 1 3 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 4 0 1 2 6 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 308 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 293 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 357 SM_AMIGA_1_ 3 -1 1 3 1 5 7 -1 -1 2 0 21 + 321 SM_AMIGA_5_ 3 -1 0 3 0 5 7 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 305 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 304 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21 + 337 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 359 SM_AMIGA_2_ 3 -1 5 2 1 5 -1 -1 4 0 21 + 367 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 334 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 315 CLK_000_D_11_ 3 -1 5 2 0 7 -1 -1 1 0 21 + 314 CLK_000_D_10_ 3 -1 0 2 5 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21 + 371 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 370 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21 + 356 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 366 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 363 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 340 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 307 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 + 369 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 353 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 + 339 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 368 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 364 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 341 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 298 pos_clk_un23_clk_000_ne_d0_i_n 3 -1 5 1 5 -1 -1 2 0 21 + 354 inst_CLK_000_NE_D0 3 -1 5 1 5 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_11_ 3 -1 3 1 6 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_10_ 3 -1 2 1 3 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_9_ 3 -1 4 1 2 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_8_ 3 -1 1 1 4 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_7_ 3 -1 2 1 1 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_6_ 3 -1 5 1 2 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_5_ 3 -1 1 1 5 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_4_ 3 -1 6 1 1 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_2_ 3 -1 3 1 0 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_1_ 3 -1 5 1 3 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_0_ 3 -1 7 1 5 -1 -1 1 0 21 + 333 CLK_000_D_12_ 3 -1 0 1 7 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 0 1 0 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 6 1 0 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 1 1 6 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 4 1 1 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 1 1 4 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 6 1 1 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 0 1 0 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 59 A_1_ 1 -1 -1 2 1 2 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +141 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 367 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 363 6 2 1 2 68 -1 3 0 21 + 70 RW 5 372 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 366 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 365 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 364 1 0 6 -1 10 0 21 + 80 DSACK1 5 370 7 0 80 -1 4 0 21 + 82 BGACK_030 5 369 7 0 82 -1 3 0 21 + 34 VMA 5 371 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 368 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 369 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 300 inst_nEXP_SPACE_D0reg 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 1 0 21 + 320 CLK_000_D_0_ 3 -1 3 5 0 2 3 5 7 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 3 5 0 2 3 5 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 4 0 2 3 7 -1 -1 15 0 21 + 351 SM_AMIGA_6_ 3 -1 2 4 1 2 5 7 -1 -1 3 0 21 + 301 inst_AS_030_000_SYNC 3 -1 0 3 0 1 2 -1 -1 7 0 21 + 296 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 352 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 0 3 0 6 7 -1 -1 3 0 21 + 295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 293 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 336 CLK_000_N_SYNC_12_ 3 -1 1 3 1 3 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 335 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 338 RST_DLY_1_ 3 -1 1 2 1 3 -1 -1 4 0 21 + 371 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 353 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 337 RST_DLY_0_ 3 -1 3 2 1 3 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 357 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 0 21 + 355 SM_AMIGA_5_ 3 -1 5 2 2 5 -1 -1 2 0 21 + 339 RST_DLY_2_ 3 -1 3 2 1 3 -1 -1 2 0 21 + 333 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 334 CLK_000_N_SYNC_0_ 3 -1 0 2 1 2 -1 -1 1 0 21 + 315 CLK_000_D_11_ 3 -1 7 2 4 7 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 2 0 6 -1 -1 1 0 21 + 366 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 365 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 364 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21 + 356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 367 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 363 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 372 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 362 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 361 N_256 3 -1 3 1 5 -1 -1 1 0 21 + 354 inst_CLK_000_NE_D0 3 -1 5 1 5 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_11_ 3 -1 6 1 1 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_10_ 3 -1 5 1 6 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_9_ 3 -1 3 1 5 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_8_ 3 -1 1 1 3 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_7_ 3 -1 6 1 1 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_6_ 3 -1 6 1 6 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_5_ 3 -1 0 1 6 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_4_ 3 -1 4 1 0 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_3_ 3 -1 2 1 4 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_2_ 3 -1 4 1 2 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_1_ 3 -1 1 1 4 -1 -1 1 0 21 + 332 CLK_000_D_12_ 3 -1 4 1 7 -1 -1 1 0 21 + 331 CLK_000_D_9_ 3 -1 6 1 6 -1 -1 1 0 21 + 330 CLK_000_D_8_ 3 -1 5 1 6 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 5 1 5 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 3 1 5 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 6 1 3 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 5 1 6 -1 -1 1 0 21 + 325 CLK_000_D_3_ 3 -1 2 1 5 -1 -1 1 0 21 + 324 CLK_000_D_2_ 3 -1 2 1 2 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 2 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 0 1 1 -1 -1 1 0 21 + 319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 + 314 CLK_000_D_10_ 3 -1 6 1 7 -1 -1 1 0 21 + 311 N_145_0 3 -1 1 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 0 1 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 2 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 3 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +141 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 4 0 4 6 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 367 7 3 0 4 6 79 -1 4 0 21 + 70 RW 5 372 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A_0_ 5 363 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 366 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 365 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 364 1 0 6 -1 10 0 21 + 80 DSACK1 5 370 7 0 80 -1 4 0 21 + 82 BGACK_030 5 369 7 0 82 -1 3 0 21 + 34 VMA 5 371 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 368 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 369 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 300 inst_nEXP_SPACE_D0reg 3 -1 1 7 0 1 2 3 4 6 7 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 7 6 0 2 3 4 5 7 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 5 0 2 3 5 7 -1 -1 15 0 21 + 333 SM_AMIGA_6_ 3 -1 0 5 0 1 2 5 7 -1 -1 3 0 21 + 320 CLK_000_D_0_ 3 -1 2 5 0 2 3 5 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 5 2 3 4 5 7 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 6 3 0 6 7 -1 -1 7 0 21 + 296 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 293 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 337 CLK_000_N_SYNC_12_ 3 -1 2 3 3 5 6 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_0_ 3 -1 7 3 0 2 3 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 6 3 1 2 6 -1 -1 1 0 21 + 301 inst_AS_030_000_SYNC 3 -1 2 2 0 2 -1 -1 7 0 21 + 336 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 2 0 6 -1 -1 4 0 21 + 371 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 2 0 6 -1 -1 3 0 21 + 356 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 0 21 + 334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 314 CLK_000_D_10_ 3 -1 6 2 0 7 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 + 366 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 365 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 364 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21 + 355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 367 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 359 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 339 RST_DLY_1_ 3 -1 6 1 6 -1 -1 4 0 21 + 363 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 357 SM_AMIGA_0_ 3 -1 5 1 5 -1 -1 3 0 21 + 352 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 + 338 RST_DLY_0_ 3 -1 6 1 6 -1 -1 3 0 21 + 372 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 362 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 354 SM_AMIGA_5_ 3 -1 5 1 5 -1 -1 2 0 21 + 340 RST_DLY_2_ 3 -1 6 1 6 -1 -1 2 0 21 + 361 N_245 3 -1 3 1 5 -1 -1 1 0 21 + 353 inst_CLK_000_NE_D0 3 -1 5 1 5 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_11_ 3 -1 5 1 2 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_10_ 3 -1 2 1 5 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_9_ 3 -1 2 1 2 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_8_ 3 -1 0 1 2 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_7_ 3 -1 2 1 0 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_6_ 3 -1 4 1 2 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_5_ 3 -1 6 1 4 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_4_ 3 -1 3 1 6 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_3_ 3 -1 0 1 3 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_2_ 3 -1 0 1 0 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_1_ 3 -1 3 1 0 -1 -1 1 0 21 + 332 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 331 CLK_000_D_9_ 3 -1 3 1 6 -1 -1 1 0 21 + 330 CLK_000_D_8_ 3 -1 2 1 3 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 3 1 2 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 1 1 3 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 4 1 1 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 3 1 4 -1 -1 1 0 21 + 325 CLK_000_D_3_ 3 -1 5 1 3 -1 -1 1 0 21 + 324 CLK_000_D_2_ 3 -1 4 1 5 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 3 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 + 315 CLK_000_D_11_ 3 -1 0 1 7 -1 -1 1 0 21 + 310 N_132_0 3 -1 2 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 63 CLK_030 1 -1 -1 3 0 6 7 63 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 55 IPL_1_ 1 -1 -1 2 1 3 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A_1_ 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 1 13 -1 + 10 CLK_000 1 -1 -1 1 2 10 -1 +141 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 + 41 AS_000 5 -1 4 4 0 2 4 7 41 -1 1 0 21 + 79 RW_000 5 367 7 3 2 4 6 79 -1 4 0 21 + 70 RW 5 372 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 68 A_0_ 5 363 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 366 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 365 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 364 1 0 6 -1 10 0 21 + 80 DSACK1 5 370 7 0 80 -1 4 0 21 + 82 BGACK_030 5 369 7 0 82 -1 3 0 21 + 34 VMA 5 371 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 368 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 369 RN_BGACK_030 3 82 7 8 0 1 2 3 4 5 6 7 82 -1 3 0 21 + 300 inst_nEXP_SPACE_D0reg 3 -1 0 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 316 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 317 CLK_000_D_0_ 3 -1 4 6 0 2 3 4 5 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 7 5 1 3 4 5 7 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 11 0 21 + 354 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 4 0 21 + 296 cpu_est_2_ 3 -1 0 3 0 3 6 -1 -1 4 0 21 + 356 SM_AMIGA_1_ 3 -1 0 3 0 5 7 -1 -1 3 0 21 + 319 SM_AMIGA_5_ 3 -1 5 3 1 5 7 -1 -1 3 0 21 + 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 3 0 21 + 293 cpu_est_3_ 3 -1 3 3 0 3 6 -1 -1 3 0 21 + 353 inst_CLK_000_NE_D0 3 -1 5 3 0 3 5 -1 -1 1 0 21 + 337 CLK_000_N_SYNC_12_ 3 -1 0 3 0 3 5 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_0_ 3 -1 5 3 2 4 5 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 0 3 1 6 7 -1 -1 1 0 21 + 304 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 303 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 5 2 2 5 -1 -1 7 0 21 + 358 SM_AMIGA_2_ 3 -1 0 2 0 5 -1 -1 5 0 21 + 357 SM_AMIGA_3_ 3 -1 0 2 0 5 -1 -1 5 0 21 + 336 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 352 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 4 0 21 + 371 RN_VMA 3 34 3 2 0 3 34 -1 3 0 21 + 333 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 2 0 2 -1 -1 3 0 21 + 334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 6 2 2 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 1 2 1 4 -1 -1 2 0 21 + 294 cpu_est_0_ 3 -1 3 2 0 3 -1 -1 2 0 21 + 309 inst_VPA_D 3 -1 6 2 0 3 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 3 2 5 6 -1 -1 1 0 21 + 366 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 365 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 364 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 355 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 370 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 367 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 339 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 306 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 + 363 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 362 SM_AMIGA_i_7__0 3 -1 5 1 5 -1 -1 3 0 21 + 338 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 372 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 368 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 359 N_162_i 3 -1 0 1 5 -1 -1 2 0 21 + 340 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 351 CLK_000_N_SYNC_11_ 3 -1 1 1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_10_ 3 -1 0 1 1 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_9_ 3 -1 6 1 0 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_8_ 3 -1 2 1 6 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_7_ 3 -1 0 1 2 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_6_ 3 -1 1 1 0 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_5_ 3 -1 3 1 1 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_4_ 3 -1 6 1 3 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_3_ 3 -1 5 1 6 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_2_ 3 -1 2 1 5 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_1_ 3 -1 4 1 2 -1 -1 1 0 21 + 332 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 331 CLK_000_D_9_ 3 -1 1 1 0 -1 -1 1 0 21 + 330 CLK_000_D_8_ 3 -1 2 1 1 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 4 1 2 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 3 1 4 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 6 1 3 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 6 1 6 -1 -1 1 0 21 + 325 CLK_000_D_3_ 3 -1 1 1 6 -1 -1 1 0 21 + 324 CLK_000_D_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 323 CLK_000_D_1_ 3 -1 4 1 5 -1 -1 1 0 21 + 322 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 320 IPL_D0_0_ 3 -1 2 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 0 1 0 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 2 1 0 -1 -1 1 0 21 + 314 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21 + 313 CLK_000_D_10_ 3 -1 0 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 10 CLK_000 1 -1 -1 6 0 2 3 4 5 7 10 -1 + 96 A_DECODE_19_ 1 -1 -1 3 4 5 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 4 5 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 4 5 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 4 5 7 58 -1 + 57 FC_1_ 1 -1 -1 3 4 5 7 57 -1 + 56 FC_0_ 1 -1 -1 3 4 5 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 2 66 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 59 A_1_ 1 -1 -1 1 6 59 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 5 0 1 2 4 7 41 -1 1 0 21 + 40 BERR 5 -1 4 4 0 1 5 7 40 -1 1 0 21 + 79 RW_000 5 363 7 3 2 4 6 79 -1 4 0 21 + 68 A_0_ 5 369 6 2 2 6 68 -1 3 0 21 + 70 RW 5 368 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 2 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 2 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 2 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 2 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 362 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 371 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 370 1 0 6 -1 10 0 21 + 80 DSACK1 5 366 7 0 80 -1 4 0 21 + 82 BGACK_030 5 365 7 0 82 -1 3 0 21 + 34 VMA 5 367 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 364 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 0 8 0 1 2 3 4 5 6 7 -1 -1 1 0 21 + 365 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 320 CLK_000_D_0_ 3 -1 3 6 0 1 2 3 5 7 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 7 6 0 1 2 3 5 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 4 5 0 3 4 5 7 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 4 0 3 5 7 -1 -1 15 0 21 + 355 SM_AMIGA_6_ 3 -1 5 4 0 2 5 6 -1 -1 3 0 21 + 338 CLK_000_N_SYNC_12_ 3 -1 6 4 0 1 3 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 4 0 1 2 6 -1 -1 1 0 21 + 296 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 308 SIZE_DMA_0_ 3 -1 2 3 2 6 7 -1 -1 3 0 21 + 295 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 293 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 357 SM_AMIGA_1_ 3 -1 1 3 1 5 7 -1 -1 2 0 21 + 321 SM_AMIGA_5_ 3 -1 0 3 0 5 7 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 305 inst_DS_000_DMA 3 -1 2 2 0 2 -1 -1 9 0 21 + 304 inst_AS_000_DMA 3 -1 2 2 2 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 0 2 0 5 -1 -1 7 0 21 + 337 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 359 SM_AMIGA_2_ 3 -1 5 2 1 5 -1 -1 4 0 21 + 367 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 334 SM_AMIGA_0_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 2 2 2 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 306 CYCLE_DMA_0_ 3 -1 1 2 1 2 -1 -1 3 0 21 + 335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 6 2 3 6 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 0 2 0 4 -1 -1 2 0 21 + 294 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 315 CLK_000_D_11_ 3 -1 5 2 0 7 -1 -1 1 0 21 + 314 CLK_000_D_10_ 3 -1 0 2 5 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21 + 371 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 370 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 358 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21 + 356 inst_CLK_030_H 3 -1 2 1 2 -1 -1 8 0 21 + 366 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 363 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 340 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 307 CYCLE_DMA_1_ 3 -1 2 1 2 -1 -1 4 0 21 + 369 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 353 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 + 339 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 368 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 364 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 341 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 298 pos_clk_un23_clk_000_ne_d0_i_n 3 -1 5 1 5 -1 -1 2 0 21 + 354 inst_CLK_000_NE_D0 3 -1 5 1 5 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_11_ 3 -1 3 1 6 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_10_ 3 -1 2 1 3 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_9_ 3 -1 4 1 2 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_8_ 3 -1 1 1 4 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_7_ 3 -1 2 1 1 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_6_ 3 -1 5 1 2 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_5_ 3 -1 1 1 5 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_4_ 3 -1 6 1 1 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_2_ 3 -1 3 1 0 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_1_ 3 -1 5 1 3 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_0_ 3 -1 7 1 5 -1 -1 1 0 21 + 333 CLK_000_D_12_ 3 -1 0 1 7 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 0 1 0 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 6 1 0 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 1 1 6 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 4 1 1 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 1 1 4 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 6 1 1 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 0 1 0 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 8 0 1 2 3 4 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 6 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 2 7 63 -1 + 59 A_1_ 1 -1 -1 2 1 2 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 13 nEXP_SPACE 1 -1 -1 1 0 13 -1 + 10 CLK_000 1 -1 -1 1 3 10 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 1 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 366 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 362 6 2 0 5 68 -1 3 0 21 + 70 RW 5 371 6 2 2 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 5 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 5 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 365 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 364 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 363 1 0 6 -1 10 0 21 + 80 DSACK1 5 369 7 0 80 -1 4 0 21 + 82 BGACK_030 5 368 7 0 82 -1 3 0 21 + 34 VMA 5 370 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 367 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 368 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 301 inst_nEXP_SPACE_D0reg 3 -1 6 7 0 1 2 3 4 6 7 -1 -1 1 0 21 + 320 CLK_000_D_0_ 3 -1 6 6 0 2 3 4 5 7 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 4 6 0 2 3 4 5 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 6 1 2 3 4 6 7 -1 -1 1 0 21 + 360 SM_AMIGA_i_7_ 3 -1 5 4 1 2 3 7 -1 -1 15 0 21 + 321 SM_AMIGA_5_ 3 -1 2 4 2 5 6 7 -1 -1 2 0 21 + 338 CLK_000_N_SYNC_12_ 3 -1 6 4 1 2 3 5 -1 -1 1 0 21 + 297 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 355 SM_AMIGA_6_ 3 -1 2 3 0 2 5 -1 -1 3 0 21 + 334 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 3 3 3 5 6 -1 -1 3 0 21 + 357 SM_AMIGA_1_ 3 -1 5 3 2 5 7 -1 -1 2 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 2 3 1 6 7 -1 -1 1 0 21 + 358 SM_AMIGA_3_ 3 -1 5 2 2 5 -1 -1 8 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 1 2 1 2 -1 -1 7 0 21 + 337 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 359 SM_AMIGA_2_ 3 -1 5 2 2 5 -1 -1 4 0 21 + 370 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 353 SM_AMIGA_4_ 3 -1 2 2 2 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 5 2 3 5 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 335 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 0 2 0 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 354 inst_CLK_000_NE_D0 3 -1 1 2 3 5 -1 -1 1 0 21 + 336 CLK_000_N_SYNC_0_ 3 -1 4 2 2 3 -1 -1 1 0 21 + 319 inst_CLK_OUT_PRE_50 3 -1 4 2 2 4 -1 -1 1 0 21 + 315 CLK_000_D_11_ 3 -1 7 2 6 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 3 2 3 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 2 1 6 -1 -1 1 0 21 + 365 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 364 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 363 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 356 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 369 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 366 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 340 RST_DLY_1_ 3 -1 2 1 2 -1 -1 4 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 362 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 339 RST_DLY_0_ 3 -1 2 1 2 -1 -1 3 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 293 N_199_i 3 -1 2 1 5 -1 -1 3 0 21 + 371 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 367 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 361 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 341 RST_DLY_2_ 3 -1 2 1 2 -1 -1 2 0 21 + 352 CLK_000_N_SYNC_11_ 3 -1 4 1 6 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_10_ 3 -1 0 1 4 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_9_ 3 -1 3 1 0 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_8_ 3 -1 0 1 3 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_7_ 3 -1 3 1 0 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_6_ 3 -1 0 1 3 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_5_ 3 -1 1 1 0 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_4_ 3 -1 6 1 1 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_3_ 3 -1 0 1 6 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_2_ 3 -1 0 1 0 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_1_ 3 -1 3 1 0 -1 -1 1 0 21 + 333 CLK_000_D_12_ 3 -1 6 1 7 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 1 1 6 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 3 1 1 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 5 1 3 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 1 1 5 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 0 1 1 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 0 1 0 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 5 1 0 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 4 1 5 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 0 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 + 314 CLK_000_D_10_ 3 -1 6 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 1 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 1 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 1 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 1 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 1 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 1 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 0 1 67 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 13 nEXP_SPACE 1 -1 -1 2 1 6 13 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A_1_ 1 -1 -1 1 1 59 -1 + 35 VPA 1 -1 -1 1 3 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 6 10 -1 +139 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 362 7 3 0 4 6 79 -1 4 0 21 + 81 AS_030 5 -1 7 3 1 4 7 81 -1 1 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 368 6 2 1 2 68 -1 3 0 21 + 70 RW 5 367 6 2 2 7 70 -1 2 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 361 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 370 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 369 1 0 6 -1 10 0 21 + 80 DSACK1 5 365 7 0 80 -1 4 0 21 + 82 BGACK_030 5 364 7 0 82 -1 3 0 21 + 34 VMA 5 366 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 363 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 364 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 317 CLK_000_D_1_ 3 -1 2 6 0 2 3 5 6 7 -1 -1 1 0 21 + 319 CLK_000_D_0_ 3 -1 1 5 0 2 3 5 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 1 5 0 2 3 4 7 -1 -1 1 0 21 + 359 SM_AMIGA_i_7_ 3 -1 5 4 0 2 3 7 -1 -1 15 0 21 + 297 cpu_est_2_ 3 -1 3 3 3 5 6 -1 -1 4 0 21 + 354 SM_AMIGA_6_ 3 -1 2 3 1 2 5 -1 -1 3 0 21 + 333 SM_AMIGA_0_ 3 -1 5 3 2 5 7 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 356 SM_AMIGA_1_ 3 -1 2 3 2 5 7 -1 -1 2 0 21 + 320 SM_AMIGA_5_ 3 -1 2 3 2 5 7 -1 -1 2 0 21 + 337 CLK_000_N_SYNC_12_ 3 -1 6 3 2 3 5 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 3 0 1 6 -1 -1 1 0 21 + 357 SM_AMIGA_3_ 3 -1 5 2 2 5 -1 -1 8 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 0 2 0 2 -1 -1 7 0 21 + 336 inst_DS_000_ENABLE 3 -1 2 2 2 3 -1 -1 5 0 21 + 358 SM_AMIGA_2_ 3 -1 5 2 2 5 -1 -1 4 0 21 + 366 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 352 SM_AMIGA_4_ 3 -1 5 2 2 5 -1 -1 3 0 21 + 311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 1 2 1 3 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 2 2 2 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 3 2 3 5 -1 -1 2 0 21 + 353 inst_CLK_000_NE_D0 3 -1 3 2 3 5 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 + 370 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 369 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 361 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 365 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 362 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 339 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 368 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 338 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 293 N_296_i 3 -1 2 1 5 -1 -1 3 0 21 + 367 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 363 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 360 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 340 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 351 CLK_000_N_SYNC_11_ 3 -1 5 1 6 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_10_ 3 -1 6 1 5 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_9_ 3 -1 2 1 6 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_8_ 3 -1 5 1 2 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_7_ 3 -1 3 1 5 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_6_ 3 -1 0 1 3 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_5_ 3 -1 6 1 0 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_4_ 3 -1 1 1 6 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_3_ 3 -1 6 1 1 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_2_ 3 -1 3 1 6 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_1_ 3 -1 2 1 3 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_0_ 3 -1 3 1 2 -1 -1 1 0 21 + 332 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 331 CLK_000_D_9_ 3 -1 6 1 5 -1 -1 1 0 21 + 330 CLK_000_D_8_ 3 -1 6 1 6 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 0 1 6 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 4 1 0 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 6 1 4 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 4 1 6 -1 -1 1 0 21 + 325 CLK_000_D_3_ 3 -1 4 1 4 -1 -1 1 0 21 + 324 CLK_000_D_2_ 3 -1 6 1 4 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 5 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 1 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 1 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21 + 314 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21 + 313 CLK_000_D_10_ 3 -1 5 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 13 nEXP_SPACE 1 -1 -1 7 0 1 2 3 4 6 7 13 -1 + 96 A_DECODE_19_ 1 -1 -1 3 0 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 0 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 0 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 0 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 0 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 0 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 5 67 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 59 A_1_ 1 -1 -1 1 1 59 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 1 10 -1 +139 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 79 RW_000 5 365 7 2 4 6 79 -1 8 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 70 RW 5 370 6 1 7 70 -1 2 0 21 + 40 BERR 5 -1 4 1 7 40 -1 1 0 21 + 31 UDS_000 5 -1 3 1 6 31 -1 1 0 21 + 18 AHIGH_24_ 5 -1 -1 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 -1 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 -1 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 -1 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 -1 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 -1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 -1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 -1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 0 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 10 0 21 + 80 DSACK1 0 7 0 80 -1 4 0 21 + 82 BGACK_030 0 7 0 82 -1 3 0 21 + 68 A_0_ 5 361 6 0 68 -1 3 0 21 + 34 VMA 0 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 78 SIZE_1_ 0 -1 0 78 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 69 SIZE_0_ 0 6 0 69 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 -1 0 32 -1 1 0 21 + 30 LDS_000 0 3 0 30 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 -1 0 2 -1 1 0 21 + 367 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 -1 5 0 3 4 6 7 -1 -1 2 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 -1 3 1 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 -1 3 3 4 7 -1 -1 1 0 21 + 359 SM_AMIGA_i_7_ 3 -1 -1 2 3 7 -1 -1 15 0 21 + 294 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 297 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 320 CLK_000_D_0_ 3 -1 -1 2 3 7 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 -1 2 3 7 -1 -1 1 0 21 + 364 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 363 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 -1 1 0 -1 -1 9 0 21 + 365 RN_RW_000 3 79 7 1 7 79 -1 8 0 21 + 303 inst_AS_000_DMA 3 -1 -1 1 7 -1 -1 7 0 21 + 336 inst_DS_000_ENABLE 3 -1 -1 1 3 -1 -1 5 0 21 + 368 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 369 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 361 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 333 SM_AMIGA_0_ 3 -1 -1 1 7 -1 -1 3 0 21 + 311 inst_LDS_000_INT 3 -1 -1 1 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 -1 1 6 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 -1 1 6 -1 -1 3 0 21 + 370 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 366 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 360 CIIN_0 3 -1 -1 1 4 -1 -1 2 0 21 + 356 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 2 0 21 + 334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 -1 1 3 -1 -1 2 0 21 + 321 SM_AMIGA_5_ 3 -1 -1 1 7 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 -1 1 3 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 -1 1 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 337 CLK_000_N_SYNC_12_ 3 -1 -1 1 3 -1 -1 1 0 21 + 332 CLK_000_D_12_ 3 -1 -1 1 7 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 -1 1 7 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 -1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 -1 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 -1 1 1 -1 -1 1 0 21 + 315 CLK_000_D_11_ 3 -1 -1 1 7 -1 -1 1 0 21 + 314 CLK_000_D_10_ 3 -1 -1 1 7 -1 -1 1 0 21 + 313 CLK_000_D_3_ 3 -1 -1 1 7 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 -1 1 6 -1 -1 1 0 21 + 357 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 8 0 21 + 355 inst_CLK_030_H 3 -1 -1 0 -1 -1 8 0 21 + 301 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 7 0 21 + 358 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 4 0 21 + 339 RST_DLY_1_ 3 -1 -1 0 -1 -1 4 0 21 + 306 CYCLE_DMA_1_ 3 -1 -1 0 -1 -1 4 0 21 + 354 SM_AMIGA_6_ 3 -1 -1 0 -1 -1 3 0 21 + 352 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 3 0 21 + 338 RST_DLY_0_ 3 -1 -1 0 -1 -1 3 0 21 + 305 CYCLE_DMA_0_ 3 -1 -1 0 -1 -1 3 0 21 + 293 N_194_i 3 -1 -1 0 -1 -1 3 0 21 + 340 RST_DLY_2_ 3 -1 -1 0 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 -1 0 -1 -1 2 0 21 + 353 inst_CLK_000_NE_D0 3 -1 -1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_11_ 3 -1 -1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_10_ 3 -1 -1 0 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_9_ 3 -1 -1 0 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_8_ 3 -1 -1 0 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_7_ 3 -1 -1 0 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_6_ 3 -1 -1 0 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_5_ 3 -1 -1 0 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_4_ 3 -1 -1 0 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_3_ 3 -1 -1 0 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_2_ 3 -1 -1 0 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_1_ 3 -1 -1 0 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_0_ 3 -1 -1 0 -1 -1 1 0 21 + 331 CLK_000_D_9_ 3 -1 -1 0 -1 -1 1 0 21 + 330 CLK_000_D_8_ 3 -1 -1 0 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 -1 0 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 -1 0 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 -1 0 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 -1 0 -1 -1 1 0 21 + 319 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 63 CLK_030 1 -1 -1 1 7 63 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 59 A_1_ 1 -1 -1 0 59 -1 + 35 VPA 1 -1 -1 0 35 -1 + 29 DTACK 1 -1 -1 0 29 -1 + 10 CLK_000 1 -1 -1 0 10 -1 +139 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 79 RW_000 5 365 7 2 4 6 79 -1 5 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 70 RW 5 370 6 1 7 70 -1 2 0 21 + 40 BERR 5 -1 4 1 7 40 -1 1 0 21 + 31 UDS_000 5 -1 3 1 6 31 -1 1 0 21 + 18 AHIGH_24_ 5 -1 -1 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 -1 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 -1 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 -1 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 -1 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 -1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 -1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 -1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 0 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 10 0 21 + 80 DSACK1 0 7 0 80 -1 4 0 21 + 82 BGACK_030 0 7 0 82 -1 3 0 21 + 68 A_0_ 5 361 6 0 68 -1 3 0 21 + 34 VMA 0 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 78 SIZE_1_ 0 -1 0 78 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 69 SIZE_0_ 0 6 0 69 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 -1 0 32 -1 1 0 21 + 30 LDS_000 0 3 0 30 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 -1 0 2 -1 1 0 21 + 367 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 -1 5 0 3 4 6 7 -1 -1 2 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 -1 3 1 6 7 -1 -1 1 0 21 + 299 inst_AS_030_D0 3 -1 -1 3 3 4 7 -1 -1 1 0 21 + 359 SM_AMIGA_i_7_ 3 -1 -1 2 3 7 -1 -1 15 0 21 + 293 cpu_est_2_ 3 -1 -1 2 3 6 -1 -1 4 0 21 + 296 cpu_est_1_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 -1 2 3 6 -1 -1 3 0 21 + 320 CLK_000_D_0_ 3 -1 -1 2 3 7 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 -1 2 3 7 -1 -1 1 0 21 + 364 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 363 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 362 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 -1 1 0 -1 -1 9 0 21 + 303 inst_AS_000_DMA 3 -1 -1 1 7 -1 -1 7 0 21 + 365 RN_RW_000 3 79 7 1 7 79 -1 5 0 21 + 336 inst_DS_000_ENABLE 3 -1 -1 1 3 -1 -1 5 0 21 + 368 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 369 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 361 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 333 SM_AMIGA_0_ 3 -1 -1 1 7 -1 -1 3 0 21 + 311 inst_LDS_000_INT 3 -1 -1 1 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 -1 1 6 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 -1 1 6 -1 -1 3 0 21 + 370 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 366 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 360 CIIN_0 3 -1 -1 1 4 -1 -1 2 0 21 + 356 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 2 0 21 + 334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 -1 1 3 -1 -1 2 0 21 + 321 SM_AMIGA_5_ 3 -1 -1 1 7 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 -1 1 3 -1 -1 2 0 21 + 297 inst_AS_000_INT 3 -1 -1 1 4 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 337 CLK_000_N_SYNC_12_ 3 -1 -1 1 3 -1 -1 1 0 21 + 332 CLK_000_D_12_ 3 -1 -1 1 7 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 -1 1 7 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 -1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 -1 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 -1 1 1 -1 -1 1 0 21 + 315 CLK_000_D_11_ 3 -1 -1 1 7 -1 -1 1 0 21 + 314 CLK_000_D_10_ 3 -1 -1 1 7 -1 -1 1 0 21 + 313 CLK_000_D_3_ 3 -1 -1 1 7 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 -1 1 6 -1 -1 1 0 21 + 357 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 8 0 21 + 355 inst_CLK_030_H 3 -1 -1 0 -1 -1 8 0 21 + 301 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 7 0 21 + 358 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 4 0 21 + 339 RST_DLY_1_ 3 -1 -1 0 -1 -1 4 0 21 + 306 CYCLE_DMA_1_ 3 -1 -1 0 -1 -1 4 0 21 + 354 SM_AMIGA_6_ 3 -1 -1 0 -1 -1 3 0 21 + 352 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 3 0 21 + 338 RST_DLY_0_ 3 -1 -1 0 -1 -1 3 0 21 + 305 CYCLE_DMA_0_ 3 -1 -1 0 -1 -1 3 0 21 + 340 RST_DLY_2_ 3 -1 -1 0 -1 -1 2 0 21 + 300 N_140_i 3 -1 -1 0 -1 -1 2 0 21 + 298 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 -1 0 -1 -1 2 0 21 + 353 inst_CLK_000_NE_D0 3 -1 -1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_11_ 3 -1 -1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_10_ 3 -1 -1 0 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_9_ 3 -1 -1 0 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_8_ 3 -1 -1 0 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_7_ 3 -1 -1 0 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_6_ 3 -1 -1 0 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_5_ 3 -1 -1 0 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_4_ 3 -1 -1 0 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_3_ 3 -1 -1 0 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_2_ 3 -1 -1 0 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_1_ 3 -1 -1 0 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_0_ 3 -1 -1 0 -1 -1 1 0 21 + 331 CLK_000_D_9_ 3 -1 -1 0 -1 -1 1 0 21 + 330 CLK_000_D_8_ 3 -1 -1 0 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 -1 0 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 -1 0 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 -1 0 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 -1 0 -1 -1 1 0 21 + 319 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 63 CLK_030 1 -1 -1 1 7 63 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 59 A_1_ 1 -1 -1 0 59 -1 + 35 VPA 1 -1 -1 0 35 -1 + 29 DTACK 1 -1 -1 0 29 -1 + 10 CLK_000 1 -1 -1 0 10 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 79 RW_000 5 363 7 2 4 6 79 -1 4 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 70 RW 5 368 6 1 7 70 -1 2 0 21 + 40 BERR 5 -1 4 1 7 40 -1 1 0 21 + 31 UDS_000 5 -1 3 1 6 31 -1 1 0 21 + 18 AHIGH_24_ 5 -1 -1 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 -1 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 -1 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 -1 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 -1 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 -1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 -1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 -1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 0 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 0 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 0 1 0 6 -1 10 0 21 + 80 DSACK1 0 7 0 80 -1 4 0 21 + 82 BGACK_030 0 7 0 82 -1 3 0 21 + 68 A_0_ 5 369 6 0 68 -1 3 0 21 + 34 VMA 0 3 0 34 -1 3 0 21 + 65 E 0 -1 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 -1 0 33 -1 2 0 21 + 28 BG_000 0 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 -1 0 91 -1 1 0 21 + 78 SIZE_1_ 0 -1 0 78 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 69 SIZE_0_ 0 6 0 69 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 -1 0 32 -1 1 0 21 + 30 LDS_000 0 3 0 30 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 -1 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 -1 0 2 -1 1 0 21 + 365 RN_BGACK_030 3 82 7 5 0 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 -1 5 0 3 4 6 7 -1 -1 2 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 -1 3 1 6 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 -1 3 3 4 7 -1 -1 1 0 21 + 319 CLK_000_D_0_ 3 -1 -1 2 3 7 -1 -1 1 0 21 + 317 CLK_000_D_1_ 3 -1 -1 2 3 7 -1 -1 1 0 21 + 359 SM_AMIGA_i_7_ 3 -1 -1 1 7 -1 -1 14 0 21 + 371 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 370 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 362 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 -1 1 0 -1 -1 9 0 21 + 303 inst_AS_000_DMA 3 -1 -1 1 7 -1 -1 7 0 21 + 336 inst_DS_000_ENABLE 3 -1 -1 1 3 -1 -1 5 0 21 + 366 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 363 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 297 cpu_est_2_ 3 -1 -1 1 3 -1 -1 4 0 21 + 369 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 367 RN_VMA 3 34 3 1 3 34 -1 3 0 21 + 333 SM_AMIGA_0_ 3 -1 -1 1 7 -1 -1 3 0 21 + 311 inst_LDS_000_INT 3 -1 -1 1 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 -1 1 6 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 -1 1 6 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 -1 1 3 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 -1 1 3 -1 -1 3 0 21 + 368 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 364 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 360 CIIN_0 3 -1 -1 1 4 -1 -1 2 0 21 + 356 SM_AMIGA_1_ 3 -1 -1 1 7 -1 -1 2 0 21 + 320 SM_AMIGA_5_ 3 -1 -1 1 7 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 -1 1 3 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 -1 1 4 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 -1 1 3 -1 -1 2 0 21 + 337 CLK_000_N_SYNC_12_ 3 -1 -1 1 3 -1 -1 1 0 21 + 332 CLK_000_D_12_ 3 -1 -1 1 7 -1 -1 1 0 21 + 325 CLK_000_D_3_ 3 -1 -1 1 7 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 -1 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 -1 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 -1 1 1 -1 -1 1 0 21 + 314 CLK_000_D_11_ 3 -1 -1 1 7 -1 -1 1 0 21 + 313 CLK_000_D_10_ 3 -1 -1 1 7 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 -1 1 3 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 -1 1 6 -1 -1 1 0 21 + 357 SM_AMIGA_3_ 3 -1 -1 0 -1 -1 8 0 21 + 355 inst_CLK_030_H 3 -1 -1 0 -1 -1 8 0 21 + 301 inst_AS_030_000_SYNC 3 -1 -1 0 -1 -1 7 0 21 + 358 SM_AMIGA_2_ 3 -1 -1 0 -1 -1 4 0 21 + 339 RST_DLY_1_ 3 -1 -1 0 -1 -1 4 0 21 + 306 CYCLE_DMA_1_ 3 -1 -1 0 -1 -1 4 0 21 + 361 SM_AMIGA_i_7__0 3 -1 -1 0 -1 -1 3 0 21 + 354 SM_AMIGA_6_ 3 -1 -1 0 -1 -1 3 0 21 + 352 SM_AMIGA_4_ 3 -1 -1 0 -1 -1 3 0 21 + 338 RST_DLY_0_ 3 -1 -1 0 -1 -1 3 0 21 + 305 CYCLE_DMA_0_ 3 -1 -1 0 -1 -1 3 0 21 + 340 RST_DLY_2_ 3 -1 -1 0 -1 -1 2 0 21 + 334 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 -1 0 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 -1 0 -1 -1 2 0 21 + 293 N_151 3 -1 -1 0 -1 -1 2 0 21 + 353 inst_CLK_000_NE_D0 3 -1 -1 0 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_11_ 3 -1 -1 0 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_10_ 3 -1 -1 0 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_9_ 3 -1 -1 0 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_8_ 3 -1 -1 0 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_7_ 3 -1 -1 0 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_6_ 3 -1 -1 0 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_5_ 3 -1 -1 0 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_4_ 3 -1 -1 0 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_3_ 3 -1 -1 0 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_2_ 3 -1 -1 0 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_1_ 3 -1 -1 0 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_0_ 3 -1 -1 0 -1 -1 1 0 21 + 331 CLK_000_D_9_ 3 -1 -1 0 -1 -1 1 0 21 + 330 CLK_000_D_8_ 3 -1 -1 0 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 -1 0 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 -1 0 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 -1 0 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 -1 0 -1 -1 1 0 21 + 324 CLK_000_D_2_ 3 -1 -1 0 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 -1 0 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 -1 0 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 5 0 3 4 6 7 13 -1 + 85 RST 1 -1 -1 4 1 3 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 2 4 7 94 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 58 A_DECODE_17_ 1 -1 -1 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 2 4 7 56 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 66 IPL_0_ 1 -1 -1 1 1 66 -1 + 63 CLK_030 1 -1 -1 1 7 63 -1 + 55 IPL_1_ 1 -1 -1 1 1 55 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 59 A_1_ 1 -1 -1 0 59 -1 + 35 VPA 1 -1 -1 0 35 -1 + 29 DTACK 1 -1 -1 0 29 -1 + 10 CLK_000 1 -1 -1 0 10 -1 +140 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 5 0 1 2 5 7 40 -1 1 0 21 + 79 RW_000 5 364 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 369 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A_0_ 5 370 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 363 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 362 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 371 1 0 6 -1 10 0 21 + 80 DSACK1 5 367 7 0 80 -1 4 0 21 + 82 BGACK_030 5 366 7 0 82 -1 3 0 21 + 34 VMA 5 368 3 0 34 -1 3 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 28 BG_000 5 365 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 366 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 2 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 359 SM_AMIGA_i_7_ 3 -1 5 5 0 2 3 5 7 -1 -1 14 0 21 + 320 SM_AMIGA_5_ 3 -1 1 5 0 1 2 5 7 -1 -1 2 0 21 + 336 CLK_000_N_SYNC_12_ 3 -1 6 5 1 2 3 5 6 -1 -1 1 0 21 + 319 CLK_000_D_0_ 3 -1 4 5 0 1 3 5 7 -1 -1 1 0 21 + 317 CLK_000_D_1_ 3 -1 7 5 0 1 3 5 7 -1 -1 1 0 21 + 300 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21 + 333 SM_AMIGA_0_ 3 -1 5 4 0 3 5 7 -1 -1 3 0 21 + 297 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 354 SM_AMIGA_6_ 3 -1 5 3 0 1 5 -1 -1 3 0 21 + 296 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 294 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 335 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21 + 338 RST_DLY_1_ 3 -1 6 2 2 6 -1 -1 4 0 21 + 368 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 351 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 337 RST_DLY_0_ 3 -1 6 2 2 6 -1 -1 3 0 21 + 311 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 356 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 0 21 + 353 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 339 RST_DLY_2_ 3 -1 2 2 2 6 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 295 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 334 CLK_000_N_SYNC_0_ 3 -1 0 2 2 5 -1 -1 1 0 21 + 313 CLK_000_D_10_ 3 -1 0 2 0 7 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 3 2 2 6 -1 -1 1 0 21 + 371 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 363 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 362 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 357 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21 + 355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 367 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 364 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 358 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 370 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 361 SM_AMIGA_i_7__0 3 -1 5 1 5 -1 -1 3 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 369 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 365 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 360 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 293 N_149_i 3 -1 5 1 5 -1 -1 2 0 21 + 352 inst_CLK_000_NE_D0 3 -1 3 1 5 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_11_ 3 -1 2 1 6 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_10_ 3 -1 6 1 2 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_9_ 3 -1 1 1 6 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_8_ 3 -1 3 1 1 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_7_ 3 -1 5 1 3 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_6_ 3 -1 0 1 5 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_5_ 3 -1 5 1 0 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_4_ 3 -1 6 1 5 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_3_ 3 -1 1 1 6 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_2_ 3 -1 3 1 1 -1 -1 1 0 21 + 340 CLK_000_N_SYNC_1_ 3 -1 2 1 3 -1 -1 1 0 21 + 332 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 331 CLK_000_D_9_ 3 -1 1 1 0 -1 -1 1 0 21 + 330 CLK_000_D_8_ 3 -1 6 1 1 -1 -1 1 0 21 + 329 CLK_000_D_7_ 3 -1 1 1 6 -1 -1 1 0 21 + 328 CLK_000_D_6_ 3 -1 3 1 1 -1 -1 1 0 21 + 327 CLK_000_D_5_ 3 -1 4 1 3 -1 -1 1 0 21 + 326 CLK_000_D_4_ 3 -1 4 1 4 -1 -1 1 0 21 + 325 CLK_000_D_3_ 3 -1 6 1 4 -1 -1 1 0 21 + 324 CLK_000_D_2_ 3 -1 3 1 6 -1 -1 1 0 21 + 323 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 322 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 + 321 IPL_D0_0_ 3 -1 6 1 1 -1 -1 1 0 21 + 318 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 3 1 5 -1 -1 1 0 21 + 314 CLK_000_D_11_ 3 -1 0 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 6 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 4 10 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 59 A_1_ 1 -1 -1 1 2 59 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 3 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 +139 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 0 2 5 7 40 -1 1 0 21 + 79 RW_000 5 362 7 3 0 4 6 79 -1 4 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 70 RW 5 367 6 2 0 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 68 A_0_ 5 368 6 1 1 68 -1 3 0 21 + 78 SIZE_1_ 5 -1 7 1 1 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 1 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 361 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 370 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 369 1 0 6 -1 10 0 21 + 80 DSACK1 5 365 7 0 80 -1 4 0 21 + 82 BGACK_030 5 364 7 0 82 -1 3 0 21 + 34 VMA 5 366 3 0 34 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 2 0 21 + 28 BG_000 5 363 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 364 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 317 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 301 inst_AS_030_D0 3 -1 7 5 0 2 3 4 7 -1 -1 1 0 21 + 359 SM_AMIGA_i_7_ 3 -1 5 4 0 2 5 7 -1 -1 15 0 21 + 321 SM_AMIGA_5_ 3 -1 5 4 0 2 5 7 -1 -1 2 0 21 + 320 CLK_000_D_0_ 3 -1 5 4 0 3 5 7 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 7 4 0 3 5 7 -1 -1 1 0 21 + 294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 354 SM_AMIGA_6_ 3 -1 5 3 0 1 5 -1 -1 3 0 21 + 334 SM_AMIGA_0_ 3 -1 5 3 0 5 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 337 CLK_000_N_SYNC_12_ 3 -1 2 3 3 4 5 -1 -1 1 0 21 + 313 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 304 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 302 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 336 inst_DS_000_ENABLE 3 -1 0 2 0 3 -1 -1 5 0 21 + 366 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 352 SM_AMIGA_4_ 3 -1 5 2 0 5 -1 -1 3 0 21 + 312 inst_LDS_000_INT 3 -1 1 2 1 3 -1 -1 3 0 21 + 309 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 308 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 356 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 2 0 21 + 311 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 6 2 3 6 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 2 2 2 4 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 5 2 3 5 -1 -1 2 0 21 + 335 CLK_000_N_SYNC_0_ 3 -1 0 2 3 5 -1 -1 1 0 21 + 315 CLK_000_D_11_ 3 -1 4 2 3 7 -1 -1 1 0 21 + 314 CLK_000_D_10_ 3 -1 4 2 4 7 -1 -1 1 0 21 + 310 inst_VPA_D 3 -1 6 2 3 5 -1 -1 1 0 21 + 303 inst_BGACK_030_INT_D 3 -1 7 2 2 6 -1 -1 1 0 21 + 370 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 369 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 361 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 305 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 357 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 8 0 21 + 355 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 365 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 362 RN_RW_000 3 79 7 1 7 79 -1 4 0 21 + 358 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 339 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 307 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 4 0 21 + 368 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 338 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 306 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 3 0 21 + 367 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 363 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 360 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 340 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 300 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 2 1 2 -1 -1 2 0 21 + 293 N_151_i 3 -1 5 1 5 -1 -1 2 0 21 + 353 inst_CLK_000_NE_D0 3 -1 4 1 5 -1 -1 1 0 21 + 351 CLK_000_N_SYNC_11_ 3 -1 6 1 2 -1 -1 1 0 21 + 350 CLK_000_N_SYNC_10_ 3 -1 1 1 6 -1 -1 1 0 21 + 349 CLK_000_N_SYNC_9_ 3 -1 0 1 1 -1 -1 1 0 21 + 348 CLK_000_N_SYNC_8_ 3 -1 2 1 0 -1 -1 1 0 21 + 347 CLK_000_N_SYNC_7_ 3 -1 1 1 2 -1 -1 1 0 21 + 346 CLK_000_N_SYNC_6_ 3 -1 6 1 1 -1 -1 1 0 21 + 345 CLK_000_N_SYNC_5_ 3 -1 5 1 6 -1 -1 1 0 21 + 344 CLK_000_N_SYNC_4_ 3 -1 2 1 5 -1 -1 1 0 21 + 343 CLK_000_N_SYNC_3_ 3 -1 1 1 2 -1 -1 1 0 21 + 342 CLK_000_N_SYNC_2_ 3 -1 6 1 1 -1 -1 1 0 21 + 341 CLK_000_N_SYNC_1_ 3 -1 3 1 6 -1 -1 1 0 21 + 333 CLK_000_D_12_ 3 -1 3 1 7 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 2 1 4 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 1 1 2 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 6 1 1 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 1 1 6 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 3 1 1 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 0 1 3 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 2 1 0 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 0 1 2 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 2 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 6 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 319 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 316 inst_DTACK_D0 3 -1 6 1 5 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 67 IPL_2_ 1 -1 -1 2 1 2 67 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 59 A_1_ 1 -1 -1 2 2 6 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 6 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 35 VPA 1 -1 -1 1 6 35 -1 + 29 DTACK 1 -1 -1 1 6 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 + 10 CLK_000 1 -1 -1 1 5 10 -1 +150 "number of signals after reading design file" + +"sig sig sig pair blk fan PT xor sync" +"num name type sig num out pin node cnt PT type" +"--- ---- ---- ---- --- --- --- ---- --- --- ----" + + 40 BERR 5 -1 4 4 2 5 6 7 40 -1 1 0 21 + 79 RW_000 5 373 7 3 0 4 6 79 -1 3 0 21 + 41 AS_000 5 -1 4 3 0 4 7 41 -1 1 0 21 + 68 A_0_ 5 374 6 2 0 1 68 -1 3 0 21 + 70 RW 5 381 6 2 5 7 70 -1 2 0 21 + 81 AS_030 5 -1 7 2 4 7 81 -1 1 0 21 + 31 UDS_000 5 -1 3 2 0 6 31 -1 1 0 21 + 30 LDS_000 5 -1 3 2 0 6 30 -1 1 0 21 + 78 SIZE_1_ 5 -1 7 1 0 78 -1 1 0 21 + 69 SIZE_0_ 5 -1 6 1 0 69 -1 1 0 21 + 18 AHIGH_24_ 5 -1 2 1 4 18 -1 1 0 21 + 17 AHIGH_25_ 5 -1 2 1 4 17 -1 1 0 21 + 16 AHIGH_26_ 5 -1 2 1 4 16 -1 1 0 21 + 15 AHIGH_27_ 5 -1 2 1 4 15 -1 1 0 21 + 14 AHIGH_28_ 5 -1 2 1 4 14 -1 1 0 21 + 5 AHIGH_29_ 5 -1 1 1 4 5 -1 1 0 21 + 4 AHIGH_30_ 5 -1 1 1 4 4 -1 1 0 21 + 3 AHIGH_31_ 5 -1 1 1 4 3 -1 1 0 21 + 8 IPL_030_2_ 5 372 1 0 8 -1 10 0 21 + 7 IPL_030_0_ 5 376 1 0 7 -1 10 0 21 + 6 IPL_030_1_ 5 375 1 0 6 -1 10 0 21 + 80 DSACK1 5 379 7 0 80 -1 4 0 21 + 82 BGACK_030 5 378 7 0 82 -1 3 0 21 + 34 VMA 5 380 3 0 34 -1 3 0 21 + 33 AMIGA_BUS_ENABLE_HIGH 0 3 0 33 -1 3 0 21 + 65 E 0 6 0 65 -1 2 0 21 + 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 2 0 21 + 28 BG_000 5 377 3 0 28 -1 2 0 21 + 97 DS_030 0 0 0 97 -1 1 0 21 + 91 AVEC 0 0 0 91 -1 1 0 21 + 77 FPU_CS 0 7 0 77 -1 1 0 21 + 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21 + 46 CIIN 0 4 0 46 -1 1 0 21 + 32 AMIGA_ADDR_ENABLE 0 3 0 32 -1 1 0 21 + 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21 + 9 CLK_EXP 0 1 0 9 -1 1 0 21 + 2 RESET 0 1 0 2 -1 1 0 21 + 378 RN_BGACK_030 3 82 7 7 0 1 2 3 4 6 7 82 -1 3 0 21 + 316 inst_RESET_OUT 3 -1 3 7 0 1 2 3 4 6 7 -1 -1 2 0 21 + 300 inst_AS_030_D0 3 -1 7 6 2 3 4 5 6 7 -1 -1 1 0 21 + 320 CLK_000_P_SYNC_10_ 3 -1 0 5 0 2 3 5 7 -1 -1 1 0 21 + 370 SM_AMIGA_i_7_ 3 -1 5 4 2 3 5 7 -1 -1 14 0 21 + 365 SM_AMIGA_6_ 3 -1 2 4 0 1 2 5 -1 -1 3 0 21 + 294 cpu_est_2_ 3 -1 5 3 3 5 6 -1 -1 4 0 21 + 321 SM_AMIGA_5_ 3 -1 5 3 5 6 7 -1 -1 3 0 21 + 297 cpu_est_1_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 295 cpu_est_3_ 3 -1 5 3 3 5 6 -1 -1 3 0 21 + 334 SM_AMIGA_0_ 3 -1 5 3 3 5 7 -1 -1 2 0 21 + 296 cpu_est_0_ 3 -1 1 3 1 3 5 -1 -1 2 0 21 + 338 CLK_000_N_SYNC_12_ 3 -1 3 3 3 4 5 -1 -1 1 0 21 + 335 CLK_000_N_SYNC_0_ 3 -1 3 3 2 4 5 -1 -1 1 0 21 + 312 inst_CLK_OUT_PRE_D 3 -1 4 3 1 6 7 -1 -1 1 0 21 + 302 inst_BGACK_030_INT_D 3 -1 7 3 1 2 6 -1 -1 1 0 21 + 303 inst_AS_000_DMA 3 -1 0 2 0 7 -1 -1 7 0 21 + 301 inst_AS_030_000_SYNC 3 -1 2 2 2 5 -1 -1 7 0 21 + 337 inst_DS_000_ENABLE 3 -1 5 2 3 5 -1 -1 5 0 21 + 380 RN_VMA 3 34 3 2 3 5 34 -1 3 0 21 + 367 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21 + 311 inst_LDS_000_INT 3 -1 0 2 0 3 -1 -1 3 0 21 + 308 SIZE_DMA_1_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 307 SIZE_DMA_0_ 3 -1 6 2 6 7 -1 -1 3 0 21 + 364 inst_AMIGA_BUS_ENABLE_DMA_HIGH 3 -1 2 2 2 3 -1 -1 2 0 21 + 310 inst_UDS_000_INT 3 -1 1 2 1 3 -1 -1 2 0 21 + 299 inst_AMIGA_BUS_ENABLE_DMA_LOW 3 -1 1 2 1 2 -1 -1 2 0 21 + 298 inst_AS_000_INT 3 -1 6 2 4 6 -1 -1 2 0 21 + 363 inst_CLK_000_NE_D0 3 -1 4 2 1 5 -1 -1 1 0 21 + 319 CLK_000_D_0_ 3 -1 6 2 2 3 -1 -1 1 0 21 + 318 CLK_000_D_1_ 3 -1 2 2 3 6 -1 -1 1 0 21 + 309 inst_VPA_D 3 -1 0 2 3 5 -1 -1 1 0 21 + 376 RN_IPL_030_0_ 3 7 1 1 1 7 -1 10 0 21 + 375 RN_IPL_030_1_ 3 6 1 1 1 6 -1 10 0 21 + 372 RN_IPL_030_2_ 3 8 1 1 1 8 -1 10 0 21 + 304 inst_DS_000_DMA 3 -1 0 1 0 -1 -1 9 0 21 + 366 inst_CLK_030_H 3 -1 0 1 0 -1 -1 8 0 21 + 368 SM_AMIGA_3_ 3 -1 5 1 5 -1 -1 5 0 21 + 379 RN_DSACK1 3 80 7 1 7 80 -1 4 0 21 + 369 SM_AMIGA_2_ 3 -1 5 1 5 -1 -1 4 0 21 + 340 RST_DLY_1_ 3 -1 3 1 3 -1 -1 4 0 21 + 374 RN_A_0_ 3 68 6 1 6 68 -1 3 0 21 + 373 RN_RW_000 3 79 7 1 7 79 -1 3 0 21 + 339 RST_DLY_0_ 3 -1 3 1 3 -1 -1 3 0 21 + 336 SM_AMIGA_4_ 3 -1 5 1 5 -1 -1 3 0 21 + 306 CYCLE_DMA_1_ 3 -1 0 1 0 -1 -1 3 0 21 + 293 N_226 3 -1 5 1 5 -1 -1 3 0 21 + 381 RN_RW 3 70 6 1 6 70 -1 2 0 21 + 377 RN_BG_000 3 28 3 1 3 28 -1 2 0 21 + 371 CIIN_0 3 -1 4 1 4 -1 -1 2 0 21 + 341 RST_DLY_2_ 3 -1 3 1 3 -1 -1 2 0 21 + 305 CYCLE_DMA_0_ 3 -1 0 1 0 -1 -1 2 0 21 + 362 CLK_000_N_SYNC_11_ 3 -1 2 1 3 -1 -1 1 0 21 + 361 CLK_000_N_SYNC_10_ 3 -1 2 1 2 -1 -1 1 0 21 + 360 CLK_000_N_SYNC_9_ 3 -1 5 1 2 -1 -1 1 0 21 + 359 CLK_000_N_SYNC_8_ 3 -1 1 1 5 -1 -1 1 0 21 + 358 CLK_000_N_SYNC_7_ 3 -1 6 1 1 -1 -1 1 0 21 + 357 CLK_000_N_SYNC_6_ 3 -1 1 1 6 -1 -1 1 0 21 + 356 CLK_000_N_SYNC_5_ 3 -1 0 1 1 -1 -1 1 0 21 + 355 CLK_000_N_SYNC_4_ 3 -1 0 1 0 -1 -1 1 0 21 + 354 CLK_000_N_SYNC_3_ 3 -1 5 1 0 -1 -1 1 0 21 + 353 CLK_000_N_SYNC_2_ 3 -1 0 1 5 -1 -1 1 0 21 + 352 CLK_000_N_SYNC_1_ 3 -1 4 1 0 -1 -1 1 0 21 + 351 CLK_000_P_SYNC_9_ 3 -1 2 1 0 -1 -1 1 0 21 + 350 CLK_000_P_SYNC_8_ 3 -1 0 1 2 -1 -1 1 0 21 + 349 CLK_000_P_SYNC_7_ 3 -1 3 1 0 -1 -1 1 0 21 + 348 CLK_000_P_SYNC_6_ 3 -1 6 1 3 -1 -1 1 0 21 + 347 CLK_000_P_SYNC_5_ 3 -1 6 1 6 -1 -1 1 0 21 + 346 CLK_000_P_SYNC_4_ 3 -1 0 1 6 -1 -1 1 0 21 + 345 CLK_000_P_SYNC_3_ 3 -1 2 1 0 -1 -1 1 0 21 + 344 CLK_000_P_SYNC_2_ 3 -1 5 1 2 -1 -1 1 0 21 + 343 CLK_000_P_SYNC_1_ 3 -1 0 1 5 -1 -1 1 0 21 + 342 CLK_000_P_SYNC_0_ 3 -1 3 1 0 -1 -1 1 0 21 + 333 CLK_000_D_12_ 3 -1 7 1 7 -1 -1 1 0 21 + 332 CLK_000_D_9_ 3 -1 3 1 6 -1 -1 1 0 21 + 331 CLK_000_D_8_ 3 -1 1 1 3 -1 -1 1 0 21 + 330 CLK_000_D_7_ 3 -1 6 1 1 -1 -1 1 0 21 + 329 CLK_000_D_6_ 3 -1 1 1 6 -1 -1 1 0 21 + 328 CLK_000_D_5_ 3 -1 4 1 1 -1 -1 1 0 21 + 327 CLK_000_D_4_ 3 -1 2 1 4 -1 -1 1 0 21 + 326 CLK_000_D_3_ 3 -1 6 1 2 -1 -1 1 0 21 + 325 CLK_000_D_2_ 3 -1 6 1 6 -1 -1 1 0 21 + 324 IPL_D0_2_ 3 -1 1 1 1 -1 -1 1 0 21 + 323 IPL_D0_1_ 3 -1 5 1 1 -1 -1 1 0 21 + 322 IPL_D0_0_ 3 -1 3 1 1 -1 -1 1 0 21 + 317 inst_CLK_OUT_PRE_50 3 -1 4 1 4 -1 -1 1 0 21 + 315 inst_DTACK_D0 3 -1 2 1 5 -1 -1 1 0 21 + 314 CLK_000_D_11_ 3 -1 7 1 7 -1 -1 1 0 21 + 313 CLK_000_D_10_ 3 -1 6 1 7 -1 -1 1 0 21 + 60 CLK_OSZI 9 -1 0 60 -1 + 13 nEXP_SPACE 1 -1 -1 8 0 1 2 3 4 5 6 7 13 -1 + 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1 + 96 A_DECODE_19_ 1 -1 -1 3 2 4 7 96 -1 + 95 A_DECODE_16_ 1 -1 -1 3 2 4 7 95 -1 + 94 A_DECODE_18_ 1 -1 -1 3 2 4 7 94 -1 + 58 A_DECODE_17_ 1 -1 -1 3 2 4 7 58 -1 + 57 FC_1_ 1 -1 -1 3 2 4 7 57 -1 + 56 FC_0_ 1 -1 -1 3 2 4 7 56 -1 + 90 FPU_SENSE 1 -1 -1 2 4 7 90 -1 + 66 IPL_0_ 1 -1 -1 2 1 3 66 -1 + 63 CLK_030 1 -1 -1 2 0 7 63 -1 + 59 A_1_ 1 -1 -1 2 1 2 59 -1 + 55 IPL_1_ 1 -1 -1 2 1 5 55 -1 + 27 BGACK_000 1 -1 -1 2 4 7 27 -1 + 10 CLK_000 1 -1 -1 2 3 6 10 -1 + 93 A_DECODE_21_ 1 -1 -1 1 4 93 -1 + 92 A_DECODE_20_ 1 -1 -1 1 4 92 -1 + 84 A_DECODE_23_ 1 -1 -1 1 4 84 -1 + 83 A_DECODE_22_ 1 -1 -1 1 4 83 -1 + 67 IPL_2_ 1 -1 -1 1 1 67 -1 + 35 VPA 1 -1 -1 1 0 35 -1 + 29 DTACK 1 -1 -1 1 2 29 -1 + 20 BG_030 1 -1 -1 1 3 20 -1 \ No newline at end of file diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc index 0782a97..0cb8fab 100644 --- a/Logic/68030_tk.plc +++ b/Logic/68030_tk.plc @@ -8,155 +8,173 @@ ; Source file 68030_tk.tt4 ; FITTER-generated Placements. ; DEVICE mach447a -; DATE Wed Aug 17 17:45:51 2016 +; DATE Fri Aug 19 00:20:46 2016 +Pin 84 A_DECODE_22_ +Pin 94 A_DECODE_21_ Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 287 -Pin 4 A_31_ +Pin 93 A_DECODE_20_ +Pin 97 A_DECODE_19_ +Pin 4 AHIGH_31_ Comb ; S6=1 S9=1 Pair 143 +Pin 95 A_DECODE_18_ +Pin 59 A_DECODE_17_ +Pin 85 A_DECODE_23_ +Pin 96 A_DECODE_16_ Pin 68 IPL_2_ -Pin 56 IPL_1_ Pin 58 FC_1_ -Pin 67 IPL_0_ Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281 -Pin 57 FC_0_ Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203 Pin 98 DS_030 Comb ; S6=1 S9=1 Pair 101 Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185 Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191 -Pin 60 A1 Pin 14 nEXP_SPACE Pin 41 BERR Comb ; S6=1 S9=1 Pair 197 Pin 21 BG_030 +Pin 56 IPL_1_ +Pin 67 IPL_0_ Pin 28 BGACK_000 +Pin 57 FC_0_ Pin 64 CLK_030 +Pin 60 A_1_ Pin 11 CLK_000 Pin 61 CLK_OSZI Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 247 -Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 271 +Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 275 Pin 91 FPU_SENSE Pin 30 DTACK Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 Pin 66 E Comb ; S6=1 S9=1 Pair 251 Pin 36 VPA Pin 86 RST -Pin 3 RESET Comb ; S6=1 S9=1 Pair 127 +Pin 3 RESET Comb ; S6=1 S9=1 Pair 133 Pin 33 AMIGA_ADDR_ENABLE Comb ; S6=1 S9=1 Pair 181 -Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263 Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199 -Pin 5 A_30_ -Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 149 -Pin 6 A_29_ +Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 151 Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 179 -Pin 15 A_28_ Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 -Pin 16 A_27_ -Pin 17 A_26_ -Pin 18 A_25_ -Pin 19 A_24_ -Pin 85 A_23_ -Pin 84 A_22_ -Pin 94 A_21_ -Pin 93 A_20_ -Pin 97 A_19_ -Pin 95 A_18_ -Pin 59 A_17_ -Pin 96 A_16_ +Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263 +Pin 5 AHIGH_30_ Comb ; S6=1 S9=1 Pair 125 +Pin 6 AHIGH_29_ Comb ; S6=1 S9=1 Pair 145 +Pin 15 AHIGH_28_ Comb ; S6=1 S9=1 Pair 149 +Pin 16 AHIGH_27_ Comb ; S6=1 S9=1 Pair 155 +Pin 17 AHIGH_26_ Comb ; S6=1 S9=1 Pair 157 +Pin 18 AHIGH_25_ Comb ; S6=1 S9=1 Pair 167 +Pin 19 AHIGH_24_ Comb ; S6=1 S9=1 Pair 161 Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131 -Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143 -Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137 Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269 -Pin 69 A0 Reg ; S6=1 S9=1 Pair 257 +Pin 69 A_0_ Reg ; S6=1 S9=1 Pair 257 +Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 139 +Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137 Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175 -Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275 -Pin 10 CLK_EXP Reg ; S6=1 S9=1 Pair 125 +Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 278 +Pin 10 CLK_EXP Reg ; S6=1 S9=1 Pair 127 Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 283 Pin 35 VMA Reg ; S6=1 S9=1 Pair 173 Pin 71 RW Reg ; S6=1 S9=1 Pair 245 Node 287 RN_SIZE_1_ Comb ; S6=1 S9=1 +Node 143 RN_AHIGH_31_ Comb ; S6=1 S9=1 Node 281 RN_AS_030 Comb ; S6=1 S9=1 Node 203 RN_AS_000 Comb ; S6=1 S9=1 Node 185 RN_UDS_000 Comb ; S6=1 S9=1 Node 191 RN_LDS_000 Comb ; S6=1 S9=1 Node 197 RN_BERR Comb ; S6=1 S9=1 Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1 +Node 125 RN_AHIGH_30_ Comb ; S6=1 S9=1 +Node 145 RN_AHIGH_29_ Comb ; S6=1 S9=1 +Node 149 RN_AHIGH_28_ Comb ; S6=1 S9=1 +Node 155 RN_AHIGH_27_ Comb ; S6=1 S9=1 +Node 157 RN_AHIGH_26_ Comb ; S6=1 S9=1 +Node 167 RN_AHIGH_25_ Comb ; S6=1 S9=1 +Node 161 RN_AHIGH_24_ Comb ; S6=1 S9=1 Node 131 RN_IPL_030_2_ Reg ; S6=1 S9=1 -Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1 -Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1 Node 269 RN_RW_000 Reg ; S6=1 S9=1 -Node 257 RN_A0 Reg ; S6=1 S9=1 +Node 257 RN_A_0_ Reg ; S6=1 S9=1 +Node 139 RN_IPL_030_1_ Reg ; S6=1 S9=1 +Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1 Node 175 RN_BG_000 Reg ; S6=1 S9=1 -Node 275 RN_BGACK_030 Reg ; S6=1 S9=1 +Node 278 RN_BGACK_030 Reg ; S6=1 S9=1 Node 283 RN_DSACK1 Reg ; S6=1 S9=1 Node 173 RN_VMA Reg ; S6=1 S9=1 Node 245 RN_RW Reg ; S6=1 S9=1 -Node 242 N_317_i Comb ; S6=1 S9=1 -Node 193 cpu_est_2_ Reg ; S6=1 S9=1 -Node 239 cpu_est_3_ Reg ; S6=1 S9=1 -Node 182 cpu_est_0_ Reg ; S6=1 S9=1 -Node 176 cpu_est_1_ Reg ; S6=1 S9=1 -Node 151 inst_AS_000_INT Reg ; S6=1 S9=1 -Node 233 SM_AMIGA_5_ Reg ; S6=1 S9=1 -Node 128 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 -Node 274 inst_AS_030_D0 Reg ; S6=1 S9=1 -Node 113 inst_nEXP_SPACE_D0reg Reg ; S6=1 S9=1 -Node 155 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 242 N_226 Comb ; S6=1 S9=1 +Node 227 cpu_est_2_ Reg ; S6=1 S9=1 +Node 223 cpu_est_3_ Reg ; S6=1 S9=1 +Node 128 cpu_est_0_ Reg ; S6=1 S9=1 +Node 239 cpu_est_1_ Reg ; S6=1 S9=1 +Node 248 inst_AS_000_INT Reg ; S6=1 S9=1 +Node 140 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 +Node 271 inst_AS_030_D0 Reg ; S6=1 S9=1 +Node 169 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 Node 289 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 -Node 103 inst_AS_000_DMA Reg ; S6=1 S9=1 -Node 121 inst_DS_000_DMA Reg ; S6=1 S9=1 -Node 133 CYCLE_DMA_0_ Reg ; S6=1 S9=1 -Node 167 CYCLE_DMA_1_ Reg ; S6=1 S9=1 -Node 265 SIZE_DMA_0_ Reg ; S6=1 S9=1 -Node 259 SIZE_DMA_1_ Reg ; S6=1 S9=1 -Node 224 inst_VPA_D Reg ; S6=1 S9=1 -Node 115 inst_UDS_000_INT Reg ; S6=1 S9=1 -Node 109 inst_LDS_000_INT Reg ; S6=1 S9=1 -Node 119 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 -Node 148 inst_DTACK_D0 Reg ; S6=1 S9=1 +Node 119 inst_AS_000_DMA Reg ; S6=1 S9=1 +Node 115 inst_DS_000_DMA Reg ; S6=1 S9=1 +Node 116 CYCLE_DMA_0_ Reg ; S6=1 S9=1 +Node 104 CYCLE_DMA_1_ Reg ; S6=1 S9=1 +Node 259 SIZE_DMA_0_ Reg ; S6=1 S9=1 +Node 253 SIZE_DMA_1_ Reg ; S6=1 S9=1 +Node 109 inst_VPA_D Reg ; S6=1 S9=1 +Node 134 inst_UDS_000_INT Reg ; S6=1 S9=1 +Node 103 inst_LDS_000_INT Reg ; S6=1 S9=1 +Node 209 inst_CLK_OUT_PRE_D Reg ; S6=1 S9=1 +Node 268 CLK_000_D_10_ Reg ; S6=1 S9=1 +Node 284 CLK_000_D_11_ Reg ; S6=1 S9=1 +Node 172 inst_DTACK_D0 Reg ; S6=1 S9=1 Node 187 inst_RESET_OUT Reg ; S6=1 S9=1 -Node 241 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 -Node 209 CLK_000_D_1_ Reg ; S6=1 S9=1 -Node 139 CLK_000_D_0_ Reg ; S6=1 S9=1 -Node 253 inst_CLK_000_PE Reg ; S6=1 S9=1 -Node 268 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1 -Node 248 inst_CLK_000_NE Reg ; S6=1 S9=1 -Node 278 CLK_000_N_SYNC_11_ Reg ; S6=1 S9=1 -Node 262 IPL_D0_0_ Reg ; S6=1 S9=1 -Node 196 IPL_D0_1_ Reg ; S6=1 S9=1 -Node 142 IPL_D0_2_ Reg ; S6=1 S9=1 -Node 188 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1 -Node 223 SM_AMIGA_0_ Reg ; S6=1 S9=1 -Node 145 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 -Node 235 SM_AMIGA_4_ Reg ; S6=1 S9=1 -Node 161 inst_DS_000_ENABLE Reg ; S6=1 S9=1 -Node 178 RST_DLY_0_ Reg ; S6=1 S9=1 -Node 194 RST_DLY_1_ Reg ; S6=1 S9=1 -Node 184 RST_DLY_2_ Reg ; S6=1 S9=1 -Node 200 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1 -Node 136 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1 -Node 256 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1 -Node 217 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1 -Node 250 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1 +Node 200 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 +Node 158 CLK_000_D_1_ Reg ; S6=1 S9=1 +Node 265 CLK_000_D_0_ Reg ; S6=1 S9=1 +Node 113 CLK_000_P_SYNC_10_ Reg ; S6=1 S9=1 +Node 233 SM_AMIGA_5_ Reg ; S6=1 S9=1 +Node 196 IPL_D0_0_ Reg ; S6=1 S9=1 +Node 244 IPL_D0_1_ Reg ; S6=1 S9=1 +Node 148 IPL_D0_2_ Reg ; S6=1 S9=1 +Node 262 CLK_000_D_2_ Reg ; S6=1 S9=1 +Node 256 CLK_000_D_3_ Reg ; S6=1 S9=1 +Node 166 CLK_000_D_4_ Reg ; S6=1 S9=1 +Node 217 CLK_000_D_5_ Reg ; S6=1 S9=1 +Node 142 CLK_000_D_6_ Reg ; S6=1 S9=1 +Node 250 CLK_000_D_7_ Reg ; S6=1 S9=1 +Node 136 CLK_000_D_8_ Reg ; S6=1 S9=1 +Node 190 CLK_000_D_9_ Reg ; S6=1 S9=1 +Node 272 CLK_000_D_12_ Reg ; S6=1 S9=1 +Node 229 SM_AMIGA_0_ Reg ; S6=1 S9=1 +Node 176 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1 +Node 236 SM_AMIGA_4_ Reg ; S6=1 S9=1 +Node 235 inst_DS_000_ENABLE Reg ; S6=1 S9=1 +Node 193 CLK_000_N_SYNC_12_ Reg ; S6=1 S9=1 +Node 188 RST_DLY_0_ Reg ; S6=1 S9=1 +Node 182 RST_DLY_1_ Reg ; S6=1 S9=1 +Node 194 RST_DLY_2_ Reg ; S6=1 S9=1 +Node 184 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1 +Node 124 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1 +Node 238 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1 +Node 160 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1 +Node 118 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1 Node 266 CLK_000_P_SYNC_5_ Reg ; S6=1 S9=1 -Node 106 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1 -Node 130 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1 -Node 260 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1 -Node 211 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1 -Node 122 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1 -Node 146 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1 -Node 140 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1 -Node 134 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1 -Node 190 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1 -Node 254 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1 -Node 226 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1 -Node 116 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1 -Node 110 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1 -Node 272 CLK_000_N_SYNC_10_ Reg ; S6=1 S9=1 -Node 227 SM_AMIGA_6_ Reg ; S6=1 S9=1 -Node 104 inst_CLK_030_H Reg ; S6=1 S9=1 -Node 229 SM_AMIGA_1_ Reg ; S6=1 S9=1 -Node 230 SM_AMIGA_3_ Reg ; S6=1 S9=1 -Node 236 SM_AMIGA_2_ Reg ; S6=1 S9=1 +Node 260 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1 +Node 178 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1 +Node 112 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1 +Node 154 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1 +Node 211 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1 +Node 106 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1 +Node 232 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1 +Node 122 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1 +Node 110 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1 +Node 130 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1 +Node 254 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1 +Node 146 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1 +Node 226 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1 +Node 170 CLK_000_N_SYNC_10_ Reg ; S6=1 S9=1 +Node 164 CLK_000_N_SYNC_11_ Reg ; S6=1 S9=1 +Node 205 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1 +Node 152 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 +Node 163 SM_AMIGA_6_ Reg ; S6=1 S9=1 +Node 121 inst_CLK_030_H Reg ; S6=1 S9=1 +Node 241 SM_AMIGA_1_ Reg ; S6=1 S9=1 +Node 224 SM_AMIGA_3_ Reg ; S6=1 S9=1 +Node 230 SM_AMIGA_2_ Reg ; S6=1 S9=1 Node 221 SM_AMIGA_i_7_ Reg ; S6=1 S9=1 -Node 205 CIIN_0 Comb ; S6=1 S9=1 +Node 212 CIIN_0 Comb ; S6=1 S9=1 ; Unused Pins & Nodes ; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index ddce524..14669db 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Wed Aug 17 17:45:51 2016 -End : Wed Aug 17 17:45:51 2016 $$$ Elapsed time: 00:00:00 +Start: Fri Aug 19 00:20:46 2016 +End : Fri Aug 19 00:20:46 2016 $$$ Elapsed time: 00:00:00 =========================================================================== Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] @@ -21,18 +21,18 @@ Part [E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 13 | 13 => 100% | 8 | 8 => 100% | 33 | 26 => 78% - 1 | 16 | 16 | 16 => 100% | 8 | 8 => 100% | 33 | 27 => 81% - 2 | 16 | 5 | 5 => 100% | 8 | 7 => 87% | 33 | 26 => 78% - 3 | 16 | 16 | 16 => 100% | 8 | 8 => 100% | 33 | 27 => 81% - 4 | 16 | 9 | 9 => 100% | 8 | 4 => 50% | 33 | 32 => 96% - 5 | 16 | 13 | 13 => 100% | 8 | 5 => 62% | 33 | 28 => 84% - 6 | 16 | 16 | 16 => 100% | 8 | 7 => 87% | 33 | 25 => 75% - 7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 31 => 93% + 0 | 16 | 16 | 16 => 100% | 8 | 8 => 100% | 33 | 28 => 84% + 1 | 16 | 16 | 16 => 100% | 8 | 8 => 100% | 33 | 26 => 78% + 2 | 16 | 16 | 16 => 100% | 8 | 7 => 87% | 33 | 28 => 84% + 3 | 16 | 16 | 16 => 100% | 8 | 8 => 100% | 33 | 31 => 93% + 4 | 16 | 10 | 10 => 100% | 8 | 4 => 50% | 33 | 33 => 100% + 5 | 16 | 16 | 16 => 100% | 8 | 5 => 62% | 33 | 31 => 93% + 6 | 16 | 16 | 16 => 100% | 8 | 7 => 87% | 33 | 28 => 84% + 7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 32 => 96% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 27.75 => 84% + | Avg number of array inputs in used blocks : 29.63 => 89% -* Input/Clock Signal count: 32 -> placed: 32 = 100% +* Input/Clock Signal count: 24 -> placed: 24 = 100% Resources Available Used ----------------------------------------------------------------- @@ -41,13 +41,13 @@ _|____|____|____|_______________|____|_____________|___|________________ Clock Only Pins : 0 0 => 0% Clock/Input Pins : 4 4 => 100% Logic Blocks : 8 8 => 100% - Macrocells : 128 98 => 76% - PT Clusters : 128 55 => 42% - - Single PT Clusters : 128 53 => 41% + Macrocells : 128 116 => 90% + PT Clusters : 128 56 => 43% + - Single PT Clusters : 128 70 => 54% Input Registers : 0 * Routing Completion: 100% -* Attempts: Place [ 246] Route [ 0] +* Attempts: Place [ 1335] Route [ 1] =========================================================================== Signal Fanout Table =========================================================================== @@ -57,33 +57,33 @@ _|____|____|____|_______________|____|_____________|___|________________ | | | +- Signal-to-Pin Assignment | | | | Fanout to Logic Blocks Signal Name ___|__|__|____|____________________________________________________________ - 1| 6| IO| 69|=> 0...|....| A0 - |=> Paired w/: RN_A0 - 2| 5|INP| 60|=> .1..|....| A1 - 3| 3|OUT| 33|=> ....|....| AMIGA_ADDR_ENABLE - 4| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR - 5| 3|OUT| 34|=> ....|....| AMIGA_BUS_ENABLE_HIGH - 6| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW - 7| 4| IO| 42|=> 012.|4..7| AS_000 - 8| 7| IO| 82|=> ....|4..7| AS_030 - 9| 0|OUT| 92|=> ....|....| AVEC - 10| 0|INP| 96|=> ..2.|4..7| A_16_ - 11| 5|INP| 59|=> ..2.|4..7| A_17_ - 12| 0|INP| 95|=> ..2.|4..7| A_18_ - 13| 0|INP| 97|=> ..2.|4..7| A_19_ - 14| 0|INP| 93|=> ....|4...| A_20_ - 15| 0|INP| 94|=> ....|4...| A_21_ - 16| 7|INP| 84|=> ....|4...| A_22_ - 17| 7|INP| 85|=> ....|4...| A_23_ - 18| 2|INP| 19|=> ....|4...| A_24_ - 19| 2|INP| 18|=> ....|4...| A_25_ - 20| 2|INP| 17|=> ....|4...| A_26_ - 21| 2|INP| 16|=> ....|4...| A_27_ - 22| 2|INP| 15|=> ....|4...| A_28_ - 23| 1|INP| 6|=> ....|4...| A_29_ - 24| 1|INP| 5|=> ....|4...| A_30_ - 25| 1|INP| 4|=> ....|4...| A_31_ - 26| 4| IO| 41|=> ..2.|.5.7| BERR + 1| 2| IO| 19|=> ....|4...| AHIGH_24_ + 2| 2| IO| 18|=> ....|4...| AHIGH_25_ + 3| 2| IO| 17|=> ....|4...| AHIGH_26_ + 4| 2| IO| 16|=> ....|4...| AHIGH_27_ + 5| 2| IO| 15|=> ....|4...| AHIGH_28_ + 6| 1| IO| 6|=> ....|4...| AHIGH_29_ + 7| 1| IO| 5|=> ....|4...| AHIGH_30_ + 8| 1| IO| 4|=> ....|4...| AHIGH_31_ + 9| 3|OUT| 33|=> ....|....| AMIGA_ADDR_ENABLE + 10| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR + 11| 3|OUT| 34|=> ....|....| AMIGA_BUS_ENABLE_HIGH + 12| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW + 13| 4| IO| 42|=> 0...|4..7| AS_000 + 14| 7| IO| 82|=> ....|4..7| AS_030 + 15| 0|OUT| 92|=> ....|....| AVEC + 16| 6| IO| 69|=> 01..|....| A_0_ + |=> Paired w/: RN_A_0_ + 17| 5|INP| 60|=> .12.|....| A_1_ + 18| 0|INP| 96|=> ..2.|4..7| A_DECODE_16_ + 19| 5|INP| 59|=> ..2.|4..7| A_DECODE_17_ + 20| 0|INP| 95|=> ..2.|4..7| A_DECODE_18_ + 21| 0|INP| 97|=> ..2.|4..7| A_DECODE_19_ + 22| 0|INP| 93|=> ....|4...| A_DECODE_20_ + 23| 0|INP| 94|=> ....|4...| A_DECODE_21_ + 24| 7|INP| 84|=> ....|4...| A_DECODE_22_ + 25| 7|INP| 85|=> ....|4...| A_DECODE_23_ + 26| 4| IO| 41|=> ..2.|.567| BERR 27| 3|INP| 28|=> ....|4..7| BGACK_000 28| 7| IO| 83|=> ....|....| BGACK_030 |=> Paired w/: RN_BGACK_030 @@ -92,131 +92,141 @@ ___|__|__|____|____________________________________________________________ 30| 2|INP| 21|=> ...3|....| BG_030 31| 4|OUT| 47|=> ....|....| CIIN 32| 4|NOD| . |=> ....|4...| CIIN_0 - 33| +|INP| 11|=> .1..|....| CLK_000 - 34| 1|NOD| . |=> ...3|45..| CLK_000_D_0_ - 35| 4|NOD| . |=> ....|45..| CLK_000_D_1_ - 36| 4|NOD| . |=> 0...|....| CLK_000_N_SYNC_0_ - 37| 7|NOD| . |=> ....|...7| CLK_000_N_SYNC_10_ - 38| 7|NOD| . |=> ....|..6.| CLK_000_N_SYNC_11_ - 39| 0|NOD| . |=> .1..|....| CLK_000_N_SYNC_1_ - 40| 1|NOD| . |=> .1..|....| CLK_000_N_SYNC_2_ - 41| 1|NOD| . |=> .1..|....| CLK_000_N_SYNC_3_ - 42| 1|NOD| . |=> ...3|....| CLK_000_N_SYNC_4_ - 43| 3|NOD| . |=> ....|..6.| CLK_000_N_SYNC_5_ - 44| 6|NOD| . |=> ....|.5..| CLK_000_N_SYNC_6_ - 45| 5|NOD| . |=> 0...|....| CLK_000_N_SYNC_7_ - 46| 0|NOD| . |=> 0...|....| CLK_000_N_SYNC_8_ - 47| 0|NOD| . |=> ....|...7| CLK_000_N_SYNC_9_ - 48| 4|NOD| . |=> .1..|....| CLK_000_P_SYNC_0_ - 49| 1|NOD| . |=> ....|..6.| CLK_000_P_SYNC_1_ - 50| 6|NOD| . |=> ....|4...| CLK_000_P_SYNC_2_ - 51| 4|NOD| . |=> ....|..6.| CLK_000_P_SYNC_3_ - 52| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_4_ - 53| 6|NOD| . |=> 0...|....| CLK_000_P_SYNC_5_ - 54| 0|NOD| . |=> .1..|....| CLK_000_P_SYNC_6_ - 55| 1|NOD| . |=> ....|..6.| CLK_000_P_SYNC_7_ - 56| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_8_ - 57| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_9_ - 58| +|INP| 64|=> 0...|...7| CLK_030 - 59| 6|OUT| 65|=> ....|....| CLK_DIV_OUT - 60| 1|OUT| 10|=> ....|....| CLK_EXP - 61| +|Cin| 61|=> ....|....| CLK_OSZI - 62| 1|NOD| . |=> 012.|....| CYCLE_DMA_0_ - 63| 2|NOD| . |=> 0.2.|....| CYCLE_DMA_1_ - 64| 7| IO| 81|=> ....|....| DSACK1 + 33| +|INP| 11|=> ...3|..6.| CLK_000 + 34| 6|NOD| . |=> ..23|....| CLK_000_D_0_ + 35| 6|NOD| . |=> ....|...7| CLK_000_D_10_ + 36| 7|NOD| . |=> ....|...7| CLK_000_D_11_ + 37| 7|NOD| . |=> ....|...7| CLK_000_D_12_ + 38| 2|NOD| . |=> ...3|..6.| CLK_000_D_1_ + 39| 6|NOD| . |=> ....|..6.| CLK_000_D_2_ + 40| 6|NOD| . |=> ..2.|....| CLK_000_D_3_ + 41| 2|NOD| . |=> ....|4...| CLK_000_D_4_ + 42| 4|NOD| . |=> .1..|....| CLK_000_D_5_ + 43| 1|NOD| . |=> ....|..6.| CLK_000_D_6_ + 44| 6|NOD| . |=> .1..|....| CLK_000_D_7_ + 45| 1|NOD| . |=> ...3|....| CLK_000_D_8_ + 46| 3|NOD| . |=> ....|..6.| CLK_000_D_9_ + 47| 3|NOD| . |=> ..2.|45..| CLK_000_N_SYNC_0_ + 48| 2|NOD| . |=> ..2.|....| CLK_000_N_SYNC_10_ + 49| 2|NOD| . |=> ...3|....| CLK_000_N_SYNC_11_ + 50| 3|NOD| . |=> ...3|45..| CLK_000_N_SYNC_12_ + 51| 4|NOD| . |=> 0...|....| CLK_000_N_SYNC_1_ + 52| 0|NOD| . |=> ....|.5..| CLK_000_N_SYNC_2_ + 53| 5|NOD| . |=> 0...|....| CLK_000_N_SYNC_3_ + 54| 0|NOD| . |=> 0...|....| CLK_000_N_SYNC_4_ + 55| 0|NOD| . |=> .1..|....| CLK_000_N_SYNC_5_ + 56| 1|NOD| . |=> ....|..6.| CLK_000_N_SYNC_6_ + 57| 6|NOD| . |=> .1..|....| CLK_000_N_SYNC_7_ + 58| 1|NOD| . |=> ....|.5..| CLK_000_N_SYNC_8_ + 59| 5|NOD| . |=> ..2.|....| CLK_000_N_SYNC_9_ + 60| 3|NOD| . |=> 0...|....| CLK_000_P_SYNC_0_ + 61| 0|NOD| . |=> 0.23|.5.7| CLK_000_P_SYNC_10_ + 62| 0|NOD| . |=> ....|.5..| CLK_000_P_SYNC_1_ + 63| 5|NOD| . |=> ..2.|....| CLK_000_P_SYNC_2_ + 64| 2|NOD| . |=> 0...|....| CLK_000_P_SYNC_3_ + 65| 0|NOD| . |=> ....|..6.| CLK_000_P_SYNC_4_ + 66| 6|NOD| . |=> ....|..6.| CLK_000_P_SYNC_5_ + 67| 6|NOD| . |=> ...3|....| CLK_000_P_SYNC_6_ + 68| 3|NOD| . |=> 0...|....| CLK_000_P_SYNC_7_ + 69| 0|NOD| . |=> ..2.|....| CLK_000_P_SYNC_8_ + 70| 2|NOD| . |=> 0...|....| CLK_000_P_SYNC_9_ + 71| +|INP| 64|=> 0...|...7| CLK_030 + 72| 6|OUT| 65|=> ....|....| CLK_DIV_OUT + 73| 1|OUT| 10|=> ....|....| CLK_EXP + 74| +|Cin| 61|=> ....|....| CLK_OSZI + 75| 0|NOD| . |=> 0...|....| CYCLE_DMA_0_ + 76| 0|NOD| . |=> 0...|....| CYCLE_DMA_1_ + 77| 7| IO| 81|=> ....|....| DSACK1 |=> Paired w/: RN_DSACK1 - 65| 0|OUT| 98|=> ....|....| DS_030 - 66| 3|INP| 30|=> .1..|....| DTACK - 67| 6|OUT| 66|=> ....|....| E - 68| 5|INP| 57|=> ..2.|4..7| FC_0_ - 69| 5|INP| 58|=> ..2.|4..7| FC_1_ - 70| 7|OUT| 78|=> ....|....| FPU_CS - 71| 0|INP| 91|=> ....|4..7| FPU_SENSE - 72| 1| IO| 8|=> ....|....| IPL_030_0_ + 78| 0|OUT| 98|=> ....|....| DS_030 + 79| 3|INP| 30|=> ..2.|....| DTACK + 80| 6|OUT| 66|=> ....|....| E + 81| 5|INP| 57|=> ..2.|4..7| FC_0_ + 82| 5|INP| 58|=> ..2.|4..7| FC_1_ + 83| 7|OUT| 78|=> ....|....| FPU_CS + 84| 0|INP| 91|=> ....|4..7| FPU_SENSE + 85| 1| IO| 8|=> ....|....| IPL_030_0_ |=> Paired w/: RN_IPL_030_0_ - 73| 1| IO| 7|=> ....|....| IPL_030_1_ + 86| 1| IO| 7|=> ....|....| IPL_030_1_ |=> Paired w/: RN_IPL_030_1_ - 74| 1| IO| 9|=> ....|....| IPL_030_2_ + 87| 1| IO| 9|=> ....|....| IPL_030_2_ |=> Paired w/: RN_IPL_030_2_ - 75| 6|INP| 67|=> .1..|..6.| IPL_0_ - 76| 5|INP| 56|=> .1.3|....| IPL_1_ - 77| 6|INP| 68|=> .1..|....| IPL_2_ - 78| 6|NOD| . |=> .1..|....| IPL_D0_0_ - 79| 3|NOD| . |=> .1..|....| IPL_D0_1_ - 80| 1|NOD| . |=> .1..|....| IPL_D0_2_ - 81| 3| IO| 31|=> 0...|..6.| LDS_000 - 82| 5|NOD| . |=> ....|.5..| N_317_i - 83| 1|OUT| 3|=> ....|....| RESET - 84| 6|NOD| . |=> ....|..6.| RN_A0 - |=> Paired w/: A0 - 85| 7|NOD| . |=> 0123|4.67| RN_BGACK_030 + 88| 6|INP| 67|=> .1.3|....| IPL_0_ + 89| 5|INP| 56|=> .1..|.5..| IPL_1_ + 90| 6|INP| 68|=> .1..|....| IPL_2_ + 91| 3|NOD| . |=> .1..|....| IPL_D0_0_ + 92| 5|NOD| . |=> .1..|....| IPL_D0_1_ + 93| 1|NOD| . |=> .1..|....| IPL_D0_2_ + 94| 3| IO| 31|=> 0...|..6.| LDS_000 + 95| 5|NOD| . |=> ....|.5..| N_226 + 96| 1|OUT| 3|=> ....|....| RESET + 97| 6|NOD| . |=> ....|..6.| RN_A_0_ + |=> Paired w/: A_0_ + 98| 7|NOD| . |=> 0123|4.67| RN_BGACK_030 |=> Paired w/: BGACK_030 - 86| 3|NOD| . |=> ...3|....| RN_BG_000 + 99| 3|NOD| . |=> ...3|....| RN_BG_000 |=> Paired w/: BG_000 - 87| 7|NOD| . |=> ....|...7| RN_DSACK1 + 100| 7|NOD| . |=> ....|...7| RN_DSACK1 |=> Paired w/: DSACK1 - 88| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + 101| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ |=> Paired w/: IPL_030_0_ - 89| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + 102| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ |=> Paired w/: IPL_030_1_ - 90| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + 103| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ |=> Paired w/: IPL_030_2_ - 91| 6|NOD| . |=> ....|..6.| RN_RW + 104| 6|NOD| . |=> ....|..6.| RN_RW |=> Paired w/: RW - 92| 7|NOD| . |=> ....|...7| RN_RW_000 + 105| 7|NOD| . |=> ....|...7| RN_RW_000 |=> Paired w/: RW_000 - 93| 3|NOD| . |=> ...3|.5..| RN_VMA + 106| 3|NOD| . |=> ...3|.5..| RN_VMA |=> Paired w/: VMA - 94| +|INP| 86|=> 0123|.567| RST - 95| 3|NOD| . |=> ...3|....| RST_DLY_0_ - 96| 3|NOD| . |=> ...3|....| RST_DLY_1_ - 97| 3|NOD| . |=> ...3|....| RST_DLY_2_ - 98| 6| IO| 71|=> ..2.|...7| RW + 107| +|INP| 86|=> 0123|.567| RST + 108| 3|NOD| . |=> ...3|....| RST_DLY_0_ + 109| 3|NOD| . |=> ...3|....| RST_DLY_1_ + 110| 3|NOD| . |=> ...3|....| RST_DLY_2_ + 111| 6| IO| 71|=> ....|.5.7| RW |=> Paired w/: RN_RW - 99| 7| IO| 80|=> 0...|4.6.| RW_000 + 112| 7| IO| 80|=> 0...|4.6.| RW_000 |=> Paired w/: RN_RW_000 - 100| 6| IO| 70|=> 0...|....| SIZE_0_ - 101| 7| IO| 79|=> 0...|....| SIZE_1_ - 102| 6|NOD| . |=> ....|..67| SIZE_DMA_0_ - 103| 6|NOD| . |=> ....|..67| SIZE_DMA_1_ - 104| 5|NOD| . |=> ..2.|.5.7| SM_AMIGA_0_ - 105| 5|NOD| . |=> ....|.5.7| SM_AMIGA_1_ - 106| 5|NOD| . |=> ....|.5..| SM_AMIGA_2_ - 107| 5|NOD| . |=> ....|.5..| SM_AMIGA_3_ - 108| 5|NOD| . |=> ..2.|.5..| SM_AMIGA_4_ - 109| 5|NOD| . |=> ..2.|.5.7| SM_AMIGA_5_ - 110| 5|NOD| . |=> 0.2.|.5..| SM_AMIGA_6_ - 111| 5|NOD| . |=> ..23|.5.7| SM_AMIGA_i_7_ - 112| 3| IO| 32|=> 0...|..6.| UDS_000 - 113| 3| IO| 35|=> ....|....| VMA + 113| 6| IO| 70|=> 0...|....| SIZE_0_ + 114| 7| IO| 79|=> 0...|....| SIZE_1_ + 115| 6|NOD| . |=> ....|..67| SIZE_DMA_0_ + 116| 6|NOD| . |=> ....|..67| SIZE_DMA_1_ + 117| 5|NOD| . |=> ...3|.5.7| SM_AMIGA_0_ + 118| 5|NOD| . |=> ....|.5.7| SM_AMIGA_1_ + 119| 5|NOD| . |=> ....|.5..| SM_AMIGA_2_ + 120| 5|NOD| . |=> ....|.5..| SM_AMIGA_3_ + 121| 5|NOD| . |=> ....|.5..| SM_AMIGA_4_ + 122| 5|NOD| . |=> ....|.567| SM_AMIGA_5_ + 123| 2|NOD| . |=> 012.|.5..| SM_AMIGA_6_ + 124| 5|NOD| . |=> ..23|.5.7| SM_AMIGA_i_7_ + 125| 3| IO| 32|=> 0...|..6.| UDS_000 + 126| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 114| +|INP| 36|=> ....|.5..| VPA - 115| 3|NOD| . |=> ...3|.5..| cpu_est_0_ - 116| 3|NOD| . |=> ...3|.56.| cpu_est_1_ - 117| 3|NOD| . |=> ...3|.56.| cpu_est_2_ - 118| 5|NOD| . |=> ...3|.56.| cpu_est_3_ - 119| 1|NOD| . |=> .1.3|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH - 120| 1|NOD| . |=> .12.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW - 121| 0|NOD| . |=> 0...|...7| inst_AS_000_DMA - 122| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT - 123| 2|NOD| . |=> ..2.|.5..| inst_AS_030_000_SYNC - 124| 7|NOD| . |=> ..23|4..7| inst_AS_030_D0 - 125| 7|NOD| . |=> .12.|..6.| inst_BGACK_030_INT_D - 126| 6|NOD| . |=> ...3|.5..| inst_CLK_000_NE - 127| 3|NOD| . |=> ...3|.5..| inst_CLK_000_NE_D0 - 128| 6|NOD| . |=> .123|.5.7| inst_CLK_000_PE - 129| 0|NOD| . |=> 0...|....| inst_CLK_030_H - 130| 5|NOD| . |=> 0...|.5..| inst_CLK_OUT_PRE_50 - 131| 0|NOD| . |=> .1..|..67| inst_CLK_OUT_PRE_D - 132| 0|NOD| . |=> 0...|....| inst_DS_000_DMA - 133| 2|NOD| . |=> ..23|....| inst_DS_000_ENABLE - 134| 1|NOD| . |=> ....|.5..| inst_DTACK_D0 - 135| 0|NOD| . |=> 0..3|....| inst_LDS_000_INT - 136| 3|NOD| . |=> 01.3|4.67| inst_RESET_OUT - 137| 0|NOD| . |=> 0..3|....| inst_UDS_000_INT - 138| 5|NOD| . |=> ...3|.5..| inst_VPA_D - 139| 0|NOD| . |=> 0.23|4567| inst_nEXP_SPACE_D0reg - 140| +|INP| 14|=> 0...|....| nEXP_SPACE + 127| +|INP| 36|=> 0...|....| VPA + 128| 1|NOD| . |=> .1.3|.5..| cpu_est_0_ + 129| 5|NOD| . |=> ...3|.56.| cpu_est_1_ + 130| 5|NOD| . |=> ...3|.56.| cpu_est_2_ + 131| 5|NOD| . |=> ...3|.56.| cpu_est_3_ + 132| 2|NOD| . |=> ..23|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH + 133| 1|NOD| . |=> .12.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW + 134| 0|NOD| . |=> 0...|...7| inst_AS_000_DMA + 135| 6|NOD| . |=> ....|4.6.| inst_AS_000_INT + 136| 2|NOD| . |=> ..2.|.5..| inst_AS_030_000_SYNC + 137| 7|NOD| . |=> ..23|4567| inst_AS_030_D0 + 138| 7|NOD| . |=> .12.|..6.| inst_BGACK_030_INT_D + 139| 4|NOD| . |=> .1..|.5..| inst_CLK_000_NE_D0 + 140| 0|NOD| . |=> 0...|....| inst_CLK_030_H + 141| 4|NOD| . |=> ....|4...| inst_CLK_OUT_PRE_50 + 142| 4|NOD| . |=> .1..|..67| inst_CLK_OUT_PRE_D + 143| 0|NOD| . |=> 0...|....| inst_DS_000_DMA + 144| 5|NOD| . |=> ...3|.5..| inst_DS_000_ENABLE + 145| 2|NOD| . |=> ....|.5..| inst_DTACK_D0 + 146| 0|NOD| . |=> 0..3|....| inst_LDS_000_INT + 147| 3|NOD| . |=> 0123|4.67| inst_RESET_OUT + 148| 1|NOD| . |=> .1.3|....| inst_UDS_000_INT + 149| 0|NOD| . |=> ...3|.5..| inst_VPA_D + 150| +|INP| 14|=> 0123|4567| nEXP_SPACE --------------------------------------------------------------------------- =========================================================================== < E:/ispLEVER_Classic2_0/ispcpld/dat/mach4a/mach447a Device Pin Assignments > @@ -228,9 +238,9 @@ ____|_____|_________|______________________________________________________ 1 | GND | | | (pwr/test) 2 | JTAG | | | (pwr/test) 3 | I_O | 1_07|*| RESET - 4 | I_O | 1_06|*| A_31_ - 5 | I_O | 1_05|*| A_30_ - 6 | I_O | 1_04|*| A_29_ + 4 | I_O | 1_06|*| AHIGH_31_ + 5 | I_O | 1_05|*| AHIGH_30_ + 6 | I_O | 1_04|*| AHIGH_29_ 7 | I_O | 1_03|*| IPL_030_1_ 8 | I_O | 1_02|*| IPL_030_0_ 9 | I_O | 1_01|*| IPL_030_2_ @@ -239,11 +249,11 @@ ____|_____|_________|______________________________________________________ 12 | Vcc | | | (pwr/test) 13 | GND | | | (pwr/test) 14 | CkIn | |*| nEXP_SPACE - 15 | I_O | 2_00|*| A_28_ - 16 | I_O | 2_01|*| A_27_ - 17 | I_O | 2_02|*| A_26_ - 18 | I_O | 2_03|*| A_25_ - 19 | I_O | 2_04|*| A_24_ + 15 | I_O | 2_00|*| AHIGH_28_ + 16 | I_O | 2_01|*| AHIGH_27_ + 17 | I_O | 2_02|*| AHIGH_26_ + 18 | I_O | 2_03|*| AHIGH_25_ + 19 | I_O | 2_04|*| AHIGH_24_ 20 | I_O | 2_05|*| AMIGA_BUS_ENABLE_LOW 21 | I_O | 2_06|*| BG_030 22 | I_O | 2_07| | - @@ -283,8 +293,8 @@ ____|_____|_________|______________________________________________________ 56 | I_O | 5_04|*| IPL_1_ 57 | I_O | 5_03|*| FC_0_ 58 | I_O | 5_02|*| FC_1_ - 59 | I_O | 5_01|*| A_17_ - 60 | I_O | 5_00|*| A1 + 59 | I_O | 5_01|*| A_DECODE_17_ + 60 | I_O | 5_00|*| A_1_ 61 | CkIn | |*| CLK_OSZI 62 | Vcc | | | (pwr/test) 63 | GND | | | (pwr/test) @@ -293,7 +303,7 @@ ____|_____|_________|______________________________________________________ 66 | I_O | 6_01|*| E 67 | I_O | 6_02|*| IPL_0_ 68 | I_O | 6_03|*| IPL_2_ - 69 | I_O | 6_04|*| A0 + 69 | I_O | 6_04|*| A_0_ 70 | I_O | 6_05|*| SIZE_0_ 71 | I_O | 6_06|*| RW 72 | I_O | 6_07| | - @@ -308,8 +318,8 @@ ____|_____|_________|______________________________________________________ 81 | I_O | 7_04|*| DSACK1 82 | I_O | 7_03|*| AS_030 83 | I_O | 7_02|*| BGACK_030 - 84 | I_O | 7_01|*| A_22_ - 85 | I_O | 7_00|*| A_23_ + 84 | I_O | 7_01|*| A_DECODE_22_ + 85 | I_O | 7_00|*| A_DECODE_23_ 86 | Inp | |*| RST 87 | Vcc | | | (pwr/test) 88 | GND | | | (pwr/test) @@ -317,11 +327,11 @@ ____|_____|_________|______________________________________________________ 90 | Vcc | | | (pwr/test) 91 | I_O | 0_00|*| FPU_SENSE 92 | I_O | 0_01|*| AVEC - 93 | I_O | 0_02|*| A_20_ - 94 | I_O | 0_03|*| A_21_ - 95 | I_O | 0_04|*| A_18_ - 96 | I_O | 0_05|*| A_16_ - 97 | I_O | 0_06|*| A_19_ + 93 | I_O | 0_02|*| A_DECODE_20_ + 94 | I_O | 0_03|*| A_DECODE_21_ + 95 | I_O | 0_04|*| A_DECODE_18_ + 96 | I_O | 0_05|*| A_DECODE_16_ + 97 | I_O | 0_06|*| A_DECODE_19_ 98 | I_O | 0_07|*| DS_030 99 | GND | | | (pwr/test) 100 | GND | | | (pwr/test) @@ -336,22 +346,22 @@ ____|_____|_________|______________________________________________________ | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| DS_030|OUT| | S | 1 | 4 to [ 1]| 1 XOR to [ 0] for 1 PT sig - 1|inst_AS_000_DMA|NOD| | S | 7 | 4 to [ 1]| 1 XOR to [ 1] as logic PT - 2|inst_CLK_030_H|NOD| | S | 8 | 4 to [ 2]| 1 XOR to [ 2] as logic PT - 3|CLK_000_P_SYNC_6_|NOD| | S | 1 | 4 to [ 2]| 1 XOR to [ 3] for 1 PT sig + 0| DS_030|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1|inst_LDS_000_INT|NOD| | S | 3 | 4 to [ 1]| 1 XOR free + 2| CYCLE_DMA_1_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free + 3|CLK_000_N_SYNC_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig 4| AVEC|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5|inst_LDS_000_INT|NOD| | S | 3 | 4 to [ 5]| 1 XOR free - 6|CLK_000_N_SYNC_9_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig - 7| | ? | | S | | 4 free | 1 XOR free - 8|inst_nEXP_SPACE_D0reg|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9|inst_UDS_000_INT|NOD| | S | 2 | 4 to [ 9]| 1 XOR free -10|CLK_000_N_SYNC_8_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig -11| | ? | | S | | 4 free | 1 XOR free -12|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 to [13]| 1 XOR to [12] for 1 PT sig -13|inst_DS_000_DMA|NOD| | S | 9 | 4 to [13]| 1 XOR to [13] as logic PT -14|CLK_000_N_SYNC_1_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig -15| | ? | | S | | 4 free | 1 XOR free + 5| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 6|CLK_000_N_SYNC_5_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7|CLK_000_P_SYNC_8_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 8|CLK_000_P_SYNC_10_|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9|inst_DS_000_DMA|NOD| | S | 9 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +10| CYCLE_DMA_0_|NOD| | S | 2 | 4 to [10]| 1 XOR free +11|CLK_000_P_SYNC_4_|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [11] for 1 PT sig +12|inst_AS_000_DMA|NOD| | S | 7 | 4 to [12]| 1 XOR to [12] as logic PT +13|inst_CLK_030_H|NOD| | S | 8 | 4 to [12]| 1 XOR free +14|CLK_000_N_SYNC_4_|NOD| | S | 1 | 4 to [13]| 1 XOR to [14] for 1 PT sig +15|CLK_000_P_SYNC_1_|NOD| | S | 1 | 4 to [13]| 1 XOR to [15] for 1 PT sig --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Maximum PT Capacity @@ -363,22 +373,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| DS_030|OUT| | S | 1 |=> can support up to [ 1] logic PT(s) - 1|inst_AS_000_DMA|NOD| | S | 7 |=> can support up to [ 9] logic PT(s) - 2|inst_CLK_030_H|NOD| | S | 8 |=> can support up to [ 13] logic PT(s) - 3|CLK_000_P_SYNC_6_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) - 4| AVEC|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 5|inst_LDS_000_INT|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) - 6|CLK_000_N_SYNC_9_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 7| | ? | | S | |=> can support up to [ 13] logic PT(s) - 8|inst_nEXP_SPACE_D0reg|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 9|inst_UDS_000_INT|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) -10|CLK_000_N_SYNC_8_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) -11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) -13|inst_DS_000_DMA|NOD| | S | 9 |=> can support up to [ 18] logic PT(s) -14|CLK_000_N_SYNC_1_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) -15| | ? | | S | |=> can support up to [ 9] logic PT(s) + 0| DS_030|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) + 1|inst_LDS_000_INT|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) + 2| CYCLE_DMA_1_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) + 3|CLK_000_N_SYNC_2_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 4| AVEC|OUT| | S | 1 |=> can support up to [ 17] logic PT(s) + 5| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) + 6|CLK_000_N_SYNC_5_|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) + 7|CLK_000_P_SYNC_8_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 8|CLK_000_P_SYNC_10_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 9|inst_DS_000_DMA|NOD| | S | 9 |=> can support up to [ 13] logic PT(s) +10| CYCLE_DMA_0_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) +11|CLK_000_P_SYNC_4_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) +12|inst_AS_000_DMA|NOD| | S | 7 |=> can support up to [ 10] logic PT(s) +13|inst_CLK_030_H|NOD| | S | 8 |=> can support up to [ 8] logic PT(s) +14|CLK_000_N_SYNC_4_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) +15|CLK_000_P_SYNC_1_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Node-Pin Assignments @@ -389,21 +399,21 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| DS_030|OUT| | => | 5 6 ( 7) 0 | 96 97 ( 98) 91 - 1|inst_AS_000_DMA|NOD| | => | 5 6 7 0 | 96 97 98 91 - 2|inst_CLK_030_H|NOD| | => | 6 7 0 1 | 97 98 91 92 - 3|CLK_000_P_SYNC_6_|NOD| | => | 6 7 0 1 | 97 98 91 92 + 1|inst_LDS_000_INT|NOD| | => | 5 6 7 0 | 96 97 98 91 + 2| CYCLE_DMA_1_|NOD| | => | 6 7 0 1 | 97 98 91 92 + 3|CLK_000_N_SYNC_2_|NOD| | => | 6 7 0 1 | 97 98 91 92 4| AVEC|OUT| | => | 7 0 ( 1) 2 | 98 91 ( 92) 93 - 5|inst_LDS_000_INT|NOD| | => | 7 0 1 2 | 98 91 92 93 - 6|CLK_000_N_SYNC_9_|NOD| | => | 0 1 2 3 | 91 92 93 94 - 7| | | | => | 0 1 2 3 | 91 92 93 94 - 8|inst_nEXP_SPACE_D0reg|NOD| | => | 1 2 3 4 | 92 93 94 95 - 9|inst_UDS_000_INT|NOD| | => | 1 2 3 4 | 92 93 94 95 -10|CLK_000_N_SYNC_8_|NOD| | => | 2 3 4 5 | 93 94 95 96 -11| | | | => | 2 3 4 5 | 93 94 95 96 -12|inst_CLK_OUT_PRE_D|NOD| | => | 3 4 5 6 | 94 95 96 97 -13|inst_DS_000_DMA|NOD| | => | 3 4 5 6 | 94 95 96 97 -14|CLK_000_N_SYNC_1_|NOD| | => | 4 5 6 7 | 95 96 97 98 -15| | | | => | 4 5 6 7 | 95 96 97 98 + 5| inst_VPA_D|NOD| | => | 7 0 1 2 | 98 91 92 93 + 6|CLK_000_N_SYNC_5_|NOD| | => | 0 1 2 3 | 91 92 93 94 + 7|CLK_000_P_SYNC_8_|NOD| | => | 0 1 2 3 | 91 92 93 94 + 8|CLK_000_P_SYNC_10_|NOD| | => | 1 2 3 4 | 92 93 94 95 + 9|inst_DS_000_DMA|NOD| | => | 1 2 3 4 | 92 93 94 95 +10| CYCLE_DMA_0_|NOD| | => | 2 3 4 5 | 93 94 95 96 +11|CLK_000_P_SYNC_4_|NOD| | => | 2 3 4 5 | 93 94 95 96 +12|inst_AS_000_DMA|NOD| | => | 3 4 5 6 | 94 95 96 97 +13|inst_CLK_030_H|NOD| | => | 3 4 5 6 | 94 95 96 97 +14|CLK_000_N_SYNC_4_|NOD| | => | 4 5 6 7 | 95 96 97 98 +15|CLK_000_P_SYNC_1_|NOD| | => | 4 5 6 7 | 95 96 97 98 --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > IO-to-Node Pin Mapping @@ -416,11 +426,11 @@ _|_________________|__|_____|____________________|________________________ _|_________________|__|___|_____|___________________________________________ 0| FPU_SENSE|INP|*| 91| => | 0 1 2 3 4 5 6 7 1| AVEC|OUT|*| 92| => | 2 3 ( 4) 5 6 7 8 9 - 2| A_20_|INP|*| 93| => | 4 5 6 7 8 9 10 11 - 3| A_21_|INP|*| 94| => | 6 7 8 9 10 11 12 13 - 4| A_18_|INP|*| 95| => | 8 9 10 11 12 13 14 15 - 5| A_16_|INP|*| 96| => | 10 11 12 13 14 15 0 1 - 6| A_19_|INP|*| 97| => | 12 13 14 15 0 1 2 3 + 2| A_DECODE_20_|INP|*| 93| => | 4 5 6 7 8 9 10 11 + 3| A_DECODE_21_|INP|*| 94| => | 6 7 8 9 10 11 12 13 + 4| A_DECODE_18_|INP|*| 95| => | 8 9 10 11 12 13 14 15 + 5| A_DECODE_16_|INP|*| 96| => | 10 11 12 13 14 15 0 1 + 6| A_DECODE_19_|INP|*| 97| => | 12 13 14 15 0 1 2 3 7| DS_030|OUT|*| 98| => | 14 15 ( 0) 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== @@ -434,11 +444,11 @@ _|_________________|__|___|_____|___________________________________________ _|_________________|__|___|_____|__________________________________________ 0| FPU_SENSE|INP|*| 91| => | Input macrocell [ -] 1| AVEC|OUT|*| 92| => | Input macrocell [ -] - 2| A_20_|INP|*| 93| => | Input macrocell [ -] - 3| A_21_|INP|*| 94| => | Input macrocell [ -] - 4| A_18_|INP|*| 95| => | Input macrocell [ -] - 5| A_16_|INP|*| 96| => | Input macrocell [ -] - 6| A_19_|INP|*| 97| => | Input macrocell [ -] + 2| A_DECODE_20_|INP|*| 93| => | Input macrocell [ -] + 3| A_DECODE_21_|INP|*| 94| => | Input macrocell [ -] + 4| A_DECODE_18_|INP|*| 95| => | Input macrocell [ -] + 5| A_DECODE_16_|INP|*| 96| => | Input macrocell [ -] + 6| A_DECODE_19_|INP|*| 97| => | Input macrocell [ -] 7| DS_030|OUT|*| 98| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== @@ -453,42 +463,42 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 91|INP FPU_SENSE|*|*] [RegIn 0 |102| -| | ] [MCell 0 |101|OUT DS_030| | ] - [MCell 1 |103|NOD inst_AS_000_DMA| |*] + [MCell 1 |103|NOD inst_LDS_000_INT| |*] 1 [IOpin 1 | 92|OUT AVEC|*| ] [RegIn 1 |105| -| | ] - [MCell 2 |104|NOD inst_CLK_030_H| |*] - [MCell 3 |106|NOD CLK_000_P_SYNC_6_| |*] + [MCell 2 |104|NOD CYCLE_DMA_1_| |*] + [MCell 3 |106|NOD CLK_000_N_SYNC_2_| |*] - 2 [IOpin 2 | 93|INP A_20_|*|*] + 2 [IOpin 2 | 93|INP A_DECODE_20_|*|*] [RegIn 2 |108| -| | ] [MCell 4 |107|OUT AVEC| | ] - [MCell 5 |109|NOD inst_LDS_000_INT| |*] + [MCell 5 |109|NOD inst_VPA_D| |*] - 3 [IOpin 3 | 94|INP A_21_|*|*] + 3 [IOpin 3 | 94|INP A_DECODE_21_|*|*] [RegIn 3 |111| -| | ] - [MCell 6 |110|NOD CLK_000_N_SYNC_9_| |*] - [MCell 7 |112| -| | ] + [MCell 6 |110|NOD CLK_000_N_SYNC_5_| |*] + [MCell 7 |112|NOD CLK_000_P_SYNC_8_| |*] - 4 [IOpin 4 | 95|INP A_18_|*|*] + 4 [IOpin 4 | 95|INP A_DECODE_18_|*|*] [RegIn 4 |114| -| | ] - [MCell 8 |113|NOD inst_nEXP_SPACE_D0reg| |*] - [MCell 9 |115|NOD inst_UDS_000_INT| |*] + [MCell 8 |113|NOD CLK_000_P_SYNC_10_| |*] + [MCell 9 |115|NOD inst_DS_000_DMA| |*] - 5 [IOpin 5 | 96|INP A_16_|*|*] + 5 [IOpin 5 | 96|INP A_DECODE_16_|*|*] [RegIn 5 |117| -| | ] - [MCell 10 |116|NOD CLK_000_N_SYNC_8_| |*] - [MCell 11 |118| -| | ] + [MCell 10 |116|NOD CYCLE_DMA_0_| |*] + [MCell 11 |118|NOD CLK_000_P_SYNC_4_| |*] - 6 [IOpin 6 | 97|INP A_19_|*|*] + 6 [IOpin 6 | 97|INP A_DECODE_19_|*|*] [RegIn 6 |120| -| | ] - [MCell 12 |119|NOD inst_CLK_OUT_PRE_D| |*] - [MCell 13 |121|NOD inst_DS_000_DMA| |*] + [MCell 12 |119|NOD inst_AS_000_DMA| |*] + [MCell 13 |121|NOD inst_CLK_030_H| |*] 7 [IOpin 7 | 98|OUT DS_030|*| ] [RegIn 7 |123| -| | ] - [MCell 14 |122|NOD CLK_000_N_SYNC_1_| |*] - [MCell 15 |124| -| | ] + [MCell 14 |122|NOD CLK_000_N_SYNC_4_| |*] + [MCell 15 |124|NOD CLK_000_P_SYNC_1_| |*] --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Logic Array Fan-in @@ -496,37 +506,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 4 ( 69)| A0 +Mux00| IOPin 6 4 ( 69)| A_0_ Mux01| ... | ... -Mux02| Mcel 4 9 ( 211)| CLK_000_N_SYNC_0_ -Mux03| Mcel 0 8 ( 113)| inst_nEXP_SPACE_D0reg -Mux04| Mcel 2 12 ( 167)| CYCLE_DMA_1_ +Mux02| Mcel 4 9 ( 211)| CLK_000_N_SYNC_1_ +Mux03| Mcel 0 14 ( 122)| CLK_000_N_SYNC_4_ +Mux04| Input Pin ( 64)| CLK_030 Mux05| Input Pin ( 14)| nEXP_SPACE -Mux06| IOPin 7 5 ( 80)| RW_000 -Mux07| Mcel 5 3 ( 226)| CLK_000_N_SYNC_7_ +Mux06| Mcel 2 7 ( 160)| CLK_000_P_SYNC_3_ +Mux07| Mcel 3 9 ( 187)| inst_RESET_OUT Mux08| IOPin 3 3 ( 32)| UDS_000 -Mux09| Mcel 0 1 ( 103)| inst_AS_000_DMA -Mux10| Mcel 5 4 ( 227)| SM_AMIGA_6_ -Mux11| Mcel 6 14 ( 266)| CLK_000_P_SYNC_5_ -Mux12| Mcel 3 9 ( 187)| inst_RESET_OUT -Mux13| ... | ... -Mux14| Mcel 0 10 ( 116)| CLK_000_N_SYNC_8_ -Mux15| Mcel 5 13 ( 241)| inst_CLK_OUT_PRE_50 -Mux16| IOPin 4 1 ( 42)| AS_000 +Mux09| Mcel 3 3 ( 178)| CLK_000_P_SYNC_7_ +Mux10| Input Pin ( 36)| VPA +Mux11| ... | ... +Mux12| Mcel 2 3 ( 154)| CLK_000_P_SYNC_9_ +Mux13| Mcel 3 7 ( 184)| CLK_000_P_SYNC_0_ +Mux14| Mcel 0 10 ( 116)| CYCLE_DMA_0_ +Mux15| Mcel 0 12 ( 119)| inst_AS_000_DMA +Mux16| Mcel 5 7 ( 232)| CLK_000_N_SYNC_3_ Mux17| IOPin 6 5 ( 70)| SIZE_0_ -Mux18| Mcel 0 5 ( 109)| inst_LDS_000_INT -Mux19| Mcel 0 9 ( 115)| inst_UDS_000_INT -Mux20| Input Pin ( 64)| CLK_030 -Mux21| Input Pin ( 86)| RST -Mux22| Mcel 0 2 ( 104)| inst_CLK_030_H -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| IOPin 3 4 ( 31)| LDS_000 -Mux25| Mcel 0 13 ( 121)| inst_DS_000_DMA -Mux26| ... | ... -Mux27| IOPin 7 6 ( 79)| SIZE_1_ -Mux28| Mcel 1 5 ( 133)| CYCLE_DMA_0_ +Mux18| Mcel 0 8 ( 113)| CLK_000_P_SYNC_10_ +Mux19| Mcel 0 9 ( 115)| inst_DS_000_DMA +Mux20| IOPin 7 6 ( 79)| SIZE_1_ +Mux21| Mcel 0 1 ( 103)| inst_LDS_000_INT +Mux22| Mcel 0 2 ( 104)| CYCLE_DMA_1_ +Mux23| Mcel 2 9 ( 163)| SM_AMIGA_6_ +Mux24| Input Pin ( 86)| RST +Mux25| Mcel 0 13 ( 121)| inst_CLK_030_H +Mux26| IOPin 4 1 ( 42)| AS_000 +Mux27| IOPin 3 4 ( 31)| LDS_000 +Mux28| IOPin 7 5 ( 80)| RW_000 Mux29| ... | ... -Mux30| ... | ... +Mux30| Mcel 7 6 ( 278)| RN_BGACK_030 Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- @@ -540,22 +550,22 @@ Mux32| ... | ... | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1| RESET|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 | 4 to [ 2]| 1 XOR free - 3|CLK_000_P_SYNC_7_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 0| AHIGH_30_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2| cpu_est_0_|NOD| | S | 2 | 4 to [ 2]| 1 XOR free + 3|CLK_000_N_SYNC_6_|NOD| | S | 1 | 4 to [ 4]| 1 XOR to [ 3] for 1 PT sig 4| IPL_030_2_| IO| | S |10 | 4 to [ 4]| 1 XOR to [ 4] as logic PT - 5| CYCLE_DMA_0_|NOD| | S | 2 | 4 to [ 4]| 1 XOR to [ 4] as logic PT - 6|CLK_000_N_SYNC_4_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig - 7|CLK_000_P_SYNC_1_|NOD| | S | 1 | 4 to [ 5]| 1 XOR to [ 7] for 1 PT sig + 5| RESET|OUT| | S | 1 | 4 to [ 4]| 1 XOR to [ 5] for 1 PT sig + 6|inst_UDS_000_INT|NOD| | S | 2 | 4 to [ 6]| 1 XOR free + 7| CLK_000_D_8_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig 8| IPL_030_0_| IO| | S |10 | 4 to [ 8]| 1 XOR to [ 8] as logic PT - 9| CLK_000_D_0_|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig -10|CLK_000_N_SYNC_3_|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [10] for 1 PT sig -11| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig -12| IPL_030_1_| IO| | S |10 | 4 to [12]| 1 XOR to [12] as logic PT -13|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 | 4 to [12]| 1 XOR to [12] as logic PT -14|CLK_000_N_SYNC_2_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig -15| inst_DTACK_D0|NOD| | S | 1 | 4 to [13]| 1 XOR to [15] for 1 PT sig + 9| IPL_030_1_| IO| | S |10 | 4 to [ 8]| 1 XOR to [ 8] as logic PT +10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +11| CLK_000_D_6_|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +12| AHIGH_31_| IO| | S | 1 | 4 to [10]| 1 XOR to [12] for 1 PT sig +13| AHIGH_29_| IO| | S | 1 | 4 to [11]| 1 XOR to [13] for 1 PT sig +14|CLK_000_N_SYNC_8_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15| IPL_D0_2_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Maximum PT Capacity @@ -567,22 +577,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| CLK_EXP|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) - 1| RESET|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) - 2|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) - 3|CLK_000_P_SYNC_7_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) - 4| IPL_030_2_| IO| | S |10 |=> can support up to [ 18] logic PT(s) - 5| CYCLE_DMA_0_|NOD| | S | 2 |=> can support up to [ 8] logic PT(s) - 6|CLK_000_N_SYNC_4_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) - 7|CLK_000_P_SYNC_1_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) - 8| IPL_030_0_| IO| | S |10 |=> can support up to [ 13] logic PT(s) - 9| CLK_000_D_0_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) -10|CLK_000_N_SYNC_3_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) -11| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) -12| IPL_030_1_| IO| | S |10 |=> can support up to [ 18] logic PT(s) -13|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 8] logic PT(s) -14|CLK_000_N_SYNC_2_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) -15| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 0| AHIGH_30_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) + 1| CLK_EXP|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) + 2| cpu_est_0_|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) + 3|CLK_000_N_SYNC_6_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) + 4| IPL_030_2_| IO| | S |10 |=> can support up to [ 13] logic PT(s) + 5| RESET|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) + 6|inst_UDS_000_INT|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) + 7| CLK_000_D_8_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 8| IPL_030_0_| IO| | S |10 |=> can support up to [ 14] logic PT(s) + 9| IPL_030_1_| IO| | S |10 |=> can support up to [ 10] logic PT(s) +10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 |=> can support up to [ 4] logic PT(s) +11| CLK_000_D_6_|NOD| | S | 1 |=> can support up to [ 4] logic PT(s) +12| AHIGH_31_| IO| | S | 1 |=> can support up to [ 5] logic PT(s) +13| AHIGH_29_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) +14|CLK_000_N_SYNC_8_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) +15| IPL_D0_2_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Node-Pin Assignments @@ -592,22 +602,22 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 1] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) - 1| RESET|OUT| | => | 5 6 ( 7) 0 | 5 4 ( 3) 10 - 2|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 6 7 0 1 | 4 3 10 9 - 3|CLK_000_P_SYNC_7_|NOD| | => | 6 7 0 1 | 4 3 10 9 + 0| AHIGH_30_| IO| | => |( 5) 6 7 0 |( 5) 4 3 10 + 1| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) + 2| cpu_est_0_|NOD| | => | 6 7 0 1 | 4 3 10 9 + 3|CLK_000_N_SYNC_6_|NOD| | => | 6 7 0 1 | 4 3 10 9 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 - 5| CYCLE_DMA_0_|NOD| | => | 7 0 1 2 | 3 10 9 8 - 6|CLK_000_N_SYNC_4_|NOD| | => | 0 1 2 3 | 10 9 8 7 - 7|CLK_000_P_SYNC_1_|NOD| | => | 0 1 2 3 | 10 9 8 7 + 5| RESET|OUT| | => |( 7) 0 1 2 |( 3) 10 9 8 + 6|inst_UDS_000_INT|NOD| | => | 0 1 2 3 | 10 9 8 7 + 7| CLK_000_D_8_|NOD| | => | 0 1 2 3 | 10 9 8 7 8| IPL_030_0_| IO| | => | 1 ( 2) 3 4 | 9 ( 8) 7 6 - 9| CLK_000_D_0_|NOD| | => | 1 2 3 4 | 9 8 7 6 -10|CLK_000_N_SYNC_3_|NOD| | => | 2 3 4 5 | 8 7 6 5 -11| IPL_D0_2_|NOD| | => | 2 3 4 5 | 8 7 6 5 -12| IPL_030_1_| IO| | => |( 3) 4 5 6 |( 7) 6 5 4 -13|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 3 4 5 6 | 7 6 5 4 -14|CLK_000_N_SYNC_2_|NOD| | => | 4 5 6 7 | 6 5 4 3 -15| inst_DTACK_D0|NOD| | => | 4 5 6 7 | 6 5 4 3 + 9| IPL_030_1_| IO| | => | 1 2 ( 3) 4 | 9 8 ( 7) 6 +10|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 2 3 4 5 | 8 7 6 5 +11| CLK_000_D_6_|NOD| | => | 2 3 4 5 | 8 7 6 5 +12| AHIGH_31_| IO| | => | 3 4 5 ( 6)| 7 6 5 ( 4) +13| AHIGH_29_| IO| | => | 3 ( 4) 5 6 | 7 ( 6) 5 4 +14|CLK_000_N_SYNC_8_|NOD| | => | 4 5 6 7 | 6 5 4 3 +15| IPL_D0_2_|NOD| | => | 4 5 6 7 | 6 5 4 3 --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > IO-to-Node Pin Mapping @@ -618,14 +628,14 @@ _|_________________|__|_____|____________________|________________________ | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ - 0| CLK_EXP|OUT|*| 10| => | ( 0) 1 2 3 4 5 6 7 + 0| CLK_EXP|OUT|*| 10| => | 0 ( 1) 2 3 4 5 6 7 1| IPL_030_2_| IO|*| 9| => | 2 3 ( 4) 5 6 7 8 9 2| IPL_030_0_| IO|*| 8| => | 4 5 6 7 ( 8) 9 10 11 - 3| IPL_030_1_| IO|*| 7| => | 6 7 8 9 10 11 (12) 13 - 4| A_29_|INP|*| 6| => | 8 9 10 11 12 13 14 15 - 5| A_30_|INP|*| 5| => | 10 11 12 13 14 15 0 1 - 6| A_31_|INP|*| 4| => | 12 13 14 15 0 1 2 3 - 7| RESET|OUT|*| 3| => | 14 15 0 ( 1) 2 3 4 5 + 3| IPL_030_1_| IO|*| 7| => | 6 7 8 ( 9) 10 11 12 13 + 4| AHIGH_29_| IO|*| 6| => | 8 9 10 11 12 (13) 14 15 + 5| AHIGH_30_| IO|*| 5| => | 10 11 12 13 14 15 ( 0) 1 + 6| AHIGH_31_| IO|*| 4| => | (12) 13 14 15 0 1 2 3 + 7| RESET|OUT|*| 3| => | 14 15 0 1 2 3 4 ( 5) --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > IO/Node and IO/Input Macrocell Pairing Table @@ -643,9 +653,9 @@ _|_________________|__|___|_____|__________________________________________ | | | | | | IO paired w/ node [ RN_IPL_030_0_] 3| IPL_030_1_| IO|*| 7| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_IPL_030_1_] - 4| A_29_|INP|*| 6| => | Input macrocell [ -] - 5| A_30_|INP|*| 5| => | Input macrocell [ -] - 6| A_31_|INP|*| 4| => | Input macrocell [ -] + 4| AHIGH_29_| IO|*| 6| => | Input macrocell [ -] + 5| AHIGH_30_| IO|*| 5| => | Input macrocell [ -] + 6| AHIGH_31_| IO|*| 4| => | Input macrocell [ -] 7| RESET|OUT|*| 3| => | Input macrocell [ -] --------------------------------------------------------------------------- =========================================================================== @@ -659,43 +669,43 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 10|OUT CLK_EXP|*| ] [RegIn 0 |126| -| | ] - [MCell 0 |125|OUT CLK_EXP| | ] - [MCell 1 |127|OUT RESET| | ] + [MCell 0 |125| IO AHIGH_30_| | ] + [MCell 1 |127|OUT CLK_EXP| | ] 1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_] [RegIn 1 |129| -| | ] - [MCell 2 |128|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] - [MCell 3 |130|NOD CLK_000_P_SYNC_7_| |*] + [MCell 2 |128|NOD cpu_est_0_| |*] + [MCell 3 |130|NOD CLK_000_N_SYNC_6_| |*] 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] [RegIn 2 |132| -| | ] [MCell 4 |131|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] - [MCell 5 |133|NOD CYCLE_DMA_0_| |*] + [MCell 5 |133|OUT RESET| | ] 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] - [MCell 6 |134|NOD CLK_000_N_SYNC_4_| |*] - [MCell 7 |136|NOD CLK_000_P_SYNC_1_| |*] + [MCell 6 |134|NOD inst_UDS_000_INT| |*] + [MCell 7 |136|NOD CLK_000_D_8_| |*] - 4 [IOpin 4 | 6|INP A_29_|*|*] + 4 [IOpin 4 | 6| IO AHIGH_29_|*|*] [RegIn 4 |138| -| | ] [MCell 8 |137|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] - [MCell 9 |139|NOD CLK_000_D_0_| |*] + [MCell 9 |139|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] - 5 [IOpin 5 | 5|INP A_30_|*|*] + 5 [IOpin 5 | 5| IO AHIGH_30_|*|*] [RegIn 5 |141| -| | ] - [MCell 10 |140|NOD CLK_000_N_SYNC_3_| |*] - [MCell 11 |142|NOD IPL_D0_2_| |*] + [MCell 10 |140|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] + [MCell 11 |142|NOD CLK_000_D_6_| |*] - 6 [IOpin 6 | 4|INP A_31_|*|*] + 6 [IOpin 6 | 4| IO AHIGH_31_|*|*] [RegIn 6 |144| -| | ] - [MCell 12 |143|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] - [MCell 13 |145|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] + [MCell 12 |143| IO AHIGH_31_| | ] + [MCell 13 |145| IO AHIGH_29_| | ] 7 [IOpin 7 | 3|OUT RESET|*| ] [RegIn 7 |147| -| | ] - [MCell 14 |146|NOD CLK_000_N_SYNC_2_| |*] - [MCell 15 |148|NOD inst_DTACK_D0| |*] + [MCell 14 |146|NOD CLK_000_N_SYNC_8_| |*] + [MCell 15 |148|NOD IPL_D0_2_| |*] --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Logic Array Fan-in @@ -704,37 +714,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- Mux00| IOPin 6 2 ( 67)| IPL_0_ -Mux01| Mcel 1 12 ( 143)| RN_IPL_030_1_ -Mux02| Mcel 3 15 ( 196)| IPL_D0_1_ -Mux03| Input Pin ( 11)| CLK_000 +Mux01| ... | ... +Mux02| Mcel 3 15 ( 196)| IPL_D0_0_ +Mux03| Mcel 2 9 ( 163)| SM_AMIGA_6_ Mux04| IOPin 6 3 ( 68)| IPL_2_ -Mux05| ... | ... -Mux06| Mcel 0 3 ( 106)| CLK_000_P_SYNC_6_ -Mux07| Mcel 1 11 ( 142)| IPL_D0_2_ -Mux08| Mcel 1 8 ( 137)| RN_IPL_030_0_ -Mux09| Mcel 0 12 ( 119)| inst_CLK_OUT_PRE_D -Mux10| Mcel 1 2 ( 128)| inst_AMIGA_BUS_ENABLE_DMA_LOW -Mux11| IOPin 5 0 ( 60)| A1 -Mux12| Mcel 1 10 ( 140)| CLK_000_N_SYNC_3_ -Mux13| Mcel 6 11 ( 262)| IPL_D0_0_ -Mux14| IOPin 3 5 ( 30)| DTACK -Mux15| Mcel 4 2 ( 200)| CLK_000_P_SYNC_0_ -Mux16| IOPin 4 1 ( 42)| AS_000 -Mux17| ... | ... -Mux18| ... | ... -Mux19| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D -Mux20| Mcel 0 14 ( 122)| CLK_000_N_SYNC_1_ -Mux21| IOPin 5 4 ( 56)| IPL_1_ -Mux22| Mcel 6 5 ( 253)| inst_CLK_000_PE -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| Input Pin ( 86)| RST +Mux05| Mcel 6 6 ( 254)| CLK_000_N_SYNC_7_ +Mux06| Mcel 1 9 ( 139)| RN_IPL_030_1_ +Mux07| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D +Mux08| Mcel 1 15 ( 148)| IPL_D0_2_ +Mux09| ... | ... +Mux10| Mcel 1 2 ( 128)| cpu_est_0_ +Mux11| Mcel 1 6 ( 134)| inst_UDS_000_INT +Mux12| Mcel 1 10 ( 140)| inst_AMIGA_BUS_ENABLE_DMA_LOW +Mux13| Mcel 4 13 ( 217)| CLK_000_D_5_ +Mux14| Mcel 4 5 ( 205)| inst_CLK_000_NE_D0 +Mux15| Input Pin ( 14)| nEXP_SPACE +Mux16| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D +Mux17| Mcel 1 8 ( 137)| RN_IPL_030_0_ +Mux18| IOPin 6 4 ( 69)| A_0_ +Mux19| Mcel 5 15 ( 244)| IPL_D0_1_ +Mux20| ... | ... +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 0 6 ( 110)| CLK_000_N_SYNC_5_ +Mux23| IOPin 5 0 ( 60)| A_1_ +Mux24| Mcel 6 3 ( 250)| CLK_000_D_7_ Mux25| Mcel 3 9 ( 187)| inst_RESET_OUT Mux26| ... | ... Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ -Mux28| Mcel 1 13 ( 145)| inst_AMIGA_BUS_ENABLE_DMA_HIGH -Mux29| Mcel 1 14 ( 146)| CLK_000_N_SYNC_2_ -Mux30| ... | ... -Mux31| Mcel 1 5 ( 133)| CYCLE_DMA_0_ +Mux28| ... | ... +Mux29| ... | ... +Mux30| Mcel 7 6 ( 278)| RN_BGACK_030 +Mux31| IOPin 5 4 ( 56)| IPL_1_ Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -747,22 +757,22 @@ Mux32| ... | ... | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1|inst_AS_000_INT|NOD| | S | 2 | 4 to [ 1]| 1 XOR free - 2| | ? | | S | | 4 free | 1 XOR free - 3| | ? | | S | | 4 free | 1 XOR free - 4|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 4]| 1 XOR to [ 4] as logic PT - 5| | ? | | S | | 4 to [ 4]| 1 XOR free - 6| | ? | | S | | 4 free | 1 XOR free - 7| | ? | | S | | 4 free | 1 XOR free - 8|inst_DS_000_ENABLE|NOD| | S | 5 | 4 to [ 8]| 1 XOR to [ 8] as logic PT - 9| | ? | | S | | 4 free | 1 XOR free -10| | ? | | S | | 4 free | 1 XOR free -11| | ? | | S | | 4 free | 1 XOR free -12| CYCLE_DMA_1_|NOD| | S | 3 | 4 to [12]| 1 XOR free -13| | ? | | S | | 4 free | 1 XOR free -14| | ? | | S | | 4 free | 1 XOR free -15| | ? | | S | | 4 free | 1 XOR free + 0| AHIGH_28_| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 | 4 to [ 2]| 1 XOR free + 3|CLK_000_P_SYNC_9_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 4| AHIGH_27_| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 5| AHIGH_26_| IO| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 6| CLK_000_D_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7|CLK_000_P_SYNC_3_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 8| AHIGH_24_| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9| SM_AMIGA_6_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free +10|CLK_000_N_SYNC_11_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11| CLK_000_D_4_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig +12| AHIGH_25_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [13]| 1 XOR to [13] as logic PT +14|CLK_000_N_SYNC_10_|NOD| | S | 1 | 4 to [13]| 1 XOR to [14] for 1 PT sig +15| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Maximum PT Capacity @@ -774,22 +784,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) - 1|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) - 2| | ? | | S | |=> can support up to [ 10] logic PT(s) - 3| | ? | | S | |=> can support up to [ 10] logic PT(s) - 4|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 20] logic PT(s) - 5| | ? | | S | |=> can support up to [ 11] logic PT(s) - 6| | ? | | S | |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 15] logic PT(s) - 8|inst_DS_000_ENABLE|NOD| | S | 5 |=> can support up to [ 20] logic PT(s) - 9| | ? | | S | |=> can support up to [ 15] logic PT(s) -10| | ? | | S | |=> can support up to [ 15] logic PT(s) -11| | ? | | S | |=> can support up to [ 15] logic PT(s) -12| CYCLE_DMA_1_|NOD| | S | 3 |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 15] logic PT(s) -14| | ? | | S | |=> can support up to [ 15] logic PT(s) -15| | ? | | S | |=> can support up to [ 10] logic PT(s) + 0| AHIGH_28_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) + 1|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) + 2|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 17] logic PT(s) + 3|CLK_000_P_SYNC_9_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 4| AHIGH_27_| IO| | S | 1 |=> can support up to [ 17] logic PT(s) + 5| AHIGH_26_| IO| | S | 1 |=> can support up to [ 17] logic PT(s) + 6| CLK_000_D_1_|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) + 7|CLK_000_P_SYNC_3_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 8| AHIGH_24_| IO| | S | 1 |=> can support up to [ 13] logic PT(s) + 9| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 17] logic PT(s) +10|CLK_000_N_SYNC_11_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) +11| CLK_000_D_4_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) +12| AHIGH_25_| IO| | S | 1 |=> can support up to [ 9] logic PT(s) +13|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 17] logic PT(s) +14|CLK_000_N_SYNC_10_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) +15| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Node-Pin Assignments @@ -799,22 +809,22 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 2] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0|AMIGA_BUS_ENABLE_LOW|OUT| | => |( 5) 6 7 0 |( 20) 21 22 15 - 1|inst_AS_000_INT|NOD| | => | 5 6 7 0 | 20 21 22 15 - 2| | | | => | 6 7 0 1 | 21 22 15 16 - 3| | | | => | 6 7 0 1 | 21 22 15 16 - 4|inst_AS_030_000_SYNC|NOD| | => | 7 0 1 2 | 22 15 16 17 - 5| | | | => | 7 0 1 2 | 22 15 16 17 - 6| | | | => | 0 1 2 3 | 15 16 17 18 - 7| | | | => | 0 1 2 3 | 15 16 17 18 - 8|inst_DS_000_ENABLE|NOD| | => | 1 2 3 4 | 16 17 18 19 - 9| | | | => | 1 2 3 4 | 16 17 18 19 -10| | | | => | 2 3 4 5 | 17 18 19 20 -11| | | | => | 2 3 4 5 | 17 18 19 20 -12| CYCLE_DMA_1_|NOD| | => | 3 4 5 6 | 18 19 20 21 -13| | | | => | 3 4 5 6 | 18 19 20 21 -14| | | | => | 4 5 6 7 | 19 20 21 22 -15| | | | => | 4 5 6 7 | 19 20 21 22 + 0| AHIGH_28_| IO| | => | 5 6 7 ( 0)| 20 21 22 ( 15) + 1|AMIGA_BUS_ENABLE_LOW|OUT| | => |( 5) 6 7 0 |( 20) 21 22 15 + 2|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 6 7 0 1 | 21 22 15 16 + 3|CLK_000_P_SYNC_9_|NOD| | => | 6 7 0 1 | 21 22 15 16 + 4| AHIGH_27_| IO| | => | 7 0 ( 1) 2 | 22 15 ( 16) 17 + 5| AHIGH_26_| IO| | => | 7 0 1 ( 2)| 22 15 16 ( 17) + 6| CLK_000_D_1_|NOD| | => | 0 1 2 3 | 15 16 17 18 + 7|CLK_000_P_SYNC_3_|NOD| | => | 0 1 2 3 | 15 16 17 18 + 8| AHIGH_24_| IO| | => | 1 2 3 ( 4)| 16 17 18 ( 19) + 9| SM_AMIGA_6_|NOD| | => | 1 2 3 4 | 16 17 18 19 +10|CLK_000_N_SYNC_11_|NOD| | => | 2 3 4 5 | 17 18 19 20 +11| CLK_000_D_4_|NOD| | => | 2 3 4 5 | 17 18 19 20 +12| AHIGH_25_| IO| | => |( 3) 4 5 6 |( 18) 19 20 21 +13|inst_AS_030_000_SYNC|NOD| | => | 3 4 5 6 | 18 19 20 21 +14|CLK_000_N_SYNC_10_|NOD| | => | 4 5 6 7 | 19 20 21 22 +15| inst_DTACK_D0|NOD| | => | 4 5 6 7 | 19 20 21 22 --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > IO-to-Node Pin Mapping @@ -825,12 +835,12 @@ _|_________________|__|_____|____________________|________________________ | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ - 0| A_28_|INP|*| 15| => | 0 1 2 3 4 5 6 7 - 1| A_27_|INP|*| 16| => | 2 3 4 5 6 7 8 9 - 2| A_26_|INP|*| 17| => | 4 5 6 7 8 9 10 11 - 3| A_25_|INP|*| 18| => | 6 7 8 9 10 11 12 13 - 4| A_24_|INP|*| 19| => | 8 9 10 11 12 13 14 15 - 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | 10 11 12 13 14 15 ( 0) 1 + 0| AHIGH_28_| IO|*| 15| => | ( 0) 1 2 3 4 5 6 7 + 1| AHIGH_27_| IO|*| 16| => | 2 3 ( 4) 5 6 7 8 9 + 2| AHIGH_26_| IO|*| 17| => | 4 ( 5) 6 7 8 9 10 11 + 3| AHIGH_25_| IO|*| 18| => | 6 7 8 9 10 11 (12) 13 + 4| AHIGH_24_| IO|*| 19| => | ( 8) 9 10 11 12 13 14 15 + 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | 10 11 12 13 14 15 0 ( 1) 6| BG_030|INP|*| 21| => | 12 13 14 15 0 1 2 3 7| | | | 22| => | 14 15 0 1 2 3 4 5 --------------------------------------------------------------------------- @@ -843,11 +853,11 @@ _|_________________|__|___|_____|___________________________________________ | Sig Type--+ | | | | Signal Name | | | | Input Macrocell and Node Pairs _|_________________|__|___|_____|__________________________________________ - 0| A_28_|INP|*| 15| => | Input macrocell [ -] - 1| A_27_|INP|*| 16| => | Input macrocell [ -] - 2| A_26_|INP|*| 17| => | Input macrocell [ -] - 3| A_25_|INP|*| 18| => | Input macrocell [ -] - 4| A_24_|INP|*| 19| => | Input macrocell [ -] + 0| AHIGH_28_| IO|*| 15| => | Input macrocell [ -] + 1| AHIGH_27_| IO|*| 16| => | Input macrocell [ -] + 2| AHIGH_26_| IO|*| 17| => | Input macrocell [ -] + 3| AHIGH_25_| IO|*| 18| => | Input macrocell [ -] + 4| AHIGH_24_| IO|*| 19| => | Input macrocell [ -] 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | Input macrocell [ -] 6| BG_030|INP|*| 21| => | Input macrocell [ -] 7| | | | 22| => | Input macrocell [ -] @@ -861,45 +871,45 @@ IMX No. | +---- Block IO Pin or Macrocell Number | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell | | | | Sig Type | | +- Feedback Required (*) ---|-------|----|---|---|----------|------|-|------------------------------ - 0 [IOpin 0 | 15|INP A_28_|*|*] + 0 [IOpin 0 | 15| IO AHIGH_28_|*|*] [RegIn 0 |150| -| | ] - [MCell 0 |149|OUT AMIGA_BUS_ENABLE_LOW| | ] - [MCell 1 |151|NOD inst_AS_000_INT| |*] + [MCell 0 |149| IO AHIGH_28_| | ] + [MCell 1 |151|OUT AMIGA_BUS_ENABLE_LOW| | ] - 1 [IOpin 1 | 16|INP A_27_|*|*] + 1 [IOpin 1 | 16| IO AHIGH_27_|*|*] [RegIn 1 |153| -| | ] - [MCell 2 |152| -| | ] - [MCell 3 |154| -| | ] + [MCell 2 |152|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] + [MCell 3 |154|NOD CLK_000_P_SYNC_9_| |*] - 2 [IOpin 2 | 17|INP A_26_|*|*] + 2 [IOpin 2 | 17| IO AHIGH_26_|*|*] [RegIn 2 |156| -| | ] - [MCell 4 |155|NOD inst_AS_030_000_SYNC| |*] - [MCell 5 |157| -| | ] + [MCell 4 |155| IO AHIGH_27_| | ] + [MCell 5 |157| IO AHIGH_26_| | ] - 3 [IOpin 3 | 18|INP A_25_|*|*] + 3 [IOpin 3 | 18| IO AHIGH_25_|*|*] [RegIn 3 |159| -| | ] - [MCell 6 |158| -| | ] - [MCell 7 |160| -| | ] + [MCell 6 |158|NOD CLK_000_D_1_| |*] + [MCell 7 |160|NOD CLK_000_P_SYNC_3_| |*] - 4 [IOpin 4 | 19|INP A_24_|*|*] + 4 [IOpin 4 | 19| IO AHIGH_24_|*|*] [RegIn 4 |162| -| | ] - [MCell 8 |161|NOD inst_DS_000_ENABLE| |*] - [MCell 9 |163| -| | ] + [MCell 8 |161| IO AHIGH_24_| | ] + [MCell 9 |163|NOD SM_AMIGA_6_| |*] 5 [IOpin 5 | 20|OUT AMIGA_BUS_ENABLE_LOW|*| ] [RegIn 5 |165| -| | ] - [MCell 10 |164| -| | ] - [MCell 11 |166| -| | ] + [MCell 10 |164|NOD CLK_000_N_SYNC_11_| |*] + [MCell 11 |166|NOD CLK_000_D_4_| |*] 6 [IOpin 6 | 21|INP BG_030|*|*] [RegIn 6 |168| -| | ] - [MCell 12 |167|NOD CYCLE_DMA_1_| |*] - [MCell 13 |169| -| | ] + [MCell 12 |167| IO AHIGH_25_| | ] + [MCell 13 |169|NOD inst_AS_030_000_SYNC| |*] 7 [IOpin 7 | 22| -| | ] [RegIn 7 |171| -| | ] - [MCell 14 |170| -| | ] - [MCell 15 |172| -| | ] + [MCell 14 |170|NOD CLK_000_N_SYNC_10_| |*] + [MCell 15 |172|NOD inst_DTACK_D0| |*] --------------------------------------------------------------------------- =========================================================================== < Block [ 2] > Logic Array Fan-in @@ -907,38 +917,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux01| Mcel 2 1 ( 151)| inst_AS_000_INT -Mux02| Mcel 5 8 ( 233)| SM_AMIGA_5_ -Mux03| Mcel 0 8 ( 113)| inst_nEXP_SPACE_D0reg -Mux04| IOPin 0 4 ( 95)| A_18_ +Mux00| Input Pin ( 86)| RST +Mux01| IOPin 4 0 ( 41)| BERR +Mux02| Mcel 1 10 ( 140)| inst_AMIGA_BUS_ENABLE_DMA_LOW +Mux03| IOPin 5 0 ( 60)| A_1_ +Mux04| IOPin 0 4 ( 95)| A_DECODE_18_ Mux05| Mcel 5 0 ( 221)| SM_AMIGA_i_7_ -Mux06| IOPin 0 5 ( 96)| A_16_ -Mux07| Mcel 2 8 ( 161)| inst_DS_000_ENABLE -Mux08| IOPin 6 6 ( 71)| RW -Mux09| ... | ... -Mux10| Mcel 1 2 ( 128)| inst_AMIGA_BUS_ENABLE_DMA_LOW -Mux11| Mcel 7 3 ( 274)| inst_AS_030_D0 -Mux12| IOPin 0 6 ( 97)| A_19_ -Mux13| IOPin 5 1 ( 59)| A_17_ -Mux14| Mcel 2 4 ( 155)| inst_AS_030_000_SYNC -Mux15| Mcel 2 12 ( 167)| CYCLE_DMA_1_ -Mux16| IOPin 4 1 ( 42)| AS_000 -Mux17| IOPin 5 3 ( 57)| FC_0_ -Mux18| Mcel 5 9 ( 235)| SM_AMIGA_4_ +Mux06| IOPin 5 3 ( 57)| FC_0_ +Mux07| Mcel 3 9 ( 187)| inst_RESET_OUT +Mux08| IOPin 5 1 ( 59)| A_DECODE_17_ +Mux09| IOPin 3 5 ( 30)| DTACK +Mux10| Mcel 7 1 ( 271)| inst_AS_030_D0 +Mux11| IOPin 0 5 ( 96)| A_DECODE_16_ +Mux12| IOPin 5 2 ( 58)| FC_1_ +Mux13| Mcel 2 9 ( 163)| SM_AMIGA_6_ +Mux14| ... | ... +Mux15| Input Pin ( 14)| nEXP_SPACE +Mux16| Mcel 3 2 ( 176)| CLK_000_N_SYNC_0_ +Mux17| Mcel 5 3 ( 226)| CLK_000_N_SYNC_9_ +Mux18| Mcel 0 8 ( 113)| CLK_000_P_SYNC_10_ Mux19| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D -Mux20| IOPin 5 2 ( 58)| FC_1_ -Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 5 ( 253)| inst_CLK_000_PE +Mux20| Mcel 5 11 ( 238)| CLK_000_P_SYNC_2_ +Mux21| Mcel 7 6 ( 278)| RN_BGACK_030 +Mux22| Mcel 2 2 ( 152)| inst_AMIGA_BUS_ENABLE_DMA_HIGH Mux23| ... | ... Mux24| ... | ... -Mux25| IOPin 4 0 ( 41)| BERR -Mux26| ... | ... -Mux27| ... | ... -Mux28| Mcel 1 5 ( 133)| CYCLE_DMA_0_ -Mux29| Mcel 5 4 ( 227)| SM_AMIGA_6_ -Mux30| Mcel 5 1 ( 223)| SM_AMIGA_0_ -Mux31| ... | ... +Mux25| Mcel 6 13 ( 265)| CLK_000_D_0_ +Mux26| Mcel 6 7 ( 256)| CLK_000_D_3_ +Mux27| IOPin 0 6 ( 97)| A_DECODE_19_ +Mux28| Mcel 0 7 ( 112)| CLK_000_P_SYNC_8_ +Mux29| ... | ... +Mux30| Mcel 2 13 ( 169)| inst_AS_030_000_SYNC +Mux31| Mcel 2 14 ( 170)| CLK_000_N_SYNC_10_ Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -953,20 +963,20 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| VMA| IO| | S | 3 | 4 to [ 0]| 1 XOR free 1| BG_000| IO| | S | 2 | 4 to [ 1]| 1 XOR free - 2| cpu_est_1_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free - 3| RST_DLY_0_|NOD| | S | 3 | 4 to [ 3]| 1 XOR free - 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 | 4 to [ 4]| 1 XOR free + 2|CLK_000_N_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3|CLK_000_P_SYNC_7_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 3 | 4 to [ 4]| 1 XOR free 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6| cpu_est_0_|NOD| | S | 2 | 4 to [ 6]| 1 XOR free - 7| RST_DLY_2_|NOD| | S | 2 | 4 to [ 7]| 1 XOR free + 6| RST_DLY_1_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free + 7|CLK_000_P_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig 8| UDS_000| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig 9|inst_RESET_OUT|NOD| | S | 2 | 4 to [ 9]| 1 XOR free -10|inst_CLK_000_NE_D0|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig -11|CLK_000_N_SYNC_5_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig +10| RST_DLY_0_|NOD| | S | 3 | 4 to [10]| 1 XOR free +11| CLK_000_D_9_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig 12| LDS_000| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| cpu_est_2_|NOD| | S | 4 | 4 to [13]| 1 XOR free -14| RST_DLY_1_|NOD| | S | 4 | 4 to [14]| 1 XOR free -15| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig +13|CLK_000_N_SYNC_12_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +14| RST_DLY_2_|NOD| | S | 2 | 4 to [14]| 1 XOR free +15| IPL_D0_0_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Maximum PT Capacity @@ -978,22 +988,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| VMA| IO| | S | 3 |=> can support up to [ 5] logic PT(s) - 1| BG_000| IO| | S | 2 |=> can support up to [ 5] logic PT(s) - 2| cpu_est_1_|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) - 3| RST_DLY_0_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) - 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2 |=> can support up to [ 9] logic PT(s) - 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) - 6| cpu_est_0_|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) - 7| RST_DLY_2_|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) + 0| VMA| IO| | S | 3 |=> can support up to [ 9] logic PT(s) + 1| BG_000| IO| | S | 2 |=> can support up to [ 13] logic PT(s) + 2|CLK_000_N_SYNC_0_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 3|CLK_000_P_SYNC_7_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 3 |=> can support up to [ 13] logic PT(s) + 5|AMIGA_ADDR_ENABLE|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) + 6| RST_DLY_1_|NOD| | S | 4 |=> can support up to [ 17] logic PT(s) + 7|CLK_000_P_SYNC_0_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) 8| UDS_000| IO| | S | 1 |=> can support up to [ 9] logic PT(s) - 9|inst_RESET_OUT|NOD| | S | 2 |=> can support up to [ 17] logic PT(s) -10|inst_CLK_000_NE_D0|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) -11|CLK_000_N_SYNC_5_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) -12| LDS_000| IO| | S | 1 |=> can support up to [ 9] logic PT(s) -13| cpu_est_2_|NOD| | S | 4 |=> can support up to [ 13] logic PT(s) -14| RST_DLY_1_|NOD| | S | 4 |=> can support up to [ 9] logic PT(s) -15| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 9|inst_RESET_OUT|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) +10| RST_DLY_0_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) +11| CLK_000_D_9_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) +12| LDS_000| IO| | S | 1 |=> can support up to [ 13] logic PT(s) +13|CLK_000_N_SYNC_12_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) +14| RST_DLY_2_|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) +15| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Node-Pin Assignments @@ -1005,20 +1015,20 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| VMA| IO| | => | 5 6 7 ( 0)| 30 29 28 ( 35) 1| BG_000| IO| | => | 5 ( 6) 7 0 | 30 ( 29) 28 35 - 2| cpu_est_1_|NOD| | => | 6 7 0 1 | 29 28 35 34 - 3| RST_DLY_0_|NOD| | => | 6 7 0 1 | 29 28 35 34 + 2|CLK_000_N_SYNC_0_|NOD| | => | 6 7 0 1 | 29 28 35 34 + 3|CLK_000_P_SYNC_7_|NOD| | => | 6 7 0 1 | 29 28 35 34 4|AMIGA_BUS_ENABLE_HIGH|OUT| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 5|AMIGA_ADDR_ENABLE|OUT| | => | 7 0 1 ( 2)| 28 35 34 ( 33) - 6| cpu_est_0_|NOD| | => | 0 1 2 3 | 35 34 33 32 - 7| RST_DLY_2_|NOD| | => | 0 1 2 3 | 35 34 33 32 + 6| RST_DLY_1_|NOD| | => | 0 1 2 3 | 35 34 33 32 + 7|CLK_000_P_SYNC_0_|NOD| | => | 0 1 2 3 | 35 34 33 32 8| UDS_000| IO| | => | 1 2 ( 3) 4 | 34 33 ( 32) 31 9|inst_RESET_OUT|NOD| | => | 1 2 3 4 | 34 33 32 31 -10|inst_CLK_000_NE_D0|NOD| | => | 2 3 4 5 | 33 32 31 30 -11|CLK_000_N_SYNC_5_|NOD| | => | 2 3 4 5 | 33 32 31 30 +10| RST_DLY_0_|NOD| | => | 2 3 4 5 | 33 32 31 30 +11| CLK_000_D_9_|NOD| | => | 2 3 4 5 | 33 32 31 30 12| LDS_000| IO| | => | 3 ( 4) 5 6 | 32 ( 31) 30 29 -13| cpu_est_2_|NOD| | => | 3 4 5 6 | 32 31 30 29 -14| RST_DLY_1_|NOD| | => | 4 5 6 7 | 31 30 29 28 -15| IPL_D0_1_|NOD| | => | 4 5 6 7 | 31 30 29 28 +13|CLK_000_N_SYNC_12_|NOD| | => | 3 4 5 6 | 32 31 30 29 +14| RST_DLY_2_|NOD| | => | 4 5 6 7 | 31 30 29 28 +15| IPL_D0_0_|NOD| | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > IO-to-Node Pin Mapping @@ -1074,8 +1084,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 34|OUT AMIGA_BUS_ENABLE_HIGH|*| ] [RegIn 1 |177| -| | ] - [MCell 2 |176|NOD cpu_est_1_| |*] - [MCell 3 |178|NOD RST_DLY_0_| |*] + [MCell 2 |176|NOD CLK_000_N_SYNC_0_| |*] + [MCell 3 |178|NOD CLK_000_P_SYNC_7_| |*] 2 [IOpin 2 | 33|OUT AMIGA_ADDR_ENABLE|*| ] [RegIn 2 |180| -| | ] @@ -1084,8 +1094,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 3 [IOpin 3 | 32| IO UDS_000|*|*] [RegIn 3 |183| -| | ] - [MCell 6 |182|NOD cpu_est_0_| |*] - [MCell 7 |184|NOD RST_DLY_2_| |*] + [MCell 6 |182|NOD RST_DLY_1_| |*] + [MCell 7 |184|NOD CLK_000_P_SYNC_0_| |*] 4 [IOpin 4 | 31| IO LDS_000|*|*] [RegIn 4 |186| -| | ] @@ -1094,18 +1104,18 @@ IMX No. | +---- Block IO Pin or Macrocell Number 5 [IOpin 5 | 30|INP DTACK|*|*] [RegIn 5 |189| -| | ] - [MCell 10 |188|NOD inst_CLK_000_NE_D0| |*] - [MCell 11 |190|NOD CLK_000_N_SYNC_5_| |*] + [MCell 10 |188|NOD RST_DLY_0_| |*] + [MCell 11 |190|NOD CLK_000_D_9_| |*] 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] [RegIn 6 |192| -| | ] [MCell 12 |191| IO LDS_000| | ] - [MCell 13 |193|NOD cpu_est_2_| |*] + [MCell 13 |193|NOD CLK_000_N_SYNC_12_| |*] 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] - [MCell 14 |194|NOD RST_DLY_1_| |*] - [MCell 15 |196|NOD IPL_D0_1_| |*] + [MCell 14 |194|NOD RST_DLY_2_| |*] + [MCell 15 |196|NOD IPL_D0_0_| |*] --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Logic Array Fan-in @@ -1113,39 +1123,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux01| Mcel 5 12 ( 239)| cpu_est_3_ -Mux02| Mcel 3 1 ( 175)| RN_BG_000 -Mux03| Mcel 3 2 ( 176)| cpu_est_1_ -Mux04| IOPin 2 6 ( 21)| BG_030 +Mux00| Input Pin ( 86)| RST +Mux01| Mcel 5 9 ( 235)| inst_DS_000_ENABLE +Mux02| Mcel 0 5 ( 109)| inst_VPA_D +Mux03| Input Pin ( 11)| CLK_000 +Mux04| Mcel 3 6 ( 182)| RST_DLY_1_ Mux05| Mcel 5 0 ( 221)| SM_AMIGA_i_7_ -Mux06| Mcel 1 9 ( 139)| CLK_000_D_0_ -Mux07| Mcel 2 8 ( 161)| inst_DS_000_ENABLE -Mux08| Mcel 3 7 ( 184)| RST_DLY_2_ -Mux09| Mcel 3 3 ( 178)| RST_DLY_0_ -Mux10| Mcel 1 13 ( 145)| inst_AMIGA_BUS_ENABLE_DMA_HIGH -Mux11| Mcel 1 6 ( 134)| CLK_000_N_SYNC_4_ +Mux06| ... | ... +Mux07| Mcel 7 6 ( 278)| RN_BGACK_030 +Mux08| Mcel 2 10 ( 164)| CLK_000_N_SYNC_11_ +Mux09| Mcel 0 1 ( 103)| inst_LDS_000_INT +Mux10| Mcel 1 2 ( 128)| cpu_est_0_ +Mux11| Mcel 1 6 ( 134)| inst_UDS_000_INT Mux12| Mcel 3 9 ( 187)| inst_RESET_OUT Mux13| ... | ... -Mux14| ... | ... -Mux15| Mcel 5 2 ( 224)| inst_VPA_D -Mux16| Mcel 3 6 ( 182)| cpu_est_0_ -Mux17| Mcel 3 14 ( 194)| RST_DLY_1_ -Mux18| Mcel 7 3 ( 274)| inst_AS_030_D0 -Mux19| Mcel 0 9 ( 115)| inst_UDS_000_INT -Mux20| Mcel 3 10 ( 188)| inst_CLK_000_NE_D0 -Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 5 ( 253)| inst_CLK_000_PE -Mux23| Mcel 6 2 ( 248)| inst_CLK_000_NE -Mux24| ... | ... -Mux25| ... | ... +Mux14| Mcel 5 4 ( 227)| cpu_est_2_ +Mux15| Mcel 5 1 ( 223)| cpu_est_3_ +Mux16| IOPin 6 2 ( 67)| IPL_0_ +Mux17| Mcel 3 1 ( 175)| RN_BG_000 +Mux18| Mcel 2 6 ( 158)| CLK_000_D_1_ +Mux19| Mcel 7 1 ( 271)| inst_AS_030_D0 +Mux20| Mcel 3 10 ( 188)| RST_DLY_0_ +Mux21| Input Pin ( 14)| nEXP_SPACE +Mux22| Mcel 2 2 ( 152)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux23| IOPin 2 6 ( 21)| BG_030 +Mux24| Mcel 3 14 ( 194)| RST_DLY_2_ +Mux25| Mcel 6 13 ( 265)| CLK_000_D_0_ Mux26| Mcel 3 0 ( 173)| RN_VMA -Mux27| ... | ... -Mux28| Mcel 0 5 ( 109)| inst_LDS_000_INT -Mux29| Mcel 3 13 ( 193)| cpu_est_2_ -Mux30| Mcel 0 8 ( 113)| inst_nEXP_SPACE_D0reg -Mux31| IOPin 5 4 ( 56)| IPL_1_ -Mux32| ... | ... +Mux27| Mcel 5 5 ( 229)| SM_AMIGA_0_ +Mux28| Mcel 6 10 ( 260)| CLK_000_P_SYNC_6_ +Mux29| Mcel 3 13 ( 193)| CLK_000_N_SYNC_12_ +Mux30| Mcel 0 8 ( 113)| CLK_000_P_SYNC_10_ +Mux31| Mcel 5 12 ( 239)| cpu_est_1_ +Mux32| Mcel 1 7 ( 136)| CLK_000_D_8_ --------------------------------------------------------------------------- =========================================================================== < Block [ 4] > Macrocell (MCell) Cluster Assignments @@ -1159,18 +1169,18 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| BERR| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 | 4 to [ 1]| 1 XOR free - 2|CLK_000_P_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 2|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig 3| | ? | | S | | 4 free | 1 XOR free 4| AS_000| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5| CIIN_0|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 5|inst_CLK_000_NE_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| CLK_000_D_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig - 9|CLK_000_N_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig -10| | ? | | S | | 4 free | 1 XOR free + 8|inst_CLK_OUT_PRE_D|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9|CLK_000_N_SYNC_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig +10| CIIN_0|NOD| | S | 2 | 4 to [10]| 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| CIIN|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13|CLK_000_P_SYNC_3_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +13| CLK_000_D_5_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1186,18 +1196,18 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ _|_________________|__|__|___|_____|_______________________________________ 0| BERR| IO| | S | 1 |=> can support up to [ 9] logic PT(s) 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 |=> can support up to [ 18] logic PT(s) - 2|CLK_000_P_SYNC_0_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 3| | ? | | S | |=> can support up to [ 13] logic PT(s) - 4| AS_000| IO| | S | 1 |=> can support up to [ 15] logic PT(s) - 5| CIIN_0|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) - 6| | ? | | S | |=> can support up to [ 14] logic PT(s) + 2|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 17] logic PT(s) + 4| AS_000| IO| | S | 1 |=> can support up to [ 19] logic PT(s) + 5|inst_CLK_000_NE_D0|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 6| | ? | | S | |=> can support up to [ 18] logic PT(s) 7| | ? | | S | |=> can support up to [ 18] logic PT(s) - 8| CLK_000_D_1_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) - 9|CLK_000_N_SYNC_0_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) -10| | ? | | S | |=> can support up to [ 18] logic PT(s) -11| | ? | | S | |=> can support up to [ 18] logic PT(s) + 8|inst_CLK_OUT_PRE_D|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 9|CLK_000_N_SYNC_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +10| CIIN_0|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) +11| | ? | | S | |=> can support up to [ 13] logic PT(s) 12| CIIN|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) -13|CLK_000_P_SYNC_3_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +13| CLK_000_D_5_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) 14| | ? | | S | |=> can support up to [ 14] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- @@ -1211,18 +1221,18 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| BERR| IO| | => | 5 6 7 ( 0)| 46 47 48 ( 41) 1|AMIGA_BUS_DATA_DIR|OUT| | => | 5 6 ( 7) 0 | 46 47 ( 48) 41 - 2|CLK_000_P_SYNC_0_|NOD| | => | 6 7 0 1 | 47 48 41 42 + 2|inst_CLK_OUT_PRE_50|NOD| | => | 6 7 0 1 | 47 48 41 42 3| | | | => | 6 7 0 1 | 47 48 41 42 4| AS_000| IO| | => | 7 0 ( 1) 2 | 48 41 ( 42) 43 - 5| CIIN_0|NOD| | => | 7 0 1 2 | 48 41 42 43 + 5|inst_CLK_000_NE_D0|NOD| | => | 7 0 1 2 | 48 41 42 43 6| | | | => | 0 1 2 3 | 41 42 43 44 7| | | | => | 0 1 2 3 | 41 42 43 44 - 8| CLK_000_D_1_|NOD| | => | 1 2 3 4 | 42 43 44 45 - 9|CLK_000_N_SYNC_0_|NOD| | => | 1 2 3 4 | 42 43 44 45 -10| | | | => | 2 3 4 5 | 43 44 45 46 + 8|inst_CLK_OUT_PRE_D|NOD| | => | 1 2 3 4 | 42 43 44 45 + 9|CLK_000_N_SYNC_1_|NOD| | => | 1 2 3 4 | 42 43 44 45 +10| CIIN_0|NOD| | => | 2 3 4 5 | 43 44 45 46 11| | | | => | 2 3 4 5 | 43 44 45 46 12| CIIN|OUT| | => | 3 4 5 ( 6)| 44 45 46 ( 47) -13|CLK_000_P_SYNC_3_|NOD| | => | 3 4 5 6 | 44 45 46 47 +13| CLK_000_D_5_|NOD| | => | 3 4 5 6 | 44 45 46 47 14| | | | => | 4 5 6 7 | 45 46 47 48 15| | | | => | 4 5 6 7 | 45 46 47 48 --------------------------------------------------------------------------- @@ -1278,13 +1288,13 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 42| IO AS_000|*|*] [RegIn 1 |201| -| | ] - [MCell 2 |200|NOD CLK_000_P_SYNC_0_| |*] + [MCell 2 |200|NOD inst_CLK_OUT_PRE_50| |*] [MCell 3 |202| -| | ] 2 [IOpin 2 | 43| -| | ] [RegIn 2 |204| -| | ] [MCell 4 |203| IO AS_000| | ] - [MCell 5 |205|NOD CIIN_0| |*] + [MCell 5 |205|NOD inst_CLK_000_NE_D0| |*] 3 [IOpin 3 | 44| -| | ] [RegIn 3 |207| -| | ] @@ -1293,18 +1303,18 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 45| -| | ] [RegIn 4 |210| -| | ] - [MCell 8 |209|NOD CLK_000_D_1_| |*] - [MCell 9 |211|NOD CLK_000_N_SYNC_0_| |*] + [MCell 8 |209|NOD inst_CLK_OUT_PRE_D| |*] + [MCell 9 |211|NOD CLK_000_N_SYNC_1_| |*] 5 [IOpin 5 | 46| -| | ] [RegIn 5 |213| -| | ] - [MCell 10 |212| -| | ] + [MCell 10 |212|NOD CIIN_0| |*] [MCell 11 |214| -| | ] 6 [IOpin 6 | 47|OUT CIIN|*| ] [RegIn 6 |216| -| | ] [MCell 12 |215|OUT CIIN| | ] - [MCell 13 |217|NOD CLK_000_P_SYNC_3_| |*] + [MCell 13 |217|NOD CLK_000_D_5_| |*] 7 [IOpin 7 | 48|OUT AMIGA_BUS_DATA_DIR|*| ] [RegIn 7 |219| -| | ] @@ -1317,39 +1327,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux01| IOPin 1 6 ( 4)| A_31_ +Mux00| Mcel 2 11 ( 166)| CLK_000_D_4_ +Mux01| IOPin 5 2 ( 58)| FC_1_ Mux02| IOPin 4 1 ( 42)| AS_000 -Mux03| IOPin 2 3 ( 18)| A_25_ -Mux04| IOPin 3 7 ( 28)| BGACK_000 -Mux05| IOPin 2 4 ( 19)| A_24_ -Mux06| Mcel 1 9 ( 139)| CLK_000_D_0_ -Mux07| IOPin 2 0 ( 15)| A_28_ -Mux08| Mcel 6 7 ( 256)| CLK_000_P_SYNC_2_ -Mux09| IOPin 7 1 ( 84)| A_22_ -Mux10| Mcel 7 3 ( 274)| inst_AS_030_D0 -Mux11| IOPin 0 0 ( 91)| FPU_SENSE -Mux12| IOPin 0 6 ( 97)| A_19_ -Mux13| IOPin 1 4 ( 6)| A_29_ -Mux14| Mcel 4 5 ( 205)| CIIN_0 -Mux15| IOPin 0 3 ( 94)| A_21_ -Mux16| Mcel 4 8 ( 209)| CLK_000_D_1_ -Mux17| IOPin 2 2 ( 17)| A_26_ -Mux18| IOPin 7 0 ( 85)| A_23_ -Mux19| IOPin 1 5 ( 5)| A_30_ -Mux20| IOPin 5 2 ( 58)| FC_1_ -Mux21| IOPin 2 1 ( 16)| A_27_ -Mux22| Mcel 2 1 ( 151)| inst_AS_000_INT -Mux23| ... | ... +Mux03| IOPin 0 2 ( 93)| A_DECODE_20_ +Mux04| IOPin 1 4 ( 6)| AHIGH_29_ +Mux05| IOPin 2 4 ( 19)| AHIGH_24_ +Mux06| IOPin 0 6 ( 97)| A_DECODE_19_ +Mux07| Mcel 3 9 ( 187)| inst_RESET_OUT +Mux08| IOPin 0 0 ( 91)| FPU_SENSE +Mux09| IOPin 2 2 ( 17)| AHIGH_26_ +Mux10| Mcel 7 1 ( 271)| inst_AS_030_D0 +Mux11| IOPin 2 1 ( 16)| AHIGH_27_ +Mux12| Mcel 4 10 ( 212)| CIIN_0 +Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ +Mux14| IOPin 2 0 ( 15)| AHIGH_28_ +Mux15| Input Pin ( 14)| nEXP_SPACE +Mux16| Mcel 3 2 ( 176)| CLK_000_N_SYNC_0_ +Mux17| IOPin 0 4 ( 95)| A_DECODE_18_ +Mux18| IOPin 7 0 ( 85)| A_DECODE_23_ +Mux19| IOPin 7 3 ( 82)| AS_030 +Mux20| IOPin 7 1 ( 84)| A_DECODE_22_ +Mux21| IOPin 7 5 ( 80)| RW_000 +Mux22| IOPin 2 3 ( 18)| AHIGH_25_ +Mux23| Mcel 6 2 ( 248)| inst_AS_000_INT Mux24| IOPin 5 3 ( 57)| FC_0_ -Mux25| Mcel 3 9 ( 187)| inst_RESET_OUT -Mux26| IOPin 0 5 ( 96)| A_16_ -Mux27| IOPin 5 1 ( 59)| A_17_ -Mux28| IOPin 7 5 ( 80)| RW_000 -Mux29| IOPin 0 2 ( 93)| A_20_ -Mux30| Mcel 0 8 ( 113)| inst_nEXP_SPACE_D0reg -Mux31| IOPin 0 4 ( 95)| A_18_ -Mux32| IOPin 7 3 ( 82)| AS_030 +Mux25| IOPin 1 6 ( 4)| AHIGH_31_ +Mux26| IOPin 0 5 ( 96)| A_DECODE_16_ +Mux27| Mcel 4 2 ( 200)| inst_CLK_OUT_PRE_50 +Mux28| IOPin 1 5 ( 5)| AHIGH_30_ +Mux29| Mcel 3 13 ( 193)| CLK_000_N_SYNC_12_ +Mux30| Mcel 7 6 ( 278)| RN_BGACK_030 +Mux31| IOPin 0 3 ( 94)| A_DECODE_21_ +Mux32| IOPin 3 7 ( 28)| BGACK_000 --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Macrocell (MCell) Cluster Assignments @@ -1362,21 +1372,21 @@ Mux32| IOPin 7 3 ( 82)| AS_030 | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| SM_AMIGA_i_7_|NOD| | S |14 | 4 to [ 0]| 1 XOR to [ 0] as logic PT - 1| SM_AMIGA_0_|NOD| | S | 2 | 4 to [ 0]| 1 XOR to [ 0] as logic PT - 2| inst_VPA_D|NOD| | S | 1 | 4 to [ 0]| 1 XOR to [ 2] for 1 PT sig - 3|CLK_000_N_SYNC_7_|NOD| | S | 1 | 4 to [ 1]| 1 XOR to [ 3] for 1 PT sig - 4| SM_AMIGA_6_|NOD| | S | 3 | 4 to [ 4]| 1 XOR free - 5| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free - 6| SM_AMIGA_3_|NOD| | S | 5 | 4 to [ 6]| 1 XOR to [ 6] as logic PT - 7| | ? | | S | | 4 free | 1 XOR free + 1| cpu_est_3_|NOD| | S | 3 | 4 to [ 0]| 1 XOR to [ 0] as logic PT + 2| SM_AMIGA_3_|NOD| | S | 5 | 4 to [ 0]| 1 XOR free + 3|CLK_000_N_SYNC_9_|NOD| | S | 1 | 4 to [ 1]| 1 XOR to [ 3] for 1 PT sig + 4| cpu_est_2_|NOD| | S | 4 | 4 to [ 2]| 1 XOR to [ 2] as logic PT + 5| SM_AMIGA_0_|NOD| | S | 2 | 4 to [ 4]| 1 XOR free + 6| SM_AMIGA_2_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free + 7|CLK_000_N_SYNC_3_|NOD| | S | 1 | 4 to [ 5]| 1 XOR to [ 7] for 1 PT sig 8| SM_AMIGA_5_|NOD| | S | 3 | 4 to [ 8]| 1 XOR free - 9| SM_AMIGA_4_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free -10| SM_AMIGA_2_|NOD| | S | 4 | 4 to [10]| 1 XOR free -11| | ? | | S | | 4 free | 1 XOR free -12| cpu_est_3_|NOD| | S | 3 | 4 to [12]| 1 XOR free -13|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig -14| N_317_i|NOD| | S | 4 | 4 to [14]| 1 XOR free -15| | ? | | S | | 4 free | 1 XOR free + 9|inst_DS_000_ENABLE|NOD| | S | 5 | 4 to [ 9]| 1 XOR to [ 9] as logic PT +10| SM_AMIGA_4_|NOD| | S | 3 | 4 to [10]| 1 XOR free +11|CLK_000_P_SYNC_2_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig +12| cpu_est_1_|NOD| | S | 3 | 4 to [12]| 1 XOR free +13| SM_AMIGA_1_|NOD| | S | 3 | 4 to [13]| 1 XOR free +14| N_226|NOD| | S | 3 | 4 to [14]| 1 XOR free +15| IPL_D0_1_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Maximum PT Capacity @@ -1388,22 +1398,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| SM_AMIGA_i_7_|NOD| | S |14 |=> can support up to [ 14] logic PT(s) - 1| SM_AMIGA_0_|NOD| | S | 2 |=> can support up to [ 4] logic PT(s) - 2| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) - 3|CLK_000_N_SYNC_7_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) - 4| SM_AMIGA_6_|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) - 5| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) - 6| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 5] logic PT(s) - 8| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) - 9| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) -10| SM_AMIGA_2_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) -11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12| cpu_est_3_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) -13|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) -14| N_317_i|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) -15| | ? | | S | |=> can support up to [ 5] logic PT(s) + 0| SM_AMIGA_i_7_|NOD| | S |14 |=> can support up to [ 15] logic PT(s) + 1| cpu_est_3_|NOD| | S | 3 |=> can support up to [ 4] logic PT(s) + 2| SM_AMIGA_3_|NOD| | S | 5 |=> can support up to [ 5] logic PT(s) + 3|CLK_000_N_SYNC_9_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) + 4| cpu_est_2_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) + 5| SM_AMIGA_0_|NOD| | S | 2 |=> can support up to [ 4] logic PT(s) + 6| SM_AMIGA_2_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) + 7|CLK_000_N_SYNC_3_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) + 8| SM_AMIGA_5_|NOD| | S | 3 |=> can support up to [ 5] logic PT(s) + 9|inst_DS_000_ENABLE|NOD| | S | 5 |=> can support up to [ 9] logic PT(s) +10| SM_AMIGA_4_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) +11|CLK_000_P_SYNC_2_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) +12| cpu_est_1_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) +13| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) +14| N_226|NOD| | S | 3 |=> can support up to [ 9] logic PT(s) +15| IPL_D0_1_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Node-Pin Assignments @@ -1414,21 +1424,21 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| SM_AMIGA_i_7_|NOD| | => | 5 6 7 0 | 55 54 53 60 - 1| SM_AMIGA_0_|NOD| | => | 5 6 7 0 | 55 54 53 60 - 2| inst_VPA_D|NOD| | => | 6 7 0 1 | 54 53 60 59 - 3|CLK_000_N_SYNC_7_|NOD| | => | 6 7 0 1 | 54 53 60 59 - 4| SM_AMIGA_6_|NOD| | => | 7 0 1 2 | 53 60 59 58 - 5| SM_AMIGA_1_|NOD| | => | 7 0 1 2 | 53 60 59 58 - 6| SM_AMIGA_3_|NOD| | => | 0 1 2 3 | 60 59 58 57 - 7| | | | => | 0 1 2 3 | 60 59 58 57 + 1| cpu_est_3_|NOD| | => | 5 6 7 0 | 55 54 53 60 + 2| SM_AMIGA_3_|NOD| | => | 6 7 0 1 | 54 53 60 59 + 3|CLK_000_N_SYNC_9_|NOD| | => | 6 7 0 1 | 54 53 60 59 + 4| cpu_est_2_|NOD| | => | 7 0 1 2 | 53 60 59 58 + 5| SM_AMIGA_0_|NOD| | => | 7 0 1 2 | 53 60 59 58 + 6| SM_AMIGA_2_|NOD| | => | 0 1 2 3 | 60 59 58 57 + 7|CLK_000_N_SYNC_3_|NOD| | => | 0 1 2 3 | 60 59 58 57 8| SM_AMIGA_5_|NOD| | => | 1 2 3 4 | 59 58 57 56 - 9| SM_AMIGA_4_|NOD| | => | 1 2 3 4 | 59 58 57 56 -10| SM_AMIGA_2_|NOD| | => | 2 3 4 5 | 58 57 56 55 -11| | | | => | 2 3 4 5 | 58 57 56 55 -12| cpu_est_3_|NOD| | => | 3 4 5 6 | 57 56 55 54 -13|inst_CLK_OUT_PRE_50|NOD| | => | 3 4 5 6 | 57 56 55 54 -14| N_317_i|NOD| | => | 4 5 6 7 | 56 55 54 53 -15| | | | => | 4 5 6 7 | 56 55 54 53 + 9|inst_DS_000_ENABLE|NOD| | => | 1 2 3 4 | 59 58 57 56 +10| SM_AMIGA_4_|NOD| | => | 2 3 4 5 | 58 57 56 55 +11|CLK_000_P_SYNC_2_|NOD| | => | 2 3 4 5 | 58 57 56 55 +12| cpu_est_1_|NOD| | => | 3 4 5 6 | 57 56 55 54 +13| SM_AMIGA_1_|NOD| | => | 3 4 5 6 | 57 56 55 54 +14| N_226|NOD| | => | 4 5 6 7 | 56 55 54 53 +15| IPL_D0_1_|NOD| | => | 4 5 6 7 | 56 55 54 53 --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > IO-to-Node Pin Mapping @@ -1439,8 +1449,8 @@ _|_________________|__|_____|____________________|________________________ | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ - 0| A1|INP|*| 60| => | 0 1 2 3 4 5 6 7 - 1| A_17_|INP|*| 59| => | 2 3 4 5 6 7 8 9 + 0| A_1_|INP|*| 60| => | 0 1 2 3 4 5 6 7 + 1| A_DECODE_17_|INP|*| 59| => | 2 3 4 5 6 7 8 9 2| FC_1_|INP|*| 58| => | 4 5 6 7 8 9 10 11 3| FC_0_|INP|*| 57| => | 6 7 8 9 10 11 12 13 4| IPL_1_|INP|*| 56| => | 8 9 10 11 12 13 14 15 @@ -1457,8 +1467,8 @@ _|_________________|__|___|_____|___________________________________________ | Sig Type--+ | | | | Signal Name | | | | Input Macrocell and Node Pairs _|_________________|__|___|_____|__________________________________________ - 0| A1|INP|*| 60| => | Input macrocell [ -] - 1| A_17_|INP|*| 59| => | Input macrocell [ -] + 0| A_1_|INP|*| 60| => | Input macrocell [ -] + 1| A_DECODE_17_|INP|*| 59| => | Input macrocell [ -] 2| FC_1_|INP|*| 58| => | Input macrocell [ -] 3| FC_0_|INP|*| 57| => | Input macrocell [ -] 4| IPL_1_|INP|*| 56| => | Input macrocell [ -] @@ -1475,45 +1485,45 @@ IMX No. | +---- Block IO Pin or Macrocell Number | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell | | | | Sig Type | | +- Feedback Required (*) ---|-------|----|---|---|----------|------|-|------------------------------ - 0 [IOpin 0 | 60|INP A1|*|*] + 0 [IOpin 0 | 60|INP A_1_|*|*] [RegIn 0 |222| -| | ] [MCell 0 |221|NOD SM_AMIGA_i_7_| |*] - [MCell 1 |223|NOD SM_AMIGA_0_| |*] + [MCell 1 |223|NOD cpu_est_3_| |*] - 1 [IOpin 1 | 59|INP A_17_|*|*] + 1 [IOpin 1 | 59|INP A_DECODE_17_|*|*] [RegIn 1 |225| -| | ] - [MCell 2 |224|NOD inst_VPA_D| |*] - [MCell 3 |226|NOD CLK_000_N_SYNC_7_| |*] + [MCell 2 |224|NOD SM_AMIGA_3_| |*] + [MCell 3 |226|NOD CLK_000_N_SYNC_9_| |*] 2 [IOpin 2 | 58|INP FC_1_|*|*] [RegIn 2 |228| -| | ] - [MCell 4 |227|NOD SM_AMIGA_6_| |*] - [MCell 5 |229|NOD SM_AMIGA_1_| |*] + [MCell 4 |227|NOD cpu_est_2_| |*] + [MCell 5 |229|NOD SM_AMIGA_0_| |*] 3 [IOpin 3 | 57|INP FC_0_|*|*] [RegIn 3 |231| -| | ] - [MCell 6 |230|NOD SM_AMIGA_3_| |*] - [MCell 7 |232| -| | ] + [MCell 6 |230|NOD SM_AMIGA_2_| |*] + [MCell 7 |232|NOD CLK_000_N_SYNC_3_| |*] 4 [IOpin 4 | 56|INP IPL_1_|*|*] [RegIn 4 |234| -| | ] [MCell 8 |233|NOD SM_AMIGA_5_| |*] - [MCell 9 |235|NOD SM_AMIGA_4_| |*] + [MCell 9 |235|NOD inst_DS_000_ENABLE| |*] 5 [IOpin 5 | 55| -| | ] [RegIn 5 |237| -| | ] - [MCell 10 |236|NOD SM_AMIGA_2_| |*] - [MCell 11 |238| -| | ] + [MCell 10 |236|NOD SM_AMIGA_4_| |*] + [MCell 11 |238|NOD CLK_000_P_SYNC_2_| |*] 6 [IOpin 6 | 54| -| | ] [RegIn 6 |240| -| | ] - [MCell 12 |239|NOD cpu_est_3_| |*] - [MCell 13 |241|NOD inst_CLK_OUT_PRE_50| |*] + [MCell 12 |239|NOD cpu_est_1_| |*] + [MCell 13 |241|NOD SM_AMIGA_1_| |*] 7 [IOpin 7 | 53| -| | ] [RegIn 7 |243| -| | ] - [MCell 14 |242|NOD N_317_i| |*] - [MCell 15 |244| -| | ] + [MCell 14 |242|NOD N_226| |*] + [MCell 15 |244|NOD IPL_D0_1_| |*] --------------------------------------------------------------------------- =========================================================================== < Block [ 5] > Logic Array Fan-in @@ -1521,39 +1531,39 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST +Mux00| Mcel 2 13 ( 169)| inst_AS_030_000_SYNC Mux01| IOPin 4 0 ( 41)| BERR -Mux02| Mcel 5 10 ( 236)| SM_AMIGA_2_ -Mux03| Mcel 0 8 ( 113)| inst_nEXP_SPACE_D0reg -Mux04| Mcel 6 2 ( 248)| inst_CLK_000_NE -Mux05| Mcel 6 6 ( 254)| CLK_000_N_SYNC_6_ -Mux06| Mcel 5 13 ( 241)| inst_CLK_OUT_PRE_50 +Mux02| Mcel 5 8 ( 233)| SM_AMIGA_5_ +Mux03| Mcel 0 8 ( 113)| CLK_000_P_SYNC_10_ +Mux04| ... | ... +Mux05| Mcel 5 0 ( 221)| SM_AMIGA_i_7_ +Mux06| Mcel 5 13 ( 241)| SM_AMIGA_1_ Mux07| ... | ... -Mux08| Mcel 4 8 ( 209)| CLK_000_D_1_ -Mux09| Mcel 5 2 ( 224)| inst_VPA_D -Mux10| Mcel 5 4 ( 227)| SM_AMIGA_6_ -Mux11| Mcel 5 6 ( 230)| SM_AMIGA_3_ -Mux12| ... | ... -Mux13| Input Pin ( 36)| VPA -Mux14| Mcel 5 5 ( 229)| SM_AMIGA_1_ -Mux15| Mcel 5 1 ( 223)| SM_AMIGA_0_ -Mux16| Mcel 3 2 ( 176)| cpu_est_1_ -Mux17| Mcel 5 12 ( 239)| cpu_est_3_ -Mux18| Mcel 5 9 ( 235)| SM_AMIGA_4_ -Mux19| Mcel 1 15 ( 148)| inst_DTACK_D0 -Mux20| Mcel 3 10 ( 188)| inst_CLK_000_NE_D0 -Mux21| Mcel 3 13 ( 193)| cpu_est_2_ -Mux22| Mcel 6 5 ( 253)| inst_CLK_000_PE -Mux23| ... | ... -Mux24| Mcel 5 14 ( 242)| N_317_i -Mux25| Mcel 5 0 ( 221)| SM_AMIGA_i_7_ +Mux08| IOPin 6 6 ( 71)| RW +Mux09| Mcel 5 2 ( 224)| SM_AMIGA_3_ +Mux10| Mcel 5 4 ( 227)| cpu_est_2_ +Mux11| Mcel 5 6 ( 230)| SM_AMIGA_2_ +Mux12| Mcel 7 1 ( 271)| inst_AS_030_D0 +Mux13| Mcel 0 15 ( 124)| CLK_000_P_SYNC_1_ +Mux14| Mcel 4 5 ( 205)| inst_CLK_000_NE_D0 +Mux15| Input Pin ( 14)| nEXP_SPACE +Mux16| Mcel 3 2 ( 176)| CLK_000_N_SYNC_0_ +Mux17| Mcel 5 12 ( 239)| cpu_est_1_ +Mux18| Mcel 1 2 ( 128)| cpu_est_0_ +Mux19| Mcel 5 10 ( 236)| SM_AMIGA_4_ +Mux20| Mcel 1 14 ( 146)| CLK_000_N_SYNC_8_ +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 2 15 ( 172)| inst_DTACK_D0 +Mux23| Mcel 2 9 ( 163)| SM_AMIGA_6_ +Mux24| Mcel 5 14 ( 242)| N_226 +Mux25| Mcel 0 3 ( 106)| CLK_000_N_SYNC_2_ Mux26| Mcel 3 0 ( 173)| RN_VMA -Mux27| ... | ... -Mux28| ... | ... -Mux29| Mcel 2 4 ( 155)| inst_AS_030_000_SYNC -Mux30| Mcel 3 6 ( 182)| cpu_est_0_ -Mux31| Mcel 1 9 ( 139)| CLK_000_D_0_ -Mux32| Mcel 5 8 ( 233)| SM_AMIGA_5_ +Mux27| Mcel 5 5 ( 229)| SM_AMIGA_0_ +Mux28| Mcel 0 5 ( 109)| inst_VPA_D +Mux29| Mcel 3 13 ( 193)| CLK_000_N_SYNC_12_ +Mux30| Mcel 5 1 ( 223)| cpu_est_3_ +Mux31| IOPin 5 4 ( 56)| IPL_1_ +Mux32| Mcel 5 9 ( 235)| inst_DS_000_ENABLE --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Macrocell (MCell) Cluster Assignments @@ -1567,20 +1577,20 @@ Mux32| Mcel 5 8 ( 233)| SM_AMIGA_5_ _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| RW| IO| | S | 2 | 4 to [ 0]| 1 XOR free 1| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2|inst_CLK_000_NE|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig - 3|CLK_000_P_SYNC_4_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 2|inst_AS_000_INT|NOD| | S | 2 | 4 to [ 2]| 1 XOR free + 3| CLK_000_D_7_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig 4| E|OUT| | S | 2 | 4 to [ 4]| 1 XOR free - 5|inst_CLK_000_PE|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig - 6|CLK_000_N_SYNC_6_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig - 7|CLK_000_P_SYNC_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig - 8| A0| IO| | S | 3 | 4 to [ 8]| 1 XOR free - 9| SIZE_DMA_1_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free -10|CLK_000_P_SYNC_8_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig -11| IPL_D0_0_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig + 5| SIZE_DMA_1_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free + 6|CLK_000_N_SYNC_7_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7| CLK_000_D_3_|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 8| A_0_| IO| | S | 3 | 4 to [ 8]| 1 XOR free + 9| SIZE_DMA_0_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free +10|CLK_000_P_SYNC_6_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11| CLK_000_D_2_|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig 12| SIZE_0_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| SIZE_DMA_0_|NOD| | S | 3 | 4 to [13]| 1 XOR free +13| CLK_000_D_0_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig 14|CLK_000_P_SYNC_5_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig -15|CLK_000_P_SYNC_9_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig +15| CLK_000_D_10_|NOD| | S | 1 | 4 free | 1 XOR to [15] for 1 PT sig --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Maximum PT Capacity @@ -1592,22 +1602,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| RW| IO| | S | 2 |=> can support up to [ 13] logic PT(s) - 1| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) - 2|inst_CLK_000_NE|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) - 3|CLK_000_P_SYNC_4_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) - 4| E|OUT| | S | 2 |=> can support up to [ 17] logic PT(s) - 5|inst_CLK_000_PE|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) - 6|CLK_000_N_SYNC_6_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) - 7|CLK_000_P_SYNC_2_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) - 8| A0| IO| | S | 3 |=> can support up to [ 13] logic PT(s) - 9| SIZE_DMA_1_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) -10|CLK_000_P_SYNC_8_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) -11| IPL_D0_0_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) -12| SIZE_0_| IO| | S | 1 |=> can support up to [ 13] logic PT(s) -13| SIZE_DMA_0_|NOD| | S | 3 |=> can support up to [ 17] logic PT(s) -14|CLK_000_P_SYNC_5_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) -15|CLK_000_P_SYNC_9_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 0| RW| IO| | S | 2 |=> can support up to [ 9] logic PT(s) + 1| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 9] logic PT(s) + 2|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) + 3| CLK_000_D_7_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 4| E|OUT| | S | 2 |=> can support up to [ 13] logic PT(s) + 5| SIZE_DMA_1_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) + 6|CLK_000_N_SYNC_7_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 7| CLK_000_D_3_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 8| A_0_| IO| | S | 3 |=> can support up to [ 13] logic PT(s) + 9| SIZE_DMA_0_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) +10|CLK_000_P_SYNC_6_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) +11| CLK_000_D_2_|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) +12| SIZE_0_| IO| | S | 1 |=> can support up to [ 17] logic PT(s) +13| CLK_000_D_0_|NOD| | S | 1 |=> can support up to [ 17] logic PT(s) +14|CLK_000_P_SYNC_5_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) +15| CLK_000_D_10_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Node-Pin Assignments @@ -1619,20 +1629,20 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| RW| IO| | => | 5 ( 6) 7 0 | 70 ( 71) 72 65 1| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) - 2|inst_CLK_000_NE|NOD| | => | 6 7 0 1 | 71 72 65 66 - 3|CLK_000_P_SYNC_4_|NOD| | => | 6 7 0 1 | 71 72 65 66 + 2|inst_AS_000_INT|NOD| | => | 6 7 0 1 | 71 72 65 66 + 3| CLK_000_D_7_|NOD| | => | 6 7 0 1 | 71 72 65 66 4| E|OUT| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 - 5|inst_CLK_000_PE|NOD| | => | 7 0 1 2 | 72 65 66 67 - 6|CLK_000_N_SYNC_6_|NOD| | => | 0 1 2 3 | 65 66 67 68 - 7|CLK_000_P_SYNC_2_|NOD| | => | 0 1 2 3 | 65 66 67 68 - 8| A0| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69) - 9| SIZE_DMA_1_|NOD| | => | 1 2 3 4 | 66 67 68 69 -10|CLK_000_P_SYNC_8_|NOD| | => | 2 3 4 5 | 67 68 69 70 -11| IPL_D0_0_|NOD| | => | 2 3 4 5 | 67 68 69 70 + 5| SIZE_DMA_1_|NOD| | => | 7 0 1 2 | 72 65 66 67 + 6|CLK_000_N_SYNC_7_|NOD| | => | 0 1 2 3 | 65 66 67 68 + 7| CLK_000_D_3_|NOD| | => | 0 1 2 3 | 65 66 67 68 + 8| A_0_| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69) + 9| SIZE_DMA_0_|NOD| | => | 1 2 3 4 | 66 67 68 69 +10|CLK_000_P_SYNC_6_|NOD| | => | 2 3 4 5 | 67 68 69 70 +11| CLK_000_D_2_|NOD| | => | 2 3 4 5 | 67 68 69 70 12| SIZE_0_| IO| | => | 3 4 ( 5) 6 | 68 69 ( 70) 71 -13| SIZE_DMA_0_|NOD| | => | 3 4 5 6 | 68 69 70 71 +13| CLK_000_D_0_|NOD| | => | 3 4 5 6 | 68 69 70 71 14|CLK_000_P_SYNC_5_|NOD| | => | 4 5 6 7 | 69 70 71 72 -15|CLK_000_P_SYNC_9_|NOD| | => | 4 5 6 7 | 69 70 71 72 +15| CLK_000_D_10_|NOD| | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > IO-to-Node Pin Mapping @@ -1647,7 +1657,7 @@ _|_________________|__|___|_____|___________________________________________ 1| E|OUT|*| 66| => | 2 3 ( 4) 5 6 7 8 9 2| IPL_0_|INP|*| 67| => | 4 5 6 7 8 9 10 11 3| IPL_2_|INP|*| 68| => | 6 7 8 9 10 11 12 13 - 4| A0| IO|*| 69| => | ( 8) 9 10 11 12 13 14 15 + 4| A_0_| IO|*| 69| => | ( 8) 9 10 11 12 13 14 15 5| SIZE_0_| IO|*| 70| => | 10 11 (12) 13 14 15 0 1 6| RW| IO|*| 71| => | 12 13 14 15 ( 0) 1 2 3 7| | | | 72| => | 14 15 0 1 2 3 4 5 @@ -1665,8 +1675,8 @@ _|_________________|__|___|_____|__________________________________________ 1| E|OUT|*| 66| => | Input macrocell [ -] 2| IPL_0_|INP|*| 67| => | Input macrocell [ -] 3| IPL_2_|INP|*| 68| => | Input macrocell [ -] - 4| A0| IO|*| 69| => | Input macrocell [ -] - | | | | | | IO paired w/ node [ RN_A0] + 4| A_0_| IO|*| 69| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_A_0_] 5| SIZE_0_| IO|*| 70| => | Input macrocell [ -] 6| RW| IO|*| 71| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_RW] @@ -1688,38 +1698,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 66|OUT E|*| ] [RegIn 1 |249| -| | ] - [MCell 2 |248|NOD inst_CLK_000_NE| |*] - [MCell 3 |250|NOD CLK_000_P_SYNC_4_| |*] + [MCell 2 |248|NOD inst_AS_000_INT| |*] + [MCell 3 |250|NOD CLK_000_D_7_| |*] 2 [IOpin 2 | 67|INP IPL_0_|*|*] [RegIn 2 |252| -| | ] [MCell 4 |251|OUT E| | ] - [MCell 5 |253|NOD inst_CLK_000_PE| |*] + [MCell 5 |253|NOD SIZE_DMA_1_| |*] 3 [IOpin 3 | 68|INP IPL_2_|*|*] [RegIn 3 |255| -| | ] - [MCell 6 |254|NOD CLK_000_N_SYNC_6_| |*] - [MCell 7 |256|NOD CLK_000_P_SYNC_2_| |*] + [MCell 6 |254|NOD CLK_000_N_SYNC_7_| |*] + [MCell 7 |256|NOD CLK_000_D_3_| |*] - 4 [IOpin 4 | 69| IO A0|*|*] paired w/[ RN_A0] + 4 [IOpin 4 | 69| IO A_0_|*|*] paired w/[ RN_A_0_] [RegIn 4 |258| -| | ] - [MCell 8 |257|NOD RN_A0| |*] paired w/[ A0] - [MCell 9 |259|NOD SIZE_DMA_1_| |*] + [MCell 8 |257|NOD RN_A_0_| |*] paired w/[ A_0_] + [MCell 9 |259|NOD SIZE_DMA_0_| |*] 5 [IOpin 5 | 70| IO SIZE_0_|*|*] [RegIn 5 |261| -| | ] - [MCell 10 |260|NOD CLK_000_P_SYNC_8_| |*] - [MCell 11 |262|NOD IPL_D0_0_| |*] + [MCell 10 |260|NOD CLK_000_P_SYNC_6_| |*] + [MCell 11 |262|NOD CLK_000_D_2_| |*] 6 [IOpin 6 | 71| IO RW|*|*] paired w/[ RN_RW] [RegIn 6 |264| -| | ] [MCell 12 |263| IO SIZE_0_| | ] - [MCell 13 |265|NOD SIZE_DMA_0_| |*] + [MCell 13 |265|NOD CLK_000_D_0_| |*] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] [MCell 14 |266|NOD CLK_000_P_SYNC_5_| |*] - [MCell 15 |268|NOD CLK_000_P_SYNC_9_| |*] + [MCell 15 |268|NOD CLK_000_D_10_| |*] --------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Logic Array Fan-in @@ -1727,38 +1737,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 2 ( 67)| IPL_0_ -Mux01| Mcel 1 7 ( 136)| CLK_000_P_SYNC_1_ -Mux02| Mcel 6 15 ( 268)| CLK_000_P_SYNC_9_ -Mux03| Mcel 3 11 ( 190)| CLK_000_N_SYNC_5_ -Mux04| ... | ... -Mux05| Mcel 6 3 ( 250)| CLK_000_P_SYNC_4_ +Mux00| Mcel 6 0 ( 245)| RN_RW +Mux01| IOPin 4 0 ( 41)| BERR +Mux02| Mcel 5 8 ( 233)| SM_AMIGA_5_ +Mux03| Mcel 3 11 ( 190)| CLK_000_D_9_ +Mux04| Mcel 6 2 ( 248)| inst_AS_000_INT +Mux05| Mcel 1 3 ( 130)| CLK_000_N_SYNC_6_ Mux06| IOPin 7 5 ( 80)| RW_000 -Mux07| Mcel 7 6 ( 278)| CLK_000_N_SYNC_11_ -Mux08| IOPin 3 3 ( 32)| UDS_000 -Mux09| Mcel 6 13 ( 265)| SIZE_DMA_0_ -Mux10| Mcel 6 8 ( 257)| RN_A0 -Mux11| ... | ... -Mux12| Mcel 6 9 ( 259)| SIZE_DMA_1_ -Mux13| Mcel 4 13 ( 217)| CLK_000_P_SYNC_3_ -Mux14| ... | ... -Mux15| Mcel 0 12 ( 119)| inst_CLK_OUT_PRE_D -Mux16| Mcel 3 2 ( 176)| cpu_est_1_ -Mux17| Mcel 6 0 ( 245)| RN_RW -Mux18| Mcel 0 8 ( 113)| inst_nEXP_SPACE_D0reg -Mux19| Mcel 1 3 ( 130)| CLK_000_P_SYNC_7_ -Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux07| Mcel 1 11 ( 142)| CLK_000_D_6_ +Mux08| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D +Mux09| Mcel 6 11 ( 262)| CLK_000_D_2_ +Mux10| Mcel 5 1 ( 223)| cpu_est_3_ +Mux11| Mcel 6 14 ( 266)| CLK_000_P_SYNC_5_ +Mux12| Mcel 7 1 ( 271)| inst_AS_030_D0 +Mux13| Mcel 0 11 ( 118)| CLK_000_P_SYNC_4_ +Mux14| Input Pin ( 11)| CLK_000 +Mux15| Input Pin ( 14)| nEXP_SPACE +Mux16| ... | ... +Mux17| Mcel 5 12 ( 239)| cpu_est_1_ +Mux18| Mcel 2 6 ( 158)| CLK_000_D_1_ +Mux19| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D +Mux20| IOPin 3 3 ( 32)| UDS_000 Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 10 ( 260)| CLK_000_P_SYNC_8_ +Mux22| Mcel 6 5 ( 253)| SIZE_DMA_1_ Mux23| ... | ... Mux24| IOPin 3 4 ( 31)| LDS_000 Mux25| Mcel 3 9 ( 187)| inst_RESET_OUT Mux26| ... | ... -Mux27| ... | ... -Mux28| Mcel 7 13 ( 289)| inst_BGACK_030_INT_D -Mux29| Mcel 3 13 ( 193)| cpu_est_2_ -Mux30| ... | ... -Mux31| Mcel 5 12 ( 239)| cpu_est_3_ +Mux27| Mcel 6 9 ( 259)| SIZE_DMA_0_ +Mux28| Mcel 6 8 ( 257)| RN_A_0_ +Mux29| Mcel 5 4 ( 227)| cpu_est_2_ +Mux30| Mcel 7 6 ( 278)| RN_BGACK_030 +Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -1772,16 +1782,16 @@ Mux32| ... | ... | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| RW_000| IO| | S | 3 | 4 to [ 0]| 1 XOR free - 1| FPU_CS|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2|CLK_000_N_SYNC_10_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig - 3|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig - 4| BGACK_030| IO| | S | 3 | 4 to [ 4]| 1 XOR free + 1|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2| CLK_000_D_12_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 free | 1 XOR free + 4| FPU_CS|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig 5| | ? | | S | | 4 free | 1 XOR free - 6|CLK_000_N_SYNC_11_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 6| BGACK_030| IO| | S | 3 | 4 to [ 6]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| AS_030| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig 9| DSACK1| IO| | S | 4 | 4 to [ 9]| 1 XOR free -10| | ? | | S | | 4 free | 1 XOR free +10| CLK_000_D_11_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig 11| | ? | | S | | 4 free | 1 XOR free 12| SIZE_1_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig 13|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig @@ -1799,17 +1809,17 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ 0| RW_000| IO| | S | 3 |=> can support up to [ 13] logic PT(s) - 1| FPU_CS|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) - 2|CLK_000_N_SYNC_10_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) - 3|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 4| BGACK_030| IO| | S | 3 |=> can support up to [ 18] logic PT(s) + 1|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 2| CLK_000_D_12_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 3| | ? | | S | |=> can support up to [ 18] logic PT(s) + 4| FPU_CS|OUT| | S | 1 |=> can support up to [ 15] logic PT(s) 5| | ? | | S | |=> can support up to [ 14] logic PT(s) - 6|CLK_000_N_SYNC_11_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) - 7| | ? | | S | |=> can support up to [ 13] logic PT(s) - 8| AS_030| IO| | S | 1 |=> can support up to [ 15] logic PT(s) - 9| DSACK1| IO| | S | 4 |=> can support up to [ 19] logic PT(s) -10| | ? | | S | |=> can support up to [ 14] logic PT(s) -11| | ? | | S | |=> can support up to [ 18] logic PT(s) + 6| BGACK_030| IO| | S | 3 |=> can support up to [ 19] logic PT(s) + 7| | ? | | S | |=> can support up to [ 9] logic PT(s) + 8| AS_030| IO| | S | 1 |=> can support up to [ 14] logic PT(s) + 9| DSACK1| IO| | S | 4 |=> can support up to [ 18] logic PT(s) +10| CLK_000_D_11_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 17] logic PT(s) 12| SIZE_1_| IO| | S | 1 |=> can support up to [ 19] logic PT(s) 13|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) 14| | ? | | S | |=> can support up to [ 14] logic PT(s) @@ -1824,16 +1834,16 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| RW_000| IO| | => |( 5) 6 7 0 |( 80) 79 78 85 - 1| FPU_CS|OUT| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85 - 2|CLK_000_N_SYNC_10_|NOD| | => | 6 7 0 1 | 79 78 85 84 - 3|inst_AS_030_D0|NOD| | => | 6 7 0 1 | 79 78 85 84 - 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) + 1|inst_AS_030_D0|NOD| | => | 5 6 7 0 | 80 79 78 85 + 2| CLK_000_D_12_|NOD| | => | 6 7 0 1 | 79 78 85 84 + 3| | | | => | 6 7 0 1 | 79 78 85 84 + 4| FPU_CS|OUT| | => |( 7) 0 1 2 |( 78) 85 84 83 5| | | | => | 7 0 1 2 | 78 85 84 83 - 6|CLK_000_N_SYNC_11_|NOD| | => | 0 1 2 3 | 85 84 83 82 + 6| BGACK_030| IO| | => | 0 1 ( 2) 3 | 85 84 ( 83) 82 7| | | | => | 0 1 2 3 | 85 84 83 82 8| AS_030| IO| | => | 1 2 ( 3) 4 | 84 83 ( 82) 81 9| DSACK1| IO| | => | 1 2 3 ( 4)| 84 83 82 ( 81) -10| | | | => | 2 3 4 5 | 83 82 81 80 +10| CLK_000_D_11_|NOD| | => | 2 3 4 5 | 83 82 81 80 11| | | | => | 2 3 4 5 | 83 82 81 80 12| SIZE_1_| IO| | => | 3 4 5 ( 6)| 82 81 80 ( 79) 13|inst_BGACK_030_INT_D|NOD| | => | 3 4 5 6 | 82 81 80 79 @@ -1849,14 +1859,14 @@ _|_________________|__|_____|____________________|________________________ | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ - 0| A_23_|INP|*| 85| => | 0 1 2 3 4 5 6 7 - 1| A_22_|INP|*| 84| => | 2 3 4 5 6 7 8 9 - 2| BGACK_030| IO|*| 83| => | ( 4) 5 6 7 8 9 10 11 + 0| A_DECODE_23_|INP|*| 85| => | 0 1 2 3 4 5 6 7 + 1| A_DECODE_22_|INP|*| 84| => | 2 3 4 5 6 7 8 9 + 2| BGACK_030| IO|*| 83| => | 4 5 ( 6) 7 8 9 10 11 3| AS_030| IO|*| 82| => | 6 7 ( 8) 9 10 11 12 13 4| DSACK1| IO|*| 81| => | 8 ( 9) 10 11 12 13 14 15 5| RW_000| IO|*| 80| => | 10 11 12 13 14 15 ( 0) 1 6| SIZE_1_| IO|*| 79| => | (12) 13 14 15 0 1 2 3 - 7| FPU_CS|OUT|*| 78| => | 14 15 0 ( 1) 2 3 4 5 + 7| FPU_CS|OUT|*| 78| => | 14 15 0 1 2 3 ( 4) 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > IO/Node and IO/Input Macrocell Pairing Table @@ -1867,8 +1877,8 @@ _|_________________|__|___|_____|___________________________________________ | Sig Type--+ | | | | Signal Name | | | | Input Macrocell and Node Pairs _|_________________|__|___|_____|__________________________________________ - 0| A_23_|INP|*| 85| => | Input macrocell [ -] - 1| A_22_|INP|*| 84| => | Input macrocell [ -] + 0| A_DECODE_23_|INP|*| 85| => | Input macrocell [ -] + 1| A_DECODE_22_|INP|*| 84| => | Input macrocell [ -] 2| BGACK_030| IO|*| 83| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_BGACK_030] 3| AS_030| IO|*| 82| => | Input macrocell [ -] @@ -1888,24 +1898,24 @@ IMX No. | +---- Block IO Pin or Macrocell Number | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell | | | | Sig Type | | +- Feedback Required (*) ---|-------|----|---|---|----------|------|-|------------------------------ - 0 [IOpin 0 | 85|INP A_23_|*|*] + 0 [IOpin 0 | 85|INP A_DECODE_23_|*|*] [RegIn 0 |270| -| | ] [MCell 0 |269|NOD RN_RW_000| |*] paired w/[ RW_000] - [MCell 1 |271|OUT FPU_CS| | ] + [MCell 1 |271|NOD inst_AS_030_D0| |*] - 1 [IOpin 1 | 84|INP A_22_|*|*] + 1 [IOpin 1 | 84|INP A_DECODE_22_|*|*] [RegIn 1 |273| -| | ] - [MCell 2 |272|NOD CLK_000_N_SYNC_10_| |*] - [MCell 3 |274|NOD inst_AS_030_D0| |*] + [MCell 2 |272|NOD CLK_000_D_12_| |*] + [MCell 3 |274| -| | ] 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] [RegIn 2 |276| -| | ] - [MCell 4 |275|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] + [MCell 4 |275|OUT FPU_CS| | ] [MCell 5 |277| -| | ] 3 [IOpin 3 | 82| IO AS_030|*|*] [RegIn 3 |279| -| | ] - [MCell 6 |278|NOD CLK_000_N_SYNC_11_| |*] + [MCell 6 |278|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] [MCell 7 |280| -| | ] 4 [IOpin 4 | 81| IO DSACK1|*| ] paired w/[ RN_DSACK1] @@ -1915,7 +1925,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 5 [IOpin 5 | 80| IO RW_000|*|*] paired w/[ RN_RW_000] [RegIn 5 |285| -| | ] - [MCell 10 |284| -| | ] + [MCell 10 |284|NOD CLK_000_D_11_| |*] [MCell 11 |286| -| | ] 6 [IOpin 6 | 79| IO SIZE_1_|*|*] @@ -1934,37 +1944,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux00| Input Pin ( 86)| RST Mux01| IOPin 4 0 ( 41)| BERR -Mux02| Mcel 5 8 ( 233)| SM_AMIGA_5_ -Mux03| Mcel 0 8 ( 113)| inst_nEXP_SPACE_D0reg -Mux04| IOPin 3 7 ( 28)| BGACK_000 -Mux05| Mcel 5 0 ( 221)| SM_AMIGA_i_7_ +Mux02| IOPin 4 1 ( 42)| AS_000 +Mux03| Mcel 0 8 ( 113)| CLK_000_P_SYNC_10_ +Mux04| Mcel 7 2 ( 272)| CLK_000_D_12_ +Mux05| Input Pin ( 14)| nEXP_SPACE Mux06| IOPin 5 3 ( 57)| FC_0_ Mux07| Mcel 3 9 ( 187)| inst_RESET_OUT -Mux08| IOPin 6 6 ( 71)| RW -Mux09| Mcel 0 1 ( 103)| inst_AS_000_DMA -Mux10| Mcel 6 9 ( 259)| SIZE_DMA_1_ +Mux08| IOPin 0 0 ( 91)| FPU_SENSE +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 6 9 ( 259)| SIZE_DMA_0_ Mux11| Mcel 7 9 ( 283)| RN_DSACK1 Mux12| IOPin 5 2 ( 58)| FC_1_ -Mux13| IOPin 5 1 ( 59)| A_17_ -Mux14| Mcel 5 5 ( 229)| SM_AMIGA_1_ -Mux15| Mcel 0 6 ( 110)| CLK_000_N_SYNC_9_ -Mux16| IOPin 4 1 ( 42)| AS_000 -Mux17| IOPin 0 4 ( 95)| A_18_ -Mux18| Mcel 7 3 ( 274)| inst_AS_030_D0 -Mux19| IOPin 0 0 ( 91)| FPU_SENSE -Mux20| Input Pin ( 64)| CLK_030 -Mux21| Input Pin ( 86)| RST -Mux22| Mcel 6 5 ( 253)| inst_CLK_000_PE +Mux13| IOPin 5 1 ( 59)| A_DECODE_17_ +Mux14| Mcel 5 5 ( 229)| SM_AMIGA_0_ +Mux15| Mcel 5 13 ( 241)| SM_AMIGA_1_ +Mux16| Mcel 4 8 ( 209)| inst_CLK_OUT_PRE_D +Mux17| IOPin 0 4 ( 95)| A_DECODE_18_ +Mux18| Mcel 7 10 ( 284)| CLK_000_D_11_ +Mux19| Mcel 7 1 ( 271)| inst_AS_030_D0 +Mux20| Mcel 5 8 ( 233)| SM_AMIGA_5_ +Mux21| Mcel 7 6 ( 278)| RN_BGACK_030 +Mux22| Mcel 6 5 ( 253)| SIZE_DMA_1_ Mux23| Mcel 7 0 ( 269)| RN_RW_000 -Mux24| Mcel 0 12 ( 119)| inst_CLK_OUT_PRE_D -Mux25| Mcel 6 13 ( 265)| SIZE_DMA_0_ -Mux26| IOPin 0 5 ( 96)| A_16_ -Mux27| IOPin 0 6 ( 97)| A_19_ -Mux28| Mcel 7 2 ( 272)| CLK_000_N_SYNC_10_ +Mux24| Mcel 0 12 ( 119)| inst_AS_000_DMA +Mux25| IOPin 6 6 ( 71)| RW +Mux26| IOPin 0 5 ( 96)| A_DECODE_16_ +Mux27| IOPin 0 6 ( 97)| A_DECODE_19_ +Mux28| Input Pin ( 64)| CLK_030 Mux29| ... | ... -Mux30| Mcel 5 1 ( 223)| SM_AMIGA_0_ -Mux31| ... | ... -Mux32| IOPin 7 3 ( 82)| AS_030 +Mux30| Mcel 6 15 ( 268)| CLK_000_D_10_ +Mux31| Mcel 5 0 ( 221)| SM_AMIGA_i_7_ +Mux32| IOPin 3 7 ( 28)| BGACK_000 --------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index d9cdde2..1234f24 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic -Project Fitted on : Wed Aug 17 17:45:51 2016 +Project Fitted on : Fri Aug 19 00:20:46 2016 Device : M4A5-128/64 Package : 100TQFP @@ -37,11 +37,11 @@ Fitter 00:00:00 Design_Summary ~~~~~~~~~~~~~~ - Total Input Pins : 32 + Total Input Pins : 24 Total Output Pins : 19 - Total Bidir I/O Pins : 10 - Total Flip-Flops : 79 - Total Product Terms : 233 + Total Bidir I/O Pins : 18 + Total Flip-Flops : 89 + Total Product Terms : 251 Total Reserved Pins : 0 Total Reserved Blocks : 0 @@ -54,12 +54,12 @@ Dedicated Pins Input-Only Pins 2 2 0 --> 100% Clock/Input Pins 4 4 0 --> 100% I/O Pins 64 55 9 --> 85% -Logic Macrocells 128 98 30 --> 76% +Logic Macrocells 128 116 12 --> 90% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 0 .. -CSM Outputs/Total Block Inputs 264 222 42 --> 84% -Logical Product Terms 640 233 407 --> 36% +CSM Outputs/Total Block Inputs 264 237 27 --> 89% +Logical Product Terms 640 251 389 --> 39% Product Term Clusters 128 54 74 --> 42%  @@ -71,14 +71,14 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 26 8 0 13 0 3 37 8 Lo -Block B 27 8 0 16 0 0 46 6 Lo -Block C 26 7 0 5 0 11 18 11 Lo -Block D 27 8 0 16 0 0 33 6 Lo -Block E 32 4 0 9 0 7 11 14 Lo -Block F 28 5 0 13 0 3 47 4 Lo -Block G 25 7 0 16 0 0 24 11 Lo -Block H 31 8 0 10 0 6 17 13 Lo +Block A 28 8 0 16 0 0 42 7 Lo +Block B 26 8 0 16 0 0 46 5 Lo +Block C 28 7 0 16 0 0 25 12 Lo +Block D 31 8 0 16 0 0 28 9 Lo +Block E 33 4 0 10 0 6 12 14 Lo +Block F 31 5 0 16 0 0 56 2 Lo +Block G 28 7 0 16 0 0 25 10 Lo +Block H 32 8 0 10 0 6 17 13 Lo --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. @@ -170,9 +170,9 @@ Pin No| Type |Pad |Pin | Signal name 1 | GND | | | 2 | JTAG | | | 3 | I_O | B7 | * |RESET -4 | I_O | B6 | * |A_31_ -5 | I_O | B5 | * |A_30_ -6 | I_O | B4 | * |A_29_ +4 | I_O | B6 | * |AHIGH_31_ +5 | I_O | B5 | * |AHIGH_30_ +6 | I_O | B4 | * |AHIGH_29_ 7 | I_O | B3 | * |IPL_030_1_ 8 | I_O | B2 | * |IPL_030_0_ 9 | I_O | B1 | * |IPL_030_2_ @@ -181,11 +181,11 @@ Pin No| Type |Pad |Pin | Signal name 12 | Vcc | | | 13 | GND | | | 14 | CkIn | | * |nEXP_SPACE -15 | I_O | C0 | * |A_28_ -16 | I_O | C1 | * |A_27_ -17 | I_O | C2 | * |A_26_ -18 | I_O | C3 | * |A_25_ -19 | I_O | C4 | * |A_24_ +15 | I_O | C0 | * |AHIGH_28_ +16 | I_O | C1 | * |AHIGH_27_ +17 | I_O | C2 | * |AHIGH_26_ +18 | I_O | C3 | * |AHIGH_25_ +19 | I_O | C4 | * |AHIGH_24_ 20 | I_O | C5 | * |AMIGA_BUS_ENABLE_LOW 21 | I_O | C6 | * |BG_030 22 | I_O | C7 | | @@ -225,8 +225,8 @@ Pin No| Type |Pad |Pin | Signal name 56 | I_O | F4 | * |IPL_1_ 57 | I_O | F3 | * |FC_0_ 58 | I_O | F2 | * |FC_1_ -59 | I_O | F1 | * |A_17_ -60 | I_O | F0 | * |A1 +59 | I_O | F1 | * |A_DECODE_17_ +60 | I_O | F0 | * |A_1_ 61 | CkIn | | * |CLK_OSZI 62 | Vcc | | | 63 | GND | | | @@ -235,7 +235,7 @@ Pin No| Type |Pad |Pin | Signal name 66 | I_O | G1 | * |E 67 | I_O | G2 | * |IPL_0_ 68 | I_O | G3 | * |IPL_2_ -69 | I_O | G4 | * |A0 +69 | I_O | G4 | * |A_0_ 70 | I_O | G5 | * |SIZE_0_ 71 | I_O | G6 | * |RW 72 | I_O | G7 | | @@ -250,8 +250,8 @@ Pin No| Type |Pad |Pin | Signal name 81 | I_O | H4 | * |DSACK1 82 | I_O | H3 | * |AS_030 83 | I_O | H2 | * |BGACK_030 -84 | I_O | H1 | * |A_22_ -85 | I_O | H0 | * |A_23_ +84 | I_O | H1 | * |A_DECODE_22_ +85 | I_O | H0 | * |A_DECODE_23_ 86 | Inp | | * |RST 87 | Vcc | | | 88 | GND | | | @@ -259,11 +259,11 @@ Pin No| Type |Pad |Pin | Signal name 90 | Vcc | | | 91 | I_O | A0 | * |FPU_SENSE 92 | I_O | A1 | * |AVEC -93 | I_O | A2 | * |A_20_ -94 | I_O | A3 | * |A_21_ -95 | I_O | A4 | * |A_18_ -96 | I_O | A5 | * |A_16_ -97 | I_O | A6 | * |A_19_ +93 | I_O | A2 | * |A_DECODE_20_ +94 | I_O | A3 | * |A_DECODE_21_ +95 | I_O | A4 | * |A_DECODE_18_ +96 | I_O | A5 | * |A_DECODE_16_ +97 | I_O | A6 | * |A_DECODE_19_ 98 | I_O | A7 | * |DS_030 99 | GND | | | 100 | GND | | | @@ -287,35 +287,27 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 60 F . I/O -B------ Low Slow A1 - 96 A . I/O --C-E--H Low Slow A_16_ - 59 F . I/O --C-E--H Low Slow A_17_ - 95 A . I/O --C-E--H Low Slow A_18_ - 97 A . I/O --C-E--H Low Slow A_19_ - 93 A . I/O ----E--- Low Slow A_20_ - 94 A . I/O ----E--- Low Slow A_21_ - 84 H . I/O ----E--- Low Slow A_22_ - 85 H . I/O ----E--- Low Slow A_23_ - 19 C . I/O ----E--- Low Slow A_24_ - 18 C . I/O ----E--- Low Slow A_25_ - 17 C . I/O ----E--- Low Slow A_26_ - 16 C . I/O ----E--- Low Slow A_27_ - 15 C . I/O ----E--- Low Slow A_28_ - 6 B . I/O ----E--- Low Slow A_29_ - 5 B . I/O ----E--- Low Slow A_30_ - 4 B . I/O ----E--- Low Slow A_31_ + 60 F . I/O -BC----- Low Slow A_1_ + 96 A . I/O --C-E--H Low Slow A_DECODE_16_ + 59 F . I/O --C-E--H Low Slow A_DECODE_17_ + 95 A . I/O --C-E--H Low Slow A_DECODE_18_ + 97 A . I/O --C-E--H Low Slow A_DECODE_19_ + 93 A . I/O ----E--- Low Slow A_DECODE_20_ + 94 A . I/O ----E--- Low Slow A_DECODE_21_ + 84 H . I/O ----E--- Low Slow A_DECODE_22_ + 85 H . I/O ----E--- Low Slow A_DECODE_23_ 28 D . I/O ----E--H Low Slow BGACK_000 21 C . I/O ---D---- Low Slow BG_030 - 30 D . I/O -B------ Low Slow DTACK + 30 D . I/O --C----- Low Slow DTACK 57 F . I/O --C-E--H Low Slow FC_0_ 58 F . I/O --C-E--H Low Slow FC_1_ 91 A . I/O ----E--H Low Slow FPU_SENSE - 67 G . I/O -B----G- Low Slow IPL_0_ - 56 F . I/O -B-D---- Low Slow IPL_1_ + 67 G . I/O -B-D---- Low Slow IPL_0_ + 56 F . I/O -B---F-- Low Slow IPL_1_ 68 G . I/O -B------ Low Slow IPL_2_ - 11 . . Ck/I -B------ - Slow CLK_000 - 14 . . Ck/I A------- - Slow nEXP_SPACE - 36 . . Ded -----F-- - Slow VPA + 11 . . Ck/I ---D--G- - Slow CLK_000 + 14 . . Ck/I ABCDEFGH - Slow nEXP_SPACE + 36 . . Ded A------- - Slow VPA 61 . . Ck/I ABCDEFGH - Slow CLK_OSZI 64 . . Ck/I A------H - Slow CLK_030 86 . . Ded ABCD-FGH - Slow RST @@ -336,7 +328,7 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- 33 D 1 COM -------- Low Fast AMIGA_ADDR_ENABLE 48 E 2 COM -------- Low Fast AMIGA_BUS_DATA_DIR - 34 D 2 COM -------- Low Fast AMIGA_BUS_ENABLE_HIGH + 34 D 3 COM -------- Low Fast AMIGA_BUS_ENABLE_HIGH 20 C 1 COM -------- Low Fast AMIGA_BUS_ENABLE_LOW 92 A 1 COM -------- Low Slow AVEC 83 H 3 DFF * * -------- Low Slow BGACK_030 @@ -368,12 +360,20 @@ Bidir_Signal_List Pin r e O Bidir Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 69 G 3 DFF * * A------- Low Slow A0 - 42 E 1 COM ABC-E--H Low Slow AS_000 + 19 C 1 COM ----E--- Low Slow AHIGH_24_ + 18 C 1 COM ----E--- Low Slow AHIGH_25_ + 17 C 1 COM ----E--- Low Slow AHIGH_26_ + 16 C 1 COM ----E--- Low Slow AHIGH_27_ + 15 C 1 COM ----E--- Low Slow AHIGH_28_ + 6 B 1 COM ----E--- Low Slow AHIGH_29_ + 5 B 1 COM ----E--- Low Slow AHIGH_30_ + 4 B 1 COM ----E--- Low Slow AHIGH_31_ + 42 E 1 COM A---E--H Low Slow AS_000 82 H 1 COM ----E--H Low Slow AS_030 - 41 E 1 COM --C--F-H Low Slow BERR + 69 G 3 DFF * * AB------ Low Slow A_0_ + 41 E 1 COM --C--FGH Low Slow BERR 31 D 1 COM A-----G- Low Slow LDS_000 - 71 G 2 DFF * * --C----H Low Slow RW + 71 G 2 DFF * * -----F-H Low Slow RW 80 H 3 DFF * * A---E-G- Low Slow RW_000 70 G 1 COM A------- Low Slow SIZE_0_ 79 H 1 COM A------- Low Slow SIZE_1_ @@ -393,85 +393,95 @@ Buried_Signal_List Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - E5 E 2 COM ----E--- Low Slow CIIN_0 - B9 B 1 DFF * * ---DEF-- Low Slow CLK_000_D_0_ - E8 E 1 DFF * * ----EF-- Low Slow CLK_000_D_1_ - E9 E 1 DFF * * A------- Low Slow CLK_000_N_SYNC_0_ - H2 H 1 DFF * * -------H Low Slow CLK_000_N_SYNC_10_ - H6 H 1 DFF * * ------G- Low Slow CLK_000_N_SYNC_11_ - A14 A 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_1_ - B14 B 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_2_ - B10 B 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_3_ - B6 B 1 DFF * * ---D---- Low Slow CLK_000_N_SYNC_4_ - D11 D 1 DFF * * ------G- Low Slow CLK_000_N_SYNC_5_ - G6 G 1 DFF * * -----F-- Low Slow CLK_000_N_SYNC_6_ - F3 F 1 DFF * * A------- Low Slow CLK_000_N_SYNC_7_ - A10 A 1 DFF * * A------- Low Slow CLK_000_N_SYNC_8_ - A6 A 1 DFF * * -------H Low Slow CLK_000_N_SYNC_9_ - E2 E 1 DFF * * -B------ Low Slow CLK_000_P_SYNC_0_ - B7 B 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_1_ - G7 G 1 DFF * * ----E--- Low Slow CLK_000_P_SYNC_2_ - E13 E 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_3_ - G3 G 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_4_ - G14 G 1 DFF * * A------- Low Slow CLK_000_P_SYNC_5_ - A3 A 1 DFF * * -B------ Low Slow CLK_000_P_SYNC_6_ - B3 B 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_7_ - G10 G 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_8_ - G15 G 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_9_ - B5 B 2 DFF * * ABC----- Low Slow CYCLE_DMA_0_ - C12 C 3 DFF * * A-C----- Low Slow CYCLE_DMA_1_ - G11 G 1 DFF * * -B------ Low Slow IPL_D0_0_ - D15 D 1 DFF * * -B------ Low Slow IPL_D0_1_ - B11 B 1 DFF * * -B------ Low Slow IPL_D0_2_ - F14 F 4 COM -----F-- Low Slow N_317_i - G8 G 3 DFF * * ------G- Low - RN_A0 --> A0 - H4 H 3 DFF * * ABCDE-GH Low - RN_BGACK_030 --> BGACK_030 + E10 E 2 COM ----E--- Low Slow CIIN_0 + G13 G 1 DFF * * --CD---- Low Slow CLK_000_D_0_ + G15 G 1 DFF * * -------H Low Slow CLK_000_D_10_ + H10 H 1 DFF * * -------H Low Slow CLK_000_D_11_ + H2 H 1 DFF * * -------H Low Slow CLK_000_D_12_ + C6 C 1 DFF * * ---D--G- Low Slow CLK_000_D_1_ + G11 G 1 DFF * * ------G- Low Slow CLK_000_D_2_ + G7 G 1 DFF * * --C----- Low Slow CLK_000_D_3_ + C11 C 1 DFF * * ----E--- Low Slow CLK_000_D_4_ + E13 E 1 DFF * * -B------ Low Slow CLK_000_D_5_ + B11 B 1 DFF * * ------G- Low Slow CLK_000_D_6_ + G3 G 1 DFF * * -B------ Low Slow CLK_000_D_7_ + B7 B 1 DFF * * ---D---- Low Slow CLK_000_D_8_ + D11 D 1 DFF * * ------G- Low Slow CLK_000_D_9_ + D2 D 1 DFF * * --C-EF-- Low Slow CLK_000_N_SYNC_0_ + C14 C 1 DFF * * --C----- Low Slow CLK_000_N_SYNC_10_ + C10 C 1 DFF * * ---D---- Low Slow CLK_000_N_SYNC_11_ + D13 D 1 DFF * * ---DEF-- Low Slow CLK_000_N_SYNC_12_ + E9 E 1 DFF * * A------- Low Slow CLK_000_N_SYNC_1_ + A3 A 1 DFF * * -----F-- Low Slow CLK_000_N_SYNC_2_ + F7 F 1 DFF * * A------- Low Slow CLK_000_N_SYNC_3_ + A14 A 1 DFF * * A------- Low Slow CLK_000_N_SYNC_4_ + A6 A 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_5_ + B3 B 1 DFF * * ------G- Low Slow CLK_000_N_SYNC_6_ + G6 G 1 DFF * * -B------ Low Slow CLK_000_N_SYNC_7_ + B14 B 1 DFF * * -----F-- Low Slow CLK_000_N_SYNC_8_ + F3 F 1 DFF * * --C----- Low Slow CLK_000_N_SYNC_9_ + D7 D 1 DFF * * A------- Low Slow CLK_000_P_SYNC_0_ + A8 A 1 DFF * * A-CD-F-H Low Slow CLK_000_P_SYNC_10_ + A15 A 1 DFF * * -----F-- Low Slow CLK_000_P_SYNC_1_ + F11 F 1 DFF * * --C----- Low Slow CLK_000_P_SYNC_2_ + C7 C 1 DFF * * A------- Low Slow CLK_000_P_SYNC_3_ + A11 A 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_4_ + G14 G 1 DFF * * ------G- Low Slow CLK_000_P_SYNC_5_ + G10 G 1 DFF * * ---D---- Low Slow CLK_000_P_SYNC_6_ + D3 D 1 DFF * * A------- Low Slow CLK_000_P_SYNC_7_ + A7 A 1 DFF * * --C----- Low Slow CLK_000_P_SYNC_8_ + C3 C 1 DFF * * A------- Low Slow CLK_000_P_SYNC_9_ + A10 A 2 DFF * * A------- Low Slow CYCLE_DMA_0_ + A2 A 3 DFF * * A------- Low Slow CYCLE_DMA_1_ + D15 D 1 DFF * * -B------ Low Slow IPL_D0_0_ + F15 F 1 DFF * * -B------ Low Slow IPL_D0_1_ + B15 B 1 DFF * * -B------ Low Slow IPL_D0_2_ + F14 F 3 COM -----F-- Low Slow N_226 + G8 G 3 DFF * * ------G- Low - RN_A_0_ --> A_0_ + H6 H 3 DFF * * ABCDE-GH Low - RN_BGACK_030 --> BGACK_030 D1 D 2 DFF * * ---D---- Low - RN_BG_000 --> BG_000 H9 H 4 DFF * * -------H Low - RN_DSACK1 --> DSACK1 B8 B 10 DFF * * -B------ Low - RN_IPL_030_0_ --> IPL_030_0_ - B12 B 10 DFF * * -B------ Low - RN_IPL_030_1_ --> IPL_030_1_ + B9 B 10 DFF * * -B------ Low - RN_IPL_030_1_ --> IPL_030_1_ B4 B 10 DFF * * -B------ Low - RN_IPL_030_2_ --> IPL_030_2_ G0 G 2 DFF * * ------G- Low - RN_RW --> RW H0 H 3 DFF * * -------H Low - RN_RW_000 --> RW_000 D0 D 3 TFF * * ---D-F-- Low - RN_VMA --> VMA - D3 D 3 DFF * * ---D---- Low Slow RST_DLY_0_ - D14 D 4 DFF * * ---D---- Low Slow RST_DLY_1_ - D7 D 2 DFF * * ---D---- Low Slow RST_DLY_2_ - G13 G 3 DFF * * ------GH Low Slow SIZE_DMA_0_ - G9 G 3 DFF * * ------GH Low Slow SIZE_DMA_1_ - F1 F 2 DFF * * --C--F-H Low Slow SM_AMIGA_0_ - F5 F 3 DFF * * -----F-H Low Slow SM_AMIGA_1_ - F10 F 4 DFF * * -----F-- Low Slow SM_AMIGA_2_ - F6 F 5 TFF * * -----F-- Low Slow SM_AMIGA_3_ - F9 F 3 DFF * * --C--F-- Low Slow SM_AMIGA_4_ - F8 F 3 DFF * * --C--F-H Low Slow SM_AMIGA_5_ - F4 F 3 DFF * * A-C--F-- Low Slow SM_AMIGA_6_ + D10 D 3 DFF * * ---D---- Low Slow RST_DLY_0_ + D6 D 4 DFF * * ---D---- Low Slow RST_DLY_1_ + D14 D 2 DFF * * ---D---- Low Slow RST_DLY_2_ + G9 G 3 DFF * * ------GH Low Slow SIZE_DMA_0_ + G5 G 3 DFF * * ------GH Low Slow SIZE_DMA_1_ + F5 F 2 DFF * * ---D-F-H Low Slow SM_AMIGA_0_ + F13 F 3 DFF * * -----F-H Low Slow SM_AMIGA_1_ + F6 F 4 DFF * * -----F-- Low Slow SM_AMIGA_2_ + F2 F 5 TFF * * -----F-- Low Slow SM_AMIGA_3_ + F10 F 3 DFF * * -----F-- Low Slow SM_AMIGA_4_ + F8 F 3 DFF * * -----FGH Low Slow SM_AMIGA_5_ + C9 C 3 DFF * * ABC--F-- Low Slow SM_AMIGA_6_ F0 F 14 DFF * * --CD-F-H Low Slow SM_AMIGA_i_7_ - D6 D 2 DFF * * ---D-F-- Low Slow cpu_est_0_ - D2 D 3 DFF * * ---D-FG- Low Slow cpu_est_1_ - D13 D 4 DFF * * ---D-FG- Low Slow cpu_est_2_ - F12 F 3 DFF * * ---D-FG- Low Slow cpu_est_3_ - B13 B 2 DFF * * -B-D---- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH - B2 B 2 DFF * * -BC----- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW - A1 A 7 DFF * * A------H Low Slow inst_AS_000_DMA - C1 C 2 DFF * * --C-E--- Low Slow inst_AS_000_INT - C4 C 7 DFF * * --C--F-- Low Slow inst_AS_030_000_SYNC - H3 H 1 DFF * * --CDE--H Low Slow inst_AS_030_D0 + B2 B 2 DFF * * -B-D-F-- Low Slow cpu_est_0_ + F12 F 3 DFF * * ---D-FG- Low Slow cpu_est_1_ + F4 F 4 DFF * * ---D-FG- Low Slow cpu_est_2_ + F1 F 3 DFF * * ---D-FG- Low Slow cpu_est_3_ + C2 C 2 DFF * * --CD---- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH + B10 B 2 DFF * * -BC----- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW + A12 A 7 DFF * * A------H Low Slow inst_AS_000_DMA + G2 G 2 DFF * * ----E-G- Low Slow inst_AS_000_INT + C13 C 7 DFF * * --C--F-- Low Slow inst_AS_030_000_SYNC + H1 H 1 DFF * * --CDEFGH Low Slow inst_AS_030_D0 H13 H 1 DFF * * -BC---G- Low Slow inst_BGACK_030_INT_D - G2 G 1 DFF * * ---D-F-- Low Slow inst_CLK_000_NE - D10 D 1 DFF * * ---D-F-- Low Slow inst_CLK_000_NE_D0 - G5 G 1 DFF * * -BCD-F-H Low Slow inst_CLK_000_PE - A2 A 8 DFF * * A------- Low Slow inst_CLK_030_H - F13 F 1 DFF * * A----F-- Low Slow inst_CLK_OUT_PRE_50 - A12 A 1 DFF * * -B----GH Low Slow inst_CLK_OUT_PRE_D - A13 A 9 DFF * * A------- Low Slow inst_DS_000_DMA - C8 C 5 DFF * * --CD---- Low Slow inst_DS_000_ENABLE - B15 B 1 DFF * * -----F-- Low Slow inst_DTACK_D0 - A5 A 3 DFF * * A--D---- Low Slow inst_LDS_000_INT - D9 D 2 DFF * * AB-DE-GH Low Slow inst_RESET_OUT - A9 A 2 DFF * * A--D---- Low Slow inst_UDS_000_INT - F2 F 1 DFF * * ---D-F-- Low Slow inst_VPA_D - A8 A 1 DFF * * A-CDEFGH Low Slow inst_nEXP_SPACE_D0reg + E5 E 1 DFF * * -B---F-- Low Slow inst_CLK_000_NE_D0 + A13 A 8 DFF * * A------- Low Slow inst_CLK_030_H + E2 E 1 DFF * * ----E--- Low Slow inst_CLK_OUT_PRE_50 + E8 E 1 DFF * * -B----GH Low Slow inst_CLK_OUT_PRE_D + A9 A 9 DFF * * A------- Low Slow inst_DS_000_DMA + F9 F 5 DFF * * ---D-F-- Low Slow inst_DS_000_ENABLE + C15 C 1 DFF * * -----F-- Low Slow inst_DTACK_D0 + A1 A 3 DFF * * A--D---- Low Slow inst_LDS_000_INT + D9 D 2 DFF * * ABCDE-GH Low Slow inst_RESET_OUT + B6 B 2 DFF * * -B-D---- Low Slow inst_UDS_000_INT + A5 A 1 DFF * * ---D-F-- Low Slow inst_VPA_D ---------------------------------------------------------------------- Power : Hi = High @@ -486,206 +496,222 @@ Signals_Fanout_List ~~~~~~~~~~~~~~~~~~~ Signal Source : Fanout List ----------------------------------------------------------------------------- +A_DECODE_22_{ I}: CIIN{ E} CIIN_0{ E} +A_DECODE_21_{ B}: CIIN{ E} CIIN_0{ E} SIZE_1_{ I}:inst_LDS_000_INT{ A} - A_31_{ C}: CIIN{ E} CIIN_0{ E} +A_DECODE_20_{ B}: CIIN{ E} CIIN_0{ E} +A_DECODE_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + AHIGH_31_{ C}: CIIN{ E} CIIN_0{ E} +A_DECODE_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} +A_DECODE_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} +A_DECODE_23_{ I}: CIIN{ E} CIIN_0{ E} +A_DECODE_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} IPL_2_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} : IPL_D0_2_{ B} - IPL_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_1_{ D} FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} - IPL_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : IPL_D0_0_{ G} AS_030{ I}: AS_000{ E} BERR{ E} FPU_CS{ H} : inst_AS_030_D0{ H} - FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} AS_000{ F}: AS_030{ H} DS_030{ A}AMIGA_BUS_DATA_DIR{ E} : BGACK_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} - : CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ C} inst_CLK_030_H{ A} - UDS_000{ E}: A0{ G}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} + : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} inst_CLK_030_H{ A} + UDS_000{ E}: A_0_{ G}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} : SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} inst_CLK_030_H{ A} LDS_000{ E}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} SIZE_DMA_0_{ G} : SIZE_DMA_1_{ G} inst_CLK_030_H{ A} - A1{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B} - nEXP_SPACE{. }:inst_nEXP_SPACE_D0reg{ A} - BERR{ F}: DSACK1{ H}inst_AS_000_INT{ C} SM_AMIGA_5_{ F} - :inst_AS_030_000_SYNC{ C} SM_AMIGA_0_{ F} SM_AMIGA_4_{ F} - :inst_DS_000_ENABLE{ C} SM_AMIGA_6_{ F} SM_AMIGA_1_{ F} + nEXP_SPACE{. }: SIZE_1_{ H} AHIGH_31_{ B} AS_030{ H} + : DS_030{ A}AMIGA_BUS_DATA_DIR{ E} SIZE_0_{ G} + : AHIGH_30_{ B} AHIGH_29_{ B} AHIGH_28_{ C} + : AHIGH_27_{ C} AHIGH_26_{ C} AHIGH_25_{ C} + : AHIGH_24_{ C} A_0_{ G} BG_000{ D} + : DSACK1{ H} N_226{ F}inst_AS_030_000_SYNC{ C} + : SM_AMIGA_6_{ C} CIIN_0{ E} + BERR{ F}: DSACK1{ H}inst_AS_000_INT{ G}inst_AS_030_000_SYNC{ C} + : SM_AMIGA_5_{ F} SM_AMIGA_0_{ F} SM_AMIGA_4_{ F} + :inst_DS_000_ENABLE{ F} SM_AMIGA_6_{ C} SM_AMIGA_1_{ F} : SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} BG_030{ D}: BG_000{ D} + IPL_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + : IPL_D0_1_{ F} + IPL_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + : IPL_D0_0_{ D} BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H} + FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} CLK_030{. }: DSACK1{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} : inst_CLK_030_H{ A} - CLK_000{. }: CLK_000_D_0_{ B} + A_1_{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} + CLK_000{. }:AMIGA_BUS_ENABLE_HIGH{ D} CLK_000_D_0_{ G} FPU_SENSE{ B}: BERR{ E} FPU_CS{ H} - DTACK{ E}: inst_DTACK_D0{ B} - VPA{. }: inst_VPA_D{ F} - RST{. }: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - : RW_000{ H} A0{ G} BG_000{ D} + DTACK{ E}: inst_DTACK_D0{ C} + VPA{. }: inst_VPA_D{ A} + RST{. }: IPL_030_2_{ B} RW_000{ H} A_0_{ G} + : IPL_030_1_{ B} IPL_030_0_{ B} BG_000{ D} : BGACK_030{ H} DSACK1{ H} VMA{ D} - : RW{ G}inst_AS_000_INT{ C} SM_AMIGA_5_{ F} - :inst_AMIGA_BUS_ENABLE_DMA_LOW{ B} inst_AS_030_D0{ H}inst_nEXP_SPACE_D0reg{ A} - :inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A} - :inst_DS_000_DMA{ A} CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ C} - : SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} inst_VPA_D{ F} - :inst_UDS_000_INT{ A}inst_LDS_000_INT{ A} inst_DTACK_D0{ B} - : inst_RESET_OUT{ D} IPL_D0_0_{ G} IPL_D0_1_{ D} - : IPL_D0_2_{ B} SM_AMIGA_0_{ F}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B} - : SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C} RST_DLY_0_{ D} - : RST_DLY_1_{ D} RST_DLY_2_{ D} SM_AMIGA_6_{ F} - : inst_CLK_030_H{ A} SM_AMIGA_1_{ F} SM_AMIGA_3_{ F} - : SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} + : RW{ G}inst_AS_000_INT{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B} + : inst_AS_030_D0{ H}inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ H} + :inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_0_{ A} + : CYCLE_DMA_1_{ A} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} + : inst_VPA_D{ A}inst_UDS_000_INT{ B}inst_LDS_000_INT{ A} + : inst_DTACK_D0{ C} inst_RESET_OUT{ D} SM_AMIGA_5_{ F} + : IPL_D0_0_{ D} IPL_D0_1_{ F} IPL_D0_2_{ B} + : SM_AMIGA_0_{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ F} + : RST_DLY_0_{ D} RST_DLY_1_{ D} RST_DLY_2_{ D} + :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} SM_AMIGA_6_{ C} inst_CLK_030_H{ A} + : SM_AMIGA_1_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + : SM_AMIGA_i_7_{ F} SIZE_0_{ H}:inst_LDS_000_INT{ A} - A_30_{ C}: CIIN{ E} CIIN_0{ E} - A_29_{ C}: CIIN{ E} CIIN_0{ E} - A_28_{ D}: CIIN{ E} CIIN_0{ E} - A_27_{ D}: CIIN{ E} CIIN_0{ E} - A_26_{ D}: CIIN{ E} CIIN_0{ E} - A_25_{ D}: CIIN{ E} CIIN_0{ E} - A_24_{ D}: CIIN{ E} CIIN_0{ E} - A_23_{ I}: CIIN{ E} CIIN_0{ E} - A_22_{ I}: CIIN{ E} CIIN_0{ E} - A_21_{ B}: CIIN{ E} CIIN_0{ E} - A_20_{ B}: CIIN{ E} CIIN_0{ E} - A_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} - A_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} - A_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} - A_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ C} + AHIGH_30_{ C}: CIIN{ E} CIIN_0{ E} + AHIGH_29_{ C}: CIIN{ E} CIIN_0{ E} + AHIGH_28_{ D}: CIIN{ E} CIIN_0{ E} + AHIGH_27_{ D}: CIIN{ E} CIIN_0{ E} + AHIGH_26_{ D}: CIIN{ E} CIIN_0{ E} + AHIGH_25_{ D}: CIIN{ E} CIIN_0{ E} + AHIGH_24_{ D}: CIIN{ E} CIIN_0{ E} RN_IPL_030_2_{ C}: IPL_030_2_{ B} -RN_IPL_030_1_{ C}: IPL_030_1_{ B} -RN_IPL_030_0_{ C}: IPL_030_0_{ B} RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} RW{ G}inst_DS_000_DMA{ A} RN_RW_000{ I}: RW_000{ H} - A0{ H}:inst_UDS_000_INT{ A}inst_LDS_000_INT{ A} - RN_A0{ H}: A0{ G} + A_0_{ H}:inst_UDS_000_INT{ B}inst_LDS_000_INT{ A} + RN_A_0_{ H}: A_0_{ G} +RN_IPL_030_1_{ C}: IPL_030_1_{ B} +RN_IPL_030_0_{ C}: IPL_030_0_{ B} RN_BG_000{ E}: BG_000{ D} -RN_BGACK_030{ I}: SIZE_1_{ H} AS_030{ H} AS_000{ E} - : DS_030{ A} UDS_000{ D} LDS_000{ D} - : SIZE_0_{ G}AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C} - :AMIGA_BUS_ENABLE_HIGH{ D} RW_000{ H} A0{ G} - : BGACK_030{ H} RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B} - :inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A} - :inst_DS_000_DMA{ A} CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ C} - : SIZE_DMA_0_{ G} SIZE_DMA_1_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B} - : inst_CLK_030_H{ A} +RN_BGACK_030{ I}: SIZE_1_{ H} AHIGH_31_{ B} AS_030{ H} + : AS_000{ E} DS_030{ A} UDS_000{ D} + : LDS_000{ D}AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C} + :AMIGA_BUS_ENABLE_HIGH{ D} SIZE_0_{ G} AHIGH_30_{ B} + : AHIGH_29_{ B} AHIGH_28_{ C} AHIGH_27_{ C} + : AHIGH_26_{ C} AHIGH_25_{ C} AHIGH_24_{ C} + : RW_000{ H} A_0_{ G} BGACK_030{ H} + : RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}inst_AS_030_000_SYNC{ C} + :inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} + : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} SIZE_DMA_0_{ G} + : SIZE_DMA_1_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} inst_CLK_030_H{ A} RN_DSACK1{ I}: DSACK1{ H} RN_VMA{ E}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} : SM_AMIGA_i_7_{ F} - RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ C} + RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ F} RN_RW{ H}: RW{ G} - N_317_i{ G}: SM_AMIGA_i_7_{ F} - cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_2_{ D} + N_226{ G}: SM_AMIGA_i_7_{ F} + cpu_est_2_{ G}: E{ G} VMA{ D} cpu_est_2_{ F} : cpu_est_3_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} : SM_AMIGA_i_7_{ F} cpu_est_3_{ G}: E{ G} VMA{ D} cpu_est_3_{ F} - : cpu_est_1_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + : cpu_est_1_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} : SM_AMIGA_i_7_{ F} - cpu_est_0_{ E}: VMA{ D} cpu_est_2_{ D} cpu_est_3_{ F} - : cpu_est_0_{ D} cpu_est_1_{ D} SM_AMIGA_3_{ F} + cpu_est_0_{ C}: VMA{ D} cpu_est_2_{ F} cpu_est_3_{ F} + : cpu_est_0_{ B} cpu_est_1_{ F} SM_AMIGA_3_{ F} : SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} - cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_2_{ D} - : cpu_est_3_{ F} cpu_est_1_{ D} SM_AMIGA_3_{ F} + cpu_est_1_{ G}: E{ G} VMA{ D} cpu_est_2_{ F} + : cpu_est_3_{ F} cpu_est_1_{ F} SM_AMIGA_3_{ F} : SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} -inst_AS_000_INT{ D}: AS_000{ E}inst_AS_000_INT{ C} -SM_AMIGA_5_{ G}: RW_000{ H} N_317_i{ F}inst_AS_000_INT{ C} - : SM_AMIGA_5_{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C} - : SM_AMIGA_i_7_{ F} +inst_AS_000_INT{ H}: AS_000{ E}inst_AS_000_INT{ G} inst_AMIGA_BUS_ENABLE_DMA_LOW{ C}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B} inst_AS_030_D0{ I}: CIIN{ E} BG_000{ D} DSACK1{ H} - :inst_AS_000_INT{ C}inst_AS_030_000_SYNC{ C}inst_DS_000_ENABLE{ C} + :inst_AS_000_INT{ G}inst_AS_030_000_SYNC{ C}inst_DS_000_ENABLE{ F} : CIIN_0{ E} -inst_nEXP_SPACE_D0reg{ B}: SIZE_1_{ H} AS_030{ H} DS_030{ A} - : SIZE_0_{ G}AMIGA_BUS_DATA_DIR{ E} A0{ G} - : BG_000{ D} DSACK1{ H} N_317_i{ F} - :inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ F} CIIN_0{ E} -inst_AS_030_000_SYNC{ D}: N_317_i{ F}inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ F} -inst_BGACK_030_INT_D{ I}: A0{ G} RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B} +inst_AS_030_000_SYNC{ D}: N_226{ F}inst_AS_030_000_SYNC{ C} SM_AMIGA_6_{ C} +inst_BGACK_030_INT_D{ I}: A_0_{ G} RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B} :inst_AS_030_000_SYNC{ C} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} - :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B} + :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} inst_AS_000_DMA{ B}: AS_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} : inst_CLK_030_H{ A} inst_DS_000_DMA{ B}: DS_030{ A}inst_DS_000_DMA{ A} -CYCLE_DMA_0_{ C}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_0_{ B} - : CYCLE_DMA_1_{ C} inst_CLK_030_H{ A} -CYCLE_DMA_1_{ D}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_1_{ C} +CYCLE_DMA_0_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_0_{ A} + : CYCLE_DMA_1_{ A} inst_CLK_030_H{ A} +CYCLE_DMA_1_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A} CYCLE_DMA_1_{ A} : inst_CLK_030_H{ A} SIZE_DMA_0_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_0_{ G} SIZE_DMA_1_{ H}: SIZE_1_{ H} SIZE_0_{ G} SIZE_DMA_1_{ G} - inst_VPA_D{ G}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + inst_VPA_D{ B}: VMA{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} : SM_AMIGA_i_7_{ F} -inst_UDS_000_INT{ B}: UDS_000{ D}inst_UDS_000_INT{ A} +inst_UDS_000_INT{ C}: UDS_000{ D}inst_UDS_000_INT{ B} inst_LDS_000_INT{ B}: LDS_000{ D}inst_LDS_000_INT{ A} -inst_CLK_OUT_PRE_D{ B}: CLK_DIV_OUT{ G} CLK_EXP{ B} DSACK1{ H} -inst_DTACK_D0{ C}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} -inst_RESET_OUT{ E}: AS_030{ H} AS_000{ E} DS_030{ A} - : UDS_000{ D} LDS_000{ D} RESET{ B} - : RW_000{ H} A0{ G} RW{ G} - : inst_RESET_OUT{ D} -inst_CLK_OUT_PRE_50{ G}:inst_CLK_OUT_PRE_D{ A}inst_CLK_OUT_PRE_50{ F} -CLK_000_D_1_{ F}: N_317_i{ F}CLK_000_P_SYNC_0_{ E}CLK_000_N_SYNC_0_{ E} - : SM_AMIGA_6_{ F} -CLK_000_D_0_{ C}: BG_000{ D} N_317_i{ F} CLK_000_D_1_{ E} - :CLK_000_P_SYNC_0_{ E}CLK_000_N_SYNC_0_{ E} SM_AMIGA_6_{ F} -inst_CLK_000_PE{ H}: RW_000{ H} BGACK_030{ H} VMA{ D} - : SM_AMIGA_5_{ F} CYCLE_DMA_0_{ B} CYCLE_DMA_1_{ C} - : SM_AMIGA_0_{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C} - : SM_AMIGA_6_{ F} SM_AMIGA_1_{ F} SM_AMIGA_3_{ F} +inst_CLK_OUT_PRE_D{ F}: CLK_DIV_OUT{ G} CLK_EXP{ B} DSACK1{ H} +CLK_000_D_10_{ H}: DSACK1{ H} CLK_000_D_11_{ H} +CLK_000_D_11_{ I}: DSACK1{ H} CLK_000_D_12_{ H} +inst_DTACK_D0{ D}: SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} +inst_RESET_OUT{ E}: AHIGH_31_{ B} AS_030{ H} AS_000{ E} + : DS_030{ A} UDS_000{ D} LDS_000{ D} + : RESET{ B} AHIGH_30_{ B} AHIGH_29_{ B} + : AHIGH_28_{ C} AHIGH_27_{ C} AHIGH_26_{ C} + : AHIGH_25_{ C} AHIGH_24_{ C} RW_000{ H} + : A_0_{ G} RW{ G} inst_RESET_OUT{ D} +inst_CLK_OUT_PRE_50{ F}:inst_CLK_OUT_PRE_D{ E}inst_CLK_OUT_PRE_50{ E} +CLK_000_D_1_{ D}: CLK_000_D_2_{ G}CLK_000_N_SYNC_0_{ D}CLK_000_P_SYNC_0_{ D} +CLK_000_D_0_{ H}: BG_000{ D} CLK_000_D_1_{ C}CLK_000_N_SYNC_0_{ D} + :CLK_000_P_SYNC_0_{ D} +CLK_000_P_SYNC_10_{ B}: RW_000{ H} BGACK_030{ H} VMA{ D} + : CYCLE_DMA_0_{ A} CYCLE_DMA_1_{ A} SM_AMIGA_5_{ F} + : SM_AMIGA_0_{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ F} + : SM_AMIGA_6_{ C} SM_AMIGA_1_{ F} SM_AMIGA_3_{ F} : SM_AMIGA_2_{ F} SM_AMIGA_i_7_{ F} -CLK_000_P_SYNC_9_{ H}:inst_CLK_000_PE{ G} -inst_CLK_000_NE{ H}: VMA{ D} SM_AMIGA_5_{ F} inst_RESET_OUT{ D} - :inst_CLK_000_NE_D0{ D} SM_AMIGA_0_{ F} SM_AMIGA_4_{ F} - : RST_DLY_0_{ D} RST_DLY_1_{ D} RST_DLY_2_{ D} - : SM_AMIGA_1_{ F} SM_AMIGA_i_7_{ F} -CLK_000_N_SYNC_11_{ I}:inst_CLK_000_NE{ G} - IPL_D0_0_{ H}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - IPL_D0_1_{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} - IPL_D0_2_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} -inst_CLK_000_NE_D0{ E}: cpu_est_2_{ D} cpu_est_3_{ F} cpu_est_0_{ D} - : cpu_est_1_{ D} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} +SM_AMIGA_5_{ G}: RW_000{ H} N_226{ F}inst_AS_000_INT{ G} + : SM_AMIGA_5_{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ F} : SM_AMIGA_i_7_{ F} -SM_AMIGA_0_{ G}: RW_000{ H} N_317_i{ F} SM_AMIGA_0_{ F} - :inst_DS_000_ENABLE{ C} SM_AMIGA_i_7_{ F} -inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B} -SM_AMIGA_4_{ G}: N_317_i{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C} + IPL_D0_0_{ E}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_1_{ G}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + IPL_D0_2_{ C}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} +CLK_000_D_2_{ H}: CLK_000_D_3_{ G} +CLK_000_D_3_{ H}: CLK_000_D_4_{ C} +CLK_000_D_4_{ D}: CLK_000_D_5_{ E} +CLK_000_D_5_{ F}: CLK_000_D_6_{ B} +CLK_000_D_6_{ C}: CLK_000_D_7_{ G} +CLK_000_D_7_{ H}: CLK_000_D_8_{ B} +CLK_000_D_8_{ C}: CLK_000_D_9_{ D} +CLK_000_D_9_{ E}: CLK_000_D_10_{ G} +CLK_000_D_12_{ I}: DSACK1{ H} +SM_AMIGA_0_{ G}:AMIGA_BUS_ENABLE_HIGH{ D} RW_000{ H} N_226{ F} + : SM_AMIGA_0_{ F}inst_DS_000_ENABLE{ F} SM_AMIGA_i_7_{ F} +CLK_000_N_SYNC_0_{ E}: N_226{ F}CLK_000_N_SYNC_1_{ E} SM_AMIGA_6_{ C} +SM_AMIGA_4_{ G}: N_226{ F} SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ F} : SM_AMIGA_3_{ F} SM_AMIGA_i_7_{ F} -inst_DS_000_ENABLE{ D}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ C} +inst_DS_000_ENABLE{ G}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ F} +CLK_000_N_SYNC_12_{ E}: VMA{ D} inst_RESET_OUT{ D} SM_AMIGA_5_{ F} + : SM_AMIGA_0_{ F} SM_AMIGA_4_{ F} RST_DLY_0_{ D} + : RST_DLY_1_{ D} RST_DLY_2_{ D}inst_CLK_000_NE_D0{ E} + : SM_AMIGA_1_{ F} SM_AMIGA_i_7_{ F} RST_DLY_0_{ E}: inst_RESET_OUT{ D} RST_DLY_0_{ D} RST_DLY_1_{ D} : RST_DLY_2_{ D} RST_DLY_1_{ E}: inst_RESET_OUT{ D} RST_DLY_0_{ D} RST_DLY_1_{ D} : RST_DLY_2_{ D} RST_DLY_2_{ E}: inst_RESET_OUT{ D} RST_DLY_0_{ D} RST_DLY_1_{ D} : RST_DLY_2_{ D} -CLK_000_P_SYNC_0_{ F}:CLK_000_P_SYNC_1_{ B} -CLK_000_P_SYNC_1_{ C}:CLK_000_P_SYNC_2_{ G} -CLK_000_P_SYNC_2_{ H}:CLK_000_P_SYNC_3_{ E} -CLK_000_P_SYNC_3_{ F}:CLK_000_P_SYNC_4_{ G} -CLK_000_P_SYNC_4_{ H}:CLK_000_P_SYNC_5_{ G} -CLK_000_P_SYNC_5_{ H}:CLK_000_P_SYNC_6_{ A} -CLK_000_P_SYNC_6_{ B}:CLK_000_P_SYNC_7_{ B} -CLK_000_P_SYNC_7_{ C}:CLK_000_P_SYNC_8_{ G} -CLK_000_P_SYNC_8_{ H}:CLK_000_P_SYNC_9_{ G} -CLK_000_N_SYNC_0_{ F}:CLK_000_N_SYNC_1_{ A} -CLK_000_N_SYNC_1_{ B}:CLK_000_N_SYNC_2_{ B} -CLK_000_N_SYNC_2_{ C}:CLK_000_N_SYNC_3_{ B} -CLK_000_N_SYNC_3_{ C}:CLK_000_N_SYNC_4_{ B} -CLK_000_N_SYNC_4_{ C}:CLK_000_N_SYNC_5_{ D} -CLK_000_N_SYNC_5_{ E}:CLK_000_N_SYNC_6_{ G} -CLK_000_N_SYNC_6_{ H}:CLK_000_N_SYNC_7_{ F} -CLK_000_N_SYNC_7_{ G}:CLK_000_N_SYNC_8_{ A} -CLK_000_N_SYNC_8_{ B}:CLK_000_N_SYNC_9_{ A} -CLK_000_N_SYNC_9_{ B}: DSACK1{ H}CLK_000_N_SYNC_10_{ H} -CLK_000_N_SYNC_10_{ I}: DSACK1{ H}CLK_000_N_SYNC_11_{ H} -SM_AMIGA_6_{ G}: N_317_i{ F} SM_AMIGA_5_{ F}inst_UDS_000_INT{ A} - :inst_LDS_000_INT{ A}inst_DS_000_ENABLE{ C} SM_AMIGA_6_{ F} +CLK_000_P_SYNC_0_{ E}:CLK_000_P_SYNC_1_{ A} +CLK_000_P_SYNC_1_{ B}:CLK_000_P_SYNC_2_{ F} +CLK_000_P_SYNC_2_{ G}:CLK_000_P_SYNC_3_{ C} +CLK_000_P_SYNC_3_{ D}:CLK_000_P_SYNC_4_{ A} +CLK_000_P_SYNC_4_{ B}:CLK_000_P_SYNC_5_{ G} +CLK_000_P_SYNC_5_{ H}:CLK_000_P_SYNC_6_{ G} +CLK_000_P_SYNC_6_{ H}:CLK_000_P_SYNC_7_{ D} +CLK_000_P_SYNC_7_{ E}:CLK_000_P_SYNC_8_{ A} +CLK_000_P_SYNC_8_{ B}:CLK_000_P_SYNC_9_{ C} +CLK_000_P_SYNC_9_{ D}:CLK_000_P_SYNC_10_{ A} +CLK_000_N_SYNC_1_{ F}:CLK_000_N_SYNC_2_{ A} +CLK_000_N_SYNC_2_{ B}:CLK_000_N_SYNC_3_{ F} +CLK_000_N_SYNC_3_{ G}:CLK_000_N_SYNC_4_{ A} +CLK_000_N_SYNC_4_{ B}:CLK_000_N_SYNC_5_{ A} +CLK_000_N_SYNC_5_{ B}:CLK_000_N_SYNC_6_{ B} +CLK_000_N_SYNC_6_{ C}:CLK_000_N_SYNC_7_{ G} +CLK_000_N_SYNC_7_{ H}:CLK_000_N_SYNC_8_{ B} +CLK_000_N_SYNC_8_{ C}:CLK_000_N_SYNC_9_{ F} +CLK_000_N_SYNC_9_{ G}:CLK_000_N_SYNC_10_{ C} +CLK_000_N_SYNC_10_{ D}:CLK_000_N_SYNC_11_{ C} +CLK_000_N_SYNC_11_{ D}:CLK_000_N_SYNC_12_{ D} +inst_CLK_000_NE_D0{ F}: cpu_est_2_{ F} cpu_est_3_{ F} cpu_est_0_{ B} + : cpu_est_1_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + : SM_AMIGA_i_7_{ F} +inst_AMIGA_BUS_ENABLE_DMA_HIGH{ D}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C} +SM_AMIGA_6_{ D}: N_226{ F}inst_UDS_000_INT{ B}inst_LDS_000_INT{ A} + : SM_AMIGA_5_{ F}inst_DS_000_ENABLE{ F} SM_AMIGA_6_{ C} : SM_AMIGA_i_7_{ F} inst_CLK_030_H{ B}:inst_DS_000_DMA{ A} inst_CLK_030_H{ A} -SM_AMIGA_1_{ G}: DSACK1{ H} N_317_i{ F} SM_AMIGA_0_{ F} +SM_AMIGA_1_{ G}: DSACK1{ H} N_226{ F} SM_AMIGA_0_{ F} : SM_AMIGA_1_{ F} SM_AMIGA_i_7_{ F} -SM_AMIGA_3_{ G}: N_317_i{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} +SM_AMIGA_3_{ G}: N_226{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} : SM_AMIGA_i_7_{ F} -SM_AMIGA_2_{ G}: N_317_i{ F} SM_AMIGA_1_{ F} SM_AMIGA_2_{ F} +SM_AMIGA_2_{ G}: N_226{ F} SM_AMIGA_1_{ F} SM_AMIGA_2_{ F} : SM_AMIGA_i_7_{ F} SM_AMIGA_i_7_{ G}:AMIGA_BUS_ENABLE_HIGH{ D} RW_000{ H}inst_AS_030_000_SYNC{ C} - :inst_DS_000_ENABLE{ C} SM_AMIGA_6_{ F} + :inst_DS_000_ENABLE{ F} SM_AMIGA_6_{ C} CIIN_0{ F}: CIIN{ E} ----------------------------------------------------------------------------- @@ -704,23 +730,26 @@ Equations : +-----+-----+-----+-----+------------------------ | | | | | DS_030 | | | | | AVEC -| * | S | BS | BR | inst_nEXP_SPACE_D0reg -| * | S | BS | BR | inst_CLK_OUT_PRE_D +| * | S | BS | BR | CLK_000_P_SYNC_10_ | * | S | BS | BR | inst_AS_000_DMA | * | S | BS | BR | inst_LDS_000_INT -| * | S | BS | BR | inst_UDS_000_INT +| * | S | BS | BR | inst_VPA_D | * | S | BS | BR | inst_DS_000_DMA | * | S | BS | BR | inst_CLK_030_H -| * | S | BS | BR | CLK_000_N_SYNC_9_ -| * | S | BS | BR | CLK_000_N_SYNC_8_ -| * | S | BS | BR | CLK_000_N_SYNC_1_ -| * | S | BS | BR | CLK_000_P_SYNC_6_ -| | | | | A_19_ -| | | | | A_16_ -| | | | | A_18_ +| * | S | BS | BR | CYCLE_DMA_1_ +| * | S | BS | BR | CYCLE_DMA_0_ +| * | S | BS | BR | CLK_000_N_SYNC_5_ +| * | S | BS | BR | CLK_000_N_SYNC_4_ +| * | S | BS | BR | CLK_000_N_SYNC_2_ +| * | S | BS | BR | CLK_000_P_SYNC_8_ +| * | S | BS | BR | CLK_000_P_SYNC_4_ +| * | S | BS | BR | CLK_000_P_SYNC_1_ +| | | | | A_DECODE_19_ +| | | | | A_DECODE_16_ +| | | | | A_DECODE_18_ | | | | | FPU_SENSE -| | | | | A_21_ -| | | | | A_20_ +| | | | | A_DECODE_21_ +| | | | | A_DECODE_20_ Block B @@ -730,28 +759,25 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ +| | | | | AHIGH_29_ +| | | | | AHIGH_30_ +| | | | | AHIGH_31_ | * | S | BS | BR | IPL_030_2_ | * | S | BS | BR | IPL_030_0_ | * | S | BS | BR | IPL_030_1_ | * | S | BS | BR | CLK_EXP | | | | | RESET -| * | S | BS | BR | CYCLE_DMA_0_ -| * | S | BS | BR | CLK_000_D_0_ -| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH +| * | S | BS | BR | cpu_est_0_ +| * | S | BS | BR | inst_UDS_000_INT | * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ | * | S | BS | BR | RN_IPL_030_2_ -| * | S | BS | BR | CLK_000_N_SYNC_4_ -| * | S | BS | BR | CLK_000_N_SYNC_3_ -| * | S | BS | BR | CLK_000_N_SYNC_2_ -| * | S | BS | BR | CLK_000_P_SYNC_7_ -| * | S | BS | BR | CLK_000_P_SYNC_1_ +| * | S | BS | BR | CLK_000_N_SYNC_8_ +| * | S | BS | BR | CLK_000_N_SYNC_6_ +| * | S | BS | BR | CLK_000_D_8_ +| * | S | BS | BR | CLK_000_D_6_ | * | S | BS | BR | IPL_D0_2_ -| * | S | BS | BR | inst_DTACK_D0 -| | | | | A_29_ -| | | | | A_30_ -| | | | | A_31_ Block C @@ -761,17 +787,23 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ +| | | | | AHIGH_24_ +| | | | | AHIGH_25_ +| | | | | AHIGH_26_ +| | | | | AHIGH_27_ +| | | | | AHIGH_28_ | | | | | AMIGA_BUS_ENABLE_LOW +| * | S | BS | BR | SM_AMIGA_6_ | * | S | BS | BR | inst_AS_030_000_SYNC -| * | S | BS | BR | inst_DS_000_ENABLE -| * | S | BS | BR | CYCLE_DMA_1_ -| * | S | BS | BR | inst_AS_000_INT +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH +| * | S | BS | BR | CLK_000_D_1_ +| * | S | BS | BR | CLK_000_N_SYNC_11_ +| * | S | BS | BR | CLK_000_N_SYNC_10_ +| * | S | BS | BR | CLK_000_P_SYNC_9_ +| * | S | BS | BR | CLK_000_P_SYNC_3_ +| * | S | BS | BR | CLK_000_D_4_ +| * | S | BS | BR | inst_DTACK_D0 | | | | | BG_030 -| | | | | A_24_ -| | | | | A_25_ -| | | | | A_26_ -| | | | | A_27_ -| | | | | A_28_ Block D @@ -788,17 +820,17 @@ Equations : | * | S | BS | BR | BG_000 | | | | | AMIGA_ADDR_ENABLE | * | S | BS | BR | inst_RESET_OUT -| * | S | BS | BR | cpu_est_2_ -| * | S | BS | BR | cpu_est_1_ +| * | S | BS | BR | CLK_000_N_SYNC_12_ +| * | S | BS | BR | CLK_000_N_SYNC_0_ | * | S | BS | BR | RN_VMA -| * | S | BS | BR | cpu_est_0_ -| * | S | BS | BR | inst_CLK_000_NE_D0 | * | S | BS | BR | RST_DLY_1_ | * | S | BS | BR | RST_DLY_0_ | * | S | BS | BR | RN_BG_000 | * | S | BS | BR | RST_DLY_2_ -| * | S | BS | BR | CLK_000_N_SYNC_5_ -| * | S | BS | BR | IPL_D0_1_ +| * | S | BS | BR | CLK_000_P_SYNC_7_ +| * | S | BS | BR | CLK_000_P_SYNC_0_ +| * | S | BS | BR | CLK_000_D_9_ +| * | S | BS | BR | IPL_D0_0_ | | | | | BGACK_000 | | | | | DTACK @@ -810,15 +842,16 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| | | | | AS_000 | | | | | BERR +| | | | | AS_000 | | | | | AMIGA_BUS_DATA_DIR | | | | | CIIN -| * | S | BS | BR | CLK_000_D_1_ +| * | S | BS | BR | inst_CLK_OUT_PRE_D +| * | S | BS | BR | inst_CLK_000_NE_D0 | | | | | CIIN_0 -| * | S | BS | BR | CLK_000_N_SYNC_0_ -| * | S | BS | BR | CLK_000_P_SYNC_3_ -| * | S | BS | BR | CLK_000_P_SYNC_0_ +| * | S | BS | BR | CLK_000_N_SYNC_1_ +| * | S | BS | BR | CLK_000_D_5_ +| * | S | BS | BR | inst_CLK_OUT_PRE_50 Block F @@ -829,23 +862,26 @@ Equations : | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | * | S | BS | BR | SM_AMIGA_i_7_ -| * | S | BS | BR | SM_AMIGA_6_ +| * | S | BS | BR | cpu_est_2_ | * | S | BS | BR | SM_AMIGA_5_ +| * | S | BS | BR | cpu_est_1_ | * | S | BS | BR | cpu_est_3_ | * | S | BS | BR | SM_AMIGA_0_ +| * | S | BS | BR | inst_DS_000_ENABLE | * | S | BS | BR | SM_AMIGA_1_ -| * | S | BS | BR | SM_AMIGA_4_ -| * | S | BS | BR | inst_CLK_OUT_PRE_50 -| * | S | BS | BR | inst_VPA_D | * | S | BS | BR | SM_AMIGA_3_ | * | S | BS | BR | SM_AMIGA_2_ -| | | | | N_317_i -| * | S | BS | BR | CLK_000_N_SYNC_7_ -| | | | | A_17_ +| * | S | BS | BR | SM_AMIGA_4_ +| | | | | N_226 +| * | S | BS | BR | CLK_000_N_SYNC_9_ +| * | S | BS | BR | CLK_000_N_SYNC_3_ +| * | S | BS | BR | CLK_000_P_SYNC_2_ +| * | S | BS | BR | IPL_D0_1_ +| | | | | A_DECODE_17_ | | | | | FC_1_ | | | | | FC_0_ +| | | | | A_1_ | | | | | IPL_1_ -| | | | | A1 Block G @@ -855,24 +891,24 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ +| * | S | BS | BR | A_0_ | * | S | BS | BR | RW -| * | S | BS | BR | A0 | | | | | SIZE_0_ | | | | | E | * | S | BS | BR | CLK_DIV_OUT -| * | S | BS | BR | inst_CLK_000_PE | * | S | BS | BR | SIZE_DMA_1_ | * | S | BS | BR | SIZE_DMA_0_ -| * | S | BS | BR | inst_CLK_000_NE -| * | S | BS | BR | RN_A0 +| * | S | BS | BR | inst_AS_000_INT +| * | S | BS | BR | CLK_000_D_0_ +| * | S | BS | BR | RN_A_0_ | * | S | BS | BR | RN_RW -| * | S | BS | BR | CLK_000_N_SYNC_6_ -| * | S | BS | BR | CLK_000_P_SYNC_8_ +| * | S | BS | BR | CLK_000_N_SYNC_7_ +| * | S | BS | BR | CLK_000_P_SYNC_6_ | * | S | BS | BR | CLK_000_P_SYNC_5_ -| * | S | BS | BR | CLK_000_P_SYNC_4_ -| * | S | BS | BR | CLK_000_P_SYNC_2_ -| * | S | BS | BR | IPL_D0_0_ -| * | S | BS | BR | CLK_000_P_SYNC_9_ +| * | S | BS | BR | CLK_000_D_7_ +| * | S | BS | BR | CLK_000_D_3_ +| * | S | BS | BR | CLK_000_D_2_ +| * | S | BS | BR | CLK_000_D_10_ | | | | | IPL_0_ | | | | | IPL_2_ @@ -895,10 +931,10 @@ Equations : | * | S | BS | BR | inst_BGACK_030_INT_D | * | S | BS | BR | RN_DSACK1 | * | S | BS | BR | RN_RW_000 -| * | S | BS | BR | CLK_000_N_SYNC_10_ -| * | S | BS | BR | CLK_000_N_SYNC_11_ -| | | | | A_23_ -| | | | | A_22_ +| * | S | BS | BR | CLK_000_D_12_ +| * | S | BS | BR | CLK_000_D_11_ +| | | | | A_DECODE_23_ +| | | | | A_DECODE_22_ (S) means the macrocell is configured in synchronous mode @@ -915,23 +951,23 @@ BLOCK_A_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx A0 A0 pin 69 mx A17 SIZE_0_ pin 70 -mx A1 ... ... mx A18inst_LDS_000_INT mcell A5 -mx A2CLK_000_N_SYNC_0_ mcell E9 mx A19inst_UDS_000_INT mcell A9 -mx A3inst_nEXP_SPACE_D0reg mcell A8 mx A20 CLK_030 pin 64 -mx A4 CYCLE_DMA_1_ mcell C12 mx A21 RST pin 86 -mx A5 nEXP_SPACE pin 14 mx A22 inst_CLK_030_H mcell A2 -mx A6 RW_000 pin 80 mx A23 RN_BGACK_030 mcell H4 -mx A7CLK_000_N_SYNC_7_ mcell F3 mx A24 LDS_000 pin 31 -mx A8 UDS_000 pin 32 mx A25 inst_DS_000_DMA mcell A13 -mx A9 inst_AS_000_DMA mcell A1 mx A26 ... ... -mx A10 SM_AMIGA_6_ mcell F4 mx A27 SIZE_1_ pin 79 -mx A11CLK_000_P_SYNC_5_ mcell G14 mx A28 CYCLE_DMA_0_ mcell B5 -mx A12 inst_RESET_OUT mcell D9 mx A29 ... ... -mx A13 ... ... mx A30 ... ... -mx A14CLK_000_N_SYNC_8_ mcell A10 mx A31 ... ... -mx A15inst_CLK_OUT_PRE_50 mcell F13 mx A32 ... ... -mx A16 AS_000 pin 42 +mx A0 A_0_ pin 69 mx A17 SIZE_0_ pin 70 +mx A1 ... ... mx A18CLK_000_P_SYNC_10_ mcell A8 +mx A2CLK_000_N_SYNC_1_ mcell E9 mx A19 inst_DS_000_DMA mcell A9 +mx A3CLK_000_N_SYNC_4_ mcell A14 mx A20 SIZE_1_ pin 79 +mx A4 CLK_030 pin 64 mx A21inst_LDS_000_INT mcell A1 +mx A5 nEXP_SPACE pin 14 mx A22 CYCLE_DMA_1_ mcell A2 +mx A6CLK_000_P_SYNC_3_ mcell C7 mx A23 SM_AMIGA_6_ mcell C9 +mx A7 inst_RESET_OUT mcell D9 mx A24 RST pin 86 +mx A8 UDS_000 pin 32 mx A25 inst_CLK_030_H mcell A13 +mx A9CLK_000_P_SYNC_7_ mcell D3 mx A26 AS_000 pin 42 +mx A10 VPA pin 36 mx A27 LDS_000 pin 31 +mx A11 ... ... mx A28 RW_000 pin 80 +mx A12CLK_000_P_SYNC_9_ mcell C3 mx A29 ... ... +mx A13CLK_000_P_SYNC_0_ mcell D7 mx A30 RN_BGACK_030 mcell H6 +mx A14 CYCLE_DMA_0_ mcell A10 mx A31 ... ... +mx A15 inst_AS_000_DMA mcell A12 mx A32 ... ... +mx A16CLK_000_N_SYNC_3_ mcell F7 ---------------------------------------------------------------------------- @@ -939,23 +975,23 @@ BLOCK_B_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx B0 IPL_0_ pin 67 mx B17 ... ... -mx B1 RN_IPL_030_1_ mcell B12 mx B18 ... ... -mx B2 IPL_D0_1_ mcell D15 mx B19inst_BGACK_030_INT_D mcell H13 -mx B3 CLK_000 pin 11 mx B20CLK_000_N_SYNC_1_ mcell A14 -mx B4 IPL_2_ pin 68 mx B21 IPL_1_ pin 56 -mx B5 ... ... mx B22 inst_CLK_000_PE mcell G5 -mx B6CLK_000_P_SYNC_6_ mcell A3 mx B23 RN_BGACK_030 mcell H4 -mx B7 IPL_D0_2_ mcell B11 mx B24 RST pin 86 -mx B8 RN_IPL_030_0_ mcell B8 mx B25 inst_RESET_OUT mcell D9 -mx B9inst_CLK_OUT_PRE_D mcell A12 mx B26 ... ... -mx B10inst_AMIGA_BUS_ENABLE_DMA_LOW mcell B2 mx B27 RN_IPL_030_2_ mcell B4 -mx B11 A1 pin 60 mx B28inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell B13 -mx B12CLK_000_N_SYNC_3_ mcell B10 mx B29CLK_000_N_SYNC_2_ mcell B14 -mx B13 IPL_D0_0_ mcell G11 mx B30 ... ... -mx B14 DTACK pin 30 mx B31 CYCLE_DMA_0_ mcell B5 -mx B15CLK_000_P_SYNC_0_ mcell E2 mx B32 ... ... -mx B16 AS_000 pin 42 +mx B0 IPL_0_ pin 67 mx B17 RN_IPL_030_0_ mcell B8 +mx B1 ... ... mx B18 A_0_ pin 69 +mx B2 IPL_D0_0_ mcell D15 mx B19 IPL_D0_1_ mcell F15 +mx B3 SM_AMIGA_6_ mcell C9 mx B20 ... ... +mx B4 IPL_2_ pin 68 mx B21 RST pin 86 +mx B5CLK_000_N_SYNC_7_ mcell G6 mx B22CLK_000_N_SYNC_5_ mcell A6 +mx B6 RN_IPL_030_1_ mcell B9 mx B23 A_1_ pin 60 +mx B7inst_BGACK_030_INT_D mcell H13 mx B24 CLK_000_D_7_ mcell G3 +mx B8 IPL_D0_2_ mcell B15 mx B25 inst_RESET_OUT mcell D9 +mx B9 ... ... mx B26 ... ... +mx B10 cpu_est_0_ mcell B2 mx B27 RN_IPL_030_2_ mcell B4 +mx B11inst_UDS_000_INT mcell B6 mx B28 ... ... +mx B12inst_AMIGA_BUS_ENABLE_DMA_LOW mcell B10 mx B29 ... ... +mx B13 CLK_000_D_5_ mcell E13 mx B30 RN_BGACK_030 mcell H6 +mx B14inst_CLK_000_NE_D0 mcell E5 mx B31 IPL_1_ pin 56 +mx B15 nEXP_SPACE pin 14 mx B32 ... ... +mx B16inst_CLK_OUT_PRE_D mcell E8 ---------------------------------------------------------------------------- @@ -963,23 +999,23 @@ BLOCK_C_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx C0 RN_BGACK_030 mcell H4 mx C17 FC_0_ pin 57 -mx C1 inst_AS_000_INT mcell C1 mx C18 SM_AMIGA_4_ mcell F9 -mx C2 SM_AMIGA_5_ mcell F8 mx C19inst_BGACK_030_INT_D mcell H13 -mx C3inst_nEXP_SPACE_D0reg mcell A8 mx C20 FC_1_ pin 58 -mx C4 A_18_ pin 95 mx C21 RST pin 86 -mx C5 SM_AMIGA_i_7_ mcell F0 mx C22 inst_CLK_000_PE mcell G5 -mx C6 A_16_ pin 96 mx C23 ... ... -mx C7inst_DS_000_ENABLE mcell C8 mx C24 ... ... -mx C8 RW pin 71 mx C25 BERR pin 41 -mx C9 ... ... mx C26 ... ... -mx C10inst_AMIGA_BUS_ENABLE_DMA_LOW mcell B2 mx C27 ... ... -mx C11 inst_AS_030_D0 mcell H3 mx C28 CYCLE_DMA_0_ mcell B5 -mx C12 A_19_ pin 97 mx C29 SM_AMIGA_6_ mcell F4 -mx C13 A_17_ pin 59 mx C30 SM_AMIGA_0_ mcell F1 -mx C14inst_AS_030_000_SYNC mcell C4 mx C31 ... ... -mx C15 CYCLE_DMA_1_ mcell C12 mx C32 ... ... -mx C16 AS_000 pin 42 +mx C0 RST pin 86 mx C17CLK_000_N_SYNC_9_ mcell F3 +mx C1 BERR pin 41 mx C18CLK_000_P_SYNC_10_ mcell A8 +mx C2inst_AMIGA_BUS_ENABLE_DMA_LOW mcell B10 mx C19inst_BGACK_030_INT_D mcell H13 +mx C3 A_1_ pin 60 mx C20CLK_000_P_SYNC_2_ mcell F11 +mx C4 A_DECODE_18_ pin 95 mx C21 RN_BGACK_030 mcell H6 +mx C5 SM_AMIGA_i_7_ mcell F0 mx C22inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell C2 +mx C6 FC_0_ pin 57 mx C23 ... ... +mx C7 inst_RESET_OUT mcell D9 mx C24 ... ... +mx C8 A_DECODE_17_ pin 59 mx C25 CLK_000_D_0_ mcell G13 +mx C9 DTACK pin 30 mx C26 CLK_000_D_3_ mcell G7 +mx C10 inst_AS_030_D0 mcell H1 mx C27 A_DECODE_19_ pin 97 +mx C11 A_DECODE_16_ pin 96 mx C28CLK_000_P_SYNC_8_ mcell A7 +mx C12 FC_1_ pin 58 mx C29 ... ... +mx C13 SM_AMIGA_6_ mcell C9 mx C30inst_AS_030_000_SYNC mcell C13 +mx C14 ... ... mx C31CLK_000_N_SYNC_10_ mcell C14 +mx C15 nEXP_SPACE pin 14 mx C32 ... ... +mx C16CLK_000_N_SYNC_0_ mcell D2 ---------------------------------------------------------------------------- @@ -987,23 +1023,23 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 RN_BGACK_030 mcell H4 mx D17 RST_DLY_1_ mcell D14 -mx D1 cpu_est_3_ mcell F12 mx D18 inst_AS_030_D0 mcell H3 -mx D2 RN_BG_000 mcell D1 mx D19inst_UDS_000_INT mcell A9 -mx D3 cpu_est_1_ mcell D2 mx D20inst_CLK_000_NE_D0 mcell D10 -mx D4 BG_030 pin 21 mx D21 RST pin 86 -mx D5 SM_AMIGA_i_7_ mcell F0 mx D22 inst_CLK_000_PE mcell G5 -mx D6 CLK_000_D_0_ mcell B9 mx D23 inst_CLK_000_NE mcell G2 -mx D7inst_DS_000_ENABLE mcell C8 mx D24 ... ... -mx D8 RST_DLY_2_ mcell D7 mx D25 ... ... -mx D9 RST_DLY_0_ mcell D3 mx D26 RN_VMA mcell D0 -mx D10inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell B13 mx D27 ... ... -mx D11CLK_000_N_SYNC_4_ mcell B6 mx D28inst_LDS_000_INT mcell A5 -mx D12 inst_RESET_OUT mcell D9 mx D29 cpu_est_2_ mcell D13 -mx D13 ... ... mx D30inst_nEXP_SPACE_D0reg mcell A8 -mx D14 ... ... mx D31 IPL_1_ pin 56 -mx D15 inst_VPA_D mcell F2 mx D32 ... ... -mx D16 cpu_est_0_ mcell D6 +mx D0 RST pin 86 mx D17 RN_BG_000 mcell D1 +mx D1inst_DS_000_ENABLE mcell F9 mx D18 CLK_000_D_1_ mcell C6 +mx D2 inst_VPA_D mcell A5 mx D19 inst_AS_030_D0 mcell H1 +mx D3 CLK_000 pin 11 mx D20 RST_DLY_0_ mcell D10 +mx D4 RST_DLY_1_ mcell D6 mx D21 nEXP_SPACE pin 14 +mx D5 SM_AMIGA_i_7_ mcell F0 mx D22inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell C2 +mx D6 ... ... mx D23 BG_030 pin 21 +mx D7 RN_BGACK_030 mcell H6 mx D24 RST_DLY_2_ mcell D14 +mx D8CLK_000_N_SYNC_11_ mcell C10 mx D25 CLK_000_D_0_ mcell G13 +mx D9inst_LDS_000_INT mcell A1 mx D26 RN_VMA mcell D0 +mx D10 cpu_est_0_ mcell B2 mx D27 SM_AMIGA_0_ mcell F5 +mx D11inst_UDS_000_INT mcell B6 mx D28CLK_000_P_SYNC_6_ mcell G10 +mx D12 inst_RESET_OUT mcell D9 mx D29CLK_000_N_SYNC_12_ mcell D13 +mx D13 ... ... mx D30CLK_000_P_SYNC_10_ mcell A8 +mx D14 cpu_est_2_ mcell F4 mx D31 cpu_est_1_ mcell F12 +mx D15 cpu_est_3_ mcell F1 mx D32 CLK_000_D_8_ mcell B7 +mx D16 IPL_0_ pin 67 ---------------------------------------------------------------------------- @@ -1011,23 +1047,23 @@ BLOCK_E_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx E0 RN_BGACK_030 mcell H4 mx E17 A_26_ pin 17 -mx E1 A_31_ pin 4 mx E18 A_23_ pin 85 -mx E2 AS_000 pin 42 mx E19 A_30_ pin 5 -mx E3 A_25_ pin 18 mx E20 FC_1_ pin 58 -mx E4 BGACK_000 pin 28 mx E21 A_27_ pin 16 -mx E5 A_24_ pin 19 mx E22 inst_AS_000_INT mcell C1 -mx E6 CLK_000_D_0_ mcell B9 mx E23 ... ... -mx E7 A_28_ pin 15 mx E24 FC_0_ pin 57 -mx E8CLK_000_P_SYNC_2_ mcell G7 mx E25 inst_RESET_OUT mcell D9 -mx E9 A_22_ pin 84 mx E26 A_16_ pin 96 -mx E10 inst_AS_030_D0 mcell H3 mx E27 A_17_ pin 59 -mx E11 FPU_SENSE pin 91 mx E28 RW_000 pin 80 -mx E12 A_19_ pin 97 mx E29 A_20_ pin 93 -mx E13 A_29_ pin 6 mx E30inst_nEXP_SPACE_D0reg mcell A8 -mx E14 CIIN_0 mcell E5 mx E31 A_18_ pin 95 -mx E15 A_21_ pin 94 mx E32 AS_030 pin 82 -mx E16 CLK_000_D_1_ mcell E8 +mx E0 CLK_000_D_4_ mcell C11 mx E17 A_DECODE_18_ pin 95 +mx E1 FC_1_ pin 58 mx E18 A_DECODE_23_ pin 85 +mx E2 AS_000 pin 42 mx E19 AS_030 pin 82 +mx E3 A_DECODE_20_ pin 93 mx E20 A_DECODE_22_ pin 84 +mx E4 AHIGH_29_ pin 6 mx E21 RW_000 pin 80 +mx E5 AHIGH_24_ pin 19 mx E22 AHIGH_25_ pin 18 +mx E6 A_DECODE_19_ pin 97 mx E23 inst_AS_000_INT mcell G2 +mx E7 inst_RESET_OUT mcell D9 mx E24 FC_0_ pin 57 +mx E8 FPU_SENSE pin 91 mx E25 AHIGH_31_ pin 4 +mx E9 AHIGH_26_ pin 17 mx E26 A_DECODE_16_ pin 96 +mx E10 inst_AS_030_D0 mcell H1 mx E27inst_CLK_OUT_PRE_50 mcell E2 +mx E11 AHIGH_27_ pin 16 mx E28 AHIGH_30_ pin 5 +mx E12 CIIN_0 mcell E10 mx E29CLK_000_N_SYNC_12_ mcell D13 +mx E13 A_DECODE_17_ pin 59 mx E30 RN_BGACK_030 mcell H6 +mx E14 AHIGH_28_ pin 15 mx E31 A_DECODE_21_ pin 94 +mx E15 nEXP_SPACE pin 14 mx E32 BGACK_000 pin 28 +mx E16CLK_000_N_SYNC_0_ mcell D2 ---------------------------------------------------------------------------- @@ -1035,23 +1071,23 @@ BLOCK_F_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx F0 RST pin 86 mx F17 cpu_est_3_ mcell F12 -mx F1 BERR pin 41 mx F18 SM_AMIGA_4_ mcell F9 -mx F2 SM_AMIGA_2_ mcell F10 mx F19 inst_DTACK_D0 mcell B15 -mx F3inst_nEXP_SPACE_D0reg mcell A8 mx F20inst_CLK_000_NE_D0 mcell D10 -mx F4 inst_CLK_000_NE mcell G2 mx F21 cpu_est_2_ mcell D13 -mx F5CLK_000_N_SYNC_6_ mcell G6 mx F22 inst_CLK_000_PE mcell G5 -mx F6inst_CLK_OUT_PRE_50 mcell F13 mx F23 ... ... -mx F7 ... ... mx F24 N_317_i mcell F14 -mx F8 CLK_000_D_1_ mcell E8 mx F25 SM_AMIGA_i_7_ mcell F0 -mx F9 inst_VPA_D mcell F2 mx F26 RN_VMA mcell D0 -mx F10 SM_AMIGA_6_ mcell F4 mx F27 ... ... -mx F11 SM_AMIGA_3_ mcell F6 mx F28 ... ... -mx F12 ... ... mx F29inst_AS_030_000_SYNC mcell C4 -mx F13 VPA pin 36 mx F30 cpu_est_0_ mcell D6 -mx F14 SM_AMIGA_1_ mcell F5 mx F31 CLK_000_D_0_ mcell B9 -mx F15 SM_AMIGA_0_ mcell F1 mx F32 SM_AMIGA_5_ mcell F8 -mx F16 cpu_est_1_ mcell D2 +mx F0inst_AS_030_000_SYNC mcell C13 mx F17 cpu_est_1_ mcell F12 +mx F1 BERR pin 41 mx F18 cpu_est_0_ mcell B2 +mx F2 SM_AMIGA_5_ mcell F8 mx F19 SM_AMIGA_4_ mcell F10 +mx F3CLK_000_P_SYNC_10_ mcell A8 mx F20CLK_000_N_SYNC_8_ mcell B14 +mx F4 ... ... mx F21 RST pin 86 +mx F5 SM_AMIGA_i_7_ mcell F0 mx F22 inst_DTACK_D0 mcell C15 +mx F6 SM_AMIGA_1_ mcell F13 mx F23 SM_AMIGA_6_ mcell C9 +mx F7 ... ... mx F24 N_226 mcell F14 +mx F8 RW pin 71 mx F25CLK_000_N_SYNC_2_ mcell A3 +mx F9 SM_AMIGA_3_ mcell F2 mx F26 RN_VMA mcell D0 +mx F10 cpu_est_2_ mcell F4 mx F27 SM_AMIGA_0_ mcell F5 +mx F11 SM_AMIGA_2_ mcell F6 mx F28 inst_VPA_D mcell A5 +mx F12 inst_AS_030_D0 mcell H1 mx F29CLK_000_N_SYNC_12_ mcell D13 +mx F13CLK_000_P_SYNC_1_ mcell A15 mx F30 cpu_est_3_ mcell F1 +mx F14inst_CLK_000_NE_D0 mcell E5 mx F31 IPL_1_ pin 56 +mx F15 nEXP_SPACE pin 14 mx F32inst_DS_000_ENABLE mcell F9 +mx F16CLK_000_N_SYNC_0_ mcell D2 ---------------------------------------------------------------------------- @@ -1059,23 +1095,23 @@ BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx G0 IPL_0_ pin 67 mx G17 RN_RW mcell G0 -mx G1CLK_000_P_SYNC_1_ mcell B7 mx G18inst_nEXP_SPACE_D0reg mcell A8 -mx G2CLK_000_P_SYNC_9_ mcell G15 mx G19CLK_000_P_SYNC_7_ mcell B3 -mx G3CLK_000_N_SYNC_5_ mcell D11 mx G20 RN_BGACK_030 mcell H4 -mx G4 ... ... mx G21 RST pin 86 -mx G5CLK_000_P_SYNC_4_ mcell G3 mx G22CLK_000_P_SYNC_8_ mcell G10 +mx G0 RN_RW mcell G0 mx G17 cpu_est_1_ mcell F12 +mx G1 BERR pin 41 mx G18 CLK_000_D_1_ mcell C6 +mx G2 SM_AMIGA_5_ mcell F8 mx G19inst_BGACK_030_INT_D mcell H13 +mx G3 CLK_000_D_9_ mcell D11 mx G20 UDS_000 pin 32 +mx G4 inst_AS_000_INT mcell G2 mx G21 RST pin 86 +mx G5CLK_000_N_SYNC_6_ mcell B3 mx G22 SIZE_DMA_1_ mcell G5 mx G6 RW_000 pin 80 mx G23 ... ... -mx G7CLK_000_N_SYNC_11_ mcell H6 mx G24 LDS_000 pin 31 -mx G8 UDS_000 pin 32 mx G25 inst_RESET_OUT mcell D9 -mx G9 SIZE_DMA_0_ mcell G13 mx G26 ... ... -mx G10 RN_A0 mcell G8 mx G27 ... ... -mx G11 ... ... mx G28inst_BGACK_030_INT_D mcell H13 -mx G12 SIZE_DMA_1_ mcell G9 mx G29 cpu_est_2_ mcell D13 -mx G13CLK_000_P_SYNC_3_ mcell E13 mx G30 ... ... -mx G14 ... ... mx G31 cpu_est_3_ mcell F12 -mx G15inst_CLK_OUT_PRE_D mcell A12 mx G32 ... ... -mx G16 cpu_est_1_ mcell D2 +mx G7 CLK_000_D_6_ mcell B11 mx G24 LDS_000 pin 31 +mx G8inst_CLK_OUT_PRE_D mcell E8 mx G25 inst_RESET_OUT mcell D9 +mx G9 CLK_000_D_2_ mcell G11 mx G26 ... ... +mx G10 cpu_est_3_ mcell F1 mx G27 SIZE_DMA_0_ mcell G9 +mx G11CLK_000_P_SYNC_5_ mcell G14 mx G28 RN_A_0_ mcell G8 +mx G12 inst_AS_030_D0 mcell H1 mx G29 cpu_est_2_ mcell F4 +mx G13CLK_000_P_SYNC_4_ mcell A11 mx G30 RN_BGACK_030 mcell H6 +mx G14 CLK_000 pin 11 mx G31 ... ... +mx G15 nEXP_SPACE pin 14 mx G32 ... ... +mx G16 ... ... ---------------------------------------------------------------------------- @@ -1083,23 +1119,23 @@ BLOCK_H_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx H0 RN_BGACK_030 mcell H4 mx H17 A_18_ pin 95 -mx H1 BERR pin 41 mx H18 inst_AS_030_D0 mcell H3 -mx H2 SM_AMIGA_5_ mcell F8 mx H19 FPU_SENSE pin 91 -mx H3inst_nEXP_SPACE_D0reg mcell A8 mx H20 CLK_030 pin 64 -mx H4 BGACK_000 pin 28 mx H21 RST pin 86 -mx H5 SM_AMIGA_i_7_ mcell F0 mx H22 inst_CLK_000_PE mcell G5 +mx H0 RST pin 86 mx H17 A_DECODE_18_ pin 95 +mx H1 BERR pin 41 mx H18 CLK_000_D_11_ mcell H10 +mx H2 AS_000 pin 42 mx H19 inst_AS_030_D0 mcell H1 +mx H3CLK_000_P_SYNC_10_ mcell A8 mx H20 SM_AMIGA_5_ mcell F8 +mx H4 CLK_000_D_12_ mcell H2 mx H21 RN_BGACK_030 mcell H6 +mx H5 nEXP_SPACE pin 14 mx H22 SIZE_DMA_1_ mcell G5 mx H6 FC_0_ pin 57 mx H23 RN_RW_000 mcell H0 -mx H7 inst_RESET_OUT mcell D9 mx H24inst_CLK_OUT_PRE_D mcell A12 -mx H8 RW pin 71 mx H25 SIZE_DMA_0_ mcell G13 -mx H9 inst_AS_000_DMA mcell A1 mx H26 A_16_ pin 96 -mx H10 SIZE_DMA_1_ mcell G9 mx H27 A_19_ pin 97 -mx H11 RN_DSACK1 mcell H9 mx H28CLK_000_N_SYNC_10_ mcell H2 +mx H7 inst_RESET_OUT mcell D9 mx H24 inst_AS_000_DMA mcell A12 +mx H8 FPU_SENSE pin 91 mx H25 RW pin 71 +mx H9 AS_030 pin 82 mx H26 A_DECODE_16_ pin 96 +mx H10 SIZE_DMA_0_ mcell G9 mx H27 A_DECODE_19_ pin 97 +mx H11 RN_DSACK1 mcell H9 mx H28 CLK_030 pin 64 mx H12 FC_1_ pin 58 mx H29 ... ... -mx H13 A_17_ pin 59 mx H30 SM_AMIGA_0_ mcell F1 -mx H14 SM_AMIGA_1_ mcell F5 mx H31 ... ... -mx H15CLK_000_N_SYNC_9_ mcell A6 mx H32 AS_030 pin 82 -mx H16 AS_000 pin 42 +mx H13 A_DECODE_17_ pin 59 mx H30 CLK_000_D_10_ mcell G15 +mx H14 SM_AMIGA_0_ mcell F5 mx H31 SM_AMIGA_i_7_ mcell F0 +mx H15 SM_AMIGA_1_ mcell F13 mx H32 BGACK_000 pin 28 +mx H16inst_CLK_OUT_PRE_D mcell E8 ---------------------------------------------------------------------------- CSM indicates the mux inputs from the Central Switch Matrix. @@ -1116,6 +1152,8 @@ PostFit_Equations --------- ------ ------- ---- ----------------- 1 2 1 Pin SIZE_1_ 1 2 1 Pin SIZE_1_.OE + 0 0 1 Pin AHIGH_31_ + 1 3 1 Pin AHIGH_31_.OE 1 2 1 Pin AS_030- 1 3 1 Pin AS_030.OE 1 2 1 Pin AS_000- @@ -1136,25 +1174,39 @@ PostFit_Equations 0 0 1 Pin RESET 1 1 1 Pin RESET.OE 0 0 1 Pin AMIGA_ADDR_ENABLE - 1 2 1 Pin SIZE_0_ - 1 2 1 Pin SIZE_0_.OE 2 4 1 Pin AMIGA_BUS_DATA_DIR 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- - 2 3 1 Pin AMIGA_BUS_ENABLE_HIGH + 3 5 1 Pin AMIGA_BUS_ENABLE_HIGH 1 13 1 Pin CIIN 1 1 1 Pin CIIN.OE + 1 2 1 Pin SIZE_0_ + 1 2 1 Pin SIZE_0_.OE + 0 0 1 Pin AHIGH_30_ + 1 3 1 Pin AHIGH_30_.OE + 0 0 1 Pin AHIGH_29_ + 1 3 1 Pin AHIGH_29_.OE + 0 0 1 Pin AHIGH_28_ + 1 3 1 Pin AHIGH_28_.OE + 0 0 1 Pin AHIGH_27_ + 1 3 1 Pin AHIGH_27_.OE + 0 0 1 Pin AHIGH_26_ + 1 3 1 Pin AHIGH_26_.OE + 0 0 1 Pin AHIGH_25_ + 1 3 1 Pin AHIGH_25_.OE + 0 0 1 Pin AHIGH_24_ + 1 3 1 Pin AHIGH_24_.OE 10 8 1 Pin IPL_030_2_.D- 1 1 1 Pin IPL_030_2_.C + 1 2 1 Pin RW_000.OE + 3 7 1 Pin RW_000.D- + 1 1 1 Pin RW_000.C + 1 3 1 Pin A_0_.OE + 3 5 1 Pin A_0_.D + 1 1 1 Pin A_0_.C 10 8 1 Pin IPL_030_1_.D- 1 1 1 Pin IPL_030_1_.C 10 8 1 Pin IPL_030_0_.D- 1 1 1 Pin IPL_030_0_.C - 1 2 1 Pin RW_000.OE - 3 7 1 Pin RW_000.D- - 1 1 1 Pin RW_000.C - 1 3 1 Pin A0.OE - 3 5 1 Pin A0.D - 1 1 1 Pin A0.C 2 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.C 3 5 1 Pin BGACK_030.D @@ -1162,14 +1214,14 @@ PostFit_Equations 1 1 1 Pin CLK_EXP.D 1 1 1 Pin CLK_EXP.C 1 1 1 Pin DSACK1.OE - 4 9 1 Pin DSACK1.D- + 4 10 1 Pin DSACK1.D- 1 1 1 Pin DSACK1.C 3 9 1 Pin VMA.T 1 1 1 Pin VMA.C 1 2 1 Pin RW.OE 2 5 1 Pin RW.D- 1 1 1 Pin RW.C - 4 11 1 Node N_317_i- + 3 10 1 Node N_226 4 4 1 Node cpu_est_2_.D 1 1 1 Node cpu_est_2_.C 3 5 1 Node cpu_est_3_.D @@ -1180,14 +1232,10 @@ PostFit_Equations 1 1 1 Node cpu_est_1_.C 2 5 1 Node inst_AS_000_INT.D- 1 1 1 Node inst_AS_000_INT.C - 3 6 1 Node SM_AMIGA_5_.D - 1 1 1 Node SM_AMIGA_5_.C 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C 1 2 1 Node inst_AS_030_D0.D- 1 1 1 Node inst_AS_030_D0.C - 1 2 1 Node inst_nEXP_SPACE_D0reg.D- - 1 1 1 Node inst_nEXP_SPACE_D0reg.C 7 14 1 Node inst_AS_030_000_SYNC.D- 1 1 1 Node inst_AS_030_000_SYNC.C 1 2 1 Node inst_BGACK_030_INT_D.D- @@ -1212,6 +1260,10 @@ PostFit_Equations 1 1 1 Node inst_LDS_000_INT.C 1 1 1 Node inst_CLK_OUT_PRE_D.D 1 1 1 Node inst_CLK_OUT_PRE_D.C + 1 1 1 Node CLK_000_D_10_.D + 1 1 1 Node CLK_000_D_10_.C + 1 1 1 Node CLK_000_D_11_.D + 1 1 1 Node CLK_000_D_11_.C 1 2 1 Node inst_DTACK_D0.D- 1 1 1 Node inst_DTACK_D0.C 2 6 1 Node inst_RESET_OUT.D @@ -1222,30 +1274,44 @@ PostFit_Equations 1 1 1 Node CLK_000_D_1_.C 1 1 1 Node CLK_000_D_0_.D 1 1 1 Node CLK_000_D_0_.C - 1 1 1 Node inst_CLK_000_PE.D - 1 1 1 Node inst_CLK_000_PE.C - 1 1 1 Node CLK_000_P_SYNC_9_.D - 1 1 1 Node CLK_000_P_SYNC_9_.C - 1 1 1 Node inst_CLK_000_NE.D - 1 1 1 Node inst_CLK_000_NE.C - 1 1 1 Node CLK_000_N_SYNC_11_.D - 1 1 1 Node CLK_000_N_SYNC_11_.C + 1 1 1 Node CLK_000_P_SYNC_10_.D + 1 1 1 Node CLK_000_P_SYNC_10_.C + 3 6 1 Node SM_AMIGA_5_.D + 1 1 1 Node SM_AMIGA_5_.C 1 2 1 Node IPL_D0_0_.D- 1 1 1 Node IPL_D0_0_.C 1 2 1 Node IPL_D0_1_.D- 1 1 1 Node IPL_D0_1_.C 1 2 1 Node IPL_D0_2_.D- 1 1 1 Node IPL_D0_2_.C - 1 1 1 Node inst_CLK_000_NE_D0.D - 1 1 1 Node inst_CLK_000_NE_D0.C + 1 1 1 Node CLK_000_D_2_.D + 1 1 1 Node CLK_000_D_2_.C + 1 1 1 Node CLK_000_D_3_.D + 1 1 1 Node CLK_000_D_3_.C + 1 1 1 Node CLK_000_D_4_.D + 1 1 1 Node CLK_000_D_4_.C + 1 1 1 Node CLK_000_D_5_.D + 1 1 1 Node CLK_000_D_5_.C + 1 1 1 Node CLK_000_D_6_.D + 1 1 1 Node CLK_000_D_6_.C + 1 1 1 Node CLK_000_D_7_.D + 1 1 1 Node CLK_000_D_7_.C + 1 1 1 Node CLK_000_D_8_.D + 1 1 1 Node CLK_000_D_8_.C + 1 1 1 Node CLK_000_D_9_.D + 1 1 1 Node CLK_000_D_9_.C + 1 1 1 Node CLK_000_D_12_.D + 1 1 1 Node CLK_000_D_12_.C 2 6 1 Node SM_AMIGA_0_.D 1 1 1 Node SM_AMIGA_0_.C - 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- - 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C + 1 2 1 Node CLK_000_N_SYNC_0_.D + 1 1 1 Node CLK_000_N_SYNC_0_.C 3 6 1 Node SM_AMIGA_4_.D 1 1 1 Node SM_AMIGA_4_.C 5 11 1 Node inst_DS_000_ENABLE.D 1 1 1 Node inst_DS_000_ENABLE.C + 1 1 1 Node CLK_000_N_SYNC_12_.D + 1 1 1 Node CLK_000_N_SYNC_12_.C 3 5 1 Node RST_DLY_0_.D 1 1 1 Node RST_DLY_0_.C 4 5 1 Node RST_DLY_1_.D @@ -1270,8 +1336,8 @@ PostFit_Equations 1 1 1 Node CLK_000_P_SYNC_7_.C 1 1 1 Node CLK_000_P_SYNC_8_.D 1 1 1 Node CLK_000_P_SYNC_8_.C - 1 2 1 Node CLK_000_N_SYNC_0_.D - 1 1 1 Node CLK_000_N_SYNC_0_.C + 1 1 1 Node CLK_000_P_SYNC_9_.D + 1 1 1 Node CLK_000_P_SYNC_9_.C 1 1 1 Node CLK_000_N_SYNC_1_.D 1 1 1 Node CLK_000_N_SYNC_1_.C 1 1 1 Node CLK_000_N_SYNC_2_.D @@ -1292,7 +1358,13 @@ PostFit_Equations 1 1 1 Node CLK_000_N_SYNC_9_.C 1 1 1 Node CLK_000_N_SYNC_10_.D 1 1 1 Node CLK_000_N_SYNC_10_.C - 3 9 1 Node SM_AMIGA_6_.D + 1 1 1 Node CLK_000_N_SYNC_11_.D + 1 1 1 Node CLK_000_N_SYNC_11_.C + 1 1 1 Node inst_CLK_000_NE_D0.D + 1 1 1 Node inst_CLK_000_NE_D0.C + 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- + 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C + 3 8 1 Node SM_AMIGA_6_.D 1 1 1 Node SM_AMIGA_6_.C 8 10 1 Node inst_CLK_030_H.D 1 1 1 Node inst_CLK_030_H.C @@ -1306,9 +1378,9 @@ PostFit_Equations 1 1 1 Node SM_AMIGA_i_7_.C 2 14 1 Node CIIN_0 ========= - 323 P-Term Total: 323 + 351 P-Term Total: 351 Total Pins: 61 - Total Nodes: 69 + Total Nodes: 79 Average P-Term/Output: 2 @@ -1316,11 +1388,15 @@ Equations: SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q); -SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q); +SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q); + +AHIGH_31_ = (0); + +AHIGH_31_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); !AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN); -AS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q); +AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); !AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN); @@ -1328,7 +1404,7 @@ AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); !DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN); -DS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q); +DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); !UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q); @@ -1340,13 +1416,13 @@ LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); BERR = (0); -BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); +BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q); CLK_DIV_OUT.C = (CLK_OSZI); -!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); +!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_DECODE_19_ & !A_DECODE_18_ & A_DECODE_17_ & !A_DECODE_16_ & FC_0_ & !AS_030.PIN); AVEC = (1); @@ -1359,22 +1435,51 @@ RESET.OE = (!inst_RESET_OUT.Q); AMIGA_ADDR_ENABLE = (0); -SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); - -SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q); - AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN - # !BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & !AS_000.PIN & RW_000.PIN); + # !nEXP_SPACE & !BGACK_030.Q & !AS_000.PIN & RW_000.PIN); !AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q); AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q - # BGACK_030.Q & !SM_AMIGA_i_7_.Q); + # BGACK_030.Q & !SM_AMIGA_i_7_.Q + # CLK_000 & BGACK_030.Q & SM_AMIGA_0_.Q); -CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q); +CIIN = (A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); CIIN.OE = (CIIN_0); +SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); + +SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); + +AHIGH_30_ = (0); + +AHIGH_30_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + +AHIGH_29_ = (0); + +AHIGH_29_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + +AHIGH_28_ = (0); + +AHIGH_28_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + +AHIGH_27_ = (0); + +AHIGH_27_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + +AHIGH_26_ = (0); + +AHIGH_26_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + +AHIGH_25_ = (0); + +AHIGH_25_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + +AHIGH_24_ = (0); + +AHIGH_24_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + !IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q @@ -1388,6 +1493,22 @@ CIIN.OE = (CIIN_0); IPL_030_2_.C = (CLK_OSZI); +RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); + +!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN + # RST & !CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q + # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q); + +RW_000.C = (CLK_OSZI); + +A_0_.OE = (!nEXP_SPACE & !BGACK_030.Q & inst_RESET_OUT.Q); + +A_0_.D = (!RST + # !BGACK_030.Q & UDS_000.PIN + # BGACK_030.Q & inst_BGACK_030_INT_D.Q & A_0_.Q); + +A_0_.C = (CLK_OSZI); + !IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q # RST & !IPL_D0_1_.Q & !IPL_030_1_.Q # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q @@ -1414,30 +1535,14 @@ IPL_030_1_.C = (CLK_OSZI); IPL_030_0_.C = (CLK_OSZI); -RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q); - -!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN - # RST & !SM_AMIGA_5_.Q & !inst_CLK_000_PE.Q & !RW_000.Q & SM_AMIGA_i_7_.Q - # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q); - -RW_000.C = (CLK_OSZI); - -A0.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q); - -A0.D = (!RST - # !BGACK_030.Q & UDS_000.PIN - # BGACK_030.Q & inst_BGACK_030_INT_D.Q & A0.Q); - -A0.C = (CLK_OSZI); - !BG_000.D = (!BG_030 & RST & !BG_000.Q - # !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & CLK_000_D_0_.Q); + # nEXP_SPACE & !BG_030 & RST & inst_AS_030_D0.Q & CLK_000_D_0_.Q); BG_000.C = (CLK_OSZI); BGACK_030.D = (!RST # BGACK_000 & BGACK_030.Q - # BGACK_000 & inst_CLK_000_PE.Q & AS_000.PIN); + # BGACK_000 & CLK_000_P_SYNC_10_.Q & AS_000.PIN); BGACK_030.C = (CLK_OSZI); @@ -1445,18 +1550,18 @@ CLK_EXP.D = (inst_CLK_OUT_PRE_D.Q); CLK_EXP.C = (CLK_OSZI); -DSACK1.OE = (inst_nEXP_SPACE_D0reg.Q); +DSACK1.OE = (nEXP_SPACE); -!DSACK1.D = (RST & CLK_000_N_SYNC_10_.Q & SM_AMIGA_1_.Q - # !CLK_030 & RST & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q - # RST & inst_CLK_OUT_PRE_D.Q & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q - # RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN); +!DSACK1.D = (RST & !CLK_000_D_11_.Q & CLK_000_D_12_.Q & SM_AMIGA_1_.Q + # RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN + # !CLK_030 & RST & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q + # RST & inst_CLK_OUT_PRE_D.Q & !CLK_000_D_10_.Q & CLK_000_D_11_.Q & SM_AMIGA_1_.Q); DSACK1.C = (CLK_OSZI); VMA.T = (!RST & !VMA.Q - # !VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_PE.Q - # RST & VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q); + # !VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & CLK_000_P_SYNC_10_.Q + # RST & VMA.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & cpu_est_0_.Q & cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_N_SYNC_12_.Q); VMA.C = (CLK_OSZI); @@ -1467,10 +1572,9 @@ RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q); RW.C = (CLK_OSZI); -!N_317_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & !CLK_000_D_1_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # !SM_AMIGA_5_.Q & CLK_000_D_0_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q); +N_226 = (!nEXP_SPACE & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q + # inst_AS_030_000_SYNC.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q + # !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !CLK_000_N_SYNC_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q); cpu_est_2_.D = (cpu_est_2_.Q & !cpu_est_0_.Q # cpu_est_2_.Q & !cpu_est_1_.Q @@ -1501,13 +1605,7 @@ cpu_est_1_.C = (CLK_OSZI); inst_AS_000_INT.C = (CLK_OSZI); -SM_AMIGA_5_.D = (RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & SM_AMIGA_6_.Q - # RST & SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & BERR.PIN - # RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN); - -SM_AMIGA_5_.C = (CLK_OSZI); - -!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (A1 & RST & !BGACK_030.Q +!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (RST & A_1_ & !BGACK_030.Q # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q); inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); @@ -1516,17 +1614,13 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); inst_AS_030_D0.C = (CLK_OSZI); -!inst_nEXP_SPACE_D0reg.D = (!nEXP_SPACE & RST); - -inst_nEXP_SPACE_D0reg.C = (CLK_OSZI); - !inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_D0.Q & !inst_AS_030_000_SYNC.Q & BERR.PIN - # !FC_1_ & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN - # RST & A_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN - # RST & A_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN - # RST & !A_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN - # RST & A_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN - # RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN); + # !FC_1_ & nEXP_SPACE & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # nEXP_SPACE & RST & A_DECODE_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # nEXP_SPACE & RST & A_DECODE_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # nEXP_SPACE & RST & !A_DECODE_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # nEXP_SPACE & RST & A_DECODE_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN + # nEXP_SPACE & RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN); inst_AS_030_000_SYNC.C = (CLK_OSZI); @@ -1556,14 +1650,14 @@ inst_DS_000_DMA.D = (!RST inst_DS_000_DMA.C = (CLK_OSZI); -CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & inst_CLK_000_PE.Q & !AS_000.PIN - # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN); +CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CLK_000_P_SYNC_10_.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CLK_000_P_SYNC_10_.Q & !AS_000.PIN); CYCLE_DMA_0_.C = (CLK_OSZI); CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN - # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN - # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_000_PE.Q & !AS_000.PIN); + # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !CLK_000_P_SYNC_10_.Q & !AS_000.PIN + # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & CLK_000_P_SYNC_10_.Q & !AS_000.PIN); CYCLE_DMA_1_.C = (CLK_OSZI); @@ -1584,13 +1678,13 @@ SIZE_DMA_1_.C = (CLK_OSZI); inst_VPA_D.C = (CLK_OSZI); !inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q - # RST & SM_AMIGA_6_.Q & !A0.PIN); + # RST & SM_AMIGA_6_.Q & !A_0_.PIN); inst_UDS_000_INT.C = (CLK_OSZI); inst_LDS_000_INT.D = (!RST # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q - # SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN); + # SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A_0_.PIN); inst_LDS_000_INT.C = (CLK_OSZI); @@ -1598,12 +1692,20 @@ inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_50.Q); inst_CLK_OUT_PRE_D.C = (CLK_OSZI); +CLK_000_D_10_.D = (CLK_000_D_9_.Q); + +CLK_000_D_10_.C = (CLK_OSZI); + +CLK_000_D_11_.D = (CLK_000_D_10_.Q); + +CLK_000_D_11_.C = (CLK_OSZI); + !inst_DTACK_D0.D = (!DTACK & RST); inst_DTACK_D0.C = (CLK_OSZI); inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q - # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); + # RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); inst_RESET_OUT.C = (CLK_OSZI); @@ -1619,21 +1721,15 @@ CLK_000_D_0_.D = (CLK_000); CLK_000_D_0_.C = (CLK_OSZI); -inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q); +CLK_000_P_SYNC_10_.D = (CLK_000_P_SYNC_9_.Q); -inst_CLK_000_PE.C = (CLK_OSZI); +CLK_000_P_SYNC_10_.C = (CLK_OSZI); -CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q); +SM_AMIGA_5_.D = (RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & SM_AMIGA_6_.Q + # RST & SM_AMIGA_5_.Q & !CLK_000_N_SYNC_12_.Q & BERR.PIN + # RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN); -CLK_000_P_SYNC_9_.C = (CLK_OSZI); - -inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q); - -inst_CLK_000_NE.C = (CLK_OSZI); - -CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q); - -CLK_000_N_SYNC_11_.C = (CLK_OSZI); +SM_AMIGA_5_.C = (CLK_OSZI); !IPL_D0_0_.D = (RST & !IPL_0_); @@ -1647,49 +1743,84 @@ IPL_D0_1_.C = (CLK_OSZI); IPL_D0_2_.C = (CLK_OSZI); -inst_CLK_000_NE_D0.D = (inst_CLK_000_NE.Q); +CLK_000_D_2_.D = (CLK_000_D_1_.Q); -inst_CLK_000_NE_D0.C = (CLK_OSZI); +CLK_000_D_2_.C = (CLK_OSZI); -SM_AMIGA_0_.D = (RST & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & SM_AMIGA_1_.Q - # RST & !inst_CLK_000_PE.Q & SM_AMIGA_0_.Q & BERR.PIN); +CLK_000_D_3_.D = (CLK_000_D_2_.Q); + +CLK_000_D_3_.C = (CLK_OSZI); + +CLK_000_D_4_.D = (CLK_000_D_3_.Q); + +CLK_000_D_4_.C = (CLK_OSZI); + +CLK_000_D_5_.D = (CLK_000_D_4_.Q); + +CLK_000_D_5_.C = (CLK_OSZI); + +CLK_000_D_6_.D = (CLK_000_D_5_.Q); + +CLK_000_D_6_.C = (CLK_OSZI); + +CLK_000_D_7_.D = (CLK_000_D_6_.Q); + +CLK_000_D_7_.C = (CLK_OSZI); + +CLK_000_D_8_.D = (CLK_000_D_7_.Q); + +CLK_000_D_8_.C = (CLK_OSZI); + +CLK_000_D_9_.D = (CLK_000_D_8_.Q); + +CLK_000_D_9_.C = (CLK_OSZI); + +CLK_000_D_12_.D = (CLK_000_D_11_.Q); + +CLK_000_D_12_.C = (CLK_OSZI); + +SM_AMIGA_0_.D = (RST & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & SM_AMIGA_1_.Q + # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_0_.Q & BERR.PIN); SM_AMIGA_0_.C = (CLK_OSZI); -!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (!A1 & RST & !BGACK_030.Q - # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); +CLK_000_N_SYNC_0_.D = (CLK_000_D_1_.Q & !CLK_000_D_0_.Q); -inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); +CLK_000_N_SYNC_0_.C = (CLK_OSZI); -SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & inst_CLK_000_NE.Q - # RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q - # RST & !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & BERR.PIN); +SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q + # RST & SM_AMIGA_5_.Q & CLK_000_N_SYNC_12_.Q + # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_4_.Q & BERR.PIN); SM_AMIGA_4_.C = (CLK_OSZI); inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN - # RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q + # RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q - # RST & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN + # RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN # RST & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN); inst_DS_000_ENABLE.C = (CLK_OSZI); -RST_DLY_0_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_0_.Q - # RST & inst_CLK_000_NE.Q & !RST_DLY_0_.Q +CLK_000_N_SYNC_12_.D = (CLK_000_N_SYNC_11_.Q); + +CLK_000_N_SYNC_12_.C = (CLK_OSZI); + +RST_DLY_0_.D = (RST & !CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q + # RST & CLK_000_N_SYNC_12_.Q & !RST_DLY_0_.Q # RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q); RST_DLY_0_.C = (CLK_OSZI); -RST_DLY_1_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_1_.Q +RST_DLY_1_.D = (RST & !CLK_000_N_SYNC_12_.Q & RST_DLY_1_.Q # RST & !RST_DLY_0_.Q & RST_DLY_1_.Q # RST & RST_DLY_1_.Q & RST_DLY_2_.Q - # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q); + # RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q); RST_DLY_1_.C = (CLK_OSZI); RST_DLY_2_.D = (RST & RST_DLY_2_.Q - # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q); + # RST & CLK_000_N_SYNC_12_.Q & RST_DLY_0_.Q & RST_DLY_1_.Q); RST_DLY_2_.C = (CLK_OSZI); @@ -1729,9 +1860,9 @@ CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q); CLK_000_P_SYNC_8_.C = (CLK_OSZI); -CLK_000_N_SYNC_0_.D = (CLK_000_D_1_.Q & !CLK_000_D_0_.Q); +CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q); -CLK_000_N_SYNC_0_.C = (CLK_OSZI); +CLK_000_P_SYNC_9_.C = (CLK_OSZI); CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q); @@ -1773,9 +1904,22 @@ CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q); CLK_000_N_SYNC_10_.C = (CLK_OSZI); +CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q); + +CLK_000_N_SYNC_11_.C = (CLK_OSZI); + +inst_CLK_000_NE_D0.D = (CLK_000_N_SYNC_12_.Q); + +inst_CLK_000_NE_D0.C = (CLK_OSZI); + +!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (RST & !A_1_ & !BGACK_030.Q + # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); + +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); + SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q - # RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN - # RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & CLK_000_D_1_.Q & !CLK_000_D_0_.Q & !SM_AMIGA_i_7_.Q); + # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_6_.Q & BERR.PIN + # nEXP_SPACE & RST & !inst_AS_030_000_SYNC.Q & CLK_000_N_SYNC_0_.Q & !SM_AMIGA_i_7_.Q); SM_AMIGA_6_.C = (CLK_OSZI); @@ -1790,46 +1934,46 @@ inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst inst_CLK_030_H.C = (CLK_OSZI); -SM_AMIGA_1_.D = (RST & inst_CLK_000_PE.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q - # RST & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & BERR.PIN +SM_AMIGA_1_.D = (RST & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q + # RST & !CLK_000_N_SYNC_12_.Q & SM_AMIGA_1_.Q & BERR.PIN # RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q & BERR.PIN); SM_AMIGA_1_.C = (CLK_OSZI); SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q # SM_AMIGA_3_.Q & !BERR.PIN - # RST & inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q - # inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q - # !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q); + # RST & CLK_000_P_SYNC_10_.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q + # inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q + # !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q); SM_AMIGA_3_.C = (CLK_OSZI); SM_AMIGA_2_.D = (RST & SM_AMIGA_3_.Q & SM_AMIGA_2_.Q - # RST & !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN + # RST & !CLK_000_P_SYNC_10_.Q & SM_AMIGA_2_.Q & BERR.PIN # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q # RST & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q); SM_AMIGA_2_.C = (CLK_OSZI); -SM_AMIGA_i_7_.D = (RST & N_317_i & !inst_CLK_000_PE.Q & BERR.PIN - # RST & N_317_i & !SM_AMIGA_0_.Q & BERR.PIN - # RST & N_317_i & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_3_.Q - # RST & N_317_i & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q - # RST & N_317_i & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q - # RST & N_317_i & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # RST & N_317_i & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q - # RST & N_317_i & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q - # RST & N_317_i & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q - # RST & N_317_i & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q - # RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q - # RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q - # RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q - # RST & !VMA.Q & N_317_i & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q); +SM_AMIGA_i_7_.D = (RST & !N_226 & !CLK_000_P_SYNC_10_.Q & BERR.PIN + # RST & !N_226 & !SM_AMIGA_0_.Q & BERR.PIN + # RST & !N_226 & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & !SM_AMIGA_3_.Q + # RST & !N_226 & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q + # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q + # RST & !N_226 & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q + # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_1_.Q + # RST & !N_226 & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q + # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q + # RST & !N_226 & inst_VPA_D.Q & !inst_DTACK_D0.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q + # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_0_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q + # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & CLK_000_P_SYNC_10_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_1_.Q + # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & CLK_000_N_SYNC_12_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q + # RST & !N_226 & !VMA.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q); SM_AMIGA_i_7_.C = (CLK_OSZI); -CIIN_0 = (inst_nEXP_SPACE_D0reg.Q - # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q); +CIIN_0 = (nEXP_SPACE + # A_DECODE_23_ & A_DECODE_22_ & A_DECODE_21_ & A_DECODE_20_ & !inst_AS_030_D0.Q & !AHIGH_24_.PIN & !AHIGH_25_.PIN & !AHIGH_26_.PIN & !AHIGH_27_.PIN & !AHIGH_28_.PIN & !AHIGH_29_.PIN & !AHIGH_30_.PIN & !AHIGH_31_.PIN); Reverse-Polarity Equations: diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index 3123d42..88fdb9d 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -39,9 +39,7 @@ SIGNAL NAME min max min max min max min max AMIGA_BUS_DATA_DIR .. .. .. .. 1 2 .. .. BGACK_030 1 2 0 1 .. .. 1 1 RN_BGACK_030 1 2 0 1 .. .. 1 1 - SM_AMIGA_5_ 1 1 .. .. .. .. 1 2 inst_AS_030_D0 1 2 1 1 .. .. 1 1 -inst_nEXP_SPACE_D0reg 1 1 1 1 .. .. 1 2 inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2 inst_DS_000_DMA 1 2 1 1 .. .. .. .. CYCLE_DMA_0_ 1 2 .. .. .. .. 1 1 @@ -50,9 +48,9 @@ inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2 SIZE_DMA_1_ 1 1 1 1 .. .. 2 2 inst_UDS_000_INT 1 1 1 1 .. .. 2 2 inst_LDS_000_INT 1 1 1 1 .. .. 2 2 - CLK_000_D_1_ .. .. .. .. .. .. 1 2 - CLK_000_D_0_ 1 1 .. .. .. .. 1 2 - SM_AMIGA_0_ 1 1 .. .. .. .. 1 2 + SM_AMIGA_5_ 1 1 .. .. .. .. 1 2 + SM_AMIGA_0_ 1 1 1 1 .. .. 1 2 +CLK_000_N_SYNC_0_ .. .. .. .. .. .. 1 2 SM_AMIGA_4_ 1 1 .. .. .. .. 1 2 inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2 SM_AMIGA_6_ 1 1 .. .. .. .. 1 2 @@ -60,19 +58,21 @@ inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2 SM_AMIGA_1_ 1 1 .. .. .. .. 1 2 SM_AMIGA_3_ 1 1 .. .. .. .. 1 2 SM_AMIGA_2_ 1 1 .. .. .. .. 1 2 + SM_AMIGA_i_7_ 1 2 1 1 .. .. 1 1 AS_030 .. .. .. .. 1 1 .. .. AS_000 .. .. .. .. 1 1 .. .. +AMIGA_BUS_ENABLE_HIGH .. .. .. .. 1 1 .. .. CIIN .. .. .. .. 1 1 .. .. IPL_030_2_ 1 1 0 0 .. .. 1 1 RN_IPL_030_2_ 1 1 0 0 .. .. 1 1 + RW_000 1 1 0 0 .. .. 1 1 + RN_RW_000 1 1 0 0 .. .. 1 1 + A_0_ 1 1 0 0 .. .. 1 1 + RN_A_0_ 1 1 0 0 .. .. 1 1 IPL_030_1_ 1 1 0 0 .. .. 1 1 RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 IPL_030_0_ 1 1 0 0 .. .. 1 1 RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 - RW_000 1 1 0 0 .. .. 1 1 - RN_RW_000 1 1 0 0 .. .. 1 1 - A0 1 1 0 0 .. .. 1 1 - RN_A0 1 1 0 0 .. .. 1 1 BG_000 1 1 0 0 .. .. 1 1 RN_BG_000 1 1 0 0 .. .. 1 1 DSACK1 1 1 0 0 .. .. 1 1 @@ -81,6 +81,7 @@ inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2 RN_VMA 1 1 0 0 .. .. 1 1 RW 1 1 0 0 .. .. 1 1 RN_RW 1 1 0 0 .. .. 1 1 + N_226 .. .. .. .. 1 1 .. .. cpu_est_2_ .. .. 1 1 .. .. 1 1 cpu_est_3_ .. .. 1 1 .. .. 1 1 cpu_est_0_ .. .. .. .. .. .. 1 1 @@ -89,18 +90,27 @@ inst_AMIGA_BUS_ENABLE_DMA_LOW 1 1 1 1 .. .. .. .. inst_BGACK_030_INT_D 1 1 .. .. .. .. 1 1 inst_VPA_D 1 1 .. .. .. .. 1 1 inst_CLK_OUT_PRE_D .. .. .. .. .. .. 1 1 + CLK_000_D_10_ .. .. .. .. .. .. 1 1 + CLK_000_D_11_ .. .. .. .. .. .. 1 1 inst_DTACK_D0 1 1 .. .. .. .. 1 1 inst_RESET_OUT 1 1 .. .. .. .. .. .. inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1 - inst_CLK_000_PE .. .. .. .. .. .. 1 1 -CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1 - inst_CLK_000_NE .. .. .. .. .. .. 1 1 -CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1 + CLK_000_D_1_ .. .. .. .. .. .. 1 1 + CLK_000_D_0_ 1 1 .. .. .. .. 1 1 +CLK_000_P_SYNC_10_ .. .. .. .. .. .. 1 1 IPL_D0_0_ 1 1 .. .. .. .. 1 1 IPL_D0_1_ 1 1 .. .. .. .. 1 1 IPL_D0_2_ 1 1 .. .. .. .. 1 1 -inst_CLK_000_NE_D0 .. .. .. .. .. .. 1 1 -inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. .. + CLK_000_D_2_ .. .. .. .. .. .. 1 1 + CLK_000_D_3_ .. .. .. .. .. .. 1 1 + CLK_000_D_4_ .. .. .. .. .. .. 1 1 + CLK_000_D_5_ .. .. .. .. .. .. 1 1 + CLK_000_D_6_ .. .. .. .. .. .. 1 1 + CLK_000_D_7_ .. .. .. .. .. .. 1 1 + CLK_000_D_8_ .. .. .. .. .. .. 1 1 + CLK_000_D_9_ .. .. .. .. .. .. 1 1 + CLK_000_D_12_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_12_ .. .. .. .. .. .. 1 1 RST_DLY_0_ 1 1 .. .. .. .. 1 1 RST_DLY_1_ 1 1 .. .. .. .. 1 1 RST_DLY_2_ 1 1 .. .. .. .. 1 1 @@ -113,7 +123,7 @@ CLK_000_P_SYNC_5_ .. .. .. .. .. .. 1 1 CLK_000_P_SYNC_6_ .. .. .. .. .. .. 1 1 CLK_000_P_SYNC_7_ .. .. .. .. .. .. 1 1 CLK_000_P_SYNC_8_ .. .. .. .. .. .. 1 1 -CLK_000_N_SYNC_0_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_1_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_2_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_3_ .. .. .. .. .. .. 1 1 @@ -124,5 +134,7 @@ CLK_000_N_SYNC_7_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_8_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_9_ .. .. .. .. .. .. 1 1 CLK_000_N_SYNC_10_ .. .. .. .. .. .. 1 1 - SM_AMIGA_i_7_ 1 1 1 1 .. .. 1 1 +CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1 +inst_CLK_000_NE_D0 .. .. .. .. .. .. 1 1 +inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 1 1 1 .. .. .. .. CIIN_0 .. .. .. .. 1 1 .. .. \ No newline at end of file diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index 006ff1c..243740c 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,566 +1,588 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Wed Aug 17 17:45:46 2016 +#$ DATE Fri Aug 19 00:20:41 2016 #$ MODULE 68030_tk -#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW -#$ NODES 68 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ +#$ PINS 61 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ AHIGH_31_ A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 IPL_1_ IPL_0_ BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ IPL_030_2_ RW_000 A_0_ IPL_030_1_ IPL_030_0_ BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW +#$ NODES 78 N_226 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ CLK_000_P_SYNC_10_ SM_AMIGA_5_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ SM_AMIGA_0_ CLK_000_N_SYNC_0_ SM_AMIGA_4_ inst_DS_000_ENABLE CLK_000_N_SYNC_12_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_P_SYNC_9_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_N_SYNC_11_ inst_CLK_000_NE_D0 inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ .type fr -.i 120 -.o 190 -.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN -.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C RST_DLY_0_.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C A0.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_000_PE.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D -.p 554 ------------------------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --1---------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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--------------1----------------------------0----------------------------0----------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1-------------------1------------------0-------------------0---------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------1---------------------1----------------0-------------------0---------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------1----------------------0---------------0-------------------0---------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------1-----------------------1--------------0-------------------0---------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------1------------------------1-------------0-------------------0---------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------1--------------------------------------1---1---------------0---------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------1------------------------------------------------------0---0---------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------1----------------------------------------------------------1------------------------------1--------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ---0----------1------------------1---------01-1-----------------------------------------------------------0------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1-----------1------1---------01-1-----------------------------------------------------------0------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1------------1-----1---------01-1-----------------------------------------------------------0------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1-------------0----1---------01-1-----------------------------------------------------------0------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1--------------1---1---------01-1-----------------------------------------------------------0------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1-----------------01---------01-1-----------------------------------------------------------0------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1-----------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------0-----------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1----------------------0------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------------------------------1------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------------------------------------------------------0----------1---------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -----------------------------------------------------------------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------0--------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------------------------------------------------------------------1---------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ----------------------------------------------------------------0--------------------------------------1---------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------1------------------0--------------------------------------------------1--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ------------------------------------1----------------0--------------------------------------------------1--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------0---------------0--------------------------------------------------1--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------------------------------1--------------0--------------------------------------------------1--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ---------------------------------------1-------------0--------------------------------------------------1--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -----------------------------------------------------1---1----------------------------------------------1--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ---------------------------------------------------------------------0----------------------------------1--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------------------------------------------------------------------------------------------------0--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ --------------------------------------------------------------0------------------------------------------1-------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------------------------------------------------------------------1------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ----------------------------------------------------------------------------------------------------------0------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1--------------------------1------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----------------------------------------1-1----------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1--------------------------------0---------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1-----------------------------------------------------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.i 130 +.o 226 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ N_226 BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q CLK_000_P_SYNC_10_.Q SM_AMIGA_5_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_8_.Q CLK_000_D_9_.Q CLK_000_D_12_.Q SM_AMIGA_0_.Q DSACK1.Q CLK_000_N_SYNC_0_.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q CLK_000_N_SYNC_12_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_P_SYNC_9_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q CLK_000_N_SYNC_11_.Q RW_000.Q RW.Q inst_CLK_000_NE_D0.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q A_0_.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN +.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_2_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CLK_000_N_SYNC_12_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_10_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C CLK_000_D_5_.C CLK_000_D_6_.C CLK_000_D_7_.C CLK_000_D_8_.C CLK_000_D_9_.C CLK_000_D_10_.C CLK_000_D_11_.C CLK_000_D_12_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C VMA.C inst_UDS_000_INT.C A_0_.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_CLK_000_NE_D0.C inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_OUT_PRE_50.C SIZE_1_ AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ N_226 AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D CLK_000_D_10_.D CLK_000_D_11_.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D CLK_000_D_1_.D CLK_000_D_0_.D CLK_000_P_SYNC_10_.D SM_AMIGA_5_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_3_.D CLK_000_D_4_.D CLK_000_D_5_.D CLK_000_D_6_.D CLK_000_D_7_.D CLK_000_D_8_.D CLK_000_D_9_.D CLK_000_D_12_.D SM_AMIGA_0_.D DSACK1.D CLK_000_N_SYNC_0_.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D CLK_000_N_SYNC_12_.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_9_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_11_.D RW_000.D RW.D inst_CLK_000_NE_D0.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D A_0_.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D +.p 576 +---------------------------------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1-------------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0------------------------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1------------------------------------------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-----0---------------------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1-------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------------------------------------------------------------------------------------------------------------ ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------1----------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1---------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0--------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1111111~~11111~~~1~~~~~~111~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~11~~~~~~1~111 +----------------1----------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1---------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------0--------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------1-------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------1------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------1------------------------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------0----------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------1-------------------------------------------------------------------------------------------------------- ~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1-------------------1-------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0---------------------0-------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1-0-------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-----------------------0-0-------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0-------------0------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------1-0---------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------010---------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------10-1--------------------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------01--------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------1--0--------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------01-0--------------------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------1-------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1------------------------------------------------------------------------------------------------- ~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------1------1------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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+-----------------------------1------------0--------------------------------------------------------------1----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +------------------------------1-----------0--------------------------------------------------------------1----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +------------------------------------------1-----1--------------------------------------------------------1----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------------------------------------------------------------------0-----1----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------------------------------------------------------------------------0----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-----------------------------------------------------0----------------------------------------------------1---------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +-----------------------------------------------------------------------------------------------------------1--------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +-----------------------------------------------------------------------------------------------------------0--------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1-----------------------------------------1--------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +---------------------------------1--------------------1--------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------1----------------0---------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------1-------------------------------------------------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index 8a26ce8..6e0ed44 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,566 +1,588 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Wed Aug 17 17:45:46 2016 +#$ DATE Fri Aug 19 00:20:41 2016 #$ MODULE 68030_tk -#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW -#$ NODES 68 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ +#$ PINS 61 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ AHIGH_31_ A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ IPL_2_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 IPL_1_ IPL_0_ BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ IPL_030_2_ RW_000 A_0_ IPL_030_1_ IPL_030_0_ BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW +#$ NODES 78 N_226 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ CLK_000_P_SYNC_10_ SM_AMIGA_5_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ SM_AMIGA_0_ CLK_000_N_SYNC_0_ SM_AMIGA_4_ inst_DS_000_ENABLE CLK_000_N_SYNC_12_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_P_SYNC_9_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_N_SYNC_11_ inst_CLK_000_NE_D0 inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ .type fr -.i 120 -.o 190 -.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN -.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C cpu_est_3_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C RST_DLY_0_.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C A0.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_000_PE.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ N_317_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D CLK_000_D_1_.D CLK_000_D_0_.D inst_CLK_000_PE.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D -.p 554 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--------1-----1------------------0-------------0-10---------------------------------------------------1---------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1------------------0--------------001---------------------------------------------------0---------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1------------------0--------------010---------------------------------------------------0---------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1------------------0---------------01-------------------------------------------------------------010------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1------------------0---------------10-------------------------------------------------------------010------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1------------------0---------------------------------------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------------------------------------------------------11----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ --------1-----1------------------0---------------01-------------------------------------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1------------------0-------------0-01-------------------------------------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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--------------1--------------------------------------------------------------------------------------1---------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1--------------------------------------------------------------------------------------1----------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1--------------------------------------------------------------------------------------1----------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1-------------------------0--0---------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1----------------------------0-0-------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1----------------------------0----------------------------0----------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1-------------------1------------------0-------------------0---------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------1---------------------1----------------0-------------------0---------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------1----------------------0---------------0-------------------0---------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------1-----------------------1--------------0-------------------0---------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------1------------------------1-------------0-------------------0---------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------1--------------------------------------1---1---------------0---------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------1------------------------------------------------------0---0---------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ --------------1----------------------------------------------------------1------------------------------1--------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ---0----------1------------------1---------01-1-----------------------------------------------------------0------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1-----------1------1---------01-1-----------------------------------------------------------0------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1------------1-----1---------01-1-----------------------------------------------------------0------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1-------------0----1---------01-1-----------------------------------------------------------0------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1--------------1---1---------01-1-----------------------------------------------------------0------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1-----------------01---------01-1-----------------------------------------------------------0------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1-----------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------0-----------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1----------------------0------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------------------------------1------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------------------------------------------------------0----------1---------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -----------------------------------------------------------------------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------0--------------------------------------1-----------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------------------------------------------------------------------1---------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ----------------------------------------------------------------0--------------------------------------1---------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------1------------------0--------------------------------------------------1--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ------------------------------------1----------------0--------------------------------------------------1--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------0---------------0--------------------------------------------------1--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------------------------------1--------------0--------------------------------------------------1--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ---------------------------------------1-------------0--------------------------------------------------1--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -----------------------------------------------------1---1----------------------------------------------1--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ---------------------------------------------------------------------0----------------------------------1--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------------------------------------------------------------------------------------------------0--------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ --------------------------------------------------------------0------------------------------------------1-------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ ----------------------------------------------------------------------------------------------------------1------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ ----------------------------------------------------------------------------------------------------------0------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------1--------------------------1------------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ -----------------------------------------1-1----------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1--------------------------------0---------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------1-----------------------------------------------------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.i 130 +.o 226 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ N_226 BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q CLK_000_P_SYNC_10_.Q SM_AMIGA_5_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_8_.Q CLK_000_D_9_.Q CLK_000_D_12_.Q SM_AMIGA_0_.Q DSACK1.Q CLK_000_N_SYNC_0_.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q CLK_000_N_SYNC_12_.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_P_SYNC_9_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q CLK_000_N_SYNC_11_.Q RW_000.Q RW.Q inst_CLK_000_NE_D0.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q A_0_.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN +.ob DS_030 FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_2_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CLK_000_N_SYNC_12_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_10_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.C CLK_000_D_0_.C CLK_000_D_1_.C CLK_000_D_2_.C CLK_000_D_3_.C CLK_000_D_4_.C CLK_000_D_5_.C CLK_000_D_6_.C CLK_000_D_7_.C CLK_000_D_8_.C CLK_000_D_9_.C CLK_000_D_10_.C CLK_000_D_11_.C CLK_000_D_12_.C CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C inst_CLK_030_H.C inst_RESET_OUT.C inst_DS_000_ENABLE.C VMA.C inst_UDS_000_INT.C A_0_.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_VPA_D.C inst_DTACK_D0.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_CLK_000_NE_D0.C inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.C CLK_EXP.C inst_CLK_OUT_PRE_50.C SIZE_1_ AHIGH_31_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ N_226 AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D VMA.T cpu_est_2_.D cpu_est_3_.D cpu_est_0_.D cpu_est_1_.D inst_AS_000_INT.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D CLK_000_D_10_.D CLK_000_D_11_.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D CLK_000_D_1_.D CLK_000_D_0_.D CLK_000_P_SYNC_10_.D SM_AMIGA_5_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D CLK_000_D_2_.D CLK_000_D_3_.D CLK_000_D_4_.D CLK_000_D_5_.D CLK_000_D_6_.D CLK_000_D_7_.D CLK_000_D_8_.D CLK_000_D_9_.D CLK_000_D_12_.D SM_AMIGA_0_.D DSACK1.D CLK_000_N_SYNC_0_.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D CLK_000_N_SYNC_12_.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_9_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_11_.D RW_000.D RW.D inst_CLK_000_NE_D0.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D A_0_.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D +.p 576 +---------------------------------------------------------------------------------------------------------------------------------- ~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1-------------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0------------------------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1------------------------------------------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1----------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-----0---------------------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1-------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1------------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1------------------------------------------------------------------------------------------------------------------------ ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------1----------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1---------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0--------------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1111111~~11111~~~1~~~~~~111~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~11~~~~~~1~111 +----------------1----------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------1---------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------0--------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------1-------------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------1------------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------1------------------------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------0----------------------------------------------------------------------------------------------------------- ~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------1-------------------------------------------------------------------------------------------------------- ~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1-------------------1-------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0---------------------0-------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1-0-------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-----------------------0-0-------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------0-------------0------------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------1-0---------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------010---------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------10-1--------------------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------01--------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------1--0--------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------01-0--------------------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------1-------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------1------------------------------------------------------------------------------------------------- ~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------1------1------------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1------------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0------------------------------1----------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--1-------------0010--1-----------1----------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------0--------1----------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------1---------0---------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~ +----------------------------------10---------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1--------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0-----------------------------1--------------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1-------------------------------------------------------------------------------------------- 1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------11------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------00------------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------1---------1----1----------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------1---------1-----1---------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------01---------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------10---------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------1-------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------1------------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------1------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +----------------------------------------------1----------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------1---------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1--------------------------1-----------0-1---------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1------------11---------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1------------------------------------1-------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------1-----------------------1-------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------0-----------------------1-------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0---------------------0-----------------------1-------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~111111111~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0-------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------0------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------1------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------1----------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------01----------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------10----------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------00000----------------------1---------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------1----------------------0--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1--------------------0--------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1------------------11---------------------------------111------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111 +-1------------------10---------------------------------011------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11 +-1------------------01---------------------------------101------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1 +-1------------------00---------------------------------001------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +-0------------------11---------------------------------110------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~ +-0------------------10---------------------------------010------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +-0------------------01---------------------------------100------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +----------------------------------------------------------1----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------------1-------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------1------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------------------1----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1-------------0------------------0--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1-----------------1-----------------------------------------1-------------------------------------------------------------- ~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------10------------1-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +------1--------------------------------------0-1--------------------1------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------11--------------------1------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------0------------------0-1------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1-----------------------------------------1---------------1----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------------0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ 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+------------------------------1-----------0--------------------------------------------------------------1----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +------------------------------------------1-----1--------------------------------------------------------1----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------------------------------------------------------------------0-----1----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +---------------------------------------------------------------------------------------------------------0----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ +-----------------------------------------------------0----------------------------------------------------1---------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ +-----------------------------------------------------------------------------------------------------------1--------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ +-----------------------------------------------------------------------------------------------------------0--------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------1-----------------------------------------1--------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +---------------------------------1--------------------1--------------------------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------1----------------0---------------------------------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------1-------------------------------------------------------------------------00 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index 46beba7..a2dbaf1 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,314 +1,338 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Wed Aug 17 17:45:46 2016 +#$ DATE Fri Aug 19 00:20:41 2016 #$ MODULE BUS68030 -#$ PINS 61 SIZE_1_ A_31_ IPL_2_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 DS_030 - UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI - CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE - SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ - AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ - A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 - BGACK_030 CLK_EXP DSACK1 VMA RW -#$ NODES 69 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT - SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg - inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA - CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT - inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT - inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_ - inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ - inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ - inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ - CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ - CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ - CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ - CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ - CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ - inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0 +#$ PINS 61 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ + AHIGH_31_ A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ IPL_2_ FC_1_ + AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 IPL_1_ IPL_0_ + BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK + AVEC E VPA RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW + AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ + AHIGH_26_ AHIGH_25_ AHIGH_24_ IPL_030_2_ RW_000 A_0_ IPL_030_1_ IPL_030_0_ + BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW +#$ NODES 79 N_226 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT + inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC + inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ + SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT + inst_CLK_OUT_PRE_D CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 inst_RESET_OUT + inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ CLK_000_P_SYNC_10_ SM_AMIGA_5_ + IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ + CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ + SM_AMIGA_0_ CLK_000_N_SYNC_0_ SM_AMIGA_4_ inst_DS_000_ENABLE CLK_000_N_SYNC_12_ + RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ + CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ + CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_P_SYNC_9_ + CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ + CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ + CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_N_SYNC_11_ inst_CLK_000_NE_D0 + inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ + SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0 .type f -.i 121 -.o 191 -.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI - FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ - A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q - N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q - SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q - inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q - inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q - SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q - inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q - CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q - inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q - inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q - SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q - CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q - CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q - CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q - CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q - CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q - RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q - SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q - AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN - A0.PIN BERR.PIN RW.PIN CIIN_0 -.ob SIZE_1_ SIZE_1_.OE AS_030% AS_030.OE AS_000% AS_000.OE DS_030% DS_030.OE - UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C - FPU_CS% AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE SIZE_0_ SIZE_0_.OE +.i 131 +.o 227 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 + CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ + A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ + N_226 BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q + inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q + inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q + inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q + inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q + CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q + inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q CLK_000_P_SYNC_10_.Q + SM_AMIGA_5_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q + CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_8_.Q + CLK_000_D_9_.Q CLK_000_D_12_.Q SM_AMIGA_0_.Q DSACK1.Q CLK_000_N_SYNC_0_.Q + SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q CLK_000_N_SYNC_12_.Q RST_DLY_0_.Q + RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q + CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q + CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_P_SYNC_9_.Q + CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q + CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q + CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q CLK_000_N_SYNC_11_.Q RW_000.Q RW.Q + inst_CLK_000_NE_D0.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q A_0_.Q SM_AMIGA_6_.Q + inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q + BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN + UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN + AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN + AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0 +.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030% AS_030.OE AS_000% + AS_000.OE DS_030% DS_030.OE UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE + CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS% AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE - IPL_030_2_.D% IPL_030_2_.C IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C - RW_000.D% RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D% BG_000.C BGACK_030.D - BGACK_030.C CLK_EXP.D CLK_EXP.C DSACK1.D% DSACK1.C DSACK1.OE VMA.T VMA.C RW.D% - RW.C RW.OE N_317_i% cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C - cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C inst_AS_000_INT.D% - inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D% - inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% inst_AS_030_D0.C - inst_nEXP_SPACE_D0reg.D% inst_nEXP_SPACE_D0reg.C inst_AS_030_000_SYNC.D% + SIZE_0_ SIZE_0_.OE AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE AHIGH_28_ + AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_ + AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE IPL_030_2_.D% IPL_030_2_.C RW_000.D% + RW_000.C RW_000.OE A_0_.D A_0_.C A_0_.OE IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% + IPL_030_0_.C BG_000.D% BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C + DSACK1.D% DSACK1.C DSACK1.OE VMA.T VMA.C RW.D% RW.C RW.OE N_226 cpu_est_2_.D + cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D + cpu_est_1_.C inst_AS_000_INT.D% inst_AS_000_INT.C + inst_AMIGA_BUS_ENABLE_DMA_LOW.D% inst_AMIGA_BUS_ENABLE_DMA_LOW.C + inst_AS_030_D0.D% inst_AS_030_D0.C inst_AS_030_000_SYNC.D% inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D% inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D% SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D% inst_VPA_D.C inst_UDS_000_INT.D% inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C - inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D% inst_DTACK_D0.C + inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_000_D_10_.D CLK_000_D_10_.C + CLK_000_D_11_.D CLK_000_D_11_.C inst_DTACK_D0.D% inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C - CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_000_PE.D - inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D - inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C IPL_D0_0_.D% - IPL_D0_0_.C IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C - inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C - inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_4_.D - SM_AMIGA_4_.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C RST_DLY_0_.D + CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_P_SYNC_10_.D + CLK_000_P_SYNC_10_.C SM_AMIGA_5_.D SM_AMIGA_5_.C IPL_D0_0_.D% IPL_D0_0_.C + IPL_D0_1_.D% IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C + CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D + CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C + CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_12_.D + CLK_000_D_12_.C SM_AMIGA_0_.D SM_AMIGA_0_.C CLK_000_N_SYNC_0_.D + CLK_000_N_SYNC_0_.C SM_AMIGA_4_.D SM_AMIGA_4_.C inst_DS_000_ENABLE.D + inst_DS_000_ENABLE.C CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C - CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C + CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D - CLK_000_N_SYNC_10_.C SM_AMIGA_6_.D SM_AMIGA_6_.C inst_CLK_030_H.D + CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C + inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D% + inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_6_.D SM_AMIGA_6_.C inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_3_.T SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C CIIN_0 -.phase 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BGACK_000 CLK_030 CLK_000 CLK_OSZI - CLK_DIV_OUT FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE - SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ - AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ - A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 - BGACK_030 CLK_EXP DSACK1 VMA RW -#$ NODES 69 N_317_i cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT - SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg - inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA - CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT - inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT - inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ inst_CLK_000_PE CLK_000_P_SYNC_9_ - inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ - inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ - inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ - CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ - CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ - CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ - CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ - CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ - inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0 +#$ PINS 61 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ + AHIGH_31_ A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ IPL_2_ FC_1_ + AS_030 AS_000 DS_030 UDS_000 LDS_000 nEXP_SPACE BERR BG_030 IPL_1_ IPL_0_ + BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT FPU_CS FPU_SENSE DTACK + AVEC E VPA RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW + AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ + AHIGH_26_ AHIGH_25_ AHIGH_24_ IPL_030_2_ RW_000 A_0_ IPL_030_1_ IPL_030_0_ + BG_000 BGACK_030 CLK_EXP DSACK1 VMA RW +#$ NODES 79 N_226 cpu_est_2_ cpu_est_3_ cpu_est_0_ cpu_est_1_ inst_AS_000_INT + inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_AS_030_000_SYNC + inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ + SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT + inst_CLK_OUT_PRE_D CLK_000_D_10_ CLK_000_D_11_ inst_DTACK_D0 inst_RESET_OUT + inst_CLK_OUT_PRE_50 CLK_000_D_1_ CLK_000_D_0_ CLK_000_P_SYNC_10_ SM_AMIGA_5_ + IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_D_2_ CLK_000_D_3_ CLK_000_D_4_ + CLK_000_D_5_ CLK_000_D_6_ CLK_000_D_7_ CLK_000_D_8_ CLK_000_D_9_ CLK_000_D_12_ + SM_AMIGA_0_ CLK_000_N_SYNC_0_ SM_AMIGA_4_ inst_DS_000_ENABLE CLK_000_N_SYNC_12_ + RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ + CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ + CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_P_SYNC_9_ + CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ + CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ + CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ CLK_000_N_SYNC_11_ inst_CLK_000_NE_D0 + inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ + SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0 .type f -.i 121 -.o 191 -.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI - FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ - A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q - N_317_i cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q inst_AS_000_INT.Q - SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q - inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q - inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q - SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q - inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q - CLK_000_D_1_.Q CLK_000_D_0_.Q inst_CLK_000_PE.Q CLK_000_P_SYNC_9_.Q - inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q - inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q - SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q - CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q - CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q - CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q - CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q - CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q - RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q - SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q - AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN - A0.PIN BERR.PIN RW.PIN CIIN_0 -.ob SIZE_1_ SIZE_1_.OE AS_030- AS_030.OE AS_000- AS_000.OE DS_030- DS_030.OE - UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C - FPU_CS- AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE SIZE_0_ SIZE_0_.OE +.i 131 +.o 227 +.ilb A_DECODE_23_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 + CLK_OSZI FPU_SENSE DTACK VPA RST A_DECODE_22_ A_DECODE_21_ A_DECODE_20_ + A_DECODE_19_ A_DECODE_18_ A_DECODE_17_ A_DECODE_16_ IPL_1_ IPL_0_ FC_0_ A_1_ + N_226 BGACK_030.Q VMA.Q cpu_est_2_.Q cpu_est_3_.Q cpu_est_0_.Q cpu_est_1_.Q + inst_AS_000_INT.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q + inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q + inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q + inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q + CLK_000_D_10_.Q CLK_000_D_11_.Q inst_DTACK_D0.Q inst_RESET_OUT.Q + inst_CLK_OUT_PRE_50.Q CLK_000_D_1_.Q CLK_000_D_0_.Q CLK_000_P_SYNC_10_.Q + SM_AMIGA_5_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q CLK_000_D_2_.Q CLK_000_D_3_.Q + CLK_000_D_4_.Q CLK_000_D_5_.Q CLK_000_D_6_.Q CLK_000_D_7_.Q CLK_000_D_8_.Q + CLK_000_D_9_.Q CLK_000_D_12_.Q SM_AMIGA_0_.Q DSACK1.Q CLK_000_N_SYNC_0_.Q + SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q CLK_000_N_SYNC_12_.Q RST_DLY_0_.Q + RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q + CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q + CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_P_SYNC_9_.Q + CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q + CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q + CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q CLK_000_N_SYNC_11_.Q RW_000.Q RW.Q + inst_CLK_000_NE_D0.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q A_0_.Q SM_AMIGA_6_.Q + inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q + BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN + UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN + AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN + AHIGH_31_.PIN A_0_.PIN BERR.PIN RW.PIN CIIN_0 +.ob SIZE_1_ SIZE_1_.OE AHIGH_31_ AHIGH_31_.OE AS_030- AS_030.OE AS_000- + AS_000.OE DS_030- DS_030.OE UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE + CLK_DIV_OUT.D CLK_DIV_OUT.C FPU_CS- AVEC E RESET RESET.OE AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE - IPL_030_2_.D- IPL_030_2_.C IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C - RW_000.D- RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D- BG_000.C BGACK_030.D - BGACK_030.C CLK_EXP.D CLK_EXP.C DSACK1.D- DSACK1.C DSACK1.OE VMA.T VMA.C RW.D- - RW.C RW.OE N_317_i- cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C - cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C inst_AS_000_INT.D- - inst_AS_000_INT.C SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D- - inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- inst_AS_030_D0.C - inst_nEXP_SPACE_D0reg.D- inst_nEXP_SPACE_D0reg.C inst_AS_030_000_SYNC.D- + SIZE_0_ SIZE_0_.OE AHIGH_30_ AHIGH_30_.OE AHIGH_29_ AHIGH_29_.OE AHIGH_28_ + AHIGH_28_.OE AHIGH_27_ AHIGH_27_.OE AHIGH_26_ AHIGH_26_.OE AHIGH_25_ + AHIGH_25_.OE AHIGH_24_ AHIGH_24_.OE IPL_030_2_.D- IPL_030_2_.C RW_000.D- + RW_000.C RW_000.OE A_0_.D A_0_.C A_0_.OE IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- + IPL_030_0_.C BG_000.D- BG_000.C BGACK_030.D BGACK_030.C CLK_EXP.D CLK_EXP.C + DSACK1.D- DSACK1.C DSACK1.OE VMA.T VMA.C RW.D- RW.C RW.OE N_226 cpu_est_2_.D + cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D + cpu_est_1_.C inst_AS_000_INT.D- inst_AS_000_INT.C + inst_AMIGA_BUS_ENABLE_DMA_LOW.D- inst_AMIGA_BUS_ENABLE_DMA_LOW.C + inst_AS_030_D0.D- inst_AS_030_D0.C inst_AS_030_000_SYNC.D- inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D- SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D- inst_VPA_D.C inst_UDS_000_INT.D- inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C - inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D- inst_DTACK_D0.C + inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_000_D_10_.D CLK_000_D_10_.C + CLK_000_D_11_.D CLK_000_D_11_.C inst_DTACK_D0.D- inst_DTACK_D0.C inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C - CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C inst_CLK_000_PE.D - inst_CLK_000_PE.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D - inst_CLK_000_NE.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C IPL_D0_0_.D- - IPL_D0_0_.C IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C - inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C SM_AMIGA_0_.D SM_AMIGA_0_.C - inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_4_.D - SM_AMIGA_4_.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C RST_DLY_0_.D + CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_P_SYNC_10_.D + CLK_000_P_SYNC_10_.C SM_AMIGA_5_.D SM_AMIGA_5_.C IPL_D0_0_.D- IPL_D0_0_.C + IPL_D0_1_.D- IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C CLK_000_D_2_.D CLK_000_D_2_.C + CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D + CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C + CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_12_.D + CLK_000_D_12_.C SM_AMIGA_0_.D SM_AMIGA_0_.C CLK_000_N_SYNC_0_.D + CLK_000_N_SYNC_0_.C SM_AMIGA_4_.D SM_AMIGA_4_.C inst_DS_000_ENABLE.D + inst_DS_000_ENABLE.C CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C - CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C + CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D - CLK_000_N_SYNC_10_.C SM_AMIGA_6_.D SM_AMIGA_6_.C inst_CLK_030_H.D + CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C + inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- + inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_6_.D SM_AMIGA_6_.C inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_3_.T SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C CIIN_0 -.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 -.p 221 ---------------------------------------------------01--------------------------------------------------------------------- 10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ---------------------------------0----------0----------------------------------------------------------------------------- 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+------------1-----------0----------------------------0--------------------------------------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 +------------1-----------0------------------------------------------0------------------------------------------------------------1-- 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index c964397..d4186e5 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 8/17/16; -TIME = 17:45:51; +DATE = 8/19/16; +TIME = 00:20:46; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -136,25 +136,33 @@ layer = OFF; [LOCATION ASSIGNMENT] Layer = OFF -AS_000 = OUTPUT,42,4,-; -RW_000 = BIDIR,80,7,-; BERR = OUTPUT,41,4,-; +RW_000 = BIDIR,80,7,-; +AS_000 = OUTPUT,42,4,-; +A_0_ = BIDIR,69,6,-; RW = BIDIR,71,6,-; AS_030 = OUTPUT,82,7,-; UDS_000 = OUTPUT,32,3,-; LDS_000 = OUTPUT,31,3,-; -A0 = BIDIR,69,6,-; SIZE_1_ = OUTPUT,79,7,-; SIZE_0_ = OUTPUT,70,6,-; +AHIGH_24_ = OUTPUT,19,2,-; +AHIGH_25_ = OUTPUT,18,2,-; +AHIGH_26_ = OUTPUT,17,2,-; +AHIGH_27_ = OUTPUT,16,2,-; +AHIGH_28_ = OUTPUT,15,2,-; +AHIGH_29_ = OUTPUT,6,1,-; +AHIGH_30_ = OUTPUT,5,1,-; +AHIGH_31_ = OUTPUT,4,1,-; IPL_030_2_ = OUTPUT,9,1,-; IPL_030_0_ = OUTPUT,8,1,-; IPL_030_1_ = OUTPUT,7,1,-; DSACK1 = OUTPUT,81,7,-; BGACK_030 = OUTPUT,83,7,-; VMA = OUTPUT,35,3,-; +AMIGA_BUS_ENABLE_HIGH = OUTPUT,34,3,-; E = OUTPUT,66,6,-; AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-; -AMIGA_BUS_ENABLE_HIGH = OUTPUT,34,3,-; BG_000 = OUTPUT,29,3,-; DS_030 = OUTPUT,98,0,-; AVEC = OUTPUT,92,0,-; @@ -166,41 +174,37 @@ AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-; CLK_EXP = OUTPUT,10,1,-; RESET = OUTPUT,3,1,-; RN_BGACK_030 = NODE,-1,7,-; -inst_nEXP_SPACE_D0reg = NODE,*,0,-; inst_RESET_OUT = NODE,*,3,-; -inst_CLK_000_PE = NODE,*,6,-; -SM_AMIGA_i_7_ = NODE,*,5,-; inst_AS_030_D0 = NODE,*,7,-; -cpu_est_2_ = NODE,*,3,-; -SM_AMIGA_6_ = NODE,*,5,-; +CLK_000_P_SYNC_10_ = NODE,*,0,-; +SM_AMIGA_i_7_ = NODE,*,5,-; +SM_AMIGA_6_ = NODE,*,2,-; +cpu_est_2_ = NODE,*,5,-; SM_AMIGA_5_ = NODE,*,5,-; -cpu_est_1_ = NODE,*,3,-; +cpu_est_1_ = NODE,*,5,-; cpu_est_3_ = NODE,*,5,-; SM_AMIGA_0_ = NODE,*,5,-; -CYCLE_DMA_0_ = NODE,*,1,-; -CLK_000_D_0_ = NODE,*,1,-; -inst_CLK_OUT_PRE_D = NODE,*,0,-; +cpu_est_0_ = NODE,*,1,-; +CLK_000_N_SYNC_12_ = NODE,*,3,-; +CLK_000_N_SYNC_0_ = NODE,*,3,-; +inst_CLK_OUT_PRE_D = NODE,*,4,-; inst_BGACK_030_INT_D = NODE,*,7,-; inst_AS_000_DMA = NODE,*,0,-; inst_AS_030_000_SYNC = NODE,*,2,-; -inst_DS_000_ENABLE = NODE,*,2,-; +inst_DS_000_ENABLE = NODE,*,5,-; RN_VMA = NODE,-1,3,-; SM_AMIGA_1_ = NODE,*,5,-; -SM_AMIGA_4_ = NODE,*,5,-; inst_LDS_000_INT = NODE,*,0,-; SIZE_DMA_1_ = NODE,*,6,-; SIZE_DMA_0_ = NODE,*,6,-; -CYCLE_DMA_1_ = NODE,*,2,-; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,1,-; -inst_UDS_000_INT = NODE,*,0,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,2,-; +inst_UDS_000_INT = NODE,*,1,-; inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,1,-; -inst_AS_000_INT = NODE,*,2,-; -cpu_est_0_ = NODE,*,3,-; -inst_CLK_000_NE_D0 = NODE,*,3,-; -inst_CLK_000_NE = NODE,*,6,-; -CLK_000_D_1_ = NODE,*,4,-; -inst_CLK_OUT_PRE_50 = NODE,*,5,-; -inst_VPA_D = NODE,*,5,-; +inst_AS_000_INT = NODE,*,6,-; +inst_CLK_000_NE_D0 = NODE,*,4,-; +CLK_000_D_0_ = NODE,*,6,-; +CLK_000_D_1_ = NODE,*,2,-; +inst_VPA_D = NODE,*,0,-; RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; RN_IPL_030_2_ = NODE,-1,1,-; @@ -210,38 +214,52 @@ SM_AMIGA_3_ = NODE,*,5,-; RN_DSACK1 = NODE,-1,7,-; SM_AMIGA_2_ = NODE,*,5,-; RST_DLY_1_ = NODE,*,3,-; -N_317_i = NODE,*,5,-; -RN_A0 = NODE,-1,6,-; +RN_A_0_ = NODE,-1,6,-; RN_RW_000 = NODE,-1,7,-; RST_DLY_0_ = NODE,*,3,-; +SM_AMIGA_4_ = NODE,*,5,-; +CYCLE_DMA_1_ = NODE,*,0,-; +N_226 = NODE,*,5,-; RN_RW = NODE,-1,6,-; RN_BG_000 = NODE,-1,3,-; CIIN_0 = NODE,*,4,-; RST_DLY_2_ = NODE,*,3,-; -CLK_000_N_SYNC_10_ = NODE,*,7,-; -CLK_000_N_SYNC_9_ = NODE,*,0,-; -CLK_000_N_SYNC_8_ = NODE,*,0,-; -CLK_000_N_SYNC_7_ = NODE,*,5,-; -CLK_000_N_SYNC_6_ = NODE,*,6,-; -CLK_000_N_SYNC_5_ = NODE,*,3,-; -CLK_000_N_SYNC_4_ = NODE,*,1,-; -CLK_000_N_SYNC_3_ = NODE,*,1,-; -CLK_000_N_SYNC_2_ = NODE,*,1,-; -CLK_000_N_SYNC_1_ = NODE,*,0,-; -CLK_000_N_SYNC_0_ = NODE,*,4,-; -CLK_000_P_SYNC_8_ = NODE,*,6,-; -CLK_000_P_SYNC_7_ = NODE,*,1,-; -CLK_000_P_SYNC_6_ = NODE,*,0,-; +CYCLE_DMA_0_ = NODE,*,0,-; +CLK_000_N_SYNC_11_ = NODE,*,2,-; +CLK_000_N_SYNC_10_ = NODE,*,2,-; +CLK_000_N_SYNC_9_ = NODE,*,5,-; +CLK_000_N_SYNC_8_ = NODE,*,1,-; +CLK_000_N_SYNC_7_ = NODE,*,6,-; +CLK_000_N_SYNC_6_ = NODE,*,1,-; +CLK_000_N_SYNC_5_ = NODE,*,0,-; +CLK_000_N_SYNC_4_ = NODE,*,0,-; +CLK_000_N_SYNC_3_ = NODE,*,5,-; +CLK_000_N_SYNC_2_ = NODE,*,0,-; +CLK_000_N_SYNC_1_ = NODE,*,4,-; +CLK_000_P_SYNC_9_ = NODE,*,2,-; +CLK_000_P_SYNC_8_ = NODE,*,0,-; +CLK_000_P_SYNC_7_ = NODE,*,3,-; +CLK_000_P_SYNC_6_ = NODE,*,6,-; CLK_000_P_SYNC_5_ = NODE,*,6,-; -CLK_000_P_SYNC_4_ = NODE,*,6,-; -CLK_000_P_SYNC_3_ = NODE,*,4,-; -CLK_000_P_SYNC_2_ = NODE,*,6,-; -CLK_000_P_SYNC_1_ = NODE,*,1,-; -CLK_000_P_SYNC_0_ = NODE,*,4,-; +CLK_000_P_SYNC_4_ = NODE,*,0,-; +CLK_000_P_SYNC_3_ = NODE,*,2,-; +CLK_000_P_SYNC_2_ = NODE,*,5,-; +CLK_000_P_SYNC_1_ = NODE,*,0,-; +CLK_000_P_SYNC_0_ = NODE,*,3,-; +CLK_000_D_12_ = NODE,*,7,-; +CLK_000_D_9_ = NODE,*,3,-; +CLK_000_D_8_ = NODE,*,1,-; +CLK_000_D_7_ = NODE,*,6,-; +CLK_000_D_6_ = NODE,*,1,-; +CLK_000_D_5_ = NODE,*,4,-; +CLK_000_D_4_ = NODE,*,2,-; +CLK_000_D_3_ = NODE,*,6,-; +CLK_000_D_2_ = NODE,*,6,-; IPL_D0_2_ = NODE,*,1,-; -IPL_D0_1_ = NODE,*,3,-; -IPL_D0_0_ = NODE,*,6,-; -CLK_000_N_SYNC_11_ = NODE,*,7,-; -CLK_000_P_SYNC_9_ = NODE,*,6,-; -inst_DTACK_D0 = NODE,*,1,-; +IPL_D0_1_ = NODE,*,5,-; +IPL_D0_0_ = NODE,*,3,-; +inst_CLK_OUT_PRE_50 = NODE,*,4,-; +inst_DTACK_D0 = NODE,*,2,-; +CLK_000_D_11_ = NODE,*,7,-; +CLK_000_D_10_ = NODE,*,6,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index 9525a33..1ec2132 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -17,8 +17,8 @@ Parent = m4a5.lci; SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; -DATE = 8/17/16; -TIME = 17:45:51; +DATE = 8/19/16; +TIME = 00:20:46; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -136,24 +136,32 @@ layer = OFF; [LOCATION ASSIGNMENT] Layer = OFF; +A_DECODE_22_ = INPUT,84, H,-; +A_DECODE_21_ = INPUT,94, A,-; SIZE_1_ = BIDIR,79, H,-; -A_31_ = INPUT,4, B,-; +A_DECODE_20_ = INPUT,93, A,-; +A_DECODE_19_ = INPUT,97, A,-; +AHIGH_31_ = BIDIR,4, B,-; +A_DECODE_18_ = INPUT,95, A,-; +A_DECODE_17_ = INPUT,59, F,-; +A_DECODE_23_ = INPUT,85, H,-; +A_DECODE_16_ = INPUT,96, A,-; IPL_2_ = INPUT,68, G,-; -IPL_1_ = INPUT,56, F,-; FC_1_ = INPUT,58, F,-; -IPL_0_ = INPUT,67, G,-; AS_030 = BIDIR,82, H,-; -FC_0_ = INPUT,57, F,-; AS_000 = BIDIR,42, E,-; DS_030 = OUTPUT,98, A,-; UDS_000 = BIDIR,32, D,-; LDS_000 = BIDIR,31, D,-; -A1 = INPUT,60, F,-; nEXP_SPACE = INPUT,14,-,-; BERR = BIDIR,41, E,-; BG_030 = INPUT,21, C,-; +IPL_1_ = INPUT,56, F,-; +IPL_0_ = INPUT,67, G,-; BGACK_000 = INPUT,28, D,-; +FC_0_ = INPUT,57, F,-; CLK_030 = INPUT,64,-,-; +A_1_ = INPUT,60, F,-; CLK_000 = INPUT,11,-,-; CLK_OSZI = INPUT,61,-,-; CLK_DIV_OUT = OUTPUT,65, G,-; @@ -166,103 +174,105 @@ VPA = INPUT,36,-,-; RST = INPUT,86,-,-; RESET = OUTPUT,3, B,-; AMIGA_ADDR_ENABLE = OUTPUT,33, D,-; -SIZE_0_ = BIDIR,70, G,-; AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; -A_30_ = INPUT,5, B,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; -A_29_ = INPUT,6, B,-; AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-; -A_28_ = INPUT,15, C,-; CIIN = OUTPUT,47, E,-; -A_27_ = INPUT,16, C,-; -A_26_ = INPUT,17, C,-; -A_25_ = INPUT,18, C,-; -A_24_ = INPUT,19, C,-; -A_23_ = INPUT,85, H,-; -A_22_ = INPUT,84, H,-; -A_21_ = INPUT,94, A,-; -A_20_ = INPUT,93, A,-; -A_19_ = INPUT,97, A,-; -A_18_ = INPUT,95, A,-; -A_17_ = INPUT,59, F,-; -A_16_ = INPUT,96, A,-; +SIZE_0_ = BIDIR,70, G,-; +AHIGH_30_ = BIDIR,5, B,-; +AHIGH_29_ = BIDIR,6, B,-; +AHIGH_28_ = BIDIR,15, C,-; +AHIGH_27_ = BIDIR,16, C,-; +AHIGH_26_ = BIDIR,17, C,-; +AHIGH_25_ = BIDIR,18, C,-; +AHIGH_24_ = BIDIR,19, C,-; IPL_030_2_ = OUTPUT,9, B,-; +RW_000 = BIDIR,80, H,-; +A_0_ = BIDIR,69, G,-; IPL_030_1_ = OUTPUT,7, B,-; IPL_030_0_ = OUTPUT,8, B,-; -RW_000 = BIDIR,80, H,-; -A0 = BIDIR,69, G,-; BG_000 = OUTPUT,29, D,-; BGACK_030 = OUTPUT,83, H,-; CLK_EXP = OUTPUT,10, B,-; DSACK1 = OUTPUT,81, H,-; VMA = OUTPUT,35, D,-; RW = BIDIR,71, G,-; -N_317_i = NODE,14, F,-; -cpu_est_2_ = NODE,13, D,-; -cpu_est_3_ = NODE,12, F,-; -cpu_est_0_ = NODE,6, D,-; -cpu_est_1_ = NODE,2, D,-; -inst_AS_000_INT = NODE,1, C,-; -SM_AMIGA_5_ = NODE,8, F,-; -inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,2, B,-; -inst_AS_030_D0 = NODE,3, H,-; -inst_nEXP_SPACE_D0reg = NODE,8, A,-; -inst_AS_030_000_SYNC = NODE,4, C,-; +N_226 = NODE,14, F,-; +cpu_est_2_ = NODE,4, F,-; +cpu_est_3_ = NODE,1, F,-; +cpu_est_0_ = NODE,2, B,-; +cpu_est_1_ = NODE,12, F,-; +inst_AS_000_INT = NODE,2, G,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,10, B,-; +inst_AS_030_D0 = NODE,1, H,-; +inst_AS_030_000_SYNC = NODE,13, C,-; inst_BGACK_030_INT_D = NODE,13, H,-; -inst_AS_000_DMA = NODE,1, A,-; -inst_DS_000_DMA = NODE,13, A,-; -CYCLE_DMA_0_ = NODE,5, B,-; -CYCLE_DMA_1_ = NODE,12, C,-; -SIZE_DMA_0_ = NODE,13, G,-; -SIZE_DMA_1_ = NODE,9, G,-; -inst_VPA_D = NODE,2, F,-; -inst_UDS_000_INT = NODE,9, A,-; -inst_LDS_000_INT = NODE,5, A,-; -inst_CLK_OUT_PRE_D = NODE,12, A,-; -inst_DTACK_D0 = NODE,15, B,-; +inst_AS_000_DMA = NODE,12, A,-; +inst_DS_000_DMA = NODE,9, A,-; +CYCLE_DMA_0_ = NODE,10, A,-; +CYCLE_DMA_1_ = NODE,2, A,-; +SIZE_DMA_0_ = NODE,9, G,-; +SIZE_DMA_1_ = NODE,5, G,-; +inst_VPA_D = NODE,5, A,-; +inst_UDS_000_INT = NODE,6, B,-; +inst_LDS_000_INT = NODE,1, A,-; +inst_CLK_OUT_PRE_D = NODE,8, E,-; +CLK_000_D_10_ = NODE,15, G,-; +CLK_000_D_11_ = NODE,10, H,-; +inst_DTACK_D0 = NODE,15, C,-; inst_RESET_OUT = NODE,9, D,-; -inst_CLK_OUT_PRE_50 = NODE,13, F,-; -CLK_000_D_1_ = NODE,8, E,-; -CLK_000_D_0_ = NODE,9, B,-; -inst_CLK_000_PE = NODE,5, G,-; -CLK_000_P_SYNC_9_ = NODE,15, G,-; -inst_CLK_000_NE = NODE,2, G,-; -CLK_000_N_SYNC_11_ = NODE,6, H,-; -IPL_D0_0_ = NODE,11, G,-; -IPL_D0_1_ = NODE,15, D,-; -IPL_D0_2_ = NODE,11, B,-; -inst_CLK_000_NE_D0 = NODE,10, D,-; -SM_AMIGA_0_ = NODE,1, F,-; -inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,13, B,-; -SM_AMIGA_4_ = NODE,9, F,-; -inst_DS_000_ENABLE = NODE,8, C,-; -RST_DLY_0_ = NODE,3, D,-; -RST_DLY_1_ = NODE,14, D,-; -RST_DLY_2_ = NODE,7, D,-; -CLK_000_P_SYNC_0_ = NODE,2, E,-; -CLK_000_P_SYNC_1_ = NODE,7, B,-; -CLK_000_P_SYNC_2_ = NODE,7, G,-; -CLK_000_P_SYNC_3_ = NODE,13, E,-; -CLK_000_P_SYNC_4_ = NODE,3, G,-; +inst_CLK_OUT_PRE_50 = NODE,2, E,-; +CLK_000_D_1_ = NODE,6, C,-; +CLK_000_D_0_ = NODE,13, G,-; +CLK_000_P_SYNC_10_ = NODE,8, A,-; +SM_AMIGA_5_ = NODE,8, F,-; +IPL_D0_0_ = NODE,15, D,-; +IPL_D0_1_ = NODE,15, F,-; +IPL_D0_2_ = NODE,15, B,-; +CLK_000_D_2_ = NODE,11, G,-; +CLK_000_D_3_ = NODE,7, G,-; +CLK_000_D_4_ = NODE,11, C,-; +CLK_000_D_5_ = NODE,13, E,-; +CLK_000_D_6_ = NODE,11, B,-; +CLK_000_D_7_ = NODE,3, G,-; +CLK_000_D_8_ = NODE,7, B,-; +CLK_000_D_9_ = NODE,11, D,-; +CLK_000_D_12_ = NODE,2, H,-; +SM_AMIGA_0_ = NODE,5, F,-; +CLK_000_N_SYNC_0_ = NODE,2, D,-; +SM_AMIGA_4_ = NODE,10, F,-; +inst_DS_000_ENABLE = NODE,9, F,-; +CLK_000_N_SYNC_12_ = NODE,13, D,-; +RST_DLY_0_ = NODE,10, D,-; +RST_DLY_1_ = NODE,6, D,-; +RST_DLY_2_ = NODE,14, D,-; +CLK_000_P_SYNC_0_ = NODE,7, D,-; +CLK_000_P_SYNC_1_ = NODE,15, A,-; +CLK_000_P_SYNC_2_ = NODE,11, F,-; +CLK_000_P_SYNC_3_ = NODE,7, C,-; +CLK_000_P_SYNC_4_ = NODE,11, A,-; CLK_000_P_SYNC_5_ = NODE,14, G,-; -CLK_000_P_SYNC_6_ = NODE,3, A,-; -CLK_000_P_SYNC_7_ = NODE,3, B,-; -CLK_000_P_SYNC_8_ = NODE,10, G,-; -CLK_000_N_SYNC_0_ = NODE,9, E,-; -CLK_000_N_SYNC_1_ = NODE,14, A,-; -CLK_000_N_SYNC_2_ = NODE,14, B,-; -CLK_000_N_SYNC_3_ = NODE,10, B,-; -CLK_000_N_SYNC_4_ = NODE,6, B,-; -CLK_000_N_SYNC_5_ = NODE,11, D,-; -CLK_000_N_SYNC_6_ = NODE,6, G,-; -CLK_000_N_SYNC_7_ = NODE,3, F,-; -CLK_000_N_SYNC_8_ = NODE,10, A,-; -CLK_000_N_SYNC_9_ = NODE,6, A,-; -CLK_000_N_SYNC_10_ = NODE,2, H,-; -SM_AMIGA_6_ = NODE,4, F,-; -inst_CLK_030_H = NODE,2, A,-; -SM_AMIGA_1_ = NODE,5, F,-; -SM_AMIGA_3_ = NODE,6, F,-; -SM_AMIGA_2_ = NODE,10, F,-; +CLK_000_P_SYNC_6_ = NODE,10, G,-; +CLK_000_P_SYNC_7_ = NODE,3, D,-; +CLK_000_P_SYNC_8_ = NODE,7, A,-; +CLK_000_P_SYNC_9_ = NODE,3, C,-; +CLK_000_N_SYNC_1_ = NODE,9, E,-; +CLK_000_N_SYNC_2_ = NODE,3, A,-; +CLK_000_N_SYNC_3_ = NODE,7, F,-; +CLK_000_N_SYNC_4_ = NODE,14, A,-; +CLK_000_N_SYNC_5_ = NODE,6, A,-; +CLK_000_N_SYNC_6_ = NODE,3, B,-; +CLK_000_N_SYNC_7_ = NODE,6, G,-; +CLK_000_N_SYNC_8_ = NODE,14, B,-; +CLK_000_N_SYNC_9_ = NODE,3, F,-; +CLK_000_N_SYNC_10_ = NODE,14, C,-; +CLK_000_N_SYNC_11_ = NODE,10, C,-; +inst_CLK_000_NE_D0 = NODE,5, E,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,2, C,-; +SM_AMIGA_6_ = NODE,9, C,-; +inst_CLK_030_H = NODE,13, A,-; +SM_AMIGA_1_ = NODE,13, F,-; +SM_AMIGA_3_ = NODE,2, F,-; +SM_AMIGA_2_ = NODE,6, F,-; SM_AMIGA_i_7_ = NODE,0, F,-; -CIIN_0 = NODE,5, E,-; +CIIN_0 = NODE,10, E,-; diff --git a/Logic/68030_tk.vct b/Logic/68030_tk.vct index c26f14d..a90ec30 100644 --- a/Logic/68030_tk.vct +++ b/Logic/68030_tk.vct @@ -15,8 +15,8 @@ Voltage = 5.0; RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; -DATE = 03/16/2015; -TIME = 21:53:52; +DATE = 08/18/2016; +TIME = 23:26:14; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -177,6 +177,24 @@ FPU_SENSE = input,91,A,-; A1 = input,60,F,-; A_3_ = input,44,E,-; A_2_ = input,43,E,-; +AHIGH_24_ = input,19,C,-; +AHIGH_25_ = input,18,C,-; +AHIGH_26_ = input,17,C,-; +AHIGH_27_ = input,16,C,-; +AHIGH_28_ = input,15,C,-; +AHIGH_29_ = input,6,B,-; +AHIGH_30_ = input,5,B,-; +AHIGH_31_ = input,4,B,-; +A_1_ = input,60,F,-; +A_0_ = input,69,G,-; +A_DECODE_16_ = input,96,A,-; +A_DECODE_17_ = input,59,F,-; +A_DECODE_18_ = input,95,A,-; +A_DECODE_19_ = input,97,A,-; +A_DECODE_20_ = input,93,A,-; +A_DECODE_21_ = input,94,A,-; +A_DECODE_22_ = input,84,H,-; +A_DECODE_23_ = input,85,H,-; [GROUP ASSIGNMENT] Layer = OFF; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index 6389c2e..e6cfb84 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 2.0.00.17.20.15 -Design '68030_tk' created Wed Aug 17 17:45:46 2016 +Design '68030_tk' created Fri Aug 19 00:20:41 2016 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index 79f04b4..f539379 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,237 +1,243 @@ -#$ DATE Wed Aug 17 17:45:46 2016 +#$ DATE Fri Aug 19 00:20:41 2016 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 75 A_8_ A_7_ SIZE_1_ A_6_ A_5_ A_31_ A_4_ A_3_ IPL_030_2_ A_2_ IPL_030_1_ IPL_2_ IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE SIZE_0_ AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_15_ A_14_ A_13_ A_12_ A_11_ A_10_ A_9_ -#$ NODES 680 N_280 N_210_0 cpu_est_0_1__un0_n N_279 N_289_0 cpu_est_0_2__un3_n N_271 N_218_0 cpu_est_0_2__un1_n N_272 \ -# cpu_est_0_2__un0_n N_276 N_242_i cpu_est_0_3__un3_n DS_000_ENABLE_1_sqmuxa_1 N_246_i cpu_est_0_3__un1_n inst_BGACK_030_INTreg N_4 N_240_i \ -# cpu_est_0_3__un0_n vcc_n_n N_5 N_241_i ipl_030_0_0__un3_n inst_VMA_INTreg N_7 ipl_030_0_0__un1_n gnd_n_n N_10 \ -# N_266_i ipl_030_0_0__un0_n un1_amiga_bus_enable_low N_18 N_267_i ipl_030_0_1__un3_n un3_size N_24 N_254_i ipl_030_0_1__un1_n \ -# un4_size N_6 N_317_i ipl_030_0_1__un0_n un4_uds_000 un1_amiga_bus_enable_low_i ipl_030_0_2__un3_n un4_lds_000 un21_fpu_cs_i N_313_i \ -# ipl_030_0_2__un1_n un5_ciin BGACK_030_INT_i N_316_i ipl_030_0_2__un0_n un4_as_000 AMIGA_BUS_ENABLE_DMA_LOW_i N_312_i a0_dma_0_un3_n un21_fpu_cs \ -# UDS_000_INT_i a0_dma_0_un1_n un22_berr LDS_000_INT_i N_347_i a0_dma_0_un0_n un6_ds_030 N_236_i N_323_i uds_000_int_0_un3_n \ -# cpu_est_2_ sm_amiga_i_5__n N_324_i uds_000_int_0_un1_n cpu_est_3_ DS_000_ENABLE_1_sqmuxa_i N_222_i uds_000_int_0_un0_n cpu_est_0_ N_276_i \ -# AS_000_DMA_i vma_int_0_un3_n cpu_est_1_ RST_i N_221_0 vma_int_0_un1_n inst_AS_000_INT a_i_19__n N_220_0 vma_int_0_un0_n \ -# SM_AMIGA_5_ a_i_18__n N_219_0 amiga_bus_enable_dma_high_0_un3_n inst_AMIGA_BUS_ENABLE_DMA_LOW size_dma_i_1__n N_216_0 amiga_bus_enable_dma_high_0_un1_n inst_AS_030_D0 size_dma_i_0__n \ -# N_290_0 amiga_bus_enable_dma_high_0_un0_n inst_nEXP_SPACE_D0reg RW_i N_212_0 bg_000_0_un3_n inst_AS_030_000_SYNC CLK_000_PE_i N_211_0 bg_000_0_un1_n \ -# inst_BGACK_030_INT_D a_i_16__n N_204_0 bg_000_0_un0_n inst_AS_000_DMA RESET_OUT_i N_351_i ds_000_dma_0_un3_n inst_DS_000_DMA BERR_i \ -# N_353_i ds_000_dma_0_un1_n CYCLE_DMA_0_ sm_amiga_i_i_7__n N_201_i ds_000_dma_0_un0_n CYCLE_DMA_1_ nEXP_SPACE_D0_i VMA_INT_i as_000_dma_0_un3_n \ -# SIZE_DMA_0_ sm_amiga_i_4__n N_197_i as_000_dma_0_un1_n SIZE_DMA_1_ FPU_SENSE_i N_196_i as_000_dma_0_un0_n inst_VPA_D AS_030_i \ -# N_193_i lds_000_int_0_un3_n inst_UDS_000_INT AS_030_D0_i N_192_0 lds_000_int_0_un1_n inst_LDS_000_INT a_i_24__n clk_000_n_sync_i_10__n lds_000_int_0_un0_n \ -# inst_CLK_OUT_PRE_D sm_amiga_i_3__n N_350_i rw_000_dma_0_un3_n inst_DTACK_D0 cpu_est_i_0__n N_188_0 rw_000_dma_0_un1_n inst_RESET_OUT cpu_est_i_3__n \ -# N_187_i rw_000_dma_0_un0_n inst_CLK_OUT_PRE_50 cpu_est_i_2__n N_185_i a_15__n CLK_000_D_1_ cpu_est_i_1__n N_182_i CLK_000_D_0_ \ -# VPA_D_i N_181_i a_14__n inst_CLK_000_PE CLK_000_NE_i CLK_OUT_PRE_D_i CLK_000_P_SYNC_9_ sm_amiga_i_1__n N_175_0 a_13__n \ -# inst_CLK_000_NE rst_dly_i_2__n N_168_i CLK_000_N_SYNC_11_ CLK_030_i AS_030_000_SYNC_i a_12__n IPL_D0_0_ rst_dly_i_0__n N_158_i \ -# IPL_D0_1_ rst_dly_i_1__n clk_000_d_i_0__n a_11__n IPL_D0_2_ clk_000_d_i_1__n N_148_i inst_CLK_000_NE_D0 DTACK_D0_i N_345_i \ -# a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i SM_AMIGA_0_ CLK_030_H_i N_144_0 a_9__n inst_AMIGA_BUS_ENABLE_DMA_HIGH sm_amiga_i_6__n \ -# N_138_0 inst_DSACK1_INTreg sm_amiga_i_2__n a_8__n AS_000_i N_342_i pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n \ -# SM_AMIGA_4_ A1_i N_124_0 inst_DS_000_ENABLE a_i_31__n N_341_i a_6__n RST_DLY_0_ a_i_29__n N_119_0 \ -# RST_DLY_1_ a_i_30__n N_340_i a_5__n RST_DLY_2_ a_i_27__n N_361_i pos_clk_un9_bg_030_n a_i_28__n cpu_est_2_0_2__n \ -# a_4__n CLK_000_P_SYNC_0_ a_i_25__n N_338_i CLK_000_P_SYNC_1_ a_i_26__n N_339_i a_3__n CLK_000_P_SYNC_2_ N_213_i \ -# cpu_est_2_0_1__n CLK_000_P_SYNC_3_ N_214_i N_332_i a_2__n CLK_000_P_SYNC_4_ N_215_i N_336_i CLK_000_P_SYNC_5_ pos_clk_un7_clk_000_pe_0_n \ -# CLK_000_P_SYNC_6_ N_275_i N_99_0 CLK_000_P_SYNC_7_ un6_ds_030_i N_331_i CLK_000_P_SYNC_8_ DS_000_DMA_i N_96_0 CLK_000_N_SYNC_0_ \ -# un4_as_000_i N_330_i CLK_000_N_SYNC_1_ AS_000_INT_i N_90_0 CLK_000_N_SYNC_2_ un4_lds_000_i N_328_i CLK_000_N_SYNC_3_ un4_uds_000_i \ -# CLK_000_N_SYNC_4_ AS_030_c N_80_0 CLK_000_N_SYNC_5_ N_325_i CLK_000_N_SYNC_6_ AS_000_c N_326_i CLK_000_N_SYNC_7_ N_258_0 \ -# CLK_000_N_SYNC_8_ RW_000_c N_217_i CLK_000_N_SYNC_9_ N_321_i CLK_000_N_SYNC_10_ N_322_i inst_RW_000_INT UDS_000_c inst_RW_000_DMA \ -# N_320_i pos_clk_un7_clk_000_pe_n LDS_000_c inst_A0_DMA un5_ciin_i pos_clk_a0_dma_3_n size_c_0__n N_61_0 SM_AMIGA_6_ N_310_i \ -# inst_CLK_030_H size_c_1__n SM_AMIGA_1_ N_305_i SM_AMIGA_3_ N_307_i SM_AMIGA_2_ N_3 N_303_i N_8 \ -# N_304_i N_283_0 N_301_i N_300_i N_123_0 N_17 N_278_i N_19 N_297_i N_20 \ -# AMIGA_BUS_DATA_DIR_c_0 N_21 N_277_i N_22 N_25 N_26 pos_clk_un8_sm_amiga_i_n N_27 A0_c_i N_28 \ -# size_c_i_1__n N_29 N_29_i N_32_0 N_28_i N_31_0 N_27_i N_30_0 ipl_c_i_2__n N_53_0 \ -# ipl_c_i_1__n N_52_0 a_c_16__n ipl_c_i_0__n N_51_0 a_c_17__n DTACK_c_i N_56_0 a_c_18__n VPA_c_i \ -# N_55_0 a_c_19__n nEXP_SPACE_c_i N_54_0 a_c_20__n N_3_i N_49_0 a_c_21__n N_8_i N_45_0 \ -# a_c_22__n N_17_i N_42_0 a_c_23__n N_19_i N_40_0 SM_AMIGA_i_7_ a_c_24__n N_20_i N_123 \ -# N_39_0 cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i G_134 \ -# N_37_0 G_135 a_c_27__n N_25_i G_136 N_34_0 N_217 a_c_28__n N_26_i N_33_0 \ -# N_61 a_c_29__n BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 N_289_0_1 a_c_31__n \ -# un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c \ -# N_351_2 N_124 N_168_i_1 N_138 nEXP_SPACE_c N_192_0_1 N_144 N_192_0_2 N_158 BERR_c \ -# N_137_i_1 N_168 N_137_i_2 N_175 BG_030_c N_145_i_1 N_182 N_145_i_2 N_185 BG_000DFFreg \ -# N_145_i_3 N_187 N_260_i_1 N_188 N_260_i_2 N_192 BGACK_000_c N_259_i_1 N_193 N_259_i_2 \ -# N_197 CLK_030_c N_336_1 N_201 N_336_2 N_204 N_332_1 N_206 N_332_2 N_207 \ -# CLK_OSZI_c N_332_3 N_317_1 N_211 N_317_2 N_212 CLK_OUT_INTreg N_317_3 N_290 N_304_1 \ -# N_216 N_304_2 N_219 FPU_SENSE_c un5_ciin_1 N_220 un5_ciin_2 N_221 IPL_030DFF_0_reg un5_ciin_3 \ -# N_227 un5_ciin_4 N_229 IPL_030DFF_1_reg un5_ciin_5 N_230 un5_ciin_6 N_236 IPL_030DFF_2_reg un5_ciin_7 \ -# N_240 un5_ciin_8 N_241 ipl_c_0__n un5_ciin_9 N_242 un5_ciin_10 N_246 ipl_c_1__n un5_ciin_11 \ -# N_254 un22_berr_1_0 N_266 ipl_c_2__n un21_fpu_cs_1 N_267 N_375_1 N_275 N_375_2 N_277 \ -# DTACK_c N_375_3 N_278 N_375_4 N_297 N_134_i_1 N_300 N_96_0_1 N_301 VPA_c \ -# N_83_i_1 N_303 N_261_i_1 N_304 N_141_i_1 N_305 RST_c N_139_i_1 N_307 N_133_i_1 \ -# N_310 N_123_0_1 N_312 RW_c N_282_i_1 N_313 N_343_1 N_316 fc_c_0__n N_339_1 \ -# N_317 pos_clk_un6_bg_030_1_n N_320 fc_c_1__n N_326_1 N_321 N_325_1 N_322 N_324_1 N_323 \ -# AMIGA_BUS_DATA_DIR_c N_316_1 N_324 N_313_1 N_325 N_303_1 N_326 N_297_1 N_328 N_266_1 \ -# N_330 N_24_i N_240_1 N_331 N_35_0 pos_clk_ipl_1_n N_332 N_18_i amiga_bus_enable_dma_low_0_un3_n N_336 \ -# N_41_0 amiga_bus_enable_dma_low_0_un1_n N_338 N_10_i amiga_bus_enable_dma_low_0_un0_n N_339 N_43_0 rw_000_int_0_un3_n N_340 N_7_i \ -# rw_000_int_0_un1_n N_341 N_46_0 rw_000_int_0_un0_n N_342 N_5_i bgack_030_int_0_un3_n N_343 N_47_0 bgack_030_int_0_un1_n \ -# N_344 N_4_i bgack_030_int_0_un0_n N_345 N_48_0 as_030_000_sync_0_un3_n N_347 N_272_i as_030_000_sync_0_un1_n N_350 \ -# N_271_i as_030_000_sync_0_un0_n N_351 N_279_0 ds_000_enable_0_un3_n N_353 N_280_0 ds_000_enable_0_un1_n N_361 N_281_0 \ -# ds_000_enable_0_un0_n pos_clk_un23_bgack_030_int_i_i_a4_i_x2 N_298_i as_000_int_0_un3_n pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_size_dma_6_0_0__n as_000_int_0_un1_n cpu_est_0_0_x2_0_ N_299_i as_000_int_0_un0_n \ -# pos_clk_CYCLE_DMA_5_1_i_x2 pos_clk_size_dma_6_0_1__n dsack1_int_0_un3_n un22_berr_1 un1_as_000_i dsack1_int_0_un1_n N_375 N_358_i dsack1_int_0_un0_n N_218 \ -# pos_clk_un6_bgack_000_0_n size_dma_0_1__un3_n N_156 N_284_i size_dma_0_1__un1_n N_289 N_285_i size_dma_0_1__un0_n N_354 N_286_0 \ -# size_dma_0_0__un3_n N_205 N_88_0 size_dma_0_0__un1_n un1_SM_AMIGA_5 pos_clk_un3_as_030_d0_i_n size_dma_0_0__un0_n DS_000_ENABLE_1_sqmuxa N_156_i sm_amiga_srsts_i_0_m2_1__un3_n \ -# N_349 N_349_i sm_amiga_srsts_i_0_m2_1__un1_n pos_clk_un3_as_030_d0_n N_194_i sm_amiga_srsts_i_0_m2_1__un0_n N_286 un1_SM_AMIGA_5_i un1_amiga_bus_enable_dma_high_i_m2_0__un3_n pos_clk_un6_bgack_000_n \ -# UDS_000_c_i un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_358 LDS_000_c_i un1_amiga_bus_enable_dma_high_i_m2_0__un0_n pos_clk_size_dma_6_1__n N_205_i sm_amiga_srsts_i_0_m2_5__un3_n N_299 N_206_0 \ -# sm_amiga_srsts_i_0_m2_5__un1_n pos_clk_size_dma_6_0__n N_207_0 sm_amiga_srsts_i_0_m2_5__un0_n N_298 N_354_i cpu_est_0_1__un3_n N_281 N_208_0 cpu_est_0_1__un1_n \ -# +#$ PINS 75 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ AHIGH_31_ A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ A_DECODE_15_ A_DECODE_14_ A_DECODE_13_ IPL_030_2_ A_DECODE_12_ A_DECODE_11_ IPL_2_ A_DECODE_10_ A_DECODE_9_ FC_1_ A_DECODE_8_ AS_030 A_DECODE_7_ AS_000 A_DECODE_6_ RW_000 A_DECODE_5_ DS_030 A_DECODE_4_ UDS_000 A_DECODE_3_ LDS_000 A_DECODE_2_ nEXP_SPACE A_0_ BERR IPL_030_1_ BG_030 IPL_030_0_ BG_000 IPL_1_ BGACK_030 IPL_0_ BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ +#$ NODES 694 N_166 N_32_0 cpu_est_0_3__un0_n N_141 a_c_i_0__n cpu_est_0_2__un3_n N_226 size_c_i_1__n cpu_est_0_2__un1_n N_357 \ +# pos_clk_un10_sm_amiga_i_n cpu_est_0_2__un0_n N_219 N_258_0 sm_amiga_srsts_i_0_m2_1__un3_n N_217 N_357_i sm_amiga_srsts_i_0_m2_1__un1_n N_221 N_254_i \ +# sm_amiga_srsts_i_0_m2_1__un0_n N_220 cpu_est_2_0_2__n vma_int_0_un3_n inst_BGACK_030_INTreg N_223 N_315_i vma_int_0_un1_n vcc_n_n N_343 \ +# N_291_0 vma_int_0_un0_n inst_VMA_INTreg N_192 AS_030_000_SYNC_i cpu_est_0_1__un3_n gnd_n_n N_164 N_146_0 cpu_est_0_1__un1_n \ +# un1_amiga_bus_enable_dma_high_0__n N_291 N_149_i cpu_est_0_1__un0_n un1_amiga_bus_enable_low N_315 N_164_i sm_amiga_srsts_i_0_0_m2_5__un3_n un6_as_030 cpu_est_2_2__n \ +# N_166_i sm_amiga_srsts_i_0_0_m2_5__un1_n un3_size N_254 N_172_i sm_amiga_srsts_i_0_0_m2_5__un0_n un4_size N_258 N_176_i rw_000_int_0_un3_n \ +# un4_uds_000 N_29 N_186_0 rw_000_int_0_un1_n un4_lds_000 N_28 N_192_0 rw_000_int_0_un0_n un4_as_000 N_27 \ +# N_228_i bgack_030_int_0_un3_n un10_ciin N_4 N_227_i bgack_030_int_0_un1_n un21_fpu_cs N_17 N_343_i bgack_030_int_0_un0_n \ +# un22_berr N_21 as_000_int_0_un3_n un6_ds_030 N_26 N_223_i as_000_int_0_un1_n cpu_est_2_ pos_clk_un9_bg_030_n N_225_i \ +# as_000_int_0_un0_n cpu_est_3_ un1_amiga_bus_enable_low_i N_224_i ds_000_enable_0_un3_n cpu_est_0_ un21_fpu_cs_i N_226_i ds_000_enable_0_un1_n cpu_est_1_ \ +# N_275_i ds_000_enable_0_un0_n inst_AS_000_INT clk_000_n_sync_i_12__n N_220_i as_030_000_sync_0_un3_n inst_AMIGA_BUS_ENABLE_DMA_LOW rst_dly_i_2__n N_221_i as_030_000_sync_0_un1_n \ +# inst_AS_030_D0 rst_dly_i_1__n N_222_i as_030_000_sync_0_un0_n inst_AS_030_000_SYNC BERR_i un1_amiga_bus_enable_dma_high_0_m2_0__un3_n inst_BGACK_030_INT_D cpu_est_i_2__n N_217_i \ +# un1_amiga_bus_enable_dma_high_0_m2_0__un1_n inst_AS_000_DMA nEXP_SPACE_i N_215_i un1_amiga_bus_enable_dma_high_0_m2_0__un0_n inst_DS_000_DMA rst_dly_i_0__n N_219_i amiga_bus_enable_dma_low_0_un3_n CYCLE_DMA_0_ \ +# cpu_est_i_1__n amiga_bus_enable_dma_low_0_un1_n CYCLE_DMA_1_ cpu_est_i_0__n N_200_i amiga_bus_enable_dma_low_0_un0_n SIZE_DMA_0_ VPA_D_i N_195_0 amiga_bus_enable_dma_high_0_un3_n \ +# SIZE_DMA_1_ sm_amiga_i_3__n N_190_0 amiga_bus_enable_dma_high_0_un1_n inst_VPA_D sm_amiga_i_0__n N_157_i amiga_bus_enable_dma_high_0_un0_n inst_UDS_000_INT cpu_est_i_3__n \ +# N_154_i size_dma_0_0__un3_n inst_LDS_000_INT sm_amiga_i_1__n N_340_i size_dma_0_0__un1_n inst_CLK_OUT_PRE_D RESET_OUT_i N_141_0 size_dma_0_0__un0_n \ +# CLK_000_D_10_ BGACK_030_INT_i un3_as_030_i size_dma_0_1__un3_n CLK_000_D_11_ sm_amiga_i_2__n N_216_i size_dma_0_1__un1_n inst_DTACK_D0 sm_amiga_i_4__n \ +# N_337_i size_dma_0_1__un0_n inst_RESET_OUT clk_000_p_sync_i_10__n ds_000_dma_0_un3_n inst_CLK_OUT_PRE_50 sm_amiga_i_5__n un10_ciin_i ds_000_dma_0_un1_n CLK_000_D_1_ \ +# sm_amiga_i_i_7__n N_296_0 ds_000_dma_0_un0_n CLK_000_D_0_ clk_000_d_i_11__n un1_as_000_i as_000_dma_0_un3_n CLK_000_P_SYNC_10_ sm_amiga_i_6__n N_284_i \ +# as_000_dma_0_un1_n SM_AMIGA_5_ RW_i N_285_i as_000_dma_0_un0_n IPL_D0_0_ DS_000_ENABLE_1_sqmuxa_i N_292_0 rw_000_dma_0_un3_n IPL_D0_1_ \ +# LDS_000_INT_i N_280_i rw_000_dma_0_un1_n IPL_D0_2_ UDS_000_INT_i N_277_i rw_000_dma_0_un0_n CLK_000_D_2_ AS_030_i N_257_0 \ +# a0_dma_0_un3_n CLK_000_D_3_ AS_000_INT_i N_235_i a0_dma_0_un1_n CLK_000_D_4_ a_decode_i_19__n N_236_i a0_dma_0_un0_n CLK_000_D_5_ \ +# a_decode_i_18__n cpu_est_2_0_1__n a_decode_15__n CLK_000_D_6_ a_decode_i_16__n N_231_i CLK_000_D_7_ AS_000_i N_230_i a_decode_14__n \ +# CLK_000_D_8_ FPU_SENSE_i pos_clk_un4_clk_000_pe_0_n CLK_000_D_9_ AMIGA_BUS_ENABLE_DMA_HIGH_i N_22_i a_decode_13__n CLK_000_D_12_ CLK_030_i N_37_0 \ +# pos_clk_un6_bg_030_n DTACK_D0_i a_decode_12__n SM_AMIGA_0_ clk_000_d_i_10__n N_334_i inst_DSACK1_INTreg RW_000_i N_335_i a_decode_11__n \ +# a_i_1__n N_194_0 CLK_030_H_i N_191_0 a_decode_10__n pos_clk_ipl_n AS_000_DMA_i un1_SM_AMIGA_5_i CLK_000_N_SYNC_0_ clk_000_d_i_0__n \ +# N_346_i a_decode_9__n SM_AMIGA_4_ clk_000_d_i_1__n N_163_i inst_DS_000_ENABLE AS_030_D0_i N_345_i a_decode_8__n CLK_000_N_SYNC_12_ \ +# size_dma_i_0__n N_344_i RST_DLY_0_ size_dma_i_1__n N_153_0 a_decode_7__n RST_DLY_1_ ahigh_i_30__n pos_clk_un3_as_030_d0_i_n RST_DLY_2_ \ +# ahigh_i_31__n N_293_0 a_decode_6__n CLK_000_P_SYNC_0_ ahigh_i_28__n N_233_i CLK_000_P_SYNC_1_ ahigh_i_29__n N_232_i a_decode_5__n \ +# CLK_000_P_SYNC_2_ ahigh_i_26__n N_290_0 CLK_000_P_SYNC_3_ ahigh_i_27__n VPA_c_i a_decode_4__n CLK_000_P_SYNC_4_ ahigh_i_24__n N_54_0 \ +# CLK_000_P_SYNC_5_ ahigh_i_25__n N_5_i a_decode_3__n CLK_000_P_SYNC_6_ N_212_i N_47_0 CLK_000_P_SYNC_7_ N_213_i N_7_i \ +# a_decode_2__n CLK_000_P_SYNC_8_ N_214_i N_46_0 CLK_000_P_SYNC_9_ N_18_i CLK_000_N_SYNC_1_ N_41_0 CLK_000_N_SYNC_2_ N_321_i \ +# N_10_i CLK_000_N_SYNC_3_ N_322_i N_43_0 CLK_000_N_SYNC_4_ un6_ds_030_i DTACK_c_i CLK_000_N_SYNC_5_ DS_000_DMA_i N_55_0 \ +# CLK_000_N_SYNC_6_ un4_as_000_i pos_clk_un6_bgack_000_0_n CLK_000_N_SYNC_7_ un6_as_030_i N_137_i CLK_000_N_SYNC_8_ un4_lds_000_i N_184_0 CLK_000_N_SYNC_9_ \ +# un4_uds_000_i N_349_i CLK_000_N_SYNC_10_ AMIGA_BUS_ENABLE_DMA_LOW_i N_185_i CLK_000_N_SYNC_11_ AS_030_c N_187_0 pos_clk_un5_bgack_030_int_d_n N_203_i \ +# inst_RW_000_INT AS_000_c N_324_i inst_RW_000_DMA inst_CLK_000_NE_D0 RW_000_c N_199_0 inst_AMIGA_BUS_ENABLE_DMA_HIGH N_197_0 inst_A0_DMA \ +# N_196_0 pos_clk_a0_dma_3_n UDS_000_c LDS_000_c_i SM_AMIGA_6_ UDS_000_c_i inst_CLK_030_H LDS_000_c N_181_i SM_AMIGA_1_ \ +# N_347_i SM_AMIGA_3_ size_c_0__n N_348_i SM_AMIGA_2_ N_178_i pos_clk_ds_000_dma_4_n size_c_1__n VMA_INT_i N_3 \ +# pos_clk_un5_bgack_030_int_d_i_n N_8 ahigh_c_24__n pos_clk_un23_bgack_030_int_i_1_0_n CLK_OUT_PRE_D_i ahigh_c_25__n N_148_0 N_341_i ahigh_c_26__n N_338_i \ +# N_339_i N_19 ahigh_c_27__n N_20 N_336_i N_24 ahigh_c_28__n N_122_0 N_25 N_211_i \ +# ahigh_c_29__n N_332_i ahigh_c_30__n N_331_i N_120_0 ahigh_c_31__n N_330_i pos_clk_ds_000_dma_4_0_n N_329_i pos_clk_size_dma_6_0_1__n \ +# N_328_i pos_clk_size_dma_6_0_0__n N_325_i N_327_i AMIGA_BUS_DATA_DIR_c_0 N_320_i N_298_0 N_295_0 N_294_0 N_319_i \ +# un1_amiga_bus_enable_dma_high_0_0__n N_206_i N_283_i SM_AMIGA_i_7_ N_122 N_281_i pos_clk_size_dma_6_0__n N_282_i pos_clk_size_dma_6_1__n G_134 \ +# N_3_i G_135 N_49_0 G_136 N_8_i N_45_0 pos_clk_un23_bgack_030_int_i_1_n N_19_i N_292 N_40_0 \ +# N_294 a_decode_c_16__n N_20_i N_295 N_39_0 N_296 a_decode_c_17__n N_24_i N_298 N_35_0 \ +# N_120 a_decode_c_18__n N_25_i N_148 N_34_0 N_149 a_decode_c_19__n N_194_0_1 N_157 N_237_i_1 \ +# N_172 a_decode_c_20__n N_237_i_2 N_176 N_238_i_1 N_178 a_decode_c_21__n N_238_i_2 N_181 N_144_i_1 \ +# N_184 a_decode_c_22__n N_144_i_2 N_144_i_3 N_196 a_decode_c_23__n N_136_i_1 N_197 N_136_i_2 N_206 \ +# a_c_0__n N_176_i_1 N_207 N_146_0_1 N_211 a_c_1__n pos_clk_un10_sm_amiga_i_1_n N_215 un10_ciin_1 N_222 \ +# nEXP_SPACE_c un10_ciin_2 N_224 un10_ciin_3 N_225 BERR_c un10_ciin_4 N_227 un10_ciin_5 N_228 \ +# BG_030_c un10_ciin_6 N_236 un10_ciin_7 N_277 BG_000DFFreg un10_ciin_8 N_281 un10_ciin_9 N_282 \ +# un10_ciin_10 N_283 BGACK_000_c un10_ciin_11 N_285 N_347_1 N_318 CLK_030_c N_347_2 N_319 \ +# pos_clk_un23_bgack_030_int_i_1_0_1_n N_320 CLK_000_c pos_clk_un23_bgack_030_int_i_1_0_2_n N_321 un21_fpu_cs_1 N_322 CLK_OSZI_c un22_berr_1_0 N_323 \ +# N_366_1 N_325 N_366_2 N_327 CLK_OUT_INTreg N_366_3 N_328 N_366_4 N_329 un1_SM_AMIGA_5_i_1 \ +# N_330 FPU_SENSE_c un1_SM_AMIGA_5_i_2 N_331 N_142_i_1 N_332 IPL_030DFF_0_reg N_142_i_2 N_336 N_339_1 \ +# N_338 IPL_030DFF_1_reg N_280_1 N_339 N_280_2 N_341 IPL_030DFF_2_reg N_231_1 N_344 N_231_2 \ +# N_347 ipl_c_0__n N_230_1 N_348 N_230_2 pos_clk_un23_bgack_030_int_i_0_x2 ipl_c_1__n N_230_3 cpu_est_0_0_x2_0_x2_0_ N_226_1 \ +# pos_clk_CYCLE_DMA_5_0_i_x2 ipl_c_2__n N_226_2 pos_clk_CYCLE_DMA_5_1_i_x2 N_226_3 N_199 N_239_i_1 N_324 DTACK_c N_122_0_1 \ +# un22_berr_1 N_132_i_1 N_366 N_120_0_1 N_335 N_106_i_1 N_208 VPA_c N_103_i_1 N_203 \ +# N_92_i_1 N_187 N_140_i_1 N_137 RST_c N_138_i_1 N_349 N_344_1 pos_clk_un6_bgack_000_n pos_clk_un6_bg_030_1_n \ +# N_10 RW_c N_327_1 N_5 N_319_1 N_293 fc_c_0__n N_285_1 N_6 N_277_1 \ +# un1_SM_AMIGA_5 fc_c_1__n N_236_1 DS_000_ENABLE_1_sqmuxa_1 N_228_1 N_7 N_225_1 pos_clk_un3_as_030_d0_n AMIGA_BUS_DATA_DIR_c N_224_1 \ +# N_290 N_222_1 N_18 N_215_1 DS_000_ENABLE_1_sqmuxa pos_clk_ipl_1_n N_232 bg_000_0_un3_n N_194 BG_030_c_i \ +# bg_000_0_un1_n N_233 pos_clk_un6_bg_030_i_n bg_000_0_un0_n N_275 pos_clk_un9_bg_030_0_n uds_000_int_0_un3_n N_153 N_26_i uds_000_int_0_un1_n \ +# N_191 N_33_0 uds_000_int_0_un0_n N_334 N_21_i lds_000_int_0_un3_n N_146 N_38_0 lds_000_int_0_un1_n N_345 \ +# N_17_i lds_000_int_0_un0_n N_346 N_42_0 dsack1_int_0_un3_n N_163 N_4_i dsack1_int_0_un1_n N_22 N_48_0 \ +# dsack1_int_0_un0_n pos_clk_un4_clk_000_pe_n ipl_c_i_0__n ipl_030_0_2__un3_n cpu_est_2_1__n N_51_0 ipl_030_0_2__un1_n N_235 ipl_c_i_1__n ipl_030_0_2__un0_n \ +# N_284 N_52_0 ipl_030_0_1__un3_n N_190 ipl_c_i_2__n ipl_030_0_1__un1_n N_337 N_53_0 ipl_030_0_1__un0_n N_195 \ +# N_27_i ipl_030_0_0__un3_n N_340 N_30_0 ipl_030_0_0__un1_n N_231 N_28_i ipl_030_0_0__un0_n N_230 N_31_0 \ +# cpu_est_0_3__un3_n N_280 N_29_i cpu_est_0_3__un1_n .model bus68030 -.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ - CLK_OSZI.BLIF FPU_SENSE.BLIF DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \ - A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF \ - A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF \ - A_8_.BLIF A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ - FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_280.BLIF N_210_0.BLIF cpu_est_0_1__un0_n.BLIF N_279.BLIF N_289_0.BLIF cpu_est_0_2__un3_n.BLIF N_271.BLIF N_218_0.BLIF \ - cpu_est_0_2__un1_n.BLIF N_272.BLIF cpu_est_0_2__un0_n.BLIF N_276.BLIF N_242_i.BLIF cpu_est_0_3__un3_n.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF N_246_i.BLIF cpu_est_0_3__un1_n.BLIF \ - inst_BGACK_030_INTreg.BLIF N_4.BLIF N_240_i.BLIF cpu_est_0_3__un0_n.BLIF vcc_n_n.BLIF N_5.BLIF N_241_i.BLIF ipl_030_0_0__un3_n.BLIF inst_VMA_INTreg.BLIF \ - N_7.BLIF ipl_030_0_0__un1_n.BLIF gnd_n_n.BLIF N_10.BLIF N_266_i.BLIF ipl_030_0_0__un0_n.BLIF un1_amiga_bus_enable_low.BLIF N_18.BLIF N_267_i.BLIF \ - ipl_030_0_1__un3_n.BLIF un3_size.BLIF N_24.BLIF N_254_i.BLIF ipl_030_0_1__un1_n.BLIF un4_size.BLIF N_6.BLIF N_317_i.BLIF ipl_030_0_1__un0_n.BLIF \ - un4_uds_000.BLIF un1_amiga_bus_enable_low_i.BLIF ipl_030_0_2__un3_n.BLIF un4_lds_000.BLIF un21_fpu_cs_i.BLIF N_313_i.BLIF ipl_030_0_2__un1_n.BLIF un5_ciin.BLIF BGACK_030_INT_i.BLIF \ - N_316_i.BLIF ipl_030_0_2__un0_n.BLIF un4_as_000.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_312_i.BLIF a0_dma_0_un3_n.BLIF un21_fpu_cs.BLIF UDS_000_INT_i.BLIF a0_dma_0_un1_n.BLIF \ - un22_berr.BLIF LDS_000_INT_i.BLIF N_347_i.BLIF a0_dma_0_un0_n.BLIF un6_ds_030.BLIF N_236_i.BLIF N_323_i.BLIF uds_000_int_0_un3_n.BLIF cpu_est_2_.BLIF \ - sm_amiga_i_5__n.BLIF N_324_i.BLIF uds_000_int_0_un1_n.BLIF cpu_est_3_.BLIF DS_000_ENABLE_1_sqmuxa_i.BLIF N_222_i.BLIF uds_000_int_0_un0_n.BLIF cpu_est_0_.BLIF N_276_i.BLIF \ - AS_000_DMA_i.BLIF vma_int_0_un3_n.BLIF cpu_est_1_.BLIF RST_i.BLIF N_221_0.BLIF vma_int_0_un1_n.BLIF inst_AS_000_INT.BLIF a_i_19__n.BLIF N_220_0.BLIF \ - vma_int_0_un0_n.BLIF SM_AMIGA_5_.BLIF a_i_18__n.BLIF N_219_0.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF size_dma_i_1__n.BLIF N_216_0.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF \ - inst_AS_030_D0.BLIF size_dma_i_0__n.BLIF N_290_0.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF inst_nEXP_SPACE_D0reg.BLIF RW_i.BLIF N_212_0.BLIF bg_000_0_un3_n.BLIF inst_AS_030_000_SYNC.BLIF \ - CLK_000_PE_i.BLIF N_211_0.BLIF bg_000_0_un1_n.BLIF inst_BGACK_030_INT_D.BLIF a_i_16__n.BLIF N_204_0.BLIF bg_000_0_un0_n.BLIF inst_AS_000_DMA.BLIF RESET_OUT_i.BLIF \ - N_351_i.BLIF ds_000_dma_0_un3_n.BLIF inst_DS_000_DMA.BLIF BERR_i.BLIF N_353_i.BLIF ds_000_dma_0_un1_n.BLIF CYCLE_DMA_0_.BLIF sm_amiga_i_i_7__n.BLIF N_201_i.BLIF \ - ds_000_dma_0_un0_n.BLIF CYCLE_DMA_1_.BLIF nEXP_SPACE_D0_i.BLIF VMA_INT_i.BLIF as_000_dma_0_un3_n.BLIF SIZE_DMA_0_.BLIF sm_amiga_i_4__n.BLIF N_197_i.BLIF as_000_dma_0_un1_n.BLIF \ - SIZE_DMA_1_.BLIF FPU_SENSE_i.BLIF N_196_i.BLIF as_000_dma_0_un0_n.BLIF inst_VPA_D.BLIF AS_030_i.BLIF N_193_i.BLIF lds_000_int_0_un3_n.BLIF inst_UDS_000_INT.BLIF \ - AS_030_D0_i.BLIF N_192_0.BLIF lds_000_int_0_un1_n.BLIF inst_LDS_000_INT.BLIF a_i_24__n.BLIF clk_000_n_sync_i_10__n.BLIF lds_000_int_0_un0_n.BLIF inst_CLK_OUT_PRE_D.BLIF sm_amiga_i_3__n.BLIF \ - N_350_i.BLIF rw_000_dma_0_un3_n.BLIF inst_DTACK_D0.BLIF cpu_est_i_0__n.BLIF N_188_0.BLIF rw_000_dma_0_un1_n.BLIF inst_RESET_OUT.BLIF cpu_est_i_3__n.BLIF N_187_i.BLIF \ - rw_000_dma_0_un0_n.BLIF inst_CLK_OUT_PRE_50.BLIF cpu_est_i_2__n.BLIF N_185_i.BLIF a_15__n.BLIF CLK_000_D_1_.BLIF cpu_est_i_1__n.BLIF N_182_i.BLIF CLK_000_D_0_.BLIF \ - VPA_D_i.BLIF N_181_i.BLIF a_14__n.BLIF inst_CLK_000_PE.BLIF CLK_000_NE_i.BLIF CLK_OUT_PRE_D_i.BLIF CLK_000_P_SYNC_9_.BLIF sm_amiga_i_1__n.BLIF N_175_0.BLIF \ - a_13__n.BLIF inst_CLK_000_NE.BLIF rst_dly_i_2__n.BLIF N_168_i.BLIF CLK_000_N_SYNC_11_.BLIF CLK_030_i.BLIF AS_030_000_SYNC_i.BLIF a_12__n.BLIF IPL_D0_0_.BLIF \ - rst_dly_i_0__n.BLIF N_158_i.BLIF IPL_D0_1_.BLIF rst_dly_i_1__n.BLIF clk_000_d_i_0__n.BLIF a_11__n.BLIF IPL_D0_2_.BLIF clk_000_d_i_1__n.BLIF N_148_i.BLIF \ - inst_CLK_000_NE_D0.BLIF DTACK_D0_i.BLIF N_345_i.BLIF a_10__n.BLIF pos_clk_un6_bg_030_n.BLIF RW_000_i.BLIF N_344_i.BLIF SM_AMIGA_0_.BLIF CLK_030_H_i.BLIF \ - N_144_0.BLIF a_9__n.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF sm_amiga_i_6__n.BLIF N_138_0.BLIF inst_DSACK1_INTreg.BLIF sm_amiga_i_2__n.BLIF a_8__n.BLIF AS_000_i.BLIF \ - N_342_i.BLIF pos_clk_ipl_n.BLIF sm_amiga_i_0__n.BLIF N_343_i.BLIF a_7__n.BLIF SM_AMIGA_4_.BLIF A1_i.BLIF N_124_0.BLIF inst_DS_000_ENABLE.BLIF \ - a_i_31__n.BLIF N_341_i.BLIF a_6__n.BLIF RST_DLY_0_.BLIF a_i_29__n.BLIF N_119_0.BLIF RST_DLY_1_.BLIF a_i_30__n.BLIF N_340_i.BLIF \ - a_5__n.BLIF RST_DLY_2_.BLIF a_i_27__n.BLIF N_361_i.BLIF pos_clk_un9_bg_030_n.BLIF a_i_28__n.BLIF cpu_est_2_0_2__n.BLIF a_4__n.BLIF CLK_000_P_SYNC_0_.BLIF \ - a_i_25__n.BLIF N_338_i.BLIF CLK_000_P_SYNC_1_.BLIF a_i_26__n.BLIF N_339_i.BLIF a_3__n.BLIF CLK_000_P_SYNC_2_.BLIF N_213_i.BLIF cpu_est_2_0_1__n.BLIF \ - CLK_000_P_SYNC_3_.BLIF N_214_i.BLIF N_332_i.BLIF a_2__n.BLIF CLK_000_P_SYNC_4_.BLIF N_215_i.BLIF N_336_i.BLIF CLK_000_P_SYNC_5_.BLIF pos_clk_un7_clk_000_pe_0_n.BLIF \ - CLK_000_P_SYNC_6_.BLIF N_275_i.BLIF N_99_0.BLIF CLK_000_P_SYNC_7_.BLIF un6_ds_030_i.BLIF N_331_i.BLIF CLK_000_P_SYNC_8_.BLIF DS_000_DMA_i.BLIF N_96_0.BLIF \ - CLK_000_N_SYNC_0_.BLIF un4_as_000_i.BLIF N_330_i.BLIF CLK_000_N_SYNC_1_.BLIF AS_000_INT_i.BLIF N_90_0.BLIF CLK_000_N_SYNC_2_.BLIF un4_lds_000_i.BLIF N_328_i.BLIF \ - CLK_000_N_SYNC_3_.BLIF un4_uds_000_i.BLIF CLK_000_N_SYNC_4_.BLIF AS_030_c.BLIF N_80_0.BLIF CLK_000_N_SYNC_5_.BLIF N_325_i.BLIF CLK_000_N_SYNC_6_.BLIF AS_000_c.BLIF \ - N_326_i.BLIF CLK_000_N_SYNC_7_.BLIF N_258_0.BLIF CLK_000_N_SYNC_8_.BLIF RW_000_c.BLIF N_217_i.BLIF CLK_000_N_SYNC_9_.BLIF N_321_i.BLIF CLK_000_N_SYNC_10_.BLIF \ - N_322_i.BLIF inst_RW_000_INT.BLIF UDS_000_c.BLIF inst_RW_000_DMA.BLIF N_320_i.BLIF pos_clk_un7_clk_000_pe_n.BLIF LDS_000_c.BLIF inst_A0_DMA.BLIF un5_ciin_i.BLIF \ - pos_clk_a0_dma_3_n.BLIF size_c_0__n.BLIF N_61_0.BLIF SM_AMIGA_6_.BLIF N_310_i.BLIF inst_CLK_030_H.BLIF size_c_1__n.BLIF SM_AMIGA_1_.BLIF N_305_i.BLIF \ - SM_AMIGA_3_.BLIF N_307_i.BLIF SM_AMIGA_2_.BLIF N_3.BLIF N_303_i.BLIF N_8.BLIF N_304_i.BLIF N_283_0.BLIF N_301_i.BLIF \ - N_300_i.BLIF N_123_0.BLIF N_17.BLIF N_278_i.BLIF N_19.BLIF N_297_i.BLIF N_20.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_21.BLIF \ - N_277_i.BLIF N_22.BLIF N_25.BLIF N_26.BLIF pos_clk_un8_sm_amiga_i_n.BLIF N_27.BLIF A0_c_i.BLIF N_28.BLIF size_c_i_1__n.BLIF \ - N_29.BLIF N_29_i.BLIF N_32_0.BLIF N_28_i.BLIF N_31_0.BLIF N_27_i.BLIF N_30_0.BLIF ipl_c_i_2__n.BLIF N_53_0.BLIF \ - ipl_c_i_1__n.BLIF N_52_0.BLIF a_c_16__n.BLIF ipl_c_i_0__n.BLIF N_51_0.BLIF a_c_17__n.BLIF DTACK_c_i.BLIF N_56_0.BLIF a_c_18__n.BLIF \ - VPA_c_i.BLIF N_55_0.BLIF a_c_19__n.BLIF nEXP_SPACE_c_i.BLIF N_54_0.BLIF a_c_20__n.BLIF N_3_i.BLIF N_49_0.BLIF a_c_21__n.BLIF \ - N_8_i.BLIF N_45_0.BLIF a_c_22__n.BLIF N_17_i.BLIF N_42_0.BLIF a_c_23__n.BLIF N_19_i.BLIF N_40_0.BLIF SM_AMIGA_i_7_.BLIF \ - a_c_24__n.BLIF N_20_i.BLIF N_123.BLIF N_39_0.BLIF cpu_est_2_1__n.BLIF a_c_25__n.BLIF N_21_i.BLIF cpu_est_2_2__n.BLIF N_38_0.BLIF \ - N_209.BLIF a_c_26__n.BLIF N_22_i.BLIF G_134.BLIF N_37_0.BLIF G_135.BLIF a_c_27__n.BLIF N_25_i.BLIF G_136.BLIF \ - N_34_0.BLIF N_217.BLIF a_c_28__n.BLIF N_26_i.BLIF N_33_0.BLIF N_61.BLIF a_c_29__n.BLIF BG_030_c_i.BLIF N_127.BLIF \ - pos_clk_un6_bg_030_i_n.BLIF a_c_30__n.BLIF pos_clk_un9_bg_030_0_n.BLIF N_80.BLIF N_289_0_1.BLIF a_c_31__n.BLIF un1_SM_AMIGA_5_i_1.BLIF N_90.BLIF un1_SM_AMIGA_5_i_2.BLIF \ - N_96.BLIF A0_c.BLIF pos_clk_un8_sm_amiga_i_1_n.BLIF N_99.BLIF N_351_1.BLIF N_119.BLIF A1_c.BLIF N_351_2.BLIF N_124.BLIF \ - N_168_i_1.BLIF N_138.BLIF nEXP_SPACE_c.BLIF N_192_0_1.BLIF N_144.BLIF N_192_0_2.BLIF N_158.BLIF BERR_c.BLIF N_137_i_1.BLIF \ - N_168.BLIF N_137_i_2.BLIF N_175.BLIF BG_030_c.BLIF N_145_i_1.BLIF N_182.BLIF N_145_i_2.BLIF N_185.BLIF BG_000DFFreg.BLIF \ - N_145_i_3.BLIF N_187.BLIF N_260_i_1.BLIF N_188.BLIF N_260_i_2.BLIF N_192.BLIF BGACK_000_c.BLIF N_259_i_1.BLIF N_193.BLIF \ - N_259_i_2.BLIF N_197.BLIF CLK_030_c.BLIF N_336_1.BLIF N_201.BLIF N_336_2.BLIF N_204.BLIF N_332_1.BLIF N_206.BLIF \ - N_332_2.BLIF N_207.BLIF CLK_OSZI_c.BLIF N_332_3.BLIF N_317_1.BLIF N_211.BLIF N_317_2.BLIF N_212.BLIF CLK_OUT_INTreg.BLIF \ - N_317_3.BLIF N_290.BLIF N_304_1.BLIF N_216.BLIF N_304_2.BLIF N_219.BLIF FPU_SENSE_c.BLIF un5_ciin_1.BLIF N_220.BLIF \ - un5_ciin_2.BLIF N_221.BLIF IPL_030DFF_0_reg.BLIF un5_ciin_3.BLIF N_227.BLIF un5_ciin_4.BLIF N_229.BLIF IPL_030DFF_1_reg.BLIF un5_ciin_5.BLIF \ - N_230.BLIF un5_ciin_6.BLIF N_236.BLIF IPL_030DFF_2_reg.BLIF un5_ciin_7.BLIF N_240.BLIF un5_ciin_8.BLIF N_241.BLIF ipl_c_0__n.BLIF \ - un5_ciin_9.BLIF N_242.BLIF un5_ciin_10.BLIF N_246.BLIF ipl_c_1__n.BLIF un5_ciin_11.BLIF N_254.BLIF un22_berr_1_0.BLIF N_266.BLIF \ - ipl_c_2__n.BLIF un21_fpu_cs_1.BLIF N_267.BLIF N_375_1.BLIF N_275.BLIF N_375_2.BLIF N_277.BLIF DTACK_c.BLIF N_375_3.BLIF \ - N_278.BLIF N_375_4.BLIF N_297.BLIF N_134_i_1.BLIF N_300.BLIF N_96_0_1.BLIF N_301.BLIF VPA_c.BLIF N_83_i_1.BLIF \ - N_303.BLIF N_261_i_1.BLIF N_304.BLIF N_141_i_1.BLIF N_305.BLIF RST_c.BLIF N_139_i_1.BLIF N_307.BLIF N_133_i_1.BLIF \ - N_310.BLIF N_123_0_1.BLIF N_312.BLIF RW_c.BLIF N_282_i_1.BLIF N_313.BLIF N_343_1.BLIF N_316.BLIF fc_c_0__n.BLIF \ - N_339_1.BLIF N_317.BLIF pos_clk_un6_bg_030_1_n.BLIF N_320.BLIF fc_c_1__n.BLIF N_326_1.BLIF N_321.BLIF N_325_1.BLIF N_322.BLIF \ - N_324_1.BLIF N_323.BLIF AMIGA_BUS_DATA_DIR_c.BLIF N_316_1.BLIF N_324.BLIF N_313_1.BLIF N_325.BLIF N_303_1.BLIF N_326.BLIF \ - N_297_1.BLIF N_328.BLIF N_266_1.BLIF N_330.BLIF N_24_i.BLIF N_240_1.BLIF N_331.BLIF N_35_0.BLIF pos_clk_ipl_1_n.BLIF \ - N_332.BLIF N_18_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF N_336.BLIF N_41_0.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF N_338.BLIF N_10_i.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF \ - N_339.BLIF N_43_0.BLIF rw_000_int_0_un3_n.BLIF N_340.BLIF N_7_i.BLIF rw_000_int_0_un1_n.BLIF N_341.BLIF N_46_0.BLIF rw_000_int_0_un0_n.BLIF \ - N_342.BLIF N_5_i.BLIF bgack_030_int_0_un3_n.BLIF N_343.BLIF N_47_0.BLIF bgack_030_int_0_un1_n.BLIF N_344.BLIF N_4_i.BLIF bgack_030_int_0_un0_n.BLIF \ - N_345.BLIF N_48_0.BLIF as_030_000_sync_0_un3_n.BLIF N_347.BLIF N_272_i.BLIF as_030_000_sync_0_un1_n.BLIF N_350.BLIF N_271_i.BLIF as_030_000_sync_0_un0_n.BLIF \ - N_351.BLIF N_279_0.BLIF ds_000_enable_0_un3_n.BLIF N_353.BLIF N_280_0.BLIF ds_000_enable_0_un1_n.BLIF N_361.BLIF N_281_0.BLIF ds_000_enable_0_un0_n.BLIF \ - pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_298_i.BLIF as_000_int_0_un3_n.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF pos_clk_size_dma_6_0_0__n.BLIF as_000_int_0_un1_n.BLIF cpu_est_0_0_x2_0_.BLIF N_299_i.BLIF as_000_int_0_un0_n.BLIF \ - pos_clk_CYCLE_DMA_5_1_i_x2.BLIF pos_clk_size_dma_6_0_1__n.BLIF dsack1_int_0_un3_n.BLIF un22_berr_1.BLIF un1_as_000_i.BLIF dsack1_int_0_un1_n.BLIF N_375.BLIF N_358_i.BLIF dsack1_int_0_un0_n.BLIF \ - N_218.BLIF pos_clk_un6_bgack_000_0_n.BLIF size_dma_0_1__un3_n.BLIF N_156.BLIF N_284_i.BLIF size_dma_0_1__un1_n.BLIF N_289.BLIF N_285_i.BLIF size_dma_0_1__un0_n.BLIF \ - N_354.BLIF N_286_0.BLIF size_dma_0_0__un3_n.BLIF N_205.BLIF N_88_0.BLIF size_dma_0_0__un1_n.BLIF un1_SM_AMIGA_5.BLIF pos_clk_un3_as_030_d0_i_n.BLIF size_dma_0_0__un0_n.BLIF \ - DS_000_ENABLE_1_sqmuxa.BLIF N_156_i.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF N_349.BLIF N_349_i.BLIF sm_amiga_srsts_i_0_m2_1__un1_n.BLIF pos_clk_un3_as_030_d0_n.BLIF N_194_i.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF \ - N_286.BLIF un1_SM_AMIGA_5_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF pos_clk_un6_bgack_000_n.BLIF UDS_000_c_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF N_358.BLIF LDS_000_c_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF \ - pos_clk_size_dma_6_1__n.BLIF N_205_i.BLIF sm_amiga_srsts_i_0_m2_5__un3_n.BLIF N_299.BLIF N_206_0.BLIF sm_amiga_srsts_i_0_m2_5__un1_n.BLIF pos_clk_size_dma_6_0__n.BLIF N_207_0.BLIF sm_amiga_srsts_i_0_m2_5__un0_n.BLIF \ - N_298.BLIF N_354_i.BLIF cpu_est_0_1__un3_n.BLIF N_281.BLIF N_208_0.BLIF cpu_est_0_1__un1_n.BLIF AS_030.PIN AS_000.PIN RW_000.PIN \ - UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN +.inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF \ + FPU_SENSE.BLIF DTACK.BLIF VPA.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF \ + A_DECODE_17_.BLIF A_DECODE_16_.BLIF A_DECODE_15_.BLIF A_DECODE_14_.BLIF A_DECODE_13_.BLIF A_DECODE_12_.BLIF A_DECODE_11_.BLIF A_DECODE_10_.BLIF A_DECODE_9_.BLIF \ + A_DECODE_8_.BLIF A_DECODE_7_.BLIF A_DECODE_6_.BLIF A_DECODE_5_.BLIF A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ + FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_166.BLIF N_32_0.BLIF cpu_est_0_3__un0_n.BLIF N_141.BLIF a_c_i_0__n.BLIF cpu_est_0_2__un3_n.BLIF N_226.BLIF \ + size_c_i_1__n.BLIF cpu_est_0_2__un1_n.BLIF N_357.BLIF pos_clk_un10_sm_amiga_i_n.BLIF cpu_est_0_2__un0_n.BLIF N_219.BLIF N_258_0.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF N_217.BLIF \ + N_357_i.BLIF sm_amiga_srsts_i_0_m2_1__un1_n.BLIF N_221.BLIF N_254_i.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_220.BLIF cpu_est_2_0_2__n.BLIF vma_int_0_un3_n.BLIF inst_BGACK_030_INTreg.BLIF \ + N_223.BLIF N_315_i.BLIF vma_int_0_un1_n.BLIF vcc_n_n.BLIF N_343.BLIF N_291_0.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.BLIF N_192.BLIF \ + AS_030_000_SYNC_i.BLIF cpu_est_0_1__un3_n.BLIF gnd_n_n.BLIF N_164.BLIF N_146_0.BLIF cpu_est_0_1__un1_n.BLIF un1_amiga_bus_enable_dma_high_0__n.BLIF N_291.BLIF N_149_i.BLIF \ + cpu_est_0_1__un0_n.BLIF un1_amiga_bus_enable_low.BLIF N_315.BLIF N_164_i.BLIF sm_amiga_srsts_i_0_0_m2_5__un3_n.BLIF un6_as_030.BLIF cpu_est_2_2__n.BLIF N_166_i.BLIF sm_amiga_srsts_i_0_0_m2_5__un1_n.BLIF \ + un3_size.BLIF N_254.BLIF N_172_i.BLIF sm_amiga_srsts_i_0_0_m2_5__un0_n.BLIF un4_size.BLIF N_258.BLIF N_176_i.BLIF rw_000_int_0_un3_n.BLIF un4_uds_000.BLIF \ + N_29.BLIF N_186_0.BLIF rw_000_int_0_un1_n.BLIF un4_lds_000.BLIF N_28.BLIF N_192_0.BLIF rw_000_int_0_un0_n.BLIF un4_as_000.BLIF N_27.BLIF \ + N_228_i.BLIF bgack_030_int_0_un3_n.BLIF un10_ciin.BLIF N_4.BLIF N_227_i.BLIF bgack_030_int_0_un1_n.BLIF un21_fpu_cs.BLIF N_17.BLIF N_343_i.BLIF \ + bgack_030_int_0_un0_n.BLIF un22_berr.BLIF N_21.BLIF as_000_int_0_un3_n.BLIF un6_ds_030.BLIF N_26.BLIF N_223_i.BLIF as_000_int_0_un1_n.BLIF cpu_est_2_.BLIF \ + pos_clk_un9_bg_030_n.BLIF N_225_i.BLIF as_000_int_0_un0_n.BLIF cpu_est_3_.BLIF un1_amiga_bus_enable_low_i.BLIF N_224_i.BLIF ds_000_enable_0_un3_n.BLIF cpu_est_0_.BLIF un21_fpu_cs_i.BLIF \ + N_226_i.BLIF ds_000_enable_0_un1_n.BLIF cpu_est_1_.BLIF N_275_i.BLIF ds_000_enable_0_un0_n.BLIF inst_AS_000_INT.BLIF clk_000_n_sync_i_12__n.BLIF N_220_i.BLIF as_030_000_sync_0_un3_n.BLIF \ + inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF rst_dly_i_2__n.BLIF N_221_i.BLIF as_030_000_sync_0_un1_n.BLIF inst_AS_030_D0.BLIF rst_dly_i_1__n.BLIF N_222_i.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF \ + BERR_i.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF inst_BGACK_030_INT_D.BLIF cpu_est_i_2__n.BLIF N_217_i.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF inst_AS_000_DMA.BLIF nEXP_SPACE_i.BLIF N_215_i.BLIF \ + un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF inst_DS_000_DMA.BLIF rst_dly_i_0__n.BLIF N_219_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF CYCLE_DMA_0_.BLIF cpu_est_i_1__n.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF CYCLE_DMA_1_.BLIF \ + cpu_est_i_0__n.BLIF N_200_i.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF SIZE_DMA_0_.BLIF VPA_D_i.BLIF N_195_0.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF SIZE_DMA_1_.BLIF sm_amiga_i_3__n.BLIF \ + N_190_0.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF inst_VPA_D.BLIF sm_amiga_i_0__n.BLIF N_157_i.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF inst_UDS_000_INT.BLIF cpu_est_i_3__n.BLIF N_154_i.BLIF \ + size_dma_0_0__un3_n.BLIF inst_LDS_000_INT.BLIF sm_amiga_i_1__n.BLIF N_340_i.BLIF size_dma_0_0__un1_n.BLIF inst_CLK_OUT_PRE_D.BLIF RESET_OUT_i.BLIF N_141_0.BLIF size_dma_0_0__un0_n.BLIF \ + CLK_000_D_10_.BLIF BGACK_030_INT_i.BLIF un3_as_030_i.BLIF size_dma_0_1__un3_n.BLIF CLK_000_D_11_.BLIF sm_amiga_i_2__n.BLIF N_216_i.BLIF size_dma_0_1__un1_n.BLIF inst_DTACK_D0.BLIF \ + sm_amiga_i_4__n.BLIF N_337_i.BLIF size_dma_0_1__un0_n.BLIF inst_RESET_OUT.BLIF clk_000_p_sync_i_10__n.BLIF ds_000_dma_0_un3_n.BLIF inst_CLK_OUT_PRE_50.BLIF sm_amiga_i_5__n.BLIF un10_ciin_i.BLIF \ + ds_000_dma_0_un1_n.BLIF CLK_000_D_1_.BLIF sm_amiga_i_i_7__n.BLIF N_296_0.BLIF ds_000_dma_0_un0_n.BLIF CLK_000_D_0_.BLIF clk_000_d_i_11__n.BLIF un1_as_000_i.BLIF as_000_dma_0_un3_n.BLIF \ + CLK_000_P_SYNC_10_.BLIF sm_amiga_i_6__n.BLIF N_284_i.BLIF as_000_dma_0_un1_n.BLIF SM_AMIGA_5_.BLIF RW_i.BLIF N_285_i.BLIF as_000_dma_0_un0_n.BLIF IPL_D0_0_.BLIF \ + DS_000_ENABLE_1_sqmuxa_i.BLIF N_292_0.BLIF rw_000_dma_0_un3_n.BLIF IPL_D0_1_.BLIF LDS_000_INT_i.BLIF N_280_i.BLIF rw_000_dma_0_un1_n.BLIF IPL_D0_2_.BLIF UDS_000_INT_i.BLIF \ + N_277_i.BLIF rw_000_dma_0_un0_n.BLIF CLK_000_D_2_.BLIF AS_030_i.BLIF N_257_0.BLIF a0_dma_0_un3_n.BLIF CLK_000_D_3_.BLIF AS_000_INT_i.BLIF N_235_i.BLIF \ + a0_dma_0_un1_n.BLIF CLK_000_D_4_.BLIF a_decode_i_19__n.BLIF N_236_i.BLIF a0_dma_0_un0_n.BLIF CLK_000_D_5_.BLIF a_decode_i_18__n.BLIF cpu_est_2_0_1__n.BLIF a_decode_15__n.BLIF \ + CLK_000_D_6_.BLIF a_decode_i_16__n.BLIF N_231_i.BLIF CLK_000_D_7_.BLIF AS_000_i.BLIF N_230_i.BLIF a_decode_14__n.BLIF CLK_000_D_8_.BLIF FPU_SENSE_i.BLIF \ + pos_clk_un4_clk_000_pe_0_n.BLIF CLK_000_D_9_.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_22_i.BLIF a_decode_13__n.BLIF CLK_000_D_12_.BLIF CLK_030_i.BLIF N_37_0.BLIF pos_clk_un6_bg_030_n.BLIF \ + DTACK_D0_i.BLIF a_decode_12__n.BLIF SM_AMIGA_0_.BLIF clk_000_d_i_10__n.BLIF N_334_i.BLIF inst_DSACK1_INTreg.BLIF RW_000_i.BLIF N_335_i.BLIF a_decode_11__n.BLIF \ + a_i_1__n.BLIF N_194_0.BLIF CLK_030_H_i.BLIF N_191_0.BLIF a_decode_10__n.BLIF pos_clk_ipl_n.BLIF AS_000_DMA_i.BLIF un1_SM_AMIGA_5_i.BLIF CLK_000_N_SYNC_0_.BLIF \ + clk_000_d_i_0__n.BLIF N_346_i.BLIF a_decode_9__n.BLIF SM_AMIGA_4_.BLIF clk_000_d_i_1__n.BLIF N_163_i.BLIF inst_DS_000_ENABLE.BLIF AS_030_D0_i.BLIF N_345_i.BLIF \ + a_decode_8__n.BLIF CLK_000_N_SYNC_12_.BLIF size_dma_i_0__n.BLIF N_344_i.BLIF RST_DLY_0_.BLIF size_dma_i_1__n.BLIF N_153_0.BLIF a_decode_7__n.BLIF RST_DLY_1_.BLIF \ + ahigh_i_30__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF RST_DLY_2_.BLIF ahigh_i_31__n.BLIF N_293_0.BLIF a_decode_6__n.BLIF CLK_000_P_SYNC_0_.BLIF ahigh_i_28__n.BLIF N_233_i.BLIF \ + CLK_000_P_SYNC_1_.BLIF ahigh_i_29__n.BLIF N_232_i.BLIF a_decode_5__n.BLIF CLK_000_P_SYNC_2_.BLIF ahigh_i_26__n.BLIF N_290_0.BLIF CLK_000_P_SYNC_3_.BLIF ahigh_i_27__n.BLIF \ + VPA_c_i.BLIF a_decode_4__n.BLIF CLK_000_P_SYNC_4_.BLIF ahigh_i_24__n.BLIF N_54_0.BLIF CLK_000_P_SYNC_5_.BLIF ahigh_i_25__n.BLIF N_5_i.BLIF a_decode_3__n.BLIF \ + CLK_000_P_SYNC_6_.BLIF N_212_i.BLIF N_47_0.BLIF CLK_000_P_SYNC_7_.BLIF N_213_i.BLIF N_7_i.BLIF a_decode_2__n.BLIF CLK_000_P_SYNC_8_.BLIF N_214_i.BLIF \ + N_46_0.BLIF CLK_000_P_SYNC_9_.BLIF N_18_i.BLIF CLK_000_N_SYNC_1_.BLIF N_41_0.BLIF CLK_000_N_SYNC_2_.BLIF N_321_i.BLIF N_10_i.BLIF CLK_000_N_SYNC_3_.BLIF \ + N_322_i.BLIF N_43_0.BLIF CLK_000_N_SYNC_4_.BLIF un6_ds_030_i.BLIF DTACK_c_i.BLIF CLK_000_N_SYNC_5_.BLIF DS_000_DMA_i.BLIF N_55_0.BLIF CLK_000_N_SYNC_6_.BLIF \ + un4_as_000_i.BLIF pos_clk_un6_bgack_000_0_n.BLIF CLK_000_N_SYNC_7_.BLIF un6_as_030_i.BLIF N_137_i.BLIF CLK_000_N_SYNC_8_.BLIF un4_lds_000_i.BLIF N_184_0.BLIF CLK_000_N_SYNC_9_.BLIF \ + un4_uds_000_i.BLIF N_349_i.BLIF CLK_000_N_SYNC_10_.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_185_i.BLIF CLK_000_N_SYNC_11_.BLIF AS_030_c.BLIF N_187_0.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ + N_203_i.BLIF inst_RW_000_INT.BLIF AS_000_c.BLIF N_324_i.BLIF inst_RW_000_DMA.BLIF inst_CLK_000_NE_D0.BLIF RW_000_c.BLIF N_199_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ + N_197_0.BLIF inst_A0_DMA.BLIF N_196_0.BLIF pos_clk_a0_dma_3_n.BLIF UDS_000_c.BLIF LDS_000_c_i.BLIF SM_AMIGA_6_.BLIF UDS_000_c_i.BLIF inst_CLK_030_H.BLIF \ + LDS_000_c.BLIF N_181_i.BLIF SM_AMIGA_1_.BLIF N_347_i.BLIF SM_AMIGA_3_.BLIF size_c_0__n.BLIF N_348_i.BLIF SM_AMIGA_2_.BLIF N_178_i.BLIF \ + pos_clk_ds_000_dma_4_n.BLIF size_c_1__n.BLIF VMA_INT_i.BLIF N_3.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_8.BLIF ahigh_c_24__n.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF CLK_OUT_PRE_D_i.BLIF \ + ahigh_c_25__n.BLIF N_148_0.BLIF N_341_i.BLIF ahigh_c_26__n.BLIF N_338_i.BLIF N_339_i.BLIF N_19.BLIF ahigh_c_27__n.BLIF N_20.BLIF \ + N_336_i.BLIF N_24.BLIF ahigh_c_28__n.BLIF N_122_0.BLIF N_25.BLIF N_211_i.BLIF ahigh_c_29__n.BLIF N_332_i.BLIF ahigh_c_30__n.BLIF \ + N_331_i.BLIF N_120_0.BLIF ahigh_c_31__n.BLIF N_330_i.BLIF pos_clk_ds_000_dma_4_0_n.BLIF N_329_i.BLIF pos_clk_size_dma_6_0_1__n.BLIF N_328_i.BLIF pos_clk_size_dma_6_0_0__n.BLIF \ + N_325_i.BLIF N_327_i.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_320_i.BLIF N_298_0.BLIF N_295_0.BLIF N_294_0.BLIF N_319_i.BLIF un1_amiga_bus_enable_dma_high_0_0__n.BLIF \ + N_206_i.BLIF N_283_i.BLIF SM_AMIGA_i_7_.BLIF N_122.BLIF N_281_i.BLIF pos_clk_size_dma_6_0__n.BLIF N_282_i.BLIF pos_clk_size_dma_6_1__n.BLIF G_134.BLIF \ + N_3_i.BLIF G_135.BLIF N_49_0.BLIF G_136.BLIF N_8_i.BLIF N_45_0.BLIF pos_clk_un23_bgack_030_int_i_1_n.BLIF N_19_i.BLIF N_292.BLIF \ + N_40_0.BLIF N_294.BLIF a_decode_c_16__n.BLIF N_20_i.BLIF N_295.BLIF N_39_0.BLIF N_296.BLIF a_decode_c_17__n.BLIF N_24_i.BLIF \ + N_298.BLIF N_35_0.BLIF N_120.BLIF a_decode_c_18__n.BLIF N_25_i.BLIF N_148.BLIF N_34_0.BLIF N_149.BLIF a_decode_c_19__n.BLIF \ + N_194_0_1.BLIF N_157.BLIF N_237_i_1.BLIF N_172.BLIF a_decode_c_20__n.BLIF N_237_i_2.BLIF N_176.BLIF N_238_i_1.BLIF N_178.BLIF \ + a_decode_c_21__n.BLIF N_238_i_2.BLIF N_181.BLIF N_144_i_1.BLIF N_184.BLIF a_decode_c_22__n.BLIF N_144_i_2.BLIF N_144_i_3.BLIF N_196.BLIF \ + a_decode_c_23__n.BLIF N_136_i_1.BLIF N_197.BLIF N_136_i_2.BLIF N_206.BLIF a_c_0__n.BLIF N_176_i_1.BLIF N_207.BLIF N_146_0_1.BLIF \ + N_211.BLIF a_c_1__n.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF N_215.BLIF un10_ciin_1.BLIF N_222.BLIF nEXP_SPACE_c.BLIF un10_ciin_2.BLIF N_224.BLIF \ + un10_ciin_3.BLIF N_225.BLIF BERR_c.BLIF un10_ciin_4.BLIF N_227.BLIF un10_ciin_5.BLIF N_228.BLIF BG_030_c.BLIF un10_ciin_6.BLIF \ + N_236.BLIF un10_ciin_7.BLIF N_277.BLIF BG_000DFFreg.BLIF un10_ciin_8.BLIF N_281.BLIF un10_ciin_9.BLIF N_282.BLIF un10_ciin_10.BLIF \ + N_283.BLIF BGACK_000_c.BLIF un10_ciin_11.BLIF N_285.BLIF N_347_1.BLIF N_318.BLIF CLK_030_c.BLIF N_347_2.BLIF N_319.BLIF \ + pos_clk_un23_bgack_030_int_i_1_0_1_n.BLIF N_320.BLIF CLK_000_c.BLIF pos_clk_un23_bgack_030_int_i_1_0_2_n.BLIF N_321.BLIF un21_fpu_cs_1.BLIF N_322.BLIF CLK_OSZI_c.BLIF un22_berr_1_0.BLIF \ + N_323.BLIF N_366_1.BLIF N_325.BLIF N_366_2.BLIF N_327.BLIF CLK_OUT_INTreg.BLIF N_366_3.BLIF N_328.BLIF N_366_4.BLIF \ + N_329.BLIF un1_SM_AMIGA_5_i_1.BLIF N_330.BLIF FPU_SENSE_c.BLIF un1_SM_AMIGA_5_i_2.BLIF N_331.BLIF N_142_i_1.BLIF N_332.BLIF IPL_030DFF_0_reg.BLIF \ + N_142_i_2.BLIF N_336.BLIF N_339_1.BLIF N_338.BLIF IPL_030DFF_1_reg.BLIF N_280_1.BLIF N_339.BLIF N_280_2.BLIF N_341.BLIF \ + IPL_030DFF_2_reg.BLIF N_231_1.BLIF N_344.BLIF N_231_2.BLIF N_347.BLIF ipl_c_0__n.BLIF N_230_1.BLIF N_348.BLIF N_230_2.BLIF \ + pos_clk_un23_bgack_030_int_i_0_x2.BLIF ipl_c_1__n.BLIF N_230_3.BLIF cpu_est_0_0_x2_0_x2_0_.BLIF N_226_1.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF ipl_c_2__n.BLIF N_226_2.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF \ + N_226_3.BLIF N_199.BLIF N_239_i_1.BLIF N_324.BLIF DTACK_c.BLIF N_122_0_1.BLIF un22_berr_1.BLIF N_132_i_1.BLIF N_366.BLIF \ + N_120_0_1.BLIF N_335.BLIF N_106_i_1.BLIF N_208.BLIF VPA_c.BLIF N_103_i_1.BLIF N_203.BLIF N_92_i_1.BLIF N_187.BLIF \ + N_140_i_1.BLIF N_137.BLIF RST_c.BLIF N_138_i_1.BLIF N_349.BLIF N_344_1.BLIF pos_clk_un6_bgack_000_n.BLIF pos_clk_un6_bg_030_1_n.BLIF N_10.BLIF \ + RW_c.BLIF N_327_1.BLIF N_5.BLIF N_319_1.BLIF N_293.BLIF fc_c_0__n.BLIF N_285_1.BLIF N_6.BLIF N_277_1.BLIF \ + un1_SM_AMIGA_5.BLIF fc_c_1__n.BLIF N_236_1.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF N_228_1.BLIF N_7.BLIF N_225_1.BLIF pos_clk_un3_as_030_d0_n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ + N_224_1.BLIF N_290.BLIF N_222_1.BLIF N_18.BLIF N_215_1.BLIF DS_000_ENABLE_1_sqmuxa.BLIF pos_clk_ipl_1_n.BLIF N_232.BLIF bg_000_0_un3_n.BLIF \ + N_194.BLIF BG_030_c_i.BLIF bg_000_0_un1_n.BLIF N_233.BLIF pos_clk_un6_bg_030_i_n.BLIF bg_000_0_un0_n.BLIF N_275.BLIF pos_clk_un9_bg_030_0_n.BLIF uds_000_int_0_un3_n.BLIF \ + N_153.BLIF N_26_i.BLIF uds_000_int_0_un1_n.BLIF N_191.BLIF N_33_0.BLIF uds_000_int_0_un0_n.BLIF N_334.BLIF N_21_i.BLIF lds_000_int_0_un3_n.BLIF \ + N_146.BLIF N_38_0.BLIF lds_000_int_0_un1_n.BLIF N_345.BLIF N_17_i.BLIF lds_000_int_0_un0_n.BLIF N_346.BLIF N_42_0.BLIF dsack1_int_0_un3_n.BLIF \ + N_163.BLIF N_4_i.BLIF dsack1_int_0_un1_n.BLIF N_22.BLIF N_48_0.BLIF dsack1_int_0_un0_n.BLIF pos_clk_un4_clk_000_pe_n.BLIF ipl_c_i_0__n.BLIF ipl_030_0_2__un3_n.BLIF \ + cpu_est_2_1__n.BLIF N_51_0.BLIF ipl_030_0_2__un1_n.BLIF N_235.BLIF ipl_c_i_1__n.BLIF ipl_030_0_2__un0_n.BLIF N_284.BLIF N_52_0.BLIF ipl_030_0_1__un3_n.BLIF \ + N_190.BLIF ipl_c_i_2__n.BLIF ipl_030_0_1__un1_n.BLIF N_337.BLIF N_53_0.BLIF ipl_030_0_1__un0_n.BLIF N_195.BLIF N_27_i.BLIF ipl_030_0_0__un3_n.BLIF \ + N_340.BLIF N_30_0.BLIF ipl_030_0_0__un1_n.BLIF N_231.BLIF N_28_i.BLIF ipl_030_0_0__un0_n.BLIF N_230.BLIF N_31_0.BLIF cpu_est_0_3__un3_n.BLIF \ + N_280.BLIF N_29_i.BLIF cpu_est_0_3__un1_n.BLIF AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN \ + SIZE_1_.PIN AHIGH_24_.PIN AHIGH_25_.PIN AHIGH_26_.PIN AHIGH_27_.PIN AHIGH_28_.PIN AHIGH_29_.PIN AHIGH_30_.PIN AHIGH_31_.PIN \ + A_0_.PIN BERR.PIN RW.PIN .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E VMA \ - RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D \ - SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C \ - IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D \ - SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C \ - SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D \ - cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C \ - CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D \ - CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C RST_DLY_1_.D RST_DLY_1_.C \ - RST_DLY_2_.D RST_DLY_2_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \ - CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ - inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D \ - inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C \ - inst_VMA_INTreg.D inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D \ - inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ - inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C pos_clk_CYCLE_DMA_5_0_i_x2.X1 \ - pos_clk_CYCLE_DMA_5_0_i_x2.X2 cpu_est_0_0_x2_0_.X1 cpu_est_0_0_x2_0_.X2 pos_clk_CYCLE_DMA_5_1_i_x2.X1 pos_clk_CYCLE_DMA_5_1_i_x2.X2 pos_clk_un23_bgack_030_int_i_i_a4_i_x2.X1 pos_clk_un23_bgack_030_int_i_i_a4_i_x2.X2 G_134.X1 G_134.X2 G_135.X1 G_135.X2 \ - G_136.X1 G_136.X2 SIZE_1_ AS_030 AS_000 RW_000 UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_280 N_210_0 cpu_est_0_1__un0_n N_279 N_289_0 cpu_est_0_2__un3_n N_271 N_218_0 cpu_est_0_2__un1_n \ - N_272 cpu_est_0_2__un0_n N_276 N_242_i cpu_est_0_3__un3_n DS_000_ENABLE_1_sqmuxa_1 N_246_i cpu_est_0_3__un1_n N_4 N_240_i cpu_est_0_3__un0_n \ - vcc_n_n N_5 N_241_i ipl_030_0_0__un3_n N_7 ipl_030_0_0__un1_n gnd_n_n N_10 N_266_i ipl_030_0_0__un0_n un1_amiga_bus_enable_low \ - N_18 N_267_i ipl_030_0_1__un3_n un3_size N_24 N_254_i ipl_030_0_1__un1_n un4_size N_6 N_317_i ipl_030_0_1__un0_n \ - un4_uds_000 un1_amiga_bus_enable_low_i ipl_030_0_2__un3_n un4_lds_000 un21_fpu_cs_i N_313_i ipl_030_0_2__un1_n un5_ciin BGACK_030_INT_i N_316_i ipl_030_0_2__un0_n \ - un4_as_000 AMIGA_BUS_ENABLE_DMA_LOW_i N_312_i a0_dma_0_un3_n un21_fpu_cs UDS_000_INT_i a0_dma_0_un1_n un22_berr LDS_000_INT_i N_347_i a0_dma_0_un0_n \ - un6_ds_030 N_236_i N_323_i uds_000_int_0_un3_n sm_amiga_i_5__n N_324_i uds_000_int_0_un1_n DS_000_ENABLE_1_sqmuxa_i N_222_i uds_000_int_0_un0_n N_276_i \ - AS_000_DMA_i vma_int_0_un3_n RST_i N_221_0 vma_int_0_un1_n a_i_19__n N_220_0 vma_int_0_un0_n a_i_18__n N_219_0 amiga_bus_enable_dma_high_0_un3_n \ - size_dma_i_1__n N_216_0 amiga_bus_enable_dma_high_0_un1_n size_dma_i_0__n N_290_0 amiga_bus_enable_dma_high_0_un0_n RW_i N_212_0 bg_000_0_un3_n CLK_000_PE_i N_211_0 \ - bg_000_0_un1_n a_i_16__n N_204_0 bg_000_0_un0_n RESET_OUT_i N_351_i ds_000_dma_0_un3_n BERR_i N_353_i ds_000_dma_0_un1_n sm_amiga_i_i_7__n \ - N_201_i ds_000_dma_0_un0_n nEXP_SPACE_D0_i VMA_INT_i as_000_dma_0_un3_n sm_amiga_i_4__n N_197_i as_000_dma_0_un1_n FPU_SENSE_i N_196_i as_000_dma_0_un0_n \ - AS_030_i N_193_i lds_000_int_0_un3_n AS_030_D0_i N_192_0 lds_000_int_0_un1_n a_i_24__n clk_000_n_sync_i_10__n lds_000_int_0_un0_n sm_amiga_i_3__n N_350_i \ - rw_000_dma_0_un3_n cpu_est_i_0__n N_188_0 rw_000_dma_0_un1_n cpu_est_i_3__n N_187_i rw_000_dma_0_un0_n cpu_est_i_2__n N_185_i a_15__n cpu_est_i_1__n \ - N_182_i VPA_D_i N_181_i a_14__n CLK_000_NE_i CLK_OUT_PRE_D_i sm_amiga_i_1__n N_175_0 a_13__n rst_dly_i_2__n N_168_i \ - CLK_030_i AS_030_000_SYNC_i a_12__n rst_dly_i_0__n N_158_i rst_dly_i_1__n clk_000_d_i_0__n a_11__n clk_000_d_i_1__n N_148_i DTACK_D0_i \ - N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i CLK_030_H_i N_144_0 a_9__n sm_amiga_i_6__n N_138_0 sm_amiga_i_2__n \ - a_8__n AS_000_i N_342_i pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n A1_i N_124_0 a_i_31__n N_341_i \ - a_6__n a_i_29__n N_119_0 a_i_30__n N_340_i a_5__n a_i_27__n N_361_i pos_clk_un9_bg_030_n a_i_28__n cpu_est_2_0_2__n \ - a_4__n a_i_25__n N_338_i a_i_26__n N_339_i a_3__n N_213_i cpu_est_2_0_1__n N_214_i N_332_i a_2__n \ - N_215_i N_336_i pos_clk_un7_clk_000_pe_0_n N_275_i N_99_0 un6_ds_030_i N_331_i DS_000_DMA_i N_96_0 un4_as_000_i N_330_i \ - AS_000_INT_i N_90_0 un4_lds_000_i N_328_i un4_uds_000_i AS_030_c N_80_0 N_325_i AS_000_c N_326_i N_258_0 \ - RW_000_c N_217_i N_321_i N_322_i UDS_000_c N_320_i pos_clk_un7_clk_000_pe_n LDS_000_c un5_ciin_i pos_clk_a0_dma_3_n size_c_0__n \ - N_61_0 N_310_i size_c_1__n N_305_i N_307_i N_3 N_303_i N_8 N_304_i N_283_0 N_301_i \ - N_300_i N_123_0 N_17 N_278_i N_19 N_297_i N_20 AMIGA_BUS_DATA_DIR_c_0 N_21 N_277_i N_22 \ - N_25 N_26 pos_clk_un8_sm_amiga_i_n N_27 A0_c_i N_28 size_c_i_1__n N_29 N_29_i N_32_0 N_28_i \ - N_31_0 N_27_i N_30_0 ipl_c_i_2__n N_53_0 ipl_c_i_1__n N_52_0 a_c_16__n ipl_c_i_0__n N_51_0 a_c_17__n \ - DTACK_c_i N_56_0 a_c_18__n VPA_c_i N_55_0 a_c_19__n nEXP_SPACE_c_i N_54_0 a_c_20__n N_3_i N_49_0 \ - a_c_21__n N_8_i N_45_0 a_c_22__n N_17_i N_42_0 a_c_23__n N_19_i N_40_0 a_c_24__n N_20_i \ - N_123 N_39_0 cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i N_37_0 \ - a_c_27__n N_25_i N_34_0 N_217 a_c_28__n N_26_i N_33_0 N_61 a_c_29__n BG_030_c_i N_127 \ - pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \ - pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c N_351_2 N_124 N_168_i_1 N_138 nEXP_SPACE_c N_192_0_1 \ - N_144 N_192_0_2 N_158 BERR_c N_137_i_1 N_168 N_137_i_2 N_175 BG_030_c N_145_i_1 N_182 \ - N_145_i_2 N_185 N_145_i_3 N_187 N_260_i_1 N_188 N_260_i_2 N_192 BGACK_000_c N_259_i_1 N_193 \ - N_259_i_2 N_197 CLK_030_c N_336_1 N_201 N_336_2 N_204 N_332_1 N_206 N_332_2 N_207 \ - CLK_OSZI_c N_332_3 N_317_1 N_211 N_317_2 N_212 N_317_3 N_290 N_304_1 N_216 N_304_2 \ - N_219 FPU_SENSE_c un5_ciin_1 N_220 un5_ciin_2 N_221 un5_ciin_3 N_227 un5_ciin_4 N_229 un5_ciin_5 \ - N_230 un5_ciin_6 N_236 un5_ciin_7 N_240 un5_ciin_8 N_241 ipl_c_0__n un5_ciin_9 N_242 un5_ciin_10 \ - N_246 ipl_c_1__n un5_ciin_11 N_254 un22_berr_1_0 N_266 ipl_c_2__n un21_fpu_cs_1 N_267 N_375_1 N_275 \ - N_375_2 N_277 DTACK_c N_375_3 N_278 N_375_4 N_297 N_134_i_1 N_300 N_96_0_1 N_301 \ - VPA_c N_83_i_1 N_303 N_261_i_1 N_304 N_141_i_1 N_305 RST_c N_139_i_1 N_307 N_133_i_1 \ - N_310 N_123_0_1 N_312 RW_c N_282_i_1 N_313 N_343_1 N_316 fc_c_0__n N_339_1 N_317 \ - pos_clk_un6_bg_030_1_n N_320 fc_c_1__n N_326_1 N_321 N_325_1 N_322 N_324_1 N_323 AMIGA_BUS_DATA_DIR_c N_316_1 \ - N_324 N_313_1 N_325 N_303_1 N_326 N_297_1 N_328 N_266_1 N_330 N_24_i N_240_1 \ - N_331 N_35_0 pos_clk_ipl_1_n N_332 N_18_i amiga_bus_enable_dma_low_0_un3_n N_336 N_41_0 amiga_bus_enable_dma_low_0_un1_n N_338 N_10_i \ - amiga_bus_enable_dma_low_0_un0_n N_339 N_43_0 rw_000_int_0_un3_n N_340 N_7_i rw_000_int_0_un1_n N_341 N_46_0 rw_000_int_0_un0_n N_342 \ - N_5_i bgack_030_int_0_un3_n N_343 N_47_0 bgack_030_int_0_un1_n N_344 N_4_i bgack_030_int_0_un0_n N_345 N_48_0 as_030_000_sync_0_un3_n \ - N_347 N_272_i as_030_000_sync_0_un1_n N_350 N_271_i as_030_000_sync_0_un0_n N_351 N_279_0 ds_000_enable_0_un3_n N_353 N_280_0 \ - ds_000_enable_0_un1_n N_361 N_281_0 ds_000_enable_0_un0_n N_298_i as_000_int_0_un3_n pos_clk_size_dma_6_0_0__n as_000_int_0_un1_n N_299_i as_000_int_0_un0_n pos_clk_size_dma_6_0_1__n \ - dsack1_int_0_un3_n un22_berr_1 un1_as_000_i dsack1_int_0_un1_n N_375 N_358_i dsack1_int_0_un0_n N_218 pos_clk_un6_bgack_000_0_n size_dma_0_1__un3_n N_156 \ - N_284_i size_dma_0_1__un1_n N_289 N_285_i size_dma_0_1__un0_n N_354 N_286_0 size_dma_0_0__un3_n N_205 N_88_0 size_dma_0_0__un1_n \ - un1_SM_AMIGA_5 pos_clk_un3_as_030_d0_i_n size_dma_0_0__un0_n DS_000_ENABLE_1_sqmuxa N_156_i sm_amiga_srsts_i_0_m2_1__un3_n N_349 N_349_i sm_amiga_srsts_i_0_m2_1__un1_n pos_clk_un3_as_030_d0_n N_194_i \ - sm_amiga_srsts_i_0_m2_1__un0_n N_286 un1_SM_AMIGA_5_i un1_amiga_bus_enable_dma_high_i_m2_0__un3_n pos_clk_un6_bgack_000_n UDS_000_c_i un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_358 LDS_000_c_i un1_amiga_bus_enable_dma_high_i_m2_0__un0_n pos_clk_size_dma_6_1__n \ - N_205_i sm_amiga_srsts_i_0_m2_5__un3_n N_299 N_206_0 sm_amiga_srsts_i_0_m2_5__un1_n pos_clk_size_dma_6_0__n N_207_0 sm_amiga_srsts_i_0_m2_5__un0_n N_298 N_354_i cpu_est_0_1__un3_n \ - N_281 N_208_0 cpu_est_0_1__un1_n AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ - SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE -.names N_138.BLIF AS_030 + RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D \ + SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \ + SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ + IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \ + CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C CYCLE_DMA_0_.D \ + CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ + CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D \ + CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_10_.D CLK_000_P_SYNC_10_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C \ + CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D \ + CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C \ + CLK_000_D_7_.D CLK_000_D_7_.C CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_10_.D CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C CLK_000_D_12_.D \ + CLK_000_D_12_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ + inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_VMA_INTreg.D inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D \ + inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C \ + inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_VPA_D.D \ + inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ + inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C G_136.X1 G_136.X2 G_135.X1 \ + G_135.X2 G_134.X1 G_134.X2 cpu_est_0_0_x2_0_x2_0_.X1 cpu_est_0_0_x2_0_x2_0_.X2 pos_clk_CYCLE_DMA_5_1_i_x2.X1 pos_clk_CYCLE_DMA_5_1_i_x2.X2 pos_clk_CYCLE_DMA_5_0_i_x2.X1 pos_clk_CYCLE_DMA_5_0_i_x2.X2 pos_clk_un23_bgack_030_int_i_0_x2.X1 pos_clk_un23_bgack_030_int_i_0_x2.X2 \ + SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ A_0_ N_166 N_32_0 cpu_est_0_3__un0_n N_141 a_c_i_0__n cpu_est_0_2__un3_n N_226 size_c_i_1__n cpu_est_0_2__un1_n N_357 pos_clk_un10_sm_amiga_i_n \ + cpu_est_0_2__un0_n N_219 N_258_0 sm_amiga_srsts_i_0_m2_1__un3_n N_217 N_357_i sm_amiga_srsts_i_0_m2_1__un1_n N_221 N_254_i sm_amiga_srsts_i_0_m2_1__un0_n N_220 \ + cpu_est_2_0_2__n vma_int_0_un3_n N_223 N_315_i vma_int_0_un1_n vcc_n_n N_343 N_291_0 vma_int_0_un0_n N_192 AS_030_000_SYNC_i \ + cpu_est_0_1__un3_n gnd_n_n N_164 N_146_0 cpu_est_0_1__un1_n un1_amiga_bus_enable_dma_high_0__n N_291 N_149_i cpu_est_0_1__un0_n un1_amiga_bus_enable_low N_315 \ + N_164_i sm_amiga_srsts_i_0_0_m2_5__un3_n un6_as_030 cpu_est_2_2__n N_166_i sm_amiga_srsts_i_0_0_m2_5__un1_n un3_size N_254 N_172_i sm_amiga_srsts_i_0_0_m2_5__un0_n un4_size \ + N_258 N_176_i rw_000_int_0_un3_n un4_uds_000 N_29 N_186_0 rw_000_int_0_un1_n un4_lds_000 N_28 N_192_0 rw_000_int_0_un0_n \ + un4_as_000 N_27 N_228_i bgack_030_int_0_un3_n un10_ciin N_4 N_227_i bgack_030_int_0_un1_n un21_fpu_cs N_17 N_343_i \ + bgack_030_int_0_un0_n un22_berr N_21 as_000_int_0_un3_n un6_ds_030 N_26 N_223_i as_000_int_0_un1_n pos_clk_un9_bg_030_n N_225_i as_000_int_0_un0_n \ + un1_amiga_bus_enable_low_i N_224_i ds_000_enable_0_un3_n un21_fpu_cs_i N_226_i ds_000_enable_0_un1_n N_275_i ds_000_enable_0_un0_n clk_000_n_sync_i_12__n N_220_i as_030_000_sync_0_un3_n \ + rst_dly_i_2__n N_221_i as_030_000_sync_0_un1_n rst_dly_i_1__n N_222_i as_030_000_sync_0_un0_n BERR_i un1_amiga_bus_enable_dma_high_0_m2_0__un3_n cpu_est_i_2__n N_217_i un1_amiga_bus_enable_dma_high_0_m2_0__un1_n \ + nEXP_SPACE_i N_215_i un1_amiga_bus_enable_dma_high_0_m2_0__un0_n rst_dly_i_0__n N_219_i amiga_bus_enable_dma_low_0_un3_n cpu_est_i_1__n amiga_bus_enable_dma_low_0_un1_n cpu_est_i_0__n N_200_i amiga_bus_enable_dma_low_0_un0_n \ + VPA_D_i N_195_0 amiga_bus_enable_dma_high_0_un3_n sm_amiga_i_3__n N_190_0 amiga_bus_enable_dma_high_0_un1_n sm_amiga_i_0__n N_157_i amiga_bus_enable_dma_high_0_un0_n cpu_est_i_3__n N_154_i \ + size_dma_0_0__un3_n sm_amiga_i_1__n N_340_i size_dma_0_0__un1_n RESET_OUT_i N_141_0 size_dma_0_0__un0_n BGACK_030_INT_i un3_as_030_i size_dma_0_1__un3_n sm_amiga_i_2__n \ + N_216_i size_dma_0_1__un1_n sm_amiga_i_4__n N_337_i size_dma_0_1__un0_n clk_000_p_sync_i_10__n ds_000_dma_0_un3_n sm_amiga_i_5__n un10_ciin_i ds_000_dma_0_un1_n sm_amiga_i_i_7__n \ + N_296_0 ds_000_dma_0_un0_n clk_000_d_i_11__n un1_as_000_i as_000_dma_0_un3_n sm_amiga_i_6__n N_284_i as_000_dma_0_un1_n RW_i N_285_i as_000_dma_0_un0_n \ + DS_000_ENABLE_1_sqmuxa_i N_292_0 rw_000_dma_0_un3_n LDS_000_INT_i N_280_i rw_000_dma_0_un1_n UDS_000_INT_i N_277_i rw_000_dma_0_un0_n AS_030_i N_257_0 \ + a0_dma_0_un3_n AS_000_INT_i N_235_i a0_dma_0_un1_n a_decode_i_19__n N_236_i a0_dma_0_un0_n a_decode_i_18__n cpu_est_2_0_1__n a_decode_15__n a_decode_i_16__n \ + N_231_i AS_000_i N_230_i a_decode_14__n FPU_SENSE_i pos_clk_un4_clk_000_pe_0_n AMIGA_BUS_ENABLE_DMA_HIGH_i N_22_i a_decode_13__n CLK_030_i N_37_0 \ + pos_clk_un6_bg_030_n DTACK_D0_i a_decode_12__n clk_000_d_i_10__n N_334_i RW_000_i N_335_i a_decode_11__n a_i_1__n N_194_0 CLK_030_H_i \ + N_191_0 a_decode_10__n pos_clk_ipl_n AS_000_DMA_i un1_SM_AMIGA_5_i clk_000_d_i_0__n N_346_i a_decode_9__n clk_000_d_i_1__n N_163_i AS_030_D0_i \ + N_345_i a_decode_8__n size_dma_i_0__n N_344_i size_dma_i_1__n N_153_0 a_decode_7__n ahigh_i_30__n pos_clk_un3_as_030_d0_i_n ahigh_i_31__n N_293_0 \ + a_decode_6__n ahigh_i_28__n N_233_i ahigh_i_29__n N_232_i a_decode_5__n ahigh_i_26__n N_290_0 ahigh_i_27__n VPA_c_i a_decode_4__n \ + ahigh_i_24__n N_54_0 ahigh_i_25__n N_5_i a_decode_3__n N_212_i N_47_0 N_213_i N_7_i a_decode_2__n N_214_i \ + N_46_0 N_18_i N_41_0 N_321_i N_10_i N_322_i N_43_0 un6_ds_030_i DTACK_c_i DS_000_DMA_i N_55_0 \ + un4_as_000_i pos_clk_un6_bgack_000_0_n un6_as_030_i N_137_i un4_lds_000_i N_184_0 un4_uds_000_i N_349_i AMIGA_BUS_ENABLE_DMA_LOW_i N_185_i AS_030_c \ + N_187_0 pos_clk_un5_bgack_030_int_d_n N_203_i AS_000_c N_324_i RW_000_c N_199_0 N_197_0 N_196_0 pos_clk_a0_dma_3_n UDS_000_c \ + LDS_000_c_i UDS_000_c_i LDS_000_c N_181_i N_347_i size_c_0__n N_348_i N_178_i pos_clk_ds_000_dma_4_n size_c_1__n VMA_INT_i \ + N_3 pos_clk_un5_bgack_030_int_d_i_n N_8 ahigh_c_24__n pos_clk_un23_bgack_030_int_i_1_0_n CLK_OUT_PRE_D_i ahigh_c_25__n N_148_0 N_341_i ahigh_c_26__n N_338_i \ + N_339_i N_19 ahigh_c_27__n N_20 N_336_i N_24 ahigh_c_28__n N_122_0 N_25 N_211_i ahigh_c_29__n \ + N_332_i ahigh_c_30__n N_331_i N_120_0 ahigh_c_31__n N_330_i pos_clk_ds_000_dma_4_0_n N_329_i pos_clk_size_dma_6_0_1__n N_328_i pos_clk_size_dma_6_0_0__n \ + N_325_i N_327_i AMIGA_BUS_DATA_DIR_c_0 N_320_i N_298_0 N_295_0 N_294_0 N_319_i un1_amiga_bus_enable_dma_high_0_0__n N_206_i N_283_i \ + N_122 N_281_i pos_clk_size_dma_6_0__n N_282_i pos_clk_size_dma_6_1__n N_3_i N_49_0 N_8_i N_45_0 pos_clk_un23_bgack_030_int_i_1_n N_19_i \ + N_292 N_40_0 N_294 a_decode_c_16__n N_20_i N_295 N_39_0 N_296 a_decode_c_17__n N_24_i N_298 \ + N_35_0 N_120 a_decode_c_18__n N_25_i N_148 N_34_0 N_149 a_decode_c_19__n N_194_0_1 N_157 N_237_i_1 \ + N_172 a_decode_c_20__n N_237_i_2 N_176 N_238_i_1 N_178 a_decode_c_21__n N_238_i_2 N_181 N_144_i_1 N_184 \ + a_decode_c_22__n N_144_i_2 N_144_i_3 N_196 a_decode_c_23__n N_136_i_1 N_197 N_136_i_2 N_206 a_c_0__n N_176_i_1 \ + N_207 N_146_0_1 N_211 a_c_1__n pos_clk_un10_sm_amiga_i_1_n N_215 un10_ciin_1 N_222 nEXP_SPACE_c un10_ciin_2 N_224 \ + un10_ciin_3 N_225 BERR_c un10_ciin_4 N_227 un10_ciin_5 N_228 BG_030_c un10_ciin_6 N_236 un10_ciin_7 \ + N_277 un10_ciin_8 N_281 un10_ciin_9 N_282 un10_ciin_10 N_283 BGACK_000_c un10_ciin_11 N_285 N_347_1 \ + N_318 CLK_030_c N_347_2 N_319 pos_clk_un23_bgack_030_int_i_1_0_1_n N_320 CLK_000_c pos_clk_un23_bgack_030_int_i_1_0_2_n N_321 un21_fpu_cs_1 N_322 \ + CLK_OSZI_c un22_berr_1_0 N_323 N_366_1 N_325 N_366_2 N_327 N_366_3 N_328 N_366_4 N_329 \ + un1_SM_AMIGA_5_i_1 N_330 FPU_SENSE_c un1_SM_AMIGA_5_i_2 N_331 N_142_i_1 N_332 N_142_i_2 N_336 N_339_1 N_338 \ + N_280_1 N_339 N_280_2 N_341 N_231_1 N_344 N_231_2 N_347 ipl_c_0__n N_230_1 N_348 \ + N_230_2 ipl_c_1__n N_230_3 N_226_1 ipl_c_2__n N_226_2 N_226_3 N_199 N_239_i_1 N_324 DTACK_c \ + N_122_0_1 un22_berr_1 N_132_i_1 N_366 N_120_0_1 N_335 N_106_i_1 N_208 VPA_c N_103_i_1 N_203 \ + N_92_i_1 N_187 N_140_i_1 N_137 RST_c N_138_i_1 N_349 N_344_1 pos_clk_un6_bgack_000_n pos_clk_un6_bg_030_1_n N_10 \ + RW_c N_327_1 N_5 N_319_1 N_293 fc_c_0__n N_285_1 N_6 N_277_1 un1_SM_AMIGA_5 fc_c_1__n \ + N_236_1 DS_000_ENABLE_1_sqmuxa_1 N_228_1 N_7 N_225_1 pos_clk_un3_as_030_d0_n AMIGA_BUS_DATA_DIR_c N_224_1 N_290 N_222_1 N_18 \ + N_215_1 DS_000_ENABLE_1_sqmuxa pos_clk_ipl_1_n N_232 bg_000_0_un3_n N_194 BG_030_c_i bg_000_0_un1_n N_233 pos_clk_un6_bg_030_i_n bg_000_0_un0_n \ + N_275 pos_clk_un9_bg_030_0_n uds_000_int_0_un3_n N_153 N_26_i uds_000_int_0_un1_n N_191 N_33_0 uds_000_int_0_un0_n N_334 N_21_i \ + lds_000_int_0_un3_n N_146 N_38_0 lds_000_int_0_un1_n N_345 N_17_i lds_000_int_0_un0_n N_346 N_42_0 dsack1_int_0_un3_n N_163 \ + N_4_i dsack1_int_0_un1_n N_22 N_48_0 dsack1_int_0_un0_n pos_clk_un4_clk_000_pe_n ipl_c_i_0__n ipl_030_0_2__un3_n cpu_est_2_1__n N_51_0 ipl_030_0_2__un1_n \ + N_235 ipl_c_i_1__n ipl_030_0_2__un0_n N_284 N_52_0 ipl_030_0_1__un3_n N_190 ipl_c_i_2__n ipl_030_0_1__un1_n N_337 N_53_0 \ + ipl_030_0_1__un0_n N_195 N_27_i ipl_030_0_0__un3_n N_340 N_30_0 ipl_030_0_0__un1_n N_231 N_28_i ipl_030_0_0__un0_n N_230 \ + N_31_0 cpu_est_0_3__un3_n N_280 N_29_i cpu_est_0_3__un1_n AS_030.OE AS_000.OE RW_000.OE UDS_000.OE \ + LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE \ + AHIGH_30_.OE AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE +.names un6_as_030_i.BLIF AS_030 1 1 .names AS_030.PIN AS_030_c 1 1 -.names N_285_i.BLIF AS_030.OE +.names un3_as_030_i.BLIF AS_030.OE 1 1 .names un4_as_000_i.BLIF AS_000 1 1 @@ -261,19 +267,67 @@ 1 1 .names SIZE_0_.PIN size_c_0__n 1 1 -.names N_222_i.BLIF SIZE_0_.OE +.names N_200_i.BLIF SIZE_0_.OE 1 1 .names un3_size.BLIF SIZE_1_ 1 1 .names SIZE_1_.PIN size_c_1__n 1 1 -.names N_222_i.BLIF SIZE_1_.OE +.names N_200_i.BLIF SIZE_1_.OE 1 1 -.names inst_A0_DMA.BLIF A0 +.names gnd_n_n.BLIF AHIGH_24_ 1 1 -.names A0.PIN A0_c +.names AHIGH_24_.PIN ahigh_c_24__n 1 1 -.names N_285_i.BLIF A0.OE +.names un3_as_030_i.BLIF AHIGH_24_.OE +1 1 +.names gnd_n_n.BLIF AHIGH_25_ +1 1 +.names AHIGH_25_.PIN ahigh_c_25__n +1 1 +.names un3_as_030_i.BLIF AHIGH_25_.OE +1 1 +.names gnd_n_n.BLIF AHIGH_26_ +1 1 +.names AHIGH_26_.PIN ahigh_c_26__n +1 1 +.names un3_as_030_i.BLIF AHIGH_26_.OE +1 1 +.names gnd_n_n.BLIF AHIGH_27_ +1 1 +.names AHIGH_27_.PIN ahigh_c_27__n +1 1 +.names un3_as_030_i.BLIF AHIGH_27_.OE +1 1 +.names gnd_n_n.BLIF AHIGH_28_ +1 1 +.names AHIGH_28_.PIN ahigh_c_28__n +1 1 +.names un3_as_030_i.BLIF AHIGH_28_.OE +1 1 +.names gnd_n_n.BLIF AHIGH_29_ +1 1 +.names AHIGH_29_.PIN ahigh_c_29__n +1 1 +.names un3_as_030_i.BLIF AHIGH_29_.OE +1 1 +.names gnd_n_n.BLIF AHIGH_30_ +1 1 +.names AHIGH_30_.PIN ahigh_c_30__n +1 1 +.names un3_as_030_i.BLIF AHIGH_30_.OE +1 1 +.names gnd_n_n.BLIF AHIGH_31_ +1 1 +.names AHIGH_31_.PIN ahigh_c_31__n +1 1 +.names un3_as_030_i.BLIF AHIGH_31_.OE +1 1 +.names inst_A0_DMA.BLIF A_0_ +1 1 +.names A_0_.PIN a_c_0__n +1 1 +.names un3_as_030_i.BLIF A_0_.OE 1 1 .names gnd_n_n.BLIF BERR 1 1 @@ -285,1588 +339,1620 @@ 1 1 .names RW.PIN RW_c 1 1 -.names N_284_i.BLIF RW.OE +.names N_318.BLIF RW.OE 1 1 .names un6_ds_030_i.BLIF DS_030 1 1 -.names N_285_i.BLIF DS_030.OE +.names un3_as_030_i.BLIF DS_030.OE 1 1 .names inst_DSACK1_INTreg.BLIF DSACK1 1 1 -.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE +.names nEXP_SPACE_c.BLIF DSACK1.OE 1 1 .names gnd_n_n.BLIF RESET 1 1 .names RESET_OUT_i.BLIF RESET.OE 1 1 -.names un5_ciin.BLIF CIIN +.names un10_ciin.BLIF CIIN 1 1 -.names N_61.BLIF CIIN.OE +.names N_296.BLIF CIIN.OE 1 1 -.names N_304_1.BLIF N_304_2.BLIF N_304 -11 1 -.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un4_uds_000 +.names N_338_i.BLIF N_339_i.BLIF N_239_i_1 11 1 .names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n 11 1 -.names AS_030_D0_i.BLIF a_c_20__n.BLIF un5_ciin_1 -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names un4_uds_000.BLIF un4_uds_000_i -0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C +.names amiga_bus_enable_dma_high_0_un1_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_25 +1- 1 +-1 1 +.names CLK_000_D_5_.BLIF CLK_000_D_6_.D 1 1 -.names a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2 +.names N_239_i_1.BLIF RST_c.BLIF RST_DLY_0_.D 11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_1__n +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i 0 1 -.names un4_lds_000.BLIF un4_lds_000_i -0 1 -.names a_c_23__n.BLIF a_i_24__n.BLIF un5_ciin_3 +.names N_25_i.BLIF RST_c.BLIF N_34_0 11 1 -.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size -11 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names a_i_25__n.BLIF a_i_26__n.BLIF un5_ciin_4 -11 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 -11 1 -.names a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5 -11 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names un4_as_000.BLIF un4_as_000_i -0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C +.names CLK_000_D_6_.BLIF CLK_000_D_7_.D 1 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6 +.names N_336_i.BLIF sm_amiga_i_5__n.BLIF N_122_0_1 11 1 -.names N_286.BLIF size_dma_0_1__un3_n +.names un21_fpu_cs.BLIF un21_fpu_cs_i 0 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i +.names N_24_i.BLIF RST_c.BLIF N_35_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C +1 1 +.names CLK_000_D_7_.BLIF CLK_000_D_8_.D +1 1 +.names N_122_0_1.BLIF SM_AMIGA_i_7_.BLIF N_122_0 +11 1 +.names CLK_000_N_SYNC_12_.BLIF clk_000_n_sync_i_12__n 0 1 -.names un5_ciin_1.BLIF un5_ciin_2.BLIF un5_ciin_7 +.names N_20_i.BLIF RST_c.BLIF N_39_0 11 1 -.names pos_clk_size_dma_6_1__n.BLIF N_286.BLIF size_dma_0_1__un1_n +.names CLK_000_D_8_.BLIF CLK_000_D_9_.D +1 1 +.names N_211_i.BLIF N_332_i.BLIF N_132_i_1 11 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +.names RST_DLY_2_.BLIF rst_dly_i_2__n +0 1 +.names N_19_i.BLIF RST_c.BLIF N_40_0 11 1 -.names un5_ciin_3.BLIF un5_ciin_4.BLIF un5_ciin_8 +.names CLK_000_D_9_.BLIF CLK_000_D_10_.D +1 1 +.names N_132_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D 11 1 +.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_2__n.BLIF N_219 +11 1 +.names N_8_i.BLIF RST_c.BLIF N_45_0 +11 1 +.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D +1 1 +.names N_331_i.BLIF RW_000_i.BLIF N_120_0_1 +11 1 +.names N_141.BLIF N_166_i.BLIF N_217 +11 1 +.names N_3_i.BLIF RST_c.BLIF N_49_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C +1 1 +.names N_366_4.BLIF N_366_3.BLIF N_366 +11 1 +.names N_294.BLIF size_dma_0_0__un3_n +0 1 +.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_163_i.BLIF un1_SM_AMIGA_5_i_1 +11 1 +.names pos_clk_size_dma_6_0__n.BLIF N_294.BLIF size_dma_0_0__un1_n +11 1 +.names N_346_i.BLIF sm_amiga_i_0__n.BLIF un1_SM_AMIGA_5_i_2 +11 1 +.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +11 1 +.names un1_SM_AMIGA_5_i_1.BLIF un1_SM_AMIGA_5_i_2.BLIF un1_SM_AMIGA_5_i +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C +1 1 +.names N_163.BLIF N_334_i.BLIF N_142_i_1 +11 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +11 1 +.names N_294.BLIF size_dma_0_1__un3_n +0 1 +.names N_335_i.BLIF RST_c.BLIF N_142_i_2 +11 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names pos_clk_size_dma_6_1__n.BLIF N_294.BLIF size_dma_0_1__un1_n +11 1 +.names N_142_i_1.BLIF N_142_i_2.BLIF SM_AMIGA_6_.D +11 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 +1- 1 +-1 1 .names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n 11 1 -.names un6_ds_030.BLIF un6_ds_030_i -0 1 -.names un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9 +.names CLK_000_c.BLIF CLK_000_D_0_.D +1 1 +.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_0__n.BLIF N_339_1 11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 .names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D 1- 1 -1 1 -.names N_96.BLIF ds_000_dma_0_un3_n +.names N_339_1.BLIF RST_c.BLIF N_339 +11 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i 0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C +.names CLK_OSZI_c.BLIF CLK_000_D_0_.C 1 1 -.names un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10 +.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_280_1 11 1 -.names N_286.BLIF size_dma_0_0__un3_n +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low +11 1 +.names RST_c.BLIF SM_AMIGA_3_.BLIF N_280_2 +11 1 +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28 +1- 1 +-1 1 +.names un4_uds_000.BLIF un4_uds_000_i 0 1 -.names N_90.BLIF N_96.BLIF ds_000_dma_0_un1_n +.names N_280_1.BLIF N_280_2.BLIF N_280 11 1 -.names un5_ciin_9.BLIF a_i_30__n.BLIF un5_ciin_11 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names un4_lds_000.BLIF un4_lds_000_i +0 1 +.names CLK_000_D_0_.BLIF CLK_000_D_1_.D +1 1 +.names CLK_000_N_SYNC_12_.BLIF N_357.BLIF N_231_1 11 1 -.names pos_clk_size_dma_6_0__n.BLIF N_286.BLIF size_dma_0_0__un1_n +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n 11 1 +.names un6_as_030.BLIF un6_as_030_i +0 1 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_231_2 +11 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names un4_as_000.BLIF un4_as_000_i +0 1 +.names CLK_OSZI_c.BLIF CLK_000_D_1_.C +1 1 +.names N_231_1.BLIF N_231_2.BLIF N_231 +11 1 +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27 +1- 1 +-1 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n +0 1 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 +11 1 +.names N_157_i.BLIF VMA_INT_i.BLIF N_347_1 +11 1 +.names N_291.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n +11 1 +.names un6_ds_030.BLIF un6_ds_030_i +0 1 +.names CLK_000_D_1_.BLIF CLK_000_D_2_.D +1 1 +.names VPA_D_i.BLIF cpu_est_i_1__n.BLIF N_347_2 +11 1 +.names cpu_est_3_.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +11 1 +.names N_120.BLIF ds_000_dma_0_un3_n +0 1 +.names N_347_1.BLIF N_347_2.BLIF N_347 +11 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D +1- 1 +-1 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_120.BLIF ds_000_dma_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_2_.C +1 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_1_n +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n +0 1 .names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n 11 1 -.names N_266_i.BLIF N_267_i.BLIF N_260_i_2 +.names pos_clk_un23_bgack_030_int_i_0_x2.BLIF N_341_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_2_n 11 1 -.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +.names cpu_est_2_2__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n 11 1 .names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 1- 1 -1 1 -.names N_260_i_1.BLIF N_260_i_2.BLIF RST_DLY_1_.D +.names pos_clk_un23_bgack_030_int_i_1_0_1_n.BLIF pos_clk_un23_bgack_030_int_i_1_0_2_n.BLIF pos_clk_un23_bgack_030_int_i_1_0_n 11 1 -.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D +.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n +11 1 +.names N_298.BLIF as_000_dma_0_un3_n +0 1 +.names FPU_SENSE_i.BLIF N_366.BLIF un21_fpu_cs_1 +11 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D 1- 1 -1 1 -.names N_99.BLIF as_000_dma_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C +.names pos_clk_un23_bgack_030_int_i_1_n.BLIF N_298.BLIF as_000_dma_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_3_.C 1 1 -.names N_240_i.BLIF N_241_i.BLIF N_259_i_1 +.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs 11 1 -.names N_4_i.BLIF RST_c.BLIF N_48_0 -11 1 -.names N_192.BLIF N_99.BLIF as_000_dma_0_un1_n -11 1 -.names N_242_i.BLIF N_246_i.BLIF N_259_i_2 -11 1 -.names N_5_i.BLIF RST_c.BLIF N_47_0 +.names N_29_i.BLIF RST_c.BLIF N_32_0 11 1 .names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n 11 1 -.names N_259_i_1.BLIF N_259_i_2.BLIF RST_DLY_2_.D +.names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 11 1 -.names N_7_i.BLIF RST_c.BLIF N_46_0 +.names N_28_i.BLIF RST_c.BLIF N_31_0 11 1 .names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_8 1- 1 -1 1 -.names inst_CLK_000_NE.BLIF N_361.BLIF N_336_1 +.names un22_berr_1_0.BLIF N_366.BLIF un22_berr 11 1 -.names N_10_i.BLIF RST_c.BLIF N_43_0 +.names N_27_i.BLIF RST_c.BLIF N_30_0 11 1 -.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n +.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n 0 1 -.names CLK_OSZI_c.BLIF RST_DLY_0_.C +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_366_1 +11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names N_295.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_4_.C 1 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_336_2 +.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_366_2 11 1 -.names N_18_i.BLIF RST_c.BLIF N_41_0 -11 1 -.names pos_clk_un8_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n -11 1 -.names N_336_1.BLIF N_336_2.BLIF N_336 -11 1 -.names RST_c.BLIF RST_i -0 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names inst_CLK_000_PE.BLIF cpu_est_i_0__n.BLIF N_332_1 -11 1 -.names N_24_i.BLIF RST_c.BLIF N_35_0 -11 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_17 -1- 1 --1 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_332_2 -11 1 -.names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D -11 1 -.names N_193.BLIF rw_000_dma_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C -1 1 -.names N_332_1.BLIF N_332_2.BLIF N_332_3 -11 1 -.names N_276.BLIF N_276_i -0 1 -.names N_80.BLIF N_193.BLIF rw_000_dma_0_un1_n -11 1 -.names N_332_3.BLIF cpu_est_i_3__n.BLIF N_332 -11 1 -.names N_156.BLIF SM_AMIGA_0_.BLIF N_354 +.names N_157.BLIF N_315_i.BLIF N_291_0 11 1 .names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n 11 1 -.names N_168.BLIF N_194_i.BLIF N_317_1 +.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_366_3 +11 1 +.names N_254_i.BLIF N_357_i.BLIF cpu_est_2_0_2__n 11 1 -.names inst_CLK_000_PE.BLIF CLK_000_PE_i -0 1 .names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 1- 1 -1 1 -.names N_196_i.BLIF N_197_i.BLIF N_317_2 +.names N_366_1.BLIF N_366_2.BLIF N_366_4 11 1 -.names CLK_000_PE_i.BLIF SM_AMIGA_4_.BLIF N_349 +.names N_275_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_258_0 +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n +0 1 +.names AS_030_000_SYNC_i.BLIF CLK_000_N_SYNC_0_.BLIF N_146_0_1 +11 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_5_.C +1 1 +.names N_146_0_1.BLIF nEXP_SPACE_c.BLIF N_146_0 +11 1 +.names N_164_i.BLIF cpu_est_i_2__n.BLIF N_357 +11 1 +.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +11 1 +.names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n +11 1 +.names BERR_c.BLIF BERR_i +0 1 +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 +1- 1 +-1 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF pos_clk_un10_sm_amiga_i_n +11 1 +.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_343 11 1 .names vcc_n_n 1 -.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C -1 1 -.names N_317_1.BLIF N_317_2.BLIF N_317_3 +.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 11 1 -.names N_218.BLIF sm_amiga_i_5__n.BLIF N_305 +.names N_141.BLIF RST_DLY_0_.BLIF N_338 11 1 .names gnd_n_n -.names VPA_D_i.BLIF cpu_est_i_1__n.BLIF N_351_2 -11 1 -.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_300 -11 1 -.names A_15_.BLIF a_15__n +.names CLK_OSZI_c.BLIF CLK_000_D_6_.C 1 1 -.names N_351_1.BLIF N_351_2.BLIF N_351 +.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 11 1 -.names BGACK_030_INT_i.BLIF N_205_i.BLIF N_299 +.names N_164_i.BLIF cpu_est_2_.BLIF N_315 11 1 -.names A_14_.BLIF a_14__n +.names A_DECODE_15_.BLIF a_decode_15__n 1 1 -.names AS_030_000_SYNC_i.BLIF N_148_i.BLIF N_168_i_1 +.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 11 1 -.names BGACK_030_INT_i.BLIF N_205.BLIF N_298 +.names N_164.BLIF cpu_est_2_.BLIF N_254 11 1 -.names A_13_.BLIF a_13__n +.names A_DECODE_14_.BLIF a_decode_14__n 1 1 -.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 +11 1 +.names N_192.BLIF N_343.BLIF N_223 +11 1 +.names A_DECODE_13_.BLIF a_decode_13__n 1 1 -.names N_168_i_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_168_i +.names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 11 1 -.names A1_c.BLIF BGACK_030_INT_i.BLIF N_276 -11 1 -.names A_12_.BLIF a_12__n -1 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_192_0_1 -11 1 -.names pos_clk_un3_as_030_d0_i_n.BLIF un1_SM_AMIGA_5.BLIF DS_000_ENABLE_1_sqmuxa_1 -11 1 -.names A_11_.BLIF a_11__n -1 1 -.names pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_345_i.BLIF N_192_0_2 -11 1 -.names N_375.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_272 -11 1 -.names A_10_.BLIF a_10__n -1 1 -.names N_192_0_1.BLIF N_192_0_2.BLIF N_192_0 -11 1 -.names N_289.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_271 -11 1 -.names A_9_.BLIF a_9__n -1 1 -.names CLK_OSZI_c.BLIF inst_AS_030_D0.C -1 1 -.names N_323_i.BLIF N_324_i.BLIF N_137_i_1 -11 1 -.names RW_c.BLIF RW_i +.names RST_DLY_1_.BLIF rst_dly_i_1__n 0 1 -.names A_8_.BLIF a_8__n +.names A_DECODE_12_.BLIF a_decode_12__n 1 1 -.names N_347_i.BLIF RST_c.BLIF N_137_i_2 -11 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa -11 1 -.names A_7_.BLIF a_7__n +.names CLK_OSZI_c.BLIF CLK_000_D_7_.C 1 1 -.names N_137_i_1.BLIF N_137_i_2.BLIF SM_AMIGA_3_.D +.names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 11 1 -.names SIZE_DMA_0_.BLIF size_dma_i_0__n +.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_1__n.BLIF N_221 +11 1 +.names A_DECODE_11_.BLIF a_decode_11__n +1 1 +.names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 +11 1 +.names N_149_i.BLIF N_340.BLIF N_220 +11 1 +.names A_DECODE_10_.BLIF a_decode_10__n +1 1 +.names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 +11 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_200_i +11 1 +.names A_DECODE_9_.BLIF a_decode_9__n +1 1 +.names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 +11 1 +.names A_DECODE_8_.BLIF a_decode_8__n +1 1 +.names CLK_OSZI_c.BLIF CLK_000_D_8_.C +1 1 +.names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 +11 1 +.names cpu_est_3_.BLIF cpu_est_i_3__n 0 1 -.names A_6_.BLIF a_6__n +.names A_DECODE_7_.BLIF a_decode_7__n 1 1 -.names N_208_0.BLIF N_312_i.BLIF N_145_i_1 +.names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 11 1 -.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size -11 1 -.names A_5_.BLIF a_5__n -1 1 -.names CLK_OSZI_c.BLIF inst_nEXP_SPACE_D0reg.C -1 1 -.names N_313_i.BLIF N_316_i.BLIF N_145_i_2 -11 1 -.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n -11 1 -.names A_4_.BLIF a_4__n -1 1 -.names N_145_i_1.BLIF N_145_i_2.BLIF N_145_i_3 -11 1 -.names AS_030_i.BLIF RST_c.BLIF N_88_0 -11 1 -.names A_3_.BLIF a_3__n -1 1 -.names N_145_i_3.BLIF N_317_i.BLIF SM_AMIGA_i_7_.D -11 1 -.names N_193_i.BLIF RST_c.BLIF N_286_0 -11 1 -.names A_2_.BLIF a_2__n -1 1 -.names N_242_i.BLIF N_254_i.BLIF N_260_i_1 -11 1 -.names N_222_i.BLIF inst_RESET_OUT.BLIF N_285_i -11 1 -.names CLK_OSZI_c.BLIF inst_VPA_D.C -1 1 -.names N_25.BLIF N_25_i +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_284_i +.names A_DECODE_6_.BLIF a_decode_6__n +1 1 +.names N_215_i.BLIF N_217_i.BLIF N_237_i_1 11 1 -.names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n 0 1 -.names BGACK_000_c.BLIF N_358_i.BLIF pos_clk_un6_bgack_000_0_n +.names A_DECODE_5_.BLIF a_decode_5__n +1 1 +.names N_219_i.BLIF RST_c.BLIF N_237_i_2 11 1 -.names N_26.BLIF N_26_i +.names inst_VPA_D.BLIF VPA_D_i 0 1 -.names inst_RESET_OUT.BLIF RESET_OUT_i +.names A_DECODE_4_.BLIF a_decode_4__n +1 1 +.names CLK_OSZI_c.BLIF CLK_000_D_9_.C +1 1 +.names N_237_i_1.BLIF N_237_i_2.BLIF RST_DLY_2_.D +11 1 +.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_192_0 +11 1 +.names A_DECODE_3_.BLIF a_decode_3__n +1 1 +.names N_220_i.BLIF RST_c.BLIF N_238_i_1 +11 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_186_0 +11 1 +.names A_DECODE_2_.BLIF a_decode_2__n +1 1 +.names N_221_i.BLIF N_222_i.BLIF N_238_i_2 +11 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_172_i +11 1 +.names N_238_i_1.BLIF N_238_i_2.BLIF RST_DLY_1_.D +11 1 +.names N_149_i.BLIF RST_DLY_2_.BLIF N_166_i +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_10_.C +1 1 +.names N_185_i.BLIF N_223_i.BLIF N_144_i_1 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 -.names N_33_0.BLIF BG_000DFFreg.D +.names N_224_i.BLIF N_225_i.BLIF N_144_i_2 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 +.names N_144_i_1.BLIF N_144_i_2.BLIF N_144_i_3 +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_164_i +11 1 +.names CLK_000_D_10_.BLIF CLK_000_D_11_.D +1 1 +.names N_144_i_3.BLIF N_226_i.BLIF SM_AMIGA_i_7_.D +11 1 +.names RST_DLY_0_.BLIF rst_dly_i_0__n +0 1 +.names N_227_i.BLIF N_228_i.BLIF N_136_i_1 +11 1 +.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_149_i +11 1 +.names CLK_OSZI_c.BLIF CLK_000_D_11_.C +1 1 +.names N_343_i.BLIF RST_c.BLIF N_136_i_2 +11 1 +.names N_277_i.BLIF N_280_i.BLIF N_257_0 +11 1 +.names N_136_i_1.BLIF N_136_i_2.BLIF SM_AMIGA_3_.D +11 1 +.names N_284_i.BLIF N_285_i.BLIF N_292_0 +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_176_i_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names CLK_000_D_11_.BLIF CLK_000_D_12_.D +1 1 +.names N_176_i_1.BLIF sm_amiga_i_2__n.BLIF N_176_i +11 1 .names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i 11 1 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C -1 1 -.names BG_030_c.BLIF BG_030_c_i +.names N_282.BLIF N_282_i 0 1 -.names N_299_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_296_0 11 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n -0 1 -.names N_298_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n -11 1 -.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n -0 1 -.names N_236_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_281_0 -11 1 -.names N_193_i.BLIF sm_amiga_i_i_7__n.BLIF N_289_0_1 -11 1 -.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_280_0 -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_030_H.C -1 1 -.names N_289_0_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_289_0 -11 1 -.names N_271_i.BLIF N_272_i.BLIF N_279_0 -11 1 -.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_349_i.BLIF un1_SM_AMIGA_5_i_1 -11 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names N_194_i.BLIF SM_AMIGA_i_7_.BLIF un1_SM_AMIGA_5_i_2 -11 1 -.names AS_000_c.BLIF inst_CLK_000_PE.BLIF N_358 -11 1 -.names un1_SM_AMIGA_5_i_1.BLIF un1_SM_AMIGA_5_i_2.BLIF un1_SM_AMIGA_5_i -11 1 -.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 -11 1 -.names CLK_OSZI_c.BLIF inst_RESET_OUT.C -1 1 -.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un8_sm_amiga_i_1_n -11 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names pos_clk_un8_sm_amiga_i_1_n.BLIF size_c_0__n.BLIF pos_clk_un8_sm_amiga_i_n -11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n -0 1 -.names N_182_i.BLIF VMA_INT_i.BLIF N_351_1 -11 1 -.names BERR_c.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n -11 1 -.names N_54_0.BLIF inst_nEXP_SPACE_D0reg.D -0 1 -.names inst_CLK_000_PE.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C +.names CLK_OSZI_c.BLIF CLK_000_D_12_.C 1 1 .names N_3.BLIF N_3_i 0 1 -.names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_229 -1- 1 --1 1 +.names N_337_i.BLIF RST_c.BLIF inst_RESET_OUT.D +11 1 .names N_49_0.BLIF inst_DS_000_DMA.D 0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 +.names N_166.BLIF RST_c.BLIF N_216_i +11 1 .names N_8.BLIF N_8_i 0 1 -.names N_156_i.BLIF SM_AMIGA_4_.BLIF N_218_0 -11 1 +.names inst_RESET_OUT.BLIF RESET_OUT_i +0 1 .names N_45_0.BLIF inst_AS_000_DMA.D 0 1 -.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i -0 1 -.names CLK_OSZI_c.BLIF BG_000DFFreg.C +.names N_200_i.BLIF inst_RESET_OUT.BLIF un3_as_030_i +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C 1 1 -.names N_17.BLIF N_17_i -0 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_210_0 -11 1 -.names N_42_0.BLIF inst_LDS_000_INT.D -0 1 -.names N_354_i.BLIF RST_c.BLIF N_208_0 -11 1 .names N_19.BLIF N_19_i 0 1 -.names N_156.BLIF sm_amiga_i_3__n.BLIF N_207_0 +.names N_340_i.BLIF RST_c.BLIF N_141_0 11 1 .names N_40_0.BLIF inst_RW_000_DMA.D 0 1 -.names N_156.BLIF SM_AMIGA_i_7_.BLIF N_206_0 +.names cpu_est_3_.BLIF cpu_est_i_2__n.BLIF N_154_i 11 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C -1 1 .names N_20.BLIF N_20_i 0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_205_i +.names N_154_i.BLIF cpu_est_i_0__n.BLIF N_157_i 11 1 .names N_39_0.BLIF inst_A0_DMA.D 0 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names N_21.BLIF N_21_i -0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_194_i -11 1 -.names N_38_0.BLIF inst_UDS_000_INT.D -0 1 -.names BERR_c.BLIF CLK_000_PE_i.BLIF N_156_i -11 1 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -.names N_22.BLIF N_22_i -0 1 -.names BERR_c.BLIF BERR_i -0 1 -.names N_37_0.BLIF inst_VMA_INTreg.D -0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF N_222_i -11 1 -.names N_28.BLIF N_28_i -0 1 -.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n -0 1 -.names N_31_0.BLIF IPL_030DFF_1_reg.D -0 1 -.names sm_amiga_i_i_7__n.BLIF inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un1_n -11 1 -.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C -1 1 -.names N_27.BLIF N_27_i -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n -11 1 -.names N_30_0.BLIF IPL_030DFF_0_reg.D -0 1 -.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_227 -1- 1 --1 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n -0 1 -.names N_53_0.BLIF IPL_D0_2_.D -0 1 -.names SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_m2_5__un3_n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C -1 1 -.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C -1 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n -0 1 -.names BERR_c.BLIF SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_m2_5__un1_n -11 1 -.names N_52_0.BLIF IPL_D0_1_.D -0 1 -.names inst_CLK_000_PE.BLIF sm_amiga_srsts_i_0_m2_5__un3_n.BLIF sm_amiga_srsts_i_0_m2_5__un0_n -11 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n -0 1 -.names sm_amiga_srsts_i_0_m2_5__un1_n.BLIF sm_amiga_srsts_i_0_m2_5__un0_n.BLIF N_230 -1- 1 --1 1 -.names N_51_0.BLIF IPL_D0_0_.D -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 -.names CLK_OSZI_c.BLIF inst_A0_DMA.C -1 1 -.names DTACK_c.BLIF DTACK_c_i -0 1 -.names N_56_0.BLIF inst_DTACK_D0.D -0 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names VPA_c.BLIF VPA_c_i -0 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names N_55_0.BLIF inst_VPA_D.D -0 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C -1 1 -.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C -1 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i -0 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names N_307.BLIF N_307_i -0 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names N_303.BLIF N_303_i -0 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_304.BLIF N_304_i -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 -.names CLK_OSZI_c.BLIF inst_RW_000_INT.C -1 1 -.names N_283_0.BLIF SM_AMIGA_2_.D -0 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names N_301.BLIF N_301_i -0 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names N_300.BLIF N_300_i -0 1 -.names clk_000_n_sync_i_10__n.BLIF N_350_i.BLIF N_188_0 -11 1 -.names N_123_0.BLIF N_123 -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_193_i -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C -1 1 -.names N_278.BLIF N_278_i -0 1 -.names sm_amiga_i_2__n.BLIF sm_amiga_i_4__n.BLIF N_196_i -11 1 -.names N_297.BLIF N_297_i -0 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_197_i -11 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names N_351_i.BLIF N_353_i.BLIF N_201_i -11 1 -.names N_277.BLIF N_277_i -0 1 -.names N_196_i.BLIF sm_amiga_i_6__n.BLIF N_204_0 -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C -1 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C -1 1 -.names A0_c.BLIF A0_c_i -0 1 -.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_211_0 -11 1 -.names size_c_1__n.BLIF size_c_i_1__n -0 1 -.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_212_0 -11 1 -.names N_29.BLIF N_29_i -0 1 -.names inst_CLK_000_NE_D0.BLIF N_201.BLIF N_290_0 -11 1 -.names N_32_0.BLIF IPL_030DFF_2_reg.D -0 1 -.names inst_CLK_000_NE.BLIF N_187_i.BLIF N_216_0 -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C -1 1 -.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C -1 1 -.names N_330.BLIF N_330_i -0 1 -.names inst_CLK_000_NE.BLIF CLK_000_NE_i -0 1 -.names N_90_0.BLIF N_90 -0 1 .names SM_AMIGA_1_.BLIF sm_amiga_i_1__n 0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C +1 1 +.names N_24.BLIF N_24_i +0 1 +.names clk_000_n_sync_i_12__n.BLIF SM_AMIGA_1_.BLIF N_190_0 +11 1 +.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names CLK_000_N_SYNC_12_.BLIF N_166_i.BLIF N_195_0 +11 1 +.names N_25.BLIF N_25_i +0 1 +.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n +0 1 +.names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n +11 1 +.names CLK_OSZI_c.BLIF RST_DLY_0_.C +1 1 +.names sm_amiga_i_i_7__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_194_0_1 +11 1 +.names clk_000_p_sync_i_10__n.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n +11 1 +.names N_194_0_1.BLIF nEXP_SPACE_c.BLIF N_194_0 +11 1 +.names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_211 +1- 1 +-1 1 +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +0 1 +.names pos_clk_un4_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 .names N_328.BLIF N_328_i 0 1 -.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_219_0 +.names cpu_est_i_1__n.BLIF pos_clk_un4_clk_000_pe_n.BLIF vma_int_0_un1_n 11 1 -.names N_80_0.BLIF N_80 -0 1 -.names inst_CLK_000_PE.BLIF SM_AMIGA_4_.BLIF N_220_0 -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C -1 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -.names N_325.BLIF N_325_i -0 1 -.names AS_000_DMA_i.BLIF CLK_030_i.BLIF N_221_0 -11 1 -.names N_326.BLIF N_326_i -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF N_138_0 -11 1 -.names N_258_0.BLIF SM_AMIGA_6_.D -0 1 -.names N_217_i.BLIF N_217 -0 1 -.names N_344_i.BLIF RST_c.BLIF N_144_0 -11 1 -.names CLK_OSZI_c.BLIF IPL_D0_0_.C -1 1 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C -1 1 -.names N_321.BLIF N_321_i -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names N_322.BLIF N_322_i -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_148_i -11 1 -.names N_320.BLIF N_320_i -0 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n -0 1 -.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D -1 1 -.names un5_ciin.BLIF un5_ciin_i -0 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n -0 1 -.names CLK_OSZI_c.BLIF IPL_D0_1_.C -1 1 -.names N_61_0.BLIF N_61 -0 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_158_i -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C -1 1 -.names N_310.BLIF N_310_i -0 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names N_305.BLIF N_305_i -0 1 -.names CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_175_0 -11 1 -.names N_124_0.BLIF N_124 -0 1 -.names cpu_est_3_.BLIF cpu_est_i_2__n.BLIF N_181_i -11 1 -.names CLK_OSZI_c.BLIF IPL_D0_2_.C -1 1 -.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D -1 1 -.names N_341.BLIF N_341_i -0 1 -.names N_181_i.BLIF cpu_est_i_0__n.BLIF N_182_i -11 1 -.names N_119_0.BLIF N_119 -0 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_185_i -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C -1 1 -.names N_340.BLIF N_340_i -0 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n -0 1 -.names N_361.BLIF N_361_i -0 1 -.names N_158_i.BLIF RST_DLY_2_.BLIF N_187_i -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C -1 1 -.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n -0 1 -.names N_208_0.BLIF N_277_i.BLIF SM_AMIGA_0_.D -11 1 -.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D -1 1 -.names N_338.BLIF N_338_i -0 1 -.names N_278_i.BLIF N_297_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names N_339.BLIF N_339_i -0 1 -.names N_303_i.BLIF N_304_i.BLIF N_283_0 -11 1 -.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C -1 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n -0 1 -.names nEXP_SPACE_D0_i.BLIF un5_ciin_i.BLIF N_61_0 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -.names N_332.BLIF N_332_i -0 1 -.names N_320_i.BLIF RST_c.BLIF inst_RESET_OUT.D -11 1 -.names N_336.BLIF N_336_i -0 1 -.names N_187.BLIF RST_c.BLIF N_217_i -11 1 -.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n -0 1 -.names N_325_i.BLIF N_326_i.BLIF N_258_0 -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_PE.C -1 1 -.names N_99_0.BLIF N_99 -0 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_80_0 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -.names N_331.BLIF N_331_i -0 1 -.names N_192_0.BLIF N_330_i.BLIF N_90_0 -11 1 -.names N_96_0.BLIF N_96 -0 1 -.names CLK_030_i.BLIF N_192_0.BLIF N_99_0 -11 1 -.names N_187_i.BLIF N_187 -0 1 -.names N_332_i.BLIF N_336_i.BLIF pos_clk_un7_clk_000_pe_0_n -11 1 -.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D -1 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C -1 1 -.names N_185_i.BLIF N_185 -0 1 -.names N_338_i.BLIF N_339_i.BLIF cpu_est_2_0_1__n -11 1 -.names N_182_i.BLIF N_182 -0 1 -.names N_340_i.BLIF N_361_i.BLIF cpu_est_2_0_2__n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C -1 1 -.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i -0 1 -.names N_182.BLIF N_341_i.BLIF N_119_0 -11 1 -.names N_175_0.BLIF N_175 -0 1 -.names N_342_i.BLIF N_343_i.BLIF N_124_0 -11 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C -1 1 -.names N_168_i.BLIF N_168 -0 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D -1 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_330 -11 1 -.names N_158_i.BLIF N_158 -0 1 -.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_331 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C -1 1 -.names inst_CLK_000_PE.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.X1 -1 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_338 -11 1 -.names N_345.BLIF N_345_i -0 1 -.names N_185.BLIF cpu_est_2_.BLIF N_340 -11 1 -.names CYCLE_DMA_0_.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.X2 -1 1 -.names N_344.BLIF N_344_i -0 1 -.names N_185_i.BLIF cpu_est_2_.BLIF N_341 -11 1 -.names N_144_0.BLIF N_144 -0 1 -.names N_181_i.BLIF cpu_est_i_1__n.BLIF N_342 -11 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C -1 1 -.names N_138_0.BLIF N_138 -0 1 -.names inst_CLK_000_NE.BLIF N_217_i.BLIF N_344 -11 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_.X1 -1 1 -.names N_342.BLIF N_342_i -0 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_345 -11 1 -.names A_16_.BLIF a_c_16__n -1 1 -.names N_343.BLIF N_343_i -0 1 -.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_347 -11 1 -.names cpu_est_0_.BLIF cpu_est_0_0_x2_0_.X2 -1 1 -.names A_17_.BLIF a_c_17__n -1 1 -.names N_216_0.BLIF N_216 -0 1 -.names CLK_000_N_SYNC_9_.BLIF N_175.BLIF N_350 -11 1 -.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C -1 1 -.names A_18_.BLIF a_c_18__n -1 1 -.names N_290_0.BLIF N_290 -0 1 -.names CLK_000_NE_i.BLIF RST_c.BLIF N_127 -11 1 -.names A_19_.BLIF a_c_19__n -1 1 -.names N_212_0.BLIF N_212 -0 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names CYCLE_DMA_1_.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X1 -1 1 -.names A_20_.BLIF a_c_20__n -1 1 -.names N_211_0.BLIF N_211 -0 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_353 -11 1 -.names A_21_.BLIF a_c_21__n -1 1 -.names N_204_0.BLIF N_204 -0 1 -.names N_185_i.BLIF cpu_est_i_2__n.BLIF N_361 -11 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C -1 1 -.names N_209.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X2 -1 1 -.names A_22_.BLIF a_c_22__n -1 1 -.names N_351.BLIF N_351_i -0 1 -.names N_219.BLIF sm_amiga_i_0__n.BLIF N_277 -11 1 -.names A_23_.BLIF a_c_23__n -1 1 -.names N_353.BLIF N_353_i -0 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_278 -11 1 -.names A_24_.BLIF a_c_24__n -1 1 -.names N_201_i.BLIF N_201 -0 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names CYCLE_DMA_0_.BLIF pos_clk_un23_bgack_030_int_i_i_a4_i_x2.X1 -1 1 -.names A_25_.BLIF a_c_25__n -1 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C -1 1 -.names A_26_.BLIF a_c_26__n -1 1 -.names N_197_i.BLIF N_197 -0 1 -.names N_212.BLIF sm_amiga_i_2__n.BLIF N_301 -11 1 -.names CYCLE_DMA_1_.BLIF pos_clk_un23_bgack_030_int_i_i_a4_i_x2.X2 -1 1 -.names A_27_.BLIF a_c_27__n -1 1 -.names N_193_i.BLIF N_193 -0 1 -.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_307 -11 1 -.names A_28_.BLIF a_c_28__n -1 1 -.names N_192_0.BLIF N_192 -0 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names A_29_.BLIF a_c_29__n -1 1 -.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n -0 1 -.names N_211.BLIF sm_amiga_i_6__n.BLIF N_310 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -.names IPL_D0_0_.BLIF G_134.X1 +.names CLK_OSZI_c.BLIF RST_DLY_1_.C 1 1 -.names A_30_.BLIF a_c_30__n -1 1 -.names N_350.BLIF N_350_i -0 1 -.names N_290.BLIF N_347.BLIF N_312 -11 1 -.names A_31_.BLIF a_c_31__n -1 1 -.names N_188_0.BLIF N_188 -0 1 -.names N_216.BLIF RESET_OUT_i.BLIF N_320 -11 1 -.names ipl_c_0__n.BLIF G_134.X2 -1 1 -.names N_241.BLIF N_241_i -0 1 -.names N_144.BLIF RST_DLY_0_.BLIF N_321 -11 1 -.names A1.BLIF A1_c -1 1 -.names N_266.BLIF N_266_i -0 1 -.names N_127.BLIF rst_dly_i_0__n.BLIF N_322 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_1_.C -1 1 -.names nEXP_SPACE.BLIF nEXP_SPACE_c -1 1 -.names N_267.BLIF N_267_i -0 1 -.names N_220.BLIF sm_amiga_i_3__n.BLIF N_323 -11 1 -.names IPL_D0_1_.BLIF G_135.X1 -1 1 -.names N_254.BLIF N_254_i -0 1 -.names inst_CLK_030_H.BLIF CLK_030_H_i -0 1 -.names BG_030.BLIF BG_030_c -1 1 -.names N_317.BLIF N_317_i -0 1 -.names CLK_030_H_i.BLIF N_221.BLIF N_328 -11 1 -.names ipl_c_1__n.BLIF G_135.X2 -1 1 -.names BG_000DFFreg.BLIF BG_000 -1 1 -.names N_313.BLIF N_313_i -0 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030 -1 1 -.names N_316.BLIF N_316_i -0 1 -.names BGACK_000.BLIF BGACK_000_c -1 1 -.names N_312.BLIF N_312_i -0 1 -.names IPL_D0_2_.BLIF G_136.X1 -1 1 -.names CLK_030.BLIF CLK_030_c -1 1 -.names N_347.BLIF N_347_i -0 1 -.names CLK_000.BLIF CLK_000_D_0_.D -1 1 -.names N_323.BLIF N_323_i -0 1 -.names N_188.BLIF SM_AMIGA_1_.BLIF N_236 -11 1 -.names CLK_OSZI_c.BLIF cpu_est_3_.C -1 1 -.names ipl_c_2__n.BLIF G_136.X2 -1 1 -.names CLK_OSZI.BLIF CLK_OSZI_c -1 1 -.names N_324.BLIF N_324_i -0 1 -.names N_144.BLIF N_187_i.BLIF N_241 -11 1 -.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT -1 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names N_217.BLIF RST_i.BLIF N_242 -11 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP -1 1 -.names N_221_0.BLIF N_221 -0 1 -.names N_127.BLIF rst_dly_i_2__n.BLIF N_246 -11 1 -.names cpu_est_0_0_x2_0_.BLIF cpu_est_0_.D -1 1 -.names un21_fpu_cs_i.BLIF FPU_CS -1 1 -.names N_220_0.BLIF N_220 -0 1 -.names N_144.BLIF N_158_i.BLIF N_254 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C -1 1 -.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D -1 1 -.names FPU_SENSE.BLIF FPU_SENSE_c -1 1 -.names N_219_0.BLIF N_219 -0 1 -.names N_127.BLIF rst_dly_i_1__n.BLIF N_267 -11 1 -.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D -1 1 -.names IPL_030DFF_0_reg.BLIF IPL_030_0_ -1 1 -.names N_156_i.BLIF N_156 -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF CLK_000_P_SYNC_0_.D -11 1 -.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D -1 1 -.names IPL_030DFF_1_reg.BLIF IPL_030_1_ -1 1 -.names N_349.BLIF N_349_i -0 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n -11 1 -.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D -1 1 -.names IPL_030DFF_2_reg.BLIF IPL_030_2_ -1 1 -.names un1_SM_AMIGA_5_i.BLIF un1_SM_AMIGA_5 -0 1 -.names A1_c.BLIF A1_i -0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C -1 1 -.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D -1 1 -.names IPL_0_.BLIF ipl_c_0__n -1 1 -.names UDS_000_c.BLIF UDS_000_c_i -0 1 -.names A1_i.BLIF BGACK_030_INT_i.BLIF N_275 -11 1 -.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D -1 1 -.names IPL_1_.BLIF ipl_c_1__n -1 1 -.names LDS_000_c.BLIF LDS_000_c_i -0 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D -1 1 -.names IPL_2_.BLIF ipl_c_2__n -1 1 -.names N_205_i.BLIF N_205 -0 1 -.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D -0 1 -.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D -1 1 -.names N_206_0.BLIF N_206 -0 1 -.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_209 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C -1 1 -.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D -1 1 -.names DTACK.BLIF DTACK_c -1 1 -.names N_207_0.BLIF N_207 -0 1 -.names G_134.BLIF N_213_i -0 1 -.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D -1 1 -.names vcc_n_n.BLIF AVEC -1 1 -.names N_354.BLIF N_354_i -0 1 -.names G_135.BLIF N_214_i -0 1 -.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D -1 1 -.names N_124.BLIF E -1 1 -.names N_210_0.BLIF inst_BGACK_030_INT_D.D -0 1 -.names G_136.BLIF N_215_i -0 1 -.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D -1 1 -.names VPA.BLIF VPA_c -1 1 -.names N_289_0.BLIF N_289 -0 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C -1 1 -.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D -1 1 -.names inst_VMA_INTreg.BLIF VMA -1 1 -.names N_218_0.BLIF N_218 -0 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -.names RST.BLIF RST_c -1 1 -.names N_242.BLIF N_242_i -0 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D -1 1 -.names N_246.BLIF N_246_i -0 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D -1 1 -.names N_240.BLIF N_240_i -0 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C -1 1 -.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D -1 1 -.names FC_0_.BLIF fc_c_0__n -1 1 -.names N_48_0.BLIF inst_DSACK1_INTreg.D -0 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D -1 1 -.names FC_1_.BLIF fc_c_1__n -1 1 -.names N_272.BLIF N_272_i -0 1 -.names RST_c.BLIF nEXP_SPACE_c_i.BLIF N_54_0 -11 1 -.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D -1 1 -.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE -1 1 -.names N_271.BLIF N_271_i -0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_55_0 -11 1 -.names N_148_i.BLIF CLK_000_N_SYNC_0_.D -1 1 -.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D -1 1 -.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR -1 1 -.names N_279_0.BLIF N_279 -0 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_56_0 -11 1 -.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW -1 1 -.names N_280_0.BLIF N_280 -0 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_51_0 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C -1 1 -.names N_227.BLIF AMIGA_BUS_ENABLE_HIGH -1 1 -.names N_281_0.BLIF N_281 -0 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_52_0 -11 1 -.names N_298.BLIF N_298_i -0 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_53_0 -11 1 -.names N_303_1.BLIF SM_AMIGA_2_.BLIF N_303 -11 1 .names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n 0 1 -.names N_27_i.BLIF RST_c.BLIF N_30_0 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n 11 1 -.names AS_000_i.BLIF N_222_i.BLIF N_297_1 -11 1 -.names N_299.BLIF N_299_i +.names N_325.BLIF N_325_i 0 1 -.names N_28_i.BLIF RST_c.BLIF N_31_0 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C -1 1 -.names N_297_1.BLIF RW_000_c.BLIF N_297 -11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_22 +1- 1 +-1 1 +.names N_327.BLIF N_327_i 0 1 -.names N_29_i.BLIF RST_c.BLIF N_32_0 +.names N_22_i.BLIF RST_c.BLIF N_37_0 11 1 -.names N_217_i.BLIF rst_dly_i_0__n.BLIF N_266_1 -11 1 -.names N_358.BLIF N_358_i +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c 0 1 .names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n 0 1 -.names N_266_1.BLIF rst_dly_i_1__n.BLIF N_266 -11 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +.names CLK_OSZI_c.BLIF RST_DLY_2_.C +1 1 +.names N_320.BLIF N_320_i 0 1 .names cpu_est_2_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n 11 1 -.names N_158.BLIF N_217_i.BLIF N_240_1 -11 1 -.names N_286_0.BLIF N_286 +.names N_298_0.BLIF N_298 0 1 .names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C -1 1 -.names N_240_1.BLIF rst_dly_i_2__n.BLIF N_240 -11 1 -.names N_88_0.BLIF inst_AS_030_D0.D +.names N_295_0.BLIF N_295 0 1 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 -.names N_215_i.BLIF N_213_i.BLIF pos_clk_ipl_1_n -11 1 -.names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n +.names N_294_0.BLIF N_294 0 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n -0 1 -.names pos_clk_ipl_1_n.BLIF N_214_i.BLIF pos_clk_ipl_n +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_235 11 1 -.names N_24.BLIF N_24_i -0 1 -.names cpu_est_2_2__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n -11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_339_1 -11 1 -.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 -.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C +.names CLK_OSZI_c.BLIF inst_CLK_030_H.C 1 1 -.names N_339_1.BLIF cpu_est_i_3__n.BLIF N_339 -11 1 -.names N_18.BLIF N_18_i +.names N_319.BLIF N_319_i 0 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n -11 1 -.names N_41_0.BLIF inst_RW_000_INT.D +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n 0 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n +.names un1_amiga_bus_enable_dma_high_0_0__n.BLIF un1_amiga_bus_enable_dma_high_0__n 0 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n +.names clk_000_n_sync_i_12__n.BLIF sm_amiga_i_4__n.BLIF N_282 11 1 -.names N_10.BLIF N_10_i -0 1 -.names N_119.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n -11 1 -.names N_168_i.BLIF RST_c.BLIF N_326_1 -11 1 -.names N_43_0.BLIF inst_BGACK_030_INTreg.D -0 1 -.names cpu_est_3_.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C 1 1 -.names N_326_1.BLIF sm_amiga_i_i_7__n.BLIF N_326 -11 1 -.names N_7.BLIF N_7_i +.names N_206.BLIF N_206_i 0 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D -1- 1 --1 1 -.names N_206.BLIF RST_c.BLIF N_325_1 +.names N_154_i.BLIF cpu_est_i_1__n.BLIF N_284 11 1 -.names N_46_0.BLIF inst_AS_030_000_SYNC.D +.names N_283.BLIF N_283_i 0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names N_325_1.BLIF SM_AMIGA_6_.BLIF N_325 +.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_318 11 1 -.names N_5.BLIF N_5_i -0 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n -11 1 -.names inst_CLK_000_NE_D0.BLIF N_201.BLIF N_324_1 -11 1 -.names N_47_0.BLIF inst_AS_000_INT.D -0 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C +.names CLK_OSZI_c.BLIF inst_RESET_OUT.C 1 1 -.names N_324_1.BLIF sm_amiga_i_4__n.BLIF N_324 -11 1 -.names N_4.BLIF N_4_i +.names N_281.BLIF N_281_i 0 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27 -1- 1 --1 1 -.names N_197.BLIF BERR_i.BLIF N_316_1 -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n 0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +.names pos_clk_un23_bgack_030_int_i_1_0_n.BLIF pos_clk_un23_bgack_030_int_i_1_n 0 1 -.names N_316_1.BLIF CLK_000_NE_i.BLIF N_316 +.names N_190.BLIF sm_amiga_i_2__n.BLIF N_332 11 1 -.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low -11 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n -11 1 -.names N_204.BLIF BERR_i.BLIF N_313_1 -11 1 -.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i -0 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C 1 1 -.names N_313_1.BLIF CLK_000_PE_i.BLIF N_313 -11 1 -.names un21_fpu_cs.BLIF un21_fpu_cs_i +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i 0 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28 -1- 1 --1 1 -.names N_207.BLIF RST_c.BLIF N_303_1 +.names N_195.BLIF RESET_OUT_i.BLIF N_337 11 1 -.names N_193.BLIF amiga_bus_enable_dma_low_0_un3_n +.names N_148_0.BLIF N_148 0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n -0 1 -.names N_83_i_1.BLIF RST_c.BLIF inst_CLK_030_H.D +.names CLK_000_N_SYNC_12_.BLIF N_166.BLIF N_340 11 1 -.names N_276_i.BLIF N_193.BLIF amiga_bus_enable_dma_low_0_un1_n -11 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n -11 1 -.names N_242_i.BLIF N_321_i.BLIF N_261_i_1 -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C +.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C 1 1 -.names N_261_i_1.BLIF N_322_i.BLIF RST_DLY_0_.D +.names N_341.BLIF N_341_i +0 1 +.names N_230_i.BLIF N_231_i.BLIF pos_clk_un4_clk_000_pe_0_n 11 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_24 +.names N_338.BLIF N_338_i +0 1 +.names N_235_i.BLIF N_236_i.BLIF cpu_est_2_0_1__n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +.names N_339.BLIF N_339_i +0 1 +.names N_146.BLIF sm_amiga_i_6__n.BLIF N_334 +11 1 +.names N_336.BLIF N_336_i +0 1 +.names CLK_000_P_SYNC_10_.BLIF SM_AMIGA_0_.BLIF N_336 +11 1 +.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C +1 1 +.names N_122_0.BLIF N_122 +0 1 +.names CLK_000_D_11_.BLIF clk_000_d_i_11__n +0 1 +.names N_211.BLIF N_211_i +0 1 +.names CLK_000_D_12_.BLIF clk_000_d_i_11__n.BLIF N_345 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C +1 1 +.names N_332.BLIF N_332_i +0 1 +.names clk_000_p_sync_i_10__n.BLIF SM_AMIGA_4_.BLIF N_346 +11 1 +.names N_331.BLIF N_331_i +0 1 +.names N_232_i.BLIF N_233_i.BLIF N_290_0 +11 1 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +.names N_120_0.BLIF N_120 +0 1 +.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_293_0 +11 1 +.names N_330.BLIF N_330_i +0 1 +.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names N_344_i.BLIF N_345_i.BLIF N_153_0 +11 1 +.names N_329.BLIF N_329_i +0 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +.names N_349.BLIF N_349_i +0 1 +.names sm_amiga_i_6__n.BLIF SM_AMIGA_i_7_.BLIF N_163_i +11 1 +.names N_187_0.BLIF N_187 +0 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +.names N_203_i.BLIF N_203 +0 1 +.names clk_000_n_sync_i_12__n.BLIF SM_AMIGA_5_.BLIF N_191_0 +11 1 +.names N_324.BLIF N_324_i +0 1 +.names SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m2_5__un3_n +0 1 +.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C +1 1 +.names N_199_0.BLIF N_199 +0 1 +.names BERR_i.BLIF SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m2_5__un1_n +11 1 +.names N_197_0.BLIF N_197 +0 1 +.names clk_000_p_sync_i_10__n.BLIF sm_amiga_srsts_i_0_0_m2_5__un3_n.BLIF sm_amiga_srsts_i_0_0_m2_5__un0_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +.names N_196_0.BLIF N_196 +0 1 +.names sm_amiga_srsts_i_0_0_m2_5__un1_n.BLIF sm_amiga_srsts_i_0_0_m2_5__un0_n.BLIF N_206 1- 1 -1 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 -1- 1 --1 1 -.names N_230.BLIF N_310_i.BLIF N_141_i_1 -11 1 +.names LDS_000_c.BLIF LDS_000_c_i +0 1 +.names CLK_000_P_SYNC_10_.BLIF clk_000_p_sync_i_10__n +0 1 +.names CLK_OSZI_c.BLIF inst_RW_000_INT.C +1 1 +.names UDS_000_c.BLIF UDS_000_c_i +0 1 .names DS_000_ENABLE_1_sqmuxa.BLIF DS_000_ENABLE_1_sqmuxa_i 0 1 -.names N_193.BLIF a0_dma_0_un3_n +.names N_181_i.BLIF N_181 0 1 -.names N_141_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D -11 1 -.names N_123.BLIF rw_000_int_0_un3_n +.names N_122.BLIF rw_000_int_0_un3_n 0 1 -.names pos_clk_a0_dma_3_n.BLIF N_193.BLIF a0_dma_0_un1_n -11 1 -.names N_305_i.BLIF N_307_i.BLIF N_139_i_1 -11 1 -.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_123.BLIF rw_000_int_0_un1_n -11 1 -.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 -.names N_139_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +.names N_347.BLIF N_347_i +0 1 +.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_122.BLIF rw_000_int_0_un1_n 11 1 +.names N_348.BLIF N_348_i +0 1 .names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 -1- 1 --1 1 -.names N_229.BLIF N_301_i.BLIF N_133_i_1 -11 1 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +.names N_178_i.BLIF N_178 +0 1 .names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_18 1- 1 -1 1 -.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n +.names inst_VMA_INTreg.BLIF VMA_INT_i 0 1 -.names N_133_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D +.names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D 11 1 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n +0 1 +.names N_18_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names VPA_c.BLIF VPA_c_i +0 1 +.names N_7_i.BLIF RST_c.BLIF N_46_0 +11 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C +1 1 +.names N_54_0.BLIF inst_VPA_D.D +0 1 +.names N_5_i.BLIF RST_c.BLIF N_47_0 +11 1 +.names N_5.BLIF N_5_i +0 1 +.names RST_c.BLIF VPA_c_i.BLIF N_54_0 +11 1 +.names CLK_OSZI_c.BLIF cpu_est_3_.C +1 1 +.names N_47_0.BLIF inst_AS_000_INT.D +0 1 +.names RW_c.BLIF RW_i +0 1 +.names N_7.BLIF N_7_i +0 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa +11 1 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +.names N_46_0.BLIF inst_AS_030_000_SYNC.D +0 1 +.names N_194.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_232 +11 1 +.names N_18.BLIF N_18_i +0 1 +.names N_366.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_233 +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C +1 1 +.names N_41_0.BLIF inst_RW_000_INT.D +0 1 +.names N_153.BLIF SM_AMIGA_1_.BLIF N_275 +11 1 +.names N_10.BLIF N_10_i +0 1 +.names N_191.BLIF sm_amiga_i_6__n.BLIF N_283 +11 1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +.names N_43_0.BLIF inst_BGACK_030_INTreg.D +0 1 +.names pos_clk_un3_as_030_d0_i_n.BLIF un1_SM_AMIGA_5.BLIF DS_000_ENABLE_1_sqmuxa_1 +11 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C +1 1 +.names N_55_0.BLIF inst_DTACK_D0.D +0 1 +.names a_decode_c_18__n.BLIF a_decode_i_18__n +0 1 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +0 1 +.names CLK_000_P_SYNC_10_.BLIF CYCLE_DMA_0_.BLIF N_208 +11 1 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +.names N_137_i.BLIF N_137 +0 1 +.names DTACK_c_i.BLIF RST_c.BLIF N_55_0 +11 1 +.names N_184_0.BLIF N_184 +0 1 +.names N_10_i.BLIF RST_c.BLIF N_43_0 +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C +1 1 +.names N_334.BLIF N_334_i +0 1 .names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 -.names A0_c.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n -11 1 -.names N_300_i.BLIF sm_amiga_i_5__n.BLIF N_123_0_1 -11 1 +.names N_335.BLIF N_335_i +0 1 .names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n 11 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C +.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C 1 1 -.names N_123_0_1.BLIF SM_AMIGA_i_7_.BLIF N_123_0 -11 1 +.names N_194_0.BLIF N_194 +0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n 11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 -1- 1 --1 1 -.names pos_clk_CYCLE_DMA_5_0_i_x2.BLIF AS_000_i.BLIF N_282_i_1 -11 1 +.names N_191_0.BLIF N_191 +0 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_10 1- 1 -1 1 -.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n -0 1 -.names N_282_i_1.BLIF N_210_0.BLIF CYCLE_DMA_0_.D -11 1 -.names N_279.BLIF as_030_000_sync_0_un3_n -0 1 -.names cpu_est_i_1__n.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_343_1 -11 1 -.names inst_AS_030_000_SYNC.BLIF N_279.BLIF as_030_000_sync_0_un1_n -11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF RST_DLY_1_.C +.names CLK_OSZI_c.BLIF IPL_D0_0_.C 1 1 -.names N_343_1.BLIF cpu_est_i_3__n.BLIF N_343 -11 1 -.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n -11 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_22 -1- 1 --1 1 -.names un5_ciin_10.BLIF un5_ciin_11.BLIF un5_ciin -11 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_7 -1- 1 --1 1 -.names N_275.BLIF N_275_i +.names un1_SM_AMIGA_5_i.BLIF un1_SM_AMIGA_5 0 1 -.names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_346.BLIF N_346_i +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +.names N_163_i.BLIF N_163 +0 1 +.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 11 1 +.names N_345.BLIF N_345_i +0 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names CLK_OSZI_c.BLIF IPL_D0_1_.C +1 1 +.names N_344.BLIF N_344_i +0 1 +.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un4_uds_000 +11 1 +.names N_153_0.BLIF N_153 +0 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +1 1 +.names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n +0 1 +.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un4_lds_000 +11 1 +.names N_293_0.BLIF N_293 +0 1 +.names N_293.BLIF as_000_int_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF IPL_D0_2_.C +1 1 +.names N_233.BLIF N_233_i +0 1 +.names sm_amiga_i_5__n.BLIF N_293.BLIF as_000_int_0_un1_n +11 1 +.names N_232.BLIF N_232_i +0 1 +.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +.names N_290_0.BLIF N_290 +0 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_5 +1- 1 +-1 1 +.names N_296_0.BLIF N_296 +0 1 .names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n 0 1 -.names N_193.BLIF amiga_bus_enable_dma_high_0_un3_n +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C +1 1 +.names N_284.BLIF N_284_i 0 1 -.names un22_berr_1_0.BLIF N_375.BLIF un22_berr -11 1 .names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un1_n 11 1 -.names N_275_i.BLIF N_193.BLIF amiga_bus_enable_dma_high_0_un1_n -11 1 -.names CLK_OSZI_c.BLIF RST_DLY_2_.C -1 1 -.names FPU_SENSE_i.BLIF N_375.BLIF un21_fpu_cs_1 -11 1 +.names N_285.BLIF N_285_i +0 1 .names un1_SM_AMIGA_5_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n 11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n -11 1 -.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs -11 1 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 +.names N_292_0.BLIF N_292 +0 1 .names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6 1- 1 -1 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_25 +.names N_280.BLIF N_280_i +0 1 +.names N_290.BLIF as_030_000_sync_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C +1 1 +.names N_277.BLIF N_277_i +0 1 +.names inst_AS_030_000_SYNC.BLIF N_290.BLIF as_030_000_sync_0_un1_n +11 1 +.names N_257_0.BLIF SM_AMIGA_2_.D +0 1 +.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF BG_000DFFreg.C +1 1 +.names N_235.BLIF N_235_i +0 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_7 1- 1 -1 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_375_1 -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +.names N_236.BLIF N_236_i 0 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C +1 1 +.names A_DECODE_16_.BLIF a_decode_c_16__n +1 1 +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n +0 1 +.names A_DECODE_17_.BLIF a_decode_c_17__n +1 1 +.names N_231.BLIF N_231_i +0 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 +.names A_DECODE_18_.BLIF a_decode_c_18__n +1 1 +.names N_230.BLIF N_230_i +0 1 +.names AS_000_c.BLIF CLK_000_P_SYNC_10_.BLIF N_203_i +11 1 +.names A_DECODE_19_.BLIF a_decode_c_19__n +1 1 +.names pos_clk_un4_clk_000_pe_0_n.BLIF pos_clk_un4_clk_000_pe_n +0 1 +.names N_137_i.BLIF SM_AMIGA_4_.BLIF N_187_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C +1 1 +.names A_DECODE_20_.BLIF a_decode_c_20__n +1 1 +.names N_22.BLIF N_22_i +0 1 +.names N_349_i.BLIF RST_c.BLIF N_185_i +11 1 +.names A_DECODE_21_.BLIF a_decode_c_21__n +1 1 +.names N_37_0.BLIF inst_VMA_INTreg.D +0 1 +.names N_137.BLIF sm_amiga_i_3__n.BLIF N_184_0 +11 1 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 +.names A_DECODE_22_.BLIF a_decode_c_22__n +1 1 +.names N_224.BLIF N_224_i +0 1 +.names BERR_c.BLIF clk_000_p_sync_i_10__n.BLIF N_137_i +11 1 +.names A_DECODE_23_.BLIF a_decode_c_23__n +1 1 +.names N_226.BLIF N_226_i +0 1 +.names BGACK_000_c.BLIF N_203.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C +1 1 +.names N_220.BLIF N_220_i +0 1 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names CLK_000_N_SYNC_12_.BLIF inst_CLK_000_NE_D0.D +1 1 +.names A_1_.BLIF a_c_1__n +1 1 +.names N_221.BLIF N_221_i +0 1 +.names N_137.BLIF SM_AMIGA_0_.BLIF N_349 +11 1 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +.names N_222.BLIF N_222_i +0 1 +.names N_137.BLIF SM_AMIGA_i_7_.BLIF N_335 +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C +1 1 +.names N_217.BLIF N_217_i +0 1 +.names AS_030_i.BLIF RST_c.BLIF N_323 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C +1 1 +.names BG_030.BLIF BG_030_c +1 1 +.names N_215.BLIF N_215_i +0 1 +.names N_187.BLIF sm_amiga_i_5__n.BLIF N_281 +11 1 +.names BG_000DFFreg.BLIF BG_000 +1 1 +.names N_219.BLIF N_219_i +0 1 +.names a_decode_c_19__n.BLIF a_decode_i_19__n +0 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names N_195_0.BLIF N_195 +0 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C +1 1 +.names BGACK_000.BLIF BGACK_000_c +1 1 +.names N_190_0.BLIF N_190 +0 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_12_.C +1 1 +.names CLK_030.BLIF CLK_030_c +1 1 +.names N_157_i.BLIF N_157 +0 1 +.names CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_148_0 +11 1 +.names CLK_000.BLIF CLK_000_c +1 1 +.names N_340.BLIF N_340_i +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF pos_clk_un5_bgack_030_int_d_i_n +11 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D +1 1 +.names CLK_OSZI.BLIF CLK_OSZI_c +1 1 +.names N_141_0.BLIF N_141 +0 1 +.names N_347_i.BLIF N_348_i.BLIF N_178_i +11 1 +.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT +1 1 +.names N_337.BLIF N_337_i +0 1 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_181_i +11 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C +1 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C +1 1 +.names CLK_OUT_INTreg.BLIF CLK_EXP +1 1 +.names un10_ciin.BLIF un10_ciin_i +0 1 +.names CLK_000_P_SYNC_10_.BLIF SM_AMIGA_4_.BLIF N_196_0 +11 1 +.names un21_fpu_cs_i.BLIF FPU_CS +1 1 +.names N_291_0.BLIF N_291 +0 1 +.names AS_000_DMA_i.BLIF CLK_030_i.BLIF N_197_0 +11 1 +.names FPU_SENSE.BLIF FPU_SENSE_c +1 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i +0 1 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_INTreg.D +1 1 +.names IPL_030DFF_0_reg.BLIF IPL_030_0_ +1 1 +.names N_146_0.BLIF N_146 +0 1 +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n +0 1 +.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C +1 1 +.names IPL_030DFF_1_reg.BLIF IPL_030_1_ +1 1 +.names N_149_i.BLIF N_149 +0 1 +.names SM_AMIGA_i_7_.BLIF inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C +1 1 +.names IPL_030DFF_2_reg.BLIF IPL_030_2_ +1 1 +.names N_164_i.BLIF N_164 +0 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un0_n +11 1 +.names IPL_0_.BLIF ipl_c_0__n +1 1 +.names N_166_i.BLIF N_166 +0 1 +.names un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF N_207 +1- 1 +-1 1 +.names IPL_1_.BLIF ipl_c_1__n +1 1 +.names N_172_i.BLIF N_172 +0 1 +.names CLK_000_N_SYNC_12_.BLIF SM_AMIGA_1_.BLIF N_199_0 +11 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +.names IPL_2_.BLIF ipl_c_2__n +1 1 +.names N_176_i.BLIF N_176 +0 1 +.names N_185_i.BLIF N_324_i.BLIF SM_AMIGA_0_.D +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C +1 1 +.names N_186_0.BLIF inst_BGACK_030_INT_D.D +0 1 +.names N_199.BLIF sm_amiga_i_0__n.BLIF N_324 +11 1 +.names DTACK.BLIF DTACK_c +1 1 +.names N_192_0.BLIF N_192 +0 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names vcc_n_n.BLIF AVEC +1 1 +.names N_228.BLIF N_228_i +0 1 +.names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 +11 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +.names IPL_D0_2_.BLIF G_136.X1 +1 1 +.names N_292.BLIF E +1 1 +.names N_227.BLIF N_227_i +0 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names VPA.BLIF VPA_c +1 1 +.names N_343.BLIF N_343_i +0 1 +.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_330 +11 1 +.names ipl_c_2__n.BLIF G_136.X2 +1 1 +.names inst_VMA_INTreg.BLIF VMA +1 1 +.names N_223.BLIF N_223_i +0 1 +.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_331 +11 1 +.names RST.BLIF RST_c +1 1 +.names N_225.BLIF N_225_i +0 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_341 +11 1 +.names CLK_OSZI_c.BLIF cpu_est_0_.C +1 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n +0 1 +.names CLK_000_D_10_.BLIF clk_000_d_i_10__n +0 1 +.names IPL_D0_1_.BLIF G_135.X1 +1 1 +.names N_53_0.BLIF IPL_D0_2_.D +0 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names FC_0_.BLIF fc_c_0__n +1 1 +.names N_27.BLIF N_27_i +0 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_348 +11 1 +.names ipl_c_1__n.BLIF G_135.X2 +1 1 +.names FC_1_.BLIF fc_c_1__n +1 1 +.names N_30_0.BLIF IPL_030DFF_0_reg.D +0 1 +.names N_207.BLIF N_319_i.BLIF un1_amiga_bus_enable_dma_high_0_0__n +11 1 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE +1 1 +.names N_28.BLIF N_28_i +0 1 +.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_294_0 +11 1 +.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR +1 1 +.names N_31_0.BLIF IPL_030DFF_1_reg.D +0 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_295_0 +11 1 +.names IPL_D0_0_.BLIF G_134.X1 +1 1 +.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW +1 1 +.names N_29.BLIF N_29_i +0 1 +.names CLK_030_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF N_298_0 +11 1 +.names un1_amiga_bus_enable_dma_high_0__n.BLIF AMIGA_BUS_ENABLE_HIGH +1 1 +.names N_32_0.BLIF IPL_030DFF_2_reg.D +0 1 +.names N_325_i.BLIF N_327_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C +1 1 +.names ipl_c_0__n.BLIF G_134.X2 +1 1 +.names a_c_0__n.BLIF a_c_i_0__n +0 1 +.names N_328_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names N_224_1.BLIF clk_000_p_sync_i_10__n.BLIF N_224 +11 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 +.names N_329_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names N_216_i.BLIF rst_dly_i_0__n.BLIF N_222_1 +11 1 +.names N_258_0.BLIF N_258 +0 1 +.names N_330_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF pos_clk_ds_000_dma_4_0_n +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_x2_0_.X1 +1 1 +.names N_222_1.BLIF rst_dly_i_1__n.BLIF N_222 +11 1 +.names N_357.BLIF N_357_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C +1 1 +.names N_149.BLIF N_216_i.BLIF N_215_1 +11 1 +.names N_254.BLIF N_254_i +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF CLK_000_P_SYNC_0_.D +11 1 +.names cpu_est_0_.BLIF cpu_est_0_0_x2_0_x2_0_.X2 +1 1 +.names N_215_1.BLIF rst_dly_i_2__n.BLIF N_215 +11 1 +.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n +0 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names N_214_i.BLIF N_212_i.BLIF pos_clk_ipl_1_n +11 1 +.names N_315.BLIF N_315_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF CLK_000_N_SYNC_0_.D +11 1 +.names pos_clk_ipl_1_n.BLIF N_213_i.BLIF pos_clk_ipl_n +11 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C +1 1 +.names CYCLE_DMA_1_.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X1 +1 1 +.names AS_000_i.BLIF N_200_i.BLIF N_327_1 +11 1 +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +0 1 +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 +11 1 +.names N_327_1.BLIF RW_000_c.BLIF N_327 +11 1 +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n +0 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +11 1 +.names N_208.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.X2 +1 1 +.names inst_BGACK_030_INTreg.BLIF CLK_000_c.BLIF N_319_1 +11 1 +.names N_26.BLIF N_26_i +0 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names N_319_1.BLIF SM_AMIGA_0_.BLIF N_319 +11 1 +.names N_33_0.BLIF BG_000DFFreg.D +0 1 +.names CLK_030_H_i.BLIF N_197.BLIF N_320 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C +1 1 +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_285_1 +11 1 +.names N_21.BLIF N_21_i +0 1 +.names a_c_1__n.BLIF a_i_1__n +0 1 +.names CLK_000_P_SYNC_10_.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.X1 +1 1 +.names N_285_1.BLIF cpu_est_i_3__n.BLIF N_285 +11 1 +.names N_38_0.BLIF inst_UDS_000_INT.D +0 1 +.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_321 +11 1 +.names N_184.BLIF RST_c.BLIF N_277_1 +11 1 +.names N_17.BLIF N_17_i +0 1 +.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_322 +11 1 +.names CYCLE_DMA_0_.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.X2 +1 1 +.names N_277_1.BLIF SM_AMIGA_2_.BLIF N_277 +11 1 +.names N_42_0.BLIF inst_LDS_000_INT.D +0 1 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_325 +11 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C +1 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_236_1 +11 1 +.names N_4.BLIF N_4_i +0 1 +.names BGACK_030_INT_i.BLIF N_181.BLIF N_328 +11 1 +.names N_236_1.BLIF cpu_est_i_3__n.BLIF N_236 +11 1 +.names N_48_0.BLIF inst_DSACK1_INTreg.D +0 1 +.names BGACK_030_INT_i.BLIF N_181_i.BLIF N_329 +11 1 +.names CYCLE_DMA_0_.BLIF pos_clk_un23_bgack_030_int_i_0_x2.X1 +1 1 +.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_228_1 +11 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names G_136.BLIF N_214_i +0 1 +.names N_228_1.BLIF sm_amiga_i_4__n.BLIF N_228 +11 1 +.names N_51_0.BLIF IPL_D0_0_.D +0 1 +.names ahigh_c_24__n.BLIF ahigh_i_24__n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C +1 1 +.names CYCLE_DMA_1_.BLIF pos_clk_un23_bgack_030_int_i_0_x2.X2 +1 1 +.names N_172.BLIF BERR_i.BLIF N_225_1 +11 1 +.names ipl_c_1__n.BLIF ipl_c_i_1__n +0 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 +.names N_225_1.BLIF clk_000_n_sync_i_12__n.BLIF N_225 +11 1 +.names N_52_0.BLIF IPL_D0_1_.D +0 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names N_176.BLIF BERR_i.BLIF N_224_1 +11 1 +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_53_0 +11 1 +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 +.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D +1 1 +.names N_120_0_1.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF N_120_0 +11 1 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_52_0 +11 1 +.names ahigh_c_28__n.BLIF ahigh_i_28__n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C +1 1 +.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D +1 1 +.names N_320_i.BLIF RST_c.BLIF N_106_i_1 +11 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_51_0 +11 1 +.names ahigh_c_29__n.BLIF ahigh_i_29__n +0 1 +.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D +1 1 +.names N_106_i_1.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF inst_CLK_030_H.D +11 1 +.names N_4_i.BLIF RST_c.BLIF N_48_0 +11 1 +.names ahigh_c_30__n.BLIF ahigh_i_30__n +0 1 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +.names AS_000_i.BLIF N_186_0.BLIF N_103_i_1 +11 1 +.names N_17_i.BLIF RST_c.BLIF N_42_0 +11 1 +.names ahigh_c_31__n.BLIF ahigh_i_31__n +0 1 +.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D +1 1 +.names N_103_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF CYCLE_DMA_1_.D +11 1 +.names N_21_i.BLIF RST_c.BLIF N_38_0 +11 1 +.names SIZE_DMA_1_.BLIF size_dma_i_1__n +0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C +1 1 +.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D +1 1 +.names AS_000_i.BLIF N_186_0.BLIF N_92_i_1 +11 1 +.names N_26_i.BLIF RST_c.BLIF N_33_0 +11 1 +.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size +11 1 +.names CLK_000_N_SYNC_11_.BLIF CLK_000_N_SYNC_12_.D +1 1 +.names N_92_i_1.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF CYCLE_DMA_0_.D +11 1 .names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n 0 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF N_375_2 -11 1 -.names N_280.BLIF as_000_int_0_un3_n +.names SIZE_DMA_0_.BLIF size_dma_i_0__n 0 1 +.names cpu_est_0_0_x2_0_x2_0_.BLIF cpu_est_0_.D +1 1 +.names N_206_i.BLIF N_283_i.BLIF N_140_i_1 +11 1 .names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n 11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_0_.C -1 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF N_375_3 +.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size 11 1 -.names sm_amiga_i_5__n.BLIF N_280.BLIF as_000_int_0_un1_n +.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D +1 1 +.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D 11 1 .names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names N_375_1.BLIF N_375_2.BLIF N_375_4 -11 1 -.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_10_.C +1 1 +.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D +1 1 +.names N_281_i.BLIF N_282_i.BLIF N_138_i_1 11 1 .names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26 1- 1 -1 1 -.names N_375_4.BLIF N_375_3.BLIF N_375 +.names N_196.BLIF sm_amiga_i_3__n.BLIF N_227 11 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_5 +.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D +1 1 +.names N_138_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +11 1 +.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n +0 1 +.names N_323.BLIF inst_AS_030_D0.D +0 1 +.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D +1 1 +.names N_148.BLIF CLK_000_D_11_.BLIF N_344_1 +11 1 +.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n +11 1 +.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D +0 1 +.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D +1 1 +.names N_344_1.BLIF clk_000_d_i_10__n.BLIF N_344 +11 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names G_134.BLIF N_212_i +0 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C +1 1 +.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D +1 1 +.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n +11 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 1- 1 -1 1 -.names N_26_i.BLIF RST_c.BLIF N_33_0 -11 1 -.names CLK_000_D_0_.BLIF CLK_000_D_1_.D -1 1 -.names AS_000_i.BLIF N_210_0.BLIF N_134_i_1 -11 1 -.names N_236.BLIF N_236_i +.names G_135.BLIF N_213_i 0 1 -.names N_25_i.BLIF RST_c.BLIF N_34_0 -11 1 -.names N_134_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF CYCLE_DMA_1_.D -11 1 -.names N_281.BLIF dsack1_int_0_un3_n -0 1 -.names N_22_i.BLIF RST_c.BLIF N_37_0 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_D_1_.C +.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D 1 1 -.names N_192_0.BLIF N_331_i.BLIF N_96_0_1 +.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n 11 1 -.names N_236_i.BLIF N_281.BLIF dsack1_int_0_un1_n +.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n +0 1 +.names N_322.BLIF N_322_i +0 1 +.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D +1 1 +.names CLK_000_P_SYNC_10_.BLIF cpu_est_i_0__n.BLIF N_230_1 11 1 -.names N_21_i.BLIF RST_c.BLIF N_38_0 +.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n 11 1 -.names N_96_0_1.BLIF RW_000_i.BLIF N_96_0 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n +0 1 +.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D +1 1 +.names CLK_000_P_SYNC_9_.BLIF CLK_000_P_SYNC_10_.D +1 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_230_2 +11 1 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names N_322_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un1_n +11 1 +.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D +1 1 +.names N_230_1.BLIF N_230_2.BLIF N_230_3 +11 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_17 +1- 1 +-1 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C +1 1 +.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D +1 1 +.names N_230_3.BLIF cpu_est_i_3__n.BLIF N_230 +11 1 +.names N_275.BLIF N_275_i +0 1 +.names amiga_bus_enable_dma_low_0_un1_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_24 +1- 1 +-1 1 +.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D +1 1 +.names N_146.BLIF N_172_i.BLIF N_226_1 +11 1 +.names N_258.BLIF dsack1_int_0_un3_n +0 1 +.names N_321.BLIF N_321_i +0 1 +.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D +1 1 +.names N_176_i.BLIF sm_amiga_i_0__n.BLIF N_226_2 +11 1 +.names N_275_i.BLIF N_258.BLIF dsack1_int_0_un1_n +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n +0 1 +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D +1 1 +.names N_226_1.BLIF N_226_2.BLIF N_226_3 11 1 .names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n 11 1 -.names N_20_i.BLIF RST_c.BLIF N_39_0 +.names N_321_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un1_n 11 1 -.names N_192_0.BLIF N_328_i.BLIF N_83_i_1 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C +1 1 +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D +1 1 +.names N_226_3.BLIF sm_amiga_i_3__n.BLIF N_226 11 1 .names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_4 1- 1 -1 1 -.names N_19_i.BLIF RST_c.BLIF N_40_0 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n 11 1 -.names N_317_3.BLIF sm_amiga_i_3__n.BLIF N_317 -11 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i -0 1 -.names N_17_i.BLIF RST_c.BLIF N_42_0 -11 1 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C +.names CLK_000_D_4_.BLIF CLK_000_D_5_.D 1 1 -.names inst_CLK_000_NE_D0.BLIF N_201.BLIF N_304_1 -11 1 -.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un4_lds_000 -11 1 -.names N_8_i.BLIF RST_c.BLIF N_45_0 -11 1 -.names RST_c.BLIF SM_AMIGA_3_.BLIF N_304_2 -11 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names N_3_i.BLIF RST_c.BLIF N_49_0 -11 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index 7477b47..455e408 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,440 +1,500 @@ #$ TOOL ispLEVER Classic 2.0.00.17.20.15 -#$ DATE Wed Aug 17 17:45:46 2016 +#$ DATE Fri Aug 19 00:20:41 2016 #$ MODULE bus68030 -#$ PINS 75 A_8_ A_7_ SIZE_1_ A_6_ A_5_ A_31_ A_4_ A_3_ IPL_030_2_ A_2_ IPL_030_1_ IPL_2_ \ -# IPL_030_0_ IPL_1_ FC_1_ IPL_0_ AS_030 FC_0_ AS_000 RW_000 DS_030 UDS_000 LDS_000 A0 A1 \ -# nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT \ -# CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE SIZE_0_ \ -# AMIGA_BUS_DATA_DIR A_30_ AMIGA_BUS_ENABLE_LOW A_29_ AMIGA_BUS_ENABLE_HIGH A_28_ CIIN \ -# A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_15_ A_14_ A_13_ \ -# A_12_ A_11_ A_10_ A_9_ -#$ NODES 680 N_280 N_210_0 cpu_est_0_1__un0_n N_279 N_289_0 cpu_est_0_2__un3_n N_271 \ -# N_218_0 cpu_est_0_2__un1_n N_272 cpu_est_0_2__un0_n N_276 N_242_i cpu_est_0_3__un3_n \ -# DS_000_ENABLE_1_sqmuxa_1 N_246_i cpu_est_0_3__un1_n inst_BGACK_030_INTreg N_4 \ -# N_240_i cpu_est_0_3__un0_n vcc_n_n N_5 N_241_i ipl_030_0_0__un3_n inst_VMA_INTreg N_7 \ -# ipl_030_0_0__un1_n gnd_n_n N_10 N_266_i ipl_030_0_0__un0_n un1_amiga_bus_enable_low \ -# N_18 N_267_i ipl_030_0_1__un3_n un3_size N_24 N_254_i ipl_030_0_1__un1_n un4_size N_6 \ -# N_317_i ipl_030_0_1__un0_n un4_uds_000 un1_amiga_bus_enable_low_i \ -# ipl_030_0_2__un3_n un4_lds_000 un21_fpu_cs_i N_313_i ipl_030_0_2__un1_n un5_ciin \ -# BGACK_030_INT_i N_316_i ipl_030_0_2__un0_n un4_as_000 AMIGA_BUS_ENABLE_DMA_LOW_i \ -# N_312_i a0_dma_0_un3_n un21_fpu_cs UDS_000_INT_i a0_dma_0_un1_n un22_berr \ -# LDS_000_INT_i N_347_i a0_dma_0_un0_n un6_ds_030 N_236_i N_323_i uds_000_int_0_un3_n \ -# cpu_est_2_ sm_amiga_i_5__n N_324_i uds_000_int_0_un1_n cpu_est_3_ \ -# DS_000_ENABLE_1_sqmuxa_i N_222_i uds_000_int_0_un0_n cpu_est_0_ N_276_i \ -# AS_000_DMA_i vma_int_0_un3_n cpu_est_1_ RST_i N_221_0 vma_int_0_un1_n \ -# inst_AS_000_INT a_i_19__n N_220_0 vma_int_0_un0_n SM_AMIGA_5_ a_i_18__n N_219_0 \ -# amiga_bus_enable_dma_high_0_un3_n inst_AMIGA_BUS_ENABLE_DMA_LOW size_dma_i_1__n \ -# N_216_0 amiga_bus_enable_dma_high_0_un1_n inst_AS_030_D0 size_dma_i_0__n N_290_0 \ -# amiga_bus_enable_dma_high_0_un0_n inst_nEXP_SPACE_D0reg RW_i N_212_0 \ -# bg_000_0_un3_n inst_AS_030_000_SYNC CLK_000_PE_i N_211_0 bg_000_0_un1_n \ -# inst_BGACK_030_INT_D a_i_16__n N_204_0 bg_000_0_un0_n inst_AS_000_DMA RESET_OUT_i \ -# N_351_i ds_000_dma_0_un3_n inst_DS_000_DMA BERR_i N_353_i ds_000_dma_0_un1_n \ -# CYCLE_DMA_0_ sm_amiga_i_i_7__n N_201_i ds_000_dma_0_un0_n CYCLE_DMA_1_ \ -# nEXP_SPACE_D0_i VMA_INT_i as_000_dma_0_un3_n SIZE_DMA_0_ sm_amiga_i_4__n N_197_i \ -# as_000_dma_0_un1_n SIZE_DMA_1_ FPU_SENSE_i N_196_i as_000_dma_0_un0_n inst_VPA_D \ -# AS_030_i N_193_i lds_000_int_0_un3_n inst_UDS_000_INT AS_030_D0_i N_192_0 \ -# lds_000_int_0_un1_n inst_LDS_000_INT a_i_24__n clk_000_n_sync_i_10__n \ -# lds_000_int_0_un0_n inst_CLK_OUT_PRE_D sm_amiga_i_3__n N_350_i rw_000_dma_0_un3_n \ -# inst_DTACK_D0 cpu_est_i_0__n N_188_0 rw_000_dma_0_un1_n inst_RESET_OUT \ -# cpu_est_i_3__n N_187_i rw_000_dma_0_un0_n inst_CLK_OUT_PRE_50 cpu_est_i_2__n \ -# N_185_i a_15__n CLK_000_D_1_ cpu_est_i_1__n N_182_i CLK_000_D_0_ VPA_D_i N_181_i \ -# a_14__n inst_CLK_000_PE CLK_000_NE_i CLK_OUT_PRE_D_i CLK_000_P_SYNC_9_ \ -# sm_amiga_i_1__n N_175_0 a_13__n inst_CLK_000_NE rst_dly_i_2__n N_168_i \ -# CLK_000_N_SYNC_11_ CLK_030_i AS_030_000_SYNC_i a_12__n IPL_D0_0_ rst_dly_i_0__n \ -# N_158_i IPL_D0_1_ rst_dly_i_1__n clk_000_d_i_0__n a_11__n IPL_D0_2_ clk_000_d_i_1__n \ -# N_148_i inst_CLK_000_NE_D0 DTACK_D0_i N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i \ -# N_344_i SM_AMIGA_0_ CLK_030_H_i N_144_0 a_9__n inst_AMIGA_BUS_ENABLE_DMA_HIGH \ -# sm_amiga_i_6__n N_138_0 inst_DSACK1_INTreg sm_amiga_i_2__n a_8__n AS_000_i N_342_i \ -# pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n SM_AMIGA_4_ A1_i N_124_0 \ -# inst_DS_000_ENABLE a_i_31__n N_341_i a_6__n RST_DLY_0_ a_i_29__n N_119_0 RST_DLY_1_ \ -# a_i_30__n N_340_i a_5__n RST_DLY_2_ a_i_27__n N_361_i pos_clk_un9_bg_030_n a_i_28__n \ -# cpu_est_2_0_2__n a_4__n CLK_000_P_SYNC_0_ a_i_25__n N_338_i CLK_000_P_SYNC_1_ \ -# a_i_26__n N_339_i a_3__n CLK_000_P_SYNC_2_ N_213_i cpu_est_2_0_1__n \ -# CLK_000_P_SYNC_3_ N_214_i N_332_i a_2__n CLK_000_P_SYNC_4_ N_215_i N_336_i \ -# CLK_000_P_SYNC_5_ pos_clk_un7_clk_000_pe_0_n CLK_000_P_SYNC_6_ N_275_i N_99_0 \ -# CLK_000_P_SYNC_7_ un6_ds_030_i N_331_i CLK_000_P_SYNC_8_ DS_000_DMA_i N_96_0 \ -# CLK_000_N_SYNC_0_ un4_as_000_i N_330_i CLK_000_N_SYNC_1_ AS_000_INT_i N_90_0 \ -# CLK_000_N_SYNC_2_ un4_lds_000_i N_328_i CLK_000_N_SYNC_3_ un4_uds_000_i \ -# CLK_000_N_SYNC_4_ AS_030_c N_80_0 CLK_000_N_SYNC_5_ N_325_i CLK_000_N_SYNC_6_ \ -# AS_000_c N_326_i CLK_000_N_SYNC_7_ N_258_0 CLK_000_N_SYNC_8_ RW_000_c N_217_i \ -# CLK_000_N_SYNC_9_ N_321_i CLK_000_N_SYNC_10_ N_322_i inst_RW_000_INT UDS_000_c \ -# inst_RW_000_DMA N_320_i pos_clk_un7_clk_000_pe_n LDS_000_c inst_A0_DMA un5_ciin_i \ -# pos_clk_a0_dma_3_n size_c_0__n N_61_0 SM_AMIGA_6_ N_310_i inst_CLK_030_H size_c_1__n \ -# SM_AMIGA_1_ N_305_i SM_AMIGA_3_ N_307_i SM_AMIGA_2_ N_3 N_303_i N_8 N_304_i N_283_0 \ -# N_301_i N_300_i N_123_0 N_17 N_278_i N_19 N_297_i N_20 AMIGA_BUS_DATA_DIR_c_0 N_21 \ -# N_277_i N_22 N_25 N_26 pos_clk_un8_sm_amiga_i_n N_27 A0_c_i N_28 size_c_i_1__n N_29 \ -# N_29_i N_32_0 N_28_i N_31_0 N_27_i N_30_0 ipl_c_i_2__n N_53_0 ipl_c_i_1__n N_52_0 \ -# a_c_16__n ipl_c_i_0__n N_51_0 a_c_17__n DTACK_c_i N_56_0 a_c_18__n VPA_c_i N_55_0 \ -# a_c_19__n nEXP_SPACE_c_i N_54_0 a_c_20__n N_3_i N_49_0 a_c_21__n N_8_i N_45_0 a_c_22__n \ -# N_17_i N_42_0 a_c_23__n N_19_i N_40_0 SM_AMIGA_i_7_ a_c_24__n N_20_i N_123 N_39_0 \ -# cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i G_134 \ -# N_37_0 G_135 a_c_27__n N_25_i G_136 N_34_0 N_217 a_c_28__n N_26_i N_33_0 N_61 a_c_29__n \ -# BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 \ -# N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \ -# pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c N_351_2 N_124 N_168_i_1 N_138 \ -# nEXP_SPACE_c N_192_0_1 N_144 N_192_0_2 N_158 BERR_c N_137_i_1 N_168 N_137_i_2 N_175 \ -# BG_030_c N_145_i_1 N_182 N_145_i_2 N_185 BG_000DFFreg N_145_i_3 N_187 N_260_i_1 N_188 \ -# N_260_i_2 N_192 BGACK_000_c N_259_i_1 N_193 N_259_i_2 N_197 CLK_030_c N_336_1 N_201 \ -# N_336_2 N_204 N_332_1 N_206 N_332_2 N_207 CLK_OSZI_c N_332_3 N_317_1 N_211 N_317_2 N_212 \ -# CLK_OUT_INTreg N_317_3 N_290 N_304_1 N_216 N_304_2 N_219 FPU_SENSE_c un5_ciin_1 N_220 \ -# un5_ciin_2 N_221 IPL_030DFF_0_reg un5_ciin_3 N_227 un5_ciin_4 N_229 IPL_030DFF_1_reg \ -# un5_ciin_5 N_230 un5_ciin_6 N_236 IPL_030DFF_2_reg un5_ciin_7 N_240 un5_ciin_8 N_241 \ -# ipl_c_0__n un5_ciin_9 N_242 un5_ciin_10 N_246 ipl_c_1__n un5_ciin_11 N_254 \ -# un22_berr_1_0 N_266 ipl_c_2__n un21_fpu_cs_1 N_267 N_375_1 N_275 N_375_2 N_277 DTACK_c \ -# N_375_3 N_278 N_375_4 N_297 N_134_i_1 N_300 N_96_0_1 N_301 VPA_c N_83_i_1 N_303 N_261_i_1 \ -# N_304 N_141_i_1 N_305 RST_c N_139_i_1 N_307 N_133_i_1 N_310 N_123_0_1 N_312 RW_c \ -# N_282_i_1 N_313 N_343_1 N_316 fc_c_0__n N_339_1 N_317 pos_clk_un6_bg_030_1_n N_320 \ -# fc_c_1__n N_326_1 N_321 N_325_1 N_322 N_324_1 N_323 AMIGA_BUS_DATA_DIR_c N_316_1 N_324 \ -# N_313_1 N_325 N_303_1 N_326 N_297_1 N_328 N_266_1 N_330 N_24_i N_240_1 N_331 N_35_0 \ -# pos_clk_ipl_1_n N_332 N_18_i amiga_bus_enable_dma_low_0_un3_n N_336 N_41_0 \ -# amiga_bus_enable_dma_low_0_un1_n N_338 N_10_i amiga_bus_enable_dma_low_0_un0_n \ -# N_339 N_43_0 rw_000_int_0_un3_n N_340 N_7_i rw_000_int_0_un1_n N_341 N_46_0 \ -# rw_000_int_0_un0_n N_342 N_5_i bgack_030_int_0_un3_n N_343 N_47_0 \ -# bgack_030_int_0_un1_n N_344 N_4_i bgack_030_int_0_un0_n N_345 N_48_0 \ -# as_030_000_sync_0_un3_n N_347 N_272_i as_030_000_sync_0_un1_n N_350 N_271_i \ -# as_030_000_sync_0_un0_n N_351 N_279_0 ds_000_enable_0_un3_n N_353 N_280_0 \ -# ds_000_enable_0_un1_n N_361 N_281_0 ds_000_enable_0_un0_n \ -# pos_clk_un23_bgack_030_int_i_i_a4_i_x2 N_298_i as_000_int_0_un3_n \ -# pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_size_dma_6_0_0__n as_000_int_0_un1_n \ -# cpu_est_0_0_x2_0_ N_299_i as_000_int_0_un0_n pos_clk_CYCLE_DMA_5_1_i_x2 \ -# pos_clk_size_dma_6_0_1__n dsack1_int_0_un3_n un22_berr_1 un1_as_000_i \ -# dsack1_int_0_un1_n N_375 N_358_i dsack1_int_0_un0_n N_218 pos_clk_un6_bgack_000_0_n \ -# size_dma_0_1__un3_n N_156 N_284_i size_dma_0_1__un1_n N_289 N_285_i \ -# size_dma_0_1__un0_n N_354 N_286_0 size_dma_0_0__un3_n N_205 N_88_0 \ -# size_dma_0_0__un1_n un1_SM_AMIGA_5 pos_clk_un3_as_030_d0_i_n size_dma_0_0__un0_n \ -# DS_000_ENABLE_1_sqmuxa N_156_i sm_amiga_srsts_i_0_m2_1__un3_n N_349 N_349_i \ -# sm_amiga_srsts_i_0_m2_1__un1_n pos_clk_un3_as_030_d0_n N_194_i \ -# sm_amiga_srsts_i_0_m2_1__un0_n N_286 un1_SM_AMIGA_5_i \ -# un1_amiga_bus_enable_dma_high_i_m2_0__un3_n pos_clk_un6_bgack_000_n UDS_000_c_i \ -# un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_358 LDS_000_c_i \ -# un1_amiga_bus_enable_dma_high_i_m2_0__un0_n pos_clk_size_dma_6_1__n N_205_i \ -# sm_amiga_srsts_i_0_m2_5__un3_n N_299 N_206_0 sm_amiga_srsts_i_0_m2_5__un1_n \ -# pos_clk_size_dma_6_0__n N_207_0 sm_amiga_srsts_i_0_m2_5__un0_n N_298 N_354_i \ -# cpu_est_0_1__un3_n N_281 N_208_0 cpu_est_0_1__un1_n +#$ PINS 75 A_DECODE_22_ A_DECODE_21_ SIZE_1_ A_DECODE_20_ A_DECODE_19_ AHIGH_31_ \ +# A_DECODE_18_ A_DECODE_17_ A_DECODE_23_ A_DECODE_16_ A_DECODE_15_ A_DECODE_14_ \ +# A_DECODE_13_ IPL_030_2_ A_DECODE_12_ A_DECODE_11_ IPL_2_ A_DECODE_10_ A_DECODE_9_ \ +# FC_1_ A_DECODE_8_ AS_030 A_DECODE_7_ AS_000 A_DECODE_6_ RW_000 A_DECODE_5_ DS_030 \ +# A_DECODE_4_ UDS_000 A_DECODE_3_ LDS_000 A_DECODE_2_ nEXP_SPACE A_0_ BERR IPL_030_1_ \ +# BG_030 IPL_030_0_ BG_000 IPL_1_ BGACK_030 IPL_0_ BGACK_000 FC_0_ CLK_030 A_1_ CLK_000 \ +# CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW \ +# AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH \ +# CIIN SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ AHIGH_24_ +#$ NODES 694 N_166 N_32_0 cpu_est_0_3__un0_n N_141 a_c_i_0__n cpu_est_0_2__un3_n \ +# N_226 size_c_i_1__n cpu_est_0_2__un1_n N_357 pos_clk_un10_sm_amiga_i_n \ +# cpu_est_0_2__un0_n N_219 N_258_0 sm_amiga_srsts_i_0_m2_1__un3_n N_217 N_357_i \ +# sm_amiga_srsts_i_0_m2_1__un1_n N_221 N_254_i sm_amiga_srsts_i_0_m2_1__un0_n N_220 \ +# cpu_est_2_0_2__n vma_int_0_un3_n inst_BGACK_030_INTreg N_223 N_315_i \ +# vma_int_0_un1_n vcc_n_n N_343 N_291_0 vma_int_0_un0_n inst_VMA_INTreg N_192 \ +# AS_030_000_SYNC_i cpu_est_0_1__un3_n gnd_n_n N_164 N_146_0 cpu_est_0_1__un1_n \ +# un1_amiga_bus_enable_dma_high_0__n N_291 N_149_i cpu_est_0_1__un0_n \ +# un1_amiga_bus_enable_low N_315 N_164_i sm_amiga_srsts_i_0_0_m2_5__un3_n un6_as_030 \ +# cpu_est_2_2__n N_166_i sm_amiga_srsts_i_0_0_m2_5__un1_n un3_size N_254 N_172_i \ +# sm_amiga_srsts_i_0_0_m2_5__un0_n un4_size N_258 N_176_i rw_000_int_0_un3_n \ +# un4_uds_000 N_29 N_186_0 rw_000_int_0_un1_n un4_lds_000 N_28 N_192_0 \ +# rw_000_int_0_un0_n un4_as_000 N_27 N_228_i bgack_030_int_0_un3_n un10_ciin N_4 \ +# N_227_i bgack_030_int_0_un1_n un21_fpu_cs N_17 N_343_i bgack_030_int_0_un0_n \ +# un22_berr N_21 as_000_int_0_un3_n un6_ds_030 N_26 N_223_i as_000_int_0_un1_n \ +# cpu_est_2_ pos_clk_un9_bg_030_n N_225_i as_000_int_0_un0_n cpu_est_3_ \ +# un1_amiga_bus_enable_low_i N_224_i ds_000_enable_0_un3_n cpu_est_0_ un21_fpu_cs_i \ +# N_226_i ds_000_enable_0_un1_n cpu_est_1_ N_275_i ds_000_enable_0_un0_n \ +# inst_AS_000_INT clk_000_n_sync_i_12__n N_220_i as_030_000_sync_0_un3_n \ +# inst_AMIGA_BUS_ENABLE_DMA_LOW rst_dly_i_2__n N_221_i as_030_000_sync_0_un1_n \ +# inst_AS_030_D0 rst_dly_i_1__n N_222_i as_030_000_sync_0_un0_n inst_AS_030_000_SYNC \ +# BERR_i un1_amiga_bus_enable_dma_high_0_m2_0__un3_n inst_BGACK_030_INT_D \ +# cpu_est_i_2__n N_217_i un1_amiga_bus_enable_dma_high_0_m2_0__un1_n \ +# inst_AS_000_DMA nEXP_SPACE_i N_215_i un1_amiga_bus_enable_dma_high_0_m2_0__un0_n \ +# inst_DS_000_DMA rst_dly_i_0__n N_219_i amiga_bus_enable_dma_low_0_un3_n \ +# CYCLE_DMA_0_ cpu_est_i_1__n amiga_bus_enable_dma_low_0_un1_n CYCLE_DMA_1_ \ +# cpu_est_i_0__n N_200_i amiga_bus_enable_dma_low_0_un0_n SIZE_DMA_0_ VPA_D_i N_195_0 \ +# amiga_bus_enable_dma_high_0_un3_n SIZE_DMA_1_ sm_amiga_i_3__n N_190_0 \ +# amiga_bus_enable_dma_high_0_un1_n inst_VPA_D sm_amiga_i_0__n N_157_i \ +# amiga_bus_enable_dma_high_0_un0_n inst_UDS_000_INT cpu_est_i_3__n N_154_i \ +# size_dma_0_0__un3_n inst_LDS_000_INT sm_amiga_i_1__n N_340_i size_dma_0_0__un1_n \ +# inst_CLK_OUT_PRE_D RESET_OUT_i N_141_0 size_dma_0_0__un0_n CLK_000_D_10_ \ +# BGACK_030_INT_i un3_as_030_i size_dma_0_1__un3_n CLK_000_D_11_ sm_amiga_i_2__n \ +# N_216_i size_dma_0_1__un1_n inst_DTACK_D0 sm_amiga_i_4__n N_337_i \ +# size_dma_0_1__un0_n inst_RESET_OUT clk_000_p_sync_i_10__n ds_000_dma_0_un3_n \ +# inst_CLK_OUT_PRE_50 sm_amiga_i_5__n un10_ciin_i ds_000_dma_0_un1_n CLK_000_D_1_ \ +# sm_amiga_i_i_7__n N_296_0 ds_000_dma_0_un0_n CLK_000_D_0_ clk_000_d_i_11__n \ +# un1_as_000_i as_000_dma_0_un3_n CLK_000_P_SYNC_10_ sm_amiga_i_6__n N_284_i \ +# as_000_dma_0_un1_n SM_AMIGA_5_ RW_i N_285_i as_000_dma_0_un0_n IPL_D0_0_ \ +# DS_000_ENABLE_1_sqmuxa_i N_292_0 rw_000_dma_0_un3_n IPL_D0_1_ LDS_000_INT_i N_280_i \ +# rw_000_dma_0_un1_n IPL_D0_2_ UDS_000_INT_i N_277_i rw_000_dma_0_un0_n CLK_000_D_2_ \ +# AS_030_i N_257_0 a0_dma_0_un3_n CLK_000_D_3_ AS_000_INT_i N_235_i a0_dma_0_un1_n \ +# CLK_000_D_4_ a_decode_i_19__n N_236_i a0_dma_0_un0_n CLK_000_D_5_ a_decode_i_18__n \ +# cpu_est_2_0_1__n a_decode_15__n CLK_000_D_6_ a_decode_i_16__n N_231_i CLK_000_D_7_ \ +# AS_000_i N_230_i a_decode_14__n CLK_000_D_8_ FPU_SENSE_i pos_clk_un4_clk_000_pe_0_n \ +# CLK_000_D_9_ AMIGA_BUS_ENABLE_DMA_HIGH_i N_22_i a_decode_13__n CLK_000_D_12_ \ +# CLK_030_i N_37_0 pos_clk_un6_bg_030_n DTACK_D0_i a_decode_12__n SM_AMIGA_0_ \ +# clk_000_d_i_10__n N_334_i inst_DSACK1_INTreg RW_000_i N_335_i a_decode_11__n \ +# a_i_1__n N_194_0 CLK_030_H_i N_191_0 a_decode_10__n pos_clk_ipl_n AS_000_DMA_i \ +# un1_SM_AMIGA_5_i CLK_000_N_SYNC_0_ clk_000_d_i_0__n N_346_i a_decode_9__n \ +# SM_AMIGA_4_ clk_000_d_i_1__n N_163_i inst_DS_000_ENABLE AS_030_D0_i N_345_i \ +# a_decode_8__n CLK_000_N_SYNC_12_ size_dma_i_0__n N_344_i RST_DLY_0_ size_dma_i_1__n \ +# N_153_0 a_decode_7__n RST_DLY_1_ ahigh_i_30__n pos_clk_un3_as_030_d0_i_n RST_DLY_2_ \ +# ahigh_i_31__n N_293_0 a_decode_6__n CLK_000_P_SYNC_0_ ahigh_i_28__n N_233_i \ +# CLK_000_P_SYNC_1_ ahigh_i_29__n N_232_i a_decode_5__n CLK_000_P_SYNC_2_ \ +# ahigh_i_26__n N_290_0 CLK_000_P_SYNC_3_ ahigh_i_27__n VPA_c_i a_decode_4__n \ +# CLK_000_P_SYNC_4_ ahigh_i_24__n N_54_0 CLK_000_P_SYNC_5_ ahigh_i_25__n N_5_i \ +# a_decode_3__n CLK_000_P_SYNC_6_ N_212_i N_47_0 CLK_000_P_SYNC_7_ N_213_i N_7_i \ +# a_decode_2__n CLK_000_P_SYNC_8_ N_214_i N_46_0 CLK_000_P_SYNC_9_ N_18_i \ +# CLK_000_N_SYNC_1_ N_41_0 CLK_000_N_SYNC_2_ N_321_i N_10_i CLK_000_N_SYNC_3_ N_322_i \ +# N_43_0 CLK_000_N_SYNC_4_ un6_ds_030_i DTACK_c_i CLK_000_N_SYNC_5_ DS_000_DMA_i \ +# N_55_0 CLK_000_N_SYNC_6_ un4_as_000_i pos_clk_un6_bgack_000_0_n CLK_000_N_SYNC_7_ \ +# un6_as_030_i N_137_i CLK_000_N_SYNC_8_ un4_lds_000_i N_184_0 CLK_000_N_SYNC_9_ \ +# un4_uds_000_i N_349_i CLK_000_N_SYNC_10_ AMIGA_BUS_ENABLE_DMA_LOW_i N_185_i \ +# CLK_000_N_SYNC_11_ AS_030_c N_187_0 pos_clk_un5_bgack_030_int_d_n N_203_i \ +# inst_RW_000_INT AS_000_c N_324_i inst_RW_000_DMA inst_CLK_000_NE_D0 RW_000_c N_199_0 \ +# inst_AMIGA_BUS_ENABLE_DMA_HIGH N_197_0 inst_A0_DMA N_196_0 pos_clk_a0_dma_3_n \ +# UDS_000_c LDS_000_c_i SM_AMIGA_6_ UDS_000_c_i inst_CLK_030_H LDS_000_c N_181_i \ +# SM_AMIGA_1_ N_347_i SM_AMIGA_3_ size_c_0__n N_348_i SM_AMIGA_2_ N_178_i \ +# pos_clk_ds_000_dma_4_n size_c_1__n VMA_INT_i N_3 pos_clk_un5_bgack_030_int_d_i_n \ +# N_8 ahigh_c_24__n pos_clk_un23_bgack_030_int_i_1_0_n CLK_OUT_PRE_D_i ahigh_c_25__n \ +# N_148_0 N_341_i ahigh_c_26__n N_338_i N_339_i N_19 ahigh_c_27__n N_20 N_336_i N_24 \ +# ahigh_c_28__n N_122_0 N_25 N_211_i ahigh_c_29__n N_332_i ahigh_c_30__n N_331_i N_120_0 \ +# ahigh_c_31__n N_330_i pos_clk_ds_000_dma_4_0_n N_329_i pos_clk_size_dma_6_0_1__n \ +# N_328_i pos_clk_size_dma_6_0_0__n N_325_i N_327_i AMIGA_BUS_DATA_DIR_c_0 N_320_i \ +# N_298_0 N_295_0 N_294_0 N_319_i un1_amiga_bus_enable_dma_high_0_0__n N_206_i N_283_i \ +# SM_AMIGA_i_7_ N_122 N_281_i pos_clk_size_dma_6_0__n N_282_i pos_clk_size_dma_6_1__n \ +# G_134 N_3_i G_135 N_49_0 G_136 N_8_i N_45_0 pos_clk_un23_bgack_030_int_i_1_n N_19_i \ +# N_292 N_40_0 N_294 a_decode_c_16__n N_20_i N_295 N_39_0 N_296 a_decode_c_17__n N_24_i \ +# N_298 N_35_0 N_120 a_decode_c_18__n N_25_i N_148 N_34_0 N_149 a_decode_c_19__n \ +# N_194_0_1 N_157 N_237_i_1 N_172 a_decode_c_20__n N_237_i_2 N_176 N_238_i_1 N_178 \ +# a_decode_c_21__n N_238_i_2 N_181 N_144_i_1 N_184 a_decode_c_22__n N_144_i_2 N_144_i_3 \ +# N_196 a_decode_c_23__n N_136_i_1 N_197 N_136_i_2 N_206 a_c_0__n N_176_i_1 N_207 \ +# N_146_0_1 N_211 a_c_1__n pos_clk_un10_sm_amiga_i_1_n N_215 un10_ciin_1 N_222 \ +# nEXP_SPACE_c un10_ciin_2 N_224 un10_ciin_3 N_225 BERR_c un10_ciin_4 N_227 un10_ciin_5 \ +# N_228 BG_030_c un10_ciin_6 N_236 un10_ciin_7 N_277 BG_000DFFreg un10_ciin_8 N_281 \ +# un10_ciin_9 N_282 un10_ciin_10 N_283 BGACK_000_c un10_ciin_11 N_285 N_347_1 N_318 \ +# CLK_030_c N_347_2 N_319 pos_clk_un23_bgack_030_int_i_1_0_1_n N_320 CLK_000_c \ +# pos_clk_un23_bgack_030_int_i_1_0_2_n N_321 un21_fpu_cs_1 N_322 CLK_OSZI_c \ +# un22_berr_1_0 N_323 N_366_1 N_325 N_366_2 N_327 CLK_OUT_INTreg N_366_3 N_328 N_366_4 \ +# N_329 un1_SM_AMIGA_5_i_1 N_330 FPU_SENSE_c un1_SM_AMIGA_5_i_2 N_331 N_142_i_1 N_332 \ +# IPL_030DFF_0_reg N_142_i_2 N_336 N_339_1 N_338 IPL_030DFF_1_reg N_280_1 N_339 N_280_2 \ +# N_341 IPL_030DFF_2_reg N_231_1 N_344 N_231_2 N_347 ipl_c_0__n N_230_1 N_348 N_230_2 \ +# pos_clk_un23_bgack_030_int_i_0_x2 ipl_c_1__n N_230_3 cpu_est_0_0_x2_0_x2_0_ \ +# N_226_1 pos_clk_CYCLE_DMA_5_0_i_x2 ipl_c_2__n N_226_2 pos_clk_CYCLE_DMA_5_1_i_x2 \ +# N_226_3 N_199 N_239_i_1 N_324 DTACK_c N_122_0_1 un22_berr_1 N_132_i_1 N_366 N_120_0_1 \ +# N_335 N_106_i_1 N_208 VPA_c N_103_i_1 N_203 N_92_i_1 N_187 N_140_i_1 N_137 RST_c \ +# N_138_i_1 N_349 N_344_1 pos_clk_un6_bgack_000_n pos_clk_un6_bg_030_1_n N_10 RW_c \ +# N_327_1 N_5 N_319_1 N_293 fc_c_0__n N_285_1 N_6 N_277_1 un1_SM_AMIGA_5 fc_c_1__n N_236_1 \ +# DS_000_ENABLE_1_sqmuxa_1 N_228_1 N_7 N_225_1 pos_clk_un3_as_030_d0_n \ +# AMIGA_BUS_DATA_DIR_c N_224_1 N_290 N_222_1 N_18 N_215_1 DS_000_ENABLE_1_sqmuxa \ +# pos_clk_ipl_1_n N_232 bg_000_0_un3_n N_194 BG_030_c_i bg_000_0_un1_n N_233 \ +# pos_clk_un6_bg_030_i_n bg_000_0_un0_n N_275 pos_clk_un9_bg_030_0_n \ +# uds_000_int_0_un3_n N_153 N_26_i uds_000_int_0_un1_n N_191 N_33_0 \ +# uds_000_int_0_un0_n N_334 N_21_i lds_000_int_0_un3_n N_146 N_38_0 \ +# lds_000_int_0_un1_n N_345 N_17_i lds_000_int_0_un0_n N_346 N_42_0 dsack1_int_0_un3_n \ +# N_163 N_4_i dsack1_int_0_un1_n N_22 N_48_0 dsack1_int_0_un0_n \ +# pos_clk_un4_clk_000_pe_n ipl_c_i_0__n ipl_030_0_2__un3_n cpu_est_2_1__n N_51_0 \ +# ipl_030_0_2__un1_n N_235 ipl_c_i_1__n ipl_030_0_2__un0_n N_284 N_52_0 \ +# ipl_030_0_1__un3_n N_190 ipl_c_i_2__n ipl_030_0_1__un1_n N_337 N_53_0 \ +# ipl_030_0_1__un0_n N_195 N_27_i ipl_030_0_0__un3_n N_340 N_30_0 ipl_030_0_0__un1_n \ +# N_231 N_28_i ipl_030_0_0__un0_n N_230 N_31_0 cpu_est_0_3__un3_n N_280 N_29_i \ +# cpu_est_0_3__un1_n .model bus68030 -.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ +.inputs A_DECODE_23_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \ -DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \ -A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ -A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF \ -A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF \ -A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \ -SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF \ -A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_280.BLIF N_210_0.BLIF \ -cpu_est_0_1__un0_n.BLIF N_279.BLIF N_289_0.BLIF cpu_est_0_2__un3_n.BLIF \ -N_271.BLIF N_218_0.BLIF cpu_est_0_2__un1_n.BLIF N_272.BLIF \ -cpu_est_0_2__un0_n.BLIF N_276.BLIF N_242_i.BLIF cpu_est_0_3__un3_n.BLIF \ -DS_000_ENABLE_1_sqmuxa_1.BLIF N_246_i.BLIF cpu_est_0_3__un1_n.BLIF \ -inst_BGACK_030_INTreg.BLIF N_4.BLIF N_240_i.BLIF cpu_est_0_3__un0_n.BLIF \ -vcc_n_n.BLIF N_5.BLIF N_241_i.BLIF ipl_030_0_0__un3_n.BLIF \ -inst_VMA_INTreg.BLIF N_7.BLIF ipl_030_0_0__un1_n.BLIF gnd_n_n.BLIF N_10.BLIF \ -N_266_i.BLIF ipl_030_0_0__un0_n.BLIF un1_amiga_bus_enable_low.BLIF N_18.BLIF \ -N_267_i.BLIF ipl_030_0_1__un3_n.BLIF un3_size.BLIF N_24.BLIF N_254_i.BLIF \ -ipl_030_0_1__un1_n.BLIF un4_size.BLIF N_6.BLIF N_317_i.BLIF \ -ipl_030_0_1__un0_n.BLIF un4_uds_000.BLIF un1_amiga_bus_enable_low_i.BLIF \ -ipl_030_0_2__un3_n.BLIF un4_lds_000.BLIF un21_fpu_cs_i.BLIF N_313_i.BLIF \ -ipl_030_0_2__un1_n.BLIF un5_ciin.BLIF BGACK_030_INT_i.BLIF N_316_i.BLIF \ -ipl_030_0_2__un0_n.BLIF un4_as_000.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF \ -N_312_i.BLIF a0_dma_0_un3_n.BLIF un21_fpu_cs.BLIF UDS_000_INT_i.BLIF \ -a0_dma_0_un1_n.BLIF un22_berr.BLIF LDS_000_INT_i.BLIF N_347_i.BLIF \ -a0_dma_0_un0_n.BLIF un6_ds_030.BLIF N_236_i.BLIF N_323_i.BLIF \ -uds_000_int_0_un3_n.BLIF cpu_est_2_.BLIF sm_amiga_i_5__n.BLIF N_324_i.BLIF \ -uds_000_int_0_un1_n.BLIF cpu_est_3_.BLIF DS_000_ENABLE_1_sqmuxa_i.BLIF \ -N_222_i.BLIF uds_000_int_0_un0_n.BLIF cpu_est_0_.BLIF N_276_i.BLIF \ -AS_000_DMA_i.BLIF vma_int_0_un3_n.BLIF cpu_est_1_.BLIF RST_i.BLIF N_221_0.BLIF \ -vma_int_0_un1_n.BLIF inst_AS_000_INT.BLIF a_i_19__n.BLIF N_220_0.BLIF \ -vma_int_0_un0_n.BLIF SM_AMIGA_5_.BLIF a_i_18__n.BLIF N_219_0.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ -size_dma_i_1__n.BLIF N_216_0.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF \ -inst_AS_030_D0.BLIF size_dma_i_0__n.BLIF N_290_0.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF inst_nEXP_SPACE_D0reg.BLIF RW_i.BLIF \ -N_212_0.BLIF bg_000_0_un3_n.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_PE_i.BLIF \ -N_211_0.BLIF bg_000_0_un1_n.BLIF inst_BGACK_030_INT_D.BLIF a_i_16__n.BLIF \ -N_204_0.BLIF bg_000_0_un0_n.BLIF inst_AS_000_DMA.BLIF RESET_OUT_i.BLIF \ -N_351_i.BLIF ds_000_dma_0_un3_n.BLIF inst_DS_000_DMA.BLIF BERR_i.BLIF \ -N_353_i.BLIF ds_000_dma_0_un1_n.BLIF CYCLE_DMA_0_.BLIF sm_amiga_i_i_7__n.BLIF \ -N_201_i.BLIF ds_000_dma_0_un0_n.BLIF CYCLE_DMA_1_.BLIF nEXP_SPACE_D0_i.BLIF \ -VMA_INT_i.BLIF as_000_dma_0_un3_n.BLIF SIZE_DMA_0_.BLIF sm_amiga_i_4__n.BLIF \ -N_197_i.BLIF as_000_dma_0_un1_n.BLIF SIZE_DMA_1_.BLIF FPU_SENSE_i.BLIF \ -N_196_i.BLIF as_000_dma_0_un0_n.BLIF inst_VPA_D.BLIF AS_030_i.BLIF \ -N_193_i.BLIF lds_000_int_0_un3_n.BLIF inst_UDS_000_INT.BLIF AS_030_D0_i.BLIF \ -N_192_0.BLIF lds_000_int_0_un1_n.BLIF inst_LDS_000_INT.BLIF a_i_24__n.BLIF \ -clk_000_n_sync_i_10__n.BLIF lds_000_int_0_un0_n.BLIF inst_CLK_OUT_PRE_D.BLIF \ -sm_amiga_i_3__n.BLIF N_350_i.BLIF rw_000_dma_0_un3_n.BLIF inst_DTACK_D0.BLIF \ -cpu_est_i_0__n.BLIF N_188_0.BLIF rw_000_dma_0_un1_n.BLIF inst_RESET_OUT.BLIF \ -cpu_est_i_3__n.BLIF N_187_i.BLIF rw_000_dma_0_un0_n.BLIF \ -inst_CLK_OUT_PRE_50.BLIF cpu_est_i_2__n.BLIF N_185_i.BLIF a_15__n.BLIF \ -CLK_000_D_1_.BLIF cpu_est_i_1__n.BLIF N_182_i.BLIF CLK_000_D_0_.BLIF \ -VPA_D_i.BLIF N_181_i.BLIF a_14__n.BLIF inst_CLK_000_PE.BLIF CLK_000_NE_i.BLIF \ -CLK_OUT_PRE_D_i.BLIF CLK_000_P_SYNC_9_.BLIF sm_amiga_i_1__n.BLIF N_175_0.BLIF \ -a_13__n.BLIF inst_CLK_000_NE.BLIF rst_dly_i_2__n.BLIF N_168_i.BLIF \ -CLK_000_N_SYNC_11_.BLIF CLK_030_i.BLIF AS_030_000_SYNC_i.BLIF a_12__n.BLIF \ -IPL_D0_0_.BLIF rst_dly_i_0__n.BLIF N_158_i.BLIF IPL_D0_1_.BLIF \ -rst_dly_i_1__n.BLIF clk_000_d_i_0__n.BLIF a_11__n.BLIF IPL_D0_2_.BLIF \ -clk_000_d_i_1__n.BLIF N_148_i.BLIF inst_CLK_000_NE_D0.BLIF DTACK_D0_i.BLIF \ -N_345_i.BLIF a_10__n.BLIF pos_clk_un6_bg_030_n.BLIF RW_000_i.BLIF N_344_i.BLIF \ -SM_AMIGA_0_.BLIF CLK_030_H_i.BLIF N_144_0.BLIF a_9__n.BLIF \ -inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF sm_amiga_i_6__n.BLIF N_138_0.BLIF \ -inst_DSACK1_INTreg.BLIF sm_amiga_i_2__n.BLIF a_8__n.BLIF AS_000_i.BLIF \ -N_342_i.BLIF pos_clk_ipl_n.BLIF sm_amiga_i_0__n.BLIF N_343_i.BLIF a_7__n.BLIF \ -SM_AMIGA_4_.BLIF A1_i.BLIF N_124_0.BLIF inst_DS_000_ENABLE.BLIF a_i_31__n.BLIF \ -N_341_i.BLIF a_6__n.BLIF RST_DLY_0_.BLIF a_i_29__n.BLIF N_119_0.BLIF \ -RST_DLY_1_.BLIF a_i_30__n.BLIF N_340_i.BLIF a_5__n.BLIF RST_DLY_2_.BLIF \ -a_i_27__n.BLIF N_361_i.BLIF pos_clk_un9_bg_030_n.BLIF a_i_28__n.BLIF \ -cpu_est_2_0_2__n.BLIF a_4__n.BLIF CLK_000_P_SYNC_0_.BLIF a_i_25__n.BLIF \ -N_338_i.BLIF CLK_000_P_SYNC_1_.BLIF a_i_26__n.BLIF N_339_i.BLIF a_3__n.BLIF \ -CLK_000_P_SYNC_2_.BLIF N_213_i.BLIF cpu_est_2_0_1__n.BLIF \ -CLK_000_P_SYNC_3_.BLIF N_214_i.BLIF N_332_i.BLIF a_2__n.BLIF \ -CLK_000_P_SYNC_4_.BLIF N_215_i.BLIF N_336_i.BLIF CLK_000_P_SYNC_5_.BLIF \ -pos_clk_un7_clk_000_pe_0_n.BLIF CLK_000_P_SYNC_6_.BLIF N_275_i.BLIF \ -N_99_0.BLIF CLK_000_P_SYNC_7_.BLIF un6_ds_030_i.BLIF N_331_i.BLIF \ -CLK_000_P_SYNC_8_.BLIF DS_000_DMA_i.BLIF N_96_0.BLIF CLK_000_N_SYNC_0_.BLIF \ -un4_as_000_i.BLIF N_330_i.BLIF CLK_000_N_SYNC_1_.BLIF AS_000_INT_i.BLIF \ -N_90_0.BLIF CLK_000_N_SYNC_2_.BLIF un4_lds_000_i.BLIF N_328_i.BLIF \ -CLK_000_N_SYNC_3_.BLIF un4_uds_000_i.BLIF CLK_000_N_SYNC_4_.BLIF AS_030_c.BLIF \ -N_80_0.BLIF CLK_000_N_SYNC_5_.BLIF N_325_i.BLIF CLK_000_N_SYNC_6_.BLIF \ -AS_000_c.BLIF N_326_i.BLIF CLK_000_N_SYNC_7_.BLIF N_258_0.BLIF \ -CLK_000_N_SYNC_8_.BLIF RW_000_c.BLIF N_217_i.BLIF CLK_000_N_SYNC_9_.BLIF \ -N_321_i.BLIF CLK_000_N_SYNC_10_.BLIF N_322_i.BLIF inst_RW_000_INT.BLIF \ -UDS_000_c.BLIF inst_RW_000_DMA.BLIF N_320_i.BLIF pos_clk_un7_clk_000_pe_n.BLIF \ -LDS_000_c.BLIF inst_A0_DMA.BLIF un5_ciin_i.BLIF pos_clk_a0_dma_3_n.BLIF \ -size_c_0__n.BLIF N_61_0.BLIF SM_AMIGA_6_.BLIF N_310_i.BLIF inst_CLK_030_H.BLIF \ -size_c_1__n.BLIF SM_AMIGA_1_.BLIF N_305_i.BLIF SM_AMIGA_3_.BLIF N_307_i.BLIF \ -SM_AMIGA_2_.BLIF N_3.BLIF N_303_i.BLIF N_8.BLIF N_304_i.BLIF N_283_0.BLIF \ -N_301_i.BLIF N_300_i.BLIF N_123_0.BLIF N_17.BLIF N_278_i.BLIF N_19.BLIF \ -N_297_i.BLIF N_20.BLIF AMIGA_BUS_DATA_DIR_c_0.BLIF N_21.BLIF N_277_i.BLIF \ -N_22.BLIF N_25.BLIF N_26.BLIF pos_clk_un8_sm_amiga_i_n.BLIF N_27.BLIF \ -A0_c_i.BLIF N_28.BLIF size_c_i_1__n.BLIF N_29.BLIF N_29_i.BLIF N_32_0.BLIF \ -N_28_i.BLIF N_31_0.BLIF N_27_i.BLIF N_30_0.BLIF ipl_c_i_2__n.BLIF N_53_0.BLIF \ -ipl_c_i_1__n.BLIF N_52_0.BLIF a_c_16__n.BLIF ipl_c_i_0__n.BLIF N_51_0.BLIF \ -a_c_17__n.BLIF DTACK_c_i.BLIF N_56_0.BLIF a_c_18__n.BLIF VPA_c_i.BLIF \ -N_55_0.BLIF a_c_19__n.BLIF nEXP_SPACE_c_i.BLIF N_54_0.BLIF a_c_20__n.BLIF \ -N_3_i.BLIF N_49_0.BLIF a_c_21__n.BLIF N_8_i.BLIF N_45_0.BLIF a_c_22__n.BLIF \ -N_17_i.BLIF N_42_0.BLIF a_c_23__n.BLIF N_19_i.BLIF N_40_0.BLIF \ -SM_AMIGA_i_7_.BLIF a_c_24__n.BLIF N_20_i.BLIF N_123.BLIF N_39_0.BLIF \ -cpu_est_2_1__n.BLIF a_c_25__n.BLIF N_21_i.BLIF cpu_est_2_2__n.BLIF N_38_0.BLIF \ -N_209.BLIF a_c_26__n.BLIF N_22_i.BLIF G_134.BLIF N_37_0.BLIF G_135.BLIF \ -a_c_27__n.BLIF N_25_i.BLIF G_136.BLIF N_34_0.BLIF N_217.BLIF a_c_28__n.BLIF \ -N_26_i.BLIF N_33_0.BLIF N_61.BLIF a_c_29__n.BLIF BG_030_c_i.BLIF N_127.BLIF \ -pos_clk_un6_bg_030_i_n.BLIF a_c_30__n.BLIF pos_clk_un9_bg_030_0_n.BLIF \ -N_80.BLIF N_289_0_1.BLIF a_c_31__n.BLIF un1_SM_AMIGA_5_i_1.BLIF N_90.BLIF \ -un1_SM_AMIGA_5_i_2.BLIF N_96.BLIF A0_c.BLIF pos_clk_un8_sm_amiga_i_1_n.BLIF \ -N_99.BLIF N_351_1.BLIF N_119.BLIF A1_c.BLIF N_351_2.BLIF N_124.BLIF \ -N_168_i_1.BLIF N_138.BLIF nEXP_SPACE_c.BLIF N_192_0_1.BLIF N_144.BLIF \ -N_192_0_2.BLIF N_158.BLIF BERR_c.BLIF N_137_i_1.BLIF N_168.BLIF N_137_i_2.BLIF \ -N_175.BLIF BG_030_c.BLIF N_145_i_1.BLIF N_182.BLIF N_145_i_2.BLIF N_185.BLIF \ -BG_000DFFreg.BLIF N_145_i_3.BLIF N_187.BLIF N_260_i_1.BLIF N_188.BLIF \ -N_260_i_2.BLIF N_192.BLIF BGACK_000_c.BLIF N_259_i_1.BLIF N_193.BLIF \ -N_259_i_2.BLIF N_197.BLIF CLK_030_c.BLIF N_336_1.BLIF N_201.BLIF N_336_2.BLIF \ -N_204.BLIF N_332_1.BLIF N_206.BLIF N_332_2.BLIF N_207.BLIF CLK_OSZI_c.BLIF \ -N_332_3.BLIF N_317_1.BLIF N_211.BLIF N_317_2.BLIF N_212.BLIF \ -CLK_OUT_INTreg.BLIF N_317_3.BLIF N_290.BLIF N_304_1.BLIF N_216.BLIF \ -N_304_2.BLIF N_219.BLIF FPU_SENSE_c.BLIF un5_ciin_1.BLIF N_220.BLIF \ -un5_ciin_2.BLIF N_221.BLIF IPL_030DFF_0_reg.BLIF un5_ciin_3.BLIF N_227.BLIF \ -un5_ciin_4.BLIF N_229.BLIF IPL_030DFF_1_reg.BLIF un5_ciin_5.BLIF N_230.BLIF \ -un5_ciin_6.BLIF N_236.BLIF IPL_030DFF_2_reg.BLIF un5_ciin_7.BLIF N_240.BLIF \ -un5_ciin_8.BLIF N_241.BLIF ipl_c_0__n.BLIF un5_ciin_9.BLIF N_242.BLIF \ -un5_ciin_10.BLIF N_246.BLIF ipl_c_1__n.BLIF un5_ciin_11.BLIF N_254.BLIF \ -un22_berr_1_0.BLIF N_266.BLIF ipl_c_2__n.BLIF un21_fpu_cs_1.BLIF N_267.BLIF \ -N_375_1.BLIF N_275.BLIF N_375_2.BLIF N_277.BLIF DTACK_c.BLIF N_375_3.BLIF \ -N_278.BLIF N_375_4.BLIF N_297.BLIF N_134_i_1.BLIF N_300.BLIF N_96_0_1.BLIF \ -N_301.BLIF VPA_c.BLIF N_83_i_1.BLIF N_303.BLIF N_261_i_1.BLIF N_304.BLIF \ -N_141_i_1.BLIF N_305.BLIF RST_c.BLIF N_139_i_1.BLIF N_307.BLIF N_133_i_1.BLIF \ -N_310.BLIF N_123_0_1.BLIF N_312.BLIF RW_c.BLIF N_282_i_1.BLIF N_313.BLIF \ -N_343_1.BLIF N_316.BLIF fc_c_0__n.BLIF N_339_1.BLIF N_317.BLIF \ -pos_clk_un6_bg_030_1_n.BLIF N_320.BLIF fc_c_1__n.BLIF N_326_1.BLIF N_321.BLIF \ -N_325_1.BLIF N_322.BLIF N_324_1.BLIF N_323.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ -N_316_1.BLIF N_324.BLIF N_313_1.BLIF N_325.BLIF N_303_1.BLIF N_326.BLIF \ -N_297_1.BLIF N_328.BLIF N_266_1.BLIF N_330.BLIF N_24_i.BLIF N_240_1.BLIF \ -N_331.BLIF N_35_0.BLIF pos_clk_ipl_1_n.BLIF N_332.BLIF N_18_i.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF N_336.BLIF N_41_0.BLIF \ -amiga_bus_enable_dma_low_0_un1_n.BLIF N_338.BLIF N_10_i.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_339.BLIF N_43_0.BLIF \ -rw_000_int_0_un3_n.BLIF N_340.BLIF N_7_i.BLIF rw_000_int_0_un1_n.BLIF \ -N_341.BLIF N_46_0.BLIF rw_000_int_0_un0_n.BLIF N_342.BLIF N_5_i.BLIF \ -bgack_030_int_0_un3_n.BLIF N_343.BLIF N_47_0.BLIF bgack_030_int_0_un1_n.BLIF \ -N_344.BLIF N_4_i.BLIF bgack_030_int_0_un0_n.BLIF N_345.BLIF N_48_0.BLIF \ -as_030_000_sync_0_un3_n.BLIF N_347.BLIF N_272_i.BLIF \ -as_030_000_sync_0_un1_n.BLIF N_350.BLIF N_271_i.BLIF \ -as_030_000_sync_0_un0_n.BLIF N_351.BLIF N_279_0.BLIF \ -ds_000_enable_0_un3_n.BLIF N_353.BLIF N_280_0.BLIF ds_000_enable_0_un1_n.BLIF \ -N_361.BLIF N_281_0.BLIF ds_000_enable_0_un0_n.BLIF \ -pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_298_i.BLIF \ -as_000_int_0_un3_n.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF \ -pos_clk_size_dma_6_0_0__n.BLIF as_000_int_0_un1_n.BLIF cpu_est_0_0_x2_0_.BLIF \ -N_299_i.BLIF as_000_int_0_un0_n.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF \ -pos_clk_size_dma_6_0_1__n.BLIF dsack1_int_0_un3_n.BLIF un22_berr_1.BLIF \ -un1_as_000_i.BLIF dsack1_int_0_un1_n.BLIF N_375.BLIF N_358_i.BLIF \ -dsack1_int_0_un0_n.BLIF N_218.BLIF pos_clk_un6_bgack_000_0_n.BLIF \ -size_dma_0_1__un3_n.BLIF N_156.BLIF N_284_i.BLIF size_dma_0_1__un1_n.BLIF \ -N_289.BLIF N_285_i.BLIF size_dma_0_1__un0_n.BLIF N_354.BLIF N_286_0.BLIF \ -size_dma_0_0__un3_n.BLIF N_205.BLIF N_88_0.BLIF size_dma_0_0__un1_n.BLIF \ -un1_SM_AMIGA_5.BLIF pos_clk_un3_as_030_d0_i_n.BLIF size_dma_0_0__un0_n.BLIF \ -DS_000_ENABLE_1_sqmuxa.BLIF N_156_i.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF \ -N_349.BLIF N_349_i.BLIF sm_amiga_srsts_i_0_m2_1__un1_n.BLIF \ -pos_clk_un3_as_030_d0_n.BLIF N_194_i.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF \ -N_286.BLIF un1_SM_AMIGA_5_i.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF pos_clk_un6_bgack_000_n.BLIF \ -UDS_000_c_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF N_358.BLIF \ -LDS_000_c_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF \ -pos_clk_size_dma_6_1__n.BLIF N_205_i.BLIF sm_amiga_srsts_i_0_m2_5__un3_n.BLIF \ -N_299.BLIF N_206_0.BLIF sm_amiga_srsts_i_0_m2_5__un1_n.BLIF \ -pos_clk_size_dma_6_0__n.BLIF N_207_0.BLIF sm_amiga_srsts_i_0_m2_5__un0_n.BLIF \ -N_298.BLIF N_354_i.BLIF cpu_est_0_1__un3_n.BLIF N_281.BLIF N_208_0.BLIF \ -cpu_est_0_1__un1_n.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF \ -UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ -A0.PIN.BLIF BERR.PIN.BLIF RW.PIN.BLIF +DTACK.BLIF VPA.BLIF RST.BLIF A_DECODE_22_.BLIF A_DECODE_21_.BLIF \ +A_DECODE_20_.BLIF A_DECODE_19_.BLIF A_DECODE_18_.BLIF A_DECODE_17_.BLIF \ +A_DECODE_16_.BLIF A_DECODE_15_.BLIF A_DECODE_14_.BLIF A_DECODE_13_.BLIF \ +A_DECODE_12_.BLIF A_DECODE_11_.BLIF A_DECODE_10_.BLIF A_DECODE_9_.BLIF \ +A_DECODE_8_.BLIF A_DECODE_7_.BLIF A_DECODE_6_.BLIF A_DECODE_5_.BLIF \ +A_DECODE_4_.BLIF A_DECODE_3_.BLIF A_DECODE_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \ +FC_0_.BLIF A_1_.BLIF SIZE_1_.BLIF AHIGH_31_.BLIF AS_030.BLIF AS_000.BLIF \ +RW_000.BLIF UDS_000.BLIF LDS_000.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF \ +AHIGH_30_.BLIF AHIGH_29_.BLIF AHIGH_28_.BLIF AHIGH_27_.BLIF AHIGH_26_.BLIF \ +AHIGH_25_.BLIF AHIGH_24_.BLIF A_0_.BLIF N_166.BLIF N_32_0.BLIF \ +cpu_est_0_3__un0_n.BLIF N_141.BLIF a_c_i_0__n.BLIF cpu_est_0_2__un3_n.BLIF \ +N_226.BLIF size_c_i_1__n.BLIF cpu_est_0_2__un1_n.BLIF N_357.BLIF \ +pos_clk_un10_sm_amiga_i_n.BLIF cpu_est_0_2__un0_n.BLIF N_219.BLIF N_258_0.BLIF \ +sm_amiga_srsts_i_0_m2_1__un3_n.BLIF N_217.BLIF N_357_i.BLIF \ +sm_amiga_srsts_i_0_m2_1__un1_n.BLIF N_221.BLIF N_254_i.BLIF \ +sm_amiga_srsts_i_0_m2_1__un0_n.BLIF N_220.BLIF cpu_est_2_0_2__n.BLIF \ +vma_int_0_un3_n.BLIF inst_BGACK_030_INTreg.BLIF N_223.BLIF N_315_i.BLIF \ +vma_int_0_un1_n.BLIF vcc_n_n.BLIF N_343.BLIF N_291_0.BLIF vma_int_0_un0_n.BLIF \ +inst_VMA_INTreg.BLIF N_192.BLIF AS_030_000_SYNC_i.BLIF cpu_est_0_1__un3_n.BLIF \ +gnd_n_n.BLIF N_164.BLIF N_146_0.BLIF cpu_est_0_1__un1_n.BLIF \ +un1_amiga_bus_enable_dma_high_0__n.BLIF N_291.BLIF N_149_i.BLIF \ +cpu_est_0_1__un0_n.BLIF un1_amiga_bus_enable_low.BLIF N_315.BLIF N_164_i.BLIF \ +sm_amiga_srsts_i_0_0_m2_5__un3_n.BLIF un6_as_030.BLIF cpu_est_2_2__n.BLIF \ +N_166_i.BLIF sm_amiga_srsts_i_0_0_m2_5__un1_n.BLIF un3_size.BLIF N_254.BLIF \ +N_172_i.BLIF sm_amiga_srsts_i_0_0_m2_5__un0_n.BLIF un4_size.BLIF N_258.BLIF \ +N_176_i.BLIF rw_000_int_0_un3_n.BLIF un4_uds_000.BLIF N_29.BLIF N_186_0.BLIF \ +rw_000_int_0_un1_n.BLIF un4_lds_000.BLIF N_28.BLIF N_192_0.BLIF \ +rw_000_int_0_un0_n.BLIF un4_as_000.BLIF N_27.BLIF N_228_i.BLIF \ +bgack_030_int_0_un3_n.BLIF un10_ciin.BLIF N_4.BLIF N_227_i.BLIF \ +bgack_030_int_0_un1_n.BLIF un21_fpu_cs.BLIF N_17.BLIF N_343_i.BLIF \ +bgack_030_int_0_un0_n.BLIF un22_berr.BLIF N_21.BLIF as_000_int_0_un3_n.BLIF \ +un6_ds_030.BLIF N_26.BLIF N_223_i.BLIF as_000_int_0_un1_n.BLIF cpu_est_2_.BLIF \ +pos_clk_un9_bg_030_n.BLIF N_225_i.BLIF as_000_int_0_un0_n.BLIF cpu_est_3_.BLIF \ +un1_amiga_bus_enable_low_i.BLIF N_224_i.BLIF ds_000_enable_0_un3_n.BLIF \ +cpu_est_0_.BLIF un21_fpu_cs_i.BLIF N_226_i.BLIF ds_000_enable_0_un1_n.BLIF \ +cpu_est_1_.BLIF N_275_i.BLIF ds_000_enable_0_un0_n.BLIF inst_AS_000_INT.BLIF \ +clk_000_n_sync_i_12__n.BLIF N_220_i.BLIF as_030_000_sync_0_un3_n.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF rst_dly_i_2__n.BLIF N_221_i.BLIF \ +as_030_000_sync_0_un1_n.BLIF inst_AS_030_D0.BLIF rst_dly_i_1__n.BLIF \ +N_222_i.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF \ +BERR_i.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF \ +inst_BGACK_030_INT_D.BLIF cpu_est_i_2__n.BLIF N_217_i.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF inst_AS_000_DMA.BLIF \ +nEXP_SPACE_i.BLIF N_215_i.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF inst_DS_000_DMA.BLIF \ +rst_dly_i_0__n.BLIF N_219_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF \ +CYCLE_DMA_0_.BLIF cpu_est_i_1__n.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF \ +CYCLE_DMA_1_.BLIF cpu_est_i_0__n.BLIF N_200_i.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF SIZE_DMA_0_.BLIF VPA_D_i.BLIF \ +N_195_0.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF SIZE_DMA_1_.BLIF \ +sm_amiga_i_3__n.BLIF N_190_0.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF \ +inst_VPA_D.BLIF sm_amiga_i_0__n.BLIF N_157_i.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF inst_UDS_000_INT.BLIF \ +cpu_est_i_3__n.BLIF N_154_i.BLIF size_dma_0_0__un3_n.BLIF \ +inst_LDS_000_INT.BLIF sm_amiga_i_1__n.BLIF N_340_i.BLIF \ +size_dma_0_0__un1_n.BLIF inst_CLK_OUT_PRE_D.BLIF RESET_OUT_i.BLIF N_141_0.BLIF \ +size_dma_0_0__un0_n.BLIF CLK_000_D_10_.BLIF BGACK_030_INT_i.BLIF \ +un3_as_030_i.BLIF size_dma_0_1__un3_n.BLIF CLK_000_D_11_.BLIF \ +sm_amiga_i_2__n.BLIF N_216_i.BLIF size_dma_0_1__un1_n.BLIF inst_DTACK_D0.BLIF \ +sm_amiga_i_4__n.BLIF N_337_i.BLIF size_dma_0_1__un0_n.BLIF inst_RESET_OUT.BLIF \ +clk_000_p_sync_i_10__n.BLIF ds_000_dma_0_un3_n.BLIF inst_CLK_OUT_PRE_50.BLIF \ +sm_amiga_i_5__n.BLIF un10_ciin_i.BLIF ds_000_dma_0_un1_n.BLIF \ +CLK_000_D_1_.BLIF sm_amiga_i_i_7__n.BLIF N_296_0.BLIF ds_000_dma_0_un0_n.BLIF \ +CLK_000_D_0_.BLIF clk_000_d_i_11__n.BLIF un1_as_000_i.BLIF \ +as_000_dma_0_un3_n.BLIF CLK_000_P_SYNC_10_.BLIF sm_amiga_i_6__n.BLIF \ +N_284_i.BLIF as_000_dma_0_un1_n.BLIF SM_AMIGA_5_.BLIF RW_i.BLIF N_285_i.BLIF \ +as_000_dma_0_un0_n.BLIF IPL_D0_0_.BLIF DS_000_ENABLE_1_sqmuxa_i.BLIF \ +N_292_0.BLIF rw_000_dma_0_un3_n.BLIF IPL_D0_1_.BLIF LDS_000_INT_i.BLIF \ +N_280_i.BLIF rw_000_dma_0_un1_n.BLIF IPL_D0_2_.BLIF UDS_000_INT_i.BLIF \ +N_277_i.BLIF rw_000_dma_0_un0_n.BLIF CLK_000_D_2_.BLIF AS_030_i.BLIF \ +N_257_0.BLIF a0_dma_0_un3_n.BLIF CLK_000_D_3_.BLIF AS_000_INT_i.BLIF \ +N_235_i.BLIF a0_dma_0_un1_n.BLIF CLK_000_D_4_.BLIF a_decode_i_19__n.BLIF \ +N_236_i.BLIF a0_dma_0_un0_n.BLIF CLK_000_D_5_.BLIF a_decode_i_18__n.BLIF \ +cpu_est_2_0_1__n.BLIF a_decode_15__n.BLIF CLK_000_D_6_.BLIF \ +a_decode_i_16__n.BLIF N_231_i.BLIF CLK_000_D_7_.BLIF AS_000_i.BLIF \ +N_230_i.BLIF a_decode_14__n.BLIF CLK_000_D_8_.BLIF FPU_SENSE_i.BLIF \ +pos_clk_un4_clk_000_pe_0_n.BLIF CLK_000_D_9_.BLIF \ +AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_22_i.BLIF a_decode_13__n.BLIF \ +CLK_000_D_12_.BLIF CLK_030_i.BLIF N_37_0.BLIF pos_clk_un6_bg_030_n.BLIF \ +DTACK_D0_i.BLIF a_decode_12__n.BLIF SM_AMIGA_0_.BLIF clk_000_d_i_10__n.BLIF \ +N_334_i.BLIF inst_DSACK1_INTreg.BLIF RW_000_i.BLIF N_335_i.BLIF \ +a_decode_11__n.BLIF a_i_1__n.BLIF N_194_0.BLIF CLK_030_H_i.BLIF N_191_0.BLIF \ +a_decode_10__n.BLIF pos_clk_ipl_n.BLIF AS_000_DMA_i.BLIF un1_SM_AMIGA_5_i.BLIF \ +CLK_000_N_SYNC_0_.BLIF clk_000_d_i_0__n.BLIF N_346_i.BLIF a_decode_9__n.BLIF \ +SM_AMIGA_4_.BLIF clk_000_d_i_1__n.BLIF N_163_i.BLIF inst_DS_000_ENABLE.BLIF \ +AS_030_D0_i.BLIF N_345_i.BLIF a_decode_8__n.BLIF CLK_000_N_SYNC_12_.BLIF \ +size_dma_i_0__n.BLIF N_344_i.BLIF RST_DLY_0_.BLIF size_dma_i_1__n.BLIF \ +N_153_0.BLIF a_decode_7__n.BLIF RST_DLY_1_.BLIF ahigh_i_30__n.BLIF \ +pos_clk_un3_as_030_d0_i_n.BLIF RST_DLY_2_.BLIF ahigh_i_31__n.BLIF N_293_0.BLIF \ +a_decode_6__n.BLIF CLK_000_P_SYNC_0_.BLIF ahigh_i_28__n.BLIF N_233_i.BLIF \ +CLK_000_P_SYNC_1_.BLIF ahigh_i_29__n.BLIF N_232_i.BLIF a_decode_5__n.BLIF \ +CLK_000_P_SYNC_2_.BLIF ahigh_i_26__n.BLIF N_290_0.BLIF CLK_000_P_SYNC_3_.BLIF \ +ahigh_i_27__n.BLIF VPA_c_i.BLIF a_decode_4__n.BLIF CLK_000_P_SYNC_4_.BLIF \ +ahigh_i_24__n.BLIF N_54_0.BLIF CLK_000_P_SYNC_5_.BLIF ahigh_i_25__n.BLIF \ +N_5_i.BLIF a_decode_3__n.BLIF CLK_000_P_SYNC_6_.BLIF N_212_i.BLIF N_47_0.BLIF \ +CLK_000_P_SYNC_7_.BLIF N_213_i.BLIF N_7_i.BLIF a_decode_2__n.BLIF \ +CLK_000_P_SYNC_8_.BLIF N_214_i.BLIF N_46_0.BLIF CLK_000_P_SYNC_9_.BLIF \ +N_18_i.BLIF CLK_000_N_SYNC_1_.BLIF N_41_0.BLIF CLK_000_N_SYNC_2_.BLIF \ +N_321_i.BLIF N_10_i.BLIF CLK_000_N_SYNC_3_.BLIF N_322_i.BLIF N_43_0.BLIF \ +CLK_000_N_SYNC_4_.BLIF un6_ds_030_i.BLIF DTACK_c_i.BLIF CLK_000_N_SYNC_5_.BLIF \ +DS_000_DMA_i.BLIF N_55_0.BLIF CLK_000_N_SYNC_6_.BLIF un4_as_000_i.BLIF \ +pos_clk_un6_bgack_000_0_n.BLIF CLK_000_N_SYNC_7_.BLIF un6_as_030_i.BLIF \ +N_137_i.BLIF CLK_000_N_SYNC_8_.BLIF un4_lds_000_i.BLIF N_184_0.BLIF \ +CLK_000_N_SYNC_9_.BLIF un4_uds_000_i.BLIF N_349_i.BLIF CLK_000_N_SYNC_10_.BLIF \ +AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF N_185_i.BLIF CLK_000_N_SYNC_11_.BLIF \ +AS_030_c.BLIF N_187_0.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF N_203_i.BLIF \ +inst_RW_000_INT.BLIF AS_000_c.BLIF N_324_i.BLIF inst_RW_000_DMA.BLIF \ +inst_CLK_000_NE_D0.BLIF RW_000_c.BLIF N_199_0.BLIF \ +inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_197_0.BLIF inst_A0_DMA.BLIF N_196_0.BLIF \ +pos_clk_a0_dma_3_n.BLIF UDS_000_c.BLIF LDS_000_c_i.BLIF SM_AMIGA_6_.BLIF \ +UDS_000_c_i.BLIF inst_CLK_030_H.BLIF LDS_000_c.BLIF N_181_i.BLIF \ +SM_AMIGA_1_.BLIF N_347_i.BLIF SM_AMIGA_3_.BLIF size_c_0__n.BLIF N_348_i.BLIF \ +SM_AMIGA_2_.BLIF N_178_i.BLIF pos_clk_ds_000_dma_4_n.BLIF size_c_1__n.BLIF \ +VMA_INT_i.BLIF N_3.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_8.BLIF \ +ahigh_c_24__n.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF \ +CLK_OUT_PRE_D_i.BLIF ahigh_c_25__n.BLIF N_148_0.BLIF N_341_i.BLIF \ +ahigh_c_26__n.BLIF N_338_i.BLIF N_339_i.BLIF N_19.BLIF ahigh_c_27__n.BLIF \ +N_20.BLIF N_336_i.BLIF N_24.BLIF ahigh_c_28__n.BLIF N_122_0.BLIF N_25.BLIF \ +N_211_i.BLIF ahigh_c_29__n.BLIF N_332_i.BLIF ahigh_c_30__n.BLIF N_331_i.BLIF \ +N_120_0.BLIF ahigh_c_31__n.BLIF N_330_i.BLIF pos_clk_ds_000_dma_4_0_n.BLIF \ +N_329_i.BLIF pos_clk_size_dma_6_0_1__n.BLIF N_328_i.BLIF \ +pos_clk_size_dma_6_0_0__n.BLIF N_325_i.BLIF N_327_i.BLIF \ +AMIGA_BUS_DATA_DIR_c_0.BLIF N_320_i.BLIF N_298_0.BLIF N_295_0.BLIF \ +N_294_0.BLIF N_319_i.BLIF un1_amiga_bus_enable_dma_high_0_0__n.BLIF \ +N_206_i.BLIF N_283_i.BLIF SM_AMIGA_i_7_.BLIF N_122.BLIF N_281_i.BLIF \ +pos_clk_size_dma_6_0__n.BLIF N_282_i.BLIF pos_clk_size_dma_6_1__n.BLIF \ +G_134.BLIF N_3_i.BLIF G_135.BLIF N_49_0.BLIF G_136.BLIF N_8_i.BLIF N_45_0.BLIF \ +pos_clk_un23_bgack_030_int_i_1_n.BLIF N_19_i.BLIF N_292.BLIF N_40_0.BLIF \ +N_294.BLIF a_decode_c_16__n.BLIF N_20_i.BLIF N_295.BLIF N_39_0.BLIF N_296.BLIF \ +a_decode_c_17__n.BLIF N_24_i.BLIF N_298.BLIF N_35_0.BLIF N_120.BLIF \ +a_decode_c_18__n.BLIF N_25_i.BLIF N_148.BLIF N_34_0.BLIF N_149.BLIF \ +a_decode_c_19__n.BLIF N_194_0_1.BLIF N_157.BLIF N_237_i_1.BLIF N_172.BLIF \ +a_decode_c_20__n.BLIF N_237_i_2.BLIF N_176.BLIF N_238_i_1.BLIF N_178.BLIF \ +a_decode_c_21__n.BLIF N_238_i_2.BLIF N_181.BLIF N_144_i_1.BLIF N_184.BLIF \ +a_decode_c_22__n.BLIF N_144_i_2.BLIF N_144_i_3.BLIF N_196.BLIF \ +a_decode_c_23__n.BLIF N_136_i_1.BLIF N_197.BLIF N_136_i_2.BLIF N_206.BLIF \ +a_c_0__n.BLIF N_176_i_1.BLIF N_207.BLIF N_146_0_1.BLIF N_211.BLIF \ +a_c_1__n.BLIF pos_clk_un10_sm_amiga_i_1_n.BLIF N_215.BLIF un10_ciin_1.BLIF \ +N_222.BLIF nEXP_SPACE_c.BLIF un10_ciin_2.BLIF N_224.BLIF un10_ciin_3.BLIF \ +N_225.BLIF BERR_c.BLIF un10_ciin_4.BLIF N_227.BLIF un10_ciin_5.BLIF N_228.BLIF \ +BG_030_c.BLIF un10_ciin_6.BLIF N_236.BLIF un10_ciin_7.BLIF N_277.BLIF \ +BG_000DFFreg.BLIF un10_ciin_8.BLIF N_281.BLIF un10_ciin_9.BLIF N_282.BLIF \ +un10_ciin_10.BLIF N_283.BLIF BGACK_000_c.BLIF un10_ciin_11.BLIF N_285.BLIF \ +N_347_1.BLIF N_318.BLIF CLK_030_c.BLIF N_347_2.BLIF N_319.BLIF \ +pos_clk_un23_bgack_030_int_i_1_0_1_n.BLIF N_320.BLIF CLK_000_c.BLIF \ +pos_clk_un23_bgack_030_int_i_1_0_2_n.BLIF N_321.BLIF un21_fpu_cs_1.BLIF \ +N_322.BLIF CLK_OSZI_c.BLIF un22_berr_1_0.BLIF N_323.BLIF N_366_1.BLIF \ +N_325.BLIF N_366_2.BLIF N_327.BLIF CLK_OUT_INTreg.BLIF N_366_3.BLIF N_328.BLIF \ +N_366_4.BLIF N_329.BLIF un1_SM_AMIGA_5_i_1.BLIF N_330.BLIF FPU_SENSE_c.BLIF \ +un1_SM_AMIGA_5_i_2.BLIF N_331.BLIF N_142_i_1.BLIF N_332.BLIF \ +IPL_030DFF_0_reg.BLIF N_142_i_2.BLIF N_336.BLIF N_339_1.BLIF N_338.BLIF \ +IPL_030DFF_1_reg.BLIF N_280_1.BLIF N_339.BLIF N_280_2.BLIF N_341.BLIF \ +IPL_030DFF_2_reg.BLIF N_231_1.BLIF N_344.BLIF N_231_2.BLIF N_347.BLIF \ +ipl_c_0__n.BLIF N_230_1.BLIF N_348.BLIF N_230_2.BLIF \ +pos_clk_un23_bgack_030_int_i_0_x2.BLIF ipl_c_1__n.BLIF N_230_3.BLIF \ +cpu_est_0_0_x2_0_x2_0_.BLIF N_226_1.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF \ +ipl_c_2__n.BLIF N_226_2.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF N_226_3.BLIF \ +N_199.BLIF N_239_i_1.BLIF N_324.BLIF DTACK_c.BLIF N_122_0_1.BLIF \ +un22_berr_1.BLIF N_132_i_1.BLIF N_366.BLIF N_120_0_1.BLIF N_335.BLIF \ +N_106_i_1.BLIF N_208.BLIF VPA_c.BLIF N_103_i_1.BLIF N_203.BLIF N_92_i_1.BLIF \ +N_187.BLIF N_140_i_1.BLIF N_137.BLIF RST_c.BLIF N_138_i_1.BLIF N_349.BLIF \ +N_344_1.BLIF pos_clk_un6_bgack_000_n.BLIF pos_clk_un6_bg_030_1_n.BLIF \ +N_10.BLIF RW_c.BLIF N_327_1.BLIF N_5.BLIF N_319_1.BLIF N_293.BLIF \ +fc_c_0__n.BLIF N_285_1.BLIF N_6.BLIF N_277_1.BLIF un1_SM_AMIGA_5.BLIF \ +fc_c_1__n.BLIF N_236_1.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF N_228_1.BLIF \ +N_7.BLIF N_225_1.BLIF pos_clk_un3_as_030_d0_n.BLIF AMIGA_BUS_DATA_DIR_c.BLIF \ +N_224_1.BLIF N_290.BLIF N_222_1.BLIF N_18.BLIF N_215_1.BLIF \ +DS_000_ENABLE_1_sqmuxa.BLIF pos_clk_ipl_1_n.BLIF N_232.BLIF \ +bg_000_0_un3_n.BLIF N_194.BLIF BG_030_c_i.BLIF bg_000_0_un1_n.BLIF N_233.BLIF \ +pos_clk_un6_bg_030_i_n.BLIF bg_000_0_un0_n.BLIF N_275.BLIF \ +pos_clk_un9_bg_030_0_n.BLIF uds_000_int_0_un3_n.BLIF N_153.BLIF N_26_i.BLIF \ +uds_000_int_0_un1_n.BLIF N_191.BLIF N_33_0.BLIF uds_000_int_0_un0_n.BLIF \ +N_334.BLIF N_21_i.BLIF lds_000_int_0_un3_n.BLIF N_146.BLIF N_38_0.BLIF \ +lds_000_int_0_un1_n.BLIF N_345.BLIF N_17_i.BLIF lds_000_int_0_un0_n.BLIF \ +N_346.BLIF N_42_0.BLIF dsack1_int_0_un3_n.BLIF N_163.BLIF N_4_i.BLIF \ +dsack1_int_0_un1_n.BLIF N_22.BLIF N_48_0.BLIF dsack1_int_0_un0_n.BLIF \ +pos_clk_un4_clk_000_pe_n.BLIF ipl_c_i_0__n.BLIF ipl_030_0_2__un3_n.BLIF \ +cpu_est_2_1__n.BLIF N_51_0.BLIF ipl_030_0_2__un1_n.BLIF N_235.BLIF \ +ipl_c_i_1__n.BLIF ipl_030_0_2__un0_n.BLIF N_284.BLIF N_52_0.BLIF \ +ipl_030_0_1__un3_n.BLIF N_190.BLIF ipl_c_i_2__n.BLIF ipl_030_0_1__un1_n.BLIF \ +N_337.BLIF N_53_0.BLIF ipl_030_0_1__un0_n.BLIF N_195.BLIF N_27_i.BLIF \ +ipl_030_0_0__un3_n.BLIF N_340.BLIF N_30_0.BLIF ipl_030_0_0__un1_n.BLIF \ +N_231.BLIF N_28_i.BLIF ipl_030_0_0__un0_n.BLIF N_230.BLIF N_31_0.BLIF \ +cpu_est_0_3__un3_n.BLIF N_280.BLIF N_29_i.BLIF cpu_est_0_3__un1_n.BLIF \ +AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF \ +LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF AHIGH_24_.PIN.BLIF \ +AHIGH_25_.PIN.BLIF AHIGH_26_.PIN.BLIF AHIGH_27_.PIN.BLIF AHIGH_28_.PIN.BLIF \ +AHIGH_29_.PIN.BLIF AHIGH_30_.PIN.BLIF AHIGH_31_.PIN.BLIF A_0_.PIN.BLIF \ +BERR.PIN.BLIF RW.PIN.BLIF .outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \ AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ -AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_4_.D SM_AMIGA_4_.C \ -SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D \ -SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C IPL_030DFF_0_reg.D \ +AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \ +SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \ +SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D \ +SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \ +cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D \ IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \ IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \ -IPL_D0_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C \ -SM_AMIGA_5_.D SM_AMIGA_5_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \ -CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ +IPL_D0_2_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D \ +CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C \ +CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D \ +CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C \ +CLK_000_N_SYNC_12_.D CLK_000_N_SYNC_12_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \ CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \ -SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D \ -cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C \ -CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D \ -CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C \ -CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D \ -CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C \ -CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D \ -CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C \ -CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \ -CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \ -CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \ -CLK_000_N_SYNC_9_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C \ -CLK_000_D_0_.D CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C \ -CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \ -CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C \ -CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D \ -CLK_000_P_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C inst_AS_000_INT.D \ -inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \ -inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D \ -inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D \ -inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D \ -inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C BG_000DFFreg.D \ +SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \ +CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D \ +CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C \ +CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \ +CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C \ +CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D \ +CLK_000_P_SYNC_9_.C CLK_000_P_SYNC_10_.D CLK_000_P_SYNC_10_.C \ +CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D \ +CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C \ +CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D \ +CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_D_0_.D \ +CLK_000_D_0_.C CLK_000_D_1_.D CLK_000_D_1_.C CLK_000_D_2_.D CLK_000_D_2_.C \ +CLK_000_D_3_.D CLK_000_D_3_.C CLK_000_D_4_.D CLK_000_D_4_.C CLK_000_D_5_.D \ +CLK_000_D_5_.C CLK_000_D_6_.D CLK_000_D_6_.C CLK_000_D_7_.D CLK_000_D_7_.C \ +CLK_000_D_8_.D CLK_000_D_8_.C CLK_000_D_9_.D CLK_000_D_9_.C CLK_000_D_10_.D \ +CLK_000_D_10_.C CLK_000_D_11_.D CLK_000_D_11_.C CLK_000_D_12_.D \ +CLK_000_D_12_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C CLK_000_P_SYNC_1_.D \ +CLK_000_P_SYNC_1_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \ +RST_DLY_2_.D RST_DLY_2_.C inst_CLK_030_H.D inst_CLK_030_H.C inst_RESET_OUT.D \ +inst_RESET_OUT.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_VMA_INTreg.D \ +inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D \ +inst_A0_DMA.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D \ +inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \ +inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \ +inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \ +inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \ +inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C BG_000DFFreg.D \ BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \ inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \ -inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \ -inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \ -inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C \ -inst_LDS_000_INT.D inst_LDS_000_INT.C inst_BGACK_030_INTreg.D \ -inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C \ -inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D \ -inst_BGACK_030_INT_D.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ -inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C \ -inst_CLK_000_PE.D inst_CLK_000_PE.C inst_CLK_000_NE.D inst_CLK_000_NE.C \ -inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C SIZE_1_ AS_030 AS_000 RW_000 \ -UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_280 N_210_0 cpu_est_0_1__un0_n N_279 \ -N_289_0 cpu_est_0_2__un3_n N_271 N_218_0 cpu_est_0_2__un1_n N_272 \ -cpu_est_0_2__un0_n N_276 N_242_i cpu_est_0_3__un3_n DS_000_ENABLE_1_sqmuxa_1 \ -N_246_i cpu_est_0_3__un1_n N_4 N_240_i cpu_est_0_3__un0_n vcc_n_n N_5 N_241_i \ -ipl_030_0_0__un3_n N_7 ipl_030_0_0__un1_n gnd_n_n N_10 N_266_i \ -ipl_030_0_0__un0_n un1_amiga_bus_enable_low N_18 N_267_i ipl_030_0_1__un3_n \ -un3_size N_24 N_254_i ipl_030_0_1__un1_n un4_size N_6 N_317_i \ -ipl_030_0_1__un0_n un4_uds_000 un1_amiga_bus_enable_low_i ipl_030_0_2__un3_n \ -un4_lds_000 un21_fpu_cs_i N_313_i ipl_030_0_2__un1_n un5_ciin BGACK_030_INT_i \ -N_316_i ipl_030_0_2__un0_n un4_as_000 AMIGA_BUS_ENABLE_DMA_LOW_i N_312_i \ -a0_dma_0_un3_n un21_fpu_cs UDS_000_INT_i a0_dma_0_un1_n un22_berr \ -LDS_000_INT_i N_347_i a0_dma_0_un0_n un6_ds_030 N_236_i N_323_i \ -uds_000_int_0_un3_n sm_amiga_i_5__n N_324_i uds_000_int_0_un1_n \ -DS_000_ENABLE_1_sqmuxa_i N_222_i uds_000_int_0_un0_n N_276_i AS_000_DMA_i \ -vma_int_0_un3_n RST_i N_221_0 vma_int_0_un1_n a_i_19__n N_220_0 \ -vma_int_0_un0_n a_i_18__n N_219_0 amiga_bus_enable_dma_high_0_un3_n \ -size_dma_i_1__n N_216_0 amiga_bus_enable_dma_high_0_un1_n size_dma_i_0__n \ -N_290_0 amiga_bus_enable_dma_high_0_un0_n RW_i N_212_0 bg_000_0_un3_n \ -CLK_000_PE_i N_211_0 bg_000_0_un1_n a_i_16__n N_204_0 bg_000_0_un0_n \ -RESET_OUT_i N_351_i ds_000_dma_0_un3_n BERR_i N_353_i ds_000_dma_0_un1_n \ -sm_amiga_i_i_7__n N_201_i ds_000_dma_0_un0_n nEXP_SPACE_D0_i VMA_INT_i \ -as_000_dma_0_un3_n sm_amiga_i_4__n N_197_i as_000_dma_0_un1_n FPU_SENSE_i \ -N_196_i as_000_dma_0_un0_n AS_030_i N_193_i lds_000_int_0_un3_n AS_030_D0_i \ -N_192_0 lds_000_int_0_un1_n a_i_24__n clk_000_n_sync_i_10__n \ -lds_000_int_0_un0_n sm_amiga_i_3__n N_350_i rw_000_dma_0_un3_n cpu_est_i_0__n \ -N_188_0 rw_000_dma_0_un1_n cpu_est_i_3__n N_187_i rw_000_dma_0_un0_n \ -cpu_est_i_2__n N_185_i a_15__n cpu_est_i_1__n N_182_i VPA_D_i N_181_i a_14__n \ -CLK_000_NE_i CLK_OUT_PRE_D_i sm_amiga_i_1__n N_175_0 a_13__n rst_dly_i_2__n \ -N_168_i CLK_030_i AS_030_000_SYNC_i a_12__n rst_dly_i_0__n N_158_i \ -rst_dly_i_1__n clk_000_d_i_0__n a_11__n clk_000_d_i_1__n N_148_i DTACK_D0_i \ -N_345_i a_10__n pos_clk_un6_bg_030_n RW_000_i N_344_i CLK_030_H_i N_144_0 \ -a_9__n sm_amiga_i_6__n N_138_0 sm_amiga_i_2__n a_8__n AS_000_i N_342_i \ -pos_clk_ipl_n sm_amiga_i_0__n N_343_i a_7__n A1_i N_124_0 a_i_31__n N_341_i \ -a_6__n a_i_29__n N_119_0 a_i_30__n N_340_i a_5__n a_i_27__n N_361_i \ -pos_clk_un9_bg_030_n a_i_28__n cpu_est_2_0_2__n a_4__n a_i_25__n N_338_i \ -a_i_26__n N_339_i a_3__n N_213_i cpu_est_2_0_1__n N_214_i N_332_i a_2__n \ -N_215_i N_336_i pos_clk_un7_clk_000_pe_0_n N_275_i N_99_0 un6_ds_030_i N_331_i \ -DS_000_DMA_i N_96_0 un4_as_000_i N_330_i AS_000_INT_i N_90_0 un4_lds_000_i \ -N_328_i un4_uds_000_i AS_030_c N_80_0 N_325_i AS_000_c N_326_i N_258_0 \ -RW_000_c N_217_i N_321_i N_322_i UDS_000_c N_320_i pos_clk_un7_clk_000_pe_n \ -LDS_000_c un5_ciin_i pos_clk_a0_dma_3_n size_c_0__n N_61_0 N_310_i size_c_1__n \ -N_305_i N_307_i N_3 N_303_i N_8 N_304_i N_283_0 N_301_i N_300_i N_123_0 N_17 \ -N_278_i N_19 N_297_i N_20 AMIGA_BUS_DATA_DIR_c_0 N_21 N_277_i N_22 N_25 N_26 \ -pos_clk_un8_sm_amiga_i_n N_27 A0_c_i N_28 size_c_i_1__n N_29 N_29_i N_32_0 \ -N_28_i N_31_0 N_27_i N_30_0 ipl_c_i_2__n N_53_0 ipl_c_i_1__n N_52_0 a_c_16__n \ -ipl_c_i_0__n N_51_0 a_c_17__n DTACK_c_i N_56_0 a_c_18__n VPA_c_i N_55_0 \ -a_c_19__n nEXP_SPACE_c_i N_54_0 a_c_20__n N_3_i N_49_0 a_c_21__n N_8_i N_45_0 \ -a_c_22__n N_17_i N_42_0 a_c_23__n N_19_i N_40_0 a_c_24__n N_20_i N_123 N_39_0 \ -cpu_est_2_1__n a_c_25__n N_21_i cpu_est_2_2__n N_38_0 N_209 a_c_26__n N_22_i \ -N_37_0 a_c_27__n N_25_i N_34_0 N_217 a_c_28__n N_26_i N_33_0 N_61 a_c_29__n \ -BG_030_c_i N_127 pos_clk_un6_bg_030_i_n a_c_30__n pos_clk_un9_bg_030_0_n N_80 \ -N_289_0_1 a_c_31__n un1_SM_AMIGA_5_i_1 N_90 un1_SM_AMIGA_5_i_2 N_96 A0_c \ -pos_clk_un8_sm_amiga_i_1_n N_99 N_351_1 N_119 A1_c N_351_2 N_124 N_168_i_1 \ -N_138 nEXP_SPACE_c N_192_0_1 N_144 N_192_0_2 N_158 BERR_c N_137_i_1 N_168 \ -N_137_i_2 N_175 BG_030_c N_145_i_1 N_182 N_145_i_2 N_185 N_145_i_3 N_187 \ -N_260_i_1 N_188 N_260_i_2 N_192 BGACK_000_c N_259_i_1 N_193 N_259_i_2 N_197 \ -CLK_030_c N_336_1 N_201 N_336_2 N_204 N_332_1 N_206 N_332_2 N_207 CLK_OSZI_c \ -N_332_3 N_317_1 N_211 N_317_2 N_212 N_317_3 N_290 N_304_1 N_216 N_304_2 N_219 \ -FPU_SENSE_c un5_ciin_1 N_220 un5_ciin_2 N_221 un5_ciin_3 N_227 un5_ciin_4 \ -N_229 un5_ciin_5 N_230 un5_ciin_6 N_236 un5_ciin_7 N_240 un5_ciin_8 N_241 \ -ipl_c_0__n un5_ciin_9 N_242 un5_ciin_10 N_246 ipl_c_1__n un5_ciin_11 N_254 \ -un22_berr_1_0 N_266 ipl_c_2__n un21_fpu_cs_1 N_267 N_375_1 N_275 N_375_2 N_277 \ -DTACK_c N_375_3 N_278 N_375_4 N_297 N_134_i_1 N_300 N_96_0_1 N_301 VPA_c \ -N_83_i_1 N_303 N_261_i_1 N_304 N_141_i_1 N_305 RST_c N_139_i_1 N_307 N_133_i_1 \ -N_310 N_123_0_1 N_312 RW_c N_282_i_1 N_313 N_343_1 N_316 fc_c_0__n N_339_1 \ -N_317 pos_clk_un6_bg_030_1_n N_320 fc_c_1__n N_326_1 N_321 N_325_1 N_322 \ -N_324_1 N_323 AMIGA_BUS_DATA_DIR_c N_316_1 N_324 N_313_1 N_325 N_303_1 N_326 \ -N_297_1 N_328 N_266_1 N_330 N_24_i N_240_1 N_331 N_35_0 pos_clk_ipl_1_n N_332 \ -N_18_i amiga_bus_enable_dma_low_0_un3_n N_336 N_41_0 \ -amiga_bus_enable_dma_low_0_un1_n N_338 N_10_i amiga_bus_enable_dma_low_0_un0_n \ -N_339 N_43_0 rw_000_int_0_un3_n N_340 N_7_i rw_000_int_0_un1_n N_341 N_46_0 \ -rw_000_int_0_un0_n N_342 N_5_i bgack_030_int_0_un3_n N_343 N_47_0 \ -bgack_030_int_0_un1_n N_344 N_4_i bgack_030_int_0_un0_n N_345 N_48_0 \ -as_030_000_sync_0_un3_n N_347 N_272_i as_030_000_sync_0_un1_n N_350 N_271_i \ -as_030_000_sync_0_un0_n N_351 N_279_0 ds_000_enable_0_un3_n N_353 N_280_0 \ -ds_000_enable_0_un1_n N_361 N_281_0 ds_000_enable_0_un0_n N_298_i \ -as_000_int_0_un3_n pos_clk_size_dma_6_0_0__n as_000_int_0_un1_n N_299_i \ -as_000_int_0_un0_n pos_clk_size_dma_6_0_1__n dsack1_int_0_un3_n un22_berr_1 \ -un1_as_000_i dsack1_int_0_un1_n N_375 N_358_i dsack1_int_0_un0_n N_218 \ -pos_clk_un6_bgack_000_0_n size_dma_0_1__un3_n N_156 N_284_i \ -size_dma_0_1__un1_n N_289 N_285_i size_dma_0_1__un0_n N_354 N_286_0 \ -size_dma_0_0__un3_n N_205 N_88_0 size_dma_0_0__un1_n un1_SM_AMIGA_5 \ -pos_clk_un3_as_030_d0_i_n size_dma_0_0__un0_n DS_000_ENABLE_1_sqmuxa N_156_i \ -sm_amiga_srsts_i_0_m2_1__un3_n N_349 N_349_i sm_amiga_srsts_i_0_m2_1__un1_n \ -pos_clk_un3_as_030_d0_n N_194_i sm_amiga_srsts_i_0_m2_1__un0_n N_286 \ -un1_SM_AMIGA_5_i un1_amiga_bus_enable_dma_high_i_m2_0__un3_n \ -pos_clk_un6_bgack_000_n UDS_000_c_i \ -un1_amiga_bus_enable_dma_high_i_m2_0__un1_n N_358 LDS_000_c_i \ -un1_amiga_bus_enable_dma_high_i_m2_0__un0_n pos_clk_size_dma_6_1__n N_205_i \ -sm_amiga_srsts_i_0_m2_5__un3_n N_299 N_206_0 sm_amiga_srsts_i_0_m2_5__un1_n \ -pos_clk_size_dma_6_0__n N_207_0 sm_amiga_srsts_i_0_m2_5__un0_n N_298 N_354_i \ -cpu_est_0_1__un3_n N_281 N_208_0 cpu_est_0_1__un1_n AS_030.OE AS_000.OE \ -RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE \ -DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_134 G_135 G_136 \ -pos_clk_un23_bgack_030_int_i_i_a4_i_x2 pos_clk_CYCLE_DMA_5_0_i_x2 \ -cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 -.names N_139_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \ +inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_OUT_PRE_D.D \ +inst_CLK_OUT_PRE_D.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C inst_CLK_OUT_PRE_50.D \ +inst_CLK_OUT_PRE_50.C SIZE_1_ AHIGH_31_ AS_030 AS_000 RW_000 UDS_000 LDS_000 \ +BERR RW SIZE_0_ AHIGH_30_ AHIGH_29_ AHIGH_28_ AHIGH_27_ AHIGH_26_ AHIGH_25_ \ +AHIGH_24_ A_0_ N_166 N_32_0 cpu_est_0_3__un0_n N_141 a_c_i_0__n \ +cpu_est_0_2__un3_n N_226 size_c_i_1__n cpu_est_0_2__un1_n N_357 \ +pos_clk_un10_sm_amiga_i_n cpu_est_0_2__un0_n N_219 N_258_0 \ +sm_amiga_srsts_i_0_m2_1__un3_n N_217 N_357_i sm_amiga_srsts_i_0_m2_1__un1_n \ +N_221 N_254_i sm_amiga_srsts_i_0_m2_1__un0_n N_220 cpu_est_2_0_2__n \ +vma_int_0_un3_n N_223 N_315_i vma_int_0_un1_n vcc_n_n N_343 N_291_0 \ +vma_int_0_un0_n N_192 AS_030_000_SYNC_i cpu_est_0_1__un3_n gnd_n_n N_164 \ +N_146_0 cpu_est_0_1__un1_n un1_amiga_bus_enable_dma_high_0__n N_291 N_149_i \ +cpu_est_0_1__un0_n un1_amiga_bus_enable_low N_315 N_164_i \ +sm_amiga_srsts_i_0_0_m2_5__un3_n un6_as_030 cpu_est_2_2__n N_166_i \ +sm_amiga_srsts_i_0_0_m2_5__un1_n un3_size N_254 N_172_i \ +sm_amiga_srsts_i_0_0_m2_5__un0_n un4_size N_258 N_176_i rw_000_int_0_un3_n \ +un4_uds_000 N_29 N_186_0 rw_000_int_0_un1_n un4_lds_000 N_28 N_192_0 \ +rw_000_int_0_un0_n un4_as_000 N_27 N_228_i bgack_030_int_0_un3_n un10_ciin N_4 \ +N_227_i bgack_030_int_0_un1_n un21_fpu_cs N_17 N_343_i bgack_030_int_0_un0_n \ +un22_berr N_21 as_000_int_0_un3_n un6_ds_030 N_26 N_223_i as_000_int_0_un1_n \ +pos_clk_un9_bg_030_n N_225_i as_000_int_0_un0_n un1_amiga_bus_enable_low_i \ +N_224_i ds_000_enable_0_un3_n un21_fpu_cs_i N_226_i ds_000_enable_0_un1_n \ +N_275_i ds_000_enable_0_un0_n clk_000_n_sync_i_12__n N_220_i \ +as_030_000_sync_0_un3_n rst_dly_i_2__n N_221_i as_030_000_sync_0_un1_n \ +rst_dly_i_1__n N_222_i as_030_000_sync_0_un0_n BERR_i \ +un1_amiga_bus_enable_dma_high_0_m2_0__un3_n cpu_est_i_2__n N_217_i \ +un1_amiga_bus_enable_dma_high_0_m2_0__un1_n nEXP_SPACE_i N_215_i \ +un1_amiga_bus_enable_dma_high_0_m2_0__un0_n rst_dly_i_0__n N_219_i \ +amiga_bus_enable_dma_low_0_un3_n cpu_est_i_1__n \ +amiga_bus_enable_dma_low_0_un1_n cpu_est_i_0__n N_200_i \ +amiga_bus_enable_dma_low_0_un0_n VPA_D_i N_195_0 \ +amiga_bus_enable_dma_high_0_un3_n sm_amiga_i_3__n N_190_0 \ +amiga_bus_enable_dma_high_0_un1_n sm_amiga_i_0__n N_157_i \ +amiga_bus_enable_dma_high_0_un0_n cpu_est_i_3__n N_154_i size_dma_0_0__un3_n \ +sm_amiga_i_1__n N_340_i size_dma_0_0__un1_n RESET_OUT_i N_141_0 \ +size_dma_0_0__un0_n BGACK_030_INT_i un3_as_030_i size_dma_0_1__un3_n \ +sm_amiga_i_2__n N_216_i size_dma_0_1__un1_n sm_amiga_i_4__n N_337_i \ +size_dma_0_1__un0_n clk_000_p_sync_i_10__n ds_000_dma_0_un3_n sm_amiga_i_5__n \ +un10_ciin_i ds_000_dma_0_un1_n sm_amiga_i_i_7__n N_296_0 ds_000_dma_0_un0_n \ +clk_000_d_i_11__n un1_as_000_i as_000_dma_0_un3_n sm_amiga_i_6__n N_284_i \ +as_000_dma_0_un1_n RW_i N_285_i as_000_dma_0_un0_n DS_000_ENABLE_1_sqmuxa_i \ +N_292_0 rw_000_dma_0_un3_n LDS_000_INT_i N_280_i rw_000_dma_0_un1_n \ +UDS_000_INT_i N_277_i rw_000_dma_0_un0_n AS_030_i N_257_0 a0_dma_0_un3_n \ +AS_000_INT_i N_235_i a0_dma_0_un1_n a_decode_i_19__n N_236_i a0_dma_0_un0_n \ +a_decode_i_18__n cpu_est_2_0_1__n a_decode_15__n a_decode_i_16__n N_231_i \ +AS_000_i N_230_i a_decode_14__n FPU_SENSE_i pos_clk_un4_clk_000_pe_0_n \ +AMIGA_BUS_ENABLE_DMA_HIGH_i N_22_i a_decode_13__n CLK_030_i N_37_0 \ +pos_clk_un6_bg_030_n DTACK_D0_i a_decode_12__n clk_000_d_i_10__n N_334_i \ +RW_000_i N_335_i a_decode_11__n a_i_1__n N_194_0 CLK_030_H_i N_191_0 \ +a_decode_10__n pos_clk_ipl_n AS_000_DMA_i un1_SM_AMIGA_5_i clk_000_d_i_0__n \ +N_346_i a_decode_9__n clk_000_d_i_1__n N_163_i AS_030_D0_i N_345_i \ +a_decode_8__n size_dma_i_0__n N_344_i size_dma_i_1__n N_153_0 a_decode_7__n \ +ahigh_i_30__n pos_clk_un3_as_030_d0_i_n ahigh_i_31__n N_293_0 a_decode_6__n \ +ahigh_i_28__n N_233_i ahigh_i_29__n N_232_i a_decode_5__n ahigh_i_26__n \ +N_290_0 ahigh_i_27__n VPA_c_i a_decode_4__n ahigh_i_24__n N_54_0 ahigh_i_25__n \ +N_5_i a_decode_3__n N_212_i N_47_0 N_213_i N_7_i a_decode_2__n N_214_i N_46_0 \ +N_18_i N_41_0 N_321_i N_10_i N_322_i N_43_0 un6_ds_030_i DTACK_c_i \ +DS_000_DMA_i N_55_0 un4_as_000_i pos_clk_un6_bgack_000_0_n un6_as_030_i \ +N_137_i un4_lds_000_i N_184_0 un4_uds_000_i N_349_i AMIGA_BUS_ENABLE_DMA_LOW_i \ +N_185_i AS_030_c N_187_0 pos_clk_un5_bgack_030_int_d_n N_203_i AS_000_c \ +N_324_i RW_000_c N_199_0 N_197_0 N_196_0 pos_clk_a0_dma_3_n UDS_000_c \ +LDS_000_c_i UDS_000_c_i LDS_000_c N_181_i N_347_i size_c_0__n N_348_i N_178_i \ +pos_clk_ds_000_dma_4_n size_c_1__n VMA_INT_i N_3 \ +pos_clk_un5_bgack_030_int_d_i_n N_8 ahigh_c_24__n \ +pos_clk_un23_bgack_030_int_i_1_0_n CLK_OUT_PRE_D_i ahigh_c_25__n N_148_0 \ +N_341_i ahigh_c_26__n N_338_i N_339_i N_19 ahigh_c_27__n N_20 N_336_i N_24 \ +ahigh_c_28__n N_122_0 N_25 N_211_i ahigh_c_29__n N_332_i ahigh_c_30__n N_331_i \ +N_120_0 ahigh_c_31__n N_330_i pos_clk_ds_000_dma_4_0_n N_329_i \ +pos_clk_size_dma_6_0_1__n N_328_i pos_clk_size_dma_6_0_0__n N_325_i N_327_i \ +AMIGA_BUS_DATA_DIR_c_0 N_320_i N_298_0 N_295_0 N_294_0 N_319_i \ +un1_amiga_bus_enable_dma_high_0_0__n N_206_i N_283_i N_122 N_281_i \ +pos_clk_size_dma_6_0__n N_282_i pos_clk_size_dma_6_1__n N_3_i N_49_0 N_8_i \ +N_45_0 pos_clk_un23_bgack_030_int_i_1_n N_19_i N_292 N_40_0 N_294 \ +a_decode_c_16__n N_20_i N_295 N_39_0 N_296 a_decode_c_17__n N_24_i N_298 \ +N_35_0 N_120 a_decode_c_18__n N_25_i N_148 N_34_0 N_149 a_decode_c_19__n \ +N_194_0_1 N_157 N_237_i_1 N_172 a_decode_c_20__n N_237_i_2 N_176 N_238_i_1 \ +N_178 a_decode_c_21__n N_238_i_2 N_181 N_144_i_1 N_184 a_decode_c_22__n \ +N_144_i_2 N_144_i_3 N_196 a_decode_c_23__n N_136_i_1 N_197 N_136_i_2 N_206 \ +a_c_0__n N_176_i_1 N_207 N_146_0_1 N_211 a_c_1__n pos_clk_un10_sm_amiga_i_1_n \ +N_215 un10_ciin_1 N_222 nEXP_SPACE_c un10_ciin_2 N_224 un10_ciin_3 N_225 \ +BERR_c un10_ciin_4 N_227 un10_ciin_5 N_228 BG_030_c un10_ciin_6 N_236 \ +un10_ciin_7 N_277 un10_ciin_8 N_281 un10_ciin_9 N_282 un10_ciin_10 N_283 \ +BGACK_000_c un10_ciin_11 N_285 N_347_1 N_318 CLK_030_c N_347_2 N_319 \ +pos_clk_un23_bgack_030_int_i_1_0_1_n N_320 CLK_000_c \ +pos_clk_un23_bgack_030_int_i_1_0_2_n N_321 un21_fpu_cs_1 N_322 CLK_OSZI_c \ +un22_berr_1_0 N_323 N_366_1 N_325 N_366_2 N_327 N_366_3 N_328 N_366_4 N_329 \ +un1_SM_AMIGA_5_i_1 N_330 FPU_SENSE_c un1_SM_AMIGA_5_i_2 N_331 N_142_i_1 N_332 \ +N_142_i_2 N_336 N_339_1 N_338 N_280_1 N_339 N_280_2 N_341 N_231_1 N_344 \ +N_231_2 N_347 ipl_c_0__n N_230_1 N_348 N_230_2 ipl_c_1__n N_230_3 N_226_1 \ +ipl_c_2__n N_226_2 N_226_3 N_199 N_239_i_1 N_324 DTACK_c N_122_0_1 un22_berr_1 \ +N_132_i_1 N_366 N_120_0_1 N_335 N_106_i_1 N_208 VPA_c N_103_i_1 N_203 N_92_i_1 \ +N_187 N_140_i_1 N_137 RST_c N_138_i_1 N_349 N_344_1 pos_clk_un6_bgack_000_n \ +pos_clk_un6_bg_030_1_n N_10 RW_c N_327_1 N_5 N_319_1 N_293 fc_c_0__n N_285_1 \ +N_6 N_277_1 un1_SM_AMIGA_5 fc_c_1__n N_236_1 DS_000_ENABLE_1_sqmuxa_1 N_228_1 \ +N_7 N_225_1 pos_clk_un3_as_030_d0_n AMIGA_BUS_DATA_DIR_c N_224_1 N_290 N_222_1 \ +N_18 N_215_1 DS_000_ENABLE_1_sqmuxa pos_clk_ipl_1_n N_232 bg_000_0_un3_n N_194 \ +BG_030_c_i bg_000_0_un1_n N_233 pos_clk_un6_bg_030_i_n bg_000_0_un0_n N_275 \ +pos_clk_un9_bg_030_0_n uds_000_int_0_un3_n N_153 N_26_i uds_000_int_0_un1_n \ +N_191 N_33_0 uds_000_int_0_un0_n N_334 N_21_i lds_000_int_0_un3_n N_146 N_38_0 \ +lds_000_int_0_un1_n N_345 N_17_i lds_000_int_0_un0_n N_346 N_42_0 \ +dsack1_int_0_un3_n N_163 N_4_i dsack1_int_0_un1_n N_22 N_48_0 \ +dsack1_int_0_un0_n pos_clk_un4_clk_000_pe_n ipl_c_i_0__n ipl_030_0_2__un3_n \ +cpu_est_2_1__n N_51_0 ipl_030_0_2__un1_n N_235 ipl_c_i_1__n ipl_030_0_2__un0_n \ +N_284 N_52_0 ipl_030_0_1__un3_n N_190 ipl_c_i_2__n ipl_030_0_1__un1_n N_337 \ +N_53_0 ipl_030_0_1__un0_n N_195 N_27_i ipl_030_0_0__un3_n N_340 N_30_0 \ +ipl_030_0_0__un1_n N_231 N_28_i ipl_030_0_0__un0_n N_230 N_31_0 \ +cpu_est_0_3__un3_n N_280 N_29_i cpu_est_0_3__un1_n AS_030.OE AS_000.OE \ +RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE AHIGH_24_.OE \ +AHIGH_25_.OE AHIGH_26_.OE AHIGH_27_.OE AHIGH_28_.OE AHIGH_29_.OE AHIGH_30_.OE \ +AHIGH_31_.OE A_0_.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE G_134 \ +G_135 G_136 pos_clk_un23_bgack_030_int_i_0_x2 cpu_est_0_0_x2_0_x2_0_ \ +pos_clk_CYCLE_DMA_5_0_i_x2 pos_clk_CYCLE_DMA_5_1_i_x2 +.names N_144_i_3.BLIF N_226_i.BLIF SM_AMIGA_i_7_.D 11 1 -.names N_137_i_1.BLIF N_137_i_2.BLIF SM_AMIGA_3_.D +.names N_142_i_1.BLIF N_142_i_2.BLIF SM_AMIGA_6_.D 11 1 -.names N_283_0.BLIF SM_AMIGA_2_.D +.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D +11 1 +.names N_138_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D +11 1 +.names N_136_i_1.BLIF N_136_i_2.BLIF SM_AMIGA_3_.D +11 1 +.names N_257_0.BLIF SM_AMIGA_2_.D 0 1 -.names N_133_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D +.names N_132_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D 11 1 -.names N_208_0.BLIF N_277_i.BLIF SM_AMIGA_0_.D +.names N_185_i.BLIF N_324_i.BLIF SM_AMIGA_0_.D 11 1 +.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D +1- 1 +-1 1 .names N_30_0.BLIF IPL_030DFF_0_reg.D 0 1 .names N_31_0.BLIF IPL_030DFF_1_reg.D @@ -447,15 +507,9 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 0 1 .names N_53_0.BLIF IPL_D0_2_.D 0 1 -.names N_145_i_3.BLIF N_317_i.BLIF SM_AMIGA_i_7_.D +.names N_92_i_1.BLIF pos_clk_CYCLE_DMA_5_0_i_x2.BLIF CYCLE_DMA_0_.D 11 1 -.names N_258_0.BLIF SM_AMIGA_6_.D -0 1 -.names N_141_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D -11 1 -.names N_282_i_1.BLIF N_210_0.BLIF CYCLE_DMA_0_.D -11 1 -.names N_134_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF CYCLE_DMA_1_.D +.names N_103_i_1.BLIF pos_clk_CYCLE_DMA_5_1_i_x2.BLIF CYCLE_DMA_1_.D 11 1 .names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D 1- 1 @@ -466,46 +520,22 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 .names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 -.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D -1- 1 --1 1 -.names N_260_i_1.BLIF N_260_i_2.BLIF RST_DLY_1_.D -11 1 -.names N_259_i_1.BLIF N_259_i_2.BLIF RST_DLY_2_.D +.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF CLK_000_N_SYNC_0_.D 11 1 .names CLK_000_D_0_.BLIF clk_000_d_i_1__n.BLIF CLK_000_P_SYNC_0_.D 11 1 -.names N_261_i_1.BLIF N_322_i.BLIF RST_DLY_0_.D +.names N_239_i_1.BLIF RST_c.BLIF RST_DLY_0_.D 11 1 -.names N_47_0.BLIF inst_AS_000_INT.D -0 1 -.names N_48_0.BLIF inst_DSACK1_INTreg.D -0 1 -.names N_49_0.BLIF inst_DS_000_DMA.D -0 1 -.names N_88_0.BLIF inst_AS_030_D0.D -0 1 -.names N_54_0.BLIF inst_nEXP_SPACE_D0reg.D -0 1 -.names N_55_0.BLIF inst_VPA_D.D -0 1 -.names N_56_0.BLIF inst_DTACK_D0.D -0 1 -.names N_83_i_1.BLIF RST_c.BLIF inst_CLK_030_H.D +.names N_238_i_1.BLIF N_238_i_2.BLIF RST_DLY_1_.D 11 1 -.names N_320_i.BLIF RST_c.BLIF inst_RESET_OUT.D +.names N_237_i_1.BLIF N_237_i_2.BLIF RST_DLY_2_.D +11 1 +.names N_106_i_1.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF inst_CLK_030_H.D +11 1 +.names N_337_i.BLIF RST_c.BLIF inst_RESET_OUT.D 11 1 .names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D 11 1 -.names N_33_0.BLIF BG_000DFFreg.D -0 1 -.names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D -0 1 -.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D -0 1 .names N_37_0.BLIF inst_VMA_INTreg.D 0 1 .names N_38_0.BLIF inst_UDS_000_INT.D @@ -524,568 +554,695 @@ cpu_est_0_0_x2_0_ pos_clk_CYCLE_DMA_5_1_i_x2 0 1 .names N_46_0.BLIF inst_AS_030_000_SYNC.D 0 1 -.names N_210_0.BLIF inst_BGACK_030_INT_D.D +.names N_47_0.BLIF inst_AS_000_INT.D +0 1 +.names N_48_0.BLIF inst_DSACK1_INTreg.D +0 1 +.names N_49_0.BLIF inst_DS_000_DMA.D +0 1 +.names N_323.BLIF inst_AS_030_D0.D +0 1 +.names N_54_0.BLIF inst_VPA_D.D +0 1 +.names N_55_0.BLIF inst_DTACK_D0.D +0 1 +.names N_33_0.BLIF BG_000DFFreg.D +0 1 +.names N_34_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D +0 1 +.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D +0 1 +.names N_186_0.BLIF inst_BGACK_030_INT_D.D 0 1 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D 0 1 -.names N_280_0.BLIF N_280 +.names N_166_i.BLIF N_166 0 1 -.names BGACK_030_INT_i.BLIF RST_c.BLIF N_210_0 +.names N_29_i.BLIF RST_c.BLIF N_32_0 11 1 -.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n +.names cpu_est_3_.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n 11 1 -.names N_279_0.BLIF N_279 +.names N_141_0.BLIF N_141 +0 1 +.names a_c_0__n.BLIF a_c_i_0__n 0 1 -.names N_289_0_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_289_0 -11 1 .names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n 0 1 -.names N_289.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_271 -11 1 -.names N_156_i.BLIF SM_AMIGA_4_.BLIF N_218_0 +.names N_226_3.BLIF sm_amiga_i_3__n.BLIF N_226 11 1 +.names size_c_1__n.BLIF size_c_i_1__n +0 1 .names cpu_est_2_2__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n 11 1 -.names N_375.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_272 +.names N_164_i.BLIF cpu_est_i_2__n.BLIF N_357 +11 1 +.names pos_clk_un10_sm_amiga_i_1_n.BLIF size_c_i_1__n.BLIF \ +pos_clk_un10_sm_amiga_i_n 11 1 .names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n 11 1 -.names A1_c.BLIF BGACK_030_INT_i.BLIF N_276 +.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_2__n.BLIF N_219 11 1 -.names N_242.BLIF N_242_i -0 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n -0 1 -.names pos_clk_un3_as_030_d0_i_n.BLIF un1_SM_AMIGA_5.BLIF \ -DS_000_ENABLE_1_sqmuxa_1 +.names N_275_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_258_0 11 1 -.names N_246.BLIF N_246_i +.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n 0 1 -.names N_119.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n +.names N_141.BLIF N_166_i.BLIF N_217 11 1 -.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_4 -1- 1 --1 1 -.names N_240.BLIF N_240_i +.names N_357.BLIF N_357_i 0 1 -.names cpu_est_3_.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n +.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n +11 1 +.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_1__n.BLIF N_221 +11 1 +.names N_254.BLIF N_254_i +0 1 +.names clk_000_p_sync_i_10__n.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF \ +sm_amiga_srsts_i_0_m2_1__un0_n +11 1 +.names N_149_i.BLIF N_340.BLIF N_220 +11 1 +.names N_254_i.BLIF N_357_i.BLIF cpu_est_2_0_2__n +11 1 +.names pos_clk_un4_clk_000_pe_n.BLIF vma_int_0_un3_n +0 1 +.names N_192.BLIF N_343.BLIF N_223 +11 1 +.names N_315.BLIF N_315_i +0 1 +.names cpu_est_i_1__n.BLIF pos_clk_un4_clk_000_pe_n.BLIF vma_int_0_un1_n 11 1 .names vcc_n_n 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_5 -1- 1 --1 1 -.names N_241.BLIF N_241_i -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n -0 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_7 -1- 1 --1 1 -.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_343 11 1 -.names gnd_n_n -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_10 -1- 1 --1 1 -.names N_266.BLIF N_266_i +.names N_157.BLIF N_315_i.BLIF N_291_0 +11 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names N_192_0.BLIF N_192 0 1 -.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n +0 1 +.names gnd_n_n +.names N_164_i.BLIF N_164 +0 1 +.names N_146_0_1.BLIF nEXP_SPACE_c.BLIF N_146_0 +11 1 +.names cpu_est_2_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n +11 1 +.names un1_amiga_bus_enable_dma_high_0_0__n.BLIF \ +un1_amiga_bus_enable_dma_high_0__n +0 1 +.names N_291_0.BLIF N_291 +0 1 +.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_149_i +11 1 +.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n 11 1 .names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \ un1_amiga_bus_enable_low 11 1 -.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_18 -1- 1 --1 1 -.names N_267.BLIF N_267_i +.names N_164_i.BLIF cpu_est_2_.BLIF N_315 +11 1 +.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_164_i +11 1 +.names SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m2_5__un3_n 0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +.names AS_000_DMA_i.BLIF AS_000_i.BLIF un6_as_030 +11 1 +.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n 0 1 +.names N_149_i.BLIF RST_DLY_2_.BLIF N_166_i +11 1 +.names BERR_i.BLIF SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m2_5__un1_n +11 1 .names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size 11 1 -.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ -amiga_bus_enable_dma_low_0_un0_n.BLIF N_24 -1- 1 --1 1 -.names N_254.BLIF N_254_i -0 1 -.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +.names N_164.BLIF cpu_est_2_.BLIF N_254 +11 1 +.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_172_i +11 1 +.names clk_000_p_sync_i_10__n.BLIF sm_amiga_srsts_i_0_0_m2_5__un3_n.BLIF \ +sm_amiga_srsts_i_0_0_m2_5__un0_n 11 1 .names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size 11 1 -.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6 -1- 1 --1 1 -.names N_317.BLIF N_317_i +.names N_258_0.BLIF N_258 0 1 -.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +.names N_176_i_1.BLIF sm_amiga_i_2__n.BLIF N_176_i 11 1 +.names N_122.BLIF rw_000_int_0_un3_n +0 1 .names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un4_uds_000 11 1 -.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i -0 1 -.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n -0 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 +1- 1 +-1 1 +.names BGACK_030_INT_i.BLIF RST_c.BLIF N_186_0 +11 1 +.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_122.BLIF rw_000_int_0_un1_n +11 1 .names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un4_lds_000 11 1 -.names un21_fpu_cs.BLIF un21_fpu_cs_i -0 1 -.names N_313.BLIF N_313_i -0 1 -.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28 +1- 1 +-1 1 +.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_192_0 11 1 -.names un5_ciin_10.BLIF un5_ciin_11.BLIF un5_ciin -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names N_316.BLIF N_316_i -0 1 -.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n 11 1 .names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000 11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i -0 1 -.names N_312.BLIF N_312_i -0 1 -.names N_193.BLIF a0_dma_0_un3_n -0 1 -.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs -11 1 -.names inst_UDS_000_INT.BLIF UDS_000_INT_i -0 1 -.names pos_clk_a0_dma_3_n.BLIF N_193.BLIF a0_dma_0_un1_n -11 1 -.names un22_berr_1_0.BLIF N_375.BLIF un22_berr -11 1 -.names inst_LDS_000_INT.BLIF LDS_000_INT_i -0 1 -.names N_347.BLIF N_347_i -0 1 -.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n -11 1 -.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 -11 1 -.names N_236.BLIF N_236_i -0 1 -.names N_323.BLIF N_323_i -0 1 -.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n -0 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names N_324.BLIF N_324_i -0 1 -.names A0_c.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n -11 1 -.names DS_000_ENABLE_1_sqmuxa.BLIF DS_000_ENABLE_1_sqmuxa_i -0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF N_222_i -11 1 -.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names N_276.BLIF N_276_i -0 1 -.names inst_AS_000_DMA.BLIF AS_000_DMA_i -0 1 -.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n -0 1 -.names RST_c.BLIF RST_i -0 1 -.names AS_000_DMA_i.BLIF CLK_030_i.BLIF N_221_0 -11 1 -.names cpu_est_i_1__n.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n -11 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names inst_CLK_000_PE.BLIF SM_AMIGA_4_.BLIF N_220_0 -11 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_219_0 -11 1 -.names N_193.BLIF amiga_bus_enable_dma_high_0_un3_n -0 1 -.names SIZE_DMA_1_.BLIF size_dma_i_1__n -0 1 -.names inst_CLK_000_NE.BLIF N_187_i.BLIF N_216_0 -11 1 -.names N_275_i.BLIF N_193.BLIF amiga_bus_enable_dma_high_0_un1_n -11 1 -.names SIZE_DMA_0_.BLIF size_dma_i_0__n -0 1 -.names inst_CLK_000_NE_D0.BLIF N_201.BLIF N_290_0 -11 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n -11 1 -.names RW_c.BLIF RW_i -0 1 -.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_212_0 -11 1 -.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n -0 1 -.names inst_CLK_000_PE.BLIF CLK_000_PE_i -0 1 -.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_211_0 -11 1 -.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n -11 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names N_196_i.BLIF sm_amiga_i_6__n.BLIF N_204_0 -11 1 -.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 -.names inst_RESET_OUT.BLIF RESET_OUT_i -0 1 -.names N_351.BLIF N_351_i -0 1 -.names N_96.BLIF ds_000_dma_0_un3_n -0 1 -.names BERR_c.BLIF BERR_i -0 1 -.names N_353.BLIF N_353_i -0 1 -.names N_90.BLIF N_96.BLIF ds_000_dma_0_un1_n -11 1 -.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n -0 1 -.names N_351_i.BLIF N_353_i.BLIF N_201_i -11 1 -.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n -11 1 -.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names N_99.BLIF as_000_dma_0_un3_n -0 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_197_i -11 1 -.names N_192.BLIF N_99.BLIF as_000_dma_0_un1_n -11 1 -.names FPU_SENSE_c.BLIF FPU_SENSE_i -0 1 -.names sm_amiga_i_2__n.BLIF sm_amiga_i_4__n.BLIF N_196_i -11 1 -.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_193_i -11 1 -.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n -0 1 -.names inst_AS_030_D0.BLIF AS_030_D0_i -0 1 -.names N_192_0_1.BLIF N_192_0_2.BLIF N_192_0 -11 1 -.names pos_clk_un8_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n -11 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n -0 1 -.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_350.BLIF N_350_i -0 1 -.names N_193.BLIF rw_000_dma_0_un3_n -0 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names clk_000_n_sync_i_10__n.BLIF N_350_i.BLIF N_188_0 -11 1 -.names N_80.BLIF N_193.BLIF rw_000_dma_0_un1_n -11 1 -.names cpu_est_3_.BLIF cpu_est_i_3__n -0 1 -.names N_158_i.BLIF RST_DLY_2_.BLIF N_187_i -11 1 -.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_185_i -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names N_181_i.BLIF cpu_est_i_0__n.BLIF N_182_i -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names cpu_est_3_.BLIF cpu_est_i_2__n.BLIF N_181_i -11 1 -.names inst_CLK_000_NE.BLIF CLK_000_NE_i -0 1 -.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i -0 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_175_0 -11 1 -.names RST_DLY_2_.BLIF rst_dly_i_2__n -0 1 -.names N_168_i_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_168_i -11 1 -.names CLK_030_c.BLIF CLK_030_i -0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names RST_DLY_0_.BLIF rst_dly_i_0__n -0 1 -.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_158_i -11 1 -.names RST_DLY_1_.BLIF rst_dly_i_1__n -0 1 -.names CLK_000_D_0_.BLIF clk_000_d_i_0__n -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_1__n -0 1 -.names CLK_000_D_1_.BLIF clk_000_d_i_0__n.BLIF N_148_i -11 1 -.names inst_DTACK_D0.BLIF DTACK_D0_i -0 1 -.names N_345.BLIF N_345_i -0 1 -.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n -11 1 -.names RW_000_c.BLIF RW_000_i -0 1 -.names N_344.BLIF N_344_i -0 1 -.names inst_CLK_030_H.BLIF CLK_030_H_i -0 1 -.names N_344_i.BLIF RST_c.BLIF N_144_0 -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names AS_000_DMA_i.BLIF AS_000_i.BLIF N_138_0 -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names AS_000_c.BLIF AS_000_i -0 1 -.names N_342.BLIF N_342_i -0 1 -.names pos_clk_ipl_1_n.BLIF N_214_i.BLIF pos_clk_ipl_n -11 1 -.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n -0 1 -.names N_343.BLIF N_343_i -0 1 -.names A1_c.BLIF A1_i -0 1 -.names N_342_i.BLIF N_343_i.BLIF N_124_0 -11 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names N_341.BLIF N_341_i -0 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names N_182.BLIF N_341_i.BLIF N_119_0 -11 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names N_340.BLIF N_340_i -0 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names N_361.BLIF N_361_i -0 1 -.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n -0 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names N_340_i.BLIF N_361_i.BLIF cpu_est_2_0_2__n -11 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names N_338.BLIF N_338_i -0 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names N_339.BLIF N_339_i -0 1 -.names G_134.BLIF N_213_i -0 1 -.names N_338_i.BLIF N_339_i.BLIF cpu_est_2_0_1__n -11 1 -.names G_135.BLIF N_214_i -0 1 -.names N_332.BLIF N_332_i -0 1 -.names G_136.BLIF N_215_i -0 1 -.names N_336.BLIF N_336_i -0 1 -.names N_332_i.BLIF N_336_i.BLIF pos_clk_un7_clk_000_pe_0_n -11 1 -.names N_275.BLIF N_275_i -0 1 -.names CLK_030_i.BLIF N_192_0.BLIF N_99_0 -11 1 -.names un6_ds_030.BLIF un6_ds_030_i -0 1 -.names N_331.BLIF N_331_i -0 1 -.names inst_DS_000_DMA.BLIF DS_000_DMA_i -0 1 -.names N_96_0_1.BLIF RW_000_i.BLIF N_96_0 -11 1 -.names un4_as_000.BLIF un4_as_000_i -0 1 -.names N_330.BLIF N_330_i -0 1 -.names inst_AS_000_INT.BLIF AS_000_INT_i -0 1 -.names N_192_0.BLIF N_330_i.BLIF N_90_0 -11 1 -.names un4_lds_000.BLIF un4_lds_000_i -0 1 -.names N_328.BLIF N_328_i -0 1 -.names un4_uds_000.BLIF un4_uds_000_i -0 1 -.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_80_0 -11 1 -.names N_325.BLIF N_325_i -0 1 -.names N_326.BLIF N_326_i -0 1 -.names N_325_i.BLIF N_326_i.BLIF N_258_0 -11 1 -.names N_187.BLIF RST_c.BLIF N_217_i -11 1 -.names N_321.BLIF N_321_i -0 1 -.names N_322.BLIF N_322_i -0 1 -.names N_320.BLIF N_320_i -0 1 -.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n -0 1 -.names un5_ciin.BLIF un5_ciin_i -0 1 -.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n -11 1 -.names nEXP_SPACE_D0_i.BLIF un5_ciin_i.BLIF N_61_0 -11 1 -.names N_310.BLIF N_310_i -0 1 -.names N_305.BLIF N_305_i -0 1 -.names N_307.BLIF N_307_i -0 1 -.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 -1- 1 --1 1 -.names N_303.BLIF N_303_i -0 1 -.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_8 -1- 1 --1 1 -.names N_304.BLIF N_304_i -0 1 -.names N_303_i.BLIF N_304_i.BLIF N_283_0 -11 1 -.names N_301.BLIF N_301_i -0 1 -.names N_300.BLIF N_300_i -0 1 -.names N_123_0_1.BLIF SM_AMIGA_i_7_.BLIF N_123_0 -11 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_17 -1- 1 --1 1 -.names N_278.BLIF N_278_i -0 1 -.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 -1- 1 --1 1 -.names N_297.BLIF N_297_i -0 1 -.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 -1- 1 --1 1 -.names N_278_i.BLIF N_297_i.BLIF AMIGA_BUS_DATA_DIR_c_0 -11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 -1- 1 --1 1 -.names N_277.BLIF N_277_i -0 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_22 -1- 1 --1 1 -.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ -amiga_bus_enable_dma_high_0_un0_n.BLIF N_25 -1- 1 --1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26 -1- 1 --1 1 -.names pos_clk_un8_sm_amiga_i_1_n.BLIF size_c_0__n.BLIF \ -pos_clk_un8_sm_amiga_i_n -11 1 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27 1- 1 -1 1 -.names A0_c.BLIF A0_c_i +.names N_228.BLIF N_228_i 0 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28 +.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +0 1 +.names un10_ciin_10.BLIF un10_ciin_11.BLIF un10_ciin +11 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_4 1- 1 -1 1 -.names size_c_1__n.BLIF size_c_i_1__n +.names N_227.BLIF N_227_i 0 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29 +.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +11 1 +.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs +11 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_17 1- 1 -1 1 -.names N_29.BLIF N_29_i +.names N_343.BLIF N_343_i 0 1 -.names N_29_i.BLIF RST_c.BLIF N_32_0 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ +bgack_030_int_0_un0_n 11 1 -.names N_28.BLIF N_28_i +.names un22_berr_1_0.BLIF N_366.BLIF un22_berr +11 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21 +1- 1 +-1 1 +.names N_293.BLIF as_000_int_0_un3_n 0 1 -.names N_28_i.BLIF RST_c.BLIF N_31_0 +.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030 11 1 -.names N_27.BLIF N_27_i +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26 +1- 1 +-1 1 +.names N_223.BLIF N_223_i 0 1 -.names N_27_i.BLIF RST_c.BLIF N_30_0 +.names sm_amiga_i_5__n.BLIF N_293.BLIF as_000_int_0_un1_n 11 1 -.names ipl_c_2__n.BLIF ipl_c_i_2__n +.names pos_clk_un9_bg_030_0_n.BLIF pos_clk_un9_bg_030_n 0 1 -.names ipl_c_i_2__n.BLIF RST_c.BLIF N_53_0 -11 1 -.names ipl_c_1__n.BLIF ipl_c_i_1__n +.names N_225.BLIF N_225_i 0 1 -.names ipl_c_i_1__n.BLIF RST_c.BLIF N_52_0 +.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 -.names ipl_c_0__n.BLIF ipl_c_i_0__n +.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i 0 1 -.names ipl_c_i_0__n.BLIF RST_c.BLIF N_51_0 -11 1 -.names DTACK_c.BLIF DTACK_c_i +.names N_224.BLIF N_224_i 0 1 -.names DTACK_c_i.BLIF RST_c.BLIF N_56_0 +.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n +0 1 +.names un21_fpu_cs.BLIF un21_fpu_cs_i +0 1 +.names N_226.BLIF N_226_i +0 1 +.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF \ +ds_000_enable_0_un1_n 11 1 +.names N_275.BLIF N_275_i +0 1 +.names un1_SM_AMIGA_5_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n +11 1 +.names CLK_000_N_SYNC_12_.BLIF clk_000_n_sync_i_12__n +0 1 +.names N_220.BLIF N_220_i +0 1 +.names N_290.BLIF as_030_000_sync_0_un3_n +0 1 +.names RST_DLY_2_.BLIF rst_dly_i_2__n +0 1 +.names N_221.BLIF N_221_i +0 1 +.names inst_AS_030_000_SYNC.BLIF N_290.BLIF as_030_000_sync_0_un1_n +11 1 +.names RST_DLY_1_.BLIF rst_dly_i_1__n +0 1 +.names N_222.BLIF N_222_i +0 1 +.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un0_n +11 1 +.names BERR_c.BLIF BERR_i +0 1 +.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_0_m2_0__un3_n +0 1 +.names cpu_est_2_.BLIF cpu_est_i_2__n +0 1 +.names N_217.BLIF N_217_i +0 1 +.names SM_AMIGA_i_7_.BLIF inst_BGACK_030_INTreg.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un1_n +11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names N_215.BLIF N_215_i +0 1 +.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un3_n.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un0_n +11 1 +.names RST_DLY_0_.BLIF rst_dly_i_0__n +0 1 +.names N_219.BLIF N_219_i +0 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_low_0_un3_n +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names N_322_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +amiga_bus_enable_dma_low_0_un1_n +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_200_i +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ +amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n +11 1 +.names inst_VPA_D.BLIF VPA_D_i +0 1 +.names CLK_000_N_SYNC_12_.BLIF N_166_i.BLIF N_195_0 +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF amiga_bus_enable_dma_high_0_un3_n +0 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names clk_000_n_sync_i_12__n.BLIF SM_AMIGA_1_.BLIF N_190_0 +11 1 +.names N_321_i.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +amiga_bus_enable_dma_high_0_un1_n +11 1 +.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n +0 1 +.names N_154_i.BLIF cpu_est_i_0__n.BLIF N_157_i +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ +amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n +11 1 +.names cpu_est_3_.BLIF cpu_est_i_3__n +0 1 +.names cpu_est_3_.BLIF cpu_est_i_2__n.BLIF N_154_i +11 1 +.names N_294.BLIF size_dma_0_0__un3_n +0 1 +.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n +0 1 +.names N_340.BLIF N_340_i +0 1 +.names pos_clk_size_dma_6_0__n.BLIF N_294.BLIF size_dma_0_0__un1_n +11 1 +.names inst_RESET_OUT.BLIF RESET_OUT_i +0 1 +.names N_340_i.BLIF RST_c.BLIF N_141_0 +11 1 +.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names N_200_i.BLIF inst_RESET_OUT.BLIF un3_as_030_i +11 1 +.names N_294.BLIF size_dma_0_1__un3_n +0 1 +.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n +0 1 +.names N_166.BLIF RST_c.BLIF N_216_i +11 1 +.names pos_clk_size_dma_6_1__n.BLIF N_294.BLIF size_dma_0_1__un1_n +11 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names N_337.BLIF N_337_i +0 1 +.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n +11 1 +.names CLK_000_P_SYNC_10_.BLIF clk_000_p_sync_i_10__n +0 1 +.names N_120.BLIF ds_000_dma_0_un3_n +0 1 +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n +0 1 +.names un10_ciin.BLIF un10_ciin_i +0 1 +.names pos_clk_ds_000_dma_4_n.BLIF N_120.BLIF ds_000_dma_0_un1_n +11 1 +.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n +0 1 +.names nEXP_SPACE_i.BLIF un10_ciin_i.BLIF N_296_0 +11 1 +.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names CLK_000_D_11_.BLIF clk_000_d_i_11__n +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i +11 1 +.names N_298.BLIF as_000_dma_0_un3_n +0 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names N_284.BLIF N_284_i +0 1 +.names pos_clk_un23_bgack_030_int_i_1_n.BLIF N_298.BLIF as_000_dma_0_un1_n +11 1 +.names RW_c.BLIF RW_i +0 1 +.names N_285.BLIF N_285_i +0 1 +.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names DS_000_ENABLE_1_sqmuxa.BLIF DS_000_ENABLE_1_sqmuxa_i +0 1 +.names N_284_i.BLIF N_285_i.BLIF N_292_0 +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un3_n +0 1 +.names inst_LDS_000_INT.BLIF LDS_000_INT_i +0 1 +.names N_280.BLIF N_280_i +0 1 +.names N_295.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF rw_000_dma_0_un1_n +11 1 +.names inst_UDS_000_INT.BLIF UDS_000_INT_i +0 1 +.names N_277.BLIF N_277_i +0 1 +.names inst_RW_000_DMA.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_277_i.BLIF N_280_i.BLIF N_257_0 +11 1 +.names pos_clk_un5_bgack_030_int_d_n.BLIF a0_dma_0_un3_n +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_i +0 1 +.names N_235.BLIF N_235_i +0 1 +.names pos_clk_a0_dma_3_n.BLIF pos_clk_un5_bgack_030_int_d_n.BLIF \ +a0_dma_0_un1_n +11 1 +.names a_decode_c_19__n.BLIF a_decode_i_19__n +0 1 +.names N_236.BLIF N_236_i +0 1 +.names inst_A0_DMA.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +11 1 +.names a_decode_c_18__n.BLIF a_decode_i_18__n +0 1 +.names N_235_i.BLIF N_236_i.BLIF cpu_est_2_0_1__n +11 1 +.names a_decode_c_16__n.BLIF a_decode_i_16__n +0 1 +.names N_231.BLIF N_231_i +0 1 +.names AS_000_c.BLIF AS_000_i +0 1 +.names N_230.BLIF N_230_i +0 1 +.names FPU_SENSE_c.BLIF FPU_SENSE_i +0 1 +.names N_230_i.BLIF N_231_i.BLIF pos_clk_un4_clk_000_pe_0_n +11 1 +.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i +0 1 +.names N_22.BLIF N_22_i +0 1 +.names CLK_030_c.BLIF CLK_030_i +0 1 +.names N_22_i.BLIF RST_c.BLIF N_37_0 +11 1 +.names pos_clk_un6_bg_030_1_n.BLIF CLK_000_D_0_.BLIF pos_clk_un6_bg_030_n +11 1 +.names inst_DTACK_D0.BLIF DTACK_D0_i +0 1 +.names CLK_000_D_10_.BLIF clk_000_d_i_10__n +0 1 +.names N_334.BLIF N_334_i +0 1 +.names RW_000_c.BLIF RW_000_i +0 1 +.names N_335.BLIF N_335_i +0 1 +.names a_c_1__n.BLIF a_i_1__n +0 1 +.names N_194_0_1.BLIF nEXP_SPACE_c.BLIF N_194_0 +11 1 +.names inst_CLK_030_H.BLIF CLK_030_H_i +0 1 +.names clk_000_n_sync_i_12__n.BLIF SM_AMIGA_5_.BLIF N_191_0 +11 1 +.names pos_clk_ipl_1_n.BLIF N_213_i.BLIF pos_clk_ipl_n +11 1 +.names inst_AS_000_DMA.BLIF AS_000_DMA_i +0 1 +.names un1_SM_AMIGA_5_i_1.BLIF un1_SM_AMIGA_5_i_2.BLIF un1_SM_AMIGA_5_i +11 1 +.names CLK_000_D_0_.BLIF clk_000_d_i_0__n +0 1 +.names N_346.BLIF N_346_i +0 1 +.names CLK_000_D_1_.BLIF clk_000_d_i_1__n +0 1 +.names sm_amiga_i_6__n.BLIF SM_AMIGA_i_7_.BLIF N_163_i +11 1 +.names inst_AS_030_D0.BLIF AS_030_D0_i +0 1 +.names N_345.BLIF N_345_i +0 1 +.names SIZE_DMA_0_.BLIF size_dma_i_0__n +0 1 +.names N_344.BLIF N_344_i +0 1 +.names SIZE_DMA_1_.BLIF size_dma_i_1__n +0 1 +.names N_344_i.BLIF N_345_i.BLIF N_153_0 +11 1 +.names ahigh_c_30__n.BLIF ahigh_i_30__n +0 1 +.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n +11 1 +.names ahigh_c_31__n.BLIF ahigh_i_31__n +0 1 +.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_293_0 +11 1 +.names ahigh_c_28__n.BLIF ahigh_i_28__n +0 1 +.names N_233.BLIF N_233_i +0 1 +.names ahigh_c_29__n.BLIF ahigh_i_29__n +0 1 +.names N_232.BLIF N_232_i +0 1 +.names ahigh_c_26__n.BLIF ahigh_i_26__n +0 1 +.names N_232_i.BLIF N_233_i.BLIF N_290_0 +11 1 +.names ahigh_c_27__n.BLIF ahigh_i_27__n +0 1 .names VPA_c.BLIF VPA_c_i 0 1 -.names RST_c.BLIF VPA_c_i.BLIF N_55_0 -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i +.names ahigh_c_24__n.BLIF ahigh_i_24__n 0 1 -.names RST_c.BLIF nEXP_SPACE_c_i.BLIF N_54_0 +.names RST_c.BLIF VPA_c_i.BLIF N_54_0 11 1 +.names ahigh_c_25__n.BLIF ahigh_i_25__n +0 1 +.names N_5.BLIF N_5_i +0 1 +.names G_134.BLIF N_212_i +0 1 +.names N_5_i.BLIF RST_c.BLIF N_47_0 +11 1 +.names G_135.BLIF N_213_i +0 1 +.names N_7.BLIF N_7_i +0 1 +.names G_136.BLIF N_214_i +0 1 +.names N_7_i.BLIF RST_c.BLIF N_46_0 +11 1 +.names N_18.BLIF N_18_i +0 1 +.names N_18_i.BLIF RST_c.BLIF N_41_0 +11 1 +.names N_321.BLIF N_321_i +0 1 +.names N_10.BLIF N_10_i +0 1 +.names N_322.BLIF N_322_i +0 1 +.names N_10_i.BLIF RST_c.BLIF N_43_0 +11 1 +.names un6_ds_030.BLIF un6_ds_030_i +0 1 +.names DTACK_c.BLIF DTACK_c_i +0 1 +.names inst_DS_000_DMA.BLIF DS_000_DMA_i +0 1 +.names DTACK_c_i.BLIF RST_c.BLIF N_55_0 +11 1 +.names un4_as_000.BLIF un4_as_000_i +0 1 +.names BGACK_000_c.BLIF N_203.BLIF pos_clk_un6_bgack_000_0_n +11 1 +.names un6_as_030.BLIF un6_as_030_i +0 1 +.names BERR_c.BLIF clk_000_p_sync_i_10__n.BLIF N_137_i +11 1 +.names un4_lds_000.BLIF un4_lds_000_i +0 1 +.names N_137.BLIF sm_amiga_i_3__n.BLIF N_184_0 +11 1 +.names un4_uds_000.BLIF un4_uds_000_i +0 1 +.names N_349.BLIF N_349_i +0 1 +.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i +0 1 +.names N_349_i.BLIF RST_c.BLIF N_185_i +11 1 +.names N_137_i.BLIF SM_AMIGA_4_.BLIF N_187_0 +11 1 +.names pos_clk_un5_bgack_030_int_d_i_n.BLIF pos_clk_un5_bgack_030_int_d_n +0 1 +.names AS_000_c.BLIF CLK_000_P_SYNC_10_.BLIF N_203_i +11 1 +.names N_324.BLIF N_324_i +0 1 +.names CLK_000_N_SYNC_12_.BLIF SM_AMIGA_1_.BLIF N_199_0 +11 1 +.names AS_000_DMA_i.BLIF CLK_030_i.BLIF N_197_0 +11 1 +.names CLK_000_P_SYNC_10_.BLIF SM_AMIGA_4_.BLIF N_196_0 +11 1 +.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n +11 1 +.names LDS_000_c.BLIF LDS_000_c_i +0 1 +.names UDS_000_c.BLIF UDS_000_c_i +0 1 +.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_181_i +11 1 +.names N_347.BLIF N_347_i +0 1 +.names N_348.BLIF N_348_i +0 1 +.names N_347_i.BLIF N_348_i.BLIF N_178_i +11 1 +.names pos_clk_ds_000_dma_4_0_n.BLIF pos_clk_ds_000_dma_4_n +0 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3 +1- 1 +-1 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +pos_clk_un5_bgack_030_int_d_i_n +11 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_8 +1- 1 +-1 1 +.names pos_clk_un23_bgack_030_int_i_1_0_1_n.BLIF \ +pos_clk_un23_bgack_030_int_i_1_0_2_n.BLIF pos_clk_un23_bgack_030_int_i_1_0_n +11 1 +.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i +0 1 +.names CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_148_0 +11 1 +.names N_341.BLIF N_341_i +0 1 +.names N_338.BLIF N_338_i +0 1 +.names N_339.BLIF N_339_i +0 1 +.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19 +1- 1 +-1 1 +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20 +1- 1 +-1 1 +.names N_336.BLIF N_336_i +0 1 +.names amiga_bus_enable_dma_low_0_un1_n.BLIF \ +amiga_bus_enable_dma_low_0_un0_n.BLIF N_24 +1- 1 +-1 1 +.names N_122_0_1.BLIF SM_AMIGA_i_7_.BLIF N_122_0 +11 1 +.names amiga_bus_enable_dma_high_0_un1_n.BLIF \ +amiga_bus_enable_dma_high_0_un0_n.BLIF N_25 +1- 1 +-1 1 +.names N_211.BLIF N_211_i +0 1 +.names N_332.BLIF N_332_i +0 1 +.names N_331.BLIF N_331_i +0 1 +.names N_120_0_1.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF N_120_0 +11 1 +.names N_330.BLIF N_330_i +0 1 +.names N_330_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF \ +pos_clk_ds_000_dma_4_0_n +11 1 +.names N_329.BLIF N_329_i +0 1 +.names N_329_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n +11 1 +.names N_328.BLIF N_328_i +0 1 +.names N_328_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n +11 1 +.names N_325.BLIF N_325_i +0 1 +.names N_327.BLIF N_327_i +0 1 +.names N_325_i.BLIF N_327_i.BLIF AMIGA_BUS_DATA_DIR_c_0 +11 1 +.names N_320.BLIF N_320_i +0 1 +.names CLK_030_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_n.BLIF N_298_0 +11 1 +.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_295_0 +11 1 +.names RST_c.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_294_0 +11 1 +.names N_319.BLIF N_319_i +0 1 +.names N_207.BLIF N_319_i.BLIF un1_amiga_bus_enable_dma_high_0_0__n +11 1 +.names N_206.BLIF N_206_i +0 1 +.names N_283.BLIF N_283_i +0 1 +.names N_122_0.BLIF N_122 +0 1 +.names N_281.BLIF N_281_i +0 1 +.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +0 1 +.names N_282.BLIF N_282_i +0 1 +.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +0 1 .names N_3.BLIF N_3_i 0 1 .names N_3_i.BLIF RST_c.BLIF N_49_0 @@ -1094,558 +1251,464 @@ pos_clk_un8_sm_amiga_i_n 0 1 .names N_8_i.BLIF RST_c.BLIF N_45_0 11 1 -.names N_17.BLIF N_17_i +.names pos_clk_un23_bgack_030_int_i_1_0_n.BLIF \ +pos_clk_un23_bgack_030_int_i_1_n 0 1 -.names N_17_i.BLIF RST_c.BLIF N_42_0 -11 1 .names N_19.BLIF N_19_i 0 1 +.names N_292_0.BLIF N_292 +0 1 .names N_19_i.BLIF RST_c.BLIF N_40_0 11 1 +.names N_294_0.BLIF N_294 +0 1 .names N_20.BLIF N_20_i 0 1 -.names N_123_0.BLIF N_123 +.names N_295_0.BLIF N_295 0 1 .names N_20_i.BLIF RST_c.BLIF N_39_0 11 1 -.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n +.names N_296_0.BLIF N_296 0 1 -.names N_21.BLIF N_21_i +.names N_24.BLIF N_24_i 0 1 -.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n +.names N_298_0.BLIF N_298 0 1 -.names N_21_i.BLIF RST_c.BLIF N_38_0 +.names N_24_i.BLIF RST_c.BLIF N_35_0 11 1 -.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_209 -11 1 -.names N_22.BLIF N_22_i +.names N_120_0.BLIF N_120 0 1 -.names N_22_i.BLIF RST_c.BLIF N_37_0 -11 1 .names N_25.BLIF N_25_i 0 1 +.names N_148_0.BLIF N_148 +0 1 .names N_25_i.BLIF RST_c.BLIF N_34_0 11 1 -.names N_217_i.BLIF N_217 +.names N_149_i.BLIF N_149 0 1 -.names N_26.BLIF N_26_i +.names sm_amiga_i_i_7__n.BLIF pos_clk_un5_bgack_030_int_d_i_n.BLIF N_194_0_1 +11 1 +.names N_157_i.BLIF N_157 0 1 -.names N_26_i.BLIF RST_c.BLIF N_33_0 +.names N_215_i.BLIF N_217_i.BLIF N_237_i_1 11 1 -.names N_61_0.BLIF N_61 +.names N_172_i.BLIF N_172 0 1 -.names BG_030_c.BLIF BG_030_c_i +.names N_219_i.BLIF RST_c.BLIF N_237_i_2 +11 1 +.names N_176_i.BLIF N_176 0 1 -.names CLK_000_NE_i.BLIF RST_c.BLIF N_127 +.names N_220_i.BLIF RST_c.BLIF N_238_i_1 11 1 -.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n +.names N_178_i.BLIF N_178 0 1 -.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n +.names N_221_i.BLIF N_222_i.BLIF N_238_i_2 11 1 -.names N_80_0.BLIF N_80 +.names N_181_i.BLIF N_181 0 1 -.names N_193_i.BLIF sm_amiga_i_i_7__n.BLIF N_289_0_1 +.names N_185_i.BLIF N_223_i.BLIF N_144_i_1 11 1 -.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_349_i.BLIF un1_SM_AMIGA_5_i_1 -11 1 -.names N_90_0.BLIF N_90 +.names N_184_0.BLIF N_184 0 1 -.names N_194_i.BLIF SM_AMIGA_i_7_.BLIF un1_SM_AMIGA_5_i_2 +.names N_224_i.BLIF N_225_i.BLIF N_144_i_2 11 1 -.names N_96_0.BLIF N_96 +.names N_144_i_1.BLIF N_144_i_2.BLIF N_144_i_3 +11 1 +.names N_196_0.BLIF N_196 0 1 -.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un8_sm_amiga_i_1_n +.names N_227_i.BLIF N_228_i.BLIF N_136_i_1 11 1 -.names N_99_0.BLIF N_99 +.names N_197_0.BLIF N_197 0 1 -.names N_182_i.BLIF VMA_INT_i.BLIF N_351_1 +.names N_343_i.BLIF RST_c.BLIF N_136_i_2 11 1 -.names N_119_0.BLIF N_119 -0 1 -.names VPA_D_i.BLIF cpu_est_i_1__n.BLIF N_351_2 -11 1 -.names N_124_0.BLIF N_124 -0 1 -.names AS_030_000_SYNC_i.BLIF N_148_i.BLIF N_168_i_1 -11 1 -.names N_138_0.BLIF N_138 -0 1 -.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_192_0_1 -11 1 -.names N_144_0.BLIF N_144 -0 1 -.names pos_clk_un23_bgack_030_int_i_i_a4_i_x2.BLIF N_345_i.BLIF N_192_0_2 -11 1 -.names N_158_i.BLIF N_158 -0 1 -.names N_323_i.BLIF N_324_i.BLIF N_137_i_1 -11 1 -.names N_168_i.BLIF N_168 -0 1 -.names N_347_i.BLIF RST_c.BLIF N_137_i_2 -11 1 -.names N_175_0.BLIF N_175 -0 1 -.names N_208_0.BLIF N_312_i.BLIF N_145_i_1 -11 1 -.names N_182_i.BLIF N_182 -0 1 -.names N_313_i.BLIF N_316_i.BLIF N_145_i_2 -11 1 -.names N_185_i.BLIF N_185 -0 1 -.names N_145_i_1.BLIF N_145_i_2.BLIF N_145_i_3 -11 1 -.names N_187_i.BLIF N_187 -0 1 -.names N_242_i.BLIF N_254_i.BLIF N_260_i_1 -11 1 -.names N_188_0.BLIF N_188 -0 1 -.names N_266_i.BLIF N_267_i.BLIF N_260_i_2 -11 1 -.names N_192_0.BLIF N_192 -0 1 -.names N_240_i.BLIF N_241_i.BLIF N_259_i_1 -11 1 -.names N_193_i.BLIF N_193 -0 1 -.names N_242_i.BLIF N_246_i.BLIF N_259_i_2 -11 1 -.names N_197_i.BLIF N_197 -0 1 -.names inst_CLK_000_NE.BLIF N_361.BLIF N_336_1 -11 1 -.names N_201_i.BLIF N_201 -0 1 -.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_336_2 -11 1 -.names N_204_0.BLIF N_204 -0 1 -.names inst_CLK_000_PE.BLIF cpu_est_i_0__n.BLIF N_332_1 -11 1 -.names N_206_0.BLIF N_206 -0 1 -.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_332_2 -11 1 -.names N_207_0.BLIF N_207 -0 1 -.names N_332_1.BLIF N_332_2.BLIF N_332_3 -11 1 -.names N_168.BLIF N_194_i.BLIF N_317_1 -11 1 -.names N_211_0.BLIF N_211 -0 1 -.names N_196_i.BLIF N_197_i.BLIF N_317_2 -11 1 -.names N_212_0.BLIF N_212 -0 1 -.names N_317_1.BLIF N_317_2.BLIF N_317_3 -11 1 -.names N_290_0.BLIF N_290 -0 1 -.names inst_CLK_000_NE_D0.BLIF N_201.BLIF N_304_1 -11 1 -.names N_216_0.BLIF N_216 -0 1 -.names RST_c.BLIF SM_AMIGA_3_.BLIF N_304_2 -11 1 -.names N_219_0.BLIF N_219 -0 1 -.names AS_030_D0_i.BLIF a_c_20__n.BLIF un5_ciin_1 -11 1 -.names N_220_0.BLIF N_220 -0 1 -.names a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2 -11 1 -.names N_221_0.BLIF N_221 -0 1 -.names a_c_23__n.BLIF a_i_24__n.BLIF un5_ciin_3 -11 1 -.names un1_amiga_bus_enable_dma_high_i_m2_0__un1_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un0_n.BLIF N_227 +.names sm_amiga_srsts_i_0_0_m2_5__un1_n.BLIF \ +sm_amiga_srsts_i_0_0_m2_5__un0_n.BLIF N_206 1- 1 -1 1 -.names a_i_25__n.BLIF a_i_26__n.BLIF un5_ciin_4 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_6__n.BLIF N_176_i_1 +11 1 +.names un1_amiga_bus_enable_dma_high_0_m2_0__un1_n.BLIF \ +un1_amiga_bus_enable_dma_high_0_m2_0__un0_n.BLIF N_207 +1- 1 +-1 1 +.names AS_030_000_SYNC_i.BLIF CLK_000_N_SYNC_0_.BLIF N_146_0_1 11 1 .names sm_amiga_srsts_i_0_m2_1__un1_n.BLIF sm_amiga_srsts_i_0_m2_1__un0_n.BLIF \ -N_229 +N_211 1- 1 -1 1 -.names a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5 +.names size_c_0__n.BLIF a_c_i_0__n.BLIF pos_clk_un10_sm_amiga_i_1_n 11 1 -.names sm_amiga_srsts_i_0_m2_5__un1_n.BLIF sm_amiga_srsts_i_0_m2_5__un0_n.BLIF \ -N_230 -1- 1 --1 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6 +.names N_215_1.BLIF rst_dly_i_2__n.BLIF N_215 11 1 -.names N_188.BLIF SM_AMIGA_1_.BLIF N_236 +.names ahigh_i_24__n.BLIF ahigh_i_25__n.BLIF un10_ciin_1 11 1 -.names un5_ciin_1.BLIF un5_ciin_2.BLIF un5_ciin_7 +.names N_222_1.BLIF rst_dly_i_1__n.BLIF N_222 11 1 -.names N_240_1.BLIF rst_dly_i_2__n.BLIF N_240 +.names ahigh_i_26__n.BLIF ahigh_i_27__n.BLIF un10_ciin_2 11 1 -.names un5_ciin_3.BLIF un5_ciin_4.BLIF un5_ciin_8 +.names N_224_1.BLIF clk_000_p_sync_i_10__n.BLIF N_224 11 1 -.names N_144.BLIF N_187_i.BLIF N_241 +.names ahigh_i_28__n.BLIF ahigh_i_29__n.BLIF un10_ciin_3 11 1 -.names un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9 +.names N_225_1.BLIF clk_000_n_sync_i_12__n.BLIF N_225 11 1 -.names N_217.BLIF RST_i.BLIF N_242 +.names ahigh_i_30__n.BLIF ahigh_i_31__n.BLIF un10_ciin_4 11 1 -.names un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10 +.names N_196.BLIF sm_amiga_i_3__n.BLIF N_227 11 1 -.names N_127.BLIF rst_dly_i_2__n.BLIF N_246 +.names a_decode_c_23__n.BLIF AS_030_D0_i.BLIF un10_ciin_5 11 1 -.names un5_ciin_9.BLIF a_i_30__n.BLIF un5_ciin_11 +.names N_228_1.BLIF sm_amiga_i_4__n.BLIF N_228 11 1 -.names N_144.BLIF N_158_i.BLIF N_254 +.names a_decode_c_20__n.BLIF a_decode_c_21__n.BLIF un10_ciin_6 +11 1 +.names N_236_1.BLIF cpu_est_i_3__n.BLIF N_236 +11 1 +.names un10_ciin_1.BLIF un10_ciin_2.BLIF un10_ciin_7 +11 1 +.names N_277_1.BLIF SM_AMIGA_2_.BLIF N_277 +11 1 +.names un10_ciin_3.BLIF un10_ciin_4.BLIF un10_ciin_8 +11 1 +.names N_187.BLIF sm_amiga_i_5__n.BLIF N_281 +11 1 +.names un10_ciin_5.BLIF un10_ciin_6.BLIF un10_ciin_9 +11 1 +.names clk_000_n_sync_i_12__n.BLIF sm_amiga_i_4__n.BLIF N_282 +11 1 +.names un10_ciin_7.BLIF un10_ciin_8.BLIF un10_ciin_10 +11 1 +.names N_191.BLIF sm_amiga_i_6__n.BLIF N_283 +11 1 +.names un10_ciin_9.BLIF a_decode_c_22__n.BLIF un10_ciin_11 +11 1 +.names N_285_1.BLIF cpu_est_i_3__n.BLIF N_285 +11 1 +.names N_157_i.BLIF VMA_INT_i.BLIF N_347_1 +11 1 +.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_318 +11 1 +.names VPA_D_i.BLIF cpu_est_i_1__n.BLIF N_347_2 +11 1 +.names N_319_1.BLIF SM_AMIGA_0_.BLIF N_319 +11 1 +.names AS_000_i.BLIF BGACK_030_INT_i.BLIF pos_clk_un23_bgack_030_int_i_1_0_1_n +11 1 +.names CLK_030_H_i.BLIF N_197.BLIF N_320 +11 1 +.names pos_clk_un23_bgack_030_int_i_0_x2.BLIF N_341_i.BLIF \ +pos_clk_un23_bgack_030_int_i_1_0_2_n +11 1 +.names a_i_1__n.BLIF BGACK_030_INT_i.BLIF N_321 +11 1 +.names FPU_SENSE_i.BLIF N_366.BLIF un21_fpu_cs_1 +11 1 +.names a_c_1__n.BLIF BGACK_030_INT_i.BLIF N_322 11 1 .names un22_berr_1.BLIF FPU_SENSE_c.BLIF un22_berr_1_0 11 1 -.names N_266_1.BLIF rst_dly_i_1__n.BLIF N_266 +.names AS_030_i.BLIF RST_c.BLIF N_323 11 1 -.names FPU_SENSE_i.BLIF N_375.BLIF un21_fpu_cs_1 +.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_366_1 11 1 -.names N_127.BLIF rst_dly_i_1__n.BLIF N_267 +.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_325 11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_375_1 +.names a_decode_c_17__n.BLIF a_decode_i_16__n.BLIF N_366_2 11 1 -.names A1_i.BLIF BGACK_030_INT_i.BLIF N_275 +.names N_327_1.BLIF RW_000_c.BLIF N_327 11 1 -.names a_c_17__n.BLIF a_i_16__n.BLIF N_375_2 +.names a_decode_i_18__n.BLIF a_decode_i_19__n.BLIF N_366_3 11 1 -.names N_219.BLIF sm_amiga_i_0__n.BLIF N_277 +.names BGACK_030_INT_i.BLIF N_181.BLIF N_328 11 1 -.names a_i_18__n.BLIF a_i_19__n.BLIF N_375_3 +.names N_366_1.BLIF N_366_2.BLIF N_366_4 11 1 -.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_278 +.names BGACK_030_INT_i.BLIF N_181_i.BLIF N_329 11 1 -.names N_375_1.BLIF N_375_2.BLIF N_375_4 -11 1 -.names N_297_1.BLIF RW_000_c.BLIF N_297 -11 1 -.names AS_000_i.BLIF N_210_0.BLIF N_134_i_1 -11 1 -.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_300 -11 1 -.names N_192_0.BLIF N_331_i.BLIF N_96_0_1 -11 1 -.names N_212.BLIF sm_amiga_i_2__n.BLIF N_301 -11 1 -.names N_192_0.BLIF N_328_i.BLIF N_83_i_1 -11 1 -.names N_303_1.BLIF SM_AMIGA_2_.BLIF N_303 -11 1 -.names N_242_i.BLIF N_321_i.BLIF N_261_i_1 -11 1 -.names N_304_1.BLIF N_304_2.BLIF N_304 -11 1 -.names N_230.BLIF N_310_i.BLIF N_141_i_1 -11 1 -.names N_218.BLIF sm_amiga_i_5__n.BLIF N_305 -11 1 -.names N_305_i.BLIF N_307_i.BLIF N_139_i_1 -11 1 -.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_307 -11 1 -.names N_229.BLIF N_301_i.BLIF N_133_i_1 -11 1 -.names N_211.BLIF sm_amiga_i_6__n.BLIF N_310 -11 1 -.names N_300_i.BLIF sm_amiga_i_5__n.BLIF N_123_0_1 -11 1 -.names N_290.BLIF N_347.BLIF N_312 -11 1 -.names pos_clk_CYCLE_DMA_5_0_i_x2.BLIF AS_000_i.BLIF N_282_i_1 -11 1 -.names N_313_1.BLIF CLK_000_PE_i.BLIF N_313 -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_343_1 -11 1 -.names N_316_1.BLIF CLK_000_NE_i.BLIF N_316 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_339_1 -11 1 -.names N_317_3.BLIF sm_amiga_i_3__n.BLIF N_317 -11 1 -.names inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n -11 1 -.names N_216.BLIF RESET_OUT_i.BLIF N_320 -11 1 -.names N_168_i.BLIF RST_c.BLIF N_326_1 -11 1 -.names N_144.BLIF RST_DLY_0_.BLIF N_321 -11 1 -.names N_206.BLIF RST_c.BLIF N_325_1 -11 1 -.names N_127.BLIF rst_dly_i_0__n.BLIF N_322 -11 1 -.names inst_CLK_000_NE_D0.BLIF N_201.BLIF N_324_1 -11 1 -.names N_220.BLIF sm_amiga_i_3__n.BLIF N_323 -11 1 -.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c -0 1 -.names N_197.BLIF BERR_i.BLIF N_316_1 -11 1 -.names N_324_1.BLIF sm_amiga_i_4__n.BLIF N_324 -11 1 -.names N_204.BLIF BERR_i.BLIF N_313_1 -11 1 -.names N_325_1.BLIF SM_AMIGA_6_.BLIF N_325 -11 1 -.names N_207.BLIF RST_c.BLIF N_303_1 -11 1 -.names N_326_1.BLIF sm_amiga_i_i_7__n.BLIF N_326 -11 1 -.names AS_000_i.BLIF N_222_i.BLIF N_297_1 -11 1 -.names CLK_030_H_i.BLIF N_221.BLIF N_328 -11 1 -.names N_217_i.BLIF rst_dly_i_0__n.BLIF N_266_1 +.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_163_i.BLIF un1_SM_AMIGA_5_i_1 11 1 .names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_330 11 1 -.names N_24.BLIF N_24_i -0 1 -.names N_158.BLIF N_217_i.BLIF N_240_1 +.names N_346_i.BLIF sm_amiga_i_0__n.BLIF un1_SM_AMIGA_5_i_2 11 1 .names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_331 11 1 -.names N_24_i.BLIF RST_c.BLIF N_35_0 +.names N_163.BLIF N_334_i.BLIF N_142_i_1 11 1 -.names N_215_i.BLIF N_213_i.BLIF pos_clk_ipl_1_n +.names N_190.BLIF sm_amiga_i_2__n.BLIF N_332 11 1 -.names N_332_3.BLIF cpu_est_i_3__n.BLIF N_332 +.names N_335_i.BLIF RST_c.BLIF N_142_i_2 11 1 -.names N_18.BLIF N_18_i +.names CLK_000_P_SYNC_10_.BLIF SM_AMIGA_0_.BLIF N_336 +11 1 +.names clk_000_n_sync_i_12__n.BLIF rst_dly_i_0__n.BLIF N_339_1 +11 1 +.names N_141.BLIF RST_DLY_0_.BLIF N_338 +11 1 +.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_280_1 +11 1 +.names N_339_1.BLIF RST_c.BLIF N_339 +11 1 +.names RST_c.BLIF SM_AMIGA_3_.BLIF N_280_2 +11 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_341 +11 1 +.names CLK_000_N_SYNC_12_.BLIF N_357.BLIF N_231_1 +11 1 +.names N_344_1.BLIF clk_000_d_i_10__n.BLIF N_344 +11 1 +.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_231_2 +11 1 +.names N_347_1.BLIF N_347_2.BLIF N_347 +11 1 +.names CLK_000_P_SYNC_10_.BLIF cpu_est_i_0__n.BLIF N_230_1 +11 1 +.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_348 +11 1 +.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_230_2 +11 1 +.names N_230_1.BLIF N_230_2.BLIF N_230_3 +11 1 +.names N_146.BLIF N_172_i.BLIF N_226_1 +11 1 +.names N_176_i.BLIF sm_amiga_i_0__n.BLIF N_226_2 +11 1 +.names N_226_1.BLIF N_226_2.BLIF N_226_3 +11 1 +.names N_199_0.BLIF N_199 0 1 -.names N_193.BLIF amiga_bus_enable_dma_low_0_un3_n -0 1 -.names N_336_1.BLIF N_336_2.BLIF N_336 +.names N_338_i.BLIF N_339_i.BLIF N_239_i_1 11 1 -.names N_18_i.BLIF RST_c.BLIF N_41_0 +.names N_199.BLIF sm_amiga_i_0__n.BLIF N_324 11 1 -.names N_276_i.BLIF N_193.BLIF amiga_bus_enable_dma_low_0_un1_n +.names N_336_i.BLIF sm_amiga_i_5__n.BLIF N_122_0_1 11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_338 -11 1 -.names N_10.BLIF N_10_i -0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \ -amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n -11 1 -.names N_339_1.BLIF cpu_est_i_3__n.BLIF N_339 -11 1 -.names N_10_i.BLIF RST_c.BLIF N_43_0 -11 1 -.names N_123.BLIF rw_000_int_0_un3_n -0 1 -.names N_185.BLIF cpu_est_2_.BLIF N_340 -11 1 -.names N_7.BLIF N_7_i -0 1 -.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_123.BLIF rw_000_int_0_un1_n -11 1 -.names N_185_i.BLIF cpu_est_2_.BLIF N_341 -11 1 -.names N_7_i.BLIF RST_c.BLIF N_46_0 -11 1 -.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n -11 1 -.names N_181_i.BLIF cpu_est_i_1__n.BLIF N_342 -11 1 -.names N_5.BLIF N_5_i -0 1 -.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n -0 1 -.names N_343_1.BLIF cpu_est_i_3__n.BLIF N_343 -11 1 -.names N_5_i.BLIF RST_c.BLIF N_47_0 -11 1 -.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n -11 1 -.names inst_CLK_000_NE.BLIF N_217_i.BLIF N_344 -11 1 -.names N_4.BLIF N_4_i -0 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ -bgack_030_int_0_un0_n -11 1 -.names LDS_000_c.BLIF UDS_000_c.BLIF N_345 -11 1 -.names N_4_i.BLIF RST_c.BLIF N_48_0 -11 1 -.names N_279.BLIF as_030_000_sync_0_un3_n -0 1 -.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_347 -11 1 -.names N_272.BLIF N_272_i -0 1 -.names inst_AS_030_000_SYNC.BLIF N_279.BLIF as_030_000_sync_0_un1_n -11 1 -.names CLK_000_N_SYNC_9_.BLIF N_175.BLIF N_350 -11 1 -.names N_271.BLIF N_271_i -0 1 -.names pos_clk_un3_as_030_d0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 -.names N_351_1.BLIF N_351_2.BLIF N_351 -11 1 -.names N_271_i.BLIF N_272_i.BLIF N_279_0 -11 1 -.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n -0 1 -.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_353 -11 1 -.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_280_0 -11 1 -.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF \ -ds_000_enable_0_un1_n -11 1 -.names N_185_i.BLIF cpu_est_i_2__n.BLIF N_361 -11 1 -.names N_236_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_281_0 -11 1 -.names un1_SM_AMIGA_5_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n -11 1 -.names N_298.BLIF N_298_i -0 1 -.names N_280.BLIF as_000_int_0_un3_n -0 1 -.names N_298_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n -11 1 -.names sm_amiga_i_5__n.BLIF N_280.BLIF as_000_int_0_un1_n -11 1 -.names N_299.BLIF N_299_i -0 1 -.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n -11 1 -.names N_299_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n -11 1 -.names N_281.BLIF dsack1_int_0_un3_n -0 1 .names AS_030_i.BLIF BGACK_000_c.BLIF un22_berr_1 11 1 -.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF un1_as_000_i +.names N_211_i.BLIF N_332_i.BLIF N_132_i_1 11 1 -.names N_236_i.BLIF N_281.BLIF dsack1_int_0_un1_n +.names N_366_4.BLIF N_366_3.BLIF N_366 11 1 -.names N_375_4.BLIF N_375_3.BLIF N_375 +.names N_331_i.BLIF RW_000_i.BLIF N_120_0_1 11 1 -.names N_358.BLIF N_358_i +.names N_137.BLIF SM_AMIGA_i_7_.BLIF N_335 +11 1 +.names N_320_i.BLIF RST_c.BLIF N_106_i_1 +11 1 +.names CLK_000_P_SYNC_10_.BLIF CYCLE_DMA_0_.BLIF N_208 +11 1 +.names AS_000_i.BLIF N_186_0.BLIF N_103_i_1 +11 1 +.names N_203_i.BLIF N_203 0 1 -.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +.names AS_000_i.BLIF N_186_0.BLIF N_92_i_1 11 1 -.names N_218_0.BLIF N_218 +.names N_187_0.BLIF N_187 0 1 -.names BGACK_000_c.BLIF N_358_i.BLIF pos_clk_un6_bgack_000_0_n +.names N_206_i.BLIF N_283_i.BLIF N_140_i_1 11 1 -.names N_286.BLIF size_dma_0_1__un3_n +.names N_137_i.BLIF N_137 0 1 -.names N_156_i.BLIF N_156 +.names N_281_i.BLIF N_282_i.BLIF N_138_i_1 +11 1 +.names N_137.BLIF SM_AMIGA_0_.BLIF N_349 +11 1 +.names N_148.BLIF CLK_000_D_11_.BLIF N_344_1 +11 1 +.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n 0 1 -.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_284_i +.names nEXP_SPACE_c.BLIF inst_AS_030_D0.BLIF pos_clk_un6_bg_030_1_n 11 1 -.names pos_clk_size_dma_6_1__n.BLIF N_286.BLIF size_dma_0_1__un1_n +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_10 +1- 1 +-1 1 +.names AS_000_i.BLIF N_200_i.BLIF N_327_1 11 1 -.names N_289_0.BLIF N_289 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_5 +1- 1 +-1 1 +.names inst_BGACK_030_INTreg.BLIF CLK_000_c.BLIF N_319_1 +11 1 +.names N_293_0.BLIF N_293 0 1 -.names N_222_i.BLIF inst_RESET_OUT.BLIF N_285_i +.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_285_1 11 1 -.names SIZE_DMA_1_.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n -11 1 -.names N_156.BLIF SM_AMIGA_0_.BLIF N_354 -11 1 -.names N_193_i.BLIF RST_c.BLIF N_286_0 -11 1 -.names N_286.BLIF size_dma_0_0__un3_n -0 1 -.names N_205_i.BLIF N_205 -0 1 -.names AS_030_i.BLIF RST_c.BLIF N_88_0 -11 1 -.names pos_clk_size_dma_6_0__n.BLIF N_286.BLIF size_dma_0_0__un1_n +.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6 +1- 1 +-1 1 +.names N_184.BLIF RST_c.BLIF N_277_1 11 1 .names un1_SM_AMIGA_5_i.BLIF un1_SM_AMIGA_5 0 1 -.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_236_1 11 1 -.names SIZE_DMA_0_.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +.names pos_clk_un3_as_030_d0_i_n.BLIF un1_SM_AMIGA_5.BLIF \ +DS_000_ENABLE_1_sqmuxa_1 11 1 -.names RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa +.names inst_CLK_000_NE_D0.BLIF N_178.BLIF N_228_1 11 1 -.names BERR_c.BLIF CLK_000_PE_i.BLIF N_156_i -11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un3_n -0 1 -.names CLK_000_PE_i.BLIF SM_AMIGA_4_.BLIF N_349 -11 1 -.names N_349.BLIF N_349_i -0 1 -.names BERR_c.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_m2_1__un1_n +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_7 +1- 1 +-1 1 +.names N_172.BLIF BERR_i.BLIF N_225_1 11 1 .names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n 0 1 -.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_194_i -11 1 -.names inst_CLK_000_PE.BLIF sm_amiga_srsts_i_0_m2_1__un3_n.BLIF \ -sm_amiga_srsts_i_0_m2_1__un0_n -11 1 -.names N_286_0.BLIF N_286 +.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c 0 1 -.names un1_SM_AMIGA_5_i_1.BLIF un1_SM_AMIGA_5_i_2.BLIF un1_SM_AMIGA_5_i +.names N_176.BLIF BERR_i.BLIF N_224_1 11 1 -.names inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0__un3_n +.names N_290_0.BLIF N_290 0 1 -.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n +.names N_216_i.BLIF rst_dly_i_0__n.BLIF N_222_1 +11 1 +.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_18 +1- 1 +-1 1 +.names N_149.BLIF N_216_i.BLIF N_215_1 +11 1 +.names RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa +11 1 +.names N_214_i.BLIF N_212_i.BLIF pos_clk_ipl_1_n +11 1 +.names N_194.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_232 +11 1 +.names pos_clk_un9_bg_030_n.BLIF bg_000_0_un3_n 0 1 -.names UDS_000_c.BLIF UDS_000_c_i +.names N_194_0.BLIF N_194 0 1 -.names sm_amiga_i_i_7__n.BLIF inst_BGACK_030_INTreg.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un1_n -11 1 -.names AS_000_c.BLIF inst_CLK_000_PE.BLIF N_358 -11 1 -.names LDS_000_c.BLIF LDS_000_c_i +.names BG_030_c.BLIF BG_030_c_i 0 1 -.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un3_n.BLIF \ -un1_amiga_bus_enable_dma_high_i_m2_0__un0_n +.names BG_030_c.BLIF pos_clk_un9_bg_030_n.BLIF bg_000_0_un1_n 11 1 -.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n +.names N_366.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_233 +11 1 +.names pos_clk_un6_bg_030_n.BLIF pos_clk_un6_bg_030_i_n 0 1 -.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_205_i +.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_m2_5__un3_n +.names N_153.BLIF SM_AMIGA_1_.BLIF N_275 +11 1 +.names BG_030_c_i.BLIF pos_clk_un6_bg_030_i_n.BLIF pos_clk_un9_bg_030_0_n +11 1 +.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n 0 1 -.names BGACK_030_INT_i.BLIF N_205_i.BLIF N_299 -11 1 -.names N_156.BLIF SM_AMIGA_i_7_.BLIF N_206_0 -11 1 -.names BERR_c.BLIF SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_m2_5__un1_n -11 1 -.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n +.names N_153_0.BLIF N_153 0 1 -.names N_156.BLIF sm_amiga_i_3__n.BLIF N_207_0 -11 1 -.names inst_CLK_000_PE.BLIF sm_amiga_srsts_i_0_m2_5__un3_n.BLIF \ -sm_amiga_srsts_i_0_m2_5__un0_n -11 1 -.names BGACK_030_INT_i.BLIF N_205.BLIF N_298 -11 1 -.names N_354.BLIF N_354_i +.names N_26.BLIF N_26_i 0 1 -.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n -0 1 -.names N_281_0.BLIF N_281 -0 1 -.names N_354_i.BLIF RST_c.BLIF N_208_0 +.names a_c_0__n.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n 11 1 -.names cpu_est_2_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n +.names N_191_0.BLIF N_191 +0 1 +.names N_26_i.BLIF RST_c.BLIF N_33_0 +11 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names N_146.BLIF sm_amiga_i_6__n.BLIF N_334 +11 1 +.names N_21.BLIF N_21_i +0 1 +.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n +0 1 +.names N_146_0.BLIF N_146 +0 1 +.names N_21_i.BLIF RST_c.BLIF N_38_0 +11 1 +.names pos_clk_un10_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n +11 1 +.names CLK_000_D_12_.BLIF clk_000_d_i_11__n.BLIF N_345 +11 1 +.names N_17.BLIF N_17_i +0 1 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names clk_000_p_sync_i_10__n.BLIF SM_AMIGA_4_.BLIF N_346 +11 1 +.names N_17_i.BLIF RST_c.BLIF N_42_0 +11 1 +.names N_258.BLIF dsack1_int_0_un3_n +0 1 +.names N_163_i.BLIF N_163 +0 1 +.names N_4.BLIF N_4_i +0 1 +.names N_275_i.BLIF N_258.BLIF dsack1_int_0_un1_n +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_22 +1- 1 +-1 1 +.names N_4_i.BLIF RST_c.BLIF N_48_0 +11 1 +.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +11 1 +.names pos_clk_un4_clk_000_pe_0_n.BLIF pos_clk_un4_clk_000_pe_n +0 1 +.names ipl_c_0__n.BLIF ipl_c_i_0__n +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n +0 1 +.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n +0 1 +.names ipl_c_i_0__n.BLIF RST_c.BLIF N_51_0 +11 1 +.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n +11 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_235 +11 1 +.names ipl_c_1__n.BLIF ipl_c_i_1__n +0 1 +.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names N_154_i.BLIF cpu_est_i_1__n.BLIF N_284 +11 1 +.names ipl_c_i_1__n.BLIF RST_c.BLIF N_52_0 +11 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n +0 1 +.names N_190_0.BLIF N_190 +0 1 +.names ipl_c_2__n.BLIF ipl_c_i_2__n +0 1 +.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n +11 1 +.names N_195.BLIF RESET_OUT_i.BLIF N_337 +11 1 +.names ipl_c_i_2__n.BLIF RST_c.BLIF N_53_0 +11 1 +.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names N_195_0.BLIF N_195 +0 1 +.names N_27.BLIF N_27_i +0 1 +.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n +0 1 +.names CLK_000_N_SYNC_12_.BLIF N_166.BLIF N_340 +11 1 +.names N_27_i.BLIF RST_c.BLIF N_30_0 +11 1 +.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n +11 1 +.names N_231_1.BLIF N_231_2.BLIF N_231 +11 1 +.names N_28.BLIF N_28_i +0 1 +.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names N_230_3.BLIF cpu_est_i_3__n.BLIF N_230 +11 1 +.names N_28_i.BLIF RST_c.BLIF N_31_0 +11 1 +.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n +0 1 +.names N_280_1.BLIF N_280_2.BLIF N_280 +11 1 +.names N_29.BLIF N_29_i +0 1 +.names N_291.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n 11 1 .names IPL_030DFF_2_reg.BLIF IPL_030_2_ 1 1 @@ -1674,7 +1737,7 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names vcc_n_n.BLIF AVEC 1 1 0 0 -.names N_124.BLIF E +.names N_292.BLIF E 1 1 0 0 .names inst_VMA_INTreg.BLIF VMA @@ -1692,10 +1755,10 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_227.BLIF AMIGA_BUS_ENABLE_HIGH +.names un1_amiga_bus_enable_dma_high_0__n.BLIF AMIGA_BUS_ENABLE_HIGH 1 1 0 0 -.names un5_ciin.BLIF CIIN +.names un10_ciin.BLIF CIIN 1 1 0 0 .names IPL_030DFF_1_reg.BLIF IPL_030_1_ @@ -1704,6 +1767,15 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names IPL_030DFF_0_reg.BLIF IPL_030_0_ 1 1 0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -1719,6 +1791,12 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF SM_AMIGA_0_.C 1 1 0 0 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF cpu_est_3_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C 1 1 0 0 @@ -1737,13 +1815,28 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF IPL_D0_2_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C +.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C +1 1 +0 0 +.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C +1 1 +0 0 +.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C 1 1 0 0 .names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D @@ -1758,6 +1851,12 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C 1 1 0 0 +.names CLK_000_N_SYNC_11_.BLIF CLK_000_N_SYNC_12_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_12_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C 1 1 0 0 @@ -1770,7 +1869,7 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF SIZE_DMA_1_.C 1 1 0 0 -.names cpu_est_0_0_x2_0_.BLIF cpu_est_0_.D +.names cpu_est_0_0_x2_0_x2_0_.BLIF cpu_est_0_.D 1 1 0 0 .names CLK_OSZI_c.BLIF cpu_est_0_.C @@ -1779,10 +1878,22 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF cpu_est_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_2_.C +.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D 1 1 0 0 -.names CLK_OSZI_c.BLIF cpu_est_3_.C +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C +1 1 +0 0 +.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C +1 1 +0 0 +.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C 1 1 0 0 .names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D @@ -1815,7 +1926,10 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C 1 1 0 0 -.names N_148_i.BLIF CLK_000_N_SYNC_0_.D +.names CLK_000_P_SYNC_9_.BLIF CLK_000_P_SYNC_10_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_10_.C 1 1 0 0 .names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C @@ -1851,37 +1965,7 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C 1 1 0 0 -.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C -1 1 -0 0 -.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C -1 1 -0 0 -.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C -1 1 -0 0 -.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF RST_DLY_1_.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF RST_DLY_2_.C -1 1 -0 0 -.names CLK_000.BLIF CLK_000_D_0_.D +.names CLK_000_c.BLIF CLK_000_D_0_.D 1 1 0 0 .names CLK_OSZI_c.BLIF CLK_000_D_0_.C @@ -1893,6 +1977,72 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF CLK_000_D_1_.C 1 1 0 0 +.names CLK_000_D_1_.BLIF CLK_000_D_2_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_2_.C +1 1 +0 0 +.names CLK_000_D_2_.BLIF CLK_000_D_3_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_3_.C +1 1 +0 0 +.names CLK_000_D_3_.BLIF CLK_000_D_4_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_4_.C +1 1 +0 0 +.names CLK_000_D_4_.BLIF CLK_000_D_5_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_5_.C +1 1 +0 0 +.names CLK_000_D_5_.BLIF CLK_000_D_6_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_6_.C +1 1 +0 0 +.names CLK_000_D_6_.BLIF CLK_000_D_7_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_7_.C +1 1 +0 0 +.names CLK_000_D_7_.BLIF CLK_000_D_8_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_8_.C +1 1 +0 0 +.names CLK_000_D_8_.BLIF CLK_000_D_9_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_9_.C +1 1 +0 0 +.names CLK_000_D_9_.BLIF CLK_000_D_10_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_10_.C +1 1 +0 0 +.names CLK_000_D_10_.BLIF CLK_000_D_11_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_11_.C +1 1 +0 0 +.names CLK_000_D_11_.BLIF CLK_000_D_12_.D +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_000_D_12_.C +1 1 +0 0 .names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C 1 1 0 0 @@ -1902,46 +2052,13 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C 1 1 0 0 -.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C -1 1 -0 0 -.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C -1 1 -0 0 -.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C -1 1 -0 0 .names CLK_OSZI_c.BLIF RST_DLY_0_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +.names CLK_OSZI_c.BLIF RST_DLY_1_.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_D0.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_nEXP_SPACE_D0reg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_VPA_D.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +.names CLK_OSZI_c.BLIF RST_DLY_2_.C 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_030_H.C @@ -1953,15 +2070,6 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C 1 1 0 0 -.names CLK_OSZI_c.BLIF BG_000DFFreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 0 0 @@ -1989,15 +2097,42 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C 1 1 0 0 -.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D +.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_D0.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_VPA_D.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DTACK_D0.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF BG_000DFFreg.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C +1 1 +0 0 +.names CLK_000_N_SYNC_12_.BLIF inst_CLK_000_NE_D0.D 1 1 0 0 .names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C +1 1 +0 0 .names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_D.D 1 1 0 0 @@ -2010,25 +2145,16 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 0 0 -.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_000_PE.C -1 1 -0 0 -.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C 1 1 0 0 .names un3_size.BLIF SIZE_1_ 1 1 0 0 -.names N_138.BLIF AS_030 +.names gnd_n_n.BLIF AHIGH_31_ +1 1 +0 0 +.names un6_as_030_i.BLIF AS_030 1 1 0 0 .names un4_as_000_i.BLIF AS_000 @@ -2043,9 +2169,6 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names un4_lds_000_i.BLIF LDS_000 1 1 0 0 -.names inst_A0_DMA.BLIF A0 -1 1 -0 0 .names gnd_n_n.BLIF BERR 1 1 0 0 @@ -2055,46 +2178,70 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names un4_size.BLIF SIZE_0_ 1 1 0 0 -.names A_15_.BLIF a_15__n +.names gnd_n_n.BLIF AHIGH_30_ 1 1 0 0 -.names A_14_.BLIF a_14__n +.names gnd_n_n.BLIF AHIGH_29_ 1 1 0 0 -.names A_13_.BLIF a_13__n +.names gnd_n_n.BLIF AHIGH_28_ 1 1 0 0 -.names A_12_.BLIF a_12__n +.names gnd_n_n.BLIF AHIGH_27_ 1 1 0 0 -.names A_11_.BLIF a_11__n +.names gnd_n_n.BLIF AHIGH_26_ 1 1 0 0 -.names A_10_.BLIF a_10__n +.names gnd_n_n.BLIF AHIGH_25_ 1 1 0 0 -.names A_9_.BLIF a_9__n +.names gnd_n_n.BLIF AHIGH_24_ 1 1 0 0 -.names A_8_.BLIF a_8__n +.names inst_A0_DMA.BLIF A_0_ 1 1 0 0 -.names A_7_.BLIF a_7__n +.names A_DECODE_15_.BLIF a_decode_15__n 1 1 0 0 -.names A_6_.BLIF a_6__n +.names A_DECODE_14_.BLIF a_decode_14__n 1 1 0 0 -.names A_5_.BLIF a_5__n +.names A_DECODE_13_.BLIF a_decode_13__n 1 1 0 0 -.names A_4_.BLIF a_4__n +.names A_DECODE_12_.BLIF a_decode_12__n 1 1 0 0 -.names A_3_.BLIF a_3__n +.names A_DECODE_11_.BLIF a_decode_11__n 1 1 0 0 -.names A_2_.BLIF a_2__n +.names A_DECODE_10_.BLIF a_decode_10__n +1 1 +0 0 +.names A_DECODE_9_.BLIF a_decode_9__n +1 1 +0 0 +.names A_DECODE_8_.BLIF a_decode_8__n +1 1 +0 0 +.names A_DECODE_7_.BLIF a_decode_7__n +1 1 +0 0 +.names A_DECODE_6_.BLIF a_decode_6__n +1 1 +0 0 +.names A_DECODE_5_.BLIF a_decode_5__n +1 1 +0 0 +.names A_DECODE_4_.BLIF a_decode_4__n +1 1 +0 0 +.names A_DECODE_3_.BLIF a_decode_3__n +1 1 +0 0 +.names A_DECODE_2_.BLIF a_decode_2__n 1 1 0 0 .names AS_030.PIN.BLIF AS_030_c @@ -2118,58 +2265,58 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names SIZE_1_.PIN.BLIF size_c_1__n 1 1 0 0 -.names A_16_.BLIF a_c_16__n +.names AHIGH_24_.PIN.BLIF ahigh_c_24__n 1 1 0 0 -.names A_17_.BLIF a_c_17__n +.names AHIGH_25_.PIN.BLIF ahigh_c_25__n 1 1 0 0 -.names A_18_.BLIF a_c_18__n +.names AHIGH_26_.PIN.BLIF ahigh_c_26__n 1 1 0 0 -.names A_19_.BLIF a_c_19__n +.names AHIGH_27_.PIN.BLIF ahigh_c_27__n 1 1 0 0 -.names A_20_.BLIF a_c_20__n +.names AHIGH_28_.PIN.BLIF ahigh_c_28__n 1 1 0 0 -.names A_21_.BLIF a_c_21__n +.names AHIGH_29_.PIN.BLIF ahigh_c_29__n 1 1 0 0 -.names A_22_.BLIF a_c_22__n +.names AHIGH_30_.PIN.BLIF ahigh_c_30__n 1 1 0 0 -.names A_23_.BLIF a_c_23__n +.names AHIGH_31_.PIN.BLIF ahigh_c_31__n 1 1 0 0 -.names A_24_.BLIF a_c_24__n +.names A_DECODE_16_.BLIF a_decode_c_16__n 1 1 0 0 -.names A_25_.BLIF a_c_25__n +.names A_DECODE_17_.BLIF a_decode_c_17__n 1 1 0 0 -.names A_26_.BLIF a_c_26__n +.names A_DECODE_18_.BLIF a_decode_c_18__n 1 1 0 0 -.names A_27_.BLIF a_c_27__n +.names A_DECODE_19_.BLIF a_decode_c_19__n 1 1 0 0 -.names A_28_.BLIF a_c_28__n +.names A_DECODE_20_.BLIF a_decode_c_20__n 1 1 0 0 -.names A_29_.BLIF a_c_29__n +.names A_DECODE_21_.BLIF a_decode_c_21__n 1 1 0 0 -.names A_30_.BLIF a_c_30__n +.names A_DECODE_22_.BLIF a_decode_c_22__n 1 1 0 0 -.names A_31_.BLIF a_c_31__n +.names A_DECODE_23_.BLIF a_decode_c_23__n 1 1 0 0 -.names A0.PIN.BLIF A0_c +.names A_0_.PIN.BLIF a_c_0__n 1 1 0 0 -.names A1.BLIF A1_c +.names A_1_.BLIF a_c_1__n 1 1 0 0 .names nEXP_SPACE.BLIF nEXP_SPACE_c @@ -2187,6 +2334,9 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names CLK_030.BLIF CLK_030_c 1 1 0 0 +.names CLK_000.BLIF CLK_000_c +1 1 +0 0 .names CLK_OSZI.BLIF CLK_OSZI_c 1 1 0 0 @@ -2220,7 +2370,7 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names FC_1_.BLIF fc_c_1__n 1 1 0 0 -.names N_285_i.BLIF AS_030.OE +.names un3_as_030_i.BLIF AS_030.OE 1 1 0 0 .names un1_as_000_i.BLIF AS_000.OE @@ -2235,31 +2385,55 @@ sm_amiga_srsts_i_0_m2_5__un0_n .names un1_as_000_i.BLIF LDS_000.OE 1 1 0 0 -.names N_222_i.BLIF SIZE_0_.OE +.names N_200_i.BLIF SIZE_0_.OE 1 1 0 0 -.names N_222_i.BLIF SIZE_1_.OE +.names N_200_i.BLIF SIZE_1_.OE 1 1 0 0 -.names N_285_i.BLIF A0.OE +.names un3_as_030_i.BLIF AHIGH_24_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF AHIGH_25_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF AHIGH_26_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF AHIGH_27_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF AHIGH_28_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF AHIGH_29_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF AHIGH_30_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF AHIGH_31_.OE +1 1 +0 0 +.names un3_as_030_i.BLIF A_0_.OE 1 1 0 0 .names un22_berr.BLIF BERR.OE 1 1 0 0 -.names N_284_i.BLIF RW.OE +.names N_318.BLIF RW.OE 1 1 0 0 -.names N_285_i.BLIF DS_030.OE +.names un3_as_030_i.BLIF DS_030.OE 1 1 0 0 -.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE +.names nEXP_SPACE_c.BLIF DSACK1.OE 1 1 0 0 .names RESET_OUT_i.BLIF RESET.OE 1 1 0 0 -.names N_61.BLIF CIIN.OE +.names N_296.BLIF CIIN.OE 1 1 0 0 .names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_134 @@ -2277,23 +2451,22 @@ sm_amiga_srsts_i_0_m2_5__un0_n 10 1 11 0 00 0 -.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \ -pos_clk_un23_bgack_030_int_i_i_a4_i_x2 +.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF pos_clk_un23_bgack_030_int_i_0_x2 01 1 10 1 11 0 00 0 -.names CYCLE_DMA_0_.BLIF inst_CLK_000_PE.BLIF pos_clk_CYCLE_DMA_5_0_i_x2 +.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_x2_0_ 01 1 10 1 11 0 00 0 -.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_ +.names CYCLE_DMA_0_.BLIF CLK_000_P_SYNC_10_.BLIF pos_clk_CYCLE_DMA_5_0_i_x2 01 1 10 1 11 0 00 0 -.names CYCLE_DMA_1_.BLIF N_209.BLIF pos_clk_CYCLE_DMA_5_1_i_x2 +.names CYCLE_DMA_1_.BLIF N_208.BLIF pos_clk_CYCLE_DMA_5_1_i_x2 01 1 10 1 11 0 diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index 2fa153c..c87028c 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2016 8 17 17 45 43) + (timeStamp 2016 8 19 0 20 36) (author "Synopsys, Inc.") (program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R")) ) @@ -99,7 +99,9 @@ (view behavioral (viewType NETLIST) (interface (port (array (rename size "SIZE(1:0)") 2) (direction INOUT)) - (port (array (rename a "A(31:2)") 30) (direction INPUT)) + (port (array (rename ahigh "AHIGH(31:24)") 8) (direction INOUT)) + (port (array (rename a_decode "A_DECODE(23:2)") 22) (direction INPUT)) + (port (array (rename a "A(1:0)") 2) (direction INOUT)) (port (array (rename ipl_030 "IPL_030(2:0)") 3) (direction OUTPUT)) (port (array (rename ipl "IPL(2:0)") 3) (direction INPUT)) (port (array (rename fc "FC(1:0)") 2) (direction INPUT)) @@ -109,8 +111,6 @@ (port DS_030 (direction OUTPUT)) (port UDS_000 (direction INOUT)) (port LDS_000 (direction INOUT)) - (port A0 (direction INOUT)) - (port A1 (direction INPUT)) (port nEXP_SPACE (direction INPUT)) (port BERR (direction INOUT)) (port BG_030 (direction INPUT)) @@ -140,6 +140,12 @@ (port CIIN (direction OUTPUT)) ) (contents + (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -150,6 +156,10 @@ ) (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename IPL_030DFF_0 "IPL_030DFF[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename IPL_030DFF_1 "IPL_030DFF[1]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -162,16 +172,20 @@ ) (instance (rename IPL_D0_2 "IPL_D0[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_N_SYNC_6 "CLK_000_N_SYNC[6]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_N_SYNC_7 "CLK_000_N_SYNC[7]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance (rename CLK_000_N_SYNC_12 "CLK_000_N_SYNC[12]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -184,9 +198,11 @@ ) (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_P_SYNC_2 "CLK_000_P_SYNC[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename CLK_000_P_SYNC_3 "CLK_000_P_SYNC[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_4 "CLK_000_P_SYNC[4]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_P_SYNC_5 "CLK_000_P_SYNC[5]") (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -198,6 +214,8 @@ ) (instance (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance (rename CLK_000_P_SYNC_10 "CLK_000_P_SYNC[10]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename CLK_000_N_SYNC_0 "CLK_000_N_SYNC[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_N_SYNC_1 "CLK_000_N_SYNC[1]") (viewRef prim (cellRef DFF (libraryRef mach))) @@ -210,47 +228,41 @@ ) (instance (rename CLK_000_N_SYNC_5 "CLK_000_N_SYNC[5]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_N_SYNC_6 "CLK_000_N_SYNC[6]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_7 "CLK_000_N_SYNC[7]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename RST_DLY_1 "RST_DLY[1]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename RST_DLY_2 "RST_DLY[2]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance (rename CLK_000_D_0 "CLK_000_D[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_D_1 "CLK_000_D[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance (rename CLK_000_D_2 "CLK_000_D[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_D_3 "CLK_000_D[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_D_4 "CLK_000_D[4]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_D_5 "CLK_000_D[5]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_D_6 "CLK_000_D[6]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_D_7 "CLK_000_D[7]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_D_8 "CLK_000_D[8]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_D_9 "CLK_000_D[9]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_D_10 "CLK_000_D[10]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_D_11 "CLK_000_D[11]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_D_12 "CLK_000_D[12]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance (rename CLK_000_P_SYNC_1 "CLK_000_P_SYNC[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance (rename CLK_000_P_SYNC_2 "CLK_000_P_SYNC[2]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_P_SYNC_3 "CLK_000_P_SYNC[3]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance (rename CLK_000_P_SYNC_4 "CLK_000_P_SYNC[4]") (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance (rename RST_DLY_0 "RST_DLY[0]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance AS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename RST_DLY_1 "RST_DLY[1]") (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance DSACK1_INT (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance DS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AS_030_D0 (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance nEXP_SPACE_D0 (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance VPA_D (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance DTACK_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + (instance (rename RST_DLY_2 "RST_DLY[2]") (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance CLK_030_H (viewRef prim (cellRef DFF (libraryRef mach))) ) @@ -258,12 +270,6 @@ ) (instance DS_000_ENABLE (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance BG_000DFF (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance AMIGA_BUS_ENABLE_DMA_LOW (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance VMA_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance UDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) @@ -282,18 +288,32 @@ ) (instance AS_030_000_SYNC (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance BGACK_030_INT_D (viewRef prim (cellRef DFF (libraryRef mach))) + (instance AS_000_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance DSACK1_INT (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance DS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_030_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance VPA_D (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance DTACK_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance BG_000DFF (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AMIGA_BUS_ENABLE_DMA_LOW (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance CLK_000_NE_D0 (viewRef prim (cellRef DFF (libraryRef mach))) ) + (instance BGACK_030_INT_D (viewRef prim (cellRef DFF (libraryRef mach))) + ) (instance CLK_OUT_PRE_D (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance CLK_OUT_INT (viewRef prim (cellRef DFF (libraryRef mach))) ) - (instance CLK_000_PE (viewRef prim (cellRef DFF (libraryRef mach))) - ) - (instance CLK_000_NE (viewRef prim (cellRef DFF (libraryRef mach))) - ) (instance CLK_OUT_PRE_50 (viewRef prim (cellRef DFF (libraryRef mach))) ) (instance AS_030 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) @@ -304,38 +324,38 @@ (instance LDS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) (instance (rename SIZE_0 "SIZE[0]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) (instance (rename SIZE_1 "SIZE[1]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) - (instance (rename A_2 "A[2]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_3 "A[3]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_4 "A[4]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_5 "A[5]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_6 "A[6]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_7 "A[7]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_8 "A[8]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_9 "A[9]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_10 "A[10]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_11 "A[11]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_12 "A[12]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_13 "A[13]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_14 "A[14]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_15 "A[15]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_16 "A[16]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_17 "A[17]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_18 "A[18]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_19 "A[19]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_20 "A[20]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_21 "A[21]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_22 "A[22]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_23 "A[23]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_24 "A[24]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_25 "A[25]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_26 "A[26]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_27 "A[27]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_28 "A[28]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_29 "A[29]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_30 "A[30]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_31 "A[31]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance A0 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) - (instance A1 (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename AHIGH_24 "AHIGH[24]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename AHIGH_25 "AHIGH[25]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename AHIGH_26 "AHIGH[26]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename AHIGH_27 "AHIGH[27]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename AHIGH_28 "AHIGH[28]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename AHIGH_29 "AHIGH[29]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename AHIGH_30 "AHIGH[30]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename AHIGH_31 "AHIGH[31]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename A_DECODE_2 "A_DECODE[2]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_3 "A_DECODE[3]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_4 "A_DECODE[4]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_5 "A_DECODE[5]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_6 "A_DECODE[6]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_7 "A_DECODE[7]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_8 "A_DECODE[8]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_9 "A_DECODE[9]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_10 "A_DECODE[10]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_11 "A_DECODE[11]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_12 "A_DECODE[12]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_13 "A_DECODE[13]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_14 "A_DECODE[14]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_15 "A_DECODE[15]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_16 "A_DECODE[16]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_17 "A_DECODE[17]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_18 "A_DECODE[18]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_19 "A_DECODE[19]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_20 "A_DECODE[20]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_21 "A_DECODE[21]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_22 "A_DECODE[22]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_DECODE_23 "A_DECODE[23]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_0 "A[0]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename A_1 "A[1]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) (instance nEXP_SPACE (viewRef prim (cellRef IBUF (libraryRef mach))) ) (instance BERR (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) (instance BG_030 (viewRef prim (cellRef IBUF (libraryRef mach))) ) @@ -371,580 +391,583 @@ (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_HIGH (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_a3_2 "SM_AMIGA_srsts_i_i_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a3_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_a2_0_0 "SM_AMIGA_nss_i_i_0_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_a2_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance G_137_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance G_137 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a3_1_1_1 "cpu_est_2_0_0_a3_1_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_a3_1_1 "cpu_est_2_0_0_a3_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_0_a2_0_a3_1 "pos_clk.un6_bg_030_0_a2_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_0_a2_0_a3 "pos_clk.un6_bg_030_0_a2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_a3_0_1_6 "SM_AMIGA_srsts_i_i_0_a3_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_a3_0_6 "SM_AMIGA_srsts_i_i_0_a3_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_a3_1_6 "SM_AMIGA_srsts_i_i_0_a3_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_a3_6 "SM_AMIGA_srsts_i_i_0_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a3_0_1_3 "SM_AMIGA_srsts_i_0_0_a3_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a3_0_3 "SM_AMIGA_srsts_i_0_0_a3_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_a3_1_1_0 "SM_AMIGA_nss_i_i_0_a3_1_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_a3_1_0 "SM_AMIGA_nss_i_i_0_a3_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_a3_0_1_0 "SM_AMIGA_nss_i_i_0_a3_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_a3_0_0 "SM_AMIGA_nss_i_i_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_a3_1_2 "SM_AMIGA_srsts_i_i_a3_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_2_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_1_5 "SM_AMIGA_srsts_i_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_5 "SM_AMIGA_srsts_i_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_1_4 "SM_AMIGA_srsts_i_0_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_4 "SM_AMIGA_srsts_i_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_1_1 "SM_AMIGA_srsts_i_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_1 "SM_AMIGA_srsts_i_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_3_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_3_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_1 "pos_clk.CYCLE_DMA_5_0_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i "pos_clk.CYCLE_DMA_5_0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_i_i_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_i_i_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_ciin_0_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un22_berr_0_a2_0_a3_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un22_berr_0_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_fpu_cs_0_a2_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un21_fpu_cs_0_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un22_berr_0_a2_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un22_berr_0_a2_0_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un22_berr_0_a2_0_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un22_berr_0_a2_0_a2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un22_berr_0_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_1_0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_i_i_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_i_i_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_0_a2_1_2 "SM_AMIGA_srsts_i_i_0_a2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_0_a2_2 "SM_AMIGA_srsts_i_i_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a2_1_1_1 "cpu_est_2_0_0_a2_1_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a2_1_1 "cpu_est_2_0_0_a2_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_1_3 "SM_AMIGA_srsts_i_0_0_a2_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_3 "SM_AMIGA_srsts_i_0_0_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_a2_1_1_0 "SM_AMIGA_nss_i_i_0_0_a2_1_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_a2_1_0 "SM_AMIGA_nss_i_i_0_0_a2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_a2_0_1_0 "SM_AMIGA_nss_i_i_0_0_a2_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_CYCLE_DMA_5_1_i_1 "pos_clk.CYCLE_DMA_5_1_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename pos_clk_CYCLE_DMA_5_1_i "pos_clk.CYCLE_DMA_5_1_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_0_a2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_2_0_a2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_a3_2_0 "SM_AMIGA_nss_i_i_0_a3_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_a3_0_1_2 "SM_AMIGA_srsts_i_i_a3_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_a3_0_2_2 "SM_AMIGA_srsts_i_i_a3_0_2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_a3_0_2 "SM_AMIGA_srsts_i_i_a3_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_ciin_0_a2_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_ciin_0_a2_0_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_ciin_0_a2_0_a3_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_ciin_0_a2_0_a3_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_ciin_0_a2_0_a3_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_ciin_0_a2_0_a3_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_ciin_0_a2_0_a3_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_ciin_0_a2_0_a3_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_ciin_0_a2_0_a3_9 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_ciin_0_a2_0_a3_10 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_ciin_0_a2_0_a3_11 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_1 "pos_clk.CYCLE_DMA_5_0_i_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i "pos_clk.CYCLE_DMA_5_0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_1_5 "SM_AMIGA_srsts_i_0_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_5 "SM_AMIGA_srsts_i_0_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_1_4 "SM_AMIGA_srsts_i_0_0_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_4 "SM_AMIGA_srsts_i_0_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_0_a2_1 "pos_clk.un6_bg_030_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_0_a2 "pos_clk.un6_bg_030_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un4_clk_000_pe_0_0_a2_1 "pos_clk.un4_clk_000_pe_0_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un4_clk_000_pe_0_0_a2_2 "pos_clk.un4_clk_000_pe_0_0_a2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un4_clk_000_pe_0_0_a2_3 "pos_clk.un4_clk_000_pe_0_0_a2_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un4_clk_000_pe_0_0_a2 "pos_clk.un4_clk_000_pe_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_a2_2_1_0 "SM_AMIGA_nss_i_i_0_0_a2_2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_a2_2_2_0 "SM_AMIGA_nss_i_i_0_0_a2_2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_a2_2_3_0 "SM_AMIGA_nss_i_i_0_0_a2_2_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_a2_2_0 "SM_AMIGA_nss_i_i_0_0_a2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_3_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_3_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_1 "SM_AMIGA_srsts_i_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1 "SM_AMIGA_srsts_i_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_0_i_a2_1 "pos_clk.un37_as_030_d0_0_i_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_5_0_o2_2_o2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_5_0_o2_2_o2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_5_0_o2_2_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_1_6 "SM_AMIGA_srsts_i_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_2_6 "SM_AMIGA_srsts_i_0_2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_6 "SM_AMIGA_srsts_i_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_0_a2_0_1_2 "SM_AMIGA_srsts_i_i_0_a2_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_0_a2_0_2_2 "SM_AMIGA_srsts_i_i_0_a2_0_2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_0_a2_0_2 "SM_AMIGA_srsts_i_i_0_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un4_clk_000_pe_0_0_a2_0_1 "pos_clk.un4_clk_000_pe_0_0_a2_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un4_clk_000_pe_0_0_a2_0_2 "pos_clk.un4_clk_000_pe_0_0_a2_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un4_clk_000_pe_0_0_a2_0 "pos_clk.un4_clk_000_pe_0_0_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_2_1_3 "SM_AMIGA_srsts_i_0_0_a2_2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_2_2_3 "SM_AMIGA_srsts_i_0_0_a2_2_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_2_3 "SM_AMIGA_srsts_i_0_0_a2_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_0_o2_1 "pos_clk.un23_bgack_030_int_i_0_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_0_o2_2 "pos_clk.un23_bgack_030_int_i_0_o2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_0_o2 "pos_clk.un23_bgack_030_int_i_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un22_berr_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un22_berr_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_0_i_a2_1_1 "pos_clk.un37_as_030_d0_0_i_a2_1_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_0_i_a2_1_2 "pos_clk.un37_as_030_d0_0_i_a2_1_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_0_i_a2_1_3 "pos_clk.un37_as_030_d0_0_i_a2_1_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_0_i_a2_1_4 "pos_clk.un37_as_030_d0_0_i_a2_1_4") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0_1_0 "SM_AMIGA_nss_i_i_0_0_o2_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0_0 "SM_AMIGA_nss_i_i_0_0_o2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un10_sm_amiga_1 "pos_clk.un10_sm_amiga_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un10_sm_amiga "pos_clk.un10_sm_amiga") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_7 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_8 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_9 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_10 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un10_ciin_0_a2_11 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance RST_DLY_e2_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance RST_DLY_e2_i_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance RST_DLY_e2_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un7_clk_000_pe_0_0_a3_0_1 "pos_clk.un7_clk_000_pe_0_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un7_clk_000_pe_0_0_a3_0_2 "pos_clk.un7_clk_000_pe_0_0_a3_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un7_clk_000_pe_0_0_a3_0 "pos_clk.un7_clk_000_pe_0_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un7_clk_000_pe_0_0_a3_1 "pos_clk.un7_clk_000_pe_0_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un7_clk_000_pe_0_0_a3_2 "pos_clk.un7_clk_000_pe_0_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un7_clk_000_pe_0_0_a3_3 "pos_clk.un7_clk_000_pe_0_0_a3_3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un7_clk_000_pe_0_0_a3 "pos_clk.un7_clk_000_pe_0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_a3_2_1_0 "SM_AMIGA_nss_i_i_0_a3_2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_a3_2_2_0 "SM_AMIGA_nss_i_i_0_a3_2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_a3_2_3_0 "SM_AMIGA_nss_i_i_0_a3_2_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_a2_2_2 "SM_AMIGA_srsts_i_i_a2_2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_a2_2 "SM_AMIGA_srsts_i_i_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_o2_1_0_0 "SM_AMIGA_nss_i_i_0_o2_1_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_o2_0 "SM_AMIGA_nss_i_i_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_o3_1 "pos_clk.un23_bgack_030_int_i_i_a4_i_o3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_o3_2 "pos_clk.un23_bgack_030_int_i_i_a4_i_o3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_o3 "pos_clk.un23_bgack_030_int_i_i_a4_i_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_1_0 "SM_AMIGA_nss_i_i_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_2_0 "SM_AMIGA_nss_i_i_0_0_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_3_0 "SM_AMIGA_nss_i_i_0_0_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_0 "SM_AMIGA_nss_i_i_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_0_0_1_3 "SM_AMIGA_srsts_i_0_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_0_0_2_3 "SM_AMIGA_srsts_i_0_0_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_0_0_3 "SM_AMIGA_srsts_i_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_1_0 "SM_AMIGA_nss_i_i_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_2_0 "SM_AMIGA_nss_i_i_0_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_3_0 "SM_AMIGA_nss_i_i_0_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_0 "SM_AMIGA_nss_i_i_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_25_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_HIGH_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_26_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un9_bg_030_i "pos_clk.un9_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_i_o2_1 "pos_clk.un37_as_030_d0_i_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_i_o2 "pos_clk.un37_as_030_d0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_5_0_o3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_5_0_o3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_5_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un8_sm_amiga_1 "pos_clk.un8_sm_amiga_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un8_sm_amiga "pos_clk.un8_sm_amiga") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_a2_1_2 "SM_AMIGA_srsts_i_i_a2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance nEXP_SPACE_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_2_1_0 "SM_AMIGA_nss_i_i_0_0_o2_2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_2_0 "SM_AMIGA_nss_i_i_0_0_o2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_282_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_3_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_8_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_17_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance RW_000_DMA_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_20_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance A0_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_21_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_22_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_28_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_27_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_0 "IPL_030_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_c_i_2 "IPL_c_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_i_2 "IPL_D0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_c_i_1 "IPL_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_i_1 "IPL_D0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_c_i_0 "IPL_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_D0_0_i_0 "IPL_D0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_D_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance nEXP_SPACE_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_307_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_303_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_304_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_i_2 "SM_AMIGA_srsts_i_i_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_301_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_300_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_3_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_278_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_297_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_277_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance A0_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_29_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_1_i_2 "IPL_030_1_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_330_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f0_i_a2_i_i "pos_clk.DS_000_DMA_4_f0_i_a2_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_328_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un14_amiga_bus_data_dir_0_a2_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_325_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_326_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_i_6 "SM_AMIGA_srsts_i_i_0_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RESET_OUT_1_sqmuxa_i_0_143_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_321_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_322_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_320_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un5_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un8_ciin_i_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_310_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_305_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un5_e_i_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_341_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_i_i_3 "cpu_est_2_i_0_i_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_340_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_361_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_i_2 "cpu_est_2_0_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_338_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_339_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_i_1 "cpu_est_2_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_332_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_336_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un7_clk_000_pe_0_0_i "pos_clk.un7_clk_000_pe_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_DMA_1_sqmuxa_0_a2_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_331_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_0_a2_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RESET_OUT_1_sqmuxa_i_0_143_1_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_o2_i_2 "cpu_est_2_0_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_i_o2_i_3 "cpu_est_2_i_0_i_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_OUT_PRE_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_0_sqmuxa_i_i_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_o2_i_0 "SM_AMIGA_nss_i_i_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_345_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_344_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un6_as_030_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_342_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_343_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RESET_OUT_2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_o2_2_i_0 "SM_AMIGA_nss_i_i_0_o2_2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_i_1 "SM_AMIGA_srsts_i_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_i_5 "SM_AMIGA_srsts_i_0_o2_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_o2_1_i_0 "SM_AMIGA_nss_i_i_0_o2_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_351_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_353_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_o2_0_i_2 "SM_AMIGA_srsts_i_i_o2_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_o2_0_i_0 "SM_AMIGA_nss_i_i_0_o2_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un5_bgack_030_int_d_i_0_a4_i_o3_i "pos_clk.un5_bgack_030_int_d_i_0_a4_i_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_o3_i "pos_clk.un23_bgack_030_int_i_i_a4_i_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename CLK_000_N_SYNC_i_10 "CLK_000_N_SYNC_i[10]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_350_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_0_sqmuxa_i_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_241_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_266_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_267_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_254_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_317_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_313_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_316_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_312_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_347_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_323_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_324_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_H_2_0_a2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_3 "SM_AMIGA_srsts_i_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_i_0 "SM_AMIGA_srsts_i_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_0_i_0 "SM_AMIGA_srsts_i_0_o2_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_349_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_5_0_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance UDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance LDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_o2_i_0 "pos_clk.SIZE_DMA_6_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_o2_i_6 "SM_AMIGA_srsts_i_i_0_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_o2_i_2 "SM_AMIGA_srsts_i_i_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_354_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_o3_i "pos_clk.CYCLE_DMA_5_0_i_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_i_o2_i "pos_clk.un37_as_030_d0_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_i_4 "SM_AMIGA_srsts_i_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_242_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_246_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_240_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_272_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_271_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_i_i "pos_clk.un37_as_030_d0_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_298_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_299_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_358_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000_0_0_i "pos_clk.un6_bgack_000_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_0_a2_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_D0_0_i_a2_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un3_as_030_d0_0_o3_i "pos_clk.un3_as_030_d0_0_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_24_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_DMA_LOW_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_25_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_0_i_o2_1 "pos_clk.un37_as_030_d0_0_i_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_0_i_o2 "pos_clk.un37_as_030_d0_0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_328_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_325_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_327_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_320_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un14_amiga_bus_data_dir_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_319_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_i_0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_206_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_283_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_281_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_0_o2_i "pos_clk.un23_bgack_030_int_i_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_OUT_PRE_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_341_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_338_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_339_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_336_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_3_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_211_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_332_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_331_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_330_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0_i "pos_clk.DS_000_DMA_4_f0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_329_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_349_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_4 "SM_AMIGA_srsts_i_0_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un4_bgack_000_i_o2_i "pos_clk.un4_bgack_000_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_324_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_0 "SM_AMIGA_srsts_i_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_3 "SM_AMIGA_srsts_i_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance LDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_o2_i_0 "pos_clk.SIZE_DMA_6_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_347_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_348_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_i_3 "SM_AMIGA_srsts_i_0_0_o2_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_D_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_5_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_7_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_18_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance RW_000_INT_2_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_10_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance BGACK_030_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_7_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_5_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_D0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0_i "pos_clk.un6_bgack_000_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_6 "SM_AMIGA_srsts_i_0_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_0_o2_i_2 "SM_AMIGA_srsts_i_i_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_334_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_335_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_0_i_o2_i "pos_clk.un37_as_030_d0_0_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_5 "SM_AMIGA_srsts_i_0_0_o2_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_5_0_o2_2_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_346_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_0_i_6 "SM_AMIGA_srsts_i_0_o2_0_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_345_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_344_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un3_as_030_d0_0_o2_0_o2_i "pos_clk.un3_as_030_d0_0_o2_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_INT_1_sqmuxa_0_a2_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_233_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_232_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_0_i_i "pos_clk.un37_as_030_d0_0_i_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un13_ciin_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_284_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_285_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un5_e_i_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_280_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_277_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_0_i_2 "SM_AMIGA_srsts_i_i_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_235_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_236_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_i_1 "cpu_est_2_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_231_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_230_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un4_clk_000_pe_0_0_i "pos_clk.un4_clk_000_pe_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_22_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_224_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_226_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_220_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_221_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_222_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_217_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_215_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_219_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RESET_OUT_2_0_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_i_1 "SM_AMIGA_srsts_i_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_i_o2_i_3 "cpu_est_2_i_0_i_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_340_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_337_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un10_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_i_i_3 "cpu_est_2_i_0_i_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0_i_0 "SM_AMIGA_nss_i_i_0_0_o2_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_o2_i_2 "cpu_est_2_0_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RESET_OUT_1_sqmuxa_i_0_143_1_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_1_i_0 "SM_AMIGA_nss_i_i_0_0_o2_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_2_i_0 "SM_AMIGA_nss_i_i_0_0_o2_2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_3_i_0 "SM_AMIGA_nss_i_i_0_0_o2_3_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_228_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_227_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_343_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_223_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_225_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_c_i_2 "IPL_c_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_2 "IPL_D0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_27_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_0 "IPL_030_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_28_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_29_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_1_i_2 "IPL_030_1_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_357_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_254_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_i_2 "cpu_est_2_0_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_315_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un9_bg_030_i "pos_clk.un9_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_26_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_21_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance UDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_17_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance LDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_4_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_LOW_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_amiga_bus_enable_low (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_c_i_0 "IPL_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_0 "IPL_D0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_c_i_1 "IPL_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_i_1 "IPL_D0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_D0_0_2 "IPL_D0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_D0_0_1 "IPL_D0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_D0_0_0 "IPL_D0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BG_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_275_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_p "DSACK1_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un1_amiga_bus_enable_low_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un21_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_r "AMIGA_BUS_ENABLE_DMA_LOW_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_m "AMIGA_BUS_ENABLE_DMA_LOW_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_n "AMIGA_BUS_ENABLE_DMA_LOW_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_p "AMIGA_BUS_ENABLE_DMA_LOW_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename CLK_000_N_SYNC_i_12 "CLK_000_N_SYNC_i[12]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RST_DLY_i_2 "RST_DLY_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_136 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_135 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_134 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_1_2 "IPL_030_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_1 "IPL_030_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_i_3 "cpu_est_2_i_0_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_2 "cpu_est_2_0_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_a2_0_2 "cpu_est_2_0_0_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_252 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_1_3 "SM_AMIGA_srsts_i_0_0_a2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e0_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_i_a2_3 "cpu_est_2_i_0_i_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_a2_2 "cpu_est_2_0_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_a2_0 "SM_AMIGA_nss_i_i_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RST_DLY_i_1 "RST_DLY_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e1_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_030_i_a2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_x2_0_x2_0 "cpu_est_0_0_x2_0_x2[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_3_0 "SM_AMIGA_nss_i_i_0_0_o2_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_1_0 "SM_AMIGA_nss_i_i_0_0_o2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_1_sqmuxa_i_0_143_1_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_o2_2 "cpu_est_2_0_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RST_DLY_i_0 "RST_DLY_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_0_2 "SM_AMIGA_srsts_i_i_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_i_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_as_000_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un13_ciin_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_1_sqmuxa_i_0_143_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un3_as_030_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_i_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_i_0_i_o2_3 "cpu_est_2_i_0_i_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_1 "SM_AMIGA_srsts_i_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_0_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_m2_1__r "SM_AMIGA_srsts_i_0_m2_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_m2_1__m "SM_AMIGA_srsts_i_0_m2_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_m2_1__n "SM_AMIGA_srsts_i_0_m2_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_m2_1__p "SM_AMIGA_srsts_i_0_m2_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance VMA_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_a2_1 "cpu_est_2_0_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_4 "SM_AMIGA_srsts_i_0_0_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un5_e_i_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un2_rw_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_1 "SM_AMIGA_srsts_i_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_OUT_2_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RST_DLY_e2_i_0_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un4_clk_000_pe_0_0 "pos_clk.un4_clk_000_pe_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_2_0_0_0_1 "cpu_est_2_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_6 "SM_AMIGA_srsts_i_0_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_3_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_000_D_i_11 "CLK_000_D_i[11]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_5_0_o2_2_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_0_i "pos_clk.un37_as_030_d0_0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_1_sqmuxa_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un3_as_030_d0_0_o2_0_o2 "pos_clk.un3_as_030_d0_0_o2_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_0_6 "SM_AMIGA_srsts_i_0_o2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_5 "SM_AMIGA_srsts_i_0_0_o2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_m2_5__r "SM_AMIGA_srsts_i_0_0_m2_5_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_m2_5__m "SM_AMIGA_srsts_i_0_0_m2_5_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_m2_5__n "SM_AMIGA_srsts_i_0_0_m2_5_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_m2_5__p "SM_AMIGA_srsts_i_0_0_m2_5_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename CLK_000_P_SYNC_i_10 "CLK_000_P_SYNC_i[10]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DS_000_ENABLE_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_INT_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_253 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_0_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_0_i_a2 "pos_clk.un37_as_030_d0_0_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un37_as_030_d0_0_i_a2_0 "pos_clk.un37_as_030_d0_0_i_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_5 "SM_AMIGA_srsts_i_0_0_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_ENABLE_1_sqmuxa_1_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_DECODE_i_18 "A_DECODE_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_129 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_r "DS_000_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_m "DS_000_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_n "DS_000_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DS_000_ENABLE_0_p "DS_000_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_254 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_as_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_uds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_lds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_236_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK1_INT_0_p "DSACK1_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un4_lds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un4_uds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_r "DS_000_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_m "DS_000_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_n "DS_000_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_p "DS_000_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_1_i_x2 "pos_clk.CYCLE_DMA_5_1_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename pos_clk_CYCLE_DMA_5_0_i_x2 "pos_clk.CYCLE_DMA_5_0_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance I_255 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un4_bgack_000_i_o2 "pos_clk.un4_bgack_000_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_4 "SM_AMIGA_srsts_i_0_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0 "SM_AMIGA_nss_i_i_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_i_0_o2_2 "SM_AMIGA_srsts_i_i_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_6 "SM_AMIGA_srsts_i_0_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_DECODE_i_16 "A_DECODE_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_nss_i_i_0_0_a2_3_0 "SM_AMIGA_nss_i_i_0_0_a2_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_0_6 "SM_AMIGA_srsts_i_0_a2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_D0_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_4 "SM_AMIGA_srsts_i_0_0_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_DECODE_i_19 "A_DECODE_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_0_x2 "pos_clk.un23_bgack_030_int_i_0_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_3 "SM_AMIGA_srsts_i_0_0_o2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_o2_0 "pos_clk.SIZE_DMA_6_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_o2_3 "SM_AMIGA_srsts_i_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__r "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__n "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__p "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_o2_0 "SM_AMIGA_srsts_i_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0 "SM_AMIGA_srsts_i_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_a2_0 "SM_AMIGA_srsts_i_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_256 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0_a2 "pos_clk.DS_000_DMA_4_f0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_2_sqmuxa_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_un23_bgack_030_int_i_0_a2 "pos_clk.un23_bgack_030_int_i_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_000_D_i_10 "CLK_000_D_i[10]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_srsts_i_0_0_a2_3_3 "SM_AMIGA_srsts_i_0_0_a2_3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SIZE_DMA_3_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un14_amiga_bus_data_dir_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_0 "pos_clk.SIZE_DMA_6_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_1 "pos_clk.SIZE_DMA_6_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_DS_000_DMA_4_f0_0 "pos_clk.DS_000_DMA_4_f0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CLK_000_P_SYNC_2_0_a2_0 "pos_clk.CLK_000_P_SYNC_2_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CLK_000_N_SYNC_2_0_a2_0 "pos_clk.CLK_000_N_SYNC_2_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un6_as_030_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_A0_DMA_3_0_a2 "pos_clk.A0_DMA_3_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_1 "A_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_a2_0 "pos_clk.SIZE_DMA_6_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_SIZE_DMA_6_0_0_a2_1 "pos_clk.SIZE_DMA_6_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_214_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_263 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_264 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_261 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_262 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_259 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_260 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_257 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_258 (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un4_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__r "SIZE_DMA_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__m "SIZE_DMA_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__n "SIZE_DMA_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_1__p "SIZE_DMA_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__r "SIZE_DMA_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__m "SIZE_DMA_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__n "SIZE_DMA_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SIZE_DMA_0_0__p "SIZE_DMA_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance DSACK1_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RW_000_INT_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_DMA_LOW_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance N_276_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_a2_0 "SM_AMIGA_srsts_i_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_PE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_SM_AMIGA_5_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_a3_4 "SM_AMIGA_srsts_i_0_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_SM_AMIGA_3_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_a3_1 "pos_clk.SIZE_DMA_6_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_a3_0 "pos_clk.SIZE_DMA_6_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a3 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_1_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_i_a3_0 "pos_clk.un37_as_030_d0_i_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_i_a3 "pos_clk.un37_as_030_d0_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_195 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_000_ENABLE_1_sqmuxa_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un3_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un3_as_030_d0_0_o3 "pos_clk.un3_as_030_d0_0_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_D0_0_i_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance SIZE_DMA_3_sqmuxa_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un3_as_030_i_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un2_rw_i_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000_0_0 "pos_clk.un6_bgack_000_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_000_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_1 "pos_clk.SIZE_DMA_6_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_0 "pos_clk.SIZE_DMA_6_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un37_as_030_d0_i "pos_clk.un37_as_030_d0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_un6_bgack_000_0_0_a2 "pos_clk.un6_bgack_000_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un22_berr_0_a2_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_1__r "SM_AMIGA_srsts_i_0_m2_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_1__m "SM_AMIGA_srsts_i_0_m2_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_1__n "SM_AMIGA_srsts_i_0_m2_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_1__p "SM_AMIGA_srsts_i_0_m2_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_4 "SM_AMIGA_srsts_i_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance nEXP_SPACE_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_o3 "pos_clk.CYCLE_DMA_5_0_i_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o3_0 "SM_AMIGA_srsts_i_0_o3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_o2_2 "SM_AMIGA_srsts_i_i_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_o2_6 "SM_AMIGA_srsts_i_i_0_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_SIZE_DMA_6_0_0_o2_0 "pos_clk.SIZE_DMA_6_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_o2_4_0 "SM_AMIGA_nss_i_i_0_o2_4[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_0_0 "SM_AMIGA_srsts_i_0_o2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_196 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_030_i_a4_i_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_0_i_x2 "pos_clk.CYCLE_DMA_5_0_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_5__r "SM_AMIGA_srsts_i_0_m2_5_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_5__m "SM_AMIGA_srsts_i_0_m2_5_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_5__n "SM_AMIGA_srsts_i_0_m2_5_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_m2_5__p "SM_AMIGA_srsts_i_0_m2_5_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_0_x2_0 "cpu_est_0_0_x2[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance (rename pos_clk_CYCLE_DMA_5_1_i_x2 "pos_clk.CYCLE_DMA_5_1_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance I_197 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_0_sqmuxa_i_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un5_bgack_030_int_d_i_0_a4_i_o3 "pos_clk.un5_bgack_030_int_d_i_0_a4_i_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_o2_5_0 "SM_AMIGA_nss_i_i_0_o2_5[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_o2_0_0 "SM_AMIGA_nss_i_i_0_o2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_o2_0_2 "SM_AMIGA_srsts_i_i_o2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_o2_1_0 "SM_AMIGA_nss_i_i_0_o2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_5 "SM_AMIGA_srsts_i_0_o2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_1 "SM_AMIGA_srsts_i_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_o2_2_0 "SM_AMIGA_nss_i_i_0_o2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_NE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_o2_0 "SM_AMIGA_srsts_i_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_o2_3 "SM_AMIGA_srsts_i_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_2_0_a2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un6_as_030_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_x2 "pos_clk.un23_bgack_030_int_i_i_a4_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0 "pos_clk.CLK_000_N_SYNC_2_0_a4_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RST_DLY_i_0 "RST_DLY_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename RST_DLY_i_1 "RST_DLY_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK1_INT_0_sqmuxa_i_i_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_i_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_i_o2_3 "cpu_est_2_i_0_i_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_o2_2 "cpu_est_2_0_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename RST_DLY_i_2 "RST_DLY_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance RESET_OUT_1_sqmuxa_i_0_143_1_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0 "SM_AMIGA_srsts_i_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_2 "SM_AMIGA_srsts_i_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un8_ciin_i_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_1_sqmuxa_i_0_143_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_0_6 "SM_AMIGA_srsts_i_i_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un14_amiga_bus_data_dir_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f0_i_a2_i "pos_clk.DS_000_DMA_4_f0_i_a2_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_DMA_1_sqmuxa_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un7_clk_000_pe_0_0 "pos_clk.un7_clk_000_pe_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_1 "cpu_est_2_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_2 "cpu_est_2_0_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_i_3 "cpu_est_2_i_0_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_i_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_198 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_DS_000_DMA_4_f0_i_a2_i_a3 "pos_clk.DS_000_DMA_4_f0_i_a2_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DS_000_DMA_2_sqmuxa_0_a2_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_a3_1 "cpu_est_2_0_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_a3_2 "cpu_est_2_0_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_i_0_i_a3_3 "cpu_est_2_i_0_i_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un5_e_i_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un23_bgack_030_int_i_i_a4_i_a2 "pos_clk.un23_bgack_030_int_i_i_a4_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_srsts_i_0_0_a2_3 "SM_AMIGA_srsts_i_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK1_INT_0_sqmuxa_i_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLYlde_i_a4_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_i_a2_0_2 "SM_AMIGA_srsts_i_i_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_2_0_0_0_a2_2 "cpu_est_2_0_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_a3_0 "SM_AMIGA_srsts_i_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_DATA_DIR_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_199 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_a3_1 "SM_AMIGA_srsts_i_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_a3_0_4 "SM_AMIGA_srsts_i_0_a3_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_a3_5 "SM_AMIGA_srsts_i_0_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_nss_i_i_0_a3_0 "SM_AMIGA_nss_i_i_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RESET_OUT_2_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e0_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_srsts_i_0_0_a3_3 "SM_AMIGA_srsts_i_0_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_030_H_2_0_a2_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_134 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_135 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_136 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance DSACK1_INT_0_sqmuxa_i_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e2_i_0_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance RST_DLY_e1_i_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_CLK_000_P_SYNC_2_0_a3_0 "pos_clk.CLK_000_P_SYNC_2_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_A0_DMA_3_0_a3 "pos_clk.A0_DMA_3_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance A1_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a3 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_323_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_129 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_212_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_213_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_214_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_215_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_27 "A_i[27]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance nEXP_SPACE_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_D0_0_0 "IPL_D0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_D0_0_1 "IPL_D0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_D0_0_2 "IPL_D0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_1_1 "IPL_030_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_1_2 "IPL_030_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_r "A0_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A0_DMA_0_m "A0_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_n "A0_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A0_DMA_0_p "A0_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_275_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_322_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_r "AMIGA_BUS_ENABLE_DMA_LOW_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_m "AMIGA_BUS_ENABLE_DMA_LOW_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_n "AMIGA_BUS_ENABLE_DMA_LOW_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_p "AMIGA_BUS_ENABLE_DMA_LOW_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_321_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_r "AMIGA_BUS_ENABLE_DMA_HIGH_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_m "AMIGA_BUS_ENABLE_DMA_HIGH_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_n "AMIGA_BUS_ENABLE_DMA_HIGH_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_p "AMIGA_BUS_ENABLE_DMA_HIGH_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance BG_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_DMA_HIGH_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VMA_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance UDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance A0_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance RW_000_DMA_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__r "SIZE_DMA_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__m "SIZE_DMA_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__n "SIZE_DMA_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__p "SIZE_DMA_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__r "SIZE_DMA_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__m "SIZE_DMA_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__n "SIZE_DMA_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__p "SIZE_DMA_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_amiga_bus_enable_low (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un4_uds_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un4_lds_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un4_as_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un6_as_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un4_as_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance DS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance un6_ds_030 (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -957,23 +980,24 @@ (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename RW_000_DMA_0_r "RW_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename RW_000_DMA_0_m "RW_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename RW_000_DMA_0_n "RW_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename RW_000_DMA_0_p "RW_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_r "A0_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A0_DMA_0_m "A0_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_n "A0_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_p "A0_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3)) - (portRef I0 (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a4_i_o3)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r)) - (portRef I0 (instanceRef un1_as_000_0_0)) - (portRef I0 (instanceRef BGACK_030_INT_i)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__r)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_o2)) (portRef I0 (instanceRef BGACK_030_INT_0_n)) + (portRef I0 (instanceRef un1_as_000_0)) + (portRef I0 (instanceRef BGACK_030_INT_i)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_1_0)) (portRef I0 (instanceRef BGACK_030)) )) (net VCC (joined @@ -986,14 +1010,30 @@ (portRef I0 (instanceRef VMA)) )) (net GND (joined + (portRef I0 (instanceRef AHIGH_24)) + (portRef I0 (instanceRef AHIGH_25)) + (portRef I0 (instanceRef AHIGH_26)) + (portRef I0 (instanceRef AHIGH_27)) + (portRef I0 (instanceRef AHIGH_28)) + (portRef I0 (instanceRef AHIGH_29)) + (portRef I0 (instanceRef AHIGH_30)) + (portRef I0 (instanceRef AHIGH_31)) (portRef I0 (instanceRef AMIGA_ADDR_ENABLE)) (portRef I0 (instanceRef BERR)) (portRef I0 (instanceRef RESET)) )) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH[0]") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_i_0)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_HIGH)) + )) (net un1_amiga_bus_enable_low (joined (portRef O (instanceRef un1_amiga_bus_enable_low)) (portRef I0 (instanceRef un1_amiga_bus_enable_low_i)) )) + (net un6_as_030 (joined + (portRef O (instanceRef un6_as_030_0_a2)) + (portRef I0 (instanceRef un6_as_030_i)) + )) (net un3_size (joined (portRef O (instanceRef un3_size)) (portRef I0 (instanceRef SIZE_1)) @@ -1010,21 +1050,21 @@ (portRef O (instanceRef un4_lds_000)) (portRef I0 (instanceRef un4_lds_000_i)) )) - (net un5_ciin (joined - (portRef O (instanceRef un5_ciin_0_a2_0_a3)) - (portRef I0 (instanceRef un5_ciin_i)) - (portRef I0 (instanceRef CIIN)) - )) (net un4_as_000 (joined (portRef O (instanceRef un4_as_000)) (portRef I0 (instanceRef un4_as_000_i)) )) + (net un10_ciin (joined + (portRef O (instanceRef un10_ciin_0_a2)) + (portRef I0 (instanceRef un10_ciin_i)) + (portRef I0 (instanceRef CIIN)) + )) (net un21_fpu_cs (joined - (portRef O (instanceRef un21_fpu_cs_0_a2_0_a3)) + (portRef O (instanceRef un21_fpu_cs_0_a2)) (portRef I0 (instanceRef un21_fpu_cs_i)) )) (net un22_berr (joined - (portRef O (instanceRef un22_berr_0_a2_0_a3)) + (portRef O (instanceRef un22_berr_0_a2)) (portRef OE (instanceRef BERR)) )) (net un6_ds_030 (joined @@ -1033,63 +1073,47 @@ )) (net (rename cpu_est_2 "cpu_est[2]") (joined (portRef Q (instanceRef cpu_est_2)) - (portRef I0 (instanceRef cpu_est_0_2__n)) - (portRef I1 (instanceRef cpu_est_2_i_0_i_a3_3)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_a3_2)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_2)) + (portRef I1 (instanceRef cpu_est_2_i_0_i_a2_3)) (portRef I0 (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef un5_e_i_i_a3_0_1)) + (portRef I0 (instanceRef cpu_est_0_2__n)) + (portRef I1 (instanceRef un5_e_i_i_a2_0_1)) )) (net (rename cpu_est_3 "cpu_est[3]") (joined (portRef Q (instanceRef cpu_est_3)) - (portRef I0 (instanceRef cpu_est_0_3__n)) (portRef I0 (instanceRef un5_e_i_i_o2)) (portRef I0 (instanceRef cpu_est_i_3)) + (portRef I0 (instanceRef cpu_est_0_3__n)) )) (net (rename cpu_est_0 "cpu_est[0]") (joined (portRef Q (instanceRef cpu_est_0)) (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_2)) (portRef I0 (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef cpu_est_0_0_x2_0)) - (portRef I0 (instanceRef cpu_est_2_0_0_a3_1_1_1)) + (portRef I1 (instanceRef cpu_est_0_0_x2_0_x2_0)) + (portRef I0 (instanceRef cpu_est_2_0_0_a2_1_1_1)) )) (net (rename cpu_est_1 "cpu_est[1]") (joined (portRef Q (instanceRef cpu_est_1)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_1)) (portRef I0 (instanceRef cpu_est_0_1__n)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_a3_1)) (portRef I1 (instanceRef cpu_est_2_0_0_0_o2_2)) (portRef I0 (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef un5_e_i_i_a3_0_1)) + (portRef I0 (instanceRef un5_e_i_i_a2_0_1)) )) (net AS_000_INT (joined (portRef Q (instanceRef AS_000_INT)) - (portRef I0 (instanceRef AS_000_INT_i)) (portRef I0 (instanceRef AS_000_INT_0_n)) - )) - (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined - (portRef Q (instanceRef SM_AMIGA_5)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_5)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_5__m)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_5__r)) - (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_0_a3)) - (portRef I0 (instanceRef SM_AMIGA_i_5)) + (portRef I0 (instanceRef AS_000_INT_i)) )) (net AMIGA_BUS_ENABLE_DMA_LOW (joined (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) )) (net AS_030_D0 (joined (portRef Q (instanceRef AS_030_D0)) (portRef I0 (instanceRef AS_030_D0_i)) - (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_0_a3_1)) - )) - (net nEXP_SPACE_D0 (joined - (portRef Q (instanceRef nEXP_SPACE_D0)) - (portRef I0 (instanceRef nEXP_SPACE_D0_i)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_o2)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o2_0)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2_0_a3_1)) - (portRef OE (instanceRef DSACK1)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_1)) )) (net AS_030_000_SYNC (joined (portRef Q (instanceRef AS_030_000_SYNC)) @@ -1098,13 +1122,13 @@ )) (net BGACK_030_INT_D (joined (portRef Q (instanceRef BGACK_030_INT_D)) - (portRef I1 (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a4_i_o3)) + (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_i_o2)) )) (net AS_000_DMA (joined (portRef Q (instanceRef AS_000_DMA)) (portRef I0 (instanceRef AS_000_DMA_0_n)) - (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i_a3)) (portRef I0 (instanceRef AS_000_DMA_i)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_a2)) )) (net DS_000_DMA (joined (portRef Q (instanceRef DS_000_DMA)) @@ -1113,57 +1137,68 @@ )) (net (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (joined (portRef Q (instanceRef CYCLE_DMA_0)) - (portRef I1 (instanceRef G_129)) - (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_x2)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_x2)) (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2)) + (portRef I1 (instanceRef G_129)) )) (net (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (joined (portRef Q (instanceRef CYCLE_DMA_1)) - (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_x2)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_x2)) (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) )) (net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined (portRef Q (instanceRef SIZE_DMA_0)) - (portRef I0 (instanceRef SIZE_DMA_i_0)) (portRef I0 (instanceRef SIZE_DMA_0_0__n)) + (portRef I0 (instanceRef SIZE_DMA_i_0)) (portRef I0 (instanceRef un4_size)) )) (net (rename SIZE_DMA_1 "SIZE_DMA[1]") (joined (portRef Q (instanceRef SIZE_DMA_1)) - (portRef I0 (instanceRef un3_size)) (portRef I0 (instanceRef SIZE_DMA_0_1__n)) + (portRef I0 (instanceRef un3_size)) (portRef I0 (instanceRef SIZE_DMA_i_1)) )) (net VPA_D (joined (portRef Q (instanceRef VPA_D)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a2_0_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3_3)) (portRef I0 (instanceRef VPA_D_i)) )) (net UDS_000_INT (joined (portRef Q (instanceRef UDS_000_INT)) - (portRef I0 (instanceRef UDS_000_INT_0_n)) (portRef I0 (instanceRef UDS_000_INT_i)) + (portRef I0 (instanceRef UDS_000_INT_0_n)) )) (net LDS_000_INT (joined (portRef Q (instanceRef LDS_000_INT)) - (portRef I0 (instanceRef LDS_000_INT_0_n)) (portRef I0 (instanceRef LDS_000_INT_i)) + (portRef I0 (instanceRef LDS_000_INT_0_n)) )) (net CLK_OUT_PRE_D (joined (portRef Q (instanceRef CLK_OUT_PRE_D)) (portRef I0 (instanceRef CLK_OUT_PRE_D_i)) (portRef D (instanceRef CLK_OUT_INT)) )) + (net (rename CLK_000_D_10 "CLK_000_D[10]") (joined + (portRef Q (instanceRef CLK_000_D_10)) + (portRef I0 (instanceRef CLK_000_D_i_10)) + (portRef D (instanceRef CLK_000_D_11)) + )) + (net (rename CLK_000_D_11 "CLK_000_D[11]") (joined + (portRef Q (instanceRef CLK_000_D_11)) + (portRef I0 (instanceRef CLK_000_D_i_11)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_0_1)) + (portRef D (instanceRef CLK_000_D_12)) + )) (net DTACK_D0 (joined (portRef Q (instanceRef DTACK_D0)) (portRef I0 (instanceRef DTACK_D0_i)) )) (net RESET_OUT (joined (portRef Q (instanceRef RESET_OUT)) - (portRef I1 (instanceRef un1_as_000_0_0)) + (portRef I1 (instanceRef un2_rw_i_a2)) + (portRef I1 (instanceRef un3_as_030_0)) (portRef I0 (instanceRef RESET_OUT_i)) - (portRef I1 (instanceRef un2_rw_i_a2_i)) - (portRef I1 (instanceRef un3_as_030_i_a2_i)) + (portRef I1 (instanceRef un1_as_000_0)) )) (net CLK_OUT_PRE_50 (joined (portRef Q (instanceRef CLK_OUT_PRE_50)) @@ -1172,44 +1207,34 @@ )) (net (rename CLK_000_D_1 "CLK_000_D[1]") (joined (portRef Q (instanceRef CLK_000_D_1)) - (portRef I0 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0)) + (portRef I0 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a2_0)) (portRef I0 (instanceRef CLK_000_D_i_1)) + (portRef D (instanceRef CLK_000_D_2)) )) (net (rename CLK_000_D_0 "CLK_000_D[0]") (joined (portRef Q (instanceRef CLK_000_D_0)) - (portRef I0 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a3_0)) (portRef I0 (instanceRef CLK_000_D_i_0)) - (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_0_a3)) + (portRef I0 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_0)) + (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2)) (portRef D (instanceRef CLK_000_D_1)) )) - (net CLK_000_PE (joined - (portRef Q (instanceRef CLK_000_PE)) - (portRef I0 (instanceRef G_129)) + (net (rename CLK_000_P_SYNC_10 "CLK_000_P_SYNC[10]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_10)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_5__n)) + (portRef I1 (instanceRef pos_clk_un4_bgack_000_i_o2)) (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) - (portRef I1 (instanceRef pos_clk_un6_bgack_000_0_0_a2)) - (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0_a3)) - (portRef I0 (instanceRef CLK_000_PE_i)) - (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_1)) + (portRef I0 (instanceRef G_129)) + (portRef I0 (instanceRef CLK_000_P_SYNC_i_10)) + (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0_a2)) + (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_1)) )) - (net (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (joined - (portRef Q (instanceRef CLK_000_P_SYNC_9)) - (portRef D (instanceRef CLK_000_PE)) - )) - (net CLK_000_NE (joined - (portRef Q (instanceRef CLK_000_NE)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0)) - (portRef I0 (instanceRef CLK_000_NE_i)) - (portRef I0 (instanceRef RESET_OUT_2_i_0_o2)) - (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0_1)) - (portRef D (instanceRef CLK_000_NE_D0)) - )) - (net (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_11)) - (portRef D (instanceRef CLK_000_NE)) + (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined + (portRef Q (instanceRef SM_AMIGA_5)) + (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_0_a2_0_a2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__m)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__r)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_5)) + (portRef I0 (instanceRef SM_AMIGA_i_5)) )) (net (rename IPL_D0_0 "IPL_D0[0]") (joined (portRef Q (instanceRef IPL_D0_0)) @@ -1223,33 +1248,52 @@ (portRef Q (instanceRef IPL_D0_2)) (portRef I0 (instanceRef G_136)) )) - (net CLK_000_NE_D0 (joined - (portRef Q (instanceRef CLK_000_NE_D0)) - (portRef I1 (instanceRef cpu_est_0_3__m)) - (portRef I0 (instanceRef cpu_est_0_3__r)) - (portRef I1 (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__r)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o2_2_0)) - (portRef I0 (instanceRef cpu_est_0_0_x2_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a3_0_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_1_3)) + (net (rename CLK_000_D_2 "CLK_000_D[2]") (joined + (portRef Q (instanceRef CLK_000_D_2)) + (portRef D (instanceRef CLK_000_D_3)) + )) + (net (rename CLK_000_D_3 "CLK_000_D[3]") (joined + (portRef Q (instanceRef CLK_000_D_3)) + (portRef D (instanceRef CLK_000_D_4)) + )) + (net (rename CLK_000_D_4 "CLK_000_D[4]") (joined + (portRef Q (instanceRef CLK_000_D_4)) + (portRef D (instanceRef CLK_000_D_5)) + )) + (net (rename CLK_000_D_5 "CLK_000_D[5]") (joined + (portRef Q (instanceRef CLK_000_D_5)) + (portRef D (instanceRef CLK_000_D_6)) + )) + (net (rename CLK_000_D_6 "CLK_000_D[6]") (joined + (portRef Q (instanceRef CLK_000_D_6)) + (portRef D (instanceRef CLK_000_D_7)) + )) + (net (rename CLK_000_D_7 "CLK_000_D[7]") (joined + (portRef Q (instanceRef CLK_000_D_7)) + (portRef D (instanceRef CLK_000_D_8)) + )) + (net (rename CLK_000_D_8 "CLK_000_D[8]") (joined + (portRef Q (instanceRef CLK_000_D_8)) + (portRef D (instanceRef CLK_000_D_9)) + )) + (net (rename CLK_000_D_9 "CLK_000_D[9]") (joined + (portRef Q (instanceRef CLK_000_D_9)) + (portRef D (instanceRef CLK_000_D_10)) + )) + (net (rename CLK_000_D_12 "CLK_000_D[12]") (joined + (portRef Q (instanceRef CLK_000_D_12)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_1)) )) (net (rename pos_clk_un6_bg_030 "pos_clk.un6_bg_030") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_0_a2_0_a3)) + (portRef O (instanceRef pos_clk_un6_bg_030_0_a2)) (portRef I0 (instanceRef pos_clk_un6_bg_030_i)) )) (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined (portRef Q (instanceRef SM_AMIGA_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_3_0)) + (portRef I1 (instanceRef un1_SM_AMIGA_3_i_0_a2)) (portRef I0 (instanceRef SM_AMIGA_i_0)) - (portRef I1 (instanceRef un1_SM_AMIGA_3_i_0_a3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0)) - )) - (net AMIGA_BUS_ENABLE_DMA_HIGH (joined - (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_0)) )) (net DSACK1_INT (joined (portRef Q (instanceRef DSACK1_INT)) @@ -1257,36 +1301,54 @@ (portRef I0 (instanceRef DSACK1)) )) (net (rename pos_clk_CLK_000_P_SYNC_2_0 "pos_clk.CLK_000_P_SYNC_2[0]") (joined - (portRef O (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a3_0)) + (portRef O (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_0)) (portRef D (instanceRef CLK_000_P_SYNC_0)) )) + (net (rename pos_clk_CLK_000_N_SYNC_2_0 "pos_clk.CLK_000_N_SYNC_2[0]") (joined + (portRef O (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a2_0)) + (portRef D (instanceRef CLK_000_N_SYNC_0)) + )) (net (rename pos_clk_ipl "pos_clk.ipl") (joined (portRef O (instanceRef G_137)) - (portRef I1 (instanceRef IPL_030_0_2__m)) - (portRef I0 (instanceRef IPL_030_0_2__r)) - (portRef I1 (instanceRef IPL_030_0_1__m)) - (portRef I0 (instanceRef IPL_030_0_1__r)) (portRef I1 (instanceRef IPL_030_0_0__m)) (portRef I0 (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__r)) + )) + (net (rename CLK_000_N_SYNC_0 "CLK_000_N_SYNC[0]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_1_0)) + (portRef D (instanceRef CLK_000_N_SYNC_1)) )) (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined (portRef Q (instanceRef SM_AMIGA_4)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_4)) + (portRef I1 (instanceRef un1_SM_AMIGA_5_0_o2_2_a2)) (portRef I0 (instanceRef SM_AMIGA_i_4)) - (portRef I1 (instanceRef un1_SM_AMIGA_5_0_a2)) )) (net DS_000_ENABLE (joined (portRef Q (instanceRef DS_000_ENABLE)) - (portRef I0 (instanceRef un4_uds_000)) - (portRef I0 (instanceRef un4_lds_000)) (portRef I0 (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef un4_lds_000)) + (portRef I0 (instanceRef un4_uds_000)) + )) + (net (rename CLK_000_N_SYNC_12 "CLK_000_N_SYNC[12]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_12)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_a2_3)) + (portRef I0 (instanceRef RESET_OUT_2_0_i_o2)) + (portRef I0 (instanceRef CLK_000_N_SYNC_i_12)) + (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0_1)) + (portRef D (instanceRef CLK_000_NE_D0)) )) (net (rename RST_DLY_0 "RST_DLY[0]") (joined (portRef Q (instanceRef RST_DLY_0)) - (portRef I1 (instanceRef RST_DLY_e0_i_0_a3)) (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_0)) (portRef I0 (instanceRef RST_DLY_i_0)) + (portRef I1 (instanceRef RST_DLY_e0_i_0_a2)) )) (net (rename RST_DLY_1 "RST_DLY[1]") (joined (portRef Q (instanceRef RST_DLY_1)) @@ -1298,11 +1360,6 @@ (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2)) (portRef I0 (instanceRef RST_DLY_i_2)) )) - (net (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (joined - (portRef O (instanceRef pos_clk_un9_bg_030_i)) - (portRef I1 (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_r)) - )) (net (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (joined (portRef Q (instanceRef CLK_000_P_SYNC_0)) (portRef D (instanceRef CLK_000_P_SYNC_1)) @@ -1339,9 +1396,9 @@ (portRef Q (instanceRef CLK_000_P_SYNC_8)) (portRef D (instanceRef CLK_000_P_SYNC_9)) )) - (net (rename CLK_000_N_SYNC_0 "CLK_000_N_SYNC[0]") (joined - (portRef Q (instanceRef CLK_000_N_SYNC_0)) - (portRef D (instanceRef CLK_000_N_SYNC_1)) + (net (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_9)) + (portRef D (instanceRef CLK_000_P_SYNC_10)) )) (net (rename CLK_000_N_SYNC_1 "CLK_000_N_SYNC[1]") (joined (portRef Q (instanceRef CLK_000_N_SYNC_1)) @@ -1377,14 +1434,27 @@ )) (net (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (joined (portRef Q (instanceRef CLK_000_N_SYNC_9)) - (portRef I0 (instanceRef DSACK1_INT_0_sqmuxa_i_i_a2)) (portRef D (instanceRef CLK_000_N_SYNC_10)) )) (net (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (joined (portRef Q (instanceRef CLK_000_N_SYNC_10)) - (portRef I0 (instanceRef CLK_000_N_SYNC_i_10)) (portRef D (instanceRef CLK_000_N_SYNC_11)) )) + (net (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_11)) + (portRef D (instanceRef CLK_000_N_SYNC_12)) + )) + (net (rename pos_clk_un5_bgack_030_int_d "pos_clk.un5_bgack_030_int_d") (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i)) + (portRef I1 (instanceRef A0_DMA_0_m)) + (portRef I0 (instanceRef A0_DMA_0_r)) + (portRef I1 (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW_000_DMA_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) + )) (net RW_000_INT (joined (portRef Q (instanceRef RW_000_INT)) (portRef I0 (instanceRef RW_000_INT_0_n)) @@ -1395,53 +1465,69 @@ (portRef I0 (instanceRef RW_000_DMA_0_n)) (portRef I0 (instanceRef RW)) )) - (net (rename pos_clk_un7_clk_000_pe "pos_clk.un7_clk_000_pe") (joined - (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0_i)) - (portRef I1 (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_r)) + (net CLK_000_NE_D0 (joined + (portRef Q (instanceRef CLK_000_NE_D0)) + (portRef I1 (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__r)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_3_0)) + (portRef I0 (instanceRef cpu_est_0_0_x2_0_x2_0)) + (portRef I1 (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_0_3__r)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1_3)) + )) + (net AMIGA_BUS_ENABLE_DMA_HIGH (joined + (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_i)) )) (net A0_DMA (joined (portRef Q (instanceRef A0_DMA)) (portRef I0 (instanceRef A0_DMA_0_n)) - (portRef I0 (instanceRef A0)) + (portRef I0 (instanceRef A_0)) )) (net (rename pos_clk_A0_DMA_3 "pos_clk.A0_DMA_3") (joined - (portRef O (instanceRef pos_clk_A0_DMA_3_0_a3)) + (portRef O (instanceRef pos_clk_A0_DMA_3_0_a2)) (portRef I0 (instanceRef A0_DMA_0_m)) )) (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined (portRef Q (instanceRef SM_AMIGA_6)) + (portRef I0 (instanceRef SM_AMIGA_i_6)) (portRef I1 (instanceRef LDS_000_INT_0_m)) (portRef I0 (instanceRef LDS_000_INT_0_r)) (portRef I1 (instanceRef UDS_000_INT_0_m)) (portRef I0 (instanceRef UDS_000_INT_0_r)) - (portRef I0 (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a3_6)) )) (net CLK_030_H (joined (portRef Q (instanceRef CLK_030_H)) (portRef I0 (instanceRef CLK_030_H_i)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_a3)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_a2)) )) (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined (portRef Q (instanceRef SM_AMIGA_1)) - (portRef I1 (instanceRef DSACK1_INT_0_sqmuxa_i_i_a3)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_0)) - (portRef I0 (instanceRef SM_AMIGA_i_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_1)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_1__m)) (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__r)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_1)) + (portRef I0 (instanceRef SM_AMIGA_i_1)) )) (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined (portRef Q (instanceRef SM_AMIGA_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) (portRef I0 (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a3_0_2_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_2_2)) )) (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined (portRef Q (instanceRef SM_AMIGA_2)) (portRef I0 (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a3_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a2_2)) + )) + (net (rename pos_clk_DS_000_DMA_4 "pos_clk.DS_000_DMA_4") (joined + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0_i)) + (portRef I0 (instanceRef DS_000_DMA_0_m)) )) (net N_3 (joined (portRef O (instanceRef DS_000_DMA_0_p)) @@ -1471,10 +1557,6 @@ (portRef O (instanceRef cpu_est_0_3__p)) (portRef D (instanceRef cpu_est_3)) )) - (net N_17 (joined - (portRef O (instanceRef LDS_000_INT_0_p)) - (portRef I0 (instanceRef N_17_i)) - )) (net N_19 (joined (portRef O (instanceRef RW_000_DMA_0_p)) (portRef I0 (instanceRef N_19_i)) @@ -1483,34 +1565,14 @@ (portRef O (instanceRef A0_DMA_0_p)) (portRef I0 (instanceRef N_20_i)) )) - (net N_21 (joined - (portRef O (instanceRef UDS_000_INT_0_p)) - (portRef I0 (instanceRef N_21_i)) - )) - (net N_22 (joined - (portRef O (instanceRef VMA_INT_0_p)) - (portRef I0 (instanceRef N_22_i)) + (net N_24 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + (portRef I0 (instanceRef N_24_i)) )) (net N_25 (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) (portRef I0 (instanceRef N_25_i)) )) - (net N_26 (joined - (portRef O (instanceRef BG_000_0_p)) - (portRef I0 (instanceRef N_26_i)) - )) - (net N_27 (joined - (portRef O (instanceRef IPL_030_0_0__p)) - (portRef I0 (instanceRef N_27_i)) - )) - (net N_28 (joined - (portRef O (instanceRef IPL_030_0_1__p)) - (portRef I0 (instanceRef N_28_i)) - )) - (net N_29 (joined - (portRef O (instanceRef IPL_030_0_2__p)) - (portRef I0 (instanceRef N_29_i)) - )) (net N_30 (joined (portRef O (instanceRef IPL_030_1_i_0)) (portRef D (instanceRef IPL_030DFF_0)) @@ -1596,579 +1658,587 @@ (portRef D (instanceRef IPL_D0_2)) )) (net N_54 (joined - (portRef O (instanceRef nEXP_SPACE_D0_0_i)) - (portRef D (instanceRef nEXP_SPACE_D0)) - )) - (net N_55 (joined (portRef O (instanceRef VPA_D_0_i)) (portRef D (instanceRef VPA_D)) )) - (net N_56 (joined + (net N_55 (joined (portRef O (instanceRef DTACK_D0_0_i)) (portRef D (instanceRef DTACK_D0)) )) - (net N_59 (joined + (net N_58 (joined (portRef O (instanceRef DS_000_ENABLE_1)) (portRef D (instanceRef DS_000_ENABLE)) )) (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined (portRef Q (instanceRef SM_AMIGA_i_7)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0_6)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_0_6)) (portRef I0 (instanceRef SM_AMIGA_i_i_7)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_o2_6)) - (portRef I1 (instanceRef un1_SM_AMIGA_5_0_o3_2)) (portRef I1 (instanceRef un1_SM_AMIGA_3_i_0)) )) - (net N_123 (joined + (net N_122 (joined (portRef O (instanceRef un1_SM_AMIGA_3_i_0_i)) (portRef I1 (instanceRef RW_000_INT_0_m)) (portRef I0 (instanceRef RW_000_INT_0_r)) )) - (net (rename cpu_est_2_1 "cpu_est_2[1]") (joined - (portRef O (instanceRef cpu_est_2_0_0_0_i_1)) - (portRef I0 (instanceRef cpu_est_0_1__m)) - )) - (net (rename cpu_est_2_2 "cpu_est_2[2]") (joined - (portRef O (instanceRef cpu_est_2_0_0_0_i_2)) - (portRef I0 (instanceRef cpu_est_0_2__m)) - )) - (net N_209 (joined - (portRef O (instanceRef G_129)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) - )) - (net N_213 (joined - (portRef O (instanceRef G_134)) - (portRef I0 (instanceRef N_213_i)) - )) - (net N_214 (joined - (portRef O (instanceRef G_135)) - (portRef I0 (instanceRef N_214_i)) - )) - (net N_215 (joined - (portRef O (instanceRef G_136)) - (portRef I0 (instanceRef N_215_i)) - )) - (net N_217 (joined - (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_i)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a3_1)) - )) - (net N_258 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_i_6)) - (portRef D (instanceRef SM_AMIGA_6)) - )) - (net N_61 (joined - (portRef O (instanceRef un8_ciin_i_0_0_i)) - (portRef OE (instanceRef CIIN)) - )) - (net N_127 (joined - (portRef O (instanceRef RST_DLYlde_i_a4_0_a2)) - (portRef I0 (instanceRef RST_DLY_e1_i_0_a3_1)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a3_2)) - (portRef I0 (instanceRef RST_DLY_e0_i_0_a3_0)) - )) - (net N_283 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_i_2)) - (portRef D (instanceRef SM_AMIGA_2)) - )) - (net N_80 (joined - (portRef O (instanceRef un14_amiga_bus_data_dir_0_a2_i_i)) - (portRef I0 (instanceRef RW_000_DMA_0_m)) - )) - (net N_88 (joined - (portRef O (instanceRef AS_030_D0_0_i_a2_i_i)) - (portRef D (instanceRef AS_030_D0)) - )) - (net N_90 (joined - (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i_i)) - (portRef I0 (instanceRef DS_000_DMA_0_m)) - )) - (net N_96 (joined - (portRef O (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_i)) - (portRef I1 (instanceRef DS_000_DMA_0_m)) - (portRef I0 (instanceRef DS_000_DMA_0_r)) - )) - (net N_99 (joined - (portRef O (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i_i)) - (portRef I1 (instanceRef AS_000_DMA_0_m)) - (portRef I0 (instanceRef AS_000_DMA_0_r)) - )) - (net N_119 (joined - (portRef O (instanceRef cpu_est_2_i_0_i_i_3)) - (portRef I0 (instanceRef cpu_est_0_3__m)) - )) - (net N_124 (joined - (portRef O (instanceRef un5_e_i_i_i)) - (portRef I0 (instanceRef E)) - )) - (net N_138 (joined - (portRef O (instanceRef un6_as_030_i_0_i)) - (portRef I0 (instanceRef AS_030)) - )) - (net N_144 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_o2_i)) - (portRef I0 (instanceRef RST_DLY_e1_i_0_a3)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a3_0)) - (portRef I0 (instanceRef RST_DLY_e0_i_0_a3)) - )) - (net N_158 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_o2_0_i)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a3_1_0)) - )) - (net N_168 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o2_i_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a3_2_1_0)) - )) - (net N_175 (joined - (portRef O (instanceRef DSACK1_INT_0_sqmuxa_i_i_o2_0_i)) - (portRef I1 (instanceRef DSACK1_INT_0_sqmuxa_i_i_a2)) - )) - (net N_182 (joined - (portRef O (instanceRef cpu_est_2_i_0_i_o2_i_3)) - (portRef I0 (instanceRef cpu_est_2_i_0_i_3)) - )) - (net N_185 (joined - (portRef O (instanceRef cpu_est_2_0_0_0_o2_i_2)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_a3_2)) - )) - (net N_187 (joined - (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2_i)) - (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1)) - )) - (net N_188 (joined - (portRef O (instanceRef DSACK1_INT_0_sqmuxa_i_i_o2_i)) - (portRef I0 (instanceRef DSACK1_INT_0_sqmuxa_i_i_a3)) - )) - (net N_192 (joined - (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_i)) - (portRef I0 (instanceRef AS_000_DMA_0_m)) - )) - (net N_193 (joined - (portRef O (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a4_i_o3_i)) - (portRef I1 (instanceRef RW_000_DMA_0_m)) - (portRef I0 (instanceRef RW_000_DMA_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) - (portRef I1 (instanceRef A0_DMA_0_m)) - (portRef I0 (instanceRef A0_DMA_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) - )) - (net N_197 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o2_0_i_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a3_1_1_0)) - )) - (net N_201 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_o2_0_i_2)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o2_2_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a3_0_1_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_1_3)) - )) - (net N_204 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o2_1_i_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a3_0_1_0)) - )) - (net N_206 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_o2_i_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a3_1_6)) - )) - (net N_207 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_o2_i_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a3_1_2)) - )) - (net N_210 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_o3_i)) - (portRef D (instanceRef BGACK_030_INT_D)) - )) - (net N_211 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a3_5)) - )) - (net N_212 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a3_1)) - )) - (net N_290 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o2_2_i_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a3_0)) - )) - (net N_216 (joined - (portRef O (instanceRef RESET_OUT_2_i_0_o2_i)) - (portRef I0 (instanceRef RESET_OUT_2_i_0_a3)) - )) - (net N_219 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a3_0)) - )) - (net N_220 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_3)) - )) - (net N_221 (joined - (portRef O (instanceRef CLK_030_H_2_0_a2_i_o2_i)) - (portRef I1 (instanceRef CLK_030_H_2_0_a2_i_a3)) - )) - (net N_227 (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_HIGH)) - )) - (net N_229 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__p)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_1)) - )) - (net N_230 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_5__p)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_5)) - )) - (net N_236 (joined - (portRef O (instanceRef DSACK1_INT_0_sqmuxa_i_i_a3)) - (portRef I0 (instanceRef N_236_i)) - )) - (net N_240 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a3)) - (portRef I0 (instanceRef N_240_i)) - )) - (net N_241 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a3_0)) - (portRef I0 (instanceRef N_241_i)) - )) - (net N_242 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a3_1)) - (portRef I0 (instanceRef N_242_i)) - )) - (net N_246 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a3_2)) - (portRef I0 (instanceRef N_246_i)) - )) - (net N_254 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_a3)) - (portRef I0 (instanceRef N_254_i)) - )) - (net N_266 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_a3_0)) - (portRef I0 (instanceRef N_266_i)) - )) - (net N_267 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_a3_1)) - (portRef I0 (instanceRef N_267_i)) - )) - (net N_275 (joined - (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a3)) - (portRef I0 (instanceRef N_275_i)) - )) - (net N_277 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_a3_0)) - (portRef I0 (instanceRef N_277_i)) - )) - (net N_278 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3)) - (portRef I0 (instanceRef N_278_i)) - )) - (net N_297 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0)) - (portRef I0 (instanceRef N_297_i)) - )) - (net N_300 (joined - (portRef O (instanceRef un1_SM_AMIGA_3_i_0_a3)) - (portRef I0 (instanceRef N_300_i)) - )) - (net N_301 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_a3_1)) - (portRef I0 (instanceRef N_301_i)) - )) - (net N_303 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_a3_2)) - (portRef I0 (instanceRef N_303_i)) - )) - (net N_304 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_a3_0_2)) - (portRef I0 (instanceRef N_304_i)) - )) - (net N_305 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_a3_4)) - (portRef I0 (instanceRef N_305_i)) - )) - (net N_307 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_a3_0_4)) - (portRef I0 (instanceRef N_307_i)) - )) - (net N_310 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_a3_5)) - (portRef I0 (instanceRef N_310_i)) - )) - (net N_312 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a3_0)) - (portRef I0 (instanceRef N_312_i)) - )) - (net N_313 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a3_0_0)) - (portRef I0 (instanceRef N_313_i)) - )) - (net N_316 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a3_1_0)) - (portRef I0 (instanceRef N_316_i)) - )) - (net N_317 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a3_2_0)) - (portRef I0 (instanceRef N_317_i)) - )) - (net N_320 (joined - (portRef O (instanceRef RESET_OUT_2_i_0_a3)) - (portRef I0 (instanceRef N_320_i)) - )) - (net N_321 (joined - (portRef O (instanceRef RST_DLY_e0_i_0_a3)) - (portRef I0 (instanceRef N_321_i)) - )) - (net N_322 (joined - (portRef O (instanceRef RST_DLY_e0_i_0_a3_0)) - (portRef I0 (instanceRef N_322_i)) - )) - (net N_323 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a3_3)) - (portRef I0 (instanceRef N_323_i)) - )) - (net N_324 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_3)) - (portRef I0 (instanceRef N_324_i)) - )) - (net N_325 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a3_6)) - (portRef I0 (instanceRef N_325_i)) - )) - (net N_326 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_6)) - (portRef I0 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(instanceRef N_339_i)) + )) + (net N_341 (joined + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_0_a2)) + (portRef I0 (instanceRef N_341_i)) + )) + (net N_344 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_0)) + (portRef I0 (instanceRef N_344_i)) + )) + (net N_347 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) + (portRef I0 (instanceRef N_347_i)) + )) + (net N_348 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_3_3)) + (portRef I0 (instanceRef N_348_i)) + )) + (net N_135_i (joined + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_0_x2)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2)) + )) + (net N_205_i (joined + (portRef O (instanceRef cpu_est_0_0_x2_0_x2_0)) + (portRef D (instanceRef cpu_est_0)) + )) + (net N_209_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_x2)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i)) + )) + (net N_210_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i)) + )) + (net N_199 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_0)) + )) + (net N_324 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_0)) + (portRef I0 (instanceRef N_324_i)) + )) + (net un22_berr_1 (joined + (portRef O (instanceRef un21_fpu_cs_0_a2_1)) + (portRef I0 (instanceRef un22_berr_0_a2_1)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2)) + )) + (net N_366 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_0)) + (portRef I1 (instanceRef un22_berr_0_a2)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2_1_0)) + )) + (net N_335 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_0_6)) + (portRef I0 (instanceRef N_335_i)) + )) + (net N_208 (joined + (portRef O (instanceRef G_129)) + (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_x2)) + )) + (net N_203 (joined + (portRef O (instanceRef pos_clk_un4_bgack_000_i_o2_i)) + (portRef I1 (instanceRef pos_clk_un6_bgack_000_0)) + )) + (net N_187 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_4)) + )) + (net N_137 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_0_6)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_3_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_o2_2)) + )) + (net N_349 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_3_0)) + (portRef I0 (instanceRef N_349_i)) + )) + (net (rename pos_clk_un6_bgack_000 "pos_clk.un6_bgack_000") (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0_i)) + (portRef I1 (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_r)) )) (net N_10 (joined (portRef O (instanceRef BGACK_030_INT_0_p)) (portRef I0 (instanceRef N_10_i)) )) - (net N_18 (joined - (portRef O (instanceRef RW_000_INT_0_p)) - (portRef I0 (instanceRef N_18_i)) + (net N_5 (joined + (portRef O (instanceRef AS_000_INT_0_p)) + (portRef I0 (instanceRef N_5_i)) )) - (net N_24 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) - (portRef I0 (instanceRef N_24_i)) + (net N_293 (joined + (portRef O (instanceRef AS_000_INT_1_sqmuxa_0_a2_i_i)) + (portRef I1 (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_r)) )) (net N_6 (joined (portRef O (instanceRef DS_000_ENABLE_0_p)) (portRef I0 (instanceRef DS_000_ENABLE_1)) )) + (net un1_SM_AMIGA_5 (joined + (portRef O (instanceRef un1_SM_AMIGA_5_0_o2_2_o2_i)) + (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_1_a2_0_a2)) + )) + (net DS_000_ENABLE_1_sqmuxa_1 (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_1_a2_0_a2)) + (portRef I1 (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef DS_000_ENABLE_0_r)) + )) + (net N_7 (joined + (portRef O (instanceRef AS_030_000_SYNC_0_p)) + (portRef I0 (instanceRef N_7_i)) + )) + (net (rename pos_clk_un3_as_030_d0 "pos_clk.un3_as_030_d0") (joined + (portRef O (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o2_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) + )) + (net N_290 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_i)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) + )) + (net N_18 (joined + (portRef O (instanceRef RW_000_INT_0_p)) + (portRef I0 (instanceRef N_18_i)) + )) + (net DS_000_ENABLE_1_sqmuxa (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_0_a2_0_a2)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i)) + )) + (net N_232 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_a2)) + (portRef I0 (instanceRef N_232_i)) + )) + (net N_194 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_o2_i)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_a2)) + )) + (net N_233 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_a2_0)) + (portRef I0 (instanceRef N_233_i)) + )) + (net N_275 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2)) + (portRef I0 (instanceRef N_275_i)) + )) + (net N_153 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_i)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2)) + )) + (net N_191 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_5)) + )) + (net N_334 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_a2_6)) + (portRef I0 (instanceRef N_334_i)) + )) + (net N_146 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_i_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_6)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_1_0)) + )) + (net N_345 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_1)) + (portRef I0 (instanceRef N_345_i)) + )) + (net N_346 (joined + (portRef O (instanceRef un1_SM_AMIGA_5_0_o2_2_a2)) + (portRef I0 (instanceRef N_346_i)) + )) + (net N_163 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_0_i_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_6)) + )) + (net N_22 (joined + (portRef O (instanceRef VMA_INT_0_p)) + (portRef I0 (instanceRef N_22_i)) + )) + (net (rename pos_clk_un4_clk_000_pe "pos_clk.un4_clk_000_pe") (joined + (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_i)) + (portRef I1 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_r)) + )) + (net (rename cpu_est_2_1 "cpu_est_2[1]") (joined + (portRef O (instanceRef cpu_est_2_0_0_0_i_1)) + (portRef I0 (instanceRef cpu_est_0_1__m)) + )) + (net N_235 (joined + (portRef O (instanceRef cpu_est_2_0_0_0_a2_1)) + (portRef I0 (instanceRef N_235_i)) + )) + (net N_284 (joined + (portRef O (instanceRef un5_e_i_i_a2)) + (portRef I0 (instanceRef N_284_i)) + )) + (net N_190 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_i_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a2_1)) + )) + (net N_337 (joined + (portRef O (instanceRef RESET_OUT_2_0_i_a2)) + (portRef I0 (instanceRef N_337_i)) + )) + (net N_195 (joined + (portRef O (instanceRef RESET_OUT_2_0_i_o2_i)) + (portRef I0 (instanceRef RESET_OUT_2_0_i_a2)) + )) + (net N_340 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_a2_3)) + (portRef I1 (instanceRef RST_DLY_e1_i_0_a2)) + (portRef I0 (instanceRef N_340_i)) + )) + (net N_231 (joined + (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0)) + (portRef I0 (instanceRef N_231_i)) + )) + (net N_230 (joined + (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_a2)) + (portRef I0 (instanceRef N_230_i)) + )) + (net N_280 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_2)) + (portRef I0 (instanceRef N_280_i)) + )) + (net N_166 (joined + (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2_i)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_a2_3)) + (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1)) + )) + (net N_141 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_o2_i)) + (portRef I0 (instanceRef RST_DLY_e0_i_0_a2)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_a2_0)) + )) + (net N_226 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_0)) + (portRef I0 (instanceRef N_226_i)) + )) + (net N_357 (joined + (portRef O (instanceRef cpu_est_2_0_0_a2_0_2)) + (portRef I0 (instanceRef N_357_i)) + (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0_1)) + )) + (net N_219 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_a2_2)) + (portRef I0 (instanceRef N_219_i)) + )) + (net N_217 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_a2_0)) + (portRef I0 (instanceRef N_217_i)) + )) + (net N_221 (joined + (portRef O (instanceRef RST_DLY_e1_i_0_a2_0)) + (portRef I0 (instanceRef N_221_i)) + )) + (net N_220 (joined + (portRef O (instanceRef RST_DLY_e1_i_0_a2)) + (portRef I0 (instanceRef N_220_i)) + )) + (net N_223 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) + (portRef I0 (instanceRef N_223_i)) + )) + (net N_343 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) + (portRef I0 (instanceRef N_343_i)) + )) + (net N_192 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_3_i_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0)) + )) + (net N_164 (joined + (portRef O (instanceRef cpu_est_2_0_0_0_o2_i_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_2)) + )) + (net N_291 (joined + (portRef O (instanceRef cpu_est_2_i_0_i_i_3)) + (portRef I0 (instanceRef cpu_est_0_3__m)) + )) + (net N_315 (joined + (portRef O (instanceRef cpu_est_2_i_0_i_a2_3)) + (portRef I0 (instanceRef N_315_i)) + )) + (net (rename cpu_est_2_2 "cpu_est_2[2]") (joined + (portRef O (instanceRef cpu_est_2_0_0_0_i_2)) + (portRef I0 (instanceRef cpu_est_0_2__m)) + )) + (net N_254 (joined + (portRef O (instanceRef cpu_est_2_0_0_0_a2_2)) + (portRef I0 (instanceRef N_254_i)) + )) + (net N_258 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_i)) + (portRef I1 (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_0_r)) + )) + (net N_29 (joined + (portRef O (instanceRef IPL_030_0_2__p)) + (portRef I0 (instanceRef N_29_i)) + )) + (net N_28 (joined + (portRef O (instanceRef IPL_030_0_1__p)) + (portRef I0 (instanceRef N_28_i)) + )) + (net N_27 (joined + (portRef O (instanceRef IPL_030_0_0__p)) + (portRef I0 (instanceRef N_27_i)) + )) + (net N_4 (joined + (portRef O (instanceRef DSACK1_INT_0_p)) + (portRef I0 (instanceRef N_4_i)) + )) + (net N_17 (joined + (portRef O (instanceRef LDS_000_INT_0_p)) + (portRef I0 (instanceRef N_17_i)) + )) + (net N_21 (joined + (portRef O (instanceRef UDS_000_INT_0_p)) + (portRef I0 (instanceRef N_21_i)) + )) + (net N_26 (joined + (portRef O (instanceRef BG_000_0_p)) + (portRef I0 (instanceRef N_26_i)) + )) + (net (rename pos_clk_un9_bg_030 "pos_clk.un9_bg_030") (joined + (portRef O (instanceRef pos_clk_un9_bg_030_i)) + (portRef I1 (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_r)) + )) (net un1_amiga_bus_enable_low_i (joined (portRef O (instanceRef un1_amiga_bus_enable_low_i)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_LOW)) @@ -2177,301 +2247,328 @@ (portRef O (instanceRef un21_fpu_cs_i)) (portRef I0 (instanceRef FPU_CS)) )) + (net N_275_i (joined + (portRef O (instanceRef N_275_i)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0)) + (portRef I0 (instanceRef DSACK1_INT_0_m)) + )) + (net (rename CLK_000_N_SYNC_i_12 "CLK_000_N_SYNC_i[12]") (joined + (portRef O (instanceRef CLK_000_N_SYNC_i_12)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_1)) + (portRef I0 (instanceRef RST_DLY_e1_i_0_a2_0)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_a2_2)) + (portRef I0 (instanceRef RST_DLY_e0_i_0_a2_0_1)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_1_0)) + )) + (net (rename RST_DLY_i_2 "RST_DLY_i[2]") (joined + (portRef O (instanceRef RST_DLY_i_2)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_a2_2)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_a2)) + )) + (net (rename RST_DLY_i_1 "RST_DLY_i[1]") (joined + (portRef O (instanceRef RST_DLY_i_1)) + (portRef I1 (instanceRef RST_DLY_e1_i_0_a2_0)) + (portRef I1 (instanceRef RST_DLY_e1_i_0_a2_1)) + )) + (net BERR_i (joined + (portRef O (instanceRef I_252)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__m)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__m)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_1_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_1_1_0)) + )) + (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined + (portRef O (instanceRef cpu_est_i_2)) + (portRef I1 (instanceRef un5_e_i_i_o2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a2_0_2)) + (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_2)) + )) + (net nEXP_SPACE_i (joined + (portRef O (instanceRef nEXP_SPACE_i)) + (portRef I0 (instanceRef un13_ciin_i_0)) + (portRef I1 (instanceRef un1_as_030_i_a2_i_o2)) + )) + (net (rename RST_DLY_i_0 "RST_DLY_i[0]") (joined + (portRef O (instanceRef RST_DLY_i_0)) + (portRef I1 (instanceRef RST_DLY_e0_i_0_a2_0_1)) + (portRef I1 (instanceRef RST_DLY_e1_i_0_a2_1_1)) + )) + (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined + (portRef O (instanceRef cpu_est_i_1)) + (portRef I1 (instanceRef un5_e_i_i_a2)) + (portRef I0 (instanceRef VMA_INT_0_m)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_2_3)) + (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a2_1_1_1)) + )) + (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined + (portRef O (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_1)) + (portRef I1 (instanceRef cpu_est_2_i_0_i_o2_3)) + (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_1)) + )) + (net VPA_D_i (joined + (portRef O (instanceRef VPA_D_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_2_3)) + (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0_2)) + )) + (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined + (portRef O (instanceRef SM_AMIGA_i_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_o2_2)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_0)) + )) + (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined + (portRef O (instanceRef SM_AMIGA_i_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_0)) + (portRef I1 (instanceRef un1_SM_AMIGA_5_0_o2_2_o2_2)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_2_0)) + )) + (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined + (portRef O (instanceRef cpu_est_i_3)) + (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0_2)) + (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2)) + (portRef I1 (instanceRef cpu_est_2_0_0_a2_1_1)) + (portRef I1 (instanceRef un5_e_i_i_a2_0)) + )) + (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined + (portRef O (instanceRef SM_AMIGA_i_1)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) + )) + (net RESET_OUT_i (joined + (portRef O (instanceRef RESET_OUT_i)) + (portRef I1 (instanceRef RESET_OUT_2_0_i_a2)) + (portRef OE (instanceRef RESET)) + )) (net BGACK_030_INT_i (joined (portRef O (instanceRef BGACK_030_INT_i)) - (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a3)) - (portRef I0 (instanceRef pos_clk_A0_DMA_3_0_a3)) - (portRef I0 (instanceRef un14_amiga_bus_data_dir_0_a2_i)) - (portRef I0 (instanceRef un1_as_030_i_a4_i_o3)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_o3)) - (portRef I0 (instanceRef un2_rw_i_a2_i)) - (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a3)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a3_0)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a3_1)) (portRef I1 (instanceRef un1_amiga_bus_enable_low)) - (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_0)) + (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2)) + (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) + (portRef I0 (instanceRef pos_clk_A0_DMA_3_0_a2)) + (portRef I0 (instanceRef un14_amiga_bus_data_dir_i_0)) + (portRef I0 (instanceRef un2_rw_i_a2)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_o2)) + (portRef I0 (instanceRef un1_as_030_i_a2_i_o2)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_1)) )) - (net AMIGA_BUS_ENABLE_DMA_LOW_i (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) - (portRef I0 (instanceRef un1_amiga_bus_enable_low)) + (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined + (portRef O (instanceRef SM_AMIGA_i_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_1)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0)) )) - (net UDS_000_INT_i (joined - (portRef O (instanceRef UDS_000_INT_i)) - (portRef I1 (instanceRef un4_uds_000)) + (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined + (portRef O (instanceRef SM_AMIGA_i_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_4)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_1_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) + )) + (net (rename CLK_000_P_SYNC_i_10 "CLK_000_P_SYNC_i[10]") (joined + (portRef O (instanceRef CLK_000_P_SYNC_i_10)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__n)) + (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o2_2_a2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_0)) + )) + (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined + (portRef O (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_4)) + (portRef I0 (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_0_a2_i)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) + (portRef I1 (instanceRef un1_SM_AMIGA_3_i_0_1)) + )) + (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined + (portRef O (instanceRef SM_AMIGA_i_i_7)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_o2_1)) + )) + (net (rename CLK_000_D_i_11 "CLK_000_D_i[11]") (joined + (portRef O (instanceRef CLK_000_D_i_11)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_1)) + )) + (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined + (portRef O (instanceRef SM_AMIGA_i_6)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0_6)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a2_6)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_1_0)) + )) + (net RW_i (joined + (portRef O (instanceRef I_253)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_0_a2_0_a2)) + )) + (net DS_000_ENABLE_1_sqmuxa_i (joined + (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i)) + (portRef I0 (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o2_2_o2_1)) )) (net LDS_000_INT_i (joined (portRef O (instanceRef LDS_000_INT_i)) (portRef I1 (instanceRef un4_lds_000)) )) - (net N_236_i (joined - (portRef O (instanceRef N_236_i)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i)) - (portRef I0 (instanceRef DSACK1_INT_0_m)) + (net UDS_000_INT_i (joined + (portRef O (instanceRef UDS_000_INT_i)) + (portRef I1 (instanceRef un4_uds_000)) )) - (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined - (portRef O (instanceRef SM_AMIGA_i_5)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o2_0_0)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a3_4)) - (portRef I0 (instanceRef AS_000_INT_0_m)) - (portRef I1 (instanceRef un1_SM_AMIGA_3_i_0_1)) + (net AS_030_i (joined + (portRef O (instanceRef I_254)) + (portRef I0 (instanceRef un21_fpu_cs_0_a2_1)) + (portRef I0 (instanceRef AS_030_D0_0_i_a2)) + (portRef I1 (instanceRef un4_as_000)) )) - (net DS_000_ENABLE_1_sqmuxa_i (joined - (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i)) - (portRef I0 (instanceRef RW_000_INT_0_m)) - (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o3_1)) + (net AS_000_INT_i (joined + (portRef O (instanceRef AS_000_INT_i)) + (portRef I0 (instanceRef un4_as_000)) )) - (net N_276_i (joined - (portRef O (instanceRef N_276_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + (net (rename A_DECODE_i_19 "A_DECODE_i[19]") (joined + (portRef O (instanceRef A_DECODE_i_19)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_3)) )) - (net RST_i (joined - (portRef O (instanceRef RST_i)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_a3_1)) + (net (rename A_DECODE_i_18 "A_DECODE_i[18]") (joined + (portRef O (instanceRef A_DECODE_i_18)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_3)) )) - (net (rename A_i_19 "A_i[19]") (joined - (portRef O (instanceRef A_i_19)) - (portRef I1 (instanceRef un22_berr_0_a2_0_a2_3)) + (net (rename A_DECODE_i_16 "A_DECODE_i[16]") (joined + (portRef O (instanceRef A_DECODE_i_16)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_2)) )) - (net (rename A_i_18 "A_i[18]") (joined - (portRef O (instanceRef A_i_18)) - (portRef I0 (instanceRef un22_berr_0_a2_0_a2_3)) + (net AS_000_i (joined + (portRef O (instanceRef I_255)) + (portRef I0 (instanceRef un6_ds_030)) + (portRef I1 (instanceRef un6_as_030_0_a2)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0_1)) )) - (net (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (joined - (portRef O (instanceRef SIZE_DMA_i_1)) - (portRef I1 (instanceRef un4_size)) + (net FPU_SENSE_i (joined + (portRef O (instanceRef FPU_SENSE_i)) + (portRef I0 (instanceRef un21_fpu_cs_0_a2_1_0)) + )) + (net AMIGA_BUS_ENABLE_DMA_HIGH_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_i)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__n)) + )) + (net CLK_030_i (joined + (portRef O (instanceRef CLK_030_i)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i)) + (portRef I1 (instanceRef CLK_030_H_2_i_o2)) + )) + (net DTACK_D0_i (joined + (portRef O (instanceRef DTACK_D0_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3_3)) + )) + (net (rename CLK_000_D_i_10 "CLK_000_D_i[10]") (joined + (portRef O (instanceRef CLK_000_D_i_10)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_0)) + )) + (net RW_000_i (joined + (portRef O (instanceRef I_256)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2)) + (portRef I1 (instanceRef un14_amiga_bus_data_dir_i_0)) + (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0_a2)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_1)) + )) + (net (rename A_i_1 "A_i[1]") (joined + (portRef O (instanceRef A_i_1)) + (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2)) + )) + (net CLK_030_H_i (joined + (portRef O (instanceRef CLK_030_H_i)) + (portRef I0 (instanceRef CLK_030_H_2_i_a2)) + )) + (net AS_000_DMA_i (joined + (portRef O (instanceRef AS_000_DMA_i)) + (portRef I0 (instanceRef un6_as_030_0_a2)) + (portRef I0 (instanceRef CLK_030_H_2_i_o2)) + )) + (net (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (joined + (portRef O (instanceRef CLK_000_D_i_0)) + (portRef I1 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a2_0)) + )) + (net (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (joined + (portRef O (instanceRef CLK_000_D_i_1)) + (portRef I1 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_0)) + )) + (net AS_030_D0_i (joined + (portRef O (instanceRef AS_030_D0_i)) + (portRef I0 (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o2)) + (portRef I1 (instanceRef un10_ciin_0_a2_5)) )) (net (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (joined (portRef O (instanceRef SIZE_DMA_i_0)) (portRef I1 (instanceRef un3_size)) )) - (net RW_i (joined - (portRef O (instanceRef I_195)) - (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_0_a3)) + (net (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (joined + (portRef O (instanceRef SIZE_DMA_i_1)) + (portRef I1 (instanceRef un4_size)) )) - (net CLK_000_PE_i (joined - (portRef O (instanceRef CLK_000_PE_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o2_0_0)) - (portRef I0 (instanceRef un1_SM_AMIGA_5_0_a2)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a3_0_0)) + (net (rename AHIGH_i_30 "AHIGH_i[30]") (joined + (portRef O (instanceRef I_257)) + (portRef I0 (instanceRef un10_ciin_0_a2_4)) )) - (net (rename A_i_16 "A_i[16]") (joined - (portRef O (instanceRef A_i_16)) - (portRef I1 (instanceRef un22_berr_0_a2_0_a2_2)) + (net (rename AHIGH_i_31 "AHIGH_i[31]") (joined + (portRef O (instanceRef I_258)) + (portRef I1 (instanceRef un10_ciin_0_a2_4)) )) - (net RESET_OUT_i (joined - (portRef O (instanceRef RESET_OUT_i)) - (portRef I1 (instanceRef RESET_OUT_2_i_0_a3)) - (portRef OE (instanceRef RESET)) + (net (rename AHIGH_i_28 "AHIGH_i[28]") (joined + (portRef O (instanceRef I_259)) + (portRef I0 (instanceRef un10_ciin_0_a2_3)) )) - (net BERR_i (joined - (portRef O (instanceRef I_196)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a3_0_1_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a3_1_1_0)) + (net (rename AHIGH_i_29 "AHIGH_i[29]") (joined + (portRef O (instanceRef I_260)) + (portRef I1 (instanceRef un10_ciin_0_a2_3)) )) - (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined - (portRef O (instanceRef SM_AMIGA_i_i_7)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) - (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_o2_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_6)) + (net (rename AHIGH_i_26 "AHIGH_i[26]") (joined + (portRef O (instanceRef I_261)) + (portRef I0 (instanceRef un10_ciin_0_a2_2)) )) - (net nEXP_SPACE_D0_i (joined - (portRef O (instanceRef nEXP_SPACE_D0_i)) - (portRef I0 (instanceRef un8_ciin_i_0_0)) - (portRef I1 (instanceRef un1_as_030_i_a4_i_o3)) + (net (rename AHIGH_i_27 "AHIGH_i[27]") (joined + (portRef O (instanceRef I_262)) + (portRef I1 (instanceRef un10_ciin_0_a2_2)) )) - (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined - (portRef O (instanceRef SM_AMIGA_i_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a3_0_4)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o2_5_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_3)) + (net (rename AHIGH_i_24 "AHIGH_i[24]") (joined + (portRef O (instanceRef I_263)) + (portRef I0 (instanceRef un10_ciin_0_a2_1)) )) - (net FPU_SENSE_i (joined - (portRef O (instanceRef FPU_SENSE_i)) - (portRef I0 (instanceRef un21_fpu_cs_0_a2_0_a3_1)) + (net (rename AHIGH_i_25 "AHIGH_i[25]") (joined + (portRef O (instanceRef I_264)) + (portRef I1 (instanceRef un10_ciin_0_a2_1)) )) - (net AS_030_i (joined - (portRef O (instanceRef I_197)) - (portRef I1 (instanceRef un4_as_000)) - (portRef I0 (instanceRef un22_berr_0_a2_0_a3_1)) - (portRef I0 (instanceRef AS_030_D0_0_i_a2_i)) - )) - (net AS_030_D0_i (joined - (portRef O (instanceRef AS_030_D0_i)) - (portRef I0 (instanceRef pos_clk_un3_as_030_d0_0_o3)) - (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_1)) - )) - (net (rename A_i_24 "A_i[24]") (joined - (portRef O (instanceRef A_i_24)) - (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_3)) - )) - (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined - (portRef O (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_o2_2)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a3_2_0)) - )) - (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined - (portRef O (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_a3_1)) - (portRef I1 (instanceRef cpu_est_2_i_0_i_o2_3)) - (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_1)) - )) - (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined - (portRef O (instanceRef cpu_est_i_3)) - (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3)) - (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0_2)) - (portRef I1 (instanceRef un5_e_i_i_a3_0)) - (portRef I1 (instanceRef cpu_est_2_0_0_a3_1_1)) - )) - (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined - (portRef O (instanceRef cpu_est_i_2)) - (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_2)) - (portRef I1 (instanceRef un5_e_i_i_o2)) - (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_2)) - )) - (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined - (portRef O (instanceRef cpu_est_i_1)) - (portRef I0 (instanceRef VMA_INT_0_m)) - (portRef I1 (instanceRef un5_e_i_i_a3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a2_2_2)) - (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_2)) - (portRef I1 (instanceRef cpu_est_2_0_0_a3_1_1_1)) - )) - (net VPA_D_i (joined - (portRef O (instanceRef VPA_D_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_2_2)) - (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0_2)) - )) - (net CLK_000_NE_i (joined - (portRef O (instanceRef CLK_000_NE_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_a3_0_4)) - (portRef I0 (instanceRef RST_DLYlde_i_a4_0_a2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_5)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a3_1_0)) - )) - (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined - (portRef O (instanceRef SM_AMIGA_i_1)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o2_0_0)) - )) - (net (rename RST_DLY_i_2 "RST_DLY_i[2]") (joined - (portRef O (instanceRef RST_DLY_i_2)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_a3_2)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_a3)) - )) - (net CLK_030_i (joined - (portRef O (instanceRef CLK_030_i)) - (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i)) - (portRef I1 (instanceRef CLK_030_H_2_0_a2_i_o2)) - )) - (net (rename RST_DLY_i_0 "RST_DLY_i[0]") (joined - (portRef O (instanceRef RST_DLY_i_0)) - (portRef I1 (instanceRef RST_DLY_e0_i_0_a3_0)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_0_1)) - )) - (net (rename RST_DLY_i_1 "RST_DLY_i[1]") (joined - (portRef O (instanceRef RST_DLY_i_1)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_1)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_0)) - )) - (net (rename CLK_000_D_i_1 "CLK_000_D_i[1]") (joined - (portRef O (instanceRef CLK_000_D_i_1)) - (portRef I1 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a3_0)) - )) - (net DTACK_D0_i (joined - (portRef O (instanceRef DTACK_D0_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_0_2)) - )) - (net RW_000_i (joined - (portRef O (instanceRef I_198)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3)) - (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i_a3)) - (portRef I1 (instanceRef un14_amiga_bus_data_dir_0_a2_i)) - (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i)) - )) - (net CLK_030_H_i (joined - (portRef O (instanceRef CLK_030_H_i)) - (portRef I0 (instanceRef CLK_030_H_2_0_a2_i_a3)) - )) - (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined - (portRef O (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a3_5)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o2_1_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o2_4_0)) - )) - (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined - (portRef O (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a3_1)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o2_5_0)) - )) - (net AS_000_i (joined - (portRef O (instanceRef I_199)) - (portRef I0 (instanceRef un6_ds_030)) - (portRef I1 (instanceRef un6_as_030_i_0)) - (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0_1)) - )) - (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined - (portRef O (instanceRef SM_AMIGA_i_0)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_a3_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o2_4_0)) - )) - (net A1_i (joined - (portRef O (instanceRef A1_i)) - (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a3)) - )) - (net (rename A_i_31 "A_i[31]") (joined - (portRef O (instanceRef A_i_31)) - (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_5)) - )) - (net (rename A_i_29 "A_i[29]") (joined - (portRef O (instanceRef A_i_29)) - (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_6)) - )) - (net (rename A_i_30 "A_i[30]") (joined - (portRef O (instanceRef A_i_30)) - (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_11)) - )) - (net (rename A_i_27 "A_i[27]") (joined - (portRef O (instanceRef A_i_27)) - (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_5)) - )) - (net (rename A_i_28 "A_i[28]") (joined - (portRef O (instanceRef A_i_28)) - (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_6)) - )) - (net (rename A_i_25 "A_i[25]") (joined - (portRef O (instanceRef A_i_25)) - (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_4)) - )) - (net (rename A_i_26 "A_i[26]") (joined - (portRef O (instanceRef A_i_26)) - (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_4)) + (net N_212_i (joined + (portRef O (instanceRef N_212_i)) + (portRef I1 (instanceRef G_137_1)) )) (net N_213_i (joined (portRef O (instanceRef N_213_i)) - (portRef I1 (instanceRef G_137_1)) + (portRef I1 (instanceRef G_137)) )) (net N_214_i (joined (portRef O (instanceRef N_214_i)) - (portRef I1 (instanceRef G_137)) - )) - (net N_215_i (joined - (portRef O (instanceRef N_215_i)) (portRef I0 (instanceRef G_137_1)) )) (net CLK_OUT_PRE_50_i (joined (portRef O (instanceRef CLK_OUT_PRE_50_i)) (portRef D (instanceRef CLK_OUT_PRE_50)) )) - (net N_275_i (joined - (portRef O (instanceRef N_275_i)) + (net N_323_i (joined + (portRef O (instanceRef N_323_i)) + (portRef D (instanceRef AS_030_D0)) + )) + (net N_321_i (joined + (portRef O (instanceRef N_321_i)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m)) )) + (net N_322_i (joined + (portRef O (instanceRef N_322_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + )) (net un6_ds_030_i (joined (portRef O (instanceRef un6_ds_030_i)) (portRef I0 (instanceRef DS_030)) @@ -2484,9 +2581,9 @@ (portRef O (instanceRef un4_as_000_i)) (portRef I0 (instanceRef AS_000)) )) - (net AS_000_INT_i (joined - (portRef O (instanceRef AS_000_INT_i)) - (portRef I0 (instanceRef un4_as_000)) + (net un6_as_030_i (joined + (portRef O (instanceRef un6_as_030_i)) + (portRef I0 (instanceRef AS_030)) )) (net un4_lds_000_i (joined (portRef O (instanceRef un4_lds_000_i)) @@ -2496,9 +2593,13 @@ (portRef O (instanceRef un4_uds_000_i)) (portRef I0 (instanceRef UDS_000)) )) + (net AMIGA_BUS_ENABLE_DMA_LOW_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) + (portRef I0 (instanceRef un1_amiga_bus_enable_low)) + )) (net AS_030_c (joined (portRef O (instanceRef AS_030)) - (portRef I0 (instanceRef I_197)) + (portRef I0 (instanceRef I_254)) )) (net AS_030 (joined (portRef AS_030) @@ -2506,8 +2607,8 @@ )) (net AS_000_c (joined (portRef O (instanceRef AS_000)) - (portRef I0 (instanceRef I_199)) - (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0_a2)) + (portRef I0 (instanceRef pos_clk_un4_bgack_000_i_o2)) + (portRef I0 (instanceRef I_255)) )) (net AS_000 (joined (portRef AS_000) @@ -2515,8 +2616,8 @@ )) (net RW_000_c (joined (portRef O (instanceRef RW_000)) - (portRef I0 (instanceRef I_198)) - (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0)) + (portRef I0 (instanceRef I_256)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0)) )) (net RW_000 (joined (portRef IO (instanceRef RW_000)) @@ -2528,8 +2629,8 @@ )) (net UDS_000_c (joined (portRef O (instanceRef UDS_000)) - (portRef I1 (instanceRef pos_clk_A0_DMA_3_0_a3)) - (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_a2)) + (portRef I1 (instanceRef pos_clk_A0_DMA_3_0_a2)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_a2)) (portRef I0 (instanceRef UDS_000_c_i)) )) (net UDS_000 (joined @@ -2538,7 +2639,7 @@ )) (net LDS_000_c (joined (portRef O (instanceRef LDS_000)) - (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_a2)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_a2)) (portRef I0 (instanceRef LDS_000_c_i)) )) (net LDS_000 (joined @@ -2547,7 +2648,7 @@ )) (net (rename SIZE_c_0 "SIZE_c[0]") (joined (portRef O (instanceRef SIZE_0)) - (portRef I1 (instanceRef pos_clk_un8_sm_amiga)) + (portRef I0 (instanceRef pos_clk_un10_sm_amiga_1)) )) (net (rename SIZE_0 "SIZE[0]") (joined (portRef IO (instanceRef SIZE_0)) @@ -2561,253 +2662,257 @@ (portRef (member size 0)) (portRef IO (instanceRef SIZE_1)) )) - (net (rename A_c_2 "A_c[2]") (joined - (portRef O (instanceRef A_2)) + (net (rename AHIGH_c_24 "AHIGH_c[24]") (joined + (portRef O (instanceRef AHIGH_24)) + (portRef I0 (instanceRef I_263)) )) - (net (rename A_2 "A[2]") (joined - (portRef (member a 29)) - (portRef I0 (instanceRef A_2)) + (net (rename AHIGH_24 "AHIGH[24]") (joined + (portRef IO (instanceRef AHIGH_24)) + (portRef (member ahigh 7)) )) - (net (rename A_c_3 "A_c[3]") (joined - (portRef O (instanceRef A_3)) + (net (rename AHIGH_c_25 "AHIGH_c[25]") (joined + (portRef O (instanceRef AHIGH_25)) + (portRef I0 (instanceRef I_264)) )) - (net (rename A_3 "A[3]") (joined - (portRef (member a 28)) - (portRef I0 (instanceRef A_3)) + (net (rename AHIGH_25 "AHIGH[25]") (joined + (portRef IO (instanceRef AHIGH_25)) + (portRef (member ahigh 6)) )) - (net (rename A_c_4 "A_c[4]") (joined - (portRef O (instanceRef A_4)) + (net (rename AHIGH_c_26 "AHIGH_c[26]") (joined + (portRef O (instanceRef AHIGH_26)) + (portRef I0 (instanceRef I_261)) )) - (net (rename A_4 "A[4]") (joined - (portRef (member a 27)) - (portRef I0 (instanceRef A_4)) + (net (rename AHIGH_26 "AHIGH[26]") (joined + (portRef IO (instanceRef AHIGH_26)) + (portRef (member ahigh 5)) )) - (net (rename A_c_5 "A_c[5]") (joined - (portRef O (instanceRef A_5)) + (net (rename AHIGH_c_27 "AHIGH_c[27]") (joined + (portRef O (instanceRef AHIGH_27)) + (portRef I0 (instanceRef I_262)) )) - (net (rename A_5 "A[5]") (joined - (portRef (member a 26)) - (portRef I0 (instanceRef A_5)) + (net (rename AHIGH_27 "AHIGH[27]") (joined + (portRef IO (instanceRef AHIGH_27)) + (portRef (member ahigh 4)) )) - (net (rename A_c_6 "A_c[6]") (joined - (portRef O (instanceRef A_6)) + (net (rename AHIGH_c_28 "AHIGH_c[28]") (joined + (portRef O (instanceRef AHIGH_28)) + (portRef I0 (instanceRef I_259)) )) - (net (rename A_6 "A[6]") (joined - (portRef (member a 25)) - (portRef I0 (instanceRef A_6)) + (net (rename AHIGH_28 "AHIGH[28]") (joined + (portRef IO (instanceRef AHIGH_28)) + (portRef (member ahigh 3)) )) - (net (rename A_c_7 "A_c[7]") (joined - (portRef O (instanceRef A_7)) + (net (rename AHIGH_c_29 "AHIGH_c[29]") (joined + (portRef O (instanceRef AHIGH_29)) + (portRef I0 (instanceRef I_260)) )) - (net (rename A_7 "A[7]") (joined - (portRef (member a 24)) - (portRef I0 (instanceRef A_7)) + (net (rename AHIGH_29 "AHIGH[29]") (joined + (portRef IO (instanceRef AHIGH_29)) + (portRef (member ahigh 2)) )) - (net (rename A_c_8 "A_c[8]") (joined - (portRef O (instanceRef A_8)) + (net (rename AHIGH_c_30 "AHIGH_c[30]") (joined + (portRef O (instanceRef AHIGH_30)) + (portRef I0 (instanceRef I_257)) )) - (net (rename A_8 "A[8]") (joined - (portRef (member a 23)) - (portRef I0 (instanceRef A_8)) + (net (rename AHIGH_30 "AHIGH[30]") (joined + (portRef IO (instanceRef AHIGH_30)) + (portRef (member ahigh 1)) )) - (net (rename A_c_9 "A_c[9]") (joined - (portRef O (instanceRef A_9)) + (net (rename AHIGH_c_31 "AHIGH_c[31]") (joined + (portRef O (instanceRef AHIGH_31)) + (portRef I0 (instanceRef I_258)) )) - (net (rename A_9 "A[9]") (joined - (portRef (member a 22)) - (portRef I0 (instanceRef A_9)) + (net (rename AHIGH_31 "AHIGH[31]") (joined + (portRef (member ahigh 0)) + (portRef IO (instanceRef AHIGH_31)) )) - (net (rename A_c_10 "A_c[10]") (joined - (portRef O (instanceRef A_10)) + (net (rename A_DECODE_c_2 "A_DECODE_c[2]") (joined + (portRef O (instanceRef A_DECODE_2)) )) - (net (rename A_10 "A[10]") (joined - (portRef (member a 21)) - (portRef I0 (instanceRef A_10)) + (net (rename A_DECODE_2 "A_DECODE[2]") (joined + (portRef (member a_decode 21)) + (portRef I0 (instanceRef A_DECODE_2)) )) - (net (rename A_c_11 "A_c[11]") (joined - (portRef O (instanceRef A_11)) + (net (rename A_DECODE_c_3 "A_DECODE_c[3]") (joined + (portRef O (instanceRef A_DECODE_3)) )) - (net (rename A_11 "A[11]") (joined - (portRef (member a 20)) - (portRef I0 (instanceRef A_11)) + (net (rename A_DECODE_3 "A_DECODE[3]") (joined + (portRef (member a_decode 20)) + (portRef I0 (instanceRef A_DECODE_3)) )) - (net (rename A_c_12 "A_c[12]") (joined - (portRef O (instanceRef A_12)) + (net (rename A_DECODE_c_4 "A_DECODE_c[4]") (joined + (portRef O (instanceRef A_DECODE_4)) )) - (net (rename A_12 "A[12]") (joined - (portRef (member a 19)) - (portRef I0 (instanceRef A_12)) + (net (rename A_DECODE_4 "A_DECODE[4]") (joined + (portRef (member a_decode 19)) + (portRef I0 (instanceRef A_DECODE_4)) )) - (net (rename A_c_13 "A_c[13]") (joined - (portRef O (instanceRef A_13)) + (net (rename A_DECODE_c_5 "A_DECODE_c[5]") (joined + (portRef O (instanceRef A_DECODE_5)) )) - (net (rename A_13 "A[13]") (joined - (portRef (member a 18)) - (portRef I0 (instanceRef A_13)) + (net (rename A_DECODE_5 "A_DECODE[5]") (joined + (portRef (member a_decode 18)) + (portRef I0 (instanceRef A_DECODE_5)) )) - (net (rename A_c_14 "A_c[14]") (joined - (portRef O (instanceRef A_14)) + (net (rename A_DECODE_c_6 "A_DECODE_c[6]") (joined + (portRef O (instanceRef A_DECODE_6)) )) - (net (rename A_14 "A[14]") (joined - (portRef (member a 17)) - (portRef I0 (instanceRef A_14)) + (net (rename A_DECODE_6 "A_DECODE[6]") (joined + (portRef (member a_decode 17)) + (portRef I0 (instanceRef A_DECODE_6)) )) - (net (rename A_c_15 "A_c[15]") (joined - (portRef O (instanceRef A_15)) + (net (rename A_DECODE_c_7 "A_DECODE_c[7]") (joined + (portRef O (instanceRef A_DECODE_7)) )) - (net (rename A_15 "A[15]") (joined - (portRef (member a 16)) - (portRef I0 (instanceRef A_15)) + (net (rename A_DECODE_7 "A_DECODE[7]") (joined + (portRef (member a_decode 16)) + (portRef I0 (instanceRef A_DECODE_7)) )) - (net (rename A_c_16 "A_c[16]") (joined - (portRef O (instanceRef A_16)) - (portRef I0 (instanceRef A_i_16)) + (net (rename A_DECODE_c_8 "A_DECODE_c[8]") (joined + (portRef O (instanceRef A_DECODE_8)) )) - (net (rename A_16 "A[16]") (joined - (portRef (member a 15)) - (portRef I0 (instanceRef A_16)) + (net (rename A_DECODE_8 "A_DECODE[8]") (joined + (portRef (member a_decode 15)) + (portRef I0 (instanceRef A_DECODE_8)) )) - (net (rename A_c_17 "A_c[17]") (joined - (portRef O (instanceRef A_17)) - (portRef I0 (instanceRef un22_berr_0_a2_0_a2_2)) + (net (rename A_DECODE_c_9 "A_DECODE_c[9]") (joined + (portRef O (instanceRef A_DECODE_9)) )) - (net (rename A_17 "A[17]") (joined - (portRef (member a 14)) - (portRef I0 (instanceRef A_17)) + (net (rename A_DECODE_9 "A_DECODE[9]") (joined + (portRef (member a_decode 14)) + (portRef I0 (instanceRef A_DECODE_9)) )) - (net (rename A_c_18 "A_c[18]") (joined - (portRef O (instanceRef A_18)) - (portRef I0 (instanceRef A_i_18)) + (net (rename A_DECODE_c_10 "A_DECODE_c[10]") (joined + (portRef O (instanceRef A_DECODE_10)) )) - (net (rename A_18 "A[18]") (joined - (portRef (member a 13)) - (portRef I0 (instanceRef A_18)) + (net (rename A_DECODE_10 "A_DECODE[10]") (joined + (portRef (member a_decode 13)) + (portRef I0 (instanceRef A_DECODE_10)) )) - (net (rename A_c_19 "A_c[19]") (joined - (portRef O (instanceRef A_19)) - (portRef I0 (instanceRef A_i_19)) + (net (rename A_DECODE_c_11 "A_DECODE_c[11]") (joined + (portRef O (instanceRef A_DECODE_11)) )) - (net (rename A_19 "A[19]") (joined - (portRef (member a 12)) - (portRef I0 (instanceRef A_19)) + (net (rename A_DECODE_11 "A_DECODE[11]") (joined + (portRef (member a_decode 12)) + (portRef I0 (instanceRef A_DECODE_11)) )) - (net (rename A_c_20 "A_c[20]") (joined - (portRef O (instanceRef A_20)) - (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_1)) + (net (rename A_DECODE_c_12 "A_DECODE_c[12]") (joined + (portRef O (instanceRef A_DECODE_12)) )) - (net (rename A_20 "A[20]") (joined - (portRef (member a 11)) - (portRef I0 (instanceRef A_20)) + (net (rename A_DECODE_12 "A_DECODE[12]") (joined + (portRef (member a_decode 11)) + (portRef I0 (instanceRef A_DECODE_12)) )) - (net (rename A_c_21 "A_c[21]") (joined - (portRef O (instanceRef A_21)) - (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_2)) + (net (rename A_DECODE_c_13 "A_DECODE_c[13]") (joined + (portRef O (instanceRef A_DECODE_13)) )) - (net (rename A_21 "A[21]") (joined - (portRef (member a 10)) - (portRef I0 (instanceRef A_21)) + (net (rename A_DECODE_13 "A_DECODE[13]") (joined + (portRef (member a_decode 10)) + (portRef I0 (instanceRef A_DECODE_13)) )) - (net (rename A_c_22 "A_c[22]") (joined - (portRef O (instanceRef A_22)) - (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_2)) + (net (rename A_DECODE_c_14 "A_DECODE_c[14]") (joined + (portRef O (instanceRef A_DECODE_14)) )) - (net (rename A_22 "A[22]") (joined - (portRef (member a 9)) - (portRef I0 (instanceRef A_22)) + (net (rename A_DECODE_14 "A_DECODE[14]") (joined + (portRef (member a_decode 9)) + (portRef I0 (instanceRef A_DECODE_14)) )) - (net (rename A_c_23 "A_c[23]") (joined - (portRef O (instanceRef A_23)) - (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_3)) + (net (rename A_DECODE_c_15 "A_DECODE_c[15]") (joined + (portRef O (instanceRef A_DECODE_15)) )) - (net (rename A_23 "A[23]") (joined - (portRef (member a 8)) - (portRef I0 (instanceRef A_23)) + (net (rename A_DECODE_15 "A_DECODE[15]") (joined + (portRef (member a_decode 8)) + (portRef I0 (instanceRef A_DECODE_15)) )) - (net (rename A_c_24 "A_c[24]") (joined - (portRef O (instanceRef A_24)) - (portRef I0 (instanceRef A_i_24)) + (net (rename A_DECODE_c_16 "A_DECODE_c[16]") (joined + (portRef O (instanceRef A_DECODE_16)) + (portRef I0 (instanceRef A_DECODE_i_16)) )) - (net (rename A_24 "A[24]") (joined - (portRef (member a 7)) - (portRef I0 (instanceRef A_24)) + (net (rename A_DECODE_16 "A_DECODE[16]") (joined + (portRef (member a_decode 7)) + (portRef I0 (instanceRef A_DECODE_16)) )) - (net (rename A_c_25 "A_c[25]") (joined - (portRef O (instanceRef A_25)) - (portRef I0 (instanceRef A_i_25)) + (net (rename A_DECODE_c_17 "A_DECODE_c[17]") (joined + (portRef O (instanceRef A_DECODE_17)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_2)) )) - (net (rename A_25 "A[25]") (joined - (portRef (member a 6)) - (portRef I0 (instanceRef A_25)) + (net (rename A_DECODE_17 "A_DECODE[17]") (joined + (portRef (member a_decode 6)) + (portRef I0 (instanceRef A_DECODE_17)) )) - (net (rename A_c_26 "A_c[26]") (joined - (portRef O (instanceRef A_26)) - (portRef I0 (instanceRef A_i_26)) + (net (rename A_DECODE_c_18 "A_DECODE_c[18]") (joined + (portRef O (instanceRef A_DECODE_18)) + (portRef I0 (instanceRef A_DECODE_i_18)) )) - (net (rename A_26 "A[26]") (joined - (portRef (member a 5)) - (portRef I0 (instanceRef A_26)) + (net (rename A_DECODE_18 "A_DECODE[18]") (joined + (portRef (member a_decode 5)) + (portRef I0 (instanceRef A_DECODE_18)) )) - (net (rename A_c_27 "A_c[27]") (joined - (portRef O (instanceRef A_27)) - (portRef I0 (instanceRef A_i_27)) + (net (rename A_DECODE_c_19 "A_DECODE_c[19]") (joined + (portRef O (instanceRef A_DECODE_19)) + (portRef I0 (instanceRef A_DECODE_i_19)) )) - (net (rename A_27 "A[27]") (joined - (portRef (member a 4)) - (portRef I0 (instanceRef A_27)) + (net (rename A_DECODE_19 "A_DECODE[19]") (joined + (portRef (member a_decode 4)) + (portRef I0 (instanceRef A_DECODE_19)) )) - (net (rename A_c_28 "A_c[28]") (joined - (portRef O (instanceRef A_28)) - (portRef I0 (instanceRef A_i_28)) + (net (rename A_DECODE_c_20 "A_DECODE_c[20]") (joined + (portRef O (instanceRef A_DECODE_20)) + (portRef I0 (instanceRef un10_ciin_0_a2_6)) )) - (net (rename A_28 "A[28]") (joined - (portRef (member a 3)) - (portRef I0 (instanceRef A_28)) + (net (rename A_DECODE_20 "A_DECODE[20]") (joined + (portRef (member a_decode 3)) + (portRef I0 (instanceRef A_DECODE_20)) )) - (net (rename A_c_29 "A_c[29]") (joined - (portRef O (instanceRef A_29)) - (portRef I0 (instanceRef A_i_29)) + (net (rename A_DECODE_c_21 "A_DECODE_c[21]") (joined + (portRef O (instanceRef A_DECODE_21)) + (portRef I1 (instanceRef un10_ciin_0_a2_6)) )) - (net (rename A_29 "A[29]") (joined - (portRef (member a 2)) - (portRef I0 (instanceRef A_29)) + (net (rename A_DECODE_21 "A_DECODE[21]") (joined + (portRef (member a_decode 2)) + (portRef I0 (instanceRef A_DECODE_21)) )) - (net (rename A_c_30 "A_c[30]") (joined - (portRef O (instanceRef A_30)) - (portRef I0 (instanceRef A_i_30)) + (net (rename A_DECODE_c_22 "A_DECODE_c[22]") (joined + (portRef O (instanceRef A_DECODE_22)) + (portRef I1 (instanceRef un10_ciin_0_a2_11)) )) - (net (rename A_30 "A[30]") (joined - (portRef (member a 1)) - (portRef I0 (instanceRef A_30)) + (net (rename A_DECODE_22 "A_DECODE[22]") (joined + (portRef (member a_decode 1)) + (portRef I0 (instanceRef A_DECODE_22)) )) - (net (rename A_c_31 "A_c[31]") (joined - (portRef O (instanceRef A_31)) - (portRef I0 (instanceRef A_i_31)) + (net (rename A_DECODE_c_23 "A_DECODE_c[23]") (joined + (portRef O (instanceRef A_DECODE_23)) + (portRef I0 (instanceRef un10_ciin_0_a2_5)) )) - (net (rename A_31 "A[31]") (joined - (portRef (member a 0)) - (portRef I0 (instanceRef A_31)) + (net (rename A_DECODE_23 "A_DECODE[23]") (joined + (portRef (member a_decode 0)) + (portRef I0 (instanceRef A_DECODE_23)) )) - (net A0_c (joined - (portRef O (instanceRef A0)) + (net (rename A_c_0 "A_c[0]") (joined + (portRef O (instanceRef A_0)) (portRef I0 (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef A0_c_i)) + (portRef I0 (instanceRef A_c_i_0)) )) - (net A0 (joined - (portRef A0) - (portRef IO (instanceRef A0)) + (net (rename A_0 "A[0]") (joined + (portRef IO (instanceRef A_0)) + (portRef (member a 1)) )) - (net A1_c (joined - (portRef O (instanceRef A1)) - (portRef I0 (instanceRef A1_i)) - (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a3)) + (net (rename A_c_1 "A_c[1]") (joined + (portRef O (instanceRef A_1)) + (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2)) + (portRef I0 (instanceRef A_i_1)) )) - (net A1 (joined - (portRef A1) - (portRef I0 (instanceRef A1)) + (net (rename A_1 "A[1]") (joined + (portRef (member a 0)) + (portRef I0 (instanceRef A_1)) )) (net nEXP_SPACE_c (joined (portRef O (instanceRef nEXP_SPACE)) - (portRef I0 (instanceRef nEXP_SPACE_c_i)) + (portRef I0 (instanceRef nEXP_SPACE_i)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_o2)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_0)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2_1)) + (portRef OE (instanceRef DSACK1)) )) (net nEXP_SPACE (joined (portRef nEXP_SPACE) @@ -2815,11 +2920,9 @@ )) (net BERR_c (joined (portRef O (instanceRef BERR)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_5__m)) - (portRef I0 (instanceRef I_196)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_0_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__m)) - (portRef I1 (instanceRef pos_clk_un3_as_030_d0_0_o3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_6)) + (portRef I1 (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o2)) + (portRef I0 (instanceRef I_252)) )) (net BERR (joined (portRef BERR) @@ -2849,8 +2952,8 @@ )) (net BGACK_000_c (joined (portRef O (instanceRef BGACK_000)) - (portRef I1 (instanceRef un22_berr_0_a2_0_a3_1)) - (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2_1)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0)) (portRef I0 (instanceRef BGACK_030_INT_0_m)) )) (net BGACK_000 (joined @@ -2859,8 +2962,8 @@ )) (net CLK_030_c (joined (portRef O (instanceRef CLK_030)) - (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_a3)) - (portRef I0 (instanceRef DSACK1_INT_0_sqmuxa_i_i_o2_0)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i_a2)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_0)) (portRef I0 (instanceRef CLK_030_i)) )) (net CLK_030 (joined @@ -2869,6 +2972,7 @@ )) (net CLK_000_c (joined (portRef O (instanceRef CLK_000)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_1_0)) (portRef D (instanceRef CLK_000_D_0)) )) (net CLK_000 (joined @@ -2889,7 +2993,17 @@ (portRef CLK (instanceRef BG_000DFF)) (portRef CLK (instanceRef CLK_000_D_0)) (portRef CLK (instanceRef CLK_000_D_1)) - (portRef CLK (instanceRef CLK_000_NE)) + (portRef CLK (instanceRef CLK_000_D_2)) + (portRef CLK (instanceRef CLK_000_D_3)) + (portRef CLK (instanceRef CLK_000_D_4)) + (portRef CLK (instanceRef CLK_000_D_5)) + (portRef CLK (instanceRef CLK_000_D_6)) + (portRef CLK (instanceRef CLK_000_D_7)) + (portRef CLK (instanceRef CLK_000_D_8)) + (portRef CLK (instanceRef CLK_000_D_9)) + (portRef CLK (instanceRef CLK_000_D_10)) + (portRef CLK (instanceRef CLK_000_D_11)) + (portRef CLK (instanceRef CLK_000_D_12)) (portRef CLK (instanceRef CLK_000_NE_D0)) (portRef CLK (instanceRef CLK_000_N_SYNC_0)) (portRef CLK (instanceRef CLK_000_N_SYNC_1)) @@ -2903,7 +3017,7 @@ (portRef CLK (instanceRef CLK_000_N_SYNC_9)) (portRef CLK (instanceRef CLK_000_N_SYNC_10)) (portRef CLK (instanceRef CLK_000_N_SYNC_11)) - (portRef CLK (instanceRef CLK_000_PE)) + (portRef CLK (instanceRef CLK_000_N_SYNC_12)) (portRef CLK (instanceRef CLK_000_P_SYNC_0)) (portRef CLK (instanceRef CLK_000_P_SYNC_1)) (portRef CLK (instanceRef CLK_000_P_SYNC_2)) @@ -2914,6 +3028,7 @@ (portRef CLK (instanceRef CLK_000_P_SYNC_7)) (portRef CLK (instanceRef CLK_000_P_SYNC_8)) (portRef CLK (instanceRef CLK_000_P_SYNC_9)) + (portRef CLK (instanceRef CLK_000_P_SYNC_10)) (portRef CLK (instanceRef CLK_030_H)) (portRef CLK (instanceRef CLK_OUT_INT)) (portRef CLK (instanceRef CLK_OUT_PRE_50)) @@ -2954,7 +3069,6 @@ (portRef CLK (instanceRef cpu_est_1)) (portRef CLK (instanceRef cpu_est_2)) (portRef CLK (instanceRef cpu_est_3)) - (portRef CLK (instanceRef nEXP_SPACE_D0)) )) (net CLK_OSZI (joined (portRef CLK_OSZI) @@ -2980,7 +3094,7 @@ (net FPU_SENSE_c (joined (portRef O (instanceRef FPU_SENSE)) (portRef I0 (instanceRef FPU_SENSE_i)) - (portRef I1 (instanceRef un22_berr_0_a2_0_a3_1_0)) + (portRef I1 (instanceRef un22_berr_0_a2_1)) )) (net FPU_SENSE (joined (portRef FPU_SENSE) @@ -3079,49 +3193,49 @@ (portRef O (instanceRef RST)) (portRef I1 (instanceRef DS_000_DMA_1)) (portRef I1 (instanceRef AS_000_DMA_1)) - (portRef I1 (instanceRef LDS_000_INT_1)) (portRef I1 (instanceRef RW_000_DMA_2)) (portRef I1 (instanceRef A0_DMA_1)) - (portRef I1 (instanceRef UDS_000_INT_1)) - (portRef I1 (instanceRef VMA_INT_1)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) - (portRef I1 (instanceRef BG_000_1)) - (portRef I1 (instanceRef IPL_030_1_2)) - (portRef I1 (instanceRef IPL_030_1_1)) - (portRef I1 (instanceRef IPL_030_1_0)) - (portRef I1 (instanceRef IPL_D0_0_2)) - (portRef I1 (instanceRef IPL_D0_0_1)) - (portRef I1 (instanceRef IPL_D0_0_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i)) + (portRef I1 (instanceRef AS_030_D0_0_i_a2)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0)) + (portRef I1 (instanceRef BGACK_030_INT_1)) (portRef I1 (instanceRef DTACK_D0_0)) (portRef I0 (instanceRef VPA_D_0)) - (portRef I0 (instanceRef nEXP_SPACE_D0_0)) - (portRef I1 (instanceRef RST_DLYlde_i_a4_0_a2)) - (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1)) - (portRef I1 (instanceRef RESET_OUT_2_i_0)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_o2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_o3_0)) - (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_o3)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) - (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) - (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_0_a2_i)) - (portRef I1 (instanceRef AS_030_D0_0_i_a2_i)) - (portRef I1 (instanceRef DS_000_ENABLE_1)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) - (portRef I0 (instanceRef RST_i)) - (portRef I1 (instanceRef RW_000_INT_2)) - (portRef I1 (instanceRef BGACK_030_INT_1)) - (portRef I1 (instanceRef AS_030_000_SYNC_1)) (portRef I1 (instanceRef AS_000_INT_1)) + (portRef I1 (instanceRef AS_030_000_SYNC_1)) + (portRef I1 (instanceRef RW_000_INT_2)) + (portRef I1 (instanceRef DS_000_ENABLE_1)) + (portRef I1 (instanceRef VMA_INT_1)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_o2)) + (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1)) + (portRef I1 (instanceRef RESET_OUT_2_0_i)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_o2)) + (portRef I1 (instanceRef IPL_030_1_0)) + (portRef I1 (instanceRef IPL_030_1_1)) + (portRef I1 (instanceRef IPL_030_1_2)) + (portRef I1 (instanceRef BG_000_1)) + (portRef I1 (instanceRef UDS_000_INT_1)) + (portRef I1 (instanceRef LDS_000_INT_1)) (portRef I1 (instanceRef DSACK1_INT_1)) + (portRef I1 (instanceRef IPL_D0_0_0)) + (portRef I1 (instanceRef IPL_D0_0_1)) + (portRef I1 (instanceRef IPL_D0_0_2)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_2_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a3_0_2_2)) + (portRef I1 (instanceRef RST_DLY_e1_i_0_1)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_2_2)) + (portRef I1 (instanceRef RST_DLY_e0_i_0_a2_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_2_6)) (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_4)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_5)) - (portRef I1 (instanceRef CLK_030_H_2_0_a2_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a3_1_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a3_1_6)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_1_6)) + (portRef I1 (instanceRef RST_DLY_e0_i_0)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_4)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_5)) + (portRef I1 (instanceRef CLK_030_H_2_i_1)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a2_1_2)) )) (net RST (joined (portRef RST) @@ -3133,7 +3247,7 @@ )) (net RW_c (joined (portRef O (instanceRef RW)) - (portRef I0 (instanceRef I_195)) + (portRef I0 (instanceRef I_253)) )) (net RW (joined (portRef IO (instanceRef RW)) @@ -3141,7 +3255,7 @@ )) (net (rename FC_c_0 "FC_c[0]") (joined (portRef O (instanceRef FC_0)) - (portRef I0 (instanceRef un22_berr_0_a2_0_a2_1)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_1)) )) (net (rename FC_0 "FC[0]") (joined (portRef (member fc 1)) @@ -3149,7 +3263,7 @@ )) (net (rename FC_c_1 "FC_c[1]") (joined (portRef O (instanceRef FC_1)) - (portRef I1 (instanceRef un22_berr_0_a2_0_a2_1)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_1)) )) (net (rename FC_1 "FC[1]") (joined (portRef (member fc 0)) @@ -3179,13 +3293,473 @@ (portRef O (instanceRef CIIN)) (portRef CIIN) )) - (net N_24_i (joined - (portRef O (instanceRef N_24_i)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) + (net BG_030_c_i (joined + (portRef O (instanceRef BG_030_c_i)) + (portRef I0 (instanceRef pos_clk_un9_bg_030)) )) - (net N_35_0 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) + (net (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (joined + (portRef O (instanceRef pos_clk_un6_bg_030_i)) + (portRef I1 (instanceRef pos_clk_un9_bg_030)) + )) + (net (rename pos_clk_un9_bg_030_0 "pos_clk.un9_bg_030_0") (joined + (portRef O (instanceRef pos_clk_un9_bg_030)) + (portRef I0 (instanceRef pos_clk_un9_bg_030_i)) + )) + (net N_26_i (joined + (portRef O (instanceRef N_26_i)) + (portRef I0 (instanceRef BG_000_1)) + )) + (net N_33_0 (joined + (portRef O (instanceRef BG_000_1)) + (portRef I0 (instanceRef BG_000_1_i)) + )) + (net N_21_i (joined + (portRef O (instanceRef N_21_i)) + (portRef I0 (instanceRef UDS_000_INT_1)) + )) + (net N_38_0 (joined + (portRef O (instanceRef UDS_000_INT_1)) + (portRef I0 (instanceRef UDS_000_INT_1_i)) + )) + (net N_17_i (joined + (portRef O (instanceRef N_17_i)) + (portRef I0 (instanceRef LDS_000_INT_1)) + )) + (net N_42_0 (joined + (portRef O (instanceRef LDS_000_INT_1)) + (portRef I0 (instanceRef LDS_000_INT_1_i)) + )) + (net N_4_i (joined + (portRef O (instanceRef N_4_i)) + (portRef I0 (instanceRef DSACK1_INT_1)) + )) + (net N_48_0 (joined + (portRef O (instanceRef DSACK1_INT_1)) + (portRef I0 (instanceRef DSACK1_INT_1_i)) + )) + (net (rename IPL_c_i_0 "IPL_c_i[0]") (joined + (portRef O (instanceRef IPL_c_i_0)) + (portRef I0 (instanceRef IPL_D0_0_0)) + )) + (net N_51_0 (joined + (portRef O (instanceRef IPL_D0_0_0)) + (portRef I0 (instanceRef IPL_D0_0_i_0)) + )) + (net (rename IPL_c_i_1 "IPL_c_i[1]") (joined + (portRef O (instanceRef IPL_c_i_1)) + (portRef I0 (instanceRef IPL_D0_0_1)) + )) + (net N_52_0 (joined + (portRef O (instanceRef IPL_D0_0_1)) + (portRef I0 (instanceRef IPL_D0_0_i_1)) + )) + (net (rename IPL_c_i_2 "IPL_c_i[2]") (joined + (portRef O (instanceRef IPL_c_i_2)) + (portRef I0 (instanceRef IPL_D0_0_2)) + )) + (net N_53_0 (joined + (portRef O (instanceRef IPL_D0_0_2)) + (portRef I0 (instanceRef IPL_D0_0_i_2)) + )) + (net N_27_i (joined + (portRef O (instanceRef N_27_i)) + (portRef I0 (instanceRef IPL_030_1_0)) + )) + (net N_30_0 (joined + (portRef O (instanceRef IPL_030_1_0)) + (portRef I0 (instanceRef IPL_030_1_i_0)) + )) + (net N_28_i (joined + (portRef O (instanceRef N_28_i)) + (portRef I0 (instanceRef IPL_030_1_1)) + )) + (net N_31_0 (joined + (portRef O (instanceRef IPL_030_1_1)) + (portRef I0 (instanceRef IPL_030_1_i_1)) + )) + (net N_29_i (joined + (portRef O (instanceRef N_29_i)) + (portRef I0 (instanceRef IPL_030_1_2)) + )) + (net N_32_0 (joined + (portRef O (instanceRef IPL_030_1_2)) + (portRef I0 (instanceRef IPL_030_1_i_2)) + )) + (net (rename A_c_i_0 "A_c_i[0]") (joined + (portRef O (instanceRef A_c_i_0)) + (portRef I1 (instanceRef pos_clk_un10_sm_amiga_1)) + )) + (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined + (portRef O (instanceRef SIZE_c_i_1)) + (portRef I1 (instanceRef pos_clk_un10_sm_amiga)) + )) + (net (rename pos_clk_un10_sm_amiga_i "pos_clk.un10_sm_amiga_i") (joined + (portRef O (instanceRef pos_clk_un10_sm_amiga)) + (portRef I0 (instanceRef LDS_000_INT_0_m)) + )) + (net N_258_0 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_i)) + )) + (net N_357_i (joined + (portRef O (instanceRef N_357_i)) + (portRef I1 (instanceRef cpu_est_2_0_0_0_2)) + )) + (net N_254_i (joined + (portRef O (instanceRef N_254_i)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_2)) + )) + (net (rename cpu_est_2_0_2 "cpu_est_2_0[2]") (joined + (portRef O (instanceRef cpu_est_2_0_0_0_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_i_2)) + )) + (net N_315_i (joined + (portRef O (instanceRef N_315_i)) + (portRef I1 (instanceRef cpu_est_2_i_0_i_3)) + )) + (net N_291_0 (joined + (portRef O (instanceRef cpu_est_2_i_0_i_3)) + (portRef I0 (instanceRef cpu_est_2_i_0_i_i_3)) + )) + (net AS_030_000_SYNC_i (joined + (portRef O (instanceRef AS_030_000_SYNC_i)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_1_0)) + )) + (net N_146_0 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_i_0)) + )) + (net N_149_i (joined + (portRef O (instanceRef RST_DLY_e2_i_0_o2_0)) + (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2)) + (portRef I0 (instanceRef RST_DLY_e1_i_0_a2)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_0_i)) + )) + (net N_164_i (joined + (portRef O (instanceRef cpu_est_2_0_0_0_o2_2)) + (portRef I0 (instanceRef cpu_est_2_i_0_i_a2_3)) + (portRef I0 (instanceRef cpu_est_2_0_0_a2_0_2)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_i_2)) + )) + (net N_166_i (joined + (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2)) + (portRef I1 (instanceRef RESET_OUT_2_0_i_o2)) + (portRef I1 (instanceRef RST_DLY_e2_i_0_a2_0)) + (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2_i)) + )) + (net N_172_i (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0)) + (portRef I0 (instanceRef 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I1 (instanceRef cpu_est_2_0_0_0_1)) + )) + (net (rename cpu_est_2_0_1 "cpu_est_2_0[1]") (joined + (portRef O (instanceRef cpu_est_2_0_0_0_1)) + (portRef I0 (instanceRef cpu_est_2_0_0_0_i_1)) + )) + (net N_231_i (joined + (portRef O (instanceRef N_231_i)) + (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0)) + )) + (net N_230_i (joined + (portRef O (instanceRef N_230_i)) + (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0)) + )) + (net (rename pos_clk_un4_clk_000_pe_0 "pos_clk.un4_clk_000_pe_0") (joined + (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0)) + (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_i)) + )) + (net N_22_i (joined + (portRef O (instanceRef N_22_i)) + (portRef I0 (instanceRef VMA_INT_1)) + )) + (net N_37_0 (joined + (portRef O (instanceRef VMA_INT_1)) + (portRef I0 (instanceRef VMA_INT_1_i)) + )) + (net N_142_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_6)) + (portRef D (instanceRef SM_AMIGA_6)) + )) + (net N_334_i (joined + (portRef O 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N_345_i (joined + (portRef O (instanceRef N_345_i)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2)) + )) + (net N_344_i (joined + (portRef O (instanceRef N_344_i)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2)) + )) + (net N_153_0 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_i)) + )) + (net (rename pos_clk_un3_as_030_d0_i "pos_clk.un3_as_030_d0_i") (joined + (portRef O (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o2)) + (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_1_a2_0_a2)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_0)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_a2)) + (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_0_a2_i)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0)) + (portRef I0 (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o2_i)) + )) + (net N_293_0 (joined + (portRef O (instanceRef AS_000_INT_1_sqmuxa_0_a2_i)) + (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_0_a2_i_i)) + )) + (net N_233_i (joined + (portRef O (instanceRef N_233_i)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i)) + )) + (net N_232_i (joined + (portRef O (instanceRef N_232_i)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i)) + )) + (net N_290_0 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_i)) + )) + (net VPA_c_i (joined + (portRef O (instanceRef VPA_c_i)) + (portRef I1 (instanceRef VPA_D_0)) + )) + (net N_54_0 (joined + (portRef O (instanceRef VPA_D_0)) + (portRef I0 (instanceRef VPA_D_0_i)) + )) + (net N_5_i (joined + (portRef O (instanceRef N_5_i)) + (portRef I0 (instanceRef AS_000_INT_1)) + )) + (net N_47_0 (joined + (portRef O (instanceRef AS_000_INT_1)) + (portRef I0 (instanceRef AS_000_INT_1_i)) + )) + (net N_7_i (joined + (portRef O (instanceRef N_7_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_1)) + )) + (net N_46_0 (joined + (portRef O (instanceRef AS_030_000_SYNC_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_i)) )) (net N_18_i (joined (portRef O (instanceRef N_18_i)) @@ -3203,705 +3777,254 @@ (portRef O (instanceRef BGACK_030_INT_1)) (portRef I0 (instanceRef BGACK_030_INT_1_i)) )) - (net N_7_i (joined - (portRef O (instanceRef N_7_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_1)) + (net DTACK_c_i (joined + (portRef O (instanceRef DTACK_c_i)) + (portRef I0 (instanceRef DTACK_D0_0)) )) - (net N_46_0 (joined - (portRef O (instanceRef AS_030_000_SYNC_1)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_i)) + (net N_55_0 (joined + (portRef O (instanceRef DTACK_D0_0)) + (portRef I0 (instanceRef DTACK_D0_0_i)) )) - (net N_5_i (joined - (portRef O (instanceRef N_5_i)) - (portRef I0 (instanceRef AS_000_INT_1)) + (net (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (joined + (portRef O (instanceRef pos_clk_un6_bgack_000_0)) + (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_i)) )) - (net N_47_0 (joined - (portRef O (instanceRef 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)) - (net N_271_i (joined - (portRef O (instanceRef N_271_i)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i)) + (net N_187_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_4)) )) - (net N_279_0 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_i)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_i)) + (net N_203_i (joined + (portRef O (instanceRef pos_clk_un4_bgack_000_i_o2)) + (portRef I0 (instanceRef pos_clk_un4_bgack_000_i_o2_i)) )) - (net N_280_0 (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa_i)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i_i)) + (net N_324_i (joined + (portRef O (instanceRef N_324_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0)) )) - (net N_281_0 (joined - (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i)) - (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_i)) + (net N_130_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0)) + (portRef D (instanceRef SM_AMIGA_0)) )) - (net N_298_i (joined - (portRef O (instanceRef N_298_i)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) + (net N_199_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_o2_i_0)) )) - (net (rename pos_clk_SIZE_DMA_6_0_0 "pos_clk.SIZE_DMA_6_0[0]") (joined - (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) - (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) + (net N_197_0 (joined + (portRef O (instanceRef CLK_030_H_2_i_o2)) + (portRef I0 (instanceRef CLK_030_H_2_i_o2_i)) )) - (net N_299_i (joined - (portRef O (instanceRef N_299_i)) + (net N_196_0 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_3)) + )) + (net LDS_000_c_i (joined + (portRef O (instanceRef LDS_000_c_i)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) + )) + (net UDS_000_c_i (joined + (portRef O (instanceRef UDS_000_c_i)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) + )) + (net N_181_i (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_0)) + (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_a2_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_o2_i_0)) + )) + (net N_347_i (joined + (portRef O (instanceRef N_347_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) + )) + (net N_348_i (joined + (portRef O (instanceRef N_348_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) + )) + (net N_178_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_i_3)) + )) + (net VMA_INT_i (joined + (portRef O (instanceRef VMA_INT_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_1_3)) + )) + (net (rename pos_clk_un5_bgack_030_int_d_i "pos_clk.un5_bgack_030_int_d_i") (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_o2)) + (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_i)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_o2_1)) + )) + (net (rename pos_clk_un23_bgack_030_int_i_1_0 "pos_clk.un23_bgack_030_int_i_1_0") (joined + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_0_o2)) + (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_0)) + (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_i)) + (portRef I1 (instanceRef CLK_030_H_2_i)) + (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_i)) + )) + (net CLK_OUT_PRE_D_i (joined + (portRef O (instanceRef CLK_OUT_PRE_D_i)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_0)) + )) + (net N_148_0 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_0)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_0_i)) + )) + (net N_341_i (joined + (portRef O (instanceRef N_341_i)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2)) + )) + (net N_338_i (joined + (portRef O (instanceRef N_338_i)) + (portRef I0 (instanceRef RST_DLY_e0_i_0_1)) + )) + (net N_339_i (joined + (portRef O (instanceRef N_339_i)) + (portRef I1 (instanceRef RST_DLY_e0_i_0_1)) + )) + (net N_239_i (joined + (portRef O (instanceRef RST_DLY_e0_i_0)) + (portRef D (instanceRef RST_DLY_0)) + )) + (net N_336_i (joined + (portRef O (instanceRef N_336_i)) + (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0_1)) + )) + (net N_122_0 (joined + (portRef O (instanceRef un1_SM_AMIGA_3_i_0)) + (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0_i)) + )) + (net N_211_i (joined + (portRef O (instanceRef N_211_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_1)) + )) + (net N_332_i (joined + (portRef O (instanceRef N_332_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_1)) + )) + (net N_132_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1)) + (portRef D (instanceRef SM_AMIGA_1)) + )) + (net N_331_i (joined + (portRef O (instanceRef N_331_i)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_1)) + )) + (net N_120_0 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i_i)) + )) + (net N_330_i (joined + (portRef O (instanceRef N_330_i)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0)) + )) + (net (rename pos_clk_DS_000_DMA_4_0 "pos_clk.DS_000_DMA_4_0") (joined + (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_0)) + (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_0_i)) + )) + (net N_329_i (joined + (portRef O (instanceRef N_329_i)) (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) )) (net (rename pos_clk_SIZE_DMA_6_0_1 "pos_clk.SIZE_DMA_6_0[1]") (joined (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_1)) (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_1)) )) - (net un1_as_000_i (joined - (portRef O (instanceRef un1_as_000_0_0)) - (portRef OE (instanceRef AS_000)) - (portRef OE (instanceRef LDS_000)) - (portRef OE (instanceRef RW_000)) - (portRef OE (instanceRef UDS_000)) - )) - (net N_358_i (joined - (portRef O (instanceRef N_358_i)) - (portRef I1 (instanceRef pos_clk_un6_bgack_000_0_0)) - )) - (net (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (joined - (portRef O (instanceRef pos_clk_un6_bgack_000_0_0)) - (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0_i)) - )) - (net N_284_i (joined - (portRef O (instanceRef un2_rw_i_a2_i)) - (portRef OE (instanceRef RW)) - )) - (net N_285_i (joined - (portRef O (instanceRef un3_as_030_i_a2_i)) - (portRef OE (instanceRef A0)) - (portRef OE (instanceRef AS_030)) - (portRef OE (instanceRef DS_030)) - )) - (net N_286_0 (joined - (portRef O (instanceRef SIZE_DMA_3_sqmuxa_0_a2_i)) - (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_0_a2_i_i)) - )) - (net N_88_0 (joined - (portRef O (instanceRef AS_030_D0_0_i_a2_i)) - (portRef I0 (instanceRef AS_030_D0_0_i_a2_i_i)) - )) - (net (rename pos_clk_un3_as_030_d0_i "pos_clk.un3_as_030_d0_i") (joined - (portRef O (instanceRef pos_clk_un3_as_030_d0_0_o3)) - (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_i)) - (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i)) - (portRef I1 (instanceRef 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SM_AMIGA_nss_i_i_0_a3_2_2_0)) - )) - (net N_193_i (joined - (portRef O (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a4_i_o3)) - (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_0_a2_i)) - (portRef I0 (instanceRef pos_clk_un5_bgack_030_int_d_i_0_a4_i_o3_i)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_o2_1)) - )) - (net N_192_0 (joined - (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3)) - (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i)) - (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i)) - (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_i)) - (portRef I0 (instanceRef CLK_030_H_2_0_a2_i_1)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_1)) - )) - (net (rename CLK_000_N_SYNC_i_10 "CLK_000_N_SYNC_i[10]") (joined - (portRef O (instanceRef CLK_000_N_SYNC_i_10)) - (portRef I0 (instanceRef DSACK1_INT_0_sqmuxa_i_i_o2)) - )) - (net N_350_i (joined - (portRef O (instanceRef N_350_i)) - (portRef I1 (instanceRef DSACK1_INT_0_sqmuxa_i_i_o2)) - )) - (net N_188_0 (joined - (portRef O (instanceRef DSACK1_INT_0_sqmuxa_i_i_o2)) - (portRef I0 (instanceRef DSACK1_INT_0_sqmuxa_i_i_o2_i)) - )) - (net N_187_i (joined - (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_a3_0)) - (portRef I1 (instanceRef RESET_OUT_2_i_0_o2)) - (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2_i)) - )) - (net N_185_i (joined - (portRef O (instanceRef cpu_est_2_0_0_0_o2_2)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_2)) - (portRef I0 (instanceRef cpu_est_2_i_0_i_a3_3)) - (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_i_2)) - )) - (net N_182_i (joined - (portRef O (instanceRef cpu_est_2_i_0_i_o2_3)) - (portRef I0 (instanceRef cpu_est_2_i_0_i_o2_i_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_1_2)) - )) - (net N_181_i (joined - (portRef O (instanceRef un5_e_i_i_o2)) - (portRef I0 (instanceRef un5_e_i_i_a3)) - (portRef I0 (instanceRef cpu_est_2_i_0_i_o2_3)) - )) - (net CLK_OUT_PRE_D_i (joined - (portRef O (instanceRef CLK_OUT_PRE_D_i)) - (portRef I1 (instanceRef DSACK1_INT_0_sqmuxa_i_i_o2_0)) - )) - (net N_175_0 (joined - (portRef O (instanceRef DSACK1_INT_0_sqmuxa_i_i_o2_0)) - (portRef I0 (instanceRef DSACK1_INT_0_sqmuxa_i_i_o2_0_i)) - )) - (net N_168_i (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o2_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o2_i_0)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_1_6)) - )) - (net AS_030_000_SYNC_i (joined - (portRef O (instanceRef AS_030_000_SYNC_i)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o2_1_0_0)) - )) - (net N_158_i (joined - (portRef O (instanceRef RST_DLY_e2_i_0_o2_0)) - (portRef I1 (instanceRef RST_DLY_e1_i_0_a3)) - (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_o2)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_0_i)) - )) - (net (rename CLK_000_D_i_0 "CLK_000_D_i[0]") (joined - (portRef O (instanceRef CLK_000_D_i_0)) - (portRef I1 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0)) - )) - (net N_148_i (joined - (portRef O (instanceRef pos_clk_CLK_000_N_SYNC_2_0_a4_0_o2_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_o2_1_0_0)) - (portRef D (instanceRef CLK_000_N_SYNC_0)) - )) - (net N_345_i (joined - (portRef O (instanceRef N_345_i)) - (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_2)) - )) - (net N_344_i (joined - (portRef O (instanceRef N_344_i)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_o2)) - )) - (net N_144_0 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_o2)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_i)) - )) - (net N_138_0 (joined - (portRef O (instanceRef un6_as_030_i_0)) - (portRef I0 (instanceRef un6_as_030_i_0_i)) - )) - (net N_134_i (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i)) - (portRef D (instanceRef CYCLE_DMA_1)) - )) - (net N_342_i (joined - (portRef O (instanceRef N_342_i)) - (portRef I0 (instanceRef un5_e_i_i)) - )) - (net N_343_i (joined - (portRef O (instanceRef N_343_i)) - (portRef I1 (instanceRef un5_e_i_i)) - )) - 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(portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i)) - )) - (net N_90_0 (joined - (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i)) - (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i_i)) - )) (net N_328_i (joined (portRef O (instanceRef N_328_i)) - (portRef I1 (instanceRef CLK_030_H_2_0_a2_i_1)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) )) - (net N_83_i (joined - (portRef O (instanceRef CLK_030_H_2_0_a2_i)) - (portRef D (instanceRef CLK_030_H)) - )) - (net N_80_0 (joined - (portRef O (instanceRef un14_amiga_bus_data_dir_0_a2_i)) - (portRef I0 (instanceRef un14_amiga_bus_data_dir_0_a2_i_i)) + (net (rename pos_clk_SIZE_DMA_6_0_0 "pos_clk.SIZE_DMA_6_0[0]") (joined + (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0)) + (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_i_0)) )) (net N_325_i (joined (portRef O (instanceRef N_325_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_6)) - )) - (net N_326_i (joined - (portRef O (instanceRef N_326_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_6)) - )) - (net N_258_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_i_6)) - )) - (net N_217_i (joined - (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_a2)) - (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_1_i)) - (portRef I1 (instanceRef RST_DLY_e2_i_0_a3_1_0)) - (portRef I0 (instanceRef RST_DLY_e1_i_0_a3_0_1)) - )) - (net N_321_i (joined - (portRef O (instanceRef N_321_i)) - (portRef I1 (instanceRef RST_DLY_e0_i_0_1)) - )) - (net N_322_i (joined - (portRef O (instanceRef N_322_i)) - (portRef I1 (instanceRef RST_DLY_e0_i_0)) - )) - (net N_261_i (joined - (portRef O (instanceRef RST_DLY_e0_i_0)) - (portRef D (instanceRef RST_DLY_0)) - )) - (net N_320_i (joined - (portRef O (instanceRef N_320_i)) - (portRef I0 (instanceRef RESET_OUT_2_i_0)) - )) - (net N_262_i (joined - (portRef O (instanceRef RESET_OUT_2_i_0)) - (portRef D (instanceRef RESET_OUT)) - )) - (net un5_ciin_i (joined - (portRef O (instanceRef un5_ciin_i)) - (portRef I1 (instanceRef un8_ciin_i_0_0)) - )) - (net N_61_0 (joined - (portRef O (instanceRef un8_ciin_i_0_0)) - (portRef I0 (instanceRef un8_ciin_i_0_0_i)) - )) - (net N_310_i (joined - (portRef O (instanceRef N_310_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_5)) - )) - (net N_141_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_5)) - (portRef D (instanceRef SM_AMIGA_5)) - )) - (net N_305_i (joined - (portRef O (instanceRef N_305_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1_4)) - )) - (net N_307_i (joined - (portRef O (instanceRef N_307_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_4)) - )) - (net N_139_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_4)) - (portRef D (instanceRef SM_AMIGA_4)) - )) - (net N_303_i (joined - (portRef O (instanceRef N_303_i)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_2)) - )) - (net N_304_i (joined - (portRef O (instanceRef N_304_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_2)) - )) - (net N_283_0 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_i_2)) - )) - (net N_301_i (joined - (portRef O (instanceRef N_301_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_1_1)) - )) - (net N_133_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_1)) - (portRef D (instanceRef SM_AMIGA_1)) - )) - (net N_300_i (joined - (portRef O (instanceRef N_300_i)) - (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0_1)) - )) - (net N_123_0 (joined - (portRef O (instanceRef un1_SM_AMIGA_3_i_0)) - (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0_i)) - )) - (net N_278_i (joined - (portRef O (instanceRef N_278_i)) (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0)) )) - (net N_297_i (joined - (portRef O (instanceRef N_297_i)) + (net N_327_i (joined + (portRef O (instanceRef N_327_i)) (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0)) )) (net AMIGA_BUS_DATA_DIR_c_0 (joined (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0)) (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_i)) )) - (net N_277_i (joined - (portRef O (instanceRef N_277_i)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0)) + (net N_320_i (joined + (portRef O (instanceRef N_320_i)) + (portRef I0 (instanceRef CLK_030_H_2_i_1)) )) - (net N_131_i (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0)) - (portRef D (instanceRef SM_AMIGA_0)) + (net N_106_i (joined + (portRef O (instanceRef CLK_030_H_2_i)) + (portRef D (instanceRef CLK_030_H)) )) - (net N_282_i (joined + (net N_103_i (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i)) + (portRef D (instanceRef CYCLE_DMA_1)) + )) + (net N_92_i (joined (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i)) (portRef D (instanceRef CYCLE_DMA_0)) )) - (net (rename pos_clk_un8_sm_amiga_i "pos_clk.un8_sm_amiga_i") (joined - (portRef O (instanceRef pos_clk_un8_sm_amiga)) - (portRef I0 (instanceRef LDS_000_INT_0_m)) + (net N_298_0 (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_i)) )) - (net A0_c_i (joined - (portRef O (instanceRef A0_c_i)) - (portRef I1 (instanceRef pos_clk_un8_sm_amiga_1)) + (net N_295_0 (joined + (portRef O (instanceRef un14_amiga_bus_data_dir_i_0)) + (portRef I0 (instanceRef un14_amiga_bus_data_dir_i_0_i)) )) - (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined - (portRef O (instanceRef SIZE_c_i_1)) - (portRef I0 (instanceRef pos_clk_un8_sm_amiga_1)) + (net N_294_0 (joined + (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i)) + (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_i)) )) - (net N_29_i (joined - (portRef O (instanceRef N_29_i)) - (portRef I0 (instanceRef IPL_030_1_2)) + (net N_319_i (joined + (portRef O (instanceRef N_319_i)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_0)) )) - (net N_32_0 (joined - (portRef O (instanceRef IPL_030_1_2)) - (portRef I0 (instanceRef IPL_030_1_i_2)) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0[0]") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_0)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_i_0)) )) - (net N_28_i (joined - (portRef O (instanceRef N_28_i)) - (portRef I0 (instanceRef IPL_030_1_1)) + (net N_206_i (joined + (portRef O (instanceRef N_206_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_5)) )) - (net N_31_0 (joined - (portRef O (instanceRef IPL_030_1_1)) - (portRef I0 (instanceRef IPL_030_1_i_1)) + (net N_283_i (joined + (portRef O (instanceRef N_283_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_5)) )) - (net N_27_i (joined - (portRef O (instanceRef N_27_i)) - (portRef I0 (instanceRef IPL_030_1_0)) + (net N_140_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_5)) + (portRef D (instanceRef SM_AMIGA_5)) )) - (net N_30_0 (joined - (portRef O (instanceRef IPL_030_1_0)) - (portRef I0 (instanceRef IPL_030_1_i_0)) + (net N_281_i (joined + (portRef O (instanceRef N_281_i)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) )) - (net (rename IPL_c_i_2 "IPL_c_i[2]") (joined - (portRef O (instanceRef IPL_c_i_2)) - (portRef I0 (instanceRef IPL_D0_0_2)) + (net N_282_i (joined + (portRef O (instanceRef N_282_i)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) )) - (net N_53_0 (joined - (portRef O (instanceRef IPL_D0_0_2)) - (portRef I0 (instanceRef IPL_D0_0_i_2)) - )) - (net (rename IPL_c_i_1 "IPL_c_i[1]") (joined - (portRef O (instanceRef IPL_c_i_1)) - (portRef I0 (instanceRef IPL_D0_0_1)) - )) - (net N_52_0 (joined - (portRef O (instanceRef IPL_D0_0_1)) - (portRef I0 (instanceRef IPL_D0_0_i_1)) - )) - (net (rename IPL_c_i_0 "IPL_c_i[0]") (joined - (portRef O (instanceRef IPL_c_i_0)) - (portRef I0 (instanceRef IPL_D0_0_0)) - )) - (net N_51_0 (joined - (portRef O (instanceRef IPL_D0_0_0)) - (portRef I0 (instanceRef IPL_D0_0_i_0)) - )) - (net DTACK_c_i (joined - (portRef O (instanceRef DTACK_c_i)) - (portRef I0 (instanceRef DTACK_D0_0)) - )) - (net N_56_0 (joined - (portRef O (instanceRef DTACK_D0_0)) - (portRef I0 (instanceRef DTACK_D0_0_i)) - )) - (net VPA_c_i (joined - (portRef O (instanceRef VPA_c_i)) - (portRef I1 (instanceRef VPA_D_0)) - )) - (net N_55_0 (joined - (portRef O (instanceRef VPA_D_0)) - (portRef I0 (instanceRef VPA_D_0_i)) - )) - (net nEXP_SPACE_c_i (joined - (portRef O (instanceRef nEXP_SPACE_c_i)) - (portRef I1 (instanceRef nEXP_SPACE_D0_0)) - )) - (net N_54_0 (joined - (portRef O (instanceRef nEXP_SPACE_D0_0)) - (portRef I0 (instanceRef nEXP_SPACE_D0_0_i)) + (net N_138_i (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_4)) + (portRef D (instanceRef SM_AMIGA_4)) )) (net N_3_i (joined (portRef O (instanceRef N_3_i)) @@ -3919,14 +4042,6 @@ (portRef O (instanceRef AS_000_DMA_1)) (portRef I0 (instanceRef AS_000_DMA_1_i)) )) - (net N_17_i (joined - (portRef O (instanceRef N_17_i)) - (portRef I0 (instanceRef LDS_000_INT_1)) - )) - (net N_42_0 (joined - (portRef O (instanceRef LDS_000_INT_1)) - (portRef I0 (instanceRef LDS_000_INT_1_i)) - )) (net N_19_i (joined (portRef O (instanceRef N_19_i)) (portRef I0 (instanceRef RW_000_DMA_2)) @@ -3943,21 +4058,13 @@ (portRef O (instanceRef A0_DMA_1)) (portRef I0 (instanceRef A0_DMA_1_i)) )) - (net N_21_i (joined - (portRef O (instanceRef N_21_i)) - (portRef I0 (instanceRef UDS_000_INT_1)) + (net N_24_i (joined + (portRef O (instanceRef N_24_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) )) - (net N_38_0 (joined - (portRef O (instanceRef UDS_000_INT_1)) - (portRef I0 (instanceRef UDS_000_INT_1_i)) - )) - (net N_22_i (joined - (portRef O (instanceRef N_22_i)) - (portRef I0 (instanceRef VMA_INT_1)) - )) - (net N_37_0 (joined - (portRef O (instanceRef VMA_INT_1)) - (portRef I0 (instanceRef VMA_INT_1_i)) + (net N_35_0 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i)) )) (net N_25_i (joined (portRef O (instanceRef N_25_i)) @@ -3967,305 +4074,445 @@ (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i)) )) - (net N_26_i (joined - (portRef O (instanceRef N_26_i)) - (portRef I0 (instanceRef BG_000_1)) + (net N_194_0_1 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_o2_1)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_o2)) )) - (net N_33_0 (joined - (portRef O (instanceRef BG_000_1)) - (portRef I0 (instanceRef BG_000_1_i)) - )) - (net BG_030_c_i (joined - (portRef O (instanceRef BG_030_c_i)) - (portRef I0 (instanceRef pos_clk_un9_bg_030)) - )) - (net (rename pos_clk_un6_bg_030_i "pos_clk.un6_bg_030_i") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_i)) - (portRef I1 (instanceRef pos_clk_un9_bg_030)) - )) - (net (rename pos_clk_un9_bg_030_0 "pos_clk.un9_bg_030_0") (joined - (portRef O (instanceRef pos_clk_un9_bg_030)) - (portRef I0 (instanceRef pos_clk_un9_bg_030_i)) - )) - (net N_289_0_1 (joined - (portRef O (instanceRef pos_clk_un37_as_030_d0_i_o2_1)) - (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_o2)) - )) - (net un1_SM_AMIGA_5_i_1 (joined - (portRef O (instanceRef un1_SM_AMIGA_5_0_o3_1)) - (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o3)) - )) - (net un1_SM_AMIGA_5_i_2 (joined - (portRef O (instanceRef un1_SM_AMIGA_5_0_o3_2)) - (portRef I1 (instanceRef un1_SM_AMIGA_5_0_o3)) - )) - (net (rename pos_clk_un8_sm_amiga_i_1 "pos_clk.un8_sm_amiga_i_1") (joined - (portRef O (instanceRef pos_clk_un8_sm_amiga_1)) - (portRef I0 (instanceRef pos_clk_un8_sm_amiga)) - )) - (net N_351_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_a2_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a2_2)) - )) - (net N_351_2 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_a2_2_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a2_2)) - )) - (net N_168_i_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_o2_1_0_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_o2_0)) - )) - (net N_192_0_1 (joined - (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_1)) - (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3)) - )) - (net N_192_0_2 (joined - (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3_2)) - (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_i_a4_i_o3)) - )) - (net N_137_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_3)) - )) - (net N_137_i_2 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_2_3)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_3)) - )) - (net N_145_i_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_3_0)) - )) - (net N_145_i_2 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_2_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_3_0)) - )) - (net N_145_i_3 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_3_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0)) - )) - (net N_260_i_1 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_1)) - (portRef I0 (instanceRef RST_DLY_e1_i_0)) - )) - (net N_260_i_2 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_2)) - (portRef I1 (instanceRef RST_DLY_e1_i_0)) - )) - (net N_259_i_1 (joined + (net N_237_i_1 (joined (portRef O (instanceRef RST_DLY_e2_i_0_1)) (portRef I0 (instanceRef RST_DLY_e2_i_0)) )) - (net N_259_i_2 (joined + (net N_237_i_2 (joined (portRef O (instanceRef RST_DLY_e2_i_0_2)) (portRef I1 (instanceRef RST_DLY_e2_i_0)) )) - (net N_336_1 (joined - (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0_1)) - (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0)) + (net N_238_i_1 (joined + (portRef O (instanceRef RST_DLY_e1_i_0_1)) + (portRef I0 (instanceRef RST_DLY_e1_i_0)) )) - (net N_336_2 (joined - (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0_2)) - (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0)) + (net N_238_i_2 (joined + (portRef O (instanceRef RST_DLY_e1_i_0_2)) + (portRef I1 (instanceRef RST_DLY_e1_i_0)) )) - (net N_332_1 (joined - (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_1)) - (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_3)) + (net N_144_i_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_3_0)) )) - (net N_332_2 (joined - (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_2)) - (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_3)) + (net N_144_i_2 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_2_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_3_0)) )) - (net N_332_3 (joined - (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_3)) - (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3)) + (net N_144_i_3 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_3_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_0)) )) - (net N_317_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a3_2_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a3_2_3_0)) + (net N_136_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_3)) )) - (net N_317_2 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a3_2_2_0)) - (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_a3_2_3_0)) + (net N_136_i_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_2_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_3)) )) - (net N_317_3 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a3_2_3_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a3_2_0)) + (net N_176_i_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0)) )) - (net N_304_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_a3_0_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a3_0_2)) + (net N_146_0_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_0)) )) - (net N_304_2 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_a3_0_2_2)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_a3_0_2)) + (net (rename pos_clk_un10_sm_amiga_i_1 "pos_clk.un10_sm_amiga_i_1") (joined + (portRef O (instanceRef pos_clk_un10_sm_amiga_1)) + (portRef I0 (instanceRef pos_clk_un10_sm_amiga)) )) - (net un5_ciin_1 (joined - (portRef O (instanceRef un5_ciin_0_a2_0_a3_1)) - (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_7)) + (net un10_ciin_1 (joined + (portRef O (instanceRef un10_ciin_0_a2_1)) + (portRef I0 (instanceRef un10_ciin_0_a2_7)) )) - (net un5_ciin_2 (joined - (portRef O (instanceRef un5_ciin_0_a2_0_a3_2)) - (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_7)) + (net un10_ciin_2 (joined + (portRef O (instanceRef un10_ciin_0_a2_2)) + (portRef I1 (instanceRef un10_ciin_0_a2_7)) )) - (net un5_ciin_3 (joined - (portRef O (instanceRef un5_ciin_0_a2_0_a3_3)) - (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_8)) + (net un10_ciin_3 (joined + (portRef O (instanceRef un10_ciin_0_a2_3)) + (portRef I0 (instanceRef un10_ciin_0_a2_8)) )) - (net un5_ciin_4 (joined - (portRef O (instanceRef un5_ciin_0_a2_0_a3_4)) - (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_8)) + (net un10_ciin_4 (joined + (portRef O (instanceRef un10_ciin_0_a2_4)) + (portRef I1 (instanceRef un10_ciin_0_a2_8)) )) - (net un5_ciin_5 (joined - (portRef O (instanceRef un5_ciin_0_a2_0_a3_5)) - (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_9)) + (net un10_ciin_5 (joined + (portRef O (instanceRef un10_ciin_0_a2_5)) + (portRef I0 (instanceRef un10_ciin_0_a2_9)) )) - (net un5_ciin_6 (joined - (portRef O (instanceRef un5_ciin_0_a2_0_a3_6)) - (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_9)) + (net un10_ciin_6 (joined + (portRef O (instanceRef un10_ciin_0_a2_6)) + (portRef I1 (instanceRef un10_ciin_0_a2_9)) )) - (net un5_ciin_7 (joined - (portRef O (instanceRef un5_ciin_0_a2_0_a3_7)) - (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_10)) + (net un10_ciin_7 (joined + (portRef O (instanceRef un10_ciin_0_a2_7)) + (portRef I0 (instanceRef un10_ciin_0_a2_10)) )) - (net un5_ciin_8 (joined - (portRef O (instanceRef un5_ciin_0_a2_0_a3_8)) - (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_10)) + (net un10_ciin_8 (joined + (portRef O (instanceRef un10_ciin_0_a2_8)) + (portRef I1 (instanceRef un10_ciin_0_a2_10)) )) - (net un5_ciin_9 (joined - (portRef O (instanceRef un5_ciin_0_a2_0_a3_9)) - (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_11)) + (net un10_ciin_9 (joined + (portRef O (instanceRef un10_ciin_0_a2_9)) + (portRef I0 (instanceRef un10_ciin_0_a2_11)) )) - (net un5_ciin_10 (joined - (portRef O (instanceRef un5_ciin_0_a2_0_a3_10)) - (portRef I0 (instanceRef un5_ciin_0_a2_0_a3)) + (net un10_ciin_10 (joined + (portRef O (instanceRef un10_ciin_0_a2_10)) + (portRef I0 (instanceRef un10_ciin_0_a2)) )) - (net un5_ciin_11 (joined - (portRef O (instanceRef un5_ciin_0_a2_0_a3_11)) - (portRef I1 (instanceRef un5_ciin_0_a2_0_a3)) + (net un10_ciin_11 (joined + (portRef O (instanceRef un10_ciin_0_a2_11)) + (portRef I1 (instanceRef un10_ciin_0_a2)) )) - (net un22_berr_1_0 (joined - (portRef O (instanceRef un22_berr_0_a2_0_a3_1_0)) - (portRef I0 (instanceRef un22_berr_0_a2_0_a3)) + (net N_347_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) + )) + (net N_347_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_2_3)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_2_3)) + )) + (net (rename pos_clk_un23_bgack_030_int_i_1_0_1 "pos_clk.un23_bgack_030_int_i_1_0_1") (joined + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_1)) + (portRef I0 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2)) + )) + (net (rename pos_clk_un23_bgack_030_int_i_1_0_2 "pos_clk.un23_bgack_030_int_i_1_0_2") (joined + (portRef O (instanceRef pos_clk_un23_bgack_030_int_i_0_o2_2)) + (portRef I1 (instanceRef pos_clk_un23_bgack_030_int_i_0_o2)) )) (net un21_fpu_cs_1 (joined - (portRef O (instanceRef un21_fpu_cs_0_a2_0_a3_1)) - (portRef I0 (instanceRef un21_fpu_cs_0_a2_0_a3)) + (portRef O (instanceRef un21_fpu_cs_0_a2_1_0)) + (portRef I0 (instanceRef un21_fpu_cs_0_a2)) )) - (net N_375_1 (joined - (portRef O (instanceRef un22_berr_0_a2_0_a2_1)) - (portRef I0 (instanceRef un22_berr_0_a2_0_a2_4)) + (net un22_berr_1_0 (joined + (portRef O (instanceRef un22_berr_0_a2_1)) + (portRef I0 (instanceRef un22_berr_0_a2)) )) - (net N_375_2 (joined - (portRef O (instanceRef un22_berr_0_a2_0_a2_2)) - (portRef I1 (instanceRef un22_berr_0_a2_0_a2_4)) + (net N_366_1 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_1)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_4)) )) - (net N_375_3 (joined - (portRef O (instanceRef un22_berr_0_a2_0_a2_3)) - (portRef I1 (instanceRef un22_berr_0_a2_0_a2)) + (net N_366_2 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_2)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_4)) )) - (net N_375_4 (joined - (portRef O (instanceRef un22_berr_0_a2_0_a2_4)) - (portRef I0 (instanceRef un22_berr_0_a2_0_a2)) + (net N_366_3 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_3)) + (portRef I1 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1)) )) - (net N_134_i_1 (joined - (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) - (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i)) + (net N_366_4 (joined + (portRef O (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1_4)) + (portRef I0 (instanceRef pos_clk_un37_as_030_d0_0_i_a2_1)) )) - (net N_96_0_1 (joined - (portRef O (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_1)) - (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i)) + (net un1_SM_AMIGA_5_i_1 (joined + (portRef O (instanceRef un1_SM_AMIGA_5_0_o2_2_o2_1)) + (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o2_2_o2)) )) - (net N_83_i_1 (joined - (portRef O (instanceRef CLK_030_H_2_0_a2_i_1)) - (portRef I0 (instanceRef CLK_030_H_2_0_a2_i)) + (net un1_SM_AMIGA_5_i_2 (joined + (portRef O (instanceRef un1_SM_AMIGA_5_0_o2_2_o2_2)) + (portRef I1 (instanceRef un1_SM_AMIGA_5_0_o2_2_o2)) )) - (net N_261_i_1 (joined + (net N_142_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_6)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_6)) + )) + (net N_142_i_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_2_6)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_6)) + )) + (net N_339_1 (joined + (portRef O (instanceRef RST_DLY_e0_i_0_a2_0_1)) + (portRef I0 (instanceRef RST_DLY_e0_i_0_a2_0)) + )) + (net N_280_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_2)) + )) + (net N_280_2 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_2_2)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a2_0_2)) + )) + (net N_231_1 (joined + (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0_1)) + (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0)) + )) + (net N_231_2 (joined + (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0_2)) + (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_0)) + )) + (net N_230_1 (joined + (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_1)) + (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_3)) + )) + (net N_230_2 (joined + (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_2)) + (portRef I1 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_3)) + )) + (net N_230_3 (joined + (portRef O (instanceRef pos_clk_un4_clk_000_pe_0_0_a2_3)) + (portRef I0 (instanceRef pos_clk_un4_clk_000_pe_0_0_a2)) + )) + (net N_226_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_3_0)) + )) + (net N_226_2 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_2_0)) + (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_3_0)) + )) + (net N_226_3 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_3_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_2_0)) + )) + (net N_239_i_1 (joined (portRef O (instanceRef RST_DLY_e0_i_0_1)) (portRef I0 (instanceRef RST_DLY_e0_i_0)) )) - (net N_141_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_5)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_5)) - )) - (net N_139_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_4)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_4)) - )) - (net N_133_i_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_1)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1)) - )) - (net N_123_0_1 (joined + (net N_122_0_1 (joined (portRef O (instanceRef un1_SM_AMIGA_3_i_0_1)) (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0)) )) - (net N_282_i_1 (joined + (net N_132_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_1_1)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_1)) + )) + (net N_120_0_1 (joined + (portRef O (instanceRef DS_000_DMA_2_sqmuxa_i_1)) + (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_i)) + )) + (net N_106_i_1 (joined + (portRef O (instanceRef CLK_030_H_2_i_1)) + (portRef I0 (instanceRef CLK_030_H_2_i)) + )) + (net N_103_i_1 (joined + (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_1)) + (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i)) + )) + (net N_92_i_1 (joined (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_1)) (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i)) )) - (net N_343_1 (joined - (portRef O (instanceRef un5_e_i_i_a3_0_1)) - (portRef I0 (instanceRef un5_e_i_i_a3_0)) + (net N_140_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_5)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_5)) )) - (net N_339_1 (joined - (portRef O (instanceRef cpu_est_2_0_0_a3_1_1_1)) - (portRef I0 (instanceRef cpu_est_2_0_0_a3_1_1)) + (net N_138_i_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_4)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_4)) + )) + (net N_344_1 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_0_1)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2_0)) )) (net (rename pos_clk_un6_bg_030_1 "pos_clk.un6_bg_030_1") (joined - (portRef O (instanceRef pos_clk_un6_bg_030_0_a2_0_a3_1)) - (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2_0_a3)) + (portRef O (instanceRef pos_clk_un6_bg_030_0_a2_1)) + (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2)) )) - (net N_326_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_1_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_6)) + (net N_327_1 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a2_0)) )) - (net N_325_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a3_1_6)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a3_6)) + (net N_319_1 (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_1_0)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_a2_0)) )) - (net N_324_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_1_3)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_3)) + (net N_285_1 (joined + (portRef O (instanceRef un5_e_i_i_a2_0_1)) + (portRef I0 (instanceRef un5_e_i_i_a2_0)) )) - (net N_316_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a3_1_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a3_1_0)) + (net N_277_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a2_1_2)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a2_2)) )) - (net N_313_1 (joined - (portRef O (instanceRef SM_AMIGA_nss_i_i_0_a3_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_a3_0_0)) + (net N_236_1 (joined + (portRef O (instanceRef cpu_est_2_0_0_a2_1_1_1)) + (portRef I0 (instanceRef cpu_est_2_0_0_a2_1_1)) )) - (net N_303_1 (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_i_a3_1_2)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_a3_2)) + (net N_228_1 (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1_3)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3)) )) - (net N_297_1 (joined - (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0_1)) - (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_a3_0)) + (net N_225_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_1_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_1_0)) )) - (net N_266_1 (joined - (portRef O (instanceRef RST_DLY_e1_i_0_a3_0_1)) - (portRef I0 (instanceRef RST_DLY_e1_i_0_a3_0)) + (net N_224_1 (joined + (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0_0)) )) - (net N_240_1 (joined - (portRef O (instanceRef RST_DLY_e2_i_0_a3_1_0)) - (portRef I0 (instanceRef RST_DLY_e2_i_0_a3)) + (net N_222_1 (joined + (portRef O (instanceRef RST_DLY_e1_i_0_a2_1_1)) + (portRef I0 (instanceRef RST_DLY_e1_i_0_a2_1)) + )) + (net N_215_1 (joined + (portRef O (instanceRef RST_DLY_e2_i_0_a2_1)) + (portRef I0 (instanceRef RST_DLY_e2_i_0_a2)) )) (net (rename pos_clk_ipl_1 "pos_clk.ipl_1") (joined (portRef O (instanceRef G_137_1)) (portRef I0 (instanceRef G_137)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un3 "AMIGA_BUS_ENABLE_DMA_LOW_0.un3") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) + (net (rename BG_000_0_un3 "BG_000_0.un3") (joined + (portRef O (instanceRef BG_000_0_r)) + (portRef I1 (instanceRef BG_000_0_n)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un1 "AMIGA_BUS_ENABLE_DMA_LOW_0.un1") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + (net (rename BG_000_0_un1 "BG_000_0.un1") (joined + (portRef O (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_p)) )) - (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un0 "AMIGA_BUS_ENABLE_DMA_LOW_0.un0") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) + (net (rename BG_000_0_un0 "BG_000_0.un0") (joined + (portRef O (instanceRef BG_000_0_n)) + (portRef I1 (instanceRef BG_000_0_p)) + )) + (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined + (portRef O (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef UDS_000_INT_0_n)) + )) + (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined + (portRef O (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined + (portRef O (instanceRef UDS_000_INT_0_n)) + (portRef I1 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined + (portRef O (instanceRef LDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_n)) + )) + (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined + (portRef O (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_p)) + )) + (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined + (portRef O (instanceRef LDS_000_INT_0_n)) + (portRef I1 (instanceRef LDS_000_INT_0_p)) + )) + (net (rename DSACK1_INT_0_un3 "DSACK1_INT_0.un3") (joined + (portRef O (instanceRef DSACK1_INT_0_r)) + (portRef I1 (instanceRef DSACK1_INT_0_n)) + )) + (net (rename DSACK1_INT_0_un1 "DSACK1_INT_0.un1") (joined + (portRef O (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_0_p)) + )) + (net (rename DSACK1_INT_0_un0 "DSACK1_INT_0.un0") (joined + (portRef O (instanceRef DSACK1_INT_0_n)) + (portRef I1 (instanceRef DSACK1_INT_0_p)) + )) + (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined + (portRef O (instanceRef IPL_030_0_2__r)) + (portRef I1 (instanceRef IPL_030_0_2__n)) + )) + (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined + (portRef O (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__p)) + )) + (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined + (portRef O (instanceRef IPL_030_0_2__n)) + (portRef I1 (instanceRef IPL_030_0_2__p)) + )) + (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined + (portRef O (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_1__n)) + )) + (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined + (portRef O (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__p)) + )) + (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined + (portRef O (instanceRef IPL_030_0_1__n)) + (portRef I1 (instanceRef IPL_030_0_1__p)) + )) + (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined + (portRef O (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef IPL_030_0_0__n)) + )) + (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined + (portRef O (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__p)) + )) + (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined + (portRef O (instanceRef IPL_030_0_0__n)) + (portRef I1 (instanceRef IPL_030_0_0__p)) + )) + (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined + (portRef O (instanceRef cpu_est_0_3__r)) + (portRef I1 (instanceRef cpu_est_0_3__n)) + )) + (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined + (portRef O (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_0_3__p)) + )) + (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined + (portRef O (instanceRef cpu_est_0_3__n)) + (portRef I1 (instanceRef cpu_est_0_3__p)) + )) + (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined + (portRef O (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_2__n)) + )) + (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined + (portRef O (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__p)) + )) + (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined + (portRef O (instanceRef cpu_est_0_2__n)) + (portRef I1 (instanceRef cpu_est_0_2__p)) + )) + (net (rename SM_AMIGA_srsts_i_0_m2_1__un3 "SM_AMIGA_srsts_i_0_m2_1_.un3") (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__r)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) + )) + (net (rename SM_AMIGA_srsts_i_0_m2_1__un1 "SM_AMIGA_srsts_i_0_m2_1_.un1") (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__m)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__p)) + )) + (net (rename SM_AMIGA_srsts_i_0_m2_1__un0 "SM_AMIGA_srsts_i_0_m2_1_.un0") (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_1__p)) + )) + (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined + (portRef O (instanceRef VMA_INT_0_r)) + (portRef I1 (instanceRef VMA_INT_0_n)) + )) + (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined + (portRef O (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_p)) + )) + (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined + (portRef O (instanceRef VMA_INT_0_n)) + (portRef I1 (instanceRef VMA_INT_0_p)) + )) + (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined + (portRef O (instanceRef cpu_est_0_1__r)) + (portRef I1 (instanceRef cpu_est_0_1__n)) + )) + (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined + (portRef O (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__p)) + )) + (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined + (portRef O (instanceRef cpu_est_0_1__n)) + (portRef I1 (instanceRef cpu_est_0_1__p)) + )) + (net (rename SM_AMIGA_srsts_i_0_0_m2_5__un3 "SM_AMIGA_srsts_i_0_0_m2_5_.un3") (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__r)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__n)) + )) + (net (rename SM_AMIGA_srsts_i_0_0_m2_5__un1 "SM_AMIGA_srsts_i_0_0_m2_5_.un1") (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__m)) + (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__p)) + )) + (net (rename SM_AMIGA_srsts_i_0_0_m2_5__un0 "SM_AMIGA_srsts_i_0_0_m2_5_.un0") (joined + (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__n)) + (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_m2_5__p)) )) (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined (portRef O (instanceRef RW_000_INT_0_r)) @@ -4291,17 +4538,17 @@ (portRef O (instanceRef BGACK_030_INT_0_n)) (portRef I1 (instanceRef BGACK_030_INT_0_p)) )) - (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_r)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) + (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined + (portRef O (instanceRef AS_000_INT_0_r)) + (portRef I1 (instanceRef AS_000_INT_0_n)) )) - (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) + (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined + (portRef O (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_p)) )) - (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_n)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) + (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined + (portRef O (instanceRef AS_000_INT_0_n)) + (portRef I1 (instanceRef AS_000_INT_0_p)) )) (net (rename DS_000_ENABLE_0_un3 "DS_000_ENABLE_0.un3") (joined (portRef O (instanceRef DS_000_ENABLE_0_r)) @@ -4315,197 +4562,41 @@ (portRef O (instanceRef DS_000_ENABLE_0_n)) (portRef I1 (instanceRef DS_000_ENABLE_0_p)) )) - (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined - (portRef O (instanceRef AS_000_INT_0_r)) - (portRef I1 (instanceRef AS_000_INT_0_n)) + (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_r)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) )) - (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined - (portRef O (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_p)) + (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) )) - (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined - (portRef O (instanceRef AS_000_INT_0_n)) - (portRef I1 (instanceRef AS_000_INT_0_p)) + (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_n)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) )) - (net (rename DSACK1_INT_0_un3 "DSACK1_INT_0.un3") (joined - (portRef O (instanceRef DSACK1_INT_0_r)) - (portRef I1 (instanceRef DSACK1_INT_0_n)) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__un3 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un3") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__r)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__n)) )) - (net (rename DSACK1_INT_0_un1 "DSACK1_INT_0.un1") (joined - (portRef O (instanceRef DSACK1_INT_0_m)) - (portRef I0 (instanceRef DSACK1_INT_0_p)) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__un1 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un1") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__m)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__p)) )) - (net (rename DSACK1_INT_0_un0 "DSACK1_INT_0.un0") (joined - (portRef O (instanceRef DSACK1_INT_0_n)) - (portRef I1 (instanceRef DSACK1_INT_0_p)) + (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__un0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0_.un0") (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__n)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_0_m2_0__p)) )) - (net (rename SIZE_DMA_0_1__un3 "SIZE_DMA_0_1_.un3") (joined - (portRef O (instanceRef SIZE_DMA_0_1__r)) - (portRef I1 (instanceRef SIZE_DMA_0_1__n)) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un3 "AMIGA_BUS_ENABLE_DMA_LOW_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) )) - (net (rename SIZE_DMA_0_1__un1 "SIZE_DMA_0_1_.un1") (joined - (portRef O (instanceRef SIZE_DMA_0_1__m)) - (portRef I0 (instanceRef SIZE_DMA_0_1__p)) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un1 "AMIGA_BUS_ENABLE_DMA_LOW_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) )) - (net (rename SIZE_DMA_0_1__un0 "SIZE_DMA_0_1_.un0") (joined - (portRef O (instanceRef SIZE_DMA_0_1__n)) - (portRef I1 (instanceRef SIZE_DMA_0_1__p)) - )) - (net (rename SIZE_DMA_0_0__un3 "SIZE_DMA_0_0_.un3") (joined - (portRef O (instanceRef SIZE_DMA_0_0__r)) - (portRef I1 (instanceRef SIZE_DMA_0_0__n)) - )) - (net (rename SIZE_DMA_0_0__un1 "SIZE_DMA_0_0_.un1") (joined - (portRef O (instanceRef SIZE_DMA_0_0__m)) - (portRef I0 (instanceRef SIZE_DMA_0_0__p)) - )) - (net (rename SIZE_DMA_0_0__un0 "SIZE_DMA_0_0_.un0") (joined - (portRef O (instanceRef SIZE_DMA_0_0__n)) - (portRef I1 (instanceRef SIZE_DMA_0_0__p)) - )) - (net (rename SM_AMIGA_srsts_i_0_m2_1__un3 "SM_AMIGA_srsts_i_0_m2_1_.un3") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__r)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) - )) - (net (rename SM_AMIGA_srsts_i_0_m2_1__un1 "SM_AMIGA_srsts_i_0_m2_1_.un1") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__m)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_1__p)) - )) - (net (rename SM_AMIGA_srsts_i_0_m2_1__un0 "SM_AMIGA_srsts_i_0_m2_1_.un0") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_1__n)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_1__p)) - )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un3 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un3") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__r)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) - )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un1 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un1") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__m)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p)) - )) - (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__un0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_.un0") (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__n)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0__p)) - )) - (net (rename SM_AMIGA_srsts_i_0_m2_5__un3 "SM_AMIGA_srsts_i_0_m2_5_.un3") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_5__r)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_5__n)) - )) - (net (rename SM_AMIGA_srsts_i_0_m2_5__un1 "SM_AMIGA_srsts_i_0_m2_5_.un1") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_5__m)) - (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_m2_5__p)) - )) - (net (rename SM_AMIGA_srsts_i_0_m2_5__un0 "SM_AMIGA_srsts_i_0_m2_5_.un0") (joined - (portRef O (instanceRef SM_AMIGA_srsts_i_0_m2_5__n)) - (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_m2_5__p)) - )) - (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined - (portRef O (instanceRef cpu_est_0_1__r)) - (portRef I1 (instanceRef cpu_est_0_1__n)) - )) - (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined - (portRef O (instanceRef cpu_est_0_1__m)) - (portRef I0 (instanceRef cpu_est_0_1__p)) - )) - (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined - (portRef O (instanceRef cpu_est_0_1__n)) - (portRef I1 (instanceRef cpu_est_0_1__p)) - )) - (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined - (portRef O (instanceRef cpu_est_0_2__r)) - (portRef I1 (instanceRef cpu_est_0_2__n)) - )) - (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined - (portRef O (instanceRef cpu_est_0_2__m)) - (portRef I0 (instanceRef cpu_est_0_2__p)) - )) - (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined - (portRef O (instanceRef cpu_est_0_2__n)) - (portRef I1 (instanceRef cpu_est_0_2__p)) - )) - (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined - (portRef O (instanceRef cpu_est_0_3__r)) - (portRef I1 (instanceRef cpu_est_0_3__n)) - )) - (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined - (portRef O (instanceRef cpu_est_0_3__m)) - (portRef I0 (instanceRef cpu_est_0_3__p)) - )) - (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined - (portRef O (instanceRef cpu_est_0_3__n)) - (portRef I1 (instanceRef cpu_est_0_3__p)) - )) - (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined - (portRef O (instanceRef IPL_030_0_0__r)) - (portRef I1 (instanceRef IPL_030_0_0__n)) - )) - (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined - (portRef O (instanceRef IPL_030_0_0__m)) - (portRef I0 (instanceRef IPL_030_0_0__p)) - )) - (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined - (portRef O (instanceRef IPL_030_0_0__n)) - (portRef I1 (instanceRef IPL_030_0_0__p)) - )) - (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined - (portRef O (instanceRef IPL_030_0_1__r)) - (portRef I1 (instanceRef IPL_030_0_1__n)) - )) - (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined - (portRef O (instanceRef IPL_030_0_1__m)) - (portRef I0 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined - (portRef O (instanceRef IPL_030_0_1__n)) - (portRef I1 (instanceRef IPL_030_0_1__p)) - )) - (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined - (portRef O (instanceRef IPL_030_0_2__r)) - (portRef I1 (instanceRef IPL_030_0_2__n)) - )) - (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined - (portRef O (instanceRef IPL_030_0_2__m)) - (portRef I0 (instanceRef IPL_030_0_2__p)) - )) - (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined - (portRef O (instanceRef IPL_030_0_2__n)) - (portRef I1 (instanceRef IPL_030_0_2__p)) - )) - (net (rename A0_DMA_0_un3 "A0_DMA_0.un3") (joined - (portRef O (instanceRef A0_DMA_0_r)) - (portRef I1 (instanceRef A0_DMA_0_n)) - )) - (net (rename A0_DMA_0_un1 "A0_DMA_0.un1") (joined - (portRef O (instanceRef A0_DMA_0_m)) - (portRef I0 (instanceRef A0_DMA_0_p)) - )) - (net (rename A0_DMA_0_un0 "A0_DMA_0.un0") (joined - (portRef O (instanceRef A0_DMA_0_n)) - (portRef I1 (instanceRef A0_DMA_0_p)) - )) - (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined - (portRef O (instanceRef UDS_000_INT_0_r)) - (portRef I1 (instanceRef UDS_000_INT_0_n)) - )) - (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined - (portRef O (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined - (portRef O (instanceRef UDS_000_INT_0_n)) - (portRef I1 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined - (portRef O (instanceRef VMA_INT_0_r)) - (portRef I1 (instanceRef VMA_INT_0_n)) - )) - (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined - (portRef O (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_p)) - )) - (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined - (portRef O (instanceRef VMA_INT_0_n)) - (portRef I1 (instanceRef VMA_INT_0_p)) + (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un0 "AMIGA_BUS_ENABLE_DMA_LOW_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p)) )) (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un3 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un3") (joined (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r)) @@ -4519,17 +4610,29 @@ (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n)) (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p)) )) - (net (rename BG_000_0_un3 "BG_000_0.un3") (joined - (portRef O (instanceRef BG_000_0_r)) - (portRef I1 (instanceRef BG_000_0_n)) + (net (rename SIZE_DMA_0_0__un3 "SIZE_DMA_0_0_.un3") (joined + (portRef O (instanceRef SIZE_DMA_0_0__r)) + (portRef I1 (instanceRef SIZE_DMA_0_0__n)) )) - (net (rename BG_000_0_un1 "BG_000_0.un1") (joined - (portRef O (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_p)) + (net (rename SIZE_DMA_0_0__un1 "SIZE_DMA_0_0_.un1") (joined + (portRef O (instanceRef SIZE_DMA_0_0__m)) + (portRef I0 (instanceRef SIZE_DMA_0_0__p)) )) - (net (rename BG_000_0_un0 "BG_000_0.un0") (joined - (portRef O (instanceRef BG_000_0_n)) - (portRef I1 (instanceRef BG_000_0_p)) + (net (rename SIZE_DMA_0_0__un0 "SIZE_DMA_0_0_.un0") (joined + (portRef O (instanceRef SIZE_DMA_0_0__n)) + (portRef I1 (instanceRef SIZE_DMA_0_0__p)) + )) + (net (rename SIZE_DMA_0_1__un3 "SIZE_DMA_0_1_.un3") (joined + (portRef O (instanceRef SIZE_DMA_0_1__r)) + (portRef I1 (instanceRef SIZE_DMA_0_1__n)) + )) + (net (rename SIZE_DMA_0_1__un1 "SIZE_DMA_0_1_.un1") (joined + (portRef O (instanceRef SIZE_DMA_0_1__m)) + (portRef I0 (instanceRef SIZE_DMA_0_1__p)) + )) + (net (rename SIZE_DMA_0_1__un0 "SIZE_DMA_0_1_.un0") (joined + (portRef O (instanceRef SIZE_DMA_0_1__n)) + (portRef I1 (instanceRef SIZE_DMA_0_1__p)) )) (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined (portRef O (instanceRef DS_000_DMA_0_r)) @@ -4555,18 +4658,6 @@ (portRef O (instanceRef AS_000_DMA_0_n)) (portRef I1 (instanceRef AS_000_DMA_0_p)) )) - (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined - (portRef O (instanceRef LDS_000_INT_0_r)) - (portRef I1 (instanceRef LDS_000_INT_0_n)) - )) - (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined - (portRef O (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_p)) - )) - (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined - (portRef O (instanceRef LDS_000_INT_0_n)) - (portRef I1 (instanceRef LDS_000_INT_0_p)) - )) (net (rename RW_000_DMA_0_un3 "RW_000_DMA_0.un3") (joined (portRef O (instanceRef RW_000_DMA_0_r)) (portRef I1 (instanceRef RW_000_DMA_0_n)) @@ -4579,6 +4670,18 @@ (portRef O (instanceRef RW_000_DMA_0_n)) (portRef I1 (instanceRef RW_000_DMA_0_p)) )) + (net (rename A0_DMA_0_un3 "A0_DMA_0.un3") (joined + (portRef O (instanceRef A0_DMA_0_r)) + (portRef I1 (instanceRef A0_DMA_0_n)) + )) + (net (rename A0_DMA_0_un1 "A0_DMA_0.un1") (joined + (portRef O (instanceRef A0_DMA_0_m)) + (portRef I0 (instanceRef A0_DMA_0_p)) + )) + (net (rename A0_DMA_0_un0 "A0_DMA_0.un0") (joined + (portRef O (instanceRef A0_DMA_0_n)) + (portRef I1 (instanceRef A0_DMA_0_p)) + )) ) (property orig_inst_of (string "BUS68030")) ) diff --git a/Logic/BUS68030.fse b/Logic/BUS68030.fse index b89de70..b871b07 100644 --- a/Logic/BUS68030.fse +++ b/Logic/BUS68030.fse @@ -1,20 +1,20 @@ -fsm_encoding {7134371341} onehot +fsm_encoding {7139371391} onehot -fsm_state_encoding {7134371341} idle_p {00000000} +fsm_state_encoding {7139371391} idle_p {00000000} -fsm_state_encoding {7134371341} idle_n {00000011} +fsm_state_encoding {7139371391} idle_n {00000011} -fsm_state_encoding {7134371341} as_set_p {00000101} +fsm_state_encoding {7139371391} as_set_p {00000101} -fsm_state_encoding {7134371341} as_set_n {00001001} +fsm_state_encoding {7139371391} as_set_n {00001001} -fsm_state_encoding {7134371341} sample_dtack_p {00010001} +fsm_state_encoding {7139371391} sample_dtack_p {00010001} -fsm_state_encoding {7134371341} data_fetch_n {00100001} +fsm_state_encoding {7139371391} data_fetch_n {00100001} -fsm_state_encoding {7134371341} data_fetch_p {01000001} +fsm_state_encoding {7139371391} data_fetch_p {01000001} -fsm_state_encoding {7134371341} end_cycle_n {10000001} +fsm_state_encoding {7139371391} end_cycle_n {10000001} -fsm_registers {7134371341} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]} +fsm_registers {7139371391} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA_i[7]} diff --git a/Logic/BUS68030.naf b/Logic/BUS68030.naf index 24daa01..292766a 100644 --- a/Logic/BUS68030.naf +++ b/Logic/BUS68030.naf @@ -6,38 +6,38 @@ UDS_000 b LDS_000 b SIZE[1] b SIZE[0] b -A[31] i -A[30] i -A[29] i -A[28] i -A[27] i -A[26] i -A[25] i -A[24] i -A[23] i -A[22] i -A[21] i -A[20] i -A[19] i -A[18] i -A[17] i -A[16] i -A[15] i -A[14] i -A[13] i -A[12] i -A[11] i -A[10] i -A[9] i -A[8] i -A[7] i -A[6] i -A[5] i -A[4] i -A[3] i -A[2] i -A0 b -A1 i +AHIGH[31] b +AHIGH[30] b +AHIGH[29] b +AHIGH[28] b +AHIGH[27] b +AHIGH[26] b +AHIGH[25] b +AHIGH[24] b +A_DECODE[23] i +A_DECODE[22] i +A_DECODE[21] i +A_DECODE[20] i +A_DECODE[19] i +A_DECODE[18] i +A_DECODE[17] i +A_DECODE[16] i +A_DECODE[15] i +A_DECODE[14] i +A_DECODE[13] i +A_DECODE[12] i +A_DECODE[11] i +A_DECODE[10] i +A_DECODE[9] i +A_DECODE[8] i +A_DECODE[7] i +A_DECODE[6] i +A_DECODE[5] i +A_DECODE[4] i +A_DECODE[3] i +A_DECODE[2] i +A[1] b +A[0] b nEXP_SPACE i BERR b BG_030 i diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index d8c8daa..e3c6872 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj -#-- Written on Wed Aug 17 17:45:34 2016 +#-- Written on Fri Aug 19 00:20:27 2016 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index 36e5e5d..fca5b83 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -202,8 +202,8 @@ PVR3D_FIDbFF#s_LFM CR j;}N; P$R#M#_HlCHG8MDNo;R4 RNP3M#$_#lV_FoskHb_8;Rj -RNP3M#$_lMkOsEN#nRU. -U;N3PR#_$MD HMC8sHRn"{c(dU7-7UdqBq-.cwqn-Uq(4-w4AUc(4nn}dU"N; +RNP3M#$_lMkOsEN#(RU( +.;N3PR#_$MD HMC8sHRc"{gggjU-A.dBBc-6cA6j-g(7 -.qnqn.Bcn} ("N; POR38#L_NRPC{P NRM#$_VsCCMsCOOC_D FORN{ P$R1#l0CRN{ @@ -248,422 +248,341 @@ NR83CHsVNsMN$NRlC'x#HC bQR1Zj r9N; b$R#MF_bsD0VNRo#Uo; bQR1Z4 r9N; +b$R#MF_bsD0VNRo#UL; +R(@@::.d4d:.:q6:]]Qtr:d4.Rc9qt]Q]4rd:9.cRQq]td]r4c:.9N; +HsR30FD_sMHoNRlC"Qq]t;]" +RNH3HC8VsNsNN$Ml'CRNoEHE +';N#HR$0M_s0H#NR0C4o; +b]RqQrt].;c9 +RNb#_$Mb0FsVoDN#;RU +Robqt]Q]6r.9N; +b$R#MF_bsD0VNRo#Uo; +b]RqQrt].;n9 +RNb#_$Mb0FsVoDN#;RU +Robqt]Q](r.9N; +b$R#MF_bsD0VNRo#Uo; +b]RqQrt].;U9 +RNb#_$Mb0FsVoDN#;RU +Robqt]Q]gr.9N; +b$R#MF_bsD0VNRo#Uo; +b]RqQrt]d;j9 +RNb#_$Mb0FsVoDN#;RU +Robqt]Q]4rd9N; b$R#MF_bsD0VNRo#UH; -R(@@::.d4d:.:q4:r:d4.q9Rr:d4.q9Rr:d4. -9;N3HRs_0DFosHMCNlR""q;H -NR83CHsVNsMN$NRlC';N' -@LR@.(:c::4..c::Rqjq -j;N3HRs_0DFosHMCNlRj"q"N; -H$R#Ms_0HN#004CR;b -oR;qj -RNb#_$Mb0FsVoDN#;RU -@HR@.(:6::4..6::Rq4q -4;N3HRs_0DFosHMCNlR4"q"H; -R(@@::.n4n:.::4jMu X_q1uBM R _Xu1Buq N; -HsR30FD_sMHoNRlC"XM uu_1q"B ;R -L@:@(.4(:::.(c :A)A)R ;)) -RNH3Ds0_HFsolMNCAR" "));H -NRM#$_H0s#00NC;R4 -RobA) );b -NRM#$_sbF0NVDoU#R;R -H@:@(.4U:::.Unt:A_jjdR_Atj;dj -RNH3Ds0_HFsolMNCAR"td_jj -";F@R@(g:.:.4:g::nAjt_jAjRtj_jjN; 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b/Logic/BUS68030.srr @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Wed Aug 17 17:45:41 2016 +#Fri Aug 19 00:20:34 2016 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014 @N|Running in 64-bit mode @@ -18,20 +18,17 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - VHDL syntax check successful! File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":65:10:65:11|Using sequential encoding for type sm_e -@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000 -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven +@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":71:10:71:11|Using sequential encoding for type sm_e +@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":88:14:88:15|Using sequential encoding for type sm_68000 +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register DS_030_D0_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register AMIGA_BUS_ENABLE_INT_5 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":151:2:151:3|Pruning register CLK_030_D0_2 -@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:61:130:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... -@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:55:129:64|Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... -@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:38:127:40|Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ... -@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ... -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register DS_030_D0_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register nEXP_SPACE_D0_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":163:2:163:3|Pruning register CLK_030_D0_2 +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ... +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -42,14 +39,14 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register cpu_est -@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est +@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused @END -At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB) +At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Aug 17 17:45:41 2016 +# Fri Aug 19 00:20:34 2016 ###########################################################] Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014 @@ -59,7 +56,7 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Aug 17 17:45:43 2016 +# Fri Aug 19 00:20:35 2016 ###########################################################] Map & Optimize Report @@ -68,7 +65,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2014.03LC @N: MF248 |Running in 64-bit mode. -@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0] +@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0] Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral)) original code -> new code 000 -> 00000000 @@ -83,13 +80,13 @@ original code -> new code Resource Usage Report Simple gate primitives: -DFF 78 uses -BI_DIR 10 uses +DFF 88 uses +BI_DIR 18 uses BUFTH 4 uses -IBUF 46 uses +IBUF 38 uses OBUF 15 uses -AND2 299 uses -INV 261 uses +AND2 301 uses +INV 262 uses OR2 27 uses XOR2 7 uses @@ -101,6 +98,6 @@ Mapper successful! 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z+1bfhkBCXpWcEBRN!_ddu9JTb$?Ys|tM*h%2yQ$d|_GqcPCluJnavQ4GaZjjTJ7rI(t6Rqvnf3(zdaAJc`*m}1=4mW! zj##&L=Bdh8MQX4shG!J7kvff&`)qXlO7J10H~su&lne3P{YgHYo78k1J zmH*jPc*@|L?b{CZ;g);?HMgkKZ~&Es`XUD6G>b$y;~~2jCeB>wixAh!(P3&PrP-nmTi!> zhErnv$7@%eH-a>-ZQ-~) zvt`Lx{sA(ZWjdg32$I9Hbxi new code + 000 -> 00000000 + 001 -> 00000011 + 010 -> 00000101 + 011 -> 00001001 + 100 -> 00010001 + 101 -> 00100001 + 110 -> 01000001 + 111 -> 10000001 +--------------------------------------- +Resource Usage Report + +Simple gate primitives: +DFF 88 uses +BI_DIR 18 uses +BUFTH 4 uses +IBUF 38 uses +OBUF 15 uses +AND2 301 uses +INV 262 uses +OR2 27 uses +XOR2 7 uses + + +@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. +I-2014.03LC +Mapper successful! + +At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) + +Process took 0h:00m:01s realtime, 0h:00m:01s cputime +# Fri Aug 19 00:20:36 2016 ###########################################################] diff --git a/Logic/run_options.txt b/Logic/run_options.txt index e0d2e03..2808a7b 100644 --- a/Logic/run_options.txt +++ b/Logic/run_options.txt @@ -1,7 +1,7 @@ #-- Synopsys, Inc. #-- Version I-2014.03LC #-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt -#-- Written on Wed Aug 17 17:45:41 2016 +#-- Written on Fri Aug 19 00:20:34 2016 #project files diff --git a/Logic/synlog/BUS68030_multi_srs_gen.srr b/Logic/synlog/BUS68030_multi_srs_gen.srr index 4b424a7..2d21907 100644 --- a/Logic/synlog/BUS68030_multi_srs_gen.srr +++ b/Logic/synlog/BUS68030_multi_srs_gen.srr @@ -5,6 +5,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Aug 17 17:45:43 2016 +# Fri Aug 19 00:20:35 2016 ###########################################################] diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr index 9b74b68..f1af172 100644 --- a/Logic/synlog/bus68030_fpga_mapper.srr +++ b/Logic/synlog/bus68030_fpga_mapper.srr @@ -2,7 +2,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May 6 2014 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited. Product Version I-2014.03LC @N: MF248 |Running in 64-bit mode. -@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0] +@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0] Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral)) original code -> new code 000 -> 00000000 @@ -17,13 +17,13 @@ original code -> new code Resource Usage Report Simple gate primitives: -DFF 78 uses -BI_DIR 10 uses +DFF 88 uses +BI_DIR 18 uses BUFTH 4 uses -IBUF 46 uses +IBUF 38 uses OBUF 15 uses -AND2 299 uses -INV 261 uses +AND2 301 uses +INV 262 uses OR2 27 uses XOR2 7 uses @@ -35,6 +35,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Wed Aug 17 17:45:43 2016 +# Fri Aug 19 00:20:36 2016 ###########################################################] diff --git a/Logic/synlog/report/BUS68030_compiler_errors.txt b/Logic/synlog/report/BUS68030_compiler_errors.txt index 90d992b..8fc355f 100644 --- a/Logic/synlog/report/BUS68030_compiler_errors.txt +++ b/Logic/synlog/report/BUS68030_compiler_errors.txt @@ -1,3 +1,3 @@ -@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":380:22:380:22|No identifier "clk_000_ne_d" in scope +@E: CD415 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":406:49:406:49|Expecting keyword then @E|Parse errors encountered - exiting diff --git a/Logic/synlog/report/BUS68030_compiler_notes.txt b/Logic/synlog/report/BUS68030_compiler_notes.txt index cc211d4..1020aa7 100644 --- a/Logic/synlog/report/BUS68030_compiler_notes.txt +++ b/Logic/synlog/report/BUS68030_compiler_notes.txt @@ -2,8 +2,8 @@ @N: CD720 :"E:\ispLEVER_Classic2_0\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030. @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":65:10:65:11|Using sequential encoding for type sm_e -@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000 -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register SM_AMIGA -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Trying to extract state machine for register cpu_est +@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":71:10:71:11|Using sequential encoding for type sm_e +@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":88:14:88:15|Using sequential encoding for type sm_68000 +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml index ed7ba33..90baef6 100644 --- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml +++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml @@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt - 11 + 8 C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt @@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t - - 1471448741 + 1471558834 \ No newline at end of file diff --git a/Logic/synlog/report/BUS68030_compiler_warnings.txt b/Logic/synlog/report/BUS68030_compiler_warnings.txt index e71ab26..af8fe07 100644 --- a/Logic/synlog/report/BUS68030_compiler_warnings.txt +++ b/Logic/synlog/report/BUS68030_compiler_warnings.txt @@ -1,12 +1,9 @@ -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register DS_030_D0_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Pruning register AMIGA_BUS_ENABLE_INT_5 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:34:126:36|Pruning register CLK_OUT_EXP_INT_1 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":122:36:122:38|Pruning register CLK_OUT_PRE_25_3 -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":151:2:151:3|Pruning register CLK_030_D0_2 -@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:61:130:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... -@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:55:129:64|Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... -@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:38:127:40|Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ... -@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:37:134:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ... -@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused +@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":129:7:129:17|Signal clk_out_pre is undriven +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register DS_030_D0_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register nEXP_SPACE_D0_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_OUT_EXP_INT_1 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:36:127:38|Pruning register CLK_OUT_PRE_25_3 +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":163:2:163:3|Pruning register CLK_030_D0_2 +@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ... +@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":24:1:24:8|Input port bits 15 to 2 of a_decode(23 downto 2) are unused diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml index 6a75afc..b060c55 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml +++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml @@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the 105MB -1471448743 +1471558836 diff --git a/Logic/syntmp/BUS68030_srr.htm b/Logic/syntmp/BUS68030_srr.htm index 418d023..3760611 100644 --- a/Logic/syntmp/BUS68030_srr.htm +++ b/Logic/syntmp/BUS68030_srr.htm @@ -1,5 +1,5 @@ 
-
+
 #Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
 #install: E:\ispLEVER_Classic2_0\synpbase
 #OS: Windows 7 6.2
@@ -8,32 +8,29 @@
 #Implementation: logic
 
 $ Start of Compile
-#Wed Aug 17 17:45:41 2016
+#Fri Aug 19 00:20:34 2016
 
 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
-@N: :  | Running in 64-bit mode 
+@N: :  | Running in 64-bit mode 
 Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
 
-@N:CD720 : std.vhd(123) | Setting time resolution to ns
-@N: : 68030-68000-bus.vhd(13) | Top entity is set to BUS68030.
+@N:CD720 : std.vhd(123) | Setting time resolution to ns
+@N: : 68030-68000-bus.vhd(13) | Top entity is set to BUS68030.
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
 VHDL syntax check successful!
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
-@N:CD630 : 68030-68000-bus.vhd(13) | Synthesizing work.bus68030.behavioral 
-@N:CD233 : 68030-68000-bus.vhd(65) | Using sequential encoding for type sm_e
-@N:CD233 : 68030-68000-bus.vhd(82) | Using sequential encoding for type sm_68000
-@W:CD638 : 68030-68000-bus.vhd(124) | Signal clk_out_pre is undriven 
+@N:CD630 : 68030-68000-bus.vhd(13) | Synthesizing work.bus68030.behavioral 
+@N:CD233 : 68030-68000-bus.vhd(71) | Using sequential encoding for type sm_e
+@N:CD233 : 68030-68000-bus.vhd(88) | Using sequential encoding for type sm_68000
+@W:CD638 : 68030-68000-bus.vhd(129) | Signal clk_out_pre is undriven 
 Post processing for work.bus68030.behavioral
-@W:CL169 : 68030-68000-bus.vhd(134) | Pruning register DS_030_D0_3  
-@W:CL169 : 68030-68000-bus.vhd(134) | Pruning register AMIGA_BUS_ENABLE_INT_5  
-@W:CL169 : 68030-68000-bus.vhd(126) | Pruning register CLK_OUT_EXP_INT_1  
-@W:CL169 : 68030-68000-bus.vhd(122) | Pruning register CLK_OUT_PRE_25_3  
-@W:CL169 : 68030-68000-bus.vhd(151) | Pruning register CLK_030_D0_2  
-@W:CL265 : 68030-68000-bus.vhd(130) | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
-@W:CL271 : 68030-68000-bus.vhd(129) | Pruning bits 12 to 10 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
-@W:CL271 : 68030-68000-bus.vhd(127) | Pruning bits 7 to 2 of CLK_000_D_3(7 downto 0) -- not in use ... 
-@W:CL189 : 68030-68000-bus.vhd(134) | Register bit BGACK_030_INT_PRE is always 1, optimizing ...
-@N:CL201 : 68030-68000-bus.vhd(134) | Trying to extract state machine for register SM_AMIGA
+@W:CL169 : 68030-68000-bus.vhd(139) | Pruning register DS_030_D0_3  
+@W:CL169 : 68030-68000-bus.vhd(139) | Pruning register nEXP_SPACE_D0_3  
+@W:CL169 : 68030-68000-bus.vhd(131) | Pruning register CLK_OUT_EXP_INT_1  
+@W:CL169 : 68030-68000-bus.vhd(127) | Pruning register CLK_OUT_PRE_25_3  
+@W:CL169 : 68030-68000-bus.vhd(163) | Pruning register CLK_030_D0_2  
+@W:CL189 : 68030-68000-bus.vhd(139) | Register bit BGACK_030_INT_PRE is always 1, optimizing ...
+@N:CL201 : 68030-68000-bus.vhd(139) | Trying to extract state machine for register SM_AMIGA
 Extracted state machine for register SM_AMIGA
 State machine has 8 reachable states with original encodings of:
    000
@@ -44,24 +41,24 @@ State machine has 8 reachable states with original encodings of:
    101
    110
    111
-@N:CL201 : 68030-68000-bus.vhd(134) | Trying to extract state machine for register cpu_est
-@W:CL246 : 68030-68000-bus.vhd(23) | Input port bits 15 to 2 of a(31 downto 2) are unused 
+@N:CL201 : 68030-68000-bus.vhd(139) | Trying to extract state machine for register cpu_est
+@W:CL246 : 68030-68000-bus.vhd(24) | Input port bits 15 to 2 of a_decode(23 downto 2) are unused 
 @END
 
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 17 17:45:41 2016
+# Fri Aug 19 00:20:34 2016
 
 ###########################################################]
 Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
-@N: :  | Running in 64-bit mode 
+@N: :  | Running in 64-bit mode 
 File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
 
 At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 17 17:45:43 2016
+# Fri Aug 19 00:20:35 2016
 
 ###########################################################]
 Map & Optimize Report
@@ -69,8 +66,8 @@ Map & Optimize Report
 Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014
 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
 Product Version I-2014.03LC 
-@N:MF248 :  | Running in 64-bit mode. 
-@N: : 68030-68000-bus.vhd(134) | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
+@N:MF248 :  | Running in 64-bit mode. 
+@N: : 68030-68000-bus.vhd(139) | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
 Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
 original code -> new code
    000 -> 00000000
@@ -85,25 +82,25 @@ original code -> new code
 Resource Usage Report
 
 Simple gate primitives:
-DFF             78 uses
-BI_DIR          10 uses
+DFF             88 uses
+BI_DIR          18 uses
 BUFTH           4 uses
-IBUF            46 uses
+IBUF            38 uses
 OBUF            15 uses
-AND2            299 uses
-INV             261 uses
+AND2            301 uses
+INV             262 uses
 OR2             27 uses
 XOR2            7 uses
 
 
-@N:FC100 :  | Timing Report not generated for this device, please use place and route tools for timing analysis. 
+@N:FC100 :  | Timing Report not generated for this device, please use place and route tools for timing analysis. 
 I-2014.03LC 
 Mapper successful!
 
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Wed Aug 17 17:45:43 2016
+# Fri Aug 19 00:20:36 2016
 
 ###########################################################]
 
diff --git a/Logic/syntmp/BUS68030_toc.htm b/Logic/syntmp/BUS68030_toc.htm
index e264070..78fcf6d 100644
--- a/Logic/syntmp/BUS68030_toc.htm
+++ b/Logic/syntmp/BUS68030_toc.htm
@@ -16,7 +16,7 @@
 
  • Mapper Report  
 
    • 
-
  • Session Log (17:45 17-Aug)  
+
  • Session Log (00:20 19-Aug)  
 
      •          
         
    
diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml
index 9ee9522..6fb15cf 100644
--- a/Logic/syntmp/run_option.xml
+++ b/Logic/syntmp/run_option.xml
@@ -3,7 +3,7 @@
   Synopsys, Inc.
   Version I-2014.03LC 
   Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
-  Written on Wed Aug 17 17:45:41 2016
+  Written on Fri Aug 19 00:20:34 2016
 
 
 --> 
diff --git a/Logic/syntmp/statusReport.html b/Logic/syntmp/statusReport.html
index 44bb874..346c0e2 100644
--- a/Logic/syntmp/statusReport.html
+++ b/Logic/syntmp/statusReport.html
@@ -33,12 +33,12 @@
   
   Compile InputComplete
  8
- 11
+ 8
 0
 -
 0m:00s
 -
-17.08.2016
      17:45:41
+19.08.2016
      00:20:34
  
 
  
@@ -49,12 +49,12 @@
 0m:00s
 0m:00s
 105MB
-17.08.2016
      17:45:43
+19.08.2016
      00:20:36
  
 
 
   Multi-srs Generator
-  Complete0m:01s17.08.2016
      17:45:43 		
+  Complete0m:00s19.08.2016
      00:20:35 		
      
   
  
\ No newline at end of file
diff --git a/Logic/synwork/BUS68030_comp.fdep b/Logic/synwork/BUS68030_comp.fdep
index 9d6997c..a9765cb 100644
--- a/Logic/synwork/BUS68030_comp.fdep
+++ b/Logic/synwork/BUS68030_comp.fdep
@@ -9,7 +9,7 @@
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471448728
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471558823
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_comp.fdeporig b/Logic/synwork/BUS68030_comp.fdeporig
index c20705c..3dd5757 100644
--- a/Logic/synwork/BUS68030_comp.fdeporig
+++ b/Logic/synwork/BUS68030_comp.fdeporig
@@ -9,7 +9,7 @@
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\arith.vhd":1401223722
 #CUR:"E:\\ispLEVER_Classic2_0\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471448728
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1471558823
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_comp.srs b/Logic/synwork/BUS68030_comp.srs
index dc96d5831817c9b253026a1a3046ba62073fbde2..63737dc57464882844302bdb2e9ef361310df514 100644
GIT binary patch
delta 10642
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