From 2bc1b94e91e004143d1671dee60cb6c174370034 Mon Sep 17 00:00:00 2001 From: MHeinrichs Date: Sat, 24 May 2014 21:59:56 +0200 Subject: [PATCH] DMA-TK-Side first non working version --- Logic/68030-68000-bus.vhd | 337 +- Logic/68030_TK.STY | 6 +- Logic/68030_TK.lci | 8 +- Logic/68030_TK.lct | 8 +- Logic/68030_TK.tcl | 4325 +++++++++++++++++ Logic/68030_tk.bl2 | 2043 ++++---- Logic/68030_tk.bl3 | 959 ++-- Logic/68030_tk.crf | 2 +- Logic/68030_tk.eq3 | 322 +- Logic/68030_tk.fti | 242 +- Logic/68030_tk.grp | 32 +- Logic/68030_tk.ipr | Bin 39 -> 39 bytes Logic/68030_tk.jed | 973 ++-- Logic/68030_tk.lco | 108 +- Logic/68030_tk.out | 2091 +++++++- Logic/68030_tk.plc | 151 +- Logic/68030_tk.prd | 1139 +++-- Logic/68030_tk.rpt | 1021 ++-- Logic/68030_tk.tal | 68 +- Logic/68030_tk.tt2 | 696 +-- Logic/68030_tk.tt3 | 696 +-- Logic/68030_tk.tt4 | 361 +- Logic/68030_tk.tte | 361 +- Logic/68030_tk.vcl | 89 +- Logic/68030_tk.vco | 119 +- Logic/68030_tk.vct | 8 +- Logic/68030_tk.xrf | 2 +- Logic/BUS68030.bl0 | 2022 ++++---- Logic/BUS68030.bl1 | 2043 ++++---- Logic/BUS68030.cmd | 8 + Logic/BUS68030.edi | 2883 ++++++----- Logic/BUS68030.fse | 46 +- Logic/BUS68030.naf | 49 +- Logic/BUS68030.prj | 2 +- Logic/BUS68030.srm | 3622 +++++++------- Logic/BUS68030.srr | 37 +- Logic/BUS68030.srs | Bin 9320 -> 10365 bytes Logic/bus68030.exf | 820 ++-- Logic/bus68030.srf | 37 +- Logic/dm/BUS68030_compiler.xdm | 1 - Logic/lattice_cmd.rs2 | 2 +- Logic/run_options.txt | 2 +- Logic/synlog.tcl | 2 + Logic/synlog/bus68030_fpga_mapper.srr | 20 +- .../report/BUS68030_compiler_errors.txt | 2 +- .../synlog/report/BUS68030_compiler_notes.txt | 4 +- .../report/BUS68030_compiler_runstatus.xml | 4 +- .../report/BUS68030_compiler_warnings.txt | 8 +- .../report/BUS68030_fpga_mapper_runstatus.xml | 4 +- .../report/BUS68030_fpga_mapper_warnings.txt | 1 + Logic/syntmp/run_option.xml | 2 +- Logic/synwork/BUS68030_compiler.fdep | 2 +- Logic/synwork/BUS68030_compiler.fdeporig | 2 +- Logic/synwork/BUS68030_compiler.srs | Bin 9320 -> 10365 bytes Logic/synwork/BUS68030_compiler.tlg | 13 +- 55 files changed, 17930 insertions(+), 9875 deletions(-) create mode 100644 Logic/BUS68030.cmd create mode 100644 Logic/synlog.tcl diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index 5e43d0c..3419955 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -19,7 +19,8 @@ port( UDS_000: inout std_logic; LDS_000: inout std_logic; SIZE: inout std_logic_vector ( 1 downto 0 ); - A: inout std_logic_vector ( 31 downto 0 ); + A: in std_logic_vector ( 31 downto 16 ); + A0: inout std_logic; nEXP_SPACE: in std_logic ; BERR: inout std_logic ; BG_030: in std_logic ; @@ -76,8 +77,7 @@ constant E22 : ESTATE := "1001"; constant E23 : ESTATE := "1101"; constant E24 : ESTATE := "1110"; -signal cpu_est : ESTATE := E20; -signal cpu_est_d : ESTATE := E20; +signal cpu_est : ESTATE; subtype AMIGA_STATE is std_logic_vector(2 downto 0); @@ -90,34 +90,36 @@ constant DATA_FETCH_N: AMIGA_STATE := "101"; constant DATA_FETCH_P : AMIGA_STATE := "110"; constant END_CYCLE_N : AMIGA_STATE := "111"; -signal SM_AMIGA : AMIGA_STATE := IDLE_P; +signal SM_AMIGA : AMIGA_STATE; --signal Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000"; -signal AS_000_INT:STD_LOGIC:= '1'; -signal AS_030_000_SYNC:STD_LOGIC:= '1'; -signal BGACK_030_INT:STD_LOGIC:= '1'; -signal DTACK_SYNC:STD_LOGIC:= '1'; -signal DTACK_DMA:STD_LOGIC:= '1'; -signal FPU_CS_INT:STD_LOGIC:= '1'; -signal VPA_D: STD_LOGIC:='1'; -signal VPA_SYNC: STD_LOGIC:='1'; -signal VMA_INT: STD_LOGIC:='1'; -signal UDS_000_INT: STD_LOGIC:='1'; -signal LDS_000_INT: STD_LOGIC:='1'; -signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11"; -signal CLK_CNT_P: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00"; -signal CLK_CNT_N: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00"; -signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10"; -signal CLK_OUT_PRE: STD_LOGIC:='1'; -signal CLK_OUT_INT: STD_LOGIC:='1'; -signal CLK_030_D: STD_LOGIC:='1'; -signal CLK_000_D0: STD_LOGIC := '1'; -signal CLK_000_D1: STD_LOGIC := '1'; -signal CLK_000_D2: STD_LOGIC := '1'; -signal CLK_000_D3: STD_LOGIC := '1'; -signal CLK_000_D4: STD_LOGIC := '1'; -signal CLK_000_D5: STD_LOGIC := '1'; -signal CLK_000_D6: STD_LOGIC := '1'; +signal AS_000_INT:STD_LOGIC := '1'; +signal AS_030_000_SYNC:STD_LOGIC := '1'; +signal BGACK_030_INT:STD_LOGIC := '1'; +signal BGACK_030_INT_D:STD_LOGIC := '1'; +signal DTACK_SYNC:STD_LOGIC := '1'; +signal AS_000_DMA:STD_LOGIC := '1'; +signal DS_000_DMA:STD_LOGIC := '1'; +signal SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11"; +signal A0_DMA: STD_LOGIC := '1'; +signal FPU_CS_INT:STD_LOGIC := '1'; +signal VPA_SYNC: STD_LOGIC := '1'; +signal VMA_INT: STD_LOGIC := '1'; +signal UDS_000_INT: STD_LOGIC := '1'; +signal LDS_000_INT: STD_LOGIC := '1'; +signal DSACK1_INT: STD_LOGIC := '1'; +signal CLK_CNT_P: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00"; +signal CLK_CNT_N: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00"; +signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10"; +signal CLK_OUT_PRE: STD_LOGIC := '1'; +signal CLK_OUT_INT: STD_LOGIC := '1'; +signal CLK_000_D0: STD_LOGIC := '1'; +signal CLK_000_D1: STD_LOGIC := '1'; +signal CLK_000_D2: STD_LOGIC := '1'; +signal CLK_000_D3: STD_LOGIC := '1'; +signal CLK_000_D4: STD_LOGIC := '1'; +signal CLK_000_D5: STD_LOGIC := '1'; +signal CLK_000_D6: STD_LOGIC := '1'; begin @@ -146,8 +148,6 @@ begin CLK_OUT_PRE <= '0'; CLK_OUT_INT <= '0'; cpu_est <= E20; - cpu_est_d <= E20; - VPA_D <= '1'; CLK_000_D0 <= '1'; CLK_000_D1 <= '1'; CLK_000_D2 <= '1'; @@ -209,8 +209,6 @@ begin null; end case; end if; - cpu_est_d <= cpu_est; - VPA_D <= VPA; end if; end process clk; @@ -229,11 +227,18 @@ begin FPU_CS_INT <= '1'; BG_000 <= '1'; BGACK_030_INT <= '1'; - DSACK_INT <= "11"; - DTACK_DMA <= '1'; + BGACK_030_INT_D <= '1'; + DSACK1_INT <= '1'; DTACK_SYNC <= '1'; VPA_SYNC <= '1'; IPL_030 <= "111"; + AMIGA_BUS_ENABLE <= '1' ; + AS_000_DMA <= '1'; + DS_000_DMA <= '1'; + SIZE_DMA <= "11"; + A0_DMA <= '1'; + + elsif(rising_edge(CLK_OSZI)) then @@ -244,6 +249,7 @@ begin elsif (BGACK_000='1' AND CLK_000_D1='0' and CLK_000_D0='1') then -- BGACK_000 is high here! BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high end if; + BGACK_030_INT_D <= BGACK_030_INT; --bus grant only in idle state if(BG_030= '1')then @@ -266,13 +272,12 @@ begin if(AS_030 ='1') then -- "async" reset of various signals AS_030_000_SYNC <= '1'; FPU_CS_INT <= '1'; - DSACK_INT <="11"; + DSACK1_INT <= '1'; AS_000_INT <= '1'; UDS_000_INT <= '1'; LDS_000_INT <= '1'; DTACK_SYNC <= '1'; VPA_SYNC <= '1'; - AMIGA_BUS_ENABLE <= '1'; elsif( CLK_030 = '1' AND --68030 has a valid AS on high clocks AS_030 = '0') then if(FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1') then @@ -285,106 +290,145 @@ begin end if; -- VMA generation - if(CLK_000_D0='0' AND VPA_D='0' AND cpu_est = E4)then --assert + if(CLK_000_D0='0' AND VPA='0' AND cpu_est = E4)then --assert VMA_INT <= '0'; elsif(CLK_000_D0='1' AND AS_000_INT='1' AND cpu_est=E1)then --deassert VMA_INT <= '1'; end if; - --Amiga statemachine - case (SM_AMIGA) is - when IDLE_P => --68000:S0 wait for a falling edge - if( CLK_000_D2='0' and CLK_000_D3= '1' and AS_030_000_SYNC = '0')then - SM_AMIGA<=IDLE_N; --go to s1 - end if; - when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe - if(nEXP_SPACE ='1')then - AMIGA_BUS_ENABLE <= '0' ;--for now: allways on for amiga - else -- if this a delayed expansion space detection, aboard this cycle! - AMIGA_BUS_ENABLE <= '1'; - AS_030_000_SYNC <= '1'; - SM_AMIGA <= IDLE_P; --aboard - end if; + --Amiga statemachine + case (SM_AMIGA) is + when IDLE_P => --68000:S0 wait for a falling edge + if( CLK_000_D2='0' and CLK_000_D3= '1' and AS_030_000_SYNC = '0')then + SM_AMIGA<=IDLE_N; --go to s1 + end if; + when IDLE_N => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe + if(nEXP_SPACE ='1')then + AMIGA_BUS_ENABLE <= '0' ;--for now: allways on for amiga + else -- if this a delayed expansion space detection, aboard this cycle! + AS_030_000_SYNC <= '1'; + SM_AMIGA <= IDLE_P; --aboard + end if; + + if(CLK_000_D0='1')then --go to s2 + SM_AMIGA <= AS_SET_P; --as for amiga set! + end if; + when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here + AS_000_INT <= '0'; + if (RW='1' and DS_030 = '0') then --read: set udl/lds + if(A0='0') then + UDS_000_INT <= '0'; + else + UDS_000_INT <= '1'; + end if; + if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then + LDS_000_INT <= '0'; + else + LDS_000_INT <= '1'; + end if; + end if; + + + if(CLK_000_D0='0')then --go to s3 + SM_AMIGA<=AS_SET_N; + end if; + when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write + if (RW='0' and DS_030 = '0') then --write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late + if(A0='0') then + UDS_000_INT <= '0'; + else + UDS_000_INT <= '1'; + end if; + if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then + LDS_000_INT <= '0'; + else + LDS_000_INT <= '1'; + end if; + end if; + if(CLK_000_D0='1')then --go to s4 + SM_AMIGA <= SAMPLE_DTACK_P; + end if; + when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA + if(CLK_000_D0='0' )then --go to s5 + if(DTACK_SYNC = '0' OR VPA_SYNC ='0')then + SM_AMIGA<=DATA_FETCH_N; + end if; + elsif(CLK_000_D0='1' )then -- high clock: sample DTACK + if(VPA = '1' AND DTACK='0') then + DTACK_SYNC <= '0'; + elsif(VPA='0' AND cpu_est=E9 AND VMA_INT='0') then --vpa/vma cycle: sync VPA on E9: one 7M-clock to latch! + VPA_SYNC <= '0'; + end if; + end if; + when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock + if(CLK_000_D0='1')then --go to s6 + SM_AMIGA<=DATA_FETCH_P; + end if; + when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus! + if( CLK_000_D5 ='1' AND CLK_000_D6 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge + DSACK1_INT <='0'; + AS_030_000_SYNC <= '1'; --cycle end + elsif( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge + --DSACK1_INT<='0'; + SM_AMIGA<=END_CYCLE_N; + --AS_030_000_SYNC <= '1'; --cycle end + end if; + when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock + if(CLK_000_D0='1' and AS_000_INT = '1' )then --go to s0 + AMIGA_BUS_ENABLE <= '1'; + SM_AMIGA<=IDLE_P; + end if; + end case; - if(CLK_000_D0='1')then --go to s2 - SM_AMIGA <= AS_SET_P; --as for amiga set! - end if; - when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here - AS_000_INT <= '0'; - if (RW='1' and DS_030 = '0') then --read: set udl/lds - if(A(0)='0') then - UDS_000_INT <= '0'; - else - UDS_000_INT <= '1'; - end if; - if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then - LDS_000_INT <= '0'; - else - LDS_000_INT <= '1'; - end if; - end if; + if(BGACK_030_INT='1') then + if(BGACK_030_INT_D='0')then + AMIGA_BUS_ENABLE <= '1' ; --end of DMA cycle + AS_000_DMA <= '1'; + DS_000_DMA <= '1'; + SIZE_DMA <= "11"; + A0_DMA <= '0'; + end if; + else + --dma stuff + + --switch amiga bus on/off on the edges + if(BGACK_030_INT_D='1' )then + AMIGA_BUS_ENABLE <= '0' ; + end if; + --as can only be done if we know the uds/lds! + if(AS_000='0' and CLK_030='0' and (UDS_000='0' or LDS_000='0'))then --sampled on rising edges! - if(CLK_000_D0='0')then --go to s3 - SM_AMIGA<=AS_SET_N; + --set AS_000 + AS_000_DMA <= '0'; + if(RW='1') then + DS_000_DMA <='0'; + else + DS_000_DMA <=AS_000_DMA; -- write: one clock delayed! end if; - when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write - if (RW='0' and DS_030 = '0') then --write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late - if(A(0)='0') then - UDS_000_INT <= '0'; - else - UDS_000_INT <= '1'; - end if; - if((A(0)='1' OR SIZE(0)='0' OR SIZE(1)='1')) then - LDS_000_INT <= '0'; - else - LDS_000_INT <= '1'; - end if; + -- now determine the size: if both uds and lds is set its 16 bit else 8 bit! + if(UDS_000='0' and LDS_000='0') then + SIZE_DMA <= "10"; --16bit + else + SIZE_DMA <= "01"; --8 bit end if; - if(CLK_000_D0='1')then --go to s4 - SM_AMIGA <= SAMPLE_DTACK_P; - end if; - when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA - if(CLK_000_D0='0' )then --go to s5 - if(DTACK_SYNC = '0' OR VPA_SYNC ='0')then - SM_AMIGA<=DATA_FETCH_N; - end if; - elsif(CLK_000_D0='1' )then -- high clock: sample DTACK - if(VPA_D = '1' AND DTACK='0') then - DTACK_SYNC <= '0'; - elsif(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0') then --vpa/vma cycle: sync VPA on E9: one 7M-clock to latch! - VPA_SYNC <= '0'; - end if; - end if; - when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock - if(CLK_000_D0='1')then --go to s6 - SM_AMIGA<=DATA_FETCH_P; - end if; - when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus! - if( CLK_000_D5 ='1' AND CLK_000_D6 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge - DSACK_INT<="01"; - AS_030_000_SYNC <= '1'; --cycle end - elsif( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge - --DSACK_INT<="01"; - SM_AMIGA<=END_CYCLE_N; - --AS_030_000_SYNC <= '1'; --cycle end - end if; - when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock - if(CLK_000_D0='1' and AS_000_INT = '1' )then --go to s0 - SM_AMIGA<=IDLE_P; - end if; - end case; - - - --dma stuff - --DTACK for DMA cycles - if(AS_000_INT ='0' AND DSACK(1) ='0') then - DTACK_DMA <= '0'; - else - DTACK_DMA <= '1'; + + --now calculate the offset: + --if uds is set low, a0 is so too. + --if only lds is set a1 is high + --therefore a1 = uds + --great! life is simple here! + A0_DMA <= UDS_000; + + --A1 is set by the amiga side + else + AS_000_DMA <= '1'; + DS_000_DMA <= '1'; + SIZE_DMA <= "11"; + A0_DMA <= '0'; + end if; end if; - end if; end process state_machine; @@ -393,10 +437,18 @@ begin CLK_EXP <= CLK_OUT_INT; AVEC_EXP <= 'Z' when FPU_CS_INT ='1' else '0'; - --dtack for dma - DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else - DTACK_DMA; - + --dma stuff + DTACK <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else + DSACK(1); + AS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else + AS_000_DMA; + DS_030 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else + DS_000_DMA; + A0 <= 'Z' when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else + A0_DMA; + SIZE <= "ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE = '1' else + SIZE_DMA; + --fpu FPU_CS <= FPU_CS_INT; @@ -412,7 +464,10 @@ begin '0'; --bus buffers - AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0'; + AMIGA_BUS_DATA_DIR <= '1' WHEN (RW='0' AND BGACK_030_INT ='1') ELSE + '0' WHEN (RW='1' AND BGACK_030_INT ='1') ELSE + '1' WHEN (RW='1' AND BGACK_030_INT ='0') ELSE + '0' ; AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off --e and VMA @@ -426,28 +481,16 @@ begin --as and uds/lds AS_000 <= 'Z' when BGACK_030_INT ='0' else AS_000_INT; + + UDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle UDS_000_INT; LDS_000 <= 'Z' when BGACK_030_INT ='0' else -- output on cpu cycle LDS_000_INT; --dsack - DSACK <= "ZZ" when nEXP_SPACE = '0' else -- output on amiga cycle - DSACK_INT; - BGACK_030 <= BGACK_030_INT; - -- signal assignment - --DS_030 <= "ZZ"; - --DS_030 <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle - -- DS_030_INT; - - --A(1) <= 'Z'; - --A(0) <= 'Z'; - --A[1 downto 0] <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle - -- A_INT; - - --SIZE <= "ZZ"; - --SIZE <= "ZZ" when BGACK_030_INT ='1' else -- output on dma cycle - -- SIZE_INT; - + DSACK(1) <= 'Z' when nEXP_SPACE = '0' else -- output on amiga cycle + DSACK1_INT; + BGACK_030 <= BGACK_030_INT; end Behavioral; diff --git a/Logic/68030_TK.STY b/Logic/68030_TK.STY index f74ee1f..0e8afb8 100644 --- a/Logic/68030_TK.STY +++ b/Logic/68030_TK.STY @@ -1,6 +1,4 @@ -[STRATEGY-LIST] -Normal=True, 1385910337 -[TOUCHED-REPORT] -Design.tt4File=1400149811 [synthesis-type] tool=Synplify +[STRATEGY-LIST] +Normal=True, 1385910337 diff --git a/Logic/68030_TK.lci b/Logic/68030_TK.lci index 11d9481..247fad0 100644 --- a/Logic/68030_TK.lci +++ b/Logic/68030_TK.lci @@ -12,8 +12,8 @@ EN_PinMacrocell = Yes; [Revision] Parent = m4a5.lci; -DATE = 05/15/2014; -TIME = 12:30:11; +DATE = 05/24/2014; +TIME = 21:28:20; Source_Format = Pure_VHDL; Synthesis = Synplify; @@ -25,7 +25,7 @@ Synthesis = Synplify; [Global Constraints] Spread_placement = Yes; -Zero_hold_time = Yes; +Zero_hold_time = No; [Location Assignments] layer = OFF; @@ -88,6 +88,8 @@ A_31_ = Pin, 4, -, B, -; DS_030 = Pin, 98, -, A, -; AVEC_EXP = Pin, 22, -, C, -; BERR = Pin, 41, -, E, -; +nEXP_SPACE = Pin, 14, -, -, -; +A0 = Pin, 69, -, G, -; [Group Assignments] layer = OFF; diff --git a/Logic/68030_TK.lct b/Logic/68030_TK.lct index 11d9481..247fad0 100644 --- a/Logic/68030_TK.lct +++ b/Logic/68030_TK.lct @@ -12,8 +12,8 @@ EN_PinMacrocell = Yes; [Revision] Parent = m4a5.lci; -DATE = 05/15/2014; -TIME = 12:30:11; +DATE = 05/24/2014; +TIME = 21:28:20; Source_Format = Pure_VHDL; Synthesis = Synplify; @@ -25,7 +25,7 @@ Synthesis = Synplify; [Global Constraints] Spread_placement = Yes; -Zero_hold_time = Yes; +Zero_hold_time = No; [Location Assignments] layer = OFF; @@ -88,6 +88,8 @@ A_31_ = Pin, 4, -, B, -; DS_030 = Pin, 98, -, A, -; AVEC_EXP = Pin, 22, -, C, -; BERR = Pin, 41, -, E, -; +nEXP_SPACE = Pin, 14, -, -, -; +A0 = Pin, 69, -, G, -; [Group Assignments] layer = OFF; diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index b960bf9..51d0523 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -150339,3 +150339,4328 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 05/24/14 19:56:13 ########### + +########## Tcl recorder starts at 05/24/14 20:54:19 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 20:54:19 ########### + + +########## Tcl recorder starts at 05/24/14 20:54:19 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 20:54:19 ########### + + +########## Tcl recorder starts at 05/24/14 20:55:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 20:55:08 ########### + + +########## Tcl recorder starts at 05/24/14 20:55:08 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 20:55:08 ########### + + +########## Tcl recorder starts at 05/24/14 20:55:26 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 20:55:26 ########### + + +########## Tcl recorder starts at 05/24/14 20:55:26 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 20:55:26 ########### + + +########## Tcl recorder starts at 05/24/14 20:55:46 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 20:55:46 ########### + + +########## Tcl recorder starts at 05/24/14 21:02:17 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:02:17 ########### + + +########## Tcl recorder starts at 05/24/14 21:02:17 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:02:17 ########### + + +########## Tcl recorder starts at 05/24/14 21:02:35 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:02:35 ########### + + +########## Tcl recorder starts at 05/24/14 21:03:49 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:03:49 ########### + + +########## Tcl recorder starts at 05/24/14 21:08:23 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:08:23 ########### + + +########## Tcl recorder starts at 05/24/14 21:08:23 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:08:23 ########### + + +########## Tcl recorder starts at 05/24/14 21:11:08 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:11:08 ########### + + +########## Tcl recorder starts at 05/24/14 21:11:08 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:11:08 ########### + + +########## Tcl recorder starts at 05/24/14 21:12:52 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:12:52 ########### + + +########## Tcl recorder starts at 05/24/14 21:13:22 ########## + +# Commands to make the Process: +# JEDEC File +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:13:22 ########### + + +########## Tcl recorder starts at 05/24/14 21:17:22 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:17:22 ########### + + +########## Tcl recorder starts at 05/24/14 21:17:22 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:17:22 ########### + + +########## Tcl recorder starts at 05/24/14 21:20:44 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:20:44 ########### + + +########## Tcl recorder starts at 05/24/14 21:20:45 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:20:45 ########### + + +########## Tcl recorder starts at 05/24/14 21:21:27 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:21:27 ########### + + +########## Tcl recorder starts at 05/24/14 21:21:27 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:21:27 ########### + + +########## Tcl recorder starts at 05/24/14 21:23:59 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:23:59 ########### + + +########## Tcl recorder starts at 05/24/14 21:23:59 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:23:59 ########### + + +########## Tcl recorder starts at 05/24/14 21:24:27 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:24:27 ########### + + +########## Tcl recorder starts at 05/24/14 21:24:27 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:24:27 ########### + + +########## Tcl recorder starts at 05/24/14 21:25:21 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:25:21 ########### + + +########## Tcl recorder starts at 05/24/14 21:25:22 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:25:22 ########### + + +########## Tcl recorder starts at 05/24/14 21:25:37 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:25:37 ########### + + +########## Tcl recorder starts at 05/24/14 21:27:13 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:27:13 ########### + + +########## Tcl recorder starts at 05/24/14 21:27:14 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:27:14 ########### + + +########## Tcl recorder starts at 05/24/14 21:28:02 ########## + +# Commands to make the Process: +# Constraint Editor +# - none - +# Application to view the Process: +# Constraint Editor +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -lci \"68030_tk.lct\" -touch \"68030_tk.tt4\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:28:02 ########### + + +########## Tcl recorder starts at 05/24/14 21:28:25 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:28:25 ########### + + +########## Tcl recorder starts at 05/24/14 21:29:58 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:29:58 ########### + + +########## Tcl recorder starts at 05/24/14 21:29:59 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:29:59 ########### + + +########## Tcl recorder starts at 05/24/14 21:49:46 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:49:46 ########### + + +########## Tcl recorder starts at 05/24/14 21:49:47 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:49:47 ########### + + +########## Tcl recorder starts at 05/24/14 21:50:40 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:50:41 ########### + + +########## Tcl recorder starts at 05/24/14 21:50:41 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:50:41 ########### + + +########## Tcl recorder starts at 05/24/14 21:51:55 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:51:55 ########### + + +########## Tcl recorder starts at 05/24/14 21:51:55 ########## + +# Commands to make the Process: +# Post-Fit Pinouts +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +# Application to view the Process: +# Post-Fit Pinouts +if [catch {open lattice_cmd.rs2 w} rspFile] { + puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile" +} else { + puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -postfit -lci 68030_tk.lco +" + close $rspFile +} +if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:51:55 ########### + + +########## Tcl recorder starts at 05/24/14 21:52:19 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:52:20 ########### + + +########## Tcl recorder starts at 05/24/14 21:52:20 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:52:20 ########### + + +########## Tcl recorder starts at 05/24/14 21:55:14 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:55:14 ########### + + +########## Tcl recorder starts at 05/24/14 21:55:14 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:55:14 ########### + + +########## Tcl recorder starts at 05/24/14 21:56:14 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:56:14 ########### + + +########## Tcl recorder starts at 05/24/14 21:56:15 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:56:15 ########### + + +########## Tcl recorder starts at 05/24/14 21:56:40 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:56:40 ########### + + +########## Tcl recorder starts at 05/24/14 21:56:40 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:56:41 ########### + + +########## Tcl recorder starts at 05/24/14 21:59:07 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:59:07 ########### + + +########## Tcl recorder starts at 05/24/14 21:59:07 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 05/24/14 21:59:07 ########### + diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2 index 8e6dda1..c6af2e5 100644 --- a/Logic/68030_tk.bl2 +++ b/Logic/68030_tk.bl2 @@ -1,271 +1,306 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat May 24 19:56:20 2014 +#$ DATE Sat May 24 21:59:14 2014 #$ MODULE 68030_tk -#$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 SIZE_0_ DS_030 \ -# A_30_ UDS_000 A_29_ LDS_000 A_28_ nEXP_SPACE A_27_ BERR A_26_ BG_030 A_25_ BG_000 A_24_ \ -# BGACK_030 A_23_ BGACK_000 A_22_ CLK_030 A_21_ CLK_000 A_20_ CLK_OSZI A_19_ CLK_DIV_OUT \ -# A_18_ CLK_EXP A_17_ FPU_CS A_16_ DTACK A_15_ AVEC A_14_ AVEC_EXP A_13_ E A_12_ VPA A_11_ VMA \ -# A_10_ RST A_9_ RESET A_8_ RW A_7_ AMIGA_BUS_ENABLE A_6_ AMIGA_BUS_DATA_DIR A_5_ \ -# AMIGA_BUS_ENABLE_LOW A_4_ CIIN A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ \ -# DSACK_0_ FC_0_ -#$ NODES 365 CLK_000_c CLK_OSZI_c CLK_OUT_INTreg inst_BGACK_030_INTreg \ -# inst_FPU_CS_INTreg IPL_030DFFSH_0_reg inst_VMA_INTreg inst_AS_000_INTreg \ -# IPL_030DFFSH_1_reg inst_AS_030_000_SYNC inst_DTACK_SYNC IPL_030DFFSH_2_reg \ -# inst_VPA_D inst_VPA_SYNC ipl_c_0__n inst_CLK_000_D0 inst_CLK_000_D1 ipl_c_1__n \ -# inst_CLK_000_D2 inst_CLK_000_D6 ipl_c_2__n SM_AMIGA_5_ SM_AMIGA_6_ vcc_n_n \ -# dsack_c_1__n gnd_n_n inst_UDS_000_INTreg DTACK_c inst_LDS_000_INTreg DSACK_INT_1_ \ -# AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n inst_CLK_000_D3 SM_AMIGA_4_ \ -# state_machine_un23_clk_000_d0_n state_machine_un6_clk_000_d5_n RST_c \ -# inst_CLK_000_D5 SM_AMIGA_7_ RESETDFFRHreg SM_AMIGA_3_ \ -# state_machine_un6_bgack_000_n RW_c SM_AMIGA_1_ inst_DTACK_DMA fc_c_0__n G_102 \ -# CLK_CNT_N_0_ fc_c_1__n CLK_CNT_N_1_ G_108 AMIGA_BUS_ENABLEDFFreg CLK_CNT_P_0_ \ -# CLK_CNT_P_1_ SM_AMIGA_2_ SM_AMIGA_0_ state_machine_un10_bg_030_n cpu_est_ns_0_1__n \ -# state_machine_un7_as_000_int_n N_129_i inst_CLK_000_D4 N_131_i \ -# state_machine_un15_clk_000_d0_n N_221_i state_machine_lds_000_int_5_n N_222_i \ -# state_machine_uds_000_int_5_n N_63_0 un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_62_0 \ -# inst_CLK_OUT_PRE N_132_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_60_i N_59_i \ -# N_57_i N_56_i N_55_i CLK_000_D1_i N_54_i N_51_i N_50_i N_125_i N_126_i \ -# cpu_est_ns_e_0_0__n N_85_i N_123_i N_124_i sm_amiga_ns_0_0__n cpu_est_0_ N_122_i \ -# cpu_est_1_ N_227_i cpu_est_2_ N_228_i cpu_est_3_reg cpu_est_ns_0_2__n N_226_i N_44_i \ -# N_130_i N_225_i cpu_est_ns_1__n N_158_i cpu_est_ns_2__n N_219_i N_204 N_220_i N_205 \ -# sm_amiga_ns_0_7__n N_206 N_215_i N_26 N_216_i N_30 N_49 N_95_i N_50 N_214_i N_51 \ -# sm_amiga_ns_0_5__n N_54 N_94_i N_55 N_133_i N_56 N_57 N_87_i N_59 N_60 N_86_i N_62 N_63 \ -# N_83_i N_68 N_70 N_82_i N_72 state_machine_lds_000_int_5_0_n N_73 \ -# state_machine_uds_000_int_5_0_n N_74 N_80_i N_76 N_30_0 N_78 N_26_0 N_80 N_76_i N_82 \ -# N_206_0 N_83 N_205_0 N_85 N_72_i N_86 N_73_i N_87 state_machine_un15_clk_000_d0_0_n \ -# N_94 N_204_0 N_95 BG_030_c_i N_214 N_70_i N_215 state_machine_un10_bg_030_0_n N_216 \ -# state_machine_un6_bgack_000_0_n N_219 N_220 state_machine_un23_clk_000_d0_0_n \ -# N_221 N_236_1 N_222 N_236_2 N_225 N_236_3 N_226 N_236_4 N_227 N_236_5 N_228 N_236_6 N_122 \ -# N_239_1 N_123 N_239_2 N_124 state_machine_un8_clk_000_d2_1_n N_125 N_55_i_1 N_126 \ -# N_55_i_2 N_129 N_55_i_3 N_130 N_55_i_4 N_131 N_55_i_5 N_132 cpu_est_ns_0_1_1__n N_133 \ -# cpu_est_ns_0_2_1__n N_236 N_80_1 N_239 N_80_2 RW_i N_78_1 VMA_INT_i N_78_2 VPA_D_i \ -# N_74_1 DTACK_i N_74_2 CLK_000_D0_i N_74_3 sm_amiga_i_4__n N_70_1 cpu_est_i_3__n N_70_2 \ -# sm_amiga_i_1__n sm_amiga_ns_0_1_0__n state_machine_un6_clk_000_d5_i_n \ -# cpu_est_ns_0_1_2__n sm_amiga_i_6__n N_226_1 nEXP_SPACE_i N_220_1 AS_000_INT_i N_82_1 \ -# cpu_est_i_1__n N_73_1 cpu_est_i_0__n N_72_1 AMIGA_BUS_ENABLE_i \ -# state_machine_uds_000_int_5_0_m2_un3_n AS_030_i \ -# state_machine_uds_000_int_5_0_m2_un1_n cpu_est_i_2__n \ -# state_machine_uds_000_int_5_0_m2_un0_n sm_amiga_i_2__n vpa_sync_0_un3_n \ -# sm_amiga_i_3__n vpa_sync_0_un1_n sm_amiga_i_5__n vpa_sync_0_un0_n \ -# state_machine_un8_clk_000_d2_i_n vma_int_0_un3_n sm_amiga_i_7__n vma_int_0_un1_n \ -# a_i_0__n vma_int_0_un0_n size_i_1__n bg_000_0_un3_n dsack_i_1__n bg_000_0_un1_n \ -# BGACK_030_INT_i bg_000_0_un0_n CLK_000_D2_i bgack_030_int_0_un3_n \ -# AS_030_000_SYNC_i bgack_030_int_0_un1_n a_i_19__n bgack_030_int_0_un0_n a_i_16__n \ -# as_000_int_0_un3_n a_i_18__n as_000_int_0_un1_n a_i_30__n as_000_int_0_un0_n \ -# a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n a_i_29__n \ -# ipl_030_0_0__un0_n a_i_26__n ipl_030_0_1__un3_n a_i_27__n ipl_030_0_1__un1_n \ -# a_i_24__n ipl_030_0_1__un0_n a_i_25__n ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n \ -# ipl_030_0_2__un0_n cpu_estse_0_un3_n CLK_OSZI_i cpu_estse_0_un1_n \ -# cpu_estse_0_un0_n N_74_i cpu_estse_1_un3_n N_78_i cpu_estse_1_un1_n FPU_CS_INT_i \ -# cpu_estse_1_un0_n CLK_000_D6_i cpu_estse_2_un3_n AS_030_c cpu_estse_2_un1_n \ -# cpu_estse_2_un0_n as_030_000_sync_0_un3_n DS_030_c as_030_000_sync_0_un1_n \ -# as_030_000_sync_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n size_c_0__n \ -# dtack_sync_0_un0_n fpu_cs_int_0_un3_n size_c_1__n fpu_cs_int_0_un1_n \ -# fpu_cs_int_0_un0_n a_c_0__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n \ -# dsack_int_0_1__un0_n amiga_bus_enable_0_un3_n amiga_bus_enable_0_un1_n \ -# amiga_bus_enable_0_un0_n uds_000_int_0_un3_n uds_000_int_0_un1_n \ -# uds_000_int_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n \ -# a_15__n a_14__n a_13__n a_c_16__n a_12__n a_c_17__n a_11__n a_c_18__n a_10__n a_c_19__n \ -# a_9__n a_c_20__n a_8__n a_c_21__n a_7__n a_c_22__n a_6__n a_c_23__n a_5__n a_c_24__n \ -# a_4__n a_c_25__n a_3__n a_c_26__n a_2__n a_c_27__n a_1__n a_c_28__n a_c_29__n a_c_30__n \ -# a_c_31__n nEXP_SPACE_c BG_030_c BG_000DFFSHreg BGACK_000_c CLK_030_c +#$ PINS 59 IPL_030_1_ IPL_030_0_ SIZE_1_ IPL_1_ IPL_0_ A_31_ DSACK_0_ FC_0_ IPL_030_2_ \ +# IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 nEXP_SPACE BERR BG_030 \ +# BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DTACK \ +# AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ +# AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ \ +# A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ +#$ NODES 398 BG_030_c BG_000DFFSHreg BGACK_000_c inst_BGACK_030_INTreg \ +# inst_FPU_CS_INTreg CLK_030_c inst_VMA_INTreg inst_AS_030_000_SYNC CLK_000_c \ +# inst_BGACK_030_INT_D inst_DTACK_SYNC CLK_OSZI_c inst_VPA_SYNC inst_CLK_000_D0 \ +# inst_CLK_000_D1 CLK_OUT_INTreg inst_CLK_000_D2 inst_CLK_000_D6 SM_AMIGA_5_ \ +# IPL_030DFFSH_0_reg vcc_n_n gnd_n_n IPL_030DFFSH_1_reg inst_AS_000_INT SM_AMIGA_6_ \ +# IPL_030DFFSH_2_reg inst_UDS_000_INT inst_LDS_000_INT ipl_c_0__n inst_DSACK1_INT \ +# inst_CLK_000_D3 ipl_c_1__n state_machine_un23_clk_000_d0_n inst_CLK_000_D5 \ +# ipl_c_2__n SM_AMIGA_3_ SM_AMIGA_0_ SM_AMIGA_1_ dsack_c_1__n inst_AS_000_DMA \ +# inst_DS_000_DMA DTACK_c SIZE_DMA_0_ SIZE_DMA_1_ inst_A0_DMA G_103 CLK_CNT_N_0_ VPA_c \ +# CLK_CNT_N_1_ G_109 CLK_CNT_P_0_ RST_c CLK_CNT_P_1_ inst_CLK_000_D4 RESETDFFRHreg \ +# SM_AMIGA_7_ state_machine_un15_clk_000_d0_n RW_c SM_AMIGA_4_ \ +# un1_AMIGA_BUS_ENABLE_0_sqmuxa_2 fc_c_0__n inst_CLK_OUT_PRE SM_AMIGA_2_ fc_c_1__n \ +# AMIGA_BUS_ENABLEDFFSHreg state_machine_un23_clk_000_d0_0_n \ +# state_machine_un6_bgack_000_0_n N_214_0 BG_030_c_i N_227_i \ +# state_machine_un10_bg_030_0_n N_215_0 N_216_0 N_126_i N_33_0 N_127_i N_35_0 \ +# state_machine_uds_000_int_5_0_n N_130_i state_machine_lds_000_int_5_0_n N_132_i \ +# N_131_i cpu_est_0_ cpu_est_1_ N_133_i cpu_est_2_ cpu_est_3_reg N_134_i N_137_i N_138_i \ +# sm_amiga_ns_0_5__n cpu_est_ns_1__n N_139_i cpu_est_ns_2__n N_140_i N_46_0 N_52 \ +# N_142_i N_59 N_141_i N_62 sm_amiga_ns_0_7__n N_65 N_144_i N_67 \ +# state_machine_ds_000_dma_5_0_n N_72 CLK_030_c_i N_77 AS_000_c_i N_88 N_59_i N_217 \ +# N_61_0 N_219 N_62_i N_221 CLK_000_D1_i N_224 N_65_i N_225 N_66_i N_226 N_67_i N_128 \ +# N_175_i N_130 un1_as_000_dma5_i_0__n N_132 state_machine_un6_clk_000_d5_i_n N_135 \ +# N_71_i N_136 DS_030_c_i N_138 N_73_i N_143 N_156_i N_145 \ +# un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i N_146 N_75_0 N_147 N_176_i N_148 N_52_0 N_151 \ +# N_173_i N_153 N_226_i N_154 N_77_0 N_155 N_72_i N_173 N_147_i cpu_est_ns_0_0_x2_1_ \ +# N_148_i AMIGA_BUS_DATA_DIR_m1_0_x2 cpu_est_ns_e_0_0__n N_228_1 N_146_i N_237 \ +# sm_amiga_ns_0_0__n N_247 N_88_i N_227 N_145_i N_228 cpu_est_ns_0_2__n N_127 N_143_i \ +# N_66 N_154_i N_175 N_161_i N_176 N_153_i N_75 N_155_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_4 \ +# cpu_est_ns_0_1__n N_61 N_135_i N_156 N_136_i N_73 N_57 N_225_i N_71 \ +# un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0 state_machine_un6_clk_000_d5_n N_219_i \ +# un1_as_000_dma5_0__n N_221_i N_223 state_machine_un15_clk_000_d0_0_n \ +# state_machine_ds_000_dma_5_n N_144 N_66_i_1 N_141 N_66_i_2 N_142 N_66_i_3 N_139 \ +# N_66_i_4 N_140 N_66_i_5 N_137 N_237_1 N_134 N_237_2 N_133 N_247_1 N_131 N_247_2 \ +# state_machine_lds_000_int_5_n N_247_3 state_machine_uds_000_int_5_n N_247_4 N_35 \ +# N_247_5 N_33 N_247_6 N_126 N_52_0_1 N_216 N_52_0_2 N_215 N_224_1 \ +# state_machine_un10_bg_030_n N_224_2 N_214 N_227_1 state_machine_un6_bgack_000_n \ +# N_227_2 state_machine_un8_clk_000_d2_n N_228_1_0 SIZE_DMA_1_sqmuxa N_127_1 \ +# SIZE_DMA_0_sqmuxa N_127_2 AS_000_INT_1_sqmuxa N_151_1 N_249 SIZE_DMA_1_sqmuxa_1 \ +# CLK_000_D6_i state_machine_un8_clk_000_d2_1_n N_228_i sm_amiga_ns_0_1_0__n \ +# sm_amiga_i_5__n cpu_est_ns_0_1_1__n N_224_i N_138_1 N_223_i N_130_1 \ +# SIZE_DMA_0_sqmuxa_i N_128_1 SIZE_DMA_1_sqmuxa_i N_221_1 a_i_18__n N_219_1 a_i_16__n \ +# vpa_sync_0_un3_n a_i_19__n vpa_sync_0_un1_n AS_030_000_SYNC_i vpa_sync_0_un0_n \ +# CLK_000_D2_i as_000_int_0_un3_n BGACK_030_INT_i as_000_int_0_un1_n nEXP_SPACE_i \ +# as_000_int_0_un0_n AS_030_i as_000_dma_0_un3_n BGACK_030_INT_D_i \ +# as_000_dma_0_un1_n sm_amiga_i_7__n as_000_dma_0_un0_n \ +# state_machine_un8_clk_000_d2_i_n bg_000_0_un3_n sm_amiga_i_6__n bg_000_0_un1_n \ +# sm_amiga_i_4__n bg_000_0_un0_n CLK_000_D0_i a0_dma_0_un3_n RW_i a0_dma_0_un1_n \ +# UDS_000_i a0_dma_0_un0_n LDS_000_i dtack_sync_0_un3_n DTACK_i dtack_sync_0_un1_n \ +# VMA_INT_i dtack_sync_0_un0_n VPA_i lds_000_int_0_un3_n cpu_est_i_0__n \ +# lds_000_int_0_un1_n sm_amiga_i_3__n lds_000_int_0_un0_n cpu_est_i_3__n \ +# uds_000_int_0_un3_n cpu_est_i_1__n uds_000_int_0_un1_n A0_i uds_000_int_0_un0_n \ +# size_i_1__n fpu_cs_int_0_un3_n a_i_30__n fpu_cs_int_0_un1_n a_i_31__n \ +# fpu_cs_int_0_un0_n a_i_28__n ds_000_dma_0_un3_n a_i_29__n ds_000_dma_0_un1_n \ +# a_i_26__n ds_000_dma_0_un0_n a_i_27__n as_030_000_sync_0_un3_n a_i_24__n \ +# as_030_000_sync_0_un1_n a_i_25__n as_030_000_sync_0_un0_n RST_i \ +# size_dma_0_1__un3_n size_dma_0_1__un1_n CLK_OSZI_i size_dma_0_1__un0_n \ +# size_dma_0_0__un3_n FPU_CS_INT_i size_dma_0_0__un1_n AS_030_c size_dma_0_0__un0_n \ +# bgack_030_int_0_un3_n AS_000_c bgack_030_int_0_un1_n bgack_030_int_0_un0_n \ +# DS_030_c dsack1_int_0_un3_n dsack1_int_0_un1_n UDS_000_c dsack1_int_0_un0_n \ +# state_machine_uds_000_int_5_0_m2_un3_n LDS_000_c \ +# state_machine_uds_000_int_5_0_m2_un1_n state_machine_uds_000_int_5_0_m2_un0_n \ +# size_c_0__n cpu_est_ns_0_0_m2_2__un3_n cpu_est_ns_0_0_m2_2__un1_n size_c_1__n \ +# cpu_est_ns_0_0_m2_2__un0_n amiga_bus_enable_0_un3_n a_c_16__n \ +# amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n a_c_17__n vma_int_0_un3_n \ +# vma_int_0_un1_n a_c_18__n vma_int_0_un0_n ipl_030_0_0__un3_n a_c_19__n \ +# ipl_030_0_0__un1_n ipl_030_0_0__un0_n a_c_20__n ipl_030_0_1__un3_n \ +# ipl_030_0_1__un1_n a_c_21__n ipl_030_0_1__un0_n ipl_030_0_2__un3_n a_c_22__n \ +# ipl_030_0_2__un1_n ipl_030_0_2__un0_n a_c_23__n cpu_estse_0_un3_n \ +# cpu_estse_0_un1_n a_c_24__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_25__n \ +# cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_26__n cpu_estse_2_un3_n cpu_estse_2_un1_n \ +# a_c_27__n cpu_estse_2_un0_n a_c_28__n a_c_29__n a_c_30__n a_c_31__n A0_c nEXP_SPACE_c .model bus68030 -.inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ -nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ -CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \ -A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \ -A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF \ -A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF \ -A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF A_1_.BLIF \ -A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF \ -DSACK_0_.BLIF CLK_000_c.BLIF CLK_OSZI_c.BLIF CLK_OUT_INTreg.BLIF \ -inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF \ -inst_VMA_INTreg.BLIF inst_AS_000_INTreg.BLIF IPL_030DFFSH_1_reg.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF IPL_030DFFSH_2_reg.BLIF \ -inst_VPA_D.BLIF inst_VPA_SYNC.BLIF ipl_c_0__n.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF ipl_c_1__n.BLIF inst_CLK_000_D2.BLIF inst_CLK_000_D6.BLIF \ -ipl_c_2__n.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_6_.BLIF vcc_n_n.BLIF \ -dsack_c_1__n.BLIF gnd_n_n.BLIF inst_UDS_000_INTreg.BLIF DTACK_c.BLIF \ -inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF AS_000_INT_1_sqmuxa.BLIF \ -state_machine_un8_clk_000_d2_n.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF \ -state_machine_un23_clk_000_d0_n.BLIF state_machine_un6_clk_000_d5_n.BLIF \ -RST_c.BLIF inst_CLK_000_D5.BLIF SM_AMIGA_7_.BLIF RESETDFFRHreg.BLIF \ -SM_AMIGA_3_.BLIF state_machine_un6_bgack_000_n.BLIF RW_c.BLIF SM_AMIGA_1_.BLIF \ -inst_DTACK_DMA.BLIF fc_c_0__n.BLIF G_102.BLIF CLK_CNT_N_0_.BLIF fc_c_1__n.BLIF \ -CLK_CNT_N_1_.BLIF G_108.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF CLK_CNT_P_0_.BLIF \ -CLK_CNT_P_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF \ -state_machine_un10_bg_030_n.BLIF cpu_est_ns_0_1__n.BLIF \ -state_machine_un7_as_000_int_n.BLIF N_129_i.BLIF inst_CLK_000_D4.BLIF \ -N_131_i.BLIF state_machine_un15_clk_000_d0_n.BLIF N_221_i.BLIF \ -state_machine_lds_000_int_5_n.BLIF N_222_i.BLIF \ -state_machine_uds_000_int_5_n.BLIF N_63_0.BLIF \ -un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_62_0.BLIF inst_CLK_OUT_PRE.BLIF \ -N_132_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF DS_030_c_i.BLIF \ -N_60_i.BLIF N_59_i.BLIF N_57_i.BLIF N_56_i.BLIF N_55_i.BLIF CLK_000_D1_i.BLIF \ -N_54_i.BLIF N_51_i.BLIF N_50_i.BLIF N_125_i.BLIF N_126_i.BLIF \ -cpu_est_ns_e_0_0__n.BLIF N_85_i.BLIF N_123_i.BLIF N_124_i.BLIF \ -sm_amiga_ns_0_0__n.BLIF cpu_est_0_.BLIF N_122_i.BLIF cpu_est_1_.BLIF \ -N_227_i.BLIF cpu_est_2_.BLIF N_228_i.BLIF cpu_est_3_reg.BLIF \ -cpu_est_ns_0_2__n.BLIF N_226_i.BLIF N_44_i.BLIF N_130_i.BLIF N_225_i.BLIF \ -cpu_est_ns_1__n.BLIF N_158_i.BLIF cpu_est_ns_2__n.BLIF N_219_i.BLIF N_204.BLIF \ -N_220_i.BLIF N_205.BLIF sm_amiga_ns_0_7__n.BLIF N_206.BLIF N_215_i.BLIF \ -N_26.BLIF N_216_i.BLIF N_30.BLIF N_49.BLIF N_95_i.BLIF N_50.BLIF N_214_i.BLIF \ -N_51.BLIF sm_amiga_ns_0_5__n.BLIF N_54.BLIF N_94_i.BLIF N_55.BLIF N_133_i.BLIF \ -N_56.BLIF N_57.BLIF N_87_i.BLIF N_59.BLIF N_60.BLIF N_86_i.BLIF N_62.BLIF \ -N_63.BLIF N_83_i.BLIF N_68.BLIF N_70.BLIF N_82_i.BLIF N_72.BLIF \ -state_machine_lds_000_int_5_0_n.BLIF N_73.BLIF \ -state_machine_uds_000_int_5_0_n.BLIF N_74.BLIF N_80_i.BLIF N_76.BLIF \ -N_30_0.BLIF N_78.BLIF N_26_0.BLIF N_80.BLIF N_76_i.BLIF N_82.BLIF N_206_0.BLIF \ -N_83.BLIF N_205_0.BLIF N_85.BLIF N_72_i.BLIF N_86.BLIF N_73_i.BLIF N_87.BLIF \ -state_machine_un15_clk_000_d0_0_n.BLIF N_94.BLIF N_204_0.BLIF N_95.BLIF \ -BG_030_c_i.BLIF N_214.BLIF N_70_i.BLIF N_215.BLIF \ -state_machine_un10_bg_030_0_n.BLIF N_216.BLIF \ -state_machine_un6_bgack_000_0_n.BLIF N_219.BLIF N_220.BLIF \ -state_machine_un23_clk_000_d0_0_n.BLIF N_221.BLIF N_236_1.BLIF N_222.BLIF \ -N_236_2.BLIF N_225.BLIF N_236_3.BLIF N_226.BLIF N_236_4.BLIF N_227.BLIF \ -N_236_5.BLIF N_228.BLIF N_236_6.BLIF N_122.BLIF N_239_1.BLIF N_123.BLIF \ -N_239_2.BLIF N_124.BLIF state_machine_un8_clk_000_d2_1_n.BLIF N_125.BLIF \ -N_55_i_1.BLIF N_126.BLIF N_55_i_2.BLIF N_129.BLIF N_55_i_3.BLIF N_130.BLIF \ -N_55_i_4.BLIF N_131.BLIF N_55_i_5.BLIF N_132.BLIF cpu_est_ns_0_1_1__n.BLIF \ -N_133.BLIF cpu_est_ns_0_2_1__n.BLIF N_236.BLIF N_80_1.BLIF N_239.BLIF \ -N_80_2.BLIF RW_i.BLIF N_78_1.BLIF VMA_INT_i.BLIF N_78_2.BLIF VPA_D_i.BLIF \ -N_74_1.BLIF DTACK_i.BLIF N_74_2.BLIF CLK_000_D0_i.BLIF N_74_3.BLIF \ -sm_amiga_i_4__n.BLIF N_70_1.BLIF cpu_est_i_3__n.BLIF N_70_2.BLIF \ -sm_amiga_i_1__n.BLIF sm_amiga_ns_0_1_0__n.BLIF \ -state_machine_un6_clk_000_d5_i_n.BLIF cpu_est_ns_0_1_2__n.BLIF \ -sm_amiga_i_6__n.BLIF N_226_1.BLIF nEXP_SPACE_i.BLIF N_220_1.BLIF \ -AS_000_INT_i.BLIF N_82_1.BLIF cpu_est_i_1__n.BLIF N_73_1.BLIF \ -cpu_est_i_0__n.BLIF N_72_1.BLIF AMIGA_BUS_ENABLE_i.BLIF \ -state_machine_uds_000_int_5_0_m2_un3_n.BLIF AS_030_i.BLIF \ -state_machine_uds_000_int_5_0_m2_un1_n.BLIF cpu_est_i_2__n.BLIF \ -state_machine_uds_000_int_5_0_m2_un0_n.BLIF sm_amiga_i_2__n.BLIF \ -vpa_sync_0_un3_n.BLIF sm_amiga_i_3__n.BLIF vpa_sync_0_un1_n.BLIF \ -sm_amiga_i_5__n.BLIF vpa_sync_0_un0_n.BLIF \ -state_machine_un8_clk_000_d2_i_n.BLIF vma_int_0_un3_n.BLIF \ -sm_amiga_i_7__n.BLIF vma_int_0_un1_n.BLIF a_i_0__n.BLIF vma_int_0_un0_n.BLIF \ -size_i_1__n.BLIF bg_000_0_un3_n.BLIF dsack_i_1__n.BLIF bg_000_0_un1_n.BLIF \ -BGACK_030_INT_i.BLIF bg_000_0_un0_n.BLIF CLK_000_D2_i.BLIF \ -bgack_030_int_0_un3_n.BLIF AS_030_000_SYNC_i.BLIF bgack_030_int_0_un1_n.BLIF \ -a_i_19__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_16__n.BLIF \ -as_000_int_0_un3_n.BLIF a_i_18__n.BLIF as_000_int_0_un1_n.BLIF a_i_30__n.BLIF \ -as_000_int_0_un0_n.BLIF a_i_31__n.BLIF ipl_030_0_0__un3_n.BLIF a_i_28__n.BLIF \ -ipl_030_0_0__un1_n.BLIF a_i_29__n.BLIF ipl_030_0_0__un0_n.BLIF a_i_26__n.BLIF \ -ipl_030_0_1__un3_n.BLIF a_i_27__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_24__n.BLIF \ -ipl_030_0_1__un0_n.BLIF a_i_25__n.BLIF ipl_030_0_2__un3_n.BLIF RST_i.BLIF \ -ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF cpu_estse_0_un3_n.BLIF \ -CLK_OSZI_i.BLIF cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF N_74_i.BLIF \ -cpu_estse_1_un3_n.BLIF N_78_i.BLIF cpu_estse_1_un1_n.BLIF FPU_CS_INT_i.BLIF \ -cpu_estse_1_un0_n.BLIF CLK_000_D6_i.BLIF cpu_estse_2_un3_n.BLIF AS_030_c.BLIF \ -cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ -DS_030_c.BLIF as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ -dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF size_c_0__n.BLIF \ -dtack_sync_0_un0_n.BLIF fpu_cs_int_0_un3_n.BLIF size_c_1__n.BLIF \ -fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF a_c_0__n.BLIF \ -dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF \ -amiga_bus_enable_0_un3_n.BLIF amiga_bus_enable_0_un1_n.BLIF \ -amiga_bus_enable_0_un0_n.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF \ -lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_15__n.BLIF a_14__n.BLIF \ -a_13__n.BLIF a_c_16__n.BLIF a_12__n.BLIF a_c_17__n.BLIF a_11__n.BLIF \ -a_c_18__n.BLIF a_10__n.BLIF a_c_19__n.BLIF a_9__n.BLIF a_c_20__n.BLIF \ -a_8__n.BLIF a_c_21__n.BLIF a_7__n.BLIF a_c_22__n.BLIF a_6__n.BLIF \ -a_c_23__n.BLIF a_5__n.BLIF a_c_24__n.BLIF a_4__n.BLIF a_c_25__n.BLIF \ -a_3__n.BLIF a_c_26__n.BLIF a_2__n.BLIF a_c_27__n.BLIF a_1__n.BLIF \ -a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF nEXP_SPACE_c.BLIF \ -BG_030_c.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF \ -DSACK_1_.PIN.BLIF DTACK.PIN.BLIF -.outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ -CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C \ -cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D \ -cpu_est_3_reg.C cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \ -SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \ -SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \ -SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ -SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_N_0_.D CLK_CNT_N_0_.C \ +.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ +BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \ +RW.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF \ +A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF \ +A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF \ +DSACK_1_.BLIF AS_030.BLIF AS_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF \ +A0.BLIF DTACK.BLIF SIZE_0_.BLIF DSACK_0_.BLIF BG_030_c.BLIF \ +BG_000DFFSHreg.BLIF BGACK_000_c.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_FPU_CS_INTreg.BLIF CLK_030_c.BLIF inst_VMA_INTreg.BLIF \ +inst_AS_030_000_SYNC.BLIF CLK_000_c.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_DTACK_SYNC.BLIF CLK_OSZI_c.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \ +inst_CLK_000_D1.BLIF CLK_OUT_INTreg.BLIF inst_CLK_000_D2.BLIF \ +inst_CLK_000_D6.BLIF SM_AMIGA_5_.BLIF IPL_030DFFSH_0_reg.BLIF vcc_n_n.BLIF \ +gnd_n_n.BLIF IPL_030DFFSH_1_reg.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF \ +IPL_030DFFSH_2_reg.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \ +ipl_c_0__n.BLIF inst_DSACK1_INT.BLIF inst_CLK_000_D3.BLIF ipl_c_1__n.BLIF \ +state_machine_un23_clk_000_d0_n.BLIF inst_CLK_000_D5.BLIF ipl_c_2__n.BLIF \ +SM_AMIGA_3_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_1_.BLIF dsack_c_1__n.BLIF \ +inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF DTACK_c.BLIF SIZE_DMA_0_.BLIF \ +SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF G_103.BLIF CLK_CNT_N_0_.BLIF VPA_c.BLIF \ +CLK_CNT_N_1_.BLIF G_109.BLIF CLK_CNT_P_0_.BLIF RST_c.BLIF CLK_CNT_P_1_.BLIF \ +inst_CLK_000_D4.BLIF RESETDFFRHreg.BLIF SM_AMIGA_7_.BLIF \ +state_machine_un15_clk_000_d0_n.BLIF RW_c.BLIF SM_AMIGA_4_.BLIF \ +un1_AMIGA_BUS_ENABLE_0_sqmuxa_2.BLIF fc_c_0__n.BLIF inst_CLK_OUT_PRE.BLIF \ +SM_AMIGA_2_.BLIF fc_c_1__n.BLIF AMIGA_BUS_ENABLEDFFSHreg.BLIF \ +state_machine_un23_clk_000_d0_0_n.BLIF state_machine_un6_bgack_000_0_n.BLIF \ +N_214_0.BLIF BG_030_c_i.BLIF N_227_i.BLIF state_machine_un10_bg_030_0_n.BLIF \ +N_215_0.BLIF N_216_0.BLIF N_126_i.BLIF N_33_0.BLIF N_127_i.BLIF N_35_0.BLIF \ +state_machine_uds_000_int_5_0_n.BLIF N_130_i.BLIF \ +state_machine_lds_000_int_5_0_n.BLIF N_132_i.BLIF N_131_i.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF N_133_i.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_134_i.BLIF \ +N_137_i.BLIF N_138_i.BLIF sm_amiga_ns_0_5__n.BLIF cpu_est_ns_1__n.BLIF \ +N_139_i.BLIF cpu_est_ns_2__n.BLIF N_140_i.BLIF N_46_0.BLIF N_52.BLIF \ +N_142_i.BLIF N_59.BLIF N_141_i.BLIF N_62.BLIF sm_amiga_ns_0_7__n.BLIF \ +N_65.BLIF N_144_i.BLIF N_67.BLIF state_machine_ds_000_dma_5_0_n.BLIF N_72.BLIF \ +CLK_030_c_i.BLIF N_77.BLIF AS_000_c_i.BLIF N_88.BLIF N_59_i.BLIF N_217.BLIF \ +N_61_0.BLIF N_219.BLIF N_62_i.BLIF N_221.BLIF CLK_000_D1_i.BLIF N_224.BLIF \ +N_65_i.BLIF N_225.BLIF N_66_i.BLIF N_226.BLIF N_67_i.BLIF N_128.BLIF \ +N_175_i.BLIF N_130.BLIF un1_as_000_dma5_i_0__n.BLIF N_132.BLIF \ +state_machine_un6_clk_000_d5_i_n.BLIF N_135.BLIF N_71_i.BLIF N_136.BLIF \ +DS_030_c_i.BLIF N_138.BLIF N_73_i.BLIF N_143.BLIF N_156_i.BLIF N_145.BLIF \ +un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i.BLIF N_146.BLIF N_75_0.BLIF N_147.BLIF \ +N_176_i.BLIF N_148.BLIF N_52_0.BLIF N_151.BLIF N_173_i.BLIF N_153.BLIF \ +N_226_i.BLIF N_154.BLIF N_77_0.BLIF N_155.BLIF N_72_i.BLIF N_173.BLIF \ +N_147_i.BLIF cpu_est_ns_0_0_x2_1_.BLIF N_148_i.BLIF \ +AMIGA_BUS_DATA_DIR_m1_0_x2.BLIF cpu_est_ns_e_0_0__n.BLIF N_228_1.BLIF \ +N_146_i.BLIF N_237.BLIF sm_amiga_ns_0_0__n.BLIF N_247.BLIF N_88_i.BLIF \ +N_227.BLIF N_145_i.BLIF N_228.BLIF cpu_est_ns_0_2__n.BLIF N_127.BLIF \ +N_143_i.BLIF N_66.BLIF N_154_i.BLIF N_175.BLIF N_161_i.BLIF N_176.BLIF \ +N_153_i.BLIF N_75.BLIF N_155_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_4.BLIF \ +cpu_est_ns_0_1__n.BLIF N_61.BLIF N_135_i.BLIF N_156.BLIF N_136_i.BLIF \ +N_73.BLIF N_57.BLIF N_225_i.BLIF N_71.BLIF \ +un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0.BLIF state_machine_un6_clk_000_d5_n.BLIF \ +N_219_i.BLIF un1_as_000_dma5_0__n.BLIF N_221_i.BLIF N_223.BLIF \ +state_machine_un15_clk_000_d0_0_n.BLIF state_machine_ds_000_dma_5_n.BLIF \ +N_144.BLIF N_66_i_1.BLIF N_141.BLIF N_66_i_2.BLIF N_142.BLIF N_66_i_3.BLIF \ +N_139.BLIF N_66_i_4.BLIF N_140.BLIF N_66_i_5.BLIF N_137.BLIF N_237_1.BLIF \ +N_134.BLIF N_237_2.BLIF N_133.BLIF N_247_1.BLIF N_131.BLIF N_247_2.BLIF \ +state_machine_lds_000_int_5_n.BLIF N_247_3.BLIF \ +state_machine_uds_000_int_5_n.BLIF N_247_4.BLIF N_35.BLIF N_247_5.BLIF \ +N_33.BLIF N_247_6.BLIF N_126.BLIF N_52_0_1.BLIF N_216.BLIF N_52_0_2.BLIF \ +N_215.BLIF N_224_1.BLIF state_machine_un10_bg_030_n.BLIF N_224_2.BLIF \ +N_214.BLIF N_227_1.BLIF state_machine_un6_bgack_000_n.BLIF N_227_2.BLIF \ +state_machine_un8_clk_000_d2_n.BLIF N_228_1_0.BLIF SIZE_DMA_1_sqmuxa.BLIF \ +N_127_1.BLIF SIZE_DMA_0_sqmuxa.BLIF N_127_2.BLIF AS_000_INT_1_sqmuxa.BLIF \ +N_151_1.BLIF N_249.BLIF SIZE_DMA_1_sqmuxa_1.BLIF CLK_000_D6_i.BLIF \ +state_machine_un8_clk_000_d2_1_n.BLIF N_228_i.BLIF sm_amiga_ns_0_1_0__n.BLIF \ +sm_amiga_i_5__n.BLIF cpu_est_ns_0_1_1__n.BLIF N_224_i.BLIF N_138_1.BLIF \ +N_223_i.BLIF N_130_1.BLIF SIZE_DMA_0_sqmuxa_i.BLIF N_128_1.BLIF \ +SIZE_DMA_1_sqmuxa_i.BLIF N_221_1.BLIF a_i_18__n.BLIF N_219_1.BLIF \ +a_i_16__n.BLIF vpa_sync_0_un3_n.BLIF a_i_19__n.BLIF vpa_sync_0_un1_n.BLIF \ +AS_030_000_SYNC_i.BLIF vpa_sync_0_un0_n.BLIF CLK_000_D2_i.BLIF \ +as_000_int_0_un3_n.BLIF BGACK_030_INT_i.BLIF as_000_int_0_un1_n.BLIF \ +nEXP_SPACE_i.BLIF as_000_int_0_un0_n.BLIF AS_030_i.BLIF \ +as_000_dma_0_un3_n.BLIF BGACK_030_INT_D_i.BLIF as_000_dma_0_un1_n.BLIF \ +sm_amiga_i_7__n.BLIF as_000_dma_0_un0_n.BLIF \ +state_machine_un8_clk_000_d2_i_n.BLIF bg_000_0_un3_n.BLIF sm_amiga_i_6__n.BLIF \ +bg_000_0_un1_n.BLIF sm_amiga_i_4__n.BLIF bg_000_0_un0_n.BLIF CLK_000_D0_i.BLIF \ +a0_dma_0_un3_n.BLIF RW_i.BLIF a0_dma_0_un1_n.BLIF UDS_000_i.BLIF \ +a0_dma_0_un0_n.BLIF LDS_000_i.BLIF dtack_sync_0_un3_n.BLIF DTACK_i.BLIF \ +dtack_sync_0_un1_n.BLIF VMA_INT_i.BLIF dtack_sync_0_un0_n.BLIF VPA_i.BLIF \ +lds_000_int_0_un3_n.BLIF cpu_est_i_0__n.BLIF lds_000_int_0_un1_n.BLIF \ +sm_amiga_i_3__n.BLIF lds_000_int_0_un0_n.BLIF cpu_est_i_3__n.BLIF \ +uds_000_int_0_un3_n.BLIF cpu_est_i_1__n.BLIF uds_000_int_0_un1_n.BLIF \ +A0_i.BLIF uds_000_int_0_un0_n.BLIF size_i_1__n.BLIF fpu_cs_int_0_un3_n.BLIF \ +a_i_30__n.BLIF fpu_cs_int_0_un1_n.BLIF a_i_31__n.BLIF fpu_cs_int_0_un0_n.BLIF \ +a_i_28__n.BLIF ds_000_dma_0_un3_n.BLIF a_i_29__n.BLIF ds_000_dma_0_un1_n.BLIF \ +a_i_26__n.BLIF ds_000_dma_0_un0_n.BLIF a_i_27__n.BLIF \ +as_030_000_sync_0_un3_n.BLIF a_i_24__n.BLIF as_030_000_sync_0_un1_n.BLIF \ +a_i_25__n.BLIF as_030_000_sync_0_un0_n.BLIF RST_i.BLIF \ +size_dma_0_1__un3_n.BLIF size_dma_0_1__un1_n.BLIF CLK_OSZI_i.BLIF \ +size_dma_0_1__un0_n.BLIF size_dma_0_0__un3_n.BLIF FPU_CS_INT_i.BLIF \ +size_dma_0_0__un1_n.BLIF AS_030_c.BLIF size_dma_0_0__un0_n.BLIF \ +bgack_030_int_0_un3_n.BLIF AS_000_c.BLIF bgack_030_int_0_un1_n.BLIF \ +bgack_030_int_0_un0_n.BLIF DS_030_c.BLIF dsack1_int_0_un3_n.BLIF \ +dsack1_int_0_un1_n.BLIF UDS_000_c.BLIF dsack1_int_0_un0_n.BLIF \ +state_machine_uds_000_int_5_0_m2_un3_n.BLIF LDS_000_c.BLIF \ +state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ +state_machine_uds_000_int_5_0_m2_un0_n.BLIF size_c_0__n.BLIF \ +cpu_est_ns_0_0_m2_2__un3_n.BLIF cpu_est_ns_0_0_m2_2__un1_n.BLIF \ +size_c_1__n.BLIF cpu_est_ns_0_0_m2_2__un0_n.BLIF amiga_bus_enable_0_un3_n.BLIF \ +a_c_16__n.BLIF amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF \ +a_c_17__n.BLIF vma_int_0_un3_n.BLIF vma_int_0_un1_n.BLIF a_c_18__n.BLIF \ +vma_int_0_un0_n.BLIF ipl_030_0_0__un3_n.BLIF a_c_19__n.BLIF \ +ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF a_c_20__n.BLIF \ +ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF a_c_21__n.BLIF \ +ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF a_c_22__n.BLIF \ +ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF a_c_23__n.BLIF \ +cpu_estse_0_un3_n.BLIF cpu_estse_0_un1_n.BLIF a_c_24__n.BLIF \ +cpu_estse_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF a_c_25__n.BLIF \ +cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF a_c_26__n.BLIF \ +cpu_estse_2_un3_n.BLIF cpu_estse_2_un1_n.BLIF a_c_27__n.BLIF \ +cpu_estse_2_un0_n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF \ +a_c_31__n.BLIF A0_c.BLIF nEXP_SPACE_c.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ +DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ +SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +.outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ +AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR \ +cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C \ +cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR SM_AMIGA_4_.D \ +SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \ +SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_P_1_.D \ +CLK_CNT_P_1_.C CLK_CNT_P_1_.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP \ +SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP IPL_030DFFSH_0_reg.D \ +IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ +IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ +IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ +SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \ +SM_AMIGA_5_.C SM_AMIGA_5_.AR inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ +inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_VMA_INTreg.D \ +inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP CLK_CNT_N_0_.D CLK_CNT_N_0_.C \ CLK_CNT_N_0_.AR CLK_CNT_N_1_.D CLK_CNT_N_1_.C CLK_CNT_N_1_.AP CLK_CNT_P_0_.D \ -CLK_CNT_P_0_.C CLK_CNT_P_0_.AR CLK_CNT_P_1_.D CLK_CNT_P_1_.C CLK_CNT_P_1_.AR \ -IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ -IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ -IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D \ -SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ -inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP \ -inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP \ -inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_VMA_INTreg.D \ -inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ -BG_000DFFSHreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ -inst_BGACK_030_INTreg.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C \ -inst_AS_000_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \ -inst_CLK_OUT_PRE.AR CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR \ -inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ -inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D \ -inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C \ -DSACK_INT_1_.AP AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C \ -inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_CLK_000_D5.D \ -inst_CLK_000_D5.C inst_CLK_000_D5.AP inst_CLK_000_D6.D inst_CLK_000_D6.C \ -inst_CLK_000_D6.AP inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP \ -inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D3.D \ -inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \ +CLK_CNT_P_0_.C CLK_CNT_P_0_.AR inst_LDS_000_INT.D inst_LDS_000_INT.C \ +inst_LDS_000_INT.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP \ +inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ +BG_000DFFSHreg.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \ +AMIGA_BUS_ENABLEDFFSHreg.D AMIGA_BUS_ENABLEDFFSHreg.C \ +AMIGA_BUS_ENABLEDFFSHreg.AP inst_AS_000_INT.D inst_AS_000_INT.C \ +inst_AS_000_INT.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_AS_030_000_SYNC.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP \ +inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \ +inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP CLK_OUT_INTreg.D \ +CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \ +inst_CLK_OUT_PRE.AR inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_000_D5.AP \ +inst_CLK_000_D6.D inst_CLK_000_D6.C inst_CLK_000_D6.AP inst_CLK_000_D4.D \ +inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_CLK_000_D2.D inst_CLK_000_D2.C \ +inst_CLK_000_D2.AP inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP \ +inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP \ inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP RESETDFFRHreg.D \ RESETDFFRHreg.C RESETDFFRHreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C \ -inst_CLK_000_D1.AP DSACK_1_ DTACK DSACK_0_ CLK_000_c CLK_OSZI_c ipl_c_0__n \ -ipl_c_1__n ipl_c_2__n vcc_n_n dsack_c_1__n gnd_n_n DTACK_c AS_000_INT_1_sqmuxa \ -state_machine_un8_clk_000_d2_n state_machine_un23_clk_000_d0_n \ -state_machine_un6_clk_000_d5_n RST_c state_machine_un6_bgack_000_n RW_c \ -fc_c_0__n fc_c_1__n state_machine_un10_bg_030_n cpu_est_ns_0_1__n \ -state_machine_un7_as_000_int_n N_129_i N_131_i state_machine_un15_clk_000_d0_n \ -N_221_i state_machine_lds_000_int_5_n N_222_i state_machine_uds_000_int_5_n \ -N_63_0 un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_62_0 N_132_i \ -un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_60_i N_59_i N_57_i N_56_i \ -N_55_i CLK_000_D1_i N_54_i N_51_i N_50_i N_125_i N_126_i cpu_est_ns_e_0_0__n \ -N_85_i N_123_i N_124_i sm_amiga_ns_0_0__n N_122_i N_227_i N_228_i \ -cpu_est_ns_0_2__n N_226_i N_44_i N_130_i N_225_i cpu_est_ns_1__n N_158_i \ -cpu_est_ns_2__n N_219_i N_204 N_220_i N_205 sm_amiga_ns_0_7__n N_206 N_215_i \ -N_26 N_216_i N_30 N_49 N_95_i N_50 N_214_i N_51 sm_amiga_ns_0_5__n N_54 N_94_i \ -N_55 N_133_i N_56 N_57 N_87_i N_59 N_60 N_86_i N_62 N_63 N_83_i N_68 N_70 \ -N_82_i N_72 state_machine_lds_000_int_5_0_n N_73 \ -state_machine_uds_000_int_5_0_n N_74 N_80_i N_76 N_30_0 N_78 N_26_0 N_80 \ -N_76_i N_82 N_206_0 N_83 N_205_0 N_85 N_72_i N_86 N_73_i N_87 \ -state_machine_un15_clk_000_d0_0_n N_94 N_204_0 N_95 BG_030_c_i N_214 N_70_i \ -N_215 state_machine_un10_bg_030_0_n N_216 state_machine_un6_bgack_000_0_n \ -N_219 N_220 state_machine_un23_clk_000_d0_0_n N_221 N_236_1 N_222 N_236_2 \ -N_225 N_236_3 N_226 N_236_4 N_227 N_236_5 N_228 N_236_6 N_122 N_239_1 N_123 \ -N_239_2 N_124 state_machine_un8_clk_000_d2_1_n N_125 N_55_i_1 N_126 N_55_i_2 \ -N_129 N_55_i_3 N_130 N_55_i_4 N_131 N_55_i_5 N_132 cpu_est_ns_0_1_1__n N_133 \ -cpu_est_ns_0_2_1__n N_236 N_80_1 N_239 N_80_2 RW_i N_78_1 VMA_INT_i N_78_2 \ -VPA_D_i N_74_1 DTACK_i N_74_2 CLK_000_D0_i N_74_3 sm_amiga_i_4__n N_70_1 \ -cpu_est_i_3__n N_70_2 sm_amiga_i_1__n sm_amiga_ns_0_1_0__n \ -state_machine_un6_clk_000_d5_i_n cpu_est_ns_0_1_2__n sm_amiga_i_6__n N_226_1 \ -nEXP_SPACE_i N_220_1 AS_000_INT_i N_82_1 cpu_est_i_1__n N_73_1 cpu_est_i_0__n \ -N_72_1 AMIGA_BUS_ENABLE_i state_machine_uds_000_int_5_0_m2_un3_n AS_030_i \ -state_machine_uds_000_int_5_0_m2_un1_n cpu_est_i_2__n \ -state_machine_uds_000_int_5_0_m2_un0_n sm_amiga_i_2__n vpa_sync_0_un3_n \ -sm_amiga_i_3__n vpa_sync_0_un1_n sm_amiga_i_5__n vpa_sync_0_un0_n \ -state_machine_un8_clk_000_d2_i_n vma_int_0_un3_n sm_amiga_i_7__n \ -vma_int_0_un1_n a_i_0__n vma_int_0_un0_n size_i_1__n bg_000_0_un3_n \ -dsack_i_1__n bg_000_0_un1_n BGACK_030_INT_i bg_000_0_un0_n CLK_000_D2_i \ -bgack_030_int_0_un3_n AS_030_000_SYNC_i bgack_030_int_0_un1_n a_i_19__n \ -bgack_030_int_0_un0_n a_i_16__n as_000_int_0_un3_n a_i_18__n \ -as_000_int_0_un1_n a_i_30__n as_000_int_0_un0_n a_i_31__n ipl_030_0_0__un3_n \ -a_i_28__n ipl_030_0_0__un1_n a_i_29__n ipl_030_0_0__un0_n a_i_26__n \ -ipl_030_0_1__un3_n a_i_27__n ipl_030_0_1__un1_n a_i_24__n ipl_030_0_1__un0_n \ -a_i_25__n ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n ipl_030_0_2__un0_n \ -cpu_estse_0_un3_n CLK_OSZI_i cpu_estse_0_un1_n cpu_estse_0_un0_n N_74_i \ -cpu_estse_1_un3_n N_78_i cpu_estse_1_un1_n FPU_CS_INT_i cpu_estse_1_un0_n \ -CLK_000_D6_i cpu_estse_2_un3_n AS_030_c cpu_estse_2_un1_n cpu_estse_2_un0_n \ -as_030_000_sync_0_un3_n DS_030_c as_030_000_sync_0_un1_n \ -as_030_000_sync_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n size_c_0__n \ -dtack_sync_0_un0_n fpu_cs_int_0_un3_n size_c_1__n fpu_cs_int_0_un1_n \ -fpu_cs_int_0_un0_n a_c_0__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n \ -dsack_int_0_1__un0_n amiga_bus_enable_0_un3_n amiga_bus_enable_0_un1_n \ -amiga_bus_enable_0_un0_n uds_000_int_0_un3_n uds_000_int_0_un1_n \ -uds_000_int_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n \ -lds_000_int_0_un0_n a_15__n a_14__n a_13__n a_c_16__n a_12__n a_c_17__n \ -a_11__n a_c_18__n a_10__n a_c_19__n a_9__n a_c_20__n a_8__n a_c_21__n a_7__n \ -a_c_22__n a_6__n a_c_23__n a_5__n a_c_24__n a_4__n a_c_25__n a_3__n a_c_26__n \ -a_2__n a_c_27__n a_1__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c \ -BG_030_c BGACK_000_c CLK_030_c DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE \ -LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE G_102 G_108 +inst_CLK_000_D1.AP SIZE_1_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 \ +DTACK SIZE_0_ DSACK_0_ BG_030_c BGACK_000_c CLK_030_c CLK_000_c CLK_OSZI_c \ +vcc_n_n gnd_n_n ipl_c_0__n ipl_c_1__n state_machine_un23_clk_000_d0_n \ +ipl_c_2__n dsack_c_1__n DTACK_c VPA_c RST_c state_machine_un15_clk_000_d0_n \ +RW_c un1_AMIGA_BUS_ENABLE_0_sqmuxa_2 fc_c_0__n fc_c_1__n \ +state_machine_un23_clk_000_d0_0_n state_machine_un6_bgack_000_0_n N_214_0 \ +BG_030_c_i N_227_i state_machine_un10_bg_030_0_n N_215_0 N_216_0 N_126_i \ +N_33_0 N_127_i N_35_0 state_machine_uds_000_int_5_0_n N_130_i \ +state_machine_lds_000_int_5_0_n N_132_i N_131_i N_133_i N_134_i N_137_i \ +N_138_i sm_amiga_ns_0_5__n cpu_est_ns_1__n N_139_i cpu_est_ns_2__n N_140_i \ +N_46_0 N_52 N_142_i N_59 N_141_i N_62 sm_amiga_ns_0_7__n N_65 N_144_i N_67 \ +state_machine_ds_000_dma_5_0_n N_72 CLK_030_c_i N_77 AS_000_c_i N_88 N_59_i \ +N_217 N_61_0 N_219 N_62_i N_221 CLK_000_D1_i N_224 N_65_i N_225 N_66_i N_226 \ +N_67_i N_128 N_175_i N_130 un1_as_000_dma5_i_0__n N_132 \ +state_machine_un6_clk_000_d5_i_n N_135 N_71_i N_136 DS_030_c_i N_138 N_73_i \ +N_143 N_156_i N_145 un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i N_146 N_75_0 N_147 \ +N_176_i N_148 N_52_0 N_151 N_173_i N_153 N_226_i N_154 N_77_0 N_155 N_72_i \ +N_173 N_147_i N_148_i cpu_est_ns_e_0_0__n N_228_1 N_146_i N_237 \ +sm_amiga_ns_0_0__n N_247 N_88_i N_227 N_145_i N_228 cpu_est_ns_0_2__n N_127 \ +N_143_i N_66 N_154_i N_175 N_161_i N_176 N_153_i N_75 N_155_i \ +un1_AMIGA_BUS_ENABLE_1_sqmuxa_4 cpu_est_ns_0_1__n N_61 N_135_i N_156 N_136_i \ +N_73 N_57 N_225_i N_71 un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0 \ +state_machine_un6_clk_000_d5_n N_219_i un1_as_000_dma5_0__n N_221_i N_223 \ +state_machine_un15_clk_000_d0_0_n state_machine_ds_000_dma_5_n N_144 N_66_i_1 \ +N_141 N_66_i_2 N_142 N_66_i_3 N_139 N_66_i_4 N_140 N_66_i_5 N_137 N_237_1 \ +N_134 N_237_2 N_133 N_247_1 N_131 N_247_2 state_machine_lds_000_int_5_n \ +N_247_3 state_machine_uds_000_int_5_n N_247_4 N_35 N_247_5 N_33 N_247_6 N_126 \ +N_52_0_1 N_216 N_52_0_2 N_215 N_224_1 state_machine_un10_bg_030_n N_224_2 \ +N_214 N_227_1 state_machine_un6_bgack_000_n N_227_2 \ +state_machine_un8_clk_000_d2_n N_228_1_0 SIZE_DMA_1_sqmuxa N_127_1 \ +SIZE_DMA_0_sqmuxa N_127_2 AS_000_INT_1_sqmuxa N_151_1 N_249 \ +SIZE_DMA_1_sqmuxa_1 CLK_000_D6_i state_machine_un8_clk_000_d2_1_n N_228_i \ +sm_amiga_ns_0_1_0__n sm_amiga_i_5__n cpu_est_ns_0_1_1__n N_224_i N_138_1 \ +N_223_i N_130_1 SIZE_DMA_0_sqmuxa_i N_128_1 SIZE_DMA_1_sqmuxa_i N_221_1 \ +a_i_18__n N_219_1 a_i_16__n vpa_sync_0_un3_n a_i_19__n vpa_sync_0_un1_n \ +AS_030_000_SYNC_i vpa_sync_0_un0_n CLK_000_D2_i as_000_int_0_un3_n \ +BGACK_030_INT_i as_000_int_0_un1_n nEXP_SPACE_i as_000_int_0_un0_n AS_030_i \ +as_000_dma_0_un3_n BGACK_030_INT_D_i as_000_dma_0_un1_n sm_amiga_i_7__n \ +as_000_dma_0_un0_n state_machine_un8_clk_000_d2_i_n bg_000_0_un3_n \ +sm_amiga_i_6__n bg_000_0_un1_n sm_amiga_i_4__n bg_000_0_un0_n CLK_000_D0_i \ +a0_dma_0_un3_n RW_i a0_dma_0_un1_n UDS_000_i a0_dma_0_un0_n LDS_000_i \ +dtack_sync_0_un3_n DTACK_i dtack_sync_0_un1_n VMA_INT_i dtack_sync_0_un0_n \ +VPA_i lds_000_int_0_un3_n cpu_est_i_0__n lds_000_int_0_un1_n sm_amiga_i_3__n \ +lds_000_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n cpu_est_i_1__n \ +uds_000_int_0_un1_n A0_i uds_000_int_0_un0_n size_i_1__n fpu_cs_int_0_un3_n \ +a_i_30__n fpu_cs_int_0_un1_n a_i_31__n fpu_cs_int_0_un0_n a_i_28__n \ +ds_000_dma_0_un3_n a_i_29__n ds_000_dma_0_un1_n a_i_26__n ds_000_dma_0_un0_n \ +a_i_27__n as_030_000_sync_0_un3_n a_i_24__n as_030_000_sync_0_un1_n a_i_25__n \ +as_030_000_sync_0_un0_n RST_i size_dma_0_1__un3_n size_dma_0_1__un1_n \ +CLK_OSZI_i size_dma_0_1__un0_n size_dma_0_0__un3_n FPU_CS_INT_i \ +size_dma_0_0__un1_n AS_030_c size_dma_0_0__un0_n bgack_030_int_0_un3_n \ +AS_000_c bgack_030_int_0_un1_n bgack_030_int_0_un0_n DS_030_c \ +dsack1_int_0_un3_n dsack1_int_0_un1_n UDS_000_c dsack1_int_0_un0_n \ +state_machine_uds_000_int_5_0_m2_un3_n LDS_000_c \ +state_machine_uds_000_int_5_0_m2_un1_n state_machine_uds_000_int_5_0_m2_un0_n \ +size_c_0__n cpu_est_ns_0_0_m2_2__un3_n cpu_est_ns_0_0_m2_2__un1_n size_c_1__n \ +cpu_est_ns_0_0_m2_2__un0_n amiga_bus_enable_0_un3_n a_c_16__n \ +amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n a_c_17__n vma_int_0_un3_n \ +vma_int_0_un1_n a_c_18__n vma_int_0_un0_n ipl_030_0_0__un3_n a_c_19__n \ +ipl_030_0_0__un1_n ipl_030_0_0__un0_n a_c_20__n ipl_030_0_1__un3_n \ +ipl_030_0_1__un1_n a_c_21__n ipl_030_0_1__un0_n ipl_030_0_2__un3_n a_c_22__n \ +ipl_030_0_2__un1_n ipl_030_0_2__un0_n a_c_23__n cpu_estse_0_un3_n \ +cpu_estse_0_un1_n a_c_24__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_25__n \ +cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_26__n cpu_estse_2_un3_n \ +cpu_estse_2_un1_n a_c_27__n cpu_estse_2_un0_n a_c_28__n a_c_29__n a_c_30__n \ +a_c_31__n A0_c nEXP_SPACE_c AS_030.OE AS_000.OE DS_030.OE UDS_000.OE \ +LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK_1_.OE DTACK.OE BERR.OE \ +DSACK_0_.OE AVEC_EXP.OE CIIN.OE G_103 G_109 cpu_est_ns_0_0_x2_1_ \ +AMIGA_BUS_DATA_DIR_m1_0_x2 .names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 @@ -277,22 +312,22 @@ LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE G_102 G_108 -1 1 .names cpu_est_ns_e_0_0__n.BLIF cpu_est_0_.D 0 1 -.names inst_CLK_000_D0.BLIF N_86_i.BLIF SM_AMIGA_5_.D +.names CLK_000_D0_i.BLIF N_134_i.BLIF SM_AMIGA_4_.D 11 1 -.names CLK_000_D0_i.BLIF N_87_i.BLIF SM_AMIGA_4_.D -11 1 -.names N_94_i.BLIF N_133_i.BLIF SM_AMIGA_3_.D +.names N_135_i.BLIF N_136_i.BLIF SM_AMIGA_3_.D 11 1 .names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D 0 1 -.names N_215_i.BLIF N_216_i.BLIF SM_AMIGA_1_.D -11 1 +.names N_46_0.BLIF SM_AMIGA_1_.D +0 1 .names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D 0 1 -.names G_102.BLIF CLK_CNT_N_0_.D -0 1 -.names G_108.BLIF CLK_CNT_P_0_.D -0 1 +.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D +1- 1 +-1 1 +.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D +1- 1 +-1 1 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D 1- 1 -1 1 @@ -304,604 +339,706 @@ LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE G_102 G_108 -1 1 .names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D 0 1 -.names N_83_i.BLIF N_85_i.BLIF SM_AMIGA_6_.D +.names N_131_i.BLIF N_132_i.BLIF SM_AMIGA_6_.D +11 1 +.names inst_CLK_000_D0.BLIF N_133_i.BLIF SM_AMIGA_5_.D 11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D -1- 1 --1 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D -1- 1 --1 1 .names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D 1- 1 -1 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D 1- 1 -1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 -1 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ inst_BGACK_030_INTreg.D 1- 1 -1 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D -1- 1 --1 1 -.names G_108.BLIF G_102.BLIF inst_CLK_OUT_PRE.D -11 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ -inst_AS_030_000_SYNC.D +.names G_103.BLIF CLK_CNT_N_0_.D +0 1 +.names G_109.BLIF CLK_CNT_P_0_.D +0 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D 1- 1 -1 1 .names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D 1- 1 -1 1 -.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF inst_A0_DMA.D 1- 1 -1 1 -.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +1- 1 +-1 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D 1- 1 -1 1 .names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF \ -AMIGA_BUS_ENABLEDFFreg.D +AMIGA_BUS_ENABLEDFFSHreg.D 1- 1 -1 1 -.names state_machine_un7_as_000_int_n.BLIF inst_DTACK_DMA.D -0 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D +1- 1 +-1 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ +inst_AS_030_000_SYNC.D +1- 1 +-1 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D +1- 1 +-1 1 +.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D +1- 1 +-1 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D +1- 1 +-1 1 +.names G_109.BLIF G_103.BLIF inst_CLK_OUT_PRE.D +11 1 .names vcc_n_n 1 .names gnd_n_n -.names AS_030_i.BLIF sm_amiga_i_5__n.BLIF AS_000_INT_1_sqmuxa +.names state_machine_un23_clk_000_d0_0_n.BLIF state_machine_un23_clk_000_d0_n +0 1 +.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n +0 1 +.names un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_0_sqmuxa_2 +0 1 +.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ +state_machine_un23_clk_000_d0_0_n +11 1 +.names BGACK_000_c.BLIF N_65.BLIF state_machine_un6_bgack_000_0_n +11 1 +.names AS_030_i.BLIF N_224_i.BLIF N_214_0 +11 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names N_227.BLIF N_227_i +0 1 +.names BG_030_c_i.BLIF N_227_i.BLIF state_machine_un10_bg_030_0_n +11 1 +.names AS_030_i.BLIF N_73.BLIF N_215_0 +11 1 +.names AS_030_i.BLIF N_228_i.BLIF N_216_0 +11 1 +.names N_126.BLIF N_126_i +0 1 +.names AS_030_i.BLIF N_126_i.BLIF N_33_0 +11 1 +.names N_127.BLIF N_127_i +0 1 +.names N_127_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i.BLIF N_35_0 +11 1 +.names A0_i.BLIF N_73_i.BLIF state_machine_uds_000_int_5_0_n +11 1 +.names N_130.BLIF N_130_i +0 1 +.names N_73_i.BLIF N_130_i.BLIF state_machine_lds_000_int_5_0_n +11 1 +.names N_132.BLIF N_132_i +0 1 +.names N_131.BLIF N_131_i +0 1 +.names N_133.BLIF N_133_i +0 1 +.names N_134.BLIF N_134_i +0 1 +.names N_137.BLIF N_137_i +0 1 +.names N_138.BLIF N_138_i +0 1 +.names N_137_i.BLIF N_138_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n +0 1 +.names N_139.BLIF N_139_i +0 1 +.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n +0 1 +.names N_140.BLIF N_140_i +0 1 +.names N_139_i.BLIF N_140_i.BLIF N_46_0 +11 1 +.names N_52_0.BLIF N_52 +0 1 +.names N_142.BLIF N_142_i +0 1 +.names N_59_i.BLIF N_59 +0 1 +.names N_141.BLIF N_141_i +0 1 +.names N_62_i.BLIF N_62 +0 1 +.names N_141_i.BLIF N_142_i.BLIF sm_amiga_ns_0_7__n +11 1 +.names N_65_i.BLIF N_65 +0 1 +.names N_144.BLIF N_144_i +0 1 +.names N_67_i.BLIF N_67 +0 1 +.names N_144_i.BLIF un1_as_000_dma5_i_0__n.BLIF state_machine_ds_000_dma_5_0_n +11 1 +.names N_72_i.BLIF N_72 +0 1 +.names CLK_030_c.BLIF CLK_030_c_i +0 1 +.names N_77_0.BLIF N_77 +0 1 +.names AS_000_c.BLIF AS_000_c_i +0 1 +.names cpu_est_ns_0_0_m2_2__un1_n.BLIF cpu_est_ns_0_0_m2_2__un0_n.BLIF N_88 +1- 1 +-1 1 +.names inst_AS_000_INT.BLIF inst_CLK_000_D0.BLIF N_59_i +11 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_217 +11 1 +.names AS_030_i.BLIF N_223_i.BLIF N_61_0 +11 1 +.names N_219_1.BLIF VPA_i.BLIF N_219 +11 1 +.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_i.BLIF N_62_i +11 1 +.names N_221_1.BLIF cpu_est_2_.BLIF N_221 +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names N_224_1.BLIF N_224_2.BLIF N_224 +11 1 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_65_i +11 1 +.names N_62.BLIF N_173.BLIF N_225 +11 1 +.names N_66_i_4.BLIF N_66_i_5.BLIF N_66_i +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF N_226 +11 1 +.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_67_i +11 1 +.names N_128_1.BLIF UDS_000_c.BLIF N_128 +11 1 +.names N_175.BLIF N_175_i +0 1 +.names N_130_1.BLIF size_i_1__n.BLIF N_130 +11 1 +.names N_151.BLIF N_175_i.BLIF un1_as_000_dma5_i_0__n +11 1 +.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_132 +11 1 +.names state_machine_un6_clk_000_d5_n.BLIF state_machine_un6_clk_000_d5_i_n +0 1 +.names CLK_000_D0_i.BLIF N_77.BLIF N_135 +11 1 +.names CLK_000_D0_i.BLIF state_machine_un6_clk_000_d5_i_n.BLIF N_71_i +11 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_136 +11 1 +.names DS_030_c.BLIF DS_030_c_i +0 1 +.names N_138_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_138 +11 1 +.names DS_030_c_i.BLIF N_57.BLIF N_73_i +11 1 +.names N_72.BLIF cpu_est_2_.BLIF N_143 +11 1 +.names N_156.BLIF N_156_i +0 1 +.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_145 +11 1 +.names N_61_0.BLIF N_156_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i +11 1 +.names CLK_000_D0_i.BLIF N_156.BLIF N_146 +11 1 +.names CLK_000_D0_i.BLIF N_67_i.BLIF N_75_0 +11 1 +.names N_65.BLIF cpu_est_0_.BLIF N_147 +11 1 +.names N_176.BLIF N_176_i +0 1 +.names N_65_i.BLIF cpu_est_i_0__n.BLIF N_148 +11 1 +.names N_52_0_1.BLIF N_52_0_2.BLIF N_52_0 +11 1 +.names N_151_1.BLIF BGACK_030_INT_i.BLIF N_151 +11 1 +.names N_173.BLIF N_173_i +0 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_153 +11 1 +.names N_226.BLIF N_226_i +0 1 +.names N_153.BLIF cpu_est_i_3__n.BLIF N_154 +11 1 +.names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_0_n.BLIF N_77_0 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_155 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_72_i +11 1 +.names N_59_i.BLIF SM_AMIGA_0_.BLIF N_173 +11 1 +.names N_147.BLIF N_147_i +0 1 +.names N_148.BLIF N_148_i +0 1 +.names N_147_i.BLIF N_148_i.BLIF cpu_est_ns_e_0_0__n +11 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF N_228_1 +11 1 +.names N_146.BLIF N_146_i +0 1 +.names N_237_1.BLIF N_237_2.BLIF N_237 +11 1 +.names sm_amiga_ns_0_1_0__n.BLIF N_146_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names N_247_5.BLIF N_247_6.BLIF N_247 +11 1 +.names N_88.BLIF N_88_i +0 1 +.names N_227_1.BLIF N_227_2.BLIF N_227 +11 1 +.names N_145.BLIF N_145_i +0 1 +.names N_228_1_0.BLIF VPA_c.BLIF N_228 +11 1 +.names N_88_i.BLIF N_145_i.BLIF cpu_est_ns_0_2__n +11 1 +.names N_127_1.BLIF N_127_2.BLIF N_127 +11 1 +.names N_143.BLIF N_143_i +0 1 +.names N_66_i.BLIF N_66 +0 1 +.names N_154.BLIF N_154_i +0 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_175 +11 1 +.names N_143_i.BLIF N_154_i.BLIF N_161_i +11 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF N_176 +11 1 +.names N_153.BLIF N_153_i +0 1 +.names N_75_0.BLIF N_75 +0 1 +.names N_155.BLIF N_155_i +0 1 +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_4 +0 1 +.names cpu_est_ns_0_1_1__n.BLIF N_153_i.BLIF cpu_est_ns_0_1__n +11 1 +.names N_61_0.BLIF N_61 +0 1 +.names N_135.BLIF N_135_i +0 1 +.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_156 +11 1 +.names N_136.BLIF N_136_i +0 1 +.names N_73_i.BLIF N_73 +0 1 +.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ +state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_57 +1- 1 +-1 1 +.names N_225.BLIF N_225_i +0 1 +.names N_71_i.BLIF N_71 +0 1 +.names N_225_i.BLIF N_226_i.BLIF un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0 +11 1 +.names inst_CLK_000_D5.BLIF CLK_000_D6_i.BLIF state_machine_un6_clk_000_d5_n +11 1 +.names N_219.BLIF N_219_i +0 1 +.names un1_as_000_dma5_i_0__n.BLIF un1_as_000_dma5_0__n +0 1 +.names N_221.BLIF N_221_i +0 1 +.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d5_n.BLIF N_223 +11 1 +.names N_219_i.BLIF N_221_i.BLIF state_machine_un15_clk_000_d0_0_n +11 1 +.names state_machine_ds_000_dma_5_0_n.BLIF state_machine_ds_000_dma_5_n +0 1 +.names inst_AS_000_DMA.BLIF RW_i.BLIF N_144 +11 1 +.names BGACK_000_c.BLIF a_i_19__n.BLIF N_66_i_1 +11 1 +.names N_59.BLIF SM_AMIGA_0_.BLIF N_141 +11 1 +.names a_i_16__n.BLIF a_i_18__n.BLIF N_66_i_2 +11 1 +.names N_71_i.BLIF SM_AMIGA_1_.BLIF N_142 +11 1 +.names a_c_17__n.BLIF fc_c_0__n.BLIF N_66_i_3 +11 1 +.names N_71.BLIF SM_AMIGA_1_.BLIF N_139 +11 1 +.names N_66_i_1.BLIF N_66_i_2.BLIF N_66_i_4 +11 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_140 +11 1 +.names N_66_i_3.BLIF fc_c_1__n.BLIF N_66_i_5 +11 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_137 +11 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_237_1 +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_134 +11 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_237_2 +11 1 +.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_133 +11 1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_247_1 +11 1 +.names N_75.BLIF sm_amiga_i_7__n.BLIF N_131 +11 1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_247_2 +11 1 +.names state_machine_lds_000_int_5_0_n.BLIF state_machine_lds_000_int_5_n +0 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_247_3 +11 1 +.names state_machine_uds_000_int_5_0_n.BLIF state_machine_uds_000_int_5_n +0 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_247_4 +11 1 +.names N_35_0.BLIF N_35 +0 1 +.names N_247_1.BLIF N_247_2.BLIF N_247_5 +11 1 +.names N_33_0.BLIF N_33 +0 1 +.names N_247_3.BLIF N_247_4.BLIF N_247_6 +11 1 +.names CLK_030_c.BLIF N_66_i.BLIF N_126 +11 1 +.names N_62.BLIF N_67.BLIF N_52_0_1 +11 1 +.names N_216_0.BLIF N_216 +0 1 +.names N_173_i.BLIF N_226_i.BLIF N_52_0_2 +11 1 +.names N_215_0.BLIF N_215 +0 1 +.names N_72_i.BLIF N_228_1.BLIF N_224_1 +11 1 +.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n +0 1 +.names VMA_INT_i.BLIF VPA_i.BLIF N_224_2 +11 1 +.names N_214_0.BLIF N_214 +0 1 +.names AS_030_c.BLIF CLK_000_c.BLIF N_227_1 +11 1 +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n +0 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_227_2 11 1 .names state_machine_un8_clk_000_d2_1_n.BLIF CLK_000_D2_i.BLIF \ state_machine_un8_clk_000_d2_n 11 1 -.names state_machine_un23_clk_000_d0_0_n.BLIF state_machine_un23_clk_000_d0_n +.names DTACK_i.BLIF N_228_1.BLIF N_228_1_0 +11 1 +.names SIZE_DMA_1_sqmuxa_1.BLIF N_175_i.BLIF SIZE_DMA_1_sqmuxa +11 1 +.names CLK_030_c.BLIF N_66.BLIF N_127_1 +11 1 +.names N_151.BLIF N_176.BLIF SIZE_DMA_0_sqmuxa +11 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_127_2 +11 1 +.names AS_030_i.BLIF sm_amiga_i_5__n.BLIF AS_000_INT_1_sqmuxa +11 1 +.names CLK_030_c_i.BLIF AS_000_c_i.BLIF N_151_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_249 +11 1 +.names N_176_i.BLIF N_151.BLIF SIZE_DMA_1_sqmuxa_1 +11 1 +.names inst_CLK_000_D6.BLIF CLK_000_D6_i 0 1 -.names inst_CLK_000_D5.BLIF CLK_000_D6_i.BLIF state_machine_un6_clk_000_d5_n -11 1 -.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n -0 1 -.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n -0 1 -.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n -11 1 -.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un7_as_000_int_n -11 1 -.names N_129.BLIF N_129_i -0 1 -.names N_131.BLIF N_131_i -0 1 -.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n -0 1 -.names N_221.BLIF N_221_i -0 1 -.names state_machine_lds_000_int_5_0_n.BLIF state_machine_lds_000_int_5_n -0 1 -.names N_222.BLIF N_222_i -0 1 -.names state_machine_uds_000_int_5_0_n.BLIF state_machine_uds_000_int_5_n -0 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_63_0 -11 1 -.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 -0 1 -.names CLK_000_D0_i.BLIF N_56_i.BLIF N_62_0 -11 1 -.names N_132.BLIF N_132_i -0 1 -.names N_51_i.BLIF N_132_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 -11 1 -.names DS_030_c.BLIF DS_030_c_i -0 1 -.names DS_030_c_i.BLIF N_49.BLIF N_60_i -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_59_i -11 1 -.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d5_n.BLIF N_57_i -11 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_56_i -11 1 -.names N_55_i_4.BLIF N_55_i_5.BLIF N_55_i -11 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_54_i -11 1 -.names AS_030_i.BLIF N_57.BLIF N_51_i -11 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF N_50_i -11 1 -.names N_125.BLIF N_125_i -0 1 -.names N_126.BLIF N_126_i -0 1 -.names N_125_i.BLIF N_126_i.BLIF cpu_est_ns_e_0_0__n -11 1 -.names N_85.BLIF N_85_i -0 1 -.names N_123.BLIF N_123_i -0 1 -.names N_124.BLIF N_124_i -0 1 -.names sm_amiga_ns_0_1_0__n.BLIF N_123_i.BLIF sm_amiga_ns_0_0__n -11 1 -.names N_122.BLIF N_122_i -0 1 -.names N_227.BLIF N_227_i -0 1 -.names N_228.BLIF N_228_i -0 1 -.names cpu_est_ns_0_1_2__n.BLIF N_227_i.BLIF cpu_est_ns_0_2__n -11 1 -.names N_226.BLIF N_226_i -0 1 -.names N_56.BLIF N_226_i.BLIF N_44_i -11 1 -.names N_130.BLIF N_130_i -0 1 -.names N_225.BLIF N_225_i -0 1 -.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n -0 1 -.names N_130_i.BLIF N_225_i.BLIF N_158_i -11 1 -.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n -0 1 -.names N_219.BLIF N_219_i -0 1 -.names N_204_0.BLIF N_204 -0 1 -.names N_220.BLIF N_220_i -0 1 -.names N_205_0.BLIF N_205 -0 1 -.names N_219_i.BLIF N_220_i.BLIF sm_amiga_ns_0_7__n -11 1 -.names N_206_0.BLIF N_206 -0 1 -.names N_215.BLIF N_215_i -0 1 -.names N_26_0.BLIF N_26 -0 1 -.names N_216.BLIF N_216_i -0 1 -.names N_30_0.BLIF N_30 -0 1 -.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ -state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_49 -1- 1 --1 1 -.names N_95.BLIF N_95_i -0 1 -.names N_50_i.BLIF N_50 -0 1 -.names N_214.BLIF N_214_i -0 1 -.names N_51_i.BLIF N_51 -0 1 -.names N_95_i.BLIF N_214_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names N_54_i.BLIF N_54 -0 1 -.names N_94.BLIF N_94_i -0 1 -.names N_55_i.BLIF N_55 -0 1 -.names N_133.BLIF N_133_i -0 1 -.names N_56_i.BLIF N_56 -0 1 -.names N_57_i.BLIF N_57 -0 1 -.names N_87.BLIF N_87_i -0 1 -.names N_59_i.BLIF N_59 -0 1 -.names N_60_i.BLIF N_60 -0 1 -.names N_86.BLIF N_86_i -0 1 -.names N_62_0.BLIF N_62 -0 1 -.names N_63_0.BLIF N_63 -0 1 -.names N_83.BLIF N_83_i -0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_68 -11 1 -.names N_70_1.BLIF N_70_2.BLIF N_70 -11 1 -.names N_82.BLIF N_82_i -0 1 -.names N_72_1.BLIF VPA_D_i.BLIF N_72 -11 1 -.names N_60_i.BLIF N_82_i.BLIF state_machine_lds_000_int_5_0_n -11 1 -.names N_73_1.BLIF cpu_est_2_.BLIF N_73 -11 1 -.names a_i_0__n.BLIF N_60_i.BLIF state_machine_uds_000_int_5_0_n -11 1 -.names N_74_3.BLIF VPA_D_i.BLIF N_74 -11 1 -.names N_80.BLIF N_80_i -0 1 -.names CLK_030_c.BLIF N_55_i.BLIF N_76 -11 1 -.names N_80_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_30_0 -11 1 -.names N_78_1.BLIF N_78_2.BLIF N_78 -11 1 -.names AS_030_i.BLIF N_78_i.BLIF N_26_0 -11 1 -.names N_80_1.BLIF N_80_2.BLIF N_80 -11 1 -.names N_76.BLIF N_76_i -0 1 -.names N_82_1.BLIF size_i_1__n.BLIF N_82 -11 1 -.names AS_030_i.BLIF N_76_i.BLIF N_206_0 -11 1 -.names N_62.BLIF sm_amiga_i_7__n.BLIF N_83 -11 1 -.names AS_030_i.BLIF N_74_i.BLIF N_205_0 -11 1 -.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_85 -11 1 -.names N_72.BLIF N_72_i -0 1 -.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_86 -11 1 -.names N_73.BLIF N_73_i -0 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_87 -11 1 -.names N_72_i.BLIF N_73_i.BLIF state_machine_un15_clk_000_d0_0_n -11 1 -.names N_63.BLIF sm_amiga_i_3__n.BLIF N_94 -11 1 -.names AS_030_i.BLIF N_60.BLIF N_204_0 -11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_95 -11 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names N_133.BLIF SM_AMIGA_3_.BLIF N_214 -11 1 -.names N_70.BLIF N_70_i -0 1 -.names CLK_000_D0_i.BLIF N_57.BLIF N_215 -11 1 -.names BG_030_c_i.BLIF N_70_i.BLIF state_machine_un10_bg_030_0_n -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_216 -11 1 -.names BGACK_000_c.BLIF N_54.BLIF state_machine_un6_bgack_000_0_n -11 1 -.names N_50.BLIF SM_AMIGA_0_.BLIF N_219 -11 1 -.names N_220_1.BLIF state_machine_un6_clk_000_d5_i_n.BLIF N_220 -11 1 -.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ -state_machine_un23_clk_000_d0_0_n -11 1 -.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_221 -11 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_236_1 -11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_222 -11 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_236_2 -11 1 -.names N_59.BLIF cpu_est_2_.BLIF N_225 -11 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_236_3 -11 1 -.names N_226_1.BLIF sm_amiga_i_6__n.BLIF N_226 -11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_236_4 -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_227 -11 1 -.names N_236_1.BLIF N_236_2.BLIF N_236_5 -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_228 -11 1 -.names N_236_3.BLIF N_236_4.BLIF N_236_6 -11 1 -.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_122 -11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_239_1 -11 1 -.names CLK_000_D0_i.BLIF N_132.BLIF N_123 -11 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_239_2 -11 1 -.names N_50_i.BLIF SM_AMIGA_0_.BLIF N_124 -11 1 .names inst_CLK_000_D3.BLIF AS_030_000_SYNC_i.BLIF \ state_machine_un8_clk_000_d2_1_n 11 1 -.names N_54.BLIF cpu_est_0_.BLIF N_125 -11 1 -.names a_c_17__n.BLIF BGACK_000_c.BLIF N_55_i_1 -11 1 -.names N_54_i.BLIF cpu_est_i_0__n.BLIF N_126 -11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_55_i_2 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_129 -11 1 -.names a_i_19__n.BLIF a_i_16__n.BLIF N_55_i_3 -11 1 -.names N_129.BLIF cpu_est_i_3__n.BLIF N_130 -11 1 -.names N_55_i_1.BLIF N_55_i_2.BLIF N_55_i_4 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_131 -11 1 -.names N_55_i_3.BLIF a_i_18__n.BLIF N_55_i_5 -11 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_132 -11 1 -.names N_129_i.BLIF N_131_i.BLIF cpu_est_ns_0_1_1__n -11 1 -.names CLK_000_D0_i.BLIF state_machine_un23_clk_000_d0_n.BLIF N_133 -11 1 -.names N_221_i.BLIF N_222_i.BLIF cpu_est_ns_0_2_1__n -11 1 -.names N_236_5.BLIF N_236_6.BLIF N_236 -11 1 -.names CLK_030_c.BLIF N_55.BLIF N_80_1 -11 1 -.names N_239_1.BLIF N_239_2.BLIF N_239 -11 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_80_2 -11 1 -.names RW_c.BLIF RW_i +.names N_228.BLIF N_228_i 0 1 -.names inst_CLK_000_D0.BLIF DTACK_i.BLIF N_78_1 -11 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names SM_AMIGA_3_.BLIF inst_VPA_D.BLIF N_78_2 -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names inst_CLK_000_D0.BLIF N_59_i.BLIF N_74_1 -11 1 -.names DTACK_c.BLIF DTACK_i -0 1 -.names SM_AMIGA_3_.BLIF VMA_INT_i.BLIF N_74_2 -11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names N_74_1.BLIF N_74_2.BLIF N_74_3 -11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names AS_030_c.BLIF CLK_000_c.BLIF N_70_1 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_70_2 -11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names N_124_i.BLIF N_85_i.BLIF sm_amiga_ns_0_1_0__n -11 1 -.names state_machine_un6_clk_000_d5_n.BLIF state_machine_un6_clk_000_d5_i_n -0 1 -.names N_228_i.BLIF N_122_i.BLIF cpu_est_ns_0_1_2__n -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF N_226_1 -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_1_.BLIF N_220_1 -11 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 -.names a_i_0__n.BLIF size_c_0__n.BLIF N_82_1 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names N_50_i.BLIF N_130.BLIF N_73_1 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names CLK_000_D0_i.BLIF N_131.BLIF N_72_1 -11 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i -0 1 -.names RW_c.BLIF state_machine_uds_000_int_5_0_m2_un3_n -0 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names SM_AMIGA_5_.BLIF RW_c.BLIF state_machine_uds_000_int_5_0_m2_un1_n -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names SM_AMIGA_4_.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF \ -state_machine_uds_000_int_5_0_m2_un0_n -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names N_205.BLIF vpa_sync_0_un3_n -0 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_74_i.BLIF N_205.BLIF vpa_sync_0_un1_n +.names N_173_i.BLIF N_132_i.BLIF sm_amiga_ns_0_1_0__n 11 1 .names SM_AMIGA_5_.BLIF sm_amiga_i_5__n 0 1 +.names N_155_i.BLIF cpu_est_ns_0_0_x2_1_.BLIF cpu_est_ns_0_1_1__n +11 1 +.names N_224.BLIF N_224_i +0 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_138_1 +11 1 +.names N_223.BLIF N_223_i +0 1 +.names A0_i.BLIF size_c_0__n.BLIF N_130_1 +11 1 +.names SIZE_DMA_0_sqmuxa.BLIF SIZE_DMA_0_sqmuxa_i +0 1 +.names LDS_000_i.BLIF N_151.BLIF N_128_1 +11 1 +.names SIZE_DMA_1_sqmuxa.BLIF SIZE_DMA_1_sqmuxa_i +0 1 +.names N_59_i.BLIF N_154.BLIF N_221_1 +11 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names CLK_000_D0_i.BLIF N_155.BLIF N_219_1 +11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names N_214.BLIF vpa_sync_0_un3_n +0 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names N_224_i.BLIF N_214.BLIF vpa_sync_0_un1_n +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 .names inst_VPA_SYNC.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n 11 1 -.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n -0 1 -.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n -0 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names N_50_i.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n -11 1 -.names a_c_0__n.BLIF a_i_0__n -0 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names size_c_1__n.BLIF size_i_1__n -0 1 -.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n -0 1 -.names dsack_c_1__n.BLIF dsack_i_1__n -0 1 -.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 .names inst_CLK_000_D2.BLIF CLK_000_D2_i 0 1 -.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_249.BLIF as_000_dma_0_un3_n +0 1 +.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i +0 1 +.names inst_AS_000_DMA.BLIF N_249.BLIF as_000_dma_0_un1_n +11 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names un1_as_000_dma5_0__n.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n +0 1 +.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names N_249.BLIF a0_dma_0_un3_n +0 1 +.names RW_c.BLIF RW_i +0 1 +.names inst_A0_DMA.BLIF N_249.BLIF a0_dma_0_un1_n +11 1 +.names UDS_000_c.BLIF UDS_000_i +0 1 +.names N_128.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +11 1 +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names N_216.BLIF dtack_sync_0_un3_n +0 1 +.names DTACK_c.BLIF DTACK_i +0 1 +.names N_228_i.BLIF N_216.BLIF dtack_sync_0_un1_n +11 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names inst_DTACK_SYNC.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n +11 1 +.names VPA_c.BLIF VPA_i +0 1 +.names N_215.BLIF lds_000_int_0_un3_n +0 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names state_machine_lds_000_int_5_n.BLIF N_215.BLIF lds_000_int_0_un1_n +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names N_215.BLIF uds_000_int_0_un3_n +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names state_machine_uds_000_int_5_n.BLIF N_215.BLIF uds_000_int_0_un1_n +11 1 +.names A0_c.BLIF A0_i +0 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names size_c_1__n.BLIF size_i_1__n +0 1 +.names N_33.BLIF fpu_cs_int_0_un3_n +0 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names AS_030_c.BLIF N_33.BLIF fpu_cs_int_0_un1_n +11 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n +11 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names N_249.BLIF ds_000_dma_0_un3_n +0 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names inst_DS_000_DMA.BLIF N_249.BLIF ds_000_dma_0_un1_n +11 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names state_machine_ds_000_dma_5_n.BLIF ds_000_dma_0_un3_n.BLIF \ +ds_000_dma_0_un0_n +11 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 +.names N_35.BLIF as_030_000_sync_0_un3_n +0 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_4.BLIF N_35.BLIF as_030_000_sync_0_un1_n +11 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un0_n +11 1 +.names RST_c.BLIF RST_i +0 1 +.names N_249.BLIF size_dma_0_1__un3_n +0 1 +.names SIZE_DMA_1_.BLIF N_249.BLIF size_dma_0_1__un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_OSZI_i +0 1 +.names SIZE_DMA_1_sqmuxa_i.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n +11 1 +.names N_249.BLIF size_dma_0_0__un3_n +0 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +0 1 +.names SIZE_DMA_0_.BLIF N_249.BLIF size_dma_0_0__un1_n +11 1 +.names SIZE_DMA_0_sqmuxa_i.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +11 1 +.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 .names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ bgack_030_int_0_un1_n 11 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names a_c_16__n.BLIF a_i_16__n +.names N_61.BLIF dsack1_int_0_un3_n 0 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n -0 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +.names N_223_i.BLIF N_61.BLIF dsack1_int_0_un1_n 11 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +.names inst_DSACK1_INT.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n 11 1 -.names a_c_31__n.BLIF a_i_31__n +.names RW_c.BLIF state_machine_uds_000_int_5_0_m2_un3_n 0 1 -.names N_54.BLIF ipl_030_0_0__un3_n -0 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names IPL_030DFFSH_0_reg.BLIF N_54.BLIF ipl_030_0_0__un1_n +.names SM_AMIGA_5_.BLIF RW_c.BLIF state_machine_uds_000_int_5_0_m2_un1_n 11 1 -.names a_c_29__n.BLIF a_i_29__n +.names SM_AMIGA_4_.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF \ +state_machine_uds_000_int_5_0_m2_un0_n +11 1 +.names cpu_est_1_.BLIF cpu_est_ns_0_0_m2_2__un3_n 0 1 +.names cpu_est_2_.BLIF cpu_est_1_.BLIF cpu_est_ns_0_0_m2_2__un1_n +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_ns_0_0_m2_2__un3_n.BLIF \ +cpu_est_ns_0_0_m2_2__un0_n +11 1 +.names N_52.BLIF amiga_bus_enable_0_un3_n +0 1 +.names un1_AMIGA_BUS_ENABLE_0_sqmuxa_2.BLIF N_52.BLIF amiga_bus_enable_0_un1_n +11 1 +.names AMIGA_BUS_ENABLEDFFSHreg.BLIF amiga_bus_enable_0_un3_n.BLIF \ +amiga_bus_enable_0_un0_n +11 1 +.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n +0 1 +.names N_59_i.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +11 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names N_65.BLIF ipl_030_0_0__un3_n +0 1 +.names IPL_030DFFSH_0_reg.BLIF N_65.BLIF ipl_030_0_0__un1_n +11 1 .names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names a_c_26__n.BLIF a_i_26__n +.names N_65.BLIF ipl_030_0_1__un3_n 0 1 -.names N_54.BLIF ipl_030_0_1__un3_n -0 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names IPL_030DFFSH_1_reg.BLIF N_54.BLIF ipl_030_0_1__un1_n +.names IPL_030DFFSH_1_reg.BLIF N_65.BLIF ipl_030_0_1__un1_n 11 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 .names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 -.names a_c_25__n.BLIF a_i_25__n +.names N_65.BLIF ipl_030_0_2__un3_n 0 1 -.names N_54.BLIF ipl_030_0_2__un3_n -0 1 -.names RST_c.BLIF RST_i -0 1 -.names IPL_030DFFSH_2_reg.BLIF N_54.BLIF ipl_030_0_2__un1_n +.names IPL_030DFFSH_2_reg.BLIF N_65.BLIF ipl_030_0_2__un1_n 11 1 .names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 -.names N_54.BLIF cpu_estse_0_un3_n +.names N_65.BLIF cpu_estse_0_un3_n 0 1 -.names CLK_OSZI_c.BLIF CLK_OSZI_i -0 1 -.names cpu_est_1_.BLIF N_54.BLIF cpu_estse_0_un1_n +.names cpu_est_1_.BLIF N_65.BLIF cpu_estse_0_un1_n 11 1 .names cpu_est_ns_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n 11 1 -.names N_74.BLIF N_74_i +.names N_65.BLIF cpu_estse_1_un3_n 0 1 -.names N_54.BLIF cpu_estse_1_un3_n -0 1 -.names N_78.BLIF N_78_i -0 1 -.names cpu_est_2_.BLIF N_54.BLIF cpu_estse_1_un1_n +.names cpu_est_2_.BLIF N_65.BLIF cpu_estse_1_un1_n 11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i -0 1 .names cpu_est_ns_2__n.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n 11 1 -.names inst_CLK_000_D6.BLIF CLK_000_D6_i +.names N_65.BLIF cpu_estse_2_un3_n 0 1 -.names N_54.BLIF cpu_estse_2_un3_n -0 1 -.names cpu_est_3_reg.BLIF N_54.BLIF cpu_estse_2_un1_n +.names cpu_est_3_reg.BLIF N_65.BLIF cpu_estse_2_un1_n 11 1 -.names N_158_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n +.names N_161_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n 11 1 -.names N_30.BLIF as_030_000_sync_0_un3_n -0 1 -.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_30.BLIF as_030_000_sync_0_un1_n -11 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 -.names N_26.BLIF dtack_sync_0_un3_n -0 1 -.names N_78_i.BLIF N_26.BLIF dtack_sync_0_un1_n -11 1 -.names inst_DTACK_SYNC.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n -11 1 -.names N_206.BLIF fpu_cs_int_0_un3_n -0 1 -.names AS_030_c.BLIF N_206.BLIF fpu_cs_int_0_un1_n -11 1 -.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n -11 1 -.names N_51.BLIF dsack_int_0_1__un3_n -0 1 -.names N_57.BLIF N_51.BLIF dsack_int_0_1__un1_n -11 1 -.names DSACK_INT_1_.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n -11 1 -.names RST_c.BLIF amiga_bus_enable_0_un3_n -0 1 -.names N_44_i.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n -11 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF \ -amiga_bus_enable_0_un0_n -11 1 -.names N_204.BLIF uds_000_int_0_un3_n -0 1 -.names state_machine_uds_000_int_5_n.BLIF N_204.BLIF uds_000_int_0_un1_n -11 1 -.names inst_UDS_000_INTreg.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names N_204.BLIF lds_000_int_0_un3_n -0 1 -.names state_machine_lds_000_int_5_n.BLIF N_204.BLIF lds_000_int_0_un1_n -11 1 -.names inst_LDS_000_INTreg.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF G_102 +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF G_103 01 1 10 1 11 0 00 0 -.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF G_108 +.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF G_109 +01 1 +10 1 +11 0 +00 0 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_ns_0_0_x2_1_ +01 1 +10 1 +11 0 +00 0 +.names inst_BGACK_030_INTreg.BLIF RW_c.BLIF AMIGA_BUS_DATA_DIR_m1_0_x2 01 1 10 1 11 0 @@ -909,15 +1046,6 @@ amiga_bus_enable_0_un0_n .names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ 1 1 0 0 -.names inst_AS_000_INTreg.BLIF AS_000 -1 1 -0 0 -.names inst_UDS_000_INTreg.BLIF UDS_000 -1 1 -0 0 -.names inst_LDS_000_INTreg.BLIF LDS_000 -1 1 -0 0 .names gnd_n_n.BLIF BERR 1 1 0 0 @@ -951,16 +1079,16 @@ amiga_bus_enable_0_un0_n .names RESETDFFRHreg.BLIF RESET 1 1 0 0 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE +.names AMIGA_BUS_ENABLEDFFSHreg.BLIF AMIGA_BUS_ENABLE 1 1 0 0 -.names RW_i.BLIF AMIGA_BUS_DATA_DIR +.names AMIGA_BUS_DATA_DIR_m1_0_x2.BLIF AMIGA_BUS_DATA_DIR 1 1 0 0 .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_239.BLIF CIIN +.names N_237.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -993,12 +1121,6 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF cpu_est_0_.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_5_.AR -1 1 -0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -1029,27 +1151,6 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF SM_AMIGA_0_.AR 1 1 0 0 -.names CLK_OSZI_i.BLIF CLK_CNT_N_0_.C -1 1 -0 0 -.names RST_i.BLIF CLK_CNT_N_0_.AR -1 1 -0 0 -.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D -1 1 -0 0 -.names CLK_OSZI_i.BLIF CLK_CNT_N_1_.C -1 1 -0 0 -.names RST_i.BLIF CLK_CNT_N_1_.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_CNT_P_0_.C -1 1 -0 0 -.names RST_i.BLIF CLK_CNT_P_0_.AR -1 1 -0 0 .names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.D 1 1 0 0 @@ -1059,6 +1160,18 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF CLK_CNT_P_1_.AR 1 1 0 0 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +0 0 +.names RST_i.BLIF SIZE_DMA_0_.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names RST_i.BLIF SIZE_DMA_1_.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C 1 1 0 0 @@ -1089,16 +1202,10 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF SM_AMIGA_6_.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 0 0 -.names RST_i.BLIF inst_UDS_000_INTreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_LDS_000_INTreg.AP +.names RST_i.BLIF SM_AMIGA_5_.AR 1 1 0 0 .names CLK_OSZI_c.BLIF inst_VPA_SYNC.C @@ -1107,34 +1214,109 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF inst_VPA_SYNC.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +1 1 +0 0 +.names RST_i.BLIF inst_DSACK1_INT.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 0 0 .names RST_i.BLIF inst_VMA_INTreg.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -0 0 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 .names RST_i.BLIF inst_BGACK_030_INTreg.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C +.names CLK_OSZI_i.BLIF CLK_CNT_N_0_.C 1 1 0 0 -.names RST_i.BLIF inst_AS_000_INTreg.AP +.names RST_i.BLIF CLK_CNT_N_0_.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D 1 1 0 0 -.names RST_i.BLIF inst_CLK_OUT_PRE.AR +.names CLK_OSZI_i.BLIF CLK_CNT_N_1_.C +1 1 +0 0 +.names RST_i.BLIF CLK_CNT_N_1_.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_CNT_P_0_.C +1 1 +0 0 +.names RST_i.BLIF CLK_CNT_P_0_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names RST_i.BLIF inst_LDS_000_INT.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C +1 1 +0 0 +.names RST_i.BLIF inst_DTACK_SYNC.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +0 0 +.names RST_i.BLIF inst_A0_DMA.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST_i.BLIF BG_000DFFSHreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +0 0 +.names RST_i.BLIF inst_AS_000_DMA.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFSHreg.C +1 1 +0 0 +.names RST_i.BLIF AMIGA_BUS_ENABLEDFFSHreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +0 0 +.names RST_i.BLIF inst_AS_000_INT.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names RST_i.BLIF inst_AS_030_000_SYNC.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +0 0 +.names RST_i.BLIF inst_DS_000_DMA.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C +1 1 +0 0 +.names RST_i.BLIF inst_FPU_CS_INTreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +0 0 +.names RST_i.BLIF inst_UDS_000_INT.AP 1 1 0 0 .names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D @@ -1146,37 +1328,10 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF CLK_OUT_INTreg.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C 1 1 0 0 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C -1 1 -0 0 -.names RST_i.BLIF inst_DTACK_SYNC.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_FPU_CS_INTreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF DSACK_INT_1_.C -1 1 -0 0 -.names RST_i.BLIF DSACK_INT_1_.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DTACK_DMA.C -1 1 -0 0 -.names RST_i.BLIF inst_DTACK_DMA.AP +.names RST_i.BLIF inst_CLK_OUT_PRE.AR 1 1 0 0 .names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D @@ -1224,13 +1379,13 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF inst_CLK_000_D3.AP 1 1 0 0 -.names VPA.BLIF inst_VPA_D.D +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_VPA_D.C +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 -.names RST_i.BLIF inst_VPA_D.AP +.names RST_i.BLIF inst_BGACK_030_INT_D.AP 1 1 0 0 .names CLK_000_c.BLIF inst_CLK_000_D0.D @@ -1260,13 +1415,46 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF inst_CLK_000_D1.AP 1 1 0 0 -.names DSACK_INT_1_.BLIF DSACK_1_ +.names SIZE_DMA_1_.BLIF SIZE_1_ 1 1 0 0 -.names inst_DTACK_DMA.BLIF DTACK +.names inst_DSACK1_INT.BLIF DSACK_1_ 1 1 0 0 -.names vcc_n_n.BLIF DSACK_0_ +.names inst_AS_000_DMA.BLIF AS_030 +1 1 +0 0 +.names inst_AS_000_INT.BLIF AS_000 +1 1 +0 0 +.names inst_DS_000_DMA.BLIF DS_030 +1 1 +0 0 +.names inst_UDS_000_INT.BLIF UDS_000 +1 1 +0 0 +.names inst_LDS_000_INT.BLIF LDS_000 +1 1 +0 0 +.names inst_A0_DMA.BLIF A0 +1 1 +0 0 +.names dsack_c_1__n.BLIF DTACK +1 1 +0 0 +.names SIZE_DMA_0_.BLIF SIZE_0_ +1 1 +0 0 +.names gnd_n_n.BLIF DSACK_0_ +1 1 +0 0 +.names BG_030.BLIF BG_030_c +1 1 +0 0 +.names BGACK_000.BLIF BGACK_000_c +1 1 +0 0 +.names CLK_030.BLIF CLK_030_c 1 1 0 0 .names CLK_000.BLIF CLK_000_c @@ -1290,6 +1478,9 @@ amiga_bus_enable_0_un0_n .names DTACK.PIN.BLIF DTACK_c 1 1 0 0 +.names VPA.BLIF VPA_c +1 1 +0 0 .names RST.BLIF RST_c 1 1 0 0 @@ -1302,102 +1493,63 @@ amiga_bus_enable_0_un0_n .names FC_1_.BLIF fc_c_1__n 1 1 0 0 -.names AS_030.BLIF AS_030_c +.names AS_030.PIN.BLIF AS_030_c 1 1 0 0 -.names DS_030.BLIF DS_030_c +.names AS_000.PIN.BLIF AS_000_c 1 1 0 0 -.names SIZE_0_.BLIF size_c_0__n +.names DS_030.PIN.BLIF DS_030_c 1 1 0 0 -.names SIZE_1_.BLIF size_c_1__n +.names UDS_000.PIN.BLIF UDS_000_c 1 1 0 0 -.names A_0_.BLIF a_c_0__n +.names LDS_000.PIN.BLIF LDS_000_c 1 1 0 0 -.names A_15_.BLIF a_15__n +.names SIZE_0_.PIN.BLIF size_c_0__n 1 1 0 0 -.names A_14_.BLIF a_14__n -1 1 -0 0 -.names A_13_.BLIF a_13__n +.names SIZE_1_.PIN.BLIF size_c_1__n 1 1 0 0 .names A_16_.BLIF a_c_16__n 1 1 0 0 -.names A_12_.BLIF a_12__n -1 1 -0 0 .names A_17_.BLIF a_c_17__n 1 1 0 0 -.names A_11_.BLIF a_11__n -1 1 -0 0 .names A_18_.BLIF a_c_18__n 1 1 0 0 -.names A_10_.BLIF a_10__n -1 1 -0 0 .names A_19_.BLIF a_c_19__n 1 1 0 0 -.names A_9_.BLIF a_9__n -1 1 -0 0 .names A_20_.BLIF a_c_20__n 1 1 0 0 -.names A_8_.BLIF a_8__n -1 1 -0 0 .names A_21_.BLIF a_c_21__n 1 1 0 0 -.names A_7_.BLIF a_7__n -1 1 -0 0 .names A_22_.BLIF a_c_22__n 1 1 0 0 -.names A_6_.BLIF a_6__n -1 1 -0 0 .names A_23_.BLIF a_c_23__n 1 1 0 0 -.names A_5_.BLIF a_5__n -1 1 -0 0 .names A_24_.BLIF a_c_24__n 1 1 0 0 -.names A_4_.BLIF a_4__n -1 1 -0 0 .names A_25_.BLIF a_c_25__n 1 1 0 0 -.names A_3_.BLIF a_3__n -1 1 -0 0 .names A_26_.BLIF a_c_26__n 1 1 0 0 -.names A_2_.BLIF a_2__n -1 1 -0 0 .names A_27_.BLIF a_c_27__n 1 1 0 0 -.names A_1_.BLIF a_1__n -1 1 -0 0 .names A_28_.BLIF a_c_28__n 1 1 0 0 @@ -1410,43 +1562,52 @@ amiga_bus_enable_0_un0_n .names A_31_.BLIF a_c_31__n 1 1 0 0 +.names A0.PIN.BLIF A0_c +1 1 +0 0 .names nEXP_SPACE.BLIF nEXP_SPACE_c 1 1 0 0 -.names BG_030.BLIF BG_030_c -1 1 -0 0 -.names BGACK_000.BLIF BGACK_000_c -1 1 -0 0 -.names CLK_030.BLIF CLK_030_c -1 1 -0 0 -.names nEXP_SPACE_c.BLIF DSACK_1_.OE -1 1 -0 0 -.names N_68.BLIF DTACK.OE +.names N_217.BLIF AS_030.OE 1 1 0 0 .names inst_BGACK_030_INTreg.BLIF AS_000.OE 1 1 0 0 +.names N_217.BLIF DS_030.OE +1 1 +0 0 .names inst_BGACK_030_INTreg.BLIF UDS_000.OE 1 1 0 0 .names inst_BGACK_030_INTreg.BLIF LDS_000.OE 1 1 0 0 +.names N_217.BLIF SIZE_0_.OE +1 1 +0 0 +.names N_217.BLIF SIZE_1_.OE +1 1 +0 0 +.names N_217.BLIF A0.OE +1 1 +0 0 +.names nEXP_SPACE_c.BLIF DSACK_1_.OE +1 1 +0 0 +.names N_217.BLIF DTACK.OE +1 1 +0 0 .names FPU_CS_INT_i.BLIF BERR.OE 1 1 0 0 -.names nEXP_SPACE_c.BLIF DSACK_0_.OE +.names gnd_n_n.BLIF DSACK_0_.OE 1 1 0 0 .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 0 0 -.names N_236.BLIF CIIN.OE +.names N_247.BLIF CIIN.OE 1 1 0 0 .end diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3 index c252ceb..c6b5cd0 100644 --- a/Logic/68030_tk.bl3 +++ b/Logic/68030_tk.bl3 @@ -1,78 +1,86 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat May 24 19:56:20 2014 +#$ DATE Sat May 24 21:59:14 2014 #$ MODULE 68030_tk -#$ PINS 59 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 SIZE_0_ DS_030 \ -# A_30_ UDS_000 A_29_ LDS_000 A_28_ nEXP_SPACE A_27_ BERR A_26_ BG_030 A_25_ BG_000 A_24_ \ -# BGACK_030 A_23_ BGACK_000 A_22_ CLK_030 A_21_ CLK_000 A_20_ CLK_OSZI A_19_ CLK_DIV_OUT \ -# A_18_ CLK_EXP A_17_ FPU_CS A_16_ DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE \ -# AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ \ -# DSACK_0_ FC_0_ -#$ NODES 43 CLK_OUT_INTreg inst_BGACK_030_INTreg inst_FPU_CS_INTreg \ -# IPL_030DFFSH_0_reg inst_VMA_INTreg inst_AS_000_INTreg IPL_030DFFSH_1_reg \ -# inst_AS_030_000_SYNC inst_DTACK_SYNC IPL_030DFFSH_2_reg inst_VPA_D inst_VPA_SYNC \ -# inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D6 SM_AMIGA_5_ \ -# SM_AMIGA_6_ inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ inst_CLK_000_D3 \ -# SM_AMIGA_4_ inst_CLK_000_D5 SM_AMIGA_7_ RESETDFFRHreg SM_AMIGA_3_ SM_AMIGA_1_ \ -# inst_DTACK_DMA CLK_CNT_N_0_ CLK_CNT_N_1_ AMIGA_BUS_ENABLEDFFreg CLK_CNT_P_0_ \ -# CLK_CNT_P_1_ SM_AMIGA_2_ SM_AMIGA_0_ inst_CLK_000_D4 inst_CLK_OUT_PRE cpu_est_0_ \ -# cpu_est_1_ cpu_est_2_ cpu_est_3_reg BG_000DFFSHreg +#$ PINS 59 IPL_030_1_ IPL_030_0_ SIZE_1_ IPL_1_ IPL_0_ A_31_ DSACK_0_ FC_0_ IPL_030_2_ \ +# IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 nEXP_SPACE BERR BG_030 \ +# BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DTACK \ +# AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ +# AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ \ +# A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ +#$ NODES 47 BG_000DFFSHreg inst_BGACK_030_INTreg inst_FPU_CS_INTreg \ +# inst_VMA_INTreg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_DTACK_SYNC \ +# inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 CLK_OUT_INTreg inst_CLK_000_D2 \ +# inst_CLK_000_D6 SM_AMIGA_5_ IPL_030DFFSH_0_reg IPL_030DFFSH_1_reg inst_AS_000_INT \ +# SM_AMIGA_6_ IPL_030DFFSH_2_reg inst_UDS_000_INT inst_LDS_000_INT inst_DSACK1_INT \ +# inst_CLK_000_D3 inst_CLK_000_D5 SM_AMIGA_3_ SM_AMIGA_0_ SM_AMIGA_1_ inst_AS_000_DMA \ +# inst_DS_000_DMA SIZE_DMA_0_ SIZE_DMA_1_ inst_A0_DMA CLK_CNT_N_0_ CLK_CNT_N_1_ \ +# CLK_CNT_P_0_ CLK_CNT_P_1_ inst_CLK_000_D4 RESETDFFRHreg SM_AMIGA_7_ SM_AMIGA_4_ \ +# inst_CLK_OUT_PRE SM_AMIGA_2_ AMIGA_BUS_ENABLEDFFSHreg cpu_est_0_ cpu_est_1_ \ +# cpu_est_2_ cpu_est_3_reg .model bus68030 -.inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ -nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ -CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \ -A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \ -A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_0_.BLIF \ -IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF CLK_OUT_INTreg.BLIF \ -inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF \ -inst_VMA_INTreg.BLIF inst_AS_000_INTreg.BLIF IPL_030DFFSH_1_reg.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF IPL_030DFFSH_2_reg.BLIF \ -inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ -inst_CLK_000_D2.BLIF inst_CLK_000_D6.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_6_.BLIF \ -inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF \ -inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF inst_CLK_000_D5.BLIF SM_AMIGA_7_.BLIF \ -RESETDFFRHreg.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF \ -CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF \ -CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF \ -inst_CLK_000_D4.BLIF inst_CLK_OUT_PRE.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \ -cpu_est_2_.BLIF cpu_est_3_reg.BLIF BG_000DFFSHreg.BLIF DSACK_1_.PIN.BLIF \ -DTACK.PIN.BLIF -.outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ -CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C \ -cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.C \ -cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR SM_AMIGA_5_.D \ -SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \ -SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \ -SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D \ -SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_N_0_.D CLK_CNT_N_0_.C CLK_CNT_N_0_.AR \ -CLK_CNT_N_1_.D CLK_CNT_N_1_.C CLK_CNT_N_1_.AP CLK_CNT_P_0_.D CLK_CNT_P_0_.C \ -CLK_CNT_P_0_.AR CLK_CNT_P_1_.D CLK_CNT_P_1_.C CLK_CNT_P_1_.AR \ -IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ -IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ -IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D \ -SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ -inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP \ -inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP \ -inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_VMA_INTreg.C \ -inst_VMA_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \ +.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ +BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \ +RW.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF \ +A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF \ +A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF BG_000DFFSHreg.BLIF \ +inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF inst_VMA_INTreg.BLIF \ +inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF inst_DTACK_SYNC.BLIF \ +inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ +CLK_OUT_INTreg.BLIF inst_CLK_000_D2.BLIF inst_CLK_000_D6.BLIF SM_AMIGA_5_.BLIF \ +IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_1_reg.BLIF inst_AS_000_INT.BLIF \ +SM_AMIGA_6_.BLIF IPL_030DFFSH_2_reg.BLIF inst_UDS_000_INT.BLIF \ +inst_LDS_000_INT.BLIF inst_DSACK1_INT.BLIF inst_CLK_000_D3.BLIF \ +inst_CLK_000_D5.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_1_.BLIF \ +inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF \ +inst_A0_DMA.BLIF CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF CLK_CNT_P_0_.BLIF \ +CLK_CNT_P_1_.BLIF inst_CLK_000_D4.BLIF RESETDFFRHreg.BLIF SM_AMIGA_7_.BLIF \ +SM_AMIGA_4_.BLIF inst_CLK_OUT_PRE.BLIF SM_AMIGA_2_.BLIF \ +AMIGA_BUS_ENABLEDFFSHreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ +cpu_est_3_reg.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF DS_030.PIN.BLIF \ +UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF \ +A0.PIN.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +.outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ +AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR \ +cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.C cpu_est_3_reg.AR \ +cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \ +SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \ +SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ +SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_P_1_.D CLK_CNT_P_1_.C \ +CLK_CNT_P_1_.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP SIZE_DMA_1_.D \ +SIZE_DMA_1_.C SIZE_DMA_1_.AP IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C \ +IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C \ +IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C \ +IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D \ +SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR \ +inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_DSACK1_INT.D \ +inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_VMA_INTreg.C inst_VMA_INTreg.AP \ inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP \ -inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP \ -inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR CLK_OUT_INTreg.D \ -CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_AS_030_000_SYNC.D \ -inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D \ -inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C \ -inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP \ -AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C inst_DTACK_DMA.D \ -inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_CLK_000_D5.D inst_CLK_000_D5.C \ -inst_CLK_000_D5.AP inst_CLK_000_D6.D inst_CLK_000_D6.C inst_CLK_000_D6.AP \ -inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_CLK_000_D2.D \ -inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D3.D inst_CLK_000_D3.C \ -inst_CLK_000_D3.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP inst_CLK_000_D0.D \ +CLK_CNT_N_0_.D CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.D CLK_CNT_N_1_.C \ +CLK_CNT_N_1_.AP CLK_CNT_P_0_.D CLK_CNT_P_0_.C CLK_CNT_P_0_.AR \ +inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_DTACK_SYNC.D \ +inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_A0_DMA.D inst_A0_DMA.C \ +inst_A0_DMA.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \ +inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \ +AMIGA_BUS_ENABLEDFFSHreg.C AMIGA_BUS_ENABLEDFFSHreg.AP inst_AS_000_INT.D \ +inst_AS_000_INT.C inst_AS_000_INT.AP inst_AS_030_000_SYNC.D \ +inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DS_000_DMA.D \ +inst_DS_000_DMA.C inst_DS_000_DMA.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C \ +inst_FPU_CS_INTreg.AP inst_UDS_000_INT.D inst_UDS_000_INT.C \ +inst_UDS_000_INT.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR \ +inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR inst_CLK_000_D5.D \ +inst_CLK_000_D5.C inst_CLK_000_D5.AP inst_CLK_000_D6.D inst_CLK_000_D6.C \ +inst_CLK_000_D6.AP inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP \ +inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D3.D \ +inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_BGACK_030_INT_D.D \ +inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_000_D0.D \ inst_CLK_000_D0.C inst_CLK_000_D0.AP RESETDFFRHreg.D RESETDFFRHreg.C \ RESETDFFRHreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP \ -DSACK_1_ DTACK DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE \ -BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE inst_VMA_INTreg.D.X1 \ -inst_VMA_INTreg.D.X2 cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 +SIZE_1_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 DTACK SIZE_0_ \ +DSACK_0_ AS_030.OE AS_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \ +SIZE_1_.OE A0.OE DSACK_1_.OE DTACK.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE \ +inst_VMA_INTreg.D.X1 inst_VMA_INTreg.D.X2 AMIGA_BUS_ENABLEDFFSHreg.D.X1 \ +AMIGA_BUS_ENABLEDFFSHreg.D.X2 cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 .names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.BLIF \ cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_1_.D 1010-- 1 @@ -106,25 +114,20 @@ cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_2_.D 101 0 -10 0 0-0 0 -.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.D -11- 1 -1-1 1 --00 0 -0-- 0 .names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_4_.D 01- 1 0-1 1 -00 0 1-- 0 .names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \ -SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D +SM_AMIGA_3_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.D +11-1- 1 --11- 1 -11--1 1 --1-1 1 -00-- 0 0-0-- 0 +--00- 0 ---00 0 ---0-0 0 .names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \ SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_2_.D -001- 1 @@ -142,66 +145,79 @@ SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.D 01--- 0 0--0- 0 ---00 0 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D6.BLIF \ -inst_CLK_000_D5.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D --0-01- 1 --01-1- 1 -0----1 1 --0---1 1 -11---- 0 ---01-0 0 +.names inst_CLK_000_D0.BLIF inst_CLK_000_D6.BLIF inst_AS_000_INT.BLIF \ +inst_CLK_000_D5.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.D +--0-1- 1 +0--0-1 1 +01---1 1 +0---1- 1 +-0-10- 0 +1-1--- 0 +1---0- 0 ----00 0 --1---0 0 -.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF CLK_CNT_N_0_.D -00 1 -11 1 -10 0 -01 0 -.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF CLK_CNT_P_0_.D -00 1 -11 1 -10 0 -01 0 -.names IPL_0_.BLIF IPL_030DFFSH_0_reg.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF IPL_030DFFSH_0_reg.D -1-10 1 --10- 1 --1-1 1 -0-10 0 --00- 0 --0-1 0 -.names IPL_1_.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF IPL_030DFFSH_1_reg.D -1-10 1 --10- 1 --1-1 1 -0-10 0 --00- 0 --0-1 0 -.names IPL_2_.BLIF IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF IPL_030DFFSH_2_reg.D -1-10 1 --10- 1 --1-1 1 -0-10 0 --00- 0 --0-1 0 -.names nEXP_SPACE.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \ -inst_CLK_000_D0.BLIF inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF \ -inst_CLK_000_D3.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.D -0--0-1--- 1 --1-1----1 1 -------01- 1 -----1--1- 1 ---1----1- 1 --0010-1-- 0 ---00001-- 0 -1-000-1-- 0 ---010-1-0 0 --0-1---0- 0 ----0-0-0- 0 -1--0---0- 0 ----1---00 0 +.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +SIZE_DMA_0_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +SIZE_DMA_0_.D +-1-1--- 1 +-0---1- 1 +-0--1-- 1 +10----- 1 +-10---- 1 +-0----1 1 +00--000 0 +-110--- 0 +.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +SIZE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +SIZE_DMA_1_.D +-1-1--- 1 +-0---00 1 +-0---11 1 +-0--1-- 1 +10----- 1 +-10---- 1 +00--010 0 +00--001 0 +-110--- 0 +.names IPL_0_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ +IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_0_reg.D +110- 1 +--11 1 +-0-1 1 +010- 0 +--10 0 +-0-0 0 +.names IPL_1_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ +IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_1_reg.D +110- 1 +--11 1 +-0-1 1 +010- 0 +--10 0 +-0-0 0 +.names IPL_2_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ +IPL_030DFFSH_2_reg.BLIF IPL_030DFFSH_2_reg.D +110- 1 +--11 1 +-0-1 1 +010- 0 +--10 0 +-0-0 0 +.names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF \ +inst_CLK_000_D2.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF \ +inst_CLK_000_D3.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_7_.D +--1-1--1- 1 +0-0--1--- 1 +------0-1 1 +---1----1 1 +-1------1 1 +-010--10- 0 +-000-01-- 0 +-0100-1-- 0 +1000--1-- 0 +--1----00 0 +--0--0--0 0 +--1-0---0 0 +1-0-----0 0 .names nEXP_SPACE.BLIF inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF \ inst_CLK_000_D2.BLIF SM_AMIGA_6_.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_7_.BLIF \ SM_AMIGA_6_.D @@ -213,67 +229,38 @@ SM_AMIGA_6_.D -----01 0 ---1--1 0 -1----1 0 -.names AS_030.BLIF DS_030.BLIF RW.BLIF A_0_.BLIF SM_AMIGA_5_.BLIF \ -inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D --0111-- 1 ---1-01- 1 --001--1 1 ---0--10 1 --1---1- 1 -1-1-0-- 1 -1-0---0 1 -11----- 1 --0101-- 0 -0-1-00- 0 --000--1 0 -0-0--00 0 -01---0- 0 -.names SIZE_1_.BLIF AS_030.BLIF DS_030.BLIF RW.BLIF SIZE_0_.BLIF A_0_.BLIF \ -SM_AMIGA_5_.BLIF inst_LDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF \ -inst_LDS_000_INTreg.D -0-01101-- 1 -0-0010--1 1 ----1--01- 1 --1-1--0-- 1 ----0---10 1 --1-0----0 1 ---1----1- 1 --11------ 1 --0-1--00- 0 --01----0- 0 ---01-11-- 0 ---010-1-- 0 -1-01--1-- 0 --0-0---00 0 ---00-1--1 0 ---000---1 0 -1-00----1 0 -.names AS_030.BLIF inst_VMA_INTreg.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF \ -inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF cpu_est_1_.BLIF cpu_est_3_reg.BLIF \ +.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_5_.D +11- 1 +1-1 1 +-00 0 +0-- 0 +.names VPA.BLIF inst_VMA_INTreg.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \ +SM_AMIGA_3_.BLIF cpu_est_1_.BLIF cpu_est_3_reg.BLIF AS_030.PIN.BLIF \ inst_VPA_SYNC.D ----1--1- 1 ----1-0-- 1 ----10--- 1 ---11---- 1 --1-1---- 1 ----1---0 1 -1-----1- 1 -1----0-- 1 -1---0--- 1 +--1---0- 1 +--1--1-- 1 +--1-0--- 1 +--10---- 1 +-11----- 1 1-1----- 1 -11------ 1 -1------0 1 --00-1101 0 -0--0---- 0 -.names AS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF CLK_000.BLIF SM_AMIGA_7_.BLIF \ -BG_000DFFSHreg.BLIF BG_000DFFSHreg.D ---1--- 1 -----01 1 ----0-1 1 --0---1 1 -0----1 1 -11011- 0 ---0--0 0 +------01 1 +-----1-1 1 +----0--1 1 +---0---1 1 +-1-----1 1 +1------1 1 +00-1101- 0 +--0----0 0 +.names inst_CLK_000_D6.BLIF inst_DSACK1_INT.BLIF inst_CLK_000_D5.BLIF \ +SM_AMIGA_1_.BLIF AS_030.PIN.BLIF inst_DSACK1_INT.D +-1-0- 1 +-10-- 1 +11--- 1 +---01 1 +--0-1 1 +1---1 1 +0-11- 0 +-0--0 0 .names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \ inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D 1-10 1 @@ -281,12 +268,165 @@ inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D -00- 0 0--- 0 -0-1 0 -.names AS_030.BLIF inst_AS_000_INTreg.BLIF SM_AMIGA_5_.BLIF \ -inst_AS_000_INTreg.D --10 1 -1-0 1 -00- 0 ---1 0 +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF CLK_CNT_N_0_.D +00 1 +11 1 +10 0 +01 0 +.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF CLK_CNT_P_0_.D +00 1 +11 1 +10 0 +01 0 +.names RW.BLIF SM_AMIGA_5_.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_4_.BLIF \ +AS_030.PIN.BLIF DS_030.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF \ +inst_LDS_000_INT.D +0--1-0100 1 +11---0100 1 +0--01---- 1 +10--1---- 1 +0-10----- 1 +101------ 1 +----11--- 1 +--1--1--- 1 +0--1-0-1- 0 +11---0-1- 0 +0--1-00-- 0 +11---00-- 0 +0-000---- 0 +100-0---- 0 +0--1-0--1 0 +11---0--1 0 +--0-01--- 0 +.names VPA.BLIF inst_DTACK_SYNC.BLIF inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF \ +AS_030.PIN.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D +-1-0-- 1 +-10--- 1 +01---- 1 +-1---1 1 +---01- 1 +--0-1- 1 +0---1- 1 +----11 1 +1-11-0 0 +-0--0- 0 +.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_A0_DMA.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +inst_A0_DMA.D +00--010 1 +-111--- 1 +-1-0--- 0 +-10---- 0 +-0---0- 0 +-0--1-- 0 +10----- 0 +-0----1 0 +.names nEXP_SPACE.BLIF BG_030.BLIF CLK_000.BLIF BG_000DFFSHreg.BLIF \ +SM_AMIGA_7_.BLIF AS_030.PIN.BLIF BG_000DFFSHreg.D +---10- 1 +--01-- 1 +0--1-- 1 +---1-0 1 +-1---- 1 +101-11 0 +-0-0-- 0 +.names CLK_030.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_AS_000_DMA.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \ +inst_AS_000_DMA.D +-1-1--- 1 +-0--1-- 1 +10----- 1 +-0---11 1 +-10---- 1 +00--00- 0 +00--0-0 0 +-110--- 0 +.names SM_AMIGA_5_.BLIF inst_AS_000_INT.BLIF AS_030.PIN.BLIF inst_AS_000_INT.D +01- 1 +0-1 1 +-00 0 +1-- 0 +.names FC_1_.BLIF nEXP_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF \ +A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF inst_AS_030_000_SYNC.BLIF \ +inst_CLK_000_D6.BLIF SM_AMIGA_6_.BLIF inst_CLK_000_D5.BLIF SM_AMIGA_1_.BLIF \ +SM_AMIGA_7_.BLIF AS_030.PIN.BLIF inst_AS_030_000_SYNC.D +1-1-001011------ 1 +----------0-11-- 1 +-0---------1---- 1 +---------1----0- 1 +---0-----1------ 1 +-0-------1------ 1 +---------------1 1 +---------0-0-0-0 0 +---------0-00--0 0 +---------010---0 0 +-1-1----0----010 0 +-1-1---1-----010 0 +-1-1--0------010 0 +-1-1-1-------010 0 +-1-11--------010 0 +-101---------010 0 +01-1---------010 0 +-1-1----0---0-10 0 +-1-1---1----0-10 0 +-1-1--0-----0-10 0 +-1-1-1------0-10 0 +-1-11-------0-10 0 +-101--------0-10 0 +01-1--------0-10 0 +-1-1----0-1---10 0 +-1-1---1--1---10 0 +-1-1--0---1---10 0 +-1-1-1----1---10 0 +-1-11-----1---10 0 +-101------1---10 0 +01-1------1---10 0 +-1-------0---0-0 0 +-1-------0--0--0 0 +-1-------01----0 0 +.names CLK_030.BLIF RW.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF \ +AS_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_DS_000_DMA.D +--1--1--- 1 +-00-1---- 1 +--0---1-- 1 +1-0------ 1 +--0----11 1 +--10----- 1 +0-0-0-00- 0 +010---00- 0 +--11-0--- 0 +0-0-0-0-0 0 +010---0-0 0 +.names FC_1_.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF \ +A_16_.BLIF FC_0_.BLIF inst_FPU_CS_INTreg.BLIF AS_030.PIN.BLIF \ +inst_FPU_CS_INTreg.D +-------01- 1 +------1-1- 1 +-----0--1- 1 +----1---1- 1 +---1----1- 1 +--0-----1- 1 +-0------1- 1 +0-------1- 1 +---------1 1 +11100101-0 0 +--------00 0 +.names RW.BLIF SM_AMIGA_5_.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_4_.BLIF \ +AS_030.PIN.BLIF DS_030.PIN.BLIF A0.PIN.BLIF inst_UDS_000_INT.D +0-10--- 1 +101---- 1 +0--1-01 1 +11---01 1 +0--01-- 1 +10--1-- 1 +--1--1- 1 +----11- 1 +0--1-00 0 +11---00 0 +0-000-- 0 +100-0-- 0 +--0-01- 0 .names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF \ inst_CLK_OUT_PRE.D 1010 1 @@ -297,105 +437,9 @@ inst_CLK_OUT_PRE.D 11-- 0 --00 0 --11 0 -.names FC_1_.BLIF AS_030.BLIF nEXP_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF \ -A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_CLK_000_D6.BLIF SM_AMIGA_6_.BLIF \ -inst_CLK_000_D5.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_1_.BLIF inst_AS_030_000_SYNC.D -1--1-001011----- 1 ------------0-1-1 1 ---0---------1--- 1 -----------1---0- 1 -----0-----1----- 1 ---0-------1----- 1 --1-------------- 1 --0--------0-00-- 0 --0--------010--- 0 --01-1----0---01- 0 --01-1---1----01- 0 --01-1--0-----01- 0 --01-1-1------01- 0 --01-11-------01- 0 --0101--------01- 0 -001-1--------01- 0 --01-1----0-1--1- 0 --01-1---1--1--1- 0 --01-1--0---1--1- 0 --01-1-1----1--1- 0 --01-11-----1--1- 0 --0101------1--1- 0 -001-1------1--1- 0 --0--------0-0--0 0 --01-1----0----10 0 --01-1---1-----10 0 --01-1--0------10 0 --01-1-1-------10 0 --01-11--------10 0 --0101---------10 0 -001-1---------10 0 --01-------0--0-- 0 --01-------01---- 0 --01-------0----0 0 -.names AS_030.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF \ -SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D --1--0- 1 --1-0-- 1 --10--- 1 --1---1 1 -1---0- 1 -1--0-- 1 -1-0--- 1 -1----1 1 ---1110 0 -00---- 0 -.names FC_1_.BLIF AS_030.BLIF BGACK_000.BLIF CLK_030.BLIF A_19_.BLIF \ -A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF inst_FPU_CS_INTreg.BLIF \ -inst_FPU_CS_INTreg.D --1-------- 1 ---------01 1 --------1-1 1 -------0--1 1 ------1---1 1 -----1----1 1 ----0-----1 1 ---0------1 1 -0--------1 1 -101100101- 0 --0-------0 0 -.names AS_030.BLIF inst_CLK_000_D6.BLIF DSACK_INT_1_.BLIF inst_CLK_000_D5.BLIF \ -SM_AMIGA_1_.BLIF DSACK_INT_1_.D ---10- 1 --11-- 1 ---1-0 1 -1--0- 1 -11--- 1 -1---0 1 --0-11 0 -0-0-- 0 -.names AS_030.BLIF nEXP_SPACE.BLIF RST.BLIF SM_AMIGA_6_.BLIF \ -AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D -1-10- 1 --011- 1 ----01 1 ---0-1 1 --111- 0 -0--00 0 ---0-0 0 -.names inst_AS_000_INTreg.BLIF DSACK_1_.PIN.BLIF inst_DTACK_DMA.D -1- 1 --1 1 -00 0 .names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ 1 1 0 0 -.names inst_AS_000_INTreg.BLIF AS_000 -1 1 -0 0 -.names inst_UDS_000_INTreg.BLIF UDS_000 -1 1 -0 0 -.names inst_LDS_000_INTreg.BLIF LDS_000 -1 1 -0 0 .names BERR 0 .names BG_000DFFSHreg.BLIF BG_000 @@ -426,12 +470,14 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names RESETDFFRHreg.BLIF RESET 1 1 0 0 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE +.names AMIGA_BUS_ENABLEDFFSHreg.BLIF AMIGA_BUS_ENABLE 1 1 0 0 -.names RW.BLIF AMIGA_BUS_DATA_DIR -0 1 -1 0 +.names RW.BLIF inst_BGACK_030_INTreg.BLIF AMIGA_BUS_DATA_DIR +10 1 +01 1 +00 0 +11 0 .names AMIGA_BUS_ENABLE_LOW 1 .names A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF CIIN @@ -470,12 +516,6 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names RST.BLIF cpu_est_0_.AR 0 1 1 0 -.names CLK_OSZI.BLIF SM_AMIGA_5_.C -1 1 -0 0 -.names RST.BLIF SM_AMIGA_5_.AR -0 1 -1 0 .names CLK_OSZI.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -506,27 +546,6 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names RST.BLIF SM_AMIGA_0_.AR 0 1 1 0 -.names CLK_OSZI.BLIF CLK_CNT_N_0_.C -0 1 -1 0 -.names RST.BLIF CLK_CNT_N_0_.AR -0 1 -1 0 -.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D -1 1 -0 0 -.names CLK_OSZI.BLIF CLK_CNT_N_1_.C -0 1 -1 0 -.names RST.BLIF CLK_CNT_N_1_.AP -0 1 -1 0 -.names CLK_OSZI.BLIF CLK_CNT_P_0_.C -1 1 -0 0 -.names RST.BLIF CLK_CNT_P_0_.AR -0 1 -1 0 .names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.D 1 1 0 0 @@ -536,6 +555,18 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names RST.BLIF CLK_CNT_P_1_.AR 0 1 1 0 +.names CLK_OSZI.BLIF SIZE_DMA_0_.C +1 1 +0 0 +.names RST.BLIF SIZE_DMA_0_.AP +0 1 +1 0 +.names CLK_OSZI.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names RST.BLIF SIZE_DMA_1_.AP +0 1 +1 0 .names CLK_OSZI.BLIF IPL_030DFFSH_0_reg.C 1 1 0 0 @@ -566,16 +597,10 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names RST.BLIF SM_AMIGA_6_.AR 0 1 1 0 -.names CLK_OSZI.BLIF inst_UDS_000_INTreg.C +.names CLK_OSZI.BLIF SM_AMIGA_5_.C 1 1 0 0 -.names RST.BLIF inst_UDS_000_INTreg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_LDS_000_INTreg.C -1 1 -0 0 -.names RST.BLIF inst_LDS_000_INTreg.AP +.names RST.BLIF SM_AMIGA_5_.AR 0 1 1 0 .names CLK_OSZI.BLIF inst_VPA_SYNC.C @@ -584,34 +609,109 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names RST.BLIF inst_VPA_SYNC.AP 0 1 1 0 +.names CLK_OSZI.BLIF inst_DSACK1_INT.C +1 1 +0 0 +.names RST.BLIF inst_DSACK1_INT.AP +0 1 +1 0 .names CLK_OSZI.BLIF inst_VMA_INTreg.C 1 1 0 0 .names RST.BLIF inst_VMA_INTreg.AP 0 1 1 0 -.names CLK_OSZI.BLIF BG_000DFFSHreg.C -1 1 -0 0 -.names RST.BLIF BG_000DFFSHreg.AP -0 1 -1 0 .names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 .names RST.BLIF inst_BGACK_030_INTreg.AP 0 1 1 0 -.names CLK_OSZI.BLIF inst_AS_000_INTreg.C -1 1 -0 0 -.names RST.BLIF inst_AS_000_INTreg.AP +.names CLK_OSZI.BLIF CLK_CNT_N_0_.C 0 1 1 0 -.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C +.names RST.BLIF CLK_CNT_N_0_.AR +0 1 +1 0 +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D 1 1 0 0 -.names RST.BLIF inst_CLK_OUT_PRE.AR +.names CLK_OSZI.BLIF CLK_CNT_N_1_.C +0 1 +1 0 +.names RST.BLIF CLK_CNT_N_1_.AP +0 1 +1 0 +.names CLK_OSZI.BLIF CLK_CNT_P_0_.C +1 1 +0 0 +.names RST.BLIF CLK_CNT_P_0_.AR +0 1 +1 0 +.names CLK_OSZI.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names RST.BLIF inst_LDS_000_INT.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_DTACK_SYNC.C +1 1 +0 0 +.names RST.BLIF inst_DTACK_SYNC.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_A0_DMA.C +1 1 +0 0 +.names RST.BLIF inst_A0_DMA.AP +0 1 +1 0 +.names CLK_OSZI.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST.BLIF BG_000DFFSHreg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_AS_000_DMA.C +1 1 +0 0 +.names RST.BLIF inst_AS_000_DMA.AP +0 1 +1 0 +.names CLK_OSZI.BLIF AMIGA_BUS_ENABLEDFFSHreg.C +1 1 +0 0 +.names RST.BLIF AMIGA_BUS_ENABLEDFFSHreg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_AS_000_INT.C +1 1 +0 0 +.names RST.BLIF inst_AS_000_INT.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names RST.BLIF inst_AS_030_000_SYNC.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_DS_000_DMA.C +1 1 +0 0 +.names RST.BLIF inst_DS_000_DMA.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_FPU_CS_INTreg.C +1 1 +0 0 +.names RST.BLIF inst_FPU_CS_INTreg.AP +0 1 +1 0 +.names CLK_OSZI.BLIF inst_UDS_000_INT.C +1 1 +0 0 +.names RST.BLIF inst_UDS_000_INT.AP 0 1 1 0 .names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D @@ -623,37 +723,10 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names RST.BLIF CLK_OUT_INTreg.AR 0 1 1 0 -.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C +.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C 1 1 0 0 -.names RST.BLIF inst_AS_030_000_SYNC.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_DTACK_SYNC.C -1 1 -0 0 -.names RST.BLIF inst_DTACK_SYNC.AP -0 1 -1 0 -.names CLK_OSZI.BLIF inst_FPU_CS_INTreg.C -1 1 -0 0 -.names RST.BLIF inst_FPU_CS_INTreg.AP -0 1 -1 0 -.names CLK_OSZI.BLIF DSACK_INT_1_.C -1 1 -0 0 -.names RST.BLIF DSACK_INT_1_.AP -0 1 -1 0 -.names CLK_OSZI.BLIF AMIGA_BUS_ENABLEDFFreg.C -1 1 -0 0 -.names CLK_OSZI.BLIF inst_DTACK_DMA.C -1 1 -0 0 -.names RST.BLIF inst_DTACK_DMA.AP +.names RST.BLIF inst_CLK_OUT_PRE.AR 0 1 1 0 .names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D @@ -701,13 +774,13 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names RST.BLIF inst_CLK_000_D3.AP 0 1 1 0 -.names VPA.BLIF inst_VPA_D.D +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D 1 1 0 0 -.names CLK_OSZI.BLIF inst_VPA_D.C +.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 -.names RST.BLIF inst_VPA_D.AP +.names RST.BLIF inst_BGACK_030_INT_D.AP 0 1 1 0 .names CLK_000.BLIF inst_CLK_000_D0.D @@ -736,14 +809,67 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D .names RST.BLIF inst_CLK_000_D1.AP 0 1 1 0 -.names DSACK_INT_1_.BLIF DSACK_1_ +.names SIZE_DMA_1_.BLIF SIZE_1_ 1 1 0 0 -.names inst_DTACK_DMA.BLIF DTACK +.names inst_DSACK1_INT.BLIF DSACK_1_ +1 1 +0 0 +.names inst_AS_000_DMA.BLIF AS_030 +1 1 +0 0 +.names inst_AS_000_INT.BLIF AS_000 +1 1 +0 0 +.names inst_DS_000_DMA.BLIF DS_030 +1 1 +0 0 +.names inst_UDS_000_INT.BLIF UDS_000 +1 1 +0 0 +.names inst_LDS_000_INT.BLIF LDS_000 +1 1 +0 0 +.names inst_A0_DMA.BLIF A0 +1 1 +0 0 +.names DSACK_1_.PIN.BLIF DTACK +1 1 +0 0 +.names SIZE_DMA_0_.BLIF SIZE_0_ 1 1 0 0 .names DSACK_0_ - 1 + 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF AS_030.OE +00 1 +1- 0 +-1 0 +.names inst_BGACK_030_INTreg.BLIF AS_000.OE +1 1 +0 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF DS_030.OE +00 1 +1- 0 +-1 0 +.names inst_BGACK_030_INTreg.BLIF UDS_000.OE +1 1 +0 0 +.names inst_BGACK_030_INTreg.BLIF LDS_000.OE +1 1 +0 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF SIZE_0_.OE +00 1 +1- 0 +-1 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF SIZE_1_.OE +00 1 +1- 0 +-1 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF A0.OE +00 1 +1- 0 +-1 0 .names nEXP_SPACE.BLIF DSACK_1_.OE 1 1 0 0 @@ -751,21 +877,11 @@ AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLEDFFreg.D 00 1 1- 0 -1 0 -.names inst_BGACK_030_INTreg.BLIF AS_000.OE -1 1 -0 0 -.names inst_BGACK_030_INTreg.BLIF UDS_000.OE -1 1 -0 0 -.names inst_BGACK_030_INTreg.BLIF LDS_000.OE -1 1 -0 0 .names inst_FPU_CS_INTreg.BLIF BERR.OE 0 1 1 0 -.names nEXP_SPACE.BLIF DSACK_0_.OE -1 1 -0 0 +.names DSACK_0_.OE + 0 .names inst_FPU_CS_INTreg.BLIF AVEC_EXP.OE 0 1 1 0 @@ -784,20 +900,45 @@ A_25_.BLIF A_24_.BLIF CIIN.OE 10 1 0- 0 -1 0 -.names inst_VMA_INTreg.BLIF inst_AS_000_INTreg.BLIF inst_VPA_D.BLIF \ -inst_CLK_000_D0.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF \ -cpu_est_3_reg.BLIF inst_VMA_INTreg.D.X2 -1-0-10-- 1 -1--1---- 1 --1-10110 1 -00------ 0 ---10---- 0 -0---1--- 0 ----00--- 0 ----0-1-- 0 -0----0-- 0 -0-----0- 0 -0------1 0 +.names VPA.BLIF inst_VMA_INTreg.BLIF inst_CLK_000_D0.BLIF inst_AS_000_INT.BLIF \ +cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF \ +inst_VMA_INTreg.D.X2 +01--10-- 1 +-11----- 1 +--110110 1 +1-0----- 0 +-0-0---- 0 +-0--1--- 0 +--0-0--- 0 +--0--1-- 0 +-0---0-- 0 +-0----0- 0 +-0-----1 0 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +AMIGA_BUS_ENABLEDFFSHreg.D.X1 +01 1 +1- 0 +-0 0 +.names nEXP_SPACE.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_CLK_000_D0.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_0_.BLIF \ +AMIGA_BUS_ENABLEDFFSHreg.BLIF AMIGA_BUS_ENABLEDFFSHreg.D.X2 +0------1 1 +-----0-1 1 +---11-1- 1 +-01----- 1 +-10----- 1 +-110---0 0 +-000---0 0 +-11-0--0 0 +-00-0--0 0 +-11---00 0 +-00---00 0 +1110-1-- 0 +1000-1-- 0 +111-01-- 0 +100-01-- 0 +111--10- 0 +100--10- 0 .names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_1_.BLIF \ cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_3_reg.D.X1 10111 1 diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index 4d6727b..1315fee 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 1.7.00.05.28.13 -// Design '68030_tk' created Sat May 24 19:56:20 2014 +// Design '68030_tk' created Sat May 24 21:59:14 2014 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3 index b907aca..edc9fd4 100644 --- a/Logic/68030_tk.eq3 +++ b/Logic/68030_tk.eq3 @@ -2,25 +2,37 @@ Copyright(C), 1992-2013, Lattice Semiconductor Corp. All Rights Reserved. -Design bus68030 created Sat May 24 19:56:20 2014 +Design bus68030 created Sat May 24 21:59:14 2014 P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- + 0 0 1 Pin DSACK_0_ + 0 0 1 Pin DSACK_0_.OE 0 0 1 Pin BERR 1 1 1 Pin BERR.OE 1 1 1 Pin CLK_DIV_OUT.AR 1 1 1 Pin CLK_DIV_OUT.D 1 1 1 Pin CLK_DIV_OUT.C + 1 1 1 Pin DTACK + 1 2 1 Pin DTACK.OE 1 0 1 Pin AVEC 0 0 1 Pin AVEC_EXP 1 1 1 Pin AVEC_EXP.OE - 1 1 1 Pin AMIGA_BUS_DATA_DIR + 2 2 1 Pin AMIGA_BUS_DATA_DIR 1 0 1 Pin AMIGA_BUS_ENABLE_LOW 1 4 1 Pin CIIN 1 8 1 Pin CIIN.OE - 1 0 1 Pin DSACK_0_ - 1 1 1 Pin DSACK_0_.OE + 3 4 1 Pin IPL_030_1_.D + 1 1 1 Pin IPL_030_1_.AP + 1 1 1 Pin IPL_030_1_.C + 3 4 1 Pin IPL_030_0_.D + 1 1 1 Pin IPL_030_0_.AP + 1 1 1 Pin IPL_030_0_.C + 1 2 1 Pin SIZE_1_.OE + 3 7 1 Pin SIZE_1_.D- + 1 1 1 Pin SIZE_1_.AP + 1 1 1 Pin SIZE_1_.C 3 4 1 Pin IPL_030_2_.D 1 1 1 Pin IPL_030_2_.AP 1 1 1 Pin IPL_030_2_.C @@ -28,10 +40,18 @@ Design bus68030 created Sat May 24 19:56:20 2014 2 5 1 Pin DSACK_1_.D- 1 1 1 Pin DSACK_1_.AP 1 1 1 Pin DSACK_1_.C + 1 2 1 Pin AS_030.OE + 3 7 1 Pin AS_030.D- + 1 1 1 Pin AS_030.AP + 1 1 1 Pin AS_030.C 1 1 1 Pin AS_000.OE 2 3 1 Pin AS_000.D 1 1 1 Pin AS_000.AP 1 1 1 Pin AS_000.C + 1 2 1 Pin DS_030.OE + 5 9 1 Pin DS_030.D- + 1 1 1 Pin DS_030.AP + 1 1 1 Pin DS_030.C 1 1 1 Pin UDS_000.OE 5 7 1 Pin UDS_000.D- 1 1 1 Pin UDS_000.AP @@ -40,6 +60,10 @@ Design bus68030 created Sat May 24 19:56:20 2014 8 9 1 Pin LDS_000.D 1 1 1 Pin LDS_000.AP 1 1 1 Pin LDS_000.C + 1 2 1 Pin A0.OE + 2 7 1 Pin A0.D + 1 1 1 Pin A0.AP + 1 1 1 Pin A0.C 2 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.AP 1 1 1 Pin BG_000.C @@ -52,10 +76,6 @@ Design bus68030 created Sat May 24 19:56:20 2014 2 10 1 Pin FPU_CS.D- 1 1 1 Pin FPU_CS.AP 1 1 1 Pin FPU_CS.C - 1 2 1 Pin DTACK.OE - 1 2 1 Pin DTACK.D- - 1 1 1 Pin DTACK.AP - 1 1 1 Pin DTACK.C 3 6 1 PinX1 E.D.X1 1 1 1 PinX2 E.D.X2 1 1 1 Pin E.AR @@ -67,23 +87,22 @@ Design bus68030 created Sat May 24 19:56:20 2014 1 1 1 Pin RESET.AR 1 0 1 Pin RESET.D 1 1 1 Pin RESET.C - 3 5 1 Pin AMIGA_BUS_ENABLE.D- + 7 8 1 Pin AMIGA_BUS_ENABLE.D + 1 1 1 Pin AMIGA_BUS_ENABLE.AP 1 1 1 Pin AMIGA_BUS_ENABLE.C - 3 4 1 Pin IPL_030_1_.D - 1 1 1 Pin IPL_030_1_.AP - 1 1 1 Pin IPL_030_1_.C - 3 4 1 Pin IPL_030_0_.D - 1 1 1 Pin IPL_030_0_.AP - 1 1 1 Pin IPL_030_0_.C + 1 2 1 Pin SIZE_0_.OE + 2 7 1 Pin SIZE_0_.D- + 1 1 1 Pin SIZE_0_.AP + 1 1 1 Pin SIZE_0_.C 7 16 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C + 1 1 1 Node inst_BGACK_030_INT_D.D + 1 1 1 Node inst_BGACK_030_INT_D.AP + 1 1 1 Node inst_BGACK_030_INT_D.C 2 6 1 Node inst_DTACK_SYNC.D- 1 1 1 Node inst_DTACK_SYNC.AP 1 1 1 Node inst_DTACK_SYNC.C - 1 1 1 Node inst_VPA_D.D - 1 1 1 Node inst_VPA_D.AP - 1 1 1 Node inst_VPA_D.C 2 8 1 Node inst_VPA_SYNC.D- 1 1 1 Node inst_VPA_SYNC.AP 1 1 1 Node inst_VPA_SYNC.C @@ -108,18 +127,15 @@ Design bus68030 created Sat May 24 19:56:20 2014 1 1 1 Node inst_CLK_000_D3.D 1 1 1 Node inst_CLK_000_D3.AP 1 1 1 Node inst_CLK_000_D3.C - 1 1 1 Node SM_AMIGA_4_.AR - 2 3 1 Node SM_AMIGA_4_.D - 1 1 1 Node SM_AMIGA_4_.C 1 1 1 Node inst_CLK_000_D5.D 1 1 1 Node inst_CLK_000_D5.AP 1 1 1 Node inst_CLK_000_D5.C - 5 9 1 Node SM_AMIGA_7_.D - 1 1 1 Node SM_AMIGA_7_.AP - 1 1 1 Node SM_AMIGA_7_.C 1 1 1 Node SM_AMIGA_3_.AR 3 5 1 Node SM_AMIGA_3_.D 1 1 1 Node SM_AMIGA_3_.C + 1 1 1 Node SM_AMIGA_0_.AR + 4 6 1 Node SM_AMIGA_0_.D + 1 1 1 Node SM_AMIGA_0_.C 1 1 1 Node SM_AMIGA_1_.AR 3 5 1 Node SM_AMIGA_1_.D 1 1 1 Node SM_AMIGA_1_.C @@ -135,18 +151,21 @@ Design bus68030 created Sat May 24 19:56:20 2014 1 1 1 Node CLK_CNT_P_1_.AR 1 1 1 Node CLK_CNT_P_1_.D 1 1 1 Node CLK_CNT_P_1_.C - 1 1 1 Node SM_AMIGA_2_.AR - 3 5 1 Node SM_AMIGA_2_.D - 1 1 1 Node SM_AMIGA_2_.C - 1 1 1 Node SM_AMIGA_0_.AR - 4 6 1 Node SM_AMIGA_0_.D - 1 1 1 Node SM_AMIGA_0_.C 1 1 1 Node inst_CLK_000_D4.D 1 1 1 Node inst_CLK_000_D4.AP 1 1 1 Node inst_CLK_000_D4.C + 5 9 1 Node SM_AMIGA_7_.D + 1 1 1 Node SM_AMIGA_7_.AP + 1 1 1 Node SM_AMIGA_7_.C + 1 1 1 Node SM_AMIGA_4_.AR + 2 3 1 Node SM_AMIGA_4_.D + 1 1 1 Node SM_AMIGA_4_.C 1 1 1 Node inst_CLK_OUT_PRE.AR 4 4 1 Node inst_CLK_OUT_PRE.D 1 1 1 Node inst_CLK_OUT_PRE.C + 1 1 1 Node SM_AMIGA_2_.AR + 3 5 1 Node SM_AMIGA_2_.D + 1 1 1 Node SM_AMIGA_2_.C 1 1 1 Node cpu_est_0_.AR 3 3 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C @@ -158,7 +177,7 @@ Design bus68030 created Sat May 24 19:56:20 2014 1 1 1 Node cpu_est_2_.AR 1 1 1 Node cpu_est_2_.C ========= - 211 P-Term Total: 211 + 243 P-Term Total: 243 Total Pins: 59 Total Nodes: 27 Average P-Term/Output: 2 @@ -166,6 +185,10 @@ Design bus68030 created Sat May 24 19:56:20 2014 Equations: +DSACK_0_ = (0); + +DSACK_0_.OE = (0); + BERR = (0); BERR.OE = (!FPU_CS.Q); @@ -176,13 +199,18 @@ CLK_DIV_OUT.D = (inst_CLK_OUT_PRE.Q); CLK_DIV_OUT.C = (CLK_OSZI); +DTACK = (DSACK_1_.PIN); + +DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q); + AVEC = (1); AVEC_EXP = (0); AVEC_EXP.OE = (!FPU_CS.Q); -AMIGA_BUS_DATA_DIR = (!RW); +AMIGA_BUS_DATA_DIR = (!RW & BGACK_030.Q + # RW & !BGACK_030.Q); AMIGA_BUS_ENABLE_LOW = (1); @@ -190,12 +218,34 @@ CIIN = (A_23_ & A_22_ & A_21_ & A_20_); CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_); -DSACK_0_ = (1); +IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q + # inst_CLK_000_D1.Q & IPL_030_1_.Q + # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); -DSACK_0_.OE = (nEXP_SPACE); +IPL_030_1_.AP = (!RST); -IPL_030_2_.D = (IPL_030_2_.Q & !inst_CLK_000_D0.Q - # IPL_030_2_.Q & inst_CLK_000_D1.Q +IPL_030_1_.C = (CLK_OSZI); + +IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q + # inst_CLK_000_D1.Q & IPL_030_0_.Q + # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); + +IPL_030_0_.AP = (!RST); + +IPL_030_0_.C = (CLK_OSZI); + +SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q); + +!SIZE_1_.D = (BGACK_030.Q & inst_BGACK_030_INT_D.Q & !SIZE_1_.Q + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & LDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN); + +SIZE_1_.AP = (!RST); + +SIZE_1_.C = (CLK_OSZI); + +IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q + # inst_CLK_000_D1.Q & IPL_030_2_.Q # IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); IPL_030_2_.AP = (!RST); @@ -204,29 +254,51 @@ IPL_030_2_.C = (CLK_OSZI); DSACK_1_.OE = (nEXP_SPACE); -!DSACK_1_.D = (!AS_030 & !DSACK_1_.Q +!DSACK_1_.D = (!DSACK_1_.Q & !AS_030.PIN # !inst_CLK_000_D6.Q & inst_CLK_000_D5.Q & SM_AMIGA_1_.Q); DSACK_1_.AP = (!RST); DSACK_1_.C = (CLK_OSZI); +AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q); + +!AS_030.D = (BGACK_030.Q & inst_BGACK_030_INT_D.Q & !AS_030.Q + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !LDS_000.PIN); + +AS_030.AP = (!RST); + +AS_030.C = (CLK_OSZI); + AS_000.OE = (BGACK_030.Q); -AS_000.D = (AS_030 & !SM_AMIGA_5_.Q - # AS_000.Q & !SM_AMIGA_5_.Q); +AS_000.D = (!SM_AMIGA_5_.Q & AS_000.Q + # !SM_AMIGA_5_.Q & AS_030.PIN); AS_000.AP = (!RST); AS_000.C = (CLK_OSZI); +DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q); + +!DS_030.D = (BGACK_030.Q & inst_BGACK_030_INT_D.Q & !DS_030.Q + # !CLK_030 & RW & !BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !UDS_000.PIN + # !CLK_030 & RW & !BGACK_030.Q & !AS_000.PIN & !LDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !LDS_000.PIN); + +DS_030.AP = (!RST); + +DS_030.C = (CLK_OSZI); + UDS_000.OE = (BGACK_030.Q); -!UDS_000.D = (!AS_030 & DS_030 & !UDS_000.Q - # !DS_030 & RW & !A_0_ & SM_AMIGA_5_.Q - # !AS_030 & RW & !SM_AMIGA_5_.Q & !UDS_000.Q - # !DS_030 & !RW & !A_0_ & SM_AMIGA_4_.Q - # !AS_030 & !RW & !UDS_000.Q & !SM_AMIGA_4_.Q); +!UDS_000.D = (!UDS_000.Q & !AS_030.PIN & DS_030.PIN + # RW & !SM_AMIGA_5_.Q & !UDS_000.Q & !AS_030.PIN + # !RW & !UDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN + # RW & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN + # !RW & SM_AMIGA_4_.Q & !DS_030.PIN & !A0.PIN); UDS_000.AP = (!RST); @@ -234,21 +306,30 @@ UDS_000.C = (CLK_OSZI); LDS_000.OE = (BGACK_030.Q); -LDS_000.D = (AS_030 & DS_030 - # DS_030 & LDS_000.Q - # AS_030 & RW & !SM_AMIGA_5_.Q +LDS_000.D = (LDS_000.Q & DS_030.PIN + # AS_030.PIN & DS_030.PIN # RW & !SM_AMIGA_5_.Q & LDS_000.Q - # AS_030 & !RW & !SM_AMIGA_4_.Q # !RW & LDS_000.Q & !SM_AMIGA_4_.Q - # !SIZE_1_ & !DS_030 & RW & SIZE_0_ & !A_0_ & SM_AMIGA_5_.Q - # !SIZE_1_ & !DS_030 & !RW & SIZE_0_ & !A_0_ & SM_AMIGA_4_.Q); + # RW & !SM_AMIGA_5_.Q & AS_030.PIN + # !RW & !SM_AMIGA_4_.Q & AS_030.PIN + # RW & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN + # !RW & SM_AMIGA_4_.Q & !DS_030.PIN & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN); LDS_000.AP = (!RST); LDS_000.C = (CLK_OSZI); +A0.OE = (!nEXP_SPACE & !BGACK_030.Q); + +A0.D = (BGACK_030.Q & inst_BGACK_030_INT_D.Q & A0.Q + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN); + +A0.AP = (!RST); + +A0.C = (CLK_OSZI); + !BG_000.D = (!BG_030 & !BG_000.Q - # AS_030 & nEXP_SPACE & !BG_030 & CLK_000 & SM_AMIGA_7_.Q); + # nEXP_SPACE & !BG_030 & CLK_000 & SM_AMIGA_7_.Q & AS_030.PIN); BG_000.AP = (!RST); @@ -267,21 +348,13 @@ CLK_EXP.D = (inst_CLK_OUT_PRE.Q); CLK_EXP.C = (CLK_OSZI); -!FPU_CS.D = (!AS_030 & !FPU_CS.Q - # FC_1_ & !AS_030 & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_); +!FPU_CS.D = (!FPU_CS.Q & !AS_030.PIN + # FC_1_ & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); FPU_CS.AP = (!RST); FPU_CS.C = (CLK_OSZI); -DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q); - -!DTACK.D = (!AS_000.Q & !DSACK_1_.PIN); - -DTACK.AP = (!RST); - -DTACK.C = (CLK_OSZI); - E.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_1_.Q & cpu_est_2_.Q & E.Q # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & !E.Q # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q); @@ -293,9 +366,9 @@ E.AR = (!RST); E.C = (CLK_OSZI); VMA.D.X1 = (VMA.Q - # !VMA.Q & AS_000.Q & inst_CLK_000_D0.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & !E.Q); + # !VMA.Q & inst_CLK_000_D0.Q & AS_000.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & !E.Q); -VMA.D.X2 = (VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & cpu_est_0_.Q & !cpu_est_1_.Q); +VMA.D.X2 = (!VPA & VMA.Q & !inst_CLK_000_D0.Q & cpu_est_0_.Q & !cpu_est_1_.Q); VMA.AP = (!RST); @@ -307,29 +380,28 @@ RESET.D = (1); RESET.C = (CLK_OSZI); -!AMIGA_BUS_ENABLE.D = (!RST & !AMIGA_BUS_ENABLE.Q - # nEXP_SPACE & RST & SM_AMIGA_6_.Q - # !AS_030 & !SM_AMIGA_6_.Q & !AMIGA_BUS_ENABLE.Q); +AMIGA_BUS_ENABLE.D = (BGACK_030.Q & !inst_BGACK_030_INT_D.Q + # !nEXP_SPACE & BGACK_030.Q & AMIGA_BUS_ENABLE.Q + # !nEXP_SPACE & !inst_BGACK_030_INT_D.Q & AMIGA_BUS_ENABLE.Q + # BGACK_030.Q & !SM_AMIGA_6_.Q & AMIGA_BUS_ENABLE.Q + # !inst_BGACK_030_INT_D.Q & !SM_AMIGA_6_.Q & AMIGA_BUS_ENABLE.Q + # BGACK_030.Q & inst_CLK_000_D0.Q & AS_000.Q & SM_AMIGA_0_.Q + # !inst_BGACK_030_INT_D.Q & inst_CLK_000_D0.Q & AS_000.Q & SM_AMIGA_0_.Q); + +AMIGA_BUS_ENABLE.AP = (!RST); AMIGA_BUS_ENABLE.C = (CLK_OSZI); -IPL_030_1_.D = (IPL_030_1_.Q & !inst_CLK_000_D0.Q - # IPL_030_1_.Q & inst_CLK_000_D1.Q - # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); +SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); -IPL_030_1_.AP = (!RST); +!SIZE_0_.D = (BGACK_030.Q & inst_BGACK_030_INT_D.Q & !SIZE_0_.Q + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN); -IPL_030_1_.C = (CLK_OSZI); +SIZE_0_.AP = (!RST); -IPL_030_0_.D = (IPL_030_0_.Q & !inst_CLK_000_D0.Q - # IPL_030_0_.Q & inst_CLK_000_D1.Q - # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); +SIZE_0_.C = (CLK_OSZI); -IPL_030_0_.AP = (!RST); - -IPL_030_0_.C = (CLK_OSZI); - -inst_AS_030_000_SYNC.D = (AS_030 +inst_AS_030_000_SYNC.D = (AS_030.PIN # !nEXP_SPACE & inst_AS_030_000_SYNC.Q # !CLK_030 & inst_AS_030_000_SYNC.Q # !nEXP_SPACE & SM_AMIGA_6_.Q @@ -341,21 +413,21 @@ inst_AS_030_000_SYNC.AP = (!RST); inst_AS_030_000_SYNC.C = (CLK_OSZI); -!inst_DTACK_SYNC.D = (!AS_030 & !inst_DTACK_SYNC.Q - # inst_VPA_D.Q & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !DTACK.PIN); +inst_BGACK_030_INT_D.D = (BGACK_030.Q); + +inst_BGACK_030_INT_D.AP = (!RST); + +inst_BGACK_030_INT_D.C = (CLK_OSZI); + +!inst_DTACK_SYNC.D = (!inst_DTACK_SYNC.Q & !AS_030.PIN + # VPA & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !DTACK.PIN); inst_DTACK_SYNC.AP = (!RST); inst_DTACK_SYNC.C = (CLK_OSZI); -inst_VPA_D.D = (VPA); - -inst_VPA_D.AP = (!RST); - -inst_VPA_D.C = (CLK_OSZI); - -!inst_VPA_SYNC.D = (!AS_030 & !inst_VPA_SYNC.Q - # !VMA.Q & !inst_VPA_D.Q & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); +!inst_VPA_SYNC.D = (!inst_VPA_SYNC.Q & !AS_030.PIN + # !VPA & !VMA.Q & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); inst_VPA_SYNC.AP = (!RST); @@ -405,37 +477,29 @@ inst_CLK_000_D3.AP = (!RST); inst_CLK_000_D3.C = (CLK_OSZI); -SM_AMIGA_4_.AR = (!RST); - -SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q - # !inst_CLK_000_D0.Q & SM_AMIGA_4_.Q); - -SM_AMIGA_4_.C = (CLK_OSZI); - inst_CLK_000_D5.D = (inst_CLK_000_D4.Q); inst_CLK_000_D5.AP = (!RST); inst_CLK_000_D5.C = (CLK_OSZI); -SM_AMIGA_7_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_7_.Q - # inst_CLK_000_D2.Q & SM_AMIGA_7_.Q - # !inst_CLK_000_D3.Q & SM_AMIGA_7_.Q - # !nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q - # AS_000.Q & inst_CLK_000_D0.Q & SM_AMIGA_0_.Q); - -SM_AMIGA_7_.AP = (!RST); - -SM_AMIGA_7_.C = (CLK_OSZI); - SM_AMIGA_3_.AR = (!RST); -SM_AMIGA_3_.D = (inst_CLK_000_D0.Q & SM_AMIGA_4_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_3_.Q +SM_AMIGA_3_.D = (inst_CLK_000_D0.Q & SM_AMIGA_3_.Q + # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q # inst_DTACK_SYNC.Q & inst_VPA_SYNC.Q & SM_AMIGA_3_.Q); SM_AMIGA_3_.C = (CLK_OSZI); +SM_AMIGA_0_.AR = (!RST); + +SM_AMIGA_0_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_0_.Q + # !AS_000.Q & SM_AMIGA_0_.Q + # !inst_CLK_000_D0.Q & inst_CLK_000_D6.Q & SM_AMIGA_1_.Q + # !inst_CLK_000_D0.Q & !inst_CLK_000_D5.Q & SM_AMIGA_1_.Q); + +SM_AMIGA_0_.C = (CLK_OSZI); + SM_AMIGA_1_.AR = (!RST); SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q @@ -470,29 +534,29 @@ CLK_CNT_P_1_.D = (CLK_CNT_P_0_.Q); CLK_CNT_P_1_.C = (CLK_OSZI); -SM_AMIGA_2_.AR = (!RST); - -SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q - # !inst_DTACK_SYNC.Q & !inst_CLK_000_D0.Q & SM_AMIGA_3_.Q - # !inst_VPA_SYNC.Q & !inst_CLK_000_D0.Q & SM_AMIGA_3_.Q); - -SM_AMIGA_2_.C = (CLK_OSZI); - -SM_AMIGA_0_.AR = (!RST); - -SM_AMIGA_0_.D = (!AS_000.Q & SM_AMIGA_0_.Q - # !inst_CLK_000_D0.Q & SM_AMIGA_0_.Q - # !inst_CLK_000_D0.Q & inst_CLK_000_D6.Q & SM_AMIGA_1_.Q - # !inst_CLK_000_D0.Q & !inst_CLK_000_D5.Q & SM_AMIGA_1_.Q); - -SM_AMIGA_0_.C = (CLK_OSZI); - inst_CLK_000_D4.D = (inst_CLK_000_D3.Q); inst_CLK_000_D4.AP = (!RST); inst_CLK_000_D4.C = (CLK_OSZI); +SM_AMIGA_7_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_7_.Q + # inst_CLK_000_D2.Q & SM_AMIGA_7_.Q + # !inst_CLK_000_D3.Q & SM_AMIGA_7_.Q + # !nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q + # inst_CLK_000_D0.Q & AS_000.Q & SM_AMIGA_0_.Q); + +SM_AMIGA_7_.AP = (!RST); + +SM_AMIGA_7_.C = (CLK_OSZI); + +SM_AMIGA_4_.AR = (!RST); + +SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q + # !inst_CLK_000_D0.Q & SM_AMIGA_4_.Q); + +SM_AMIGA_4_.C = (CLK_OSZI); + inst_CLK_OUT_PRE.AR = (!RST); inst_CLK_OUT_PRE.D = (!CLK_CNT_N_0_.Q & CLK_CNT_N_1_.Q & !CLK_CNT_P_0_.Q & CLK_CNT_P_1_.Q @@ -502,6 +566,14 @@ inst_CLK_OUT_PRE.D = (!CLK_CNT_N_0_.Q & CLK_CNT_N_1_.Q & !CLK_CNT_P_0_.Q & CLK_C inst_CLK_OUT_PRE.C = (CLK_OSZI); +SM_AMIGA_2_.AR = (!RST); + +SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q + # !inst_DTACK_SYNC.Q & !inst_CLK_000_D0.Q & SM_AMIGA_3_.Q + # !inst_VPA_SYNC.Q & !inst_CLK_000_D0.Q & SM_AMIGA_3_.Q); + +SM_AMIGA_2_.C = (CLK_OSZI); + cpu_est_0_.AR = (!RST); cpu_est_0_.D = (!inst_CLK_000_D0.Q & cpu_est_0_.Q diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti index 29b8365..574abc6 100644 --- a/Logic/68030_tk.fti +++ b/Logic/68030_tk.fti @@ -1,16 +1,16 @@ #PLAFILE 68030_tk.tt4 -#DATE 05/15/2014 +#DATE 05/24/2014 #DESIGN #DEVICE mach447a +DATA LOCATION A0:G_8_69 // IO {RN_A0} DATA LOCATION AMIGA_BUS_DATA_DIR:E_0_48 // OUT -DATA LOCATION AMIGA_BUS_ENABLE:D_4_34 // IO {RN_AMIGA_BUS_ENABLE} +DATA LOCATION AMIGA_BUS_ENABLE:D_5_34 // IO {RN_AMIGA_BUS_ENABLE} DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_12_20 // OUT -DATA LOCATION AS_000:D_5_33 // IO {RN_AS_000} -DATA LOCATION AS_030:H_*_82 // INP +DATA LOCATION AS_000:D_4_33 // IO {RN_AS_000} +DATA LOCATION AS_030:H_8_82 // IO {RN_AS_030} DATA LOCATION AVEC:A_4_92 // OUT DATA LOCATION AVEC_EXP:C_0_22 // OUT -DATA LOCATION A_0_:G_*_69 // INP DATA LOCATION A_16_:A_*_96 // INP DATA LOCATION A_17_:F_*_59 // INP DATA LOCATION A_18_:A_*_95 // INP @@ -35,21 +35,21 @@ DATA LOCATION BG_030:C_*_21 // INP DATA LOCATION CIIN:E_12_47 // OUT DATA LOCATION CLK_000:*_*_11 // INP DATA LOCATION CLK_030:*_*_64 // INP -DATA LOCATION CLK_CNT_N_0_:B_9 // NOD -DATA LOCATION CLK_CNT_N_1_:B_13 // NOD +DATA LOCATION CLK_CNT_N_0_:C_1 // NOD +DATA LOCATION CLK_CNT_N_1_:A_9 // NOD DATA LOCATION CLK_CNT_P_0_:G_5 // NOD -DATA LOCATION CLK_CNT_P_1_:H_14 // NOD -DATA LOCATION CLK_DIV_OUT:G_0_65 // OUT +DATA LOCATION CLK_CNT_P_1_:E_5 // NOD +DATA LOCATION CLK_DIV_OUT:G_1_65 // OUT DATA LOCATION CLK_EXP:B_0_10 // OUT DATA LOCATION CLK_OSZI:*_*_61 // Cin -DATA LOCATION DSACK_0_:H_12_80 // OUT -DATA LOCATION DSACK_1_:H_8_81 // IO {RN_DSACK_1_} -DATA LOCATION DS_030:A_*_98 // INP +DATA LOCATION DSACK_0_:H_13_80 // OUT +DATA LOCATION DSACK_1_:H_12_81 // IO {RN_DSACK_1_} +DATA LOCATION DS_030:A_0_98 // IO {RN_DS_030} DATA LOCATION DTACK:D_0_30 // IO DATA LOCATION E:G_4_66 // IO {RN_E} DATA LOCATION FC_0_:F_*_57 // INP DATA LOCATION FC_1_:F_*_58 // INP -DATA LOCATION FPU_CS:H_0_78 // IO {RN_FPU_CS} +DATA LOCATION FPU_CS:H_1_78 // IO {RN_FPU_CS} DATA LOCATION IPL_030_0_:B_8_8 // IO {RN_IPL_030_0_} DATA LOCATION IPL_030_1_:B_12_7 // IO {RN_IPL_030_1_} DATA LOCATION IPL_030_2_:B_4_9 // IO {RN_IPL_030_2_} @@ -58,58 +58,63 @@ DATA LOCATION IPL_1_:F_*_56 // INP DATA LOCATION IPL_2_:G_*_68 // INP DATA LOCATION LDS_000:D_8_31 // IO {RN_LDS_000} DATA LOCATION RESET:B_1_3 // OUT -DATA LOCATION RN_AMIGA_BUS_ENABLE:D_4 // NOD {AMIGA_BUS_ENABLE} -DATA LOCATION RN_AS_000:D_5 // NOD {AS_000} +DATA LOCATION RN_A0:G_8 // NOD {A0} +DATA LOCATION RN_AMIGA_BUS_ENABLE:D_5 // NOD {AMIGA_BUS_ENABLE} +DATA LOCATION RN_AS_000:D_4 // NOD {AS_000} +DATA LOCATION RN_AS_030:H_8 // NOD {AS_030} DATA LOCATION RN_BGACK_030:H_4 // NOD {BGACK_030} DATA LOCATION RN_BG_000:D_13 // NOD {BG_000} -DATA LOCATION RN_DSACK_1_:H_8 // NOD {DSACK_1_} +DATA LOCATION RN_DSACK_1_:H_12 // NOD {DSACK_1_} +DATA LOCATION RN_DS_030:A_0 // NOD {DS_030} DATA LOCATION RN_E:G_4 // NOD {E} -DATA LOCATION RN_FPU_CS:H_0 // NOD {FPU_CS} +DATA LOCATION RN_FPU_CS:H_1 // NOD {FPU_CS} DATA LOCATION RN_IPL_030_0_:B_8 // NOD {IPL_030_0_} DATA LOCATION RN_IPL_030_1_:B_12 // NOD {IPL_030_1_} DATA LOCATION RN_IPL_030_2_:B_4 // NOD {IPL_030_2_} DATA LOCATION RN_LDS_000:D_8 // NOD {LDS_000} +DATA LOCATION RN_SIZE_0_:G_0 // NOD {SIZE_0_} +DATA LOCATION RN_SIZE_1_:H_0 // NOD {SIZE_1_} DATA LOCATION RN_UDS_000:D_12 // NOD {UDS_000} DATA LOCATION RN_VMA:D_1 // NOD {VMA} DATA LOCATION RST:*_*_86 // INP DATA LOCATION RW:G_*_71 // INP -DATA LOCATION SIZE_0_:G_*_70 // INP -DATA LOCATION SIZE_1_:H_*_79 // INP -DATA LOCATION SM_AMIGA_0_:G_13 // NOD -DATA LOCATION SM_AMIGA_1_:H_13 // NOD -DATA LOCATION SM_AMIGA_2_:B_5 // NOD -DATA LOCATION SM_AMIGA_3_:B_6 // NOD -DATA LOCATION SM_AMIGA_4_:G_12 // NOD -DATA LOCATION SM_AMIGA_5_:D_14 // NOD -DATA LOCATION SM_AMIGA_6_:H_5 // NOD -DATA LOCATION SM_AMIGA_7_:G_8 // NOD +DATA LOCATION SIZE_0_:G_0_70 // IO {RN_SIZE_0_} +DATA LOCATION SIZE_1_:H_0_79 // IO {RN_SIZE_1_} +DATA LOCATION SM_AMIGA_0_:F_1 // NOD +DATA LOCATION SM_AMIGA_1_:B_5 // NOD +DATA LOCATION SM_AMIGA_2_:B_9 // NOD +DATA LOCATION SM_AMIGA_3_:C_8 // NOD +DATA LOCATION SM_AMIGA_4_:A_12 // NOD +DATA LOCATION SM_AMIGA_5_:A_1 // NOD +DATA LOCATION SM_AMIGA_6_:F_8 // NOD +DATA LOCATION SM_AMIGA_7_:F_12 // NOD DATA LOCATION UDS_000:D_12_32 // IO {RN_UDS_000} DATA LOCATION VMA:D_1_35 // IO {RN_VMA} DATA LOCATION VPA:*_*_36 // INP -DATA LOCATION cpu_est_0_:H_1 // NOD -DATA LOCATION cpu_est_1_:D_6 // NOD -DATA LOCATION cpu_est_2_:D_10 // NOD -DATA LOCATION inst_AS_030_000_SYNC:H_9 // NOD -DATA LOCATION inst_CLK_000_D0:D_2 // NOD -DATA LOCATION inst_CLK_000_D1:D_9 // NOD -DATA LOCATION inst_CLK_000_D2:D_3 // NOD -DATA LOCATION inst_CLK_000_D3:H_2 // NOD -DATA LOCATION inst_CLK_000_D4:H_10 // NOD -DATA LOCATION inst_CLK_000_D5:G_9 // NOD -DATA LOCATION inst_CLK_000_D6:H_6 // NOD -DATA LOCATION inst_CLK_OUT_PRE:G_1 // NOD -DATA LOCATION inst_DTACK_SYNC:B_14 // NOD -DATA LOCATION inst_VPA_D:B_2 // NOD -DATA LOCATION inst_VPA_SYNC:B_10 // NOD +DATA LOCATION cpu_est_0_:A_8 // NOD +DATA LOCATION cpu_est_1_:G_12 // NOD +DATA LOCATION cpu_est_2_:G_9 // NOD +DATA LOCATION inst_AS_030_000_SYNC:F_5 // NOD +DATA LOCATION inst_BGACK_030_INT_D:F_4 // NOD +DATA LOCATION inst_CLK_000_D0:E_8 // NOD +DATA LOCATION inst_CLK_000_D1:F_0 // NOD +DATA LOCATION inst_CLK_000_D2:A_5 // NOD +DATA LOCATION inst_CLK_000_D3:E_9 // NOD +DATA LOCATION inst_CLK_000_D4:F_9 // NOD +DATA LOCATION inst_CLK_000_D5:E_1 // NOD +DATA LOCATION inst_CLK_000_D6:H_5 // NOD +DATA LOCATION inst_CLK_OUT_PRE:C_4 // NOD +DATA LOCATION inst_DTACK_SYNC:C_9 // NOD +DATA LOCATION inst_VPA_SYNC:C_5 // NOD DATA LOCATION nEXP_SPACE:*_*_14 // INP +DATA IO_DIR A0:BI DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT DATA IO_DIR AMIGA_BUS_ENABLE:OUT DATA IO_DIR AMIGA_BUS_ENABLE_LOW:OUT -DATA IO_DIR AS_000:OUT -DATA IO_DIR AS_030:IN +DATA IO_DIR AS_000:BI +DATA IO_DIR AS_030:BI DATA IO_DIR AVEC:OUT DATA IO_DIR AVEC_EXP:OUT -DATA IO_DIR A_0_:IN DATA IO_DIR A_16_:IN DATA IO_DIR A_17_:IN DATA IO_DIR A_18_:IN @@ -139,7 +144,7 @@ DATA IO_DIR CLK_EXP:OUT DATA IO_DIR CLK_OSZI:IN DATA IO_DIR DSACK_0_:OUT DATA IO_DIR DSACK_1_:BI -DATA IO_DIR DS_030:IN +DATA IO_DIR DS_030:BI DATA IO_DIR DTACK:BI DATA IO_DIR E:OUT DATA IO_DIR FC_0_:IN @@ -151,73 +156,45 @@ DATA IO_DIR IPL_030_2_:OUT DATA IO_DIR IPL_0_:IN DATA IO_DIR IPL_1_:IN DATA IO_DIR IPL_2_:IN -DATA IO_DIR LDS_000:OUT +DATA IO_DIR LDS_000:BI DATA IO_DIR RESET:OUT DATA IO_DIR RST:IN DATA IO_DIR RW:IN -DATA IO_DIR SIZE_0_:IN -DATA IO_DIR SIZE_1_:IN -DATA IO_DIR UDS_000:OUT +DATA IO_DIR SIZE_0_:BI +DATA IO_DIR SIZE_1_:BI +DATA IO_DIR UDS_000:BI DATA IO_DIR VMA:OUT DATA IO_DIR VPA:IN DATA IO_DIR nEXP_SPACE:IN DATA GLB_CLOCK CLK_OSZI -DATA PW_LEVEL SIZE_1_:0 -DATA SLEW SIZE_1_:0 +DATA PW_LEVEL IPL_1_:0 +DATA SLEW IPL_1_:0 +DATA PW_LEVEL IPL_0_:0 +DATA SLEW IPL_0_:0 DATA PW_LEVEL A_31_:0 DATA SLEW A_31_:0 +DATA PW_LEVEL DSACK_0_:0 +DATA SLEW DSACK_0_:0 +DATA PW_LEVEL FC_0_:0 +DATA SLEW FC_0_:0 DATA PW_LEVEL IPL_2_:0 DATA SLEW IPL_2_:0 DATA PW_LEVEL FC_1_:0 DATA SLEW FC_1_:0 -DATA PW_LEVEL AS_030:0 -DATA SLEW AS_030:0 -DATA PW_LEVEL SIZE_0_:0 -DATA SLEW SIZE_0_:0 -DATA PW_LEVEL DS_030:0 -DATA SLEW DS_030:0 -DATA PW_LEVEL A_30_:0 -DATA SLEW A_30_:0 -DATA PW_LEVEL A_29_:0 -DATA SLEW A_29_:0 -DATA PW_LEVEL A_28_:0 -DATA SLEW A_28_:0 DATA SLEW nEXP_SPACE:0 -DATA PW_LEVEL A_27_:0 -DATA SLEW A_27_:0 DATA PW_LEVEL BERR:0 DATA SLEW BERR:0 -DATA PW_LEVEL A_26_:0 -DATA SLEW A_26_:0 DATA PW_LEVEL BG_030:0 DATA SLEW BG_030:0 -DATA PW_LEVEL A_25_:0 -DATA SLEW A_25_:0 -DATA PW_LEVEL A_24_:0 -DATA SLEW A_24_:0 -DATA PW_LEVEL A_23_:0 -DATA SLEW A_23_:0 DATA PW_LEVEL BGACK_000:0 DATA SLEW BGACK_000:0 -DATA PW_LEVEL A_22_:0 -DATA SLEW A_22_:0 DATA SLEW CLK_030:0 -DATA PW_LEVEL A_21_:0 -DATA SLEW A_21_:0 DATA SLEW CLK_000:0 -DATA PW_LEVEL A_20_:0 -DATA SLEW A_20_:0 DATA SLEW CLK_OSZI:0 -DATA PW_LEVEL A_19_:0 -DATA SLEW A_19_:0 DATA PW_LEVEL CLK_DIV_OUT:0 DATA SLEW CLK_DIV_OUT:0 -DATA PW_LEVEL A_18_:0 -DATA SLEW A_18_:0 -DATA PW_LEVEL A_17_:0 -DATA SLEW A_17_:0 -DATA PW_LEVEL A_16_:0 -DATA SLEW A_16_:0 +DATA PW_LEVEL DTACK:0 +DATA SLEW DTACK:0 DATA PW_LEVEL AVEC:0 DATA SLEW AVEC:0 DATA PW_LEVEL AVEC_EXP:0 @@ -232,26 +209,58 @@ DATA PW_LEVEL AMIGA_BUS_ENABLE_LOW:0 DATA SLEW AMIGA_BUS_ENABLE_LOW:0 DATA PW_LEVEL CIIN:0 DATA SLEW CIIN:0 -DATA PW_LEVEL A_0_:0 -DATA SLEW A_0_:0 -DATA PW_LEVEL IPL_1_:0 -DATA SLEW IPL_1_:0 -DATA PW_LEVEL IPL_0_:0 -DATA SLEW IPL_0_:0 -DATA PW_LEVEL DSACK_0_:0 -DATA SLEW DSACK_0_:0 -DATA PW_LEVEL FC_0_:0 -DATA SLEW FC_0_:0 +DATA PW_LEVEL A_30_:0 +DATA SLEW A_30_:0 +DATA PW_LEVEL A_29_:0 +DATA SLEW A_29_:0 +DATA PW_LEVEL A_28_:0 +DATA SLEW A_28_:0 +DATA PW_LEVEL A_27_:0 +DATA SLEW A_27_:0 +DATA PW_LEVEL A_26_:0 +DATA SLEW A_26_:0 +DATA PW_LEVEL A_25_:0 +DATA SLEW A_25_:0 +DATA PW_LEVEL A_24_:0 +DATA SLEW A_24_:0 +DATA PW_LEVEL A_23_:0 +DATA SLEW A_23_:0 +DATA PW_LEVEL A_22_:0 +DATA SLEW A_22_:0 +DATA PW_LEVEL A_21_:0 +DATA SLEW A_21_:0 +DATA PW_LEVEL A_20_:0 +DATA SLEW A_20_:0 +DATA PW_LEVEL A_19_:0 +DATA SLEW A_19_:0 +DATA PW_LEVEL A_18_:0 +DATA SLEW A_18_:0 +DATA PW_LEVEL A_17_:0 +DATA SLEW A_17_:0 +DATA PW_LEVEL A_16_:0 +DATA SLEW A_16_:0 +DATA PW_LEVEL IPL_030_1_:0 +DATA SLEW IPL_030_1_:0 +DATA PW_LEVEL IPL_030_0_:0 +DATA SLEW IPL_030_0_:0 +DATA PW_LEVEL SIZE_1_:0 +DATA SLEW SIZE_1_:0 DATA PW_LEVEL IPL_030_2_:0 DATA SLEW IPL_030_2_:0 DATA PW_LEVEL DSACK_1_:0 DATA SLEW DSACK_1_:0 +DATA PW_LEVEL AS_030:0 +DATA SLEW AS_030:0 DATA PW_LEVEL AS_000:0 DATA SLEW AS_000:0 +DATA PW_LEVEL DS_030:0 +DATA SLEW DS_030:0 DATA PW_LEVEL UDS_000:0 DATA SLEW UDS_000:0 DATA PW_LEVEL LDS_000:0 DATA SLEW LDS_000:0 +DATA PW_LEVEL A0:0 +DATA SLEW A0:0 DATA PW_LEVEL BG_000:0 DATA SLEW BG_000:0 DATA PW_LEVEL BGACK_030:0 @@ -260,8 +269,6 @@ DATA PW_LEVEL CLK_EXP:0 DATA SLEW CLK_EXP:0 DATA PW_LEVEL FPU_CS:0 DATA SLEW FPU_CS:0 -DATA PW_LEVEL DTACK:0 -DATA SLEW DTACK:0 DATA PW_LEVEL E:0 DATA SLEW E:0 DATA PW_LEVEL VMA:0 @@ -270,16 +277,14 @@ DATA PW_LEVEL RESET:0 DATA SLEW RESET:0 DATA PW_LEVEL AMIGA_BUS_ENABLE:0 DATA SLEW AMIGA_BUS_ENABLE:0 -DATA PW_LEVEL IPL_030_1_:0 -DATA SLEW IPL_030_1_:0 -DATA PW_LEVEL IPL_030_0_:0 -DATA SLEW IPL_030_0_:0 +DATA PW_LEVEL SIZE_0_:0 +DATA SLEW SIZE_0_:0 DATA PW_LEVEL inst_AS_030_000_SYNC:0 DATA SLEW inst_AS_030_000_SYNC:0 +DATA PW_LEVEL inst_BGACK_030_INT_D:0 +DATA SLEW inst_BGACK_030_INT_D:0 DATA PW_LEVEL inst_DTACK_SYNC:0 DATA SLEW inst_DTACK_SYNC:0 -DATA PW_LEVEL inst_VPA_D:0 -DATA SLEW inst_VPA_D:0 DATA PW_LEVEL inst_VPA_SYNC:0 DATA SLEW inst_VPA_SYNC:0 DATA PW_LEVEL inst_CLK_000_D0:0 @@ -296,14 +301,12 @@ DATA PW_LEVEL SM_AMIGA_6_:0 DATA SLEW SM_AMIGA_6_:0 DATA PW_LEVEL inst_CLK_000_D3:0 DATA SLEW inst_CLK_000_D3:0 -DATA PW_LEVEL SM_AMIGA_4_:0 -DATA SLEW SM_AMIGA_4_:0 DATA PW_LEVEL inst_CLK_000_D5:0 DATA SLEW inst_CLK_000_D5:0 -DATA PW_LEVEL SM_AMIGA_7_:0 -DATA SLEW SM_AMIGA_7_:0 DATA PW_LEVEL SM_AMIGA_3_:0 DATA SLEW SM_AMIGA_3_:0 +DATA PW_LEVEL SM_AMIGA_0_:0 +DATA SLEW SM_AMIGA_0_:0 DATA PW_LEVEL SM_AMIGA_1_:0 DATA SLEW SM_AMIGA_1_:0 DATA PW_LEVEL CLK_CNT_N_0_:0 @@ -314,31 +317,38 @@ DATA PW_LEVEL CLK_CNT_P_0_:0 DATA SLEW CLK_CNT_P_0_:0 DATA PW_LEVEL CLK_CNT_P_1_:0 DATA SLEW CLK_CNT_P_1_:0 -DATA PW_LEVEL SM_AMIGA_2_:0 -DATA SLEW SM_AMIGA_2_:0 -DATA PW_LEVEL SM_AMIGA_0_:0 -DATA SLEW SM_AMIGA_0_:0 DATA PW_LEVEL inst_CLK_000_D4:0 DATA SLEW inst_CLK_000_D4:0 +DATA PW_LEVEL SM_AMIGA_7_:0 +DATA SLEW SM_AMIGA_7_:0 +DATA PW_LEVEL SM_AMIGA_4_:0 +DATA SLEW SM_AMIGA_4_:0 DATA PW_LEVEL inst_CLK_OUT_PRE:0 DATA SLEW inst_CLK_OUT_PRE:0 +DATA PW_LEVEL SM_AMIGA_2_:0 +DATA SLEW SM_AMIGA_2_:0 DATA PW_LEVEL cpu_est_0_:0 DATA SLEW cpu_est_0_:0 DATA PW_LEVEL cpu_est_1_:0 DATA SLEW cpu_est_1_:0 DATA PW_LEVEL cpu_est_2_:0 DATA SLEW cpu_est_2_:0 +DATA PW_LEVEL RN_IPL_030_1_:0 +DATA PW_LEVEL RN_IPL_030_0_:0 +DATA PW_LEVEL RN_SIZE_1_:0 DATA PW_LEVEL RN_IPL_030_2_:0 DATA PW_LEVEL RN_DSACK_1_:0 +DATA PW_LEVEL RN_AS_030:0 DATA PW_LEVEL RN_AS_000:0 +DATA PW_LEVEL RN_DS_030:0 DATA PW_LEVEL RN_UDS_000:0 DATA PW_LEVEL RN_LDS_000:0 +DATA PW_LEVEL RN_A0:0 DATA PW_LEVEL RN_BG_000:0 DATA PW_LEVEL RN_BGACK_030:0 DATA PW_LEVEL RN_FPU_CS:0 DATA PW_LEVEL RN_E:0 DATA PW_LEVEL RN_VMA:0 DATA PW_LEVEL RN_AMIGA_BUS_ENABLE:0 -DATA PW_LEVEL RN_IPL_030_1_:0 -DATA PW_LEVEL RN_IPL_030_0_:0 +DATA PW_LEVEL RN_SIZE_0_:0 END diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp index f5ca19d..b0ce9a9 100644 --- a/Logic/68030_tk.grp +++ b/Logic/68030_tk.grp @@ -1,16 +1,18 @@ -GROUP MACH_SEG_A AVEC -GROUP MACH_SEG_B inst_VPA_SYNC inst_DTACK_SYNC SM_AMIGA_2_ SM_AMIGA_3_ - IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ RN_IPL_030_2_ - CLK_CNT_N_0_ inst_VPA_D CLK_EXP CLK_CNT_N_1_ RESET -GROUP MACH_SEG_C AVEC_EXP AMIGA_BUS_ENABLE_LOW -GROUP MACH_SEG_D LDS_000 RN_LDS_000 UDS_000 RN_UDS_000 VMA RN_VMA BG_000 - RN_BG_000 cpu_est_1_ cpu_est_2_ AMIGA_BUS_ENABLE RN_AMIGA_BUS_ENABLE - AS_000 RN_AS_000 DTACK SM_AMIGA_5_ inst_CLK_000_D0 inst_CLK_000_D2 - inst_CLK_000_D1 -GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR -GROUP MACH_SEG_G SM_AMIGA_7_ SM_AMIGA_0_ E RN_E inst_CLK_OUT_PRE SM_AMIGA_4_ - CLK_CNT_P_0_ inst_CLK_000_D5 CLK_DIV_OUT -GROUP MACH_SEG_H inst_AS_030_000_SYNC FPU_CS RN_FPU_CS SM_AMIGA_6_ DSACK_1_ - RN_DSACK_1_ SM_AMIGA_1_ BGACK_030 RN_BGACK_030 cpu_est_0_ inst_CLK_000_D3 - CLK_CNT_P_1_ inst_CLK_000_D4 inst_CLK_000_D6 DSACK_0_ \ No newline at end of file +GROUP MACH_SEG_A DS_030 RN_DS_030 SM_AMIGA_4_ SM_AMIGA_5_ cpu_est_0_ CLK_CNT_N_1_ + inst_CLK_000_D2 AVEC +GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ + RN_IPL_030_2_ CLK_EXP RESET SM_AMIGA_2_ SM_AMIGA_1_ +GROUP MACH_SEG_C inst_VPA_SYNC inst_DTACK_SYNC SM_AMIGA_3_ inst_CLK_OUT_PRE + CLK_CNT_N_0_ AVEC_EXP AMIGA_BUS_ENABLE_LOW +GROUP MACH_SEG_D LDS_000 RN_LDS_000 AMIGA_BUS_ENABLE RN_AMIGA_BUS_ENABLE + UDS_000 RN_UDS_000 VMA RN_VMA BG_000 RN_BG_000 AS_000 RN_AS_000 DTACK + +GROUP MACH_SEG_E inst_CLK_000_D5 inst_CLK_000_D0 inst_CLK_000_D3 CLK_CNT_P_1_ + CIIN AMIGA_BUS_DATA_DIR BERR +GROUP MACH_SEG_F inst_AS_030_000_SYNC SM_AMIGA_7_ SM_AMIGA_6_ SM_AMIGA_0_ + inst_CLK_000_D4 inst_BGACK_030_INT_D inst_CLK_000_D1 +GROUP MACH_SEG_G A0 RN_A0 SIZE_0_ RN_SIZE_0_ E RN_E CLK_DIV_OUT cpu_est_1_ + cpu_est_2_ CLK_CNT_P_0_ +GROUP MACH_SEG_H FPU_CS RN_FPU_CS SIZE_1_ RN_SIZE_1_ AS_030 RN_AS_030 DSACK_1_ + RN_DSACK_1_ BGACK_030 RN_BGACK_030 inst_CLK_000_D6 DSACK_0_ \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index af8479d3f798badec60fe5b81c5d07646aa3d74e..098eec0bee3834fb0fdefdcc03368bd44cffa85b 100644 GIT binary patch delta 20 bcmY#apCG|+Vq$J&WMk&+ALH*)8>s;RFMS05 delta 20 bcmY#apCG|+U} None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd index 75b64c6..cd5c566 100644 --- a/Logic/68030_tk.prd +++ b/Logic/68030_tk.prd @@ -5,8 +5,8 @@ |--------------------------------------------| -Start: Sat May 24 19:56:24 2014 -End : Sat May 24 19:56:24 2014 $$$ Elapsed time: 00:00:00 +Start: Sat May 24 21:59:18 2014 +End : Sat May 24 21:59:18 2014 $$$ Elapsed time: 00:00:00 =========================================================================== Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] @@ -21,18 +21,18 @@ Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030 | | +- Signals to Place | | +----- Logic Array Inputs | | | +- Placed | | | +- Array Inputs Used _|____|____|____|_______________|____|_____________|___|________________ - 0 | 16 | 1 | 1 => 100% | 8 | 7 => 87% | 33 | 0 => 0% - 1 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 24 => 72% - 2 | 16 | 2 | 2 => 100% | 8 | 8 => 100% | 33 | 1 => 3% - 3 | 16 | 13 | 13 => 100% | 8 | 8 => 100% | 33 | 30 => 90% - 4 | 16 | 3 | 3 => 100% | 8 | 3 => 37% | 33 | 14 => 42% - 5 | 16 | 0 | 0 => n/a | 8 | 4 => 50% | 33 | 0 => 0% - 6 | 16 | 8 | 8 => 100% | 8 | 7 => 87% | 33 | 26 => 78% - 7 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 27 => 81% + 0 | 16 | 7 | 7 => 100% | 8 | 7 => 87% | 33 | 18 => 54% + 1 | 16 | 7 | 7 => 100% | 8 | 8 => 100% | 33 | 17 => 51% + 2 | 16 | 7 | 7 => 100% | 8 | 8 => 100% | 33 | 17 => 51% + 3 | 16 | 7 | 7 => 100% | 8 | 8 => 100% | 33 | 30 => 90% + 4 | 16 | 7 | 7 => 100% | 8 | 3 => 37% | 33 | 20 => 60% + 5 | 16 | 7 | 7 => 100% | 8 | 4 => 50% | 33 | 23 => 69% + 6 | 16 | 7 | 7 => 100% | 8 | 7 => 87% | 33 | 19 => 57% + 7 | 16 | 7 | 7 => 100% | 8 | 8 => 100% | 33 | 25 => 75% ---|----|----|------------|-------|------------|-----|------------------ - | Avg number of array inputs in used blocks : 20.33 => 61% + | Avg number of array inputs in used blocks : 21.13 => 64% -* Input/Clock Signal count: 35 -> placed: 35 = 100% +* Input/Clock Signal count: 30 -> placed: 30 = 100% Resources Available Used ----------------------------------------------------------------- @@ -40,14 +40,14 @@ _|____|____|____|_______________|____|_____________|___|________________ I/O Pins : 64 53 => 82% Clock Only Pins : 0 0 => 0% Clock/Input Pins : 4 4 => 100% - Logic Blocks : 8 6 => 75% - Macrocells : 128 51 => 39% - PT Clusters : 128 32 => 25% - - Single PT Clusters : 128 21 => 16% + Logic Blocks : 8 8 => 100% + Macrocells : 128 56 => 43% + PT Clusters : 128 39 => 30% + - Single PT Clusters : 128 20 => 15% Input Registers : 0 * Routing Completion: 100% -* Attempts: Place [ 99] Route [ 0] +* Attempts: Place [ 104] Route [ 0] =========================================================================== Signal Fanout Table =========================================================================== @@ -57,20 +57,22 @@ _|____|____|____|_______________|____|_____________|___|________________ | | | +- Signal-to-Pin Assignment | | | | Fanout to Logic Blocks Signal Name ___|__|__|____|____________________________________________________________ - 1| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR - 2| 3| IO| 34|=> ....|....| AMIGA_BUS_ENABLE + 1| 6| IO| 69|=> ...3|....| A0 + |=> Paired w/: RN_A0 + 2| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR + 3| 3| IO| 34|=> ....|....| AMIGA_BUS_ENABLE |=> Paired w/: RN_AMIGA_BUS_ENABLE - 3| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW - 4| 3| IO| 33|=> ....|....| AS_000 + 4| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW + 5| 3| IO| 33|=> 0...|..67| AS_000 |=> Paired w/: RN_AS_000 - 5| 7|INP| 82|=> .1.3|...7| AS_030 - 6| 0|OUT| 92|=> ....|....| AVEC - 7| 2|OUT| 22|=> ....|....| AVEC_EXP - 8| 6|INP| 69|=> ...3|....| A_0_ - 9| 0|INP| 96|=> ....|...7| A_16_ - 10| 5|INP| 59|=> ....|...7| A_17_ - 11| 0|INP| 95|=> ....|...7| A_18_ - 12| 0|INP| 97|=> ....|...7| A_19_ + 6| 7| IO| 82|=> ..23|.5.7| AS_030 + |=> Paired w/: RN_AS_030 + 7| 0|OUT| 92|=> ....|....| AVEC + 8| 2|OUT| 22|=> ....|....| AVEC_EXP + 9| 0|INP| 96|=> ....|.5.7| A_16_ + 10| 5|INP| 59|=> ....|.5.7| A_17_ + 11| 0|INP| 95|=> ....|.5.7| A_18_ + 12| 0|INP| 97|=> ....|.5.7| A_19_ 13| 0|INP| 93|=> ....|4...| A_20_ 14| 0|INP| 94|=> ....|4...| A_21_ 15| 7|INP| 85|=> ....|4...| A_22_ @@ -84,31 +86,32 @@ ___|__|__|____|____________________________________________________________ 23| 1|INP| 5|=> ....|4...| A_30_ 24| 1|INP| 4|=> ....|4...| A_31_ 25| 4|OUT| 41|=> ....|....| BERR - 26| 3|INP| 28|=> ....|...7| BGACK_000 + 26| 3|INP| 28|=> ....|.5.7| BGACK_000 27| 7| IO| 83|=> ....|....| BGACK_030 |=> Paired w/: RN_BGACK_030 28| 3| IO| 29|=> ....|....| BG_000 |=> Paired w/: RN_BG_000 29| 2|INP| 21|=> ...3|....| BG_030 30| 4|OUT| 47|=> ....|....| CIIN - 31| +|INP| 11|=> ...3|....| CLK_000 - 32| +|INP| 64|=> ....|...7| CLK_030 - 33| 1|NOD| . |=> .1..|..6.| CLK_CNT_N_0_ - 34| 1|NOD| . |=> .1..|..6.| CLK_CNT_N_1_ - 35| 6|NOD| . |=> ....|..67| CLK_CNT_P_0_ - 36| 7|NOD| . |=> ....|..6.| CLK_CNT_P_1_ + 31| +|INP| 11|=> ...3|4...| CLK_000 + 32| +|INP| 64|=> 0...|.567| CLK_030 + 33| 2|NOD| . |=> 0.2.|....| CLK_CNT_N_0_ + 34| 0|NOD| . |=> ..2.|....| CLK_CNT_N_1_ + 35| 6|NOD| . |=> ..2.|4.6.| CLK_CNT_P_0_ + 36| 4|NOD| . |=> ..2.|..6.| CLK_CNT_P_1_ 37| 6|OUT| 65|=> ....|....| CLK_DIV_OUT 38| 1|OUT| 10|=> ....|....| CLK_EXP - 39| +|Cin| 61|=> ...3|....| CLK_OSZI + 39| +|Cin| 61|=> ....|....| CLK_OSZI 40| 7|OUT| 80|=> ....|....| DSACK_0_ 41| 7| IO| 81|=> ...3|....| DSACK_1_ |=> Paired w/: RN_DSACK_1_ - 42| 0|INP| 98|=> ...3|....| DS_030 - 43| 3| IO| 30|=> .1..|....| DTACK + 42| 0| IO| 98|=> ...3|....| DS_030 + |=> Paired w/: RN_DS_030 + 43| 3| IO| 30|=> ..2.|....| DTACK 44| 6| IO| 66|=> ....|....| E |=> Paired w/: RN_E - 45| 5|INP| 57|=> ....|...7| FC_0_ - 46| 5|INP| 58|=> ....|...7| FC_1_ + 45| 5|INP| 57|=> ....|.5.7| FC_0_ + 46| 5|INP| 58|=> ....|.5.7| FC_1_ 47| 7| IO| 78|=> ....|....| FPU_CS |=> Paired w/: RN_FPU_CS 48| 1| IO| 8|=> ....|....| IPL_030_0_ @@ -120,68 +123,80 @@ ___|__|__|____|____________________________________________________________ 51| 6|INP| 67|=> .1..|....| IPL_0_ 52| 5|INP| 56|=> .1..|....| IPL_1_ 53| 6|INP| 68|=> .1..|....| IPL_2_ - 54| 3| IO| 31|=> ....|....| LDS_000 + 54| 3| IO| 31|=> 0...|..67| LDS_000 |=> Paired w/: RN_LDS_000 55| 1|OUT| 3|=> ....|....| RESET - 56| 3|NOD| . |=> ...3|....| RN_AMIGA_BUS_ENABLE + 56| 6|NOD| . |=> ....|..6.| RN_A0 + |=> Paired w/: A0 + 57| 3|NOD| . |=> ...3|....| RN_AMIGA_BUS_ENABLE |=> Paired w/: AMIGA_BUS_ENABLE - 57| 3|NOD| . |=> ...3|..6.| RN_AS_000 + 58| 3|NOD| . |=> ...3|.5..| RN_AS_000 |=> Paired w/: AS_000 - 58| 7|NOD| . |=> ...3|...7| RN_BGACK_030 + 59| 7|NOD| . |=> 0...|...7| RN_AS_030 + |=> Paired w/: AS_030 + 60| 7|NOD| . |=> 0..3|4567| RN_BGACK_030 |=> Paired w/: BGACK_030 - 59| 3|NOD| . |=> ...3|....| RN_BG_000 + 61| 3|NOD| . |=> ...3|....| RN_BG_000 |=> Paired w/: BG_000 - 60| 7|NOD| . |=> ....|...7| RN_DSACK_1_ + 62| 7|NOD| . |=> ....|...7| RN_DSACK_1_ |=> Paired w/: DSACK_1_ - 61| 6|NOD| . |=> .1.3|..6.| RN_E + 63| 0|NOD| . |=> 0...|....| RN_DS_030 + |=> Paired w/: DS_030 + 64| 6|NOD| . |=> ..23|..6.| RN_E |=> Paired w/: E - 62| 7|NOD| . |=> ..2.|4..7| RN_FPU_CS + 65| 7|NOD| . |=> ..2.|4..7| RN_FPU_CS |=> Paired w/: FPU_CS - 63| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + 66| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ |=> Paired w/: IPL_030_0_ - 64| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + 67| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ |=> Paired w/: IPL_030_1_ - 65| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + 68| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ |=> Paired w/: IPL_030_2_ - 66| 3|NOD| . |=> ...3|....| RN_LDS_000 + 69| 3|NOD| . |=> ...3|....| RN_LDS_000 |=> Paired w/: LDS_000 - 67| 3|NOD| . |=> ...3|....| RN_UDS_000 + 70| 6|NOD| . |=> ....|..6.| RN_SIZE_0_ + |=> Paired w/: SIZE_0_ + 71| 7|NOD| . |=> ....|...7| RN_SIZE_1_ + |=> Paired w/: SIZE_1_ + 72| 3|NOD| . |=> ...3|....| RN_UDS_000 |=> Paired w/: UDS_000 - 68| 3|NOD| . |=> .1.3|....| RN_VMA + 73| 3|NOD| . |=> ..23|....| RN_VMA |=> Paired w/: VMA - 69| +|INP| 86|=> .1.3|..67| RST - 70| 6|INP| 71|=> ...3|4...| RW - 71| 6|INP| 70|=> ...3|....| SIZE_0_ - 72| 7|INP| 79|=> ...3|....| SIZE_1_ - 73| 6|NOD| . |=> ....|..6.| SM_AMIGA_0_ - 74| 7|NOD| . |=> ....|..67| SM_AMIGA_1_ - 75| 1|NOD| . |=> .1..|...7| SM_AMIGA_2_ - 76| 1|NOD| . |=> .1..|....| SM_AMIGA_3_ - 77| 6|NOD| . |=> .1.3|..6.| SM_AMIGA_4_ - 78| 3|NOD| . |=> ...3|..6.| SM_AMIGA_5_ - 79| 7|NOD| . |=> ...3|..67| SM_AMIGA_6_ - 80| 6|NOD| . |=> ...3|..67| SM_AMIGA_7_ - 81| 3| IO| 32|=> ....|....| UDS_000 + 74| +|INP| 86|=> 0123|4567| RST + 75| 6|INP| 71|=> 0..3|4...| RW + 76| 6| IO| 70|=> ...3|....| SIZE_0_ + |=> Paired w/: RN_SIZE_0_ + 77| 7| IO| 79|=> ...3|....| SIZE_1_ + |=> Paired w/: RN_SIZE_1_ + 78| 5|NOD| . |=> ...3|.5..| SM_AMIGA_0_ + 79| 1|NOD| . |=> .1..|.5.7| SM_AMIGA_1_ + 80| 1|NOD| . |=> .1..|....| SM_AMIGA_2_ + 81| 2|NOD| . |=> .12.|....| SM_AMIGA_3_ + 82| 0|NOD| . |=> 0.23|....| SM_AMIGA_4_ + 83| 0|NOD| . |=> 0..3|....| SM_AMIGA_5_ + 84| 5|NOD| . |=> 0..3|.5..| SM_AMIGA_6_ + 85| 5|NOD| . |=> ...3|.5..| SM_AMIGA_7_ + 86| 3| IO| 32|=> 0...|..67| UDS_000 |=> Paired w/: RN_UDS_000 - 82| 3| IO| 35|=> ....|....| VMA + 87| 3| IO| 35|=> ....|....| VMA |=> Paired w/: RN_VMA - 83| +|INP| 36|=> .1..|....| VPA - 84| 7|NOD| . |=> ...3|..67| cpu_est_0_ - 85| 3|NOD| . |=> .1.3|..6.| cpu_est_1_ - 86| 3|NOD| . |=> ...3|..6.| cpu_est_2_ - 87| 7|NOD| . |=> ....|..67| inst_AS_030_000_SYNC - 88| 3|NOD| . |=> .1.3|..67| inst_CLK_000_D0 - 89| 3|NOD| . |=> .1.3|..67| inst_CLK_000_D1 - 90| 3|NOD| . |=> ....|..67| inst_CLK_000_D2 - 91| 7|NOD| . |=> ....|..67| inst_CLK_000_D3 - 92| 7|NOD| . |=> ....|..6.| inst_CLK_000_D4 - 93| 6|NOD| . |=> ....|..67| inst_CLK_000_D5 - 94| 7|NOD| . |=> ....|..67| inst_CLK_000_D6 - 95| 6|NOD| . |=> .1..|..6.| inst_CLK_OUT_PRE - 96| 1|NOD| . |=> .1..|....| inst_DTACK_SYNC - 97| 1|NOD| . |=> .1.3|....| inst_VPA_D - 98| 1|NOD| . |=> .1..|....| inst_VPA_SYNC - 99| +|INP| 14|=> ...3|..67| nEXP_SPACE + 88| +|INP| 36|=> ..23|....| VPA + 89| 0|NOD| . |=> 0..3|..6.| cpu_est_0_ + 90| 6|NOD| . |=> ..23|..6.| cpu_est_1_ + 91| 6|NOD| . |=> ...3|..6.| cpu_est_2_ + 92| 5|NOD| . |=> ....|.5..| inst_AS_030_000_SYNC + 93| 5|NOD| . |=> 0..3|..67| inst_BGACK_030_INT_D + 94| 4|NOD| . |=> 0123|.567| inst_CLK_000_D0 + 95| 5|NOD| . |=> 01..|..67| inst_CLK_000_D1 + 96| 0|NOD| . |=> ....|45..| inst_CLK_000_D2 + 97| 4|NOD| . |=> ....|.5..| inst_CLK_000_D3 + 98| 5|NOD| . |=> ....|4...| inst_CLK_000_D4 + 99| 4|NOD| . |=> .1..|.5.7| inst_CLK_000_D5 + 100| 7|NOD| . |=> .1..|.5.7| inst_CLK_000_D6 + 101| 2|NOD| . |=> .1..|..6.| inst_CLK_OUT_PRE + 102| 2|NOD| . |=> .12.|....| inst_DTACK_SYNC + 103| 2|NOD| . |=> .12.|....| inst_VPA_SYNC + 104| +|INP| 14|=> 0..3|.567| nEXP_SPACE --------------------------------------------------------------------------- =========================================================================== < C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments > @@ -203,7 +218,7 @@ ____|_____|_________|______________________________________________________ 11 | CkIn | |*| CLK_000 12 | Vcc | | | (pwr/test) 13 | GND | | | (pwr/test) - 14 | CkIn | | | nEXP_SPACE + 14 | CkIn | |*| nEXP_SPACE 15 | I_O | 2_00|*| A_28_ 16 | I_O | 2_01|*| A_27_ 17 | I_O | 2_02|*| A_26_ @@ -258,7 +273,7 @@ ____|_____|_________|______________________________________________________ 66 | I_O | 6_01|*| E 67 | I_O | 6_02|*| IPL_0_ 68 | I_O | 6_03|*| IPL_2_ - 69 | I_O | 6_04|*| A_0_ + 69 | I_O | 6_04|*| A0 70 | I_O | 6_05|*| SIZE_0_ 71 | I_O | 6_06|*| RW 72 | I_O | 6_07| | - @@ -301,19 +316,19 @@ ____|_____|_________|______________________________________________________ | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| | ? | | S | | 4 free | 1 XOR free - 1| | ? | | S | | 4 free | 1 XOR free + 0| DS_030| IO| | S | 5 | 4 to [ 0]| 1 XOR to [ 0] as logic PT + 1| SM_AMIGA_5_|NOD| | S | 2 | 4 to [ 1]| 1 XOR free 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| AVEC|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5| | ? | | S | | 4 free | 1 XOR free + 5|inst_CLK_000_D2|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| | ? | | S | | 4 free | 1 XOR free - 9| | ? | | S | | 4 free | 1 XOR free + 8| cpu_est_0_|NOD| | S | 3 | 4 to [ 8]| 1 XOR free + 9| CLK_CNT_N_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| | ? | | S | | 4 free | 1 XOR free +12| SM_AMIGA_4_|NOD| | S | 2 | 4 to [12]| 1 XOR free 13| | ? | | S | | 4 free | 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free @@ -328,20 +343,20 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| | ? | | S | |=> can support up to [ 15] logic PT(s) - 1| | ? | | S | |=> can support up to [ 20] logic PT(s) - 2| | ? | | S | |=> can support up to [ 19] logic PT(s) - 3| | ? | | S | |=> can support up to [ 19] logic PT(s) - 4| AVEC|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) - 5| | ? | | S | |=> can support up to [ 19] logic PT(s) - 6| | ? | | S | |=> can support up to [ 20] logic PT(s) - 7| | ? | | S | |=> can support up to [ 20] logic PT(s) - 8| | ? | | S | |=> can support up to [ 20] logic PT(s) - 9| | ? | | S | |=> can support up to [ 20] logic PT(s) -10| | ? | | S | |=> can support up to [ 20] logic PT(s) -11| | ? | | S | |=> can support up to [ 20] logic PT(s) -12| | ? | | S | |=> can support up to [ 20] logic PT(s) -13| | ? | | S | |=> can support up to [ 20] logic PT(s) + 0| DS_030| IO| | S | 5 |=> can support up to [ 10] logic PT(s) + 1| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) + 2| | ? | | S | |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 18] logic PT(s) + 4| AVEC|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) + 5|inst_CLK_000_D2|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 6| | ? | | S | |=> can support up to [ 14] logic PT(s) + 7| | ? | | S | |=> can support up to [ 14] logic PT(s) + 8| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) + 9| CLK_CNT_N_1_|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 15] logic PT(s) +12| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 20] logic PT(s) +13| | ? | | S | |=> can support up to [ 15] logic PT(s) 14| | ? | | S | |=> can support up to [ 15] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- @@ -353,19 +368,19 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 0] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| | | | => | 5 6 7 0 | 96 97 98 91 - 1| | | | => | 5 6 7 0 | 96 97 98 91 + 0| DS_030| IO| | => | 5 6 ( 7) 0 | 96 97 ( 98) 91 + 1| SM_AMIGA_5_|NOD| | => | 5 6 7 0 | 96 97 98 91 2| | | | => | 6 7 0 1 | 97 98 91 92 3| | | | => | 6 7 0 1 | 97 98 91 92 4| AVEC|OUT| | => | 7 0 ( 1) 2 | 98 91 ( 92) 93 - 5| | | | => | 7 0 1 2 | 98 91 92 93 + 5|inst_CLK_000_D2|NOD| | => | 7 0 1 2 | 98 91 92 93 6| | | | => | 0 1 2 3 | 91 92 93 94 7| | | | => | 0 1 2 3 | 91 92 93 94 - 8| | | | => | 1 2 3 4 | 92 93 94 95 - 9| | | | => | 1 2 3 4 | 92 93 94 95 + 8| cpu_est_0_|NOD| | => | 1 2 3 4 | 92 93 94 95 + 9| CLK_CNT_N_1_|NOD| | => | 1 2 3 4 | 92 93 94 95 10| | | | => | 2 3 4 5 | 93 94 95 96 11| | | | => | 2 3 4 5 | 93 94 95 96 -12| | | | => | 3 4 5 6 | 94 95 96 97 +12| SM_AMIGA_4_|NOD| | => | 3 4 5 6 | 94 95 96 97 13| | | | => | 3 4 5 6 | 94 95 96 97 14| | | | => | 4 5 6 7 | 95 96 97 98 15| | | | => | 4 5 6 7 | 95 96 97 98 @@ -386,7 +401,7 @@ _|_________________|__|___|_____|___________________________________________ 4| A_18_|INP|*| 95| => | 8 9 10 11 12 13 14 15 5| A_16_|INP|*| 96| => | 10 11 12 13 14 15 0 1 6| A_19_|INP|*| 97| => | 12 13 14 15 0 1 2 3 - 7| DS_030|INP|*| 98| => | 14 15 0 1 2 3 4 5 + 7| DS_030| IO|*| 98| => | 14 15 ( 0) 1 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > IO/Node and IO/Input Macrocell Pairing Table @@ -404,7 +419,8 @@ _|_________________|__|___|_____|__________________________________________ 4| A_18_|INP|*| 95| => | Input macrocell [ -] 5| A_16_|INP|*| 96| => | Input macrocell [ -] 6| A_19_|INP|*| 97| => | Input macrocell [ -] - 7| DS_030|INP|*| 98| => | Input macrocell [ -] + 7| DS_030| IO|*| 98| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_DS_030] --------------------------------------------------------------------------- =========================================================================== < Block [ 0] > Input Multiplexer (IMX) Assignments @@ -417,8 +433,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 91| -| | ] [RegIn 0 |102| -| | ] - [MCell 0 |101| -| | ] - [MCell 1 |103| -| | ] + [MCell 0 |101|NOD RN_DS_030| |*] paired w/[ DS_030] + [MCell 1 |103|NOD SM_AMIGA_5_| |*] 1 [IOpin 1 | 92|OUT AVEC|*| ] [RegIn 1 |105| -| | ] @@ -428,7 +444,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 93|INP A_20_|*|*] [RegIn 2 |108| -| | ] [MCell 4 |107|OUT AVEC| | ] - [MCell 5 |109| -| | ] + [MCell 5 |109|NOD inst_CLK_000_D2| |*] 3 [IOpin 3 | 94|INP A_21_|*|*] [RegIn 3 |111| -| | ] @@ -437,8 +453,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 95|INP A_18_|*|*] [RegIn 4 |114| -| | ] - [MCell 8 |113| -| | ] - [MCell 9 |115| -| | ] + [MCell 8 |113|NOD cpu_est_0_| |*] + [MCell 9 |115|NOD CLK_CNT_N_1_| |*] 5 [IOpin 5 | 96|INP A_16_|*|*] [RegIn 5 |117| -| | ] @@ -447,14 +463,54 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 97|INP A_19_|*|*] [RegIn 6 |120| -| | ] - [MCell 12 |119| -| | ] + [MCell 12 |119|NOD SM_AMIGA_4_| |*] [MCell 13 |121| -| | ] - 7 [IOpin 7 | 98|INP DS_030|*|*] + 7 [IOpin 7 | 98| IO DS_030|*|*] paired w/[ RN_DS_030] [RegIn 7 |123| -| | ] [MCell 14 |122| -| | ] [MCell 15 |124| -| | ] --------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Input Pin ( 86)| RST +Mux01| Mcel 2 1 ( 151)| CLK_CNT_N_0_ +Mux02| Mcel 5 8 ( 233)| SM_AMIGA_6_ +Mux03| Mcel 7 8 ( 281)| RN_AS_030 +Mux04| Input Pin ( 64)| CLK_030 +Mux05| Input Pin ( 14)| nEXP_SPACE +Mux06| ... | ... +Mux07| ... | ... +Mux08| IOPin 6 6 ( 71)| RW +Mux09| Mcel 0 1 ( 103)| SM_AMIGA_5_ +Mux10| Mcel 5 4 ( 227)| inst_BGACK_030_INT_D +Mux11| ... | ... +Mux12| IOPin 3 3 ( 32)| UDS_000 +Mux13| ... | ... +Mux14| ... | ... +Mux15| Mcel 0 0 ( 101)| RN_DS_030 +Mux16| Mcel 4 8 ( 209)| inst_CLK_000_D0 +Mux17| ... | ... +Mux18| Mcel 0 8 ( 113)| cpu_est_0_ +Mux19| ... | ... +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| ... | ... +Mux22| ... | ... +Mux23| IOPin 3 2 ( 33)| AS_000 +Mux24| Mcel 0 12 ( 119)| SM_AMIGA_4_ +Mux25| Mcel 5 0 ( 221)| inst_CLK_000_D1 +Mux26| ... | ... +Mux27| IOPin 3 4 ( 31)| LDS_000 +Mux28| ... | ... +Mux29| ... | ... +Mux30| ... | ... +Mux31| ... | ... +Mux32| ... | ... +--------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Macrocell (MCell) Cluster Assignments =========================================================================== @@ -467,19 +523,19 @@ IMX No. | +---- Block IO Pin or Macrocell Number _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| RESET|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig - 2| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| IPL_030_2_| IO| | S | 3 | 4 to [ 4]| 1 XOR free - 5| SM_AMIGA_2_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free - 6| SM_AMIGA_3_|NOD| | S | 3 | 4 to [ 6]| 1 XOR free + 5| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 5]| 1 XOR free + 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free 8| IPL_030_0_| IO| | S | 3 | 4 to [ 8]| 1 XOR free - 9| CLK_CNT_N_0_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free -10| inst_VPA_SYNC|NOD| | S | 2 | 4 to [10]| 1 XOR free + 9| SM_AMIGA_2_|NOD| | S | 3 | 4 to [ 9]| 1 XOR free +10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| IPL_030_1_| IO| | S | 3 | 4 to [12]| 1 XOR free -13| CLK_CNT_N_1_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig -14|inst_DTACK_SYNC|NOD| | S | 2 | 4 to [14]| 1 XOR free +13| | ? | | S | | 4 free | 1 XOR free +14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -492,22 +548,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| CLK_EXP|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) - 1| RESET|OUT| | S | 1 |=> can support up to [ 18] logic PT(s) - 2| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) - 3| | ? | | S | |=> can support up to [ 9] logic PT(s) - 4| IPL_030_2_| IO| | S | 3 |=> can support up to [ 10] logic PT(s) - 5| SM_AMIGA_2_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) - 6| SM_AMIGA_3_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 5] logic PT(s) - 8| IPL_030_0_| IO| | S | 3 |=> can support up to [ 10] logic PT(s) - 9| CLK_CNT_N_0_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) -10| inst_VPA_SYNC|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) -11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12| IPL_030_1_| IO| | S | 3 |=> can support up to [ 14] logic PT(s) -13| CLK_CNT_N_1_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) -14|inst_DTACK_SYNC|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) -15| | ? | | S | |=> can support up to [ 5] logic PT(s) + 0| CLK_EXP|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) + 1| RESET|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) + 2| | ? | | S | |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 10] logic PT(s) + 4| IPL_030_2_| IO| | S | 3 |=> can support up to [ 15] logic PT(s) + 5| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) + 6| | ? | | S | |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 10] logic PT(s) + 8| IPL_030_0_| IO| | S | 3 |=> can support up to [ 15] logic PT(s) + 9| SM_AMIGA_2_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) +10| | ? | | S | |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 15] logic PT(s) +12| IPL_030_1_| IO| | S | 3 |=> can support up to [ 20] logic PT(s) +13| | ? | | S | |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 15] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 1] > Node-Pin Assignments @@ -519,19 +575,19 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) 1| RESET|OUT| | => | 5 6 ( 7) 0 | 5 4 ( 3) 10 - 2| inst_VPA_D|NOD| | => | 6 7 0 1 | 4 3 10 9 + 2| | | | => | 6 7 0 1 | 4 3 10 9 3| | | | => | 6 7 0 1 | 4 3 10 9 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 - 5| SM_AMIGA_2_|NOD| | => | 7 0 1 2 | 3 10 9 8 - 6| SM_AMIGA_3_|NOD| | => | 0 1 2 3 | 10 9 8 7 + 5| SM_AMIGA_1_|NOD| | => | 7 0 1 2 | 3 10 9 8 + 6| | | | => | 0 1 2 3 | 10 9 8 7 7| | | | => | 0 1 2 3 | 10 9 8 7 8| IPL_030_0_| IO| | => | 1 ( 2) 3 4 | 9 ( 8) 7 6 - 9| CLK_CNT_N_0_|NOD| | => | 1 2 3 4 | 9 8 7 6 -10| inst_VPA_SYNC|NOD| | => | 2 3 4 5 | 8 7 6 5 + 9| SM_AMIGA_2_|NOD| | => | 1 2 3 4 | 9 8 7 6 +10| | | | => | 2 3 4 5 | 8 7 6 5 11| | | | => | 2 3 4 5 | 8 7 6 5 12| IPL_030_1_| IO| | => |( 3) 4 5 6 |( 7) 6 5 4 -13| CLK_CNT_N_1_|NOD| | => | 3 4 5 6 | 7 6 5 4 -14|inst_DTACK_SYNC|NOD| | => | 4 5 6 7 | 6 5 4 3 +13| | | | => | 3 4 5 6 | 7 6 5 4 +14| | | | => | 4 5 6 7 | 6 5 4 3 15| | | | => | 4 5 6 7 | 6 5 4 3 --------------------------------------------------------------------------- =========================================================================== @@ -589,37 +645,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_] [RegIn 1 |129| -| | ] - [MCell 2 |128|NOD inst_VPA_D| |*] + [MCell 2 |128| -| | ] [MCell 3 |130| -| | ] 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] [RegIn 2 |132| -| | ] [MCell 4 |131|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] - [MCell 5 |133|NOD SM_AMIGA_2_| |*] + [MCell 5 |133|NOD SM_AMIGA_1_| |*] 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] [RegIn 3 |135| -| | ] - [MCell 6 |134|NOD SM_AMIGA_3_| |*] + [MCell 6 |134| -| | ] [MCell 7 |136| -| | ] 4 [IOpin 4 | 6|INP A_29_|*|*] [RegIn 4 |138| -| | ] [MCell 8 |137|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] - [MCell 9 |139|NOD CLK_CNT_N_0_| |*] + [MCell 9 |139|NOD SM_AMIGA_2_| |*] 5 [IOpin 5 | 5|INP A_30_|*|*] [RegIn 5 |141| -| | ] - [MCell 10 |140|NOD inst_VPA_SYNC| |*] + [MCell 10 |140| -| | ] [MCell 11 |142| -| | ] 6 [IOpin 6 | 4|INP A_31_|*|*] [RegIn 6 |144| -| | ] [MCell 12 |143|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] - [MCell 13 |145|NOD CLK_CNT_N_1_| |*] + [MCell 13 |145| -| | ] 7 [IOpin 7 | 3|OUT RESET|*| ] [RegIn 7 |147| -| | ] - [MCell 14 |146|NOD inst_DTACK_SYNC| |*] + [MCell 14 |146| -| | ] [MCell 15 |148| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -628,38 +684,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST +Mux00| IOPin 6 2 ( 67)| IPL_0_ Mux01| Mcel 1 12 ( 143)| RN_IPL_030_1_ -Mux02| Mcel 6 4 ( 251)| RN_E -Mux03| Mcel 3 2 ( 176)| inst_CLK_000_D0 -Mux04| Mcel 3 6 ( 182)| cpu_est_1_ -Mux05| ... | ... -Mux06| Mcel 1 9 ( 139)| CLK_CNT_N_0_ -Mux07| Mcel 3 9 ( 187)| inst_CLK_000_D1 +Mux02| ... | ... +Mux03| IOPin 5 4 ( 56)| IPL_1_ +Mux04| Mcel 7 5 ( 277)| inst_CLK_000_D6 +Mux05| Mcel 4 1 ( 199)| inst_CLK_000_D5 +Mux06| Mcel 1 9 ( 139)| SM_AMIGA_2_ +Mux07| Mcel 2 5 ( 157)| inst_VPA_SYNC Mux08| Mcel 1 8 ( 137)| RN_IPL_030_0_ -Mux09| IOPin 3 5 ( 30)| DTACK -Mux10| Input Pin ( 36)| VPA -Mux11| Mcel 1 6 ( 134)| SM_AMIGA_3_ -Mux12| Mcel 1 10 ( 140)| inst_VPA_SYNC -Mux13| ... | ... -Mux14| Mcel 6 12 ( 263)| SM_AMIGA_4_ +Mux09| ... | ... +Mux10| ... | ... +Mux11| ... | ... +Mux12| ... | ... +Mux13| Mcel 2 9 ( 163)| inst_DTACK_SYNC +Mux14| Mcel 2 4 ( 155)| inst_CLK_OUT_PRE Mux15| ... | ... -Mux16| IOPin 6 2 ( 67)| IPL_0_ -Mux17| Mcel 3 1 ( 175)| RN_VMA -Mux18| Mcel 1 2 ( 128)| inst_VPA_D -Mux19| IOPin 7 3 ( 82)| AS_030 -Mux20| Mcel 1 14 ( 146)| inst_DTACK_SYNC -Mux21| IOPin 5 4 ( 56)| IPL_1_ +Mux16| Mcel 2 8 ( 161)| SM_AMIGA_3_ +Mux17| ... | ... +Mux18| ... | ... +Mux19| ... | ... +Mux20| ... | ... +Mux21| Input Pin ( 86)| RST Mux22| IOPin 6 3 ( 68)| IPL_2_ Mux23| ... | ... -Mux24| Mcel 6 1 ( 247)| inst_CLK_OUT_PRE -Mux25| ... | ... +Mux24| ... | ... +Mux25| Mcel 5 0 ( 221)| inst_CLK_000_D1 Mux26| ... | ... Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ -Mux28| Mcel 1 13 ( 145)| CLK_CNT_N_1_ +Mux28| Mcel 1 5 ( 133)| SM_AMIGA_1_ Mux29| ... | ... -Mux30| ... | ... -Mux31| Mcel 1 5 ( 133)| SM_AMIGA_2_ +Mux30| Mcel 4 8 ( 209)| inst_CLK_000_D0 +Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- =========================================================================== @@ -673,15 +729,15 @@ Mux32| ... | ... | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| AVEC_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1| | ? | | S | | 4 free | 1 XOR free + 1| CLK_CNT_N_0_|NOD| | S | 2 | 4 to [ 1]| 1 XOR free 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free - 4| | ? | | S | | 4 free | 1 XOR free - 5| | ? | | S | | 4 free | 1 XOR free + 4|inst_CLK_OUT_PRE|NOD| | S | 4 | 4 to [ 4]| 1 XOR free + 5| inst_VPA_SYNC|NOD| | S | 2 | 4 to [ 5]| 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| | ? | | S | | 4 free | 1 XOR free - 9| | ? | | S | | 4 free | 1 XOR free + 8| SM_AMIGA_3_|NOD| | S | 3 | 4 to [ 8]| 1 XOR free + 9|inst_DTACK_SYNC|NOD| | S | 2 | 4 to [ 9]| 1 XOR free 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig @@ -699,17 +755,17 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| AVEC_EXP|OUT| | S | 1 |=> can support up to [ 15] logic PT(s) - 1| | ? | | S | |=> can support up to [ 19] logic PT(s) - 2| | ? | | S | |=> can support up to [ 20] logic PT(s) - 3| | ? | | S | |=> can support up to [ 20] logic PT(s) - 4| | ? | | S | |=> can support up to [ 20] logic PT(s) - 5| | ? | | S | |=> can support up to [ 20] logic PT(s) - 6| | ? | | S | |=> can support up to [ 20] logic PT(s) - 7| | ? | | S | |=> can support up to [ 20] logic PT(s) - 8| | ? | | S | |=> can support up to [ 20] logic PT(s) - 9| | ? | | S | |=> can support up to [ 20] logic PT(s) -10| | ? | | S | |=> can support up to [ 19] logic PT(s) + 0| AVEC_EXP|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) + 1| CLK_CNT_N_0_|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) + 2| | ? | | S | |=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 10] logic PT(s) + 4|inst_CLK_OUT_PRE|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) + 5| inst_VPA_SYNC|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) + 6| | ? | | S | |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 10] logic PT(s) + 8| SM_AMIGA_3_|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) + 9|inst_DTACK_SYNC|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) 11| | ? | | S | |=> can support up to [ 19] logic PT(s) 12|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) 13| | ? | | S | |=> can support up to [ 19] logic PT(s) @@ -725,15 +781,15 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0| AVEC_EXP|OUT| | => | 5 6 ( 7) 0 | 20 21 ( 22) 15 - 1| | | | => | 5 6 7 0 | 20 21 22 15 + 1| CLK_CNT_N_0_|NOD| | => | 5 6 7 0 | 20 21 22 15 2| | | | => | 6 7 0 1 | 21 22 15 16 3| | | | => | 6 7 0 1 | 21 22 15 16 - 4| | | | => | 7 0 1 2 | 22 15 16 17 - 5| | | | => | 7 0 1 2 | 22 15 16 17 + 4|inst_CLK_OUT_PRE|NOD| | => | 7 0 1 2 | 22 15 16 17 + 5| inst_VPA_SYNC|NOD| | => | 7 0 1 2 | 22 15 16 17 6| | | | => | 0 1 2 3 | 15 16 17 18 7| | | | => | 0 1 2 3 | 15 16 17 18 - 8| | | | => | 1 2 3 4 | 16 17 18 19 - 9| | | | => | 1 2 3 4 | 16 17 18 19 + 8| SM_AMIGA_3_|NOD| | => | 1 2 3 4 | 16 17 18 19 + 9|inst_DTACK_SYNC|NOD| | => | 1 2 3 4 | 16 17 18 19 10| | | | => | 2 3 4 5 | 17 18 19 20 11| | | | => | 2 3 4 5 | 17 18 19 20 12|AMIGA_BUS_ENABLE_LOW|OUT| | => | 3 4 ( 5) 6 | 18 19 ( 20) 21 @@ -789,7 +845,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 15|INP A_28_|*|*] [RegIn 0 |150| -| | ] [MCell 0 |149|OUT AVEC_EXP| | ] - [MCell 1 |151| -| | ] + [MCell 1 |151|NOD CLK_CNT_N_0_| |*] 1 [IOpin 1 | 16|INP A_27_|*|*] [RegIn 1 |153| -| | ] @@ -798,8 +854,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 17|INP A_26_|*|*] [RegIn 2 |156| -| | ] - [MCell 4 |155| -| | ] - [MCell 5 |157| -| | ] + [MCell 4 |155|NOD inst_CLK_OUT_PRE| |*] + [MCell 5 |157|NOD inst_VPA_SYNC| |*] 3 [IOpin 3 | 18|INP A_25_|*|*] [RegIn 3 |159| -| | ] @@ -808,8 +864,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 19|INP A_24_|*|*] [RegIn 4 |162| -| | ] - [MCell 8 |161| -| | ] - [MCell 9 |163| -| | ] + [MCell 8 |161|NOD SM_AMIGA_3_| |*] + [MCell 9 |163|NOD inst_DTACK_SYNC| |*] 5 [IOpin 5 | 20|OUT AMIGA_BUS_ENABLE_LOW|*| ] [RegIn 5 |165| -| | ] @@ -832,30 +888,30 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| ... | ... -Mux01| ... | ... -Mux02| ... | ... -Mux03| ... | ... +Mux00| Input Pin ( 86)| RST +Mux01| Mcel 2 1 ( 151)| CLK_CNT_N_0_ +Mux02| Mcel 0 9 ( 115)| CLK_CNT_N_1_ +Mux03| Mcel 4 5 ( 205)| CLK_CNT_P_1_ Mux04| ... | ... Mux05| ... | ... -Mux06| Mcel 7 0 ( 269)| RN_FPU_CS -Mux07| ... | ... -Mux08| ... | ... -Mux09| ... | ... -Mux10| ... | ... -Mux11| ... | ... -Mux12| ... | ... -Mux13| ... | ... -Mux14| ... | ... +Mux06| ... | ... +Mux07| Mcel 2 5 ( 157)| inst_VPA_SYNC +Mux08| Mcel 4 8 ( 209)| inst_CLK_000_D0 +Mux09| Mcel 0 12 ( 119)| SM_AMIGA_4_ +Mux10| Input Pin ( 36)| VPA +Mux11| Mcel 6 4 ( 251)| RN_E +Mux12| Mcel 7 1 ( 271)| RN_FPU_CS +Mux13| Mcel 2 9 ( 163)| inst_DTACK_SYNC +Mux14| Mcel 6 12 ( 263)| cpu_est_1_ Mux15| ... | ... -Mux16| ... | ... -Mux17| ... | ... +Mux16| Mcel 2 8 ( 161)| SM_AMIGA_3_ +Mux17| Mcel 3 1 ( 175)| RN_VMA Mux18| ... | ... -Mux19| ... | ... +Mux19| IOPin 7 3 ( 82)| AS_030 Mux20| ... | ... Mux21| ... | ... -Mux22| ... | ... -Mux23| ... | ... +Mux22| Mcel 6 5 ( 253)| CLK_CNT_P_0_ +Mux23| IOPin 3 5 ( 30)| DTACK Mux24| ... | ... Mux25| ... | ... Mux26| ... | ... @@ -878,19 +934,19 @@ Mux32| ... | ... _|_________________|__|__|___|_____|__|______|___|__________|______________ 0| DTACK| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig 1| VMA| IO| | S | 2 :+: 1| 4 to [ 1]| 1 XOR to [ 1] - 2|inst_CLK_000_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig - 3|inst_CLK_000_D2|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig - 4|AMIGA_BUS_ENABLE| IO| | A | 3 | 2 to [ 4]| 1 XOR to [ 4] as logic PT - 5| AS_000| IO| | S | 2 | 4 to [ 5]| 1 XOR free - 6| cpu_est_1_|NOD| | S | 4 | 4 to [ 6]| 1 XOR free + 2| | ? | | S | | 4 free | 1 XOR free + 3| | ? | | S | | 4 free | 1 XOR free + 4| AS_000| IO| | S | 2 | 4 to [ 4]| 1 XOR free + 5|AMIGA_BUS_ENABLE| IO| | S | 7 | 4 to [ 5]| 1 XOR to [ 5] as logic PT + 6| | ? | | S | | 4 to [ 5]| 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| LDS_000| IO| | S | 8 | 4 to [ 8]| 1 XOR to [ 8] as logic PT - 9|inst_CLK_000_D1|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig -10| cpu_est_2_|NOD| | S | 3 :+: 1| 4 to [10]| 1 XOR to [10] + 8| LDS_000| IO| | S | 8 | 4 free | 1 XOR free + 9| | ? | | S | | 4 to [ 8]| 1 XOR free +10| | ? | | S | | 4 to [ 8]| 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| UDS_000| IO| | S | 5 | 4 to [12]| 1 XOR to [12] as logic PT 13| BG_000| IO| | S | 2 | 4 to [13]| 1 XOR free -14| SM_AMIGA_5_|NOD| | S | 2 | 4 to [14]| 1 XOR free +14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -903,22 +959,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| DTACK| IO| | S | 1 |=> can support up to [ 9] logic PT(s) - 1| VMA| IO| | S | 2 :+: 1|=> can support up to [ 16] logic PT(s) - 2|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) - 3|inst_CLK_000_D2|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) - 4|AMIGA_BUS_ENABLE| IO| | A | 3 |=> can support up to [ 7] logic PT(s) - 5| AS_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) - 6| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 5] logic PT(s) - 8| LDS_000| IO| | S | 8 |=> can support up to [ 14] logic PT(s) - 9|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 6] logic PT(s) -10| cpu_est_2_|NOD| | S | 3 :+: 1|=> can support up to [ 9] logic PT(s) + 0| DTACK| IO| | S | 1 |=> can support up to [ 10] logic PT(s) + 1| VMA| IO| | S | 2 :+: 1|=> can support up to [ 18] logic PT(s) + 2| | ? | | S | |=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 10] logic PT(s) + 4| AS_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) + 5|AMIGA_BUS_ENABLE| IO| | S | 7 |=> can support up to [ 15] logic PT(s) + 6| | ? | | S | |=> can support up to [ 11] logic PT(s) + 7| | ? | | S | |=> can support up to [ 10] logic PT(s) + 8| LDS_000| IO| | S | 8 |=> can support up to [ 20] logic PT(s) + 9| | ? | | S | |=> can support up to [ 11] logic PT(s) +10| | ? | | S | |=> can support up to [ 6] logic PT(s) 11| | ? | | S | |=> can support up to [ 5] logic PT(s) -12| UDS_000| IO| | S | 5 |=> can support up to [ 10] logic PT(s) -13| BG_000| IO| | S | 2 |=> can support up to [ 10] logic PT(s) -14| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 10] logic PT(s) -15| | ? | | S | |=> can support up to [ 5] logic PT(s) +12| UDS_000| IO| | S | 5 |=> can support up to [ 15] logic PT(s) +13| BG_000| IO| | S | 2 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 3] > Node-Pin Assignments @@ -930,19 +986,19 @@ _|_________________|__|__|___|_____|_______________________________________ _|_________________|__|_____|____________________|________________________ 0| DTACK| IO| | => |( 5) 6 7 0 |( 30) 29 28 35 1| VMA| IO| | => | 5 6 7 ( 0)| 30 29 28 ( 35) - 2|inst_CLK_000_D0|NOD| | => | 6 7 0 1 | 29 28 35 34 - 3|inst_CLK_000_D2|NOD| | => | 6 7 0 1 | 29 28 35 34 - 4|AMIGA_BUS_ENABLE| IO| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 - 5| AS_000| IO| | => | 7 0 1 ( 2)| 28 35 34 ( 33) - 6| cpu_est_1_|NOD| | => | 0 1 2 3 | 35 34 33 32 + 2| | | | => | 6 7 0 1 | 29 28 35 34 + 3| | | | => | 6 7 0 1 | 29 28 35 34 + 4| AS_000| IO| | => | 7 0 1 ( 2)| 28 35 34 ( 33) + 5|AMIGA_BUS_ENABLE| IO| | => | 7 0 ( 1) 2 | 28 35 ( 34) 33 + 6| | | | => | 0 1 2 3 | 35 34 33 32 7| | | | => | 0 1 2 3 | 35 34 33 32 8| LDS_000| IO| | => | 1 2 3 ( 4)| 34 33 32 ( 31) - 9|inst_CLK_000_D1|NOD| | => | 1 2 3 4 | 34 33 32 31 -10| cpu_est_2_|NOD| | => | 2 3 4 5 | 33 32 31 30 + 9| | | | => | 1 2 3 4 | 34 33 32 31 +10| | | | => | 2 3 4 5 | 33 32 31 30 11| | | | => | 2 3 4 5 | 33 32 31 30 12| UDS_000| IO| | => |( 3) 4 5 6 |( 32) 31 30 29 13| BG_000| IO| | => | 3 4 5 ( 6)| 32 31 30 ( 29) -14| SM_AMIGA_5_|NOD| | => | 4 5 6 7 | 31 30 29 28 +14| | | | => | 4 5 6 7 | 31 30 29 28 15| | | | => | 4 5 6 7 | 31 30 29 28 --------------------------------------------------------------------------- =========================================================================== @@ -955,8 +1011,8 @@ _|_________________|__|_____|____________________|________________________ | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ 0| VMA| IO|*| 35| => | 0 ( 1) 2 3 4 5 6 7 - 1|AMIGA_BUS_ENABLE| IO|*| 34| => | 2 3 ( 4) 5 6 7 8 9 - 2| AS_000| IO|*| 33| => | 4 ( 5) 6 7 8 9 10 11 + 1|AMIGA_BUS_ENABLE| IO|*| 34| => | 2 3 4 ( 5) 6 7 8 9 + 2| AS_000| IO|*| 33| => | ( 4) 5 6 7 8 9 10 11 3| UDS_000| IO|*| 32| => | 6 7 8 9 10 11 (12) 13 4| LDS_000| IO|*| 31| => | ( 8) 9 10 11 12 13 14 15 5| DTACK| IO|*| 30| => | 10 11 12 13 14 15 ( 0) 1 @@ -1003,27 +1059,27 @@ IMX No. | +---- Block IO Pin or Macrocell Number 1 [IOpin 1 | 34| IO AMIGA_BUS_ENABLE|*| ] paired w/[RN_AMIGA_BUS_ENABLE] [RegIn 1 |177| -| | ] - [MCell 2 |176|NOD inst_CLK_000_D0| |*] - [MCell 3 |178|NOD inst_CLK_000_D2| |*] + [MCell 2 |176| -| | ] + [MCell 3 |178| -| | ] - 2 [IOpin 2 | 33| IO AS_000|*| ] paired w/[ RN_AS_000] + 2 [IOpin 2 | 33| IO AS_000|*|*] paired w/[ RN_AS_000] [RegIn 2 |180| -| | ] - [MCell 4 |179|NOD RN_AMIGA_BUS_ENABLE| |*] paired w/[AMIGA_BUS_ENABLE] - [MCell 5 |181|NOD RN_AS_000| |*] paired w/[ AS_000] + [MCell 4 |179|NOD RN_AS_000| |*] paired w/[ AS_000] + [MCell 5 |181|NOD RN_AMIGA_BUS_ENABLE| |*] paired w/[AMIGA_BUS_ENABLE] - 3 [IOpin 3 | 32| IO UDS_000|*| ] paired w/[ RN_UDS_000] + 3 [IOpin 3 | 32| IO UDS_000|*|*] paired w/[ RN_UDS_000] [RegIn 3 |183| -| | ] - [MCell 6 |182|NOD cpu_est_1_| |*] + [MCell 6 |182| -| | ] [MCell 7 |184| -| | ] - 4 [IOpin 4 | 31| IO LDS_000|*| ] paired w/[ RN_LDS_000] + 4 [IOpin 4 | 31| IO LDS_000|*|*] paired w/[ RN_LDS_000] [RegIn 4 |186| -| | ] [MCell 8 |185|NOD RN_LDS_000| |*] paired w/[ LDS_000] - [MCell 9 |187|NOD inst_CLK_000_D1| |*] + [MCell 9 |187| -| | ] 5 [IOpin 5 | 30| IO DTACK|*|*] [RegIn 5 |189| -| | ] - [MCell 10 |188|NOD cpu_est_2_| |*] + [MCell 10 |188| -| | ] [MCell 11 |190| -| | ] 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] @@ -1033,7 +1089,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 7 [IOpin 7 | 28|INP BGACK_000|*|*] [RegIn 7 |195| -| | ] - [MCell 14 |194|NOD SM_AMIGA_5_| |*] + [MCell 14 |194| -| | ] [MCell 15 |196| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -1042,38 +1098,38 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| IOPin 6 5 ( 70)| SIZE_0_ +Mux00| IOPin 6 4 ( 69)| A0 Mux01| Mcel 3 13 ( 193)| RN_BG_000 Mux02| Mcel 6 4 ( 251)| RN_E -Mux03| Mcel 3 2 ( 176)| inst_CLK_000_D0 +Mux03| Input Pin ( 11)| CLK_000 Mux04| IOPin 2 6 ( 21)| BG_030 -Mux05| Mcel 3 8 ( 185)| RN_LDS_000 +Mux05| IOPin 0 7 ( 98)| DS_030 Mux06| IOPin 7 6 ( 79)| SIZE_1_ -Mux07| Mcel 3 9 ( 187)| inst_CLK_000_D1 -Mux08| IOPin 6 6 ( 71)| RW -Mux09| IOPin 7 3 ( 82)| AS_030 -Mux10| Mcel 3 4 ( 179)| RN_AMIGA_BUS_ENABLE +Mux07| Mcel 6 12 ( 263)| cpu_est_1_ +Mux08| Mcel 4 8 ( 209)| inst_CLK_000_D0 +Mux09| Mcel 0 12 ( 119)| SM_AMIGA_4_ +Mux10| Mcel 3 4 ( 179)| RN_AS_000 Mux11| Mcel 3 12 ( 191)| RN_UDS_000 -Mux12| IOPin 0 7 ( 98)| DS_030 -Mux13| Mcel 7 5 ( 277)| SM_AMIGA_6_ -Mux14| Input Pin ( 11)| CLK_000 +Mux12| Mcel 0 1 ( 103)| SM_AMIGA_5_ +Mux13| Input Pin ( 36)| VPA +Mux14| IOPin 6 5 ( 70)| SIZE_0_ Mux15| Input Pin ( 14)| nEXP_SPACE -Mux16| Mcel 3 6 ( 182)| cpu_est_1_ -Mux17| Mcel 3 14 ( 194)| SM_AMIGA_5_ -Mux18| IOPin 6 4 ( 69)| A_0_ -Mux19| Mcel 7 1 ( 271)| cpu_est_0_ -Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux16| Mcel 3 8 ( 185)| RN_LDS_000 +Mux17| Mcel 3 1 ( 175)| RN_VMA +Mux18| Mcel 0 8 ( 113)| cpu_est_0_ +Mux19| IOPin 7 3 ( 82)| AS_030 +Mux20| Mcel 5 8 ( 233)| SM_AMIGA_6_ Mux21| Input Pin ( 86)| RST Mux22| ... | ... -Mux23| Mcel 6 12 ( 263)| SM_AMIGA_4_ -Mux24| Mcel 3 5 ( 181)| RN_AS_000 -Mux25| Mcel 1 2 ( 128)| inst_VPA_D +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux24| Mcel 3 5 ( 181)| RN_AMIGA_BUS_ENABLE +Mux25| IOPin 6 6 ( 71)| RW Mux26| ... | ... -Mux27| Mcel 3 1 ( 175)| RN_VMA -Mux28| Mcel 6 8 ( 257)| SM_AMIGA_7_ -Mux29| Input Pin ( 61)| CLK_OSZI -Mux30| Mcel 3 10 ( 188)| cpu_est_2_ -Mux31| ... | ... +Mux27| Mcel 6 9 ( 259)| cpu_est_2_ +Mux28| ... | ... +Mux29| Mcel 5 4 ( 227)| inst_BGACK_030_INT_D +Mux30| Mcel 5 1 ( 223)| SM_AMIGA_0_ +Mux31| Mcel 5 12 ( 239)| SM_AMIGA_7_ Mux32| IOPin 7 4 ( 81)| DSACK_1_ --------------------------------------------------------------------------- =========================================================================== @@ -1086,16 +1142,16 @@ Mux32| IOPin 7 4 ( 81)| DSACK_1_ | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0|AMIGA_BUS_DATA_DIR|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1| | ? | | S | | 4 free | 1 XOR free + 0|AMIGA_BUS_DATA_DIR|OUT| | S | 2 | 4 to [ 0]| 1 XOR free + 1|inst_CLK_000_D5|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| BERR|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig - 5| | ? | | S | | 4 free | 1 XOR free + 5| CLK_CNT_P_1_|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| | ? | | S | | 4 free | 1 XOR free - 9| | ? | | S | | 4 free | 1 XOR free + 8|inst_CLK_000_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9|inst_CLK_000_D3|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free 12| CIIN|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig @@ -1113,17 +1169,17 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0|AMIGA_BUS_DATA_DIR|OUT| | S | 1 |=> can support up to [ 15] logic PT(s) - 1| | ? | | S | |=> can support up to [ 19] logic PT(s) - 2| | ? | | S | |=> can support up to [ 19] logic PT(s) - 3| | ? | | S | |=> can support up to [ 19] logic PT(s) - 4| BERR|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) - 5| | ? | | S | |=> can support up to [ 19] logic PT(s) - 6| | ? | | S | |=> can support up to [ 20] logic PT(s) - 7| | ? | | S | |=> can support up to [ 20] logic PT(s) - 8| | ? | | S | |=> can support up to [ 20] logic PT(s) - 9| | ? | | S | |=> can support up to [ 20] logic PT(s) -10| | ? | | S | |=> can support up to [ 19] logic PT(s) + 0|AMIGA_BUS_DATA_DIR|OUT| | S | 2 |=> can support up to [ 14] logic PT(s) + 1|inst_CLK_000_D5|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) + 2| | ? | | S | |=> can support up to [ 18] logic PT(s) + 3| | ? | | S | |=> can support up to [ 18] logic PT(s) + 4| BERR|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) + 5| CLK_CNT_P_1_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 6| | ? | | S | |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 18] logic PT(s) + 8|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 9|inst_CLK_000_D3|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 18] logic PT(s) 11| | ? | | S | |=> can support up to [ 19] logic PT(s) 12| CIIN|OUT| | S | 1 |=> can support up to [ 20] logic PT(s) 13| | ? | | S | |=> can support up to [ 19] logic PT(s) @@ -1139,15 +1195,15 @@ _|_________________|__|__|___|_____|_______________________________________ | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ 0|AMIGA_BUS_DATA_DIR|OUT| | => | 5 6 ( 7) 0 | 46 47 ( 48) 41 - 1| | | | => | 5 6 7 0 | 46 47 48 41 + 1|inst_CLK_000_D5|NOD| | => | 5 6 7 0 | 46 47 48 41 2| | | | => | 6 7 0 1 | 47 48 41 42 3| | | | => | 6 7 0 1 | 47 48 41 42 4| BERR|OUT| | => | 7 ( 0) 1 2 | 48 ( 41) 42 43 - 5| | | | => | 7 0 1 2 | 48 41 42 43 + 5| CLK_CNT_P_1_|NOD| | => | 7 0 1 2 | 48 41 42 43 6| | | | => | 0 1 2 3 | 41 42 43 44 7| | | | => | 0 1 2 3 | 41 42 43 44 - 8| | | | => | 1 2 3 4 | 42 43 44 45 - 9| | | | => | 1 2 3 4 | 42 43 44 45 + 8|inst_CLK_000_D0|NOD| | => | 1 2 3 4 | 42 43 44 45 + 9|inst_CLK_000_D3|NOD| | => | 1 2 3 4 | 42 43 44 45 10| | | | => | 2 3 4 5 | 43 44 45 46 11| | | | => | 2 3 4 5 | 43 44 45 46 12| CIIN|OUT| | => | 3 4 5 ( 6)| 44 45 46 ( 47) @@ -1203,7 +1259,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 0 [IOpin 0 | 41|OUT BERR|*| ] [RegIn 0 |198| -| | ] [MCell 0 |197|OUT AMIGA_BUS_DATA_DIR| | ] - [MCell 1 |199| -| | ] + [MCell 1 |199|NOD inst_CLK_000_D5| |*] 1 [IOpin 1 | 42| -| | ] [RegIn 1 |201| -| | ] @@ -1213,7 +1269,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 43| -| | ] [RegIn 2 |204| -| | ] [MCell 4 |203|OUT BERR| | ] - [MCell 5 |205| -| | ] + [MCell 5 |205|NOD CLK_CNT_P_1_| |*] 3 [IOpin 3 | 44| -| | ] [RegIn 3 |207| -| | ] @@ -1222,8 +1278,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 45| -| | ] [RegIn 4 |210| -| | ] - [MCell 8 |209| -| | ] - [MCell 9 |211| -| | ] + [MCell 8 |209|NOD inst_CLK_000_D0| |*] + [MCell 9 |211|NOD inst_CLK_000_D3| |*] 5 [IOpin 5 | 46| -| | ] [RegIn 5 |213| -| | ] @@ -1246,29 +1302,29 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| ... | ... +Mux00| Input Pin ( 86)| RST Mux01| IOPin 1 6 ( 4)| A_31_ -Mux02| ... | ... +Mux02| Mcel 0 5 ( 109)| inst_CLK_000_D2 Mux03| IOPin 2 1 ( 16)| A_27_ Mux04| IOPin 1 4 ( 6)| A_29_ Mux05| IOPin 2 4 ( 19)| A_24_ -Mux06| Mcel 7 0 ( 269)| RN_FPU_CS +Mux06| ... | ... Mux07| IOPin 2 0 ( 15)| A_28_ Mux08| IOPin 7 0 ( 85)| A_22_ Mux09| IOPin 1 5 ( 5)| A_30_ -Mux10| ... | ... +Mux10| Mcel 7 1 ( 271)| RN_FPU_CS Mux11| IOPin 7 1 ( 84)| A_23_ Mux12| IOPin 2 3 ( 18)| A_25_ Mux13| ... | ... -Mux14| ... | ... +Mux14| Input Pin ( 11)| CLK_000 Mux15| IOPin 0 3 ( 94)| A_21_ Mux16| ... | ... Mux17| IOPin 2 2 ( 17)| A_26_ -Mux18| ... | ... +Mux18| Mcel 5 9 ( 235)| inst_CLK_000_D4 Mux19| ... | ... -Mux20| ... | ... +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 Mux21| ... | ... -Mux22| ... | ... +Mux22| Mcel 6 5 ( 253)| CLK_CNT_P_0_ Mux23| ... | ... Mux24| ... | ... Mux25| IOPin 6 6 ( 71)| RW @@ -1280,6 +1336,85 @@ Mux30| ... | ... Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0|inst_CLK_000_D1|NOD| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1| SM_AMIGA_0_|NOD| | S | 4 | 4 to [ 1]| 1 XOR free + 2| | ? | | S | | 4 free | 1 XOR free + 3| | ? | | S | | 4 free | 1 XOR free + 4|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 5|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 5]| 1 XOR to [ 5] as logic PT + 6| | ? | | S | | 4 to [ 5]| 1 XOR free + 7| | ? | | S | | 4 free | 1 XOR free + 8| SM_AMIGA_6_|NOD| | S | 2 | 4 free | 1 XOR free + 9|inst_CLK_000_D4|NOD| | S | 1 | 4 to [ 8]| 1 XOR to [ 9] for 1 PT sig +10| | ? | | S | | 4 free | 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free +12| SM_AMIGA_7_|NOD| | S | 5 | 4 to [12]| 1 XOR to [12] as logic PT +13| | ? | | S | | 4 free | 1 XOR free +14| | ? | | S | | 4 free | 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 1| SM_AMIGA_0_|NOD| | S | 4 |=> can support up to [ 19] logic PT(s) + 2| | ? | | S | |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 14] logic PT(s) + 4|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 5|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 19] logic PT(s) + 6| | ? | | S | |=> can support up to [ 11] logic PT(s) + 7| | ? | | S | |=> can support up to [ 10] logic PT(s) + 8| SM_AMIGA_6_|NOD| | S | 2 |=> can support up to [ 19] logic PT(s) + 9|inst_CLK_000_D4|NOD| | S | 1 |=> can support up to [ 16] logic PT(s) +10| | ? | | S | |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 15] logic PT(s) +12| SM_AMIGA_7_|NOD| | S | 5 |=> can support up to [ 20] logic PT(s) +13| | ? | | S | |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 15] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0|inst_CLK_000_D1|NOD| | => | 5 6 7 0 | 55 54 53 60 + 1| SM_AMIGA_0_|NOD| | => | 5 6 7 0 | 55 54 53 60 + 2| | | | => | 6 7 0 1 | 54 53 60 59 + 3| | | | => | 6 7 0 1 | 54 53 60 59 + 4|inst_BGACK_030_INT_D|NOD| | => | 7 0 1 2 | 53 60 59 58 + 5|inst_AS_030_000_SYNC|NOD| | => | 7 0 1 2 | 53 60 59 58 + 6| | | | => | 0 1 2 3 | 60 59 58 57 + 7| | | | => | 0 1 2 3 | 60 59 58 57 + 8| SM_AMIGA_6_|NOD| | => | 1 2 3 4 | 59 58 57 56 + 9|inst_CLK_000_D4|NOD| | => | 1 2 3 4 | 59 58 57 56 +10| | | | => | 2 3 4 5 | 58 57 56 55 +11| | | | => | 2 3 4 5 | 58 57 56 55 +12| SM_AMIGA_7_|NOD| | => | 3 4 5 6 | 57 56 55 54 +13| | | | => | 3 4 5 6 | 57 56 55 54 +14| | | | => | 4 5 6 7 | 56 55 54 53 +15| | | | => | 4 5 6 7 | 56 55 54 53 +--------------------------------------------------------------------------- =========================================================================== < Block [ 5] > IO-to-Node Pin Mapping =========================================================================== @@ -1327,8 +1462,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 60| -| | ] [RegIn 0 |222| -| | ] - [MCell 0 |221| -| | ] - [MCell 1 |223| -| | ] + [MCell 0 |221|NOD inst_CLK_000_D1| |*] + [MCell 1 |223|NOD SM_AMIGA_0_| |*] 1 [IOpin 1 | 59|INP A_17_|*|*] [RegIn 1 |225| -| | ] @@ -1337,8 +1472,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 2 [IOpin 2 | 58|INP FC_1_|*|*] [RegIn 2 |228| -| | ] - [MCell 4 |227| -| | ] - [MCell 5 |229| -| | ] + [MCell 4 |227|NOD inst_BGACK_030_INT_D| |*] + [MCell 5 |229|NOD inst_AS_030_000_SYNC| |*] 3 [IOpin 3 | 57|INP FC_0_|*|*] [RegIn 3 |231| -| | ] @@ -1347,8 +1482,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number 4 [IOpin 4 | 56|INP IPL_1_|*|*] [RegIn 4 |234| -| | ] - [MCell 8 |233| -| | ] - [MCell 9 |235| -| | ] + [MCell 8 |233|NOD SM_AMIGA_6_| |*] + [MCell 9 |235|NOD inst_CLK_000_D4| |*] 5 [IOpin 5 | 55| -| | ] [RegIn 5 |237| -| | ] @@ -1357,7 +1492,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number 6 [IOpin 6 | 54| -| | ] [RegIn 6 |240| -| | ] - [MCell 12 |239| -| | ] + [MCell 12 |239|NOD SM_AMIGA_7_| |*] [MCell 13 |241| -| | ] 7 [IOpin 7 | 53| -| | ] @@ -1365,6 +1500,46 @@ IMX No. | +---- Block IO Pin or Macrocell Number [MCell 14 |242| -| | ] [MCell 15 |244| -| | ] --------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Input Pin ( 86)| RST +Mux01| IOPin 5 2 ( 58)| FC_1_ +Mux02| Mcel 4 9 ( 211)| inst_CLK_000_D3 +Mux03| ... | ... +Mux04| IOPin 3 7 ( 28)| BGACK_000 +Mux05| Input Pin ( 14)| nEXP_SPACE +Mux06| IOPin 5 3 ( 57)| FC_0_ +Mux07| ... | ... +Mux08| IOPin 5 1 ( 59)| A_17_ +Mux09| Mcel 5 5 ( 229)| inst_AS_030_000_SYNC +Mux10| Mcel 3 4 ( 179)| RN_AS_000 +Mux11| IOPin 0 5 ( 96)| A_16_ +Mux12| IOPin 0 6 ( 97)| A_19_ +Mux13| Mcel 7 5 ( 277)| inst_CLK_000_D6 +Mux14| ... | ... +Mux15| Mcel 5 1 ( 223)| SM_AMIGA_0_ +Mux16| Mcel 4 8 ( 209)| inst_CLK_000_D0 +Mux17| IOPin 0 4 ( 95)| A_18_ +Mux18| Mcel 0 5 ( 109)| inst_CLK_000_D2 +Mux19| IOPin 7 3 ( 82)| AS_030 +Mux20| Input Pin ( 64)| CLK_030 +Mux21| ... | ... +Mux22| ... | ... +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux24| ... | ... +Mux25| ... | ... +Mux26| ... | ... +Mux27| ... | ... +Mux28| Mcel 1 5 ( 133)| SM_AMIGA_1_ +Mux29| Mcel 4 1 ( 199)| inst_CLK_000_D5 +Mux30| ... | ... +Mux31| Mcel 5 12 ( 239)| SM_AMIGA_7_ +Mux32| Mcel 5 8 ( 233)| SM_AMIGA_6_ +--------------------------------------------------------------------------- =========================================================================== < Block [ 6] > Macrocell (MCell) Cluster Assignments =========================================================================== @@ -1375,20 +1550,20 @@ IMX No. | +---- Block IO Pin or Macrocell Number | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig - 1|inst_CLK_OUT_PRE|NOD| | S | 4 | 4 to [ 1]| 1 XOR free + 0| SIZE_0_| IO| | S | 2 | 4 to [ 0]| 1 XOR free + 1| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| E| IO| | S | 3 :+: 1| 4 to [ 4]| 1 XOR to [ 4] 5| CLK_CNT_P_0_|NOD| | S | 2 | 4 to [ 5]| 1 XOR free 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| SM_AMIGA_7_|NOD| | S | 5 | 4 to [ 8]| 1 XOR to [ 8] as logic PT - 9|inst_CLK_000_D5|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig + 8| A0| IO| | S | 2 | 4 to [ 8]| 1 XOR free + 9| cpu_est_2_|NOD| | S | 3 :+: 1| 4 to [ 9]| 1 XOR to [ 9] 10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| SM_AMIGA_4_|NOD| | S | 2 | 4 to [12]| 1 XOR free -13| SM_AMIGA_0_|NOD| | S | 4 | 4 to [13]| 1 XOR free +12| cpu_est_1_|NOD| | S | 4 | 4 to [12]| 1 XOR free +13| | ? | | S | | 4 free | 1 XOR free 14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- @@ -1402,21 +1577,21 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 10] logic PT(s) - 1|inst_CLK_OUT_PRE|NOD| | S | 4 |=> can support up to [ 19] logic PT(s) - 2| | ? | | S | |=> can support up to [ 10] logic PT(s) + 0| SIZE_0_| IO| | S | 2 |=> can support up to [ 14] logic PT(s) + 1| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 15] logic PT(s) + 2| | ? | | S | |=> can support up to [ 14] logic PT(s) 3| | ? | | S | |=> can support up to [ 10] logic PT(s) 4| E| IO| | S | 3 :+: 1|=> can support up to [ 14] logic PT(s) 5| CLK_CNT_P_0_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) 6| | ? | | S | |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 14] logic PT(s) - 8| SM_AMIGA_7_|NOD| | S | 5 |=> can support up to [ 19] logic PT(s) - 9|inst_CLK_000_D5|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) -10| | ? | | S | |=> can support up to [ 14] logic PT(s) -11| | ? | | S | |=> can support up to [ 10] logic PT(s) -12| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) -13| SM_AMIGA_0_|NOD| | S | 4 |=> can support up to [ 15] logic PT(s) -14| | ? | | S | |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 10] logic PT(s) + 8| A0| IO| | S | 2 |=> can support up to [ 15] logic PT(s) + 9| cpu_est_2_|NOD| | S | 3 :+: 1|=> can support up to [ 14] logic PT(s) +10| | ? | | S | |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 15] logic PT(s) +12| cpu_est_1_|NOD| | S | 4 |=> can support up to [ 20] logic PT(s) +13| | ? | | S | |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 15] logic PT(s) 15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== @@ -1427,20 +1602,20 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 6] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) - 1|inst_CLK_OUT_PRE|NOD| | => | 5 6 7 0 | 70 71 72 65 + 0| SIZE_0_| IO| | => |( 5) 6 7 0 |( 70) 71 72 65 + 1| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) 2| | | | => | 6 7 0 1 | 71 72 65 66 3| | | | => | 6 7 0 1 | 71 72 65 66 4| E| IO| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 5| CLK_CNT_P_0_|NOD| | => | 7 0 1 2 | 72 65 66 67 6| | | | => | 0 1 2 3 | 65 66 67 68 7| | | | => | 0 1 2 3 | 65 66 67 68 - 8| SM_AMIGA_7_|NOD| | => | 1 2 3 4 | 66 67 68 69 - 9|inst_CLK_000_D5|NOD| | => | 1 2 3 4 | 66 67 68 69 + 8| A0| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69) + 9| cpu_est_2_|NOD| | => | 1 2 3 4 | 66 67 68 69 10| | | | => | 2 3 4 5 | 67 68 69 70 11| | | | => | 2 3 4 5 | 67 68 69 70 -12| SM_AMIGA_4_|NOD| | => | 3 4 5 6 | 68 69 70 71 -13| SM_AMIGA_0_|NOD| | => | 3 4 5 6 | 68 69 70 71 +12| cpu_est_1_|NOD| | => | 3 4 5 6 | 68 69 70 71 +13| | | | => | 3 4 5 6 | 68 69 70 71 14| | | | => | 4 5 6 7 | 69 70 71 72 15| | | | => | 4 5 6 7 | 69 70 71 72 --------------------------------------------------------------------------- @@ -1453,12 +1628,12 @@ _|_________________|__|_____|____________________|________________________ | Sig Type--+ | | | | Signal Name | | | | Node Destinations Via Output Matrix _|_________________|__|___|_____|___________________________________________ - 0| CLK_DIV_OUT|OUT|*| 65| => | ( 0) 1 2 3 4 5 6 7 + 0| CLK_DIV_OUT|OUT|*| 65| => | 0 ( 1) 2 3 4 5 6 7 1| E| IO|*| 66| => | 2 3 ( 4) 5 6 7 8 9 2| IPL_0_|INP|*| 67| => | 4 5 6 7 8 9 10 11 3| IPL_2_|INP|*| 68| => | 6 7 8 9 10 11 12 13 - 4| A_0_|INP|*| 69| => | 8 9 10 11 12 13 14 15 - 5| SIZE_0_|INP|*| 70| => | 10 11 12 13 14 15 0 1 + 4| A0| IO|*| 69| => | ( 8) 9 10 11 12 13 14 15 + 5| SIZE_0_| IO|*| 70| => | 10 11 12 13 14 15 ( 0) 1 6| RW|INP|*| 71| => | 12 13 14 15 0 1 2 3 7| | | | 72| => | 14 15 0 1 2 3 4 5 --------------------------------------------------------------------------- @@ -1476,8 +1651,10 @@ _|_________________|__|___|_____|__________________________________________ | | | | | | IO paired w/ node [ RN_E] 2| IPL_0_|INP|*| 67| => | Input macrocell [ -] 3| IPL_2_|INP|*| 68| => | Input macrocell [ -] - 4| A_0_|INP|*| 69| => | Input macrocell [ -] - 5| SIZE_0_|INP|*| 70| => | Input macrocell [ -] + 4| A0| IO|*| 69| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_A0] + 5| SIZE_0_| IO|*| 70| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_SIZE_0_] 6| RW|INP|*| 71| => | Input macrocell [ -] 7| | | | 72| => | Input macrocell [ -] --------------------------------------------------------------------------- @@ -1492,8 +1669,8 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 65|OUT CLK_DIV_OUT|*| ] [RegIn 0 |246| -| | ] - [MCell 0 |245|OUT CLK_DIV_OUT| | ] - [MCell 1 |247|NOD inst_CLK_OUT_PRE| |*] + [MCell 0 |245|NOD RN_SIZE_0_| |*] paired w/[ SIZE_0_] + [MCell 1 |247|OUT CLK_DIV_OUT| | ] 1 [IOpin 1 | 66| IO E|*| ] paired w/[ RN_E] [RegIn 1 |249| -| | ] @@ -1510,20 +1687,20 @@ IMX No. | +---- Block IO Pin or Macrocell Number [MCell 6 |254| -| | ] [MCell 7 |256| -| | ] - 4 [IOpin 4 | 69|INP A_0_|*|*] + 4 [IOpin 4 | 69| IO A0|*|*] paired w/[ RN_A0] [RegIn 4 |258| -| | ] - [MCell 8 |257|NOD SM_AMIGA_7_| |*] - [MCell 9 |259|NOD inst_CLK_000_D5| |*] + [MCell 8 |257|NOD RN_A0| |*] paired w/[ A0] + [MCell 9 |259|NOD cpu_est_2_| |*] - 5 [IOpin 5 | 70|INP SIZE_0_|*|*] + 5 [IOpin 5 | 70| IO SIZE_0_|*|*] paired w/[ RN_SIZE_0_] [RegIn 5 |261| -| | ] [MCell 10 |260| -| | ] [MCell 11 |262| -| | ] 6 [IOpin 6 | 71|INP RW|*|*] [RegIn 6 |264| -| | ] - [MCell 12 |263|NOD SM_AMIGA_4_| |*] - [MCell 13 |265|NOD SM_AMIGA_0_| |*] + [MCell 12 |263|NOD cpu_est_1_| |*] + [MCell 13 |265| -| | ] 7 [IOpin 7 | 72| -| | ] [RegIn 7 |267| -| | ] @@ -1538,33 +1715,33 @@ IMX No. | +---- Block IO Pin or Macrocell Number --|--|--------------------|--------------------------------------------------- Mux00| Input Pin ( 86)| RST Mux01| ... | ... -Mux02| Mcel 7 14 ( 290)| CLK_CNT_P_1_ -Mux03| Mcel 3 2 ( 176)| inst_CLK_000_D0 -Mux04| Mcel 7 5 ( 277)| SM_AMIGA_6_ -Mux05| Mcel 7 9 ( 283)| inst_AS_030_000_SYNC -Mux06| Mcel 1 9 ( 139)| CLK_CNT_N_0_ -Mux07| Mcel 3 5 ( 181)| RN_AS_000 -Mux08| ... | ... -Mux09| Mcel 3 3 ( 178)| inst_CLK_000_D2 -Mux10| Mcel 1 13 ( 145)| CLK_CNT_N_1_ -Mux11| Mcel 6 4 ( 251)| RN_E -Mux12| Mcel 6 13 ( 265)| SM_AMIGA_0_ -Mux13| Mcel 6 8 ( 257)| SM_AMIGA_7_ -Mux14| Mcel 7 2 ( 272)| inst_CLK_000_D3 -Mux15| Input Pin ( 14)| nEXP_SPACE -Mux16| Mcel 3 6 ( 182)| cpu_est_1_ -Mux17| Mcel 3 14 ( 194)| SM_AMIGA_5_ -Mux18| Mcel 7 10 ( 284)| inst_CLK_000_D4 -Mux19| Mcel 7 1 ( 271)| cpu_est_0_ -Mux20| Mcel 3 10 ( 188)| cpu_est_2_ -Mux21| Mcel 7 6 ( 278)| inst_CLK_000_D6 +Mux02| Mcel 6 4 ( 251)| RN_E +Mux03| Mcel 4 5 ( 205)| CLK_CNT_P_1_ +Mux04| Input Pin ( 64)| CLK_030 +Mux05| Input Pin ( 14)| nEXP_SPACE +Mux06| Mcel 2 4 ( 155)| inst_CLK_OUT_PRE +Mux07| Mcel 6 12 ( 263)| cpu_est_1_ +Mux08| IOPin 3 3 ( 32)| UDS_000 +Mux09| ... | ... +Mux10| Mcel 6 8 ( 257)| RN_A0 +Mux11| ... | ... +Mux12| Mcel 6 9 ( 259)| cpu_est_2_ +Mux13| ... | ... +Mux14| Mcel 5 4 ( 227)| inst_BGACK_030_INT_D +Mux15| ... | ... +Mux16| Mcel 4 8 ( 209)| inst_CLK_000_D0 +Mux17| Mcel 6 0 ( 245)| RN_SIZE_0_ +Mux18| Mcel 0 8 ( 113)| cpu_est_0_ +Mux19| ... | ... +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| ... | ... Mux22| Mcel 6 5 ( 253)| CLK_CNT_P_0_ -Mux23| Mcel 6 12 ( 263)| SM_AMIGA_4_ -Mux24| Mcel 6 1 ( 247)| inst_CLK_OUT_PRE -Mux25| Mcel 3 9 ( 187)| inst_CLK_000_D1 +Mux23| IOPin 3 2 ( 33)| AS_000 +Mux24| IOPin 3 4 ( 31)| LDS_000 +Mux25| Mcel 5 0 ( 221)| inst_CLK_000_D1 Mux26| ... | ... -Mux27| Mcel 6 9 ( 259)| inst_CLK_000_D5 -Mux28| Mcel 7 13 ( 289)| SM_AMIGA_1_ +Mux27| ... | ... +Mux28| ... | ... Mux29| ... | ... Mux30| ... | ... Mux31| ... | ... @@ -1580,21 +1757,21 @@ Mux32| ... | ... | Sig Type-+ | | | | | | | XOR to Mcell Assignment | Signal Name | | | | | | | | | _|_________________|__|__|___|_____|__|______|___|__________|______________ - 0| FPU_CS| IO| | S | 2 | 4 to [ 0]| 1 XOR free - 1| cpu_est_0_|NOD| | S | 3 | 4 to [ 1]| 1 XOR free - 2|inst_CLK_000_D3|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 0| SIZE_1_| IO| | S | 3 | 4 to [ 0]| 1 XOR free + 1| FPU_CS| IO| | S | 2 | 4 to [ 1]| 1 XOR free + 2| | ? | | S | | 4 free | 1 XOR free 3| | ? | | S | | 4 free | 1 XOR free 4| BGACK_030| IO| | S | 2 | 4 to [ 4]| 1 XOR free - 5| SM_AMIGA_6_|NOD| | S | 2 | 4 to [ 5]| 1 XOR free - 6|inst_CLK_000_D6|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 5|inst_CLK_000_D6|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 6| | ? | | S | | 4 free | 1 XOR free 7| | ? | | S | | 4 free | 1 XOR free - 8| DSACK_1_| IO| | S | 2 | 4 to [ 8]| 1 XOR free - 9|inst_AS_030_000_SYNC|NOD| | S | 7 | 4 to [ 9]| 1 XOR to [ 9] as logic PT -10|inst_CLK_000_D4|NOD| | S | 1 | 4 to [ 9]| 1 XOR to [10] for 1 PT sig + 8| AS_030| IO| | S | 3 | 4 to [ 8]| 1 XOR free + 9| | ? | | S | | 4 free | 1 XOR free +10| | ? | | S | | 4 free | 1 XOR free 11| | ? | | S | | 4 free | 1 XOR free -12| DSACK_0_|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig -13| SM_AMIGA_1_|NOD| | S | 3 | 4 to [13]| 1 XOR free -14| CLK_CNT_P_1_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +12| DSACK_1_| IO| | S | 2 | 4 to [12]| 1 XOR free +13| DSACK_0_|OUT| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +14| | ? | | S | | 4 free | 1 XOR free 15| | ? | | S | | 4 free | 1 XOR free --------------------------------------------------------------------------- =========================================================================== @@ -1607,22 +1784,22 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________ | Sig Type-+ | | | | | Signal Name | | | | | Maximum PT Capacity _|_________________|__|__|___|_____|_______________________________________ - 0| FPU_CS| IO| | S | 2 |=> can support up to [ 9] logic PT(s) - 1| cpu_est_0_|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) - 2|inst_CLK_000_D3|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) - 3| | ? | | S | |=> can support up to [ 9] logic PT(s) - 4| BGACK_030| IO| | S | 2 |=> can support up to [ 14] logic PT(s) - 5| SM_AMIGA_6_|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) - 6|inst_CLK_000_D6|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) - 7| | ? | | S | |=> can support up to [ 9] logic PT(s) - 8| DSACK_1_| IO| | S | 2 |=> can support up to [ 10] logic PT(s) - 9|inst_AS_030_000_SYNC|NOD| | S | 7 |=> can support up to [ 14] logic PT(s) -10|inst_CLK_000_D4|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) -11| | ? | | S | |=> can support up to [ 9] logic PT(s) -12| DSACK_0_|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) -13| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 18] logic PT(s) -14| CLK_CNT_P_1_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) -15| | ? | | S | |=> can support up to [ 9] logic PT(s) + 0| SIZE_1_| IO| | S | 3 |=> can support up to [ 10] logic PT(s) + 1| FPU_CS| IO| | S | 2 |=> can support up to [ 15] logic PT(s) + 2| | ? | | S | |=> can support up to [ 10] logic PT(s) + 3| | ? | | S | |=> can support up to [ 14] logic PT(s) + 4| BGACK_030| IO| | S | 2 |=> can support up to [ 19] logic PT(s) + 5|inst_CLK_000_D6|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) + 6| | ? | | S | |=> can support up to [ 14] logic PT(s) + 7| | ? | | S | |=> can support up to [ 15] logic PT(s) + 8| AS_030| IO| | S | 3 |=> can support up to [ 20] logic PT(s) + 9| | ? | | S | |=> can support up to [ 15] logic PT(s) +10| | ? | | S | |=> can support up to [ 15] logic PT(s) +11| | ? | | S | |=> can support up to [ 14] logic PT(s) +12| DSACK_1_| IO| | S | 2 |=> can support up to [ 19] logic PT(s) +13| DSACK_0_|OUT| | S | 1 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 14] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > Node-Pin Assignments @@ -1632,21 +1809,21 @@ _|_________________|__|__|___|_____|_______________________________________ | Sig Type---+ | to | Block [ 7] IO Pin | Device Pin | Signal Name | | pin | Numbers | Numbers _|_________________|__|_____|____________________|________________________ - 0| FPU_CS| IO| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85 - 1| cpu_est_0_|NOD| | => | 5 6 7 0 | 80 79 78 85 - 2|inst_CLK_000_D3|NOD| | => | 6 7 0 1 | 79 78 85 84 + 0| SIZE_1_| IO| | => | 5 ( 6) 7 0 | 80 ( 79) 78 85 + 1| FPU_CS| IO| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85 + 2| | | | => | 6 7 0 1 | 79 78 85 84 3| | | | => | 6 7 0 1 | 79 78 85 84 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) - 5| SM_AMIGA_6_|NOD| | => | 7 0 1 2 | 78 85 84 83 - 6|inst_CLK_000_D6|NOD| | => | 0 1 2 3 | 85 84 83 82 + 5|inst_CLK_000_D6|NOD| | => | 7 0 1 2 | 78 85 84 83 + 6| | | | => | 0 1 2 3 | 85 84 83 82 7| | | | => | 0 1 2 3 | 85 84 83 82 - 8| DSACK_1_| IO| | => | 1 2 3 ( 4)| 84 83 82 ( 81) - 9|inst_AS_030_000_SYNC|NOD| | => | 1 2 3 4 | 84 83 82 81 -10|inst_CLK_000_D4|NOD| | => | 2 3 4 5 | 83 82 81 80 + 8| AS_030| IO| | => | 1 2 ( 3) 4 | 84 83 ( 82) 81 + 9| | | | => | 1 2 3 4 | 84 83 82 81 +10| | | | => | 2 3 4 5 | 83 82 81 80 11| | | | => | 2 3 4 5 | 83 82 81 80 -12| DSACK_0_|OUT| | => | 3 4 ( 5) 6 | 82 81 ( 80) 79 -13| SM_AMIGA_1_|NOD| | => | 3 4 5 6 | 82 81 80 79 -14| CLK_CNT_P_1_|NOD| | => | 4 5 6 7 | 81 80 79 78 +12| DSACK_1_| IO| | => | 3 ( 4) 5 6 | 82 ( 81) 80 79 +13| DSACK_0_|OUT| | => | 3 4 ( 5) 6 | 82 81 ( 80) 79 +14| | | | => | 4 5 6 7 | 81 80 79 78 15| | | | => | 4 5 6 7 | 81 80 79 78 --------------------------------------------------------------------------- =========================================================================== @@ -1661,11 +1838,11 @@ _|_________________|__|___|_____|___________________________________________ 0| A_22_|INP|*| 85| => | 0 1 2 3 4 5 6 7 1| A_23_|INP|*| 84| => | 2 3 4 5 6 7 8 9 2| BGACK_030| IO|*| 83| => | ( 4) 5 6 7 8 9 10 11 - 3| AS_030|INP|*| 82| => | 6 7 8 9 10 11 12 13 - 4| DSACK_1_| IO|*| 81| => | ( 8) 9 10 11 12 13 14 15 - 5| DSACK_0_|OUT|*| 80| => | 10 11 (12) 13 14 15 0 1 - 6| SIZE_1_|INP|*| 79| => | 12 13 14 15 0 1 2 3 - 7| FPU_CS| IO|*| 78| => | 14 15 ( 0) 1 2 3 4 5 + 3| AS_030| IO|*| 82| => | 6 7 ( 8) 9 10 11 12 13 + 4| DSACK_1_| IO|*| 81| => | 8 9 10 11 (12) 13 14 15 + 5| DSACK_0_|OUT|*| 80| => | 10 11 12 (13) 14 15 0 1 + 6| SIZE_1_| IO|*| 79| => | 12 13 14 15 ( 0) 1 2 3 + 7| FPU_CS| IO|*| 78| => | 14 15 0 ( 1) 2 3 4 5 --------------------------------------------------------------------------- =========================================================================== < Block [ 7] > IO/Node and IO/Input Macrocell Pairing Table @@ -1680,11 +1857,13 @@ _|_________________|__|___|_____|__________________________________________ 1| A_23_|INP|*| 84| => | Input macrocell [ -] 2| BGACK_030| IO|*| 83| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_BGACK_030] - 3| AS_030|INP|*| 82| => | Input macrocell [ -] + 3| AS_030| IO|*| 82| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_AS_030] 4| DSACK_1_| IO|*| 81| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_DSACK_1_] 5| DSACK_0_|OUT|*| 80| => | Input macrocell [ -] - 6| SIZE_1_|INP|*| 79| => | Input macrocell [ -] + 6| SIZE_1_| IO|*| 79| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_SIZE_1_] 7| FPU_CS| IO|*| 78| => | Input macrocell [ -] | | | | | | IO paired w/ node [ RN_FPU_CS] --------------------------------------------------------------------------- @@ -1699,42 +1878,42 @@ IMX No. | +---- Block IO Pin or Macrocell Number ---|-------|----|---|---|----------|------|-|------------------------------ 0 [IOpin 0 | 85|INP A_22_|*|*] [RegIn 0 |270| -| | ] - [MCell 0 |269|NOD RN_FPU_CS| |*] paired w/[ FPU_CS] - [MCell 1 |271|NOD cpu_est_0_| |*] + [MCell 0 |269|NOD RN_SIZE_1_| |*] paired w/[ SIZE_1_] + [MCell 1 |271|NOD RN_FPU_CS| |*] paired w/[ FPU_CS] 1 [IOpin 1 | 84|INP A_23_|*|*] [RegIn 1 |273| -| | ] - [MCell 2 |272|NOD inst_CLK_000_D3| |*] + [MCell 2 |272| -| | ] [MCell 3 |274| -| | ] 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] [RegIn 2 |276| -| | ] [MCell 4 |275|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] - [MCell 5 |277|NOD SM_AMIGA_6_| |*] + [MCell 5 |277|NOD inst_CLK_000_D6| |*] - 3 [IOpin 3 | 82|INP AS_030|*|*] + 3 [IOpin 3 | 82| IO AS_030|*|*] paired w/[ RN_AS_030] [RegIn 3 |279| -| | ] - [MCell 6 |278|NOD inst_CLK_000_D6| |*] + [MCell 6 |278| -| | ] [MCell 7 |280| -| | ] 4 [IOpin 4 | 81| IO DSACK_1_|*|*] paired w/[ RN_DSACK_1_] [RegIn 4 |282| -| | ] - [MCell 8 |281|NOD RN_DSACK_1_| |*] paired w/[ DSACK_1_] - [MCell 9 |283|NOD inst_AS_030_000_SYNC| |*] + [MCell 8 |281|NOD RN_AS_030| |*] paired w/[ AS_030] + [MCell 9 |283| -| | ] 5 [IOpin 5 | 80|OUT DSACK_0_|*| ] [RegIn 5 |285| -| | ] - [MCell 10 |284|NOD inst_CLK_000_D4| |*] + [MCell 10 |284| -| | ] [MCell 11 |286| -| | ] - 6 [IOpin 6 | 79|INP SIZE_1_|*|*] + 6 [IOpin 6 | 79| IO SIZE_1_|*|*] paired w/[ RN_SIZE_1_] [RegIn 6 |288| -| | ] - [MCell 12 |287|OUT DSACK_0_| | ] - [MCell 13 |289|NOD SM_AMIGA_1_| |*] + [MCell 12 |287|NOD RN_DSACK_1_| |*] paired w/[ DSACK_1_] + [MCell 13 |289|OUT DSACK_0_| | ] 7 [IOpin 7 | 78| IO FPU_CS|*| ] paired w/[ RN_FPU_CS] [RegIn 7 |291| -| | ] - [MCell 14 |290|NOD CLK_CNT_P_1_| |*] + [MCell 14 |290| -| | ] [MCell 15 |292| -| | ] --------------------------------------------------------------------------- =========================================================================== @@ -1743,37 +1922,37 @@ IMX No. | +---- Block IO Pin or Macrocell Number +- Central Switch Matrix No. | Src (ABEL Node/Pin#) Signal --|--|--------------------|--------------------------------------------------- -Mux00| Input Pin ( 86)| RST +Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 Mux01| IOPin 5 2 ( 58)| FC_1_ Mux02| ... | ... -Mux03| Mcel 7 8 ( 281)| RN_DSACK_1_ -Mux04| IOPin 0 4 ( 95)| A_18_ -Mux05| Mcel 7 9 ( 283)| inst_AS_030_000_SYNC -Mux06| IOPin 0 6 ( 97)| A_19_ -Mux07| Mcel 7 13 ( 289)| SM_AMIGA_1_ -Mux08| IOPin 5 1 ( 59)| A_17_ -Mux09| Mcel 3 3 ( 178)| inst_CLK_000_D2 -Mux10| Mcel 6 8 ( 257)| SM_AMIGA_7_ +Mux03| Mcel 7 8 ( 281)| RN_AS_030 +Mux04| Mcel 7 5 ( 277)| inst_CLK_000_D6 +Mux05| Input Pin ( 14)| nEXP_SPACE +Mux06| IOPin 5 3 ( 57)| FC_0_ +Mux07| ... | ... +Mux08| IOPin 3 3 ( 32)| UDS_000 +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 7 1 ( 271)| RN_FPU_CS Mux11| IOPin 0 5 ( 96)| A_16_ -Mux12| Mcel 7 1 ( 271)| cpu_est_0_ -Mux13| Mcel 7 5 ( 277)| SM_AMIGA_6_ -Mux14| Mcel 7 2 ( 272)| inst_CLK_000_D3 -Mux15| Input Pin ( 14)| nEXP_SPACE -Mux16| Mcel 3 2 ( 176)| inst_CLK_000_D0 -Mux17| IOPin 5 3 ( 57)| FC_0_ +Mux12| IOPin 0 6 ( 97)| A_19_ +Mux13| IOPin 5 1 ( 59)| A_17_ +Mux14| Mcel 5 4 ( 227)| inst_BGACK_030_INT_D +Mux15| Mcel 7 12 ( 287)| RN_DSACK_1_ +Mux16| Mcel 4 8 ( 209)| inst_CLK_000_D0 +Mux17| IOPin 0 4 ( 95)| A_18_ Mux18| IOPin 3 7 ( 28)| BGACK_000 -Mux19| IOPin 7 3 ( 82)| AS_030 +Mux19| ... | ... Mux20| Input Pin ( 64)| CLK_030 -Mux21| Mcel 7 6 ( 278)| inst_CLK_000_D6 -Mux22| Mcel 6 5 ( 253)| CLK_CNT_P_0_ -Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 -Mux24| ... | ... -Mux25| Mcel 3 9 ( 187)| inst_CLK_000_D1 -Mux26| ... | ... -Mux27| Mcel 6 9 ( 259)| inst_CLK_000_D5 -Mux28| Mcel 1 5 ( 133)| SM_AMIGA_2_ -Mux29| ... | ... -Mux30| Mcel 7 0 ( 269)| RN_FPU_CS +Mux21| Input Pin ( 86)| RST +Mux22| ... | ... +Mux23| Mcel 7 0 ( 269)| RN_SIZE_1_ +Mux24| IOPin 3 4 ( 31)| LDS_000 +Mux25| Mcel 5 0 ( 221)| inst_CLK_000_D1 +Mux26| IOPin 3 2 ( 33)| AS_000 +Mux27| ... | ... +Mux28| Mcel 1 5 ( 133)| SM_AMIGA_1_ +Mux29| Mcel 4 1 ( 199)| inst_CLK_000_D5 +Mux30| ... | ... Mux31| ... | ... Mux32| ... | ... --------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt index c188309..bbe8ecd 100644 --- a/Logic/68030_tk.rpt +++ b/Logic/68030_tk.rpt @@ -12,7 +12,7 @@ Project_Summary Project Name : 68030_tk Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic -Project Fitted on : Sat May 24 19:56:24 2014 +Project Fitted on : Sat May 24 21:59:18 2014 Device : M4A5-128/64 Package : 100TQFP @@ -37,11 +37,11 @@ Fitter 00:00:00 Design_Summary ~~~~~~~~~~~~~~ - Total Input Pins : 35 - Total Output Pins : 22 - Total Bidir I/O Pins : 2 - Total Flip-Flops : 44 - Total Product Terms : 114 + Total Input Pins : 30 + Total Output Pins : 19 + Total Bidir I/O Pins : 10 + Total Flip-Flops : 48 + Total Product Terms : 134 Total Reserved Pins : 0 Total Reserved Blocks : 0 @@ -54,13 +54,13 @@ Dedicated Pins Input-Only Pins 2 2 0 --> 100% Clock/Input Pins 4 4 0 --> 100% I/O Pins 64 53 11 --> 82% -Logic Macrocells 128 51 77 --> 39% +Logic Macrocells 128 56 72 --> 43% Input Registers 64 0 64 --> 0% Unusable Macrocells .. 0 .. -CSM Outputs/Total Block Inputs 264 122 142 --> 46% -Logical Product Terms 640 117 523 --> 18% -Product Term Clusters 128 32 96 --> 25% +CSM Outputs/Total Block Inputs 264 169 95 --> 64% +Logical Product Terms 640 137 503 --> 21% +Product Term Clusters 128 39 89 --> 30%  Blocks_Resource_Summary @@ -71,14 +71,14 @@ Blocks_Resource_Summary --------------------------------------------------------------------------------- Maximum 33 8 8 -- -- 16 80 16 - --------------------------------------------------------------------------------- -Block A 0 7 0 1 0 15 1 16 Hi -Block B 24 8 0 12 0 4 25 8 Hi -Block C 1 8 0 2 0 14 2 16 Hi -Block D 30 8 0 13 0 3 37 6 Hi -Block E 14 3 0 3 0 13 3 16 Hi -Block F 0 4 0 0 0 16 0 16 Hi -Block G 26 7 0 8 0 8 23 10 Hi -Block H 27 8 0 12 0 4 26 8 Hi +Block A 18 7 0 7 0 9 15 12 Hi +Block B 17 8 0 7 0 9 17 11 Hi +Block C 17 8 0 7 0 9 15 11 Hi +Block D 30 8 0 7 0 9 28 8 Hi +Block E 20 3 0 7 0 9 8 15 Hi +Block F 23 4 0 7 0 9 21 11 Hi +Block G 19 7 0 7 0 9 19 10 Hi +Block H 25 8 0 7 0 9 14 11 Hi --------------------------------------------------------------------------------- Four rightmost columns above reflect last status of the placement process. @@ -142,7 +142,7 @@ Block Reservation : No @Import_Source_Constraint_Option No -@Zero_Hold_Time Yes +@Zero_Hold_Time No @Pull_up Yes @@ -180,7 +180,7 @@ Pin No| Type |Pad |Pin | Signal name 11 | CkIn | | * |CLK_000 12 | Vcc | | | 13 | GND | | | -14 | CkIn | | |nEXP_SPACE +14 | CkIn | | * |nEXP_SPACE 15 | I_O | C0 | * |A_28_ 16 | I_O | C1 | * |A_27_ 17 | I_O | C2 | * |A_26_ @@ -235,7 +235,7 @@ Pin No| Type |Pad |Pin | Signal name 66 | I_O | G1 | * |E 67 | I_O | G2 | * |IPL_0_ 68 | I_O | G3 | * |IPL_2_ -69 | I_O | G4 | * |A_0_ +69 | I_O | G4 | * |A0 70 | I_O | G5 | * |SIZE_0_ 71 | I_O | G6 | * |RW 72 | I_O | G7 | | @@ -287,12 +287,10 @@ Input_Signal_List Pin r e O Input Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 82 H . I/O -B-D---H Hi Fast AS_030 - 69 G . I/O ---D---- Hi Fast A_0_ - 96 A . I/O -------H Hi Fast A_16_ - 59 F . I/O -------H Hi Fast A_17_ - 95 A . I/O -------H Hi Fast A_18_ - 97 A . I/O -------H Hi Fast A_19_ + 96 A . I/O -----F-H Hi Fast A_16_ + 59 F . I/O -----F-H Hi Fast A_17_ + 95 A . I/O -----F-H Hi Fast A_18_ + 97 A . I/O -----F-H Hi Fast A_19_ 93 A . I/O ----E--- Hi Fast A_20_ 94 A . I/O ----E--- Hi Fast A_21_ 85 H . I/O ----E--- Hi Fast A_22_ @@ -305,23 +303,20 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 6 B . I/O ----E--- Hi Fast A_29_ 5 B . I/O ----E--- Hi Fast A_30_ 4 B . I/O ----E--- Hi Fast A_31_ - 28 D . I/O -------H Hi Fast BGACK_000 + 28 D . I/O -----F-H Hi Fast BGACK_000 21 C . I/O ---D---- Hi Fast BG_030 - 98 A . I/O ---D---- Hi Fast DS_030 - 57 F . I/O -------H Hi Fast FC_0_ - 58 F . I/O -------H Hi Fast FC_1_ + 57 F . I/O -----F-H Hi Fast FC_0_ + 58 F . I/O -----F-H Hi Fast FC_1_ 67 G . I/O -B------ Hi Fast IPL_0_ 56 F . I/O -B------ Hi Fast IPL_1_ 68 G . I/O -B------ Hi Fast IPL_2_ - 71 G . I/O ---DE--- Hi Fast RW - 70 G . I/O ---D---- Hi Fast SIZE_0_ - 79 H . I/O ---D---- Hi Fast SIZE_1_ - 11 . . Ck/I ---D---- - Fast CLK_000 - 14 . . Ck/I ---D--GH - Fast nEXP_SPACE - 36 . . Ded -B------ - Fast VPA - 61 . . Ck/I -B-D--GH - Fast CLK_OSZI - 64 . . Ck/I -------H - Fast CLK_030 - 86 . . Ded -B-D--GH - Fast RST + 71 G . I/O A--DE--- Hi Fast RW + 11 . . Ck/I ---DE--- - Fast CLK_000 + 14 . . Ck/I A--D-FGH - Fast nEXP_SPACE + 36 . . Ded --CD---- - Fast VPA + 61 . . Ck/I ABCDEFGH - Fast CLK_OSZI + 64 . . Ck/I A----FGH - Fast CLK_030 + 86 . . Ded ABCDEFGH - Fast RST ---------------------------------------------------------------------- Power : Hi = High @@ -337,10 +332,9 @@ Output_Signal_List Pin r e O Output Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - 48 E 1 COM -------- Hi Fast AMIGA_BUS_DATA_DIR - 34 D 3 DFF * * -------- Hi Fast AMIGA_BUS_ENABLE + 48 E 2 COM -------- Hi Fast AMIGA_BUS_DATA_DIR + 34 D 7 DFF * * -------- Hi Fast AMIGA_BUS_ENABLE 20 C 1 COM -------- Hi Fast AMIGA_BUS_ENABLE_LOW - 33 D 2 DFF * * -------- Hi Fast AS_000 92 A 1 COM -------- Hi Fast AVEC 22 C 1 COM -------- Hi Fast AVEC_EXP 41 E 1 COM -------- Hi Fast BERR @@ -355,9 +349,7 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal 8 B 3 DFF * * -------- Hi Fast IPL_030_0_ 7 B 3 DFF * * -------- Hi Fast IPL_030_1_ 9 B 3 DFF * * -------- Hi Fast IPL_030_2_ - 31 D 8 DFF * * -------- Hi Fast LDS_000 3 B 1 DFF * * -------- Hi Fast RESET - 32 D 5 DFF * * -------- Hi Fast UDS_000 35 D 2 DFF * * -------- Hi Fast VMA ---------------------------------------------------------------------- @@ -374,8 +366,16 @@ Bidir_Signal_List Pin r e O Bidir Pin Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- + 69 G 2 DFF * * ---D---- Hi Fast A0 + 33 D 2 DFF * * A-----GH Hi Fast AS_000 + 82 H 3 DFF * * --CD-F-H Hi Fast AS_030 81 H 2 DFF * * ---D---- Hi Fast DSACK_1_ - 30 D 1 DFF * * -B------ Hi Fast DTACK + 98 A 5 DFF * * ---D---- Hi Fast DS_030 + 30 D 1 COM --C----- Hi Fast DTACK + 31 D 8 DFF * * A-----GH Hi Fast LDS_000 + 70 G 2 DFF * * ---D---- Hi Fast SIZE_0_ + 79 H 3 DFF * * ---D---- Hi Fast SIZE_1_ + 32 D 5 DFF * * A-----GH Hi Fast UDS_000 ---------------------------------------------------------------------- Power : Hi = High @@ -391,46 +391,51 @@ Buried_Signal_List Pin r e O Node #Mc Blk PTs Type e s E Fanout Pwr Slew Signal ---------------------------------------------------------------------- - B9 B 2 DFF * * -B----G- Hi Fast CLK_CNT_N_0_ - B13 B 1 DFF * * -B----G- Hi Fast CLK_CNT_N_1_ - G5 G 2 DFF * * ------GH Hi Fast CLK_CNT_P_0_ - H14 H 1 DFF * * ------G- Hi Fast CLK_CNT_P_1_ - D4 D 3 DFF * * ---D---- Hi - RN_AMIGA_BUS_ENABLE --> AMIGA_BUS_ENABLE - D5 D 2 DFF * * ---D--G- Hi - RN_AS_000 --> AS_000 - H4 H 2 DFF * * ---D---H Hi - RN_BGACK_030 --> BGACK_030 + C1 C 2 DFF * * A-C----- Hi Fast CLK_CNT_N_0_ + A9 A 1 DFF * * --C----- Hi Fast CLK_CNT_N_1_ + G5 G 2 DFF * * --C-E-G- Hi Fast CLK_CNT_P_0_ + E5 E 1 DFF * * --C---G- Hi Fast CLK_CNT_P_1_ + G8 G 2 DFF * * ------G- Hi - RN_A0 --> A0 + D5 D 7 DFF * * ---D---- Hi - RN_AMIGA_BUS_ENABLE --> AMIGA_BUS_ENABLE + D4 D 2 DFF * * ---D-F-- Hi - RN_AS_000 --> AS_000 + H8 H 3 DFF * * A------H Hi - RN_AS_030 --> AS_030 + H4 H 2 DFF * * A--DEFGH Hi - RN_BGACK_030 --> BGACK_030 D13 D 2 DFF * * ---D---- Hi - RN_BG_000 --> BG_000 - H8 H 2 DFF * * -------H Hi - RN_DSACK_1_ --> DSACK_1_ - G4 G 3 DFF * * -B-D--G- Hi - RN_E --> E - H0 H 2 DFF * * --C-E--H Hi - RN_FPU_CS --> FPU_CS + H12 H 2 DFF * * -------H Hi - RN_DSACK_1_ --> DSACK_1_ + A0 A 5 DFF * * A------- Hi - RN_DS_030 --> DS_030 + G4 G 3 DFF * * --CD--G- Hi - RN_E --> E + H1 H 2 DFF * * --C-E--H Hi - RN_FPU_CS --> FPU_CS B8 B 3 DFF * * -B------ Hi - RN_IPL_030_0_ --> IPL_030_0_ B12 B 3 DFF * * -B------ Hi - RN_IPL_030_1_ --> IPL_030_1_ B4 B 3 DFF * * -B------ Hi - RN_IPL_030_2_ --> IPL_030_2_ D8 D 8 DFF * * ---D---- Hi - RN_LDS_000 --> LDS_000 + G0 G 2 DFF * * ------G- Hi - RN_SIZE_0_ --> SIZE_0_ + H0 H 3 DFF * * -------H Hi - RN_SIZE_1_ --> SIZE_1_ D12 D 5 DFF * * ---D---- Hi - RN_UDS_000 --> UDS_000 - D1 D 2 DFF * * -B-D---- Hi - RN_VMA --> VMA - G13 G 4 DFF * * ------G- Hi Fast SM_AMIGA_0_ - H13 H 3 DFF * * ------GH Hi Fast SM_AMIGA_1_ - B5 B 3 DFF * * -B-----H Hi Fast SM_AMIGA_2_ - B6 B 3 DFF * * -B------ Hi Fast SM_AMIGA_3_ - G12 G 2 DFF * * -B-D--G- Hi Fast SM_AMIGA_4_ - D14 D 2 DFF * * ---D--G- Hi Fast SM_AMIGA_5_ - H5 H 2 DFF * * ---D--GH Hi Fast SM_AMIGA_6_ - G8 G 5 DFF * * ---D--GH Hi Fast SM_AMIGA_7_ - H1 H 3 DFF * * ---D--GH Hi Fast cpu_est_0_ - D6 D 4 TFF * * -B-D--G- Hi Fast cpu_est_1_ - D10 D 3 DFF * * ---D--G- Hi Fast cpu_est_2_ - H9 H 7 DFF * * ------GH Hi Fast inst_AS_030_000_SYNC - D2 D 1 DFF * * -B-D--GH Hi Fast inst_CLK_000_D0 - D9 D 1 DFF * * -B-D--GH Hi Fast inst_CLK_000_D1 - D3 D 1 DFF * * ------GH Hi Fast inst_CLK_000_D2 - H2 H 1 DFF * * ------GH Hi Fast inst_CLK_000_D3 - H10 H 1 DFF * * ------G- Hi Fast inst_CLK_000_D4 - G9 G 1 DFF * * ------GH Hi Fast inst_CLK_000_D5 - H6 H 1 DFF * * ------GH Hi Fast inst_CLK_000_D6 - G1 G 4 DFF * * -B----G- Hi Fast inst_CLK_OUT_PRE - B14 B 2 DFF * * -B------ Hi Fast inst_DTACK_SYNC - B2 B 1 DFF * * -B-D---- Hi Fast inst_VPA_D - B10 B 2 DFF * * -B------ Hi Fast inst_VPA_SYNC + D1 D 2 DFF * * --CD---- Hi - RN_VMA --> VMA + F1 F 4 DFF * * ---D-F-- Hi Fast SM_AMIGA_0_ + B5 B 3 DFF * * -B---F-H Hi Fast SM_AMIGA_1_ + B9 B 3 DFF * * -B------ Hi Fast SM_AMIGA_2_ + C8 C 3 DFF * * -BC----- Hi Fast SM_AMIGA_3_ + A12 A 2 DFF * * A-CD---- Hi Fast SM_AMIGA_4_ + A1 A 2 DFF * * A--D---- Hi Fast SM_AMIGA_5_ + F8 F 2 DFF * * A--D-F-- Hi Fast SM_AMIGA_6_ + F12 F 5 DFF * * ---D-F-- Hi Fast SM_AMIGA_7_ + A8 A 3 DFF * * A--D--G- Hi Fast cpu_est_0_ + G12 G 4 TFF * * --CD--G- Hi Fast cpu_est_1_ + G9 G 3 DFF * * ---D--G- Hi Fast cpu_est_2_ + F5 F 7 DFF * * -----F-- Hi Fast inst_AS_030_000_SYNC + F4 F 1 DFF * * A--D--GH Hi Fast inst_BGACK_030_INT_D + E8 E 1 DFF * * ABCD-FGH Hi Fast inst_CLK_000_D0 + F0 F 1 DFF * * AB----GH Hi Fast inst_CLK_000_D1 + A5 A 1 DFF * * ----EF-- Hi Fast inst_CLK_000_D2 + E9 E 1 DFF * * -----F-- Hi Fast inst_CLK_000_D3 + F9 F 1 DFF * * ----E--- Hi Fast inst_CLK_000_D4 + E1 E 1 DFF * * -B---F-H Hi Fast inst_CLK_000_D5 + H5 H 1 DFF * * -B---F-H Hi Fast inst_CLK_000_D6 + C4 C 4 DFF * * -B----G- Hi Fast inst_CLK_OUT_PRE + C9 C 2 DFF * * -BC----- Hi Fast inst_DTACK_SYNC + C5 C 2 DFF * * -BC----- Hi Fast inst_VPA_SYNC ---------------------------------------------------------------------- Power : Hi = High @@ -445,123 +450,142 @@ Signals_Fanout_List ~~~~~~~~~~~~~~~~~~~ Signal Source : Fanout List ----------------------------------------------------------------------------- - SIZE_1_{ I}: LDS_000{ D} + IPL_1_{ G}: IPL_030_1_{ B} + IPL_0_{ H}: IPL_030_0_{ B} A_31_{ C}: CIIN{ E} + FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ F} IPL_2_{ H}: IPL_030_2_{ B} - FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - AS_030{ I}: DSACK_1_{ H} AS_000{ D} UDS_000{ D} - : LDS_000{ D} BG_000{ D} FPU_CS{ H} - :AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ B} - : inst_VPA_SYNC{ B} - SIZE_0_{ H}: LDS_000{ D} - DS_030{ B}: UDS_000{ D} LDS_000{ D} + FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ F} + nEXP_SPACE{. }: DTACK{ D} SIZE_1_{ H} DSACK_1_{ H} + : AS_030{ H} DS_030{ A} A0{ G} + : BG_000{ D}AMIGA_BUS_ENABLE{ D} SIZE_0_{ G} + :inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} SM_AMIGA_7_{ F} + BG_030{ D}: BG_000{ D} + BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ F} + CLK_030{. }: SIZE_1_{ H} AS_030{ H} DS_030{ A} + : A0{ G} FPU_CS{ H} SIZE_0_{ G} + :inst_AS_030_000_SYNC{ F} + CLK_000{. }: BG_000{ D}inst_CLK_000_D0{ E} + DTACK{ E}:inst_DTACK_SYNC{ C} + VPA{. }: VMA{ D}inst_DTACK_SYNC{ C} inst_VPA_SYNC{ C} + RST{. }: CLK_DIV_OUT{ G} IPL_030_1_{ B} IPL_030_0_{ B} + : SIZE_1_{ H} IPL_030_2_{ B} DSACK_1_{ H} + : AS_030{ H} AS_000{ D} DS_030{ A} + : UDS_000{ D} LDS_000{ D} A0{ G} + : BG_000{ D} BGACK_030{ H} CLK_EXP{ B} + : FPU_CS{ H} E{ G} VMA{ D} + : RESET{ B}AMIGA_BUS_ENABLE{ D} SIZE_0_{ G} + :inst_AS_030_000_SYNC{ F}inst_BGACK_030_INT_D{ F}inst_DTACK_SYNC{ C} + : inst_VPA_SYNC{ C}inst_CLK_000_D0{ E}inst_CLK_000_D1{ F} + :inst_CLK_000_D2{ A}inst_CLK_000_D6{ H} SM_AMIGA_5_{ A} + : SM_AMIGA_6_{ F}inst_CLK_000_D3{ E}inst_CLK_000_D5{ E} + : SM_AMIGA_3_{ C} SM_AMIGA_0_{ F} SM_AMIGA_1_{ B} + : CLK_CNT_N_0_{ C} CLK_CNT_N_1_{ A} CLK_CNT_P_0_{ G} + : CLK_CNT_P_1_{ E}inst_CLK_000_D4{ F} SM_AMIGA_7_{ F} + : SM_AMIGA_4_{ A}inst_CLK_OUT_PRE{ C} SM_AMIGA_2_{ B} + : cpu_est_0_{ A} cpu_est_1_{ G} cpu_est_2_{ G} + RW{ H}:AMIGA_BUS_DATA_DIR{ E} DS_030{ A} UDS_000{ D} + : LDS_000{ D} A_30_{ C}: CIIN{ E} A_29_{ C}: CIIN{ E} A_28_{ D}: CIIN{ E} - nEXP_SPACE{. }: DSACK_0_{ H} DSACK_1_{ H} BG_000{ D} - : DTACK{ D}AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} - : SM_AMIGA_6_{ H} SM_AMIGA_7_{ G} A_27_{ D}: CIIN{ E} A_26_{ D}: CIIN{ E} - BG_030{ D}: BG_000{ D} A_25_{ D}: CIIN{ E} A_24_{ D}: CIIN{ E} A_23_{ I}: CIIN{ E} - BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_22_{ I}: CIIN{ E} - CLK_030{. }: FPU_CS{ H}inst_AS_030_000_SYNC{ H} A_21_{ B}: CIIN{ E} - CLK_000{. }: BG_000{ D}inst_CLK_000_D0{ D} A_20_{ B}: CIIN{ E} - A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} - VPA{. }: inst_VPA_D{ B} - RST{. }: CLK_DIV_OUT{ G} IPL_030_2_{ B} DSACK_1_{ H} - : AS_000{ D} UDS_000{ D} LDS_000{ D} - : BG_000{ D} BGACK_030{ H} CLK_EXP{ B} - : FPU_CS{ H} DTACK{ D} E{ G} - : VMA{ D} RESET{ B}AMIGA_BUS_ENABLE{ D} - : IPL_030_1_{ B} IPL_030_0_{ B}inst_AS_030_000_SYNC{ H} - :inst_DTACK_SYNC{ B} inst_VPA_D{ B} inst_VPA_SYNC{ B} - :inst_CLK_000_D0{ D}inst_CLK_000_D1{ D}inst_CLK_000_D2{ D} - :inst_CLK_000_D6{ H} SM_AMIGA_5_{ D} SM_AMIGA_6_{ H} - :inst_CLK_000_D3{ H} SM_AMIGA_4_{ G}inst_CLK_000_D5{ G} - : SM_AMIGA_7_{ G} SM_AMIGA_3_{ B} SM_AMIGA_1_{ H} - : CLK_CNT_N_0_{ B} CLK_CNT_N_1_{ B} CLK_CNT_P_0_{ G} - : CLK_CNT_P_1_{ H} SM_AMIGA_2_{ B} SM_AMIGA_0_{ G} - :inst_CLK_000_D4{ H}inst_CLK_OUT_PRE{ G} cpu_est_0_{ H} - : cpu_est_1_{ D} cpu_est_2_{ D} - RW{ H}:AMIGA_BUS_DATA_DIR{ E} UDS_000{ D} LDS_000{ D} - A_0_{ H}: UDS_000{ D} LDS_000{ D} - IPL_1_{ G}: IPL_030_1_{ B} - IPL_0_{ H}: IPL_030_0_{ B} - FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ F} + A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ F} + A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ F} + A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ F} +RN_IPL_030_1_{ C}: IPL_030_1_{ B} +RN_IPL_030_0_{ C}: IPL_030_0_{ B} + SIZE_1_{ I}: LDS_000{ D} + RN_SIZE_1_{ I}: SIZE_1_{ H} RN_IPL_030_2_{ C}: IPL_030_2_{ B} DSACK_1_{ I}: DTACK{ D} RN_DSACK_1_{ I}: DSACK_1_{ H} - RN_AS_000{ E}: AS_000{ D} DTACK{ D} VMA{ D} - : SM_AMIGA_7_{ G} SM_AMIGA_0_{ G} + AS_030{ I}: DSACK_1_{ H} AS_000{ D} UDS_000{ D} + : LDS_000{ D} BG_000{ D} FPU_CS{ H} + :inst_AS_030_000_SYNC{ F}inst_DTACK_SYNC{ C} inst_VPA_SYNC{ C} + RN_AS_030{ I}: AS_030{ H} DS_030{ A} + AS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A} + : A0{ G} SIZE_0_{ G} + RN_AS_000{ E}: AS_000{ D} VMA{ D}AMIGA_BUS_ENABLE{ D} + : SM_AMIGA_0_{ F} SM_AMIGA_7_{ F} + DS_030{ B}: UDS_000{ D} LDS_000{ D} + RN_DS_030{ B}: DS_030{ A} + UDS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A} + : A0{ G} SIZE_0_{ G} RN_UDS_000{ E}: UDS_000{ D} + LDS_000{ E}: SIZE_1_{ H} AS_030{ H} DS_030{ A} + : A0{ G} SIZE_0_{ G} RN_LDS_000{ E}: LDS_000{ D} + A0{ H}: UDS_000{ D} LDS_000{ D} + RN_A0{ H}: A0{ G} RN_BG_000{ E}: BG_000{ D} -RN_BGACK_030{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D} - : BGACK_030{ H} DTACK{ D} +RN_BGACK_030{ I}: DTACK{ D}AMIGA_BUS_DATA_DIR{ E} SIZE_1_{ H} + : AS_030{ H} AS_000{ D} DS_030{ A} + : UDS_000{ D} LDS_000{ D} A0{ G} + : BGACK_030{ H}AMIGA_BUS_ENABLE{ D} SIZE_0_{ G} + :inst_BGACK_030_INT_D{ F} RN_FPU_CS{ I}: BERR{ E} AVEC_EXP{ C} FPU_CS{ H} - DTACK{ E}:inst_DTACK_SYNC{ B} - RN_E{ H}: E{ G} VMA{ D} inst_VPA_SYNC{ B} - : cpu_est_1_{ D} cpu_est_2_{ D} - RN_VMA{ E}: VMA{ D} inst_VPA_SYNC{ B} + RN_E{ H}: E{ G} VMA{ D} inst_VPA_SYNC{ C} + : cpu_est_1_{ G} cpu_est_2_{ G} + RN_VMA{ E}: VMA{ D} inst_VPA_SYNC{ C} RN_AMIGA_BUS_ENABLE{ E}:AMIGA_BUS_ENABLE{ D} -RN_IPL_030_1_{ C}: IPL_030_1_{ B} -RN_IPL_030_0_{ C}: IPL_030_0_{ B} -inst_AS_030_000_SYNC{ I}:inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H} SM_AMIGA_7_{ G} -inst_DTACK_SYNC{ C}:inst_DTACK_SYNC{ B} SM_AMIGA_3_{ B} SM_AMIGA_2_{ B} - inst_VPA_D{ C}: VMA{ D}inst_DTACK_SYNC{ B} inst_VPA_SYNC{ B} -inst_VPA_SYNC{ C}: inst_VPA_SYNC{ B} SM_AMIGA_3_{ B} SM_AMIGA_2_{ B} -inst_CLK_000_D0{ E}: IPL_030_2_{ B} BGACK_030{ H} E{ G} - : VMA{ D} IPL_030_1_{ B} IPL_030_0_{ B} - :inst_DTACK_SYNC{ B} inst_VPA_SYNC{ B}inst_CLK_000_D1{ D} - : SM_AMIGA_5_{ D} SM_AMIGA_6_{ H} SM_AMIGA_4_{ G} - : SM_AMIGA_7_{ G} SM_AMIGA_3_{ B} SM_AMIGA_1_{ H} - : SM_AMIGA_2_{ B} SM_AMIGA_0_{ G} cpu_est_0_{ H} - : cpu_est_1_{ D} cpu_est_2_{ D} -inst_CLK_000_D1{ E}: IPL_030_2_{ B} BGACK_030{ H} E{ G} - : IPL_030_1_{ B} IPL_030_0_{ B}inst_CLK_000_D2{ D} - : cpu_est_0_{ H} cpu_est_1_{ D} cpu_est_2_{ D} -inst_CLK_000_D2{ E}: SM_AMIGA_6_{ H}inst_CLK_000_D3{ H} SM_AMIGA_7_{ G} -inst_CLK_000_D6{ I}: DSACK_1_{ H}inst_AS_030_000_SYNC{ H} SM_AMIGA_1_{ H} - : SM_AMIGA_0_{ G} -SM_AMIGA_5_{ E}: AS_000{ D} UDS_000{ D} LDS_000{ D} - : SM_AMIGA_5_{ D} SM_AMIGA_4_{ G} -SM_AMIGA_6_{ I}:AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_5_{ D} - : SM_AMIGA_6_{ H} SM_AMIGA_7_{ G} -inst_CLK_000_D3{ I}: SM_AMIGA_6_{ H} SM_AMIGA_7_{ G}inst_CLK_000_D4{ H} -SM_AMIGA_4_{ H}: UDS_000{ D} LDS_000{ D} SM_AMIGA_4_{ G} - : SM_AMIGA_3_{ B} -inst_CLK_000_D5{ H}: DSACK_1_{ H}inst_AS_030_000_SYNC{ H}inst_CLK_000_D6{ H} - : SM_AMIGA_1_{ H} SM_AMIGA_0_{ G} -SM_AMIGA_7_{ H}: BG_000{ D}inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ H} - : SM_AMIGA_7_{ G} -SM_AMIGA_3_{ C}:inst_DTACK_SYNC{ B} inst_VPA_SYNC{ B} SM_AMIGA_3_{ B} + SIZE_0_{ H}: LDS_000{ D} + RN_SIZE_0_{ H}: SIZE_0_{ G} +inst_AS_030_000_SYNC{ G}:inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} SM_AMIGA_7_{ F} +inst_BGACK_030_INT_D{ G}: SIZE_1_{ H} AS_030{ H} DS_030{ A} + : A0{ G}AMIGA_BUS_ENABLE{ D} SIZE_0_{ G} +inst_DTACK_SYNC{ D}:inst_DTACK_SYNC{ C} SM_AMIGA_3_{ C} SM_AMIGA_2_{ B} +inst_VPA_SYNC{ D}: inst_VPA_SYNC{ C} SM_AMIGA_3_{ C} SM_AMIGA_2_{ B} +inst_CLK_000_D0{ F}: IPL_030_1_{ B} IPL_030_0_{ B} IPL_030_2_{ B} + : BGACK_030{ H} E{ G} VMA{ D} + :AMIGA_BUS_ENABLE{ D}inst_DTACK_SYNC{ C} inst_VPA_SYNC{ C} + :inst_CLK_000_D1{ F} SM_AMIGA_5_{ A} SM_AMIGA_6_{ F} + : SM_AMIGA_3_{ C} SM_AMIGA_0_{ F} SM_AMIGA_1_{ B} + : SM_AMIGA_7_{ F} SM_AMIGA_4_{ A} SM_AMIGA_2_{ B} + : cpu_est_0_{ A} cpu_est_1_{ G} cpu_est_2_{ G} +inst_CLK_000_D1{ G}: IPL_030_1_{ B} IPL_030_0_{ B} IPL_030_2_{ B} + : BGACK_030{ H} E{ G}inst_CLK_000_D2{ A} + : cpu_est_0_{ A} cpu_est_1_{ G} cpu_est_2_{ G} +inst_CLK_000_D2{ B}: SM_AMIGA_6_{ F}inst_CLK_000_D3{ E} SM_AMIGA_7_{ F} +inst_CLK_000_D6{ I}: DSACK_1_{ H}inst_AS_030_000_SYNC{ F} SM_AMIGA_0_{ F} + : SM_AMIGA_1_{ B} +SM_AMIGA_5_{ B}: AS_000{ D} UDS_000{ D} LDS_000{ D} + : SM_AMIGA_5_{ A} SM_AMIGA_4_{ A} +SM_AMIGA_6_{ G}:AMIGA_BUS_ENABLE{ D}inst_AS_030_000_SYNC{ F} SM_AMIGA_5_{ A} + : SM_AMIGA_6_{ F} SM_AMIGA_7_{ F} +inst_CLK_000_D3{ F}: SM_AMIGA_6_{ F}inst_CLK_000_D4{ F} SM_AMIGA_7_{ F} +inst_CLK_000_D5{ F}: DSACK_1_{ H}inst_AS_030_000_SYNC{ F}inst_CLK_000_D6{ H} + : SM_AMIGA_0_{ F} SM_AMIGA_1_{ B} +SM_AMIGA_3_{ D}:inst_DTACK_SYNC{ C} inst_VPA_SYNC{ C} SM_AMIGA_3_{ C} : SM_AMIGA_2_{ B} -SM_AMIGA_1_{ I}: DSACK_1_{ H}inst_AS_030_000_SYNC{ H} SM_AMIGA_1_{ H} - : SM_AMIGA_0_{ G} -CLK_CNT_N_0_{ C}: CLK_CNT_N_0_{ B} CLK_CNT_N_1_{ B}inst_CLK_OUT_PRE{ G} -CLK_CNT_N_1_{ C}: CLK_CNT_N_0_{ B}inst_CLK_OUT_PRE{ G} -CLK_CNT_P_0_{ H}: CLK_CNT_P_0_{ G} CLK_CNT_P_1_{ H}inst_CLK_OUT_PRE{ G} -CLK_CNT_P_1_{ I}: CLK_CNT_P_0_{ G}inst_CLK_OUT_PRE{ G} -SM_AMIGA_2_{ C}: SM_AMIGA_1_{ H} SM_AMIGA_2_{ B} -SM_AMIGA_0_{ H}: SM_AMIGA_7_{ G} SM_AMIGA_0_{ G} -inst_CLK_000_D4{ I}:inst_CLK_000_D5{ G} -inst_CLK_OUT_PRE{ H}: CLK_DIV_OUT{ G} CLK_EXP{ B} - cpu_est_0_{ I}: E{ G} VMA{ D} cpu_est_0_{ H} - : cpu_est_1_{ D} cpu_est_2_{ D} - cpu_est_1_{ E}: E{ G} VMA{ D} inst_VPA_SYNC{ B} - : cpu_est_1_{ D} cpu_est_2_{ D} - cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} - : cpu_est_2_{ D} +SM_AMIGA_0_{ G}:AMIGA_BUS_ENABLE{ D} SM_AMIGA_0_{ F} SM_AMIGA_7_{ F} +SM_AMIGA_1_{ C}: DSACK_1_{ H}inst_AS_030_000_SYNC{ F} SM_AMIGA_0_{ F} + : SM_AMIGA_1_{ B} +CLK_CNT_N_0_{ D}: CLK_CNT_N_0_{ C} CLK_CNT_N_1_{ A}inst_CLK_OUT_PRE{ C} +CLK_CNT_N_1_{ B}: CLK_CNT_N_0_{ C}inst_CLK_OUT_PRE{ C} +CLK_CNT_P_0_{ H}: CLK_CNT_P_0_{ G} CLK_CNT_P_1_{ E}inst_CLK_OUT_PRE{ C} +CLK_CNT_P_1_{ F}: CLK_CNT_P_0_{ G}inst_CLK_OUT_PRE{ C} +inst_CLK_000_D4{ G}:inst_CLK_000_D5{ E} +SM_AMIGA_7_{ G}: BG_000{ D}inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ F} + : SM_AMIGA_7_{ F} +SM_AMIGA_4_{ B}: UDS_000{ D} LDS_000{ D} SM_AMIGA_3_{ C} + : SM_AMIGA_4_{ A} +inst_CLK_OUT_PRE{ D}: CLK_DIV_OUT{ G} CLK_EXP{ B} +SM_AMIGA_2_{ C}: SM_AMIGA_1_{ B} SM_AMIGA_2_{ B} + cpu_est_0_{ B}: E{ G} VMA{ D} cpu_est_0_{ A} + : cpu_est_1_{ G} cpu_est_2_{ G} + cpu_est_1_{ H}: E{ G} VMA{ D} inst_VPA_SYNC{ C} + : cpu_est_1_{ G} cpu_est_2_{ G} + cpu_est_2_{ H}: E{ G} VMA{ D} cpu_est_1_{ G} + : cpu_est_2_{ G} ----------------------------------------------------------------------------- {.} : Indicates block location of signal @@ -571,14 +595,20 @@ Set_Reset_Summary ~~~~~~~~~~~~~~~~~ Block A -block level set pt : -block level reset pt : +block level set pt : !RST +block level reset pt : GND Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ +| * | S | BS | BR | DS_030 | | | | | AVEC -| | | | | DS_030 +| * | S | BR | BS | cpu_est_0_ +| * | S | BR | BS | SM_AMIGA_4_ +| * | S | BR | BS | SM_AMIGA_5_ +| * | S | BS | BR | inst_CLK_000_D2 +| * | S | BS | BR | RN_DS_030 +| * | S | BS | BR | CLK_CNT_N_1_ | | | | | A_19_ | | | | | A_16_ | | | | | A_18_ @@ -598,30 +628,30 @@ Equations : | * | S | BS | BR | IPL_030_1_ | * | S | BR | BS | CLK_EXP | * | S | BR | BS | RESET -| * | S | BR | BS | SM_AMIGA_2_ -| * | S | BR | BS | CLK_CNT_N_0_ -| * | S | BS | BR | CLK_CNT_N_1_ -| * | S | BS | BR | inst_VPA_D +| * | S | BR | BS | SM_AMIGA_1_ +| * | S | BS | BR | RN_IPL_030_2_ | * | S | BS | BR | RN_IPL_030_0_ | * | S | BS | BR | RN_IPL_030_1_ -| * | S | BS | BR | RN_IPL_030_2_ -| * | S | BR | BS | SM_AMIGA_3_ -| * | S | BS | BR | inst_VPA_SYNC -| * | S | BS | BR | inst_DTACK_SYNC +| * | S | BR | BS | SM_AMIGA_2_ | | | | | A_29_ | | | | | A_30_ | | | | | A_31_ Block C -block level set pt : -block level reset pt : +block level set pt : !RST +block level reset pt : GND Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ | | | | | AVEC_EXP | | | | | AMIGA_BUS_ENABLE_LOW +| * | S | BR | BS | inst_CLK_OUT_PRE +| * | S | BR | BS | SM_AMIGA_3_ +| * | S | BR | BS | CLK_CNT_N_0_ +| * | S | BS | BR | inst_VPA_SYNC +| * | S | BS | BR | inst_DTACK_SYNC | | | | | BG_030 | | | | | A_24_ | | | | | A_25_ @@ -637,31 +667,25 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| * | S | BS | BR | DTACK | * | S | BS | BR | LDS_000 | * | S | BS | BR | UDS_000 -| * | A | | | AMIGA_BUS_ENABLE -| * | S | BS | BR | VMA | * | S | BS | BR | AS_000 +| | | | | DTACK +| * | S | BS | BR | AMIGA_BUS_ENABLE +| * | S | BS | BR | VMA | * | S | BS | BR | BG_000 -| * | S | BS | BR | inst_CLK_000_D1 -| * | S | BS | BR | inst_CLK_000_D0 -| * | S | BR | BS | cpu_est_1_ -| * | S | BR | BS | cpu_est_2_ | * | S | BS | BR | RN_VMA | * | S | BS | BR | RN_AS_000 -| * | S | BR | BS | SM_AMIGA_5_ -| * | S | BS | BR | inst_CLK_000_D2 | * | S | BS | BR | RN_LDS_000 +| * | S | BS | BR | RN_AMIGA_BUS_ENABLE | * | S | BS | BR | RN_UDS_000 -| * | A | | | RN_AMIGA_BUS_ENABLE | * | S | BS | BR | RN_BG_000 | | | | | BGACK_000 Block E -block level set pt : -block level reset pt : +block level set pt : GND +block level reset pt : !RST Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name @@ -669,15 +693,26 @@ Equations : | | | | | AMIGA_BUS_DATA_DIR | | | | | CIIN | | | | | BERR +| * | S | BR | BS | inst_CLK_000_D0 +| * | S | BR | BS | inst_CLK_000_D5 +| * | S | BS | BR | CLK_CNT_P_1_ +| * | S | BR | BS | inst_CLK_000_D3 Block F -block level set pt : -block level reset pt : +block level set pt : !RST +block level reset pt : GND Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ +| * | S | BS | BR | inst_CLK_000_D1 +| * | S | BS | BR | inst_BGACK_030_INT_D +| * | S | BR | BS | SM_AMIGA_6_ +| * | S | BS | BR | SM_AMIGA_7_ +| * | S | BR | BS | SM_AMIGA_0_ +| * | S | BS | BR | inst_AS_030_000_SYNC +| * | S | BS | BR | inst_CLK_000_D4 | | | | | A_17_ | | | | | FC_1_ | | | | | FC_0_ @@ -685,24 +720,23 @@ Equations : Block G -block level set pt : GND -block level reset pt : !RST +block level set pt : !RST +block level reset pt : GND Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ -| * | S | BS | BR | E -| * | S | BS | BR | CLK_DIV_OUT -| * | S | BR | BS | SM_AMIGA_7_ -| * | S | BS | BR | RN_E -| * | S | BS | BR | SM_AMIGA_4_ -| * | S | BS | BR | inst_CLK_OUT_PRE -| * | S | BS | BR | CLK_CNT_P_0_ -| * | S | BR | BS | inst_CLK_000_D5 -| * | S | BS | BR | SM_AMIGA_0_ +| * | S | BS | BR | SIZE_0_ +| * | S | BS | BR | A0 +| * | S | BR | BS | E +| * | S | BR | BS | CLK_DIV_OUT +| * | S | BR | BS | cpu_est_1_ +| * | S | BR | BS | RN_E +| * | S | BR | BS | CLK_CNT_P_0_ +| * | S | BR | BS | cpu_est_2_ +| * | S | BS | BR | RN_SIZE_0_ +| * | S | BS | BR | RN_A0 | | | | | RW -| | | | | SIZE_0_ -| | | | | A_0_ | | | | | IPL_2_ | | | | | IPL_0_ @@ -714,25 +748,20 @@ Equations : | | |Block|Block| Signal | Reg |Mode |Set |Reset| Name +-----+-----+-----+-----+------------------------ +| * | S | BS | BR | AS_030 +| * | S | BS | BR | SIZE_1_ | * | S | BS | BR | DSACK_1_ | * | S | BS | BR | BGACK_030 | * | S | BS | BR | FPU_CS | | | | | DSACK_0_ -| * | S | BR | BS | cpu_est_0_ -| * | S | BS | BR | RN_FPU_CS -| * | S | BR | BS | SM_AMIGA_6_ -| * | S | BS | BR | inst_AS_030_000_SYNC -| * | S | BR | BS | SM_AMIGA_1_ | * | S | BS | BR | RN_BGACK_030 -| * | S | BS | BR | inst_CLK_000_D3 +| * | S | BS | BR | RN_FPU_CS | * | S | BS | BR | inst_CLK_000_D6 +| * | S | BS | BR | RN_AS_030 +| * | S | BS | BR | RN_SIZE_1_ | * | S | BS | BR | RN_DSACK_1_ -| * | S | BS | BR | inst_CLK_000_D4 -| * | S | BR | BS | CLK_CNT_P_1_ -| | | | | AS_030 | | | | | A_22_ | | | | | A_23_ -| | | | | SIZE_1_ (S) means the macrocell is configured in synchronous mode @@ -745,27 +774,51 @@ Equations : +BLOCK_A_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx A0 RST pin 86 mx A17 ... ... +mx A1 CLK_CNT_N_0_ mcell C1 mx A18 cpu_est_0_ mcell A8 +mx A2 SM_AMIGA_6_ mcell F8 mx A19 ... ... +mx A3 RN_AS_030 mcell H8 mx A20 RN_BGACK_030 mcell H4 +mx A4 CLK_030 pin 64 mx A21 ... ... +mx A5 nEXP_SPACE pin 14 mx A22 ... ... +mx A6 ... ... mx A23 AS_000 pin 33 +mx A7 ... ... mx A24 SM_AMIGA_4_ mcell A12 +mx A8 RW pin 71 mx A25 inst_CLK_000_D1 mcell F0 +mx A9 SM_AMIGA_5_ mcell A1 mx A26 ... ... +mx A10inst_BGACK_030_INT_D mcell F4 mx A27 LDS_000 pin 31 +mx A11 ... ... mx A28 ... ... +mx A12 UDS_000 pin 32 mx A29 ... ... +mx A13 ... ... mx A30 ... ... +mx A14 ... ... mx A31 ... ... +mx A15 RN_DS_030 mcell A0 mx A32 ... ... +mx A16 inst_CLK_000_D0 mcell E8 +---------------------------------------------------------------------------- + + BLOCK_B_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx B0 RST pin 86 mx B17 RN_VMA mcell D1 -mx B1 RN_IPL_030_1_ mcell B12 mx B18 inst_VPA_D mcell B2 -mx B2 RN_E mcell G4 mx B19 AS_030 pin 82 -mx B3 inst_CLK_000_D0 mcell D2 mx B20 inst_DTACK_SYNC mcell B14 -mx B4 cpu_est_1_ mcell D6 mx B21 IPL_1_ pin 56 -mx B5 ... ... mx B22 IPL_2_ pin 68 -mx B6 CLK_CNT_N_0_ mcell B9 mx B23 ... ... -mx B7 inst_CLK_000_D1 mcell D9 mx B24inst_CLK_OUT_PRE mcell G1 -mx B8 RN_IPL_030_0_ mcell B8 mx B25 ... ... -mx B9 DTACK pin 30 mx B26 ... ... -mx B10 VPA pin 36 mx B27 RN_IPL_030_2_ mcell B4 -mx B11 SM_AMIGA_3_ mcell B6 mx B28 CLK_CNT_N_1_ mcell B13 -mx B12 inst_VPA_SYNC mcell B10 mx B29 ... ... -mx B13 ... ... mx B30 ... ... -mx B14 SM_AMIGA_4_ mcell G12 mx B31 SM_AMIGA_2_ mcell B5 +mx B0 IPL_0_ pin 67 mx B17 ... ... +mx B1 RN_IPL_030_1_ mcell B12 mx B18 ... ... +mx B2 ... ... mx B19 ... ... +mx B3 IPL_1_ pin 56 mx B20 ... ... +mx B4 inst_CLK_000_D6 mcell H5 mx B21 RST pin 86 +mx B5 inst_CLK_000_D5 mcell E1 mx B22 IPL_2_ pin 68 +mx B6 SM_AMIGA_2_ mcell B9 mx B23 ... ... +mx B7 inst_VPA_SYNC mcell C5 mx B24 ... ... +mx B8 RN_IPL_030_0_ mcell B8 mx B25 inst_CLK_000_D1 mcell F0 +mx B9 ... ... mx B26 ... ... +mx B10 ... ... mx B27 RN_IPL_030_2_ mcell B4 +mx B11 ... ... mx B28 SM_AMIGA_1_ mcell B5 +mx B12 ... ... mx B29 ... ... +mx B13 inst_DTACK_SYNC mcell C9 mx B30 inst_CLK_000_D0 mcell E8 +mx B14inst_CLK_OUT_PRE mcell C4 mx B31 ... ... mx B15 ... ... mx B32 ... ... -mx B16 IPL_0_ pin 67 +mx B16 SM_AMIGA_3_ mcell C8 ---------------------------------------------------------------------------- @@ -773,23 +826,23 @@ BLOCK_C_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx C0 ... ... mx C17 ... ... -mx C1 ... ... mx C18 ... ... -mx C2 ... ... mx C19 ... ... -mx C3 ... ... mx C20 ... ... +mx C0 RST pin 86 mx C17 RN_VMA mcell D1 +mx C1 CLK_CNT_N_0_ mcell C1 mx C18 ... ... +mx C2 CLK_CNT_N_1_ mcell A9 mx C19 AS_030 pin 82 +mx C3 CLK_CNT_P_1_ mcell E5 mx C20 ... ... mx C4 ... ... mx C21 ... ... -mx C5 ... ... mx C22 ... ... -mx C6 RN_FPU_CS mcell H0 mx C23 ... ... -mx C7 ... ... mx C24 ... ... -mx C8 ... ... mx C25 ... ... -mx C9 ... ... mx C26 ... ... -mx C10 ... ... mx C27 ... ... -mx C11 ... ... mx C28 ... ... -mx C12 ... ... mx C29 ... ... -mx C13 ... ... mx C30 ... ... -mx C14 ... ... mx C31 ... ... +mx C5 ... ... mx C22 CLK_CNT_P_0_ mcell G5 +mx C6 ... ... mx C23 DTACK pin 30 +mx C7 inst_VPA_SYNC mcell C5 mx C24 ... ... +mx C8 inst_CLK_000_D0 mcell E8 mx C25 ... ... +mx C9 SM_AMIGA_4_ mcell A12 mx C26 ... ... +mx C10 VPA pin 36 mx C27 ... ... +mx C11 RN_E mcell G4 mx C28 ... ... +mx C12 RN_FPU_CS mcell H1 mx C29 ... ... +mx C13 inst_DTACK_SYNC mcell C9 mx C30 ... ... +mx C14 cpu_est_1_ mcell G12 mx C31 ... ... mx C15 ... ... mx C32 ... ... -mx C16 ... ... +mx C16 SM_AMIGA_3_ mcell C8 ---------------------------------------------------------------------------- @@ -797,23 +850,23 @@ BLOCK_D_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx D0 SIZE_0_ pin 70 mx D17 SM_AMIGA_5_ mcell D14 -mx D1 RN_BG_000 mcell D13 mx D18 A_0_ pin 69 -mx D2 RN_E mcell G4 mx D19 cpu_est_0_ mcell H1 -mx D3 inst_CLK_000_D0 mcell D2 mx D20 RN_BGACK_030 mcell H4 +mx D0 A0 pin 69 mx D17 RN_VMA mcell D1 +mx D1 RN_BG_000 mcell D13 mx D18 cpu_est_0_ mcell A8 +mx D2 RN_E mcell G4 mx D19 AS_030 pin 82 +mx D3 CLK_000 pin 11 mx D20 SM_AMIGA_6_ mcell F8 mx D4 BG_030 pin 21 mx D21 RST pin 86 -mx D5 RN_LDS_000 mcell D8 mx D22 ... ... -mx D6 SIZE_1_ pin 79 mx D23 SM_AMIGA_4_ mcell G12 -mx D7 inst_CLK_000_D1 mcell D9 mx D24 RN_AS_000 mcell D5 -mx D8 RW pin 71 mx D25 inst_VPA_D mcell B2 -mx D9 AS_030 pin 82 mx D26 ... ... -mx D10RN_AMIGA_BUS_ENABLE mcell D4 mx D27 RN_VMA mcell D1 -mx D11 RN_UDS_000 mcell D12 mx D28 SM_AMIGA_7_ mcell G8 -mx D12 DS_030 pin 98 mx D29 CLK_OSZI pin 61 -mx D13 SM_AMIGA_6_ mcell H5 mx D30 cpu_est_2_ mcell D10 -mx D14 CLK_000 pin 11 mx D31 ... ... +mx D5 DS_030 pin 98 mx D22 ... ... +mx D6 SIZE_1_ pin 79 mx D23 RN_BGACK_030 mcell H4 +mx D7 cpu_est_1_ mcell G12 mx D24RN_AMIGA_BUS_ENABLE mcell D5 +mx D8 inst_CLK_000_D0 mcell E8 mx D25 RW pin 71 +mx D9 SM_AMIGA_4_ mcell A12 mx D26 ... ... +mx D10 RN_AS_000 mcell D4 mx D27 cpu_est_2_ mcell G9 +mx D11 RN_UDS_000 mcell D12 mx D28 ... ... +mx D12 SM_AMIGA_5_ mcell A1 mx D29inst_BGACK_030_INT_D mcell F4 +mx D13 VPA pin 36 mx D30 SM_AMIGA_0_ mcell F1 +mx D14 SIZE_0_ pin 70 mx D31 SM_AMIGA_7_ mcell F12 mx D15 nEXP_SPACE pin 14 mx D32 DSACK_1_ pin 81 -mx D16 cpu_est_1_ mcell D6 +mx D16 RN_LDS_000 mcell D8 ---------------------------------------------------------------------------- @@ -821,47 +874,71 @@ BLOCK_E_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx E0 ... ... mx E17 A_26_ pin 17 -mx E1 A_31_ pin 4 mx E18 ... ... -mx E2 ... ... mx E19 ... ... -mx E3 A_27_ pin 16 mx E20 ... ... +mx E0 RST pin 86 mx E17 A_26_ pin 17 +mx E1 A_31_ pin 4 mx E18 inst_CLK_000_D4 mcell F9 +mx E2 inst_CLK_000_D2 mcell A5 mx E19 ... ... +mx E3 A_27_ pin 16 mx E20 RN_BGACK_030 mcell H4 mx E4 A_29_ pin 6 mx E21 ... ... -mx E5 A_24_ pin 19 mx E22 ... ... -mx E6 RN_FPU_CS mcell H0 mx E23 ... ... +mx E5 A_24_ pin 19 mx E22 CLK_CNT_P_0_ mcell G5 +mx E6 ... ... mx E23 ... ... mx E7 A_28_ pin 15 mx E24 ... ... mx E8 A_22_ pin 85 mx E25 RW pin 71 mx E9 A_30_ pin 5 mx E26 ... ... -mx E10 ... ... mx E27 ... ... +mx E10 RN_FPU_CS mcell H1 mx E27 ... ... mx E11 A_23_ pin 84 mx E28 ... ... mx E12 A_25_ pin 18 mx E29 A_20_ pin 93 mx E13 ... ... mx E30 ... ... -mx E14 ... ... mx E31 ... ... +mx E14 CLK_000 pin 11 mx E31 ... ... mx E15 A_21_ pin 94 mx E32 ... ... mx E16 ... ... ---------------------------------------------------------------------------- +BLOCK_F_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx F0 RST pin 86 mx F17 A_18_ pin 95 +mx F1 FC_1_ pin 58 mx F18 inst_CLK_000_D2 mcell A5 +mx F2 inst_CLK_000_D3 mcell E9 mx F19 AS_030 pin 82 +mx F3 ... ... mx F20 CLK_030 pin 64 +mx F4 BGACK_000 pin 28 mx F21 ... ... +mx F5 nEXP_SPACE pin 14 mx F22 ... ... +mx F6 FC_0_ pin 57 mx F23 RN_BGACK_030 mcell H4 +mx F7 ... ... mx F24 ... ... +mx F8 A_17_ pin 59 mx F25 ... ... +mx F9inst_AS_030_000_SYNC mcell F5 mx F26 ... ... +mx F10 RN_AS_000 mcell D4 mx F27 ... ... +mx F11 A_16_ pin 96 mx F28 SM_AMIGA_1_ mcell B5 +mx F12 A_19_ pin 97 mx F29 inst_CLK_000_D5 mcell E1 +mx F13 inst_CLK_000_D6 mcell H5 mx F30 ... ... +mx F14 ... ... mx F31 SM_AMIGA_7_ mcell F12 +mx F15 SM_AMIGA_0_ mcell F1 mx F32 SM_AMIGA_6_ mcell F8 +mx F16 inst_CLK_000_D0 mcell E8 +---------------------------------------------------------------------------- + + BLOCK_G_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx G0 RST pin 86 mx G17 SM_AMIGA_5_ mcell D14 -mx G1 ... ... mx G18 inst_CLK_000_D4 mcell H10 -mx G2 CLK_CNT_P_1_ mcell H14 mx G19 cpu_est_0_ mcell H1 -mx G3 inst_CLK_000_D0 mcell D2 mx G20 cpu_est_2_ mcell D10 -mx G4 SM_AMIGA_6_ mcell H5 mx G21 inst_CLK_000_D6 mcell H6 -mx G5inst_AS_030_000_SYNC mcell H9 mx G22 CLK_CNT_P_0_ mcell G5 -mx G6 CLK_CNT_N_0_ mcell B9 mx G23 SM_AMIGA_4_ mcell G12 -mx G7 RN_AS_000 mcell D5 mx G24inst_CLK_OUT_PRE mcell G1 -mx G8 ... ... mx G25 inst_CLK_000_D1 mcell D9 -mx G9 inst_CLK_000_D2 mcell D3 mx G26 ... ... -mx G10 CLK_CNT_N_1_ mcell B13 mx G27 inst_CLK_000_D5 mcell G9 -mx G11 RN_E mcell G4 mx G28 SM_AMIGA_1_ mcell H13 -mx G12 SM_AMIGA_0_ mcell G13 mx G29 ... ... -mx G13 SM_AMIGA_7_ mcell G8 mx G30 ... ... -mx G14 inst_CLK_000_D3 mcell H2 mx G31 ... ... -mx G15 nEXP_SPACE pin 14 mx G32 ... ... -mx G16 cpu_est_1_ mcell D6 +mx G0 RST pin 86 mx G17 RN_SIZE_0_ mcell G0 +mx G1 ... ... mx G18 cpu_est_0_ mcell A8 +mx G2 RN_E mcell G4 mx G19 ... ... +mx G3 CLK_CNT_P_1_ mcell E5 mx G20 RN_BGACK_030 mcell H4 +mx G4 CLK_030 pin 64 mx G21 ... ... +mx G5 nEXP_SPACE pin 14 mx G22 CLK_CNT_P_0_ mcell G5 +mx G6inst_CLK_OUT_PRE mcell C4 mx G23 AS_000 pin 33 +mx G7 cpu_est_1_ mcell G12 mx G24 LDS_000 pin 31 +mx G8 UDS_000 pin 32 mx G25 inst_CLK_000_D1 mcell F0 +mx G9 ... ... mx G26 ... ... +mx G10 RN_A0 mcell G8 mx G27 ... ... +mx G11 ... ... mx G28 ... ... +mx G12 cpu_est_2_ mcell G9 mx G29 ... ... +mx G13 ... ... mx G30 ... ... +mx G14inst_BGACK_030_INT_D mcell F4 mx G31 ... ... +mx G15 ... ... mx G32 ... ... +mx G16 inst_CLK_000_D0 mcell E8 ---------------------------------------------------------------------------- @@ -869,23 +946,23 @@ BLOCK_H_LOGIC_ARRAY_FANIN ~~~~~~~~~~~~~~~~~~~~~~~~~ CSM Signal Source CSM Signal Source ------------------------------------ ------------------------------------ -mx H0 RST pin 86 mx H17 FC_0_ pin 57 +mx H0 RN_BGACK_030 mcell H4 mx H17 A_18_ pin 95 mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28 -mx H2 ... ... mx H19 AS_030 pin 82 -mx H3 RN_DSACK_1_ mcell H8 mx H20 CLK_030 pin 64 -mx H4 A_18_ pin 95 mx H21 inst_CLK_000_D6 mcell H6 -mx H5inst_AS_030_000_SYNC mcell H9 mx H22 CLK_CNT_P_0_ mcell G5 -mx H6 A_19_ pin 97 mx H23 RN_BGACK_030 mcell H4 -mx H7 SM_AMIGA_1_ mcell H13 mx H24 ... ... -mx H8 A_17_ pin 59 mx H25 inst_CLK_000_D1 mcell D9 -mx H9 inst_CLK_000_D2 mcell D3 mx H26 ... ... -mx H10 SM_AMIGA_7_ mcell G8 mx H27 inst_CLK_000_D5 mcell G9 -mx H11 A_16_ pin 96 mx H28 SM_AMIGA_2_ mcell B5 -mx H12 cpu_est_0_ mcell H1 mx H29 ... ... -mx H13 SM_AMIGA_6_ mcell H5 mx H30 RN_FPU_CS mcell H0 -mx H14 inst_CLK_000_D3 mcell H2 mx H31 ... ... -mx H15 nEXP_SPACE pin 14 mx H32 ... ... -mx H16 inst_CLK_000_D0 mcell D2 +mx H2 ... ... mx H19 ... ... +mx H3 RN_AS_030 mcell H8 mx H20 CLK_030 pin 64 +mx H4 inst_CLK_000_D6 mcell H5 mx H21 RST pin 86 +mx H5 nEXP_SPACE pin 14 mx H22 ... ... +mx H6 FC_0_ pin 57 mx H23 RN_SIZE_1_ mcell H0 +mx H7 ... ... mx H24 LDS_000 pin 31 +mx H8 UDS_000 pin 32 mx H25 inst_CLK_000_D1 mcell F0 +mx H9 AS_030 pin 82 mx H26 AS_000 pin 33 +mx H10 RN_FPU_CS mcell H1 mx H27 ... ... +mx H11 A_16_ pin 96 mx H28 SM_AMIGA_1_ mcell B5 +mx H12 A_19_ pin 97 mx H29 inst_CLK_000_D5 mcell E1 +mx H13 A_17_ pin 59 mx H30 ... ... +mx H14inst_BGACK_030_INT_D mcell F4 mx H31 ... ... +mx H15 RN_DSACK_1_ mcell H12 mx H32 ... ... +mx H16 inst_CLK_000_D0 mcell E8 ---------------------------------------------------------------------------- CSM indicates the mux inputs from the Central Switch Matrix. @@ -900,20 +977,32 @@ PostFit_Equations P-Terms Fan-in Fan-out Type Name (attributes) --------- ------ ------- ---- ----------------- + 0 0 1 Pin DSACK_0_ + 0 0 1 Pin DSACK_0_.OE 0 0 1 Pin BERR 1 1 1 Pin BERR.OE 1 1 1 Pin CLK_DIV_OUT.AR 1 1 1 Pin CLK_DIV_OUT.D 1 1 1 Pin CLK_DIV_OUT.C + 1 1 1 Pin DTACK + 1 2 1 Pin DTACK.OE 1 0 1 Pin AVEC 0 0 1 Pin AVEC_EXP 1 1 1 Pin AVEC_EXP.OE - 1 1 1 Pin AMIGA_BUS_DATA_DIR + 2 2 1 Pin AMIGA_BUS_DATA_DIR 1 0 1 Pin AMIGA_BUS_ENABLE_LOW 1 4 1 Pin CIIN 1 8 1 Pin CIIN.OE - 1 0 1 Pin DSACK_0_ - 1 1 1 Pin DSACK_0_.OE + 3 4 1 Pin IPL_030_1_.D + 1 1 1 Pin IPL_030_1_.AP + 1 1 1 Pin IPL_030_1_.C + 3 4 1 Pin IPL_030_0_.D + 1 1 1 Pin IPL_030_0_.AP + 1 1 1 Pin IPL_030_0_.C + 1 2 1 Pin SIZE_1_.OE + 3 7 1 Pin SIZE_1_.D- + 1 1 1 Pin SIZE_1_.AP + 1 1 1 Pin SIZE_1_.C 3 4 1 Pin IPL_030_2_.D 1 1 1 Pin IPL_030_2_.AP 1 1 1 Pin IPL_030_2_.C @@ -921,10 +1010,18 @@ PostFit_Equations 2 5 1 Pin DSACK_1_.D- 1 1 1 Pin DSACK_1_.AP 1 1 1 Pin DSACK_1_.C + 1 2 1 Pin AS_030.OE + 3 7 1 Pin AS_030.D- + 1 1 1 Pin AS_030.AP + 1 1 1 Pin AS_030.C 1 1 1 Pin AS_000.OE 2 3 1 Pin AS_000.D 1 1 1 Pin AS_000.AP 1 1 1 Pin AS_000.C + 1 2 1 Pin DS_030.OE + 5 9 1 Pin DS_030.D- + 1 1 1 Pin DS_030.AP + 1 1 1 Pin DS_030.C 1 1 1 Pin UDS_000.OE 5 7 1 Pin UDS_000.D- 1 1 1 Pin UDS_000.AP @@ -933,6 +1030,10 @@ PostFit_Equations 8 9 1 Pin LDS_000.D 1 1 1 Pin LDS_000.AP 1 1 1 Pin LDS_000.C + 1 2 1 Pin A0.OE + 2 7 1 Pin A0.D + 1 1 1 Pin A0.AP + 1 1 1 Pin A0.C 2 6 1 Pin BG_000.D- 1 1 1 Pin BG_000.AP 1 1 1 Pin BG_000.C @@ -945,10 +1046,6 @@ PostFit_Equations 2 10 1 Pin FPU_CS.D- 1 1 1 Pin FPU_CS.AP 1 1 1 Pin FPU_CS.C - 1 2 1 Pin DTACK.OE - 1 2 1 Pin DTACK.D- - 1 1 1 Pin DTACK.AP - 1 1 1 Pin DTACK.C 3 6 1 PinX1 E.D.X1 1 1 1 PinX2 E.D.X2 1 1 1 Pin E.AR @@ -960,23 +1057,22 @@ PostFit_Equations 1 1 1 Pin RESET.AR 1 0 1 Pin RESET.D 1 1 1 Pin RESET.C - 3 5 1 Pin AMIGA_BUS_ENABLE.D- + 7 8 1 Pin AMIGA_BUS_ENABLE.D + 1 1 1 Pin AMIGA_BUS_ENABLE.AP 1 1 1 Pin AMIGA_BUS_ENABLE.C - 3 4 1 Pin IPL_030_1_.D - 1 1 1 Pin IPL_030_1_.AP - 1 1 1 Pin IPL_030_1_.C - 3 4 1 Pin IPL_030_0_.D - 1 1 1 Pin IPL_030_0_.AP - 1 1 1 Pin IPL_030_0_.C + 1 2 1 Pin SIZE_0_.OE + 2 7 1 Pin SIZE_0_.D- + 1 1 1 Pin SIZE_0_.AP + 1 1 1 Pin SIZE_0_.C 7 16 1 Node inst_AS_030_000_SYNC.D 1 1 1 Node inst_AS_030_000_SYNC.AP 1 1 1 Node inst_AS_030_000_SYNC.C + 1 1 1 Node inst_BGACK_030_INT_D.D + 1 1 1 Node inst_BGACK_030_INT_D.AP + 1 1 1 Node inst_BGACK_030_INT_D.C 2 6 1 Node inst_DTACK_SYNC.D- 1 1 1 Node inst_DTACK_SYNC.AP 1 1 1 Node inst_DTACK_SYNC.C - 1 1 1 Node inst_VPA_D.D - 1 1 1 Node inst_VPA_D.AP - 1 1 1 Node inst_VPA_D.C 2 8 1 Node inst_VPA_SYNC.D- 1 1 1 Node inst_VPA_SYNC.AP 1 1 1 Node inst_VPA_SYNC.C @@ -1001,18 +1097,15 @@ PostFit_Equations 1 1 1 Node inst_CLK_000_D3.D 1 1 1 Node inst_CLK_000_D3.AP 1 1 1 Node inst_CLK_000_D3.C - 1 1 1 Node SM_AMIGA_4_.AR - 2 3 1 Node SM_AMIGA_4_.D - 1 1 1 Node SM_AMIGA_4_.C 1 1 1 Node inst_CLK_000_D5.D 1 1 1 Node inst_CLK_000_D5.AP 1 1 1 Node inst_CLK_000_D5.C - 5 9 1 Node SM_AMIGA_7_.D - 1 1 1 Node SM_AMIGA_7_.AP - 1 1 1 Node SM_AMIGA_7_.C 1 1 1 Node SM_AMIGA_3_.AR 3 5 1 Node SM_AMIGA_3_.D 1 1 1 Node SM_AMIGA_3_.C + 1 1 1 Node SM_AMIGA_0_.AR + 4 6 1 Node SM_AMIGA_0_.D + 1 1 1 Node SM_AMIGA_0_.C 1 1 1 Node SM_AMIGA_1_.AR 3 5 1 Node SM_AMIGA_1_.D 1 1 1 Node SM_AMIGA_1_.C @@ -1028,18 +1121,21 @@ PostFit_Equations 1 1 1 Node CLK_CNT_P_1_.AR 1 1 1 Node CLK_CNT_P_1_.D 1 1 1 Node CLK_CNT_P_1_.C - 1 1 1 Node SM_AMIGA_2_.AR - 3 5 1 Node SM_AMIGA_2_.D - 1 1 1 Node SM_AMIGA_2_.C - 1 1 1 Node SM_AMIGA_0_.AR - 4 6 1 Node SM_AMIGA_0_.D - 1 1 1 Node SM_AMIGA_0_.C 1 1 1 Node inst_CLK_000_D4.D 1 1 1 Node inst_CLK_000_D4.AP 1 1 1 Node inst_CLK_000_D4.C + 5 9 1 Node SM_AMIGA_7_.D + 1 1 1 Node SM_AMIGA_7_.AP + 1 1 1 Node SM_AMIGA_7_.C + 1 1 1 Node SM_AMIGA_4_.AR + 2 3 1 Node SM_AMIGA_4_.D + 1 1 1 Node SM_AMIGA_4_.C 1 1 1 Node inst_CLK_OUT_PRE.AR 4 4 1 Node inst_CLK_OUT_PRE.D 1 1 1 Node inst_CLK_OUT_PRE.C + 1 1 1 Node SM_AMIGA_2_.AR + 3 5 1 Node SM_AMIGA_2_.D + 1 1 1 Node SM_AMIGA_2_.C 1 1 1 Node cpu_est_0_.AR 3 3 1 Node cpu_est_0_.D 1 1 1 Node cpu_est_0_.C @@ -1051,7 +1147,7 @@ PostFit_Equations 1 1 1 Node cpu_est_2_.AR 1 1 1 Node cpu_est_2_.C ========= - 211 P-Term Total: 211 + 243 P-Term Total: 243 Total Pins: 59 Total Nodes: 27 Average P-Term/Output: 2 @@ -1059,6 +1155,10 @@ PostFit_Equations Equations: +DSACK_0_ = (0); + +DSACK_0_.OE = (0); + BERR = (0); BERR.OE = (!FPU_CS.Q); @@ -1069,13 +1169,18 @@ CLK_DIV_OUT.D = (inst_CLK_OUT_PRE.Q); CLK_DIV_OUT.C = (CLK_OSZI); +DTACK = (DSACK_1_.PIN); + +DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q); + AVEC = (1); AVEC_EXP = (0); AVEC_EXP.OE = (!FPU_CS.Q); -AMIGA_BUS_DATA_DIR = (!RW); +AMIGA_BUS_DATA_DIR = (!RW & BGACK_030.Q + # RW & !BGACK_030.Q); AMIGA_BUS_ENABLE_LOW = (1); @@ -1083,12 +1188,34 @@ CIIN = (A_23_ & A_22_ & A_21_ & A_20_); CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_); -DSACK_0_ = (1); +IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q + # inst_CLK_000_D1.Q & IPL_030_1_.Q + # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); -DSACK_0_.OE = (nEXP_SPACE); +IPL_030_1_.AP = (!RST); -IPL_030_2_.D = (IPL_030_2_.Q & !inst_CLK_000_D0.Q - # IPL_030_2_.Q & inst_CLK_000_D1.Q +IPL_030_1_.C = (CLK_OSZI); + +IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q + # inst_CLK_000_D1.Q & IPL_030_0_.Q + # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); + +IPL_030_0_.AP = (!RST); + +IPL_030_0_.C = (CLK_OSZI); + +SIZE_1_.OE = (!nEXP_SPACE & !BGACK_030.Q); + +!SIZE_1_.D = (BGACK_030.Q & inst_BGACK_030_INT_D.Q & !SIZE_1_.Q + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & LDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN); + +SIZE_1_.AP = (!RST); + +SIZE_1_.C = (CLK_OSZI); + +IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q + # inst_CLK_000_D1.Q & IPL_030_2_.Q # IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); IPL_030_2_.AP = (!RST); @@ -1097,29 +1224,51 @@ IPL_030_2_.C = (CLK_OSZI); DSACK_1_.OE = (nEXP_SPACE); -!DSACK_1_.D = (!AS_030 & !DSACK_1_.Q +!DSACK_1_.D = (!DSACK_1_.Q & !AS_030.PIN # !inst_CLK_000_D6.Q & inst_CLK_000_D5.Q & SM_AMIGA_1_.Q); DSACK_1_.AP = (!RST); DSACK_1_.C = (CLK_OSZI); +AS_030.OE = (!nEXP_SPACE & !BGACK_030.Q); + +!AS_030.D = (BGACK_030.Q & inst_BGACK_030_INT_D.Q & !AS_030.Q + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !LDS_000.PIN); + +AS_030.AP = (!RST); + +AS_030.C = (CLK_OSZI); + AS_000.OE = (BGACK_030.Q); -AS_000.D = (AS_030 & !SM_AMIGA_5_.Q - # AS_000.Q & !SM_AMIGA_5_.Q); +AS_000.D = (!SM_AMIGA_5_.Q & AS_000.Q + # !SM_AMIGA_5_.Q & AS_030.PIN); AS_000.AP = (!RST); AS_000.C = (CLK_OSZI); +DS_030.OE = (!nEXP_SPACE & !BGACK_030.Q); + +!DS_030.D = (BGACK_030.Q & inst_BGACK_030_INT_D.Q & !DS_030.Q + # !CLK_030 & RW & !BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !UDS_000.PIN + # !CLK_030 & RW & !BGACK_030.Q & !AS_000.PIN & !LDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !AS_030.Q & !AS_000.PIN & !LDS_000.PIN); + +DS_030.AP = (!RST); + +DS_030.C = (CLK_OSZI); + UDS_000.OE = (BGACK_030.Q); -!UDS_000.D = (!AS_030 & DS_030 & !UDS_000.Q - # !DS_030 & RW & !A_0_ & SM_AMIGA_5_.Q - # !AS_030 & RW & !SM_AMIGA_5_.Q & !UDS_000.Q - # !DS_030 & !RW & !A_0_ & SM_AMIGA_4_.Q - # !AS_030 & !RW & !UDS_000.Q & !SM_AMIGA_4_.Q); +!UDS_000.D = (!UDS_000.Q & !AS_030.PIN & DS_030.PIN + # RW & !SM_AMIGA_5_.Q & !UDS_000.Q & !AS_030.PIN + # !RW & !UDS_000.Q & !SM_AMIGA_4_.Q & !AS_030.PIN + # RW & SM_AMIGA_5_.Q & !DS_030.PIN & !A0.PIN + # !RW & SM_AMIGA_4_.Q & !DS_030.PIN & !A0.PIN); UDS_000.AP = (!RST); @@ -1127,21 +1276,30 @@ UDS_000.C = (CLK_OSZI); LDS_000.OE = (BGACK_030.Q); -LDS_000.D = (AS_030 & DS_030 - # DS_030 & LDS_000.Q - # AS_030 & RW & !SM_AMIGA_5_.Q +LDS_000.D = (LDS_000.Q & DS_030.PIN + # AS_030.PIN & DS_030.PIN # RW & !SM_AMIGA_5_.Q & LDS_000.Q - # AS_030 & !RW & !SM_AMIGA_4_.Q # !RW & LDS_000.Q & !SM_AMIGA_4_.Q - # !SIZE_1_ & !DS_030 & RW & SIZE_0_ & !A_0_ & SM_AMIGA_5_.Q - # !SIZE_1_ & !DS_030 & !RW & SIZE_0_ & !A_0_ & SM_AMIGA_4_.Q); + # RW & !SM_AMIGA_5_.Q & AS_030.PIN + # !RW & !SM_AMIGA_4_.Q & AS_030.PIN + # RW & SM_AMIGA_5_.Q & !DS_030.PIN & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN + # !RW & SM_AMIGA_4_.Q & !DS_030.PIN & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN); LDS_000.AP = (!RST); LDS_000.C = (CLK_OSZI); +A0.OE = (!nEXP_SPACE & !BGACK_030.Q); + +A0.D = (BGACK_030.Q & inst_BGACK_030_INT_D.Q & A0.Q + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN); + +A0.AP = (!RST); + +A0.C = (CLK_OSZI); + !BG_000.D = (!BG_030 & !BG_000.Q - # AS_030 & nEXP_SPACE & !BG_030 & CLK_000 & SM_AMIGA_7_.Q); + # nEXP_SPACE & !BG_030 & CLK_000 & SM_AMIGA_7_.Q & AS_030.PIN); BG_000.AP = (!RST); @@ -1160,21 +1318,13 @@ CLK_EXP.D = (inst_CLK_OUT_PRE.Q); CLK_EXP.C = (CLK_OSZI); -!FPU_CS.D = (!AS_030 & !FPU_CS.Q - # FC_1_ & !AS_030 & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_); +!FPU_CS.D = (!FPU_CS.Q & !AS_030.PIN + # FC_1_ & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); FPU_CS.AP = (!RST); FPU_CS.C = (CLK_OSZI); -DTACK.OE = (!nEXP_SPACE & !BGACK_030.Q); - -!DTACK.D = (!AS_000.Q & !DSACK_1_.PIN); - -DTACK.AP = (!RST); - -DTACK.C = (CLK_OSZI); - E.D.X1 = (inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_1_.Q & cpu_est_2_.Q & E.Q # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_0_.Q & !cpu_est_2_.Q & !E.Q # inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !E.Q); @@ -1186,9 +1336,9 @@ E.AR = (!RST); E.C = (CLK_OSZI); VMA.D.X1 = (VMA.Q - # !VMA.Q & AS_000.Q & inst_CLK_000_D0.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & !E.Q); + # !VMA.Q & inst_CLK_000_D0.Q & AS_000.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & !E.Q); -VMA.D.X2 = (VMA.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & cpu_est_0_.Q & !cpu_est_1_.Q); +VMA.D.X2 = (!VPA & VMA.Q & !inst_CLK_000_D0.Q & cpu_est_0_.Q & !cpu_est_1_.Q); VMA.AP = (!RST); @@ -1200,29 +1350,28 @@ RESET.D = (1); RESET.C = (CLK_OSZI); -!AMIGA_BUS_ENABLE.D = (!RST & !AMIGA_BUS_ENABLE.Q - # nEXP_SPACE & RST & SM_AMIGA_6_.Q - # !AS_030 & !SM_AMIGA_6_.Q & !AMIGA_BUS_ENABLE.Q); +AMIGA_BUS_ENABLE.D = (BGACK_030.Q & !inst_BGACK_030_INT_D.Q + # !nEXP_SPACE & BGACK_030.Q & AMIGA_BUS_ENABLE.Q + # !nEXP_SPACE & !inst_BGACK_030_INT_D.Q & AMIGA_BUS_ENABLE.Q + # BGACK_030.Q & !SM_AMIGA_6_.Q & AMIGA_BUS_ENABLE.Q + # !inst_BGACK_030_INT_D.Q & !SM_AMIGA_6_.Q & AMIGA_BUS_ENABLE.Q + # BGACK_030.Q & inst_CLK_000_D0.Q & AS_000.Q & SM_AMIGA_0_.Q + # !inst_BGACK_030_INT_D.Q & inst_CLK_000_D0.Q & AS_000.Q & SM_AMIGA_0_.Q); + +AMIGA_BUS_ENABLE.AP = (!RST); AMIGA_BUS_ENABLE.C = (CLK_OSZI); -IPL_030_1_.D = (IPL_030_1_.Q & !inst_CLK_000_D0.Q - # IPL_030_1_.Q & inst_CLK_000_D1.Q - # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); +SIZE_0_.OE = (!nEXP_SPACE & !BGACK_030.Q); -IPL_030_1_.AP = (!RST); +!SIZE_0_.D = (BGACK_030.Q & inst_BGACK_030_INT_D.Q & !SIZE_0_.Q + # !CLK_030 & !BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN); -IPL_030_1_.C = (CLK_OSZI); +SIZE_0_.AP = (!RST); -IPL_030_0_.D = (IPL_030_0_.Q & !inst_CLK_000_D0.Q - # IPL_030_0_.Q & inst_CLK_000_D1.Q - # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q); +SIZE_0_.C = (CLK_OSZI); -IPL_030_0_.AP = (!RST); - -IPL_030_0_.C = (CLK_OSZI); - -inst_AS_030_000_SYNC.D = (AS_030 +inst_AS_030_000_SYNC.D = (AS_030.PIN # !nEXP_SPACE & inst_AS_030_000_SYNC.Q # !CLK_030 & inst_AS_030_000_SYNC.Q # !nEXP_SPACE & SM_AMIGA_6_.Q @@ -1234,21 +1383,21 @@ inst_AS_030_000_SYNC.AP = (!RST); inst_AS_030_000_SYNC.C = (CLK_OSZI); -!inst_DTACK_SYNC.D = (!AS_030 & !inst_DTACK_SYNC.Q - # inst_VPA_D.Q & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !DTACK.PIN); +inst_BGACK_030_INT_D.D = (BGACK_030.Q); + +inst_BGACK_030_INT_D.AP = (!RST); + +inst_BGACK_030_INT_D.C = (CLK_OSZI); + +!inst_DTACK_SYNC.D = (!inst_DTACK_SYNC.Q & !AS_030.PIN + # VPA & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !DTACK.PIN); inst_DTACK_SYNC.AP = (!RST); inst_DTACK_SYNC.C = (CLK_OSZI); -inst_VPA_D.D = (VPA); - -inst_VPA_D.AP = (!RST); - -inst_VPA_D.C = (CLK_OSZI); - -!inst_VPA_SYNC.D = (!AS_030 & !inst_VPA_SYNC.Q - # !VMA.Q & !inst_VPA_D.Q & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); +!inst_VPA_SYNC.D = (!inst_VPA_SYNC.Q & !AS_030.PIN + # !VPA & !VMA.Q & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !cpu_est_1_.Q & E.Q); inst_VPA_SYNC.AP = (!RST); @@ -1298,37 +1447,29 @@ inst_CLK_000_D3.AP = (!RST); inst_CLK_000_D3.C = (CLK_OSZI); -SM_AMIGA_4_.AR = (!RST); - -SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q - # !inst_CLK_000_D0.Q & SM_AMIGA_4_.Q); - -SM_AMIGA_4_.C = (CLK_OSZI); - inst_CLK_000_D5.D = (inst_CLK_000_D4.Q); inst_CLK_000_D5.AP = (!RST); inst_CLK_000_D5.C = (CLK_OSZI); -SM_AMIGA_7_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_7_.Q - # inst_CLK_000_D2.Q & SM_AMIGA_7_.Q - # !inst_CLK_000_D3.Q & SM_AMIGA_7_.Q - # !nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q - # AS_000.Q & inst_CLK_000_D0.Q & SM_AMIGA_0_.Q); - -SM_AMIGA_7_.AP = (!RST); - -SM_AMIGA_7_.C = (CLK_OSZI); - SM_AMIGA_3_.AR = (!RST); -SM_AMIGA_3_.D = (inst_CLK_000_D0.Q & SM_AMIGA_4_.Q - # inst_CLK_000_D0.Q & SM_AMIGA_3_.Q +SM_AMIGA_3_.D = (inst_CLK_000_D0.Q & SM_AMIGA_3_.Q + # inst_CLK_000_D0.Q & SM_AMIGA_4_.Q # inst_DTACK_SYNC.Q & inst_VPA_SYNC.Q & SM_AMIGA_3_.Q); SM_AMIGA_3_.C = (CLK_OSZI); +SM_AMIGA_0_.AR = (!RST); + +SM_AMIGA_0_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_0_.Q + # !AS_000.Q & SM_AMIGA_0_.Q + # !inst_CLK_000_D0.Q & inst_CLK_000_D6.Q & SM_AMIGA_1_.Q + # !inst_CLK_000_D0.Q & !inst_CLK_000_D5.Q & SM_AMIGA_1_.Q); + +SM_AMIGA_0_.C = (CLK_OSZI); + SM_AMIGA_1_.AR = (!RST); SM_AMIGA_1_.D = (inst_CLK_000_D0.Q & SM_AMIGA_1_.Q @@ -1363,29 +1504,29 @@ CLK_CNT_P_1_.D = (CLK_CNT_P_0_.Q); CLK_CNT_P_1_.C = (CLK_OSZI); -SM_AMIGA_2_.AR = (!RST); - -SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q - # !inst_DTACK_SYNC.Q & !inst_CLK_000_D0.Q & SM_AMIGA_3_.Q - # !inst_VPA_SYNC.Q & !inst_CLK_000_D0.Q & SM_AMIGA_3_.Q); - -SM_AMIGA_2_.C = (CLK_OSZI); - -SM_AMIGA_0_.AR = (!RST); - -SM_AMIGA_0_.D = (!AS_000.Q & SM_AMIGA_0_.Q - # !inst_CLK_000_D0.Q & SM_AMIGA_0_.Q - # !inst_CLK_000_D0.Q & inst_CLK_000_D6.Q & SM_AMIGA_1_.Q - # !inst_CLK_000_D0.Q & !inst_CLK_000_D5.Q & SM_AMIGA_1_.Q); - -SM_AMIGA_0_.C = (CLK_OSZI); - inst_CLK_000_D4.D = (inst_CLK_000_D3.Q); inst_CLK_000_D4.AP = (!RST); inst_CLK_000_D4.C = (CLK_OSZI); +SM_AMIGA_7_.D = (inst_AS_030_000_SYNC.Q & SM_AMIGA_7_.Q + # inst_CLK_000_D2.Q & SM_AMIGA_7_.Q + # !inst_CLK_000_D3.Q & SM_AMIGA_7_.Q + # !nEXP_SPACE & !inst_CLK_000_D0.Q & SM_AMIGA_6_.Q + # inst_CLK_000_D0.Q & AS_000.Q & SM_AMIGA_0_.Q); + +SM_AMIGA_7_.AP = (!RST); + +SM_AMIGA_7_.C = (CLK_OSZI); + +SM_AMIGA_4_.AR = (!RST); + +SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_5_.Q + # !inst_CLK_000_D0.Q & SM_AMIGA_4_.Q); + +SM_AMIGA_4_.C = (CLK_OSZI); + inst_CLK_OUT_PRE.AR = (!RST); inst_CLK_OUT_PRE.D = (!CLK_CNT_N_0_.Q & CLK_CNT_N_1_.Q & !CLK_CNT_P_0_.Q & CLK_CNT_P_1_.Q @@ -1395,6 +1536,14 @@ inst_CLK_OUT_PRE.D = (!CLK_CNT_N_0_.Q & CLK_CNT_N_1_.Q & !CLK_CNT_P_0_.Q & CLK_C inst_CLK_OUT_PRE.C = (CLK_OSZI); +SM_AMIGA_2_.AR = (!RST); + +SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q + # !inst_DTACK_SYNC.Q & !inst_CLK_000_D0.Q & SM_AMIGA_3_.Q + # !inst_VPA_SYNC.Q & !inst_CLK_000_D0.Q & SM_AMIGA_3_.Q); + +SM_AMIGA_2_.C = (CLK_OSZI); + cpu_est_0_.AR = (!RST); cpu_est_0_.D = (!inst_CLK_000_D0.Q & cpu_est_0_.Q diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal index 78df47e..6e527a8 100644 --- a/Logic/68030_tk.tal +++ b/Logic/68030_tk.tal @@ -32,38 +32,48 @@ TCR, Clocked Output-to-Register Time, TSU TCO TPD TCR #passes #passes #passes #passes SIGNAL NAME min max min max min max min max + inst_DTACK_SYNC 1 2 .. .. .. .. 1 1 + DTACK .. .. .. .. 1 1 .. .. AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. .. CIIN .. .. .. .. 1 1 .. .. - IPL_030_2_ 1 1 0 0 .. .. 1 1 - RN_IPL_030_2_ 1 1 0 0 .. .. 1 1 - DSACK_1_ 1 1 0 0 .. .. 1 1 - RN_DSACK_1_ 1 1 0 0 .. .. 1 1 - AS_000 1 1 0 0 .. .. 1 1 - RN_AS_000 1 1 0 0 .. .. 1 1 - UDS_000 1 1 0 0 .. .. 1 1 - RN_UDS_000 1 1 0 0 .. .. 1 1 - LDS_000 1 1 0 0 .. .. 1 1 - RN_LDS_000 1 1 0 0 .. .. 1 1 - BG_000 1 1 0 0 .. .. 1 1 - RN_BG_000 1 1 0 0 .. .. 1 1 - BGACK_030 1 1 0 0 .. .. 1 1 - RN_BGACK_030 1 1 0 0 .. .. 1 1 - FPU_CS 1 1 0 0 .. .. 1 1 - RN_FPU_CS 1 1 0 0 .. .. 1 1 - DTACK 1 1 0 0 .. .. .. .. - E .. .. 0 0 .. .. 1 1 - RN_E .. .. 0 0 .. .. 1 1 - VMA .. .. 0 0 .. .. 1 1 - RN_VMA .. .. 0 0 .. .. 1 1 -AMIGA_BUS_ENABLE 1 1 0 0 .. .. 1 1 -RN_AMIGA_BUS_ENABLE 1 1 0 0 .. .. 1 1 IPL_030_1_ 1 1 0 0 .. .. 1 1 RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 IPL_030_0_ 1 1 0 0 .. .. 1 1 RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 + SIZE_1_ 1 1 0 0 .. .. 1 1 + RN_SIZE_1_ 1 1 0 0 .. .. 1 1 + IPL_030_2_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_2_ 1 1 0 0 .. .. 1 1 + DSACK_1_ 1 1 0 0 .. .. 1 1 + RN_DSACK_1_ 1 1 0 0 .. .. 1 1 + AS_030 1 1 0 0 .. .. 1 1 + RN_AS_030 1 1 0 0 .. .. 1 1 + AS_000 1 1 0 0 .. .. 1 1 + RN_AS_000 1 1 0 0 .. .. 1 1 + DS_030 1 1 0 0 .. .. 1 1 + RN_DS_030 1 1 0 0 .. .. 1 1 + UDS_000 1 1 0 0 .. .. 1 1 + RN_UDS_000 1 1 0 0 .. .. 1 1 + LDS_000 1 1 0 0 .. .. 1 1 + RN_LDS_000 1 1 0 0 .. .. 1 1 + A0 1 1 0 0 .. .. 1 1 + RN_A0 1 1 0 0 .. .. 1 1 + BG_000 1 1 0 0 .. .. 1 1 + RN_BG_000 1 1 0 0 .. .. 1 1 + BGACK_030 1 1 0 1 .. .. 1 1 + RN_BGACK_030 1 1 0 1 .. .. 1 1 + FPU_CS 1 1 0 0 .. .. 1 1 + RN_FPU_CS 1 1 0 0 .. .. 1 1 + E .. .. 0 0 .. .. 1 1 + RN_E .. .. 0 0 .. .. 1 1 + VMA 1 1 0 0 .. .. 1 1 + RN_VMA 1 1 0 0 .. .. 1 1 +AMIGA_BUS_ENABLE 1 1 0 0 .. .. 1 1 +RN_AMIGA_BUS_ENABLE 1 1 0 0 .. .. 1 1 + SIZE_0_ 1 1 0 0 .. .. 1 1 + RN_SIZE_0_ 1 1 0 0 .. .. 1 1 inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1 - inst_DTACK_SYNC 1 1 .. .. .. .. 1 1 - inst_VPA_D 1 1 .. .. .. .. 1 1 +inst_BGACK_030_INT_D .. .. .. .. .. .. 1 1 inst_VPA_SYNC 1 1 .. .. .. .. 1 1 inst_CLK_000_D0 1 1 .. .. .. .. 1 1 inst_CLK_000_D1 .. .. .. .. .. .. 1 1 @@ -72,19 +82,19 @@ inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1 SM_AMIGA_5_ .. .. .. .. .. .. 1 1 SM_AMIGA_6_ 1 1 .. .. .. .. 1 1 inst_CLK_000_D3 .. .. .. .. .. .. 1 1 - SM_AMIGA_4_ .. .. .. .. .. .. 1 1 inst_CLK_000_D5 .. .. .. .. .. .. 1 1 - SM_AMIGA_7_ 1 1 .. .. .. .. 1 1 SM_AMIGA_3_ .. .. .. .. .. .. 1 1 + SM_AMIGA_0_ .. .. .. .. .. .. 1 1 SM_AMIGA_1_ .. .. .. .. .. .. 1 1 CLK_CNT_N_0_ .. .. .. .. .. .. 1 1 CLK_CNT_N_1_ .. .. .. .. .. .. 1 1 CLK_CNT_P_0_ .. .. .. .. .. .. 1 1 CLK_CNT_P_1_ .. .. .. .. .. .. 1 1 - SM_AMIGA_2_ .. .. .. .. .. .. 1 1 - SM_AMIGA_0_ .. .. .. .. .. .. 1 1 inst_CLK_000_D4 .. .. .. .. .. .. 1 1 + SM_AMIGA_7_ 1 1 .. .. .. .. 1 1 + SM_AMIGA_4_ .. .. .. .. .. .. 1 1 inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1 + SM_AMIGA_2_ .. .. .. .. .. .. 1 1 cpu_est_0_ .. .. .. .. .. .. 1 1 cpu_est_1_ .. .. .. .. .. .. 1 1 cpu_est_2_ .. .. .. .. .. .. 1 1 \ No newline at end of file diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2 index a83d918..858afac 100644 --- a/Logic/68030_tk.tt2 +++ b/Logic/68030_tk.tt2 @@ -1,330 +1,374 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat May 24 19:56:20 2014 +#$ DATE Sat May 24 21:59:14 2014 #$ MODULE 68030_tk -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 SIZE_0_ DS_030 A_30_ A_29_ A_28_ nEXP_SPACE A_27_ BERR A_26_ BG_030 A_25_ A_24_ A_23_ BGACK_000 A_22_ CLK_030 A_21_ CLK_000 A_20_ CLK_OSZI A_19_ CLK_DIV_OUT A_18_ A_17_ A_16_ AVEC AVEC_EXP VPA RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 27 inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D6 SM_AMIGA_5_ SM_AMIGA_6_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D5 SM_AMIGA_7_ SM_AMIGA_3_ SM_AMIGA_1_ CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ CLK_CNT_P_1_ SM_AMIGA_2_ SM_AMIGA_0_ inst_CLK_000_D4 inst_CLK_OUT_PRE cpu_est_0_ cpu_est_1_ cpu_est_2_ +#$ PINS 59 IPL_1_ IPL_0_ A_31_ DSACK_0_ FC_0_ IPL_2_ FC_1_ nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_1_ IPL_030_0_ SIZE_1_ IPL_030_2_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS E VMA RESET AMIGA_BUS_ENABLE SIZE_0_ +#$ NODES 27 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_DTACK_SYNC inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D6 SM_AMIGA_5_ SM_AMIGA_6_ inst_CLK_000_D3 inst_CLK_000_D5 SM_AMIGA_3_ SM_AMIGA_0_ SM_AMIGA_1_ CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ CLK_CNT_P_1_ inst_CLK_000_D4 SM_AMIGA_7_ SM_AMIGA_4_ inst_CLK_OUT_PRE SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_ .type fr -.i 77 -.o 147 -.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q IPL_030_0_.Q VMA.Q AS_000.Q IPL_030_1_.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q IPL_030_2_.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D6.Q SM_AMIGA_5_.Q SM_AMIGA_6_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q SM_AMIGA_4_.Q inst_CLK_000_D5.Q SM_AMIGA_7_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q CLK_CNT_N_0_.Q CLK_CNT_N_1_.Q AMIGA_BUS_ENABLE.Q CLK_CNT_P_0_.Q CLK_CNT_P_1_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q inst_CLK_000_D4.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q BG_000.Q DSACK_1_.PIN DTACK.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR cpu_est_0_.C cpu_est_0_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.C CLK_CNT_N_1_.AP CLK_CNT_P_0_.C CLK_CNT_P_0_.AR CLK_CNT_P_1_.C CLK_CNT_P_1_.AR IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP VMA.C VMA.AP BG_000.C BG_000.AP BGACK_030.C BGACK_030.AP AS_000.C AS_000.AP inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR CLK_EXP.C CLK_EXP.AR inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP DSACK_1_.C DSACK_1_.AP AMIGA_BUS_ENABLE.C DTACK.C DTACK.AP inst_CLK_000_D5.C inst_CLK_000_D5.AP inst_CLK_000_D6.C inst_CLK_000_D6.AP inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_VPA_D.C inst_VPA_D.AP inst_CLK_000_D0.C inst_CLK_000_D0.AP RESET.C RESET.AR inst_CLK_000_D1.C inst_CLK_000_D1.AP DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D CLK_EXP.D BGACK_030.D FPU_CS.D IPL_030_0_.D VMA.D AS_000.D IPL_030_1_.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D IPL_030_2_.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D0.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_CLK_000_D6.D SM_AMIGA_5_.D SM_AMIGA_6_.D UDS_000.D LDS_000.D DSACK_1_.D inst_CLK_000_D3.D SM_AMIGA_4_.D inst_CLK_000_D5.D SM_AMIGA_7_.D RESET.D SM_AMIGA_3_.D SM_AMIGA_1_.D DTACK.D CLK_CNT_N_0_.D CLK_CNT_N_1_.D AMIGA_BUS_ENABLE.D CLK_CNT_P_0_.D CLK_CNT_P_1_.D SM_AMIGA_2_.D SM_AMIGA_0_.D inst_CLK_000_D4.D inst_CLK_OUT_PRE.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D BG_000.D -.p 318 ------------------------------------------------------------------------------ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ -----0-------------------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0-0----1-0------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ -------1----------------------------------0----0-0------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ------------------------------------------0----0-0--0---1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ --------------------------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~ -1----0--------0-----------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ ------0--------00----------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ ------0--------0----------------1------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ ------0--------0----------------0------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------------0-----0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~ -----0---------0-------------------------------------0---0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~ -----0---------0--------------------------------------0--0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1----------------------------------0---------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------0----------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -----0------------------------------------0---------0-----0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----1-10--1-----------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ------------------------------------------1----------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -------------------------------------------------1---------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ ----00-1--1---------------------------------------1--------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1-01---------------------------------------1--------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-----------------1---------------------1--------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------1--------------------1--------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-------------------0-------------------1--------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1--------------------1------------------1--------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------------0--------------1--------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------0--1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ ----00-1--1-----------------------------------------------01------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1-01-----------------------------------------------01------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-----------------1-----------------------------01------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------1----------------------------01------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-------------------0---------------------------01------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1--------------------1--------------------------01------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------------0----------------------01------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0---------------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------1-----------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------------------0------1-----------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ -------1---------------------------------------0-----------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ ----------------------------------------------------0------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------0----0------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ -----------------------------------------------0------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ ---------------------------------------------------------0--0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ --------------------------------------------------0-------1--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~ -----0-1----------------------------------0------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------0-------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -----0------------------------------------0---------0--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----00-1--1------------------------------------------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1-01------------------------------------------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-----------------1------------------------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------1-----------------------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1-------------------0----------------------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1--------------------1---------------------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----0-1--1------------------------0-----------------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------------------------------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~ --------------------------------------------------------------11-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------------------------------------------------------01-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ --------------------------------------------------------------10-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~ --------------------------------------------------------------00-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ --------------0-------------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -----0----------------------------------------------0-----------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~ -----------------------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~ -----------------------------------------------------------------11----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -----------------------------------------------------------------01----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----------------------------------------------------------------10----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~ -----------------------------------------------------------------00----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~ -------------------------------------------1--1--------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ ------------------------------------------------------------0------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~ -------------------------------------------------------------0-----0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ -----------------------------------------------1--------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ------------------------------------------0----1-0------1-----------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ --------------------------------------------------0-------1---------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ -----------------------------------------------1-----------0--------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ -------------------------------------------------------------0------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~ ---------------------------------------------------------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ ----------------------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------10----------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ -----------------------------------------------0-----------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ------------------------------------------------1----------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~ ---------------------------------------0--------------------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------------0-0-----------------------10----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------10-----------------------11---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ---------------------------------------0---------------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------------------------0-------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ------------------------------------------------1------------------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ -----------------------------------------------------------------------010---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ---------------------------------------0----------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------------------------------0-----0-1------------1-----------0-1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------------------------------------------111--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -----------------------------------------------------------------------0-01--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -----------------------------------------------0--------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ ------------------------------------------------1-------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------------------------------------01-0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------------10----------------------10-0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ -------------------------------------------------------------------------10--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~ -----------------------------------------------------------------------0-10--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -----------------------------------------------------------------------1-00--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ------------------------------------------------------------------------100--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ --------0------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ----------------------------------------0-----------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ---------------------------------------------1-1------------1----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.i 85 +.o 166 +.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q VMA.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_DTACK_SYNC.Q inst_VPA_SYNC.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D6.Q SM_AMIGA_5_.Q IPL_030_0_.Q IPL_030_1_.Q AS_000.Q SM_AMIGA_6_.Q IPL_030_2_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q inst_CLK_000_D5.Q SM_AMIGA_3_.Q SM_AMIGA_0_.Q SM_AMIGA_1_.Q AS_030.Q DS_030.Q SIZE_0_.Q SIZE_1_.Q A0.Q CLK_CNT_N_0_.Q CLK_CNT_N_1_.Q CLK_CNT_P_0_.Q CLK_CNT_P_1_.Q inst_CLK_000_D4.Q SM_AMIGA_7_.Q SM_AMIGA_4_.Q inst_CLK_OUT_PRE.Q SM_AMIGA_2_.Q AMIGA_BUS_ENABLE.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK_1_.PIN DTACK.PIN +.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR cpu_est_0_.C cpu_est_0_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_P_1_.C CLK_CNT_P_1_.AR SIZE_0_.C SIZE_0_.AP SIZE_1_.C SIZE_1_.AP IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR inst_VPA_SYNC.C inst_VPA_SYNC.AP DSACK_1_.C DSACK_1_.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.C CLK_CNT_N_1_.AP CLK_CNT_P_0_.C CLK_CNT_P_0_.AR LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP A0.C A0.AP BG_000.C BG_000.AP AS_030.C AS_030.AP AMIGA_BUS_ENABLE.C AMIGA_BUS_ENABLE.AP AS_000.C AS_000.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP DS_030.C DS_030.AP FPU_CS.C FPU_CS.AP UDS_000.C UDS_000.AP CLK_EXP.C CLK_EXP.AR inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR inst_CLK_000_D5.C inst_CLK_000_D5.AP inst_CLK_000_D6.C inst_CLK_000_D6.AP inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_000_D0.C inst_CLK_000_D0.AP RESET.C RESET.AR inst_CLK_000_D1.C inst_CLK_000_D1.AP DTACK DSACK_0_ AS_030.OE AS_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK_1_.OE DTACK.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D BG_000.D BGACK_030.D FPU_CS.D VMA.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_DTACK_SYNC.D inst_VPA_SYNC.D inst_CLK_000_D0.D inst_CLK_000_D1.D CLK_EXP.D inst_CLK_000_D2.D inst_CLK_000_D6.D SM_AMIGA_5_.D IPL_030_0_.D IPL_030_1_.D AS_000.D SM_AMIGA_6_.D IPL_030_2_.D UDS_000.D LDS_000.D DSACK_1_.D inst_CLK_000_D3.D inst_CLK_000_D5.D SM_AMIGA_3_.D SM_AMIGA_0_.D SM_AMIGA_1_.D AS_030.D DS_030.D SIZE_0_.D SIZE_1_.D A0.D CLK_CNT_N_0_.D CLK_CNT_N_1_.D CLK_CNT_P_0_.D CLK_CNT_P_1_.D inst_CLK_000_D4.D RESET.D SM_AMIGA_7_.D SM_AMIGA_4_.D inst_CLK_OUT_PRE.D SM_AMIGA_2_.D AMIGA_BUS_ENABLE.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D +.p 362 +------------------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +---1--------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----1-------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------1----------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------1---------------------------------------------------------------------------- ~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------0---------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------0-------------------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +0-----------0000000------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------1111-------------------------------------------------------------- ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0--------------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------0----------------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~11~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1-------------------------1----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0-------------------1----------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0---------------------------0----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~111~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------1------------------------0----------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1111~~~~~~~~~~~~~~~~ +-----------1-------------------0----------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--0-----------------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----0--------------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0-------------------------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------1--------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------1-------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------0------1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------1-----1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------0--1---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------0---------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-----------------------1--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0------------------------------1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------0---------------------------1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--1--1-----------------0010--1----1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------1---0------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1111~~~~~~~~~~~1~~~~ +---------0--------------------------1------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1---------------------------1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1---1----------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1----1---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1-0---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------10---------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-1------------------------------------10--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----1--------------------------------10--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------1----------10--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------1---------10--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------1-------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1---1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0---1------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +--------------------------------------0----1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1---1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-----1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1----1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------0--1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0------------------------------------------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1-------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0----------------------------------0-------1-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +--------------------------------------0--------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------1-------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------0-----1------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------0------1----------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1--------1---------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~ +----------------------------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1-0-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------11---------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1--------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------0-0--------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +-------------------------------------00--------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +------------------------------------1----------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1---------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0---------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1------1--------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +-------------------------------1------1------1--------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-----------------------------------0--1------1--------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +---------------------------------------------0--------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1----------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0--1-------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------0----------1--1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0-------------0--1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------1----0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------1------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~ +-----------0-------------------0------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +-------------------------------1-------------------------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~ +-------------------------------1--------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +-------------------------------1---------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +-------------------------------1---1------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +-------------------------------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~ +-------------------------------------------------------------11---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +-------------------------------------------------------------00---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~ +---------------------------------------------------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~ +---------------------------------------------------------------11-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-------------------------------------------------------------0101-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +-------------------------------------------------------------1001-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +-------------------------------------------------------------0110-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +-------------------------------------------------------------1010-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~ +---------------------------------------------------------------00-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~ +-----------------------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------1-------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +----------------------------------------1-------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +----------------------------------0-----0----------1--------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------0--------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~ +------------------------------1-----------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------1-------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1----------------------------------0-------1-------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1----------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0----------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~ +-----------0------------------------------------1------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0-------------------------------------1-----------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------1------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~ +---0---------------------------1--------------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +---0-------------------------------0----------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-------------------------------1--------------0-----------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +-----------------------------------0----------0-----------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~ +--------------------------------------0--------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +---------------------------------------1-------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +---------------------------------1-------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------10-------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~ +---------------------------------1--------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------1----------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------10-------------------------------00------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +--------------------------------------0----------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +---------------------------------------1---------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +------------------------------------------------------------------------11----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +--------------------------------------10-------------------------------1-0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------------10--------------------------------00----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------------0-----------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +---------------------------------------1----------------------------------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------------10-------------------------------1--1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~ +------------------------------------------------------------------------0-1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------------10--------------------------------011---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-------------------------------------------------------------------------01---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 +--------------------------------------10-------------------------------1-01---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +-------------------------------------1------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------10-------------------------------1-10---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +--------------------------------------1------1-------------------------0110---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------10--------------------------------000---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~ +---------------------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1-----------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------0-----------------------------------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------1-----------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------0------------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------1---------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------0--------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------0--------------------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~ +----------------------------------------------------0----------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------0---------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------------0-------------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0-------------------------------------------------------0-------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------------1--1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--------------------------------------------------------------------------01--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------1--------------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------0--------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1111~~~~~~~~~~~~~~~~ +------------------------------------------------1----------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------1---------------------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------------------1-1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------0----------------------------------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +-------------------------------0-----------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ +-------------------------------0----------------------------------------------11----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~1~~~~~~~~~~~~~~~~ +------0------------------------0--------------------------------------------0-10----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~ +-------------------------------0----------------------------------------------00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~ +-----------1------------------------------1----------------------------------0----1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0-------------------------------------------------------1---------0----1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------1----------------------------------0--100-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0-------------------------------------------------------1---------0--100-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------1-----------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------------------------------------------------------------------------1--------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +------------------------------------------------------------------------------------- 0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +1------------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~000~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---0--------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----0------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------0----------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------0--------------------------------------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +------------------------------------------------0--------------------------0-1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------------------------0-------------------------0-1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-------------------------------0----------------------------------------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +------0------------------------0--------------------------------------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +------0----1-------------------0--------------------------------------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +------0------------------------0------------------------0-------------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +-------------------------------0-----------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +------0------------------------0--------------------------------------------0-01----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +------0------------------------0--------------------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +------0----1-------------------0--------------------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +------0------------------------0------------------------0-------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +------0------------------------0--------------------------------------------0-10----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +------0------------------------0--------------------------------------------0-00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +-----------1------------------------------1----------------------------------0--0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0-------------------------------------------------------1---------0--0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------1----------------------------------0---1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0-------------------------------------------------------1---------0---1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------1----------------------------------0----1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0-------------------------------------------------------1---------0----1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------1----------------------------------0----0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0-------------------------------------------------------1---------0----0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1----------------------------1--------------1------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3 index cfe23f5..39482c9 100644 --- a/Logic/68030_tk.tt3 +++ b/Logic/68030_tk.tt3 @@ -1,330 +1,374 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat May 24 19:56:20 2014 +#$ DATE Sat May 24 21:59:14 2014 #$ MODULE 68030_tk -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 SIZE_0_ DS_030 A_30_ A_29_ A_28_ nEXP_SPACE A_27_ BERR A_26_ BG_030 A_25_ A_24_ A_23_ BGACK_000 A_22_ CLK_030 A_21_ CLK_000 A_20_ CLK_OSZI A_19_ CLK_DIV_OUT A_18_ A_17_ A_16_ AVEC AVEC_EXP VPA RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 27 inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D6 SM_AMIGA_5_ SM_AMIGA_6_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D5 SM_AMIGA_7_ SM_AMIGA_3_ SM_AMIGA_1_ CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ CLK_CNT_P_1_ SM_AMIGA_2_ SM_AMIGA_0_ inst_CLK_000_D4 inst_CLK_OUT_PRE cpu_est_0_ cpu_est_1_ cpu_est_2_ +#$ PINS 59 IPL_1_ IPL_0_ A_31_ DSACK_0_ FC_0_ IPL_2_ FC_1_ nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_1_ IPL_030_0_ SIZE_1_ IPL_030_2_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS E VMA RESET AMIGA_BUS_ENABLE SIZE_0_ +#$ NODES 27 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_DTACK_SYNC inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D6 SM_AMIGA_5_ SM_AMIGA_6_ inst_CLK_000_D3 inst_CLK_000_D5 SM_AMIGA_3_ SM_AMIGA_0_ SM_AMIGA_1_ CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ CLK_CNT_P_1_ inst_CLK_000_D4 SM_AMIGA_7_ SM_AMIGA_4_ inst_CLK_OUT_PRE SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_ .type fr -.i 77 -.o 147 -.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q IPL_030_0_.Q VMA.Q AS_000.Q IPL_030_1_.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q IPL_030_2_.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D6.Q SM_AMIGA_5_.Q SM_AMIGA_6_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q SM_AMIGA_4_.Q inst_CLK_000_D5.Q SM_AMIGA_7_.Q SM_AMIGA_3_.Q SM_AMIGA_1_.Q CLK_CNT_N_0_.Q CLK_CNT_N_1_.Q AMIGA_BUS_ENABLE.Q CLK_CNT_P_0_.Q CLK_CNT_P_1_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q inst_CLK_000_D4.Q inst_CLK_OUT_PRE.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q BG_000.Q DSACK_1_.PIN DTACK.PIN -.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR cpu_est_0_.C cpu_est_0_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.C CLK_CNT_N_1_.AP CLK_CNT_P_0_.C CLK_CNT_P_0_.AR CLK_CNT_P_1_.C CLK_CNT_P_1_.AR IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR UDS_000.C UDS_000.AP LDS_000.C LDS_000.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP VMA.C VMA.AP BG_000.C BG_000.AP BGACK_030.C BGACK_030.AP AS_000.C AS_000.AP inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR CLK_EXP.C CLK_EXP.AR inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP DSACK_1_.C DSACK_1_.AP AMIGA_BUS_ENABLE.C DTACK.C DTACK.AP inst_CLK_000_D5.C inst_CLK_000_D5.AP inst_CLK_000_D6.C inst_CLK_000_D6.AP inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_VPA_D.C inst_VPA_D.AP inst_CLK_000_D0.C inst_CLK_000_D0.AP RESET.C RESET.AR inst_CLK_000_D1.C inst_CLK_000_D1.AP DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D CLK_EXP.D BGACK_030.D FPU_CS.D IPL_030_0_.D VMA.D AS_000.D IPL_030_1_.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D IPL_030_2_.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D0.D inst_CLK_000_D1.D inst_CLK_000_D2.D inst_CLK_000_D6.D SM_AMIGA_5_.D SM_AMIGA_6_.D UDS_000.D LDS_000.D DSACK_1_.D inst_CLK_000_D3.D SM_AMIGA_4_.D inst_CLK_000_D5.D SM_AMIGA_7_.D RESET.D SM_AMIGA_3_.D SM_AMIGA_1_.D DTACK.D CLK_CNT_N_0_.D CLK_CNT_N_1_.D AMIGA_BUS_ENABLE.D CLK_CNT_P_0_.D CLK_CNT_P_1_.D SM_AMIGA_2_.D SM_AMIGA_0_.D inst_CLK_000_D4.D inst_CLK_OUT_PRE.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D BG_000.D -.p 318 ------------------------------------------------------------------------------ ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~ -----1------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----11----------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~ -------1---------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------1--------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1 -----------1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------1----------------------------------------------------------------- ~~~~~~1~1~1~1~1~1~1~1~1~1~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~11~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------0----------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------------1---------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --------------0--------------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~1~1~1~1~1~1~1~1~1~1~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------------0-------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --0--------------0000000------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------1111-------------------------------------------------- ~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ------------------------------------1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------1--------------------------1----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -------0----------------------------0----------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----0--------------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ---------0---------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------0--------------------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ----------------------------1--------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -----------------------------1-------1---------------------------------------- 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ -----------------------------------------------------------------------1-00--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~ ------------------------------------------------------------------------100--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~ --------0------------------------------------------------------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0 ----------------------------------------0-----------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~ ---------------------------------------------1-1------------1----------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.i 85 +.o 166 +.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q VMA.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_DTACK_SYNC.Q inst_VPA_SYNC.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D6.Q SM_AMIGA_5_.Q IPL_030_0_.Q IPL_030_1_.Q AS_000.Q SM_AMIGA_6_.Q IPL_030_2_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q inst_CLK_000_D5.Q SM_AMIGA_3_.Q SM_AMIGA_0_.Q SM_AMIGA_1_.Q AS_030.Q DS_030.Q SIZE_0_.Q SIZE_1_.Q A0.Q CLK_CNT_N_0_.Q CLK_CNT_N_1_.Q CLK_CNT_P_0_.Q CLK_CNT_P_1_.Q inst_CLK_000_D4.Q SM_AMIGA_7_.Q SM_AMIGA_4_.Q inst_CLK_OUT_PRE.Q SM_AMIGA_2_.Q AMIGA_BUS_ENABLE.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN DS_030.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK_1_.PIN DTACK.PIN +.ob BERR AVEC AVEC_EXP AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.C cpu_est_2_.AR E.C E.AR cpu_est_0_.C cpu_est_0_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_P_1_.C CLK_CNT_P_1_.AR SIZE_0_.C SIZE_0_.AP SIZE_1_.C SIZE_1_.AP IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR inst_VPA_SYNC.C inst_VPA_SYNC.AP DSACK_1_.C DSACK_1_.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.C CLK_CNT_N_1_.AP CLK_CNT_P_0_.C CLK_CNT_P_0_.AR LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP A0.C A0.AP BG_000.C BG_000.AP AS_030.C AS_030.AP AMIGA_BUS_ENABLE.C AMIGA_BUS_ENABLE.AP AS_000.C AS_000.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP DS_030.C DS_030.AP FPU_CS.C FPU_CS.AP UDS_000.C UDS_000.AP CLK_EXP.C CLK_EXP.AR inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR inst_CLK_000_D5.C inst_CLK_000_D5.AP inst_CLK_000_D6.C inst_CLK_000_D6.AP inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_000_D0.C inst_CLK_000_D0.AP RESET.C RESET.AR inst_CLK_000_D1.C inst_CLK_000_D1.AP DTACK DSACK_0_ AS_030.OE AS_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK_1_.OE DTACK.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.AR CLK_DIV_OUT.C CLK_DIV_OUT.D BG_000.D BGACK_030.D FPU_CS.D VMA.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_DTACK_SYNC.D inst_VPA_SYNC.D inst_CLK_000_D0.D inst_CLK_000_D1.D CLK_EXP.D inst_CLK_000_D2.D inst_CLK_000_D6.D SM_AMIGA_5_.D IPL_030_0_.D IPL_030_1_.D AS_000.D SM_AMIGA_6_.D IPL_030_2_.D UDS_000.D LDS_000.D DSACK_1_.D inst_CLK_000_D3.D inst_CLK_000_D5.D SM_AMIGA_3_.D SM_AMIGA_0_.D SM_AMIGA_1_.D AS_030.D DS_030.D SIZE_0_.D SIZE_1_.D A0.D CLK_CNT_N_0_.D CLK_CNT_N_1_.D CLK_CNT_P_0_.D CLK_CNT_P_1_.D inst_CLK_000_D4.D RESET.D SM_AMIGA_7_.D SM_AMIGA_4_.D inst_CLK_OUT_PRE.D SM_AMIGA_2_.D AMIGA_BUS_ENABLE.D cpu_est_0_.D cpu_est_1_.T cpu_est_2_.D E.D +.p 362 +------------------------------------------------------------------------------------- ~1~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~ +---1--------------------------------------------------------------------------------- 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+---1--1-------------------1-------------------------0-------------1--------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--1----------------------0----------------------0-------------1--------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +--01--1------------------------------------------------0----------1--------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1-01------------------------------------------------0----------1--------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--1----------------1-------------------------------0----------1--------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--1-----------------1------------------------------0----------1--------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---1--1------------------0-----------------------------0----------1--------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +-------------------------------0-----------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~ +------0------------------------0--------------------------------------------0-01----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +------0------------------------0--------------------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~ +------0----1-------------------0--------------------------------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +------0------------------------0------------------------0-------------------0--0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~ +------0------------------------0--------------------------------------------0-10----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~ +------0------------------------0--------------------------------------------0-00----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~ +-----------1------------------------------1----------------------------------0--0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0-------------------------------------------------------1---------0--0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------1----------------------------------0---1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0-------------------------------------------------------1---------0---1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------1----------------------------------0----1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0-------------------------------------------------------1---------0----1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------1------------------------------1----------------------------------0----0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------0-------------------------------------------------------1---------0----0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~ +-----------------------------------------------------------------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +---------1----------------------------1--------------1------------------------------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .end diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4 index 4a1fa7a..f291d58 100644 --- a/Logic/68030_tk.tt4 +++ b/Logic/68030_tk.tt4 @@ -1,174 +1,197 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat May 24 19:56:20 2014 +#$ DATE Sat May 24 21:59:14 2014 #$ MODULE BUS68030 -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 SIZE_0_ DS_030 A_30_ A_29_ A_28_ - nEXP_SPACE A_27_ BERR A_26_ BG_030 A_25_ A_24_ A_23_ BGACK_000 A_22_ CLK_030 - A_21_ CLK_000 A_20_ CLK_OSZI A_19_ CLK_DIV_OUT A_18_ A_17_ A_16_ AVEC AVEC_EXP - VPA RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ - DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 - CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 27 inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC - inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D6 SM_AMIGA_5_ - SM_AMIGA_6_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D5 SM_AMIGA_7_ SM_AMIGA_3_ - SM_AMIGA_1_ CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ CLK_CNT_P_1_ SM_AMIGA_2_ - SM_AMIGA_0_ inst_CLK_000_D4 inst_CLK_OUT_PRE cpu_est_0_ cpu_est_1_ cpu_est_2_ +#$ PINS 59 IPL_1_ IPL_0_ A_31_ DSACK_0_ FC_0_ IPL_2_ FC_1_ nEXP_SPACE BERR + BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA + RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ + A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_1_ + IPL_030_0_ SIZE_1_ IPL_030_2_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 + BG_000 BGACK_030 CLK_EXP FPU_CS E VMA RESET AMIGA_BUS_ENABLE SIZE_0_ +#$ NODES 27 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_DTACK_SYNC + inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D6 + SM_AMIGA_5_ SM_AMIGA_6_ inst_CLK_000_D3 inst_CLK_000_D5 SM_AMIGA_3_ SM_AMIGA_0_ + SM_AMIGA_1_ CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ CLK_CNT_P_1_ inst_CLK_000_D4 + SM_AMIGA_7_ SM_AMIGA_4_ inst_CLK_OUT_PRE SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ + cpu_est_2_ .type f -.i 77 -.o 150 -.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 - CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ - A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ - BGACK_030.Q FPU_CS.Q IPL_030_0_.Q VMA.Q AS_000.Q IPL_030_1_.Q - inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q IPL_030_2_.Q inst_VPA_D.Q - inst_VPA_SYNC.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q - inst_CLK_000_D6.Q SM_AMIGA_5_.Q SM_AMIGA_6_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q - inst_CLK_000_D3.Q SM_AMIGA_4_.Q inst_CLK_000_D5.Q SM_AMIGA_7_.Q SM_AMIGA_3_.Q - SM_AMIGA_1_.Q CLK_CNT_N_0_.Q CLK_CNT_N_1_.Q AMIGA_BUS_ENABLE.Q CLK_CNT_P_0_.Q - CLK_CNT_P_1_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q inst_CLK_000_D4.Q inst_CLK_OUT_PRE.Q - cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q BG_000.Q DSACK_1_.PIN DTACK.PIN -.ob BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C CLK_DIV_OUT.AR AVEC AVEC_EXP - AVEC_EXP.OE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE DSACK_0_ - DSACK_0_.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D% DSACK_1_.C - DSACK_1_.AP DSACK_1_.OE AS_000.D AS_000.C AS_000.AP AS_000.OE UDS_000.D% - UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE +.i 85 +.o 169 +.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA + RST RW A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ + A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q VMA.Q + inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_DTACK_SYNC.Q inst_VPA_SYNC.Q + inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D6.Q + SM_AMIGA_5_.Q IPL_030_0_.Q IPL_030_1_.Q AS_000.Q SM_AMIGA_6_.Q IPL_030_2_.Q + UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q inst_CLK_000_D5.Q SM_AMIGA_3_.Q + SM_AMIGA_0_.Q SM_AMIGA_1_.Q AS_030.Q DS_030.Q SIZE_0_.Q SIZE_1_.Q A0.Q + CLK_CNT_N_0_.Q CLK_CNT_N_1_.Q CLK_CNT_P_0_.Q CLK_CNT_P_1_.Q inst_CLK_000_D4.Q + SM_AMIGA_7_.Q SM_AMIGA_4_.Q inst_CLK_OUT_PRE.Q SM_AMIGA_2_.Q AMIGA_BUS_ENABLE.Q + cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN DS_030.PIN + UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK_1_.PIN DTACK.PIN +.ob DSACK_0_ DSACK_0_.OE BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C CLK_DIV_OUT.AR + DTACK DTACK.OE AVEC AVEC_EXP AVEC_EXP.OE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW + CIIN CIIN.OE IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C + IPL_030_0_.AP SIZE_1_.D% SIZE_1_.C SIZE_1_.AP SIZE_1_.OE IPL_030_2_.D + IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D% DSACK_1_.C DSACK_1_.AP DSACK_1_.OE + AS_030.D% AS_030.C AS_030.AP AS_030.OE AS_000.D AS_000.C AS_000.AP AS_000.OE + DS_030.D% DS_030.C DS_030.AP DS_030.OE UDS_000.D% UDS_000.C UDS_000.AP + UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE A0.D A0.C A0.AP A0.OE BG_000.D% BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D - CLK_EXP.C CLK_EXP.AR FPU_CS.D% FPU_CS.C FPU_CS.AP DTACK.D% DTACK.C DTACK.AP - DTACK.OE E.D.X1 E.D.X2 E.C E.AR VMA.D.X1 VMA.D.X2 VMA.C VMA.AP RESET.D RESET.C - RESET.AR AMIGA_BUS_ENABLE.D% AMIGA_BUS_ENABLE.C IPL_030_1_.D IPL_030_1_.C - IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP inst_AS_030_000_SYNC.D - inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D% - inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP - inst_VPA_SYNC.D% inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D0.D - inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_CLK_000_D1.D inst_CLK_000_D1.C - inst_CLK_000_D1.AP inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP - inst_CLK_000_D6.D inst_CLK_000_D6.C inst_CLK_000_D6.AP SM_AMIGA_5_.D - SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR - inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP SM_AMIGA_4_.D - SM_AMIGA_4_.C SM_AMIGA_4_.AR inst_CLK_000_D5.D inst_CLK_000_D5.C - inst_CLK_000_D5.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_3_.D - SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR - 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inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D6.D + inst_CLK_000_D6.C inst_CLK_000_D6.AP SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR + SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR inst_CLK_000_D3.D inst_CLK_000_D3.C + inst_CLK_000_D3.AP inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_000_D5.AP + SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C + SM_AMIGA_0_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR CLK_CNT_N_0_.D + CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.D CLK_CNT_N_1_.C CLK_CNT_N_1_.AP + CLK_CNT_P_0_.D CLK_CNT_P_0_.C CLK_CNT_P_0_.AR CLK_CNT_P_1_.D CLK_CNT_P_1_.C + CLK_CNT_P_1_.AR inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP + SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_4_.D SM_AMIGA_4_.C + SM_AMIGA_4_.AR inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR + SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR cpu_est_0_.D cpu_est_0_.C + cpu_est_0_.AR cpu_est_1_.T cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D.X1 + cpu_est_2_.D.X2 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0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte index 9eece27..7a062e0 100644 --- a/Logic/68030_tk.tte +++ b/Logic/68030_tk.tte @@ -1,174 +1,197 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat May 24 19:56:20 2014 +#$ DATE Sat May 24 21:59:14 2014 #$ MODULE BUS68030 -#$ PINS 59 SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 SIZE_0_ DS_030 A_30_ A_29_ A_28_ - nEXP_SPACE A_27_ BERR A_26_ BG_030 A_25_ A_24_ A_23_ BGACK_000 A_22_ CLK_030 - A_21_ CLK_000 A_20_ CLK_OSZI A_19_ CLK_DIV_OUT A_18_ A_17_ A_16_ AVEC AVEC_EXP - VPA RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_0_ IPL_1_ IPL_0_ - DSACK_0_ FC_0_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 - CLK_EXP FPU_CS DTACK E VMA RESET AMIGA_BUS_ENABLE IPL_030_1_ IPL_030_0_ -#$ NODES 27 inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC - inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D6 SM_AMIGA_5_ - SM_AMIGA_6_ inst_CLK_000_D3 SM_AMIGA_4_ inst_CLK_000_D5 SM_AMIGA_7_ SM_AMIGA_3_ - SM_AMIGA_1_ CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ CLK_CNT_P_1_ SM_AMIGA_2_ - SM_AMIGA_0_ inst_CLK_000_D4 inst_CLK_OUT_PRE cpu_est_0_ cpu_est_1_ cpu_est_2_ +#$ PINS 59 IPL_1_ IPL_0_ A_31_ DSACK_0_ FC_0_ IPL_2_ FC_1_ nEXP_SPACE BERR + BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA + RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ + A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_1_ + IPL_030_0_ SIZE_1_ IPL_030_2_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 + BG_000 BGACK_030 CLK_EXP FPU_CS E VMA RESET AMIGA_BUS_ENABLE SIZE_0_ +#$ NODES 27 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_DTACK_SYNC + inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D6 + SM_AMIGA_5_ SM_AMIGA_6_ inst_CLK_000_D3 inst_CLK_000_D5 SM_AMIGA_3_ SM_AMIGA_0_ + SM_AMIGA_1_ CLK_CNT_N_0_ CLK_CNT_N_1_ CLK_CNT_P_0_ CLK_CNT_P_1_ inst_CLK_000_D4 + SM_AMIGA_7_ SM_AMIGA_4_ inst_CLK_OUT_PRE SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ + cpu_est_2_ .type f -.i 77 -.o 150 -.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 - CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ - A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ - BGACK_030.Q FPU_CS.Q IPL_030_0_.Q VMA.Q AS_000.Q IPL_030_1_.Q - inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q IPL_030_2_.Q inst_VPA_D.Q - inst_VPA_SYNC.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q - inst_CLK_000_D6.Q SM_AMIGA_5_.Q SM_AMIGA_6_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q - inst_CLK_000_D3.Q SM_AMIGA_4_.Q inst_CLK_000_D5.Q SM_AMIGA_7_.Q SM_AMIGA_3_.Q - SM_AMIGA_1_.Q CLK_CNT_N_0_.Q CLK_CNT_N_1_.Q AMIGA_BUS_ENABLE.Q CLK_CNT_P_0_.Q - CLK_CNT_P_1_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q inst_CLK_000_D4.Q inst_CLK_OUT_PRE.Q - cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q BG_000.Q DSACK_1_.PIN DTACK.PIN -.ob BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C CLK_DIV_OUT.AR AVEC AVEC_EXP - AVEC_EXP.OE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN CIIN.OE DSACK_0_ - DSACK_0_.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D- DSACK_1_.C - DSACK_1_.AP DSACK_1_.OE AS_000.D AS_000.C AS_000.AP AS_000.OE UDS_000.D- - UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE +.i 85 +.o 169 +.ilb A_31_ IPL_2_ FC_1_ nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA + RST RW A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ + A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BG_000.Q BGACK_030.Q FPU_CS.Q VMA.Q + inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_DTACK_SYNC.Q inst_VPA_SYNC.Q + inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_000_D2.Q inst_CLK_000_D6.Q + SM_AMIGA_5_.Q IPL_030_0_.Q IPL_030_1_.Q AS_000.Q SM_AMIGA_6_.Q IPL_030_2_.Q + UDS_000.Q LDS_000.Q DSACK_1_.Q inst_CLK_000_D3.Q inst_CLK_000_D5.Q SM_AMIGA_3_.Q + SM_AMIGA_0_.Q SM_AMIGA_1_.Q AS_030.Q DS_030.Q SIZE_0_.Q SIZE_1_.Q A0.Q + CLK_CNT_N_0_.Q CLK_CNT_N_1_.Q CLK_CNT_P_0_.Q CLK_CNT_P_1_.Q inst_CLK_000_D4.Q + SM_AMIGA_7_.Q SM_AMIGA_4_.Q inst_CLK_OUT_PRE.Q SM_AMIGA_2_.Q AMIGA_BUS_ENABLE.Q + cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q E.Q AS_030.PIN AS_000.PIN DS_030.PIN + UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK_1_.PIN DTACK.PIN +.ob DSACK_0_ DSACK_0_.OE BERR BERR.OE CLK_DIV_OUT.D CLK_DIV_OUT.C CLK_DIV_OUT.AR + DTACK DTACK.OE AVEC AVEC_EXP AVEC_EXP.OE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW + CIIN CIIN.OE IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C + IPL_030_0_.AP SIZE_1_.D- SIZE_1_.C SIZE_1_.AP SIZE_1_.OE IPL_030_2_.D + IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D- DSACK_1_.C DSACK_1_.AP DSACK_1_.OE + AS_030.D- AS_030.C AS_030.AP AS_030.OE AS_000.D AS_000.C AS_000.AP AS_000.OE + DS_030.D- DS_030.C DS_030.AP DS_030.OE UDS_000.D- UDS_000.C UDS_000.AP + UDS_000.OE LDS_000.D LDS_000.C LDS_000.AP LDS_000.OE A0.D A0.C A0.AP A0.OE BG_000.D- BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D - CLK_EXP.C CLK_EXP.AR FPU_CS.D- FPU_CS.C FPU_CS.AP DTACK.D- DTACK.C DTACK.AP - DTACK.OE E.D.X1 E.D.X2 E.C E.AR VMA.D.X1 VMA.D.X2 VMA.C VMA.AP RESET.D RESET.C - RESET.AR AMIGA_BUS_ENABLE.D- AMIGA_BUS_ENABLE.C IPL_030_1_.D IPL_030_1_.C - IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP inst_AS_030_000_SYNC.D - inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D- - inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP - inst_VPA_SYNC.D- inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D0.D - inst_CLK_000_D0.C inst_CLK_000_D0.AP inst_CLK_000_D1.D inst_CLK_000_D1.C - inst_CLK_000_D1.AP inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP - inst_CLK_000_D6.D inst_CLK_000_D6.C inst_CLK_000_D6.AP SM_AMIGA_5_.D - SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR - inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP SM_AMIGA_4_.D - SM_AMIGA_4_.C SM_AMIGA_4_.AR inst_CLK_000_D5.D inst_CLK_000_D5.C - inst_CLK_000_D5.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_3_.D - SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR - CLK_CNT_N_0_.D CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.D CLK_CNT_N_1_.C - CLK_CNT_N_1_.AP CLK_CNT_P_0_.D CLK_CNT_P_0_.C CLK_CNT_P_0_.AR CLK_CNT_P_1_.D - CLK_CNT_P_1_.C CLK_CNT_P_1_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR - SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR inst_CLK_000_D4.D inst_CLK_000_D4.C - inst_CLK_000_D4.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR - cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR cpu_est_1_.T cpu_est_1_.C cpu_est_1_.AR - cpu_est_2_.D.X1 cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_2_.AR -.phase 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 -.p 115 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inst_DTACK_SYNC.D- inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_VPA_SYNC.D- + inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_CLK_000_D0.D inst_CLK_000_D0.C + inst_CLK_000_D0.AP inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP + inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D6.D + inst_CLK_000_D6.C inst_CLK_000_D6.AP SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR + SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR inst_CLK_000_D3.D inst_CLK_000_D3.C + inst_CLK_000_D3.AP inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_000_D5.AP + SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C + SM_AMIGA_0_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR CLK_CNT_N_0_.D + CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.D CLK_CNT_N_1_.C CLK_CNT_N_1_.AP + CLK_CNT_P_0_.D CLK_CNT_P_0_.C CLK_CNT_P_0_.AR CLK_CNT_P_1_.D CLK_CNT_P_1_.C + CLK_CNT_P_1_.AR inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP + SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_4_.D SM_AMIGA_4_.C + SM_AMIGA_4_.AR inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR + SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR cpu_est_0_.D cpu_est_0_.C + cpu_est_0_.AR cpu_est_1_.T cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D.X1 + cpu_est_2_.D.X2 cpu_est_2_.C cpu_est_2_.AR +.phase 1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 +.p 133 +------------------------------------------------------------------------------------- 0000000001000100000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 +--------------------------------0---------------------------------------------------- 0001000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 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0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 +-------------------------------------------------------------------------1----------- 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 .end diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl index 26fac0d..ad3a526 100644 --- a/Logic/68030_tk.vcl +++ b/Logic/68030_tk.vcl @@ -18,7 +18,7 @@ SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; DATE = 5/24/14; -TIME = 19:56:24; +TIME = 21:59:18; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -120,7 +120,7 @@ Default = High; Type = GLB; [HARDWARE DEVICE OPTIONS] -Zero_Hold_Time = Yes; +Zero_Hold_Time = No; Signature_Word = 0; Pull_up = Yes; Out_Slew_Rate = FAST, SLOW, 0; @@ -128,71 +128,84 @@ Device_max_fanin = 33; Device_max_pterms = 20; Usercode_Format = Hex; +[PIN RESERVATIONS] +layer = OFF; + [LOCATION ASSIGNMENT] Layer = OFF +AS_030 = BIDIR,82,7,-; +LDS_000 = BIDIR,31,3,-; +UDS_000 = BIDIR,32,3,-; +AS_000 = BIDIR,33,3,-; +DS_030 = BIDIR,98,0,-; +SIZE_1_ = BIDIR,79,7,-; DSACK_1_ = BIDIR,81,7,-; +SIZE_0_ = BIDIR,70,6,-; +A0 = BIDIR,69,6,-; DTACK = OUTPUT,30,3,-; -LDS_000 = OUTPUT,31,3,-; -UDS_000 = OUTPUT,32,3,-; -E = OUTPUT,66,6,-; AMIGA_BUS_ENABLE = OUTPUT,34,3,-; +E = OUTPUT,66,6,-; IPL_030_2_ = OUTPUT,9,1,-; IPL_030_0_ = OUTPUT,8,1,-; IPL_030_1_ = OUTPUT,7,1,-; BGACK_030 = OUTPUT,83,7,-; FPU_CS = OUTPUT,78,7,-; +AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-; VMA = OUTPUT,35,3,-; -AS_000 = OUTPUT,33,3,-; BG_000 = OUTPUT,29,3,-; AVEC = OUTPUT,92,0,-; DSACK_0_ = OUTPUT,80,7,-; CLK_DIV_OUT = OUTPUT,65,6,-; -AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-; CIIN = OUTPUT,47,4,-; BERR = OUTPUT,41,4,-; AVEC_EXP = OUTPUT,22,2,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-; CLK_EXP = OUTPUT,10,1,-; RESET = OUTPUT,3,1,-; -inst_CLK_000_D1 = NODE,*,3,-; -inst_CLK_000_D0 = NODE,*,3,-; -SM_AMIGA_7_ = NODE,*,6,-; -cpu_est_1_ = NODE,*,3,-; -RN_E = NODE,-1,6,-; -cpu_est_0_ = NODE,*,7,-; -RN_FPU_CS = NODE,-1,7,-; -SM_AMIGA_4_ = NODE,*,6,-; -SM_AMIGA_6_ = NODE,*,7,-; -inst_AS_030_000_SYNC = NODE,*,7,-; -inst_CLK_OUT_PRE = NODE,*,6,-; -cpu_est_2_ = NODE,*,3,-; -SM_AMIGA_2_ = NODE,*,1,-; -SM_AMIGA_1_ = NODE,*,7,-; -RN_VMA = NODE,-1,3,-; +inst_CLK_000_D0 = NODE,*,4,-; RN_BGACK_030 = NODE,-1,7,-; -RN_AS_000 = NODE,-1,3,-; +inst_CLK_000_D1 = NODE,*,5,-; +inst_BGACK_030_INT_D = NODE,*,5,-; +cpu_est_1_ = NODE,*,6,-; +RN_E = NODE,-1,6,-; +cpu_est_0_ = NODE,*,0,-; +SM_AMIGA_1_ = NODE,*,1,-; +RN_FPU_CS = NODE,-1,7,-; +SM_AMIGA_4_ = NODE,*,0,-; CLK_CNT_P_0_ = NODE,*,6,-; -CLK_CNT_N_0_ = NODE,*,1,-; -SM_AMIGA_5_ = NODE,*,3,-; -CLK_CNT_N_1_ = NODE,*,1,-; -inst_CLK_000_D5 = NODE,*,6,-; -inst_CLK_000_D3 = NODE,*,7,-; +SM_AMIGA_6_ = NODE,*,5,-; +inst_CLK_000_D5 = NODE,*,4,-; inst_CLK_000_D6 = NODE,*,7,-; -inst_CLK_000_D2 = NODE,*,3,-; -inst_VPA_D = NODE,*,1,-; +SM_AMIGA_7_ = NODE,*,5,-; +inst_CLK_OUT_PRE = NODE,*,2,-; +SM_AMIGA_0_ = NODE,*,5,-; +RN_AS_030 = NODE,-1,7,-; +cpu_est_2_ = NODE,*,6,-; +SM_AMIGA_3_ = NODE,*,2,-; +RN_VMA = NODE,-1,3,-; +RN_AS_000 = NODE,-1,3,-; +CLK_CNT_N_0_ = NODE,*,2,-; +SM_AMIGA_5_ = NODE,*,0,-; +inst_VPA_SYNC = NODE,*,2,-; +inst_DTACK_SYNC = NODE,*,2,-; +CLK_CNT_P_1_ = NODE,*,4,-; +inst_CLK_000_D2 = NODE,*,0,-; RN_LDS_000 = NODE,-1,3,-; +RN_AMIGA_BUS_ENABLE = NODE,-1,3,-; +inst_AS_030_000_SYNC = NODE,*,5,-; RN_UDS_000 = NODE,-1,3,-; -SM_AMIGA_0_ = NODE,*,6,-; +RN_DS_030 = NODE,-1,0,-; +RN_IPL_030_2_ = NODE,-1,1,-; +RN_SIZE_1_ = NODE,-1,7,-; RN_IPL_030_0_ = NODE,-1,1,-; RN_IPL_030_1_ = NODE,-1,1,-; -RN_AMIGA_BUS_ENABLE = NODE,-1,3,-; -RN_IPL_030_2_ = NODE,-1,1,-; -SM_AMIGA_3_ = NODE,*,1,-; +SM_AMIGA_2_ = NODE,*,1,-; +RN_SIZE_0_ = NODE,-1,6,-; RN_BG_000 = NODE,-1,3,-; +RN_A0 = NODE,-1,6,-; RN_DSACK_1_ = NODE,-1,7,-; -inst_VPA_SYNC = NODE,*,1,-; -inst_DTACK_SYNC = NODE,*,1,-; -inst_CLK_000_D4 = NODE,*,7,-; -CLK_CNT_P_1_ = NODE,*,7,-; +inst_CLK_000_D4 = NODE,*,5,-; +CLK_CNT_N_1_ = NODE,*,0,-; +inst_CLK_000_D3 = NODE,*,4,-; CLK_OSZI = INPUT,61,-,-; diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco index 9b675f4..9892544 100644 --- a/Logic/68030_tk.vco +++ b/Logic/68030_tk.vco @@ -18,7 +18,7 @@ SDS_file = m4a5.sds; Design = 68030_tk.tt4; Rev = 0.01; DATE = 5/24/14; -TIME = 19:56:24; +TIME = 21:59:18; Type = TT2; Pre_Fit_Time = 1; Source_Format = Pure_VHDL; @@ -120,7 +120,7 @@ Default = High; Type = GLB; [HARDWARE DEVICE OPTIONS] -Zero_Hold_Time = Yes; +Zero_Hold_Time = No; Signature_Word = 0; Pull_up = Yes; Out_Slew_Rate = FAST, SLOW, 0; @@ -128,39 +128,28 @@ Device_max_fanin = 33; Device_max_pterms = 20; Usercode_Format = Hex; +[PIN RESERVATIONS] +layer = OFF; + [LOCATION ASSIGNMENT] Layer = OFF; -SIZE_1_ = INPUT,79, H,-; +IPL_1_ = INPUT,56, F,-; +IPL_0_ = INPUT,67, G,-; A_31_ = INPUT,4, B,-; +DSACK_0_ = OUTPUT,80, H,-; +FC_0_ = INPUT,57, F,-; IPL_2_ = INPUT,68, G,-; FC_1_ = INPUT,58, F,-; -AS_030 = INPUT,82, H,-; -SIZE_0_ = INPUT,70, G,-; -DS_030 = INPUT,98, A,-; -A_30_ = INPUT,5, B,-; -A_29_ = INPUT,6, B,-; -A_28_ = INPUT,15, C,-; nEXP_SPACE = INPUT,14,-,-; -A_27_ = INPUT,16, C,-; BERR = OUTPUT,41, E,-; -A_26_ = INPUT,17, C,-; BG_030 = INPUT,21, C,-; -A_25_ = INPUT,18, C,-; -A_24_ = INPUT,19, C,-; -A_23_ = INPUT,84, H,-; BGACK_000 = INPUT,28, D,-; -A_22_ = INPUT,85, H,-; CLK_030 = INPUT,64,-,-; -A_21_ = INPUT,94, A,-; CLK_000 = INPUT,11,-,-; -A_20_ = INPUT,93, A,-; CLK_OSZI = INPUT,61,-,-; -A_19_ = INPUT,97, A,-; CLK_DIV_OUT = OUTPUT,65, G,-; -A_18_ = INPUT,95, A,-; -A_17_ = INPUT,59, F,-; -A_16_ = INPUT,96, A,-; +DTACK = BIDIR,30, D,-; AVEC = OUTPUT,92, A,-; AVEC_EXP = OUTPUT,22, C,-; VPA = INPUT,36,-,-; @@ -169,51 +158,65 @@ RW = INPUT,71, G,-; AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; CIIN = OUTPUT,47, E,-; -A_0_ = INPUT,69, G,-; -IPL_1_ = INPUT,56, F,-; -IPL_0_ = INPUT,67, G,-; -DSACK_0_ = OUTPUT,80, H,-; -FC_0_ = INPUT,57, F,-; +A_30_ = INPUT,5, B,-; +A_29_ = INPUT,6, B,-; +A_28_ = INPUT,15, C,-; +A_27_ = INPUT,16, C,-; +A_26_ = INPUT,17, C,-; +A_25_ = INPUT,18, C,-; +A_24_ = INPUT,19, C,-; +A_23_ = INPUT,84, H,-; +A_22_ = INPUT,85, H,-; +A_21_ = INPUT,94, A,-; +A_20_ = INPUT,93, A,-; +A_19_ = INPUT,97, A,-; +A_18_ = INPUT,95, A,-; +A_17_ = INPUT,59, F,-; +A_16_ = INPUT,96, A,-; +IPL_030_1_ = OUTPUT,7, B,-; +IPL_030_0_ = OUTPUT,8, B,-; +SIZE_1_ = BIDIR,79, H,-; IPL_030_2_ = OUTPUT,9, B,-; DSACK_1_ = BIDIR,81, H,-; -AS_000 = OUTPUT,33, D,-; -UDS_000 = OUTPUT,32, D,-; -LDS_000 = OUTPUT,31, D,-; +AS_030 = BIDIR,82, H,-; +AS_000 = BIDIR,33, D,-; +DS_030 = BIDIR,98, A,-; +UDS_000 = BIDIR,32, D,-; +LDS_000 = BIDIR,31, D,-; +A0 = BIDIR,69, G,-; BG_000 = OUTPUT,29, D,-; BGACK_030 = OUTPUT,83, H,-; CLK_EXP = OUTPUT,10, B,-; FPU_CS = OUTPUT,78, H,-; -DTACK = BIDIR,30, D,-; E = OUTPUT,66, G,-; VMA = OUTPUT,35, D,-; RESET = OUTPUT,3, B,-; AMIGA_BUS_ENABLE = OUTPUT,34, D,-; -IPL_030_1_ = OUTPUT,7, B,-; -IPL_030_0_ = OUTPUT,8, B,-; -inst_AS_030_000_SYNC = NODE,9, H,-; -inst_DTACK_SYNC = NODE,14, B,-; -inst_VPA_D = NODE,2, B,-; -inst_VPA_SYNC = NODE,10, B,-; -inst_CLK_000_D0 = NODE,2, D,-; -inst_CLK_000_D1 = NODE,9, D,-; -inst_CLK_000_D2 = NODE,3, D,-; -inst_CLK_000_D6 = NODE,6, H,-; -SM_AMIGA_5_ = NODE,14, D,-; -SM_AMIGA_6_ = NODE,5, H,-; -inst_CLK_000_D3 = NODE,2, H,-; -SM_AMIGA_4_ = NODE,12, G,-; -inst_CLK_000_D5 = NODE,9, G,-; -SM_AMIGA_7_ = NODE,8, G,-; -SM_AMIGA_3_ = NODE,6, B,-; -SM_AMIGA_1_ = NODE,13, H,-; -CLK_CNT_N_0_ = NODE,9, B,-; -CLK_CNT_N_1_ = NODE,13, B,-; +SIZE_0_ = BIDIR,70, G,-; +inst_AS_030_000_SYNC = NODE,5, F,-; +inst_BGACK_030_INT_D = NODE,4, F,-; +inst_DTACK_SYNC = NODE,9, C,-; +inst_VPA_SYNC = NODE,5, C,-; +inst_CLK_000_D0 = NODE,8, E,-; +inst_CLK_000_D1 = NODE,0, F,-; +inst_CLK_000_D2 = NODE,5, A,-; +inst_CLK_000_D6 = NODE,5, H,-; +SM_AMIGA_5_ = NODE,1, A,-; +SM_AMIGA_6_ = NODE,8, F,-; +inst_CLK_000_D3 = NODE,9, E,-; +inst_CLK_000_D5 = NODE,1, E,-; +SM_AMIGA_3_ = NODE,8, C,-; +SM_AMIGA_0_ = NODE,1, F,-; +SM_AMIGA_1_ = NODE,5, B,-; +CLK_CNT_N_0_ = NODE,1, C,-; +CLK_CNT_N_1_ = NODE,9, A,-; CLK_CNT_P_0_ = NODE,5, G,-; -CLK_CNT_P_1_ = NODE,14, H,-; -SM_AMIGA_2_ = NODE,5, B,-; -SM_AMIGA_0_ = NODE,13, G,-; -inst_CLK_000_D4 = NODE,10, H,-; -inst_CLK_OUT_PRE = NODE,1, G,-; -cpu_est_0_ = NODE,1, H,-; -cpu_est_1_ = NODE,6, D,-; -cpu_est_2_ = NODE,10, D,-; +CLK_CNT_P_1_ = NODE,5, E,-; +inst_CLK_000_D4 = NODE,9, F,-; +SM_AMIGA_7_ = NODE,12, F,-; +SM_AMIGA_4_ = NODE,12, A,-; +inst_CLK_OUT_PRE = NODE,4, C,-; +SM_AMIGA_2_ = NODE,9, B,-; +cpu_est_0_ = NODE,8, A,-; +cpu_est_1_ = NODE,12, G,-; +cpu_est_2_ = NODE,9, G,-; diff --git a/Logic/68030_tk.vct b/Logic/68030_tk.vct index d02bbc5..ca85bcb 100644 --- a/Logic/68030_tk.vct +++ b/Logic/68030_tk.vct @@ -15,8 +15,8 @@ Voltage = 5.0; RCS = "$Revision: 1.2 $"; Parent = m4a5.lci; SDS_File = m4a5.sds; -DATE = 05/15/2014; -TIME = 12:30:11; +DATE = 05/24/2014; +TIME = 21:28:20; Source_Format = Pure_VHDL; Type = TT2; Pre_Fit_Time = 1; @@ -101,7 +101,7 @@ Routing_Attempts = 2; Conf_Unused_IOs = Out_Low; [HARDWARE DEVICE OPTIONS] -Zero_Hold_Time = Yes; +Zero_Hold_Time = No; Signature_Word = 0; Pull_up = Yes; Out_Slew_Rate = FAST,SLOW,0; @@ -173,6 +173,8 @@ A_31_ = input,4,B,-; DS_030 = input,98,A,-; AVEC_EXP = input,22,C,-; BERR = input,41,E,-; +nEXP_SPACE = input,14,-,-; +A0 = input,69,G,-; [GROUP ASSIGNMENT] Layer = OFF; diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf index eccdd4d..32d990c 100644 --- a/Logic/68030_tk.xrf +++ b/Logic/68030_tk.xrf @@ -2,7 +2,7 @@ Signal Name Cross Reference File ispLEVER Classic 1.7.00.05.28.13 -Design '68030_tk' created Sat May 24 19:56:20 2014 +Design '68030_tk' created Sat May 24 21:59:14 2014 LEGEND: '>' Functional Block Port Separator diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0 index 087be5c..00c2f13 100644 --- a/Logic/BUS68030.bl0 +++ b/Logic/BUS68030.bl0 @@ -1,1122 +1,1246 @@ -#$ DATE Sat May 24 19:56:20 2014 +#$ DATE Sat May 24 21:59:14 2014 #$ TOOL EDIF2BLIF version IspLever 1.0 #$ MODULE bus68030 -#$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 SIZE_0_ DS_030 A_30_ UDS_000 A_29_ LDS_000 A_28_ nEXP_SPACE A_27_ BERR A_26_ BG_030 A_25_ BG_000 A_24_ BGACK_030 A_23_ BGACK_000 A_22_ CLK_030 A_21_ CLK_000 A_20_ CLK_OSZI A_19_ CLK_DIV_OUT A_18_ CLK_EXP A_17_ FPU_CS A_16_ DTACK A_15_ AVEC A_14_ AVEC_EXP A_13_ E A_12_ VPA A_11_ VMA A_10_ RST A_9_ RESET A_8_ RW A_7_ AMIGA_BUS_ENABLE A_6_ AMIGA_BUS_DATA_DIR A_5_ AMIGA_BUS_ENABLE_LOW A_4_ CIIN A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ -#$ NODES 365 CLK_000_c CLK_OSZI_c CLK_OUT_INTreg inst_BGACK_030_INTreg inst_FPU_CS_INTreg IPL_030DFFSH_0_reg inst_VMA_INTreg inst_AS_000_INTreg IPL_030DFFSH_1_reg inst_AS_030_000_SYNC \ -# inst_DTACK_SYNC IPL_030DFFSH_2_reg inst_VPA_D inst_VPA_SYNC ipl_c_0__n inst_CLK_000_D0 inst_CLK_000_D1 ipl_c_1__n inst_CLK_000_D2 inst_CLK_000_D6 \ -# ipl_c_2__n SM_AMIGA_5_ SM_AMIGA_6_ vcc_n_n dsack_c_1__n gnd_n_n inst_UDS_000_INTreg DTACK_c inst_LDS_000_INTreg DSACK_INT_1_ \ -# AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n inst_CLK_000_D3 SM_AMIGA_4_ state_machine_un23_clk_000_d0_n state_machine_un6_clk_000_d5_n RST_c inst_CLK_000_D5 SM_AMIGA_7_ RESETDFFRHreg \ -# SM_AMIGA_3_ state_machine_un6_bgack_000_n RW_c SM_AMIGA_1_ inst_DTACK_DMA fc_c_0__n G_102 CLK_CNT_N_0_ fc_c_1__n CLK_CNT_N_1_ \ -# G_108 AMIGA_BUS_ENABLEDFFreg CLK_CNT_P_0_ CLK_CNT_P_1_ SM_AMIGA_2_ SM_AMIGA_0_ state_machine_un10_bg_030_n cpu_est_ns_0_1__n state_machine_un7_as_000_int_n N_129_i \ -# inst_CLK_000_D4 N_131_i state_machine_un15_clk_000_d0_n N_221_i state_machine_lds_000_int_5_n N_222_i state_machine_uds_000_int_5_n N_63_0 un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_62_0 \ -# inst_CLK_OUT_PRE N_132_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_60_i N_59_i N_57_i N_56_i N_55_i CLK_000_D1_i \ -# N_54_i N_51_i N_50_i N_125_i N_126_i cpu_est_ns_e_0_0__n N_85_i N_123_i N_124_i sm_amiga_ns_0_0__n \ -# cpu_est_0_ N_122_i cpu_est_1_ N_227_i cpu_est_2_ N_228_i cpu_est_3_reg cpu_est_ns_0_2__n N_226_i N_44_i \ -# N_130_i N_225_i cpu_est_ns_1__n N_158_i cpu_est_ns_2__n N_219_i N_204 N_220_i N_205 sm_amiga_ns_0_7__n \ -# N_206 N_215_i N_26 N_216_i N_30 N_49 N_95_i N_50 N_214_i N_51 \ -# sm_amiga_ns_0_5__n N_54 N_94_i N_55 N_133_i N_56 N_57 N_87_i N_59 N_60 \ -# N_86_i N_62 N_63 N_83_i N_68 N_70 N_82_i N_72 state_machine_lds_000_int_5_0_n N_73 \ -# state_machine_uds_000_int_5_0_n N_74 N_80_i N_76 N_30_0 N_78 N_26_0 N_80 N_76_i N_82 \ -# N_206_0 N_83 N_205_0 N_85 N_72_i N_86 N_73_i N_87 state_machine_un15_clk_000_d0_0_n N_94 \ -# N_204_0 N_95 BG_030_c_i N_214 N_70_i N_215 state_machine_un10_bg_030_0_n N_216 state_machine_un6_bgack_000_0_n N_219 \ -# N_220 state_machine_un23_clk_000_d0_0_n N_221 N_236_1 N_222 N_236_2 N_225 N_236_3 N_226 N_236_4 \ -# N_227 N_236_5 N_228 N_236_6 N_122 N_239_1 N_123 N_239_2 N_124 state_machine_un8_clk_000_d2_1_n \ -# N_125 N_55_i_1 N_126 N_55_i_2 N_129 N_55_i_3 N_130 N_55_i_4 N_131 N_55_i_5 \ -# N_132 cpu_est_ns_0_1_1__n N_133 cpu_est_ns_0_2_1__n N_236 N_80_1 N_239 N_80_2 RW_i N_78_1 \ -# VMA_INT_i N_78_2 VPA_D_i N_74_1 DTACK_i N_74_2 CLK_000_D0_i N_74_3 sm_amiga_i_4__n N_70_1 \ -# cpu_est_i_3__n N_70_2 sm_amiga_i_1__n sm_amiga_ns_0_1_0__n state_machine_un6_clk_000_d5_i_n cpu_est_ns_0_1_2__n sm_amiga_i_6__n N_226_1 nEXP_SPACE_i N_220_1 \ -# AS_000_INT_i N_82_1 cpu_est_i_1__n N_73_1 cpu_est_i_0__n N_72_1 AMIGA_BUS_ENABLE_i state_machine_uds_000_int_5_0_m2_un3_n AS_030_i state_machine_uds_000_int_5_0_m2_un1_n \ -# cpu_est_i_2__n state_machine_uds_000_int_5_0_m2_un0_n sm_amiga_i_2__n vpa_sync_0_un3_n sm_amiga_i_3__n vpa_sync_0_un1_n sm_amiga_i_5__n vpa_sync_0_un0_n state_machine_un8_clk_000_d2_i_n vma_int_0_un3_n \ -# sm_amiga_i_7__n vma_int_0_un1_n a_i_0__n vma_int_0_un0_n size_i_1__n bg_000_0_un3_n dsack_i_1__n bg_000_0_un1_n BGACK_030_INT_i bg_000_0_un0_n \ -# CLK_000_D2_i bgack_030_int_0_un3_n AS_030_000_SYNC_i bgack_030_int_0_un1_n a_i_19__n bgack_030_int_0_un0_n a_i_16__n as_000_int_0_un3_n a_i_18__n as_000_int_0_un1_n \ -# a_i_30__n as_000_int_0_un0_n a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n a_i_29__n ipl_030_0_0__un0_n a_i_26__n ipl_030_0_1__un3_n \ -# a_i_27__n ipl_030_0_1__un1_n a_i_24__n ipl_030_0_1__un0_n a_i_25__n ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n ipl_030_0_2__un0_n cpu_estse_0_un3_n \ -# CLK_OSZI_i cpu_estse_0_un1_n cpu_estse_0_un0_n N_74_i cpu_estse_1_un3_n N_78_i cpu_estse_1_un1_n FPU_CS_INT_i cpu_estse_1_un0_n CLK_000_D6_i \ -# cpu_estse_2_un3_n AS_030_c cpu_estse_2_un1_n cpu_estse_2_un0_n as_030_000_sync_0_un3_n DS_030_c as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n \ -# size_c_0__n dtack_sync_0_un0_n fpu_cs_int_0_un3_n size_c_1__n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n a_c_0__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n \ -# amiga_bus_enable_0_un3_n amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n a_15__n \ -# a_14__n a_13__n a_c_16__n a_12__n a_c_17__n a_11__n a_c_18__n a_10__n a_c_19__n a_9__n \ -# a_c_20__n a_8__n a_c_21__n a_7__n a_c_22__n a_6__n a_c_23__n a_5__n a_c_24__n a_4__n \ -# a_c_25__n a_3__n a_c_26__n a_2__n a_c_27__n a_1__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n \ -# nEXP_SPACE_c BG_030_c BG_000DFFSHreg BGACK_000_c CLK_030_c +#$ PINS 59 IPL_030_1_ IPL_030_0_ SIZE_1_ IPL_1_ IPL_0_ A_31_ DSACK_0_ FC_0_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ +#$ NODES 398 BG_030_c BG_000DFFSHreg BGACK_000_c inst_BGACK_030_INTreg inst_FPU_CS_INTreg CLK_030_c inst_VMA_INTreg inst_AS_030_000_SYNC CLK_000_c inst_BGACK_030_INT_D \ +# inst_DTACK_SYNC CLK_OSZI_c inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 CLK_OUT_INTreg inst_CLK_000_D2 inst_CLK_000_D6 SM_AMIGA_5_ IPL_030DFFSH_0_reg \ +# vcc_n_n gnd_n_n IPL_030DFFSH_1_reg inst_AS_000_INT SM_AMIGA_6_ IPL_030DFFSH_2_reg inst_UDS_000_INT inst_LDS_000_INT ipl_c_0__n inst_DSACK1_INT \ +# inst_CLK_000_D3 ipl_c_1__n state_machine_un23_clk_000_d0_n inst_CLK_000_D5 ipl_c_2__n SM_AMIGA_3_ SM_AMIGA_0_ SM_AMIGA_1_ dsack_c_1__n inst_AS_000_DMA \ +# inst_DS_000_DMA DTACK_c SIZE_DMA_0_ SIZE_DMA_1_ inst_A0_DMA G_103 CLK_CNT_N_0_ VPA_c CLK_CNT_N_1_ G_109 \ +# CLK_CNT_P_0_ RST_c CLK_CNT_P_1_ inst_CLK_000_D4 RESETDFFRHreg SM_AMIGA_7_ state_machine_un15_clk_000_d0_n RW_c SM_AMIGA_4_ un1_AMIGA_BUS_ENABLE_0_sqmuxa_2 \ +# fc_c_0__n inst_CLK_OUT_PRE SM_AMIGA_2_ fc_c_1__n AMIGA_BUS_ENABLEDFFSHreg state_machine_un23_clk_000_d0_0_n state_machine_un6_bgack_000_0_n N_214_0 BG_030_c_i N_227_i \ +# state_machine_un10_bg_030_0_n N_215_0 N_216_0 N_126_i N_33_0 N_127_i N_35_0 state_machine_uds_000_int_5_0_n N_130_i state_machine_lds_000_int_5_0_n \ +# N_132_i N_131_i cpu_est_0_ cpu_est_1_ N_133_i cpu_est_2_ cpu_est_3_reg N_134_i N_137_i N_138_i \ +# sm_amiga_ns_0_5__n cpu_est_ns_1__n N_139_i cpu_est_ns_2__n N_140_i N_46_0 N_52 N_142_i N_59 N_141_i \ +# N_62 sm_amiga_ns_0_7__n N_65 N_144_i N_67 state_machine_ds_000_dma_5_0_n N_72 CLK_030_c_i N_77 AS_000_c_i \ +# N_88 N_59_i N_217 N_61_0 N_219 N_62_i N_221 CLK_000_D1_i N_224 N_65_i \ +# N_225 N_66_i N_226 N_67_i N_128 N_175_i N_130 un1_as_000_dma5_i_0__n N_132 state_machine_un6_clk_000_d5_i_n \ +# N_135 N_71_i N_136 DS_030_c_i N_138 N_73_i N_143 N_156_i N_145 un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i \ +# N_146 N_75_0 N_147 N_176_i N_148 N_52_0 N_151 N_173_i N_153 N_226_i \ +# N_154 N_77_0 N_155 N_72_i N_173 N_147_i cpu_est_ns_0_0_x2_1_ N_148_i AMIGA_BUS_DATA_DIR_m1_0_x2 cpu_est_ns_e_0_0__n \ +# N_228_1 N_146_i N_237 sm_amiga_ns_0_0__n N_247 N_88_i N_227 N_145_i N_228 cpu_est_ns_0_2__n \ +# N_127 N_143_i N_66 N_154_i N_175 N_161_i N_176 N_153_i N_75 N_155_i \ +# un1_AMIGA_BUS_ENABLE_1_sqmuxa_4 cpu_est_ns_0_1__n N_61 N_135_i N_156 N_136_i N_73 N_57 N_225_i N_71 \ +# un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0 state_machine_un6_clk_000_d5_n N_219_i un1_as_000_dma5_0__n N_221_i N_223 state_machine_un15_clk_000_d0_0_n state_machine_ds_000_dma_5_n N_144 N_66_i_1 \ +# N_141 N_66_i_2 N_142 N_66_i_3 N_139 N_66_i_4 N_140 N_66_i_5 N_137 N_237_1 \ +# N_134 N_237_2 N_133 N_247_1 N_131 N_247_2 state_machine_lds_000_int_5_n N_247_3 state_machine_uds_000_int_5_n N_247_4 \ +# N_35 N_247_5 N_33 N_247_6 N_126 N_52_0_1 N_216 N_52_0_2 N_215 N_224_1 \ +# state_machine_un10_bg_030_n N_224_2 N_214 N_227_1 state_machine_un6_bgack_000_n N_227_2 state_machine_un8_clk_000_d2_n N_228_1_0 SIZE_DMA_1_sqmuxa N_127_1 \ +# SIZE_DMA_0_sqmuxa N_127_2 AS_000_INT_1_sqmuxa N_151_1 N_249 SIZE_DMA_1_sqmuxa_1 CLK_000_D6_i state_machine_un8_clk_000_d2_1_n N_228_i sm_amiga_ns_0_1_0__n \ +# sm_amiga_i_5__n cpu_est_ns_0_1_1__n N_224_i N_138_1 N_223_i N_130_1 SIZE_DMA_0_sqmuxa_i N_128_1 SIZE_DMA_1_sqmuxa_i N_221_1 \ +# a_i_18__n N_219_1 a_i_16__n vpa_sync_0_un3_n a_i_19__n vpa_sync_0_un1_n AS_030_000_SYNC_i vpa_sync_0_un0_n CLK_000_D2_i as_000_int_0_un3_n \ +# BGACK_030_INT_i as_000_int_0_un1_n nEXP_SPACE_i as_000_int_0_un0_n AS_030_i as_000_dma_0_un3_n BGACK_030_INT_D_i as_000_dma_0_un1_n sm_amiga_i_7__n as_000_dma_0_un0_n \ +# state_machine_un8_clk_000_d2_i_n bg_000_0_un3_n sm_amiga_i_6__n bg_000_0_un1_n sm_amiga_i_4__n bg_000_0_un0_n CLK_000_D0_i a0_dma_0_un3_n RW_i a0_dma_0_un1_n \ +# UDS_000_i a0_dma_0_un0_n LDS_000_i dtack_sync_0_un3_n DTACK_i dtack_sync_0_un1_n VMA_INT_i dtack_sync_0_un0_n VPA_i lds_000_int_0_un3_n \ +# cpu_est_i_0__n lds_000_int_0_un1_n sm_amiga_i_3__n lds_000_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n cpu_est_i_1__n uds_000_int_0_un1_n A0_i uds_000_int_0_un0_n \ +# size_i_1__n fpu_cs_int_0_un3_n a_i_30__n fpu_cs_int_0_un1_n a_i_31__n fpu_cs_int_0_un0_n a_i_28__n ds_000_dma_0_un3_n a_i_29__n ds_000_dma_0_un1_n \ +# a_i_26__n ds_000_dma_0_un0_n a_i_27__n as_030_000_sync_0_un3_n a_i_24__n as_030_000_sync_0_un1_n a_i_25__n as_030_000_sync_0_un0_n RST_i size_dma_0_1__un3_n \ +# size_dma_0_1__un1_n CLK_OSZI_i size_dma_0_1__un0_n size_dma_0_0__un3_n FPU_CS_INT_i size_dma_0_0__un1_n AS_030_c size_dma_0_0__un0_n bgack_030_int_0_un3_n AS_000_c \ +# bgack_030_int_0_un1_n bgack_030_int_0_un0_n DS_030_c dsack1_int_0_un3_n dsack1_int_0_un1_n UDS_000_c dsack1_int_0_un0_n state_machine_uds_000_int_5_0_m2_un3_n LDS_000_c state_machine_uds_000_int_5_0_m2_un1_n \ +# state_machine_uds_000_int_5_0_m2_un0_n size_c_0__n cpu_est_ns_0_0_m2_2__un3_n cpu_est_ns_0_0_m2_2__un1_n size_c_1__n cpu_est_ns_0_0_m2_2__un0_n amiga_bus_enable_0_un3_n a_c_16__n amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n \ +# a_c_17__n vma_int_0_un3_n vma_int_0_un1_n a_c_18__n vma_int_0_un0_n ipl_030_0_0__un3_n a_c_19__n ipl_030_0_0__un1_n ipl_030_0_0__un0_n a_c_20__n \ +# ipl_030_0_1__un3_n ipl_030_0_1__un1_n a_c_21__n ipl_030_0_1__un0_n ipl_030_0_2__un3_n a_c_22__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n a_c_23__n cpu_estse_0_un3_n \ +# cpu_estse_0_un1_n a_c_24__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_25__n cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_26__n cpu_estse_2_un3_n cpu_estse_2_un1_n \ +# a_c_27__n cpu_estse_2_un0_n a_c_28__n a_c_29__n a_c_30__n a_c_31__n A0_c nEXP_SPACE_c .model bus68030 -.inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF \ - CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \ - A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \ - A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF \ - A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF \ - A_1_.BLIF A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF DSACK_0_.BLIF CLK_000_c.BLIF CLK_OSZI_c.BLIF CLK_OUT_INTreg.BLIF inst_BGACK_030_INTreg.BLIF \ - inst_FPU_CS_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF inst_VMA_INTreg.BLIF inst_AS_000_INTreg.BLIF IPL_030DFFSH_1_reg.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF IPL_030DFFSH_2_reg.BLIF inst_VPA_D.BLIF \ - inst_VPA_SYNC.BLIF ipl_c_0__n.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF ipl_c_1__n.BLIF inst_CLK_000_D2.BLIF inst_CLK_000_D6.BLIF ipl_c_2__n.BLIF SM_AMIGA_5_.BLIF \ - SM_AMIGA_6_.BLIF vcc_n_n.BLIF dsack_c_1__n.BLIF gnd_n_n.BLIF inst_UDS_000_INTreg.BLIF DTACK_c.BLIF inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF AS_000_INT_1_sqmuxa.BLIF \ - state_machine_un8_clk_000_d2_n.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF state_machine_un23_clk_000_d0_n.BLIF state_machine_un6_clk_000_d5_n.BLIF RST_c.BLIF inst_CLK_000_D5.BLIF SM_AMIGA_7_.BLIF RESETDFFRHreg.BLIF \ - SM_AMIGA_3_.BLIF state_machine_un6_bgack_000_n.BLIF RW_c.BLIF SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF fc_c_0__n.BLIF G_102.BLIF CLK_CNT_N_0_.BLIF fc_c_1__n.BLIF \ - CLK_CNT_N_1_.BLIF G_108.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF state_machine_un10_bg_030_n.BLIF cpu_est_ns_0_1__n.BLIF \ - state_machine_un7_as_000_int_n.BLIF N_129_i.BLIF inst_CLK_000_D4.BLIF N_131_i.BLIF state_machine_un15_clk_000_d0_n.BLIF N_221_i.BLIF state_machine_lds_000_int_5_n.BLIF N_222_i.BLIF state_machine_uds_000_int_5_n.BLIF \ - N_63_0.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_62_0.BLIF inst_CLK_OUT_PRE.BLIF N_132_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF DS_030_c_i.BLIF N_60_i.BLIF N_59_i.BLIF \ - N_57_i.BLIF N_56_i.BLIF N_55_i.BLIF CLK_000_D1_i.BLIF N_54_i.BLIF N_51_i.BLIF N_50_i.BLIF N_125_i.BLIF N_126_i.BLIF \ - cpu_est_ns_e_0_0__n.BLIF N_85_i.BLIF N_123_i.BLIF N_124_i.BLIF sm_amiga_ns_0_0__n.BLIF cpu_est_0_.BLIF N_122_i.BLIF cpu_est_1_.BLIF N_227_i.BLIF \ - cpu_est_2_.BLIF N_228_i.BLIF cpu_est_3_reg.BLIF cpu_est_ns_0_2__n.BLIF N_226_i.BLIF N_44_i.BLIF N_130_i.BLIF N_225_i.BLIF cpu_est_ns_1__n.BLIF \ - N_158_i.BLIF cpu_est_ns_2__n.BLIF N_219_i.BLIF N_204.BLIF N_220_i.BLIF N_205.BLIF sm_amiga_ns_0_7__n.BLIF N_206.BLIF N_215_i.BLIF \ - N_26.BLIF N_216_i.BLIF N_30.BLIF N_49.BLIF N_95_i.BLIF N_50.BLIF N_214_i.BLIF N_51.BLIF sm_amiga_ns_0_5__n.BLIF \ - N_54.BLIF N_94_i.BLIF N_55.BLIF N_133_i.BLIF N_56.BLIF N_57.BLIF N_87_i.BLIF N_59.BLIF N_60.BLIF \ - N_86_i.BLIF N_62.BLIF N_63.BLIF N_83_i.BLIF N_68.BLIF N_70.BLIF N_82_i.BLIF N_72.BLIF state_machine_lds_000_int_5_0_n.BLIF \ - N_73.BLIF state_machine_uds_000_int_5_0_n.BLIF N_74.BLIF N_80_i.BLIF N_76.BLIF N_30_0.BLIF N_78.BLIF N_26_0.BLIF N_80.BLIF \ - N_76_i.BLIF N_82.BLIF N_206_0.BLIF N_83.BLIF N_205_0.BLIF N_85.BLIF N_72_i.BLIF N_86.BLIF N_73_i.BLIF \ - N_87.BLIF state_machine_un15_clk_000_d0_0_n.BLIF N_94.BLIF N_204_0.BLIF N_95.BLIF BG_030_c_i.BLIF N_214.BLIF N_70_i.BLIF N_215.BLIF \ - state_machine_un10_bg_030_0_n.BLIF N_216.BLIF state_machine_un6_bgack_000_0_n.BLIF N_219.BLIF N_220.BLIF state_machine_un23_clk_000_d0_0_n.BLIF N_221.BLIF N_236_1.BLIF N_222.BLIF \ - N_236_2.BLIF N_225.BLIF N_236_3.BLIF N_226.BLIF N_236_4.BLIF N_227.BLIF N_236_5.BLIF N_228.BLIF N_236_6.BLIF \ - N_122.BLIF N_239_1.BLIF N_123.BLIF N_239_2.BLIF N_124.BLIF state_machine_un8_clk_000_d2_1_n.BLIF N_125.BLIF N_55_i_1.BLIF N_126.BLIF \ - N_55_i_2.BLIF N_129.BLIF N_55_i_3.BLIF N_130.BLIF N_55_i_4.BLIF N_131.BLIF N_55_i_5.BLIF N_132.BLIF cpu_est_ns_0_1_1__n.BLIF \ - N_133.BLIF cpu_est_ns_0_2_1__n.BLIF N_236.BLIF N_80_1.BLIF N_239.BLIF N_80_2.BLIF RW_i.BLIF N_78_1.BLIF VMA_INT_i.BLIF \ - N_78_2.BLIF VPA_D_i.BLIF N_74_1.BLIF DTACK_i.BLIF N_74_2.BLIF CLK_000_D0_i.BLIF N_74_3.BLIF sm_amiga_i_4__n.BLIF N_70_1.BLIF \ - cpu_est_i_3__n.BLIF N_70_2.BLIF sm_amiga_i_1__n.BLIF sm_amiga_ns_0_1_0__n.BLIF state_machine_un6_clk_000_d5_i_n.BLIF cpu_est_ns_0_1_2__n.BLIF sm_amiga_i_6__n.BLIF N_226_1.BLIF nEXP_SPACE_i.BLIF \ - N_220_1.BLIF AS_000_INT_i.BLIF N_82_1.BLIF cpu_est_i_1__n.BLIF N_73_1.BLIF cpu_est_i_0__n.BLIF N_72_1.BLIF AMIGA_BUS_ENABLE_i.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF \ - AS_030_i.BLIF state_machine_uds_000_int_5_0_m2_un1_n.BLIF cpu_est_i_2__n.BLIF state_machine_uds_000_int_5_0_m2_un0_n.BLIF sm_amiga_i_2__n.BLIF vpa_sync_0_un3_n.BLIF sm_amiga_i_3__n.BLIF vpa_sync_0_un1_n.BLIF sm_amiga_i_5__n.BLIF \ - vpa_sync_0_un0_n.BLIF state_machine_un8_clk_000_d2_i_n.BLIF vma_int_0_un3_n.BLIF sm_amiga_i_7__n.BLIF vma_int_0_un1_n.BLIF a_i_0__n.BLIF vma_int_0_un0_n.BLIF size_i_1__n.BLIF bg_000_0_un3_n.BLIF \ - dsack_i_1__n.BLIF bg_000_0_un1_n.BLIF BGACK_030_INT_i.BLIF bg_000_0_un0_n.BLIF CLK_000_D2_i.BLIF bgack_030_int_0_un3_n.BLIF AS_030_000_SYNC_i.BLIF bgack_030_int_0_un1_n.BLIF a_i_19__n.BLIF \ - bgack_030_int_0_un0_n.BLIF a_i_16__n.BLIF as_000_int_0_un3_n.BLIF a_i_18__n.BLIF as_000_int_0_un1_n.BLIF a_i_30__n.BLIF as_000_int_0_un0_n.BLIF a_i_31__n.BLIF ipl_030_0_0__un3_n.BLIF \ - a_i_28__n.BLIF ipl_030_0_0__un1_n.BLIF a_i_29__n.BLIF ipl_030_0_0__un0_n.BLIF a_i_26__n.BLIF ipl_030_0_1__un3_n.BLIF a_i_27__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_24__n.BLIF \ - ipl_030_0_1__un0_n.BLIF a_i_25__n.BLIF ipl_030_0_2__un3_n.BLIF RST_i.BLIF ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF cpu_estse_0_un3_n.BLIF CLK_OSZI_i.BLIF cpu_estse_0_un1_n.BLIF \ - cpu_estse_0_un0_n.BLIF N_74_i.BLIF cpu_estse_1_un3_n.BLIF N_78_i.BLIF cpu_estse_1_un1_n.BLIF FPU_CS_INT_i.BLIF cpu_estse_1_un0_n.BLIF CLK_000_D6_i.BLIF cpu_estse_2_un3_n.BLIF \ - AS_030_c.BLIF cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF as_030_000_sync_0_un3_n.BLIF DS_030_c.BLIF as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF \ - size_c_0__n.BLIF dtack_sync_0_un0_n.BLIF fpu_cs_int_0_un3_n.BLIF size_c_1__n.BLIF fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF a_c_0__n.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF \ - dsack_int_0_1__un0_n.BLIF amiga_bus_enable_0_un3_n.BLIF amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un1_n.BLIF \ - lds_000_int_0_un0_n.BLIF a_15__n.BLIF a_14__n.BLIF a_13__n.BLIF a_c_16__n.BLIF a_12__n.BLIF a_c_17__n.BLIF a_11__n.BLIF a_c_18__n.BLIF \ - a_10__n.BLIF a_c_19__n.BLIF a_9__n.BLIF a_c_20__n.BLIF a_8__n.BLIF a_c_21__n.BLIF a_7__n.BLIF a_c_22__n.BLIF a_6__n.BLIF \ - a_c_23__n.BLIF a_5__n.BLIF a_c_24__n.BLIF a_4__n.BLIF a_c_25__n.BLIF a_3__n.BLIF a_c_26__n.BLIF a_2__n.BLIF a_c_27__n.BLIF \ - a_1__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF \ - CLK_030_c.BLIF DSACK_1_.PIN DTACK.PIN -.outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ - AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D \ - cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \ - SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C \ - SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_N_0_.D CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.D \ - CLK_CNT_N_1_.C CLK_CNT_N_1_.AP CLK_CNT_P_0_.D CLK_CNT_P_0_.C CLK_CNT_P_0_.AR CLK_CNT_P_1_.D CLK_CNT_P_1_.C CLK_CNT_P_1_.AR IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ - IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C \ - SM_AMIGA_6_.AR inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_VMA_INTreg.D \ - inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP \ - inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C \ - inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C DSACK_INT_1_.AP AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C inst_DTACK_DMA.D inst_DTACK_DMA.C \ - inst_DTACK_DMA.AP inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_000_D5.AP inst_CLK_000_D6.D inst_CLK_000_D6.C inst_CLK_000_D6.AP inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_CLK_000_D2.D \ - inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP \ - RESETDFFRHreg.D RESETDFFRHreg.C RESETDFFRHreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP G_102.X1 G_102.X2 G_108.X1 G_108.X2 DSACK_1_ DTACK DSACK_0_ CLK_000_c \ - CLK_OSZI_c ipl_c_0__n ipl_c_1__n ipl_c_2__n vcc_n_n dsack_c_1__n gnd_n_n DTACK_c AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n state_machine_un23_clk_000_d0_n \ - state_machine_un6_clk_000_d5_n RST_c state_machine_un6_bgack_000_n RW_c fc_c_0__n fc_c_1__n state_machine_un10_bg_030_n cpu_est_ns_0_1__n state_machine_un7_as_000_int_n N_129_i N_131_i \ - state_machine_un15_clk_000_d0_n N_221_i state_machine_lds_000_int_5_n N_222_i state_machine_uds_000_int_5_n N_63_0 un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_62_0 N_132_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i \ - N_60_i N_59_i N_57_i N_56_i N_55_i CLK_000_D1_i N_54_i N_51_i N_50_i N_125_i N_126_i \ - cpu_est_ns_e_0_0__n N_85_i N_123_i N_124_i sm_amiga_ns_0_0__n N_122_i N_227_i N_228_i cpu_est_ns_0_2__n N_226_i N_44_i \ - N_130_i N_225_i cpu_est_ns_1__n N_158_i cpu_est_ns_2__n N_219_i N_204 N_220_i N_205 sm_amiga_ns_0_7__n N_206 \ - N_215_i N_26 N_216_i N_30 N_49 N_95_i N_50 N_214_i N_51 sm_amiga_ns_0_5__n N_54 \ - N_94_i N_55 N_133_i N_56 N_57 N_87_i N_59 N_60 N_86_i N_62 N_63 \ - N_83_i N_68 N_70 N_82_i N_72 state_machine_lds_000_int_5_0_n N_73 state_machine_uds_000_int_5_0_n N_74 N_80_i N_76 \ - N_30_0 N_78 N_26_0 N_80 N_76_i N_82 N_206_0 N_83 N_205_0 N_85 N_72_i \ - N_86 N_73_i N_87 state_machine_un15_clk_000_d0_0_n N_94 N_204_0 N_95 BG_030_c_i N_214 N_70_i N_215 \ - state_machine_un10_bg_030_0_n N_216 state_machine_un6_bgack_000_0_n N_219 N_220 state_machine_un23_clk_000_d0_0_n N_221 N_236_1 N_222 N_236_2 N_225 \ - N_236_3 N_226 N_236_4 N_227 N_236_5 N_228 N_236_6 N_122 N_239_1 N_123 N_239_2 \ - N_124 state_machine_un8_clk_000_d2_1_n N_125 N_55_i_1 N_126 N_55_i_2 N_129 N_55_i_3 N_130 N_55_i_4 N_131 \ - N_55_i_5 N_132 cpu_est_ns_0_1_1__n N_133 cpu_est_ns_0_2_1__n N_236 N_80_1 N_239 N_80_2 RW_i N_78_1 \ - VMA_INT_i N_78_2 VPA_D_i N_74_1 DTACK_i N_74_2 CLK_000_D0_i N_74_3 sm_amiga_i_4__n N_70_1 cpu_est_i_3__n \ - N_70_2 sm_amiga_i_1__n sm_amiga_ns_0_1_0__n state_machine_un6_clk_000_d5_i_n cpu_est_ns_0_1_2__n sm_amiga_i_6__n N_226_1 nEXP_SPACE_i N_220_1 AS_000_INT_i N_82_1 \ - cpu_est_i_1__n N_73_1 cpu_est_i_0__n N_72_1 AMIGA_BUS_ENABLE_i state_machine_uds_000_int_5_0_m2_un3_n AS_030_i state_machine_uds_000_int_5_0_m2_un1_n cpu_est_i_2__n state_machine_uds_000_int_5_0_m2_un0_n sm_amiga_i_2__n \ - vpa_sync_0_un3_n sm_amiga_i_3__n vpa_sync_0_un1_n sm_amiga_i_5__n vpa_sync_0_un0_n state_machine_un8_clk_000_d2_i_n vma_int_0_un3_n sm_amiga_i_7__n vma_int_0_un1_n a_i_0__n vma_int_0_un0_n \ - size_i_1__n bg_000_0_un3_n dsack_i_1__n bg_000_0_un1_n BGACK_030_INT_i bg_000_0_un0_n CLK_000_D2_i bgack_030_int_0_un3_n AS_030_000_SYNC_i bgack_030_int_0_un1_n a_i_19__n \ - bgack_030_int_0_un0_n a_i_16__n as_000_int_0_un3_n a_i_18__n as_000_int_0_un1_n a_i_30__n as_000_int_0_un0_n a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n \ - a_i_29__n ipl_030_0_0__un0_n a_i_26__n ipl_030_0_1__un3_n a_i_27__n ipl_030_0_1__un1_n a_i_24__n ipl_030_0_1__un0_n a_i_25__n ipl_030_0_2__un3_n RST_i \ - ipl_030_0_2__un1_n ipl_030_0_2__un0_n cpu_estse_0_un3_n CLK_OSZI_i cpu_estse_0_un1_n cpu_estse_0_un0_n N_74_i cpu_estse_1_un3_n N_78_i cpu_estse_1_un1_n FPU_CS_INT_i \ - cpu_estse_1_un0_n CLK_000_D6_i cpu_estse_2_un3_n AS_030_c cpu_estse_2_un1_n cpu_estse_2_un0_n as_030_000_sync_0_un3_n DS_030_c as_030_000_sync_0_un1_n as_030_000_sync_0_un0_n dtack_sync_0_un3_n \ - dtack_sync_0_un1_n size_c_0__n dtack_sync_0_un0_n fpu_cs_int_0_un3_n size_c_1__n fpu_cs_int_0_un1_n fpu_cs_int_0_un0_n a_c_0__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n dsack_int_0_1__un0_n \ - amiga_bus_enable_0_un3_n amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n uds_000_int_0_un3_n uds_000_int_0_un1_n uds_000_int_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n a_15__n a_14__n \ - a_13__n a_c_16__n a_12__n a_c_17__n a_11__n a_c_18__n a_10__n a_c_19__n a_9__n a_c_20__n a_8__n \ - a_c_21__n a_7__n a_c_22__n a_6__n a_c_23__n a_5__n a_c_24__n a_4__n a_c_25__n a_3__n a_c_26__n \ - a_2__n a_c_27__n a_1__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c BGACK_000_c CLK_030_c \ - DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE -.names DSACK_INT_1_.BLIF DSACK_1_ +.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF \ + VPA.BLIF RST.BLIF RW.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF \ + A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \ + IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF DSACK_1_.BLIF AS_030.BLIF AS_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF DTACK.BLIF SIZE_0_.BLIF DSACK_0_.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF CLK_030_c.BLIF \ + inst_VMA_INTreg.BLIF inst_AS_030_000_SYNC.BLIF CLK_000_c.BLIF inst_BGACK_030_INT_D.BLIF inst_DTACK_SYNC.BLIF CLK_OSZI_c.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \ + CLK_OUT_INTreg.BLIF inst_CLK_000_D2.BLIF inst_CLK_000_D6.BLIF SM_AMIGA_5_.BLIF IPL_030DFFSH_0_reg.BLIF vcc_n_n.BLIF gnd_n_n.BLIF IPL_030DFFSH_1_reg.BLIF inst_AS_000_INT.BLIF \ + SM_AMIGA_6_.BLIF IPL_030DFFSH_2_reg.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF ipl_c_0__n.BLIF inst_DSACK1_INT.BLIF inst_CLK_000_D3.BLIF ipl_c_1__n.BLIF state_machine_un23_clk_000_d0_n.BLIF \ + inst_CLK_000_D5.BLIF ipl_c_2__n.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_1_.BLIF dsack_c_1__n.BLIF inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF DTACK_c.BLIF \ + SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF G_103.BLIF CLK_CNT_N_0_.BLIF VPA_c.BLIF CLK_CNT_N_1_.BLIF G_109.BLIF CLK_CNT_P_0_.BLIF \ + RST_c.BLIF CLK_CNT_P_1_.BLIF inst_CLK_000_D4.BLIF RESETDFFRHreg.BLIF SM_AMIGA_7_.BLIF state_machine_un15_clk_000_d0_n.BLIF RW_c.BLIF SM_AMIGA_4_.BLIF un1_AMIGA_BUS_ENABLE_0_sqmuxa_2.BLIF \ + fc_c_0__n.BLIF inst_CLK_OUT_PRE.BLIF SM_AMIGA_2_.BLIF fc_c_1__n.BLIF AMIGA_BUS_ENABLEDFFSHreg.BLIF state_machine_un23_clk_000_d0_0_n.BLIF state_machine_un6_bgack_000_0_n.BLIF N_214_0.BLIF BG_030_c_i.BLIF \ + N_227_i.BLIF state_machine_un10_bg_030_0_n.BLIF N_215_0.BLIF N_216_0.BLIF N_126_i.BLIF N_33_0.BLIF N_127_i.BLIF N_35_0.BLIF state_machine_uds_000_int_5_0_n.BLIF \ + N_130_i.BLIF state_machine_lds_000_int_5_0_n.BLIF N_132_i.BLIF N_131_i.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF N_133_i.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF \ + N_134_i.BLIF N_137_i.BLIF N_138_i.BLIF sm_amiga_ns_0_5__n.BLIF cpu_est_ns_1__n.BLIF N_139_i.BLIF cpu_est_ns_2__n.BLIF N_140_i.BLIF N_46_0.BLIF \ + N_52.BLIF N_142_i.BLIF N_59.BLIF N_141_i.BLIF N_62.BLIF sm_amiga_ns_0_7__n.BLIF N_65.BLIF N_144_i.BLIF N_67.BLIF \ + state_machine_ds_000_dma_5_0_n.BLIF N_72.BLIF CLK_030_c_i.BLIF N_77.BLIF AS_000_c_i.BLIF N_88.BLIF N_59_i.BLIF N_217.BLIF N_61_0.BLIF \ + N_219.BLIF N_62_i.BLIF N_221.BLIF CLK_000_D1_i.BLIF N_224.BLIF N_65_i.BLIF N_225.BLIF N_66_i.BLIF N_226.BLIF \ + N_67_i.BLIF N_128.BLIF N_175_i.BLIF N_130.BLIF un1_as_000_dma5_i_0__n.BLIF N_132.BLIF state_machine_un6_clk_000_d5_i_n.BLIF N_135.BLIF N_71_i.BLIF \ + N_136.BLIF DS_030_c_i.BLIF N_138.BLIF N_73_i.BLIF N_143.BLIF N_156_i.BLIF N_145.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i.BLIF N_146.BLIF \ + N_75_0.BLIF N_147.BLIF N_176_i.BLIF N_148.BLIF N_52_0.BLIF N_151.BLIF N_173_i.BLIF N_153.BLIF N_226_i.BLIF \ + N_154.BLIF N_77_0.BLIF N_155.BLIF N_72_i.BLIF N_173.BLIF N_147_i.BLIF cpu_est_ns_0_0_x2_1_.BLIF N_148_i.BLIF AMIGA_BUS_DATA_DIR_m1_0_x2.BLIF \ + cpu_est_ns_e_0_0__n.BLIF N_228_1.BLIF N_146_i.BLIF N_237.BLIF sm_amiga_ns_0_0__n.BLIF N_247.BLIF N_88_i.BLIF N_227.BLIF N_145_i.BLIF \ + N_228.BLIF cpu_est_ns_0_2__n.BLIF N_127.BLIF N_143_i.BLIF N_66.BLIF N_154_i.BLIF N_175.BLIF N_161_i.BLIF N_176.BLIF \ + N_153_i.BLIF N_75.BLIF N_155_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_4.BLIF cpu_est_ns_0_1__n.BLIF N_61.BLIF N_135_i.BLIF N_156.BLIF N_136_i.BLIF \ + N_73.BLIF N_57.BLIF N_225_i.BLIF N_71.BLIF un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0.BLIF state_machine_un6_clk_000_d5_n.BLIF N_219_i.BLIF un1_as_000_dma5_0__n.BLIF N_221_i.BLIF \ + N_223.BLIF state_machine_un15_clk_000_d0_0_n.BLIF state_machine_ds_000_dma_5_n.BLIF N_144.BLIF N_66_i_1.BLIF N_141.BLIF N_66_i_2.BLIF N_142.BLIF N_66_i_3.BLIF \ + N_139.BLIF N_66_i_4.BLIF N_140.BLIF N_66_i_5.BLIF N_137.BLIF N_237_1.BLIF N_134.BLIF N_237_2.BLIF N_133.BLIF \ + N_247_1.BLIF N_131.BLIF N_247_2.BLIF state_machine_lds_000_int_5_n.BLIF N_247_3.BLIF state_machine_uds_000_int_5_n.BLIF N_247_4.BLIF N_35.BLIF N_247_5.BLIF \ + N_33.BLIF N_247_6.BLIF N_126.BLIF N_52_0_1.BLIF N_216.BLIF N_52_0_2.BLIF N_215.BLIF N_224_1.BLIF state_machine_un10_bg_030_n.BLIF \ + N_224_2.BLIF N_214.BLIF N_227_1.BLIF state_machine_un6_bgack_000_n.BLIF N_227_2.BLIF state_machine_un8_clk_000_d2_n.BLIF N_228_1_0.BLIF SIZE_DMA_1_sqmuxa.BLIF N_127_1.BLIF \ + SIZE_DMA_0_sqmuxa.BLIF N_127_2.BLIF AS_000_INT_1_sqmuxa.BLIF N_151_1.BLIF N_249.BLIF SIZE_DMA_1_sqmuxa_1.BLIF CLK_000_D6_i.BLIF state_machine_un8_clk_000_d2_1_n.BLIF N_228_i.BLIF \ + sm_amiga_ns_0_1_0__n.BLIF sm_amiga_i_5__n.BLIF cpu_est_ns_0_1_1__n.BLIF N_224_i.BLIF N_138_1.BLIF N_223_i.BLIF N_130_1.BLIF SIZE_DMA_0_sqmuxa_i.BLIF N_128_1.BLIF \ + SIZE_DMA_1_sqmuxa_i.BLIF N_221_1.BLIF a_i_18__n.BLIF N_219_1.BLIF a_i_16__n.BLIF vpa_sync_0_un3_n.BLIF a_i_19__n.BLIF vpa_sync_0_un1_n.BLIF AS_030_000_SYNC_i.BLIF \ + vpa_sync_0_un0_n.BLIF CLK_000_D2_i.BLIF as_000_int_0_un3_n.BLIF BGACK_030_INT_i.BLIF as_000_int_0_un1_n.BLIF nEXP_SPACE_i.BLIF as_000_int_0_un0_n.BLIF AS_030_i.BLIF as_000_dma_0_un3_n.BLIF \ + BGACK_030_INT_D_i.BLIF as_000_dma_0_un1_n.BLIF sm_amiga_i_7__n.BLIF as_000_dma_0_un0_n.BLIF state_machine_un8_clk_000_d2_i_n.BLIF bg_000_0_un3_n.BLIF sm_amiga_i_6__n.BLIF bg_000_0_un1_n.BLIF sm_amiga_i_4__n.BLIF \ + bg_000_0_un0_n.BLIF CLK_000_D0_i.BLIF a0_dma_0_un3_n.BLIF RW_i.BLIF a0_dma_0_un1_n.BLIF UDS_000_i.BLIF a0_dma_0_un0_n.BLIF LDS_000_i.BLIF dtack_sync_0_un3_n.BLIF \ + DTACK_i.BLIF dtack_sync_0_un1_n.BLIF VMA_INT_i.BLIF dtack_sync_0_un0_n.BLIF VPA_i.BLIF lds_000_int_0_un3_n.BLIF cpu_est_i_0__n.BLIF lds_000_int_0_un1_n.BLIF sm_amiga_i_3__n.BLIF \ + lds_000_int_0_un0_n.BLIF cpu_est_i_3__n.BLIF uds_000_int_0_un3_n.BLIF cpu_est_i_1__n.BLIF uds_000_int_0_un1_n.BLIF A0_i.BLIF uds_000_int_0_un0_n.BLIF size_i_1__n.BLIF fpu_cs_int_0_un3_n.BLIF \ + a_i_30__n.BLIF fpu_cs_int_0_un1_n.BLIF a_i_31__n.BLIF fpu_cs_int_0_un0_n.BLIF a_i_28__n.BLIF ds_000_dma_0_un3_n.BLIF a_i_29__n.BLIF ds_000_dma_0_un1_n.BLIF a_i_26__n.BLIF \ + ds_000_dma_0_un0_n.BLIF a_i_27__n.BLIF as_030_000_sync_0_un3_n.BLIF a_i_24__n.BLIF as_030_000_sync_0_un1_n.BLIF a_i_25__n.BLIF as_030_000_sync_0_un0_n.BLIF RST_i.BLIF size_dma_0_1__un3_n.BLIF \ + size_dma_0_1__un1_n.BLIF CLK_OSZI_i.BLIF size_dma_0_1__un0_n.BLIF size_dma_0_0__un3_n.BLIF FPU_CS_INT_i.BLIF size_dma_0_0__un1_n.BLIF AS_030_c.BLIF size_dma_0_0__un0_n.BLIF bgack_030_int_0_un3_n.BLIF \ + AS_000_c.BLIF bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF DS_030_c.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un1_n.BLIF UDS_000_c.BLIF dsack1_int_0_un0_n.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF \ + LDS_000_c.BLIF state_machine_uds_000_int_5_0_m2_un1_n.BLIF state_machine_uds_000_int_5_0_m2_un0_n.BLIF size_c_0__n.BLIF cpu_est_ns_0_0_m2_2__un3_n.BLIF cpu_est_ns_0_0_m2_2__un1_n.BLIF size_c_1__n.BLIF cpu_est_ns_0_0_m2_2__un0_n.BLIF amiga_bus_enable_0_un3_n.BLIF \ + a_c_16__n.BLIF amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF a_c_17__n.BLIF vma_int_0_un3_n.BLIF vma_int_0_un1_n.BLIF a_c_18__n.BLIF vma_int_0_un0_n.BLIF ipl_030_0_0__un3_n.BLIF \ + a_c_19__n.BLIF ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF a_c_20__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF a_c_21__n.BLIF ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF \ + a_c_22__n.BLIF ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF a_c_23__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un1_n.BLIF a_c_24__n.BLIF cpu_estse_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF \ + a_c_25__n.BLIF cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF a_c_26__n.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un1_n.BLIF a_c_27__n.BLIF cpu_estse_2_un0_n.BLIF a_c_28__n.BLIF \ + a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF A0_c.BLIF nEXP_SPACE_c.BLIF AS_030.PIN AS_000.PIN DS_030.PIN UDS_000.PIN \ + LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN DSACK_1_.PIN DTACK.PIN +.outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC AVEC_EXP E VMA \ + RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR cpu_est_2_.D \ + cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_4_.AR \ + SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C \ + SM_AMIGA_0_.AR CLK_CNT_P_1_.D CLK_CNT_P_1_.C CLK_CNT_P_1_.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP IPL_030DFFSH_0_reg.D \ + IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP \ + SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_DSACK1_INT.D inst_DSACK1_INT.C \ + inst_DSACK1_INT.AP inst_VMA_INTreg.D inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP CLK_CNT_N_0_.D CLK_CNT_N_0_.C CLK_CNT_N_0_.AR CLK_CNT_N_1_.D \ + CLK_CNT_N_1_.C CLK_CNT_N_1_.AP CLK_CNT_P_0_.D CLK_CNT_P_0_.C CLK_CNT_P_0_.AR inst_LDS_000_INT.D inst_LDS_000_INT.C inst_LDS_000_INT.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP \ + inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP AMIGA_BUS_ENABLEDFFSHreg.D AMIGA_BUS_ENABLEDFFSHreg.C \ + AMIGA_BUS_ENABLEDFFSHreg.AP inst_AS_000_INT.D inst_AS_000_INT.C inst_AS_000_INT.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP inst_FPU_CS_INTreg.D \ + inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C inst_CLK_OUT_PRE.AR \ + inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_000_D5.AP inst_CLK_000_D6.D inst_CLK_000_D6.C inst_CLK_000_D6.AP inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_CLK_000_D2.D inst_CLK_000_D2.C \ + inst_CLK_000_D2.AP inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP RESETDFFRHreg.D \ + RESETDFFRHreg.C RESETDFFRHreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_D1.AP AMIGA_BUS_DATA_DIR_m1_0_x2.X1 AMIGA_BUS_DATA_DIR_m1_0_x2.X2 cpu_est_ns_0_0_x2_1_.X1 cpu_est_ns_0_0_x2_1_.X2 G_103.X1 G_103.X2 \ + G_109.X1 G_109.X2 SIZE_1_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 DTACK SIZE_0_ DSACK_0_ BG_030_c BGACK_000_c CLK_030_c CLK_000_c CLK_OSZI_c vcc_n_n gnd_n_n ipl_c_0__n ipl_c_1__n \ + state_machine_un23_clk_000_d0_n ipl_c_2__n dsack_c_1__n DTACK_c VPA_c RST_c state_machine_un15_clk_000_d0_n RW_c un1_AMIGA_BUS_ENABLE_0_sqmuxa_2 fc_c_0__n fc_c_1__n \ + state_machine_un23_clk_000_d0_0_n state_machine_un6_bgack_000_0_n N_214_0 BG_030_c_i N_227_i state_machine_un10_bg_030_0_n N_215_0 N_216_0 N_126_i N_33_0 N_127_i \ + N_35_0 state_machine_uds_000_int_5_0_n N_130_i state_machine_lds_000_int_5_0_n N_132_i N_131_i N_133_i N_134_i N_137_i N_138_i sm_amiga_ns_0_5__n \ + cpu_est_ns_1__n N_139_i cpu_est_ns_2__n N_140_i N_46_0 N_52 N_142_i N_59 N_141_i N_62 sm_amiga_ns_0_7__n \ + N_65 N_144_i N_67 state_machine_ds_000_dma_5_0_n N_72 CLK_030_c_i N_77 AS_000_c_i N_88 N_59_i N_217 \ + N_61_0 N_219 N_62_i N_221 CLK_000_D1_i N_224 N_65_i N_225 N_66_i N_226 N_67_i \ + N_128 N_175_i N_130 un1_as_000_dma5_i_0__n N_132 state_machine_un6_clk_000_d5_i_n N_135 N_71_i N_136 DS_030_c_i N_138 \ + N_73_i N_143 N_156_i N_145 un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i N_146 N_75_0 N_147 N_176_i N_148 N_52_0 \ + N_151 N_173_i N_153 N_226_i N_154 N_77_0 N_155 N_72_i N_173 N_147_i N_148_i \ + cpu_est_ns_e_0_0__n N_228_1 N_146_i N_237 sm_amiga_ns_0_0__n N_247 N_88_i N_227 N_145_i N_228 cpu_est_ns_0_2__n \ + N_127 N_143_i N_66 N_154_i N_175 N_161_i N_176 N_153_i N_75 N_155_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_4 \ + cpu_est_ns_0_1__n N_61 N_135_i N_156 N_136_i N_73 N_57 N_225_i N_71 un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0 state_machine_un6_clk_000_d5_n \ + N_219_i un1_as_000_dma5_0__n N_221_i N_223 state_machine_un15_clk_000_d0_0_n state_machine_ds_000_dma_5_n N_144 N_66_i_1 N_141 N_66_i_2 N_142 \ + N_66_i_3 N_139 N_66_i_4 N_140 N_66_i_5 N_137 N_237_1 N_134 N_237_2 N_133 N_247_1 \ + N_131 N_247_2 state_machine_lds_000_int_5_n N_247_3 state_machine_uds_000_int_5_n N_247_4 N_35 N_247_5 N_33 N_247_6 N_126 \ + N_52_0_1 N_216 N_52_0_2 N_215 N_224_1 state_machine_un10_bg_030_n N_224_2 N_214 N_227_1 state_machine_un6_bgack_000_n N_227_2 \ + state_machine_un8_clk_000_d2_n N_228_1_0 SIZE_DMA_1_sqmuxa N_127_1 SIZE_DMA_0_sqmuxa N_127_2 AS_000_INT_1_sqmuxa N_151_1 N_249 SIZE_DMA_1_sqmuxa_1 CLK_000_D6_i \ + state_machine_un8_clk_000_d2_1_n N_228_i sm_amiga_ns_0_1_0__n sm_amiga_i_5__n cpu_est_ns_0_1_1__n N_224_i N_138_1 N_223_i N_130_1 SIZE_DMA_0_sqmuxa_i N_128_1 \ + SIZE_DMA_1_sqmuxa_i N_221_1 a_i_18__n N_219_1 a_i_16__n vpa_sync_0_un3_n a_i_19__n vpa_sync_0_un1_n AS_030_000_SYNC_i vpa_sync_0_un0_n CLK_000_D2_i \ + as_000_int_0_un3_n BGACK_030_INT_i as_000_int_0_un1_n nEXP_SPACE_i as_000_int_0_un0_n AS_030_i as_000_dma_0_un3_n BGACK_030_INT_D_i as_000_dma_0_un1_n sm_amiga_i_7__n as_000_dma_0_un0_n \ + state_machine_un8_clk_000_d2_i_n bg_000_0_un3_n sm_amiga_i_6__n bg_000_0_un1_n sm_amiga_i_4__n bg_000_0_un0_n CLK_000_D0_i a0_dma_0_un3_n RW_i a0_dma_0_un1_n UDS_000_i \ + a0_dma_0_un0_n LDS_000_i dtack_sync_0_un3_n DTACK_i dtack_sync_0_un1_n VMA_INT_i dtack_sync_0_un0_n VPA_i lds_000_int_0_un3_n cpu_est_i_0__n lds_000_int_0_un1_n \ + sm_amiga_i_3__n lds_000_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n cpu_est_i_1__n uds_000_int_0_un1_n A0_i uds_000_int_0_un0_n size_i_1__n fpu_cs_int_0_un3_n a_i_30__n \ + fpu_cs_int_0_un1_n a_i_31__n fpu_cs_int_0_un0_n a_i_28__n ds_000_dma_0_un3_n a_i_29__n ds_000_dma_0_un1_n a_i_26__n ds_000_dma_0_un0_n a_i_27__n as_030_000_sync_0_un3_n \ + a_i_24__n as_030_000_sync_0_un1_n a_i_25__n as_030_000_sync_0_un0_n RST_i size_dma_0_1__un3_n size_dma_0_1__un1_n CLK_OSZI_i size_dma_0_1__un0_n size_dma_0_0__un3_n FPU_CS_INT_i \ + size_dma_0_0__un1_n AS_030_c size_dma_0_0__un0_n bgack_030_int_0_un3_n AS_000_c bgack_030_int_0_un1_n bgack_030_int_0_un0_n DS_030_c dsack1_int_0_un3_n dsack1_int_0_un1_n UDS_000_c \ + dsack1_int_0_un0_n state_machine_uds_000_int_5_0_m2_un3_n LDS_000_c state_machine_uds_000_int_5_0_m2_un1_n state_machine_uds_000_int_5_0_m2_un0_n size_c_0__n cpu_est_ns_0_0_m2_2__un3_n cpu_est_ns_0_0_m2_2__un1_n size_c_1__n cpu_est_ns_0_0_m2_2__un0_n amiga_bus_enable_0_un3_n \ + a_c_16__n amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n a_c_17__n vma_int_0_un3_n vma_int_0_un1_n a_c_18__n vma_int_0_un0_n ipl_030_0_0__un3_n a_c_19__n ipl_030_0_0__un1_n \ + ipl_030_0_0__un0_n a_c_20__n ipl_030_0_1__un3_n ipl_030_0_1__un1_n a_c_21__n ipl_030_0_1__un0_n ipl_030_0_2__un3_n a_c_22__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n a_c_23__n \ + cpu_estse_0_un3_n cpu_estse_0_un1_n a_c_24__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_25__n cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_26__n cpu_estse_2_un3_n cpu_estse_2_un1_n \ + a_c_27__n cpu_estse_2_un0_n a_c_28__n a_c_29__n a_c_30__n a_c_31__n A0_c nEXP_SPACE_c AS_030.OE \ + AS_000.OE DS_030.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK_1_.OE DTACK.OE \ + BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE +.names inst_AS_000_DMA.BLIF AS_030 +1 1 +.names AS_030.PIN AS_030_c +1 1 +.names N_217.BLIF AS_030.OE +1 1 +.names inst_AS_000_INT.BLIF AS_000 +1 1 +.names AS_000.PIN AS_000_c +1 1 +.names inst_BGACK_030_INTreg.BLIF AS_000.OE +1 1 +.names inst_DS_000_DMA.BLIF DS_030 +1 1 +.names DS_030.PIN DS_030_c +1 1 +.names N_217.BLIF DS_030.OE +1 1 +.names inst_UDS_000_INT.BLIF UDS_000 +1 1 +.names UDS_000.PIN UDS_000_c +1 1 +.names inst_BGACK_030_INTreg.BLIF UDS_000.OE +1 1 +.names inst_LDS_000_INT.BLIF LDS_000 +1 1 +.names LDS_000.PIN LDS_000_c +1 1 +.names inst_BGACK_030_INTreg.BLIF LDS_000.OE +1 1 +.names SIZE_DMA_0_.BLIF SIZE_0_ +1 1 +.names SIZE_0_.PIN size_c_0__n +1 1 +.names N_217.BLIF SIZE_0_.OE +1 1 +.names SIZE_DMA_1_.BLIF SIZE_1_ +1 1 +.names SIZE_1_.PIN size_c_1__n +1 1 +.names N_217.BLIF SIZE_1_.OE +1 1 +.names inst_A0_DMA.BLIF A0 +1 1 +.names A0.PIN A0_c +1 1 +.names N_217.BLIF A0.OE +1 1 +.names inst_DSACK1_INT.BLIF DSACK_1_ 1 1 .names DSACK_1_.PIN dsack_c_1__n 1 1 .names nEXP_SPACE_c.BLIF DSACK_1_.OE 1 1 -.names inst_DTACK_DMA.BLIF DTACK +.names dsack_c_1__n.BLIF DTACK 1 1 .names DTACK.PIN DTACK_c 1 1 -.names N_68.BLIF DTACK.OE -1 1 -.names inst_AS_000_INTreg.BLIF AS_000 -1 1 -.names inst_BGACK_030_INTreg.BLIF AS_000.OE -1 1 -.names inst_UDS_000_INTreg.BLIF UDS_000 -1 1 -.names inst_BGACK_030_INTreg.BLIF UDS_000.OE -1 1 -.names inst_LDS_000_INTreg.BLIF LDS_000 -1 1 -.names inst_BGACK_030_INTreg.BLIF LDS_000.OE +.names N_217.BLIF DTACK.OE 1 1 .names gnd_n_n.BLIF BERR 1 1 .names FPU_CS_INT_i.BLIF BERR.OE 1 1 -.names vcc_n_n.BLIF DSACK_0_ +.names gnd_n_n.BLIF DSACK_0_ 1 1 -.names nEXP_SPACE_c.BLIF DSACK_0_.OE +.names gnd_n_n.BLIF DSACK_0_.OE 1 1 .names gnd_n_n.BLIF AVEC_EXP 1 1 .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 -.names N_239.BLIF CIIN +.names N_237.BLIF CIIN 1 1 -.names N_236.BLIF CIIN.OE +.names N_247.BLIF CIIN.OE 1 1 -.names N_131.BLIF N_131_i +.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D 0 1 -.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d5_n.BLIF N_57_i +.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D +1 1 +.names N_144.BLIF N_144_i +0 1 +.names state_machine_ds_000_dma_5_0_n.BLIF state_machine_ds_000_dma_5_n +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C +1 1 +.names state_machine_un23_clk_000_d0_0_n.BLIF state_machine_un23_clk_000_d0_n +0 1 +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n +0 1 +.names RST_i.BLIF inst_CLK_000_D2.AP +1 1 +.names N_214_0.BLIF N_214 +0 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names N_227.BLIF N_227_i +0 1 +.names CLK_OSZI_c.BLIF cpu_est_1_.C +1 1 +.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D +1 1 +.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n +0 1 +.names N_215_0.BLIF N_215 +0 1 +.names RST_i.BLIF cpu_est_1_.AR +1 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C +1 1 +.names N_216_0.BLIF N_216 +0 1 +.names N_126.BLIF N_126_i +0 1 +.names RST_i.BLIF inst_CLK_000_D3.AP +1 1 +.names N_33_0.BLIF N_33 +0 1 +.names N_127.BLIF N_127_i +0 1 +.names CLK_OSZI_c.BLIF cpu_est_2_.C +1 1 +.names N_35_0.BLIF N_35 +0 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D +1 1 +.names state_machine_uds_000_int_5_0_n.BLIF state_machine_uds_000_int_5_n +0 1 +.names RST_i.BLIF cpu_est_2_.AR +1 1 +.names N_130.BLIF N_130_i +0 1 +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C +1 1 +.names state_machine_lds_000_int_5_0_n.BLIF state_machine_lds_000_int_5_n +0 1 +.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF state_machine_un23_clk_000_d0_0_n 11 1 +.names RST_i.BLIF inst_BGACK_030_INT_D.AP +1 1 +.names N_214.BLIF vpa_sync_0_un3_n +0 1 .names CLK_OSZI_c.BLIF cpu_est_3_reg.C 1 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names CLK_CNT_P_0_.BLIF G_108.X1 -1 1 -.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_59_i +.names N_224_i.BLIF N_214.BLIF vpa_sync_0_un1_n +11 1 +.names inst_VPA_SYNC.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n 11 1 .names RST_i.BLIF cpu_est_3_reg.AR 1 1 -.names DS_030_c_i.BLIF N_49.BLIF N_60_i -11 1 -.names CLK_CNT_P_1_.BLIF G_108.X2 -1 1 -.names N_51_i.BLIF N_132_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 -11 1 -.names CLK_000_D0_i.BLIF N_56_i.BLIF N_62_0 -11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names CLK_OSZI_c.BLIF cpu_est_0_.C -1 1 -.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D -1 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D -1 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_63_0 -11 1 -.names RST_i.BLIF cpu_est_0_.AR -1 1 -.names DTACK_c.BLIF DTACK_i -0 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names RW_c.BLIF RW_i -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -.names N_215_i.BLIF N_216_i.BLIF SM_AMIGA_1_.D -11 1 -.names N_219_i.BLIF N_220_i.BLIF sm_amiga_ns_0_7__n -11 1 -.names RST_i.BLIF SM_AMIGA_5_.AR -1 1 -.names N_130_i.BLIF N_225_i.BLIF N_158_i -11 1 -.names N_56.BLIF N_226_i.BLIF N_44_i -11 1 -.names N_125_i.BLIF N_126_i.BLIF cpu_est_ns_e_0_0__n -11 1 -.names RW_c.BLIF state_machine_uds_000_int_5_0_m2_un3_n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C -1 1 -.names SM_AMIGA_5_.BLIF RW_c.BLIF state_machine_uds_000_int_5_0_m2_un1_n -11 1 -.names SM_AMIGA_4_.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF state_machine_uds_000_int_5_0_m2_un0_n -11 1 -.names RST_i.BLIF SM_AMIGA_4_.AR -1 1 -.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_49 -1- 1 --1 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF N_50_i -11 1 -.names AS_030_i.BLIF N_57.BLIF N_51_i -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C -1 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_54_i -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names RST_i.BLIF SM_AMIGA_3_.AR -1 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_56_i -11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names state_machine_un6_clk_000_d5_n.BLIF state_machine_un6_clk_000_d5_i_n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C -1 1 -.names BGACK_000_c.BLIF N_54.BLIF state_machine_un6_bgack_000_0_n -11 1 -.names BG_030_c_i.BLIF N_70_i.BLIF state_machine_un10_bg_030_0_n -11 1 -.names RST_i.BLIF SM_AMIGA_2_.AR -1 1 -.names AS_030_i.BLIF N_60.BLIF N_204_0 -11 1 -.names N_72_i.BLIF N_73_i.BLIF state_machine_un15_clk_000_d0_0_n -11 1 -.names AS_030_i.BLIF N_74_i.BLIF N_205_0 -11 1 -.names AS_030_i.BLIF N_76_i.BLIF N_206_0 -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C -1 1 -.names AS_030_i.BLIF N_78_i.BLIF N_26_0 -11 1 -.names N_80_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_30_0 -11 1 -.names RST_i.BLIF SM_AMIGA_1_.AR -1 1 -.names a_i_0__n.BLIF N_60_i.BLIF state_machine_uds_000_int_5_0_n -11 1 -.names N_60_i.BLIF N_82_i.BLIF state_machine_lds_000_int_5_0_n -11 1 -.names N_83_i.BLIF N_85_i.BLIF SM_AMIGA_6_.D -11 1 -.names inst_CLK_000_D0.BLIF N_86_i.BLIF SM_AMIGA_5_.D -11 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C -1 1 -.names CLK_000_D0_i.BLIF N_87_i.BLIF SM_AMIGA_4_.D -11 1 -.names N_94_i.BLIF N_133_i.BLIF SM_AMIGA_3_.D -11 1 -.names RST_i.BLIF SM_AMIGA_0_.AR -1 1 -.names N_95_i.BLIF N_214_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_227 -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_228 -11 1 -.names CLK_OSZI_i.BLIF CLK_CNT_N_0_.C -1 1 -.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_122 -11 1 -.names CLK_000_D0_i.BLIF N_132.BLIF N_123 -11 1 -.names RST_i.BLIF CLK_CNT_N_0_.AR -1 1 -.names N_50_i.BLIF SM_AMIGA_0_.BLIF N_124 -11 1 -.names N_54.BLIF cpu_est_0_.BLIF N_125 -11 1 -.names N_54_i.BLIF cpu_est_i_0__n.BLIF N_126 -11 1 -.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D -1 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_129 -11 1 -.names CLK_OSZI_i.BLIF CLK_CNT_N_1_.C -1 1 -.names N_129.BLIF cpu_est_i_3__n.BLIF N_130 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names RST_i.BLIF CLK_CNT_N_1_.AP -1 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_131 -11 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_132 -11 1 -.names CLK_000_D0_i.BLIF state_machine_un23_clk_000_d0_n.BLIF N_133 -11 1 -.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n -0 1 -.names CLK_OSZI_c.BLIF CLK_CNT_P_0_.C -1 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_87 -11 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names RST_i.BLIF CLK_CNT_P_0_.AR -1 1 -.names N_63.BLIF sm_amiga_i_3__n.BLIF N_94 -11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_95 -11 1 -.names N_133.BLIF SM_AMIGA_3_.BLIF N_214 -11 1 -.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.D -1 1 -.names CLK_000_D0_i.BLIF N_57.BLIF N_215 -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names CLK_OSZI_c.BLIF CLK_CNT_P_1_.C -1 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_216 -11 1 -.names N_50.BLIF SM_AMIGA_0_.BLIF N_219 -11 1 -.names RST_i.BLIF CLK_CNT_P_1_.AR -1 1 -.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_221 -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_222 -11 1 -.names N_59.BLIF cpu_est_2_.BLIF N_225 -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C -1 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i -0 1 -.names RST_i.BLIF IPL_030DFFSH_0_reg.AP -1 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_68 -11 1 -.names AS_030_i.BLIF sm_amiga_i_5__n.BLIF AS_000_INT_1_sqmuxa -11 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C -1 1 -.names dsack_c_1__n.BLIF dsack_i_1__n -0 1 -.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un7_as_000_int_n -11 1 -.names RST_i.BLIF IPL_030DFFSH_1_reg.AP -1 1 -.names CLK_030_c.BLIF N_55_i.BLIF N_76 -11 1 -.names a_c_0__n.BLIF a_i_0__n -0 1 -.names AS_030.BLIF AS_030_c -1 1 -.names size_c_1__n.BLIF size_i_1__n -0 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C -1 1 -.names DS_030.BLIF DS_030_c -1 1 -.names N_62.BLIF sm_amiga_i_7__n.BLIF N_83 -11 1 -.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n -0 1 -.names RST_i.BLIF IPL_030DFFSH_2_reg.AP -1 1 -.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_85 -11 1 -.names SIZE_0_.BLIF size_c_0__n -1 1 -.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_86 -11 1 -.names SIZE_1_.BLIF size_c_1__n -1 1 -.names RST_c.BLIF RST_i -0 1 -.names A_0_.BLIF a_c_0__n -1 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C -1 1 -.names A_16_.BLIF a_c_16__n -1 1 -.names a_c_25__n.BLIF a_i_25__n -0 1 -.names A_17_.BLIF a_c_17__n -1 1 -.names a_c_26__n.BLIF a_i_26__n -0 1 -.names RST_i.BLIF SM_AMIGA_7_.AP -1 1 -.names A_18_.BLIF a_c_18__n -1 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names A_19_.BLIF a_c_19__n -1 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names A_20_.BLIF a_c_20__n -1 1 -.names a_c_29__n.BLIF a_i_29__n -0 1 -.names A_21_.BLIF a_c_21__n -1 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C -1 1 -.names A_22_.BLIF a_c_22__n -1 1 -.names a_c_31__n.BLIF a_i_31__n -0 1 -.names A_23_.BLIF a_c_23__n -1 1 -.names a_c_16__n.BLIF a_i_16__n -0 1 -.names RST_i.BLIF SM_AMIGA_6_.AR -1 1 -.names A_24_.BLIF a_c_24__n -1 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names A_25_.BLIF a_c_25__n -1 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 -.names A_26_.BLIF a_c_26__n -1 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i -0 1 -.names A_27_.BLIF a_c_27__n -1 1 -.names inst_CLK_000_D2.BLIF CLK_000_D2_i -0 1 -.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C -1 1 -.names A_28_.BLIF a_c_28__n -1 1 -.names state_machine_un7_as_000_int_n.BLIF inst_DTACK_DMA.D -0 1 -.names A_29_.BLIF a_c_29__n -1 1 -.names G_102.BLIF CLK_CNT_N_0_.D -0 1 -.names RST_i.BLIF inst_UDS_000_INTreg.AP -1 1 -.names A_30_.BLIF a_c_30__n -1 1 -.names CLK_OSZI_c.BLIF CLK_OSZI_i -0 1 -.names A_31_.BLIF a_c_31__n -1 1 -.names G_108.BLIF CLK_CNT_P_0_.D -0 1 -.names nEXP_SPACE.BLIF nEXP_SPACE_c -1 1 -.names N_74.BLIF N_74_i -0 1 -.names N_205.BLIF vpa_sync_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C -1 1 -.names BG_030.BLIF BG_030_c -1 1 -.names N_74_i.BLIF N_205.BLIF vpa_sync_0_un1_n -11 1 -.names BG_000DFFSHreg.BLIF BG_000 -1 1 -.names inst_VPA_SYNC.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n -11 1 -.names RST_i.BLIF inst_LDS_000_INTreg.AP -1 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030 +.names CLK_000_c.BLIF inst_CLK_000_D0.D 1 1 .names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D 1- 1 -1 1 -.names BGACK_000.BLIF BGACK_000_c -1 1 -.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n +.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n 0 1 -.names CLK_030.BLIF CLK_030_c +.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C 1 1 -.names N_50_i.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n 11 1 -.names CLK_000.BLIF CLK_000_c +.names CLK_OSZI_c.BLIF cpu_est_0_.C 1 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +.names RST_i.BLIF inst_CLK_000_D0.AP +1 1 +.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n 11 1 -.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C -1 1 -.names CLK_OSZI.BLIF CLK_OSZI_c -1 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D 1- 1 -1 1 -.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT +.names RST_i.BLIF cpu_est_0_.AR +1 1 +.names N_249.BLIF as_000_dma_0_un3_n +0 1 +.names vcc_n_n.BLIF RESETDFFRHreg.D +1 1 +.names inst_AS_000_DMA.BLIF N_249.BLIF as_000_dma_0_un1_n +11 1 +.names un1_as_000_dma5_0__n.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF RESETDFFRHreg.C +1 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 .names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n 0 1 -.names RST_i.BLIF inst_VPA_SYNC.AP -1 1 -.names CLK_OUT_INTreg.BLIF CLK_EXP +.names RST_i.BLIF RESETDFFRHreg.AR 1 1 .names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n 11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS +.names RST_i.BLIF SM_AMIGA_4_.AR 1 1 .names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n 11 1 -.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ -1 1 .names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D 1- 1 -1 1 -.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ +.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D 1 1 +.names N_249.BLIF a0_dma_0_un3_n +0 1 +.names inst_A0_DMA.BLIF N_249.BLIF a0_dma_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C +1 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C +1 1 +.names N_128.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +11 1 +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF inst_A0_DMA.D +1- 1 +-1 1 +.names RST_i.BLIF SM_AMIGA_3_.AR +1 1 +.names RST_i.BLIF inst_CLK_000_D1.AP +1 1 +.names N_228.BLIF N_228_i +0 1 +.names N_216.BLIF dtack_sync_0_un3_n +0 1 +.names N_228_i.BLIF N_216.BLIF dtack_sync_0_un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF AMIGA_BUS_DATA_DIR_m1_0_x2.X1 +1 1 +.names inst_DTACK_SYNC.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C +1 1 +.names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D +1- 1 +-1 1 +.names RW_c.BLIF AMIGA_BUS_DATA_DIR_m1_0_x2.X2 +1 1 +.names N_215.BLIF lds_000_int_0_un3_n +0 1 +.names RST_i.BLIF SM_AMIGA_2_.AR +1 1 +.names state_machine_lds_000_int_5_n.BLIF N_215.BLIF lds_000_int_0_un1_n +11 1 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names cpu_est_2_.BLIF cpu_est_ns_0_0_x2_1_.X1 +1 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D +1- 1 +-1 1 +.names N_215.BLIF uds_000_int_0_un3_n +0 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C +1 1 +.names cpu_est_3_reg.BLIF cpu_est_ns_0_0_x2_1_.X2 +1 1 +.names state_machine_uds_000_int_5_n.BLIF N_215.BLIF uds_000_int_0_un1_n +11 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names RST_i.BLIF SM_AMIGA_1_.AR +1 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D +1- 1 +-1 1 +.names CLK_CNT_N_0_.BLIF G_103.X1 +1 1 +.names N_33.BLIF fpu_cs_int_0_un3_n +0 1 +.names AS_030_c.BLIF N_33.BLIF fpu_cs_int_0_un1_n +11 1 +.names CLK_CNT_N_1_.BLIF G_103.X2 +1 1 +.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C +1 1 +.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D +1- 1 +-1 1 +.names N_249.BLIF ds_000_dma_0_un3_n +0 1 +.names RST_i.BLIF SM_AMIGA_0_.AR +1 1 +.names CLK_CNT_P_0_.BLIF G_109.X1 +1 1 +.names inst_DS_000_DMA.BLIF N_249.BLIF ds_000_dma_0_un1_n +11 1 +.names state_machine_ds_000_dma_5_n.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n +11 1 +.names CLK_CNT_P_1_.BLIF G_109.X2 +1 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D +1- 1 +-1 1 +.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.D +1 1 +.names N_35.BLIF as_030_000_sync_0_un3_n +0 1 +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_4.BLIF N_35.BLIF as_030_000_sync_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_CNT_P_1_.C +1 1 +.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D +1 1 +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n +11 1 +.names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D +1 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D +1- 1 +-1 1 +.names RST_i.BLIF CLK_CNT_P_1_.AR +1 1 +.names inst_CLK_000_D6.BLIF CLK_000_D6_i +0 1 +.names inst_CLK_000_D5.BLIF CLK_000_D6_i.BLIF state_machine_un6_clk_000_d5_n +11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_217 +11 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +.names inst_CLK_000_D2.BLIF CLK_000_D2_i +0 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 +.names RST_i.BLIF SIZE_DMA_0_.AP +1 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names SIZE_DMA_1_sqmuxa.BLIF SIZE_DMA_1_sqmuxa_i +0 1 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +.names N_249.BLIF size_dma_0_1__un3_n +0 1 +.names SIZE_DMA_1_.BLIF N_249.BLIF size_dma_0_1__un1_n +11 1 +.names RST_i.BLIF SIZE_DMA_1_.AP +1 1 +.names SIZE_DMA_1_sqmuxa_i.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n +11 1 +.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D +1- 1 +-1 1 +.names SIZE_DMA_0_sqmuxa.BLIF SIZE_DMA_0_sqmuxa_i +0 1 +.names N_249.BLIF size_dma_0_0__un3_n +0 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C +1 1 +.names SIZE_DMA_0_.BLIF N_249.BLIF size_dma_0_0__un1_n +11 1 +.names SIZE_DMA_0_sqmuxa_i.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +11 1 +.names RST_i.BLIF IPL_030DFFSH_0_reg.AP +1 1 +.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D +1- 1 +-1 1 .names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 +.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +11 1 +.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +11 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C +1 1 +.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D +1- 1 +-1 1 +.names N_223.BLIF N_223_i +0 1 +.names RST_i.BLIF IPL_030DFFSH_1_reg.AP +1 1 +.names N_61.BLIF dsack1_int_0_un3_n +0 1 +.names N_223_i.BLIF N_61.BLIF dsack1_int_0_un1_n +11 1 +.names inst_DSACK1_INT.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n +11 1 +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C +1 1 +.names N_224.BLIF N_224_i +0 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_134 +11 1 +.names RST_i.BLIF IPL_030DFFSH_2_reg.AP +1 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_133 +11 1 +.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n +0 1 +.names A_16_.BLIF a_c_16__n +1 1 +.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_132 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C +1 1 +.names A_17_.BLIF a_c_17__n +1 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names A_18_.BLIF a_c_18__n +1 1 +.names N_75.BLIF sm_amiga_i_7__n.BLIF N_131 +11 1 +.names RST_i.BLIF SM_AMIGA_7_.AP +1 1 +.names A_19_.BLIF a_c_19__n +1 1 +.names CLK_030_c.BLIF N_66_i.BLIF N_126 +11 1 +.names A_20_.BLIF a_c_20__n +1 1 +.names N_151.BLIF N_176.BLIF SIZE_DMA_0_sqmuxa +11 1 +.names A_21_.BLIF a_c_21__n +1 1 +.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i +0 1 +.names A_22_.BLIF a_c_22__n +1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF N_226 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C +1 1 +.names A_23_.BLIF a_c_23__n +1 1 +.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d5_n.BLIF N_223 +11 1 +.names A_24_.BLIF a_c_24__n +1 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names RST_i.BLIF SM_AMIGA_6_.AR +1 1 +.names A_25_.BLIF a_c_25__n +1 1 +.names AS_030_i.BLIF sm_amiga_i_5__n.BLIF AS_000_INT_1_sqmuxa +11 1 +.names A_26_.BLIF a_c_26__n +1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names A_27_.BLIF a_c_27__n +1 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF N_176 +11 1 +.names A_28_.BLIF a_c_28__n +1 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_175 +11 1 +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C +1 1 +.names A_29_.BLIF a_c_29__n +1 1 +.names N_59_i.BLIF SM_AMIGA_0_.BLIF N_173 +11 1 +.names A_30_.BLIF a_c_30__n +1 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_249 +11 1 +.names RST_i.BLIF SM_AMIGA_5_.AR +1 1 +.names A_31_.BLIF a_c_31__n +1 1 +.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_156 +11 1 +.names CLK_000_D0_i.BLIF N_156.BLIF N_146 +11 1 +.names nEXP_SPACE.BLIF nEXP_SPACE_c +1 1 +.names RW_c.BLIF RW_i +0 1 +.names inst_AS_000_DMA.BLIF RW_i.BLIF N_144 +11 1 +.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C +1 1 +.names BG_030.BLIF BG_030_c +1 1 +.names N_71_i.BLIF SM_AMIGA_1_.BLIF N_142 +11 1 +.names BG_000DFFSHreg.BLIF BG_000 +1 1 +.names N_59.BLIF SM_AMIGA_0_.BLIF N_141 +11 1 +.names RST_i.BLIF inst_VPA_SYNC.AP +1 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030 +1 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_140 +11 1 +.names BGACK_000.BLIF BGACK_000_c +1 1 +.names N_71.BLIF SM_AMIGA_1_.BLIF N_139 +11 1 +.names CLK_030.BLIF CLK_030_c +1 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names CLK_000.BLIF CLK_000_c +1 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_137 +11 1 +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +1 1 +.names CLK_OSZI.BLIF CLK_OSZI_c +1 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT +1 1 +.names N_137_i.BLIF N_138_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names RST_i.BLIF inst_DSACK1_INT.AP +1 1 +.names CLK_OUT_INTreg.BLIF CLK_EXP +1 1 +.names CLK_000_D0_i.BLIF N_134_i.BLIF SM_AMIGA_4_.D +11 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS +1 1 +.names inst_CLK_000_D0.BLIF N_133_i.BLIF SM_AMIGA_5_.D +11 1 +.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_ +1 1 +.names N_131_i.BLIF N_132_i.BLIF SM_AMIGA_6_.D +11 1 +.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ +1 1 +.names N_73_i.BLIF N_130_i.BLIF state_machine_lds_000_int_5_0_n +11 1 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 .names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ 1 1 -.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n +.names A0_i.BLIF N_73_i.BLIF state_machine_uds_000_int_5_0_n 11 1 .names IPL_0_.BLIF ipl_c_0__n 1 1 -.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n +.names N_127_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i.BLIF N_35_0 11 1 .names RST_i.BLIF inst_VMA_INTreg.AP 1 1 .names IPL_1_.BLIF ipl_c_1__n 1 1 -.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D -1- 1 --1 1 +.names AS_030_i.BLIF N_126_i.BLIF N_33_0 +11 1 .names IPL_2_.BLIF ipl_c_2__n 1 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n -0 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +.names AS_030_i.BLIF N_228_i.BLIF N_216_0 11 1 -.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +.names AS_030_i.BLIF N_73.BLIF N_215_0 11 1 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D -1- 1 --1 1 -.names vcc_n_n.BLIF AVEC -1 1 -.names N_54.BLIF ipl_030_0_0__un3_n -0 1 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 -.names IPL_030DFFSH_0_reg.BLIF N_54.BLIF ipl_030_0_0__un1_n +.names BG_030_c_i.BLIF N_227_i.BLIF state_machine_un10_bg_030_0_n 11 1 -.names cpu_est_3_reg.BLIF E -1 1 -.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n -11 1 -.names VPA.BLIF inst_VPA_D.D -1 1 -.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D -1- 1 --1 1 -.names inst_VMA_INTreg.BLIF VMA -1 1 -.names N_54.BLIF ipl_030_0_1__un3_n -0 1 .names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 -.names RST.BLIF RST_c -1 1 -.names IPL_030DFFSH_1_reg.BLIF N_54.BLIF ipl_030_0_1__un1_n +.names AS_030_i.BLIF N_224_i.BLIF N_214_0 11 1 -.names RESETDFFRHreg.BLIF RESET +.names vcc_n_n.BLIF AVEC 1 1 -.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +.names BGACK_000_c.BLIF N_65.BLIF state_machine_un6_bgack_000_0_n 11 1 .names RST_i.BLIF inst_BGACK_030_INTreg.AP 1 1 +.names UDS_000_c.BLIF UDS_000_i +0 1 +.names cpu_est_3_reg.BLIF E +1 1 +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names VPA.BLIF VPA_c +1 1 +.names inst_VMA_INTreg.BLIF VMA +1 1 +.names CLK_000_D0_i.BLIF N_67_i.BLIF N_75_0 +11 1 +.names CLK_OSZI_i.BLIF CLK_CNT_N_0_.C +1 1 +.names RST.BLIF RST_c +1 1 +.names N_61_0.BLIF N_156_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i +11 1 +.names RESETDFFRHreg.BLIF RESET +1 1 +.names DS_030_c_i.BLIF N_57.BLIF N_73_i +11 1 +.names RST_i.BLIF CLK_CNT_N_0_.AR +1 1 .names RW.BLIF RW_c 1 1 -.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D -1- 1 --1 1 +.names CLK_000_D0_i.BLIF state_machine_un6_clk_000_d5_i_n.BLIF N_71_i +11 1 .names FC_0_.BLIF fc_c_0__n 1 1 -.names N_54.BLIF ipl_030_0_2__un3_n -0 1 +.names N_151.BLIF N_175_i.BLIF un1_as_000_dma5_i_0__n +11 1 .names FC_1_.BLIF fc_c_1__n 1 1 -.names IPL_030DFFSH_2_reg.BLIF N_54.BLIF ipl_030_0_2__un1_n +.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_67_i 11 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D 1 1 -.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +.names AMIGA_BUS_ENABLEDFFSHreg.BLIF AMIGA_BUS_ENABLE +1 1 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_65_i 11 1 -.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C +.names AMIGA_BUS_DATA_DIR_m1_0_x2.BLIF AMIGA_BUS_DATA_DIR 1 1 -.names RW_i.BLIF AMIGA_BUS_DATA_DIR +.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_i.BLIF N_62_i +11 1 +.names CLK_OSZI_i.BLIF CLK_CNT_N_1_.C 1 1 -.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D -1- 1 --1 1 .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 -.names N_54.BLIF cpu_estse_0_un3_n -0 1 -.names RST_i.BLIF inst_AS_000_INTreg.AP +.names AS_030_i.BLIF N_223_i.BLIF N_61_0 +11 1 +.names inst_AS_000_INT.BLIF inst_CLK_000_D0.BLIF N_59_i +11 1 +.names RST_i.BLIF CLK_CNT_N_1_.AP 1 1 -.names cpu_est_1_.BLIF N_54.BLIF cpu_estse_0_un1_n +.names N_59_i.BLIF N_154.BLIF N_221_1 11 1 -.names N_50_i.BLIF N_130.BLIF N_73_1 +.names RW_c.BLIF state_machine_uds_000_int_5_0_m2_un3_n +0 1 +.names N_221_1.BLIF cpu_est_2_.BLIF N_221 11 1 -.names cpu_est_ns_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n +.names SM_AMIGA_5_.BLIF RW_c.BLIF state_machine_uds_000_int_5_0_m2_un1_n 11 1 -.names N_73_1.BLIF cpu_est_2_.BLIF N_73 +.names CLK_000_D0_i.BLIF N_155.BLIF N_219_1 11 1 -.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D +.names SM_AMIGA_4_.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF state_machine_uds_000_int_5_0_m2_un0_n +11 1 +.names N_219_1.BLIF VPA_i.BLIF N_219 +11 1 +.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_57 1- 1 -1 1 -.names CLK_000_D0_i.BLIF N_131.BLIF N_72_1 -11 1 -.names N_54.BLIF cpu_estse_1_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +.names CLK_OSZI_c.BLIF CLK_CNT_P_0_.C 1 1 -.names N_72_1.BLIF VPA_D_i.BLIF N_72 +.names N_151_1.BLIF BGACK_030_INT_i.BLIF N_151 11 1 -.names cpu_est_2_.BLIF N_54.BLIF cpu_estse_1_un1_n +.names N_144_i.BLIF un1_as_000_dma5_i_0__n.BLIF state_machine_ds_000_dma_5_0_n 11 1 -.names N_74_1.BLIF N_74_2.BLIF N_74_3 +.names N_176_i.BLIF N_151.BLIF SIZE_DMA_1_sqmuxa_1 11 1 -.names cpu_est_ns_2__n.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n +.names N_141_i.BLIF N_142_i.BLIF sm_amiga_ns_0_7__n 11 1 -.names RST_i.BLIF inst_CLK_OUT_PRE.AR +.names RST_i.BLIF CLK_CNT_P_0_.AR 1 1 -.names N_74_3.BLIF VPA_D_i.BLIF N_74 +.names SIZE_DMA_1_sqmuxa_1.BLIF N_175_i.BLIF SIZE_DMA_1_sqmuxa 11 1 -.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D -1- 1 --1 1 -.names AS_030_c.BLIF CLK_000_c.BLIF N_70_1 +.names N_139_i.BLIF N_140_i.BLIF N_46_0 11 1 -.names N_54.BLIF cpu_estse_2_un3_n -0 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_70_2 -11 1 -.names cpu_est_3_reg.BLIF N_54.BLIF cpu_estse_2_un1_n -11 1 -.names N_70_1.BLIF N_70_2.BLIF N_70 -11 1 -.names N_158_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n -11 1 -.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C -1 1 -.names N_124_i.BLIF N_85_i.BLIF sm_amiga_ns_0_1_0__n -11 1 -.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D -1- 1 --1 1 -.names sm_amiga_ns_0_1_0__n.BLIF N_123_i.BLIF sm_amiga_ns_0_0__n -11 1 -.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF state_machine_un23_clk_000_d0_0_n -11 1 -.names RST_i.BLIF CLK_OUT_INTreg.AR -1 1 -.names N_228_i.BLIF N_122_i.BLIF cpu_est_ns_0_1_2__n -11 1 -.names inst_CLK_000_D6.BLIF CLK_000_D6_i -0 1 -.names cpu_est_ns_0_1_2__n.BLIF N_227_i.BLIF cpu_est_ns_0_2__n -11 1 -.names inst_CLK_000_D5.BLIF CLK_000_D6_i.BLIF state_machine_un6_clk_000_d5_n -11 1 -.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF N_226_1 -11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i -0 1 -.names N_226_1.BLIF sm_amiga_i_6__n.BLIF N_226 -11 1 -.names G_108.BLIF G_102.BLIF inst_CLK_OUT_PRE.D -11 1 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C -1 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_1_.BLIF N_220_1 -11 1 -.names N_30.BLIF as_030_000_sync_0_un3_n -0 1 -.names N_220_1.BLIF state_machine_un6_clk_000_d5_i_n.BLIF N_220 -11 1 -.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_30.BLIF as_030_000_sync_0_un1_n -11 1 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP -1 1 -.names a_i_0__n.BLIF size_c_0__n.BLIF N_82_1 -11 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n -11 1 -.names N_82_1.BLIF size_i_1__n.BLIF N_82 -11 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D -1- 1 --1 1 -.names a_i_19__n.BLIF a_i_16__n.BLIF N_55_i_3 -11 1 -.names N_78.BLIF N_78_i -0 1 -.names N_55_i_1.BLIF N_55_i_2.BLIF N_55_i_4 -11 1 -.names N_26.BLIF dtack_sync_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C -1 1 -.names N_55_i_3.BLIF a_i_18__n.BLIF N_55_i_5 -11 1 -.names N_78_i.BLIF N_26.BLIF dtack_sync_0_un1_n -11 1 -.names N_55_i_4.BLIF N_55_i_5.BLIF N_55_i -11 1 -.names inst_DTACK_SYNC.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n -11 1 -.names RST_i.BLIF inst_DTACK_SYNC.AP -1 1 -.names N_129_i.BLIF N_131_i.BLIF cpu_est_ns_0_1_1__n -11 1 -.names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D -1- 1 --1 1 -.names N_221_i.BLIF N_222_i.BLIF cpu_est_ns_0_2_1__n -11 1 -.names N_206.BLIF fpu_cs_int_0_un3_n -0 1 -.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n -11 1 -.names AS_030_c.BLIF N_206.BLIF fpu_cs_int_0_un1_n -11 1 -.names CLK_030_c.BLIF N_55.BLIF N_80_1 -11 1 -.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C -1 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_80_2 -11 1 -.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D -1- 1 --1 1 -.names N_80_1.BLIF N_80_2.BLIF N_80 -11 1 -.names N_51.BLIF dsack_int_0_1__un3_n -0 1 -.names RST_i.BLIF inst_FPU_CS_INTreg.AP -1 1 -.names inst_CLK_000_D0.BLIF DTACK_i.BLIF N_78_1 -11 1 -.names N_57.BLIF N_51.BLIF dsack_int_0_1__un1_n -11 1 -.names SM_AMIGA_3_.BLIF inst_VPA_D.BLIF N_78_2 -11 1 -.names DSACK_INT_1_.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n -11 1 -.names N_78_1.BLIF N_78_2.BLIF N_78 -11 1 -.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D -1- 1 --1 1 -.names inst_CLK_000_D0.BLIF N_59_i.BLIF N_74_1 -11 1 -.names RST_c.BLIF amiga_bus_enable_0_un3_n -0 1 -.names CLK_OSZI_c.BLIF DSACK_INT_1_.C -1 1 -.names SM_AMIGA_3_.BLIF VMA_INT_i.BLIF N_74_2 -11 1 -.names N_44_i.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n -11 1 -.names state_machine_un23_clk_000_d0_0_n.BLIF state_machine_un23_clk_000_d0_n -0 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF amiga_bus_enable_0_un0_n -11 1 -.names RST_i.BLIF DSACK_INT_1_.AP -1 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_236_1 -11 1 -.names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF AMIGA_BUS_ENABLEDFFreg.D -1- 1 --1 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_236_2 -11 1 -.names N_204.BLIF uds_000_int_0_un3_n -0 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_236_3 -11 1 -.names state_machine_uds_000_int_5_n.BLIF N_204.BLIF uds_000_int_0_un1_n -11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_236_4 -11 1 -.names inst_UDS_000_INTreg.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C -1 1 -.names N_236_1.BLIF N_236_2.BLIF N_236_5 -11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D -1- 1 --1 1 -.names N_236_3.BLIF N_236_4.BLIF N_236_6 -11 1 -.names N_204.BLIF lds_000_int_0_un3_n -0 1 -.names N_236_5.BLIF N_236_6.BLIF N_236 -11 1 -.names state_machine_lds_000_int_5_n.BLIF N_204.BLIF lds_000_int_0_un1_n -11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_239_1 -11 1 -.names inst_LDS_000_INTreg.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n -11 1 -.names CLK_OSZI_c.BLIF inst_DTACK_DMA.C -1 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_239_2 -11 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D -1- 1 --1 1 -.names N_239_1.BLIF N_239_2.BLIF N_239 -11 1 -.names vcc_n_n -1 -.names RST_i.BLIF inst_DTACK_DMA.AP -1 1 .names inst_CLK_000_D3.BLIF AS_030_000_SYNC_i.BLIF state_machine_un8_clk_000_d2_1_n 11 1 -.names gnd_n_n +.names N_135_i.BLIF N_136_i.BLIF SM_AMIGA_3_.D +11 1 .names state_machine_un8_clk_000_d2_1_n.BLIF CLK_000_D2_i.BLIF state_machine_un8_clk_000_d2_n 11 1 -.names A_15_.BLIF a_15__n -1 1 -.names a_c_17__n.BLIF BGACK_000_c.BLIF N_55_i_1 +.names N_143_i.BLIF N_154_i.BLIF N_161_i 11 1 -.names A_14_.BLIF a_14__n -1 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_55_i_2 +.names N_173_i.BLIF N_132_i.BLIF sm_amiga_ns_0_1_0__n 11 1 -.names A_13_.BLIF a_13__n +.names N_88_i.BLIF N_145_i.BLIF cpu_est_ns_0_2__n +11 1 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C 1 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D5.C +.names sm_amiga_ns_0_1_0__n.BLIF N_146_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names N_147_i.BLIF N_148_i.BLIF cpu_est_ns_e_0_0__n +11 1 +.names N_155_i.BLIF cpu_est_ns_0_0_x2_1_.BLIF cpu_est_ns_0_1_1__n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names RST_i.BLIF inst_LDS_000_INT.AP 1 1 -.names state_machine_uds_000_int_5_0_n.BLIF state_machine_uds_000_int_5_n +.names cpu_est_ns_0_1_1__n.BLIF N_153_i.BLIF cpu_est_ns_0_1__n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_72_i +11 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_138_1 +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n 0 1 -.names A_12_.BLIF a_12__n +.names N_138_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_138 +11 1 +.names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_0_n.BLIF N_77_0 +11 1 +.names A0_i.BLIF size_c_0__n.BLIF N_130_1 +11 1 +.names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C 1 1 -.names N_80.BLIF N_80_i +.names N_130_1.BLIF size_i_1__n.BLIF N_130 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n 0 1 -.names A_11_.BLIF a_11__n +.names LDS_000_i.BLIF N_151.BLIF N_128_1 +11 1 +.names cpu_est_1_.BLIF cpu_est_ns_0_0_m2_2__un3_n +0 1 +.names RST_i.BLIF inst_DTACK_SYNC.AP 1 1 -.names RST_i.BLIF inst_CLK_000_D5.AP +.names N_128_1.BLIF UDS_000_c.BLIF N_128 +11 1 +.names cpu_est_2_.BLIF cpu_est_1_.BLIF cpu_est_ns_0_0_m2_2__un1_n +11 1 +.names N_62.BLIF N_67.BLIF N_52_0_1 +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_ns_0_0_m2_2__un3_n.BLIF cpu_est_ns_0_0_m2_2__un0_n +11 1 +.names N_173_i.BLIF N_226_i.BLIF N_52_0_2 +11 1 +.names cpu_est_ns_0_0_m2_2__un1_n.BLIF cpu_est_ns_0_0_m2_2__un0_n.BLIF N_88 +1- 1 +-1 1 +.names N_52_0_1.BLIF N_52_0_2.BLIF N_52_0 +11 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C 1 1 -.names N_30_0.BLIF N_30 +.names N_72_i.BLIF N_228_1.BLIF N_224_1 +11 1 +.names VPA_c.BLIF VPA_i 0 1 -.names A_10_.BLIF a_10__n +.names VMA_INT_i.BLIF VPA_i.BLIF N_224_2 +11 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF N_228_1 +11 1 +.names RST_i.BLIF inst_A0_DMA.AP 1 1 -.names N_26_0.BLIF N_26 +.names N_224_1.BLIF N_224_2.BLIF N_224 +11 1 +.names DTACK_c.BLIF DTACK_i 0 1 -.names A_9_.BLIF a_9__n +.names AS_030_c.BLIF CLK_000_c.BLIF N_227_1 +11 1 +.names N_62.BLIF N_173.BLIF N_225 +11 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_227_2 +11 1 +.names A0_c.BLIF A0_i +0 1 +.names N_227_1.BLIF N_227_2.BLIF N_227 +11 1 +.names size_c_1__n.BLIF size_i_1__n +0 1 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C 1 1 -.names N_76.BLIF N_76_i -0 1 -.names A_8_.BLIF a_8__n +.names DTACK_i.BLIF N_228_1.BLIF N_228_1_0 +11 1 +.names CLK_000_D0_i.BLIF N_77.BLIF N_135 +11 1 +.names N_228_1_0.BLIF VPA_c.BLIF N_228 +11 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_136 +11 1 +.names RST_i.BLIF BG_000DFFSHreg.AP 1 1 -.names inst_CLK_000_D5.BLIF inst_CLK_000_D6.D +.names CLK_030_c.BLIF N_66.BLIF N_127_1 +11 1 +.names N_72.BLIF cpu_est_2_.BLIF N_143 +11 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_127_2 +11 1 +.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_145 +11 1 +.names N_127_1.BLIF N_127_2.BLIF N_127 +11 1 +.names N_65.BLIF cpu_est_0_.BLIF N_147 +11 1 +.names CLK_030_c_i.BLIF AS_000_c_i.BLIF N_151_1 +11 1 +.names N_65_i.BLIF cpu_est_i_0__n.BLIF N_148 +11 1 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C 1 1 -.names N_206_0.BLIF N_206 -0 1 -.names A_7_.BLIF a_7__n +.names a_i_16__n.BLIF a_i_18__n.BLIF N_66_i_2 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_153 +11 1 +.names a_c_17__n.BLIF fc_c_0__n.BLIF N_66_i_3 +11 1 +.names N_153.BLIF cpu_est_i_3__n.BLIF N_154 +11 1 +.names RST_i.BLIF inst_AS_000_DMA.AP 1 1 -.names N_205_0.BLIF N_205 +.names N_66_i_1.BLIF N_66_i_2.BLIF N_66_i_4 +11 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n 0 1 -.names A_6_.BLIF a_6__n +.names N_66_i_3.BLIF fc_c_1__n.BLIF N_66_i_5 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_155 +11 1 +.names N_66_i_4.BLIF N_66_i_5.BLIF N_66_i +11 1 +.names N_219_i.BLIF N_221_i.BLIF state_machine_un15_clk_000_d0_0_n +11 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_237_1 +11 1 +.names N_225_i.BLIF N_226_i.BLIF un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0 +11 1 +.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFSHreg.C 1 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D6.C +.names a_c_22__n.BLIF a_c_23__n.BLIF N_237_2 +11 1 +.names RST_c.BLIF RST_i +0 1 +.names N_237_1.BLIF N_237_2.BLIF N_237 +11 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 +.names RST_i.BLIF AMIGA_BUS_ENABLEDFFSHreg.AP 1 1 -.names N_72.BLIF N_72_i +.names a_i_24__n.BLIF a_i_25__n.BLIF N_247_1 +11 1 +.names a_c_25__n.BLIF a_i_25__n 0 1 -.names A_5_.BLIF a_5__n +.names a_i_26__n.BLIF a_i_27__n.BLIF N_247_2 +11 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_247_3 +11 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_247_4 +11 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C 1 1 -.names N_73.BLIF N_73_i +.names N_247_1.BLIF N_247_2.BLIF N_247_5 +11 1 +.names a_c_29__n.BLIF a_i_29__n 0 1 -.names A_4_.BLIF a_4__n +.names N_247_3.BLIF N_247_4.BLIF N_247_6 +11 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names RST_i.BLIF inst_AS_000_INT.AP 1 1 -.names RST_i.BLIF inst_CLK_000_D6.AP -1 1 -.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n +.names N_247_5.BLIF N_247_6.BLIF N_247 +11 1 +.names a_c_31__n.BLIF a_i_31__n 0 1 -.names A_3_.BLIF a_3__n -1 1 -.names N_204_0.BLIF N_204 +.names N_145.BLIF N_145_i 0 1 -.names A_2_.BLIF a_2__n -1 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names A_1_.BLIF a_1__n -1 1 -.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D -1 1 -.names N_70.BLIF N_70_i -0 1 -.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D4.C -1 1 -.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n -0 1 -.names N_219.BLIF N_219_i -0 1 -.names RST_i.BLIF inst_CLK_000_D4.AP -1 1 -.names N_220.BLIF N_220_i -0 1 -.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D -0 1 -.names N_215.BLIF N_215_i -0 1 -.names inst_CLK_000_D1.BLIF inst_CLK_000_D2.D -1 1 -.names N_216.BLIF N_216_i -0 1 -.names N_95.BLIF N_95_i -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D2.C -1 1 -.names N_214.BLIF N_214_i -0 1 -.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D -0 1 -.names RST_i.BLIF inst_CLK_000_D2.AP -1 1 -.names N_94.BLIF N_94_i -0 1 -.names N_133.BLIF N_133_i -0 1 -.names N_87.BLIF N_87_i -0 1 -.names inst_CLK_000_D2.BLIF inst_CLK_000_D3.D -1 1 -.names N_86.BLIF N_86_i -0 1 -.names N_83.BLIF N_83_i -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D3.C -1 1 -.names N_82.BLIF N_82_i -0 1 -.names state_machine_lds_000_int_5_0_n.BLIF state_machine_lds_000_int_5_n -0 1 -.names RST_i.BLIF inst_CLK_000_D3.AP -1 1 -.names N_50_i.BLIF N_50 -0 1 -.names N_125.BLIF N_125_i -0 1 -.names N_126.BLIF N_126_i -0 1 -.names cpu_est_ns_e_0_0__n.BLIF cpu_est_0_.D -0 1 -.names CLK_OSZI_c.BLIF inst_VPA_D.C -1 1 -.names N_85.BLIF N_85_i -0 1 -.names N_123.BLIF N_123_i -0 1 -.names RST_i.BLIF inst_VPA_D.AP -1 1 -.names N_124.BLIF N_124_i -0 1 -.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D -0 1 -.names N_122.BLIF N_122_i -0 1 -.names CLK_000_c.BLIF inst_CLK_000_D0.D -1 1 -.names N_227.BLIF N_227_i -0 1 -.names N_228.BLIF N_228_i -0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C -1 1 .names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n 0 1 -.names N_226.BLIF N_226_i +.names N_143.BLIF N_143_i 0 1 -.names RST_i.BLIF inst_CLK_000_D0.AP +.names G_103.BLIF CLK_CNT_N_0_.D +0 1 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C 1 1 -.names N_130.BLIF N_130_i +.names N_154.BLIF N_154_i 0 1 +.names CLK_OSZI_c.BLIF CLK_OSZI_i +0 1 +.names N_153.BLIF N_153_i +0 1 +.names G_109.BLIF CLK_CNT_P_0_.D +0 1 +.names RST_i.BLIF inst_AS_030_000_SYNC.AP +1 1 +.names N_155.BLIF N_155_i +0 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +0 1 +.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n +0 1 +.names G_109.BLIF G_103.BLIF inst_CLK_OUT_PRE.D +11 1 +.names N_135.BLIF N_135_i +0 1 +.names N_52.BLIF amiga_bus_enable_0_un3_n +0 1 +.names N_136.BLIF N_136_i +0 1 +.names un1_AMIGA_BUS_ENABLE_0_sqmuxa_2.BLIF N_52.BLIF amiga_bus_enable_0_un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 .names N_225.BLIF N_225_i 0 1 +.names AMIGA_BUS_ENABLEDFFSHreg.BLIF amiga_bus_enable_0_un3_n.BLIF amiga_bus_enable_0_un0_n +11 1 +.names un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_0_sqmuxa_2 +0 1 +.names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF AMIGA_BUS_ENABLEDFFSHreg.D +1- 1 +-1 1 +.names RST_i.BLIF inst_DS_000_DMA.AP +1 1 +.names N_219.BLIF N_219_i +0 1 +.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n +0 1 .names N_221.BLIF N_221_i 0 1 -.names vcc_n_n.BLIF RESETDFFRHreg.D +.names N_59_i.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +11 1 +.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n +0 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names BGACK_000_c.BLIF a_i_19__n.BLIF N_66_i_1 +11 1 +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C 1 1 -.names N_222.BLIF N_222_i +.names N_156.BLIF N_156_i 0 1 -.names N_63_0.BLIF N_63 +.names N_65.BLIF ipl_030_0_0__un3_n 0 1 -.names CLK_OSZI_c.BLIF RESETDFFRHreg.C +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_4 +0 1 +.names IPL_030DFFSH_0_reg.BLIF N_65.BLIF ipl_030_0_0__un1_n +11 1 +.names RST_i.BLIF inst_FPU_CS_INTreg.AP 1 1 -.names N_62_0.BLIF N_62 +.names N_75_0.BLIF N_75 0 1 -.names N_132.BLIF N_132_i +.names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n +11 1 +.names N_176.BLIF N_176_i 0 1 -.names RST_i.BLIF RESETDFFRHreg.AR +.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D +1- 1 +-1 1 +.names N_52_0.BLIF N_52 +0 1 +.names N_65.BLIF ipl_030_0_1__un3_n +0 1 +.names N_173.BLIF N_173_i +0 1 +.names IPL_030DFFSH_1_reg.BLIF N_65.BLIF ipl_030_0_1__un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C 1 1 -.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 +.names N_226.BLIF N_226_i 0 1 -.names DS_030_c.BLIF DS_030_c_i +.names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n +11 1 +.names N_77_0.BLIF N_77 0 1 -.names CLK_OSZI_c.BLIF cpu_est_1_.C +.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D +1- 1 +-1 1 +.names RST_i.BLIF inst_UDS_000_INT.AP 1 1 -.names N_60_i.BLIF N_60 +.names N_72_i.BLIF N_72 0 1 -.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D +.names N_65.BLIF ipl_030_0_2__un3_n +0 1 +.names N_147.BLIF N_147_i +0 1 +.names IPL_030DFFSH_2_reg.BLIF N_65.BLIF ipl_030_0_2__un1_n +11 1 +.names N_148.BLIF N_148_i +0 1 +.names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n +11 1 +.names cpu_est_ns_e_0_0__n.BLIF cpu_est_0_.D +0 1 +.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C 1 1 +.names N_146.BLIF N_146_i +0 1 +.names N_65.BLIF cpu_estse_0_un3_n +0 1 +.names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D +0 1 +.names cpu_est_1_.BLIF N_65.BLIF cpu_estse_0_un1_n +11 1 +.names RST_i.BLIF CLK_OUT_INTreg.AR +1 1 +.names N_88.BLIF N_88_i +0 1 +.names cpu_est_ns_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n +11 1 +.names CLK_030_c.BLIF CLK_030_c_i +0 1 +.names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D +1- 1 +-1 1 +.names AS_000_c.BLIF AS_000_c_i +0 1 +.names N_65.BLIF cpu_estse_1_un3_n +0 1 .names N_59_i.BLIF N_59 0 1 -.names RST_i.BLIF cpu_est_1_.AR +.names cpu_est_2_.BLIF N_65.BLIF cpu_estse_1_un1_n +11 1 +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C 1 1 -.names N_57_i.BLIF N_57 +.names N_61_0.BLIF N_61 0 1 -.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C -1 1 -.names N_56_i.BLIF N_56 +.names cpu_est_ns_2__n.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n +11 1 +.names N_62_i.BLIF N_62 0 1 -.names N_55_i.BLIF N_55 -0 1 -.names RST_i.BLIF inst_CLK_000_D1.AP +.names cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF cpu_est_2_.D +1- 1 +-1 1 +.names RST_i.BLIF inst_CLK_OUT_PRE.AR 1 1 .names inst_CLK_000_D1.BLIF CLK_000_D1_i 0 1 -.names CLK_OSZI_c.BLIF cpu_est_2_.C -1 1 -.names N_54_i.BLIF N_54 +.names N_65.BLIF cpu_estse_2_un3_n 0 1 -.names N_51_i.BLIF N_51 +.names N_65_i.BLIF N_65 0 1 -.names RST_i.BLIF cpu_est_2_.AR -1 1 -.names CLK_CNT_N_0_.BLIF G_102.X1 -1 1 -.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n +.names cpu_est_3_reg.BLIF N_65.BLIF cpu_estse_2_un1_n +11 1 +.names N_66_i.BLIF N_66 0 1 -.names N_129.BLIF N_129_i +.names N_161_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n +11 1 +.names N_67_i.BLIF N_67 0 1 -.names CLK_CNT_N_1_.BLIF G_102.X2 +.names cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF cpu_est_3_reg.D +1- 1 +-1 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D5.C 1 1 +.names N_175.BLIF N_175_i +0 1 +.names vcc_n_n +1 +.names un1_as_000_dma5_i_0__n.BLIF un1_as_000_dma5_0__n +0 1 +.names gnd_n_n +.names RST_i.BLIF inst_CLK_000_D5.AP +1 1 +.names state_machine_un6_clk_000_d5_n.BLIF state_machine_un6_clk_000_d5_i_n +0 1 +.names N_71_i.BLIF N_71 +0 1 +.names DS_030_c.BLIF DS_030_c_i +0 1 +.names inst_CLK_000_D5.BLIF inst_CLK_000_D6.D +1 1 +.names N_73_i.BLIF N_73 +0 1 +.names N_132.BLIF N_132_i +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D6.C +1 1 +.names N_131.BLIF N_131_i +0 1 +.names N_133.BLIF N_133_i +0 1 +.names RST_i.BLIF inst_CLK_000_D6.AP +1 1 +.names N_134.BLIF N_134_i +0 1 +.names N_137.BLIF N_137_i +0 1 +.names N_138.BLIF N_138_i +0 1 +.names inst_CLK_000_D3.BLIF inst_CLK_000_D4.D +1 1 +.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D +0 1 +.names N_139.BLIF N_139_i +0 1 +.names CLK_OSZI_c.BLIF inst_CLK_000_D4.C +1 1 +.names N_140.BLIF N_140_i +0 1 +.names N_46_0.BLIF SM_AMIGA_1_.D +0 1 +.names RST_i.BLIF inst_CLK_000_D4.AP +1 1 +.names N_142.BLIF N_142_i +0 1 +.names N_141.BLIF N_141_i +0 1 .end diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1 index 57665da..b6c6592 100644 --- a/Logic/BUS68030.bl1 +++ b/Logic/BUS68030.bl1 @@ -1,271 +1,306 @@ #$ TOOL ispLEVER Classic 1.7.00.05.28.13 -#$ DATE Sat May 24 19:56:20 2014 +#$ DATE Sat May 24 21:59:14 2014 #$ MODULE bus68030 -#$ PINS 74 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 SIZE_0_ DS_030 \ -# A_30_ UDS_000 A_29_ LDS_000 A_28_ nEXP_SPACE A_27_ BERR A_26_ BG_030 A_25_ BG_000 A_24_ \ -# BGACK_030 A_23_ BGACK_000 A_22_ CLK_030 A_21_ CLK_000 A_20_ CLK_OSZI A_19_ CLK_DIV_OUT \ -# A_18_ CLK_EXP A_17_ FPU_CS A_16_ DTACK A_15_ AVEC A_14_ AVEC_EXP A_13_ E A_12_ VPA A_11_ VMA \ -# A_10_ RST A_9_ RESET A_8_ RW A_7_ AMIGA_BUS_ENABLE A_6_ AMIGA_BUS_DATA_DIR A_5_ \ -# AMIGA_BUS_ENABLE_LOW A_4_ CIIN A_3_ A_2_ A_1_ A_0_ IPL_030_1_ IPL_030_0_ IPL_1_ IPL_0_ \ -# DSACK_0_ FC_0_ -#$ NODES 365 CLK_000_c CLK_OSZI_c CLK_OUT_INTreg inst_BGACK_030_INTreg \ -# inst_FPU_CS_INTreg IPL_030DFFSH_0_reg inst_VMA_INTreg inst_AS_000_INTreg \ -# IPL_030DFFSH_1_reg inst_AS_030_000_SYNC inst_DTACK_SYNC IPL_030DFFSH_2_reg \ -# inst_VPA_D inst_VPA_SYNC ipl_c_0__n inst_CLK_000_D0 inst_CLK_000_D1 ipl_c_1__n \ -# inst_CLK_000_D2 inst_CLK_000_D6 ipl_c_2__n SM_AMIGA_5_ SM_AMIGA_6_ vcc_n_n \ -# dsack_c_1__n gnd_n_n inst_UDS_000_INTreg DTACK_c inst_LDS_000_INTreg DSACK_INT_1_ \ -# AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d2_n inst_CLK_000_D3 SM_AMIGA_4_ \ -# state_machine_un23_clk_000_d0_n state_machine_un6_clk_000_d5_n RST_c \ -# inst_CLK_000_D5 SM_AMIGA_7_ RESETDFFRHreg SM_AMIGA_3_ \ -# state_machine_un6_bgack_000_n RW_c SM_AMIGA_1_ inst_DTACK_DMA fc_c_0__n G_102 \ -# CLK_CNT_N_0_ fc_c_1__n CLK_CNT_N_1_ G_108 AMIGA_BUS_ENABLEDFFreg CLK_CNT_P_0_ \ -# CLK_CNT_P_1_ SM_AMIGA_2_ SM_AMIGA_0_ state_machine_un10_bg_030_n cpu_est_ns_0_1__n \ -# state_machine_un7_as_000_int_n N_129_i inst_CLK_000_D4 N_131_i \ -# state_machine_un15_clk_000_d0_n N_221_i state_machine_lds_000_int_5_n N_222_i \ -# state_machine_uds_000_int_5_n N_63_0 un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_62_0 \ -# inst_CLK_OUT_PRE N_132_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_60_i N_59_i \ -# N_57_i N_56_i N_55_i CLK_000_D1_i N_54_i N_51_i N_50_i N_125_i N_126_i \ -# cpu_est_ns_e_0_0__n N_85_i N_123_i N_124_i sm_amiga_ns_0_0__n cpu_est_0_ N_122_i \ -# cpu_est_1_ N_227_i cpu_est_2_ N_228_i cpu_est_3_reg cpu_est_ns_0_2__n N_226_i N_44_i \ -# N_130_i N_225_i cpu_est_ns_1__n N_158_i cpu_est_ns_2__n N_219_i N_204 N_220_i N_205 \ -# sm_amiga_ns_0_7__n N_206 N_215_i N_26 N_216_i N_30 N_49 N_95_i N_50 N_214_i N_51 \ -# sm_amiga_ns_0_5__n N_54 N_94_i N_55 N_133_i N_56 N_57 N_87_i N_59 N_60 N_86_i N_62 N_63 \ -# N_83_i N_68 N_70 N_82_i N_72 state_machine_lds_000_int_5_0_n N_73 \ -# state_machine_uds_000_int_5_0_n N_74 N_80_i N_76 N_30_0 N_78 N_26_0 N_80 N_76_i N_82 \ -# N_206_0 N_83 N_205_0 N_85 N_72_i N_86 N_73_i N_87 state_machine_un15_clk_000_d0_0_n \ -# N_94 N_204_0 N_95 BG_030_c_i N_214 N_70_i N_215 state_machine_un10_bg_030_0_n N_216 \ -# state_machine_un6_bgack_000_0_n N_219 N_220 state_machine_un23_clk_000_d0_0_n \ -# N_221 N_236_1 N_222 N_236_2 N_225 N_236_3 N_226 N_236_4 N_227 N_236_5 N_228 N_236_6 N_122 \ -# N_239_1 N_123 N_239_2 N_124 state_machine_un8_clk_000_d2_1_n N_125 N_55_i_1 N_126 \ -# N_55_i_2 N_129 N_55_i_3 N_130 N_55_i_4 N_131 N_55_i_5 N_132 cpu_est_ns_0_1_1__n N_133 \ -# cpu_est_ns_0_2_1__n N_236 N_80_1 N_239 N_80_2 RW_i N_78_1 VMA_INT_i N_78_2 VPA_D_i \ -# N_74_1 DTACK_i N_74_2 CLK_000_D0_i N_74_3 sm_amiga_i_4__n N_70_1 cpu_est_i_3__n N_70_2 \ -# sm_amiga_i_1__n sm_amiga_ns_0_1_0__n state_machine_un6_clk_000_d5_i_n \ -# cpu_est_ns_0_1_2__n sm_amiga_i_6__n N_226_1 nEXP_SPACE_i N_220_1 AS_000_INT_i N_82_1 \ -# cpu_est_i_1__n N_73_1 cpu_est_i_0__n N_72_1 AMIGA_BUS_ENABLE_i \ -# state_machine_uds_000_int_5_0_m2_un3_n AS_030_i \ -# state_machine_uds_000_int_5_0_m2_un1_n cpu_est_i_2__n \ -# state_machine_uds_000_int_5_0_m2_un0_n sm_amiga_i_2__n vpa_sync_0_un3_n \ -# sm_amiga_i_3__n vpa_sync_0_un1_n sm_amiga_i_5__n vpa_sync_0_un0_n \ -# state_machine_un8_clk_000_d2_i_n vma_int_0_un3_n sm_amiga_i_7__n vma_int_0_un1_n \ -# a_i_0__n vma_int_0_un0_n size_i_1__n bg_000_0_un3_n dsack_i_1__n bg_000_0_un1_n \ -# BGACK_030_INT_i bg_000_0_un0_n CLK_000_D2_i bgack_030_int_0_un3_n \ -# AS_030_000_SYNC_i bgack_030_int_0_un1_n a_i_19__n bgack_030_int_0_un0_n a_i_16__n \ -# as_000_int_0_un3_n a_i_18__n as_000_int_0_un1_n a_i_30__n as_000_int_0_un0_n \ -# a_i_31__n ipl_030_0_0__un3_n a_i_28__n ipl_030_0_0__un1_n a_i_29__n \ -# ipl_030_0_0__un0_n a_i_26__n ipl_030_0_1__un3_n a_i_27__n ipl_030_0_1__un1_n \ -# a_i_24__n ipl_030_0_1__un0_n a_i_25__n ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n \ -# ipl_030_0_2__un0_n cpu_estse_0_un3_n CLK_OSZI_i cpu_estse_0_un1_n \ -# cpu_estse_0_un0_n N_74_i cpu_estse_1_un3_n N_78_i cpu_estse_1_un1_n FPU_CS_INT_i \ -# cpu_estse_1_un0_n CLK_000_D6_i cpu_estse_2_un3_n AS_030_c cpu_estse_2_un1_n \ -# cpu_estse_2_un0_n as_030_000_sync_0_un3_n DS_030_c as_030_000_sync_0_un1_n \ -# as_030_000_sync_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n size_c_0__n \ -# dtack_sync_0_un0_n fpu_cs_int_0_un3_n size_c_1__n fpu_cs_int_0_un1_n \ -# fpu_cs_int_0_un0_n a_c_0__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n \ -# dsack_int_0_1__un0_n amiga_bus_enable_0_un3_n amiga_bus_enable_0_un1_n \ -# amiga_bus_enable_0_un0_n uds_000_int_0_un3_n uds_000_int_0_un1_n \ -# uds_000_int_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n lds_000_int_0_un0_n \ -# a_15__n a_14__n a_13__n a_c_16__n a_12__n a_c_17__n a_11__n a_c_18__n a_10__n a_c_19__n \ -# a_9__n a_c_20__n a_8__n a_c_21__n a_7__n a_c_22__n a_6__n a_c_23__n a_5__n a_c_24__n \ -# a_4__n a_c_25__n a_3__n a_c_26__n a_2__n a_c_27__n a_1__n a_c_28__n a_c_29__n a_c_30__n \ -# a_c_31__n nEXP_SPACE_c BG_030_c BG_000DFFSHreg BGACK_000_c CLK_030_c +#$ PINS 59 IPL_030_1_ IPL_030_0_ SIZE_1_ IPL_1_ IPL_0_ A_31_ DSACK_0_ FC_0_ IPL_030_2_ \ +# IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 nEXP_SPACE BERR BG_030 \ +# BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DTACK \ +# AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ +# AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ \ +# A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ +#$ NODES 398 BG_030_c BG_000DFFSHreg BGACK_000_c inst_BGACK_030_INTreg \ +# inst_FPU_CS_INTreg CLK_030_c inst_VMA_INTreg inst_AS_030_000_SYNC CLK_000_c \ +# inst_BGACK_030_INT_D inst_DTACK_SYNC CLK_OSZI_c inst_VPA_SYNC inst_CLK_000_D0 \ +# inst_CLK_000_D1 CLK_OUT_INTreg inst_CLK_000_D2 inst_CLK_000_D6 SM_AMIGA_5_ \ +# IPL_030DFFSH_0_reg vcc_n_n gnd_n_n IPL_030DFFSH_1_reg inst_AS_000_INT SM_AMIGA_6_ \ +# IPL_030DFFSH_2_reg inst_UDS_000_INT inst_LDS_000_INT ipl_c_0__n inst_DSACK1_INT \ +# inst_CLK_000_D3 ipl_c_1__n state_machine_un23_clk_000_d0_n inst_CLK_000_D5 \ +# ipl_c_2__n SM_AMIGA_3_ SM_AMIGA_0_ SM_AMIGA_1_ dsack_c_1__n inst_AS_000_DMA \ +# inst_DS_000_DMA DTACK_c SIZE_DMA_0_ SIZE_DMA_1_ inst_A0_DMA G_103 CLK_CNT_N_0_ VPA_c \ +# CLK_CNT_N_1_ G_109 CLK_CNT_P_0_ RST_c CLK_CNT_P_1_ inst_CLK_000_D4 RESETDFFRHreg \ +# SM_AMIGA_7_ state_machine_un15_clk_000_d0_n RW_c SM_AMIGA_4_ \ +# un1_AMIGA_BUS_ENABLE_0_sqmuxa_2 fc_c_0__n inst_CLK_OUT_PRE SM_AMIGA_2_ fc_c_1__n \ +# AMIGA_BUS_ENABLEDFFSHreg state_machine_un23_clk_000_d0_0_n \ +# state_machine_un6_bgack_000_0_n N_214_0 BG_030_c_i N_227_i \ +# state_machine_un10_bg_030_0_n N_215_0 N_216_0 N_126_i N_33_0 N_127_i N_35_0 \ +# state_machine_uds_000_int_5_0_n N_130_i state_machine_lds_000_int_5_0_n N_132_i \ +# N_131_i cpu_est_0_ cpu_est_1_ N_133_i cpu_est_2_ cpu_est_3_reg N_134_i N_137_i N_138_i \ +# sm_amiga_ns_0_5__n cpu_est_ns_1__n N_139_i cpu_est_ns_2__n N_140_i N_46_0 N_52 \ +# N_142_i N_59 N_141_i N_62 sm_amiga_ns_0_7__n N_65 N_144_i N_67 \ +# state_machine_ds_000_dma_5_0_n N_72 CLK_030_c_i N_77 AS_000_c_i N_88 N_59_i N_217 \ +# N_61_0 N_219 N_62_i N_221 CLK_000_D1_i N_224 N_65_i N_225 N_66_i N_226 N_67_i N_128 \ +# N_175_i N_130 un1_as_000_dma5_i_0__n N_132 state_machine_un6_clk_000_d5_i_n N_135 \ +# N_71_i N_136 DS_030_c_i N_138 N_73_i N_143 N_156_i N_145 \ +# un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i N_146 N_75_0 N_147 N_176_i N_148 N_52_0 N_151 \ +# N_173_i N_153 N_226_i N_154 N_77_0 N_155 N_72_i N_173 N_147_i cpu_est_ns_0_0_x2_1_ \ +# N_148_i AMIGA_BUS_DATA_DIR_m1_0_x2 cpu_est_ns_e_0_0__n N_228_1 N_146_i N_237 \ +# sm_amiga_ns_0_0__n N_247 N_88_i N_227 N_145_i N_228 cpu_est_ns_0_2__n N_127 N_143_i \ +# N_66 N_154_i N_175 N_161_i N_176 N_153_i N_75 N_155_i un1_AMIGA_BUS_ENABLE_1_sqmuxa_4 \ +# cpu_est_ns_0_1__n N_61 N_135_i N_156 N_136_i N_73 N_57 N_225_i N_71 \ +# un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0 state_machine_un6_clk_000_d5_n N_219_i \ +# un1_as_000_dma5_0__n N_221_i N_223 state_machine_un15_clk_000_d0_0_n \ +# state_machine_ds_000_dma_5_n N_144 N_66_i_1 N_141 N_66_i_2 N_142 N_66_i_3 N_139 \ +# N_66_i_4 N_140 N_66_i_5 N_137 N_237_1 N_134 N_237_2 N_133 N_247_1 N_131 N_247_2 \ +# state_machine_lds_000_int_5_n N_247_3 state_machine_uds_000_int_5_n N_247_4 N_35 \ +# N_247_5 N_33 N_247_6 N_126 N_52_0_1 N_216 N_52_0_2 N_215 N_224_1 \ +# state_machine_un10_bg_030_n N_224_2 N_214 N_227_1 state_machine_un6_bgack_000_n \ +# N_227_2 state_machine_un8_clk_000_d2_n N_228_1_0 SIZE_DMA_1_sqmuxa N_127_1 \ +# SIZE_DMA_0_sqmuxa N_127_2 AS_000_INT_1_sqmuxa N_151_1 N_249 SIZE_DMA_1_sqmuxa_1 \ +# CLK_000_D6_i state_machine_un8_clk_000_d2_1_n N_228_i sm_amiga_ns_0_1_0__n \ +# sm_amiga_i_5__n cpu_est_ns_0_1_1__n N_224_i N_138_1 N_223_i N_130_1 \ +# SIZE_DMA_0_sqmuxa_i N_128_1 SIZE_DMA_1_sqmuxa_i N_221_1 a_i_18__n N_219_1 a_i_16__n \ +# vpa_sync_0_un3_n a_i_19__n vpa_sync_0_un1_n AS_030_000_SYNC_i vpa_sync_0_un0_n \ +# CLK_000_D2_i as_000_int_0_un3_n BGACK_030_INT_i as_000_int_0_un1_n nEXP_SPACE_i \ +# as_000_int_0_un0_n AS_030_i as_000_dma_0_un3_n BGACK_030_INT_D_i \ +# as_000_dma_0_un1_n sm_amiga_i_7__n as_000_dma_0_un0_n \ +# state_machine_un8_clk_000_d2_i_n bg_000_0_un3_n sm_amiga_i_6__n bg_000_0_un1_n \ +# sm_amiga_i_4__n bg_000_0_un0_n CLK_000_D0_i a0_dma_0_un3_n RW_i a0_dma_0_un1_n \ +# UDS_000_i a0_dma_0_un0_n LDS_000_i dtack_sync_0_un3_n DTACK_i dtack_sync_0_un1_n \ +# VMA_INT_i dtack_sync_0_un0_n VPA_i lds_000_int_0_un3_n cpu_est_i_0__n \ +# lds_000_int_0_un1_n sm_amiga_i_3__n lds_000_int_0_un0_n cpu_est_i_3__n \ +# uds_000_int_0_un3_n cpu_est_i_1__n uds_000_int_0_un1_n A0_i uds_000_int_0_un0_n \ +# size_i_1__n fpu_cs_int_0_un3_n a_i_30__n fpu_cs_int_0_un1_n a_i_31__n \ +# fpu_cs_int_0_un0_n a_i_28__n ds_000_dma_0_un3_n a_i_29__n ds_000_dma_0_un1_n \ +# a_i_26__n ds_000_dma_0_un0_n a_i_27__n as_030_000_sync_0_un3_n a_i_24__n \ +# as_030_000_sync_0_un1_n a_i_25__n as_030_000_sync_0_un0_n RST_i \ +# size_dma_0_1__un3_n size_dma_0_1__un1_n CLK_OSZI_i size_dma_0_1__un0_n \ +# size_dma_0_0__un3_n FPU_CS_INT_i size_dma_0_0__un1_n AS_030_c size_dma_0_0__un0_n \ +# bgack_030_int_0_un3_n AS_000_c bgack_030_int_0_un1_n bgack_030_int_0_un0_n \ +# DS_030_c dsack1_int_0_un3_n dsack1_int_0_un1_n UDS_000_c dsack1_int_0_un0_n \ +# state_machine_uds_000_int_5_0_m2_un3_n LDS_000_c \ +# state_machine_uds_000_int_5_0_m2_un1_n state_machine_uds_000_int_5_0_m2_un0_n \ +# size_c_0__n cpu_est_ns_0_0_m2_2__un3_n cpu_est_ns_0_0_m2_2__un1_n size_c_1__n \ +# cpu_est_ns_0_0_m2_2__un0_n amiga_bus_enable_0_un3_n a_c_16__n \ +# amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n a_c_17__n vma_int_0_un3_n \ +# vma_int_0_un1_n a_c_18__n vma_int_0_un0_n ipl_030_0_0__un3_n a_c_19__n \ +# ipl_030_0_0__un1_n ipl_030_0_0__un0_n a_c_20__n ipl_030_0_1__un3_n \ +# ipl_030_0_1__un1_n a_c_21__n ipl_030_0_1__un0_n ipl_030_0_2__un3_n a_c_22__n \ +# ipl_030_0_2__un1_n ipl_030_0_2__un0_n a_c_23__n cpu_estse_0_un3_n \ +# cpu_estse_0_un1_n a_c_24__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_25__n \ +# cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_26__n cpu_estse_2_un3_n cpu_estse_2_un1_n \ +# a_c_27__n cpu_estse_2_un0_n a_c_28__n a_c_29__n a_c_30__n a_c_31__n A0_c nEXP_SPACE_c .model bus68030 -.inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \ -nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \ -CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \ -A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \ -A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF \ -A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF \ -A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF A_1_.BLIF \ -A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF \ -DSACK_0_.BLIF CLK_000_c.BLIF CLK_OSZI_c.BLIF CLK_OUT_INTreg.BLIF \ -inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF \ -inst_VMA_INTreg.BLIF inst_AS_000_INTreg.BLIF IPL_030DFFSH_1_reg.BLIF \ -inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF IPL_030DFFSH_2_reg.BLIF \ -inst_VPA_D.BLIF inst_VPA_SYNC.BLIF ipl_c_0__n.BLIF inst_CLK_000_D0.BLIF \ -inst_CLK_000_D1.BLIF ipl_c_1__n.BLIF inst_CLK_000_D2.BLIF inst_CLK_000_D6.BLIF \ -ipl_c_2__n.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_6_.BLIF vcc_n_n.BLIF \ -dsack_c_1__n.BLIF gnd_n_n.BLIF inst_UDS_000_INTreg.BLIF DTACK_c.BLIF \ -inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF AS_000_INT_1_sqmuxa.BLIF \ -state_machine_un8_clk_000_d2_n.BLIF inst_CLK_000_D3.BLIF SM_AMIGA_4_.BLIF \ -state_machine_un23_clk_000_d0_n.BLIF state_machine_un6_clk_000_d5_n.BLIF \ -RST_c.BLIF inst_CLK_000_D5.BLIF SM_AMIGA_7_.BLIF RESETDFFRHreg.BLIF \ -SM_AMIGA_3_.BLIF state_machine_un6_bgack_000_n.BLIF RW_c.BLIF SM_AMIGA_1_.BLIF \ -inst_DTACK_DMA.BLIF fc_c_0__n.BLIF G_102.BLIF CLK_CNT_N_0_.BLIF fc_c_1__n.BLIF \ -CLK_CNT_N_1_.BLIF G_108.BLIF AMIGA_BUS_ENABLEDFFreg.BLIF CLK_CNT_P_0_.BLIF \ -CLK_CNT_P_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF \ -state_machine_un10_bg_030_n.BLIF cpu_est_ns_0_1__n.BLIF \ -state_machine_un7_as_000_int_n.BLIF N_129_i.BLIF inst_CLK_000_D4.BLIF \ -N_131_i.BLIF state_machine_un15_clk_000_d0_n.BLIF N_221_i.BLIF \ -state_machine_lds_000_int_5_n.BLIF N_222_i.BLIF \ -state_machine_uds_000_int_5_n.BLIF N_63_0.BLIF \ -un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_62_0.BLIF inst_CLK_OUT_PRE.BLIF \ -N_132_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF DS_030_c_i.BLIF \ -N_60_i.BLIF N_59_i.BLIF N_57_i.BLIF N_56_i.BLIF N_55_i.BLIF CLK_000_D1_i.BLIF \ -N_54_i.BLIF N_51_i.BLIF N_50_i.BLIF N_125_i.BLIF N_126_i.BLIF \ -cpu_est_ns_e_0_0__n.BLIF N_85_i.BLIF N_123_i.BLIF N_124_i.BLIF \ -sm_amiga_ns_0_0__n.BLIF cpu_est_0_.BLIF N_122_i.BLIF cpu_est_1_.BLIF \ -N_227_i.BLIF cpu_est_2_.BLIF N_228_i.BLIF cpu_est_3_reg.BLIF \ -cpu_est_ns_0_2__n.BLIF N_226_i.BLIF N_44_i.BLIF N_130_i.BLIF N_225_i.BLIF \ -cpu_est_ns_1__n.BLIF N_158_i.BLIF cpu_est_ns_2__n.BLIF N_219_i.BLIF N_204.BLIF \ -N_220_i.BLIF N_205.BLIF sm_amiga_ns_0_7__n.BLIF N_206.BLIF N_215_i.BLIF \ -N_26.BLIF N_216_i.BLIF N_30.BLIF N_49.BLIF N_95_i.BLIF N_50.BLIF N_214_i.BLIF \ -N_51.BLIF sm_amiga_ns_0_5__n.BLIF N_54.BLIF N_94_i.BLIF N_55.BLIF N_133_i.BLIF \ -N_56.BLIF N_57.BLIF N_87_i.BLIF N_59.BLIF N_60.BLIF N_86_i.BLIF N_62.BLIF \ -N_63.BLIF N_83_i.BLIF N_68.BLIF N_70.BLIF N_82_i.BLIF N_72.BLIF \ -state_machine_lds_000_int_5_0_n.BLIF N_73.BLIF \ -state_machine_uds_000_int_5_0_n.BLIF N_74.BLIF N_80_i.BLIF N_76.BLIF \ -N_30_0.BLIF N_78.BLIF N_26_0.BLIF N_80.BLIF N_76_i.BLIF N_82.BLIF N_206_0.BLIF \ -N_83.BLIF N_205_0.BLIF N_85.BLIF N_72_i.BLIF N_86.BLIF N_73_i.BLIF N_87.BLIF \ -state_machine_un15_clk_000_d0_0_n.BLIF N_94.BLIF N_204_0.BLIF N_95.BLIF \ -BG_030_c_i.BLIF N_214.BLIF N_70_i.BLIF N_215.BLIF \ -state_machine_un10_bg_030_0_n.BLIF N_216.BLIF \ -state_machine_un6_bgack_000_0_n.BLIF N_219.BLIF N_220.BLIF \ -state_machine_un23_clk_000_d0_0_n.BLIF N_221.BLIF N_236_1.BLIF N_222.BLIF \ -N_236_2.BLIF N_225.BLIF N_236_3.BLIF N_226.BLIF N_236_4.BLIF N_227.BLIF \ -N_236_5.BLIF N_228.BLIF N_236_6.BLIF N_122.BLIF N_239_1.BLIF N_123.BLIF \ -N_239_2.BLIF N_124.BLIF state_machine_un8_clk_000_d2_1_n.BLIF N_125.BLIF \ -N_55_i_1.BLIF N_126.BLIF N_55_i_2.BLIF N_129.BLIF N_55_i_3.BLIF N_130.BLIF \ -N_55_i_4.BLIF N_131.BLIF N_55_i_5.BLIF N_132.BLIF cpu_est_ns_0_1_1__n.BLIF \ -N_133.BLIF cpu_est_ns_0_2_1__n.BLIF N_236.BLIF N_80_1.BLIF N_239.BLIF \ -N_80_2.BLIF RW_i.BLIF N_78_1.BLIF VMA_INT_i.BLIF N_78_2.BLIF VPA_D_i.BLIF \ -N_74_1.BLIF DTACK_i.BLIF N_74_2.BLIF CLK_000_D0_i.BLIF N_74_3.BLIF \ -sm_amiga_i_4__n.BLIF N_70_1.BLIF cpu_est_i_3__n.BLIF N_70_2.BLIF \ -sm_amiga_i_1__n.BLIF sm_amiga_ns_0_1_0__n.BLIF \ -state_machine_un6_clk_000_d5_i_n.BLIF cpu_est_ns_0_1_2__n.BLIF \ -sm_amiga_i_6__n.BLIF N_226_1.BLIF nEXP_SPACE_i.BLIF N_220_1.BLIF \ -AS_000_INT_i.BLIF N_82_1.BLIF cpu_est_i_1__n.BLIF N_73_1.BLIF \ -cpu_est_i_0__n.BLIF N_72_1.BLIF AMIGA_BUS_ENABLE_i.BLIF \ -state_machine_uds_000_int_5_0_m2_un3_n.BLIF AS_030_i.BLIF \ -state_machine_uds_000_int_5_0_m2_un1_n.BLIF cpu_est_i_2__n.BLIF \ -state_machine_uds_000_int_5_0_m2_un0_n.BLIF sm_amiga_i_2__n.BLIF \ -vpa_sync_0_un3_n.BLIF sm_amiga_i_3__n.BLIF vpa_sync_0_un1_n.BLIF \ -sm_amiga_i_5__n.BLIF vpa_sync_0_un0_n.BLIF \ -state_machine_un8_clk_000_d2_i_n.BLIF vma_int_0_un3_n.BLIF \ -sm_amiga_i_7__n.BLIF vma_int_0_un1_n.BLIF a_i_0__n.BLIF vma_int_0_un0_n.BLIF \ -size_i_1__n.BLIF bg_000_0_un3_n.BLIF dsack_i_1__n.BLIF bg_000_0_un1_n.BLIF \ -BGACK_030_INT_i.BLIF bg_000_0_un0_n.BLIF CLK_000_D2_i.BLIF \ -bgack_030_int_0_un3_n.BLIF AS_030_000_SYNC_i.BLIF bgack_030_int_0_un1_n.BLIF \ -a_i_19__n.BLIF bgack_030_int_0_un0_n.BLIF a_i_16__n.BLIF \ -as_000_int_0_un3_n.BLIF a_i_18__n.BLIF as_000_int_0_un1_n.BLIF a_i_30__n.BLIF \ -as_000_int_0_un0_n.BLIF a_i_31__n.BLIF ipl_030_0_0__un3_n.BLIF a_i_28__n.BLIF \ -ipl_030_0_0__un1_n.BLIF a_i_29__n.BLIF ipl_030_0_0__un0_n.BLIF a_i_26__n.BLIF \ -ipl_030_0_1__un3_n.BLIF a_i_27__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_24__n.BLIF \ -ipl_030_0_1__un0_n.BLIF a_i_25__n.BLIF ipl_030_0_2__un3_n.BLIF RST_i.BLIF \ -ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF cpu_estse_0_un3_n.BLIF \ -CLK_OSZI_i.BLIF cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF N_74_i.BLIF \ -cpu_estse_1_un3_n.BLIF N_78_i.BLIF cpu_estse_1_un1_n.BLIF FPU_CS_INT_i.BLIF \ -cpu_estse_1_un0_n.BLIF CLK_000_D6_i.BLIF cpu_estse_2_un3_n.BLIF AS_030_c.BLIF \ -cpu_estse_2_un1_n.BLIF cpu_estse_2_un0_n.BLIF as_030_000_sync_0_un3_n.BLIF \ -DS_030_c.BLIF as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ -dtack_sync_0_un3_n.BLIF dtack_sync_0_un1_n.BLIF size_c_0__n.BLIF \ -dtack_sync_0_un0_n.BLIF fpu_cs_int_0_un3_n.BLIF size_c_1__n.BLIF \ -fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF a_c_0__n.BLIF \ -dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF \ -amiga_bus_enable_0_un3_n.BLIF amiga_bus_enable_0_un1_n.BLIF \ -amiga_bus_enable_0_un0_n.BLIF uds_000_int_0_un3_n.BLIF \ -uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF lds_000_int_0_un3_n.BLIF \ -lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF a_15__n.BLIF a_14__n.BLIF \ -a_13__n.BLIF a_c_16__n.BLIF a_12__n.BLIF a_c_17__n.BLIF a_11__n.BLIF \ -a_c_18__n.BLIF a_10__n.BLIF a_c_19__n.BLIF a_9__n.BLIF a_c_20__n.BLIF \ -a_8__n.BLIF a_c_21__n.BLIF a_7__n.BLIF a_c_22__n.BLIF a_6__n.BLIF \ -a_c_23__n.BLIF a_5__n.BLIF a_c_24__n.BLIF a_4__n.BLIF a_c_25__n.BLIF \ -a_3__n.BLIF a_c_26__n.BLIF a_2__n.BLIF a_c_27__n.BLIF a_1__n.BLIF \ -a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF nEXP_SPACE_c.BLIF \ -BG_030_c.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF \ -DSACK_1_.PIN.BLIF DTACK.PIN.BLIF -.outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \ -CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \ -AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C \ -cpu_est_1_.AR cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D \ -cpu_est_3_reg.C cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR \ -SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.D SM_AMIGA_4_.C \ -SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D \ -SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR \ -SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_N_0_.D CLK_CNT_N_0_.C \ +.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF nEXP_SPACE.BLIF BG_030.BLIF \ +BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF \ +RW.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF \ +A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF \ +A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF SIZE_1_.BLIF \ +DSACK_1_.BLIF AS_030.BLIF AS_000.BLIF DS_030.BLIF UDS_000.BLIF LDS_000.BLIF \ +A0.BLIF DTACK.BLIF SIZE_0_.BLIF DSACK_0_.BLIF BG_030_c.BLIF \ +BG_000DFFSHreg.BLIF BGACK_000_c.BLIF inst_BGACK_030_INTreg.BLIF \ +inst_FPU_CS_INTreg.BLIF CLK_030_c.BLIF inst_VMA_INTreg.BLIF \ +inst_AS_030_000_SYNC.BLIF CLK_000_c.BLIF inst_BGACK_030_INT_D.BLIF \ +inst_DTACK_SYNC.BLIF CLK_OSZI_c.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \ +inst_CLK_000_D1.BLIF CLK_OUT_INTreg.BLIF inst_CLK_000_D2.BLIF \ +inst_CLK_000_D6.BLIF SM_AMIGA_5_.BLIF IPL_030DFFSH_0_reg.BLIF vcc_n_n.BLIF \ +gnd_n_n.BLIF IPL_030DFFSH_1_reg.BLIF inst_AS_000_INT.BLIF SM_AMIGA_6_.BLIF \ +IPL_030DFFSH_2_reg.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \ +ipl_c_0__n.BLIF inst_DSACK1_INT.BLIF inst_CLK_000_D3.BLIF ipl_c_1__n.BLIF \ +state_machine_un23_clk_000_d0_n.BLIF inst_CLK_000_D5.BLIF ipl_c_2__n.BLIF \ +SM_AMIGA_3_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_1_.BLIF dsack_c_1__n.BLIF \ +inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF DTACK_c.BLIF SIZE_DMA_0_.BLIF \ +SIZE_DMA_1_.BLIF inst_A0_DMA.BLIF G_103.BLIF CLK_CNT_N_0_.BLIF VPA_c.BLIF \ +CLK_CNT_N_1_.BLIF G_109.BLIF CLK_CNT_P_0_.BLIF RST_c.BLIF CLK_CNT_P_1_.BLIF \ +inst_CLK_000_D4.BLIF RESETDFFRHreg.BLIF SM_AMIGA_7_.BLIF \ +state_machine_un15_clk_000_d0_n.BLIF RW_c.BLIF SM_AMIGA_4_.BLIF \ +un1_AMIGA_BUS_ENABLE_0_sqmuxa_2.BLIF fc_c_0__n.BLIF inst_CLK_OUT_PRE.BLIF \ +SM_AMIGA_2_.BLIF fc_c_1__n.BLIF AMIGA_BUS_ENABLEDFFSHreg.BLIF \ +state_machine_un23_clk_000_d0_0_n.BLIF state_machine_un6_bgack_000_0_n.BLIF \ +N_214_0.BLIF BG_030_c_i.BLIF N_227_i.BLIF state_machine_un10_bg_030_0_n.BLIF \ +N_215_0.BLIF N_216_0.BLIF N_126_i.BLIF N_33_0.BLIF N_127_i.BLIF N_35_0.BLIF \ +state_machine_uds_000_int_5_0_n.BLIF N_130_i.BLIF \ +state_machine_lds_000_int_5_0_n.BLIF N_132_i.BLIF N_131_i.BLIF cpu_est_0_.BLIF \ +cpu_est_1_.BLIF N_133_i.BLIF cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_134_i.BLIF \ +N_137_i.BLIF N_138_i.BLIF sm_amiga_ns_0_5__n.BLIF cpu_est_ns_1__n.BLIF \ +N_139_i.BLIF cpu_est_ns_2__n.BLIF N_140_i.BLIF N_46_0.BLIF N_52.BLIF \ +N_142_i.BLIF N_59.BLIF N_141_i.BLIF N_62.BLIF sm_amiga_ns_0_7__n.BLIF \ +N_65.BLIF N_144_i.BLIF N_67.BLIF state_machine_ds_000_dma_5_0_n.BLIF N_72.BLIF \ +CLK_030_c_i.BLIF N_77.BLIF AS_000_c_i.BLIF N_88.BLIF N_59_i.BLIF N_217.BLIF \ +N_61_0.BLIF N_219.BLIF N_62_i.BLIF N_221.BLIF CLK_000_D1_i.BLIF N_224.BLIF \ +N_65_i.BLIF N_225.BLIF N_66_i.BLIF N_226.BLIF N_67_i.BLIF N_128.BLIF \ +N_175_i.BLIF N_130.BLIF un1_as_000_dma5_i_0__n.BLIF N_132.BLIF \ +state_machine_un6_clk_000_d5_i_n.BLIF N_135.BLIF N_71_i.BLIF N_136.BLIF \ +DS_030_c_i.BLIF N_138.BLIF N_73_i.BLIF N_143.BLIF N_156_i.BLIF N_145.BLIF \ +un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i.BLIF N_146.BLIF N_75_0.BLIF N_147.BLIF \ +N_176_i.BLIF N_148.BLIF N_52_0.BLIF N_151.BLIF N_173_i.BLIF N_153.BLIF \ +N_226_i.BLIF N_154.BLIF N_77_0.BLIF N_155.BLIF N_72_i.BLIF N_173.BLIF \ +N_147_i.BLIF cpu_est_ns_0_0_x2_1_.BLIF N_148_i.BLIF \ +AMIGA_BUS_DATA_DIR_m1_0_x2.BLIF cpu_est_ns_e_0_0__n.BLIF N_228_1.BLIF \ +N_146_i.BLIF N_237.BLIF sm_amiga_ns_0_0__n.BLIF N_247.BLIF N_88_i.BLIF \ +N_227.BLIF N_145_i.BLIF N_228.BLIF cpu_est_ns_0_2__n.BLIF N_127.BLIF \ +N_143_i.BLIF N_66.BLIF N_154_i.BLIF N_175.BLIF N_161_i.BLIF N_176.BLIF \ +N_153_i.BLIF N_75.BLIF N_155_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_4.BLIF \ +cpu_est_ns_0_1__n.BLIF N_61.BLIF N_135_i.BLIF N_156.BLIF N_136_i.BLIF \ +N_73.BLIF N_57.BLIF N_225_i.BLIF N_71.BLIF \ +un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0.BLIF state_machine_un6_clk_000_d5_n.BLIF \ +N_219_i.BLIF un1_as_000_dma5_0__n.BLIF N_221_i.BLIF N_223.BLIF \ +state_machine_un15_clk_000_d0_0_n.BLIF state_machine_ds_000_dma_5_n.BLIF \ +N_144.BLIF N_66_i_1.BLIF N_141.BLIF N_66_i_2.BLIF N_142.BLIF N_66_i_3.BLIF \ +N_139.BLIF N_66_i_4.BLIF N_140.BLIF N_66_i_5.BLIF N_137.BLIF N_237_1.BLIF \ +N_134.BLIF N_237_2.BLIF N_133.BLIF N_247_1.BLIF N_131.BLIF N_247_2.BLIF \ +state_machine_lds_000_int_5_n.BLIF N_247_3.BLIF \ +state_machine_uds_000_int_5_n.BLIF N_247_4.BLIF N_35.BLIF N_247_5.BLIF \ +N_33.BLIF N_247_6.BLIF N_126.BLIF N_52_0_1.BLIF N_216.BLIF N_52_0_2.BLIF \ +N_215.BLIF N_224_1.BLIF state_machine_un10_bg_030_n.BLIF N_224_2.BLIF \ +N_214.BLIF N_227_1.BLIF state_machine_un6_bgack_000_n.BLIF N_227_2.BLIF \ +state_machine_un8_clk_000_d2_n.BLIF N_228_1_0.BLIF SIZE_DMA_1_sqmuxa.BLIF \ +N_127_1.BLIF SIZE_DMA_0_sqmuxa.BLIF N_127_2.BLIF AS_000_INT_1_sqmuxa.BLIF \ +N_151_1.BLIF N_249.BLIF SIZE_DMA_1_sqmuxa_1.BLIF CLK_000_D6_i.BLIF \ +state_machine_un8_clk_000_d2_1_n.BLIF N_228_i.BLIF sm_amiga_ns_0_1_0__n.BLIF \ +sm_amiga_i_5__n.BLIF cpu_est_ns_0_1_1__n.BLIF N_224_i.BLIF N_138_1.BLIF \ +N_223_i.BLIF N_130_1.BLIF SIZE_DMA_0_sqmuxa_i.BLIF N_128_1.BLIF \ +SIZE_DMA_1_sqmuxa_i.BLIF N_221_1.BLIF a_i_18__n.BLIF N_219_1.BLIF \ +a_i_16__n.BLIF vpa_sync_0_un3_n.BLIF a_i_19__n.BLIF vpa_sync_0_un1_n.BLIF \ +AS_030_000_SYNC_i.BLIF vpa_sync_0_un0_n.BLIF CLK_000_D2_i.BLIF \ +as_000_int_0_un3_n.BLIF BGACK_030_INT_i.BLIF as_000_int_0_un1_n.BLIF \ +nEXP_SPACE_i.BLIF as_000_int_0_un0_n.BLIF AS_030_i.BLIF \ +as_000_dma_0_un3_n.BLIF BGACK_030_INT_D_i.BLIF as_000_dma_0_un1_n.BLIF \ +sm_amiga_i_7__n.BLIF as_000_dma_0_un0_n.BLIF \ +state_machine_un8_clk_000_d2_i_n.BLIF bg_000_0_un3_n.BLIF sm_amiga_i_6__n.BLIF \ +bg_000_0_un1_n.BLIF sm_amiga_i_4__n.BLIF bg_000_0_un0_n.BLIF CLK_000_D0_i.BLIF \ +a0_dma_0_un3_n.BLIF RW_i.BLIF a0_dma_0_un1_n.BLIF UDS_000_i.BLIF \ +a0_dma_0_un0_n.BLIF LDS_000_i.BLIF dtack_sync_0_un3_n.BLIF DTACK_i.BLIF \ +dtack_sync_0_un1_n.BLIF VMA_INT_i.BLIF dtack_sync_0_un0_n.BLIF VPA_i.BLIF \ +lds_000_int_0_un3_n.BLIF cpu_est_i_0__n.BLIF lds_000_int_0_un1_n.BLIF \ +sm_amiga_i_3__n.BLIF lds_000_int_0_un0_n.BLIF cpu_est_i_3__n.BLIF \ +uds_000_int_0_un3_n.BLIF cpu_est_i_1__n.BLIF uds_000_int_0_un1_n.BLIF \ +A0_i.BLIF uds_000_int_0_un0_n.BLIF size_i_1__n.BLIF fpu_cs_int_0_un3_n.BLIF \ +a_i_30__n.BLIF fpu_cs_int_0_un1_n.BLIF a_i_31__n.BLIF fpu_cs_int_0_un0_n.BLIF \ +a_i_28__n.BLIF ds_000_dma_0_un3_n.BLIF a_i_29__n.BLIF ds_000_dma_0_un1_n.BLIF \ +a_i_26__n.BLIF ds_000_dma_0_un0_n.BLIF a_i_27__n.BLIF \ +as_030_000_sync_0_un3_n.BLIF a_i_24__n.BLIF as_030_000_sync_0_un1_n.BLIF \ +a_i_25__n.BLIF as_030_000_sync_0_un0_n.BLIF RST_i.BLIF \ +size_dma_0_1__un3_n.BLIF size_dma_0_1__un1_n.BLIF CLK_OSZI_i.BLIF \ +size_dma_0_1__un0_n.BLIF size_dma_0_0__un3_n.BLIF FPU_CS_INT_i.BLIF \ +size_dma_0_0__un1_n.BLIF AS_030_c.BLIF size_dma_0_0__un0_n.BLIF \ +bgack_030_int_0_un3_n.BLIF AS_000_c.BLIF bgack_030_int_0_un1_n.BLIF \ +bgack_030_int_0_un0_n.BLIF DS_030_c.BLIF dsack1_int_0_un3_n.BLIF \ +dsack1_int_0_un1_n.BLIF UDS_000_c.BLIF dsack1_int_0_un0_n.BLIF \ +state_machine_uds_000_int_5_0_m2_un3_n.BLIF LDS_000_c.BLIF \ +state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ +state_machine_uds_000_int_5_0_m2_un0_n.BLIF size_c_0__n.BLIF \ +cpu_est_ns_0_0_m2_2__un3_n.BLIF cpu_est_ns_0_0_m2_2__un1_n.BLIF \ +size_c_1__n.BLIF cpu_est_ns_0_0_m2_2__un0_n.BLIF amiga_bus_enable_0_un3_n.BLIF \ +a_c_16__n.BLIF amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF \ +a_c_17__n.BLIF vma_int_0_un3_n.BLIF vma_int_0_un1_n.BLIF a_c_18__n.BLIF \ +vma_int_0_un0_n.BLIF ipl_030_0_0__un3_n.BLIF a_c_19__n.BLIF \ +ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF a_c_20__n.BLIF \ +ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF a_c_21__n.BLIF \ +ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF a_c_22__n.BLIF \ +ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF a_c_23__n.BLIF \ +cpu_estse_0_un3_n.BLIF cpu_estse_0_un1_n.BLIF a_c_24__n.BLIF \ +cpu_estse_0_un0_n.BLIF cpu_estse_1_un3_n.BLIF a_c_25__n.BLIF \ +cpu_estse_1_un1_n.BLIF cpu_estse_1_un0_n.BLIF a_c_26__n.BLIF \ +cpu_estse_2_un3_n.BLIF cpu_estse_2_un1_n.BLIF a_c_27__n.BLIF \ +cpu_estse_2_un0_n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF \ +a_c_31__n.BLIF A0_c.BLIF nEXP_SPACE_c.BLIF AS_030.PIN.BLIF AS_000.PIN.BLIF \ +DS_030.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF \ +SIZE_1_.PIN.BLIF A0.PIN.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF +.outputs IPL_030_2_ BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \ +AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \ +CIIN IPL_030_1_ IPL_030_0_ cpu_est_1_.D cpu_est_1_.C cpu_est_1_.AR \ +cpu_est_2_.D cpu_est_2_.C cpu_est_2_.AR cpu_est_3_reg.D cpu_est_3_reg.C \ +cpu_est_3_reg.AR cpu_est_0_.D cpu_est_0_.C cpu_est_0_.AR SM_AMIGA_4_.D \ +SM_AMIGA_4_.C SM_AMIGA_4_.AR SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_3_.AR \ +SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C \ +SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR CLK_CNT_P_1_.D \ +CLK_CNT_P_1_.C CLK_CNT_P_1_.AR SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_0_.AP \ +SIZE_DMA_1_.D SIZE_DMA_1_.C SIZE_DMA_1_.AP IPL_030DFFSH_0_reg.D \ +IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP IPL_030DFFSH_1_reg.D \ +IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP IPL_030DFFSH_2_reg.D \ +IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D SM_AMIGA_7_.C \ +SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.D \ +SM_AMIGA_5_.C SM_AMIGA_5_.AR inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP \ +inst_DSACK1_INT.D inst_DSACK1_INT.C inst_DSACK1_INT.AP inst_VMA_INTreg.D \ +inst_VMA_INTreg.C inst_VMA_INTreg.AP inst_BGACK_030_INTreg.D \ +inst_BGACK_030_INTreg.C inst_BGACK_030_INTreg.AP CLK_CNT_N_0_.D CLK_CNT_N_0_.C \ CLK_CNT_N_0_.AR CLK_CNT_N_1_.D CLK_CNT_N_1_.C CLK_CNT_N_1_.AP CLK_CNT_P_0_.D \ -CLK_CNT_P_0_.C CLK_CNT_P_0_.AR CLK_CNT_P_1_.D CLK_CNT_P_1_.C CLK_CNT_P_1_.AR \ -IPL_030DFFSH_0_reg.D IPL_030DFFSH_0_reg.C IPL_030DFFSH_0_reg.AP \ -IPL_030DFFSH_1_reg.D IPL_030DFFSH_1_reg.C IPL_030DFFSH_1_reg.AP \ -IPL_030DFFSH_2_reg.D IPL_030DFFSH_2_reg.C IPL_030DFFSH_2_reg.AP SM_AMIGA_7_.D \ -SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_6_.AR \ -inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP \ -inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP \ -inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP inst_VMA_INTreg.D \ -inst_VMA_INTreg.C inst_VMA_INTreg.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ -BG_000DFFSHreg.AP inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C \ -inst_BGACK_030_INTreg.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C \ -inst_AS_000_INTreg.AP inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \ -inst_CLK_OUT_PRE.AR CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_INTreg.AR \ -inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP \ -inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D \ -inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP DSACK_INT_1_.D DSACK_INT_1_.C \ -DSACK_INT_1_.AP AMIGA_BUS_ENABLEDFFreg.D AMIGA_BUS_ENABLEDFFreg.C \ -inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_CLK_000_D5.D \ -inst_CLK_000_D5.C inst_CLK_000_D5.AP inst_CLK_000_D6.D inst_CLK_000_D6.C \ -inst_CLK_000_D6.AP inst_CLK_000_D4.D inst_CLK_000_D4.C inst_CLK_000_D4.AP \ -inst_CLK_000_D2.D inst_CLK_000_D2.C inst_CLK_000_D2.AP inst_CLK_000_D3.D \ -inst_CLK_000_D3.C inst_CLK_000_D3.AP inst_VPA_D.D inst_VPA_D.C inst_VPA_D.AP \ +CLK_CNT_P_0_.C CLK_CNT_P_0_.AR inst_LDS_000_INT.D inst_LDS_000_INT.C \ +inst_LDS_000_INT.AP inst_DTACK_SYNC.D inst_DTACK_SYNC.C inst_DTACK_SYNC.AP \ +inst_A0_DMA.D inst_A0_DMA.C inst_A0_DMA.AP BG_000DFFSHreg.D BG_000DFFSHreg.C \ +BG_000DFFSHreg.AP inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_000_DMA.AP \ +AMIGA_BUS_ENABLEDFFSHreg.D AMIGA_BUS_ENABLEDFFSHreg.C \ +AMIGA_BUS_ENABLEDFFSHreg.AP inst_AS_000_INT.D inst_AS_000_INT.C \ +inst_AS_000_INT.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \ +inst_AS_030_000_SYNC.AP inst_DS_000_DMA.D inst_DS_000_DMA.C inst_DS_000_DMA.AP \ +inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP \ +inst_UDS_000_INT.D inst_UDS_000_INT.C inst_UDS_000_INT.AP CLK_OUT_INTreg.D \ +CLK_OUT_INTreg.C CLK_OUT_INTreg.AR inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C \ +inst_CLK_OUT_PRE.AR inst_CLK_000_D5.D inst_CLK_000_D5.C inst_CLK_000_D5.AP \ +inst_CLK_000_D6.D inst_CLK_000_D6.C inst_CLK_000_D6.AP inst_CLK_000_D4.D \ +inst_CLK_000_D4.C inst_CLK_000_D4.AP inst_CLK_000_D2.D inst_CLK_000_D2.C \ +inst_CLK_000_D2.AP inst_CLK_000_D3.D inst_CLK_000_D3.C inst_CLK_000_D3.AP \ +inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_BGACK_030_INT_D.AP \ inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D0.AP RESETDFFRHreg.D \ RESETDFFRHreg.C RESETDFFRHreg.AR inst_CLK_000_D1.D inst_CLK_000_D1.C \ -inst_CLK_000_D1.AP DSACK_1_ DTACK DSACK_0_ CLK_000_c CLK_OSZI_c ipl_c_0__n \ -ipl_c_1__n ipl_c_2__n vcc_n_n dsack_c_1__n gnd_n_n DTACK_c AS_000_INT_1_sqmuxa \ -state_machine_un8_clk_000_d2_n state_machine_un23_clk_000_d0_n \ -state_machine_un6_clk_000_d5_n RST_c state_machine_un6_bgack_000_n RW_c \ -fc_c_0__n fc_c_1__n state_machine_un10_bg_030_n cpu_est_ns_0_1__n \ -state_machine_un7_as_000_int_n N_129_i N_131_i state_machine_un15_clk_000_d0_n \ -N_221_i state_machine_lds_000_int_5_n N_222_i state_machine_uds_000_int_5_n \ -N_63_0 un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 N_62_0 N_132_i \ -un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 DS_030_c_i N_60_i N_59_i N_57_i N_56_i \ -N_55_i CLK_000_D1_i N_54_i N_51_i N_50_i N_125_i N_126_i cpu_est_ns_e_0_0__n \ -N_85_i N_123_i N_124_i sm_amiga_ns_0_0__n N_122_i N_227_i N_228_i \ -cpu_est_ns_0_2__n N_226_i N_44_i N_130_i N_225_i cpu_est_ns_1__n N_158_i \ -cpu_est_ns_2__n N_219_i N_204 N_220_i N_205 sm_amiga_ns_0_7__n N_206 N_215_i \ -N_26 N_216_i N_30 N_49 N_95_i N_50 N_214_i N_51 sm_amiga_ns_0_5__n N_54 N_94_i \ -N_55 N_133_i N_56 N_57 N_87_i N_59 N_60 N_86_i N_62 N_63 N_83_i N_68 N_70 \ -N_82_i N_72 state_machine_lds_000_int_5_0_n N_73 \ -state_machine_uds_000_int_5_0_n N_74 N_80_i N_76 N_30_0 N_78 N_26_0 N_80 \ -N_76_i N_82 N_206_0 N_83 N_205_0 N_85 N_72_i N_86 N_73_i N_87 \ -state_machine_un15_clk_000_d0_0_n N_94 N_204_0 N_95 BG_030_c_i N_214 N_70_i \ -N_215 state_machine_un10_bg_030_0_n N_216 state_machine_un6_bgack_000_0_n \ -N_219 N_220 state_machine_un23_clk_000_d0_0_n N_221 N_236_1 N_222 N_236_2 \ -N_225 N_236_3 N_226 N_236_4 N_227 N_236_5 N_228 N_236_6 N_122 N_239_1 N_123 \ -N_239_2 N_124 state_machine_un8_clk_000_d2_1_n N_125 N_55_i_1 N_126 N_55_i_2 \ -N_129 N_55_i_3 N_130 N_55_i_4 N_131 N_55_i_5 N_132 cpu_est_ns_0_1_1__n N_133 \ -cpu_est_ns_0_2_1__n N_236 N_80_1 N_239 N_80_2 RW_i N_78_1 VMA_INT_i N_78_2 \ -VPA_D_i N_74_1 DTACK_i N_74_2 CLK_000_D0_i N_74_3 sm_amiga_i_4__n N_70_1 \ -cpu_est_i_3__n N_70_2 sm_amiga_i_1__n sm_amiga_ns_0_1_0__n \ -state_machine_un6_clk_000_d5_i_n cpu_est_ns_0_1_2__n sm_amiga_i_6__n N_226_1 \ -nEXP_SPACE_i N_220_1 AS_000_INT_i N_82_1 cpu_est_i_1__n N_73_1 cpu_est_i_0__n \ -N_72_1 AMIGA_BUS_ENABLE_i state_machine_uds_000_int_5_0_m2_un3_n AS_030_i \ -state_machine_uds_000_int_5_0_m2_un1_n cpu_est_i_2__n \ -state_machine_uds_000_int_5_0_m2_un0_n sm_amiga_i_2__n vpa_sync_0_un3_n \ -sm_amiga_i_3__n vpa_sync_0_un1_n sm_amiga_i_5__n vpa_sync_0_un0_n \ -state_machine_un8_clk_000_d2_i_n vma_int_0_un3_n sm_amiga_i_7__n \ -vma_int_0_un1_n a_i_0__n vma_int_0_un0_n size_i_1__n bg_000_0_un3_n \ -dsack_i_1__n bg_000_0_un1_n BGACK_030_INT_i bg_000_0_un0_n CLK_000_D2_i \ -bgack_030_int_0_un3_n AS_030_000_SYNC_i bgack_030_int_0_un1_n a_i_19__n \ -bgack_030_int_0_un0_n a_i_16__n as_000_int_0_un3_n a_i_18__n \ -as_000_int_0_un1_n a_i_30__n as_000_int_0_un0_n a_i_31__n ipl_030_0_0__un3_n \ -a_i_28__n ipl_030_0_0__un1_n a_i_29__n ipl_030_0_0__un0_n a_i_26__n \ -ipl_030_0_1__un3_n a_i_27__n ipl_030_0_1__un1_n a_i_24__n ipl_030_0_1__un0_n \ -a_i_25__n ipl_030_0_2__un3_n RST_i ipl_030_0_2__un1_n ipl_030_0_2__un0_n \ -cpu_estse_0_un3_n CLK_OSZI_i cpu_estse_0_un1_n cpu_estse_0_un0_n N_74_i \ -cpu_estse_1_un3_n N_78_i cpu_estse_1_un1_n FPU_CS_INT_i cpu_estse_1_un0_n \ -CLK_000_D6_i cpu_estse_2_un3_n AS_030_c cpu_estse_2_un1_n cpu_estse_2_un0_n \ -as_030_000_sync_0_un3_n DS_030_c as_030_000_sync_0_un1_n \ -as_030_000_sync_0_un0_n dtack_sync_0_un3_n dtack_sync_0_un1_n size_c_0__n \ -dtack_sync_0_un0_n fpu_cs_int_0_un3_n size_c_1__n fpu_cs_int_0_un1_n \ -fpu_cs_int_0_un0_n a_c_0__n dsack_int_0_1__un3_n dsack_int_0_1__un1_n \ -dsack_int_0_1__un0_n amiga_bus_enable_0_un3_n amiga_bus_enable_0_un1_n \ -amiga_bus_enable_0_un0_n uds_000_int_0_un3_n uds_000_int_0_un1_n \ -uds_000_int_0_un0_n lds_000_int_0_un3_n lds_000_int_0_un1_n \ -lds_000_int_0_un0_n a_15__n a_14__n a_13__n a_c_16__n a_12__n a_c_17__n \ -a_11__n a_c_18__n a_10__n a_c_19__n a_9__n a_c_20__n a_8__n a_c_21__n a_7__n \ -a_c_22__n a_6__n a_c_23__n a_5__n a_c_24__n a_4__n a_c_25__n a_3__n a_c_26__n \ -a_2__n a_c_27__n a_1__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c \ -BG_030_c BGACK_000_c CLK_030_c DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE \ -LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE G_102 G_108 +inst_CLK_000_D1.AP SIZE_1_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 \ +DTACK SIZE_0_ DSACK_0_ BG_030_c BGACK_000_c CLK_030_c CLK_000_c CLK_OSZI_c \ +vcc_n_n gnd_n_n ipl_c_0__n ipl_c_1__n state_machine_un23_clk_000_d0_n \ +ipl_c_2__n dsack_c_1__n DTACK_c VPA_c RST_c state_machine_un15_clk_000_d0_n \ +RW_c un1_AMIGA_BUS_ENABLE_0_sqmuxa_2 fc_c_0__n fc_c_1__n \ +state_machine_un23_clk_000_d0_0_n state_machine_un6_bgack_000_0_n N_214_0 \ +BG_030_c_i N_227_i state_machine_un10_bg_030_0_n N_215_0 N_216_0 N_126_i \ +N_33_0 N_127_i N_35_0 state_machine_uds_000_int_5_0_n N_130_i \ +state_machine_lds_000_int_5_0_n N_132_i N_131_i N_133_i N_134_i N_137_i \ +N_138_i sm_amiga_ns_0_5__n cpu_est_ns_1__n N_139_i cpu_est_ns_2__n N_140_i \ +N_46_0 N_52 N_142_i N_59 N_141_i N_62 sm_amiga_ns_0_7__n N_65 N_144_i N_67 \ +state_machine_ds_000_dma_5_0_n N_72 CLK_030_c_i N_77 AS_000_c_i N_88 N_59_i \ +N_217 N_61_0 N_219 N_62_i N_221 CLK_000_D1_i N_224 N_65_i N_225 N_66_i N_226 \ +N_67_i N_128 N_175_i N_130 un1_as_000_dma5_i_0__n N_132 \ +state_machine_un6_clk_000_d5_i_n N_135 N_71_i N_136 DS_030_c_i N_138 N_73_i \ +N_143 N_156_i N_145 un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i N_146 N_75_0 N_147 \ +N_176_i N_148 N_52_0 N_151 N_173_i N_153 N_226_i N_154 N_77_0 N_155 N_72_i \ +N_173 N_147_i N_148_i cpu_est_ns_e_0_0__n N_228_1 N_146_i N_237 \ +sm_amiga_ns_0_0__n N_247 N_88_i N_227 N_145_i N_228 cpu_est_ns_0_2__n N_127 \ +N_143_i N_66 N_154_i N_175 N_161_i N_176 N_153_i N_75 N_155_i \ +un1_AMIGA_BUS_ENABLE_1_sqmuxa_4 cpu_est_ns_0_1__n N_61 N_135_i N_156 N_136_i \ +N_73 N_57 N_225_i N_71 un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0 \ +state_machine_un6_clk_000_d5_n N_219_i un1_as_000_dma5_0__n N_221_i N_223 \ +state_machine_un15_clk_000_d0_0_n state_machine_ds_000_dma_5_n N_144 N_66_i_1 \ +N_141 N_66_i_2 N_142 N_66_i_3 N_139 N_66_i_4 N_140 N_66_i_5 N_137 N_237_1 \ +N_134 N_237_2 N_133 N_247_1 N_131 N_247_2 state_machine_lds_000_int_5_n \ +N_247_3 state_machine_uds_000_int_5_n N_247_4 N_35 N_247_5 N_33 N_247_6 N_126 \ +N_52_0_1 N_216 N_52_0_2 N_215 N_224_1 state_machine_un10_bg_030_n N_224_2 \ +N_214 N_227_1 state_machine_un6_bgack_000_n N_227_2 \ +state_machine_un8_clk_000_d2_n N_228_1_0 SIZE_DMA_1_sqmuxa N_127_1 \ +SIZE_DMA_0_sqmuxa N_127_2 AS_000_INT_1_sqmuxa N_151_1 N_249 \ +SIZE_DMA_1_sqmuxa_1 CLK_000_D6_i state_machine_un8_clk_000_d2_1_n N_228_i \ +sm_amiga_ns_0_1_0__n sm_amiga_i_5__n cpu_est_ns_0_1_1__n N_224_i N_138_1 \ +N_223_i N_130_1 SIZE_DMA_0_sqmuxa_i N_128_1 SIZE_DMA_1_sqmuxa_i N_221_1 \ +a_i_18__n N_219_1 a_i_16__n vpa_sync_0_un3_n a_i_19__n vpa_sync_0_un1_n \ +AS_030_000_SYNC_i vpa_sync_0_un0_n CLK_000_D2_i as_000_int_0_un3_n \ +BGACK_030_INT_i as_000_int_0_un1_n nEXP_SPACE_i as_000_int_0_un0_n AS_030_i \ +as_000_dma_0_un3_n BGACK_030_INT_D_i as_000_dma_0_un1_n sm_amiga_i_7__n \ +as_000_dma_0_un0_n state_machine_un8_clk_000_d2_i_n bg_000_0_un3_n \ +sm_amiga_i_6__n bg_000_0_un1_n sm_amiga_i_4__n bg_000_0_un0_n CLK_000_D0_i \ +a0_dma_0_un3_n RW_i a0_dma_0_un1_n UDS_000_i a0_dma_0_un0_n LDS_000_i \ +dtack_sync_0_un3_n DTACK_i dtack_sync_0_un1_n VMA_INT_i dtack_sync_0_un0_n \ +VPA_i lds_000_int_0_un3_n cpu_est_i_0__n lds_000_int_0_un1_n sm_amiga_i_3__n \ +lds_000_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n cpu_est_i_1__n \ +uds_000_int_0_un1_n A0_i uds_000_int_0_un0_n size_i_1__n fpu_cs_int_0_un3_n \ +a_i_30__n fpu_cs_int_0_un1_n a_i_31__n fpu_cs_int_0_un0_n a_i_28__n \ +ds_000_dma_0_un3_n a_i_29__n ds_000_dma_0_un1_n a_i_26__n ds_000_dma_0_un0_n \ +a_i_27__n as_030_000_sync_0_un3_n a_i_24__n as_030_000_sync_0_un1_n a_i_25__n \ +as_030_000_sync_0_un0_n RST_i size_dma_0_1__un3_n size_dma_0_1__un1_n \ +CLK_OSZI_i size_dma_0_1__un0_n size_dma_0_0__un3_n FPU_CS_INT_i \ +size_dma_0_0__un1_n AS_030_c size_dma_0_0__un0_n bgack_030_int_0_un3_n \ +AS_000_c bgack_030_int_0_un1_n bgack_030_int_0_un0_n DS_030_c \ +dsack1_int_0_un3_n dsack1_int_0_un1_n UDS_000_c dsack1_int_0_un0_n \ +state_machine_uds_000_int_5_0_m2_un3_n LDS_000_c \ +state_machine_uds_000_int_5_0_m2_un1_n state_machine_uds_000_int_5_0_m2_un0_n \ +size_c_0__n cpu_est_ns_0_0_m2_2__un3_n cpu_est_ns_0_0_m2_2__un1_n size_c_1__n \ +cpu_est_ns_0_0_m2_2__un0_n amiga_bus_enable_0_un3_n a_c_16__n \ +amiga_bus_enable_0_un1_n amiga_bus_enable_0_un0_n a_c_17__n vma_int_0_un3_n \ +vma_int_0_un1_n a_c_18__n vma_int_0_un0_n ipl_030_0_0__un3_n a_c_19__n \ +ipl_030_0_0__un1_n ipl_030_0_0__un0_n a_c_20__n ipl_030_0_1__un3_n \ +ipl_030_0_1__un1_n a_c_21__n ipl_030_0_1__un0_n ipl_030_0_2__un3_n a_c_22__n \ +ipl_030_0_2__un1_n ipl_030_0_2__un0_n a_c_23__n cpu_estse_0_un3_n \ +cpu_estse_0_un1_n a_c_24__n cpu_estse_0_un0_n cpu_estse_1_un3_n a_c_25__n \ +cpu_estse_1_un1_n cpu_estse_1_un0_n a_c_26__n cpu_estse_2_un3_n \ +cpu_estse_2_un1_n a_c_27__n cpu_estse_2_un0_n a_c_28__n a_c_29__n a_c_30__n \ +a_c_31__n A0_c nEXP_SPACE_c AS_030.OE AS_000.OE DS_030.OE UDS_000.OE \ +LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE DSACK_1_.OE DTACK.OE BERR.OE \ +DSACK_0_.OE AVEC_EXP.OE CIIN.OE G_103 G_109 cpu_est_ns_0_0_x2_1_ \ +AMIGA_BUS_DATA_DIR_m1_0_x2 .names cpu_estse_0_un1_n.BLIF cpu_estse_0_un0_n.BLIF cpu_est_1_.D 1- 1 -1 1 @@ -277,22 +312,22 @@ LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE G_102 G_108 -1 1 .names cpu_est_ns_e_0_0__n.BLIF cpu_est_0_.D 0 1 -.names inst_CLK_000_D0.BLIF N_86_i.BLIF SM_AMIGA_5_.D +.names CLK_000_D0_i.BLIF N_134_i.BLIF SM_AMIGA_4_.D 11 1 -.names CLK_000_D0_i.BLIF N_87_i.BLIF SM_AMIGA_4_.D -11 1 -.names N_94_i.BLIF N_133_i.BLIF SM_AMIGA_3_.D +.names N_135_i.BLIF N_136_i.BLIF SM_AMIGA_3_.D 11 1 .names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D 0 1 -.names N_215_i.BLIF N_216_i.BLIF SM_AMIGA_1_.D -11 1 +.names N_46_0.BLIF SM_AMIGA_1_.D +0 1 .names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D 0 1 -.names G_102.BLIF CLK_CNT_N_0_.D -0 1 -.names G_108.BLIF CLK_CNT_P_0_.D -0 1 +.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D +1- 1 +-1 1 +.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D +1- 1 +-1 1 .names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D 1- 1 -1 1 @@ -304,610 +339,693 @@ LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE G_102 G_108 -1 1 .names sm_amiga_ns_0_0__n.BLIF SM_AMIGA_7_.D 0 1 -.names N_83_i.BLIF N_85_i.BLIF SM_AMIGA_6_.D +.names N_131_i.BLIF N_132_i.BLIF SM_AMIGA_6_.D +11 1 +.names inst_CLK_000_D0.BLIF N_133_i.BLIF SM_AMIGA_5_.D 11 1 -.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D -1- 1 --1 1 -.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D -1- 1 --1 1 .names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D 1- 1 -1 1 -.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D +.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF inst_DSACK1_INT.D 1- 1 -1 1 -.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D 1- 1 -1 1 .names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF \ inst_BGACK_030_INTreg.D 1- 1 -1 1 -.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D -1- 1 --1 1 -.names G_108.BLIF G_102.BLIF inst_CLK_OUT_PRE.D -11 1 -.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ -inst_AS_030_000_SYNC.D +.names G_103.BLIF CLK_CNT_N_0_.D +0 1 +.names G_109.BLIF CLK_CNT_P_0_.D +0 1 +.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INT.D 1- 1 -1 1 .names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D 1- 1 -1 1 -.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D +.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF inst_A0_DMA.D 1- 1 -1 1 -.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D +.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D +1- 1 +-1 1 +.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF inst_AS_000_DMA.D 1- 1 -1 1 .names amiga_bus_enable_0_un1_n.BLIF amiga_bus_enable_0_un0_n.BLIF \ -AMIGA_BUS_ENABLEDFFreg.D +AMIGA_BUS_ENABLEDFFSHreg.D 1- 1 -1 1 -.names state_machine_un7_as_000_int_n.BLIF inst_DTACK_DMA.D -0 1 +.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INT.D +1- 1 +-1 1 +.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF \ +inst_AS_030_000_SYNC.D +1- 1 +-1 1 +.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF inst_DS_000_DMA.D +1- 1 +-1 1 +.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D +1- 1 +-1 1 +.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INT.D +1- 1 +-1 1 +.names G_109.BLIF G_103.BLIF inst_CLK_OUT_PRE.D +11 1 .names vcc_n_n 1 .names gnd_n_n -.names AS_030_i.BLIF sm_amiga_i_5__n.BLIF AS_000_INT_1_sqmuxa +.names state_machine_un23_clk_000_d0_0_n.BLIF state_machine_un23_clk_000_d0_n +0 1 +.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n +0 1 +.names un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_0_sqmuxa_2 +0 1 +.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ +state_machine_un23_clk_000_d0_0_n +11 1 +.names BGACK_000_c.BLIF N_65.BLIF state_machine_un6_bgack_000_0_n +11 1 +.names AS_030_i.BLIF N_224_i.BLIF N_214_0 +11 1 +.names BG_030_c.BLIF BG_030_c_i +0 1 +.names N_227.BLIF N_227_i +0 1 +.names BG_030_c_i.BLIF N_227_i.BLIF state_machine_un10_bg_030_0_n +11 1 +.names AS_030_i.BLIF N_73.BLIF N_215_0 +11 1 +.names AS_030_i.BLIF N_228_i.BLIF N_216_0 +11 1 +.names N_126.BLIF N_126_i +0 1 +.names AS_030_i.BLIF N_126_i.BLIF N_33_0 +11 1 +.names N_127.BLIF N_127_i +0 1 +.names N_127_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i.BLIF N_35_0 +11 1 +.names A0_i.BLIF N_73_i.BLIF state_machine_uds_000_int_5_0_n +11 1 +.names N_130.BLIF N_130_i +0 1 +.names N_73_i.BLIF N_130_i.BLIF state_machine_lds_000_int_5_0_n +11 1 +.names N_132.BLIF N_132_i +0 1 +.names N_131.BLIF N_131_i +0 1 +.names N_133.BLIF N_133_i +0 1 +.names N_134.BLIF N_134_i +0 1 +.names N_137.BLIF N_137_i +0 1 +.names N_138.BLIF N_138_i +0 1 +.names N_137_i.BLIF N_138_i.BLIF sm_amiga_ns_0_5__n +11 1 +.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n +0 1 +.names N_139.BLIF N_139_i +0 1 +.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n +0 1 +.names N_140.BLIF N_140_i +0 1 +.names N_139_i.BLIF N_140_i.BLIF N_46_0 +11 1 +.names N_52_0.BLIF N_52 +0 1 +.names N_142.BLIF N_142_i +0 1 +.names N_59_i.BLIF N_59 +0 1 +.names N_141.BLIF N_141_i +0 1 +.names N_62_i.BLIF N_62 +0 1 +.names N_141_i.BLIF N_142_i.BLIF sm_amiga_ns_0_7__n +11 1 +.names N_65_i.BLIF N_65 +0 1 +.names N_144.BLIF N_144_i +0 1 +.names N_67_i.BLIF N_67 +0 1 +.names N_144_i.BLIF un1_as_000_dma5_i_0__n.BLIF state_machine_ds_000_dma_5_0_n +11 1 +.names N_72_i.BLIF N_72 +0 1 +.names CLK_030_c.BLIF CLK_030_c_i +0 1 +.names N_77_0.BLIF N_77 +0 1 +.names AS_000_c.BLIF AS_000_c_i +0 1 +.names cpu_est_ns_0_0_m2_2__un1_n.BLIF cpu_est_ns_0_0_m2_2__un0_n.BLIF N_88 +1- 1 +-1 1 +.names inst_AS_000_INT.BLIF inst_CLK_000_D0.BLIF N_59_i +11 1 +.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_217 +11 1 +.names AS_030_i.BLIF N_223_i.BLIF N_61_0 +11 1 +.names N_219_1.BLIF VPA_i.BLIF N_219 +11 1 +.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_i.BLIF N_62_i +11 1 +.names N_221_1.BLIF cpu_est_2_.BLIF N_221 +11 1 +.names inst_CLK_000_D1.BLIF CLK_000_D1_i +0 1 +.names N_224_1.BLIF N_224_2.BLIF N_224 +11 1 +.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_65_i +11 1 +.names N_62.BLIF N_173.BLIF N_225 +11 1 +.names N_66_i_4.BLIF N_66_i_5.BLIF N_66_i +11 1 +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_D_i.BLIF N_226 +11 1 +.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_67_i +11 1 +.names N_128_1.BLIF UDS_000_c.BLIF N_128 +11 1 +.names N_175.BLIF N_175_i +0 1 +.names N_130_1.BLIF size_i_1__n.BLIF N_130 +11 1 +.names N_151.BLIF N_175_i.BLIF un1_as_000_dma5_i_0__n +11 1 +.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_132 +11 1 +.names state_machine_un6_clk_000_d5_n.BLIF state_machine_un6_clk_000_d5_i_n +0 1 +.names CLK_000_D0_i.BLIF N_77.BLIF N_135 +11 1 +.names CLK_000_D0_i.BLIF state_machine_un6_clk_000_d5_i_n.BLIF N_71_i +11 1 +.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_136 +11 1 +.names DS_030_c.BLIF DS_030_c_i +0 1 +.names N_138_1.BLIF state_machine_un23_clk_000_d0_n.BLIF N_138 +11 1 +.names DS_030_c_i.BLIF N_57.BLIF N_73_i +11 1 +.names N_72.BLIF cpu_est_2_.BLIF N_143 +11 1 +.names N_156.BLIF N_156_i +0 1 +.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_145 +11 1 +.names N_61_0.BLIF N_156_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i +11 1 +.names CLK_000_D0_i.BLIF N_156.BLIF N_146 +11 1 +.names CLK_000_D0_i.BLIF N_67_i.BLIF N_75_0 +11 1 +.names N_65.BLIF cpu_est_0_.BLIF N_147 +11 1 +.names N_176.BLIF N_176_i +0 1 +.names N_65_i.BLIF cpu_est_i_0__n.BLIF N_148 +11 1 +.names N_52_0_1.BLIF N_52_0_2.BLIF N_52_0 +11 1 +.names N_151_1.BLIF BGACK_030_INT_i.BLIF N_151 +11 1 +.names N_173.BLIF N_173_i +0 1 +.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_153 +11 1 +.names N_226.BLIF N_226_i +0 1 +.names N_153.BLIF cpu_est_i_3__n.BLIF N_154 +11 1 +.names SM_AMIGA_3_.BLIF state_machine_un23_clk_000_d0_0_n.BLIF N_77_0 +11 1 +.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_155 +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_72_i +11 1 +.names N_59_i.BLIF SM_AMIGA_0_.BLIF N_173 +11 1 +.names N_147.BLIF N_147_i +0 1 +.names N_148.BLIF N_148_i +0 1 +.names N_147_i.BLIF N_148_i.BLIF cpu_est_ns_e_0_0__n +11 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF N_228_1 +11 1 +.names N_146.BLIF N_146_i +0 1 +.names N_237_1.BLIF N_237_2.BLIF N_237 +11 1 +.names sm_amiga_ns_0_1_0__n.BLIF N_146_i.BLIF sm_amiga_ns_0_0__n +11 1 +.names N_247_5.BLIF N_247_6.BLIF N_247 +11 1 +.names N_88.BLIF N_88_i +0 1 +.names N_227_1.BLIF N_227_2.BLIF N_227 +11 1 +.names N_145.BLIF N_145_i +0 1 +.names N_228_1_0.BLIF VPA_c.BLIF N_228 +11 1 +.names N_88_i.BLIF N_145_i.BLIF cpu_est_ns_0_2__n +11 1 +.names N_127_1.BLIF N_127_2.BLIF N_127 +11 1 +.names N_143.BLIF N_143_i +0 1 +.names N_66_i.BLIF N_66 +0 1 +.names N_154.BLIF N_154_i +0 1 +.names LDS_000_c.BLIF UDS_000_c.BLIF N_175 +11 1 +.names N_143_i.BLIF N_154_i.BLIF N_161_i +11 1 +.names LDS_000_i.BLIF UDS_000_i.BLIF N_176 +11 1 +.names N_153.BLIF N_153_i +0 1 +.names N_75_0.BLIF N_75 +0 1 +.names N_155.BLIF N_155_i +0 1 +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_4 +0 1 +.names cpu_est_ns_0_1_1__n.BLIF N_153_i.BLIF cpu_est_ns_0_1__n +11 1 +.names N_61_0.BLIF N_61 +0 1 +.names N_135.BLIF N_135_i +0 1 +.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_156 +11 1 +.names N_136.BLIF N_136_i +0 1 +.names N_73_i.BLIF N_73 +0 1 +.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ +state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_57 +1- 1 +-1 1 +.names N_225.BLIF N_225_i +0 1 +.names N_71_i.BLIF N_71 +0 1 +.names N_225_i.BLIF N_226_i.BLIF un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0 +11 1 +.names inst_CLK_000_D5.BLIF CLK_000_D6_i.BLIF state_machine_un6_clk_000_d5_n +11 1 +.names N_219.BLIF N_219_i +0 1 +.names un1_as_000_dma5_i_0__n.BLIF un1_as_000_dma5_0__n +0 1 +.names N_221.BLIF N_221_i +0 1 +.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d5_n.BLIF N_223 +11 1 +.names N_219_i.BLIF N_221_i.BLIF state_machine_un15_clk_000_d0_0_n +11 1 +.names state_machine_ds_000_dma_5_0_n.BLIF state_machine_ds_000_dma_5_n +0 1 +.names inst_AS_000_DMA.BLIF RW_i.BLIF N_144 +11 1 +.names BGACK_000_c.BLIF a_i_19__n.BLIF N_66_i_1 +11 1 +.names N_59.BLIF SM_AMIGA_0_.BLIF N_141 +11 1 +.names a_i_16__n.BLIF a_i_18__n.BLIF N_66_i_2 +11 1 +.names N_71_i.BLIF SM_AMIGA_1_.BLIF N_142 +11 1 +.names a_c_17__n.BLIF fc_c_0__n.BLIF N_66_i_3 +11 1 +.names N_71.BLIF SM_AMIGA_1_.BLIF N_139 +11 1 +.names N_66_i_1.BLIF N_66_i_2.BLIF N_66_i_4 +11 1 +.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_140 +11 1 +.names N_66_i_3.BLIF fc_c_1__n.BLIF N_66_i_5 +11 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_137 +11 1 +.names a_c_20__n.BLIF a_c_21__n.BLIF N_237_1 +11 1 +.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_134 +11 1 +.names a_c_22__n.BLIF a_c_23__n.BLIF N_237_2 +11 1 +.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_133 +11 1 +.names a_i_24__n.BLIF a_i_25__n.BLIF N_247_1 +11 1 +.names N_75.BLIF sm_amiga_i_7__n.BLIF N_131 +11 1 +.names a_i_26__n.BLIF a_i_27__n.BLIF N_247_2 +11 1 +.names state_machine_lds_000_int_5_0_n.BLIF state_machine_lds_000_int_5_n +0 1 +.names a_i_28__n.BLIF a_i_29__n.BLIF N_247_3 +11 1 +.names state_machine_uds_000_int_5_0_n.BLIF state_machine_uds_000_int_5_n +0 1 +.names a_i_30__n.BLIF a_i_31__n.BLIF N_247_4 +11 1 +.names N_35_0.BLIF N_35 +0 1 +.names N_247_1.BLIF N_247_2.BLIF N_247_5 +11 1 +.names N_33_0.BLIF N_33 +0 1 +.names N_247_3.BLIF N_247_4.BLIF N_247_6 +11 1 +.names CLK_030_c.BLIF N_66_i.BLIF N_126 +11 1 +.names N_62.BLIF N_67.BLIF N_52_0_1 +11 1 +.names N_216_0.BLIF N_216 +0 1 +.names N_173_i.BLIF N_226_i.BLIF N_52_0_2 +11 1 +.names N_215_0.BLIF N_215 +0 1 +.names N_72_i.BLIF N_228_1.BLIF N_224_1 +11 1 +.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n +0 1 +.names VMA_INT_i.BLIF VPA_i.BLIF N_224_2 +11 1 +.names N_214_0.BLIF N_214 +0 1 +.names AS_030_c.BLIF CLK_000_c.BLIF N_227_1 +11 1 +.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n +0 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_227_2 11 1 .names state_machine_un8_clk_000_d2_1_n.BLIF CLK_000_D2_i.BLIF \ state_machine_un8_clk_000_d2_n 11 1 -.names state_machine_un23_clk_000_d0_0_n.BLIF state_machine_un23_clk_000_d0_n +.names DTACK_i.BLIF N_228_1.BLIF N_228_1_0 +11 1 +.names SIZE_DMA_1_sqmuxa_1.BLIF N_175_i.BLIF SIZE_DMA_1_sqmuxa +11 1 +.names CLK_030_c.BLIF N_66.BLIF N_127_1 +11 1 +.names N_151.BLIF N_176.BLIF SIZE_DMA_0_sqmuxa +11 1 +.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_127_2 +11 1 +.names AS_030_i.BLIF sm_amiga_i_5__n.BLIF AS_000_INT_1_sqmuxa +11 1 +.names CLK_030_c_i.BLIF AS_000_c_i.BLIF N_151_1 +11 1 +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_249 +11 1 +.names N_176_i.BLIF N_151.BLIF SIZE_DMA_1_sqmuxa_1 +11 1 +.names inst_CLK_000_D6.BLIF CLK_000_D6_i 0 1 -.names inst_CLK_000_D5.BLIF CLK_000_D6_i.BLIF state_machine_un6_clk_000_d5_n -11 1 -.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n -0 1 -.names state_machine_un10_bg_030_0_n.BLIF state_machine_un10_bg_030_n -0 1 -.names cpu_est_ns_0_1_1__n.BLIF cpu_est_ns_0_2_1__n.BLIF cpu_est_ns_0_1__n -11 1 -.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un7_as_000_int_n -11 1 -.names N_129.BLIF N_129_i -0 1 -.names N_131.BLIF N_131_i -0 1 -.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n -0 1 -.names N_221.BLIF N_221_i -0 1 -.names state_machine_lds_000_int_5_0_n.BLIF state_machine_lds_000_int_5_n -0 1 -.names N_222.BLIF N_222_i -0 1 -.names state_machine_uds_000_int_5_0_n.BLIF state_machine_uds_000_int_5_n -0 1 -.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF N_63_0 -11 1 -.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 -0 1 -.names CLK_000_D0_i.BLIF N_56_i.BLIF N_62_0 -11 1 -.names N_132.BLIF N_132_i -0 1 -.names N_51_i.BLIF N_132_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 -11 1 -.names DS_030_c.BLIF DS_030_c_i -0 1 -.names DS_030_c_i.BLIF N_49.BLIF N_60_i -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_1__n.BLIF N_59_i -11 1 -.names SM_AMIGA_1_.BLIF state_machine_un6_clk_000_d5_n.BLIF N_57_i -11 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_c.BLIF N_56_i -11 1 -.names N_55_i_4.BLIF N_55_i_5.BLIF N_55_i -11 1 -.names inst_CLK_000_D1.BLIF CLK_000_D1_i -0 1 -.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF N_54_i -11 1 -.names AS_030_i.BLIF N_57.BLIF N_51_i -11 1 -.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF N_50_i -11 1 -.names N_125.BLIF N_125_i -0 1 -.names N_126.BLIF N_126_i -0 1 -.names N_125_i.BLIF N_126_i.BLIF cpu_est_ns_e_0_0__n -11 1 -.names N_85.BLIF N_85_i -0 1 -.names N_123.BLIF N_123_i -0 1 -.names N_124.BLIF N_124_i -0 1 -.names sm_amiga_ns_0_1_0__n.BLIF N_123_i.BLIF sm_amiga_ns_0_0__n -11 1 -.names N_122.BLIF N_122_i -0 1 -.names N_227.BLIF N_227_i -0 1 -.names N_228.BLIF N_228_i -0 1 -.names cpu_est_ns_0_1_2__n.BLIF N_227_i.BLIF cpu_est_ns_0_2__n -11 1 -.names N_226.BLIF N_226_i -0 1 -.names N_56.BLIF N_226_i.BLIF N_44_i -11 1 -.names N_130.BLIF N_130_i -0 1 -.names N_225.BLIF N_225_i -0 1 -.names cpu_est_ns_0_1__n.BLIF cpu_est_ns_1__n -0 1 -.names N_130_i.BLIF N_225_i.BLIF N_158_i -11 1 -.names cpu_est_ns_0_2__n.BLIF cpu_est_ns_2__n -0 1 -.names N_219.BLIF N_219_i -0 1 -.names N_204_0.BLIF N_204 -0 1 -.names N_220.BLIF N_220_i -0 1 -.names N_205_0.BLIF N_205 -0 1 -.names N_219_i.BLIF N_220_i.BLIF sm_amiga_ns_0_7__n -11 1 -.names N_206_0.BLIF N_206 -0 1 -.names N_215.BLIF N_215_i -0 1 -.names N_26_0.BLIF N_26 -0 1 -.names N_216.BLIF N_216_i -0 1 -.names N_30_0.BLIF N_30 -0 1 -.names state_machine_uds_000_int_5_0_m2_un1_n.BLIF \ -state_machine_uds_000_int_5_0_m2_un0_n.BLIF N_49 -1- 1 --1 1 -.names N_95.BLIF N_95_i -0 1 -.names N_50_i.BLIF N_50 -0 1 -.names N_214.BLIF N_214_i -0 1 -.names N_51_i.BLIF N_51 -0 1 -.names N_95_i.BLIF N_214_i.BLIF sm_amiga_ns_0_5__n -11 1 -.names N_54_i.BLIF N_54 -0 1 -.names N_94.BLIF N_94_i -0 1 -.names N_55_i.BLIF N_55 -0 1 -.names N_133.BLIF N_133_i -0 1 -.names N_56_i.BLIF N_56 -0 1 -.names N_57_i.BLIF N_57 -0 1 -.names N_87.BLIF N_87_i -0 1 -.names N_59_i.BLIF N_59 -0 1 -.names N_60_i.BLIF N_60 -0 1 -.names N_86.BLIF N_86_i -0 1 -.names N_62_0.BLIF N_62 -0 1 -.names N_63_0.BLIF N_63 -0 1 -.names N_83.BLIF N_83_i -0 1 -.names BGACK_030_INT_i.BLIF nEXP_SPACE_i.BLIF N_68 -11 1 -.names N_70_1.BLIF N_70_2.BLIF N_70 -11 1 -.names N_82.BLIF N_82_i -0 1 -.names N_72_1.BLIF VPA_D_i.BLIF N_72 -11 1 -.names N_60_i.BLIF N_82_i.BLIF state_machine_lds_000_int_5_0_n -11 1 -.names N_73_1.BLIF cpu_est_2_.BLIF N_73 -11 1 -.names a_i_0__n.BLIF N_60_i.BLIF state_machine_uds_000_int_5_0_n -11 1 -.names N_74_3.BLIF VPA_D_i.BLIF N_74 -11 1 -.names N_80.BLIF N_80_i -0 1 -.names CLK_030_c.BLIF N_55_i.BLIF N_76 -11 1 -.names N_80_i.BLIF un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0.BLIF N_30_0 -11 1 -.names N_78_1.BLIF N_78_2.BLIF N_78 -11 1 -.names AS_030_i.BLIF N_78_i.BLIF N_26_0 -11 1 -.names N_80_1.BLIF N_80_2.BLIF N_80 -11 1 -.names N_76.BLIF N_76_i -0 1 -.names N_82_1.BLIF size_i_1__n.BLIF N_82 -11 1 -.names AS_030_i.BLIF N_76_i.BLIF N_206_0 -11 1 -.names N_62.BLIF sm_amiga_i_7__n.BLIF N_83 -11 1 -.names AS_030_i.BLIF N_74_i.BLIF N_205_0 -11 1 -.names SM_AMIGA_7_.BLIF state_machine_un8_clk_000_d2_i_n.BLIF N_85 -11 1 -.names N_72.BLIF N_72_i -0 1 -.names sm_amiga_i_5__n.BLIF sm_amiga_i_6__n.BLIF N_86 -11 1 -.names N_73.BLIF N_73_i -0 1 -.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_87 -11 1 -.names N_72_i.BLIF N_73_i.BLIF state_machine_un15_clk_000_d0_0_n -11 1 -.names N_63.BLIF sm_amiga_i_3__n.BLIF N_94 -11 1 -.names AS_030_i.BLIF N_60.BLIF N_204_0 -11 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_95 -11 1 -.names BG_030_c.BLIF BG_030_c_i -0 1 -.names N_133.BLIF SM_AMIGA_3_.BLIF N_214 -11 1 -.names N_70.BLIF N_70_i -0 1 -.names CLK_000_D0_i.BLIF N_57.BLIF N_215 -11 1 -.names BG_030_c_i.BLIF N_70_i.BLIF state_machine_un10_bg_030_0_n -11 1 -.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_216 -11 1 -.names BGACK_000_c.BLIF N_54.BLIF state_machine_un6_bgack_000_0_n -11 1 -.names N_50.BLIF SM_AMIGA_0_.BLIF N_219 -11 1 -.names N_220_1.BLIF state_machine_un6_clk_000_d5_i_n.BLIF N_220 -11 1 -.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \ -state_machine_un23_clk_000_d0_0_n -11 1 -.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF N_221 -11 1 -.names a_i_24__n.BLIF a_i_25__n.BLIF N_236_1 -11 1 -.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_222 -11 1 -.names a_i_26__n.BLIF a_i_27__n.BLIF N_236_2 -11 1 -.names N_59.BLIF cpu_est_2_.BLIF N_225 -11 1 -.names a_i_28__n.BLIF a_i_29__n.BLIF N_236_3 -11 1 -.names N_226_1.BLIF sm_amiga_i_6__n.BLIF N_226 -11 1 -.names a_i_30__n.BLIF a_i_31__n.BLIF N_236_4 -11 1 -.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_227 -11 1 -.names N_236_1.BLIF N_236_2.BLIF N_236_5 -11 1 -.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_228 -11 1 -.names N_236_3.BLIF N_236_4.BLIF N_236_6 -11 1 -.names cpu_est_0_.BLIF cpu_est_3_reg.BLIF N_122 -11 1 -.names a_c_20__n.BLIF a_c_21__n.BLIF N_239_1 -11 1 -.names CLK_000_D0_i.BLIF N_132.BLIF N_123 -11 1 -.names a_c_22__n.BLIF a_c_23__n.BLIF N_239_2 -11 1 -.names N_50_i.BLIF SM_AMIGA_0_.BLIF N_124 -11 1 .names inst_CLK_000_D3.BLIF AS_030_000_SYNC_i.BLIF \ state_machine_un8_clk_000_d2_1_n 11 1 -.names N_54.BLIF cpu_est_0_.BLIF N_125 -11 1 -.names a_c_17__n.BLIF BGACK_000_c.BLIF N_55_i_1 -11 1 -.names N_54_i.BLIF cpu_est_i_0__n.BLIF N_126 -11 1 -.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_55_i_2 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_129 -11 1 -.names a_i_19__n.BLIF a_i_16__n.BLIF N_55_i_3 -11 1 -.names N_129.BLIF cpu_est_i_3__n.BLIF N_130 -11 1 -.names N_55_i_1.BLIF N_55_i_2.BLIF N_55_i_4 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_131 -11 1 -.names N_55_i_3.BLIF a_i_18__n.BLIF N_55_i_5 -11 1 -.names SM_AMIGA_6_.BLIF nEXP_SPACE_i.BLIF N_132 -11 1 -.names N_129_i.BLIF N_131_i.BLIF cpu_est_ns_0_1_1__n -11 1 -.names CLK_000_D0_i.BLIF state_machine_un23_clk_000_d0_n.BLIF N_133 -11 1 -.names N_221_i.BLIF N_222_i.BLIF cpu_est_ns_0_2_1__n -11 1 -.names N_236_5.BLIF N_236_6.BLIF N_236 -11 1 -.names CLK_030_c.BLIF N_55.BLIF N_80_1 -11 1 -.names N_239_1.BLIF N_239_2.BLIF N_239 -11 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_80_2 -11 1 -.names RW_c.BLIF RW_i +.names N_228.BLIF N_228_i 0 1 -.names inst_CLK_000_D0.BLIF DTACK_i.BLIF N_78_1 -11 1 -.names inst_VMA_INTreg.BLIF VMA_INT_i -0 1 -.names SM_AMIGA_3_.BLIF inst_VPA_D.BLIF N_78_2 -11 1 -.names inst_VPA_D.BLIF VPA_D_i -0 1 -.names inst_CLK_000_D0.BLIF N_59_i.BLIF N_74_1 -11 1 -.names DTACK_c.BLIF DTACK_i -0 1 -.names SM_AMIGA_3_.BLIF VMA_INT_i.BLIF N_74_2 -11 1 -.names inst_CLK_000_D0.BLIF CLK_000_D0_i -0 1 -.names N_74_1.BLIF N_74_2.BLIF N_74_3 -11 1 -.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n -0 1 -.names AS_030_c.BLIF CLK_000_c.BLIF N_70_1 -11 1 -.names cpu_est_3_reg.BLIF cpu_est_i_3__n -0 1 -.names SM_AMIGA_7_.BLIF nEXP_SPACE_c.BLIF N_70_2 -11 1 -.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n -0 1 -.names N_124_i.BLIF N_85_i.BLIF sm_amiga_ns_0_1_0__n -11 1 -.names state_machine_un6_clk_000_d5_n.BLIF state_machine_un6_clk_000_d5_i_n -0 1 -.names N_228_i.BLIF N_122_i.BLIF cpu_est_ns_0_1_2__n -11 1 -.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n -0 1 -.names AMIGA_BUS_ENABLE_i.BLIF AS_030_i.BLIF N_226_1 -11 1 -.names nEXP_SPACE_c.BLIF nEXP_SPACE_i -0 1 -.names CLK_000_D0_i.BLIF SM_AMIGA_1_.BLIF N_220_1 -11 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_i -0 1 -.names a_i_0__n.BLIF size_c_0__n.BLIF N_82_1 -11 1 -.names cpu_est_1_.BLIF cpu_est_i_1__n -0 1 -.names N_50_i.BLIF N_130.BLIF N_73_1 -11 1 -.names cpu_est_0_.BLIF cpu_est_i_0__n -0 1 -.names CLK_000_D0_i.BLIF N_131.BLIF N_72_1 -11 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE_i -0 1 -.names RW_c.BLIF state_machine_uds_000_int_5_0_m2_un3_n -0 1 -.names AS_030_c.BLIF AS_030_i -0 1 -.names SM_AMIGA_5_.BLIF RW_c.BLIF state_machine_uds_000_int_5_0_m2_un1_n -11 1 -.names cpu_est_2_.BLIF cpu_est_i_2__n -0 1 -.names SM_AMIGA_4_.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF \ -state_machine_uds_000_int_5_0_m2_un0_n -11 1 -.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n -0 1 -.names N_205.BLIF vpa_sync_0_un3_n -0 1 -.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n -0 1 -.names N_74_i.BLIF N_205.BLIF vpa_sync_0_un1_n +.names N_173_i.BLIF N_132_i.BLIF sm_amiga_ns_0_1_0__n 11 1 .names SM_AMIGA_5_.BLIF sm_amiga_i_5__n 0 1 +.names N_155_i.BLIF cpu_est_ns_0_0_x2_1_.BLIF cpu_est_ns_0_1_1__n +11 1 +.names N_224.BLIF N_224_i +0 1 +.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_138_1 +11 1 +.names N_223.BLIF N_223_i +0 1 +.names A0_i.BLIF size_c_0__n.BLIF N_130_1 +11 1 +.names SIZE_DMA_0_sqmuxa.BLIF SIZE_DMA_0_sqmuxa_i +0 1 +.names LDS_000_i.BLIF N_151.BLIF N_128_1 +11 1 +.names SIZE_DMA_1_sqmuxa.BLIF SIZE_DMA_1_sqmuxa_i +0 1 +.names N_59_i.BLIF N_154.BLIF N_221_1 +11 1 +.names a_c_18__n.BLIF a_i_18__n +0 1 +.names CLK_000_D0_i.BLIF N_155.BLIF N_219_1 +11 1 +.names a_c_16__n.BLIF a_i_16__n +0 1 +.names N_214.BLIF vpa_sync_0_un3_n +0 1 +.names a_c_19__n.BLIF a_i_19__n +0 1 +.names N_224_i.BLIF N_214.BLIF vpa_sync_0_un1_n +11 1 +.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +0 1 .names inst_VPA_SYNC.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n 11 1 -.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n -0 1 -.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n -0 1 -.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n -0 1 -.names N_50_i.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n -11 1 -.names a_c_0__n.BLIF a_i_0__n -0 1 -.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n -11 1 -.names size_c_1__n.BLIF size_i_1__n -0 1 -.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n -0 1 -.names dsack_c_1__n.BLIF dsack_i_1__n -0 1 -.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n -11 1 -.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i -0 1 -.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n -11 1 .names inst_CLK_000_D2.BLIF CLK_000_D2_i 0 1 -.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n +.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n 0 1 -.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i +.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i +0 1 +.names inst_AS_000_INT.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +11 1 +.names nEXP_SPACE_c.BLIF nEXP_SPACE_i +0 1 +.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +11 1 +.names AS_030_c.BLIF AS_030_i +0 1 +.names N_249.BLIF as_000_dma_0_un3_n +0 1 +.names inst_BGACK_030_INT_D.BLIF BGACK_030_INT_D_i +0 1 +.names inst_AS_000_DMA.BLIF N_249.BLIF as_000_dma_0_un1_n +11 1 +.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n +0 1 +.names un1_as_000_dma5_0__n.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n +11 1 +.names state_machine_un8_clk_000_d2_n.BLIF state_machine_un8_clk_000_d2_i_n +0 1 +.names state_machine_un10_bg_030_n.BLIF bg_000_0_un3_n +0 1 +.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n +0 1 +.names BG_030_c.BLIF state_machine_un10_bg_030_n.BLIF bg_000_0_un1_n +11 1 +.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n +0 1 +.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n +11 1 +.names inst_CLK_000_D0.BLIF CLK_000_D0_i +0 1 +.names N_249.BLIF a0_dma_0_un3_n +0 1 +.names RW_c.BLIF RW_i +0 1 +.names inst_A0_DMA.BLIF N_249.BLIF a0_dma_0_un1_n +11 1 +.names UDS_000_c.BLIF UDS_000_i +0 1 +.names N_128.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n +11 1 +.names LDS_000_c.BLIF LDS_000_i +0 1 +.names N_216.BLIF dtack_sync_0_un3_n +0 1 +.names DTACK_c.BLIF DTACK_i +0 1 +.names N_228_i.BLIF N_216.BLIF dtack_sync_0_un1_n +11 1 +.names inst_VMA_INTreg.BLIF VMA_INT_i +0 1 +.names inst_DTACK_SYNC.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n +11 1 +.names VPA_c.BLIF VPA_i +0 1 +.names N_215.BLIF lds_000_int_0_un3_n +0 1 +.names cpu_est_0_.BLIF cpu_est_i_0__n +0 1 +.names state_machine_lds_000_int_5_n.BLIF N_215.BLIF lds_000_int_0_un1_n +11 1 +.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n +0 1 +.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +11 1 +.names cpu_est_3_reg.BLIF cpu_est_i_3__n +0 1 +.names N_215.BLIF uds_000_int_0_un3_n +0 1 +.names cpu_est_1_.BLIF cpu_est_i_1__n +0 1 +.names state_machine_uds_000_int_5_n.BLIF N_215.BLIF uds_000_int_0_un1_n +11 1 +.names A0_c.BLIF A0_i +0 1 +.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n +11 1 +.names size_c_1__n.BLIF size_i_1__n +0 1 +.names N_33.BLIF fpu_cs_int_0_un3_n +0 1 +.names a_c_30__n.BLIF a_i_30__n +0 1 +.names AS_030_c.BLIF N_33.BLIF fpu_cs_int_0_un1_n +11 1 +.names a_c_31__n.BLIF a_i_31__n +0 1 +.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n +11 1 +.names a_c_28__n.BLIF a_i_28__n +0 1 +.names N_249.BLIF ds_000_dma_0_un3_n +0 1 +.names a_c_29__n.BLIF a_i_29__n +0 1 +.names inst_DS_000_DMA.BLIF N_249.BLIF ds_000_dma_0_un1_n +11 1 +.names a_c_26__n.BLIF a_i_26__n +0 1 +.names state_machine_ds_000_dma_5_n.BLIF ds_000_dma_0_un3_n.BLIF \ +ds_000_dma_0_un0_n +11 1 +.names a_c_27__n.BLIF a_i_27__n +0 1 +.names N_35.BLIF as_030_000_sync_0_un3_n +0 1 +.names a_c_24__n.BLIF a_i_24__n +0 1 +.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_4.BLIF N_35.BLIF as_030_000_sync_0_un1_n +11 1 +.names a_c_25__n.BLIF a_i_25__n +0 1 +.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ +as_030_000_sync_0_un0_n +11 1 +.names RST_c.BLIF RST_i +0 1 +.names N_249.BLIF size_dma_0_1__un3_n +0 1 +.names SIZE_DMA_1_.BLIF N_249.BLIF size_dma_0_1__un1_n +11 1 +.names CLK_OSZI_c.BLIF CLK_OSZI_i +0 1 +.names SIZE_DMA_1_sqmuxa_i.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n +11 1 +.names N_249.BLIF size_dma_0_0__un3_n +0 1 +.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i +0 1 +.names SIZE_DMA_0_.BLIF N_249.BLIF size_dma_0_0__un1_n +11 1 +.names SIZE_DMA_0_sqmuxa_i.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n +11 1 +.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n 0 1 .names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \ bgack_030_int_0_un1_n 11 1 -.names a_c_19__n.BLIF a_i_19__n -0 1 .names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \ bgack_030_int_0_un0_n 11 1 -.names a_c_16__n.BLIF a_i_16__n +.names N_61.BLIF dsack1_int_0_un3_n 0 1 -.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n -0 1 -.names a_c_18__n.BLIF a_i_18__n -0 1 -.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n +.names N_223_i.BLIF N_61.BLIF dsack1_int_0_un1_n 11 1 -.names a_c_30__n.BLIF a_i_30__n -0 1 -.names sm_amiga_i_5__n.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n +.names inst_DSACK1_INT.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n 11 1 -.names a_c_31__n.BLIF a_i_31__n +.names RW_c.BLIF state_machine_uds_000_int_5_0_m2_un3_n 0 1 -.names N_54.BLIF ipl_030_0_0__un3_n -0 1 -.names a_c_28__n.BLIF a_i_28__n -0 1 -.names IPL_030DFFSH_0_reg.BLIF N_54.BLIF ipl_030_0_0__un1_n +.names SM_AMIGA_5_.BLIF RW_c.BLIF state_machine_uds_000_int_5_0_m2_un1_n 11 1 -.names a_c_29__n.BLIF a_i_29__n +.names SM_AMIGA_4_.BLIF state_machine_uds_000_int_5_0_m2_un3_n.BLIF \ +state_machine_uds_000_int_5_0_m2_un0_n +11 1 +.names cpu_est_1_.BLIF cpu_est_ns_0_0_m2_2__un3_n 0 1 +.names cpu_est_2_.BLIF cpu_est_1_.BLIF cpu_est_ns_0_0_m2_2__un1_n +11 1 +.names cpu_est_i_0__n.BLIF cpu_est_ns_0_0_m2_2__un3_n.BLIF \ +cpu_est_ns_0_0_m2_2__un0_n +11 1 +.names N_52.BLIF amiga_bus_enable_0_un3_n +0 1 +.names un1_AMIGA_BUS_ENABLE_0_sqmuxa_2.BLIF N_52.BLIF amiga_bus_enable_0_un1_n +11 1 +.names AMIGA_BUS_ENABLEDFFSHreg.BLIF amiga_bus_enable_0_un3_n.BLIF \ +amiga_bus_enable_0_un0_n +11 1 +.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n +0 1 +.names N_59_i.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n +11 1 +.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n +11 1 +.names N_65.BLIF ipl_030_0_0__un3_n +0 1 +.names IPL_030DFFSH_0_reg.BLIF N_65.BLIF ipl_030_0_0__un1_n +11 1 .names ipl_c_0__n.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n 11 1 -.names a_c_26__n.BLIF a_i_26__n +.names N_65.BLIF ipl_030_0_1__un3_n 0 1 -.names N_54.BLIF ipl_030_0_1__un3_n -0 1 -.names a_c_27__n.BLIF a_i_27__n -0 1 -.names IPL_030DFFSH_1_reg.BLIF N_54.BLIF ipl_030_0_1__un1_n +.names IPL_030DFFSH_1_reg.BLIF N_65.BLIF ipl_030_0_1__un1_n 11 1 -.names a_c_24__n.BLIF a_i_24__n -0 1 .names ipl_c_1__n.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n 11 1 -.names a_c_25__n.BLIF a_i_25__n +.names N_65.BLIF ipl_030_0_2__un3_n 0 1 -.names N_54.BLIF ipl_030_0_2__un3_n -0 1 -.names RST_c.BLIF RST_i -0 1 -.names IPL_030DFFSH_2_reg.BLIF N_54.BLIF ipl_030_0_2__un1_n +.names IPL_030DFFSH_2_reg.BLIF N_65.BLIF ipl_030_0_2__un1_n 11 1 .names ipl_c_2__n.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n 11 1 -.names N_54.BLIF cpu_estse_0_un3_n +.names N_65.BLIF cpu_estse_0_un3_n 0 1 -.names CLK_OSZI_c.BLIF CLK_OSZI_i -0 1 -.names cpu_est_1_.BLIF N_54.BLIF cpu_estse_0_un1_n +.names cpu_est_1_.BLIF N_65.BLIF cpu_estse_0_un1_n 11 1 .names cpu_est_ns_1__n.BLIF cpu_estse_0_un3_n.BLIF cpu_estse_0_un0_n 11 1 -.names N_74.BLIF N_74_i +.names N_65.BLIF cpu_estse_1_un3_n 0 1 -.names N_54.BLIF cpu_estse_1_un3_n -0 1 -.names N_78.BLIF N_78_i -0 1 -.names cpu_est_2_.BLIF N_54.BLIF cpu_estse_1_un1_n +.names cpu_est_2_.BLIF N_65.BLIF cpu_estse_1_un1_n 11 1 -.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i -0 1 .names cpu_est_ns_2__n.BLIF cpu_estse_1_un3_n.BLIF cpu_estse_1_un0_n 11 1 -.names inst_CLK_000_D6.BLIF CLK_000_D6_i +.names N_65.BLIF cpu_estse_2_un3_n 0 1 -.names N_54.BLIF cpu_estse_2_un3_n -0 1 -.names cpu_est_3_reg.BLIF N_54.BLIF cpu_estse_2_un1_n +.names cpu_est_3_reg.BLIF N_65.BLIF cpu_estse_2_un1_n 11 1 -.names N_158_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n -11 1 -.names N_30.BLIF as_030_000_sync_0_un3_n -0 1 -.names un1_AMIGA_BUS_ENABLE_1_sqmuxa_2.BLIF N_30.BLIF as_030_000_sync_0_un1_n -11 1 -.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \ -as_030_000_sync_0_un0_n -11 1 -.names N_26.BLIF dtack_sync_0_un3_n -0 1 -.names N_78_i.BLIF N_26.BLIF dtack_sync_0_un1_n -11 1 -.names inst_DTACK_SYNC.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n -11 1 -.names N_206.BLIF fpu_cs_int_0_un3_n -0 1 -.names AS_030_c.BLIF N_206.BLIF fpu_cs_int_0_un1_n -11 1 -.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n -11 1 -.names N_51.BLIF dsack_int_0_1__un3_n -0 1 -.names N_57.BLIF N_51.BLIF dsack_int_0_1__un1_n -11 1 -.names DSACK_INT_1_.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n -11 1 -.names RST_c.BLIF amiga_bus_enable_0_un3_n -0 1 -.names N_44_i.BLIF RST_c.BLIF amiga_bus_enable_0_un1_n -11 1 -.names AMIGA_BUS_ENABLEDFFreg.BLIF amiga_bus_enable_0_un3_n.BLIF \ -amiga_bus_enable_0_un0_n -11 1 -.names N_204.BLIF uds_000_int_0_un3_n -0 1 -.names state_machine_uds_000_int_5_n.BLIF N_204.BLIF uds_000_int_0_un1_n -11 1 -.names inst_UDS_000_INTreg.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n -11 1 -.names N_204.BLIF lds_000_int_0_un3_n -0 1 -.names state_machine_lds_000_int_5_n.BLIF N_204.BLIF lds_000_int_0_un1_n -11 1 -.names inst_LDS_000_INTreg.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n +.names N_161_i.BLIF cpu_estse_2_un3_n.BLIF cpu_estse_2_un0_n 11 1 .names IPL_030DFFSH_2_reg.BLIF IPL_030_2_ 1 1 0 0 -.names inst_AS_000_INTreg.BLIF AS_000 -1 1 -0 0 -.names inst_UDS_000_INTreg.BLIF UDS_000 -1 1 -0 0 -.names inst_LDS_000_INTreg.BLIF LDS_000 -1 1 -0 0 .names gnd_n_n.BLIF BERR 1 1 0 0 @@ -941,16 +1059,16 @@ amiga_bus_enable_0_un0_n .names RESETDFFRHreg.BLIF RESET 1 1 0 0 -.names AMIGA_BUS_ENABLEDFFreg.BLIF AMIGA_BUS_ENABLE +.names AMIGA_BUS_ENABLEDFFSHreg.BLIF AMIGA_BUS_ENABLE 1 1 0 0 -.names RW_i.BLIF AMIGA_BUS_DATA_DIR +.names AMIGA_BUS_DATA_DIR_m1_0_x2.BLIF AMIGA_BUS_DATA_DIR 1 1 0 0 .names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW 1 1 0 0 -.names N_239.BLIF CIIN +.names N_237.BLIF CIIN 1 1 0 0 .names IPL_030DFFSH_1_reg.BLIF IPL_030_1_ @@ -983,12 +1101,6 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF cpu_est_0_.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C -1 1 -0 0 -.names RST_i.BLIF SM_AMIGA_5_.AR -1 1 -0 0 .names CLK_OSZI_c.BLIF SM_AMIGA_4_.C 1 1 0 0 @@ -1019,27 +1131,6 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF SM_AMIGA_0_.AR 1 1 0 0 -.names CLK_OSZI_i.BLIF CLK_CNT_N_0_.C -1 1 -0 0 -.names RST_i.BLIF CLK_CNT_N_0_.AR -1 1 -0 0 -.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D -1 1 -0 0 -.names CLK_OSZI_i.BLIF CLK_CNT_N_1_.C -1 1 -0 0 -.names RST_i.BLIF CLK_CNT_N_1_.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF CLK_CNT_P_0_.C -1 1 -0 0 -.names RST_i.BLIF CLK_CNT_P_0_.AR -1 1 -0 0 .names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.D 1 1 0 0 @@ -1049,6 +1140,18 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF CLK_CNT_P_1_.AR 1 1 0 0 +.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C +1 1 +0 0 +.names RST_i.BLIF SIZE_DMA_0_.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C +1 1 +0 0 +.names RST_i.BLIF SIZE_DMA_1_.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C 1 1 0 0 @@ -1079,16 +1182,10 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF SM_AMIGA_6_.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C +.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C 1 1 0 0 -.names RST_i.BLIF inst_UDS_000_INTreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_LDS_000_INTreg.AP +.names RST_i.BLIF SM_AMIGA_5_.AR 1 1 0 0 .names CLK_OSZI_c.BLIF inst_VPA_SYNC.C @@ -1097,34 +1194,109 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF inst_VPA_SYNC.AP 1 1 0 0 +.names CLK_OSZI_c.BLIF inst_DSACK1_INT.C +1 1 +0 0 +.names RST_i.BLIF inst_DSACK1_INT.AP +1 1 +0 0 .names CLK_OSZI_c.BLIF inst_VMA_INTreg.C 1 1 0 0 .names RST_i.BLIF inst_VMA_INTreg.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C -1 1 -0 0 -.names RST_i.BLIF BG_000DFFSHreg.AP -1 1 -0 0 .names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C 1 1 0 0 .names RST_i.BLIF inst_BGACK_030_INTreg.AP 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C +.names CLK_OSZI_i.BLIF CLK_CNT_N_0_.C 1 1 0 0 -.names RST_i.BLIF inst_AS_000_INTreg.AP +.names RST_i.BLIF CLK_CNT_N_0_.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.D 1 1 0 0 -.names RST_i.BLIF inst_CLK_OUT_PRE.AR +.names CLK_OSZI_i.BLIF CLK_CNT_N_1_.C +1 1 +0 0 +.names RST_i.BLIF CLK_CNT_N_1_.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF CLK_CNT_P_0_.C +1 1 +0 0 +.names RST_i.BLIF CLK_CNT_P_0_.AR +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C +1 1 +0 0 +.names RST_i.BLIF inst_LDS_000_INT.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C +1 1 +0 0 +.names RST_i.BLIF inst_DTACK_SYNC.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_A0_DMA.C +1 1 +0 0 +.names RST_i.BLIF inst_A0_DMA.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C +1 1 +0 0 +.names RST_i.BLIF BG_000DFFSHreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C +1 1 +0 0 +.names RST_i.BLIF inst_AS_000_DMA.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFSHreg.C +1 1 +0 0 +.names RST_i.BLIF AMIGA_BUS_ENABLEDFFSHreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_000_INT.C +1 1 +0 0 +.names RST_i.BLIF inst_AS_000_INT.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +1 1 +0 0 +.names RST_i.BLIF inst_AS_030_000_SYNC.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C +1 1 +0 0 +.names RST_i.BLIF inst_DS_000_DMA.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C +1 1 +0 0 +.names RST_i.BLIF inst_FPU_CS_INTreg.AP +1 1 +0 0 +.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C +1 1 +0 0 +.names RST_i.BLIF inst_UDS_000_INT.AP 1 1 0 0 .names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D @@ -1136,37 +1308,10 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF CLK_OUT_INTreg.AR 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C +.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C 1 1 0 0 -.names RST_i.BLIF inst_AS_030_000_SYNC.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C -1 1 -0 0 -.names RST_i.BLIF inst_DTACK_SYNC.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C -1 1 -0 0 -.names RST_i.BLIF inst_FPU_CS_INTreg.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF DSACK_INT_1_.C -1 1 -0 0 -.names RST_i.BLIF DSACK_INT_1_.AP -1 1 -0 0 -.names CLK_OSZI_c.BLIF AMIGA_BUS_ENABLEDFFreg.C -1 1 -0 0 -.names CLK_OSZI_c.BLIF inst_DTACK_DMA.C -1 1 -0 0 -.names RST_i.BLIF inst_DTACK_DMA.AP +.names RST_i.BLIF inst_CLK_OUT_PRE.AR 1 1 0 0 .names inst_CLK_000_D4.BLIF inst_CLK_000_D5.D @@ -1214,13 +1359,13 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF inst_CLK_000_D3.AP 1 1 0 0 -.names VPA.BLIF inst_VPA_D.D +.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D 1 1 0 0 -.names CLK_OSZI_c.BLIF inst_VPA_D.C +.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C 1 1 0 0 -.names RST_i.BLIF inst_VPA_D.AP +.names RST_i.BLIF inst_BGACK_030_INT_D.AP 1 1 0 0 .names CLK_000_c.BLIF inst_CLK_000_D0.D @@ -1250,13 +1395,46 @@ amiga_bus_enable_0_un0_n .names RST_i.BLIF inst_CLK_000_D1.AP 1 1 0 0 -.names DSACK_INT_1_.BLIF DSACK_1_ +.names SIZE_DMA_1_.BLIF SIZE_1_ 1 1 0 0 -.names inst_DTACK_DMA.BLIF DTACK +.names inst_DSACK1_INT.BLIF DSACK_1_ 1 1 0 0 -.names vcc_n_n.BLIF DSACK_0_ +.names inst_AS_000_DMA.BLIF AS_030 +1 1 +0 0 +.names inst_AS_000_INT.BLIF AS_000 +1 1 +0 0 +.names inst_DS_000_DMA.BLIF DS_030 +1 1 +0 0 +.names inst_UDS_000_INT.BLIF UDS_000 +1 1 +0 0 +.names inst_LDS_000_INT.BLIF LDS_000 +1 1 +0 0 +.names inst_A0_DMA.BLIF A0 +1 1 +0 0 +.names dsack_c_1__n.BLIF DTACK +1 1 +0 0 +.names SIZE_DMA_0_.BLIF SIZE_0_ +1 1 +0 0 +.names gnd_n_n.BLIF DSACK_0_ +1 1 +0 0 +.names BG_030.BLIF BG_030_c +1 1 +0 0 +.names BGACK_000.BLIF BGACK_000_c +1 1 +0 0 +.names CLK_030.BLIF CLK_030_c 1 1 0 0 .names CLK_000.BLIF CLK_000_c @@ -1280,6 +1458,9 @@ amiga_bus_enable_0_un0_n .names DTACK.PIN.BLIF DTACK_c 1 1 0 0 +.names VPA.BLIF VPA_c +1 1 +0 0 .names RST.BLIF RST_c 1 1 0 0 @@ -1292,102 +1473,63 @@ amiga_bus_enable_0_un0_n .names FC_1_.BLIF fc_c_1__n 1 1 0 0 -.names AS_030.BLIF AS_030_c +.names AS_030.PIN.BLIF AS_030_c 1 1 0 0 -.names DS_030.BLIF DS_030_c +.names AS_000.PIN.BLIF AS_000_c 1 1 0 0 -.names SIZE_0_.BLIF size_c_0__n +.names DS_030.PIN.BLIF DS_030_c 1 1 0 0 -.names SIZE_1_.BLIF size_c_1__n +.names UDS_000.PIN.BLIF UDS_000_c 1 1 0 0 -.names A_0_.BLIF a_c_0__n +.names LDS_000.PIN.BLIF LDS_000_c 1 1 0 0 -.names A_15_.BLIF a_15__n +.names SIZE_0_.PIN.BLIF size_c_0__n 1 1 0 0 -.names A_14_.BLIF a_14__n -1 1 -0 0 -.names A_13_.BLIF a_13__n +.names SIZE_1_.PIN.BLIF size_c_1__n 1 1 0 0 .names A_16_.BLIF a_c_16__n 1 1 0 0 -.names A_12_.BLIF a_12__n -1 1 -0 0 .names A_17_.BLIF a_c_17__n 1 1 0 0 -.names A_11_.BLIF a_11__n -1 1 -0 0 .names A_18_.BLIF a_c_18__n 1 1 0 0 -.names A_10_.BLIF a_10__n -1 1 -0 0 .names A_19_.BLIF a_c_19__n 1 1 0 0 -.names A_9_.BLIF a_9__n -1 1 -0 0 .names A_20_.BLIF a_c_20__n 1 1 0 0 -.names A_8_.BLIF a_8__n -1 1 -0 0 .names A_21_.BLIF a_c_21__n 1 1 0 0 -.names A_7_.BLIF a_7__n -1 1 -0 0 .names A_22_.BLIF a_c_22__n 1 1 0 0 -.names A_6_.BLIF a_6__n -1 1 -0 0 .names A_23_.BLIF a_c_23__n 1 1 0 0 -.names A_5_.BLIF a_5__n -1 1 -0 0 .names A_24_.BLIF a_c_24__n 1 1 0 0 -.names A_4_.BLIF a_4__n -1 1 -0 0 .names A_25_.BLIF a_c_25__n 1 1 0 0 -.names A_3_.BLIF a_3__n -1 1 -0 0 .names A_26_.BLIF a_c_26__n 1 1 0 0 -.names A_2_.BLIF a_2__n -1 1 -0 0 .names A_27_.BLIF a_c_27__n 1 1 0 0 -.names A_1_.BLIF a_1__n -1 1 -0 0 .names A_28_.BLIF a_c_28__n 1 1 0 0 @@ -1400,51 +1542,70 @@ amiga_bus_enable_0_un0_n .names A_31_.BLIF a_c_31__n 1 1 0 0 +.names A0.PIN.BLIF A0_c +1 1 +0 0 .names nEXP_SPACE.BLIF nEXP_SPACE_c 1 1 0 0 -.names BG_030.BLIF BG_030_c -1 1 -0 0 -.names BGACK_000.BLIF BGACK_000_c -1 1 -0 0 -.names CLK_030.BLIF CLK_030_c -1 1 -0 0 -.names nEXP_SPACE_c.BLIF DSACK_1_.OE -1 1 -0 0 -.names N_68.BLIF DTACK.OE +.names N_217.BLIF AS_030.OE 1 1 0 0 .names inst_BGACK_030_INTreg.BLIF AS_000.OE 1 1 0 0 +.names N_217.BLIF DS_030.OE +1 1 +0 0 .names inst_BGACK_030_INTreg.BLIF UDS_000.OE 1 1 0 0 .names inst_BGACK_030_INTreg.BLIF LDS_000.OE 1 1 0 0 +.names N_217.BLIF SIZE_0_.OE +1 1 +0 0 +.names N_217.BLIF SIZE_1_.OE +1 1 +0 0 +.names N_217.BLIF A0.OE +1 1 +0 0 +.names nEXP_SPACE_c.BLIF DSACK_1_.OE +1 1 +0 0 +.names N_217.BLIF DTACK.OE +1 1 +0 0 .names FPU_CS_INT_i.BLIF BERR.OE 1 1 0 0 -.names nEXP_SPACE_c.BLIF DSACK_0_.OE +.names gnd_n_n.BLIF DSACK_0_.OE 1 1 0 0 .names FPU_CS_INT_i.BLIF AVEC_EXP.OE 1 1 0 0 -.names N_236.BLIF CIIN.OE +.names N_247.BLIF CIIN.OE 1 1 0 0 -.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF G_102 +.names CLK_CNT_N_0_.BLIF CLK_CNT_N_1_.BLIF G_103 01 1 10 1 11 0 00 0 -.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF G_108 +.names CLK_CNT_P_0_.BLIF CLK_CNT_P_1_.BLIF G_109 +01 1 +10 1 +11 0 +00 0 +.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF cpu_est_ns_0_0_x2_1_ +01 1 +10 1 +11 0 +00 0 +.names inst_BGACK_030_INTreg.BLIF RW_c.BLIF AMIGA_BUS_DATA_DIR_m1_0_x2 01 1 10 1 11 0 diff --git a/Logic/BUS68030.cmd b/Logic/BUS68030.cmd new file mode 100644 index 0000000..e7c37a0 --- /dev/null +++ b/Logic/BUS68030.cmd @@ -0,0 +1,8 @@ +STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: "c:/users/matze/documents/github/68030tk/logic" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi index 3f17245..70cf8f7 100644 --- a/Logic/BUS68030.edi +++ b/Logic/BUS68030.edi @@ -4,7 +4,7 @@ (keywordMap (keywordLevel 0)) (status (written - (timeStamp 2014 5 24 19 56 15) + (timeStamp 2014 5 24 21 59 9) (author "Synopsys, Inc.") (program "Synplify Pro" (version "G-2012.09LC-SP1 , mapper maplat, Build 621R")) ) @@ -40,15 +40,6 @@ ) ) ) - (cell DFF (cellType GENERIC) - (view prim (viewType NETLIST) - (interface - (port Q (direction OUTPUT)) - (port D (direction INPUT)) - (port CLK (direction INPUT)) - ) - ) - ) (cell DFFRH (cellType GENERIC) (view prim (viewType NETLIST) (interface @@ -118,17 +109,18 @@ (cell BUS68030 (cellType GENERIC) (view behavioral (viewType NETLIST) (interface - (port (array (rename size "SIZE(1:0)") 2) (direction INPUT)) - (port (array (rename a "A(31:0)") 32) (direction INPUT)) + (port (array (rename size "SIZE(1:0)") 2) (direction INOUT)) + (port (array (rename a "A(31:16)") 16) (direction INPUT)) (port (array (rename ipl_030 "IPL_030(2:0)") 3) (direction OUTPUT)) (port (array (rename ipl "IPL(2:0)") 3) (direction INPUT)) (port (array (rename dsack "DSACK(1:0)") 2) (direction INOUT)) (port (array (rename fc "FC(1:0)") 2) (direction INPUT)) - (port AS_030 (direction INPUT)) - (port AS_000 (direction OUTPUT)) - (port DS_030 (direction INPUT)) - (port UDS_000 (direction OUTPUT)) - (port LDS_000 (direction OUTPUT)) + (port AS_030 (direction INOUT)) + (port AS_000 (direction INOUT)) + (port DS_030 (direction INOUT)) + (port UDS_000 (direction INOUT)) + (port LDS_000 (direction INOUT)) + (port A0 (direction INOUT)) (port nEXP_SPACE (direction INPUT)) (port BERR (direction OUTPUT)) (port BG_030 (direction INPUT)) @@ -164,8 +156,6 @@ ) (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFFRH (libraryRef mach))) - ) (instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFFRH (libraryRef mach))) @@ -176,14 +166,12 @@ ) (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance (rename CLK_CNT_N_0 "CLK_CNT_N[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) - ) - (instance (rename CLK_CNT_N_1 "CLK_CNT_N[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance (rename CLK_CNT_P_0 "CLK_CNT_P[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) - ) (instance (rename CLK_CNT_P_1 "CLK_CNT_P[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) + (instance (rename SIZE_DMA_0 "SIZE_DMA[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename SIZE_DMA_1 "SIZE_DMA[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) (instance (rename IPL_030DFFSH_0 "IPL_030DFFSH[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance (rename IPL_030DFFSH_1 "IPL_030DFFSH[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) @@ -194,35 +182,47 @@ ) (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance UDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) - ) - (instance LDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance VPA_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance VMA_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance DSACK1_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance BG_000DFFSH (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance VMA_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance BGACK_030_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance AS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance (rename CLK_CNT_N_0 "CLK_CNT_N[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance CLK_OUT_PRE (viewRef prim (cellRef DFFRH (libraryRef mach))) + (instance (rename CLK_CNT_N_1 "CLK_CNT_N[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance CLK_OUT_INT (viewRef prim (cellRef DFFRH (libraryRef mach))) + (instance (rename CLK_CNT_P_0 "CLK_CNT_P[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance AS_030_000_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance LDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance DTACK_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) ) + (instance A0_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance BG_000DFFSH (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance AS_000_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance AMIGA_BUS_ENABLEDFFSH (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance AS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance AS_030_000_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance DS_000_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) (instance FPU_CS_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance (rename DSACK_INT_1 "DSACK_INT[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance UDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLEDFF (viewRef prim (cellRef DFF (libraryRef mach))) + (instance CLK_OUT_INT (viewRef prim (cellRef DFFRH (libraryRef mach))) ) - (instance DTACK_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance CLK_OUT_PRE (viewRef prim (cellRef DFFRH (libraryRef mach))) ) (instance CLK_000_D5 (viewRef prim (cellRef DFFSH (libraryRef mach))) ) @@ -234,7 +234,7 @@ ) (instance CLK_000_D3 (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance VPA_D (viewRef prim (cellRef DFFSH (libraryRef mach))) + (instance BGACK_030_INT_D (viewRef prim (cellRef DFFSH (libraryRef mach))) ) (instance CLK_000_D0 (viewRef prim (cellRef DFFSH (libraryRef mach))) ) @@ -242,14 +242,13 @@ ) (instance CLK_000_D1 (viewRef prim (cellRef DFFSH (libraryRef mach))) ) - (instance AS_030 (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance AS_000 (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance DS_030 (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance UDS_000 (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance LDS_000 (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance (rename SIZE_0 "SIZE[0]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename SIZE_1 "SIZE[1]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) - (instance (rename A_0 "A[0]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance AS_030 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance AS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance DS_030 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance UDS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance LDS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename SIZE_0 "SIZE[0]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename SIZE_1 "SIZE[1]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) (instance (rename A_16 "A[16]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) (instance (rename A_17 "A[17]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) (instance (rename A_18 "A[18]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) @@ -266,6 +265,7 @@ (instance (rename A_29 "A[29]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) (instance (rename A_30 "A[30]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) (instance (rename A_31 "A[31]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance A0 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) (instance nEXP_SPACE (viewRef prim (cellRef IBUF (libraryRef mach))) ) (instance BERR (viewRef prim (cellRef BUFTH (libraryRef mach))) ) (instance BG_030 (viewRef prim (cellRef IBUF (libraryRef mach))) ) @@ -301,41 +301,48 @@ (instance AMIGA_BUS_DATA_DIR (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0_0_a3_0_1 "state_machine.un15_clk_000_d0_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0_0_a3_0 "state_machine.un15_clk_000_d0_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0_0_a3_1 "state_machine.un15_clk_000_d0_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0_0_a3 "state_machine.un15_clk_000_d0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_i_a3_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un10_bg_030_0_a3_1 "state_machine.un10_bg_030_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un10_bg_030_0_a3_2 "state_machine.un10_bg_030_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un10_bg_030_0_a3 "state_machine.un10_bg_030_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_a2_0_1 "state_machine.un15_clk_000_d0_0_a2_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_a2_0 "state_machine.un15_clk_000_d0_0_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_a2_1 "state_machine.un15_clk_000_d0_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_a2 "state_machine.un15_clk_000_d0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SIZE_DMA_0_sqmuxa_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SIZE_DMA_1_sqmuxa_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SIZE_DMA_1_sqmuxa_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d2_1 "state_machine.un8_clk_000_d2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d2 "state_machine.un8_clk_000_d2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_0_1_0 "SM_AMIGA_ns_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_1_2 "cpu_est_ns_0_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_2 "cpu_est_ns_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1 "state_machine.AMIGA_BUS_ENABLE_3_f0_i_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3 "state_machine.AMIGA_BUS_ENABLE_3_f0_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_0_1_7 "SM_AMIGA_ns_0_a3_0_1[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_0_7 "SM_AMIGA_ns_0_a3_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_5_0_a3_1 "state_machine.LDS_000_INT_5_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_5_0_a3 "state_machine.LDS_000_INT_5_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_1_1 "cpu_est_ns_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_1 "cpu_est_ns_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a2_0_1_5 "SM_AMIGA_ns_0_a2_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a2_0_5 "SM_AMIGA_ns_0_a2_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_5_0_a2_1 "state_machine.LDS_000_INT_5_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_5_0_a2 "state_machine.LDS_000_INT_5_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_A0_DMA_4_0_a2_1_0 "state_machine.A0_DMA_4_0_a2_1_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_A0_DMA_4_0_a2 "state_machine.A0_DMA_4_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_0_sqmuxa_3_i_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_0_sqmuxa_3_i_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_0_sqmuxa_3_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_a2_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_bg_030_0_a2_1 "state_machine.un10_bg_030_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_bg_030_0_a2_2 "state_machine.un10_bg_030_0_a2_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_bg_030_0_a2 "state_machine.un10_bg_030_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1_i_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SIZE_DMA_0_sqmuxa_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_030_000_SYNC_1_sqmuxa_i_o2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_030_000_SYNC_1_sqmuxa_i_o2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_030_000_SYNC_1_sqmuxa_i_o2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance AS_030_000_SYNC_1_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_1_1 "cpu_est_ns_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_2_1 "cpu_est_ns_0_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_1 "cpu_est_ns_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_i_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_1_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_1_i_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_1_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_i_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_i_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un23_clk_000_d0_i "state_machine.un23_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un4_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un4_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -343,167 +350,253 @@ (instance un8_ciin_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance un8_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un4_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un4_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un4_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d2_1 "state_machine.un8_clk_000_d2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d2 "state_machine.un8_clk_000_d2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_i_o2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_i_o2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_5_0_i "state_machine.UDS_000_INT_5_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_80_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_76_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_030_000_sync8_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_72_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_73_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0_0_i "state_machine.un15_clk_000_d0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_as_030_3_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_70_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un10_bg_030_0_i "state_machine.un10_bg_030_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un6_bgack_000_0_i "state_machine.un6_bgack_000_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_219_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_220_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_i_7 "SM_AMIGA_ns_0_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_215_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_216_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_95_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_214_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_i_5 "SM_AMIGA_ns_0_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_94_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_133_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_87_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_86_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_83_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_82_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_5_0_i "state_machine.LDS_000_INT_5_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_89_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_125_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_126_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance cpu_estse_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_85_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_123_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_124_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_i_0 "SM_AMIGA_ns_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_122_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_227_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_228_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_145_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename cpu_est_ns_0_0_i_2 "cpu_est_ns_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_226_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_143_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_154_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_153_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_155_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_i_1 "cpu_est_ns_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_135_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_136_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_225_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_219_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_221_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_222_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_o2_i_4 "SM_AMIGA_ns_i_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0_i "state_machine.un15_clk_000_d0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_156_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_0_o2_i_1 "SM_AMIGA_ns_i_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DS_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_5_0_o3_i "state_machine.UDS_000_INT_5_0_o3_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_176_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_0_sqmuxa_3_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_173_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_226_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_o2_i_4 "SM_AMIGA_ns_i_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename cpu_est_ns_i_0_o2_i_3 "cpu_est_ns_i_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_DSACK_INT_0_sqmuxa_i_o2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2_i "state_machine.AMIGA_BUS_ENABLE_3_f0_i_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_147_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_148_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance cpu_estse_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_146_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_i_0 "SM_AMIGA_ns_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_88_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_92_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename clk_un3_clk_000_d1_0_o2_i "clk.un3_clk_000_d1_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance DSACK_INT_1_sqmuxa_i_o3_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_i_1 "cpu_est_ns_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_129_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_0_sqmuxa_3_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_175_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename un1_as_000_dma5_0_o2_i_0 "un1_as_000_dma5_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_clk_000_d5_i "state_machine.un6_clk_000_d5_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_i_o2_i_6 "SM_AMIGA_ns_i_i_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_5_0_o2_i "state_machine.UDS_000_INT_5_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance N_131_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_DSACK_INT_0_sqmuxa_i_o2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_i_0_o2_3 "cpu_est_ns_i_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_5_0_o3 "state_machine.UDS_000_INT_5_0_o3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_o2_1 "SM_AMIGA_ns_i_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_o2_4 "SM_AMIGA_ns_i_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_127 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_133_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_134_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_137_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_138_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_i_5 "SM_AMIGA_ns_0_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_139_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_140_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_i_i_6 "SM_AMIGA_ns_i_i_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_142_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_141_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_i_7 "SM_AMIGA_ns_0_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_144_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_DS_000_DMA_5_iv_0_i "state_machine.DS_000_DMA_5_iv_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un23_clk_000_d0_i "state_machine.un23_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_bgack_000_0_i "state_machine.un6_bgack_000_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_227_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un10_bg_030_0_i "state_machine.un10_bg_030_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_AS_030_2_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_126_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_as_030_000_sync8_1_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_127_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_5_0_i "state_machine.UDS_000_INT_5_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_5_0_i "state_machine.LDS_000_INT_5_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un23_clk_000_d0 "state_machine.un23_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_r "VPA_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_m "VPA_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_n "VPA_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VPA_SYNC_0_p "VPA_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_r "A0_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A0_DMA_0_m "A0_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_n "A0_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A0_DMA_0_p "A0_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_228_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DTACK_SYNC_0_r "DTACK_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DTACK_SYNC_0_m "DTACK_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DTACK_SYNC_0_n "DTACK_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DTACK_SYNC_0_p "DTACK_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_r "FPU_CS_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_m "FPU_CS_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_n "FPU_CS_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename FPU_CS_INT_0_p "FPU_CS_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_r "DS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance CLK_000_D6_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un6_clk_000_d5 "state_machine.un6_clk_000_d5") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_dtack_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_D2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance SIZE_DMA_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__r "SIZE_DMA_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__m "SIZE_DMA_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__n "SIZE_DMA_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_1__p "SIZE_DMA_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance SIZE_DMA_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__r "SIZE_DMA_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__m "SIZE_DMA_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__n "SIZE_DMA_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_0_0__p "SIZE_DMA_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_223_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_p "DSACK1_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_224_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a2_3 "SM_AMIGA_ns_i_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a2_2 "SM_AMIGA_ns_i_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_clk_000_d2_i "state_machine.un8_clk_000_d2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a2_0_1 "SM_AMIGA_ns_i_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a2_1 "SM_AMIGA_ns_i_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_030_000_sync8_1_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance SIZE_DMA_0_sqmuxa_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_DSACK1_INT_0_sqmuxa_i_o2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_154 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_INT_1_sqmuxa_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance SIZE_DMA_0_sqmuxa_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_as_000_dma5_0_a2_0_0 "un1_as_000_dma5_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_0_sqmuxa_3_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_A0_DMA_4_0_a2_1 "state_machine.A0_DMA_4_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a2_0_0 "SM_AMIGA_ns_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a2_0 "SM_AMIGA_ns_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance RW_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_6 "SM_AMIGA_ns_i_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_7 "SM_AMIGA_ns_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_i_0_3 "cpu_est_ns_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i "state_machine.AMIGA_BUS_ENABLE_3_f0_i") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance cpu_estse_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_DS_000_DMA_5_iv_0_a2 "state_machine.DS_000_DMA_5_iv_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a2_0_7 "SM_AMIGA_ns_0_a2_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a2_7 "SM_AMIGA_ns_0_a2[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_i_a2_0_6 "SM_AMIGA_ns_i_i_a2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_i_a2_6 "SM_AMIGA_ns_i_i_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_a2_5 "SM_AMIGA_ns_0_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_3 "SM_AMIGA_ns_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_2 "SM_AMIGA_ns_i_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_1 "SM_AMIGA_ns_i_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_LDS_000_INT_5_0 "state_machine.LDS_000_INT_5_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_5_0 "state_machine.UDS_000_INT_5_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_000_SYNC_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_as_030_000_sync8_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_SYNC_1_sqmuxa_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_AS_030_2_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_bg_030_0 "state_machine.un10_bg_030_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_155 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_156 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_DATA_DIR_m1_0_x2 "AMIGA_BUS_DATA_DIR.m1_0_x2") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_o2_1 "SM_AMIGA_ns_i_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_UDS_000_INT_5_0_o2 "state_machine.UDS_000_INT_5_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_i_o2_6 "SM_AMIGA_ns_i_i_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename un1_as_000_dma5_0_o2_0 "un1_as_000_dma5_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_0_sqmuxa_3_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename clk_un3_clk_000_d1_0_o2 "clk.un3_clk_000_d1_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_92_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_UDS_000_INT_5_0_m2_r "state_machine.UDS_000_INT_5_0_m2.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename state_machine_UDS_000_INT_5_0_m2_m "state_machine.UDS_000_INT_5_0_m2.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_UDS_000_INT_5_0_m2_n "state_machine.UDS_000_INT_5_0_m2.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename state_machine_UDS_000_INT_5_0_m2_p "state_machine.UDS_000_INT_5_0_m2.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_89_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DSACK_INT_1_sqmuxa_i_o3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename clk_un3_clk_000_d1_0_o2 "clk.un3_clk_000_d1_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2 "state_machine.AMIGA_BUS_ENABLE_3_f0_i_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un6_clk_000_d5_i "state_machine.un6_clk_000_d5_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un10_bg_030_0 "state_machine.un10_bg_030_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_as_030_3_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un15_clk_000_d0_0 "state_machine.un15_clk_000_d0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance VPA_SYNC_1_sqmuxa_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_as_030_000_sync8_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance DTACK_SYNC_1_sqmuxa_1_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_000_SYNC_1_sqmuxa_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_UDS_000_INT_5_0 "state_machine.UDS_000_INT_5_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_LDS_000_INT_5_0 "state_machine.LDS_000_INT_5_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_1 "SM_AMIGA_ns_i_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_2 "SM_AMIGA_ns_i_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_3 "SM_AMIGA_ns_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_DS_000_DMA_5_iv_0 "state_machine.DS_000_DMA_5_iv_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_7 "SM_AMIGA_ns_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_i_6 "SM_AMIGA_ns_i_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename SM_AMIGA_ns_i_0_4 "SM_AMIGA_ns_i_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_a3_2 "cpu_est_ns_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_a3_0_2 "cpu_est_ns_0_0_a3_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_a3_1_2 "cpu_est_ns_0_0_a3_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_0 "SM_AMIGA_ns_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_0_0 "SM_AMIGA_ns_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance cpu_estse_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance cpu_estse_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_0_3 "cpu_est_ns_i_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_2 "cpu_est_ns_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance cpu_estse_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_0_o2_3 "cpu_est_ns_i_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_o2_4 "SM_AMIGA_ns_i_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_x2_1 "cpu_est_ns_0_0_x2[1]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_a2_1 "cpu_est_ns_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_m2_2__r "cpu_est_ns_0_0_m2_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_m2_2__m "cpu_est_ns_0_0_m2_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_m2_2__n "cpu_est_ns_0_0_m2_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_m2_2__p "cpu_est_ns_0_0_m2_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_SYNC_1_sqmuxa_1_i_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_157 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_158 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_159 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a2_4 "SM_AMIGA_ns_i_0_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_a2_0_4 "SM_AMIGA_ns_i_0_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_ns_i_0_a2_3 "cpu_est_ns_i_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_a2_2 "cpu_est_ns_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance cpu_estse_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance cpu_estse_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_0_0_a2_1 "cpu_est_ns_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_ns_i_0_a2_0_3 "cpu_est_ns_i_0_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename cpu_est_ns_0_0_a2_0_1 "cpu_est_ns_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a2_0 "SM_AMIGA_ns_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a2_4 "SM_AMIGA_ns_i_0_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a3_3 "SM_AMIGA_ns_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a3_4 "SM_AMIGA_ns_i_0_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_5 "SM_AMIGA_ns_0_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_0_5 "SM_AMIGA_ns_0_a3_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a3_6 "SM_AMIGA_ns_i_0_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a3_0_6 "SM_AMIGA_ns_i_0_a3_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_0_a3_7 "SM_AMIGA_ns_0_a3[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_a3_1 "cpu_est_ns_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename cpu_est_ns_0_0_a3_0_1 "cpu_est_ns_0_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename cpu_est_ns_i_0_a3_3 "cpu_est_ns_i_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AMIGA_BUS_ENABLE_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance G_102 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance G_108 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) - (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance un1_dtack_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance AS_000_INT_1_sqmuxa_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance I_128 (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un7_as_000_int_0_a3 "state_machine.un7_as_000_int_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance un1_as_030_000_sync8_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename A_i_0 "A_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SIZE_i_1 "SIZE_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a3_1 "SM_AMIGA_ns_i_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename state_machine_un8_clk_000_d2_i "state_machine.un8_clk_000_d2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a3_0_1 "SM_AMIGA_ns_i_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename SM_AMIGA_ns_i_0_a3_2 "SM_AMIGA_ns_i_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un15_clk_000_d0_0 "state_machine.un15_clk_000_d0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) ) @@ -513,36 +606,21 @@ (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance CLK_000_D2_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un7_as_000_int_i "state_machine.un7_as_000_int_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_103 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_109 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) (instance (rename un4_clk_cnt_n_i_1 "un4_clk_cnt_n_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance CLK_OSZI_i (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename un2_clk_cnt_p_i_1 "un2_clk_cnt_p_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance N_74_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_r "VPA_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_m "VPA_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_n "VPA_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename VPA_SYNC_0_p "VPA_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance FPU_CS_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename clk_un12_clk_cnt_p "clk.un12_clk_cnt_p") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_0_r "AMIGA_BUS_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_0_m "AMIGA_BUS_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_0_n "AMIGA_BUS_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_0_p "AMIGA_BUS_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) @@ -567,53 +645,23 @@ (instance (rename cpu_estse_2_m "cpu_estse_2.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_estse_2_n "cpu_estse_2.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) (instance (rename cpu_estse_2_p "cpu_estse_2.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename state_machine_un23_clk_000_d0 "state_machine.un23_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance CLK_000_D6_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename state_machine_un6_clk_000_d5 "state_machine.un6_clk_000_d5") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance FPU_CS_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename clk_un12_clk_cnt_p "clk.un12_clk_cnt_p") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance N_78_i (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DTACK_SYNC_0_r "DTACK_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DTACK_SYNC_0_m "DTACK_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DTACK_SYNC_0_n "DTACK_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DTACK_SYNC_0_p "DTACK_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_r "FPU_CS_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_m "FPU_CS_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_n "FPU_CS_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename FPU_CS_INT_0_p "FPU_CS_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__r "DSACK_INT_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__m "DSACK_INT_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__n "DSACK_INT_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename DSACK_INT_0_1__p "DSACK_INT_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_0_r "AMIGA_BUS_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_0_m "AMIGA_BUS_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_0_n "AMIGA_BUS_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename AMIGA_BUS_ENABLE_0_p "AMIGA_BUS_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) - (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) (net BGACK_030_INT (joined (portRef Q (instanceRef BGACK_030_INT)) - (portRef I0 (instanceRef BGACK_030_INT_0_n)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_m1_0_x2)) + (portRef I0 (instanceRef state_machine_A0_DMA_4_0_a2_1)) (portRef I0 (instanceRef BGACK_030_INT_i)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0_a2_0)) + (portRef I0 (instanceRef BGACK_030_INT_0_n)) (portRef OE (instanceRef AS_000)) (portRef I0 (instanceRef BGACK_030)) + (portRef D (instanceRef BGACK_030_INT_D)) (portRef OE (instanceRef LDS_000)) (portRef OE (instanceRef UDS_000)) )) (net FPU_CS_INT (joined (portRef Q (instanceRef FPU_CS_INT)) - (portRef I0 (instanceRef FPU_CS_INT_0_n)) (portRef I0 (instanceRef FPU_CS_INT_i)) + (portRef I0 (instanceRef FPU_CS_INT_0_n)) (portRef I0 (instanceRef FPU_CS)) )) (net VMA_INT (joined @@ -622,42 +670,35 @@ (portRef I0 (instanceRef VMA_INT_i)) (portRef I0 (instanceRef VMA)) )) - (net AS_000_INT (joined - (portRef Q (instanceRef AS_000_INT)) - (portRef I0 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef N_89_i_0_o2)) - (portRef I0 (instanceRef AS_000_INT_i)) - (portRef I0 (instanceRef AS_000)) - )) (net AS_030_000_SYNC (joined (portRef Q (instanceRef AS_030_000_SYNC)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) (portRef I0 (instanceRef AS_030_000_SYNC_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) + )) + (net BGACK_030_INT_D (joined + (portRef Q (instanceRef BGACK_030_INT_D)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0_o2)) + (portRef I1 (instanceRef state_machine_A0_DMA_4_0_a2_1)) + (portRef I0 (instanceRef BGACK_030_INT_D_i)) )) (net DTACK_SYNC (joined (portRef Q (instanceRef DTACK_SYNC)) (portRef I0 (instanceRef DTACK_SYNC_0_n)) (portRef I0 (instanceRef state_machine_un23_clk_000_d0)) )) - (net VPA_D (joined - (portRef Q (instanceRef VPA_D)) - (portRef I0 (instanceRef VPA_D_i)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_2)) - )) (net VPA_SYNC (joined (portRef Q (instanceRef VPA_SYNC)) - (portRef I1 (instanceRef state_machine_un23_clk_000_d0)) (portRef I0 (instanceRef VPA_SYNC_0_n)) + (portRef I1 (instanceRef state_machine_un23_clk_000_d0)) )) (net CLK_000_D0 (joined (portRef Q (instanceRef CLK_000_D0)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_2)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a2_1)) + (portRef I1 (instanceRef N_92_i_0_o2)) (portRef I0 (instanceRef clk_un3_clk_000_d1_0_o2)) - (portRef I1 (instanceRef N_89_i_0_o2)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_2)) (portRef I0 (instanceRef CLK_000_D0_i)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_1)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_i_a2_0_6)) (portRef D (instanceRef CLK_000_D1)) )) (net CLK_000_D1 (joined @@ -676,24 +717,31 @@ )) (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined (portRef Q (instanceRef SM_AMIGA_5)) - (portRef I0 (instanceRef SM_AMIGA_i_5)) (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_m2_m)) - )) - (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined - (portRef Q (instanceRef SM_AMIGA_6)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a2_0)) - (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2)) - (portRef I0 (instanceRef SM_AMIGA_i_6)) + (portRef I0 (instanceRef SM_AMIGA_i_5)) )) (net VCC (joined (portRef I0 (instanceRef AMIGA_BUS_ENABLE_LOW)) (portRef I0 (instanceRef AVEC)) - (portRef I0 (instanceRef DSACK_0)) (portRef D (instanceRef RESETDFFRH)) )) (net GND (joined (portRef I0 (instanceRef AVEC_EXP)) (portRef I0 (instanceRef BERR)) + (portRef I0 (instanceRef DSACK_0)) + (portRef OE (instanceRef DSACK_0)) + )) + (net AS_000_INT (joined + (portRef Q (instanceRef AS_000_INT)) + (portRef I0 (instanceRef N_92_i_0_o2)) + (portRef I0 (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000)) + )) + (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined + (portRef Q (instanceRef SM_AMIGA_6)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_3_i_o2)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a2_0_0)) + (portRef I0 (instanceRef SM_AMIGA_i_6)) )) (net UDS_000_INT (joined (portRef Q (instanceRef UDS_000_INT)) @@ -705,165 +753,150 @@ (portRef I0 (instanceRef LDS_000_INT_0_n)) (portRef I0 (instanceRef LDS_000)) )) - (net (rename DSACK_INT_1 "DSACK_INT[1]") (joined - (portRef Q (instanceRef DSACK_INT_1)) - (portRef I0 (instanceRef DSACK_INT_0_1__n)) + (net DSACK1_INT (joined + (portRef Q (instanceRef DSACK1_INT)) + (portRef I0 (instanceRef DSACK1_INT_0_n)) (portRef I0 (instanceRef DSACK_1)) )) - (net AS_000_INT_1_sqmuxa (joined - (portRef O (instanceRef AS_000_INT_1_sqmuxa_0_a3)) - (portRef I1 (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_r)) - )) - (net (rename state_machine_un8_clk_000_d2 "state_machine.un8_clk_000_d2") (joined - (portRef O (instanceRef state_machine_un8_clk_000_d2)) - (portRef I0 (instanceRef state_machine_un8_clk_000_d2_i)) - )) (net CLK_000_D3 (joined (portRef Q (instanceRef CLK_000_D3)) (portRef I0 (instanceRef state_machine_un8_clk_000_d2_1)) (portRef D (instanceRef CLK_000_D4)) )) - (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined - (portRef Q (instanceRef SM_AMIGA_4)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_m2_n)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_o2_4)) - (portRef I0 (instanceRef SM_AMIGA_i_4)) - )) (net (rename state_machine_un23_clk_000_d0 "state_machine.un23_clk_000_d0") (joined (portRef O (instanceRef state_machine_un23_clk_000_d0_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a2_4)) - )) - (net (rename state_machine_un6_clk_000_d5 "state_machine.un6_clk_000_d5") (joined - (portRef O (instanceRef state_machine_un6_clk_000_d5)) - (portRef I0 (instanceRef state_machine_un6_clk_000_d5_i)) - (portRef I1 (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_o2)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a2_0_5)) )) (net CLK_000_D5 (joined (portRef Q (instanceRef CLK_000_D5)) (portRef I0 (instanceRef state_machine_un6_clk_000_d5)) (portRef D (instanceRef CLK_000_D6)) )) - (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined - (portRef Q (instanceRef SM_AMIGA_7)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_0_1)) - (portRef I0 (instanceRef SM_AMIGA_i_7)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_2)) - (portRef I0 (instanceRef state_machine_un10_bg_030_0_a3_2)) - )) (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined (portRef Q (instanceRef SM_AMIGA_3)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_5)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a2_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_4)) (portRef I0 (instanceRef SM_AMIGA_i_3)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a2_0_1_5)) )) - (net (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (joined - (portRef O (instanceRef state_machine_un6_bgack_000_0_i)) - (portRef I1 (instanceRef BGACK_030_INT_0_m)) - (portRef I0 (instanceRef BGACK_030_INT_0_r)) + (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined + (portRef Q (instanceRef SM_AMIGA_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a2_7)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_3_i_a2)) )) (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined (portRef Q (instanceRef SM_AMIGA_1)) - (portRef I0 (instanceRef SM_AMIGA_i_1)) - (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_o2)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_1_7)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_i_a2_6)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a2_0_7)) + (portRef I0 (instanceRef un1_DSACK1_INT_0_sqmuxa_i_o2_i_a2)) )) - (net DTACK_DMA (joined - (portRef Q (instanceRef DTACK_DMA)) - (portRef I0 (instanceRef DTACK)) + (net AS_000_DMA (joined + (portRef Q (instanceRef AS_000_DMA)) + (portRef I0 (instanceRef state_machine_DS_000_DMA_5_iv_0_a2)) + (portRef I0 (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_030)) + )) + (net DS_000_DMA (joined + (portRef Q (instanceRef DS_000_DMA)) + (portRef I0 (instanceRef DS_000_DMA_0_m)) + (portRef I0 (instanceRef DS_030)) + )) + (net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined + (portRef Q (instanceRef SIZE_DMA_0)) + (portRef I0 (instanceRef SIZE_DMA_0_0__m)) + (portRef I0 (instanceRef SIZE_0)) + )) + (net (rename SIZE_DMA_1 "SIZE_DMA[1]") (joined + (portRef Q (instanceRef SIZE_DMA_1)) + (portRef I0 (instanceRef SIZE_DMA_0_1__m)) + (portRef I0 (instanceRef SIZE_1)) + )) + (net A0_DMA (joined + (portRef Q (instanceRef A0_DMA)) + (portRef I0 (instanceRef A0_DMA_0_m)) + (portRef I0 (instanceRef A0)) )) (net (rename un4_clk_cnt_n_1 "un4_clk_cnt_n[1]") (joined - (portRef O (instanceRef G_102)) + (portRef O (instanceRef G_103)) (portRef I1 (instanceRef clk_un12_clk_cnt_p)) (portRef I0 (instanceRef un4_clk_cnt_n_i_1)) )) (net (rename CLK_CNT_N_0 "CLK_CNT_N[0]") (joined (portRef Q (instanceRef CLK_CNT_N_0)) - (portRef I0 (instanceRef G_102)) + (portRef I0 (instanceRef G_103)) (portRef D (instanceRef CLK_CNT_N_1)) )) (net (rename CLK_CNT_N_1 "CLK_CNT_N[1]") (joined (portRef Q (instanceRef CLK_CNT_N_1)) - (portRef I1 (instanceRef G_102)) + (portRef I1 (instanceRef G_103)) )) (net (rename un2_clk_cnt_p_1 "un2_clk_cnt_p[1]") (joined - (portRef O (instanceRef G_108)) + (portRef O (instanceRef G_109)) (portRef I0 (instanceRef clk_un12_clk_cnt_p)) (portRef I0 (instanceRef un2_clk_cnt_p_i_1)) )) (net (rename CLK_CNT_P_0 "CLK_CNT_P[0]") (joined (portRef Q (instanceRef CLK_CNT_P_0)) - (portRef I0 (instanceRef G_108)) + (portRef I0 (instanceRef G_109)) (portRef D (instanceRef CLK_CNT_P_1)) )) (net (rename CLK_CNT_P_1 "CLK_CNT_P[1]") (joined (portRef Q (instanceRef CLK_CNT_P_1)) - (portRef I1 (instanceRef G_108)) - )) - (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined - (portRef Q (instanceRef SM_AMIGA_2)) - (portRef I0 (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_5)) - )) - (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined - (portRef Q (instanceRef SM_AMIGA_0)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_7)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_0)) - )) - (net (rename state_machine_un10_bg_030 "state_machine.un10_bg_030") (joined - (portRef O (instanceRef state_machine_un10_bg_030_0_i)) - (portRef I1 (instanceRef BG_000_0_m)) - (portRef I0 (instanceRef BG_000_0_r)) - )) - (net (rename state_machine_un7_as_000_int "state_machine.un7_as_000_int") (joined - (portRef O (instanceRef state_machine_un7_as_000_int_0_a3)) - (portRef I0 (instanceRef state_machine_un7_as_000_int_i)) + (portRef I1 (instanceRef G_109)) )) (net CLK_000_D4 (joined (portRef Q (instanceRef CLK_000_D4)) (portRef D (instanceRef CLK_000_D5)) )) + (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined + (portRef Q (instanceRef SM_AMIGA_7)) + (portRef I0 (instanceRef SM_AMIGA_i_7)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a2_0_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a2_2)) + (portRef I0 (instanceRef state_machine_un10_bg_030_0_a2_2)) + )) (net (rename state_machine_un15_clk_000_d0 "state_machine.un15_clk_000_d0") (joined (portRef O (instanceRef state_machine_un15_clk_000_d0_0_i)) (portRef I1 (instanceRef VMA_INT_0_m)) (portRef I0 (instanceRef VMA_INT_0_r)) )) - (net (rename state_machine_LDS_000_INT_5 "state_machine.LDS_000_INT_5") (joined - (portRef O (instanceRef state_machine_LDS_000_INT_5_0_i)) - (portRef I0 (instanceRef LDS_000_INT_0_m)) + (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined + (portRef Q (instanceRef SM_AMIGA_4)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_m2_n)) + (portRef I0 (instanceRef SM_AMIGA_i_4)) )) - (net (rename state_machine_UDS_000_INT_5 "state_machine.UDS_000_INT_5") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_5_0_i)) - (portRef I0 (instanceRef UDS_000_INT_0_m)) - )) - (net un1_AMIGA_BUS_ENABLE_1_sqmuxa_2 (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3_i)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) + (net un1_AMIGA_BUS_ENABLE_0_sqmuxa_2 (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_m)) )) (net CLK_OUT_PRE (joined (portRef Q (instanceRef CLK_OUT_PRE)) (portRef D (instanceRef CLK_OUT_INT)) )) + (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined + (portRef Q (instanceRef SM_AMIGA_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a2_5)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_i_a2_0_6)) + )) (net N_1 (joined (portRef O (instanceRef AS_030_000_SYNC_0_p)) (portRef D (instanceRef AS_030_000_SYNC)) )) (net N_2 (joined - (portRef O (instanceRef DTACK_SYNC_0_p)) - (portRef D (instanceRef DTACK_SYNC)) + (portRef O (instanceRef DS_000_DMA_0_p)) + (portRef D (instanceRef DS_000_DMA)) )) (net N_3 (joined (portRef O (instanceRef FPU_CS_INT_0_p)) (portRef D (instanceRef FPU_CS_INT)) )) (net N_4 (joined - (portRef O (instanceRef DSACK_INT_0_1__p)) - (portRef D (instanceRef DSACK_INT_1)) + (portRef O (instanceRef SIZE_DMA_0_0__p)) + (portRef D (instanceRef SIZE_DMA_0)) )) (net N_5 (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_0_p)) - (portRef D (instanceRef AMIGA_BUS_ENABLEDFF)) + (portRef O (instanceRef SIZE_DMA_0_1__p)) + (portRef D (instanceRef SIZE_DMA_1)) )) (net N_6 (joined (portRef O (instanceRef UDS_000_INT_0_p)) @@ -874,34 +907,54 @@ (portRef D (instanceRef LDS_000_INT)) )) (net N_8 (joined - (portRef O (instanceRef VPA_SYNC_0_p)) - (portRef D (instanceRef VPA_SYNC)) + (portRef O (instanceRef DTACK_SYNC_0_p)) + (portRef D (instanceRef DTACK_SYNC)) )) (net N_9 (joined - (portRef O (instanceRef VMA_INT_0_p)) - (portRef D (instanceRef VMA_INT)) + (portRef O (instanceRef A0_DMA_0_p)) + (portRef D (instanceRef A0_DMA)) )) (net N_10 (joined (portRef O (instanceRef BG_000_0_p)) (portRef D (instanceRef BG_000DFFSH)) )) (net N_11 (joined - (portRef O (instanceRef BGACK_030_INT_0_p)) - (portRef D (instanceRef BGACK_030_INT)) + (portRef O (instanceRef AS_000_DMA_0_p)) + (portRef D (instanceRef AS_000_DMA)) )) (net N_12 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_0_p)) + (portRef D (instanceRef AMIGA_BUS_ENABLEDFFSH)) + )) + (net N_13 (joined (portRef O (instanceRef AS_000_INT_0_p)) (portRef D (instanceRef AS_000_INT)) )) - (net N_13 (joined + (net N_14 (joined + (portRef O (instanceRef VPA_SYNC_0_p)) + (portRef D (instanceRef VPA_SYNC)) + )) + (net N_15 (joined + (portRef O (instanceRef DSACK1_INT_0_p)) + (portRef D (instanceRef DSACK1_INT)) + )) + (net N_16 (joined + (portRef O (instanceRef VMA_INT_0_p)) + (portRef D (instanceRef VMA_INT)) + )) + (net N_17 (joined + (portRef O (instanceRef BGACK_030_INT_0_p)) + (portRef D (instanceRef BGACK_030_INT)) + )) + (net N_18 (joined (portRef O (instanceRef IPL_030_0_0__p)) (portRef D (instanceRef IPL_030DFFSH_0)) )) - (net N_14 (joined + (net N_19 (joined (portRef O (instanceRef IPL_030_0_1__p)) (portRef D (instanceRef IPL_030DFFSH_1)) )) - (net N_15 (joined + (net N_20 (joined (portRef O (instanceRef IPL_030_0_2__p)) (portRef D (instanceRef IPL_030DFFSH_2)) )) @@ -920,31 +973,31 @@ (net (rename cpu_est_0 "cpu_est[0]") (joined (portRef Q (instanceRef cpu_est_0)) (portRef I0 (instanceRef cpu_est_ns_0_0_a2_0_1)) + (portRef I1 (instanceRef cpu_estse_0_a2)) + (portRef I0 (instanceRef cpu_est_ns_0_0_a2_2)) (portRef I0 (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef cpu_estse_0_a3)) - (portRef I0 (instanceRef cpu_est_ns_0_0_a3_1_2)) )) (net (rename cpu_est_1 "cpu_est[1]") (joined (portRef Q (instanceRef cpu_est_1)) (portRef I0 (instanceRef cpu_estse_0_m)) (portRef I0 (instanceRef cpu_est_i_1)) (portRef I0 (instanceRef cpu_est_ns_0_0_a2_1)) - (portRef I0 (instanceRef cpu_est_ns_0_0_a3_2)) + (portRef I1 (instanceRef cpu_est_ns_0_0_m2_2__m)) + (portRef I0 (instanceRef cpu_est_ns_0_0_m2_2__r)) )) (net (rename cpu_est_2 "cpu_est[2]") (joined (portRef Q (instanceRef cpu_est_2)) (portRef I0 (instanceRef cpu_estse_1_m)) - (portRef I1 (instanceRef cpu_est_ns_i_0_a3_3)) - (portRef I0 (instanceRef cpu_est_i_2)) - (portRef I0 (instanceRef cpu_est_ns_0_0_a3_1)) - (portRef I1 (instanceRef cpu_est_ns_0_0_a3_2)) - (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3_0)) + (portRef I1 (instanceRef cpu_est_ns_i_0_a2_3)) + (portRef I0 (instanceRef cpu_est_ns_0_0_m2_2__m)) + (portRef I0 (instanceRef cpu_est_ns_0_0_x2_1)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a2_0)) )) (net (rename cpu_est_3 "cpu_est[3]") (joined (portRef Q (instanceRef cpu_est_3)) (portRef I0 (instanceRef cpu_estse_2_m)) - (portRef I1 (instanceRef cpu_est_ns_0_0_a3_1)) - (portRef I1 (instanceRef cpu_est_ns_0_0_a3_1_2)) + (portRef I1 (instanceRef cpu_est_ns_0_0_a2_2)) + (portRef I1 (instanceRef cpu_est_ns_0_0_x2_1)) (portRef I0 (instanceRef cpu_est_ns_i_0_o2_3)) (portRef I0 (instanceRef cpu_est_i_3)) (portRef I0 (instanceRef E)) @@ -973,47 +1026,25 @@ (portRef O (instanceRef cpu_est_ns_0_0_i_2)) (portRef I0 (instanceRef cpu_estse_1_n)) )) - (net N_204 (joined - (portRef O (instanceRef un1_as_030_3_i_i)) - (portRef I1 (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_r)) - (portRef I1 (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_r)) + (net N_46 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_i_i_6)) + (portRef D (instanceRef SM_AMIGA_1)) )) - (net N_205 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_i)) - (portRef I1 (instanceRef VPA_SYNC_0_m)) - (portRef I0 (instanceRef VPA_SYNC_0_r)) + (net N_52 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_3_i_i)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_r)) )) - (net N_206 (joined - (portRef O (instanceRef un1_as_030_000_sync8_i_i)) - (portRef I1 (instanceRef FPU_CS_INT_0_m)) - (portRef I0 (instanceRef FPU_CS_INT_0_r)) + (net N_59 (joined + (portRef O (instanceRef N_92_i_0_o2_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a2_7)) )) - (net N_26 (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i_i)) - (portRef I1 (instanceRef DTACK_SYNC_0_m)) - (portRef I0 (instanceRef DTACK_SYNC_0_r)) + (net N_62 (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0_o2_i)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0_a2)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_3_i_1)) )) - (net N_30 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_i)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) - )) - (net N_49 (joined - (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_p)) - (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0_o3)) - )) - (net N_50 (joined - (portRef O (instanceRef N_89_i_0_o2_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_7)) - )) - (net N_51 (joined - (portRef O (instanceRef DSACK_INT_1_sqmuxa_i_o3_i)) - (portRef I1 (instanceRef DSACK_INT_0_1__m)) - (portRef I0 (instanceRef DSACK_INT_0_1__r)) - )) - (net N_54 (joined + (net N_65 (joined (portRef O (instanceRef clk_un3_clk_000_d1_0_o2_i)) (portRef I1 (instanceRef cpu_estse_2_m)) (portRef I0 (instanceRef cpu_estse_2_r)) @@ -1027,344 +1058,492 @@ (portRef I0 (instanceRef IPL_030_0_1__r)) (portRef I1 (instanceRef IPL_030_0_0__m)) (portRef I0 (instanceRef IPL_030_0_0__r)) - (portRef I0 (instanceRef cpu_estse_0_a3)) + (portRef I0 (instanceRef cpu_estse_0_a2)) (portRef I1 (instanceRef state_machine_un6_bgack_000_0)) )) - (net N_55 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_i)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_1)) - )) - (net N_56 (joined - (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2_i)) - (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i)) - )) - (net N_57 (joined - (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_o2_i)) - (portRef I0 (instanceRef DSACK_INT_0_1__m)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_6)) - (portRef I1 (instanceRef DSACK_INT_1_sqmuxa_i_o3)) - )) - (net N_59 (joined - (portRef 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(net N_133 (joined + (net N_135 (joined (portRef O (instanceRef SM_AMIGA_ns_i_0_a2_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_5)) - (portRef I0 (instanceRef N_133_i)) + (portRef I0 (instanceRef N_135_i)) )) - (net N_236 (joined - (portRef O (instanceRef un8_ciin)) - (portRef OE (instanceRef CIIN)) + (net N_136 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_a2_0_4)) + (portRef I0 (instanceRef N_136_i)) )) - (net N_239 (joined + (net N_138 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a2_0_5)) + (portRef I0 (instanceRef N_138_i)) + )) + (net N_143 (joined + (portRef O (instanceRef cpu_est_ns_i_0_a2_3)) + (portRef I0 (instanceRef N_143_i)) + )) + (net N_145 (joined + (portRef O (instanceRef cpu_est_ns_0_0_a2_2)) + (portRef I0 (instanceRef N_145_i)) + )) + (net N_146 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a2_0)) + (portRef I0 (instanceRef N_146_i)) + )) + (net N_147 (joined + (portRef O (instanceRef cpu_estse_0_a2)) + (portRef I0 (instanceRef N_147_i)) + )) + (net N_148 (joined + (portRef O (instanceRef cpu_estse_0_a2_0)) + (portRef I0 (instanceRef N_148_i)) + )) + (net N_151 (joined + (portRef O (instanceRef SIZE_DMA_0_sqmuxa_0_a2_0)) + (portRef I0 (instanceRef un1_as_000_dma5_0_o2_0)) + (portRef I0 (instanceRef SIZE_DMA_0_sqmuxa_0_a2)) + (portRef I1 (instanceRef state_machine_A0_DMA_4_0_a2_1_0)) + (portRef I1 (instanceRef SIZE_DMA_1_sqmuxa_0_a2_1)) + )) + (net N_153 (joined + (portRef O (instanceRef cpu_est_ns_0_0_a2_1)) + (portRef I0 (instanceRef cpu_est_ns_i_0_a2_0_3)) + (portRef I0 (instanceRef N_153_i)) + )) + (net N_154 (joined + (portRef O (instanceRef cpu_est_ns_i_0_a2_0_3)) + (portRef I0 (instanceRef N_154_i)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a2_0_1)) + )) + (net N_155 (joined + (portRef O (instanceRef cpu_est_ns_0_0_a2_0_1)) + (portRef I0 (instanceRef N_155_i)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a2_1)) + )) + (net N_173 (joined + (portRef O (instanceRef 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+ (net N_227 (joined + (portRef O (instanceRef state_machine_un10_bg_030_0_a2)) + (portRef I0 (instanceRef N_227_i)) )) - (net VPA_D_i (joined - (portRef O (instanceRef VPA_D_i)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3)) - (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a3)) + (net N_228 (joined + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a2)) + (portRef I0 (instanceRef N_228_i)) )) - (net DTACK_i (joined - (portRef O (instanceRef I_127)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_1)) + (net N_127 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a2)) + (portRef I0 (instanceRef N_127_i)) )) - (net CLK_000_D0_i (joined - (portRef O (instanceRef CLK_000_D0_i)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_6)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_5)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a2_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_3)) - (portRef I0 (instanceRef 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(portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_0_6)) + (net N_75 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_o2_i_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a2_1)) )) - (net (rename state_machine_un6_clk_000_d5_i "state_machine.un6_clk_000_d5_i") (joined - (portRef O (instanceRef state_machine_un6_clk_000_d5_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_0_a3_0_7)) + (net un1_AMIGA_BUS_ENABLE_1_sqmuxa_4 (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_4_0_o2_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) )) - (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined - (portRef O (instanceRef SM_AMIGA_i_6)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_2)) - (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3)) + (net N_61 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_o2_i)) + (portRef I1 (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_0_r)) )) - (net nEXP_SPACE_i (joined - (portRef O (instanceRef nEXP_SPACE_i)) - (portRef I1 (instanceRef un1_dtack_i_a3)) + (net N_156 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a2_0_0)) (portRef I1 (instanceRef SM_AMIGA_ns_0_a2_0)) + (portRef I0 (instanceRef N_156_i)) )) - (net AS_000_INT_i (joined - (portRef O (instanceRef AS_000_INT_i)) - (portRef I0 (instanceRef state_machine_un7_as_000_int_0_a3)) + (net N_73 (joined + (portRef O (instanceRef state_machine_UDS_000_INT_5_0_o2_i)) + (portRef I1 (instanceRef un1_AS_030_2_i)) )) - (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined - (portRef O (instanceRef cpu_est_i_1)) - (portRef I1 (instanceRef cpu_est_ns_0_0_a2_0_1)) - (portRef I1 (instanceRef cpu_est_ns_0_0_a3_0_2)) - (portRef I1 (instanceRef cpu_est_ns_i_0_o2_3)) + (net N_57 (joined + (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_p)) + (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0_o2)) )) - (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined - (portRef O (instanceRef cpu_est_i_0)) - (portRef I1 (instanceRef cpu_est_ns_0_0_a2_1)) - (portRef I1 (instanceRef cpu_estse_0_a3_0)) - (portRef I0 (instanceRef cpu_est_ns_0_0_a3_0_2)) + (net N_71 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_i_o2_i_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_i_a2_6)) )) - (net AMIGA_BUS_ENABLE_i (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_i)) - (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1)) + (net (rename state_machine_un6_clk_000_d5 "state_machine.un6_clk_000_d5") (joined + (portRef O (instanceRef state_machine_un6_clk_000_d5)) + (portRef I1 (instanceRef un1_DSACK1_INT_0_sqmuxa_i_o2_i_a2)) + (portRef I0 (instanceRef state_machine_un6_clk_000_d5_i)) )) - (net AS_030_i (joined - (portRef O (instanceRef AS_030_i)) - (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_0_a3)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i)) - (portRef I0 (instanceRef un1_as_030_000_sync8_i)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i)) - (portRef I0 (instanceRef un1_as_030_3_i)) - (portRef I0 (instanceRef DSACK_INT_1_sqmuxa_i_o3)) - (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1)) + (net (rename un1_as_000_dma5_0 "un1_as_000_dma5[0]") (joined + (portRef O (instanceRef un1_as_000_dma5_0_o2_i_0)) + (portRef I0 (instanceRef AS_000_DMA_0_n)) )) - (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined - (portRef O (instanceRef cpu_est_i_2)) - (portRef I0 (instanceRef cpu_est_ns_0_0_a3_0_1)) + (net N_223 (joined + (portRef O (instanceRef un1_DSACK1_INT_0_sqmuxa_i_o2_i_a2)) + (portRef I0 (instanceRef N_223_i)) )) - (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined - (portRef O (instanceRef SM_AMIGA_i_2)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_0_6)) + (net (rename state_machine_DS_000_DMA_5 "state_machine.DS_000_DMA_5") (joined + (portRef O (instanceRef state_machine_DS_000_DMA_5_iv_0_i)) + (portRef I0 (instanceRef DS_000_DMA_0_n)) )) - (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined - (portRef O (instanceRef SM_AMIGA_i_3)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_4)) + (net N_144 (joined + (portRef O (instanceRef state_machine_DS_000_DMA_5_iv_0_a2)) + (portRef I0 (instanceRef N_144_i)) + )) + (net N_141 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a2_7)) + (portRef I0 (instanceRef N_141_i)) + )) + (net N_142 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a2_0_7)) + (portRef I0 (instanceRef N_142_i)) + )) + (net N_139 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_i_a2_6)) + (portRef I0 (instanceRef N_139_i)) + )) + (net N_140 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_i_a2_0_6)) + (portRef I0 (instanceRef N_140_i)) + )) + (net N_137 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a2_5)) + (portRef I0 (instanceRef N_137_i)) + )) + (net N_134 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_a2_3)) + (portRef I0 (instanceRef N_134_i)) + )) + (net N_133 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_a2_2)) + (portRef I0 (instanceRef N_133_i)) + )) + (net N_131 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_a2_1)) + (portRef I0 (instanceRef N_131_i)) + )) + (net (rename state_machine_LDS_000_INT_5 "state_machine.LDS_000_INT_5") (joined + (portRef O (instanceRef state_machine_LDS_000_INT_5_0_i)) + (portRef I0 (instanceRef LDS_000_INT_0_m)) + )) + (net (rename state_machine_UDS_000_INT_5 "state_machine.UDS_000_INT_5") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_5_0_i)) + (portRef I0 (instanceRef UDS_000_INT_0_m)) + )) + (net N_35 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_i)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_r)) + )) + (net N_33 (joined + (portRef O (instanceRef un1_as_030_000_sync8_1_i_i)) + (portRef I1 (instanceRef FPU_CS_INT_0_m)) + (portRef I0 (instanceRef FPU_CS_INT_0_r)) + )) + (net N_126 (joined + (portRef O (instanceRef un1_as_030_000_sync8_1_i_a2)) + (portRef I0 (instanceRef N_126_i)) + )) + (net N_216 (joined + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i_i)) + (portRef I1 (instanceRef DTACK_SYNC_0_m)) + (portRef I0 (instanceRef DTACK_SYNC_0_r)) + )) + (net N_215 (joined + (portRef O (instanceRef un1_AS_030_2_i_i)) + (portRef I1 (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_r)) + )) + (net (rename state_machine_un10_bg_030 "state_machine.un10_bg_030") (joined + (portRef O (instanceRef state_machine_un10_bg_030_0_i)) + (portRef I1 (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_r)) + )) + (net N_214 (joined + (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_i)) + (portRef I1 (instanceRef VPA_SYNC_0_m)) + (portRef I0 (instanceRef VPA_SYNC_0_r)) + )) + (net (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (joined + (portRef O (instanceRef state_machine_un6_bgack_000_0_i)) + (portRef I1 (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef BGACK_030_INT_0_r)) + )) + (net (rename state_machine_un8_clk_000_d2 "state_machine.un8_clk_000_d2") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d2)) + (portRef I0 (instanceRef state_machine_un8_clk_000_d2_i)) + )) + (net SIZE_DMA_1_sqmuxa (joined + (portRef O (instanceRef SIZE_DMA_1_sqmuxa_0_a2)) + (portRef I0 (instanceRef SIZE_DMA_1_sqmuxa_i)) + )) + (net SIZE_DMA_0_sqmuxa (joined + (portRef O (instanceRef SIZE_DMA_0_sqmuxa_0_a2)) + (portRef I0 (instanceRef SIZE_DMA_0_sqmuxa_i)) + )) + (net AS_000_INT_1_sqmuxa (joined + (portRef O (instanceRef AS_000_INT_1_sqmuxa_0_a2)) + (portRef I1 (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_r)) + )) + (net N_249 (joined + (portRef O (instanceRef state_machine_A0_DMA_4_0_a2_1)) + (portRef I1 (instanceRef SIZE_DMA_0_0__m)) + (portRef I0 (instanceRef SIZE_DMA_0_0__r)) + (portRef I1 (instanceRef SIZE_DMA_0_1__m)) + (portRef I0 (instanceRef SIZE_DMA_0_1__r)) + (portRef I1 (instanceRef DS_000_DMA_0_m)) + (portRef I0 (instanceRef DS_000_DMA_0_r)) + (portRef I1 (instanceRef A0_DMA_0_m)) + (portRef I0 (instanceRef A0_DMA_0_r)) + (portRef I1 (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_000_DMA_0_r)) + )) + (net CLK_000_D6_i (joined + (portRef O (instanceRef CLK_000_D6_i)) + (portRef I1 (instanceRef state_machine_un6_clk_000_d5)) + )) + (net N_228_i (joined + (portRef O (instanceRef N_228_i)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i)) + (portRef I0 (instanceRef DTACK_SYNC_0_m)) )) (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined (portRef O (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_0_a2)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a2_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a2_3)) (portRef I0 (instanceRef AS_000_INT_0_n)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a3_2)) - (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_0_a3)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_3)) )) - (net (rename state_machine_un8_clk_000_d2_i "state_machine.un8_clk_000_d2_i") (joined - (portRef O (instanceRef state_machine_un8_clk_000_d2_i)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_0_1)) + (net N_224_i (joined + (portRef O (instanceRef N_224_i)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i)) + (portRef I0 (instanceRef VPA_SYNC_0_m)) )) - (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined - (portRef O (instanceRef SM_AMIGA_i_7)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a3_1)) + (net N_223_i (joined + (portRef O (instanceRef N_223_i)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_o2)) + (portRef I0 (instanceRef DSACK1_INT_0_m)) )) - (net (rename A_i_0 "A_i[0]") (joined - (portRef O (instanceRef A_i_0)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_5_0_a3_1)) + (net SIZE_DMA_0_sqmuxa_i (joined + (portRef O (instanceRef SIZE_DMA_0_sqmuxa_i)) + (portRef I0 (instanceRef SIZE_DMA_0_0__n)) )) - (net (rename SIZE_i_1 "SIZE_i[1]") (joined - (portRef O (instanceRef SIZE_i_1)) - (portRef I1 (instanceRef state_machine_LDS_000_INT_5_0_a3)) + (net SIZE_DMA_1_sqmuxa_i (joined + (portRef O (instanceRef SIZE_DMA_1_sqmuxa_i)) + (portRef I0 (instanceRef SIZE_DMA_0_1__n)) )) - (net (rename DSACK_i_1 "DSACK_i[1]") (joined - (portRef O (instanceRef I_128)) - (portRef I1 (instanceRef state_machine_un7_as_000_int_0_a3)) + (net (rename A_i_18 "A_i[18]") (joined + (portRef O (instanceRef A_i_18)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_2)) )) - (net BGACK_030_INT_i (joined - (portRef O (instanceRef BGACK_030_INT_i)) - (portRef I0 (instanceRef un1_dtack_i_a3)) + (net (rename A_i_16 "A_i[16]") (joined + (portRef O (instanceRef A_i_16)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_2)) )) - (net CLK_000_D2_i (joined - (portRef O (instanceRef CLK_000_D2_i)) - (portRef I1 (instanceRef state_machine_un8_clk_000_d2)) + (net (rename A_i_19 "A_i[19]") (joined + (portRef O (instanceRef A_i_19)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_1)) )) (net AS_030_000_SYNC_i (joined (portRef O (instanceRef AS_030_000_SYNC_i)) (portRef I1 (instanceRef state_machine_un8_clk_000_d2_1)) )) - (net (rename A_i_19 "A_i[19]") (joined - (portRef O (instanceRef A_i_19)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_3)) + (net CLK_000_D2_i (joined + (portRef O (instanceRef CLK_000_D2_i)) + (portRef I1 (instanceRef state_machine_un8_clk_000_d2)) )) - (net (rename A_i_16 "A_i[16]") (joined - (portRef O (instanceRef A_i_16)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_3)) + (net BGACK_030_INT_i (joined + (portRef O (instanceRef BGACK_030_INT_i)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0_o2)) + (portRef I0 (instanceRef un1_dtack_i_a2)) + (portRef I1 (instanceRef SIZE_DMA_0_sqmuxa_0_a2_0)) )) - (net (rename A_i_18 "A_i[18]") (joined - (portRef O (instanceRef A_i_18)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5)) + (net nEXP_SPACE_i (joined + (portRef O (instanceRef nEXP_SPACE_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_a2_0_0)) + (portRef I1 (instanceRef un1_dtack_i_a2)) + )) + (net AS_030_i (joined + (portRef O (instanceRef I_154)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_o2)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i)) + (portRef I0 (instanceRef un1_AS_030_2_i)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i)) + (portRef I0 (instanceRef un1_as_030_000_sync8_1_i)) + (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_0_a2)) + )) + (net BGACK_030_INT_D_i (joined + (portRef O (instanceRef BGACK_030_INT_D_i)) + (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0_a2_0)) + )) + (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined + (portRef O (instanceRef SM_AMIGA_i_7)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a2_1)) + )) + (net (rename state_machine_un8_clk_000_d2_i "state_machine.un8_clk_000_d2_i") (joined + (portRef O (instanceRef state_machine_un8_clk_000_d2_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a2_0_1)) + )) + (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined + (portRef O (instanceRef SM_AMIGA_i_6)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a2_2)) + )) + (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined + (portRef O (instanceRef SM_AMIGA_i_4)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_a2_0_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a2_3)) + )) + (net CLK_000_D0_i (joined + (portRef O (instanceRef CLK_000_D0_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a2_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_i_o2_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a2_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a2_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a2_0_1_5)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a2_1)) + )) + (net RW_i (joined + (portRef O (instanceRef RW_i)) + (portRef I1 (instanceRef state_machine_DS_000_DMA_5_iv_0_a2)) + )) + (net UDS_000_i (joined + (portRef O (instanceRef I_155)) + (portRef I1 (instanceRef SIZE_DMA_0_sqmuxa_0_a2_1)) + )) + (net LDS_000_i (joined + (portRef O (instanceRef I_156)) + (portRef I0 (instanceRef SIZE_DMA_0_sqmuxa_0_a2_1)) + (portRef I0 (instanceRef state_machine_A0_DMA_4_0_a2_1_0)) + )) + (net DTACK_i (joined + (portRef O (instanceRef I_157)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a2_1)) + )) + (net VMA_INT_i (joined + (portRef O (instanceRef VMA_INT_i)) + (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a2_2)) + )) + (net VPA_i (joined + (portRef O (instanceRef VPA_i)) + (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a2_2)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0_a2)) + )) + (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined + (portRef O (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef cpu_est_ns_0_0_a2_1)) + (portRef I1 (instanceRef cpu_estse_0_a2_0)) + (portRef I0 (instanceRef cpu_est_ns_0_0_m2_2__n)) + )) + (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined + (portRef O (instanceRef SM_AMIGA_i_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_a2_0_4)) + )) + (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined + (portRef O (instanceRef cpu_est_i_3)) + (portRef I1 (instanceRef cpu_est_ns_i_0_a2_0_3)) + )) + (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined + (portRef O (instanceRef cpu_est_i_1)) + (portRef I1 (instanceRef cpu_est_ns_0_0_a2_0_1)) + (portRef I1 (instanceRef cpu_est_ns_i_0_o2_3)) + )) + (net A0_i (joined + (portRef O (instanceRef I_158)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0)) + (portRef I0 (instanceRef state_machine_LDS_000_INT_5_0_a2_1)) + )) + (net (rename SIZE_i_1 "SIZE_i[1]") (joined + (portRef O (instanceRef I_159)) + (portRef I1 (instanceRef state_machine_LDS_000_INT_5_0_a2)) )) (net (rename A_i_30 "A_i[30]") (joined (portRef O (instanceRef A_i_30)) @@ -1400,9 +1579,13 @@ )) (net RST_i (joined (portRef O (instanceRef RST_i)) + (portRef S (instanceRef A0_DMA)) + (portRef S (instanceRef AMIGA_BUS_ENABLEDFFSH)) + (portRef S (instanceRef AS_000_DMA)) (portRef S (instanceRef AS_000_INT)) (portRef S (instanceRef AS_030_000_SYNC)) (portRef S (instanceRef BGACK_030_INT)) + (portRef S (instanceRef BGACK_030_INT_D)) (portRef S (instanceRef BG_000DFFSH)) (portRef S (instanceRef CLK_000_D0)) (portRef S (instanceRef CLK_000_D1)) @@ -1417,8 +1600,8 @@ (portRef R (instanceRef CLK_CNT_P_1)) (portRef R (instanceRef CLK_OUT_INT)) (portRef R (instanceRef CLK_OUT_PRE)) - (portRef S (instanceRef DSACK_INT_1)) - (portRef S (instanceRef DTACK_DMA)) + (portRef S (instanceRef DSACK1_INT)) + (portRef S (instanceRef DS_000_DMA)) (portRef S (instanceRef DTACK_SYNC)) (portRef S (instanceRef FPU_CS_INT)) (portRef S (instanceRef IPL_030DFFSH_0)) @@ -1426,6 +1609,8 @@ (portRef S (instanceRef IPL_030DFFSH_2)) (portRef S (instanceRef LDS_000_INT)) (portRef R (instanceRef RESETDFFRH)) + (portRef S (instanceRef SIZE_DMA_0)) + (portRef S (instanceRef SIZE_DMA_1)) (portRef R (instanceRef SM_AMIGA_0)) (portRef R (instanceRef SM_AMIGA_1)) (portRef R (instanceRef SM_AMIGA_2)) @@ -1436,17 +1621,12 @@ (portRef S (instanceRef SM_AMIGA_7)) (portRef S (instanceRef UDS_000_INT)) (portRef S (instanceRef VMA_INT)) - (portRef S (instanceRef VPA_D)) (portRef S (instanceRef VPA_SYNC)) (portRef R (instanceRef cpu_est_0)) (portRef R (instanceRef cpu_est_1)) (portRef R (instanceRef cpu_est_2)) (portRef R (instanceRef cpu_est_3)) )) - (net (rename state_machine_un7_as_000_int_i "state_machine.un7_as_000_int_i") (joined - (portRef O (instanceRef state_machine_un7_as_000_int_i)) - (portRef D (instanceRef DTACK_DMA)) - )) (net (rename un2_clk_cnt_p_i_1 "un2_clk_cnt_p_i[1]") (joined (portRef O (instanceRef un2_clk_cnt_p_i_1)) (portRef D (instanceRef CLK_CNT_P_0)) @@ -1460,37 +1640,27 @@ (portRef O (instanceRef un4_clk_cnt_n_i_1)) (portRef D (instanceRef CLK_CNT_N_0)) )) - (net N_74_i (joined - (portRef O (instanceRef N_74_i)) - (portRef I0 (instanceRef VPA_SYNC_0_m)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i)) - )) - (net N_78_i (joined - (portRef O (instanceRef N_78_i)) - (portRef I0 (instanceRef DTACK_SYNC_0_m)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i)) - )) (net FPU_CS_INT_i (joined (portRef O (instanceRef FPU_CS_INT_i)) (portRef OE (instanceRef AVEC_EXP)) (portRef OE (instanceRef BERR)) )) - (net CLK_000_D6_i (joined - (portRef O (instanceRef CLK_000_D6_i)) - (portRef I1 (instanceRef state_machine_un6_clk_000_d5)) - )) (net AS_030_c (joined (portRef O (instanceRef AS_030)) + (portRef I0 (instanceRef I_154)) (portRef I0 (instanceRef FPU_CS_INT_0_m)) - (portRef I0 (instanceRef AS_030_i)) - (portRef I0 (instanceRef state_machine_un10_bg_030_0_a3_1)) + (portRef I0 (instanceRef state_machine_un10_bg_030_0_a2_1)) )) (net AS_030 (joined + (portRef IO (instanceRef AS_030)) (portRef AS_030) - (portRef I0 (instanceRef AS_030)) + )) + (net AS_000_c (joined + (portRef O (instanceRef AS_000)) + (portRef I0 (instanceRef AS_000_c_i)) )) (net AS_000 (joined - (portRef O (instanceRef AS_000)) + (portRef IO (instanceRef AS_000)) (portRef AS_000) )) (net DS_030_c (joined @@ -1498,85 +1668,43 @@ (portRef I0 (instanceRef DS_030_c_i)) )) (net DS_030 (joined + (portRef IO (instanceRef DS_030)) (portRef DS_030) - (portRef I0 (instanceRef DS_030)) + )) + (net UDS_000_c (joined + (portRef O (instanceRef UDS_000)) + (portRef I0 (instanceRef I_155)) + (portRef I1 (instanceRef un1_as_000_dma5_0_a2_0_0)) + (portRef I1 (instanceRef state_machine_A0_DMA_4_0_a2)) )) (net UDS_000 (joined - (portRef O (instanceRef UDS_000)) + (portRef IO (instanceRef UDS_000)) (portRef UDS_000) )) - (net LDS_000 (joined + (net LDS_000_c (joined (portRef O (instanceRef LDS_000)) + (portRef I0 (instanceRef I_156)) + (portRef I0 (instanceRef un1_as_000_dma5_0_a2_0_0)) + )) + (net LDS_000 (joined + (portRef IO (instanceRef LDS_000)) (portRef LDS_000) )) (net (rename SIZE_c_0 "SIZE_c[0]") (joined (portRef O (instanceRef SIZE_0)) - (portRef I1 (instanceRef state_machine_LDS_000_INT_5_0_a3_1)) + (portRef I1 (instanceRef state_machine_LDS_000_INT_5_0_a2_1)) )) (net (rename SIZE_0 "SIZE[0]") (joined + (portRef IO (instanceRef SIZE_0)) (portRef (member size 1)) - (portRef I0 (instanceRef SIZE_0)) )) (net (rename SIZE_c_1 "SIZE_c[1]") (joined (portRef O (instanceRef SIZE_1)) - (portRef I0 (instanceRef SIZE_i_1)) + (portRef I0 (instanceRef I_159)) )) (net (rename SIZE_1 "SIZE[1]") (joined (portRef (member size 0)) - (portRef I0 (instanceRef SIZE_1)) - )) - (net (rename A_c_0 "A_c[0]") (joined - (portRef O (instanceRef A_0)) - (portRef I0 (instanceRef A_i_0)) - )) - (net (rename A_0 "A[0]") (joined - (portRef (member a 31)) - (portRef I0 (instanceRef A_0)) - )) - (net (rename A_1 "A[1]") (joined - (portRef (member a 30)) - )) - (net (rename A_2 "A[2]") (joined - (portRef (member a 29)) - )) - (net (rename A_3 "A[3]") (joined - (portRef (member a 28)) - )) - (net (rename A_4 "A[4]") (joined - (portRef (member a 27)) - )) - (net (rename A_5 "A[5]") (joined - (portRef (member a 26)) - )) - (net (rename A_6 "A[6]") (joined - (portRef (member a 25)) - )) - (net (rename A_7 "A[7]") (joined - (portRef (member a 24)) - )) - (net (rename A_8 "A[8]") (joined - (portRef (member a 23)) - )) - (net (rename A_9 "A[9]") (joined - (portRef (member a 22)) - )) - (net (rename A_10 "A[10]") (joined - (portRef (member a 21)) - )) - (net (rename A_11 "A[11]") (joined - (portRef (member a 20)) - )) - (net (rename A_12 "A[12]") (joined - (portRef (member a 19)) - )) - (net (rename A_13 "A[13]") (joined - (portRef (member a 18)) - )) - (net (rename A_14 "A[14]") (joined - (portRef (member a 17)) - )) - (net (rename A_15 "A[15]") (joined - (portRef (member a 16)) + (portRef IO (instanceRef SIZE_1)) )) (net (rename A_c_16 "A_c[16]") (joined (portRef O (instanceRef A_16)) @@ -1588,7 +1716,7 @@ )) (net (rename A_c_17 "A_c[17]") (joined (portRef O (instanceRef A_17)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_3)) )) (net (rename A_17 "A[17]") (joined (portRef (member a 14)) @@ -1706,13 +1834,20 @@ (portRef (member a 0)) (portRef I0 (instanceRef A_31)) )) + (net A0_c (joined + (portRef O (instanceRef A0)) + (portRef I0 (instanceRef I_158)) + )) + (net A0 (joined + (portRef IO (instanceRef A0)) + (portRef A0) + )) (net nEXP_SPACE_c (joined (portRef O (instanceRef nEXP_SPACE)) - (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_sqmuxa_3_i_o2)) (portRef I0 (instanceRef nEXP_SPACE_i)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_2)) - (portRef I1 (instanceRef state_machine_un10_bg_030_0_a3_2)) - (portRef OE (instanceRef DSACK_0)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a2_2)) + (portRef I1 (instanceRef state_machine_un10_bg_030_0_a2_2)) (portRef OE (instanceRef DSACK_1)) )) (net nEXP_SPACE (joined @@ -1747,9 +1882,9 @@ )) (net BGACK_000_c (joined (portRef O (instanceRef BGACK_000)) - (portRef I0 (instanceRef BGACK_030_INT_0_m)) (portRef I0 (instanceRef state_machine_un6_bgack_000_0)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_1)) + (portRef I0 (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_1)) )) (net BGACK_000 (joined (portRef BGACK_000) @@ -1757,8 +1892,9 @@ )) (net CLK_030_c (joined (portRef O (instanceRef CLK_030)) - (portRef I0 (instanceRef un1_as_030_000_sync8_i_a3)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_1)) + (portRef I0 (instanceRef un1_as_030_000_sync8_1_i_a2)) + (portRef I0 (instanceRef CLK_030_c_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a2_1)) )) (net CLK_030 (joined (portRef CLK_030) @@ -1766,7 +1902,7 @@ )) (net CLK_000_c (joined (portRef O (instanceRef CLK_000)) - (portRef I1 (instanceRef state_machine_un10_bg_030_0_a3_1)) + (portRef I1 (instanceRef state_machine_un10_bg_030_0_a2_1)) (portRef D (instanceRef CLK_000_D0)) )) (net CLK_000 (joined @@ -1776,10 +1912,13 @@ (net CLK_OSZI_c (joined (portRef O (instanceRef CLK_OSZI)) (portRef I0 (instanceRef CLK_OSZI_i)) - (portRef CLK (instanceRef AMIGA_BUS_ENABLEDFF)) + (portRef CLK (instanceRef A0_DMA)) + (portRef CLK (instanceRef AMIGA_BUS_ENABLEDFFSH)) + (portRef CLK (instanceRef AS_000_DMA)) (portRef CLK (instanceRef AS_000_INT)) (portRef CLK (instanceRef AS_030_000_SYNC)) (portRef CLK (instanceRef BGACK_030_INT)) + (portRef CLK (instanceRef BGACK_030_INT_D)) (portRef CLK (instanceRef BG_000DFFSH)) (portRef CLK (instanceRef CLK_000_D0)) (portRef CLK (instanceRef CLK_000_D1)) @@ -1792,8 +1931,8 @@ (portRef CLK (instanceRef CLK_CNT_P_1)) (portRef CLK (instanceRef CLK_OUT_INT)) (portRef CLK (instanceRef CLK_OUT_PRE)) - (portRef CLK (instanceRef DSACK_INT_1)) - (portRef CLK (instanceRef DTACK_DMA)) + (portRef CLK (instanceRef DSACK1_INT)) + (portRef CLK (instanceRef DS_000_DMA)) (portRef CLK (instanceRef DTACK_SYNC)) (portRef CLK (instanceRef FPU_CS_INT)) (portRef CLK (instanceRef IPL_030DFFSH_0)) @@ -1801,6 +1940,8 @@ (portRef CLK (instanceRef IPL_030DFFSH_2)) (portRef CLK (instanceRef LDS_000_INT)) (portRef CLK (instanceRef RESETDFFRH)) + (portRef CLK (instanceRef SIZE_DMA_0)) + (portRef CLK (instanceRef SIZE_DMA_1)) (portRef CLK (instanceRef SM_AMIGA_0)) (portRef CLK (instanceRef SM_AMIGA_1)) (portRef CLK (instanceRef SM_AMIGA_2)) @@ -1811,7 +1952,6 @@ (portRef CLK (instanceRef SM_AMIGA_7)) (portRef CLK (instanceRef UDS_000_INT)) (portRef CLK (instanceRef VMA_INT)) - (portRef CLK (instanceRef VPA_D)) (portRef CLK (instanceRef VPA_SYNC)) (portRef CLK (instanceRef cpu_est_0)) (portRef CLK (instanceRef cpu_est_1)) @@ -1896,7 +2036,7 @@ )) (net (rename DSACK_c_1 "DSACK_c[1]") (joined (portRef O (instanceRef DSACK_1)) - (portRef I0 (instanceRef I_128)) + (portRef I0 (instanceRef DTACK)) )) (net (rename DSACK_1 "DSACK[1]") (joined (portRef (member dsack 0)) @@ -1904,7 +2044,7 @@ )) (net DTACK_c (joined (portRef O (instanceRef DTACK)) - (portRef I0 (instanceRef I_127)) + (portRef I0 (instanceRef I_157)) )) (net DTACK (joined (portRef IO (instanceRef DTACK)) @@ -1924,7 +2064,8 @@ )) (net VPA_c (joined (portRef O (instanceRef VPA)) - (portRef D (instanceRef VPA_D)) + (portRef I0 (instanceRef VPA_i)) + (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a2)) )) (net VPA (joined (portRef VPA) @@ -1936,8 +2077,6 @@ )) (net RST_c (joined (portRef O (instanceRef RST)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_r)) (portRef I0 (instanceRef RST_i)) )) (net RST (joined @@ -1956,6 +2095,7 @@ (portRef O (instanceRef RW)) (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0_m2_m)) (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_m2_r)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_m1_0_x2)) (portRef I0 (instanceRef RW_i)) )) (net RW (joined @@ -1964,7 +2104,7 @@ )) (net (rename FC_c_0 "FC_c[0]") (joined (portRef O (instanceRef FC_0)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_2)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_3)) )) (net (rename FC_0 "FC[0]") (joined (portRef (member fc 1)) @@ -1972,16 +2112,15 @@ )) (net (rename FC_c_1 "FC_c[1]") (joined (portRef O (instanceRef FC_1)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_2)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5)) )) (net (rename FC_1 "FC[1]") (joined (portRef (member fc 0)) (portRef I0 (instanceRef FC_1)) )) (net AMIGA_BUS_ENABLE_c (joined - (portRef Q (instanceRef AMIGA_BUS_ENABLEDFF)) + (portRef Q (instanceRef AMIGA_BUS_ENABLEDFFSH)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_n)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_i)) (portRef I0 (instanceRef AMIGA_BUS_ENABLE)) )) (net AMIGA_BUS_ENABLE (joined @@ -2000,445 +2139,471 @@ (portRef O (instanceRef CIIN)) (portRef CIIN) )) - (net (rename cpu_est_ns_0_1 "cpu_est_ns_0[1]") (joined - (portRef O (instanceRef cpu_est_ns_0_0_1)) - (portRef I0 (instanceRef cpu_est_ns_0_0_i_1)) + (net (rename state_machine_un23_clk_000_d0_0 "state_machine.un23_clk_000_d0_0") (joined + (portRef O (instanceRef state_machine_un23_clk_000_d0)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_o2_4)) + (portRef I0 (instanceRef state_machine_un23_clk_000_d0_i)) )) - (net N_129_i (joined - (portRef O (instanceRef N_129_i)) - (portRef I0 (instanceRef cpu_est_ns_0_0_1_1)) + (net (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (joined + (portRef O (instanceRef state_machine_un6_bgack_000_0)) + (portRef I0 (instanceRef state_machine_un6_bgack_000_0_i)) )) - (net N_131_i (joined - (portRef O (instanceRef N_131_i)) - (portRef I1 (instanceRef cpu_est_ns_0_0_1_1)) - )) - (net N_221_i (joined - (portRef O (instanceRef N_221_i)) - (portRef I0 (instanceRef cpu_est_ns_0_0_2_1)) - )) - (net N_222_i (joined - (portRef O (instanceRef N_222_i)) - (portRef I1 (instanceRef cpu_est_ns_0_0_2_1)) - )) - (net N_63_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_0_o2_4)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_i_4)) - )) - (net N_62_0 (joined - (portRef O (instanceRef SM_AMIGA_ns_i_0_o2_1)) - (portRef I0 (instanceRef SM_AMIGA_ns_i_0_o2_i_1)) - )) - (net N_132_i (joined - (portRef O (instanceRef N_132_i)) - (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3)) - )) - (net un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0 (joined - (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i)) - (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_1_sqmuxa_2_0_o3_i)) - )) - (net DS_030_c_i (joined - (portRef O (instanceRef DS_030_c_i)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_o3)) - )) - (net N_60_i (joined - (portRef O (instanceRef state_machine_UDS_000_INT_5_0_o3)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_5_0)) - (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_o3_i)) - )) - (net N_59_i (joined - (portRef O (instanceRef cpu_est_ns_i_0_o2_3)) - (portRef I0 (instanceRef cpu_est_ns_i_0_o2_i_3)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_1)) - )) - (net N_57_i (joined - (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_o2)) - (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_o2_i_o2_i)) - )) - (net N_56_i (joined - (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2)) - (portRef I1 (instanceRef SM_AMIGA_ns_i_0_o2_1)) - (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2_i)) - )) - (net N_55_i (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2)) - (portRef I1 (instanceRef un1_as_030_000_sync8_i_a3)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_i)) - )) - (net CLK_000_D1_i (joined - (portRef O (instanceRef CLK_000_D1_i)) - (portRef I1 (instanceRef clk_un3_clk_000_d1_0_o2)) - )) - (net N_54_i (joined - (portRef O (instanceRef clk_un3_clk_000_d1_0_o2)) - (portRef I0 (instanceRef cpu_estse_0_a3_0)) - (portRef I0 (instanceRef clk_un3_clk_000_d1_0_o2_i)) - )) - (net N_51_i (joined - (portRef O (instanceRef DSACK_INT_1_sqmuxa_i_o3)) - (portRef I0 (instanceRef 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(portRef I0 (instanceRef cpu_estse_0_0)) + )) + (net N_148_i (joined + (portRef O (instanceRef N_148_i)) + (portRef I1 (instanceRef cpu_estse_0_0)) + )) + (net (rename cpu_est_ns_e_0_0 "cpu_est_ns_e_0[0]") (joined + (portRef O (instanceRef cpu_estse_0_0)) + (portRef I0 (instanceRef cpu_estse_0_0_i)) + )) + (net N_146_i (joined + (portRef O (instanceRef N_146_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0)) + )) + (net (rename SM_AMIGA_ns_0_0 "SM_AMIGA_ns_0[0]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_i_0)) + )) + (net N_88_i (joined + (portRef O (instanceRef N_88_i)) + (portRef I0 (instanceRef cpu_est_ns_0_0_2)) + )) + (net N_145_i (joined + (portRef O (instanceRef N_145_i)) + (portRef I1 (instanceRef cpu_est_ns_0_0_2)) + )) + (net (rename cpu_est_ns_0_2 "cpu_est_ns_0[2]") (joined + (portRef O (instanceRef cpu_est_ns_0_0_2)) + (portRef I0 (instanceRef cpu_est_ns_0_0_i_2)) + )) + (net N_143_i (joined + (portRef O (instanceRef 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(net N_225_i (joined + (portRef O (instanceRef N_225_i)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0)) + )) + (net un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0 (joined + (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0)) + (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_0_sqmuxa_2_0_i)) + )) + (net N_219_i (joined + (portRef O (instanceRef N_219_i)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0)) + )) + (net N_221_i (joined + (portRef O (instanceRef N_221_i)) + (portRef I1 (instanceRef state_machine_un15_clk_000_d0_0)) + )) + (net (rename state_machine_un15_clk_000_d0_0 "state_machine.un15_clk_000_d0_0") (joined + (portRef O (instanceRef state_machine_un15_clk_000_d0_0)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_i)) )) (net (rename clk_un12_clk_cnt_p_i "clk.un12_clk_cnt_p_i") (joined (portRef O (instanceRef clk_un12_clk_cnt_p)) (portRef D (instanceRef CLK_OUT_PRE)) )) - (net (rename state_machine_un23_clk_000_d0_0 "state_machine.un23_clk_000_d0_0") (joined - (portRef O (instanceRef state_machine_un23_clk_000_d0)) - (portRef I0 (instanceRef state_machine_un23_clk_000_d0_i)) + (net N_66_i_1 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4)) )) - (net N_236_1 (joined - (portRef O (instanceRef un8_ciin_1)) - (portRef I0 (instanceRef un8_ciin_5)) + (net N_66_i_2 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_2)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4)) )) - (net N_236_2 (joined - (portRef O (instanceRef un8_ciin_2)) - (portRef I1 (instanceRef un8_ciin_5)) + (net N_66_i_3 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_3)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5)) )) - (net N_236_3 (joined - (portRef O (instanceRef un8_ciin_3)) - (portRef I0 (instanceRef un8_ciin_6)) + (net N_66_i_4 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2)) )) - (net N_236_4 (joined - (portRef O (instanceRef un8_ciin_4)) - (portRef I1 (instanceRef un8_ciin_6)) + (net N_66_i_5 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2)) )) - (net N_236_5 (joined - (portRef O (instanceRef un8_ciin_5)) - (portRef I0 (instanceRef un8_ciin)) - )) - (net N_236_6 (joined - (portRef O (instanceRef un8_ciin_6)) - (portRef I1 (instanceRef un8_ciin)) - )) - (net N_239_1 (joined + (net N_237_1 (joined (portRef O (instanceRef un4_ciin_1)) (portRef I0 (instanceRef un4_ciin)) )) - (net N_239_2 (joined + (net N_237_2 (joined (portRef O (instanceRef un4_ciin_2)) (portRef I1 (instanceRef un4_ciin)) )) + (net N_247_1 (joined + (portRef O (instanceRef un8_ciin_1)) + (portRef I0 (instanceRef un8_ciin_5)) + )) + (net N_247_2 (joined + (portRef O (instanceRef un8_ciin_2)) + (portRef I1 (instanceRef un8_ciin_5)) + )) + (net N_247_3 (joined + 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(portRef O (instanceRef state_machine_un10_bg_030_0_a2_1)) + (portRef I0 (instanceRef state_machine_un10_bg_030_0_a2)) + )) + (net N_227_2 (joined + (portRef O (instanceRef state_machine_un10_bg_030_0_a2_2)) + (portRef I1 (instanceRef state_machine_un10_bg_030_0_a2)) + )) + (net N_228_1_0 (joined + (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a2_1)) + (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a2)) + )) + (net N_127_1 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a2_1)) + (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a2)) + )) + (net N_127_2 (joined + (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a2_2)) + (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a2)) + )) + (net N_151_1 (joined + (portRef O (instanceRef SIZE_DMA_0_sqmuxa_0_a2_0_1)) + (portRef I0 (instanceRef SIZE_DMA_0_sqmuxa_0_a2_0)) + )) + (net SIZE_DMA_1_sqmuxa_1 (joined + (portRef O (instanceRef SIZE_DMA_1_sqmuxa_0_a2_1)) + (portRef I0 (instanceRef SIZE_DMA_1_sqmuxa_0_a2)) + )) (net (rename state_machine_un8_clk_000_d2_1 "state_machine.un8_clk_000_d2_1") (joined (portRef O (instanceRef state_machine_un8_clk_000_d2_1)) (portRef I0 (instanceRef state_machine_un8_clk_000_d2)) )) - (net N_55_i_1 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_1)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4)) - )) - (net N_55_i_2 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_2)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4)) - )) - (net N_55_i_3 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_3)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5)) - )) - (net N_55_i_4 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_4)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2)) - )) - (net N_55_i_5 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2_5)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_o2)) + (net (rename SM_AMIGA_ns_0_1_0 "SM_AMIGA_ns_0_1[0]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0)) )) (net (rename cpu_est_ns_0_1_1 "cpu_est_ns_0_1[1]") (joined (portRef O (instanceRef cpu_est_ns_0_0_1_1)) (portRef I0 (instanceRef cpu_est_ns_0_0_1)) )) - (net (rename cpu_est_ns_0_2_1 "cpu_est_ns_0_2[1]") (joined - (portRef O (instanceRef cpu_est_ns_0_0_2_1)) - (portRef I1 (instanceRef cpu_est_ns_0_0_1)) + (net N_138_1 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_a2_0_1_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_a2_0_5)) )) - (net N_80_1 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_1)) - (portRef I0 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3)) + (net N_130_1 (joined + (portRef O (instanceRef state_machine_LDS_000_INT_5_0_a2_1)) + (portRef I0 (instanceRef state_machine_LDS_000_INT_5_0_a2)) )) - (net N_80_2 (joined - (portRef O (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3_2)) - (portRef I1 (instanceRef AS_030_000_SYNC_1_sqmuxa_i_a3)) + (net N_128_1 (joined + (portRef O (instanceRef state_machine_A0_DMA_4_0_a2_1_0)) + (portRef I0 (instanceRef state_machine_A0_DMA_4_0_a2)) )) - (net N_78_1 (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_1)) - (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3)) + (net N_221_1 (joined + (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a2_0_1)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a2_0)) )) - (net N_78_2 (joined - (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3_2)) - (portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1_i_a3)) - )) - (net N_74_1 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_1)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_3)) - )) - (net N_74_2 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_2)) - (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_3)) - )) - (net N_74_3 (joined - (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3_3)) - (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_i_a3)) - )) - (net N_70_1 (joined - (portRef O (instanceRef state_machine_un10_bg_030_0_a3_1)) - (portRef I0 (instanceRef state_machine_un10_bg_030_0_a3)) - )) - (net N_70_2 (joined - (portRef O (instanceRef state_machine_un10_bg_030_0_a3_2)) - (portRef I1 (instanceRef state_machine_un10_bg_030_0_a3)) - )) - (net (rename SM_AMIGA_ns_0_1_0 "SM_AMIGA_ns_0_1[0]") (joined - (portRef O (instanceRef SM_AMIGA_ns_0_1_0)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_0)) - )) - (net (rename cpu_est_ns_0_1_2 "cpu_est_ns_0_1[2]") (joined - (portRef O (instanceRef cpu_est_ns_0_0_1_2)) - (portRef I0 (instanceRef cpu_est_ns_0_0_2)) - )) - (net N_226_1 (joined - (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1)) - (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3)) - )) - (net N_220_1 (joined - (portRef O (instanceRef SM_AMIGA_ns_0_a3_0_1_7)) - (portRef I0 (instanceRef SM_AMIGA_ns_0_a3_0_7)) - )) - (net N_82_1 (joined - (portRef O (instanceRef state_machine_LDS_000_INT_5_0_a3_1)) - (portRef I0 (instanceRef state_machine_LDS_000_INT_5_0_a3)) - )) - (net N_73_1 (joined - (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_0_1)) - (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3_0)) - )) - (net N_72_1 (joined - (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a3_1)) - (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a3)) - )) - (net (rename state_machine_UDS_000_INT_5_0_m2_un3 "state_machine.UDS_000_INT_5_0_m2.un3") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_r)) - (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0_m2_n)) - )) - (net (rename state_machine_UDS_000_INT_5_0_m2_un1 "state_machine.UDS_000_INT_5_0_m2.un1") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_m)) - (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_m2_p)) - )) - (net (rename state_machine_UDS_000_INT_5_0_m2_un0 "state_machine.UDS_000_INT_5_0_m2.un0") (joined - (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_n)) - (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0_m2_p)) + (net N_219_1 (joined + (portRef O (instanceRef state_machine_un15_clk_000_d0_0_a2_1)) + (portRef I0 (instanceRef state_machine_un15_clk_000_d0_0_a2)) )) (net (rename VPA_SYNC_0_un3 "VPA_SYNC_0.un3") (joined (portRef O (instanceRef VPA_SYNC_0_r)) @@ -2452,17 +2617,29 @@ (portRef O (instanceRef VPA_SYNC_0_n)) (portRef I1 (instanceRef VPA_SYNC_0_p)) )) - (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined - (portRef O (instanceRef VMA_INT_0_r)) - (portRef I1 (instanceRef VMA_INT_0_n)) + (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined + (portRef O (instanceRef AS_000_INT_0_r)) + (portRef I1 (instanceRef AS_000_INT_0_n)) )) - (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined - (portRef O (instanceRef VMA_INT_0_m)) - (portRef I0 (instanceRef VMA_INT_0_p)) + (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined + (portRef O (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_p)) )) - (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined - (portRef O (instanceRef VMA_INT_0_n)) - (portRef I1 (instanceRef VMA_INT_0_p)) + (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined + (portRef O (instanceRef AS_000_INT_0_n)) + (portRef I1 (instanceRef AS_000_INT_0_p)) + )) + (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined + (portRef O (instanceRef AS_000_DMA_0_r)) + (portRef I1 (instanceRef AS_000_DMA_0_n)) + )) + (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined + (portRef O (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_000_DMA_0_p)) + )) + (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined + (portRef O (instanceRef AS_000_DMA_0_n)) + (portRef I1 (instanceRef AS_000_DMA_0_p)) )) (net (rename BG_000_0_un3 "BG_000_0.un3") (joined (portRef O (instanceRef BG_000_0_r)) @@ -2476,6 +2653,114 @@ (portRef O (instanceRef BG_000_0_n)) (portRef I1 (instanceRef BG_000_0_p)) )) + (net (rename A0_DMA_0_un3 "A0_DMA_0.un3") (joined + (portRef O (instanceRef A0_DMA_0_r)) + (portRef I1 (instanceRef A0_DMA_0_n)) + )) + (net (rename A0_DMA_0_un1 "A0_DMA_0.un1") (joined + (portRef O (instanceRef A0_DMA_0_m)) + (portRef I0 (instanceRef A0_DMA_0_p)) + )) + (net (rename A0_DMA_0_un0 "A0_DMA_0.un0") (joined + (portRef O (instanceRef A0_DMA_0_n)) + (portRef I1 (instanceRef A0_DMA_0_p)) + )) + (net (rename DTACK_SYNC_0_un3 "DTACK_SYNC_0.un3") (joined + (portRef O (instanceRef DTACK_SYNC_0_r)) + (portRef I1 (instanceRef DTACK_SYNC_0_n)) + )) + (net (rename DTACK_SYNC_0_un1 "DTACK_SYNC_0.un1") (joined + (portRef O (instanceRef DTACK_SYNC_0_m)) + (portRef I0 (instanceRef DTACK_SYNC_0_p)) + )) + (net (rename DTACK_SYNC_0_un0 "DTACK_SYNC_0.un0") (joined + (portRef O (instanceRef DTACK_SYNC_0_n)) + (portRef I1 (instanceRef DTACK_SYNC_0_p)) + )) + (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined + (portRef O (instanceRef LDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_n)) + )) + (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined + (portRef O (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef LDS_000_INT_0_p)) + )) + (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined + (portRef O (instanceRef LDS_000_INT_0_n)) + (portRef I1 (instanceRef LDS_000_INT_0_p)) + )) + (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined + (portRef O (instanceRef UDS_000_INT_0_r)) + (portRef I1 (instanceRef UDS_000_INT_0_n)) + )) + (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined + (portRef O (instanceRef UDS_000_INT_0_m)) + (portRef I0 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined + (portRef O (instanceRef UDS_000_INT_0_n)) + (portRef I1 (instanceRef UDS_000_INT_0_p)) + )) + (net (rename FPU_CS_INT_0_un3 "FPU_CS_INT_0.un3") (joined + (portRef O (instanceRef FPU_CS_INT_0_r)) + (portRef I1 (instanceRef FPU_CS_INT_0_n)) + )) + (net (rename FPU_CS_INT_0_un1 "FPU_CS_INT_0.un1") (joined + (portRef O (instanceRef FPU_CS_INT_0_m)) + (portRef I0 (instanceRef FPU_CS_INT_0_p)) + )) + (net (rename FPU_CS_INT_0_un0 "FPU_CS_INT_0.un0") (joined + (portRef O (instanceRef FPU_CS_INT_0_n)) + (portRef I1 (instanceRef FPU_CS_INT_0_p)) + )) + (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined + (portRef O (instanceRef DS_000_DMA_0_r)) + (portRef I1 (instanceRef DS_000_DMA_0_n)) + )) + (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined + (portRef O (instanceRef DS_000_DMA_0_m)) + (portRef I0 (instanceRef DS_000_DMA_0_p)) + )) + (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined + (portRef O (instanceRef DS_000_DMA_0_n)) + (portRef I1 (instanceRef DS_000_DMA_0_p)) + )) + (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_r)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) + )) + (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) + )) + (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_n)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) + )) + (net (rename SIZE_DMA_0_1__un3 "SIZE_DMA_0_1_.un3") (joined + (portRef O (instanceRef SIZE_DMA_0_1__r)) + (portRef I1 (instanceRef SIZE_DMA_0_1__n)) + )) + (net (rename SIZE_DMA_0_1__un1 "SIZE_DMA_0_1_.un1") (joined + (portRef O (instanceRef SIZE_DMA_0_1__m)) + (portRef I0 (instanceRef SIZE_DMA_0_1__p)) + )) + (net (rename SIZE_DMA_0_1__un0 "SIZE_DMA_0_1_.un0") (joined + (portRef O (instanceRef SIZE_DMA_0_1__n)) + (portRef I1 (instanceRef SIZE_DMA_0_1__p)) + )) + (net (rename SIZE_DMA_0_0__un3 "SIZE_DMA_0_0_.un3") (joined + (portRef O (instanceRef SIZE_DMA_0_0__r)) + (portRef I1 (instanceRef SIZE_DMA_0_0__n)) + )) + (net (rename SIZE_DMA_0_0__un1 "SIZE_DMA_0_0_.un1") (joined + (portRef O (instanceRef SIZE_DMA_0_0__m)) + (portRef I0 (instanceRef SIZE_DMA_0_0__p)) + )) + (net (rename SIZE_DMA_0_0__un0 "SIZE_DMA_0_0_.un0") (joined + (portRef O (instanceRef SIZE_DMA_0_0__n)) + (portRef I1 (instanceRef SIZE_DMA_0_0__p)) + )) (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined (portRef O (instanceRef BGACK_030_INT_0_r)) (portRef I1 (instanceRef BGACK_030_INT_0_n)) @@ -2488,17 +2773,65 @@ (portRef O (instanceRef BGACK_030_INT_0_n)) (portRef I1 (instanceRef BGACK_030_INT_0_p)) )) - (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined - (portRef O (instanceRef AS_000_INT_0_r)) - (portRef I1 (instanceRef AS_000_INT_0_n)) + (net (rename DSACK1_INT_0_un3 "DSACK1_INT_0.un3") (joined + (portRef O (instanceRef DSACK1_INT_0_r)) + (portRef I1 (instanceRef DSACK1_INT_0_n)) )) - (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined - (portRef O (instanceRef AS_000_INT_0_m)) - (portRef I0 (instanceRef AS_000_INT_0_p)) + (net (rename DSACK1_INT_0_un1 "DSACK1_INT_0.un1") (joined + (portRef O (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_0_p)) )) - (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined - (portRef O (instanceRef AS_000_INT_0_n)) - (portRef I1 (instanceRef AS_000_INT_0_p)) + (net (rename DSACK1_INT_0_un0 "DSACK1_INT_0.un0") (joined + (portRef O (instanceRef DSACK1_INT_0_n)) + (portRef I1 (instanceRef DSACK1_INT_0_p)) + )) + (net (rename state_machine_UDS_000_INT_5_0_m2_un3 "state_machine.UDS_000_INT_5_0_m2.un3") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_r)) + (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0_m2_n)) + )) + (net (rename state_machine_UDS_000_INT_5_0_m2_un1 "state_machine.UDS_000_INT_5_0_m2.un1") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_m)) + (portRef I0 (instanceRef state_machine_UDS_000_INT_5_0_m2_p)) + )) + (net (rename state_machine_UDS_000_INT_5_0_m2_un0 "state_machine.UDS_000_INT_5_0_m2.un0") (joined + (portRef O (instanceRef state_machine_UDS_000_INT_5_0_m2_n)) + (portRef I1 (instanceRef state_machine_UDS_000_INT_5_0_m2_p)) + )) + (net (rename cpu_est_ns_0_0_m2_2__un3 "cpu_est_ns_0_0_m2_2_.un3") (joined + (portRef O (instanceRef cpu_est_ns_0_0_m2_2__r)) + (portRef I1 (instanceRef cpu_est_ns_0_0_m2_2__n)) + )) + (net (rename cpu_est_ns_0_0_m2_2__un1 "cpu_est_ns_0_0_m2_2_.un1") (joined + (portRef O (instanceRef cpu_est_ns_0_0_m2_2__m)) + (portRef I0 (instanceRef cpu_est_ns_0_0_m2_2__p)) + )) + (net (rename cpu_est_ns_0_0_m2_2__un0 "cpu_est_ns_0_0_m2_2_.un0") (joined + (portRef O (instanceRef cpu_est_ns_0_0_m2_2__n)) + (portRef I1 (instanceRef cpu_est_ns_0_0_m2_2__p)) + )) + (net (rename AMIGA_BUS_ENABLE_0_un3 "AMIGA_BUS_ENABLE_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_n)) + )) + (net (rename AMIGA_BUS_ENABLE_0_un1 "AMIGA_BUS_ENABLE_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_0_un0 "AMIGA_BUS_ENABLE_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_p)) + )) + (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined + (portRef O (instanceRef VMA_INT_0_r)) + (portRef I1 (instanceRef VMA_INT_0_n)) + )) + (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined + (portRef O (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_p)) + )) + (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined + (portRef O (instanceRef VMA_INT_0_n)) + (portRef I1 (instanceRef VMA_INT_0_p)) )) (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined (portRef O (instanceRef IPL_030_0_0__r)) @@ -2572,90 +2905,6 @@ (portRef O (instanceRef cpu_estse_2_n)) (portRef I1 (instanceRef cpu_estse_2_p)) )) - (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_r)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) - )) - (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_m)) - (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) - )) - (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined - (portRef O (instanceRef AS_030_000_SYNC_0_n)) - (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) - )) - (net (rename DTACK_SYNC_0_un3 "DTACK_SYNC_0.un3") (joined - (portRef O (instanceRef DTACK_SYNC_0_r)) - (portRef I1 (instanceRef DTACK_SYNC_0_n)) - )) - (net (rename DTACK_SYNC_0_un1 "DTACK_SYNC_0.un1") (joined - (portRef O (instanceRef DTACK_SYNC_0_m)) - (portRef I0 (instanceRef DTACK_SYNC_0_p)) - )) - (net (rename DTACK_SYNC_0_un0 "DTACK_SYNC_0.un0") (joined - (portRef O (instanceRef DTACK_SYNC_0_n)) - (portRef I1 (instanceRef DTACK_SYNC_0_p)) - )) - (net (rename FPU_CS_INT_0_un3 "FPU_CS_INT_0.un3") (joined - (portRef O (instanceRef FPU_CS_INT_0_r)) - (portRef I1 (instanceRef FPU_CS_INT_0_n)) - )) - (net (rename FPU_CS_INT_0_un1 "FPU_CS_INT_0.un1") (joined - (portRef O (instanceRef FPU_CS_INT_0_m)) - (portRef I0 (instanceRef FPU_CS_INT_0_p)) - )) - (net (rename FPU_CS_INT_0_un0 "FPU_CS_INT_0.un0") (joined - (portRef O (instanceRef FPU_CS_INT_0_n)) - (portRef I1 (instanceRef FPU_CS_INT_0_p)) - )) - (net (rename DSACK_INT_0_1__un3 "DSACK_INT_0_1_.un3") (joined - (portRef O (instanceRef DSACK_INT_0_1__r)) - (portRef I1 (instanceRef DSACK_INT_0_1__n)) - )) - (net (rename DSACK_INT_0_1__un1 "DSACK_INT_0_1_.un1") (joined - (portRef O (instanceRef DSACK_INT_0_1__m)) - (portRef I0 (instanceRef DSACK_INT_0_1__p)) - )) - (net (rename DSACK_INT_0_1__un0 "DSACK_INT_0_1_.un0") (joined - (portRef O (instanceRef DSACK_INT_0_1__n)) - (portRef I1 (instanceRef DSACK_INT_0_1__p)) - )) - (net (rename AMIGA_BUS_ENABLE_0_un3 "AMIGA_BUS_ENABLE_0.un3") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_0_r)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_n)) - )) - (net (rename AMIGA_BUS_ENABLE_0_un1 "AMIGA_BUS_ENABLE_0.un1") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_0_m)) - (portRef I0 (instanceRef AMIGA_BUS_ENABLE_0_p)) - )) - (net (rename AMIGA_BUS_ENABLE_0_un0 "AMIGA_BUS_ENABLE_0.un0") (joined - (portRef O (instanceRef AMIGA_BUS_ENABLE_0_n)) - (portRef I1 (instanceRef AMIGA_BUS_ENABLE_0_p)) - )) - (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined - (portRef O (instanceRef UDS_000_INT_0_r)) - (portRef I1 (instanceRef UDS_000_INT_0_n)) - )) - (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined - (portRef O (instanceRef UDS_000_INT_0_m)) - (portRef I0 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined - (portRef O (instanceRef UDS_000_INT_0_n)) - (portRef I1 (instanceRef UDS_000_INT_0_p)) - )) - (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined - (portRef O (instanceRef LDS_000_INT_0_r)) - (portRef I1 (instanceRef LDS_000_INT_0_n)) - )) - (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined - (portRef O (instanceRef LDS_000_INT_0_m)) - (portRef I0 (instanceRef LDS_000_INT_0_p)) - )) - (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined - (portRef O (instanceRef LDS_000_INT_0_n)) - (portRef I1 (instanceRef LDS_000_INT_0_p)) - )) ) (property orig_inst_of (string "BUS68030")) ) diff --git a/Logic/BUS68030.fse b/Logic/BUS68030.fse index e25682f..40a858a 100644 --- a/Logic/BUS68030.fse +++ b/Logic/BUS68030.fse @@ -1,46 +1,46 @@ -fsm_encoding {722122211} onehot +fsm_encoding {721922191} onehot -fsm_state_encoding {722122211} idle_p {00000001} +fsm_state_encoding {721922191} idle_p {00000001} -fsm_state_encoding {722122211} idle_n {00000010} +fsm_state_encoding {721922191} idle_n {00000010} -fsm_state_encoding {722122211} as_set_p {00000100} +fsm_state_encoding {721922191} as_set_p {00000100} -fsm_state_encoding {722122211} as_set_n {00001000} +fsm_state_encoding {721922191} as_set_n {00001000} -fsm_state_encoding {722122211} sample_dtack_p {00010000} +fsm_state_encoding {721922191} sample_dtack_p {00010000} -fsm_state_encoding {722122211} data_fetch_n {00100000} +fsm_state_encoding {721922191} data_fetch_n {00100000} -fsm_state_encoding {722122211} data_fetch_p {01000000} +fsm_state_encoding {721922191} data_fetch_p {01000000} -fsm_state_encoding {722122211} end_cycle_n {10000000} +fsm_state_encoding {721922191} end_cycle_n {10000000} -fsm_registers {722122211} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]} +fsm_registers {721922191} {SM_AMIGA[0]} {SM_AMIGA[1]} {SM_AMIGA[2]} {SM_AMIGA[3]} {SM_AMIGA[4]} {SM_AMIGA[5]} {SM_AMIGA[6]} {SM_AMIGA[7]} -fsm_encoding {7112311122} original +fsm_encoding {7115341152} original -fsm_state_encoding {7112311122} e20 {0000} +fsm_state_encoding {7115341152} e20 {0000} -fsm_state_encoding {7112311122} e5 {0010} +fsm_state_encoding {7115341152} e5 {0010} -fsm_state_encoding {7112311122} e6 {0011} +fsm_state_encoding {7115341152} e6 {0011} -fsm_state_encoding {7112311122} e3 {0100} +fsm_state_encoding {7115341152} e3 {0100} -fsm_state_encoding {7112311122} e4 {0101} +fsm_state_encoding {7115341152} e4 {0101} -fsm_state_encoding {7112311122} e1 {0110} +fsm_state_encoding {7115341152} e1 {0110} -fsm_state_encoding {7112311122} e2 {0111} +fsm_state_encoding {7115341152} e2 {0111} -fsm_state_encoding {7112311122} e7 {1010} +fsm_state_encoding {7115341152} e7 {1010} -fsm_state_encoding {7112311122} e8 {1011} +fsm_state_encoding {7115341152} e8 {1011} -fsm_state_encoding {7112311122} e9 {1100} +fsm_state_encoding {7115341152} e9 {1100} -fsm_state_encoding {7112311122} e10 {1111} +fsm_state_encoding {7115341152} e10 {1111} -fsm_registers {7112311122} {cpu_est[3]} {cpu_est[2]} {cpu_est[1]} {cpu_est[0]} +fsm_registers {7115341152} {cpu_est[3]} {cpu_est[2]} {cpu_est[1]} {cpu_est[0]} diff --git a/Logic/BUS68030.naf b/Logic/BUS68030.naf index bd9707e..4ccf646 100644 --- a/Logic/BUS68030.naf +++ b/Logic/BUS68030.naf @@ -5,38 +5,23 @@ UDS_000 b LDS_000 b SIZE[1] b SIZE[0] b -A[31] b -A[30] b -A[29] b -A[28] b -A[27] b -A[26] b -A[25] b -A[24] b -A[23] b -A[22] b -A[21] b -A[20] b -A[19] b -A[18] b -A[17] b -A[16] b -A[15] b -A[14] b -A[13] b -A[12] b -A[11] b -A[10] b -A[9] b -A[8] b -A[7] b -A[6] b -A[5] b -A[4] b -A[3] b -A[2] b -A[1] b -A[0] b +A[31] i +A[30] i +A[29] i +A[28] i +A[27] i +A[26] i +A[25] i +A[24] i +A[23] i +A[22] i +A[21] i +A[20] i +A[19] i +A[18] i +A[17] i +A[16] i +A0 b nEXP_SPACE i BERR b BG_030 i diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index ad4057b..e8522f8 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj -#-- Written on Sat May 24 19:56:13 2014 +#-- Written on Sat May 24 21:59:07 2014 #device options diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm index 776e6e7..1f3259a 100644 --- a/Logic/BUS68030.srm +++ b/Logic/BUS68030.srm @@ -35,16 +35,15 @@ af .parent_list "-1"; VNAME 'mach.MACH_DFF.prim'; # view id 0 VNAME 'mach.DFFRH.prim'; # view id 1 VNAME 'mach.DFFSH.prim'; # view id 2 -VNAME 'mach.DFF.prim'; # view id 3 +VNAME 'mach.BI_DIR.prim'; # view id 3 VNAME 'mach.IBUF.prim'; # view id 4 VNAME 'mach.BUFTH.prim'; # view id 5 VNAME 'mach.OBUF.prim'; # view id 6 -VNAME 'mach.BI_DIR.prim'; # view id 7 -VNAME 'mach.AND2.prim'; # view id 8 -VNAME 'mach.INV.prim'; # view id 9 -VNAME 'mach.OR2.prim'; # view id 10 -VNAME 'mach.XOR2.prim'; # view id 11 -VNAME 'work.BUS68030.behavioral'; # view id 12 +VNAME 'mach.AND2.prim'; # view id 7 +VNAME 'mach.INV.prim'; # view id 8 +VNAME 'mach.OR2.prim'; # view id 9 +VNAME 'mach.XOR2.prim'; # view id 10 +VNAME 'work.BUS68030.behavioral'; # view id 11 @ERMRlENORBvq]w_7wsRbH l;N3ORCV8HMCF8V;R4 RNP3#8H#PFDCRlC4N; @@ -105,94 +104,79 @@ mShaQQw t)=h 7;bjRf:HjRMkPRMk4RM14R;R bfjj:Rk0sCsR0keCRB B;bjRf:VjRNCD#RDVN#tCRh -7;MlRRNROE7RwwblsH;P -NR#3HblsHR -4;FRRTk;Mj -7HR;R -HB;pi -RoMk;Mj -RNM3P#NCC_M0D_VN4o#Rn.6;R -sfjj:ROlNEqRvB7]_wbwRsRHlQch1 -=STk -MjS77= -pSBip=Bi) -S=BeB -=S1e -BBSahmQ wQ)h=t7b; +7;MlRRNROEA7Q_Qb)Rs;Hl +RNP3bH#sRHl4F; +R +m;HjRQ;R +LQkmRM +4;N3HRHN#b8;R4 +RNH#_$M0#sH0CN0R +4;H Rm;M +oR4kM;M +NRN3#PMC_CV0_D#No46R.nb; R:fjjsR0k0CRsRkCe;BB fbRjR:jV#NDCNRVDR#Ct;h7 -RMRlENORzQAwsRbH +fbRjR:j0RsHkrMjjk9RMQ4Rj Rm;R +bfjj:RVLkRmmRR4kM;R +MROlNEARQzbwRs;Hl +RNP3bH#sRHl4F; +R +m;HjRQ;H +NR#3HbRN84b; +R:fjjkRLVRRmmjRQ;R +bfjj:Rk0sCsR0keCRB +B;bjRf:VjRNCD#RDVN#tCRh +7;MlRRNROEAazw]sRbH l;N3PRHs#bH4lR;R -FmH; -R;Qj -RNH3bH#N48R;R -bfjj:RVLkRmmRR;Qj -fbRjR:j0CskRk0sCBReBb; -R:fjjNRVDR#CV#NDChRt7M; -RNRlOAERz]waRHbslN; -PHR3#Hbsl;R4 -mFRRjmr9N; -HHR3#8bNR -4;N#HR$0M_s0H#NR0C4H; -R;Qj -mHR b; -R:fjjsR0k0CRsRkCe;BB -fbRjR:jV#NDCNRVDR#Ct;h7 -fbRjR:j0RsHkrMjjm9RrRj9QmjR M; -RNRlOmERARzwblsH;P -NR#3HblsHR -4;F;Rm -RNH3bH#N48R;R -HQ -j;bjRf:LjRkmVRRQmRjb; -R:fjjsR0k0CRsRkCe;BB -fbRjR:jV#NDCNRVDR#Ct;h7 -RMRlENOR_AQ7RQ)blsH;P -NR#3HblsHR -4;F;Rm -QHRjL; -RRQmk;M4 -RNH3bH#N48R;H -NRM#$_H0s#00NC;R4 -mHR o; -MMRk4N; -M#R3N_PCM_C0VoDN#.4R6 -n;bjRf:0jRsRkC0CskRBeB;R +FmrRmj +9;N3HRHN#b8;R4 +RNH#_$M0#sH0CN0R +4;HjRQ;R +Hm + ;bjRf:0jRsRkC0CskRBeB;R bfjj:RDVN#VCRNCD#R7th;R -bfjj:RH0sRjkMrRj9kRM4QmjR b; -R:fjjkRLVRRmmMRk4M; -RNRlOqERhR7.blsH;P -NR#3HblsHR -4;F;Rm -QHRjH; -R;Q4 -fbRjR:j0CskRk0sCBReBb; -R:fjjNRVDR#CV#NDChRt7b; -R:fjjMRN8mPRRQmRj4RQ;R -MROlNEhRQesRbH -l;N3PRHs#bH4lR;R -FmH; +bfjj:RH0sRjkMrRj9m9rjRRQjm + ;MlRRNROEmwAzRHbslN; +PHR3#Hbsl;R4 +mFR;H +NR#3HbRN84H; R;Qj -fbRjR:jHRMPmRRmQ +fbRjR:jLRkVmRRmQ j;bjRf:0jRsRkC0CskRBeB;R bfjj:RDVN#VCRNCD#R7th;R -MROlNE)Rm.sRbH -l;N3PRHs#bH4lR;R -FmH; -R;Qj -QHR4b; +MROlNEhRq7b.Rs;Hl +RNP3bH#sRHl4F; +R +m;HjRQ;R +HQ +4;bjRf:0jRsRkC0CskRBeB;R +bfjj:RDVN#VCRNCD#R7th;R +bfjj:R8NMPRRmmjRQR;Q4 +RMRlENOReQhRHbslN; +PHR3#Hbsl;R4 +mFR;R +HQ +j;bjRf:HjRMmPRRQmRjb; R:fjjsR0k0CRsRkCe;BB fbRjR:jV#NDCNRVDR#Ct;h7 -fbRjR:jFRsPmRRmQQjR4M; -RNRlOXERmR).blsH;P -NR#3HblsHR -4;F;Rm -QHRjH; -R;Q4 -fbRjR:j0CskRk0sCBReBb; -R:fjjNRVDR#CV#NDChRt7b; -R:fjjFRGsmPRRQmRj4RQ; -@ +RMRlENOR.m)RHbslN; +PHR3#Hbsl;R4 +mFR;R +HQ +j;H4RQ;R +bfjj:Rk0sCsR0keCRB +B;bjRf:VjRNCD#RDVN#tCRh +7;bjRf:FjRsmPRRQmRj4RQ;R +MROlNEmRX)b.Rs;Hl +RNP3bH#sRHl4F; +R +m;HjRQ;R +HQ +4;bjRf:0jRsRkC0CskRBeB;R +bfjj:RDVN#VCRNCD#R7th;R +bfjj:RsGFPRRmmjRQR;Q4 + +@ ftell; @E@MR@4U:d::(44d:cIRRFRs Anz1UjjdRELCNFPHs;ND RNP3MDHCRMF6 @@ -201,116 +185,114 @@ NR#3H_8PED;R4 RNP3ONsEDVHC;R( RNP38lFkVDCHRDC(N; P#R3$VM_lRNb"sIF "R\B\:\ks#C#l\\NC0x\F\8OCklM\0#\0oHE\kL\jnUd j0\F\Do\HO\jnUdnj-Ujjj-#Lk38PE\M"\"N; -POR3F0M#N_M0sRCo"q71BQi_hjar9"R4;P -NRHFsoM_H#F0_VAR"zU1nj"dj;P -NRs3FHNohl"CRAnz1Ujjd"N; -PVR3D_FI#00NC -R{N3PRVIDF_sbNC_M0H_b#NH##o8MCR -4;N3PRVIDF_FbsbN#_bHbDC48R;P -NRD3VFDI_F#Fb_FLs RCMjN; -PVR3D_FIkJMHkHHVC48R;; -} -RNP3LO8_P#NC -R{N#PR$sM_CsVCCCMO_FODO{ R -RNP10$#C{lR -RNP3M#$_VsCOODF $_0bgCR;; +PsRFHHo_M_#0F"VRAnz1Ujjd"N; +PFR3shHoNRlC"1AzndUjj +";N3PRVIDF_N#00{CR +RNP3FVDIN_bs0CM_#Hb_#N#HCoM8;R4 +RNP3FVDIs_bF_b#NDbbHRC84N; +PVR3D_FIDbFF#s_LFM CR +j;N3PRVIDF_HkMJVkHHRC84}; +;P +NR83OLN_#P{CR +RNP#_$MsCCVsOCMCD_OFRO {P +NR#1$0RCl{P +NR$3#MC_sVFODO0 _$RbCg}; +;; } -};}N; -PFR3Lb#F0M8FC;R4 -@HR@4U:n::44nn::_q1jRdjqj1_d -j;N3HRs_0DFosHMCNlR1"q_jjd"N; -HFR3s8HoH'sRHkMF0 -';F@R@U(:4:44:(::nqj1_jqjR1j_jjN; -HsR30FD_sMHoNRlC"_q1j"jj;H -NRD3#bHFsos8HRM"HF"k0;H -NRF3bsD0N8RHs"0Fk"H; -RU@@::4U4U:4:7n:1d_jj1R7_jjd;H -NR03sDs_FHNoMl"CR7j1_d;j" -RNH3HFsos8HRM'HF'k0;R -F@:@U44g:::4g(7:z1j_jj7Rz1j_jjN; -HsR30FD_sMHoNRlC"1z7_jjj"N; -H#R3DsbFHHo8sHR"M0Fk"N; -HbR3FNs0Ds8HRk"F0 -";F@R@Uj:.:.4:j::(p_71jRjjp_71j;jj -RNH3Ds0_HFsolMNCpR"7j1_j;j" -RNH3b#DFosH8RHs"FHMk;0" -RNH3sbF08NDH"sRF"k0;R -H@:@U.44:::.4cQ:1Z4 r:Rj91 QZrj4:9QR1Z4 r:;j9 -RNH3Ds0_HFsolMNC1R"Q"Z ;H -NRs3FHHo8sHR'M0Fk'N; -HCR38NHVs$sNMCNlRH'#x;C' -@HR@.U:.::4.4.::dqr49:jRdqr49:jRdqr49:j;H +};N3PRFFL#bF08M4CR;R +L@:@U44n:::4nn1:q_jjdR_q1j;dj +RNH3Ds0_HFsolMNCqR"1d_jj +";N#HR$0M_s0H#NR0C4L; +RU@@::4(4(:4:qn:1j_jj1Rq_jjj;H +NR03sDs_FHNoMl"CRqj1_j;j" +RNH#_$M0#sH0CN0R +4;L@R@UU:4:44:U::n7j1_d7jR1d_jjN; +HsR30FD_sMHoNRlC"_71j"dj;H +NRM#$_H0s#00NC;R4 +@LR@4U:g::44(g::1z7_jjjR1z7_jjj;H +NR03sDs_FHNoMl"CRz_71j"jj;H +NRM#$_H0s#00NC;R4 +@LR@.U:j::4.(j::1p7_jjjR1p7_jjj;H +NR03sDs_FHNoMl"CRp_71j"jj;H +NRM#$_H0s#00NC;R4 +@LR@.U:4::4.c4::Z1Q :r4j19RQrZ 49:jRZ1Q :r4j +9;N3HRs_0DFosHMCNlRQ"1Z; " +RNH3HC8VsNsNN$Ml'CR#CHx'N; +H$R#Ms_0HN#004CR;R +H@:@U.4.:::..4r:qd44:nq9Rr:d44Rn9q4rd:94n;H NR03sDs_FHNoMl"CRq -";N3HRFosH8RHs'FHMk;0' -RNH3HC8VsNsNN$Ml'CRN -';H@R@Ud:.:.4:dj:4:XM uu_1qRB Mu X_q1uB +";N3HRCV8HNNss$lMNCNR''L; +RU@@::.d4d:.:q.:jjRq;H +NR03sDs_FHNoMl"CRq;j" +RNH#_$M0#sH0CN0R +4;H@R@Uc:.:.4:cj:4:XM uu_1qRB Mu X_q1uB ;N3HRs_0DFosHMCNlR "MX1u_u qB"F; -RU@@::.c4c:.:Ac: R))A) );H +RU@@::.646:.:Ac: R))A) );H NR03sDs_FHNoMl"CRA) )"N; H#R3DsbFHHo8sHR"M0Fk"N; HbR3FNs0Ds8HRk"F0 -";H@R@U6:.:.4:6::nAjt_dAjRtd_jjN; +";H@R@Un:.:.4:n::nAjt_dAjRtd_jjN; HsR30FD_sMHoNRlC"_Atj"dj;R -F@:@U.4n:::.nnt:A_jjjR_Atj;jj +F@:@U.4(:::.(nt:A_jjjR_Atj;jj RNH3Ds0_HFsolMNCAR"tj_jj -";F@R@U(:.:.4:(::gABtqid_jjtRAq_Bij;dj +";F@R@UU:.:.4:U::gABtqid_jjtRAq_Bij;dj RNH3Ds0_HFsolMNCAR"tiqB_jjd"H; -RU@@::.U4U:.:Ag:tiqB_jjjRqAtBji_j +RU@@::.g4g:.:Ag:tiqB_jjjRqAtBji_j j;N3HRs_0DFosHMCNlRt"Aq_Bij"jj;R -H@:@U.4g:::.g(p:Bid_jjpRBid_jjN; +H@:@Ud4j:::dj(p:Bid_jjpRBid_jjN; HsR30FD_sMHoNRlC"iBp_jjd"H; -RU@@::dj4j:d:B(:pji_jBjRpji_j +RU@@::d444:d:B(:pji_jBjRpji_j j;N3HRs_0DFosHMCNlRp"Bij_jj -";H@R@U4:d:d4:4::UB_pimQ1ZRiBp_Zm1QN; +";H@R@U.:d:d4:.::UB_pimQ1ZRiBp_Zm1QN; HsR30FD_sMHoNRlC"iBp_Zm1Q -";F@R@U.:d:d4:.4:4:iBp_e7Q_amzRiBp_e7Q_amz;H +";F@R@Ud:d:d4:d4:4:iBp_e7Q_amzRiBp_e7Q_amz;H NR03sDs_FHNoMl"CRB_pi7_Qem"za;R -F@:@Ud4d:::dd(p:BiX_ upRBiX_ uN; +F@:@Ud4c:::dc(p:BiX_ upRBiX_ uN; HsR30FD_sMHoNRlC"iBp_u X"F; -RU@@::dc4c:d:wn:uBz_1uRwz1_B;H +RU@@::d646:d:wn:uBz_1uRwz1_B;H NR03sDs_FHNoMl"CRw_uzB;1" -@FR@dU:6::4d(6::pQu_jjdrj.:9uRQpd_jj:r.jQ9Rujp_d.jr:;j9 +@FR@dU:n::4d(n::pQu_jjdrj.:9uRQpd_jj:r.jQ9Rujp_d.jr:;j9 RNH3Ds0_HFsolMNCQR"ujp_d;j" RNH3HC8VsNsNN$Ml'CRH_bDj'dj;R -H@:@Ud4n:::dndu:Qp:r.jQ9Ru.pr:Rj9Qrup.9:j;H +H@:@Ud4(:::d(du:Qp:r.jQ9Ru.pr:Rj9Qrup.9:j;H NR03sDs_FHNoMl"CRQ"up;H NR83CHsVNsMN$NRlC'DHb'L; -RU@@::d(4(:d:76:1iqBrj4:91R7qrBi49:jRq71B4ir:;j9 +RU@@::dU4U:d:76:1iqBrj4:91R7qrBi49:jRq71B4ir:;j9 RNH3Ds0_HFsolMNC7R"1iqB"N; H#R3DsbFHHo8sHR"M0Fk"N; HCR38NHVs$sNMCNlR#'8N'O ;R -L@:@Ud4U:::dU6a:7qRBi7BaqiN; +L@:@Ud4g:::dg6a:7qRBi7BaqiN; HsR30FD_sMHoNRlC"q7aB;i" RNH#_$M0#sH0CN0R -4;F@R@Ug:d:d4:g::cqBe R qeBN; +4;F@R@Uj:c:c4:j::cqBe R qeBN; HsR30FD_sMHoNRlC" qeB -";F@R@Uj:c:c4:j::UqBe _u XR qeBX_ uN; +";F@R@U4:c:c4:4::UqBe _u XR qeBX_ uN; HsR30FD_sMHoNRlC" qeBX_ u ";N3HR#FDbs8HoH"sRHkMF0 ";N3HRb0FsNHD8sFR"k;0" -@FR@cU:4::4c44:: R;H +@FR@cU:.::4c4.:: R;H NR03sDs_FHNoMl"CR -";H@R@U.:c:c4:.::deRuqe;uq +";H@R@Ud:c:c4:d::deRuqe;uq RNH3Ds0_HFsolMNCeR"u;q" -@FR@cU:d::4cdd::qevRqev;H +@FR@cU:c::4cdc::qevRqev;H NR03sDs_FHNoMl"CRe"vq;R -H@:@Uc4c:::ccd1:)a1R)aN; +H@:@Uc46:::c6d1:)a1R)aN; HsR30FD_sMHoNRlC"a)1"F; -RU@@::c646:c:)6: a1 R1) +RU@@::cn4n:c:)6: a1 R1) a;N3HRs_0DFosHMCNlR ")1" a;R -H@:@Uc4n:::cn.W:)R;)W +H@:@Uc4(:::c(.W:)R;)W RNH3Ds0_HFsolMNC)R"W -";H@R@UU:c:c4:U::.w4Br:Rj9w4Br:Rj9w4Br:;j9 +";H@R@Ug:c:c4:g::.w4Br:Rj9w4Br:Rj9w4Br:;j9 RNH3Ds0_HFsolMNCwR"B ";N3HRCV8HNNss$lMNCVR'O -';F@R@Ug:c:c4:gn:4:QqvtAq_z 1_hpqA vRqQ_tqA_z1 Ahqp +';F@R@Uj:6:64:jn:4:QqvtAq_z 1_hpqA vRqQ_tqA_z1 Ahqp ;N3HRs_0DFosHMCNlRv"qQ_tqA_z1 Ahqp; " -@FR@6U:j::464j:Uv:qQ_tqA_z17qqa_)7QRQqvtAq_z71_q_aq7;Q) +@FR@6U:4::4644:Uv:qQ_tqA_z17qqa_)7QRQqvtAq_z71_q_aq7;Q) RNH3Ds0_HFsolMNCqR"vqQt_1Az_a7qqQ_7) -";F@R@U4:6:64:4j:.:QqvtAq_z 1_hpqA m_pWvRqQ_tqA_z1 Ahqpp _m +";F@R@U.:6:64:.j:.:QqvtAq_z 1_hpqA m_pWvRqQ_tqA_z1 Ahqpp _m W;N3HRs_0DFosHMCNlRv"qQ_tqA_z1 Ahqpp _m;W" -@FR@6U:.::46c.::QBQhQRBQ +@FR@6U:d::46cd::QBQhQRBQ h;N3HRs_0DFosHMCNlRQ"BQ;h" RoL7B1qi9rj;L NRH3L0sbF0s8HR @@ -318,7 +300,7 @@ NRH3L0sbF0s8HR RNM3P#NCC_M0D_VN4o#Rn.6;M oR.kM_ OD_0OM_4br9N; M#R3N_PCM_C0VoDN#.4R6 -n;okMRMq4_vqQt_1Az_q hA_p 4J_#lNkG_ +n;okMRMq4_vqQt_1Az_q hA_p jJ_#lNkG_ .;N3MR#CNP_0MC_NVDoR#4.;6n RoMh;_4 RNM3P#NCC_M0D_VN4o#Rn.6;M @@ -366,65 +348,55 @@ oR.h_.N; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_;.d RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_4 -4;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh4_4.N; +oR.h_cN; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_d44;M +n;ohMR_;.6 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR.h_nN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_;.( +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR.h_UN; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_c44;M NRN3#PMC_CV0_D#No46R.no; -M_Rh4;4c +M_Rh4;46 RNM3P#NCC_M0D_VN4o#Rn.6;M oR4h_4 -6;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh4_4nN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_(44;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh4;4U -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR4h_4 -g;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh._4jN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_44.;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh.;jc -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_j -6;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhj_.nN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_c.4;M -NRN3#PMC_CV0_D#No46R.no; -M_Rh.;46 -RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_4 n;N3MR#CNP_0MC_NVDoR#4.;6n -RoMh4_.gN; +RoMh4_4(N; M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_j..;M +n;ohMR_U44;M +NRN3#PMC_CV0_D#No46R.no; +M_Rh4;4g +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4h_. +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh._44N; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_.4.;M +NRN3#PMC_CV0_D#No46R.no; +M_Rh4;.d +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR4h_. +c;N3MR#CNP_0MC_NVDoR#4.;6n +RoMh4_.(N; +M#R3N_PCM_C0VoDN#.4R6 +n;ohMR_g.4;M NRN3#PMC_CV0_D#No46R.no; M_Rh.;.4 RNM3P#NCC_M0D_VN4o#Rn.6;M oR.h_. -.;N3MR#CNP_0MC_NVDoR#4.;6n +c;N3MR#CNP_0MC_NVDoR#4.;6n RoMh._.6N; M#R3N_PCM_C0VoDN#.4R6 n;ohMR_n..;M NRN3#PMC_CV0_D#No46R.no; -M_Rh.;.( +M_Rh.;d( RNM3P#NCC_M0D_VN4o#Rn.6;M -oR.h_. -U;N3MR#CNP_0MC_NVDoR#4.;6n -RoMhd_.nN; -M#R3N_PCM_C0VoDN#.4R6 -n;ohMR_g.d;M -NRN3#PMC_CV0_D#No46R.no; -M0R#N_0ClENOH\MC31z7_jjj_aQh_j6__3l.k;Md -RNM3P#NCC_M0D_VN4o#Rn.6;M -oRN#00lC_NHOEM3C\z_71j_jjQ_ha6__jlk.3M -4;N3MR#CNP_0MC_NVDoR#4.;6n -RoM#00NCN_lOMEHCz\37j1_jQj_h6a__lj_.M3kjN; +oR.h_c +(;N3MR#CNP_0MC_NVDoR#4.;6n +RoMhc_.gN; M#R3N_PCM_C0VoDN#.4R6 n;oeMRu1q_Y_hBjM3kdN; M#R3N_PCM_C0VoDN#.4R6 @@ -432,17 +404,77 @@ n;oeMRu1q_Y_hBjM3k4N; M#R3N_PCM_C0VoDN#.4R6 n;oeMRu1q_Y_hBjM3kjN; M#R3N_PCM_C0VoDN#.4R6 -n;oeMRvQq_hja_3dkM;M -NRN3#PMC_CV0_D#No46R.no; -MvReqh_Qa3_jk;M4 +n;oqMR1j_jjh_Qa3_jk;Md RNM3P#NCC_M0D_VN4o#Rn.6;M -oRqev_aQh_kj3M -j;N3MR#CNP_0MC_NVDoR#4.;6n -RoMAjt_jjj_3dkM;M +oR_q1j_jjQ_hajM3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;oqMR1j_jjh_Qa3_jk;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_q1j_jj7_vqjM3kdN; +M#R3N_PCM_C0VoDN#.4R6 +n;oqMR1j_jjv_7q3_jk;M4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_q1j_jj7_vqjM3kjN; +M#R3N_PCM_C0VoDN#.4R6 +n;oAMRtj_jj3_jk;Md +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_Atj_jjjM3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;oAMRtj_jj3_jk;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_qj7_vqjM3kdN; +M#R3N_PCM_C0VoDN#.4R6 +n;oqMRjv_7q3_jk;M4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_qj7_vqjM3kjN; +M#R3N_PCM_C0VoDN#.4R6 +n;o7MRaiqB_h1YB3_jk;Md +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRq7aB1i_Y_hBjM3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;o7MRaiqB_h1YB3_jk;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR1p7_jjj_aQh_kj3M +d;N3MR#CNP_0MC_NVDoR#4.;6n +RoMp_71j_jjQ_hajM3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;opMR7j1_jQj_hja_3jkM;M NRN3#PMC_CV0_D#No46R.no; -MtRA_jjj_kj3M +M7Rz1j_jjh_Qa3_jk;Md +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR1z7_jjj_aQh_kj3M 4;N3MR#CNP_0MC_NVDoR#4.;6n -RoMAjt_jjj_3jkM;M +RoMz_71j_jjQ_hajM3kjN; +M#R3N_PCM_C0VoDN#.4R6 +n;owMRuBz_1h_Qa3_jk;Md +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRzwu__B1Q_hajM3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;owMRuBz_1h_Qa3_jk;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_71j_jj7_vqjM3kdN; +M#R3N_PCM_C0VoDN#.4R6 +n;o7MR1j_jjv_7q3_jk;M4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_71j_jj7_vqjM3kjN; +M#R3N_PCM_C0VoDN#.4R6 +n;oqMR1d_jjj_jjY_1hjB_3dkM;M +NRN3#PMC_CV0_D#No46R.no; +M1Rq_jjd_jjj_h1YB3_jk;M4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oR_q1j_djj_jj1BYh_kj3M +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoM1 QZ_q7v_4j__M3kdN; +M#R3N_PCM_C0VoDN#.4R6 +n;o1MRQ_Z 7_vqj__434kM;M +NRN3#PMC_CV0_D#No46R.no; +MQR1Z7 _vjq__34_k;Mj +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRZ1Q v_7q__jjk_3M +d;N3MR#CNP_0MC_NVDoR#4.;6n +RoM1 QZ_q7v_jj__M3k4N; +M#R3N_PCM_C0VoDN#.4R6 +n;o1MRQ_Z 7_vqj__j3jkM;M NRN3#PMC_CV0_D#No46R.no; MtRAq_Bij_djQ_hajM3kdN; M#R3N_PCM_C0VoDN#.4R6 @@ -450,11 +482,35 @@ n;oAMRtiqB_jjd_aQh_kj3M 4;N3MR#CNP_0MC_NVDoR#4.;6n RoMABtqid_jjh_Qa3_jk;Mj RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_q1j_jjQ_hajM3kdN; +oRq71B_i4Q_hajM3kdN; M#R3N_PCM_C0VoDN#.4R6 -n;oqMR1j_jjh_Qa3_jk;M4 +n;o7MR1iqB4h_Qa3_jk;M4 RNM3P#NCC_M0D_VN4o#Rn.6;M -oR_q1j_jjQ_hajM3kjN; +oRq71B_i4Q_hajM3kjN; +M#R3N_PCM_C0VoDN#.4R6 +n;o#MR0CN0_OlNECHM\73z1j_jjh_Qa__6j._l3dkM;M +NRN3#PMC_CV0_D#No46R.no; +M0R#N_0ClENOH\MC31z7_jjj_aQh_j6__3l.k;M4 +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRN#00lC_NHOEM3C\z_71j_jjQ_ha6__jlk.3M +j;N3MR#CNP_0MC_NVDoR#4.;6n +RoMO_bkC_#0Mj#__lj_.__.3dkM;M +NRN3#PMC_CV0_D#No46R.no; +MbROk#_C0#_M_jj___l..k_3M +4;N3MR#CNP_0MC_NVDoR#4.;6n +RoMO_bkC_#0Mj#__lj_.__.3jkM;M +NRN3#PMC_CV0_D#No46R.no; +MvRqQ_tqA_z1 Ahqpj _3dkM;M +NRN3#PMC_CV0_D#No46R.no; +MvRqQ_tqA_z1 Ahqpj _34kM;M +NRN3#PMC_CV0_D#No46R.no; +MvRqQ_tqA_z1 Ahqpj _3jkM;M +NRN3#PMC_CV0_D#No46R.no; +MvReqh_Qa3_jk;Md +RNM3P#NCC_M0D_VN4o#Rn.6;M +oRqev_aQh_kj3M +4;N3MR#CNP_0MC_NVDoR#4.;6n +RoMe_vqQ_hajM3kjN; M#R3N_PCM_C0VoDN#.4R6 n;oQMRujp_djj__3j_k;Md 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+R:fjjNRlOQERhbeRsRHlO_bkC##0C3_.sm +S=kOb_0C##.C_3dkM +jSQ=nh_6s; +R:fjjNRlOqERhR7.blsHRkOb_0C##.C_3Sl +mb=Ok#_C0_#C.M3k4Q +Sjb=Ok#_C09rd +4SQ=nh_6s; +R:fjjNRlOqERhR7.blsHRkOb_0C##.C_3SM +mb=Ok#_C0_#C.M3kjQ +Sj_=h4_n4HQ +S4b=Ok#_C0_#C.M3kds; +R:fjjNRlOmER)b.RsRHlO_bkC##0C3_.bm +S=kOb_0C#__M#C9rd +jSQ=kOb_0C##.C_34kM +4SQ=kOb_0C##.C_3jkM; diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr index 231b78a..d807336 100644 --- a/Logic/BUS68030.srr +++ b/Logic/BUS68030.srr @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Sat May 24 19:56:13 2014 +#Sat May 24 21:59:07 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode @@ -18,14 +18,9 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - VHDL syntax check successful! File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:7:113:15|Signal clk_030_d is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Pruning register CLK_REF(1 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Pruning register cpu_est_d(3 downto 0) -@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Feedback mux created for signal AMIGA_BUS_ENABLE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. -@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Pruning register bit 0 of DSACK_INT(1 downto 0) -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":219:2:219:3|Pruning register CLK_REF(1 downto 0) +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":219:2:219:3|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -36,8 +31,7 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Initial value is not supported on state machine SM_AMIGA -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":115:34:115:36|Trying to extract state machine for register cpu_est Extracted state machine for register cpu_est State machine has 11 reachable states with original encodings of: 0000 @@ -51,10 +45,9 @@ State machine has 11 reachable states with original encodings of: 1011 1100 1111 -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Initial value is not supported on state machine cpu_est @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat May 24 19:56:13 2014 +# Sat May 24 21:59:08 2014 ###########################################################] Map & Optimize Report @@ -63,6 +56,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 621R, Built Mar 19 2013 Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version G-2012.09LC-SP1 @N: MF248 |Running in 64-bit mode. +@W: MO111 :|Tristate driver DSACK_tri on net DSACK[0] has its enable tied to GND (module BUS68030) Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral)) original code -> new code 000 -> 00000001 @@ -91,16 +85,15 @@ Resource Usage Report Simple gate primitives: DFFRH 17 uses -DFFSH 25 uses -DFF 1 use -IBUF 35 uses -BUFTH 7 uses +DFFSH 30 uses +BI_DIR 10 uses +IBUF 30 uses +BUFTH 4 uses OBUF 15 uses -BI_DIR 2 uses -AND2 148 uses -INV 131 uses -OR2 19 uses -XOR2 2 uses +AND2 170 uses +INV 145 uses +OR2 25 uses +XOR2 4 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -110,6 +103,6 @@ Mapper successful! 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z`9GabAi%1G`o_2E^n~D{-dNR~1wv}6MejhV$ENW!&w+WJmLse(cN%=D-Us@GyCG~KUh_18s@L9J#g=YJ)y$chqGZyI6;dFL|!mRrW`9>1lVQ8pc|L^k}YzzAAQa97aHZ z-6nzIVNk@N3S>TT@FuUMr8UEdDy>D5)u5%l(1Gz0ZS~x;h z7x=V=3p*|Cp%=3@K|i-v{~!e2Ko#r7mN(7DHI~$!kw4?*Q@xVt)S_2*N{+)W+TG=q`K13OhVj1JeAs)74oksSppTZjk&7?Tq``4w}G}?A(_>5Rymk&IdE0*X< zPs&5zH#{()Q?H#drV! diff --git a/Logic/bus68030.exf b/Logic/bus68030.exf index 6fe97d0..cd45e7c 100644 --- a/Logic/bus68030.exf +++ b/Logic/bus68030.exf @@ -1,513 +1,516 @@ Section Type Array Num Name Real Name Base Number Increment // ------------------------------------------------------------------------------------------------- - Port 1 SIZE(1:0) SIZE 1 2 -1 - Port 2 A(31:0) A 31 32 -1 - Port 3 IPL(2:0) IPL 2 3 -1 - Port 4 FC(1:0) FC 1 2 -1 - Port 5 IPL_030(2:0) IPL_030 2 3 -1 + Port 1 A(31:16) A 31 16 -1 + Port 2 IPL(2:0) IPL 2 3 -1 + Port 3 FC(1:0) FC 1 2 -1 + Port 4 IPL_030(2:0) IPL_030 2 3 -1 + Port 5 SIZE(1:0) SIZE 1 2 -1 Port 6 DSACK(1:0) DSACK 1 2 -1 End Section Member Rename Array-Notation Array Number Index // ------------------------------------------------------------------------------------- - Port SIZE_1_ SIZE[1] 1 0 - Port SIZE_0_ SIZE[0] 1 1 - Port A_31_ A[31] 2 0 - Port A_30_ A[30] 2 1 - Port A_29_ A[29] 2 2 - Port A_28_ A[28] 2 3 - Port A_27_ A[27] 2 4 - Port A_26_ A[26] 2 5 - Port A_25_ A[25] 2 6 - Port A_24_ A[24] 2 7 - Port A_23_ A[23] 2 8 - Port A_22_ A[22] 2 9 - Port A_21_ A[21] 2 10 - Port A_20_ A[20] 2 11 - Port A_19_ A[19] 2 12 - Port A_18_ A[18] 2 13 - Port A_17_ A[17] 2 14 - Port A_16_ A[16] 2 15 - Port A_15_ A[15] 2 16 - Port A_14_ A[14] 2 17 - Port A_13_ A[13] 2 18 - Port A_12_ A[12] 2 19 - Port A_11_ A[11] 2 20 - Port A_10_ A[10] 2 21 - Port A_9_ A[9] 2 22 - Port A_8_ A[8] 2 23 - Port A_7_ A[7] 2 24 - Port A_6_ A[6] 2 25 - Port A_5_ A[5] 2 26 - Port A_4_ A[4] 2 27 - Port A_3_ A[3] 2 28 - Port A_2_ A[2] 2 29 - Port A_1_ A[1] 2 30 - Port A_0_ A[0] 2 31 - Port IPL_030_2_ IPL_030[2] 5 0 - Port IPL_030_1_ IPL_030[1] 5 1 - Port IPL_030_0_ IPL_030[0] 5 2 - Port IPL_2_ IPL[2] 3 0 - Port IPL_1_ IPL[1] 3 1 - Port IPL_0_ IPL[0] 3 2 + Port SIZE_1_ SIZE[1] 5 0 + Port SIZE_0_ SIZE[0] 5 1 + Port A_31_ A[31] 1 0 + Port A_30_ A[30] 1 1 + Port A_29_ A[29] 1 2 + Port A_28_ A[28] 1 3 + Port A_27_ A[27] 1 4 + Port A_26_ A[26] 1 5 + Port A_25_ A[25] 1 6 + Port A_24_ A[24] 1 7 + Port A_23_ A[23] 1 8 + Port A_22_ A[22] 1 9 + Port A_21_ A[21] 1 10 + Port A_20_ A[20] 1 11 + Port A_19_ A[19] 1 12 + Port A_18_ A[18] 1 13 + Port A_17_ A[17] 1 14 + Port A_16_ A[16] 1 15 + Port IPL_030_2_ IPL_030[2] 4 0 + Port IPL_030_1_ IPL_030[1] 4 1 + Port IPL_030_0_ IPL_030[0] 4 2 + Port IPL_2_ IPL[2] 2 0 + Port IPL_1_ IPL[1] 2 1 + Port IPL_0_ IPL[0] 2 2 Port DSACK_1_ DSACK[1] 6 0 Port DSACK_0_ DSACK[0] 6 1 - Port FC_1_ FC[1] 4 0 - Port FC_0_ FC[0] 4 1 + Port FC_1_ FC[1] 3 0 + Port FC_0_ FC[0] 3 1 End Section Cross Reference File -Design 'BUS68030' created Sat May 24 19:56:20 2014 +Design 'BUS68030' created Sat May 24 21:59:14 2014 Type New Name Original Name // ---------------------------------------------------------------------- - Inst i_z2N2N AS_000 - Inst i_z2P2P UDS_000 - Inst i_z2Q2Q LDS_000 - Inst i_z3F3F BERR - Inst i_z4242 DTACK - Inst i_z4444 AVEC_EXP - Inst i_z4G4G CIIN - Inst cpu_est_i_3_ cpu_est_i[3] - Inst cpu_est_ns_i_0_o2_3_ cpu_est_ns_i_0_o2[3] - Inst state_machine_UDS_000_INT_5_0_o3 state_machine.UDS_000_INT_5_0_o3 - Inst SM_AMIGA_ns_i_0_o2_1_ SM_AMIGA_ns_i_0_o2[1] - Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] - Inst SM_AMIGA_ns_i_0_o2_4_ SM_AMIGA_ns_i_0_o2[4] - Inst SM_AMIGA_ns_i_0_6_ SM_AMIGA_ns_i_0[6] - Inst SM_AMIGA_ns_0_7_ SM_AMIGA_ns_0[7] - Inst cpu_est_ns_i_0_3_ cpu_est_ns_i_0[3] - Inst state_machine_AMIGA_BUS_ENABLE_3_f0_i state_machine.AMIGA_BUS_ENABLE_3_f0_i - Inst state_machine_UDS_000_INT_5_0_m2_r state_machine.UDS_000_INT_5_0_m2.r - Inst state_machine_UDS_000_INT_5_0_m2_m state_machine.UDS_000_INT_5_0_m2.m - Inst state_machine_UDS_000_INT_5_0_m2_n state_machine.UDS_000_INT_5_0_m2.n - Inst state_machine_UDS_000_INT_5_0_m2_p state_machine.UDS_000_INT_5_0_m2.p - Inst clk_un3_clk_000_d1_0_o2 clk.un3_clk_000_d1_0_o2 - Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] - Inst state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2 state_machine.AMIGA_BUS_ENABLE_3_f0_i_o2 - Inst SM_AMIGA_i_1_ SM_AMIGA_i[1] - Inst state_machine_un6_clk_000_d5_i state_machine.un6_clk_000_d5_i - Inst state_machine_un6_bgack_000_0 state_machine.un6_bgack_000_0 - Inst state_machine_un10_bg_030_0 state_machine.un10_bg_030_0 - Inst state_machine_un15_clk_000_d0_0 state_machine.un15_clk_000_d0_0 - Inst state_machine_UDS_000_INT_5_0 state_machine.UDS_000_INT_5_0 - Inst state_machine_LDS_000_INT_5_0 state_machine.LDS_000_INT_5_0 - Inst SM_AMIGA_ns_i_0_1_ SM_AMIGA_ns_i_0[1] - Inst cpu_est_1_ cpu_est[1] - Inst SM_AMIGA_ns_i_0_2_ SM_AMIGA_ns_i_0[2] - Inst cpu_est_2_ cpu_est[2] - Inst SM_AMIGA_ns_i_0_3_ SM_AMIGA_ns_i_0[3] - Inst cpu_est_3_ cpu_est[3] - Inst SM_AMIGA_ns_i_0_4_ SM_AMIGA_ns_i_0[4] - Inst cpu_est_0_ cpu_est[0] - Inst SM_AMIGA_ns_0_5_ SM_AMIGA_ns_0[5] - Inst SM_AMIGA_5_ SM_AMIGA[5] - Inst SM_AMIGA_4_ SM_AMIGA[4] - Inst cpu_est_ns_0_0_a3_2_ cpu_est_ns_0_0_a3[2] - Inst SM_AMIGA_3_ SM_AMIGA[3] - Inst cpu_est_ns_0_0_a3_0_2_ cpu_est_ns_0_0_a3_0[2] - Inst SM_AMIGA_2_ SM_AMIGA[2] - Inst cpu_est_ns_0_0_a3_1_2_ cpu_est_ns_0_0_a3_1[2] - Inst SM_AMIGA_1_ SM_AMIGA[1] - Inst SM_AMIGA_ns_0_a3_0_ SM_AMIGA_ns_0_a3[0] - Inst SM_AMIGA_0_ SM_AMIGA[0] - Inst SM_AMIGA_ns_0_a3_0_0_ SM_AMIGA_ns_0_a3_0[0] - Inst CLK_CNT_N_0_ CLK_CNT_N[0] - Inst CLK_CNT_N_1_ CLK_CNT_N[1] - Inst CLK_CNT_P_0_ CLK_CNT_P[0] - Inst cpu_est_i_0_ cpu_est_i[0] - Inst CLK_CNT_P_1_ CLK_CNT_P[1] - Inst cpu_est_ns_0_0_a2_1_ cpu_est_ns_0_0_a2[1] - Inst IPL_030DFFSH_0_ IPL_030DFFSH[0] - Inst cpu_est_ns_i_0_a2_3_ cpu_est_ns_i_0_a2[3] - Inst IPL_030DFFSH_1_ IPL_030DFFSH[1] - Inst cpu_est_i_1_ cpu_est_i[1] - Inst IPL_030DFFSH_2_ IPL_030DFFSH[2] - Inst cpu_est_ns_0_0_a2_0_1_ cpu_est_ns_0_0_a2_0[1] - Inst SM_AMIGA_7_ SM_AMIGA[7] - Inst SM_AMIGA_ns_0_a2_0_ SM_AMIGA_ns_0_a2[0] - Inst SM_AMIGA_6_ SM_AMIGA[6] - Inst SM_AMIGA_ns_i_0_a2_4_ SM_AMIGA_ns_i_0_a2[4] - Inst SM_AMIGA_i_5_ SM_AMIGA_i[5] - Inst SM_AMIGA_ns_i_0_a3_3_ SM_AMIGA_ns_i_0_a3[3] - Inst SM_AMIGA_i_3_ SM_AMIGA_i[3] - Inst SM_AMIGA_ns_i_0_a3_4_ SM_AMIGA_ns_i_0_a3[4] - Inst SM_AMIGA_ns_0_a3_5_ SM_AMIGA_ns_0_a3[5] - Inst SM_AMIGA_ns_0_a3_0_5_ SM_AMIGA_ns_0_a3_0[5] - Inst SM_AMIGA_ns_i_0_a3_6_ SM_AMIGA_ns_i_0_a3[6] - Inst SM_AMIGA_i_2_ SM_AMIGA_i[2] - Inst SM_AMIGA_ns_i_0_a3_0_6_ SM_AMIGA_ns_i_0_a3_0[6] - Inst SM_AMIGA_ns_0_a3_7_ SM_AMIGA_ns_0_a3[7] - Inst cpu_est_ns_0_0_a3_1_ cpu_est_ns_0_0_a3[1] - Inst cpu_est_i_2_ cpu_est_i[2] - Inst DSACK_INT_1_ DSACK_INT[1] - Inst cpu_est_ns_0_0_a3_0_1_ cpu_est_ns_0_0_a3_0[1] - Inst cpu_est_ns_i_0_a3_3_ cpu_est_ns_i_0_a3[3] - Inst state_machine_un7_as_000_int_0_a3 state_machine.un7_as_000_int_0_a3 - Inst A_i_0_ A_i[0] - Inst SIZE_i_1_ SIZE_i[1] - Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] - Inst SM_AMIGA_ns_i_0_a3_1_ SM_AMIGA_ns_i_0_a3[1] - Inst state_machine_un8_clk_000_d2_i state_machine.un8_clk_000_d2_i - Inst SM_AMIGA_ns_i_0_a3_0_1_ SM_AMIGA_ns_i_0_a3_0[1] - Inst SIZE_0_ SIZE[0] - Inst SM_AMIGA_ns_i_0_a3_2_ SM_AMIGA_ns_i_0_a3[2] - Inst SIZE_1_ SIZE[1] - Inst A_0_ A[0] - Inst A_i_24_ A_i[24] - Inst A_16_ A[16] - Inst A_i_25_ A_i[25] - Inst A_17_ A[17] - Inst A_i_26_ A_i[26] - Inst A_18_ A[18] - Inst A_i_27_ A_i[27] - Inst A_19_ A[19] - Inst A_i_28_ A_i[28] - Inst A_20_ A[20] - Inst A_i_29_ A_i[29] - Inst A_21_ A[21] - Inst A_i_30_ A_i[30] - Inst A_22_ A[22] - Inst A_i_31_ A_i[31] - Inst A_23_ A[23] - Inst A_i_16_ A_i[16] - Inst A_24_ A[24] - Inst A_i_18_ A_i[18] - Inst A_25_ A[25] - Inst A_i_19_ A_i[19] - Inst A_26_ A[26] - Inst A_27_ A[27] - Inst A_28_ A[28] - Inst state_machine_un7_as_000_int_i state_machine.un7_as_000_int_i - Inst A_29_ A[29] - Inst un4_clk_cnt_n_i_1_ un4_clk_cnt_n_i[1] - Inst A_30_ A[30] - Inst A_31_ A[31] - Inst un2_clk_cnt_p_i_1_ un2_clk_cnt_p_i[1] + Inst i_z2R2R AS_030 + Inst i_z2S2S AS_000 + Inst i_z2T2T DS_030 + Inst i_z2U2U UDS_000 + Inst i_z2V2V LDS_000 + Inst i_z3I3I A0 + Inst i_z3K3K BERR + Inst i_z4747 DTACK + Inst i_z4949 AVEC_EXP + Inst i_z4L4L CIIN + Inst SM_AMIGA_ns_0_i_7_ SM_AMIGA_ns_0_i[7] + Inst state_machine_DS_000_DMA_5_iv_0_i state_machine.DS_000_DMA_5_iv_0_i + Inst state_machine_un23_clk_000_d0_i state_machine.un23_clk_000_d0_i + Inst state_machine_un6_bgack_000_0_i state_machine.un6_bgack_000_0_i + Inst state_machine_un10_bg_030_0_i state_machine.un10_bg_030_0_i + Inst state_machine_UDS_000_INT_5_0_i state_machine.UDS_000_INT_5_0_i + Inst state_machine_LDS_000_INT_5_0_i state_machine.LDS_000_INT_5_0_i + Inst state_machine_un23_clk_000_d0 state_machine.un23_clk_000_d0 Inst VPA_SYNC_0_r VPA_SYNC_0.r Inst VPA_SYNC_0_m VPA_SYNC_0.m Inst VPA_SYNC_0_n VPA_SYNC_0.n Inst VPA_SYNC_0_p VPA_SYNC_0.p - Inst VMA_INT_0_r VMA_INT_0.r - Inst VMA_INT_0_m VMA_INT_0.m - Inst VMA_INT_0_n VMA_INT_0.n - Inst VMA_INT_0_p VMA_INT_0.p + Inst SM_AMIGA_i_5_ SM_AMIGA_i[5] + Inst AS_000_INT_0_r AS_000_INT_0.r + Inst AS_000_INT_0_m AS_000_INT_0.m + Inst AS_000_INT_0_n AS_000_INT_0.n + Inst AS_000_INT_0_p AS_000_INT_0.p + Inst AS_000_DMA_0_r AS_000_DMA_0.r + Inst AS_000_DMA_0_m AS_000_DMA_0.m + Inst AS_000_DMA_0_n AS_000_DMA_0.n + Inst AS_000_DMA_0_p AS_000_DMA_0.p Inst BG_000_0_r BG_000_0.r Inst BG_000_0_m BG_000_0.m Inst BG_000_0_n BG_000_0.n - Inst IPL_030_0_ IPL_030[0] Inst BG_000_0_p BG_000_0.p - Inst IPL_030_1_ IPL_030[1] + Inst A0_DMA_0_r A0_DMA_0.r + Inst A0_DMA_0_m A0_DMA_0.m + Inst A0_DMA_0_n A0_DMA_0.n + Inst A0_DMA_0_p A0_DMA_0.p + Inst DTACK_SYNC_0_r DTACK_SYNC_0.r + Inst DTACK_SYNC_0_m DTACK_SYNC_0.m + Inst DTACK_SYNC_0_n DTACK_SYNC_0.n + Inst cpu_est_1_ cpu_est[1] + Inst DTACK_SYNC_0_p DTACK_SYNC_0.p + Inst cpu_est_2_ cpu_est[2] + Inst LDS_000_INT_0_r LDS_000_INT_0.r + Inst cpu_est_3_ cpu_est[3] + Inst LDS_000_INT_0_m LDS_000_INT_0.m + Inst cpu_est_0_ cpu_est[0] + Inst LDS_000_INT_0_n LDS_000_INT_0.n + Inst SM_AMIGA_4_ SM_AMIGA[4] + Inst LDS_000_INT_0_p LDS_000_INT_0.p + Inst SM_AMIGA_3_ SM_AMIGA[3] + Inst UDS_000_INT_0_r UDS_000_INT_0.r + Inst SM_AMIGA_2_ SM_AMIGA[2] + Inst UDS_000_INT_0_m UDS_000_INT_0.m + Inst SM_AMIGA_1_ SM_AMIGA[1] + Inst UDS_000_INT_0_n UDS_000_INT_0.n + Inst SM_AMIGA_0_ SM_AMIGA[0] + Inst UDS_000_INT_0_p UDS_000_INT_0.p + Inst CLK_CNT_P_1_ CLK_CNT_P[1] + Inst FPU_CS_INT_0_r FPU_CS_INT_0.r + Inst SIZE_DMA_0_ SIZE_DMA[0] + Inst FPU_CS_INT_0_m FPU_CS_INT_0.m + Inst SIZE_DMA_1_ SIZE_DMA[1] + Inst FPU_CS_INT_0_n FPU_CS_INT_0.n + Inst IPL_030DFFSH_0_ IPL_030DFFSH[0] + Inst FPU_CS_INT_0_p FPU_CS_INT_0.p + Inst IPL_030DFFSH_1_ IPL_030DFFSH[1] + Inst DS_000_DMA_0_r DS_000_DMA_0.r + Inst IPL_030DFFSH_2_ IPL_030DFFSH[2] + Inst DS_000_DMA_0_m DS_000_DMA_0.m + Inst SM_AMIGA_7_ SM_AMIGA[7] + Inst DS_000_DMA_0_n DS_000_DMA_0.n + Inst SM_AMIGA_6_ SM_AMIGA[6] + Inst DS_000_DMA_0_p DS_000_DMA_0.p + Inst SM_AMIGA_5_ SM_AMIGA[5] + Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r + Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m + Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n + Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p + Inst CLK_CNT_N_0_ CLK_CNT_N[0] + Inst state_machine_un6_clk_000_d5 state_machine.un6_clk_000_d5 + Inst CLK_CNT_N_1_ CLK_CNT_N[1] + Inst CLK_CNT_P_0_ CLK_CNT_P[0] + Inst A_i_19_ A_i[19] + Inst A_i_18_ A_i[18] + Inst A_i_16_ A_i[16] + Inst SIZE_DMA_0_1__r SIZE_DMA_0_1_.r + Inst SIZE_DMA_0_1__m SIZE_DMA_0_1_.m + Inst SIZE_DMA_0_1__n SIZE_DMA_0_1_.n + Inst SIZE_DMA_0_1__p SIZE_DMA_0_1_.p + Inst SIZE_DMA_0_0__r SIZE_DMA_0_0_.r + Inst SIZE_DMA_0_0__m SIZE_DMA_0_0_.m + Inst SIZE_DMA_0_0__n SIZE_DMA_0_0_.n + Inst SIZE_DMA_0_0__p SIZE_DMA_0_0_.p Inst BGACK_030_INT_0_r BGACK_030_INT_0.r - Inst IPL_030_2_ IPL_030[2] Inst BGACK_030_INT_0_m BGACK_030_INT_0.m - Inst IPL_0_ IPL[0] Inst BGACK_030_INT_0_n BGACK_030_INT_0.n - Inst IPL_1_ IPL[1] Inst BGACK_030_INT_0_p BGACK_030_INT_0.p + Inst DSACK1_INT_0_r DSACK1_INT_0.r + Inst DSACK1_INT_0_m DSACK1_INT_0.m + Inst DSACK1_INT_0_n DSACK1_INT_0.n + Inst DSACK1_INT_0_p DSACK1_INT_0.p + Inst SM_AMIGA_ns_i_0_a2_3_ SM_AMIGA_ns_i_0_a2[3] + Inst SM_AMIGA_i_6_ SM_AMIGA_i[6] + Inst SIZE_0_ SIZE[0] + Inst SM_AMIGA_ns_i_0_a2_2_ SM_AMIGA_ns_i_0_a2[2] + Inst SIZE_1_ SIZE[1] + Inst state_machine_un8_clk_000_d2_i state_machine.un8_clk_000_d2_i + Inst A_16_ A[16] + Inst SM_AMIGA_ns_i_0_a2_0_1_ SM_AMIGA_ns_i_0_a2_0[1] + Inst A_17_ A[17] + Inst SM_AMIGA_i_7_ SM_AMIGA_i[7] + Inst A_18_ A[18] + Inst SM_AMIGA_ns_i_0_a2_1_ SM_AMIGA_ns_i_0_a2[1] + Inst A_19_ A[19] + Inst A_20_ A[20] + Inst A_21_ A[21] + Inst A_22_ A[22] + Inst A_23_ A[23] + Inst A_24_ A[24] + Inst A_25_ A[25] + Inst A_26_ A[26] + Inst A_27_ A[27] + Inst A_28_ A[28] + Inst un1_as_000_dma5_0_a2_0_0_ un1_as_000_dma5_0_a2_0[0] + Inst A_29_ A[29] + Inst A_30_ A[30] + Inst state_machine_A0_DMA_4_0_a2_1 state_machine.A0_DMA_4_0_a2_1 + Inst A_31_ A[31] + Inst SM_AMIGA_ns_0_a2_0_0_ SM_AMIGA_ns_0_a2_0[0] + Inst SM_AMIGA_ns_0_a2_0_ SM_AMIGA_ns_0_a2[0] + Inst state_machine_DS_000_DMA_5_iv_0_a2 state_machine.DS_000_DMA_5_iv_0_a2 + Inst SM_AMIGA_ns_0_a2_0_7_ SM_AMIGA_ns_0_a2_0[7] + Inst SM_AMIGA_ns_0_a2_7_ SM_AMIGA_ns_0_a2[7] + Inst SM_AMIGA_ns_i_i_a2_0_6_ SM_AMIGA_ns_i_i_a2_0[6] + Inst SM_AMIGA_ns_i_i_a2_6_ SM_AMIGA_ns_i_i_a2[6] + Inst SM_AMIGA_ns_0_a2_5_ SM_AMIGA_ns_0_a2[5] + Inst SM_AMIGA_i_4_ SM_AMIGA_i[4] + Inst SM_AMIGA_ns_0_5_ SM_AMIGA_ns_0[5] + Inst SM_AMIGA_ns_i_0_3_ SM_AMIGA_ns_i_0[3] + Inst SM_AMIGA_ns_i_0_2_ SM_AMIGA_ns_i_0[2] + Inst IPL_030_0_ IPL_030[0] + Inst SM_AMIGA_ns_i_0_1_ SM_AMIGA_ns_i_0[1] + Inst IPL_030_1_ IPL_030[1] + Inst state_machine_LDS_000_INT_5_0 state_machine.LDS_000_INT_5_0 + Inst IPL_030_2_ IPL_030[2] + Inst state_machine_UDS_000_INT_5_0 state_machine.UDS_000_INT_5_0 + Inst IPL_0_ IPL[0] + Inst IPL_1_ IPL[1] Inst IPL_2_ IPL[2] - Inst AS_000_INT_0_r AS_000_INT_0.r Inst DSACK_0_ DSACK[0] - Inst AS_000_INT_0_m AS_000_INT_0.m Inst DSACK_1_ DSACK[1] - Inst AS_000_INT_0_n AS_000_INT_0.n - Inst AS_000_INT_0_p AS_000_INT_0.p + Inst state_machine_un10_bg_030_0 state_machine.un10_bg_030_0 + Inst state_machine_un6_bgack_000_0 state_machine.un6_bgack_000_0 + Inst AMIGA_BUS_DATA_DIR_m1_0_x2 AMIGA_BUS_DATA_DIR.m1_0_x2 + Inst SM_AMIGA_ns_i_0_o2_1_ SM_AMIGA_ns_i_0_o2[1] + Inst state_machine_UDS_000_INT_5_0_o2 state_machine.UDS_000_INT_5_0_o2 + Inst SM_AMIGA_ns_i_i_o2_6_ SM_AMIGA_ns_i_i_o2[6] + Inst FC_0_ FC[0] + Inst un1_as_000_dma5_0_o2_0_ un1_as_000_dma5_0_o2[0] + Inst FC_1_ FC[1] + Inst clk_un3_clk_000_d1_0_o2 clk.un3_clk_000_d1_0_o2 + Inst state_machine_un15_clk_000_d0_0_a2_0_1 state_machine.un15_clk_000_d0_0_a2_0_1 + Inst state_machine_UDS_000_INT_5_0_m2_r state_machine.UDS_000_INT_5_0_m2.r + Inst state_machine_un15_clk_000_d0_0_a2_0 state_machine.un15_clk_000_d0_0_a2_0 + Inst state_machine_UDS_000_INT_5_0_m2_m state_machine.UDS_000_INT_5_0_m2.m + Inst state_machine_un15_clk_000_d0_0_a2_1 state_machine.un15_clk_000_d0_0_a2_1 + Inst state_machine_UDS_000_INT_5_0_m2_n state_machine.UDS_000_INT_5_0_m2.n + Inst state_machine_un15_clk_000_d0_0_a2 state_machine.un15_clk_000_d0_0_a2 + Inst state_machine_UDS_000_INT_5_0_m2_p state_machine.UDS_000_INT_5_0_m2.p + Inst state_machine_DS_000_DMA_5_iv_0 state_machine.DS_000_DMA_5_iv_0 + Inst SM_AMIGA_ns_0_7_ SM_AMIGA_ns_0[7] + Inst SM_AMIGA_ns_i_i_6_ SM_AMIGA_ns_i_i[6] + Inst state_machine_un8_clk_000_d2_1 state_machine.un8_clk_000_d2_1 + Inst SM_AMIGA_ns_i_0_4_ SM_AMIGA_ns_i_0[4] + Inst state_machine_un8_clk_000_d2 state_machine.un8_clk_000_d2 + Inst cpu_est_ns_i_0_3_ cpu_est_ns_i_0[3] + Inst SM_AMIGA_ns_0_1_0_ SM_AMIGA_ns_0_1[0] + Inst cpu_est_ns_0_0_2_ cpu_est_ns_0_0[2] + Inst SM_AMIGA_ns_0_0_ SM_AMIGA_ns_0[0] + Inst cpu_est_ns_0_0_1_1_ cpu_est_ns_0_0_1[1] + Inst cpu_est_i_3_ cpu_est_i[3] + Inst cpu_est_ns_0_0_1_ cpu_est_ns_0_0[1] + Inst cpu_est_ns_i_0_o2_3_ cpu_est_ns_i_0_o2[3] + Inst SM_AMIGA_ns_0_a2_0_1_5_ SM_AMIGA_ns_0_a2_0_1[5] + Inst SM_AMIGA_i_3_ SM_AMIGA_i[3] + Inst SM_AMIGA_ns_0_a2_0_5_ SM_AMIGA_ns_0_a2_0[5] + Inst SM_AMIGA_ns_i_0_o2_4_ SM_AMIGA_ns_i_0_o2[4] + Inst state_machine_LDS_000_INT_5_0_a2_1 state_machine.LDS_000_INT_5_0_a2_1 + Inst cpu_est_ns_0_0_x2_1_ cpu_est_ns_0_0_x2[1] + Inst state_machine_LDS_000_INT_5_0_a2 state_machine.LDS_000_INT_5_0_a2 + Inst cpu_est_i_0_ cpu_est_i[0] + Inst state_machine_A0_DMA_4_0_a2_1_0 state_machine.A0_DMA_4_0_a2_1_0 + Inst cpu_est_ns_0_0_m2_2__r cpu_est_ns_0_0_m2_2_.r + Inst state_machine_A0_DMA_4_0_a2 state_machine.A0_DMA_4_0_a2 + Inst cpu_est_ns_0_0_m2_2__m cpu_est_ns_0_0_m2_2_.m + Inst cpu_est_ns_0_0_m2_2__n cpu_est_ns_0_0_m2_2_.n + Inst cpu_est_ns_0_0_m2_2__p cpu_est_ns_0_0_m2_2_.p + Inst state_machine_un10_bg_030_0_a2_1 state_machine.un10_bg_030_0_a2_1 + Inst state_machine_un10_bg_030_0_a2_2 state_machine.un10_bg_030_0_a2_2 + Inst state_machine_un10_bg_030_0_a2 state_machine.un10_bg_030_0_a2 + Inst SM_AMIGA_ns_i_0_a2_4_ SM_AMIGA_ns_i_0_a2[4] + Inst SM_AMIGA_ns_i_0_a2_0_4_ SM_AMIGA_ns_i_0_a2_0[4] + Inst cpu_est_ns_i_0_a2_3_ cpu_est_ns_i_0_a2[3] + Inst cpu_est_ns_0_0_a2_2_ cpu_est_ns_0_0_a2[2] + Inst cpu_est_ns_0_0_a2_1_ cpu_est_ns_0_0_a2[1] + Inst cpu_est_ns_i_0_a2_0_3_ cpu_est_ns_i_0_a2_0[3] + Inst cpu_est_i_1_ cpu_est_i[1] + Inst cpu_est_ns_0_0_a2_0_1_ cpu_est_ns_0_0_a2_0[1] + Inst state_machine_un15_clk_000_d0_0 state_machine.un15_clk_000_d0_0 + Inst A_i_24_ A_i[24] + Inst A_i_25_ A_i[25] + Inst A_i_26_ A_i[26] + Inst A_i_27_ A_i[27] + Inst A_i_28_ A_i[28] + Inst A_i_29_ A_i[29] + Inst A_i_30_ A_i[30] + Inst A_i_31_ A_i[31] + Inst cpu_est_ns_0_0_i_2_ cpu_est_ns_0_0_i[2] + Inst un4_clk_cnt_n_i_1_ un4_clk_cnt_n_i[1] + Inst un2_clk_cnt_p_i_1_ un2_clk_cnt_p_i[1] + Inst cpu_est_ns_0_0_i_1_ cpu_est_ns_0_0_i[1] + Inst clk_un12_clk_cnt_p clk.un12_clk_cnt_p + Inst AMIGA_BUS_ENABLE_0_r AMIGA_BUS_ENABLE_0.r + Inst AMIGA_BUS_ENABLE_0_m AMIGA_BUS_ENABLE_0.m + Inst AMIGA_BUS_ENABLE_0_n AMIGA_BUS_ENABLE_0.n + Inst AMIGA_BUS_ENABLE_0_p AMIGA_BUS_ENABLE_0.p + Inst VMA_INT_0_r VMA_INT_0.r + Inst VMA_INT_0_m VMA_INT_0.m + Inst state_machine_un15_clk_000_d0_0_i state_machine.un15_clk_000_d0_0_i + Inst VMA_INT_0_n VMA_INT_0.n + Inst VMA_INT_0_p VMA_INT_0.p Inst IPL_030_0_0__r IPL_030_0_0_.r Inst IPL_030_0_0__m IPL_030_0_0_.m + Inst SM_AMIGA_ns_i_0_o2_i_1_ SM_AMIGA_ns_i_0_o2_i[1] Inst IPL_030_0_0__n IPL_030_0_0_.n Inst IPL_030_0_0__p IPL_030_0_0_.p Inst IPL_030_0_1__r IPL_030_0_1_.r Inst IPL_030_0_1__m IPL_030_0_1_.m Inst IPL_030_0_1__n IPL_030_0_1_.n + Inst SM_AMIGA_ns_i_0_o2_i_4_ SM_AMIGA_ns_i_0_o2_i[4] Inst IPL_030_0_1__p IPL_030_0_1_.p - Inst FC_0_ FC[0] + Inst cpu_est_ns_i_0_o2_i_3_ cpu_est_ns_i_0_o2_i[3] Inst IPL_030_0_2__r IPL_030_0_2_.r - Inst FC_1_ FC[1] Inst IPL_030_0_2__m IPL_030_0_2_.m Inst IPL_030_0_2__n IPL_030_0_2_.n Inst IPL_030_0_2__p IPL_030_0_2_.p Inst cpu_estse_0_r cpu_estse_0.r + Inst SM_AMIGA_ns_0_i_0_ SM_AMIGA_ns_0_i[0] Inst cpu_estse_0_m cpu_estse_0.m - Inst state_machine_un15_clk_000_d0_0_a3_0_1 state_machine.un15_clk_000_d0_0_a3_0_1 Inst cpu_estse_0_n cpu_estse_0.n - Inst state_machine_un15_clk_000_d0_0_a3_0 state_machine.un15_clk_000_d0_0_a3_0 Inst cpu_estse_0_p cpu_estse_0.p - Inst state_machine_un15_clk_000_d0_0_a3_1 state_machine.un15_clk_000_d0_0_a3_1 Inst cpu_estse_1_r cpu_estse_1.r - Inst state_machine_un15_clk_000_d0_0_a3 state_machine.un15_clk_000_d0_0_a3 Inst cpu_estse_1_m cpu_estse_1.m Inst cpu_estse_1_n cpu_estse_1.n Inst cpu_estse_1_p cpu_estse_1.p - Inst state_machine_un10_bg_030_0_a3_1 state_machine.un10_bg_030_0_a3_1 Inst cpu_estse_2_r cpu_estse_2.r - Inst state_machine_un10_bg_030_0_a3_2 state_machine.un10_bg_030_0_a3_2 - Inst cpu_estse_2_m cpu_estse_2.m - Inst state_machine_un10_bg_030_0_a3 state_machine.un10_bg_030_0_a3 - Inst cpu_estse_2_n cpu_estse_2.n - Inst SM_AMIGA_ns_0_1_0_ SM_AMIGA_ns_0_1[0] - Inst cpu_estse_2_p cpu_estse_2.p - Inst SM_AMIGA_ns_0_0_ SM_AMIGA_ns_0[0] - Inst state_machine_un23_clk_000_d0 state_machine.un23_clk_000_d0 - Inst cpu_est_ns_0_0_1_2_ cpu_est_ns_0_0_1[2] - Inst cpu_est_ns_0_0_2_ cpu_est_ns_0_0[2] - Inst state_machine_un6_clk_000_d5 state_machine.un6_clk_000_d5 - Inst state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3_1 state_machine.AMIGA_BUS_ENABLE_3_f0_i_a3_1 - Inst state_machine_AMIGA_BUS_ENABLE_3_f0_i_a3 state_machine.AMIGA_BUS_ENABLE_3_f0_i_a3 - Inst clk_un12_clk_cnt_p clk.un12_clk_cnt_p - Inst SM_AMIGA_ns_0_a3_0_1_7_ SM_AMIGA_ns_0_a3_0_1[7] - Inst AS_030_000_SYNC_0_r AS_030_000_SYNC_0.r - Inst SM_AMIGA_ns_0_a3_0_7_ SM_AMIGA_ns_0_a3_0[7] - Inst AS_030_000_SYNC_0_m AS_030_000_SYNC_0.m - Inst state_machine_LDS_000_INT_5_0_a3_1 state_machine.LDS_000_INT_5_0_a3_1 - Inst AS_030_000_SYNC_0_n AS_030_000_SYNC_0.n - Inst state_machine_LDS_000_INT_5_0_a3 state_machine.LDS_000_INT_5_0_a3 - Inst AS_030_000_SYNC_0_p AS_030_000_SYNC_0.p - Inst DTACK_SYNC_0_r DTACK_SYNC_0.r - Inst DTACK_SYNC_0_m DTACK_SYNC_0.m - Inst DTACK_SYNC_0_n DTACK_SYNC_0.n - Inst cpu_est_ns_0_0_1_1_ cpu_est_ns_0_0_1[1] - Inst DTACK_SYNC_0_p DTACK_SYNC_0.p - Inst cpu_est_ns_0_0_2_1_ cpu_est_ns_0_0_2[1] - Inst FPU_CS_INT_0_r FPU_CS_INT_0.r - Inst cpu_est_ns_0_0_1_ cpu_est_ns_0_0[1] - Inst FPU_CS_INT_0_m FPU_CS_INT_0.m - Inst FPU_CS_INT_0_n FPU_CS_INT_0.n - Inst FPU_CS_INT_0_p FPU_CS_INT_0.p - Inst DSACK_INT_0_1__r DSACK_INT_0_1_.r - Inst DSACK_INT_0_1__m DSACK_INT_0_1_.m - Inst DSACK_INT_0_1__n DSACK_INT_0_1_.n - Inst DSACK_INT_0_1__p DSACK_INT_0_1_.p - Inst AMIGA_BUS_ENABLE_0_r AMIGA_BUS_ENABLE_0.r - Inst AMIGA_BUS_ENABLE_0_m AMIGA_BUS_ENABLE_0.m - Inst state_machine_un23_clk_000_d0_i state_machine.un23_clk_000_d0_i - Inst AMIGA_BUS_ENABLE_0_n AMIGA_BUS_ENABLE_0.n - Inst AMIGA_BUS_ENABLE_0_p AMIGA_BUS_ENABLE_0.p - Inst UDS_000_INT_0_r UDS_000_INT_0.r - Inst UDS_000_INT_0_m UDS_000_INT_0.m - Inst UDS_000_INT_0_n UDS_000_INT_0.n - Inst UDS_000_INT_0_p UDS_000_INT_0.p - Inst LDS_000_INT_0_r LDS_000_INT_0.r - Inst LDS_000_INT_0_m LDS_000_INT_0.m - Inst LDS_000_INT_0_n LDS_000_INT_0.n - Inst LDS_000_INT_0_p LDS_000_INT_0.p - Inst state_machine_un8_clk_000_d2_1 state_machine.un8_clk_000_d2_1 - Inst state_machine_un8_clk_000_d2 state_machine.un8_clk_000_d2 - Inst state_machine_UDS_000_INT_5_0_i state_machine.UDS_000_INT_5_0_i - Inst state_machine_un15_clk_000_d0_0_i state_machine.un15_clk_000_d0_0_i - Inst state_machine_un10_bg_030_0_i state_machine.un10_bg_030_0_i - Inst state_machine_un6_bgack_000_0_i state_machine.un6_bgack_000_0_i - Inst SM_AMIGA_ns_0_i_7_ SM_AMIGA_ns_0_i[7] - Inst SM_AMIGA_ns_0_i_5_ SM_AMIGA_ns_0_i[5] - Inst state_machine_LDS_000_INT_5_0_i state_machine.LDS_000_INT_5_0_i - Inst SM_AMIGA_ns_0_i_0_ SM_AMIGA_ns_0_i[0] - Inst cpu_est_ns_0_0_i_2_ cpu_est_ns_0_0_i[2] - Inst SM_AMIGA_ns_i_0_o2_i_4_ SM_AMIGA_ns_i_0_o2_i[4] - Inst SM_AMIGA_ns_i_0_o2_i_1_ SM_AMIGA_ns_i_0_o2_i[1] - Inst state_machine_UDS_000_INT_5_0_o3_i state_machine.UDS_000_INT_5_0_o3_i - Inst cpu_est_ns_i_0_o2_i_3_ cpu_est_ns_i_0_o2_i[3] - Inst state_machine_AMIGA_BUS_ENABLE_3_f0_i_o2_i state_machine.AMIGA_BUS_ENABLE_3_f0_i_o2_i Inst clk_un3_clk_000_d1_0_o2_i clk.un3_clk_000_d1_0_o2_i - Inst cpu_est_ns_0_0_i_1_ cpu_est_ns_0_0_i[1] + Inst cpu_estse_2_m cpu_estse_2.m + Inst cpu_estse_2_n cpu_estse_2.n + Inst cpu_estse_2_p cpu_estse_2.p + Inst un1_as_000_dma5_0_o2_i_0_ un1_as_000_dma5_0_o2_i[0] + Inst state_machine_un6_clk_000_d5_i state_machine.un6_clk_000_d5_i + Inst SM_AMIGA_ns_i_i_o2_i_6_ SM_AMIGA_ns_i_i_o2_i[6] + Inst state_machine_UDS_000_INT_5_0_o2_i state_machine.UDS_000_INT_5_0_o2_i + Inst SM_AMIGA_ns_0_i_5_ SM_AMIGA_ns_0_i[5] + Inst SM_AMIGA_ns_i_i_i_6_ SM_AMIGA_ns_i_i_i[6] + Net sm_amiga_5__n SM_AMIGA[5] Net ipl_030_c_0__n IPL_030_c[0] + Net vcc_n_n VCC Net ipl_030_0__n IPL_030[0] + Net gnd_n_n GND Net ipl_030_c_1__n IPL_030_c[1] Net ipl_030_1__n IPL_030[1] + Net sm_amiga_6__n SM_AMIGA[6] Net ipl_030_c_2__n IPL_030_c[2] Net ipl_c_0__n IPL_c[0] Net ipl_0__n IPL[0] Net ipl_c_1__n IPL_c[1] + Net state_machine_un23_clk_000_d0_n state_machine.un23_clk_000_d0 Net ipl_1__n IPL[1] Net ipl_c_2__n IPL_c[2] - Net sm_amiga_5__n SM_AMIGA[5] - Net sm_amiga_6__n SM_AMIGA[6] - Net dsack_0__n DSACK[0] - Net vcc_n_n VCC - Net dsack_c_1__n DSACK_c[1] - Net gnd_n_n GND - Net dsack_int_1__n DSACK_INT[1] - Net state_machine_un8_clk_000_d2_n state_machine.un8_clk_000_d2 - Net sm_amiga_4__n SM_AMIGA[4] - Net state_machine_un23_clk_000_d0_n state_machine.un23_clk_000_d0 - Net state_machine_un6_clk_000_d5_n state_machine.un6_clk_000_d5 - Net sm_amiga_7__n SM_AMIGA[7] Net sm_amiga_3__n SM_AMIGA[3] - Net state_machine_un6_bgack_000_n state_machine.un6_bgack_000 + Net sm_amiga_0__n SM_AMIGA[0] + Net dsack_0__n DSACK[0] Net sm_amiga_1__n SM_AMIGA[1] - Net fc_c_0__n FC_c[0] + Net dsack_c_1__n DSACK_c[1] + Net size_dma_0__n SIZE_DMA[0] + Net size_dma_1__n SIZE_DMA[1] Net un4_clk_cnt_n_1__n un4_clk_cnt_n[1] - Net fc_0__n FC[0] Net clk_cnt_n_0__n CLK_CNT_N[0] - Net fc_c_1__n FC_c[1] Net clk_cnt_n_1__n CLK_CNT_N[1] Net un2_clk_cnt_p_1__n un2_clk_cnt_p[1] Net clk_cnt_p_0__n CLK_CNT_P[0] Net clk_cnt_p_1__n CLK_CNT_P[1] - Net sm_amiga_2__n SM_AMIGA[2] - Net sm_amiga_0__n SM_AMIGA[0] - Net state_machine_un10_bg_030_n state_machine.un10_bg_030 - Net cpu_est_ns_0_1__n cpu_est_ns_0[1] - Net state_machine_un7_as_000_int_n state_machine.un7_as_000_int + Net sm_amiga_7__n SM_AMIGA[7] Net state_machine_un15_clk_000_d0_n state_machine.un15_clk_000_d0 - Net state_machine_lds_000_int_5_n state_machine.LDS_000_INT_5 - Net state_machine_uds_000_int_5_n state_machine.UDS_000_INT_5 - Net cpu_est_ns_e_0_0__n cpu_est_ns_e_0[0] + Net sm_amiga_4__n SM_AMIGA[4] + Net fc_c_0__n FC_c[0] + Net fc_0__n FC[0] + Net sm_amiga_2__n SM_AMIGA[2] + Net fc_c_1__n FC_c[1] + Net state_machine_un23_clk_000_d0_0_n state_machine.un23_clk_000_d0_0 + Net state_machine_un6_bgack_000_0_n state_machine.un6_bgack_000_0 + Net state_machine_un10_bg_030_0_n state_machine.un10_bg_030_0 + Net state_machine_uds_000_int_5_0_n state_machine.UDS_000_INT_5_0 Net sm_amiga_ns_0__n SM_AMIGA_ns[0] + Net state_machine_lds_000_int_5_0_n state_machine.LDS_000_INT_5_0 Net sm_amiga_ns_5__n SM_AMIGA_ns[5] Net sm_amiga_ns_7__n SM_AMIGA_ns[7] - Net sm_amiga_ns_0_0__n SM_AMIGA_ns_0[0] Net cpu_est_0__n cpu_est[0] Net cpu_est_1__n cpu_est[1] Net cpu_est_2__n cpu_est[2] Net cpu_est_3__n cpu_est[3] - Net cpu_est_ns_0_2__n cpu_est_ns_0[2] Net cpu_est_ns_e_0__n cpu_est_ns_e[0] Net cpu_est_ns_e_1__n cpu_est_ns_e[1] Net cpu_est_ns_e_2__n cpu_est_ns_e[2] Net cpu_est_ns_e_3__n cpu_est_ns_e[3] + Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5] Net cpu_est_ns_1__n cpu_est_ns[1] Net cpu_est_ns_2__n cpu_est_ns[2] Net sm_amiga_ns_0_7__n SM_AMIGA_ns_0[7] - Net sm_amiga_ns_0_5__n SM_AMIGA_ns_0[5] - Net state_machine_lds_000_int_5_0_n state_machine.LDS_000_INT_5_0 - Net state_machine_uds_000_int_5_0_n state_machine.UDS_000_INT_5_0 - Net state_machine_un15_clk_000_d0_0_n state_machine.un15_clk_000_d0_0 - Net state_machine_un10_bg_030_0_n state_machine.un10_bg_030_0 - Net state_machine_un6_bgack_000_0_n state_machine.un6_bgack_000_0 - Net clk_un12_clk_cnt_p_i_n clk.un12_clk_cnt_p_i - Net state_machine_un23_clk_000_d0_0_n state_machine.un23_clk_000_d0_0 - Net state_machine_un8_clk_000_d2_1_n state_machine.un8_clk_000_d2_1 - Net cpu_est_ns_0_1_1__n cpu_est_ns_0_1[1] - Net cpu_est_ns_0_2_1__n cpu_est_ns_0_2[1] - Net sm_amiga_i_4__n SM_AMIGA_i[4] - Net cpu_est_i_3__n cpu_est_i[3] - Net sm_amiga_i_1__n SM_AMIGA_i[1] - Net sm_amiga_ns_0_1_0__n SM_AMIGA_ns_0_1[0] + Net state_machine_ds_000_dma_5_0_n state_machine.DS_000_DMA_5_0 + Net un1_as_000_dma5_i_0__n un1_as_000_dma5_i[0] Net state_machine_un6_clk_000_d5_i_n state_machine.un6_clk_000_d5_i - Net cpu_est_ns_0_1_2__n cpu_est_ns_0_1[2] - Net sm_amiga_i_6__n SM_AMIGA_i[6] - Net cpu_est_i_1__n cpu_est_i[1] - Net cpu_est_i_0__n cpu_est_i[0] - Net state_machine_uds_000_int_5_0_m2_un3_n state_machine.UDS_000_INT_5_0_m2.un3 - Net state_machine_uds_000_int_5_0_m2_un1_n state_machine.UDS_000_INT_5_0_m2.un1 - Net cpu_est_i_2__n cpu_est_i[2] - Net state_machine_uds_000_int_5_0_m2_un0_n state_machine.UDS_000_INT_5_0_m2.un0 - Net sm_amiga_i_2__n SM_AMIGA_i[2] - Net vpa_sync_0_un3_n VPA_SYNC_0.un3 - Net sm_amiga_i_3__n SM_AMIGA_i[3] - Net vpa_sync_0_un1_n VPA_SYNC_0.un1 + Net cpu_est_ns_e_0_0__n cpu_est_ns_e_0[0] + Net sm_amiga_ns_0_0__n SM_AMIGA_ns_0[0] + Net cpu_est_ns_0_2__n cpu_est_ns_0[2] + Net cpu_est_ns_0_1__n cpu_est_ns_0[1] + Net state_machine_un6_clk_000_d5_n state_machine.un6_clk_000_d5 + Net un1_as_000_dma5_0__n un1_as_000_dma5[0] + Net state_machine_un15_clk_000_d0_0_n state_machine.un15_clk_000_d0_0 + Net state_machine_ds_000_dma_5_n state_machine.DS_000_DMA_5 + Net clk_un12_clk_cnt_p_i_n clk.un12_clk_cnt_p_i + Net state_machine_lds_000_int_5_n state_machine.LDS_000_INT_5 + Net state_machine_uds_000_int_5_n state_machine.UDS_000_INT_5 + Net state_machine_un10_bg_030_n state_machine.un10_bg_030 + Net state_machine_un6_bgack_000_n state_machine.un6_bgack_000 + Net state_machine_un8_clk_000_d2_n state_machine.un8_clk_000_d2 + Net state_machine_un8_clk_000_d2_1_n state_machine.un8_clk_000_d2_1 + Net sm_amiga_ns_0_1_0__n SM_AMIGA_ns_0_1[0] Net sm_amiga_i_5__n SM_AMIGA_i[5] - Net vpa_sync_0_un0_n VPA_SYNC_0.un0 - Net state_machine_un8_clk_000_d2_i_n state_machine.un8_clk_000_d2_i - Net vma_int_0_un3_n VMA_INT_0.un3 - Net sm_amiga_i_7__n SM_AMIGA_i[7] - Net vma_int_0_un1_n VMA_INT_0.un1 - Net a_i_0__n A_i[0] - Net vma_int_0_un0_n VMA_INT_0.un0 - Net size_i_1__n SIZE_i[1] - Net bg_000_0_un3_n BG_000_0.un3 - Net dsack_i_1__n DSACK_i[1] - Net bg_000_0_un1_n BG_000_0.un1 - Net bg_000_0_un0_n BG_000_0.un0 - Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 - Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1 - Net a_i_19__n A_i[19] - Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0 - Net a_i_16__n A_i[16] - Net as_000_int_0_un3_n AS_000_INT_0.un3 + Net cpu_est_ns_0_1_1__n cpu_est_ns_0_1[1] Net a_i_18__n A_i[18] + Net a_i_16__n A_i[16] + Net vpa_sync_0_un3_n VPA_SYNC_0.un3 + Net a_i_19__n A_i[19] + Net vpa_sync_0_un1_n VPA_SYNC_0.un1 + Net vpa_sync_0_un0_n VPA_SYNC_0.un0 + Net as_000_int_0_un3_n AS_000_INT_0.un3 Net as_000_int_0_un1_n AS_000_INT_0.un1 - Net a_i_30__n A_i[30] Net as_000_int_0_un0_n AS_000_INT_0.un0 - Net a_i_31__n A_i[31] - Net ipl_030_0_0__un3_n IPL_030_0_0_.un3 - Net a_i_28__n A_i[28] - Net ipl_030_0_0__un1_n IPL_030_0_0_.un1 - Net a_i_29__n A_i[29] - Net ipl_030_0_0__un0_n IPL_030_0_0_.un0 - Net a_i_26__n A_i[26] - Net ipl_030_0_1__un3_n IPL_030_0_1_.un3 - Net a_i_27__n A_i[27] - Net ipl_030_0_1__un1_n IPL_030_0_1_.un1 - Net a_i_24__n A_i[24] - Net ipl_030_0_1__un0_n IPL_030_0_1_.un0 - Net a_i_25__n A_i[25] - Net ipl_030_0_2__un3_n IPL_030_0_2_.un3 - Net ipl_030_0_2__un1_n IPL_030_0_2_.un1 - Net state_machine_un7_as_000_int_i_n state_machine.un7_as_000_int_i - Net ipl_030_0_2__un0_n IPL_030_0_2_.un0 - Net un2_clk_cnt_p_i_1__n un2_clk_cnt_p_i[1] - Net cpu_estse_0_un3_n cpu_estse_0.un3 - Net cpu_estse_0_un1_n cpu_estse_0.un1 - Net un4_clk_cnt_n_i_1__n un4_clk_cnt_n_i[1] - Net cpu_estse_0_un0_n cpu_estse_0.un0 - Net cpu_estse_1_un3_n cpu_estse_1.un3 - Net cpu_estse_1_un1_n cpu_estse_1.un1 - Net cpu_estse_1_un0_n cpu_estse_1.un0 - Net cpu_estse_2_un3_n cpu_estse_2.un3 - Net cpu_estse_2_un1_n cpu_estse_2.un1 - Net cpu_estse_2_un0_n cpu_estse_2.un0 - Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3 - Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1 - Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0 + Net as_000_dma_0_un3_n AS_000_DMA_0.un3 + Net as_000_dma_0_un1_n AS_000_DMA_0.un1 + Net sm_amiga_i_7__n SM_AMIGA_i[7] + Net as_000_dma_0_un0_n AS_000_DMA_0.un0 + Net state_machine_un8_clk_000_d2_i_n state_machine.un8_clk_000_d2_i + Net bg_000_0_un3_n BG_000_0.un3 + Net sm_amiga_i_6__n SM_AMIGA_i[6] + Net bg_000_0_un1_n BG_000_0.un1 + Net sm_amiga_i_4__n SM_AMIGA_i[4] + Net bg_000_0_un0_n BG_000_0.un0 + Net a0_dma_0_un3_n A0_DMA_0.un3 + Net a0_dma_0_un1_n A0_DMA_0.un1 + Net a0_dma_0_un0_n A0_DMA_0.un0 Net dtack_sync_0_un3_n DTACK_SYNC_0.un3 Net dtack_sync_0_un1_n DTACK_SYNC_0.un1 - Net size_c_0__n SIZE_c[0] Net dtack_sync_0_un0_n DTACK_SYNC_0.un0 - Net size_0__n SIZE[0] - Net fpu_cs_int_0_un3_n FPU_CS_INT_0.un3 - Net size_c_1__n SIZE_c[1] - Net fpu_cs_int_0_un1_n FPU_CS_INT_0.un1 - Net fpu_cs_int_0_un0_n FPU_CS_INT_0.un0 - Net a_c_0__n A_c[0] - Net dsack_int_0_1__un3_n DSACK_INT_0_1_.un3 - Net a_0__n A[0] - Net dsack_int_0_1__un1_n DSACK_INT_0_1_.un1 - Net dsack_int_0_1__un0_n DSACK_INT_0_1_.un0 - Net amiga_bus_enable_0_un3_n AMIGA_BUS_ENABLE_0.un3 - Net amiga_bus_enable_0_un1_n AMIGA_BUS_ENABLE_0.un1 - Net amiga_bus_enable_0_un0_n AMIGA_BUS_ENABLE_0.un0 + Net lds_000_int_0_un3_n LDS_000_INT_0.un3 + Net cpu_est_i_0__n cpu_est_i[0] + Net lds_000_int_0_un1_n LDS_000_INT_0.un1 + Net sm_amiga_i_3__n SM_AMIGA_i[3] + Net lds_000_int_0_un0_n LDS_000_INT_0.un0 + Net cpu_est_i_3__n cpu_est_i[3] Net uds_000_int_0_un3_n UDS_000_INT_0.un3 + Net cpu_est_i_1__n cpu_est_i[1] Net uds_000_int_0_un1_n UDS_000_INT_0.un1 Net uds_000_int_0_un0_n UDS_000_INT_0.un0 - Net lds_000_int_0_un3_n LDS_000_INT_0.un3 - Net lds_000_int_0_un1_n LDS_000_INT_0.un1 - Net lds_000_int_0_un0_n LDS_000_INT_0.un0 - Net a_15__n A[15] - Net a_14__n A[14] - Net a_13__n A[13] + Net size_i_1__n SIZE_i[1] + Net fpu_cs_int_0_un3_n FPU_CS_INT_0.un3 + Net a_i_30__n A_i[30] + Net fpu_cs_int_0_un1_n FPU_CS_INT_0.un1 + Net a_i_31__n A_i[31] + Net fpu_cs_int_0_un0_n FPU_CS_INT_0.un0 + Net a_i_28__n A_i[28] + Net ds_000_dma_0_un3_n DS_000_DMA_0.un3 + Net a_i_29__n A_i[29] + Net ds_000_dma_0_un1_n DS_000_DMA_0.un1 + Net a_i_26__n A_i[26] + Net ds_000_dma_0_un0_n DS_000_DMA_0.un0 + Net a_i_27__n A_i[27] + Net as_030_000_sync_0_un3_n AS_030_000_SYNC_0.un3 + Net a_i_24__n A_i[24] + Net as_030_000_sync_0_un1_n AS_030_000_SYNC_0.un1 + Net a_i_25__n A_i[25] + Net as_030_000_sync_0_un0_n AS_030_000_SYNC_0.un0 + Net size_dma_0_1__un3_n SIZE_DMA_0_1_.un3 + Net un2_clk_cnt_p_i_1__n un2_clk_cnt_p_i[1] + Net size_dma_0_1__un1_n SIZE_DMA_0_1_.un1 + Net size_dma_0_1__un0_n SIZE_DMA_0_1_.un0 + Net un4_clk_cnt_n_i_1__n un4_clk_cnt_n_i[1] + Net size_dma_0_0__un3_n SIZE_DMA_0_0_.un3 + Net size_dma_0_0__un1_n SIZE_DMA_0_0_.un1 + Net size_dma_0_0__un0_n SIZE_DMA_0_0_.un0 + Net bgack_030_int_0_un3_n BGACK_030_INT_0.un3 + Net bgack_030_int_0_un1_n BGACK_030_INT_0.un1 + Net bgack_030_int_0_un0_n BGACK_030_INT_0.un0 + Net dsack1_int_0_un3_n DSACK1_INT_0.un3 + Net dsack1_int_0_un1_n DSACK1_INT_0.un1 + Net dsack1_int_0_un0_n DSACK1_INT_0.un0 + Net state_machine_uds_000_int_5_0_m2_un3_n state_machine.UDS_000_INT_5_0_m2.un3 + Net state_machine_uds_000_int_5_0_m2_un1_n state_machine.UDS_000_INT_5_0_m2.un1 + Net state_machine_uds_000_int_5_0_m2_un0_n state_machine.UDS_000_INT_5_0_m2.un0 + Net size_c_0__n SIZE_c[0] + Net cpu_est_ns_0_0_m2_2__un3_n cpu_est_ns_0_0_m2_2_.un3 + Net size_0__n SIZE[0] + Net cpu_est_ns_0_0_m2_2__un1_n cpu_est_ns_0_0_m2_2_.un1 + Net size_c_1__n SIZE_c[1] + Net cpu_est_ns_0_0_m2_2__un0_n cpu_est_ns_0_0_m2_2_.un0 + Net amiga_bus_enable_0_un3_n AMIGA_BUS_ENABLE_0.un3 Net a_c_16__n A_c[16] + Net amiga_bus_enable_0_un1_n AMIGA_BUS_ENABLE_0.un1 Net a_16__n A[16] - Net a_12__n A[12] + Net amiga_bus_enable_0_un0_n AMIGA_BUS_ENABLE_0.un0 Net a_c_17__n A_c[17] + Net vma_int_0_un3_n VMA_INT_0.un3 Net a_17__n A[17] - Net a_11__n A[11] + Net vma_int_0_un1_n VMA_INT_0.un1 Net a_c_18__n A_c[18] + Net vma_int_0_un0_n VMA_INT_0.un0 Net a_18__n A[18] - Net a_10__n A[10] + Net ipl_030_0_0__un3_n IPL_030_0_0_.un3 Net a_c_19__n A_c[19] + Net ipl_030_0_0__un1_n IPL_030_0_0_.un1 Net a_19__n A[19] - Net a_9__n A[9] + Net ipl_030_0_0__un0_n IPL_030_0_0_.un0 Net a_c_20__n A_c[20] + Net ipl_030_0_1__un3_n IPL_030_0_1_.un3 Net a_20__n A[20] - Net a_8__n A[8] + Net ipl_030_0_1__un1_n IPL_030_0_1_.un1 Net a_c_21__n A_c[21] + Net ipl_030_0_1__un0_n IPL_030_0_1_.un0 Net a_21__n A[21] - Net a_7__n A[7] + Net ipl_030_0_2__un3_n IPL_030_0_2_.un3 Net a_c_22__n A_c[22] + Net ipl_030_0_2__un1_n IPL_030_0_2_.un1 Net a_22__n A[22] - Net a_6__n A[6] + Net ipl_030_0_2__un0_n IPL_030_0_2_.un0 Net a_c_23__n A_c[23] + Net cpu_estse_0_un3_n cpu_estse_0.un3 Net a_23__n A[23] - Net a_5__n A[5] + Net cpu_estse_0_un1_n cpu_estse_0.un1 Net a_c_24__n A_c[24] + Net cpu_estse_0_un0_n cpu_estse_0.un0 Net a_24__n A[24] - Net a_4__n A[4] + Net cpu_estse_1_un3_n cpu_estse_1.un3 Net a_c_25__n A_c[25] + Net cpu_estse_1_un1_n cpu_estse_1.un1 Net a_25__n A[25] - Net a_3__n A[3] + Net cpu_estse_1_un0_n cpu_estse_1.un0 Net a_c_26__n A_c[26] + Net cpu_estse_2_un3_n cpu_estse_2.un3 Net a_26__n A[26] - Net a_2__n A[2] + Net cpu_estse_2_un1_n cpu_estse_2.un1 Net a_c_27__n A_c[27] + Net cpu_estse_2_un0_n cpu_estse_2.un0 Net a_27__n A[27] - Net a_1__n A[1] Net a_c_28__n A_c[28] Net a_28__n A[28] Net a_c_29__n A_c[29] @@ -518,12 +521,9 @@ Design 'BUS68030' created Sat May 24 19:56:20 2014 End Section Type Name // ---------------------------------------------------------------------- - Input SIZE_1_ Input A_31_ Input IPL_2_ Input FC_1_ - Input AS_030 - Input DS_030 Input nEXP_SPACE Input BG_030 Input BGACK_000 @@ -533,7 +533,6 @@ Section Type Name Input VPA Input RST Input RW - Input SIZE_0_ Input A_30_ Input A_29_ Input A_28_ @@ -549,29 +548,10 @@ Section Type Name Input A_18_ Input A_17_ Input A_16_ - Input A_15_ - Input A_14_ - Input A_13_ - Input A_12_ - Input A_11_ - Input A_10_ - Input A_9_ - Input A_8_ - Input A_7_ - Input A_6_ - Input A_5_ - Input A_4_ - Input A_3_ - Input A_2_ - Input A_1_ - Input A_0_ Input IPL_1_ Input IPL_0_ Input FC_0_ Output IPL_030_2_ - Output AS_000 - Output UDS_000 - Output LDS_000 Output BERR Output BG_000 Output BGACK_030 @@ -589,7 +569,15 @@ Section Type Name Output CIIN Output IPL_030_1_ Output IPL_030_0_ + Bidi SIZE_1_ Bidi DSACK_1_ + Bidi AS_030 + Bidi AS_000 + Bidi DS_030 + Bidi UDS_000 + Bidi LDS_000 + Bidi A0 Bidi DTACK + Bidi SIZE_0_ Bidi DSACK_0_ End diff --git a/Logic/bus68030.srf b/Logic/bus68030.srf index 231b78a..d807336 100644 --- a/Logic/bus68030.srf +++ b/Logic/bus68030.srf @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Sat May 24 19:56:13 2014 +#Sat May 24 21:59:07 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode @@ -18,14 +18,9 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - VHDL syntax check successful! File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:7:113:15|Signal clk_030_d is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Pruning register CLK_REF(1 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Pruning register cpu_est_d(3 downto 0) -@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Feedback mux created for signal AMIGA_BUS_ENABLE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. -@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Pruning register bit 0 of DSACK_INT(1 downto 0) -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":219:2:219:3|Pruning register CLK_REF(1 downto 0) +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":219:2:219:3|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -36,8 +31,7 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Initial value is not supported on state machine SM_AMIGA -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":115:34:115:36|Trying to extract state machine for register cpu_est Extracted state machine for register cpu_est State machine has 11 reachable states with original encodings of: 0000 @@ -51,10 +45,9 @@ State machine has 11 reachable states with original encodings of: 1011 1100 1111 -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Initial value is not supported on state machine cpu_est @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat May 24 19:56:13 2014 +# Sat May 24 21:59:08 2014 ###########################################################] Map & Optimize Report @@ -63,6 +56,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 621R, Built Mar 19 2013 Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version G-2012.09LC-SP1 @N: MF248 |Running in 64-bit mode. +@W: MO111 :|Tristate driver DSACK_tri on net DSACK[0] has its enable tied to GND (module BUS68030) Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral)) original code -> new code 000 -> 00000001 @@ -91,16 +85,15 @@ Resource Usage Report Simple gate primitives: DFFRH 17 uses -DFFSH 25 uses -DFF 1 use -IBUF 35 uses -BUFTH 7 uses +DFFSH 30 uses +BI_DIR 10 uses +IBUF 30 uses +BUFTH 4 uses OBUF 15 uses -BI_DIR 2 uses -AND2 148 uses -INV 131 uses -OR2 19 uses -XOR2 2 uses +AND2 170 uses +INV 145 uses +OR2 25 uses +XOR2 4 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -110,6 +103,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat May 24 19:56:15 2014 +# Sat May 24 21:59:09 2014 ###########################################################] diff --git a/Logic/dm/BUS68030_compiler.xdm b/Logic/dm/BUS68030_compiler.xdm index 446166e..6d06262 100644 --- a/Logic/dm/BUS68030_compiler.xdm +++ b/Logic/dm/BUS68030_compiler.xdm @@ -26,7 +26,6 @@ S7RCVMI="F3s Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S> SRSqS SRSqSSqS"/ diff --git a/Logic/lattice_cmd.rs2 b/Logic/lattice_cmd.rs2 index edaada4..5395962 100644 --- a/Logic/lattice_cmd.rs2 +++ b/Logic/lattice_cmd.rs2 @@ -1 +1 @@ --src 68030_tk.tt4 -type PLA -devfile "C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447ace.dev" -postfit -lci 68030_tk.lco +-src 68030_tk.tt4 -type PLA -devfile "C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447ace.dev" -lci "68030_tk.lct" -touch "68030_tk.tt4" diff --git a/Logic/run_options.txt b/Logic/run_options.txt index 9a39d84..70fdf50 100644 --- a/Logic/run_options.txt +++ b/Logic/run_options.txt @@ -1,7 +1,7 @@ #-- Synopsys, Inc. #-- Version G-2012.09LC-SP1 #-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt -#-- Written on Sat May 24 19:56:13 2014 +#-- Written on Sat May 24 21:59:07 2014 #project files diff --git a/Logic/synlog.tcl b/Logic/synlog.tcl new file mode 100644 index 0000000..c809b86 --- /dev/null +++ b/Logic/synlog.tcl @@ -0,0 +1,2 @@ +source "C:/Users/Matze/AppData/Local/Synplicity/scm_perforce.tcl" +history clear diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr index f008fbf..31f9e91 100644 --- a/Logic/synlog/bus68030_fpga_mapper.srr +++ b/Logic/synlog/bus68030_fpga_mapper.srr @@ -2,6 +2,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 621R, Built Mar 19 2013 Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version G-2012.09LC-SP1 @N: MF248 |Running in 64-bit mode. +@W: MO111 :|Tristate driver DSACK_tri on net DSACK[0] has its enable tied to GND (module BUS68030) Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral)) original code -> new code 000 -> 00000001 @@ -30,16 +31,15 @@ Resource Usage Report Simple gate primitives: DFFRH 17 uses -DFFSH 25 uses -DFF 1 use -IBUF 35 uses -BUFTH 7 uses +DFFSH 30 uses +BI_DIR 10 uses +IBUF 30 uses +BUFTH 4 uses OBUF 15 uses -BI_DIR 2 uses -AND2 148 uses -INV 131 uses -OR2 19 uses -XOR2 2 uses +AND2 170 uses +INV 145 uses +OR2 25 uses +XOR2 4 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -49,6 +49,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sat May 24 19:56:15 2014 +# Sat May 24 21:59:09 2014 ###########################################################] diff --git a/Logic/synlog/report/BUS68030_compiler_errors.txt b/Logic/synlog/report/BUS68030_compiler_errors.txt index 42beacf..f63bd62 100644 --- a/Logic/synlog/report/BUS68030_compiler_errors.txt +++ b/Logic/synlog/report/BUS68030_compiler_errors.txt @@ -1,3 +1,3 @@ -@E: CD415 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":391:6:391:7|Expecting keyword process +@E: CD200 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":426:5:426:13|Misspelled variable, signal or procedure name? @E|Parse errors encountered - exiting diff --git a/Logic/synlog/report/BUS68030_compiler_notes.txt b/Logic/synlog/report/BUS68030_compiler_notes.txt index 4145143..e84b0df 100644 --- a/Logic/synlog/report/BUS68030_compiler_notes.txt +++ b/Logic/synlog/report/BUS68030_compiler_notes.txt @@ -2,6 +2,6 @@ @N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns @N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030. @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Trying to extract state machine for register SM_AMIGA -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":219:2:219:3|Trying to extract state machine for register SM_AMIGA +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":115:34:115:36|Trying to extract state machine for register cpu_est diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml index efe259f..e6a7f6a 100644 --- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml +++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml @@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt - 7 + 1 C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt @@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t - - 1400954173 + 1400961548 \ No newline at end of file diff --git a/Logic/synlog/report/BUS68030_compiler_warnings.txt b/Logic/synlog/report/BUS68030_compiler_warnings.txt index 0434475..6e0c75d 100644 --- a/Logic/synlog/report/BUS68030_compiler_warnings.txt +++ b/Logic/synlog/report/BUS68030_compiler_warnings.txt @@ -1,8 +1,2 @@ -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:7:113:15|Signal clk_030_d is undriven -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Pruning register CLK_REF(1 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Pruning register cpu_est_d(3 downto 0) -@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Pruning register bit 0 of DSACK_INT(1 downto 0) -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Initial value is not supported on state machine SM_AMIGA -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Initial value is not supported on state machine cpu_est +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":219:2:219:3|Pruning register CLK_REF(1 downto 0) diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml index 7858efd..af40ca9 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml +++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml @@ -18,7 +18,7 @@ The file contains the job information from mapper to be displayed as part of the -0 +1 C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_warnings.txt @@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the 95MB -1400954175 +1400961549 diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt b/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt index e69de29..0580f57 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt +++ b/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt @@ -0,0 +1 @@ +@W: MO111 :|Tristate driver DSACK_tri on net DSACK[0] has its enable tied to GND (module BUS68030) diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml index 8a83eb7..5d078fd 100644 --- a/Logic/syntmp/run_option.xml +++ b/Logic/syntmp/run_option.xml @@ -3,7 +3,7 @@ Synopsys, Inc. Version G-2012.09LC-SP1 Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml - Written on Sat May 24 19:56:13 2014 + Written on Sat May 24 21:59:07 2014 --> diff --git a/Logic/synwork/BUS68030_compiler.fdep b/Logic/synwork/BUS68030_compiler.fdep index 007fc3f..12ded59 100644 --- a/Logic/synwork/BUS68030_compiler.fdep +++ b/Logic/synwork/BUS68030_compiler.fdep @@ -10,7 +10,7 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400954168 +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400961544 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) diff --git a/Logic/synwork/BUS68030_compiler.fdeporig b/Logic/synwork/BUS68030_compiler.fdeporig index 9bfbc4e..e635b0d 100644 --- a/Logic/synwork/BUS68030_compiler.fdeporig +++ b/Logic/synwork/BUS68030_compiler.fdeporig @@ -10,7 +10,7 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400954168 +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1400961544 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) diff --git a/Logic/synwork/BUS68030_compiler.srs b/Logic/synwork/BUS68030_compiler.srs index ced07c24d37a41ffcaae76ce1a3934fee0e8447a..9646766bacbe8178db607992f26e3a3487fc768b 100644 GIT binary patch delta 8480 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:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral -@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":113:7:113:15|Signal clk_030_d is undriven Post processing for work.bus68030.behavioral -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Pruning register CLK_REF(1 downto 0) -@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Pruning register cpu_est_d(3 downto 0) -@A: CL282 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Feedback mux created for signal AMIGA_BUS_ENABLE -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. -@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Optimizing register bit DSACK_INT(0) to a constant 1 -@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:52:110:55|Pruning register bit 0 of DSACK_INT(1 downto 0) -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Trying to extract state machine for register SM_AMIGA +@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":219:2:219:3|Pruning register CLK_REF(1 downto 0) +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":219:2:219:3|Trying to extract state machine for register SM_AMIGA Extracted state machine for register SM_AMIGA State machine has 8 reachable states with original encodings of: 000 @@ -17,8 +12,7 @@ State machine has 8 reachable states with original encodings of: 101 110 111 -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":221:2:221:3|Initial value is not supported on state machine SM_AMIGA -@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Trying to extract state machine for register cpu_est +@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":115:34:115:36|Trying to extract state machine for register cpu_est Extracted state machine for register cpu_est State machine has 11 reachable states with original encodings of: 0000 @@ -32,4 +26,3 @@ State machine has 11 reachable states with original encodings of: 1011 1100 1111 -@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":112:31:112:33|Initial value is not supported on state machine cpu_est