minor clean up

This commit is contained in:
MHeinrichs 2014-05-29 22:06:01 +02:00
parent 99277e926b
commit 3060b6be03
44 changed files with 14880 additions and 526 deletions

View File

@ -6331,55 +6331,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
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@ -6795,191 +6746,6 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
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</signal>
<signal name="A27">
<wire x1="82.55" y1="69.2912" x2="75.3872" y2="69.2912" width="0.1524" layer="16"/>

View File

@ -2862,9 +2862,6 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
</element>
<element name="R14" library="rcl" package="R0603" value="" x="58.674" y="85.6488" rot="R180"/>
<element name="R16" library="rcl" package="R0603" value="" x="28.6512" y="90.3732" rot="R180"/>
<element name="R17" library="rcl" package="R0603" value="4,7k" x="80.01" y="37.6428" smashed="yes" rot="R90">
<attribute name="NAME" x="79.0702" y="36.3982" size="1.27" layer="25" rot="R90"/>
</element>
</elements>
<signals>
<signal name="D0">
@ -4281,6 +4278,10 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="48.768" y1="80.1624" x2="48.006" y2="80.9244" width="0.1524" layer="1"/>
<wire x1="55.5752" y1="76.962" x2="53.7972" y2="78.74" width="0.1524" layer="1"/>
<wire x1="53.7972" y1="78.74" x2="53.7972" y2="79.5528" width="0.1524" layer="1"/>
<contactref element="IC7" pad="42"/>
<wire x1="41.7896" y1="94.8172" x2="41.7896" y2="88.2076" width="0.1524" layer="1"/>
<wire x1="41.7896" y1="88.2076" x2="48.006" y2="81.9912" width="0.1524" layer="1"/>
<wire x1="48.006" y1="81.9912" x2="48.006" y2="80.9244" width="0.1524" layer="1"/>
<contactref element="X1" pad="C30"/>
<contactref element="IC4" pad="8"/>
<wire x1="15.24" y1="79.8322" x2="16.7386" y2="79.8322" width="0.1524" layer="1"/>
@ -4288,10 +4289,6 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<via x="16.764" y="79.8576" extent="1-16" drill="0.3"/>
<wire x1="26.8224" y1="83.6676" x2="20.574" y2="83.6676" width="0.1524" layer="16"/>
<wire x1="20.574" y1="83.6676" x2="16.764" y2="79.8576" width="0.1524" layer="16"/>
<contactref element="IC7" pad="22"/>
<wire x1="48.006" y1="80.9244" x2="48.006" y2="90.3732" width="0.1524" layer="1"/>
<wire x1="48.006" y1="90.3732" x2="48.95" y2="91.3172" width="0.1524" layer="1"/>
<wire x1="48.95" y1="91.3172" x2="51.7896" y2="91.3172" width="0.1524" layer="1"/>
</signal>
<signal name="A7">
<contactref element="IC1" pad="B13"/>
@ -4847,14 +4844,12 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="18.8976" y1="85.9536" x2="18.5928" y2="86.2584" width="0.1524" layer="1"/>
<wire x1="18.5928" y1="86.2584" x2="18.5928" y2="90.9828" width="0.1524" layer="1"/>
<via x="18.5928" y="90.9828" extent="1-16" drill="0.3"/>
<wire x1="18.5928" y1="90.9828" x2="43.2816" y2="90.9828" width="0.1524" layer="16"/>
<via x="43.2816" y="90.9828" extent="1-16" drill="0.3"/>
<contactref element="IC7" pad="92"/>
<wire x1="45.7896" y1="78.8172" x2="45.7896" y2="80.2452" width="0.1524" layer="1"/>
<wire x1="45.7896" y1="80.2452" x2="43.8912" y2="82.1436" width="0.1524" layer="1"/>
<wire x1="43.8912" y1="82.1436" x2="43.8912" y2="86.868" width="0.1524" layer="1"/>
<wire x1="43.2816" y1="90.9828" x2="43.2816" y2="87.4776" width="0.1524" layer="1"/>
<wire x1="43.2816" y1="87.4776" x2="43.8912" y2="86.868" width="0.1524" layer="1"/>
<wire x1="18.5928" y1="90.9828" x2="45.2628" y2="90.9828" width="0.1524" layer="16"/>
<contactref element="IC7" pad="33"/>
<via x="45.2628" y="90.9828" extent="1-16" drill="0.3"/>
<wire x1="46.2896" y1="94.8172" x2="46.2896" y2="94.0416" width="0.1524" layer="1"/>
<wire x1="46.2896" y1="94.0416" x2="45.2628" y2="93.0148" width="0.1524" layer="1"/>
<wire x1="45.2628" y1="93.0148" x2="45.2628" y2="90.9828" width="0.1524" layer="1"/>
</signal>
<signal name="R/W">
<contactref element="IC1" pad="L03"/>
@ -5370,10 +5365,20 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<contactref element="IC1" pad="E02"/>
<wire x1="31.8262" y1="55.4228" x2="32.8168" y2="55.4228" width="0.1524" layer="16"/>
<wire x1="32.8168" y1="55.4228" x2="33.8836" y2="54.356" width="0.1524" layer="16"/>
<wire x1="44.8056" y1="54.356" x2="33.8836" y2="54.356" width="0.1524" layer="16"/>
<contactref element="IC7" pad="92"/>
<wire x1="45.7896" y1="78.8172" x2="45.7896" y2="77.7936" width="0.1524" layer="1"/>
<wire x1="45.4152" y1="71.1708" x2="45.4152" y2="70.104" width="0.1524" layer="1"/>
<wire x1="45.4152" y1="70.104" x2="45.8724" y2="69.6468" width="0.1524" layer="1"/>
<wire x1="45.8724" y1="69.6468" x2="45.8724" y2="54.5084" width="0.1524" layer="1"/>
<via x="45.8724" y="54.5084" extent="1-16" drill="0.3"/>
<wire x1="45.8724" y1="54.5084" x2="45.72" y2="54.356" width="0.1524" layer="16"/>
<wire x1="45.72" y1="54.356" x2="33.8836" y2="54.356" width="0.1524" layer="16"/>
<wire x1="45.4152" y1="71.1708" x2="46.0248" y2="71.7804" width="0.1524" layer="1"/>
<wire x1="46.0248" y1="71.7804" x2="46.0248" y2="77.5584" width="0.1524" layer="1"/>
<wire x1="46.0248" y1="77.5584" x2="45.7896" y2="77.7936" width="0.1524" layer="1"/>
<contactref element="X1" pad="A13"/>
<wire x1="87.63" y1="43.8912" x2="86.106" y2="42.3672" width="0.1524" layer="16"/>
<wire x1="78.3336" y1="42.3672" x2="71.3232" y2="42.3672" width="0.1524" layer="16"/>
<wire x1="86.106" y1="42.3672" x2="71.3232" y2="42.3672" width="0.1524" layer="16"/>
<wire x1="71.3232" y1="42.3672" x2="71.0184" y2="42.672" width="0.1524" layer="16"/>
<wire x1="71.0184" y1="42.672" x2="69.9516" y2="42.672" width="0.1524" layer="16"/>
<wire x1="69.9516" y1="42.672" x2="68.7324" y2="41.4528" width="0.1524" layer="16"/>
@ -5387,17 +5392,9 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="47.0916" y1="42.5196" x2="49.8348" y2="45.2628" width="0.1524" layer="1"/>
<wire x1="49.8348" y1="45.2628" x2="49.8348" y2="55.1688" width="0.1524" layer="1"/>
<via x="49.8348" y="55.1688" extent="1-16" drill="0.3"/>
<wire x1="49.8348" y1="55.1688" x2="49.0728" y2="55.9308" width="0.1524" layer="16"/>
<wire x1="49.0728" y1="55.9308" x2="46.3804" y2="55.9308" width="0.1524" layer="16"/>
<wire x1="46.3804" y1="55.9308" x2="44.8056" y2="54.356" width="0.1524" layer="16"/>
<contactref element="R17" pad="2"/>
<wire x1="80.01" y1="38.4928" x2="79.4648" y2="38.4928" width="0.1524" layer="1"/>
<wire x1="79.4648" y1="38.4928" x2="78.7908" y2="39.1668" width="0.1524" layer="1"/>
<wire x1="78.7908" y1="39.1668" x2="78.7908" y2="41.91" width="0.1524" layer="1"/>
<via x="78.7908" y="41.91" extent="1-16" drill="0.3"/>
<wire x1="78.7908" y1="41.91" x2="78.3336" y2="42.3672" width="0.1524" layer="16"/>
<wire x1="86.106" y1="42.3672" x2="79.248" y2="42.3672" width="0.1524" layer="16"/>
<wire x1="79.248" y1="42.3672" x2="78.7908" y2="41.91" width="0.1524" layer="16"/>
<wire x1="49.8348" y1="55.1688" x2="49.3776" y2="54.7116" width="0.1524" layer="16"/>
<wire x1="49.3776" y1="54.7116" x2="46.0756" y2="54.7116" width="0.1524" layer="16"/>
<wire x1="46.0756" y1="54.7116" x2="45.8724" y2="54.5084" width="0.1524" layer="16"/>
</signal>
<signal name="CIIN">
<contactref element="IC1" pad="L01"/>
@ -6334,9 +6331,6 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<via x="73.6092" y="52.578" extent="1-16" drill="0.3"/>
<wire x1="52.1716" y1="44.7942" x2="53.0238" y2="44.7942" width="0.6096" layer="1"/>
<wire x1="53.0238" y1="44.7942" x2="53.34" y2="45.1104" width="0.6096" layer="1"/>
<contactref element="R17" pad="1"/>
<wire x1="80.01" y1="36.7928" x2="80.01" y2="36.703" width="0.1524" layer="1"/>
<wire x1="80.01" y1="36.703" x2="79.0956" y2="35.7886" width="0.1524" layer="1"/>
<wire x1="72.8336" y1="89.916" x2="71.7804" y2="94.3102" width="0" layer="19" extent="1-1"/>
<wire x1="59.2328" y1="98.4504" x2="71.7804" y2="94.3102" width="0" layer="19" extent="1-1"/>
<wire x1="54.5592" y1="96.608" x2="57.15" y2="98.4788" width="0" layer="19" extent="1-1"/>
@ -6363,7 +6357,7 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="73.6092" y1="52.578" x2="65.0104" y2="52.8828" width="0" layer="19" extent="1-1"/>
<wire x1="75.424" y1="46.6344" x2="74.7404" y2="52.578" width="0" layer="19" extent="1-1"/>
<wire x1="75.6412" y1="59.4732" x2="74.7404" y2="52.578" width="0" layer="19" extent="1-1"/>
<wire x1="80.01" y1="36.7928" x2="75.4126" y2="44.6278" width="0" layer="19" extent="1-1"/>
<wire x1="79.0956" y1="35.7886" x2="75.4126" y2="44.6278" width="0" layer="19" extent="1-1"/>
<wire x1="75.3872" y1="31.4084" x2="79.0956" y2="33.9208" width="0" layer="19" extent="1-1"/>
<wire x1="77.8764" y1="24.9056" x2="75.3872" y2="29.6164" width="0" layer="19" extent="1-1"/>
<wire x1="87.63" y1="23.5712" x2="77.8764" y2="23.4696" width="0" layer="19" extent="1-1"/>
@ -6622,7 +6616,7 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<via x="47.4472" y="98.3488" extent="1-16" drill="0.3"/>
<via x="35.6108" y="97.6884" extent="1-16" drill="0.3"/>
<via x="33.5788" y="97.6884" extent="1-16" drill="0.3"/>
<via x="16.256" y="98.7044" extent="1-16" drill="0.3"/>
<via x="17.3228" y="98.7044" extent="1-16" drill="0.3"/>
<via x="1.8288" y="83.3628" extent="1-16" drill="0.3"/>
<via x="45.5676" y="86.9696" extent="1-16" drill="0.3"/>
<via x="42.418" y="19.8628" extent="1-16" drill="0.3"/>
@ -6630,7 +6624,7 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<via x="47.4472" y="57.9628" extent="1-16" drill="0.3"/>
<via x="48.3616" y="57.9628" extent="1-16" drill="0.3"/>
<via x="70.612" y="60.8076" extent="1-16" drill="0.3"/>
<wire x1="78.74" y1="39.5224" x2="78.74" y2="39.5224" width="0" layer="19" extent="1-16"/>
<via x="78.74" y="39.5224" extent="1-16" drill="0.3"/>
<via x="77.1906" y="39.5224" extent="1-16" drill="0.3"/>
<wire x1="47.5742" y1="55.1294" x2="47.766" y2="55.3212" width="0.6096" layer="1"/>
<wire x1="47.766" y1="55.3212" x2="48.8696" y2="55.3212" width="0.6096" layer="1"/>
@ -6772,7 +6766,19 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="76.7956" y1="31.75" x2="76.7956" y2="30.72" width="0.4064" layer="1"/>
<wire x1="76.7956" y1="30.72" x2="76.7842" y2="30.7086" width="0.4064" layer="1"/>
<via x="76.7842" y="30.7086" extent="1-16" drill="0.3"/>
<contactref element="IC4" pad="19"/>
<contactref element="IC8" pad="19"/>
<contactref element="IC9" pad="19"/>
<via x="7.5692" y="82.3976" extent="1-16" drill="0.3"/>
<wire x1="5.1816" y1="72.2122" x2="5.207" y2="72.2376" width="0.1524" layer="1"/>
<wire x1="5.207" y1="72.2376" x2="6.7056" y2="72.2376" width="0.1524" layer="1"/>
<via x="6.7056" y="72.2376" extent="1-16" drill="0.3"/>
<wire x1="5.1816" y1="56.9722" x2="5.207" y2="56.9976" width="0.1524" layer="1"/>
<wire x1="5.207" y1="56.9976" x2="6.7056" y2="56.9976" width="0.1524" layer="1"/>
<via x="6.7056" y="56.9976" extent="1-16" drill="0.3"/>
<wire x1="5.1816" y1="42.037" x2="5.207" y2="42.0624" width="0.1524" layer="1"/>
<wire x1="5.207" y1="42.0624" x2="6.7056" y2="42.0624" width="0.1524" layer="1"/>
<via x="6.7056" y="42.0624" extent="1-16" drill="0.3"/>
<wire x1="33.3134" y1="15.4686" x2="29.8336" y2="15.4686" width="0.6096" layer="1"/>
<wire x1="29.8336" y1="15.4686" x2="28.956" y2="16.3462" width="0.6096" layer="1"/>
<wire x1="28.956" y1="16.3462" x2="28.956" y2="15.24" width="0.6096" layer="1"/>
@ -6825,8 +6831,8 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="72.0852" y1="84.328" x2="67.4116" y2="90.5256" width="0" layer="19" extent="1-1"/>
<wire x1="23.114" y1="95.0468" x2="31.1912" y2="94.8944" width="0" layer="19" extent="1-1"/>
<wire x1="18.9992" y1="97.3328" x2="23.114" y2="95.0468" width="0" layer="19" extent="1-1"/>
<wire x1="17.3228" y1="98.7044" x2="18.9992" y2="97.3328" width="0" layer="19" extent="1-1"/>
<wire x1="17.018" y1="95.1992" x2="18.9992" y2="97.3328" width="0" layer="19" extent="1-1"/>
<wire x1="16.256" y1="98.7044" x2="18.9992" y2="97.3328" width="0" layer="19" extent="1-1"/>
<wire x1="21.4376" y1="88.5444" x2="23.114" y2="95.0468" width="0" layer="19" extent="1-1"/>
<wire x1="16.764" y1="82.4484" x2="21.4376" y2="88.5444" width="0" layer="19" extent="1-1"/>
<wire x1="15.1892" y1="83.7692" x2="15.24" y2="82.3722" width="0" layer="19" extent="1-1"/>
@ -6834,7 +6840,8 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="7.5692" y1="82.3976" x2="10.3746" y2="84.9376" width="0" layer="19" extent="1-1"/>
<wire x1="1.8288" y1="83.3628" x2="7.5692" y2="82.3976" width="0" layer="19" extent="1-1"/>
<wire x1="10.922" y1="77.3684" x2="7.5692" y2="82.3976" width="0" layer="19" extent="1-1"/>
<wire x1="6.971" y1="69.0372" x2="10.922" y2="77.3684" width="0" layer="19" extent="1-1"/>
<wire x1="6.7056" y1="72.2376" x2="10.922" y2="77.3684" width="0" layer="19" extent="1-1"/>
<wire x1="6.971" y1="69.0372" x2="6.7056" y2="72.2376" width="0" layer="19" extent="1-1"/>
<wire x1="10.3124" y1="66.8528" x2="7.0104" y2="67.9704" width="0" layer="19" extent="1-1"/>
<wire x1="15.24" y1="67.1322" x2="10.3124" y2="66.8528" width="0" layer="19" extent="1-1"/>
<wire x1="15.1892" y1="68.9864" x2="15.24" y2="67.1322" width="0" layer="19" extent="1-1"/>
@ -6892,7 +6899,8 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="25.7302" y1="28.829" x2="24.7904" y2="28.9052" width="0" layer="19" extent="1-1"/>
<wire x1="29.718" y1="31.3944" x2="25.7302" y2="28.829" width="0" layer="19" extent="1-1"/>
<wire x1="7.0104" y1="37.6428" x2="10.9728" y2="34.414" width="0" layer="19" extent="1-1"/>
<wire x1="10.16" y1="41.2496" x2="6.971" y2="38.862" width="0" layer="19" extent="1-1"/>
<wire x1="6.7056" y1="42.0624" x2="6.971" y2="38.862" width="0" layer="19" extent="1-1"/>
<wire x1="10.16" y1="41.2496" x2="6.7056" y2="42.0624" width="0" layer="19" extent="1-1"/>
<wire x1="34.798" y1="30.1244" x2="29.8336" y2="31.51" width="0" layer="19" extent="1-1"/>
<wire x1="36.0934" y1="30.1244" x2="34.8234" y2="30.099" width="0" layer="19" extent="1-1"/>
<wire x1="37.3634" y1="28.4086" x2="36.0934" y2="28.4086" width="0" layer="19" extent="1-1"/>
@ -6940,6 +6948,7 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="21.2852" y1="2.3876" x2="19.9136" y2="3.1496" width="0" layer="19" extent="1-1"/>
<wire x1="26.4668" y1="5.9944" x2="21.2852" y2="2.3876" width="0" layer="19" extent="1-1"/>
<wire x1="7.0104" y1="53.7578" x2="15.1892" y2="53.594" width="0" layer="19" extent="1-1"/>
<wire x1="6.7056" y1="56.9976" x2="6.8186" y2="53.9496" width="0" layer="19" extent="1-1"/>
<wire x1="74.3204" y1="49.6824" x2="78.8416" y2="57.0484" width="0" layer="19" extent="1-1"/>
<wire x1="73.6486" y1="46.609" x2="74.3204" y2="49.6824" width="0" layer="19" extent="1-1"/>
<wire x1="77.1906" y1="39.5224" x2="73.6486" y2="46.609" width="0" layer="19" extent="1-1"/>
@ -6950,7 +6959,7 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="88.4936" y1="32.4612" x2="80.1624" y2="34.5948" width="0" layer="19" extent="1-1"/>
<wire x1="91.5416" y1="32.3088" x2="88.4936" y2="32.4612" width="0" layer="19" extent="1-1"/>
<wire x1="1.9304" y1="30.2006" x2="7.0104" y2="37.6428" width="0" layer="19" extent="1-1"/>
<wire x1="88.4936" y1="42.672" x2="88.4936" y2="32.4612" width="0" layer="19" extent="1-1"/>
<wire x1="88.4936" y1="42.672" x2="78.74" y2="39.5224" width="0" layer="19" extent="1-1"/>
<wire x1="88.4936" y1="52.8828" x2="88.4936" y2="42.672" width="0" layer="19" extent="1-1"/>
<wire x1="88.4936" y1="62.9412" x2="88.4936" y2="52.8828" width="0" layer="19" extent="1-1"/>
<wire x1="91.5416" y1="62.7888" x2="88.4936" y2="62.9412" width="0" layer="19" extent="1-1"/>
@ -7225,16 +7234,16 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="45.7896" y1="97.7712" x2="44.958" y2="98.6028" width="0.1524" layer="1"/>
<wire x1="44.958" y1="98.6028" x2="18.4404" y2="98.6028" width="0.1524" layer="1"/>
<wire x1="18.4404" y1="98.6028" x2="12.0396" y2="92.202" width="0.1524" layer="1"/>
<wire x1="12.0396" y1="92.202" x2="12.0396" y2="83.9724" width="0.1524" layer="1"/>
<wire x1="12.0396" y1="83.9724" x2="8.382" y2="80.3148" width="0.1524" layer="1"/>
<wire x1="12.0396" y1="92.202" x2="12.0396" y2="84.8868" width="0.1524" layer="1"/>
<wire x1="12.0396" y1="84.8868" x2="7.9248" y2="80.772" width="0.1524" layer="1"/>
<wire x1="7.9248" y1="4.8768" x2="7.747" y2="4.699" width="0.1524" layer="1"/>
<wire x1="7.747" y1="4.699" x2="5.4864" y2="4.699" width="0.1524" layer="1"/>
<wire x1="5.334" y1="20.2438" x2="7.4422" y2="20.2438" width="0.1524" layer="1"/>
<wire x1="7.4422" y1="20.2438" x2="8.382" y2="21.1836" width="0.1524" layer="1"/>
<wire x1="7.4422" y1="20.2438" x2="7.9248" y2="20.7264" width="0.1524" layer="1"/>
<wire x1="7.9248" y1="20.7264" x2="7.9248" y2="80.772" width="0.1524" layer="1"/>
<wire x1="7.4422" y1="20.2438" x2="7.493" y2="20.2438" width="0.1524" layer="1"/>
<wire x1="7.493" y1="20.2438" x2="7.9248" y2="19.812" width="0.1524" layer="1"/>
<wire x1="7.9248" y1="19.812" x2="7.9248" y2="4.8768" width="0.1524" layer="1"/>
<wire x1="8.382" y1="21.1836" x2="8.382" y2="80.3148" width="0.1524" layer="1"/>
</signal>
<signal name="AMIGA_DATA_DIR">
<contactref element="IC7" pad="48"/>
@ -8037,11 +8046,24 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="45.72" y1="71.9328" x2="45.1104" y2="71.3232" width="0.1524" layer="1"/>
<wire x1="45.1104" y1="71.3232" x2="45.1104" y2="69.6468" width="0.1524" layer="1"/>
<wire x1="45.1104" y1="69.6468" x2="45.4152" y2="69.342" width="0.1524" layer="1"/>
<wire x1="45.4152" y1="69.342" x2="45.4152" y2="53.0352" width="0.1524" layer="1"/>
<wire x1="45.4152" y1="53.0352" x2="47.0916" y2="51.3588" width="0.1524" layer="1"/>
<wire x1="45.4152" y1="69.342" x2="45.4152" y2="55.0164" width="0.1524" layer="1"/>
<wire x1="45.4152" y1="55.0164" x2="45.2628" y2="54.864" width="0.1524" layer="1"/>
<wire x1="45.2628" y1="54.864" x2="45.2628" y2="53.1876" width="0.1524" layer="1"/>
<wire x1="45.2628" y1="53.1876" x2="47.0916" y2="51.3588" width="0.1524" layer="1"/>
</signal>
<signal name="RW_OUT">
<contactref element="IC7" pad="22"/>
<contactref element="IC9" pad="2"/>
<wire x1="51.7896" y1="91.3172" x2="50.11" y2="91.3172" width="0.1524" layer="1"/>
<wire x1="50.11" y1="91.3172" x2="49.3776" y2="92.0496" width="0.1524" layer="1"/>
<via x="49.3776" y="92.0496" extent="1-16" drill="0.3"/>
<wire x1="49.3776" y1="92.0496" x2="49.3776" y2="92.964" width="0.1524" layer="16"/>
<wire x1="49.3776" y1="92.964" x2="49.8348" y2="93.4212" width="0.1524" layer="16"/>
<wire x1="49.8348" y1="93.4212" x2="49.8348" y2="93.726" width="0.1524" layer="16"/>
<wire x1="49.8348" y1="93.726" x2="49.0728" y2="94.488" width="0.1524" layer="16"/>
<wire x1="49.0728" y1="94.488" x2="36.8808" y2="94.488" width="0.1524" layer="16"/>
<wire x1="36.8808" y1="94.488" x2="35.9664" y2="95.4024" width="0.1524" layer="16"/>
<wire x1="35.9664" y1="95.4024" x2="35.5092" y2="95.4024" width="0.1524" layer="16"/>
<wire x1="35.5092" y1="95.4024" x2="34.5948" y2="94.488" width="0.1524" layer="16"/>
<wire x1="34.5948" y1="94.488" x2="31.6992" y2="94.488" width="0.1524" layer="16"/>
<wire x1="31.6992" y1="94.488" x2="31.5468" y2="94.3356" width="0.1524" layer="16"/>
@ -8058,53 +8080,18 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="13.5636" y1="91.8972" x2="13.5636" y2="42.3672" width="0.1524" layer="1"/>
<wire x1="13.5636" y1="42.3672" x2="13.8938" y2="42.037" width="0.1524" layer="1"/>
<wire x1="13.8938" y1="42.037" x2="15.24" y2="42.037" width="0.1524" layer="1"/>
<contactref element="IC7" pad="42"/>
<wire x1="35.5092" y1="95.4024" x2="38.4048" y2="95.4024" width="0.1524" layer="16"/>
<wire x1="38.4048" y1="95.4024" x2="39.4716" y2="96.4692" width="0.1524" layer="16"/>
<via x="39.4716" y="96.4692" extent="1-16" drill="0.3"/>
<wire x1="39.4716" y1="96.4692" x2="41.3004" y2="96.4692" width="0.1524" layer="1"/>
<wire x1="41.3004" y1="96.4692" x2="41.7896" y2="95.98" width="0.1524" layer="1"/>
<wire x1="41.7896" y1="95.98" x2="41.7896" y2="94.8172" width="0.1524" layer="1"/>
</signal>
<signal name="AMIGA_ADR_ENABLE">
<contactref element="IC4" pad="19"/>
<wire x1="5.1816" y1="72.2122" x2="5.207" y2="72.2376" width="0.1524" layer="1"/>
<wire x1="5.207" y1="72.2376" x2="6.096" y2="72.2376" width="0.1524" layer="1"/>
<contactref element="IC8" pad="19"/>
<wire x1="5.1816" y1="56.9722" x2="5.207" y2="56.9976" width="0.1524" layer="1"/>
<contactref element="IC9" pad="19"/>
<wire x1="5.1816" y1="42.037" x2="5.207" y2="42.0624" width="0.1524" layer="1"/>
<wire x1="5.207" y1="42.0624" x2="6.7056" y2="42.0624" width="0.1524" layer="1"/>
<contactref element="IC7" pad="33"/>
<wire x1="46.2896" y1="94.8172" x2="46.2896" y2="97.7284" width="0.1524" layer="1"/>
<wire x1="46.2896" y1="97.7284" x2="45.1104" y2="98.9076" width="0.1524" layer="1"/>
<wire x1="45.1104" y1="98.9076" x2="17.9832" y2="98.9076" width="0.1524" layer="1"/>
<wire x1="17.9832" y1="98.9076" x2="11.5824" y2="92.5068" width="0.1524" layer="1"/>
<wire x1="11.5824" y1="92.5068" x2="11.5824" y2="84.4296" width="0.1524" layer="1"/>
<wire x1="11.5824" y1="84.4296" x2="7.62" y2="80.4672" width="0.1524" layer="1"/>
<wire x1="7.62" y1="80.4672" x2="7.62" y2="73.152" width="0.1524" layer="1"/>
<wire x1="6.096" y1="72.2376" x2="7.7724" y2="70.5612" width="0.1524" layer="1"/>
<wire x1="7.7724" y1="70.5612" x2="7.7724" y2="58.674" width="0.1524" layer="1"/>
<wire x1="7.7724" y1="43.1292" x2="6.7056" y2="42.0624" width="0.1524" layer="1"/>
<wire x1="5.207" y1="56.9976" x2="6.096" y2="56.9976" width="0.1524" layer="1"/>
<wire x1="6.096" y1="56.9976" x2="7.7724" y2="58.674" width="0.1524" layer="1"/>
<wire x1="7.7724" y1="43.1292" x2="7.7724" y2="55.3212" width="0.1524" layer="1"/>
<wire x1="7.7724" y1="55.3212" x2="6.096" y2="56.9976" width="0.1524" layer="1"/>
<wire x1="7.62" y1="73.152" x2="7.1628" y2="72.6948" width="0.1524" layer="1"/>
<wire x1="7.1628" y1="72.6948" x2="6.5532" y2="72.6948" width="0.1524" layer="1"/>
<wire x1="6.5532" y1="72.6948" x2="6.096" y2="72.2376" width="0.1524" layer="1"/>
</signal>
</signals>
<errors>
<approved hash="18,30,1b42dc4e8e6fb74c"/>
<approved hash="18,30,a5d25a4e8a6e8dce"/>
<approved hash="18,30,933d5dc68ee6b8e9"/>
<approved hash="18,30,4daddc4e8f67e619"/>
<approved hash="18,30,c2185cc68efeee34"/>
<approved hash="18,30,3849587e8adf1064"/>
<approved hash="18,30,a5d25a4e8a6e8dce"/>
<approved hash="18,30,1b42dc4e8e6fb74c"/>
<approved hash="18,30,4daddc4e8f67e619"/>
<approved hash="18,30,f646dbc696e743f0"/>
<approved hash="18,30,a0a8a9f4a989a0d5"/>
<approved hash="18,30,3849587e8adf1064"/>
<approved hash="18,30,93e4923c922593fd"/>
<approved hash="18,30,a0a8a9f4a989a0d5"/>
</errors>
</board>
</drawing>

View File

@ -2862,6 +2862,9 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
</element>
<element name="R14" library="rcl" package="R0603" value="" x="58.674" y="85.6488" rot="R180"/>
<element name="R16" library="rcl" package="R0603" value="" x="28.6512" y="90.3732" rot="R180"/>
<element name="R17" library="rcl" package="R0603" value="4,7k" x="80.01" y="37.6428" smashed="yes" rot="R90">
<attribute name="NAME" x="79.0702" y="36.3982" size="1.27" layer="25" rot="R90"/>
</element>
</elements>
<signals>
<signal name="D0">
@ -4278,10 +4281,6 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="48.768" y1="80.1624" x2="48.006" y2="80.9244" width="0.1524" layer="1"/>
<wire x1="55.5752" y1="76.962" x2="53.7972" y2="78.74" width="0.1524" layer="1"/>
<wire x1="53.7972" y1="78.74" x2="53.7972" y2="79.5528" width="0.1524" layer="1"/>
<contactref element="IC7" pad="42"/>
<wire x1="41.7896" y1="94.8172" x2="41.7896" y2="88.2076" width="0.1524" layer="1"/>
<wire x1="41.7896" y1="88.2076" x2="48.006" y2="81.9912" width="0.1524" layer="1"/>
<wire x1="48.006" y1="81.9912" x2="48.006" y2="80.9244" width="0.1524" layer="1"/>
<contactref element="X1" pad="C30"/>
<contactref element="IC4" pad="8"/>
<wire x1="15.24" y1="79.8322" x2="16.7386" y2="79.8322" width="0.1524" layer="1"/>
@ -4289,6 +4288,10 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<via x="16.764" y="79.8576" extent="1-16" drill="0.3"/>
<wire x1="26.8224" y1="83.6676" x2="20.574" y2="83.6676" width="0.1524" layer="16"/>
<wire x1="20.574" y1="83.6676" x2="16.764" y2="79.8576" width="0.1524" layer="16"/>
<contactref element="IC7" pad="22"/>
<wire x1="48.006" y1="80.9244" x2="48.006" y2="90.3732" width="0.1524" layer="1"/>
<wire x1="48.006" y1="90.3732" x2="48.95" y2="91.3172" width="0.1524" layer="1"/>
<wire x1="48.95" y1="91.3172" x2="51.7896" y2="91.3172" width="0.1524" layer="1"/>
</signal>
<signal name="A7">
<contactref element="IC1" pad="B13"/>
@ -4844,12 +4847,16 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="18.8976" y1="85.9536" x2="18.5928" y2="86.2584" width="0.1524" layer="1"/>
<wire x1="18.5928" y1="86.2584" x2="18.5928" y2="90.9828" width="0.1524" layer="1"/>
<via x="18.5928" y="90.9828" extent="1-16" drill="0.3"/>
<wire x1="18.5928" y1="90.9828" x2="45.2628" y2="90.9828" width="0.1524" layer="16"/>
<contactref element="IC7" pad="33"/>
<via x="45.2628" y="90.9828" extent="1-16" drill="0.3"/>
<wire x1="46.2896" y1="94.8172" x2="46.2896" y2="94.0416" width="0.1524" layer="1"/>
<wire x1="46.2896" y1="94.0416" x2="45.2628" y2="93.0148" width="0.1524" layer="1"/>
<wire x1="45.2628" y1="93.0148" x2="45.2628" y2="90.9828" width="0.1524" layer="1"/>
<wire x1="18.5928" y1="90.9828" x2="41.91" y2="90.9828" width="0.1524" layer="16"/>
<via x="41.91" y="90.9828" extent="1-16" drill="0.3"/>
<wire x1="45.7896" y1="80.2452" x2="43.8912" y2="82.1436" width="0" layer="19" extent="1-16"/>
<wire x1="43.8912" y1="82.1436" x2="43.8912" y2="86.868" width="0" layer="19" extent="1-16"/>
<wire x1="41.91" y1="90.9828" x2="43.2816" y2="87.4776" width="0" layer="19" extent="1-16"/>
<wire x1="43.2816" y1="87.4776" x2="43.8912" y2="86.868" width="0" layer="19" extent="1-16"/>
<contactref element="IC7" pad="42"/>
<wire x1="41.7896" y1="94.8172" x2="41.7896" y2="92.932" width="0.1524" layer="1"/>
<wire x1="41.7896" y1="92.932" x2="41.91" y2="92.8116" width="0.1524" layer="1"/>
<wire x1="41.91" y1="92.8116" x2="41.91" y2="90.9828" width="0.1524" layer="1"/>
</signal>
<signal name="R/W">
<contactref element="IC1" pad="L03"/>
@ -4893,6 +4900,16 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="35.3568" y1="38.735" x2="34.3662" y2="39.7256" width="0.1524" layer="1"/>
<wire x1="34.3662" y1="39.7256" x2="34.3662" y2="40.1828" width="0.1524" layer="1"/>
<wire x1="35.2044" y1="41.7576" x2="34.3662" y2="40.9194" width="0.1524" layer="1"/>
<contactref element="IC9" pad="2"/>
<wire x1="15.24" y1="42.037" x2="16.5862" y2="42.037" width="0.1524" layer="1"/>
<wire x1="16.5862" y1="42.037" x2="16.764" y2="42.2148" width="0.1524" layer="1"/>
<via x="16.764" y="42.2148" extent="1-16" drill="0.3"/>
<wire x1="16.764" y1="42.2148" x2="19.2024" y2="42.2148" width="0.1524" layer="16"/>
<wire x1="19.2024" y1="42.2148" x2="20.2692" y2="41.148" width="0.1524" layer="16"/>
<wire x1="20.2692" y1="41.148" x2="23.4696" y2="41.148" width="0.1524" layer="16"/>
<wire x1="23.4696" y1="41.148" x2="23.622" y2="41.3004" width="0.1524" layer="16"/>
<wire x1="23.622" y1="41.3004" x2="33.2486" y2="41.3004" width="0.1524" layer="16"/>
<wire x1="33.2486" y1="41.3004" x2="34.3662" y2="40.1828" width="0.1524" layer="16"/>
</signal>
<signal name="UDS_00">
<contactref element="IC2" pad="7"/>
@ -5365,20 +5382,10 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<contactref element="IC1" pad="E02"/>
<wire x1="31.8262" y1="55.4228" x2="32.8168" y2="55.4228" width="0.1524" layer="16"/>
<wire x1="32.8168" y1="55.4228" x2="33.8836" y2="54.356" width="0.1524" layer="16"/>
<contactref element="IC7" pad="92"/>
<wire x1="45.7896" y1="78.8172" x2="45.7896" y2="77.7936" width="0.1524" layer="1"/>
<wire x1="45.4152" y1="71.1708" x2="45.4152" y2="70.104" width="0.1524" layer="1"/>
<wire x1="45.4152" y1="70.104" x2="45.8724" y2="69.6468" width="0.1524" layer="1"/>
<wire x1="45.8724" y1="69.6468" x2="45.8724" y2="54.5084" width="0.1524" layer="1"/>
<via x="45.8724" y="54.5084" extent="1-16" drill="0.3"/>
<wire x1="45.8724" y1="54.5084" x2="45.72" y2="54.356" width="0.1524" layer="16"/>
<wire x1="45.72" y1="54.356" x2="33.8836" y2="54.356" width="0.1524" layer="16"/>
<wire x1="45.4152" y1="71.1708" x2="46.0248" y2="71.7804" width="0.1524" layer="1"/>
<wire x1="46.0248" y1="71.7804" x2="46.0248" y2="77.5584" width="0.1524" layer="1"/>
<wire x1="46.0248" y1="77.5584" x2="45.7896" y2="77.7936" width="0.1524" layer="1"/>
<wire x1="46.1772" y1="54.356" x2="33.8836" y2="54.356" width="0.1524" layer="16"/>
<contactref element="X1" pad="A13"/>
<wire x1="87.63" y1="43.8912" x2="86.106" y2="42.3672" width="0.1524" layer="16"/>
<wire x1="86.106" y1="42.3672" x2="71.3232" y2="42.3672" width="0.1524" layer="16"/>
<wire x1="78.3336" y1="42.3672" x2="71.3232" y2="42.3672" width="0.1524" layer="16"/>
<wire x1="71.3232" y1="42.3672" x2="71.0184" y2="42.672" width="0.1524" layer="16"/>
<wire x1="71.0184" y1="42.672" x2="69.9516" y2="42.672" width="0.1524" layer="16"/>
<wire x1="69.9516" y1="42.672" x2="68.7324" y2="41.4528" width="0.1524" layer="16"/>
@ -5392,9 +5399,29 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="47.0916" y1="42.5196" x2="49.8348" y2="45.2628" width="0.1524" layer="1"/>
<wire x1="49.8348" y1="45.2628" x2="49.8348" y2="55.1688" width="0.1524" layer="1"/>
<via x="49.8348" y="55.1688" extent="1-16" drill="0.3"/>
<wire x1="49.8348" y1="55.1688" x2="49.3776" y2="54.7116" width="0.1524" layer="16"/>
<wire x1="49.3776" y1="54.7116" x2="46.0756" y2="54.7116" width="0.1524" layer="16"/>
<wire x1="46.0756" y1="54.7116" x2="45.8724" y2="54.5084" width="0.1524" layer="16"/>
<wire x1="49.8348" y1="55.1688" x2="49.0728" y2="55.9308" width="0.1524" layer="16"/>
<contactref element="R17" pad="2"/>
<wire x1="80.01" y1="38.4928" x2="79.4648" y2="38.4928" width="0.1524" layer="1"/>
<wire x1="79.4648" y1="38.4928" x2="78.7908" y2="39.1668" width="0.1524" layer="1"/>
<wire x1="78.7908" y1="39.1668" x2="78.7908" y2="41.91" width="0.1524" layer="1"/>
<via x="78.7908" y="41.91" extent="1-16" drill="0.3"/>
<wire x1="78.7908" y1="41.91" x2="78.3336" y2="42.3672" width="0.1524" layer="16"/>
<wire x1="86.106" y1="42.3672" x2="79.248" y2="42.3672" width="0.1524" layer="16"/>
<wire x1="79.248" y1="42.3672" x2="78.7908" y2="41.91" width="0.1524" layer="16"/>
<contactref element="IC7" pad="92"/>
<wire x1="45.7896" y1="78.8172" x2="45.7896" y2="77.8068" width="0.1524" layer="1"/>
<wire x1="45.7896" y1="77.8068" x2="46.0248" y2="77.5716" width="0.1524" layer="1"/>
<wire x1="46.0248" y1="77.5716" x2="46.0248" y2="71.7804" width="0.1524" layer="1"/>
<wire x1="46.0248" y1="71.7804" x2="45.4152" y2="71.1708" width="0.1524" layer="1"/>
<wire x1="45.4152" y1="71.1708" x2="45.4152" y2="69.7992" width="0.1524" layer="1"/>
<wire x1="45.4152" y1="69.7992" x2="45.72" y2="69.4944" width="0.1524" layer="1"/>
<wire x1="45.72" y1="69.4944" x2="45.72" y2="60.0456" width="0.1524" layer="1"/>
<wire x1="45.72" y1="60.0456" x2="46.1772" y2="59.5884" width="0.1524" layer="1"/>
<wire x1="46.1772" y1="59.5884" x2="46.1772" y2="54.356" width="0.1524" layer="1"/>
<via x="46.1772" y="54.356" extent="1-16" drill="0.3"/>
<wire x1="46.1772" y1="54.356" x2="46.5836" y2="54.356" width="0.1524" layer="16"/>
<wire x1="46.5836" y1="54.356" x2="48.1584" y2="55.9308" width="0.1524" layer="16"/>
<wire x1="48.1584" y1="55.9308" x2="49.0728" y2="55.9308" width="0.1524" layer="16"/>
</signal>
<signal name="CIIN">
<contactref element="IC1" pad="L01"/>
@ -6331,6 +6358,58 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<via x="73.6092" y="52.578" extent="1-16" drill="0.3"/>
<wire x1="52.1716" y1="44.7942" x2="53.0238" y2="44.7942" width="0.6096" layer="1"/>
<wire x1="53.0238" y1="44.7942" x2="53.34" y2="45.1104" width="0.6096" layer="1"/>
<contactref element="R17" pad="1"/>
<wire x1="80.01" y1="36.7928" x2="80.01" y2="36.703" width="0.1524" layer="1"/>
<wire x1="80.01" y1="36.703" x2="79.0956" y2="35.7886" width="0.1524" layer="1"/>
<wire x1="72.8336" y1="89.916" x2="71.7804" y2="94.3102" width="0" layer="19" extent="1-1"/>
<wire x1="59.2328" y1="98.4504" x2="71.7804" y2="94.3102" width="0" layer="19" extent="1-1"/>
<wire x1="54.5592" y1="96.608" x2="57.15" y2="98.4788" width="0" layer="19" extent="1-1"/>
<wire x1="44.2896" y1="94.8172" x2="51.816" y2="97.9932" width="0" layer="19" extent="1-1"/>
<wire x1="49.9872" y1="86.5124" x2="44.1452" y2="93.726" width="0" layer="19" extent="1-1"/>
<wire x1="44.323" y1="80.4418" x2="49.9872" y2="86.5124" width="0" layer="19" extent="1-1"/>
<wire x1="35.7896" y1="81.8172" x2="43.2896" y2="79.9672" width="0" layer="19" extent="1-1"/>
<wire x1="33.133" y1="86.7664" x2="34.7256" y2="81.8172" width="0" layer="19" extent="1-1"/>
<wire x1="41.9862" y1="60.5028" x2="43.1292" y2="75.438" width="0" layer="19" extent="1-1"/>
<wire x1="44.0436" y1="55.3352" x2="42.5082" y2="56.8706" width="0" layer="19" extent="1-1"/>
<wire x1="47.5742" y1="53.3794" x2="44.0436" y2="54.19" width="0" layer="19" extent="1-1"/>
<wire x1="36.9062" y1="57.9628" x2="41.9862" y2="57.3926" width="0" layer="19" extent="1-1"/>
<wire x1="46.0248" y1="48.1584" x2="47.5742" y2="53.3794" width="0" layer="19" extent="1-1"/>
<wire x1="52.1462" y1="57.9628" x2="48.7172" y2="53.3908" width="0" layer="19" extent="1-1"/>
<wire x1="54.6862" y1="52.8828" x2="52.1462" y2="57.9628" width="0" layer="19" extent="1-1"/>
<wire x1="54.6862" y1="47.8028" x2="54.6862" y2="52.8828" width="0" layer="19" extent="1-1"/>
<wire x1="53.34" y1="45.1104" x2="54.6862" y2="47.8028" width="0" layer="19" extent="1-1"/>
<wire x1="52.1462" y1="42.7228" x2="52.1716" y2="44.7942" width="0" layer="19" extent="1-1"/>
<wire x1="41.9862" y1="40.1828" x2="46.0378" y2="44.9772" width="0" layer="19" extent="1-1"/>
<wire x1="37.1348" y1="42.9514" x2="41.9862" y2="40.1828" width="0" layer="19" extent="1-1"/>
<wire x1="34.3662" y1="47.8028" x2="37.3012" y2="45.2882" width="0" layer="19" extent="1-1"/>
<wire x1="31.8262" y1="52.8828" x2="34.3662" y2="47.8028" width="0" layer="19" extent="1-1"/>
<wire x1="64.4652" y1="55.0164" x2="54.6862" y2="52.8828" width="0" layer="19" extent="1-1"/>
<wire x1="73.6092" y1="52.578" x2="65.0104" y2="52.8828" width="0" layer="19" extent="1-1"/>
<wire x1="75.424" y1="46.6344" x2="74.7404" y2="52.578" width="0" layer="19" extent="1-1"/>
<wire x1="75.6412" y1="59.4732" x2="74.7404" y2="52.578" width="0" layer="19" extent="1-1"/>
<wire x1="80.01" y1="36.7928" x2="75.4126" y2="44.6278" width="0" layer="19" extent="1-1"/>
<wire x1="75.3872" y1="31.4084" x2="79.0956" y2="33.9208" width="0" layer="19" extent="1-1"/>
<wire x1="77.8764" y1="24.9056" x2="75.3872" y2="29.6164" width="0" layer="19" extent="1-1"/>
<wire x1="87.63" y1="23.5712" x2="77.8764" y2="23.4696" width="0" layer="19" extent="1-1"/>
<wire x1="87.63" y1="21.0312" x2="87.63" y2="23.5712" width="0" layer="19" extent="1-1"/>
<wire x1="87.63" y1="18.4912" x2="87.63" y2="21.0312" width="0" layer="19" extent="1-1"/>
<wire x1="31.5976" y1="33.5788" x2="36.9062" y2="42.7228" width="0" layer="19" extent="1-1"/>
<wire x1="24.7904" y1="35.2806" x2="31.5836" y2="33.5648" width="0" layer="19" extent="1-1"/>
<wire x1="33.3134" y1="19.2786" x2="33.3134" y2="26.8986" width="0" layer="19" extent="1-1"/>
<wire x1="15.3924" y1="34.3544" x2="24.7904" y2="35.2806" width="0" layer="19" extent="1-1"/>
<wire x1="10.9728" y1="37.214" x2="15.3924" y2="34.3544" width="0" layer="19" extent="1-1"/>
<wire x1="5.221" y1="38.862" x2="10.9728" y2="38.862" width="0" layer="19" extent="1-1"/>
<wire x1="1.9304" y1="40.3606" x2="5.1816" y2="40.767" width="0" layer="19" extent="1-1"/>
<wire x1="33.3134" y1="6.5786" x2="33.3134" y2="16.7386" width="0" layer="19" extent="1-1"/>
<wire x1="55.513" y1="32.4612" x2="52.1462" y2="42.7228" width="0" layer="19" extent="1-1"/>
<wire x1="56.6534" y1="18.0086" x2="55.1434" y2="28.4086" width="0" layer="19" extent="1-1"/>
<wire x1="65.5828" y1="12.5192" x2="61.4172" y2="17.4104" width="0" layer="19" extent="1-1"/>
<wire x1="60.932" y1="5.0686" x2="65.5828" y2="12.5192" width="0" layer="19" extent="1-1"/>
<wire x1="5.0686" y1="53.9496" x2="5.1816" y2="40.767" width="0" layer="19" extent="1-1"/>
<wire x1="5.221" y1="69.0372" x2="5.1816" y2="55.7022" width="0" layer="19" extent="1-1"/>
<wire x1="4.9428" y1="84.582" x2="5.1816" y2="70.9422" width="0" layer="19" extent="1-1"/>
<wire x1="5.334" y1="18.9738" x2="15.3924" y2="33.2232" width="0" layer="19" extent="1-1"/>
<wire x1="5.4864" y1="3.429" x2="5.334" y2="16.1544" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="GND">
<contactref element="IC2" pad="16"/>
@ -6567,7 +6646,7 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<via x="47.4472" y="98.3488" extent="1-16" drill="0.3"/>
<via x="35.6108" y="97.6884" extent="1-16" drill="0.3"/>
<via x="33.5788" y="97.6884" extent="1-16" drill="0.3"/>
<via x="17.3228" y="98.7044" extent="1-16" drill="0.3"/>
<via x="16.256" y="98.7044" extent="1-16" drill="0.3"/>
<via x="1.8288" y="83.3628" extent="1-16" drill="0.3"/>
<via x="45.5676" y="86.9696" extent="1-16" drill="0.3"/>
<via x="42.418" y="19.8628" extent="1-16" drill="0.3"/>
@ -6575,7 +6654,7 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<via x="47.4472" y="57.9628" extent="1-16" drill="0.3"/>
<via x="48.3616" y="57.9628" extent="1-16" drill="0.3"/>
<via x="70.612" y="60.8076" extent="1-16" drill="0.3"/>
<via x="78.74" y="39.5224" extent="1-16" drill="0.3"/>
<wire x1="78.74" y1="39.5224" x2="78.74" y2="39.5224" width="0" layer="19" extent="1-16"/>
<via x="77.1906" y="39.5224" extent="1-16" drill="0.3"/>
<wire x1="47.5742" y1="55.1294" x2="47.766" y2="55.3212" width="0.6096" layer="1"/>
<wire x1="47.766" y1="55.3212" x2="48.8696" y2="55.3212" width="0.6096" layer="1"/>
@ -6717,19 +6796,7 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="76.7956" y1="31.75" x2="76.7956" y2="30.72" width="0.4064" layer="1"/>
<wire x1="76.7956" y1="30.72" x2="76.7842" y2="30.7086" width="0.4064" layer="1"/>
<via x="76.7842" y="30.7086" extent="1-16" drill="0.3"/>
<contactref element="IC4" pad="19"/>
<contactref element="IC8" pad="19"/>
<contactref element="IC9" pad="19"/>
<via x="7.5692" y="82.3976" extent="1-16" drill="0.3"/>
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@ -6746,6 +6813,188 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
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<wire x1="74.3204" y1="49.6824" x2="78.8416" y2="57.0484" width="0" layer="19" extent="1-1"/>
<wire x1="73.6486" y1="46.609" x2="74.3204" y2="49.6824" width="0" layer="19" extent="1-1"/>
<wire x1="77.1906" y1="39.5224" x2="73.6486" y2="46.609" width="0" layer="19" extent="1-1"/>
<wire x1="78.74" y1="39.5224" x2="77.1906" y2="39.5224" width="0" layer="19" extent="1-1"/>
<wire x1="77.1144" y1="34.5948" x2="77.1906" y2="39.5224" width="0" layer="19" extent="1-1"/>
<wire x1="76.7956" y1="31.75" x2="77.1144" y2="34.5948" width="0" layer="19" extent="1-1"/>
<wire x1="80.1624" y1="34.5948" x2="77.1144" y2="34.5948" width="0" layer="19" extent="1-1"/>
<wire x1="88.4936" y1="32.4612" x2="80.1624" y2="34.5948" width="0" layer="19" extent="1-1"/>
<wire x1="91.5416" y1="32.3088" x2="88.4936" y2="32.4612" width="0" layer="19" extent="1-1"/>
<wire x1="1.9304" y1="30.2006" x2="7.0104" y2="37.6428" width="0" layer="19" extent="1-1"/>
<wire x1="88.4936" y1="42.672" x2="88.4936" y2="32.4612" width="0" layer="19" extent="1-1"/>
<wire x1="88.4936" y1="52.8828" x2="88.4936" y2="42.672" width="0" layer="19" extent="1-1"/>
<wire x1="88.4936" y1="62.9412" x2="88.4936" y2="52.8828" width="0" layer="19" extent="1-1"/>
<wire x1="91.5416" y1="62.7888" x2="88.4936" y2="62.9412" width="0" layer="19" extent="1-1"/>
<wire x1="88.4936" y1="72.9996" x2="88.4936" y2="62.9412" width="0" layer="19" extent="1-1"/>
<wire x1="88.3412" y1="83.2104" x2="88.4936" y2="72.9996" width="0" layer="19" extent="1-1"/>
<wire x1="88.4936" y1="22.2504" x2="88.4936" y2="32.4612" width="0" layer="19" extent="1-1"/>
<wire x1="87.63" y1="15.9512" x2="88.4936" y2="22.2504" width="0" layer="19" extent="1-1"/>
<wire x1="87.63" y1="13.4112" x2="87.63" y2="15.9512" width="0" layer="19" extent="1-1"/>
<wire x1="88.4936" y1="12.192" x2="87.63" y2="13.4112" width="0" layer="19" extent="1-1"/>
<wire x1="91.694" y1="12.3444" x2="88.4936" y2="12.192" width="0" layer="19" extent="1-1"/>
<wire x1="91.6432" y1="2.3368" x2="91.694" y2="12.3444" width="0" layer="19" extent="1-1"/>
<wire x1="91.6432" y1="1.2192" x2="91.6432" y2="2.3368" width="0" layer="19" extent="1-1"/>
<wire x1="90.2716" y1="1.2192" x2="91.6432" y2="1.2192" width="0" layer="19" extent="1-1"/>
<wire x1="57.2516" y1="30.1752" x2="58.5216" y2="19.9644" width="0" layer="19" extent="1-1"/>
<wire x1="52.6034" y1="29.8704" x2="57.2516" y2="30.1752" width="0" layer="19" extent="1-1"/>
<wire x1="62.4332" y1="35.1536" x2="57.263" y2="32.4612" width="0" layer="19" extent="1-1"/>
<wire x1="63.3476" y1="33.4772" x2="62.4332" y2="35.1536" width="0" layer="19" extent="1-1"/>
<wire x1="63.8048" y1="31.1912" x2="63.6016" y2="33.2232" width="0" layer="19" extent="1-1"/>
<wire x1="1.016" y1="97.9932" x2="1.8288" y2="83.3628" width="0" layer="19" extent="1-1"/>
<wire x1="1.016" y1="98.9076" x2="1.016" y2="97.9932" width="0" layer="19" extent="1-1"/>
</signal>
<signal name="A27">
<wire x1="82.55" y1="69.2912" x2="75.3872" y2="69.2912" width="0.1524" layer="16"/>
@ -7000,16 +7249,16 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="45.7896" y1="97.7712" x2="44.958" y2="98.6028" width="0.1524" layer="1"/>
<wire x1="44.958" y1="98.6028" x2="18.4404" y2="98.6028" width="0.1524" layer="1"/>
<wire x1="18.4404" y1="98.6028" x2="12.0396" y2="92.202" width="0.1524" layer="1"/>
<wire x1="12.0396" y1="92.202" x2="12.0396" y2="84.8868" width="0.1524" layer="1"/>
<wire x1="12.0396" y1="84.8868" x2="7.9248" y2="80.772" width="0.1524" layer="1"/>
<wire x1="12.0396" y1="92.202" x2="12.0396" y2="83.9724" width="0.1524" layer="1"/>
<wire x1="12.0396" y1="83.9724" x2="8.382" y2="80.3148" width="0.1524" layer="1"/>
<wire x1="7.9248" y1="4.8768" x2="7.747" y2="4.699" width="0.1524" layer="1"/>
<wire x1="7.747" y1="4.699" x2="5.4864" y2="4.699" width="0.1524" layer="1"/>
<wire x1="5.334" y1="20.2438" x2="7.4422" y2="20.2438" width="0.1524" layer="1"/>
<wire x1="7.4422" y1="20.2438" x2="7.9248" y2="20.7264" width="0.1524" layer="1"/>
<wire x1="7.9248" y1="20.7264" x2="7.9248" y2="80.772" width="0.1524" layer="1"/>
<wire x1="7.4422" y1="20.2438" x2="8.382" y2="21.1836" width="0.1524" layer="1"/>
<wire x1="7.4422" y1="20.2438" x2="7.493" y2="20.2438" width="0.1524" layer="1"/>
<wire x1="7.493" y1="20.2438" x2="7.9248" y2="19.812" width="0.1524" layer="1"/>
<wire x1="7.9248" y1="19.812" x2="7.9248" y2="4.8768" width="0.1524" layer="1"/>
<wire x1="8.382" y1="21.1836" x2="8.382" y2="80.3148" width="0.1524" layer="1"/>
</signal>
<signal name="AMIGA_DATA_DIR">
<contactref element="IC7" pad="48"/>
@ -7812,50 +8061,46 @@ minimale Strichstärke: &lt;b&gt;0.2 mm&lt;/b&gt;&lt;br&gt;&lt;br&gt;
<wire x1="45.72" y1="71.9328" x2="45.1104" y2="71.3232" width="0.1524" layer="1"/>
<wire x1="45.1104" y1="71.3232" x2="45.1104" y2="69.6468" width="0.1524" layer="1"/>
<wire x1="45.1104" y1="69.6468" x2="45.4152" y2="69.342" width="0.1524" layer="1"/>
<wire x1="45.4152" y1="69.342" x2="45.4152" y2="55.0164" width="0.1524" layer="1"/>
<wire x1="45.4152" y1="55.0164" x2="45.2628" y2="54.864" width="0.1524" layer="1"/>
<wire x1="45.2628" y1="54.864" x2="45.2628" y2="53.1876" width="0.1524" layer="1"/>
<wire x1="45.2628" y1="53.1876" x2="47.0916" y2="51.3588" width="0.1524" layer="1"/>
<wire x1="45.4152" y1="69.342" x2="45.4152" y2="53.0352" width="0.1524" layer="1"/>
<wire x1="45.4152" y1="53.0352" x2="47.0916" y2="51.3588" width="0.1524" layer="1"/>
</signal>
<signal name="RW_OUT">
<contactref element="IC7" pad="22"/>
<contactref element="IC9" pad="2"/>
<wire x1="51.7896" y1="91.3172" x2="50.11" y2="91.3172" width="0.1524" layer="1"/>
<wire x1="50.11" y1="91.3172" x2="49.3776" y2="92.0496" width="0.1524" layer="1"/>
<via x="49.3776" y="92.0496" extent="1-16" drill="0.3"/>
<wire x1="49.3776" y1="92.0496" x2="49.3776" y2="92.964" width="0.1524" layer="16"/>
<wire x1="49.3776" y1="92.964" x2="49.8348" y2="93.4212" width="0.1524" layer="16"/>
<wire x1="49.8348" y1="93.4212" x2="49.8348" y2="93.726" width="0.1524" layer="16"/>
<wire x1="49.8348" y1="93.726" x2="49.0728" y2="94.488" width="0.1524" layer="16"/>
<wire x1="49.0728" y1="94.488" x2="36.8808" y2="94.488" width="0.1524" layer="16"/>
<wire x1="36.8808" y1="94.488" x2="35.9664" y2="95.4024" width="0.1524" layer="16"/>
<wire x1="35.9664" y1="95.4024" x2="35.5092" y2="95.4024" width="0.1524" layer="16"/>
<wire x1="35.5092" y1="95.4024" x2="34.5948" y2="94.488" width="0.1524" layer="16"/>
<wire x1="34.5948" y1="94.488" x2="31.6992" y2="94.488" width="0.1524" layer="16"/>
<wire x1="31.6992" y1="94.488" x2="31.5468" y2="94.3356" width="0.1524" layer="16"/>
<wire x1="31.5468" y1="94.3356" x2="30.9372" y2="94.3356" width="0.1524" layer="16"/>
<wire x1="30.9372" y1="94.3356" x2="30.7848" y2="94.488" width="0.1524" layer="16"/>
<wire x1="30.7848" y1="94.488" x2="16.1544" y2="94.488" width="0.1524" layer="16"/>
<wire x1="16.1544" y1="94.488" x2="15.8496" y2="94.7928" width="0.1524" layer="16"/>
<wire x1="15.8496" y1="94.7928" x2="15.0876" y2="94.7928" width="0.1524" layer="16"/>
<wire x1="15.0876" y1="94.7928" x2="14.7828" y2="94.488" width="0.1524" layer="16"/>
<wire x1="14.7828" y1="94.488" x2="14.7828" y2="93.4212" width="0.1524" layer="16"/>
<via x="14.7828" y="93.4212" extent="1-16" drill="0.3"/>
<wire x1="14.7828" y1="93.4212" x2="14.7828" y2="93.1164" width="0.1524" layer="1"/>
<wire x1="14.7828" y1="93.1164" x2="13.5636" y2="91.8972" width="0.1524" layer="1"/>
<wire x1="13.5636" y1="91.8972" x2="13.5636" y2="42.3672" width="0.1524" layer="1"/>
<wire x1="13.5636" y1="42.3672" x2="13.8938" y2="42.037" width="0.1524" layer="1"/>
<wire x1="13.8938" y1="42.037" x2="15.24" y2="42.037" width="0.1524" layer="1"/>
<signal name="AMIGA_ADR_ENABLE">
<contactref element="IC4" pad="19"/>
<wire x1="5.1816" y1="72.2122" x2="5.207" y2="72.2376" width="0.1524" layer="1"/>
<wire x1="5.207" y1="72.2376" x2="6.096" y2="72.2376" width="0.1524" layer="1"/>
<contactref element="IC8" pad="19"/>
<wire x1="5.1816" y1="56.9722" x2="5.207" y2="56.9976" width="0.1524" layer="1"/>
<contactref element="IC9" pad="19"/>
<wire x1="5.1816" y1="42.037" x2="5.207" y2="42.0624" width="0.1524" layer="1"/>
<wire x1="5.207" y1="42.0624" x2="6.7056" y2="42.0624" width="0.1524" layer="1"/>
<contactref element="IC7" pad="33"/>
<wire x1="46.2896" y1="94.8172" x2="46.2896" y2="97.7284" width="0.1524" layer="1"/>
<wire x1="46.2896" y1="97.7284" x2="45.1104" y2="98.9076" width="0.1524" layer="1"/>
<wire x1="45.1104" y1="98.9076" x2="17.9832" y2="98.9076" width="0.1524" layer="1"/>
<wire x1="17.9832" y1="98.9076" x2="11.5824" y2="92.5068" width="0.1524" layer="1"/>
<wire x1="11.5824" y1="92.5068" x2="11.5824" y2="84.4296" width="0.1524" layer="1"/>
<wire x1="11.5824" y1="84.4296" x2="7.62" y2="80.4672" width="0.1524" layer="1"/>
<wire x1="7.62" y1="80.4672" x2="7.62" y2="73.152" width="0.1524" layer="1"/>
<wire x1="6.096" y1="72.2376" x2="7.7724" y2="70.5612" width="0.1524" layer="1"/>
<wire x1="7.7724" y1="70.5612" x2="7.7724" y2="58.674" width="0.1524" layer="1"/>
<wire x1="7.7724" y1="43.1292" x2="6.7056" y2="42.0624" width="0.1524" layer="1"/>
<wire x1="5.207" y1="56.9976" x2="6.096" y2="56.9976" width="0.1524" layer="1"/>
<wire x1="6.096" y1="56.9976" x2="7.7724" y2="58.674" width="0.1524" layer="1"/>
<wire x1="7.7724" y1="43.1292" x2="7.7724" y2="55.3212" width="0.1524" layer="1"/>
<wire x1="7.7724" y1="55.3212" x2="6.096" y2="56.9976" width="0.1524" layer="1"/>
<wire x1="7.62" y1="73.152" x2="7.1628" y2="72.6948" width="0.1524" layer="1"/>
<wire x1="7.1628" y1="72.6948" x2="6.5532" y2="72.6948" width="0.1524" layer="1"/>
<wire x1="6.5532" y1="72.6948" x2="6.096" y2="72.2376" width="0.1524" layer="1"/>
</signal>
</signals>
<errors>
<approved hash="18,30,933d5dc68ee6b8e9"/>
<approved hash="18,30,c2185cc68efeee34"/>
<approved hash="18,30,a5d25a4e8a6e8dce"/>
<approved hash="18,30,1b42dc4e8e6fb74c"/>
<approved hash="18,30,4daddc4e8f67e619"/>
<approved hash="18,30,1b42dc4e8e6fb74c"/>
<approved hash="18,30,a5d25a4e8a6e8dce"/>
<approved hash="18,30,f646dbc696e743f0"/>
<approved hash="18,30,3849587e8adf1064"/>
<approved hash="18,30,c2185cc68efeee34"/>
<approved hash="18,30,93e4923c922593fd"/>
<approved hash="18,30,a0a8a9f4a989a0d5"/>
</errors>

View File

@ -10116,7 +10116,6 @@ Source: RS Component / Phycomp</description>
<part name="R11" library="rcl" deviceset="R-EU_" device="R0603"/>
<part name="R14" library="rcl" deviceset="R-EU_" device="R0603"/>
<part name="R16" library="rcl" deviceset="R-EU_" device="R0603"/>
<part name="R17" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
</parts>
<sheets>
<sheet>
@ -10165,7 +10164,6 @@ Source: RS Component / Phycomp</description>
<instance part="RN3" gate="D" x="-2.54" y="132.08"/>
<instance part="R8" gate="G$1" x="-2.54" y="121.92"/>
<instance part="R9" gate="G$1" x="-2.54" y="116.84"/>
<instance part="R17" gate="G$1" x="-2.54" y="93.98"/>
</instances>
<busses>
<bus name="A[0..31]">
@ -10916,11 +10914,6 @@ Source: RS Component / Phycomp</description>
<wire x1="96.52" y1="124.46" x2="91.44" y2="124.46" width="0.1524" layer="91"/>
<label x="91.44" y="124.46" size="1.27" layer="95" rot="R180" xref="yes"/>
</segment>
<segment>
<pinref part="R17" gate="G$1" pin="2"/>
<wire x1="2.54" y1="93.98" x2="10.16" y2="93.98" width="0.1524" layer="91"/>
<label x="10.16" y="93.98" size="1.778" layer="95"/>
</segment>
</net>
<net name="CIIN" class="0">
<segment>
@ -11382,12 +11375,8 @@ Source: RS Component / Phycomp</description>
<pinref part="R9" gate="G$1" pin="1"/>
<wire x1="-7.62" y1="116.84" x2="-20.32" y2="116.84" width="0.1524" layer="91"/>
<pinref part="R2" gate="G$1" pin="2"/>
<wire x1="-20.32" y1="91.44" x2="-20.32" y2="93.98" width="0.1524" layer="91"/>
<wire x1="-20.32" y1="91.44" x2="-20.32" y2="101.6" width="0.1524" layer="91"/>
<junction x="-20.32" y="101.6"/>
<pinref part="R17" gate="G$1" pin="1"/>
<wire x1="-20.32" y1="93.98" x2="-20.32" y2="101.6" width="0.1524" layer="91"/>
<wire x1="-7.62" y1="93.98" x2="-20.32" y2="93.98" width="0.1524" layer="91"/>
<junction x="-20.32" y="93.98"/>
</segment>
<segment>
<pinref part="C19" gate="G$1" pin="1"/>
@ -12571,9 +12560,9 @@ Source: RS Component / Phycomp</description>
</net>
<net name="AS_00" class="0">
<segment>
<pinref part="IC7" gate="G$1" pin="IO1"/>
<wire x1="104.14" y1="116.84" x2="104.14" y2="121.92" width="0.1524" layer="91"/>
<label x="104.14" y="121.92" size="1.27" layer="95" rot="R90"/>
<pinref part="IC7" gate="G$1" pin="IO29"/>
<wire x1="101.6" y1="25.4" x2="101.6" y2="30.48" width="0.1524" layer="91"/>
<label x="101.6" y="25.4" size="1.27" layer="95" rot="R270"/>
</segment>
</net>
<net name="CS_FPU" class="0">
@ -12609,6 +12598,11 @@ Source: RS Component / Phycomp</description>
</net>
<net name="AVEC" class="0">
<segment>
<pinref part="IC7" gate="G$1" pin="IO1"/>
<wire x1="104.14" y1="116.84" x2="104.14" y2="121.92" width="0.1524" layer="91"/>
<label x="104.14" y="121.92" size="1.27" layer="95" rot="R90"/>
</segment>
<segment>
<label x="238.76" y="76.2" size="1.27" layer="95" xref="yes"/>
<pinref part="X1" gate="-A13" pin="B"/>
<wire x1="236.22" y1="76.2" x2="238.76" y2="76.2" width="0.1524" layer="91"/>
@ -13168,9 +13162,9 @@ Source: RS Component / Phycomp</description>
<wire x1="180.34" y1="33.02" x2="182.88" y2="33.02" width="0.1524" layer="91"/>
</segment>
<segment>
<pinref part="IC7" gate="G$1" pin="IO23"/>
<wire x1="71.12" y1="50.8" x2="66.04" y2="50.8" width="0.1524" layer="91"/>
<label x="66.04" y="50.8" size="1.27" layer="95" rot="R180"/>
<pinref part="IC7" gate="G$1" pin="IO33"/>
<wire x1="124.46" y1="30.48" x2="124.46" y2="27.94" width="0.1524" layer="91"/>
<label x="124.46" y="27.94" size="1.27" layer="95" rot="R270"/>
</segment>
</net>
<net name="A3" class="0">
@ -13412,16 +13406,9 @@ Source: RS Component / Phycomp</description>
</net>
<net name="RW_OUT" class="0">
<segment>
<pinref part="IC7" gate="G$1" pin="IO33"/>
<wire x1="124.46" y1="30.48" x2="124.46" y2="27.94" width="0.1524" layer="91"/>
<label x="124.46" y="27.94" size="1.27" layer="95" rot="R270"/>
</segment>
</net>
<net name="AMIGA_ADR_ENABLE" class="0">
<segment>
<pinref part="IC7" gate="G$1" pin="IO29"/>
<wire x1="101.6" y1="25.4" x2="101.6" y2="30.48" width="0.1524" layer="91"/>
<label x="101.6" y="25.4" size="1.27" layer="95" rot="R270"/>
<pinref part="IC7" gate="G$1" pin="IO23"/>
<wire x1="71.12" y1="50.8" x2="66.04" y2="50.8" width="0.1524" layer="91"/>
<label x="66.04" y="50.8" size="1.27" layer="95" rot="R180"/>
</segment>
</net>
</nets>
@ -13761,6 +13748,21 @@ Source: RS Component / Phycomp</description>
<wire x1="111.76" y1="15.24" x2="111.76" y2="12.7" width="0.1524" layer="91"/>
<junction x="111.76" y="12.7"/>
</segment>
<segment>
<pinref part="IC4" gate="A" pin="G"/>
<wire x1="40.64" y1="139.7" x2="45.72" y2="139.7" width="0.1524" layer="91"/>
<label x="45.72" y="139.7" size="1.27" layer="95"/>
</segment>
<segment>
<pinref part="IC8" gate="A" pin="G"/>
<wire x1="40.64" y1="99.06" x2="45.72" y2="99.06" width="0.1524" layer="91"/>
<label x="45.72" y="99.06" size="1.27" layer="95"/>
</segment>
<segment>
<pinref part="IC9" gate="A" pin="G"/>
<wire x1="40.64" y1="60.96" x2="45.72" y2="60.96" width="0.1524" layer="91"/>
<label x="45.72" y="60.96" size="1.27" layer="95"/>
</segment>
</net>
<net name="VCC" class="0">
<segment>
@ -14391,23 +14393,6 @@ Source: RS Component / Phycomp</description>
<label x="45.72" y="86.36" size="1.27" layer="95"/>
</segment>
</net>
<net name="AMIGA_ADR_ENABLE" class="0">
<segment>
<pinref part="IC4" gate="A" pin="G"/>
<wire x1="40.64" y1="139.7" x2="45.72" y2="139.7" width="0.1524" layer="91"/>
<label x="45.72" y="139.7" size="1.27" layer="95"/>
</segment>
<segment>
<pinref part="IC8" gate="A" pin="G"/>
<wire x1="40.64" y1="99.06" x2="45.72" y2="99.06" width="0.1524" layer="91"/>
<label x="45.72" y="99.06" size="1.27" layer="95"/>
</segment>
<segment>
<pinref part="IC9" gate="A" pin="G"/>
<wire x1="40.64" y1="60.96" x2="45.72" y2="60.96" width="0.1524" layer="91"/>
<label x="45.72" y="60.96" size="1.27" layer="95"/>
</segment>
</net>
</nets>
</sheet>
</sheets>

View File

@ -10116,6 +10116,7 @@ Source: RS Component / Phycomp</description>
<part name="R11" library="rcl" deviceset="R-EU_" device="R0603"/>
<part name="R14" library="rcl" deviceset="R-EU_" device="R0603"/>
<part name="R16" library="rcl" deviceset="R-EU_" device="R0603"/>
<part name="R17" library="rcl" deviceset="R-EU_" device="R0603" value="4,7k"/>
</parts>
<sheets>
<sheet>
@ -10164,6 +10165,7 @@ Source: RS Component / Phycomp</description>
<instance part="RN3" gate="D" x="-2.54" y="132.08"/>
<instance part="R8" gate="G$1" x="-2.54" y="121.92"/>
<instance part="R9" gate="G$1" x="-2.54" y="116.84"/>
<instance part="R17" gate="G$1" x="-2.54" y="93.98"/>
</instances>
<busses>
<bus name="A[0..31]">
@ -10914,6 +10916,11 @@ Source: RS Component / Phycomp</description>
<wire x1="96.52" y1="124.46" x2="91.44" y2="124.46" width="0.1524" layer="91"/>
<label x="91.44" y="124.46" size="1.27" layer="95" rot="R180" xref="yes"/>
</segment>
<segment>
<pinref part="R17" gate="G$1" pin="2"/>
<wire x1="2.54" y1="93.98" x2="10.16" y2="93.98" width="0.1524" layer="91"/>
<label x="10.16" y="93.98" size="1.778" layer="95"/>
</segment>
</net>
<net name="CIIN" class="0">
<segment>
@ -11375,8 +11382,12 @@ Source: RS Component / Phycomp</description>
<pinref part="R9" gate="G$1" pin="1"/>
<wire x1="-7.62" y1="116.84" x2="-20.32" y2="116.84" width="0.1524" layer="91"/>
<pinref part="R2" gate="G$1" pin="2"/>
<wire x1="-20.32" y1="91.44" x2="-20.32" y2="101.6" width="0.1524" layer="91"/>
<wire x1="-20.32" y1="91.44" x2="-20.32" y2="93.98" width="0.1524" layer="91"/>
<junction x="-20.32" y="101.6"/>
<pinref part="R17" gate="G$1" pin="1"/>
<wire x1="-20.32" y1="93.98" x2="-20.32" y2="101.6" width="0.1524" layer="91"/>
<wire x1="-7.62" y1="93.98" x2="-20.32" y2="93.98" width="0.1524" layer="91"/>
<junction x="-20.32" y="93.98"/>
</segment>
<segment>
<pinref part="C19" gate="G$1" pin="1"/>
@ -12558,13 +12569,6 @@ Source: RS Component / Phycomp</description>
<label x="99.06" y="25.4" size="1.27" layer="95" rot="R270"/>
</segment>
</net>
<net name="AS_00" class="0">
<segment>
<pinref part="IC7" gate="G$1" pin="IO29"/>
<wire x1="101.6" y1="25.4" x2="101.6" y2="30.48" width="0.1524" layer="91"/>
<label x="101.6" y="25.4" size="1.27" layer="95" rot="R270"/>
</segment>
</net>
<net name="CS_FPU" class="0">
<segment>
<pinref part="IC7" gate="G$1" pin="IO56"/>
@ -12598,15 +12602,15 @@ Source: RS Component / Phycomp</description>
</net>
<net name="AVEC" class="0">
<segment>
<pinref part="IC7" gate="G$1" pin="IO1"/>
<wire x1="104.14" y1="116.84" x2="104.14" y2="121.92" width="0.1524" layer="91"/>
<label x="104.14" y="121.92" size="1.27" layer="95" rot="R90"/>
</segment>
<segment>
<label x="238.76" y="76.2" size="1.27" layer="95" xref="yes"/>
<pinref part="X1" gate="-A13" pin="B"/>
<wire x1="236.22" y1="76.2" x2="238.76" y2="76.2" width="0.1524" layer="91"/>
</segment>
<segment>
<pinref part="IC7" gate="G$1" pin="IO1"/>
<wire x1="104.14" y1="116.84" x2="104.14" y2="121.92" width="0.1524" layer="91"/>
<label x="104.14" y="121.92" size="1.27" layer="95" rot="R90"/>
</segment>
</net>
<net name="BG_30" class="0">
<segment>
@ -13162,9 +13166,9 @@ Source: RS Component / Phycomp</description>
<wire x1="180.34" y1="33.02" x2="182.88" y2="33.02" width="0.1524" layer="91"/>
</segment>
<segment>
<pinref part="IC7" gate="G$1" pin="IO33"/>
<wire x1="124.46" y1="30.48" x2="124.46" y2="27.94" width="0.1524" layer="91"/>
<label x="124.46" y="27.94" size="1.27" layer="95" rot="R270"/>
<pinref part="IC7" gate="G$1" pin="IO23"/>
<wire x1="71.12" y1="50.8" x2="66.04" y2="50.8" width="0.1524" layer="91"/>
<label x="66.04" y="50.8" size="1.27" layer="95" rot="R180"/>
</segment>
</net>
<net name="A3" class="0">
@ -13404,11 +13408,18 @@ Source: RS Component / Phycomp</description>
<label x="106.68" y="121.92" size="1.27" layer="95" rot="R90"/>
</segment>
</net>
<net name="RW_OUT" class="0">
<net name="AMIGA_ADR_ENABLE" class="0">
<segment>
<pinref part="IC7" gate="G$1" pin="IO23"/>
<wire x1="71.12" y1="50.8" x2="66.04" y2="50.8" width="0.1524" layer="91"/>
<label x="66.04" y="50.8" size="1.27" layer="95" rot="R180"/>
<pinref part="IC7" gate="G$1" pin="IO29"/>
<wire x1="101.6" y1="25.4" x2="101.6" y2="30.48" width="0.1524" layer="91"/>
<label x="101.6" y="25.4" size="1.27" layer="95" rot="R270"/>
</segment>
</net>
<net name="AS_00" class="0">
<segment>
<pinref part="IC7" gate="G$1" pin="IO33"/>
<wire x1="124.46" y1="30.48" x2="124.46" y2="27.94" width="0.1524" layer="91"/>
<label x="124.46" y="27.94" size="1.27" layer="95" rot="R270"/>
</segment>
</net>
</nets>
@ -13748,21 +13759,6 @@ Source: RS Component / Phycomp</description>
<wire x1="111.76" y1="15.24" x2="111.76" y2="12.7" width="0.1524" layer="91"/>
<junction x="111.76" y="12.7"/>
</segment>
<segment>
<pinref part="IC4" gate="A" pin="G"/>
<wire x1="40.64" y1="139.7" x2="45.72" y2="139.7" width="0.1524" layer="91"/>
<label x="45.72" y="139.7" size="1.27" layer="95"/>
</segment>
<segment>
<pinref part="IC8" gate="A" pin="G"/>
<wire x1="40.64" y1="99.06" x2="45.72" y2="99.06" width="0.1524" layer="91"/>
<label x="45.72" y="99.06" size="1.27" layer="95"/>
</segment>
<segment>
<pinref part="IC9" gate="A" pin="G"/>
<wire x1="40.64" y1="60.96" x2="45.72" y2="60.96" width="0.1524" layer="91"/>
<label x="45.72" y="60.96" size="1.27" layer="95"/>
</segment>
</net>
<net name="VCC" class="0">
<segment>
@ -14386,7 +14382,24 @@ Source: RS Component / Phycomp</description>
<label x="5.08" y="147.32" size="1.27" layer="95"/>
</segment>
</net>
<net name="RW_OUT" class="0">
<net name="AMIGA_ADR_ENABLE" class="0">
<segment>
<pinref part="IC4" gate="A" pin="G"/>
<wire x1="40.64" y1="139.7" x2="45.72" y2="139.7" width="0.1524" layer="91"/>
<label x="45.72" y="139.7" size="1.27" layer="95"/>
</segment>
<segment>
<pinref part="IC8" gate="A" pin="G"/>
<wire x1="40.64" y1="99.06" x2="45.72" y2="99.06" width="0.1524" layer="91"/>
<label x="45.72" y="99.06" size="1.27" layer="95"/>
</segment>
<segment>
<pinref part="IC9" gate="A" pin="G"/>
<wire x1="40.64" y1="60.96" x2="45.72" y2="60.96" width="0.1524" layer="91"/>
<label x="45.72" y="60.96" size="1.27" layer="95"/>
</segment>
</net>
<net name="R/W" class="0">
<segment>
<pinref part="IC9" gate="A" pin="A1"/>
<wire x1="40.64" y1="86.36" x2="45.72" y2="86.36" width="0.1524" layer="91"/>

View File

@ -1,7 +1,7 @@
-- Copyright: Matthias Heinrichs 2014
-- Free for non-comercial use
-- No warranty just for fun
-- I you want to earn money with this code, ask me first!
-- If you want to earn money with this code, ask me first!
@ -508,4 +508,3 @@ begin
'1';
BGACK_030 <= BGACK_030_INT;
end Behavioral;

View File

@ -1,4 +1,4 @@
[synthesis-type]
tool=Synplify
[STRATEGY-LIST]
Normal=True, 1385910337
[synthesis-type]
tool=Synplify

File diff suppressed because it is too large Load Diff

View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
#$ DATE Wed May 28 21:24:55 2014
#$ DATE Thu May 29 22:04:27 2014
#$ MODULE 68030_tk
#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ \
# IPL_030_0_ IPL_2_ IPL_1_ IPL_0_ DSACK_1_ DSACK_0_ FC_0_ FC_1_ AS_030 AS_000 DS_030 \

View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
#$ DATE Wed May 28 21:24:55 2014
#$ DATE Thu May 29 22:04:27 2014
#$ MODULE 68030_tk
#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ \
# IPL_030_0_ IPL_2_ IPL_1_ IPL_0_ DSACK_1_ DSACK_0_ FC_0_ FC_1_ AS_030 AS_000 DS_030 \

View File

@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 1.7.00.05.28.13
// Design '68030_tk' created Wed May 28 21:24:55 2014
// Design '68030_tk' created Thu May 29 22:04:27 2014
// LEGEND: '>' Functional Block Port Separator

View File

@ -2,7 +2,7 @@
Copyright(C), 1992-2013, Lattice Semiconductor Corp.
All Rights Reserved.
Design bus68030 created Wed May 28 21:24:55 2014
Design bus68030 created Thu May 29 22:04:27 2014
P-Terms Fan-in Fan-out Type Name (attributes)

View File

@ -1 +1 @@
<LATTICE_ENCRYPTED_BLIF>5826467DGX@r^.
<LATTICE_ENCRYPTED_BLIF>77:0=67 (zS'4<

View File

@ -10,7 +10,7 @@ AUTHOR:
PATTERN:
COMPANY:
REVISION:
DATE: Wed May 28 21:25:00 2014
DATE: Thu May 29 22:04:32 2014
ABEL mach447a
*

View File

@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $";
Parent = m4a5.lci;
SDS_File = m4a5.sds;
Design = 68030_tk.tt4;
DATE = 5/28/14;
TIME = 21:25:00;
DATE = 5/29/14;
TIME = 22:04:32;
Source_Format = Pure_VHDL;
Type = TT2;
Pre_Fit_Time = 1;

File diff suppressed because it is too large Load Diff

View File

@ -8,7 +8,7 @@
; Source file 68030_tk.tt4
; FITTER-generated Placements.
; DEVICE mach447a
; DATE Wed May 28 21:25:00 2014
; DATE Thu May 29 22:04:32 2014
Pin 94 A_21_

View File

@ -5,8 +5,8 @@
|--------------------------------------------|
Start: Wed May 28 21:24:59 2014
End : Wed May 28 21:25:00 2014 $$$ Elapsed time: 00:00:01
Start: Thu May 29 22:04:32 2014
End : Thu May 29 22:04:32 2014 $$$ Elapsed time: 00:00:00
===========================================================================
Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4]

View File

@ -12,7 +12,7 @@ Project_Summary
Project Name : 68030_tk
Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic
Project Fitted on : Wed May 28 21:25:00 2014
Project Fitted on : Thu May 29 22:04:32 2014
Device : M4A5-128/64
Package : 100TQFP

View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
#$ DATE Wed May 28 21:24:55 2014
#$ DATE Thu May 29 22:04:27 2014
#$ MODULE 68030_tk
#$ PINS 59 A_21_ A_20_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ FC_1_ nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ SIZE_1_ IPL_030_2_ IPL_030_1_ IPL_030_0_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS E VMA RESET AMIGA_BUS_ENABLE SIZE_0_
#$ NODES 24 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D4 inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_6_ SM_AMIGA_5_ inst_CLK_000_D3 inst_CLK_030_H SM_AMIGA_7_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_

View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
#$ DATE Wed May 28 21:24:55 2014
#$ DATE Thu May 29 22:04:27 2014
#$ MODULE 68030_tk
#$ PINS 59 A_21_ A_20_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ IPL_1_ IPL_0_ DSACK_0_ FC_0_ FC_1_ nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT DTACK AVEC AVEC_EXP VPA RST RW AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ SIZE_1_ IPL_030_2_ IPL_030_1_ IPL_030_0_ DSACK_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 BG_000 BGACK_030 CLK_EXP FPU_CS E VMA RESET AMIGA_BUS_ENABLE SIZE_0_
#$ NODES 24 inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_VPA_D inst_CLK_OUT_PRE_50_D inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_000_D2 inst_CLK_000_D4 inst_DTACK_D0 inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE_25 SM_AMIGA_1_ SM_AMIGA_0_ SM_AMIGA_6_ SM_AMIGA_5_ inst_CLK_000_D3 inst_CLK_030_H SM_AMIGA_7_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_2_ cpu_est_0_ cpu_est_1_ cpu_est_2_

View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
#$ DATE Wed May 28 21:24:55 2014
#$ DATE Thu May 29 22:04:27 2014
#$ MODULE BUS68030
#$ PINS 59 A_21_ A_20_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ IPL_1_ IPL_0_
DSACK_0_ FC_0_ FC_1_ nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI

View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
#$ DATE Wed May 28 21:24:55 2014
#$ DATE Thu May 29 22:04:27 2014
#$ MODULE BUS68030
#$ PINS 59 A_21_ A_20_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ IPL_1_ IPL_0_
DSACK_0_ FC_0_ FC_1_ nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI

View File

@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 5/28/14;
TIME = 21:24:59;
DATE = 5/29/14;
TIME = 22:04:32;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;

View File

@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
DATE = 5/28/14;
TIME = 21:25:00;
DATE = 5/29/14;
TIME = 22:04:32;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;

View File

@ -2,7 +2,7 @@ Signal Name Cross Reference File
ispLEVER Classic 1.7.00.05.28.13
Design '68030_tk' created Wed May 28 21:24:55 2014
Design '68030_tk' created Thu May 29 22:04:27 2014
LEGEND: '>' Functional Block Port Separator

View File

@ -1,4 +1,4 @@
#$ DATE Wed May 28 21:24:55 2014
#$ DATE Thu May 29 22:04:27 2014
#$ TOOL EDIF2BLIF version IspLever 1.0
#$ MODULE bus68030
#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ IPL_2_ IPL_1_ IPL_0_ DSACK_1_ DSACK_0_ FC_0_ FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 A0 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_

View File

@ -1,5 +1,5 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
#$ DATE Wed May 28 21:24:55 2014
#$ DATE Thu May 29 22:04:27 2014
#$ MODULE bus68030
#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ \
# IPL_030_0_ IPL_2_ IPL_1_ IPL_0_ DSACK_1_ DSACK_0_ FC_0_ FC_1_ AS_030 AS_000 DS_030 \

View File

@ -4,7 +4,7 @@
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2014 5 28 21 24 50)
(timeStamp 2014 5 29 22 4 22)
(author "Synopsys, Inc.")
(program "Synplify Pro" (version "G-2012.09LC-SP1 , mapper maplat, Build 621R"))
)

View File

@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
#-- Written on Wed May 28 21:24:48 2014
#-- Written on Thu May 29 22:04:20 2014
#device options

View File

@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Wed May 28 21:24:48 2014
#Thu May 29 22:04:21 2014
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
@N|Running in 64-bit mode
@ -53,7 +53,7 @@ State machine has 11 reachable states with original encodings of:
1111
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed May 28 21:24:49 2014
# Thu May 29 22:04:21 2014
###########################################################]
Map & Optimize Report
@ -109,6 +109,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed May 28 21:24:50 2014
# Thu May 29 22:04:22 2014
###########################################################]

Binary file not shown.

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@ -19,8 +19,8 @@
<BScanVal>0</BScanVal>
</Bypass>
<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
<FileTime>05/17/14 14:58:17</FileTime>
<JedecChecksum>0x7C8A</JedecChecksum>
<FileTime>05/29/14 11:52:27</FileTime>
<JedecChecksum>0x8531</JedecChecksum>
<Operation>Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>

View File

@ -39,7 +39,7 @@ Section Member Rename Array-Notation Array Number
Port FC_0_ FC[0] 3 1
End
Section Cross Reference File
Design 'BUS68030' created Wed May 28 21:24:55 2014
Design 'BUS68030' created Thu May 29 22:04:27 2014
Type New Name Original Name
// ----------------------------------------------------------------------
Inst i_z2O2O AS_030

View File

@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Wed May 28 21:24:48 2014
#Thu May 29 22:04:21 2014
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
@N|Running in 64-bit mode
@ -53,7 +53,7 @@ State machine has 11 reachable states with original encodings of:
1111
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed May 28 21:24:49 2014
# Thu May 29 22:04:21 2014
###########################################################]
Map & Optimize Report
@ -109,6 +109,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed May 28 21:24:50 2014
# Thu May 29 22:04:22 2014
###########################################################]

View File

@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version G-2012.09LC-SP1
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
#-- Written on Wed May 28 21:24:48 2014
#-- Written on Thu May 29 22:04:21 2014
#project files

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@ -49,6 +49,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed May 28 21:24:50 2014
# Thu May 29 22:04:22 2014
###########################################################]

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@ -1,3 +1,4 @@
@E: CG119 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":367:34:367:35|Expecting closing )
@E|Parse errors encountered - exiting
@E: CD371 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":381:9:381:23|No matching overload for "="
@E: CD308 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":381:29:381:44|Unable to evaluate expression type
@E: CD676 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":381:29:381:44|Can't implement expression (no function signature?)

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@ -29,13 +29,13 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data>
</info>
<info name="Real Time">
<data>0h:00m:01s</data>
<data>0h:00m:00s</data>
</info>
<info name="Peak Memory">
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1401305089</data>
<data type="timestamp">1401393861</data>
</info>
</job_info>
</job_run_status>

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@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the
<data>95MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1401305090</data>
<data type="timestamp">1401393862</data>
</info>
</job_info>
</job_run_status>

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@ -3,7 +3,7 @@
Synopsys, Inc.
Version G-2012.09LC-SP1
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
Written on Wed May 28 21:24:48 2014
Written on Thu May 29 22:04:21 2014
-->

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@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1401305082
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1401393859
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

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@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1401305082
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1401393859
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

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