diff --git a/Layout and PCB/68030-TK-V09b.b#1 b/Layout and PCB/68030-TK-V09b.b#1
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+TOP
+Bot
+a1k.org 68030-TK v0.9b
+(c) 2013 Matthias
+Heinrichs
+a1k.org 68030-TK V0.9
+(c)2013 Matthias Heinrichs
+Free for non commercial
+reproduction
+
+JTAG
+
+
+
+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
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+>NAME
+>VALUE
+
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+<b>Dual In Line</b>
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+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
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+>NAME
+>VALUE
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+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>LeitOn Design-Regeln</b>
+<p>
+Diese DRU-Datei enthält viele erforderliche Design Einstellungen, damit Ihre Standardleiterplatte bei uns fehlerfrei und ohne Zusatzkosten produziert werden kann. Die Optionen Shapes und Misc sind nicht relevant und der minimale und maximale Wert für Roundness Shapes kann frei gewählt werden. Nach unten abweichende Design-Regeln sind möglich, können jedoch Aufpreise erfordern. Hinweis: Freistellungen und Streichstärken von Bestückungsdruck werden nicht im DRC geprüft!
+<br><br>
+<b>Ãœbersicht der LeitOn Regeln:</b<<br><br>
+<u>allgemein:</u><br>
+minimale Leiterbahnbreite/-abstand: <b>0.15 mm</b><br>
+(Strichstärke für Kupferschrift sollte mind. 0.2 mm sein um gut lesbar zu bleiben)<br>
+kleinster Bohrdurchmesser: <b>0.3 mm</b><br><br>
+<u>Kupferrestringe um DK-Bohrungen:</u><br>
+Aussenlagen: <b>0.15 mm</b><br>
+Innenlagen: <b>0.2 mm</b><br>
+<br>
+<u>Masselagen-Freimachungen:</u><br>
+Innenlagen: <b>0.35 mm</b><br>
+<br>
+<u>Bestückungsdruck</u><br>
+minimale Strichstärke: <b>0.2 mm</b><br><br>
+<b><u><font color= "blue">Wichtig:</font></b></u> Verwenden Sie als Strichstärke für Masseflächen keine Strichstärken kleiner 0.1mm. Es entstehen sonst extrem große Datenmengen, weil Eagle die Massefläche stets mit Polygonen der gleichen Strichstärke füllt.
+
+</p>
+
+
+
+
+
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+which will not be processed correctly with this version.
+
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diff --git a/Layout and PCB/68030-TK-V09b.brd b/Layout and PCB/68030-TK-V09b.brd
index b13efc1..a04b890 100644
--- a/Layout and PCB/68030-TK-V09b.brd
+++ b/Layout and PCB/68030-TK-V09b.brd
@@ -6315,6 +6315,60 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
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@@ -6370,7 +6424,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
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@@ -6460,7 +6513,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
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@@ -6683,8 +6733,6 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
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@@ -6736,9 +6784,191 @@ minimale Strichstärke: <b>0.2 mm</b><br><br>
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diff --git a/Layout and PCB/68030-TK-V09b.s#1 b/Layout and PCB/68030-TK-V09b.s#1
new file mode 100644
index 0000000..1e0f991
--- /dev/null
+++ b/Layout and PCB/68030-TK-V09b.s#1
@@ -0,0 +1,14401 @@
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+<b>Motorola MC68000 Processors</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>micro Ball Grid Array</b>
+
+
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+>NAME
+>VALUE
+
+
+<b>Dual In Line</b>
+
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+>NAME
+>VALUE
+
+
+<b>PLASTIC LEADED CHIP CARRIER</b><p>
+square
+
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+>NAME
+>VALUE
+
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+<b>PLCC Socked</b>
+
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+
+
+
+
+
+
+>VALUE
+>NAME
+68
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+VCC
+GND
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+VCC
+GND
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+GND
+VCC
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+<b>68xxx PROCESSOR</b>
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors, Capacitors, Inductors</b><p>
+Based on the previous libraries:
+<ul>
+<li>r.lbr
+<li>cap.lbr
+<li>cap-fe.lbr
+<li>captant.lbr
+<li>polcap.lbr
+<li>ipc-smd.lbr
+</ul>
+All SMD packages are defined according to the IPC specifications and CECC<p>
+<author>Created by librarian@cadsoft.de</author><p>
+<p>
+for Electrolyt Capacitors see also :<p>
+www.bccomponents.com <p>
+www.panasonic.com<p>
+www.kemet.com<p>
+http://www.secc.co.jp/pdf/os_e/2004/e_os_all.pdf <b>(SANYO)</b>
+<p>
+for trimmer refence see : <u>www.electrospec-inc.com/cross_references/trimpotcrossref.asp</u><p>
+
+<table border=0 cellspacing=0 cellpadding=0 width="100%" cellpaddding=0>
+<tr valign="top">
+
+<! <td width="10"> </td>
+<td width="90%">
+
+<b><font color="#0000FF" size="4">TRIM-POT CROSS REFERENCE</font></b>
+<P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=2>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=3 FACE=ARIAL><B>RECTANGULAR MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BOURNS</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">BI TECH</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">DALE-VISHAY</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PHILIPS/MEPCO</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MURATA</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">PANASONIC</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">SPECTROL</FONT>
+ </B>
+ </TD>
+ <TD ALIGN=CENTER>
+ <B>
+ <FONT SIZE=3 FACE=ARIAL color="#FF0000">MILSPEC</FONT>
+ </B>
+ </TD><TD> </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3 >
+ 3005P<BR>
+ 3006P<BR>
+ 3006W<BR>
+ 3006Y<BR>
+ 3009P<BR>
+ 3009W<BR>
+ 3009Y<BR>
+ 3057J<BR>
+ 3057L<BR>
+ 3057P<BR>
+ 3057Y<BR>
+ 3059J<BR>
+ 3059L<BR>
+ 3059P<BR>
+ 3059Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 89P<BR>
+ 89W<BR>
+ 89X<BR>
+ 89PH<BR>
+ 76P<BR>
+ 89XH<BR>
+ 78SLT<BR>
+ 78L ALT<BR>
+ 56P ALT<BR>
+ 78P ALT<BR>
+ T8S<BR>
+ 78L<BR>
+ 56P<BR>
+ 78P<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ T18/784<BR>
+ 783<BR>
+ 781<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2199<BR>
+ 1697/1897<BR>
+ 1680/1880<BR>
+ 2187<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 8035EKP/CT20/RJ-20P<BR>
+ -<BR>
+ RJ-20X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 1211L<BR>
+ 8012EKQ ALT<BR>
+ 8012EKR ALT<BR>
+ 1211P<BR>
+ 8012EKJ<BR>
+ 8012EKL<BR>
+ 8012EKQ<BR>
+ 8012EKR<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 2101P<BR>
+ 2101W<BR>
+ 2101Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 2102L<BR>
+ 2102S<BR>
+ 2102Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVMCOG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 43P<BR>
+ 43W<BR>
+ 43Y<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 40L<BR>
+ 40P<BR>
+ 40Y<BR>
+ 70Y-T602<BR>
+ 70L<BR>
+ 70P<BR>
+ 70Y<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ RT/RTR12<BR>
+ -<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR>
+ RJ/RJR12<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SQUARE MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3250L<BR>
+ 3250P<BR>
+ 3250W<BR>
+ 3250X<BR>
+ 3252P<BR>
+ 3252W<BR>
+ 3252X<BR>
+ 3260P<BR>
+ 3260W<BR>
+ 3260X<BR>
+ 3262P<BR>
+ 3262W<BR>
+ 3262X<BR>
+ 3266P<BR>
+ 3266W<BR>
+ 3266X<BR>
+ 3290H<BR>
+ 3290P<BR>
+ 3290W<BR>
+ 3292P<BR>
+ 3292W<BR>
+ 3292X<BR>
+ 3296P<BR>
+ 3296W<BR>
+ 3296X<BR>
+ 3296Y<BR>
+ 3296Z<BR>
+ 3299P<BR>
+ 3299W<BR>
+ 3299X<BR>
+ 3299Y<BR>
+ 3299Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66X ALT<BR>
+ -<BR>
+ 64W ALT<BR>
+ -<BR>
+ 64P ALT<BR>
+ 64W ALT<BR>
+ 64X ALT<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 66X ALT<BR>
+ 66P ALT<BR>
+ 66W ALT<BR>
+ 66P<BR>
+ 66W<BR>
+ 66X<BR>
+ 67P<BR>
+ 67W<BR>
+ 67X<BR>
+ 67Y<BR>
+ 67Z<BR>
+ 68P<BR>
+ 68W<BR>
+ 68X<BR>
+ 67Y ALT<BR>
+ 67Z ALT<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 5050<BR>
+ 5091<BR>
+ 5080<BR>
+ 5087<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T63YB<BR>
+ T63XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 5887<BR>
+ 5891<BR>
+ 5880<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ T93Z<BR>
+ T93YA<BR>
+ T93XA<BR>
+ T93YB<BR>
+ T93XB<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 8026EKP<BR>
+ 8026EKW<BR>
+ 8026EKM<BR>
+ 8026EKP<BR>
+ 8026EKB<BR>
+ 8026EKM<BR>
+ 1309X<BR>
+ 1309P<BR>
+ 1309W<BR>
+ 8024EKP<BR>
+ 8024EKW<BR>
+ 8024EKN<BR>
+ RJ-9P/CT9P<BR>
+ RJ-9W<BR>
+ RJ-9X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ 3103P<BR>
+ 3103Y<BR>
+ 3103Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3105P/3106P<BR>
+ 3105W/3106W<BR>
+ 3105X/3106X<BR>
+ 3105Y/3106Y<BR>
+ 3105Z/3105Z<BR>
+ 3102P<BR>
+ 3102W<BR>
+ 3102X<BR>
+ 3102Y<BR>
+ 3102Z<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMCBG<BR>
+ EVMCCG<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 55-1-X<BR>
+ 55-4-X<BR>
+ 55-3-X<BR>
+ 55-2-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 50-2-X<BR>
+ 50-4-X<BR>
+ 50-3-X<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 64P<BR>
+ 64W<BR>
+ 64X<BR>
+ 64Y<BR>
+ 64Z<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RT/RTR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RJ/RJR22<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RT/RTR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RJ/RJR26<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RT/RTR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ RJ/RJR24<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=8>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURN</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MURATA</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>SPECTROL</B></FONT>
+ </TD>
+ <TD ALIGN=CENTER>
+ <FONT SIZE=3 FACE=ARIAL><B>MILSPEC</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3323P<BR>
+ 3323S<BR>
+ 3323W<BR>
+ 3329H<BR>
+ 3329P<BR>
+ 3329W<BR>
+ 3339H<BR>
+ 3339P<BR>
+ 3339W<BR>
+ 3352E<BR>
+ 3352H<BR>
+ 3352K<BR>
+ 3352P<BR>
+ 3352T<BR>
+ 3352V<BR>
+ 3352W<BR>
+ 3362H<BR>
+ 3362M<BR>
+ 3362P<BR>
+ 3362R<BR>
+ 3362S<BR>
+ 3362U<BR>
+ 3362W<BR>
+ 3362X<BR>
+ 3386B<BR>
+ 3386C<BR>
+ 3386F<BR>
+ 3386H<BR>
+ 3386K<BR>
+ 3386M<BR>
+ 3386P<BR>
+ 3386S<BR>
+ 3386W<BR>
+ 3386X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 25P<BR>
+ 25S<BR>
+ 25RX<BR>
+ 82P<BR>
+ 82M<BR>
+ 82PA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 91E<BR>
+ 91X<BR>
+ 91T<BR>
+ 91B<BR>
+ 91A<BR>
+ 91V<BR>
+ 91W<BR>
+ 25W<BR>
+ 25V<BR>
+ 25P<BR>
+ -<BR>
+ 25S<BR>
+ 25U<BR>
+ 25RX<BR>
+ 25X<BR>
+ 72XW<BR>
+ 72XL<BR>
+ 72PM<BR>
+ 72RX<BR>
+ -<BR>
+ 72PX<BR>
+ 72P<BR>
+ 72RXW<BR>
+ 72RXL<BR>
+ 72X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ T7YB<BR>
+ T7YA<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ TXD<BR>
+ TYA<BR>
+ TYP<BR>
+ -<BR>
+ TYD<BR>
+ TX<BR>
+ -<BR>
+ 150SX<BR>
+ 100SX<BR>
+ 102T<BR>
+ 101S<BR>
+ 190T<BR>
+ 150TX<BR>
+ 101<BR>
+ -<BR>
+ -<BR>
+ 101SX<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ET6P<BR>
+ ET6S<BR>
+ ET6X<BR>
+ RJ-6W/8014EMW<BR>
+ RJ-6P/8014EMP<BR>
+ RJ-6X/8014EMX<BR>
+ TM7W<BR>
+ TM7P<BR>
+ TM7X<BR>
+ -<BR>
+ 8017SMS<BR>
+ -<BR>
+ 8017SMB<BR>
+ 8017SMA<BR>
+ -<BR>
+ -<BR>
+ CT-6W<BR>
+ CT-6H<BR>
+ CT-6P<BR>
+ CT-6R<BR>
+ -<BR>
+ CT-6V<BR>
+ CT-6X<BR>
+ -<BR>
+ -<BR>
+ 8038EKV<BR>
+ -<BR>
+ 8038EKX<BR>
+ -<BR>
+ -<BR>
+ 8038EKP<BR>
+ 8038EKZ<BR>
+ 8038EKW<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3321H<BR>
+ 3321P<BR>
+ 3321N<BR>
+ 1102H<BR>
+ 1102P<BR>
+ 1102T<BR>
+ RVA0911V304A<BR>
+ -<BR>
+ RVA0911H413A<BR>
+ RVG0707V100A<BR>
+ RVA0607V(H)306A<BR>
+ RVA1214H213A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 3104B<BR>
+ 3104C<BR>
+ 3104F<BR>
+ 3104H<BR>
+ -<BR>
+ 3104M<BR>
+ 3104P<BR>
+ 3104S<BR>
+ 3104W<BR>
+ 3104X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ EVMQ0G<BR>
+ EVMQIG<BR>
+ EVMQ3G<BR>
+ EVMS0G<BR>
+ EVMQ0G<BR>
+ EVMG0G<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMK4GA00B<BR>
+ EVM30GA00B<BR>
+ EVMK0GA00B<BR>
+ EVM38GA00B<BR>
+ EVMB6<BR>
+ EVLQ0<BR>
+ -<BR>
+ EVMMSG<BR>
+ EVMMBG<BR>
+ EVMMAG<BR>
+ -<BR>
+ -<BR>
+ EVMMCS<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ EVMM1<BR>
+ -<BR>
+ -<BR>
+ EVMM0<BR>
+ -<BR>
+ -<BR>
+ EVMM3<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ 62-3-1<BR>
+ 62-1-2<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67R<BR>
+ -<BR>
+ 67P<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ 67X<BR>
+ 63V<BR>
+ 63S<BR>
+ 63M<BR>
+ -<BR>
+ -<BR>
+ 63H<BR>
+ 63P<BR>
+ -<BR>
+ -<BR>
+ 63X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ RJ/RJR50<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P> <P>
+<TABLE BORDER=0 CELLSPACING=1 CELLPADDING=3>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT color="#0000FF" SIZE=4 FACE=ARIAL><B>SMD TRIM-POT CROSS REFERENCE</B></FONT>
+ <P>
+ <FONT SIZE=4 FACE=ARIAL><B>MULTI-TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3224G<BR>
+ 3224J<BR>
+ 3224W<BR>
+ 3269P<BR>
+ 3269W<BR>
+ 3269X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 44G<BR>
+ 44J<BR>
+ 44W<BR>
+ 84P<BR>
+ 84W<BR>
+ 84X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST63Z<BR>
+ ST63Y<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST5P<BR>
+ ST5W<BR>
+ ST5X<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ </TD>
+ </TR>
+ <TR>
+ <TD COLSPAN=7>
+ <FONT SIZE=4 FACE=ARIAL><B>SINGLE TURN</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BOURNS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>BI TECH</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>DALE-VISHAY</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PHILIPS/MEPCO</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>PANASONIC</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>TOCOS</B></FONT>
+ </TD>
+ <TD>
+ <FONT SIZE=3 FACE=ARIAL><B>AUX/KYOCERA</B></FONT>
+ </TD>
+ </TR>
+ <TR>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 3314G<BR>
+ 3314J<BR>
+ 3364A/B<BR>
+ 3364C/D<BR>
+ 3364W/X<BR>
+ 3313G<BR>
+ 3313J<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ 23B<BR>
+ 23A<BR>
+ 21X<BR>
+ 21W<BR>
+ -<BR>
+ 22B<BR>
+ 22A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST5YL/ST53YL<BR>
+ ST5YJ/5T53YJ<BR>
+ ST-23A<BR>
+ ST-22B<BR>
+ ST-22<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ ST-4B<BR>
+ ST-4A<BR>
+ -<BR>
+ -<BR>
+ -<BR>
+ ST-3B<BR>
+ ST-3A<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ EVM-6YS<BR>
+ EVM-1E<BR>
+ EVM-1G<BR>
+ EVM-1D<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ G4B<BR>
+ G4A<BR>
+ TR04-3S1<BR>
+ TRG04-2S1<BR>
+ -<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ <TD BGCOLOR="#cccccc" ALIGN=CENTER><FONT FACE=ARIAL SIZE=3>
+ -<BR>
+ -<BR>
+ DVR-43A<BR>
+ CVR-42C<BR>
+ CVR-42A/C<BR>
+ -<BR>
+ -<BR></FONT>
+ </TD>
+ </TR>
+</TABLE>
+<P>
+<FONT SIZE=4 FACE=ARIAL><B>ALT = ALTERNATE</B></FONT>
+<P>
+
+
+<P>
+</td>
+</tr>
+</table>
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 2.4 x 4.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 2.5 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 3 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 4 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 5 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm, outline 6 x 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 mm + 5 mm, outline 2.4 x 7 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 2.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 3.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 4.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 2.5 + 5 mm, outline 5.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 2.4 x 4.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 2.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 4.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 3 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 5.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 7.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+Horizontal, grid 5 mm, outline 7.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 3.2 x 10.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 4.2 x 10.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 5.2 x 10.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 4.3 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 5.4 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm, outline 6.4 x 13.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 10.2 mm + 15.2 mm, outline 6.2 x 18.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 5.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 6.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 7.2 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 8.4 x 18.3 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 15 mm, outline 9.1 x 18.2 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 6.2 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 7.4 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 8.7 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 10.8 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 22.5 mm, outline 11.3 x 26.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 9.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 11.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 13.4 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 20.5 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 13.7 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 16.2 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 32.5 mm, outline 18.2 x 37.4 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 19.2 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 20.3 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 5 mm, outline 3.5 x 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 37.5 mm, outline 15.5 x 41.8 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 7.5 mm, outline 6.3 x 10.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 15.4 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CAPACITOR</b><p>
+grid 27.5 mm, outline 17.3 x 31.6 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Ceramic Chip Capacitor KEMET 0204 reflow solder</b><p>
+Metric Code Size 1005
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0603 reflow solder</b><p>
+Metric Code Size 1608
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 0805 reflow solder</b><p>
+Metric Code Size 2012
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1206 reflow solder</b><p>
+Metric Code Size 3216
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1210 reflow solder</b><p>
+Metric Code Size 3225
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1812 reflow solder</b><p>
+Metric Code Size 4532
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 1825 reflow solder</b><p>
+Metric Code Size 4564
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 2220 reflow solder</b><p>Metric Code Size 5650
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Ceramic Chip Capacitor KEMET 2225 reflow solder</b><p>Metric Code Size 5664
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b> </b><p>
+Source: http://www.vishay.com/docs/10129/hpc0201a.pdf
+
+
+>NAME
+>VALUE
+
+
+
+Source: http://www.avxcorp.com/docs/catalogs/cx5r.pdf
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>CAPACITOR</b><p>
+Source: AVX .. aphvc.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>CAPACITOR</b><p>
+Source: AVX .. aphvc.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b> wave soldering<p>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b>
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+wave soldering
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b> wave soldering<p>
+Source: http://download.siliconexpert.com/pdfs/2005/02/24/Semi_Ap/2/VSH/Resistor/dcrcwfre.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.10 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.12 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.10 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.12 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+MELF 0.25 W
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0204, grid 2.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 10 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 12 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 15mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 2.5 mm
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 5 mm
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0207, grid 7.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 10mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0309, grid 2.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0411, grid 3.81 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0414, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0414, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 17.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0617, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0922, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<b>RESISTOR</b><p>
+type 0613, grid 5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b><p>
+type 0613, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type 0817, grid 22.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+0817
+
+
+
+
+<b>RESISTOR</b><p>
+type 0817, grid 6.35 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+0817
+
+
+
+<b>RESISTOR</b><p>
+type V234, grid 12.5 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type V235, grid 17.78 mm
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>RESISTOR</b><p>
+type V526-0, grid 2.5 mm
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC2211</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC2211</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC3715</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC3715</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC6123</b> Reflow Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CECC Size RC6123</b> Wave Soldering<p>
+source Beyschlag
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>RESISTOR</b><p>
+type 0922, grid 7.5 mm
+
+
+
+
+
+
+>NAME
+>VALUE
+0922
+
+
+
+<b>RESISTOR</b><p>
+type RDH, grid 15 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+RDH
+
+
+
+
+<b>Mini MELF 0102 Axial</b>
+
+
+
+
+>NAME
+>VALUE
+
+
+
+<b>RESISTOR</b> chip<p>
+Source: http://www.vishay.com/docs/20008/dcrcw.pdf
+
+
+>NAME
+>VALUE
+
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR52<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR53<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR54<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR55<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RBR56<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RNC55<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Bulk Metal® Foil Technology</b>, Tubular Axial Lead Resistors, Meets or Exceeds MIL-R-39005 Requirements<p>
+MIL SIZE RNC60<br>
+Source: VISHAY .. vta56.pdf
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Package 4527</b><p>
+Source: http://www.vishay.com/docs/31059/wsrhigh.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wirewound Resistors, Precision Power</b><p>
+Source: VISHAY wscwsn.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>CRCW1218 Thick Film, Rectangular Chip Resistors</b><p>
+Source: http://www.vishay.com .. dcrcw.pdf
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+<b>Chip Monolithic Ceramic Capacitors</b> Medium Voltage High Capacitance for General Use<p>
+Source: http://www.murata.com .. GRM43DR72E224KW01.pdf
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+<B>CAPACITOR</B>, European symbol
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+<B>RESISTOR</B>, European symbol
+
+
+
+
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+
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+
+
+
+
+
+
+
+
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+
+
+
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+
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+
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+
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+
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+
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+
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+
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+
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+
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+
+
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+
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+
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+
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+
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+
+
+
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+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
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+
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+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Frames for Sheet and Layout</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>DRAWING_NAME
+>LAST_DATE_TIME
+>SHEET
+Sheet:
+
+
+
+
+
+<b>FRAME</b><p>
+DIN A4, landscape with location and doc. field
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>TTL Devices, 74xx Series with European Symbols</b><p>
+Based on the following sources:
+<ul>
+<li>Texas Instruments <i>TTL Data Book</i> Volume 1, 1996.
+<li>TTL Data Book, Volume 2 , 1993
+<li>National Seminconductor Databook 1990, ALS/LS Logic
+<li>ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+<li>http://icmaster.com/ViewCompare.asp
+</ul>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Dual In Line Package</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Wide Small Outline package</b> 300 mil
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Leadless Chip Carrier</b><p> Ceramic Package
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+GND
+VCC
+
+
+
+
+
+
+Octal <b>BUS TRANSCEIVER</b>, 3-state
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Harting & 3M Connectors</b><p>
+Low profile connectors, straight<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+10
+>NAME
+>VALUE
+1
+2
+
+
+
+
+
+
+
+
+
+
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+1
+2
+>NAME
+>VALUE
+10
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>3M</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+<b>3M</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>HARTING</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Crystals and Crystal Resonators</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+GND
+VCC
+OUT
+
+
+
+
+
+
+
+<b>CRYSTAL RESONATOR</b>
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>VG Connectors (DIN 41612/DIN 41617)</b><p>
+The library contains devices which allow to place the contacts individually or
+in one or several blocks.<p>
+This behavior is indicated by the key words <i>single</i> and <i>block</i> in
+the respective device descriptions.<p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>CONNECTOR</b><p>
+female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+1
+a
+b
+c
+32
+DIN41612-R
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+>NAME
+
+
+
+
+
+<b>CONNECTOR</b> female, 96 pins, type R, rows ABC, grid 2.54 mm
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Resistors in DIL Packages</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>Chip Resistor Array</b> size 4 × 0603<p>
+concave termination - Phycomp Components<br>
+Source: RS Components
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array</b> size 4 × 0603<p>
+convex termination - Phycomp Components<br>
+Source: RS Components
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>BOURNS</b> Chip Resistor Array<p>
+Source: RS Component / BUORNS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>BOURNS</b> Chip Resistor Array<p>
+Source: RS Component / BUORNS
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>ARRAY CHIP RESISTOR</b> Size 4 x 0402<p>
+Source: www.yageo.com .. Pu-YC124_51_PbFree_L_1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Array chip resistor</b> size 4 × 0402<p>
+Source: http://docs-europe.electrocomponents.com/webdocs/0114/0900766b80114d99.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+<b>Chip Resistor Array 0201x4</b> 4 resistors in 1.4 mm x 0.6 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.2 mm x 1.6 mm size (EXB38V, V8V)<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0402x4</b> 4 resistors in 2.0 mm x 1.0 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0805x4</b> 4 resistors in 5.08 mm x 2.20 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
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+
+
+
+
+>NAME
+>VALUE
+
+
+<b>Chip Resistor Array 0603x4</b> 4 resistors in 3.20 mm x 1.60 mm size<p>
+Source: PANASONIC .. aoc0000ce1.pdf
+
+
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+
+
+>NAME
+>VALUE
+
+
+
+
+
+
+
+
+>VALUE
+>NAME
+
+
+
+
+
+
+<b>Array Chip Resistor</b><p>
+Source: RS Component / Phycomp
+
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+
+
+<b>AMD MACH4/MACH5 Family (Vantis)</b><p>
+<author>Created by librarian@cadsoft.de</author>
+
+
+<b>THIN QUAD FLAT PACK</b>
+
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+
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+
+
+
+
+>NAME
+>VALUE
+TQFP 100
+
+
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+
+
+
+>NAME
+>VALUE
+GND
+GND
+VCC
+GND
+GND
+VCC
+GND
+GND
+VCC
+GND
+VCC
+GND
+GND
+GND
+VCC
+GND
+VCC
+GND
+GND
+GND
+GND
+GND
+GND
+GND
+
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+
+
+
+
+<b>AMD MACH SERIES</b>
+
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diff --git a/Layout and PCB/68030-TK-V09b.sch b/Layout and PCB/68030-TK-V09b.sch
index 1e0f991..e843355 100644
--- a/Layout and PCB/68030-TK-V09b.sch
+++ b/Layout and PCB/68030-TK-V09b.sch
@@ -11374,6 +11374,9 @@ Source: RS Component / Phycomp
+
+
+
@@ -11539,12 +11542,9 @@ Source: RS Component / Phycomp
-
-
-
diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd
index 103a32b..3f5f16a 100644
--- a/Logic/68030-68000-bus.vhd
+++ b/Logic/68030-68000-bus.vhd
@@ -13,7 +13,7 @@ port(
LDS_000: inout std_logic;
SIZE: inout std_logic_vector ( 1 downto 0 );
A: inout std_logic_vector ( 31 downto 0 );
- CPU_SPACE: in std_logic ;
+ nEXP_SPACE: in std_logic ;
BERR: inout std_logic ;
BG_030: in std_logic ;
BG_000: out std_logic ;
@@ -100,12 +100,15 @@ signal LDS_000_INT: STD_LOGIC:='1';
signal DSACK_INT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "11";
signal CLK_CNT: STD_LOGIC_VECTOR ( 1 downto 0 ) := "00";
signal CLK_REF: STD_LOGIC_VECTOR ( 1 downto 0 ) := "10";
-signal CLK_000_CNT: STD_LOGIC_VECTOR ( 3 downto 0 ) := "0000";
signal CLK_OUT_PRE: STD_LOGIC:='1';
signal CLK_OUT_INT: STD_LOGIC:='1';
signal CLK_030_D: STD_LOGIC:='1';
-signal CLK_000_D: STD_LOGIC := '1';
-signal CLK_000_DD: STD_LOGIC := '1';
+signal CLK_000_D0: STD_LOGIC := '1';
+signal CLK_000_D1: STD_LOGIC := '1';
+signal CLK_000_D2: STD_LOGIC := '1';
+signal CLK_000_D3: STD_LOGIC := '1';
+signal CLK_000_D4: STD_LOGIC := '1';
+signal CLK_000_D5: STD_LOGIC := '1';
begin
@@ -128,20 +131,17 @@ begin
-- the external clock to the processor is generated here
CLK_OUT_INT <= CLK_OUT_PRE; --this way we know the clock of the next state: Its like looking in the future, cool!
--delayed Clocks for edge detection
- CLK_000_D <= CLK_000;
- CLK_000_DD <= CLK_000_D;
+ CLK_000_D0 <= CLK_000;
+ CLK_000_D1 <= CLK_000_D0;
+ CLK_000_D2 <= CLK_000_D1;
+ CLK_000_D3 <= CLK_000_D2;
+ CLK_000_D4 <= CLK_000_D3;
+ CLK_000_D5 <= CLK_000_D4;
- --cycle counter for Amiga-Bus-Timing
-
- if( CLK_000_D /= CLK_000)then --not equal
- CLK_000_CNT <= "0001";
- else
- CLK_000_CNT <= CLK_000_CNT+1; --4bit counter
- end if;
-- e-clock
- if(CLK_000_DD = '0' and CLK_000_D = '1') then
+ if(CLK_000_D1 = '0' and CLK_000_D0 = '1') then
case (cpu_est) is
when E1 => cpu_est <= E2 ;
when E2 => cpu_est <= E3 ;
@@ -196,7 +196,7 @@ begin
--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock
if(BGACK_000='0') then
BGACK_030_INT <= '0';
- elsif (BGACK_000='1' AND CLK_000_DD='0' and CLK_000_D='1') then -- BGACK_000 is high here!
+ elsif (BGACK_000='1' AND CLK_000_D1='0' and CLK_000_D0='1') then -- BGACK_000 is high here!
BGACK_030_INT <= '1'; --hold this signal high until 7m clock goes high
end if;
@@ -205,7 +205,7 @@ begin
BG_000 <= '1';
elsif(CLK_030 ='0') then
if( BG_030= '0' AND (SM_AMIGA = IDLE_N or SM_AMIGA = IDLE_P)
- and CPU_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running!
+ and nEXP_SPACE = '0' and AS_030='1') then --bus granted no local access and no AS_030 running!
BG_000 <= '0';
else
BG_000 <= '1';
@@ -214,7 +214,7 @@ begin
--interrupt buffering to avoid ghost interrupts
- if(CLK_000_DD='0' and CLK_000_D='1')then
+ if(CLK_000_D1='0' and CLK_000_D0='1')then
IPL_030<=IPL;
end if;
@@ -237,15 +237,19 @@ begin
FPU_CS_INT <= '0';
AS_030_000_SYNC <= '1';
else
- AS_030_000_SYNC <= CPU_SPACE;
+ if(nEXP_SPACE ='1')then
+ AS_030_000_SYNC <= '0';
+ else
+ AS_030_000_SYNC <= '1';
+ end if;
FPU_CS_INT <= '1';
end if;
end if;
-- VMA generation
- if(CLK_000_D='0' AND VPA_D='0' AND cpu_est = E4)then --assert
+ if(CLK_000_D0='0' AND VPA_D='0' AND cpu_est = E4)then --assert
VMA_INT <= '0';
- elsif(CLK_000_D='1' AND AS_000_INT='1' AND cpu_est=E1)then --deassert
+ elsif(CLK_000_D0='1' AND AS_000_INT='1' AND cpu_est=E1)then --deassert
VMA_INT <= '1';
end if;
@@ -253,11 +257,11 @@ begin
--Amiga statemachine
case (SM_AMIGA) is
when IDLE_P => --68000:S0 wait for a falling edge
- if( CLK_000_D='0' )then
+ if( CLK_000_D0='0' )then
SM_AMIGA<=IDLE_N;
end if;
when IDLE_N => --68000:S1 wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
- if(CLK_000_D='1' and CLK_000_DD = '0')then --sample AS only at the rising edge!
+ if(CLK_000_D0='1' and CLK_000_D1 = '0')then --sample AS only at the rising edge!
if( AS_030_000_SYNC = '0' )then
AS_000_INT <= '0';
if (RW='1' and DS_030 = '0') then --read: set udl/lds
@@ -276,11 +280,11 @@ begin
end if;
end if;
when AS_SET_P => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
- if(CLK_000_D='0')then
+ if(CLK_000_D0='0')then
SM_AMIGA<=AS_SET_N;
end if;
when AS_SET_N => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write
- if(CLK_000_D='1')then
+ if(CLK_000_D0='1')then
if (RW='0' and DS_030 = '0') then --write: set udl/lds
if(A(0)='0') then
UDS_000_INT <= '0';
@@ -296,7 +300,7 @@ begin
SM_AMIGA <= SAMPLE_DTACK_P;
end if;
when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
- if(CLK_000_D='0' )then
+ if(CLK_000_D0='0' )then
if(DTACK_SYNC = '0' OR VPA_SYNC ='0')then
SM_AMIGA<=DATA_FETCH_N;
end if;
@@ -308,16 +312,16 @@ begin
end if;
end if;
when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
- if(CLK_000_D='1')then
+ if(CLK_000_D0='1')then
SM_AMIGA<=DATA_FETCH_P;
end if;
when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
- if( CLK_000_D ='0' AND CLK_OUT_PRE='1' ) then --next 030-clock is high: dsack is sampled at the falling edge
+ if( CLK_000_D1 ='0' AND CLK_OUT_PRE='1' ) then --next 030-clock is high: dsack is sampled at the falling edge
DSACK_INT<="01";
SM_AMIGA<=END_CYCLE_N;
end if;
when END_CYCLE_N =>--68000:S7: Latch/Store data and go to IDLE on high clock
- if(CLK_000_D='1' and AS_000_INT='1' )then
+ if(CLK_000_D0='1' and AS_000_INT='1' )then
SM_AMIGA<=IDLE_P;
end if;
end case;
@@ -358,7 +362,7 @@ begin
'0';
--bus buffers
- AMIGA_BUS_ENABLE <= '0'; --for now: allways on
+ AMIGA_BUS_ENABLE <= '0' WHEN nEXP_SPACE ='1' else '1'; --for now: allways on for amiga
AMIGA_BUS_DATA_DIR <='1' WHEN RW='0' ELSE '0';
AMIGA_BUS_ENABLE_LOW <= '1'; --for now: allways off
@@ -379,7 +383,7 @@ begin
LDS_000_INT;
--dsack
- DSACK <= "ZZ" when CPU_SPACE = '1' else -- output on amiga cycle
+ DSACK <= "ZZ" when nEXP_SPACE = '0' else -- output on amiga cycle
DSACK_INT;
BGACK_030 <= BGACK_030_INT;
-- signal assignment
diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl
index 253ae88..0580b2a 100644
--- a/Logic/68030_TK.tcl
+++ b/Logic/68030_TK.tcl
@@ -120466,3 +120466,3926 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6
########## Tcl recorder end at 05/15/14 23:02:39 ###########
+
+########## Tcl recorder starts at 05/15/14 23:09:51 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/15/14 23:09:51 ###########
+
+
+########## Tcl recorder starts at 05/15/14 23:09:56 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/15/14 23:09:56 ###########
+
+
+########## Tcl recorder starts at 05/15/14 23:11:31 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/15/14 23:11:31 ###########
+
+
+########## Tcl recorder starts at 05/15/14 23:11:35 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/15/14 23:11:35 ###########
+
+
+########## Tcl recorder starts at 05/16/14 08:53:10 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 08:53:10 ###########
+
+
+########## Tcl recorder starts at 05/16/14 08:53:13 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 08:53:13 ###########
+
+
+########## Tcl recorder starts at 05/16/14 10:56:15 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 10:56:15 ###########
+
+
+########## Tcl recorder starts at 05/16/14 10:56:20 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 10:56:20 ###########
+
+
+########## Tcl recorder starts at 05/16/14 10:56:23 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 10:56:23 ###########
+
+
+########## Tcl recorder starts at 05/16/14 11:00:59 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 11:00:59 ###########
+
+
+########## Tcl recorder starts at 05/16/14 11:01:04 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 11:01:04 ###########
+
+
+########## Tcl recorder starts at 05/16/14 11:01:52 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 11:01:52 ###########
+
+
+########## Tcl recorder starts at 05/16/14 11:01:58 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 11:01:58 ###########
+
+
+########## Tcl recorder starts at 05/16/14 11:07:49 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 11:07:49 ###########
+
+
+########## Tcl recorder starts at 05/16/14 11:08:15 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 11:08:15 ###########
+
+
+########## Tcl recorder starts at 05/16/14 11:08:16 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 11:08:16 ###########
+
+
+########## Tcl recorder starts at 05/16/14 11:09:36 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 11:09:36 ###########
+
+
+########## Tcl recorder starts at 05/16/14 11:10:43 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 11:10:43 ###########
+
+
+########## Tcl recorder starts at 05/16/14 11:11:28 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 11:11:28 ###########
+
+
+########## Tcl recorder starts at 05/16/14 11:11:43 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 11:11:43 ###########
+
+
+########## Tcl recorder starts at 05/16/14 11:11:44 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 11:11:44 ###########
+
+
+########## Tcl recorder starts at 05/16/14 11:14:33 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 11:14:33 ###########
+
+
+########## Tcl recorder starts at 05/16/14 11:14:46 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 11:14:46 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:28:05 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:28:05 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:28:30 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:28:30 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:28:35 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:28:35 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:29:38 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:29:38 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:29:51 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:29:51 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:30:37 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:30:37 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:30:43 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:30:43 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:33:38 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:33:38 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:33:40 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:33:40 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:33:56 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:33:56 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:33:57 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:33:57 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:35:20 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:35:20 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:35:24 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:35:24 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:37:34 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:37:34 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:37:47 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:37:47 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:39:47 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:39:48 ###########
+
+
+########## Tcl recorder starts at 05/16/14 12:39:51 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 12:39:51 ###########
+
+
+########## Tcl recorder starts at 05/16/14 17:00:11 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 17:00:11 ###########
+
+
+########## Tcl recorder starts at 05/16/14 17:00:27 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 17:00:27 ###########
+
+
+########## Tcl recorder starts at 05/16/14 17:05:15 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 17:05:15 ###########
+
+
+########## Tcl recorder starts at 05/16/14 17:05:26 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 17:05:26 ###########
+
+
+########## Tcl recorder starts at 05/16/14 17:05:36 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 17:05:36 ###########
+
+
+########## Tcl recorder starts at 05/16/14 17:06:59 ##########
+
+# Commands to make the Process:
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 17:06:59 ###########
+
+
+########## Tcl recorder starts at 05/16/14 17:07:02 ##########
+
+# Commands to make the Process:
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+ puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+ puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+ puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+ puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
+"
+ close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+ return
+} else {
+ vwait done
+ if [checkResult $done] {
+ return
+ }
+}
+
+########## Tcl recorder end at 05/16/14 17:07:02 ###########
+
diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2
index 307216f..55926fd 100644
--- a/Logic/68030_tk.bl2
+++ b/Logic/68030_tk.bl2
@@ -1,200 +1,199 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
-#$ DATE Thu May 15 23:02:46 2014
+#$ DATE Fri May 16 17:07:08 2014
#$ MODULE 68030_tk
-#$ PINS 74 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ A_15_ A_14_ \
-# IPL_2_ A_13_ A_12_ DSACK_1_ A_11_ A_10_ FC_1_ A_9_ AS_030 A_8_ AS_000 A_7_ DS_030 A_6_ \
-# UDS_000 A_5_ LDS_000 A_4_ CPU_SPACE A_3_ BERR A_2_ BG_030 A_1_ BG_000 A_0_ BGACK_030 \
-# IPL_030_1_ BGACK_000 IPL_030_0_ CLK_030 IPL_1_ CLK_000 IPL_0_ CLK_OSZI DSACK_0_ \
-# CLK_DIV_OUT FC_0_ CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW \
-# AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \
-# A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
-#$ NODES 344 IPL_030DFFSH_1_reg IPL_030DFFSH_2_reg ipl_c_0__n ipl_c_1__n \
-# inst_BGACK_030_INTreg inst_FPU_CS_INTreg ipl_c_2__n cpu_est_3_reg inst_VMA_INTreg \
-# gnd_n_n dsack_c_1__n cpu_est_0_ cpu_est_1_ DTACK_c inst_AS_000_INTreg \
-# inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D \
-# inst_CLK_000_DD inst_CLK_OUT_PRE RST_c vcc_n_n cpu_est_2_ RESETDFFreg CLK_CNT_0_ \
-# SM_AMIGA_6_ RW_c SM_AMIGA_7_ inst_UDS_000_INTreg fc_c_0__n inst_LDS_000_INTreg \
-# state_machine_un1_clk_030_n fc_c_1__n SM_AMIGA_1_ DSACK_INT_1_ inst_DTACK_DMA \
-# SM_AMIGA_4_ state_machine_un6_bgack_000_n SM_AMIGA_3_ N_99_i \
-# state_machine_un13_as_000_int_n un1_bg_030 N_101_i SM_AMIGA_5_ sm_amiga_ns_0_2__n \
-# SM_AMIGA_2_ N_107_i SM_AMIGA_0_ N_106_i sm_amiga_ns_0_5__n N_108_i N_109_i N_110_i \
-# sm_amiga_ns_0_7__n N_91_0 CLK_OUT_PRE_i N_94_0 state_machine_un8_clk_000_d_i_n \
-# state_machine_un13_clk_000_d_i_n cpu_est_0_0_ state_machine_un15_clk_000_d_0_n \
-# N_93_0 N_104_i N_105_i N_103_i CLK_OUT_PRE_0 state_machine_un60_clk_000_d_i_n \
-# state_machine_un17_clk_030_0_n un1_as_030_3_0 N_145_i clk_un4_clk_000_dd_n \
-# a_c_i_0__n clk_cpu_est_11_1__n state_machine_uds_000_int_8_0_n \
-# state_machine_un42_clk_030_n state_machine_lds_000_int_8_0_n N_102 \
-# state_machine_as_030_000_sync_3_2_n N_98 size_c_i_1__n N_97 \
-# state_machine_un34_clk_000_d_i_n N_100 N_131_i N_92 N_132_i N_112 N_122_i N_127 \
-# N_125_i N_125 N_126_i N_128 N_134_i N_129 N_133_i N_130 N_135_i N_168 \
-# clk_cpu_est_11_0_3__n N_171 N_130_i N_135_1 clk_cpu_est_11_0_1__n \
-# state_machine_un13_clk_000_d_2_n N_128_i clk_cpu_est_11_3__n un1_bg_030_0 N_135 \
-# N_97_i N_133 BG_030_c_i N_134 N_127_i N_132 N_129_i N_131 N_92_0 N_126 N_100_i \
-# state_machine_un34_clk_000_d_n N_112_i UDS_000_INT_0_sqmuxa \
-# UDS_000_INT_0_sqmuxa_1 clk_un4_clk_000_dd_i_n state_machine_as_030_000_sync_3_n \
-# state_machine_un6_bgack_000_0_n N_145 state_machine_un1_clk_030_0_n \
-# state_machine_lds_000_int_8_n clk_cpu_est_11_0_1_3__n \
-# state_machine_uds_000_int_8_n state_machine_un34_clk_000_d_i_1_n un1_as_030_4 \
-# state_machine_as_030_000_sync_3_2_1_n un1_as_030_3 N_168_1 DSACK_INT_1_sqmuxa \
-# N_168_2 state_machine_un17_clk_030_n N_168_3 state_machine_un60_clk_000_d_n \
-# N_168_4 DTACK_SYNC_1_sqmuxa N_168_5 DTACK_SYNC_1_sqmuxa_1 N_168_6 VPA_SYNC_1_sqmuxa \
-# N_171_1 VPA_SYNC_1_sqmuxa_1 N_171_2 N_103 un1_bg_030_0_1 N_104 un1_bg_030_0_2 N_93 \
-# clk_cpu_est_11_0_1_1__n N_105 clk_cpu_est_11_0_2_1__n VPA_SYNC_1_sqmuxa_1_0 \
-# state_machine_un42_clk_030_1_n state_machine_un15_clk_000_d_n \
-# state_machine_un42_clk_030_2_n state_machine_un13_clk_000_d_n \
-# state_machine_un42_clk_030_3_n state_machine_un8_clk_000_d_n \
-# state_machine_un42_clk_030_4_n state_machine_un8_clk_000_d_1_n \
-# state_machine_un42_clk_030_5_n state_machine_un13_clk_000_d_1_n N_132_1 N_107 \
-# N_131_1 N_94 UDS_000_INT_0_sqmuxa_1_0 N_91 UDS_000_INT_0_sqmuxa_2 N_110 \
-# UDS_000_INT_0_sqmuxa_1_1 N_108 UDS_000_INT_0_sqmuxa_1_2 N_109 \
-# UDS_000_INT_0_sqmuxa_1_3 N_106 DTACK_SYNC_1_sqmuxa_1_0 N_101 \
-# state_machine_un8_clk_000_d_1_0_n N_99 state_machine_un8_clk_000_d_2_n \
-# AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d_3_n RW_i \
-# state_machine_un13_clk_000_d_1_0_n N_102_i state_machine_un13_clk_000_d_2_0_n \
-# AS_000_INT_i VPA_SYNC_1_sqmuxa_1_1 dsack_i_1__n VPA_SYNC_1_sqmuxa_2 AS_030_i \
-# VPA_SYNC_1_sqmuxa_3 sm_amiga_i_7__n VPA_SYNC_1_sqmuxa_4 CLK_000_D_i N_107_1 \
-# sm_amiga_i_2__n N_98_1 sm_amiga_i_1__n as_000_int_0_un3_n \
-# state_machine_un13_clk_000_d_1_i_n as_000_int_0_un1_n VPA_D_i as_000_int_0_un0_n \
-# VMA_INT_i vma_int_0_un3_n cpu_est_i_0__n vma_int_0_un1_n cpu_est_i_1__n \
-# vma_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n \
-# state_machine_un8_clk_000_d_1_i_0_n uds_000_int_0_un1_n DTACK_i \
-# uds_000_int_0_un0_n sm_amiga_i_3__n dtack_sync_0_un3_n sm_amiga_i_4__n \
-# dtack_sync_0_un1_n sm_amiga_i_5__n dtack_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i \
-# vpa_sync_0_un3_n VPA_SYNC_1_sqmuxa_i vpa_sync_0_un1_n N_98_i vpa_sync_0_un0_n \
-# state_machine_un42_clk_030_i_n dsack_int_0_1__un3_n UDS_000_INT_0_sqmuxa_1_i \
-# dsack_int_0_1__un1_n UDS_000_INT_0_sqmuxa_i dsack_int_0_1__un0_n \
-# AS_030_000_SYNC_i as_030_000_sync_0_un3_n DS_030_i as_030_000_sync_0_un1_n \
-# cpu_est_i_2__n as_030_000_sync_0_un0_n state_machine_un13_clk_000_d_2_i_n \
-# fpu_cs_int_0_un3_n CLK_000_DD_i fpu_cs_int_0_un1_n sm_amiga_i_6__n \
-# fpu_cs_int_0_un0_n CLK_030_i lds_000_int_0_un3_n a_i_30__n lds_000_int_0_un1_n \
-# a_i_31__n lds_000_int_0_un0_n a_i_28__n cpu_est_0_3__un3_n a_i_29__n \
-# cpu_est_0_3__un1_n a_i_26__n cpu_est_0_3__un0_n a_i_27__n cpu_est_0_2__un3_n \
-# a_i_24__n cpu_est_0_2__un1_n a_i_25__n cpu_est_0_2__un0_n a_i_19__n bg_000_0_un3_n \
-# a_i_16__n bg_000_0_un1_n a_i_18__n bg_000_0_un0_n bgack_030_int_0_un3_n RST_i \
-# bgack_030_int_0_un1_n bgack_030_int_0_un0_n FPU_CS_INT_i cpu_est_0_1__un3_n \
-# CPU_SPACE_i cpu_est_0_1__un1_n BGACK_030_INT_i cpu_est_0_1__un0_n AS_030_c \
-# ipl_030_0_0__un3_n ipl_030_0_0__un1_n ipl_030_0_0__un0_n DS_030_c \
-# ipl_030_0_1__un3_n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_2__un3_n \
-# size_c_0__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n a_15__n a_c_0__n \
-# a_14__n a_13__n a_12__n a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n \
+#$ PINS 74 A_17_ A_16_ SIZE_1_ A_15_ A_14_ A_31_ A_13_ A_12_ IPL_030_2_ A_11_ A_10_ \
+# IPL_2_ A_9_ A_8_ DSACK_1_ A_7_ A_6_ FC_1_ A_5_ AS_030 A_4_ AS_000 A_3_ DS_030 A_2_ UDS_000 \
+# A_1_ LDS_000 A_0_ nEXP_SPACE IPL_030_1_ BERR IPL_030_0_ BG_030 IPL_1_ BG_000 IPL_0_ \
+# BGACK_030 DSACK_0_ BGACK_000 FC_0_ CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS \
+# DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
+# AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ \
+# A_21_ A_20_ A_19_ A_18_
+#$ NODES 340 ipl_c_0__n ipl_c_1__n ipl_c_2__n inst_BGACK_030_INTreg \
+# inst_FPU_CS_INTreg dsack_c_1__n cpu_est_3_reg inst_VMA_INTreg DTACK_c cpu_est_0_ \
+# cpu_est_1_ inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D \
+# inst_VPA_SYNC inst_CLK_000_D0 RST_c inst_CLK_000_D1 inst_CLK_OUT_PRE RESETDFFreg \
+# vcc_n_n gnd_n_n RW_c cpu_est_2_ CLK_CNT_0_ fc_c_0__n SM_AMIGA_6_ SM_AMIGA_7_ fc_c_1__n \
+# inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ \
+# state_machine_un60_clk_000_d0_n SM_AMIGA_1_ inst_DTACK_DMA N_100_i SM_AMIGA_4_ \
+# sm_amiga_ns_0_2__n SM_AMIGA_3_ N_103_i DSACK_INT_1_sqmuxa N_104_i \
+# state_machine_un13_as_000_int_n VPA_SYNC_1_sqmuxa_1 N_106_i un1_as_030_4 N_105_i \
+# SM_AMIGA_5_ sm_amiga_ns_0_5__n SM_AMIGA_2_ N_107_i SM_AMIGA_0_ N_108_i \
+# state_machine_lds_000_int_8_n sm_amiga_ns_0_6__n state_machine_uds_000_int_8_n \
+# N_90_i N_93_0 N_128_i N_126_i N_127_i N_129_i clk_cpu_est_11_0_1__n N_133_i N_132_i \
+# N_134_i clk_cpu_est_11_0_3__n N_125_i cpu_est_0_0_ N_124_i N_130_i N_131_i N_121_i \
+# N_91_0 N_109_i sm_amiga_ns_0_7__n CLK_OUT_PRE_0 state_machine_un8_clk_000_d0_i_n \
+# state_machine_un13_clk_000_d0_i_n state_machine_un15_clk_000_d0_0_n BG_030_c_i \
+# state_machine_un1_clk_030_0_n clk_un4_clk_000_d1_n \
+# state_machine_un17_clk_030_0_n N_144 un1_as_030_3_0 N_101 \
+# state_machine_as_030_000_sync_3_2_n VPA_SYNC_1_sqmuxa N_96_i N_97 un1_bg_030_0 \
+# state_machine_un34_clk_000_d0_n clk_un4_clk_000_d1_i_n N_96 \
+# state_machine_un6_bgack_000_0_n N_102 N_98_i UDS_000_INT_0_sqmuxa \
+# UDS_000_INT_0_sqmuxa_1 N_111_i N_167 N_99_i N_170 N_92 N_92_0 N_91 \
+# state_machine_un34_clk_000_d0_i_n N_99 a_c_i_0__n N_111 size_c_i_1__n N_98 N_102_i \
+# state_machine_un6_bgack_000_n state_machine_un42_clk_030_n N_144_i \
+# DTACK_SYNC_1_sqmuxa state_machine_lds_000_int_8_0_n un1_bg_030 \
+# state_machine_uds_000_int_8_0_n state_machine_as_030_000_sync_3_n \
+# state_machine_un60_clk_000_d0_i_n DTACK_SYNC_1_sqmuxa_1 un1_bg_030_0_1 \
+# un1_as_030_3 un1_bg_030_0_2 state_machine_un17_clk_030_n \
+# state_machine_as_030_000_sync_3_2_1_n state_machine_un1_clk_030_n \
+# clk_cpu_est_11_0_1_3__n VPA_SYNC_1_sqmuxa_1_0 clk_cpu_est_11_0_1_1__n \
+# state_machine_un15_clk_000_d0_n clk_cpu_est_11_0_2_1__n \
+# state_machine_un13_clk_000_d0_n N_167_1 state_machine_un8_clk_000_d0_n N_167_2 \
+# N_109 N_167_3 state_machine_un13_clk_000_d0_1_n N_167_4 N_129 N_167_5 \
+# state_machine_un13_clk_000_d0_2_n N_167_6 N_130 N_170_1 N_131 N_170_2 N_124 \
+# UDS_000_INT_0_sqmuxa_1_1 N_125 UDS_000_INT_0_sqmuxa_1_2 N_134 \
+# UDS_000_INT_0_sqmuxa_1_3 N_134_1 UDS_000_INT_0_sqmuxa_1_0 N_106 \
+# UDS_000_INT_0_sqmuxa_2 clk_cpu_est_11_3__n state_machine_un34_clk_000_d0_i_1_n \
+# N_132 state_machine_un42_clk_030_1_n N_133 state_machine_un42_clk_030_2_n \
+# clk_cpu_est_11_1__n state_machine_un42_clk_030_3_n N_127 \
+# state_machine_un42_clk_030_4_n N_126 state_machine_un42_clk_030_5_n N_128 \
+# DTACK_SYNC_1_sqmuxa_1_0 N_93 N_130_1 N_90 N_131_1 N_107 \
+# state_machine_un8_clk_000_d0_1_n N_108 state_machine_un8_clk_000_d0_2_n N_105 \
+# state_machine_un8_clk_000_d0_3_n N_103 state_machine_un8_clk_000_d0_4_n N_104 \
+# state_machine_un13_clk_000_d0_1_0_n N_100 state_machine_un13_clk_000_d0_2_0_n \
+# AS_000_INT_1_sqmuxa VPA_SYNC_1_sqmuxa_1_1 RW_i VPA_SYNC_1_sqmuxa_2 nEXP_SPACE_i \
+# VPA_SYNC_1_sqmuxa_3 N_101_i VPA_SYNC_1_sqmuxa_4 AS_000_INT_i N_106_1 dsack_i_1__n \
+# cpu_est_0_3__un3_n AS_030_i cpu_est_0_3__un1_n CLK_000_D0_i cpu_est_0_3__un0_n \
+# sm_amiga_i_3__n cpu_est_0_1__un3_n sm_amiga_i_4__n cpu_est_0_1__un1_n CLK_000_D1_i \
+# cpu_est_0_1__un0_n cpu_est_i_0__n as_000_int_0_un3_n cpu_est_i_3__n \
+# as_000_int_0_un1_n cpu_est_i_2__n as_000_int_0_un0_n VPA_D_i bg_000_0_un3_n \
+# VMA_INT_i bg_000_0_un1_n cpu_est_i_1__n bg_000_0_un0_n \
+# state_machine_un13_clk_000_d0_2_i_n as_030_000_sync_0_un3_n \
+# state_machine_un13_clk_000_d0_1_i_n as_030_000_sync_0_un1_n DTACK_i \
+# as_030_000_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i fpu_cs_int_0_un3_n a_i_18__n \
+# fpu_cs_int_0_un1_n a_i_16__n fpu_cs_int_0_un0_n a_i_19__n dtack_sync_0_un3_n \
+# CLK_030_i dtack_sync_0_un1_n state_machine_un42_clk_030_i_n dtack_sync_0_un0_n \
+# sm_amiga_i_6__n vma_int_0_un3_n sm_amiga_i_7__n vma_int_0_un1_n AS_030_000_SYNC_i \
+# vma_int_0_un0_n DS_030_i cpu_est_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i \
+# cpu_est_0_2__un1_n UDS_000_INT_0_sqmuxa_i cpu_est_0_2__un0_n sm_amiga_i_5__n \
+# ipl_030_0_0__un3_n VPA_SYNC_1_sqmuxa_i ipl_030_0_0__un1_n N_97_i \
+# ipl_030_0_0__un0_n a_i_30__n ipl_030_0_1__un3_n a_i_31__n ipl_030_0_1__un1_n \
+# a_i_28__n ipl_030_0_1__un0_n a_i_29__n ipl_030_0_2__un3_n a_i_26__n \
+# ipl_030_0_2__un1_n a_i_27__n ipl_030_0_2__un0_n a_i_24__n bgack_030_int_0_un3_n \
+# a_i_25__n bgack_030_int_0_un1_n bgack_030_int_0_un0_n RST_i uds_000_int_0_un3_n \
+# uds_000_int_0_un1_n FPU_CS_INT_i uds_000_int_0_un0_n BGACK_030_INT_i \
+# lds_000_int_0_un3_n AS_030_c lds_000_int_0_un1_n lds_000_int_0_un0_n \
+# vpa_sync_0_un3_n DS_030_c vpa_sync_0_un1_n vpa_sync_0_un0_n dsack_int_0_1__un3_n \
+# dsack_int_0_1__un1_n size_c_0__n dsack_int_0_1__un0_n a_15__n size_c_1__n a_14__n \
+# a_c_0__n a_13__n a_12__n a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n \
# a_c_17__n a_4__n a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n \
# a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n \
-# a_c_31__n CPU_SPACE_c BG_030_c BG_000DFFSHreg BGACK_000_c CLK_030_c CLK_OSZI_c \
-# CLK_OUT_INTreg IPL_030DFFSH_0_reg
+# a_c_31__n nEXP_SPACE_c BG_030_c BG_000DFFSHreg BGACK_000_c CLK_030_c CLK_OSZI_c \
+# CLK_OUT_INTreg IPL_030DFFSH_0_reg IPL_030DFFSH_1_reg IPL_030DFFSH_2_reg
.model bus68030
.inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \
-CPU_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \
+nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \
CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \
A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \
A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF \
A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF \
A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF A_1_.BLIF \
A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF \
-DSACK_0_.BLIF IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_2_reg.BLIF ipl_c_0__n.BLIF \
-ipl_c_1__n.BLIF inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF \
-ipl_c_2__n.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF gnd_n_n.BLIF \
-dsack_c_1__n.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF DTACK_c.BLIF \
-inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF \
-inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \
-inst_CLK_OUT_PRE.BLIF RST_c.BLIF vcc_n_n.BLIF cpu_est_2_.BLIF RESETDFFreg.BLIF \
-CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF RW_c.BLIF SM_AMIGA_7_.BLIF \
-inst_UDS_000_INTreg.BLIF fc_c_0__n.BLIF inst_LDS_000_INTreg.BLIF \
-state_machine_un1_clk_030_n.BLIF fc_c_1__n.BLIF SM_AMIGA_1_.BLIF \
-DSACK_INT_1_.BLIF inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF \
-state_machine_un6_bgack_000_n.BLIF SM_AMIGA_3_.BLIF N_99_i.BLIF \
-state_machine_un13_as_000_int_n.BLIF un1_bg_030.BLIF N_101_i.BLIF \
-SM_AMIGA_5_.BLIF sm_amiga_ns_0_2__n.BLIF SM_AMIGA_2_.BLIF N_107_i.BLIF \
-SM_AMIGA_0_.BLIF N_106_i.BLIF sm_amiga_ns_0_5__n.BLIF N_108_i.BLIF \
-N_109_i.BLIF N_110_i.BLIF sm_amiga_ns_0_7__n.BLIF N_91_0.BLIF \
-CLK_OUT_PRE_i.BLIF N_94_0.BLIF state_machine_un8_clk_000_d_i_n.BLIF \
-state_machine_un13_clk_000_d_i_n.BLIF cpu_est_0_0_.BLIF \
-state_machine_un15_clk_000_d_0_n.BLIF N_93_0.BLIF N_104_i.BLIF N_105_i.BLIF \
-N_103_i.BLIF CLK_OUT_PRE_0.BLIF state_machine_un60_clk_000_d_i_n.BLIF \
-state_machine_un17_clk_030_0_n.BLIF un1_as_030_3_0.BLIF N_145_i.BLIF \
-clk_un4_clk_000_dd_n.BLIF a_c_i_0__n.BLIF clk_cpu_est_11_1__n.BLIF \
-state_machine_uds_000_int_8_0_n.BLIF state_machine_un42_clk_030_n.BLIF \
-state_machine_lds_000_int_8_0_n.BLIF N_102.BLIF \
-state_machine_as_030_000_sync_3_2_n.BLIF N_98.BLIF size_c_i_1__n.BLIF \
-N_97.BLIF state_machine_un34_clk_000_d_i_n.BLIF N_100.BLIF N_131_i.BLIF \
-N_92.BLIF N_132_i.BLIF N_112.BLIF N_122_i.BLIF N_127.BLIF N_125_i.BLIF \
-N_125.BLIF N_126_i.BLIF N_128.BLIF N_134_i.BLIF N_129.BLIF N_133_i.BLIF \
-N_130.BLIF N_135_i.BLIF N_168.BLIF clk_cpu_est_11_0_3__n.BLIF N_171.BLIF \
-N_130_i.BLIF N_135_1.BLIF clk_cpu_est_11_0_1__n.BLIF \
-state_machine_un13_clk_000_d_2_n.BLIF N_128_i.BLIF clk_cpu_est_11_3__n.BLIF \
-un1_bg_030_0.BLIF N_135.BLIF N_97_i.BLIF N_133.BLIF BG_030_c_i.BLIF N_134.BLIF \
-N_127_i.BLIF N_132.BLIF N_129_i.BLIF N_131.BLIF N_92_0.BLIF N_126.BLIF \
-N_100_i.BLIF state_machine_un34_clk_000_d_n.BLIF N_112_i.BLIF \
-UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_1.BLIF \
-clk_un4_clk_000_dd_i_n.BLIF state_machine_as_030_000_sync_3_n.BLIF \
-state_machine_un6_bgack_000_0_n.BLIF N_145.BLIF \
-state_machine_un1_clk_030_0_n.BLIF state_machine_lds_000_int_8_n.BLIF \
-clk_cpu_est_11_0_1_3__n.BLIF state_machine_uds_000_int_8_n.BLIF \
-state_machine_un34_clk_000_d_i_1_n.BLIF un1_as_030_4.BLIF \
-state_machine_as_030_000_sync_3_2_1_n.BLIF un1_as_030_3.BLIF N_168_1.BLIF \
-DSACK_INT_1_sqmuxa.BLIF N_168_2.BLIF state_machine_un17_clk_030_n.BLIF \
-N_168_3.BLIF state_machine_un60_clk_000_d_n.BLIF N_168_4.BLIF \
-DTACK_SYNC_1_sqmuxa.BLIF N_168_5.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF N_168_6.BLIF \
-VPA_SYNC_1_sqmuxa.BLIF N_171_1.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_171_2.BLIF \
-N_103.BLIF un1_bg_030_0_1.BLIF N_104.BLIF un1_bg_030_0_2.BLIF N_93.BLIF \
-clk_cpu_est_11_0_1_1__n.BLIF N_105.BLIF clk_cpu_est_11_0_2_1__n.BLIF \
-VPA_SYNC_1_sqmuxa_1_0.BLIF state_machine_un42_clk_030_1_n.BLIF \
-state_machine_un15_clk_000_d_n.BLIF state_machine_un42_clk_030_2_n.BLIF \
-state_machine_un13_clk_000_d_n.BLIF state_machine_un42_clk_030_3_n.BLIF \
-state_machine_un8_clk_000_d_n.BLIF state_machine_un42_clk_030_4_n.BLIF \
-state_machine_un8_clk_000_d_1_n.BLIF state_machine_un42_clk_030_5_n.BLIF \
-state_machine_un13_clk_000_d_1_n.BLIF N_132_1.BLIF N_107.BLIF N_131_1.BLIF \
-N_94.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_91.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \
-N_110.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_108.BLIF \
-UDS_000_INT_0_sqmuxa_1_2.BLIF N_109.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \
-N_106.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF N_101.BLIF \
-state_machine_un8_clk_000_d_1_0_n.BLIF N_99.BLIF \
-state_machine_un8_clk_000_d_2_n.BLIF AS_000_INT_1_sqmuxa.BLIF \
-state_machine_un8_clk_000_d_3_n.BLIF RW_i.BLIF \
-state_machine_un13_clk_000_d_1_0_n.BLIF N_102_i.BLIF \
-state_machine_un13_clk_000_d_2_0_n.BLIF AS_000_INT_i.BLIF \
-VPA_SYNC_1_sqmuxa_1_1.BLIF dsack_i_1__n.BLIF VPA_SYNC_1_sqmuxa_2.BLIF \
-AS_030_i.BLIF VPA_SYNC_1_sqmuxa_3.BLIF sm_amiga_i_7__n.BLIF \
-VPA_SYNC_1_sqmuxa_4.BLIF CLK_000_D_i.BLIF N_107_1.BLIF sm_amiga_i_2__n.BLIF \
-N_98_1.BLIF sm_amiga_i_1__n.BLIF as_000_int_0_un3_n.BLIF \
-state_machine_un13_clk_000_d_1_i_n.BLIF as_000_int_0_un1_n.BLIF VPA_D_i.BLIF \
-as_000_int_0_un0_n.BLIF VMA_INT_i.BLIF vma_int_0_un3_n.BLIF \
-cpu_est_i_0__n.BLIF vma_int_0_un1_n.BLIF cpu_est_i_1__n.BLIF \
-vma_int_0_un0_n.BLIF cpu_est_i_3__n.BLIF uds_000_int_0_un3_n.BLIF \
-state_machine_un8_clk_000_d_1_i_0_n.BLIF uds_000_int_0_un1_n.BLIF DTACK_i.BLIF \
-uds_000_int_0_un0_n.BLIF sm_amiga_i_3__n.BLIF dtack_sync_0_un3_n.BLIF \
-sm_amiga_i_4__n.BLIF dtack_sync_0_un1_n.BLIF sm_amiga_i_5__n.BLIF \
-dtack_sync_0_un0_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF \
-VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un1_n.BLIF N_98_i.BLIF \
-vpa_sync_0_un0_n.BLIF state_machine_un42_clk_030_i_n.BLIF \
-dsack_int_0_1__un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF \
-dsack_int_0_1__un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \
-dsack_int_0_1__un0_n.BLIF AS_030_000_SYNC_i.BLIF as_030_000_sync_0_un3_n.BLIF \
-DS_030_i.BLIF as_030_000_sync_0_un1_n.BLIF cpu_est_i_2__n.BLIF \
-as_030_000_sync_0_un0_n.BLIF state_machine_un13_clk_000_d_2_i_n.BLIF \
-fpu_cs_int_0_un3_n.BLIF CLK_000_DD_i.BLIF fpu_cs_int_0_un1_n.BLIF \
-sm_amiga_i_6__n.BLIF fpu_cs_int_0_un0_n.BLIF CLK_030_i.BLIF \
-lds_000_int_0_un3_n.BLIF a_i_30__n.BLIF lds_000_int_0_un1_n.BLIF \
-a_i_31__n.BLIF lds_000_int_0_un0_n.BLIF a_i_28__n.BLIF cpu_est_0_3__un3_n.BLIF \
-a_i_29__n.BLIF cpu_est_0_3__un1_n.BLIF a_i_26__n.BLIF cpu_est_0_3__un0_n.BLIF \
-a_i_27__n.BLIF cpu_est_0_2__un3_n.BLIF a_i_24__n.BLIF cpu_est_0_2__un1_n.BLIF \
-a_i_25__n.BLIF cpu_est_0_2__un0_n.BLIF a_i_19__n.BLIF bg_000_0_un3_n.BLIF \
-a_i_16__n.BLIF bg_000_0_un1_n.BLIF a_i_18__n.BLIF bg_000_0_un0_n.BLIF \
-bgack_030_int_0_un3_n.BLIF RST_i.BLIF bgack_030_int_0_un1_n.BLIF \
-bgack_030_int_0_un0_n.BLIF FPU_CS_INT_i.BLIF cpu_est_0_1__un3_n.BLIF \
-CPU_SPACE_i.BLIF cpu_est_0_1__un1_n.BLIF BGACK_030_INT_i.BLIF \
-cpu_est_0_1__un0_n.BLIF AS_030_c.BLIF ipl_030_0_0__un3_n.BLIF \
-ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF DS_030_c.BLIF \
-ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF \
-ipl_030_0_2__un3_n.BLIF size_c_0__n.BLIF ipl_030_0_2__un1_n.BLIF \
-ipl_030_0_2__un0_n.BLIF size_c_1__n.BLIF a_15__n.BLIF a_c_0__n.BLIF \
-a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF a_10__n.BLIF a_9__n.BLIF \
+DSACK_0_.BLIF ipl_c_0__n.BLIF ipl_c_1__n.BLIF ipl_c_2__n.BLIF \
+inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF dsack_c_1__n.BLIF \
+cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF DTACK_c.BLIF cpu_est_0_.BLIF \
+cpu_est_1_.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \
+inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \
+RST_c.BLIF inst_CLK_000_D1.BLIF inst_CLK_OUT_PRE.BLIF RESETDFFreg.BLIF \
+vcc_n_n.BLIF gnd_n_n.BLIF RW_c.BLIF cpu_est_2_.BLIF CLK_CNT_0_.BLIF \
+fc_c_0__n.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF fc_c_1__n.BLIF \
+inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF \
+state_machine_un60_clk_000_d0_n.BLIF SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF \
+N_100_i.BLIF SM_AMIGA_4_.BLIF sm_amiga_ns_0_2__n.BLIF SM_AMIGA_3_.BLIF \
+N_103_i.BLIF DSACK_INT_1_sqmuxa.BLIF N_104_i.BLIF \
+state_machine_un13_as_000_int_n.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_106_i.BLIF \
+un1_as_030_4.BLIF N_105_i.BLIF SM_AMIGA_5_.BLIF sm_amiga_ns_0_5__n.BLIF \
+SM_AMIGA_2_.BLIF N_107_i.BLIF SM_AMIGA_0_.BLIF N_108_i.BLIF \
+state_machine_lds_000_int_8_n.BLIF sm_amiga_ns_0_6__n.BLIF \
+state_machine_uds_000_int_8_n.BLIF N_90_i.BLIF N_93_0.BLIF N_128_i.BLIF \
+N_126_i.BLIF N_127_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_1__n.BLIF N_133_i.BLIF \
+N_132_i.BLIF N_134_i.BLIF clk_cpu_est_11_0_3__n.BLIF N_125_i.BLIF \
+cpu_est_0_0_.BLIF N_124_i.BLIF N_130_i.BLIF N_131_i.BLIF N_121_i.BLIF \
+N_91_0.BLIF N_109_i.BLIF sm_amiga_ns_0_7__n.BLIF CLK_OUT_PRE_0.BLIF \
+state_machine_un8_clk_000_d0_i_n.BLIF state_machine_un13_clk_000_d0_i_n.BLIF \
+state_machine_un15_clk_000_d0_0_n.BLIF BG_030_c_i.BLIF \
+state_machine_un1_clk_030_0_n.BLIF clk_un4_clk_000_d1_n.BLIF \
+state_machine_un17_clk_030_0_n.BLIF N_144.BLIF un1_as_030_3_0.BLIF N_101.BLIF \
+state_machine_as_030_000_sync_3_2_n.BLIF VPA_SYNC_1_sqmuxa.BLIF N_96_i.BLIF \
+N_97.BLIF un1_bg_030_0.BLIF state_machine_un34_clk_000_d0_n.BLIF \
+clk_un4_clk_000_d1_i_n.BLIF N_96.BLIF state_machine_un6_bgack_000_0_n.BLIF \
+N_102.BLIF N_98_i.BLIF UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_1.BLIF \
+N_111_i.BLIF N_167.BLIF N_99_i.BLIF N_170.BLIF N_92.BLIF N_92_0.BLIF N_91.BLIF \
+state_machine_un34_clk_000_d0_i_n.BLIF N_99.BLIF a_c_i_0__n.BLIF N_111.BLIF \
+size_c_i_1__n.BLIF N_98.BLIF N_102_i.BLIF state_machine_un6_bgack_000_n.BLIF \
+state_machine_un42_clk_030_n.BLIF N_144_i.BLIF DTACK_SYNC_1_sqmuxa.BLIF \
+state_machine_lds_000_int_8_0_n.BLIF un1_bg_030.BLIF \
+state_machine_uds_000_int_8_0_n.BLIF state_machine_as_030_000_sync_3_n.BLIF \
+state_machine_un60_clk_000_d0_i_n.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF \
+un1_bg_030_0_1.BLIF un1_as_030_3.BLIF un1_bg_030_0_2.BLIF \
+state_machine_un17_clk_030_n.BLIF state_machine_as_030_000_sync_3_2_1_n.BLIF \
+state_machine_un1_clk_030_n.BLIF clk_cpu_est_11_0_1_3__n.BLIF \
+VPA_SYNC_1_sqmuxa_1_0.BLIF clk_cpu_est_11_0_1_1__n.BLIF \
+state_machine_un15_clk_000_d0_n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \
+state_machine_un13_clk_000_d0_n.BLIF N_167_1.BLIF \
+state_machine_un8_clk_000_d0_n.BLIF N_167_2.BLIF N_109.BLIF N_167_3.BLIF \
+state_machine_un13_clk_000_d0_1_n.BLIF N_167_4.BLIF N_129.BLIF N_167_5.BLIF \
+state_machine_un13_clk_000_d0_2_n.BLIF N_167_6.BLIF N_130.BLIF N_170_1.BLIF \
+N_131.BLIF N_170_2.BLIF N_124.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_125.BLIF \
+UDS_000_INT_0_sqmuxa_1_2.BLIF N_134.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \
+N_134_1.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_106.BLIF \
+UDS_000_INT_0_sqmuxa_2.BLIF clk_cpu_est_11_3__n.BLIF \
+state_machine_un34_clk_000_d0_i_1_n.BLIF N_132.BLIF \
+state_machine_un42_clk_030_1_n.BLIF N_133.BLIF \
+state_machine_un42_clk_030_2_n.BLIF clk_cpu_est_11_1__n.BLIF \
+state_machine_un42_clk_030_3_n.BLIF N_127.BLIF \
+state_machine_un42_clk_030_4_n.BLIF N_126.BLIF \
+state_machine_un42_clk_030_5_n.BLIF N_128.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF \
+N_93.BLIF N_130_1.BLIF N_90.BLIF N_131_1.BLIF N_107.BLIF \
+state_machine_un8_clk_000_d0_1_n.BLIF N_108.BLIF \
+state_machine_un8_clk_000_d0_2_n.BLIF N_105.BLIF \
+state_machine_un8_clk_000_d0_3_n.BLIF N_103.BLIF \
+state_machine_un8_clk_000_d0_4_n.BLIF N_104.BLIF \
+state_machine_un13_clk_000_d0_1_0_n.BLIF N_100.BLIF \
+state_machine_un13_clk_000_d0_2_0_n.BLIF AS_000_INT_1_sqmuxa.BLIF \
+VPA_SYNC_1_sqmuxa_1_1.BLIF RW_i.BLIF VPA_SYNC_1_sqmuxa_2.BLIF \
+nEXP_SPACE_i.BLIF VPA_SYNC_1_sqmuxa_3.BLIF N_101_i.BLIF \
+VPA_SYNC_1_sqmuxa_4.BLIF AS_000_INT_i.BLIF N_106_1.BLIF dsack_i_1__n.BLIF \
+cpu_est_0_3__un3_n.BLIF AS_030_i.BLIF cpu_est_0_3__un1_n.BLIF \
+CLK_000_D0_i.BLIF cpu_est_0_3__un0_n.BLIF sm_amiga_i_3__n.BLIF \
+cpu_est_0_1__un3_n.BLIF sm_amiga_i_4__n.BLIF cpu_est_0_1__un1_n.BLIF \
+CLK_000_D1_i.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_i_0__n.BLIF \
+as_000_int_0_un3_n.BLIF cpu_est_i_3__n.BLIF as_000_int_0_un1_n.BLIF \
+cpu_est_i_2__n.BLIF as_000_int_0_un0_n.BLIF VPA_D_i.BLIF bg_000_0_un3_n.BLIF \
+VMA_INT_i.BLIF bg_000_0_un1_n.BLIF cpu_est_i_1__n.BLIF bg_000_0_un0_n.BLIF \
+state_machine_un13_clk_000_d0_2_i_n.BLIF as_030_000_sync_0_un3_n.BLIF \
+state_machine_un13_clk_000_d0_1_i_n.BLIF as_030_000_sync_0_un1_n.BLIF \
+DTACK_i.BLIF as_030_000_sync_0_un0_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF \
+fpu_cs_int_0_un3_n.BLIF a_i_18__n.BLIF fpu_cs_int_0_un1_n.BLIF a_i_16__n.BLIF \
+fpu_cs_int_0_un0_n.BLIF a_i_19__n.BLIF dtack_sync_0_un3_n.BLIF CLK_030_i.BLIF \
+dtack_sync_0_un1_n.BLIF state_machine_un42_clk_030_i_n.BLIF \
+dtack_sync_0_un0_n.BLIF sm_amiga_i_6__n.BLIF vma_int_0_un3_n.BLIF \
+sm_amiga_i_7__n.BLIF vma_int_0_un1_n.BLIF AS_030_000_SYNC_i.BLIF \
+vma_int_0_un0_n.BLIF DS_030_i.BLIF cpu_est_0_2__un3_n.BLIF \
+UDS_000_INT_0_sqmuxa_1_i.BLIF cpu_est_0_2__un1_n.BLIF \
+UDS_000_INT_0_sqmuxa_i.BLIF cpu_est_0_2__un0_n.BLIF sm_amiga_i_5__n.BLIF \
+ipl_030_0_0__un3_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF ipl_030_0_0__un1_n.BLIF \
+N_97_i.BLIF ipl_030_0_0__un0_n.BLIF a_i_30__n.BLIF ipl_030_0_1__un3_n.BLIF \
+a_i_31__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_28__n.BLIF ipl_030_0_1__un0_n.BLIF \
+a_i_29__n.BLIF ipl_030_0_2__un3_n.BLIF a_i_26__n.BLIF ipl_030_0_2__un1_n.BLIF \
+a_i_27__n.BLIF ipl_030_0_2__un0_n.BLIF a_i_24__n.BLIF \
+bgack_030_int_0_un3_n.BLIF a_i_25__n.BLIF bgack_030_int_0_un1_n.BLIF \
+bgack_030_int_0_un0_n.BLIF RST_i.BLIF uds_000_int_0_un3_n.BLIF \
+uds_000_int_0_un1_n.BLIF FPU_CS_INT_i.BLIF uds_000_int_0_un0_n.BLIF \
+BGACK_030_INT_i.BLIF lds_000_int_0_un3_n.BLIF AS_030_c.BLIF \
+lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF vpa_sync_0_un3_n.BLIF \
+DS_030_c.BLIF vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF \
+dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF size_c_0__n.BLIF \
+dsack_int_0_1__un0_n.BLIF a_15__n.BLIF size_c_1__n.BLIF a_14__n.BLIF \
+a_c_0__n.BLIF a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF a_10__n.BLIF a_9__n.BLIF \
a_8__n.BLIF a_7__n.BLIF a_6__n.BLIF a_c_16__n.BLIF a_5__n.BLIF a_c_17__n.BLIF \
a_4__n.BLIF a_c_18__n.BLIF a_3__n.BLIF a_c_19__n.BLIF a_2__n.BLIF \
a_c_20__n.BLIF a_1__n.BLIF a_c_21__n.BLIF a_c_22__n.BLIF a_c_23__n.BLIF \
a_c_24__n.BLIF a_c_25__n.BLIF a_c_26__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF \
-a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF CPU_SPACE_c.BLIF BG_030_c.BLIF \
+a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF \
BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF CLK_OSZI_c.BLIF \
-CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF
+CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_1_reg.BLIF \
+IPL_030DFFSH_2_reg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF
.outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \
CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_3_.D SM_AMIGA_3_.C \
@@ -218,86 +217,84 @@ inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_VPA_SYNC.D inst_VPA_SYNC.C \
inst_VPA_SYNC.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \
inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_UDS_000_INTreg.D \
inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP CLK_CNT_0_.D CLK_CNT_0_.C \
-inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D \
-RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C CLK_OUT_INTreg.D \
+inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D \
+RESETDFFreg.C inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_OUT_INTreg.D \
CLK_OUT_INTreg.C DSACK_1_ DTACK DSACK_0_ ipl_c_0__n ipl_c_1__n ipl_c_2__n \
-gnd_n_n dsack_c_1__n DTACK_c RST_c vcc_n_n RW_c fc_c_0__n \
-state_machine_un1_clk_030_n fc_c_1__n state_machine_un6_bgack_000_n N_99_i \
-state_machine_un13_as_000_int_n un1_bg_030 N_101_i sm_amiga_ns_0_2__n N_107_i \
-N_106_i sm_amiga_ns_0_5__n N_108_i N_109_i N_110_i sm_amiga_ns_0_7__n N_91_0 \
-CLK_OUT_PRE_i N_94_0 state_machine_un8_clk_000_d_i_n \
-state_machine_un13_clk_000_d_i_n state_machine_un15_clk_000_d_0_n N_93_0 \
-N_104_i N_105_i N_103_i state_machine_un60_clk_000_d_i_n \
-state_machine_un17_clk_030_0_n un1_as_030_3_0 N_145_i clk_un4_clk_000_dd_n \
-a_c_i_0__n clk_cpu_est_11_1__n state_machine_uds_000_int_8_0_n \
-state_machine_un42_clk_030_n state_machine_lds_000_int_8_0_n N_102 \
-state_machine_as_030_000_sync_3_2_n N_98 size_c_i_1__n N_97 \
-state_machine_un34_clk_000_d_i_n N_100 N_131_i N_92 N_132_i N_112 N_122_i \
-N_127 N_125_i N_125 N_126_i N_128 N_134_i N_129 N_133_i N_130 N_135_i N_168 \
-clk_cpu_est_11_0_3__n N_171 N_130_i N_135_1 clk_cpu_est_11_0_1__n \
-state_machine_un13_clk_000_d_2_n N_128_i clk_cpu_est_11_3__n un1_bg_030_0 \
-N_135 N_97_i N_133 BG_030_c_i N_134 N_127_i N_132 N_129_i N_131 N_92_0 N_126 \
-N_100_i state_machine_un34_clk_000_d_n N_112_i UDS_000_INT_0_sqmuxa \
-UDS_000_INT_0_sqmuxa_1 clk_un4_clk_000_dd_i_n \
-state_machine_as_030_000_sync_3_n state_machine_un6_bgack_000_0_n N_145 \
-state_machine_un1_clk_030_0_n state_machine_lds_000_int_8_n \
-clk_cpu_est_11_0_1_3__n state_machine_uds_000_int_8_n \
-state_machine_un34_clk_000_d_i_1_n un1_as_030_4 \
-state_machine_as_030_000_sync_3_2_1_n un1_as_030_3 N_168_1 DSACK_INT_1_sqmuxa \
-N_168_2 state_machine_un17_clk_030_n N_168_3 state_machine_un60_clk_000_d_n \
-N_168_4 DTACK_SYNC_1_sqmuxa N_168_5 DTACK_SYNC_1_sqmuxa_1 N_168_6 \
-VPA_SYNC_1_sqmuxa N_171_1 VPA_SYNC_1_sqmuxa_1 N_171_2 N_103 un1_bg_030_0_1 \
-N_104 un1_bg_030_0_2 N_93 clk_cpu_est_11_0_1_1__n N_105 \
-clk_cpu_est_11_0_2_1__n VPA_SYNC_1_sqmuxa_1_0 state_machine_un42_clk_030_1_n \
-state_machine_un15_clk_000_d_n state_machine_un42_clk_030_2_n \
-state_machine_un13_clk_000_d_n state_machine_un42_clk_030_3_n \
-state_machine_un8_clk_000_d_n state_machine_un42_clk_030_4_n \
-state_machine_un8_clk_000_d_1_n state_machine_un42_clk_030_5_n \
-state_machine_un13_clk_000_d_1_n N_132_1 N_107 N_131_1 N_94 \
-UDS_000_INT_0_sqmuxa_1_0 N_91 UDS_000_INT_0_sqmuxa_2 N_110 \
-UDS_000_INT_0_sqmuxa_1_1 N_108 UDS_000_INT_0_sqmuxa_1_2 N_109 \
-UDS_000_INT_0_sqmuxa_1_3 N_106 DTACK_SYNC_1_sqmuxa_1_0 N_101 \
-state_machine_un8_clk_000_d_1_0_n N_99 state_machine_un8_clk_000_d_2_n \
-AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d_3_n RW_i \
-state_machine_un13_clk_000_d_1_0_n N_102_i state_machine_un13_clk_000_d_2_0_n \
-AS_000_INT_i VPA_SYNC_1_sqmuxa_1_1 dsack_i_1__n VPA_SYNC_1_sqmuxa_2 AS_030_i \
-VPA_SYNC_1_sqmuxa_3 sm_amiga_i_7__n VPA_SYNC_1_sqmuxa_4 CLK_000_D_i N_107_1 \
-sm_amiga_i_2__n N_98_1 sm_amiga_i_1__n as_000_int_0_un3_n \
-state_machine_un13_clk_000_d_1_i_n as_000_int_0_un1_n VPA_D_i \
-as_000_int_0_un0_n VMA_INT_i vma_int_0_un3_n cpu_est_i_0__n vma_int_0_un1_n \
-cpu_est_i_1__n vma_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n \
-state_machine_un8_clk_000_d_1_i_0_n uds_000_int_0_un1_n DTACK_i \
-uds_000_int_0_un0_n sm_amiga_i_3__n dtack_sync_0_un3_n sm_amiga_i_4__n \
-dtack_sync_0_un1_n sm_amiga_i_5__n dtack_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i \
-vpa_sync_0_un3_n VPA_SYNC_1_sqmuxa_i vpa_sync_0_un1_n N_98_i vpa_sync_0_un0_n \
-state_machine_un42_clk_030_i_n dsack_int_0_1__un3_n UDS_000_INT_0_sqmuxa_1_i \
-dsack_int_0_1__un1_n UDS_000_INT_0_sqmuxa_i dsack_int_0_1__un0_n \
-AS_030_000_SYNC_i as_030_000_sync_0_un3_n DS_030_i as_030_000_sync_0_un1_n \
-cpu_est_i_2__n as_030_000_sync_0_un0_n state_machine_un13_clk_000_d_2_i_n \
-fpu_cs_int_0_un3_n CLK_000_DD_i fpu_cs_int_0_un1_n sm_amiga_i_6__n \
-fpu_cs_int_0_un0_n CLK_030_i lds_000_int_0_un3_n a_i_30__n lds_000_int_0_un1_n \
-a_i_31__n lds_000_int_0_un0_n a_i_28__n cpu_est_0_3__un3_n a_i_29__n \
-cpu_est_0_3__un1_n a_i_26__n cpu_est_0_3__un0_n a_i_27__n cpu_est_0_2__un3_n \
-a_i_24__n cpu_est_0_2__un1_n a_i_25__n cpu_est_0_2__un0_n a_i_19__n \
-bg_000_0_un3_n a_i_16__n bg_000_0_un1_n a_i_18__n bg_000_0_un0_n \
-bgack_030_int_0_un3_n RST_i bgack_030_int_0_un1_n bgack_030_int_0_un0_n \
-FPU_CS_INT_i cpu_est_0_1__un3_n CPU_SPACE_i cpu_est_0_1__un1_n BGACK_030_INT_i \
-cpu_est_0_1__un0_n AS_030_c ipl_030_0_0__un3_n ipl_030_0_0__un1_n \
-ipl_030_0_0__un0_n DS_030_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n \
-ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n ipl_030_0_2__un1_n \
-ipl_030_0_2__un0_n size_c_1__n a_15__n a_c_0__n a_14__n a_13__n a_12__n \
-a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n a_c_17__n a_4__n \
-a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n \
+dsack_c_1__n DTACK_c RST_c vcc_n_n gnd_n_n RW_c fc_c_0__n fc_c_1__n \
+state_machine_un60_clk_000_d0_n N_100_i sm_amiga_ns_0_2__n N_103_i \
+DSACK_INT_1_sqmuxa N_104_i state_machine_un13_as_000_int_n VPA_SYNC_1_sqmuxa_1 \
+N_106_i un1_as_030_4 N_105_i sm_amiga_ns_0_5__n N_107_i N_108_i \
+state_machine_lds_000_int_8_n sm_amiga_ns_0_6__n state_machine_uds_000_int_8_n \
+N_90_i N_93_0 N_128_i N_126_i N_127_i N_129_i clk_cpu_est_11_0_1__n N_133_i \
+N_132_i N_134_i clk_cpu_est_11_0_3__n N_125_i N_124_i N_130_i N_131_i N_121_i \
+N_91_0 N_109_i sm_amiga_ns_0_7__n state_machine_un8_clk_000_d0_i_n \
+state_machine_un13_clk_000_d0_i_n state_machine_un15_clk_000_d0_0_n BG_030_c_i \
+state_machine_un1_clk_030_0_n clk_un4_clk_000_d1_n \
+state_machine_un17_clk_030_0_n N_144 un1_as_030_3_0 N_101 \
+state_machine_as_030_000_sync_3_2_n VPA_SYNC_1_sqmuxa N_96_i N_97 un1_bg_030_0 \
+state_machine_un34_clk_000_d0_n clk_un4_clk_000_d1_i_n N_96 \
+state_machine_un6_bgack_000_0_n N_102 N_98_i UDS_000_INT_0_sqmuxa \
+UDS_000_INT_0_sqmuxa_1 N_111_i N_167 N_99_i N_170 N_92 N_92_0 N_91 \
+state_machine_un34_clk_000_d0_i_n N_99 a_c_i_0__n N_111 size_c_i_1__n N_98 \
+N_102_i state_machine_un6_bgack_000_n state_machine_un42_clk_030_n N_144_i \
+DTACK_SYNC_1_sqmuxa state_machine_lds_000_int_8_0_n un1_bg_030 \
+state_machine_uds_000_int_8_0_n state_machine_as_030_000_sync_3_n \
+state_machine_un60_clk_000_d0_i_n DTACK_SYNC_1_sqmuxa_1 un1_bg_030_0_1 \
+un1_as_030_3 un1_bg_030_0_2 state_machine_un17_clk_030_n \
+state_machine_as_030_000_sync_3_2_1_n state_machine_un1_clk_030_n \
+clk_cpu_est_11_0_1_3__n VPA_SYNC_1_sqmuxa_1_0 clk_cpu_est_11_0_1_1__n \
+state_machine_un15_clk_000_d0_n clk_cpu_est_11_0_2_1__n \
+state_machine_un13_clk_000_d0_n N_167_1 state_machine_un8_clk_000_d0_n N_167_2 \
+N_109 N_167_3 state_machine_un13_clk_000_d0_1_n N_167_4 N_129 N_167_5 \
+state_machine_un13_clk_000_d0_2_n N_167_6 N_130 N_170_1 N_131 N_170_2 N_124 \
+UDS_000_INT_0_sqmuxa_1_1 N_125 UDS_000_INT_0_sqmuxa_1_2 N_134 \
+UDS_000_INT_0_sqmuxa_1_3 N_134_1 UDS_000_INT_0_sqmuxa_1_0 N_106 \
+UDS_000_INT_0_sqmuxa_2 clk_cpu_est_11_3__n state_machine_un34_clk_000_d0_i_1_n \
+N_132 state_machine_un42_clk_030_1_n N_133 state_machine_un42_clk_030_2_n \
+clk_cpu_est_11_1__n state_machine_un42_clk_030_3_n N_127 \
+state_machine_un42_clk_030_4_n N_126 state_machine_un42_clk_030_5_n N_128 \
+DTACK_SYNC_1_sqmuxa_1_0 N_93 N_130_1 N_90 N_131_1 N_107 \
+state_machine_un8_clk_000_d0_1_n N_108 state_machine_un8_clk_000_d0_2_n N_105 \
+state_machine_un8_clk_000_d0_3_n N_103 state_machine_un8_clk_000_d0_4_n N_104 \
+state_machine_un13_clk_000_d0_1_0_n N_100 state_machine_un13_clk_000_d0_2_0_n \
+AS_000_INT_1_sqmuxa VPA_SYNC_1_sqmuxa_1_1 RW_i VPA_SYNC_1_sqmuxa_2 \
+nEXP_SPACE_i VPA_SYNC_1_sqmuxa_3 N_101_i VPA_SYNC_1_sqmuxa_4 AS_000_INT_i \
+N_106_1 dsack_i_1__n cpu_est_0_3__un3_n AS_030_i cpu_est_0_3__un1_n \
+CLK_000_D0_i cpu_est_0_3__un0_n sm_amiga_i_3__n cpu_est_0_1__un3_n \
+sm_amiga_i_4__n cpu_est_0_1__un1_n CLK_000_D1_i cpu_est_0_1__un0_n \
+cpu_est_i_0__n as_000_int_0_un3_n cpu_est_i_3__n as_000_int_0_un1_n \
+cpu_est_i_2__n as_000_int_0_un0_n VPA_D_i bg_000_0_un3_n VMA_INT_i \
+bg_000_0_un1_n cpu_est_i_1__n bg_000_0_un0_n \
+state_machine_un13_clk_000_d0_2_i_n as_030_000_sync_0_un3_n \
+state_machine_un13_clk_000_d0_1_i_n as_030_000_sync_0_un1_n DTACK_i \
+as_030_000_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i fpu_cs_int_0_un3_n a_i_18__n \
+fpu_cs_int_0_un1_n a_i_16__n fpu_cs_int_0_un0_n a_i_19__n dtack_sync_0_un3_n \
+CLK_030_i dtack_sync_0_un1_n state_machine_un42_clk_030_i_n dtack_sync_0_un0_n \
+sm_amiga_i_6__n vma_int_0_un3_n sm_amiga_i_7__n vma_int_0_un1_n \
+AS_030_000_SYNC_i vma_int_0_un0_n DS_030_i cpu_est_0_2__un3_n \
+UDS_000_INT_0_sqmuxa_1_i cpu_est_0_2__un1_n UDS_000_INT_0_sqmuxa_i \
+cpu_est_0_2__un0_n sm_amiga_i_5__n ipl_030_0_0__un3_n VPA_SYNC_1_sqmuxa_i \
+ipl_030_0_0__un1_n N_97_i ipl_030_0_0__un0_n a_i_30__n ipl_030_0_1__un3_n \
+a_i_31__n ipl_030_0_1__un1_n a_i_28__n ipl_030_0_1__un0_n a_i_29__n \
+ipl_030_0_2__un3_n a_i_26__n ipl_030_0_2__un1_n a_i_27__n ipl_030_0_2__un0_n \
+a_i_24__n bgack_030_int_0_un3_n a_i_25__n bgack_030_int_0_un1_n \
+bgack_030_int_0_un0_n RST_i uds_000_int_0_un3_n uds_000_int_0_un1_n \
+FPU_CS_INT_i uds_000_int_0_un0_n BGACK_030_INT_i lds_000_int_0_un3_n AS_030_c \
+lds_000_int_0_un1_n lds_000_int_0_un0_n vpa_sync_0_un3_n DS_030_c \
+vpa_sync_0_un1_n vpa_sync_0_un0_n dsack_int_0_1__un3_n dsack_int_0_1__un1_n \
+size_c_0__n dsack_int_0_1__un0_n a_15__n size_c_1__n a_14__n a_c_0__n a_13__n \
+a_12__n a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n a_c_17__n \
+a_4__n a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n \
a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n \
-a_c_30__n a_c_31__n CPU_SPACE_c BG_030_c BGACK_000_c CLK_030_c CLK_OSZI_c \
+a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c BGACK_000_c CLK_030_c CLK_OSZI_c \
DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE \
AVEC_EXP.OE CIIN.OE cpu_est_0_0_ CLK_OUT_PRE_0
-.names N_104_i.BLIF N_105_i.BLIF SM_AMIGA_3_.D
+.names N_103_i.BLIF N_104_i.BLIF SM_AMIGA_3_.D
11 1
.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D
0 1
-.names N_108_i.BLIF N_109_i.BLIF SM_AMIGA_1_.D
-11 1
+.names sm_amiga_ns_0_6__n.BLIF SM_AMIGA_1_.D
+0 1
.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D
0 1
.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D
@@ -309,13 +306,13 @@ AVEC_EXP.OE CIIN.OE cpu_est_0_0_ CLK_OUT_PRE_0
.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D
1- 1
-1 1
-.names inst_CLK_000_D.BLIF N_99_i.BLIF SM_AMIGA_7_.D
+.names inst_CLK_000_D0.BLIF N_98_i.BLIF SM_AMIGA_7_.D
11 1
-.names N_100_i.BLIF N_112_i.BLIF SM_AMIGA_6_.D
+.names N_99_i.BLIF N_111_i.BLIF SM_AMIGA_6_.D
11 1
.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D
0 1
-.names CLK_000_D_i.BLIF N_103_i.BLIF SM_AMIGA_4_.D
+.names CLK_000_D0_i.BLIF N_102_i.BLIF SM_AMIGA_4_.D
11 1
.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D
1- 1
@@ -365,516 +362,504 @@ inst_AS_030_000_SYNC.D
-1 1
.names CLK_CNT_0_.BLIF CLK_CNT_0_.D
0 1
-.names gnd_n_n
.names vcc_n_n
1
-.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n
+.names gnd_n_n
+.names state_machine_un60_clk_000_d0_i_n.BLIF state_machine_un60_clk_000_d0_n
0 1
-.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
+.names N_100.BLIF N_100_i
0 1
-.names N_99.BLIF N_99_i
-0 1
-.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un13_as_000_int_n
+.names N_100_i.BLIF N_101_i.BLIF sm_amiga_ns_0_2__n
11 1
-.names un1_bg_030_0.BLIF un1_bg_030
+.names N_103.BLIF N_103_i
0 1
-.names N_101.BLIF N_101_i
-0 1
-.names N_101_i.BLIF N_102_i.BLIF sm_amiga_ns_0_2__n
-11 1
-.names N_107.BLIF N_107_i
-0 1
-.names N_106.BLIF N_106_i
-0 1
-.names N_106_i.BLIF N_107_i.BLIF sm_amiga_ns_0_5__n
-11 1
-.names N_108.BLIF N_108_i
-0 1
-.names N_109.BLIF N_109_i
-0 1
-.names N_110.BLIF N_110_i
-0 1
-.names N_98_i.BLIF N_110_i.BLIF sm_amiga_ns_0_7__n
-11 1
-.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_91_0
-11 1
-.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i
-0 1
-.names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_94_0
-11 1
-.names state_machine_un8_clk_000_d_n.BLIF state_machine_un8_clk_000_d_i_n
-0 1
-.names state_machine_un13_clk_000_d_n.BLIF state_machine_un13_clk_000_d_i_n
-0 1
-.names state_machine_un8_clk_000_d_i_n.BLIF \
-state_machine_un13_clk_000_d_i_n.BLIF state_machine_un15_clk_000_d_0_n
-11 1
-.names SM_AMIGA_3_.BLIF state_machine_un60_clk_000_d_i_n.BLIF N_93_0
+.names AS_030_i.BLIF N_97_i.BLIF DSACK_INT_1_sqmuxa
11 1
.names N_104.BLIF N_104_i
0 1
+.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un13_as_000_int_n
+11 1
+.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1
+11 1
+.names N_106.BLIF N_106_i
+0 1
+.names AS_030_i.BLIF N_144.BLIF un1_as_030_4
+11 1
.names N_105.BLIF N_105_i
0 1
-.names N_103.BLIF N_103_i
+.names N_105_i.BLIF N_106_i.BLIF sm_amiga_ns_0_5__n
+11 1
+.names N_107.BLIF N_107_i
0 1
-.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \
-state_machine_un60_clk_000_d_i_n
+.names N_108.BLIF N_108_i
+0 1
+.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n
+0 1
+.names N_107_i.BLIF N_108_i.BLIF sm_amiga_ns_0_6__n
+11 1
+.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n
+0 1
+.names CLK_000_D1_i.BLIF inst_CLK_OUT_PRE.BLIF N_90_i
+11 1
+.names SM_AMIGA_3_.BLIF state_machine_un60_clk_000_d0_i_n.BLIF N_93_0
+11 1
+.names N_128.BLIF N_128_i
+0 1
+.names N_126.BLIF N_126_i
+0 1
+.names N_127.BLIF N_127_i
+0 1
+.names N_129.BLIF N_129_i
+0 1
+.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \
+clk_cpu_est_11_0_1__n
+11 1
+.names N_133.BLIF N_133_i
+0 1
+.names N_132.BLIF N_132_i
+0 1
+.names N_134.BLIF N_134_i
+0 1
+.names clk_cpu_est_11_0_1_3__n.BLIF N_133_i.BLIF clk_cpu_est_11_0_3__n
+11 1
+.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_125_i
+11 1
+.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_124_i
+11 1
+.names N_130.BLIF N_130_i
+0 1
+.names N_131.BLIF N_131_i
+0 1
+.names N_130_i.BLIF N_131_i.BLIF N_121_i
+11 1
+.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_91_0
+11 1
+.names N_109.BLIF N_109_i
+0 1
+.names N_97_i.BLIF N_109_i.BLIF sm_amiga_ns_0_7__n
+11 1
+.names state_machine_un8_clk_000_d0_n.BLIF state_machine_un8_clk_000_d0_i_n
+0 1
+.names state_machine_un13_clk_000_d0_n.BLIF state_machine_un13_clk_000_d0_i_n
+0 1
+.names state_machine_un8_clk_000_d0_i_n.BLIF \
+state_machine_un13_clk_000_d0_i_n.BLIF state_machine_un15_clk_000_d0_0_n
+11 1
+.names BG_030_c.BLIF BG_030_c_i
+0 1
+.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n
+11 1
+.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF clk_un4_clk_000_d1_n
11 1
.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n
11 1
+.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_144
+11 1
.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_3_0
11 1
-.names N_145.BLIF N_145_i
-0 1
-.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un4_clk_000_dd_n
-11 1
-.names a_c_0__n.BLIF a_c_i_0__n
-0 1
-.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n
-0 1
-.names a_c_i_0__n.BLIF N_145_i.BLIF state_machine_uds_000_int_8_0_n
-11 1
-.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF \
-state_machine_un42_clk_030_n
-11 1
-.names N_145_i.BLIF state_machine_un34_clk_000_d_n.BLIF \
-state_machine_lds_000_int_8_0_n
-11 1
-.names N_112.BLIF SM_AMIGA_6_.BLIF N_102
+.names N_111.BLIF SM_AMIGA_6_.BLIF N_101
11 1
.names state_machine_as_030_000_sync_3_2_1_n.BLIF \
state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n
11 1
-.names N_98_1.BLIF SM_AMIGA_1_.BLIF N_98
+.names VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa
11 1
-.names size_c_1__n.BLIF size_c_i_1__n
+.names N_96.BLIF N_96_i
0 1
-.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_97
+.names N_90_i.BLIF SM_AMIGA_1_.BLIF N_97
11 1
-.names state_machine_un34_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF \
-state_machine_un34_clk_000_d_i_n
-11 1
-.names N_92.BLIF sm_amiga_i_6__n.BLIF N_100
-11 1
-.names N_131.BLIF N_131_i
-0 1
-.names N_92_0.BLIF N_92
-0 1
-.names N_132.BLIF N_132_i
-0 1
-.names AS_030_000_SYNC_i.BLIF clk_un4_clk_000_dd_n.BLIF N_112
-11 1
-.names N_131_i.BLIF N_132_i.BLIF N_122_i
-11 1
-.names N_125.BLIF cpu_est_i_0__n.BLIF N_127
-11 1
-.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_125_i
-11 1
-.names N_125_i.BLIF N_125
-0 1
-.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_126_i
-11 1
-.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_128
-11 1
-.names N_134.BLIF N_134_i
-0 1
-.names N_125_i.BLIF cpu_est_0_.BLIF N_129
-11 1
-.names N_133.BLIF N_133_i
-0 1
-.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d_2_n.BLIF N_130
-11 1
-.names N_135.BLIF N_135_i
-0 1
-.names N_168_5.BLIF N_168_6.BLIF N_168
-11 1
-.names clk_cpu_est_11_0_1_3__n.BLIF N_134_i.BLIF clk_cpu_est_11_0_3__n
-11 1
-.names N_171_1.BLIF N_171_2.BLIF N_171
-11 1
-.names N_130.BLIF N_130_i
-0 1
-.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_135_1
-11 1
-.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \
-clk_cpu_est_11_0_1__n
-11 1
-.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d_2_n
-11 1
-.names N_128.BLIF N_128_i
-0 1
-.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n
-0 1
.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0
11 1
-.names N_135_1.BLIF cpu_est_i_2__n.BLIF N_135
+.names state_machine_un34_clk_000_d0_i_n.BLIF state_machine_un34_clk_000_d0_n
+0 1
+.names clk_un4_clk_000_d1_n.BLIF clk_un4_clk_000_d1_i_n
+0 1
+.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_96
11 1
-.names N_97.BLIF N_97_i
-0 1
-.names N_126.BLIF cpu_est_3_reg.BLIF N_133
+.names BGACK_000_c.BLIF clk_un4_clk_000_d1_i_n.BLIF \
+state_machine_un6_bgack_000_0_n
11 1
-.names BG_030_c.BLIF BG_030_c_i
-0 1
-.names N_126_i.BLIF cpu_est_i_2__n.BLIF N_134
+.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_102
11 1
-.names N_127.BLIF N_127_i
-0 1
-.names N_132_1.BLIF cpu_est_i_2__n.BLIF N_132
-11 1
-.names N_129.BLIF N_129_i
-0 1
-.names N_131_1.BLIF state_machine_un13_clk_000_d_2_i_n.BLIF N_131
-11 1
-.names CLK_000_D_i.BLIF SM_AMIGA_7_.BLIF N_92_0
-11 1
-.names N_126_i.BLIF N_126
-0 1
-.names N_100.BLIF N_100_i
-0 1
-.names state_machine_un34_clk_000_d_i_n.BLIF state_machine_un34_clk_000_d_n
-0 1
-.names N_112.BLIF N_112_i
+.names N_98.BLIF N_98_i
0 1
.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \
UDS_000_INT_0_sqmuxa
11 1
-.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un4_clk_000_dd_n.BLIF \
+.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un4_clk_000_d1_n.BLIF \
UDS_000_INT_0_sqmuxa_1
11 1
-.names clk_un4_clk_000_dd_n.BLIF clk_un4_clk_000_dd_i_n
+.names N_111.BLIF N_111_i
0 1
-.names state_machine_as_030_000_sync_3_2_n.BLIF \
-state_machine_as_030_000_sync_3_n
+.names N_167_5.BLIF N_167_6.BLIF N_167
+11 1
+.names N_99.BLIF N_99_i
0 1
-.names BGACK_000_c.BLIF clk_un4_clk_000_dd_i_n.BLIF \
-state_machine_un6_bgack_000_0_n
+.names N_170_1.BLIF N_170_2.BLIF N_170
11 1
-.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_145
-11 1
-.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n
-11 1
-.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n
+.names N_92_0.BLIF N_92
0 1
-.names N_135_i.BLIF N_133_i.BLIF clk_cpu_est_11_0_1_3__n
-11 1
-.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n
-0 1
-.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un34_clk_000_d_i_1_n
-11 1
-.names AS_030_i.BLIF N_145.BLIF un1_as_030_4
-11 1
-.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_2_1_n
-11 1
-.names un1_as_030_3_0.BLIF un1_as_030_3
-0 1
-.names a_i_24__n.BLIF a_i_25__n.BLIF N_168_1
-11 1
-.names AS_030_i.BLIF N_98_i.BLIF DSACK_INT_1_sqmuxa
-11 1
-.names a_i_26__n.BLIF a_i_27__n.BLIF N_168_2
-11 1
-.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n
-0 1
-.names a_i_28__n.BLIF a_i_29__n.BLIF N_168_3
-11 1
-.names state_machine_un60_clk_000_d_i_n.BLIF state_machine_un60_clk_000_d_n
-0 1
-.names a_i_30__n.BLIF a_i_31__n.BLIF N_168_4
-11 1
-.names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \
-DTACK_SYNC_1_sqmuxa
-11 1
-.names N_168_1.BLIF N_168_2.BLIF N_168_5
-11 1
-.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1
-11 1
-.names N_168_3.BLIF N_168_4.BLIF N_168_6
-11 1
-.names VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa
-11 1
-.names a_c_20__n.BLIF a_c_21__n.BLIF N_171_1
-11 1
-.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1
-11 1
-.names a_c_22__n.BLIF a_c_23__n.BLIF N_171_2
-11 1
-.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_103
-11 1
-.names AS_030_c.BLIF BG_030_c_i.BLIF un1_bg_030_0_1
-11 1
-.names CLK_000_D_i.BLIF N_93.BLIF N_104
-11 1
-.names CPU_SPACE_i.BLIF N_97_i.BLIF un1_bg_030_0_2
-11 1
-.names N_93_0.BLIF N_93
-0 1
-.names N_127_i.BLIF N_128_i.BLIF clk_cpu_est_11_0_1_1__n
-11 1
-.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_105
-11 1
-.names N_129_i.BLIF N_130_i.BLIF clk_cpu_est_11_0_2_1__n
-11 1
-.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0
-11 1
-.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n
-11 1
-.names state_machine_un15_clk_000_d_0_n.BLIF state_machine_un15_clk_000_d_n
-0 1
-.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n
-11 1
-.names state_machine_un13_clk_000_d_1_0_n.BLIF \
-state_machine_un13_clk_000_d_2_0_n.BLIF state_machine_un13_clk_000_d_n
-11 1
-.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n
-11 1
-.names state_machine_un8_clk_000_d_3_n.BLIF cpu_est_i_3__n.BLIF \
-state_machine_un8_clk_000_d_n
-11 1
-.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF \
-state_machine_un42_clk_030_4_n
-11 1
-.names CLK_000_D_i.BLIF cpu_est_0_.BLIF state_machine_un8_clk_000_d_1_n
-11 1
-.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF \
-state_machine_un42_clk_030_5_n
-11 1
-.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF \
-state_machine_un13_clk_000_d_1_n
-11 1
-.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_132_1
-11 1
-.names N_107_1.BLIF state_machine_un60_clk_000_d_n.BLIF N_107
-11 1
-.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_131_1
-11 1
-.names N_94_0.BLIF N_94
-0 1
-.names inst_CLK_000_D.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0
+.names CLK_000_D0_i.BLIF SM_AMIGA_7_.BLIF N_92_0
11 1
.names N_91_0.BLIF N_91
0 1
-.names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2
+.names state_machine_un34_clk_000_d0_i_1_n.BLIF size_c_0__n.BLIF \
+state_machine_un34_clk_000_d0_i_n
11 1
-.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d_1_i_n.BLIF N_110
+.names N_92.BLIF sm_amiga_i_6__n.BLIF N_99
11 1
+.names a_c_0__n.BLIF a_c_i_0__n
+0 1
+.names AS_030_000_SYNC_i.BLIF clk_un4_clk_000_d1_n.BLIF N_111
+11 1
+.names size_c_1__n.BLIF size_c_i_1__n
+0 1
+.names N_91.BLIF sm_amiga_i_7__n.BLIF N_98
+11 1
+.names N_102.BLIF N_102_i
+0 1
+.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
+0 1
+.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF \
+state_machine_un42_clk_030_n
+11 1
+.names N_144.BLIF N_144_i
+0 1
+.names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \
+DTACK_SYNC_1_sqmuxa
+11 1
+.names N_144_i.BLIF state_machine_un34_clk_000_d0_n.BLIF \
+state_machine_lds_000_int_8_0_n
+11 1
+.names un1_bg_030_0.BLIF un1_bg_030
+0 1
+.names a_c_i_0__n.BLIF N_144_i.BLIF state_machine_uds_000_int_8_0_n
+11 1
+.names state_machine_as_030_000_sync_3_2_n.BLIF \
+state_machine_as_030_000_sync_3_n
+0 1
+.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \
+state_machine_un60_clk_000_d0_i_n
+11 1
+.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1
+11 1
+.names BG_030_c_i.BLIF N_96_i.BLIF un1_bg_030_0_1
+11 1
+.names un1_as_030_3_0.BLIF un1_as_030_3
+0 1
+.names AS_030_c.BLIF nEXP_SPACE_i.BLIF un1_bg_030_0_2
+11 1
+.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n
+0 1
+.names AS_030_i.BLIF nEXP_SPACE_c.BLIF state_machine_as_030_000_sync_3_2_1_n
+11 1
+.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n
+0 1
+.names N_134_i.BLIF N_132_i.BLIF clk_cpu_est_11_0_1_3__n
+11 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0
+11 1
+.names N_129_i.BLIF N_127_i.BLIF clk_cpu_est_11_0_1_1__n
+11 1
+.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n
+0 1
+.names N_126_i.BLIF N_128_i.BLIF clk_cpu_est_11_0_2_1__n
+11 1
+.names state_machine_un13_clk_000_d0_1_0_n.BLIF \
+state_machine_un13_clk_000_d0_2_0_n.BLIF state_machine_un13_clk_000_d0_n
+11 1
+.names a_i_24__n.BLIF a_i_25__n.BLIF N_167_1
+11 1
+.names state_machine_un8_clk_000_d0_4_n.BLIF \
+state_machine_un8_clk_000_d0_3_n.BLIF state_machine_un8_clk_000_d0_n
+11 1
+.names a_i_26__n.BLIF a_i_27__n.BLIF N_167_2
+11 1
+.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF N_109
+11 1
+.names a_i_28__n.BLIF a_i_29__n.BLIF N_167_3
+11 1
+.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF \
+state_machine_un13_clk_000_d0_1_n
+11 1
+.names a_i_30__n.BLIF a_i_31__n.BLIF N_167_4
+11 1
+.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d0_2_n.BLIF N_129
+11 1
+.names N_167_1.BLIF N_167_2.BLIF N_167_5
+11 1
+.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d0_2_n
+11 1
+.names N_167_3.BLIF N_167_4.BLIF N_167_6
+11 1
+.names N_130_1.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF N_130
+11 1
+.names a_c_20__n.BLIF a_c_21__n.BLIF N_170_1
+11 1
+.names N_131_1.BLIF cpu_est_i_2__n.BLIF N_131
+11 1
+.names a_c_22__n.BLIF a_c_23__n.BLIF N_170_2
+11 1
+.names N_124_i.BLIF N_124
+0 1
.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1
11 1
-.names CLK_000_D_i.BLIF N_94.BLIF N_108
-11 1
+.names N_125_i.BLIF N_125
+0 1
.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2
11 1
-.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_109
+.names N_134_1.BLIF cpu_est_i_2__n.BLIF N_134
11 1
.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \
UDS_000_INT_0_sqmuxa_1_3
11 1
-.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_106
+.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_134_1
+11 1
+.names inst_CLK_000_D0.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0
+11 1
+.names N_106_1.BLIF state_machine_un60_clk_000_d0_n.BLIF N_106
+11 1
+.names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2
+11 1
+.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n
+0 1
+.names size_c_i_1__n.BLIF a_c_i_0__n.BLIF state_machine_un34_clk_000_d0_i_1_n
+11 1
+.names N_125.BLIF cpu_est_3_reg.BLIF N_132
+11 1
+.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n
+11 1
+.names N_125_i.BLIF cpu_est_i_2__n.BLIF N_133
+11 1
+.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n
+11 1
+.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n
+0 1
+.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n
+11 1
+.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_127
+11 1
+.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF \
+state_machine_un42_clk_030_4_n
+11 1
+.names N_124.BLIF cpu_est_i_0__n.BLIF N_126
+11 1
+.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF \
+state_machine_un42_clk_030_5_n
+11 1
+.names N_124_i.BLIF cpu_est_0_.BLIF N_128
11 1
.names DTACK_i.BLIF inst_VPA_D.BLIF DTACK_SYNC_1_sqmuxa_1_0
11 1
-.names inst_CLK_000_D.BLIF SM_AMIGA_5_.BLIF N_101
+.names N_93_0.BLIF N_93
+0 1
+.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_130_1
11 1
-.names state_machine_un8_clk_000_d_1_n.BLIF VPA_D_i.BLIF \
-state_machine_un8_clk_000_d_1_0_n
+.names N_90_i.BLIF N_90
+0 1
+.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_131_1
11 1
-.names N_91.BLIF sm_amiga_i_7__n.BLIF N_99
+.names N_90.BLIF SM_AMIGA_1_.BLIF N_107
11 1
-.names cpu_est_2_.BLIF cpu_est_i_1__n.BLIF state_machine_un8_clk_000_d_2_n
+.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF \
+state_machine_un8_clk_000_d0_1_n
11 1
-.names AS_030_i.BLIF N_102_i.BLIF AS_000_INT_1_sqmuxa
+.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_108
11 1
-.names state_machine_un8_clk_000_d_1_0_n.BLIF \
-state_machine_un8_clk_000_d_2_n.BLIF state_machine_un8_clk_000_d_3_n
+.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d0_2_n
+11 1
+.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_105
+11 1
+.names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d0_3_n
+11 1
+.names CLK_000_D0_i.BLIF N_93.BLIF N_103
+11 1
+.names state_machine_un8_clk_000_d0_1_n.BLIF \
+state_machine_un8_clk_000_d0_2_n.BLIF state_machine_un8_clk_000_d0_4_n
+11 1
+.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_104
+11 1
+.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF \
+state_machine_un13_clk_000_d0_1_0_n
+11 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF N_100
+11 1
+.names state_machine_un13_clk_000_d0_1_n.BLIF \
+state_machine_un13_clk_000_d0_2_n.BLIF state_machine_un13_clk_000_d0_2_0_n
+11 1
+.names AS_030_i.BLIF N_101_i.BLIF AS_000_INT_1_sqmuxa
+11 1
+.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1
11 1
.names RW_c.BLIF RW_i
0 1
-.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF \
-state_machine_un13_clk_000_d_1_0_n
+.names N_134_1.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_2
11 1
-.names N_102.BLIF N_102_i
-0 1
-.names state_machine_un13_clk_000_d_1_n.BLIF \
-state_machine_un13_clk_000_d_2_n.BLIF state_machine_un13_clk_000_d_2_0_n
-11 1
-.names inst_AS_000_INTreg.BLIF AS_000_INT_i
-0 1
-.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1
-11 1
-.names dsack_c_1__n.BLIF dsack_i_1__n
-0 1
-.names N_135_1.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_2
-11 1
-.names AS_030_c.BLIF AS_030_i
+.names nEXP_SPACE_c.BLIF nEXP_SPACE_i
0 1
.names VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_3
11 1
-.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
+.names N_101.BLIF N_101_i
0 1
.names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_4
11 1
-.names inst_CLK_000_D.BLIF CLK_000_D_i
+.names inst_AS_000_INTreg.BLIF AS_000_INT_i
0 1
-.names CLK_000_D_i.BLIF SM_AMIGA_3_.BLIF N_107_1
+.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_106_1
11 1
-.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n
+.names dsack_c_1__n.BLIF dsack_i_1__n
0 1
-.names CLK_000_D_i.BLIF inst_CLK_OUT_PRE.BLIF N_98_1
+.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un3_n
+0 1
+.names AS_030_c.BLIF AS_030_i
+0 1
+.names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un1_n
11 1
-.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
+.names inst_CLK_000_D0.BLIF CLK_000_D0_i
0 1
-.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n
-0 1
-.names state_machine_un13_clk_000_d_1_n.BLIF \
-state_machine_un13_clk_000_d_1_i_n
-0 1
-.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n
-11 1
-.names inst_VPA_D.BLIF VPA_D_i
-0 1
-.names N_102_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
-11 1
-.names inst_VMA_INTreg.BLIF VMA_INT_i
-0 1
-.names state_machine_un15_clk_000_d_n.BLIF vma_int_0_un3_n
-0 1
-.names cpu_est_0_.BLIF cpu_est_i_0__n
-0 1
-.names state_machine_un8_clk_000_d_1_i_0_n.BLIF \
-state_machine_un15_clk_000_d_n.BLIF vma_int_0_un1_n
-11 1
-.names cpu_est_1_.BLIF cpu_est_i_1__n
-0 1
-.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
-11 1
-.names cpu_est_3_reg.BLIF cpu_est_i_3__n
-0 1
-.names un1_as_030_4.BLIF uds_000_int_0_un3_n
-0 1
-.names state_machine_un8_clk_000_d_1_n.BLIF \
-state_machine_un8_clk_000_d_1_i_0_n
-0 1
-.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n
-11 1
-.names DTACK_c.BLIF DTACK_i
-0 1
-.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF \
-uds_000_int_0_un0_n
+.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n
11 1
.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n
0 1
-.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n
+.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un3_n
0 1
.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
0 1
-.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n
+.names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un1_n
11 1
-.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
+.names inst_CLK_000_D1.BLIF CLK_000_D1_i
0 1
-.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n
+.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n
11 1
-.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i
+.names cpu_est_0_.BLIF cpu_est_i_0__n
0 1
-.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n
+.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n
0 1
-.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i
+.names cpu_est_3_reg.BLIF cpu_est_i_3__n
0 1
-.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n
+.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n
11 1
-.names N_98.BLIF N_98_i
+.names cpu_est_2_.BLIF cpu_est_i_2__n
0 1
-.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n
+.names N_101_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
11 1
-.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n
+.names inst_VPA_D.BLIF VPA_D_i
0 1
-.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n
+.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n
0 1
-.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i
+.names inst_VMA_INTreg.BLIF VMA_INT_i
0 1
-.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n
+.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n
11 1
-.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i
+.names cpu_est_1_.BLIF cpu_est_i_1__n
0 1
-.names N_98_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n
+.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
11 1
-.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
+.names state_machine_un13_clk_000_d0_2_n.BLIF \
+state_machine_un13_clk_000_d0_2_i_n
0 1
.names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n
0 1
-.names DS_030_c.BLIF DS_030_i
+.names state_machine_un13_clk_000_d0_1_n.BLIF \
+state_machine_un13_clk_000_d0_1_i_n
0 1
.names state_machine_as_030_000_sync_3_n.BLIF \
state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n
11 1
-.names cpu_est_2_.BLIF cpu_est_i_2__n
+.names DTACK_c.BLIF DTACK_i
0 1
.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \
as_030_000_sync_0_un0_n
11 1
-.names state_machine_un13_clk_000_d_2_n.BLIF \
-state_machine_un13_clk_000_d_2_i_n
+.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i
0 1
.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n
0 1
-.names inst_CLK_000_DD.BLIF CLK_000_DD_i
+.names a_c_18__n.BLIF a_i_18__n
0 1
.names un1_as_030_3.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n
11 1
-.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
+.names a_c_16__n.BLIF a_i_16__n
0 1
.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n
11 1
+.names a_c_19__n.BLIF a_i_19__n
+0 1
+.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n
+0 1
.names CLK_030_c.BLIF CLK_030_i
0 1
-.names un1_as_030_4.BLIF lds_000_int_0_un3_n
-0 1
-.names a_c_30__n.BLIF a_i_30__n
-0 1
-.names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n
+.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n
11 1
-.names a_c_31__n.BLIF a_i_31__n
+.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n
0 1
-.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF \
-lds_000_int_0_un0_n
+.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n
11 1
-.names a_c_28__n.BLIF a_i_28__n
+.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
0 1
-.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_3__un3_n
+.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n
0 1
-.names a_c_29__n.BLIF a_i_29__n
+.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
0 1
-.names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_3__un1_n
+.names N_124.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n
11 1
-.names a_c_26__n.BLIF a_i_26__n
+.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
0 1
-.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n
+.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
11 1
-.names a_c_27__n.BLIF a_i_27__n
+.names DS_030_c.BLIF DS_030_i
0 1
-.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_2__un3_n
+.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un3_n
0 1
-.names a_c_24__n.BLIF a_i_24__n
+.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i
0 1
-.names N_122_i.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_2__un1_n
+.names N_121_i.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un1_n
11 1
-.names a_c_25__n.BLIF a_i_25__n
+.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i
0 1
.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n
11 1
-.names a_c_19__n.BLIF a_i_19__n
+.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
0 1
-.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n
+.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un3_n
0 1
-.names a_c_16__n.BLIF a_i_16__n
+.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i
0 1
-.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n
+.names ipl_c_0__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un1_n
11 1
-.names a_c_18__n.BLIF a_i_18__n
+.names N_97.BLIF N_97_i
0 1
-.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
+.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
11 1
+.names a_c_30__n.BLIF a_i_30__n
+0 1
+.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un3_n
+0 1
+.names a_c_31__n.BLIF a_i_31__n
+0 1
+.names ipl_c_1__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un1_n
+11 1
+.names a_c_28__n.BLIF a_i_28__n
+0 1
+.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
+11 1
+.names a_c_29__n.BLIF a_i_29__n
+0 1
+.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un3_n
+0 1
+.names a_c_26__n.BLIF a_i_26__n
+0 1
+.names ipl_c_2__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un1_n
+11 1
+.names a_c_27__n.BLIF a_i_27__n
+0 1
+.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
+11 1
+.names a_c_24__n.BLIF a_i_24__n
+0 1
.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n
0 1
-.names RST_c.BLIF RST_i
+.names a_c_25__n.BLIF a_i_25__n
0 1
.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \
bgack_030_int_0_un1_n
@@ -882,37 +867,39 @@ bgack_030_int_0_un1_n
.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \
bgack_030_int_0_un0_n
11 1
+.names RST_c.BLIF RST_i
+0 1
+.names un1_as_030_4.BLIF uds_000_int_0_un3_n
+0 1
+.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n
+11 1
.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i
0 1
-.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_1__un3_n
-0 1
-.names CPU_SPACE_c.BLIF CPU_SPACE_i
-0 1
-.names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_1__un1_n
+.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF \
+uds_000_int_0_un0_n
11 1
.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
0 1
-.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n
-11 1
-.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_0__un3_n
+.names un1_as_030_4.BLIF lds_000_int_0_un3_n
0 1
-.names ipl_c_0__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_0__un1_n
+.names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n
11 1
-.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
+.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF \
+lds_000_int_0_un0_n
11 1
-.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_1__un3_n
+.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n
0 1
-.names ipl_c_1__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_1__un1_n
+.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n
11 1
-.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
+.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n
11 1
-.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_2__un3_n
+.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n
0 1
-.names ipl_c_2__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_2__un1_n
+.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n
11 1
-.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
+.names N_97_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n
11 1
-.names cpu_est_0_.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_0_
+.names cpu_est_0_.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_0_
01 1
10 1
11 0
@@ -967,7 +954,7 @@ bgack_030_int_0_un0_n
.names RESETDFFreg.BLIF RESET
1 1
0 0
-.names gnd_n_n.BLIF AMIGA_BUS_ENABLE
+.names nEXP_SPACE_i.BLIF AMIGA_BUS_ENABLE
1 1
0 0
.names RW_i.BLIF AMIGA_BUS_DATA_DIR
@@ -976,7 +963,7 @@ bgack_030_int_0_un0_n
.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW
1 1
0 0
-.names N_171.BLIF CIIN
+.names N_170.BLIF CIIN
1 1
0 0
.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
@@ -1153,10 +1140,10 @@ bgack_030_int_0_un0_n
.names CLK_OSZI_c.BLIF inst_VPA_D.C
1 1
0 0
-.names CLK_000.BLIF inst_CLK_000_D.D
+.names CLK_000.BLIF inst_CLK_000_D0.D
1 1
0 0
-.names CLK_OSZI_c.BLIF inst_CLK_000_D.C
+.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C
1 1
0 0
.names RST_c.BLIF RESETDFFreg.D
@@ -1165,10 +1152,10 @@ bgack_030_int_0_un0_n
.names CLK_OSZI_c.BLIF RESETDFFreg.C
1 1
0 0
-.names inst_CLK_000_D.BLIF inst_CLK_000_DD.D
+.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
-.names CLK_OSZI_c.BLIF inst_CLK_000_DD.C
+.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C
1 1
0 0
.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D
@@ -1222,18 +1209,18 @@ bgack_030_int_0_un0_n
.names SIZE_0_.BLIF size_c_0__n
1 1
0 0
-.names SIZE_1_.BLIF size_c_1__n
-1 1
-0 0
.names A_15_.BLIF a_15__n
1 1
0 0
-.names A_0_.BLIF a_c_0__n
+.names SIZE_1_.BLIF size_c_1__n
1 1
0 0
.names A_14_.BLIF a_14__n
1 1
0 0
+.names A_0_.BLIF a_c_0__n
+1 1
+0 0
.names A_13_.BLIF a_13__n
1 1
0 0
@@ -1321,7 +1308,7 @@ bgack_030_int_0_un0_n
.names A_31_.BLIF a_c_31__n
1 1
0 0
-.names CPU_SPACE.BLIF CPU_SPACE_c
+.names nEXP_SPACE.BLIF nEXP_SPACE_c
1 1
0 0
.names BG_030.BLIF BG_030_c
@@ -1336,7 +1323,7 @@ bgack_030_int_0_un0_n
.names CLK_OSZI.BLIF CLK_OSZI_c
1 1
0 0
-.names CPU_SPACE_i.BLIF DSACK_1_.OE
+.names nEXP_SPACE_c.BLIF DSACK_1_.OE
1 1
0 0
.names BGACK_030_INT_i.BLIF DTACK.OE
@@ -1354,13 +1341,13 @@ bgack_030_int_0_un0_n
.names FPU_CS_INT_i.BLIF BERR.OE
1 1
0 0
-.names CPU_SPACE_i.BLIF DSACK_0_.OE
+.names nEXP_SPACE_c.BLIF DSACK_0_.OE
1 1
0 0
.names FPU_CS_INT_i.BLIF AVEC_EXP.OE
1 1
0 0
-.names N_168.BLIF CIIN.OE
+.names N_167.BLIF CIIN.OE
1 1
0 0
.end
diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3
index 509350c..9005ab2 100644
--- a/Logic/68030_tk.bl3
+++ b/Logic/68030_tk.bl3
@@ -1,36 +1,37 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
-#$ DATE Thu May 15 23:02:46 2014
+#$ DATE Fri May 16 17:07:08 2014
#$ MODULE 68030_tk
-#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ IPL_2_ DSACK_1_ \
-# FC_1_ AS_030 AS_000 DS_030 UDS_000 LDS_000 CPU_SPACE BERR BG_030 BG_000 A_0_ BGACK_030 \
-# IPL_030_1_ BGACK_000 IPL_030_0_ CLK_030 IPL_1_ CLK_000 IPL_0_ CLK_OSZI DSACK_0_ \
-# CLK_DIV_OUT FC_0_ CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW \
-# AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \
-# A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
-#$ NODES 34 IPL_030DFFSH_1_reg IPL_030DFFSH_2_reg inst_BGACK_030_INTreg \
-# inst_FPU_CS_INTreg cpu_est_3_reg inst_VMA_INTreg cpu_est_0_ cpu_est_1_ \
-# inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC \
-# inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_2_ RESETDFFreg CLK_CNT_0_ \
-# SM_AMIGA_6_ SM_AMIGA_7_ inst_UDS_000_INTreg inst_LDS_000_INTreg SM_AMIGA_1_ \
-# DSACK_INT_1_ inst_DTACK_DMA SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ \
-# SM_AMIGA_0_ BG_000DFFSHreg CLK_OUT_INTreg IPL_030DFFSH_0_reg
+#$ PINS 59 A_17_ A_16_ SIZE_1_ A_31_ IPL_030_2_ IPL_2_ DSACK_1_ FC_1_ AS_030 AS_000 \
+# DS_030 UDS_000 LDS_000 A_0_ nEXP_SPACE IPL_030_1_ BERR IPL_030_0_ BG_030 IPL_1_ BG_000 \
+# IPL_0_ BGACK_030 DSACK_0_ BGACK_000 FC_0_ CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP \
+# FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
+# AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ \
+# A_21_ A_20_ A_19_ A_18_
+#$ NODES 34 inst_BGACK_030_INTreg inst_FPU_CS_INTreg cpu_est_3_reg \
+# inst_VMA_INTreg cpu_est_0_ cpu_est_1_ inst_AS_000_INTreg inst_AS_030_000_SYNC \
+# inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 \
+# inst_CLK_OUT_PRE RESETDFFreg cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ \
+# inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ SM_AMIGA_1_ inst_DTACK_DMA \
+# SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_ BG_000DFFSHreg \
+# CLK_OUT_INTreg IPL_030DFFSH_0_reg IPL_030DFFSH_1_reg IPL_030DFFSH_2_reg
.model bus68030
.inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \
-CPU_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \
+nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \
CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \
A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \
A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_0_.BLIF \
-IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF IPL_030DFFSH_1_reg.BLIF \
-IPL_030DFFSH_2_reg.BLIF inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF \
-cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
-inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF \
-inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \
-inst_CLK_OUT_PRE.BLIF cpu_est_2_.BLIF RESETDFFreg.BLIF CLK_CNT_0_.BLIF \
+IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF inst_BGACK_030_INTreg.BLIF \
+inst_FPU_CS_INTreg.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF \
+cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INTreg.BLIF \
+inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF \
+inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
+inst_CLK_OUT_PRE.BLIF RESETDFFreg.BLIF cpu_est_2_.BLIF CLK_CNT_0_.BLIF \
SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF \
-inst_LDS_000_INTreg.BLIF SM_AMIGA_1_.BLIF DSACK_INT_1_.BLIF \
+inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF SM_AMIGA_1_.BLIF \
inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_5_.BLIF \
SM_AMIGA_2_.BLIF SM_AMIGA_0_.BLIF BG_000DFFSHreg.BLIF CLK_OUT_INTreg.BLIF \
-IPL_030DFFSH_0_reg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF
+IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_2_reg.BLIF \
+DSACK_1_.PIN.BLIF DTACK.PIN.BLIF
.outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \
CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_3_.D SM_AMIGA_3_.C \
@@ -54,12 +55,12 @@ inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000DFFSHreg.D \
BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DTACK_DMA.D inst_DTACK_DMA.C \
inst_DTACK_DMA.AP inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C \
inst_UDS_000_INTreg.AP CLK_CNT_0_.D CLK_CNT_0_.C inst_VPA_D.D inst_VPA_D.C \
-inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D RESETDFFreg.C \
-inst_CLK_000_DD.D inst_CLK_000_DD.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C DSACK_1_ \
+inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D RESETDFFreg.C \
+inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_OUT_INTreg.D CLK_OUT_INTreg.C DSACK_1_ \
DTACK DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE \
DSACK_0_.OE AVEC_EXP.OE CIIN.OE cpu_est_3_reg.D.X1 cpu_est_3_reg.D.X2 \
inst_VMA_INTreg.D.X1 inst_VMA_INTreg.D.X2
-.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF \
+.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \
SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D
--11- 1
11--1 1
@@ -68,7 +69,7 @@ SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D
0-0-- 0
---00 0
--0-0 0
-.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF \
+.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \
SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_2_.D
-001- 1
0-01- 1
@@ -76,24 +77,27 @@ SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_2_.D
11--0 0
--1-- 0
---00 0
-.names inst_CLK_000_D.BLIF inst_CLK_OUT_PRE.BLIF SM_AMIGA_1_.BLIF \
-SM_AMIGA_2_.BLIF SM_AMIGA_1_.D
--010 1
-1-1- 1
-1--1 1
-01-- 0
---00 0
-0--1 0
-.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF inst_CLK_OUT_PRE.BLIF \
-SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D
--011- 1
-0---1 1
--0--1 1
-11--- 0
+.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF inst_CLK_OUT_PRE.BLIF \
+SM_AMIGA_1_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_1_.D
+--01- 1
+-1-1- 1
+1---1 1
+001-- 0
+-01-0 0
+0--0- 0
---00 0
---0-0 0
--1--0 0
-.names IPL_0_.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \
+.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
+inst_CLK_OUT_PRE.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_0_.D
+--011- 1
+-0---1 1
+0----1 1
+11--0- 0
+11-0-- 0
+111--- 0
+----00 0
+---0-0 0
+--1--0 0
+.names IPL_0_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_0_reg.D
110- 1
--11 1
@@ -101,30 +105,30 @@ IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_0_reg.D
010- 0
--10 0
-0-0 0
-.names IPL_1_.BLIF IPL_030DFFSH_1_reg.BLIF inst_CLK_000_D.BLIF \
-inst_CLK_000_DD.BLIF IPL_030DFFSH_1_reg.D
-1-10 1
--10- 1
--1-1 1
-0-10 0
--00- 0
--0-1 0
-.names IPL_2_.BLIF IPL_030DFFSH_2_reg.BLIF inst_CLK_000_D.BLIF \
-inst_CLK_000_DD.BLIF IPL_030DFFSH_2_reg.D
-1-10 1
--10- 1
--1-1 1
-0-10 0
--00- 0
--0-1 0
-.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF SM_AMIGA_7_.BLIF \
+.names IPL_1_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
+IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_1_reg.D
+110- 1
+--11 1
+-0-1 1
+010- 0
+--10 0
+-0-0 0
+.names IPL_2_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
+IPL_030DFFSH_2_reg.BLIF IPL_030DFFSH_2_reg.D
+110- 1
+--11 1
+-0-1 1
+010- 0
+--10 0
+-0-0 0
+.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF SM_AMIGA_7_.BLIF \
SM_AMIGA_0_.BLIF SM_AMIGA_7_.D
-11- 1
11-1 1
0-0- 0
--00 0
-0-- 0
-.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \
+.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.D
--11- 1
-0-1- 1
@@ -133,7 +137,7 @@ SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF SM_AMIGA_6_.D
010-- 0
-1-0- 0
---00 0
-.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \
+.names inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_5_.D
0101- 1
-1--1 1
@@ -141,30 +145,30 @@ SM_AMIGA_6_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_5_.D
---00 0
--1-0 0
1---0 0
-.names inst_CLK_000_D.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.D
+.names inst_CLK_000_D0.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_5_.BLIF SM_AMIGA_4_.D
01- 1
0-1 1
-00 0
1-- 0
-.names AS_030.BLIF inst_CLK_000_D.BLIF inst_CLK_OUT_PRE.BLIF SM_AMIGA_1_.BLIF \
-DSACK_INT_1_.BLIF DSACK_INT_1_.D
-1--0- 1
+.names AS_030.BLIF inst_CLK_000_D1.BLIF inst_CLK_OUT_PRE.BLIF \
+DSACK_INT_1_.BLIF SM_AMIGA_1_.BLIF DSACK_INT_1_.D
+--01- 1
+-1-1- 1
+---10 1
1-0-- 1
11--- 1
----01 1
---0-1 1
--1--1 1
--011- 0
-0---0 0
-.names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D.BLIF \
-inst_CLK_000_DD.BLIF inst_BGACK_030_INTreg.D
+1---0 1
+-01-1 0
+0--0- 0
+.names BGACK_000.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_D0.BLIF \
+inst_CLK_000_D1.BLIF inst_BGACK_030_INTreg.D
1-10 1
11-- 1
-00- 0
0--- 0
-0-1 0
-.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \
-inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_1_.D
+.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D0.BLIF \
+inst_CLK_000_D1.BLIF cpu_est_2_.BLIF cpu_est_1_.D
0--100 1
01010- 1
10-10- 1
@@ -178,8 +182,8 @@ inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_1_.D
110--- 0
--0-1- 0
--00-- 0
-.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \
-inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_2_.D
+.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D0.BLIF \
+inst_CLK_000_D1.BLIF cpu_est_2_.BLIF cpu_est_2_.D
-0010- 1
11-10- 1
--1--1 1
@@ -191,7 +195,7 @@ inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_2_.D
----10 0
---0-0 0
.names SIZE_1_.BLIF AS_030.BLIF DS_030.BLIF RW.BLIF SIZE_0_.BLIF A_0_.BLIF \
-inst_AS_030_000_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \
+inst_AS_030_000_SYNC.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF \
SM_AMIGA_6_.BLIF inst_LDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF \
inst_LDS_000_INTreg.D
0-01100101-- 1
@@ -220,7 +224,7 @@ inst_LDS_000_INTreg.D
-0-----0--0- 0
-01-------0- 0
-0-0------00 0
-.names AS_030.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_CLK_000_D.BLIF \
+.names AS_030.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF \
SM_AMIGA_3_.BLIF DTACK.PIN.BLIF inst_DTACK_SYNC.D
-1--0- 1
-1-0-- 1
@@ -246,23 +250,24 @@ inst_FPU_CS_INTreg.D
-1-------- 1
101100101- 0
-0-0-----0 0
-.names FC_1_.BLIF AS_030.BLIF CPU_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF \
+.names FC_1_.BLIF AS_030.BLIF nEXP_SPACE.BLIF BGACK_000.BLIF CLK_030.BLIF \
A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF FC_0_.BLIF \
inst_AS_030_000_SYNC.BLIF inst_AS_030_000_SYNC.D
1--1100101- 1
----0-----1 1
---1-1------ 1
+--0-1------ 1
-1--------- 1
--00-1----0- 0
--00-1---1-- 0
--00-1--0--- 0
--00-1-1---- 0
--00-11----- 0
--0001------ 0
-000-1------ 0
+-01-1----0- 0
+-01-1---1-- 0
+-01-1--0--- 0
+-01-1-1---- 0
+-01-11----- 0
+-0101------ 0
+001-1------ 0
-0--0-----0 0
.names AS_030.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \
-inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INTreg.D
+inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF SM_AMIGA_6_.BLIF \
+inst_AS_000_INTreg.D
-1--1- 1
-1-0-- 1
-11--- 1
@@ -274,7 +279,7 @@ inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF inst_AS_000_INTreg.D
--0101 0
00---- 0
.names AS_030.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF \
-cpu_est_1_.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF \
+cpu_est_1_.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \
cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_VPA_SYNC.D
------1-0- 1
------10-- 1
@@ -294,7 +299,7 @@ cpu_est_2_.BLIF SM_AMIGA_3_.BLIF inst_VPA_SYNC.D
1--------0 1
-10000-111 0
0-----0--- 0
-.names AS_030.BLIF CPU_SPACE.BLIF BG_030.BLIF CLK_030.BLIF SM_AMIGA_6_.BLIF \
+.names AS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF CLK_030.BLIF SM_AMIGA_6_.BLIF \
SM_AMIGA_7_.BLIF BG_000DFFSHreg.BLIF BG_000DFFSHreg.D
---000- 1
---1--1 1
@@ -309,7 +314,7 @@ SM_AMIGA_7_.BLIF BG_000DFFSHreg.BLIF BG_000DFFSHreg.D
-1 1
00 0
.names AS_030.BLIF DS_030.BLIF RW.BLIF A_0_.BLIF inst_AS_030_000_SYNC.BLIF \
-inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF SM_AMIGA_6_.BLIF \
+inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF SM_AMIGA_6_.BLIF \
inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D
-0110101-- 1
-001-1---1 1
@@ -378,8 +383,9 @@ inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D
.names RESETDFFreg.BLIF RESET
1 1
0 0
-.names AMIGA_BUS_ENABLE
- 0
+.names nEXP_SPACE.BLIF AMIGA_BUS_ENABLE
+0 1
+1 0
.names RW.BLIF AMIGA_BUS_DATA_DIR
0 1
1 0
@@ -489,7 +495,7 @@ inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D
.names CLK_OSZI.BLIF inst_CLK_OUT_PRE.C
1 1
0 0
-.names cpu_est_0_.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF cpu_est_0_.D
+.names cpu_est_0_.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_D1.BLIF cpu_est_0_.D
010 1
10- 1
1-1 1
@@ -571,10 +577,10 @@ inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D
.names CLK_OSZI.BLIF inst_VPA_D.C
1 1
0 0
-.names CLK_000.BLIF inst_CLK_000_D.D
+.names CLK_000.BLIF inst_CLK_000_D0.D
1 1
0 0
-.names CLK_OSZI.BLIF inst_CLK_000_D.C
+.names CLK_OSZI.BLIF inst_CLK_000_D0.C
1 1
0 0
.names RST.BLIF RESETDFFreg.D
@@ -583,10 +589,10 @@ inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D
.names CLK_OSZI.BLIF RESETDFFreg.C
1 1
0 0
-.names inst_CLK_000_D.BLIF inst_CLK_000_DD.D
+.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
-.names CLK_OSZI.BLIF inst_CLK_000_DD.C
+.names CLK_OSZI.BLIF inst_CLK_000_D1.C
1 1
0 0
.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D
@@ -603,9 +609,9 @@ inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D
0 0
.names DSACK_0_
1
-.names CPU_SPACE.BLIF DSACK_1_.OE
-0 1
-1 0
+.names nEXP_SPACE.BLIF DSACK_1_.OE
+1 1
+0 0
.names inst_BGACK_030_INTreg.BLIF DTACK.OE
0 1
1 0
@@ -621,9 +627,9 @@ inst_UDS_000_INTreg.BLIF SM_AMIGA_4_.BLIF inst_UDS_000_INTreg.D
.names inst_FPU_CS_INTreg.BLIF BERR.OE
0 1
1 0
-.names CPU_SPACE.BLIF DSACK_0_.OE
-0 1
-1 0
+.names nEXP_SPACE.BLIF DSACK_0_.OE
+1 1
+0 0
.names inst_FPU_CS_INTreg.BLIF AVEC_EXP.OE
0 1
1 0
@@ -642,8 +648,8 @@ A_25_.BLIF A_24_.BLIF CIIN.OE
11 1
0- 0
-0 0
-.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D.BLIF \
-inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_3_reg.D.X2
+.names cpu_est_3_reg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_CLK_000_D0.BLIF \
+inst_CLK_000_D1.BLIF cpu_est_2_.BLIF cpu_est_3_reg.D.X2
10---- 1
-00100 1
011100 1
@@ -661,7 +667,7 @@ inst_CLK_000_DD.BLIF cpu_est_2_.BLIF cpu_est_3_reg.D.X2
1- 0
-0 0
.names cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
-inst_AS_000_INTreg.BLIF inst_VPA_D.BLIF inst_CLK_000_D.BLIF cpu_est_2_.BLIF \
+inst_AS_000_INTreg.BLIF inst_VPA_D.BLIF inst_CLK_000_D0.BLIF cpu_est_2_.BLIF \
inst_VMA_INTreg.D.X2
00011-11 1
-110-001 1
diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf
index a40f593..461dc97 100644
--- a/Logic/68030_tk.crf
+++ b/Logic/68030_tk.crf
@@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 1.7.00.05.28.13
-// Design '68030_tk' created Thu May 15 23:02:46 2014
+// Design '68030_tk' created Fri May 16 17:07:08 2014
// LEGEND: '>' Functional Block Port Separator
diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3
index 21108f8..fa45602 100644
--- a/Logic/68030_tk.eq3
+++ b/Logic/68030_tk.eq3
@@ -2,7 +2,7 @@
Copyright(C), 1992-2013, Lattice Semiconductor Corp.
All Rights Reserved.
-Design bus68030 created Thu May 15 23:02:46 2014
+Design bus68030 created Fri May 16 17:07:08 2014
P-Terms Fan-in Fan-out Type Name (attributes)
@@ -16,7 +16,7 @@ Design bus68030 created Thu May 15 23:02:46 2014
1 0 1 Pin AVEC
0 0 1 Pin AVEC_EXP
1 1 1 Pin AVEC_EXP.OE
- 0 0 1 Pin AMIGA_BUS_ENABLE
+ 1 1 1 Pin AMIGA_BUS_ENABLE
1 1 1 Pin AMIGA_BUS_DATA_DIR
1 0 1 Pin AMIGA_BUS_ENABLE_LOW
1 4 1 Pin CIIN
@@ -40,18 +40,18 @@ Design bus68030 created Thu May 15 23:02:46 2014
12 12 1 Pin LDS_000.D-
1 1 1 Pin LDS_000.AP
1 1 1 Pin LDS_000.C
- 3 7 1 Pin BG_000.D-
- 1 1 1 Pin BG_000.AP
- 1 1 1 Pin BG_000.C
- 2 4 1 Pin BGACK_030.D
- 1 1 1 Pin BGACK_030.AP
- 1 1 1 Pin BGACK_030.C
3 4 1 Pin IPL_030_1_.D
1 1 1 Pin IPL_030_1_.AP
1 1 1 Pin IPL_030_1_.C
3 4 1 Pin IPL_030_0_.D
1 1 1 Pin IPL_030_0_.AP
1 1 1 Pin IPL_030_0_.C
+ 3 7 1 Pin BG_000.D-
+ 1 1 1 Pin BG_000.AP
+ 1 1 1 Pin BG_000.C
+ 2 4 1 Pin BGACK_030.D
+ 1 1 1 Pin BGACK_030.AP
+ 1 1 1 Pin BGACK_030.C
1 1 1 Pin CLK_EXP.D
1 1 1 Pin CLK_EXP.C
2 10 1 Pin FPU_CS.D-
@@ -83,10 +83,10 @@ Design bus68030 created Thu May 15 23:02:46 2014
2 10 1 Node inst_VPA_SYNC.D-
1 1 1 Node inst_VPA_SYNC.AP
1 1 1 Node inst_VPA_SYNC.C
- 1 1 1 Node inst_CLK_000_D.D
- 1 1 1 Node inst_CLK_000_D.C
- 1 1 1 Node inst_CLK_000_DD.D
- 1 1 1 Node inst_CLK_000_DD.C
+ 1 1 1 Node inst_CLK_000_D0.D
+ 1 1 1 Node inst_CLK_000_D0.C
+ 1 1 1 Node inst_CLK_000_D1.D
+ 1 1 1 Node inst_CLK_000_D1.C
2 2 1 Node inst_CLK_OUT_PRE.D
1 1 1 Node inst_CLK_OUT_PRE.C
3 6 1 NodeX1 cpu_est_2_.D.X1
@@ -101,7 +101,7 @@ Design bus68030 created Thu May 15 23:02:46 2014
1 1 1 Node SM_AMIGA_7_.AP
1 1 1 Node SM_AMIGA_7_.C
1 1 1 Node SM_AMIGA_1_.AR
- 3 4 1 Node SM_AMIGA_1_.D
+ 3 5 1 Node SM_AMIGA_1_.D
1 1 1 Node SM_AMIGA_1_.C
1 1 1 Node SM_AMIGA_4_.AR
2 3 1 Node SM_AMIGA_4_.D
@@ -116,10 +116,10 @@ Design bus68030 created Thu May 15 23:02:46 2014
3 5 1 Node SM_AMIGA_2_.D
1 1 1 Node SM_AMIGA_2_.C
1 1 1 Node SM_AMIGA_0_.AR
- 3 5 1 Node SM_AMIGA_0_.D
+ 3 6 1 Node SM_AMIGA_0_.D
1 1 1 Node SM_AMIGA_0_.C
=========
- 167 P-Term Total: 167
+ 168 P-Term Total: 168
Total Pins: 59
Total Nodes: 19
Average P-Term/Output: 2
@@ -133,7 +133,7 @@ BERR.OE = (!FPU_CS.Q);
DSACK_0_ = (1);
-DSACK_0_.OE = (!CPU_SPACE);
+DSACK_0_.OE = (nEXP_SPACE);
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE.Q);
@@ -145,7 +145,7 @@ AVEC_EXP = (0);
AVEC_EXP.OE = (!FPU_CS.Q);
-AMIGA_BUS_ENABLE = (0);
+AMIGA_BUS_ENABLE = (!nEXP_SPACE);
AMIGA_BUS_DATA_DIR = (!RW);
@@ -155,18 +155,18 @@ CIIN = (A_23_ & A_22_ & A_21_ & A_20_);
CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_);
-IPL_030_2_.D = (IPL_030_2_.Q & !inst_CLK_000_D.Q
- # IPL_030_2_.Q & inst_CLK_000_DD.Q
- # IPL_2_ & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q);
+IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q
+ # inst_CLK_000_D1.Q & IPL_030_2_.Q
+ # IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
IPL_030_2_.AP = (!RST);
IPL_030_2_.C = (CLK_OSZI);
-DSACK_1_.OE = (!CPU_SPACE);
+DSACK_1_.OE = (nEXP_SPACE);
!DSACK_1_.D = (!AS_030 & !DSACK_1_.Q
- # !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q);
+ # !inst_CLK_000_D1.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q);
DSACK_1_.AP = (!RST);
@@ -175,7 +175,7 @@ DSACK_1_.C = (CLK_OSZI);
AS_000.OE = (BGACK_030.Q);
!AS_000.D = (!AS_030 & !AS_000.Q
- # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q);
+ # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & SM_AMIGA_6_.Q);
AS_000.AP = (!RST);
@@ -184,13 +184,13 @@ AS_000.C = (CLK_OSZI);
UDS_000.OE = (BGACK_030.Q);
!UDS_000.D = (!AS_030 & DS_030 & !UDS_000.Q
- # !AS_030 & !inst_CLK_000_D.Q & !UDS_000.Q
+ # !AS_030 & !inst_CLK_000_D0.Q & !UDS_000.Q
# !AS_030 & RW & inst_AS_030_000_SYNC.Q & !UDS_000.Q
- # !AS_030 & RW & inst_CLK_000_DD.Q & !UDS_000.Q
+ # !AS_030 & RW & inst_CLK_000_D1.Q & !UDS_000.Q
# !AS_030 & RW & !SM_AMIGA_6_.Q & !UDS_000.Q
# !AS_030 & !RW & !UDS_000.Q & !SM_AMIGA_4_.Q
- # !DS_030 & !RW & !A_0_ & inst_CLK_000_D.Q & SM_AMIGA_4_.Q
- # !DS_030 & RW & !A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q);
+ # !DS_030 & !RW & !A_0_ & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q
+ # !DS_030 & RW & !A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & SM_AMIGA_6_.Q);
UDS_000.AP = (!RST);
@@ -199,53 +199,53 @@ UDS_000.C = (CLK_OSZI);
LDS_000.OE = (BGACK_030.Q);
!LDS_000.D = (!AS_030 & DS_030 & !LDS_000.Q
- # !AS_030 & !inst_CLK_000_D.Q & !LDS_000.Q
+ # !AS_030 & !inst_CLK_000_D0.Q & !LDS_000.Q
# !AS_030 & RW & inst_AS_030_000_SYNC.Q & !LDS_000.Q
- # !AS_030 & RW & inst_CLK_000_DD.Q & !LDS_000.Q
+ # !AS_030 & RW & inst_CLK_000_D1.Q & !LDS_000.Q
# !AS_030 & RW & !SM_AMIGA_6_.Q & !LDS_000.Q
# !AS_030 & !RW & !LDS_000.Q & !SM_AMIGA_4_.Q
- # SIZE_1_ & !DS_030 & !RW & inst_CLK_000_D.Q & SM_AMIGA_4_.Q
- # !DS_030 & !RW & !SIZE_0_ & inst_CLK_000_D.Q & SM_AMIGA_4_.Q
- # !DS_030 & !RW & A_0_ & inst_CLK_000_D.Q & SM_AMIGA_4_.Q
- # SIZE_1_ & !DS_030 & RW & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q
- # !DS_030 & RW & !SIZE_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q
- # !DS_030 & RW & A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q);
+ # SIZE_1_ & !DS_030 & !RW & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q
+ # !DS_030 & !RW & !SIZE_0_ & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q
+ # !DS_030 & !RW & A_0_ & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q
+ # SIZE_1_ & !DS_030 & RW & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & SM_AMIGA_6_.Q
+ # !DS_030 & RW & !SIZE_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & SM_AMIGA_6_.Q
+ # !DS_030 & RW & A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & SM_AMIGA_6_.Q);
LDS_000.AP = (!RST);
LDS_000.C = (CLK_OSZI);
+IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q
+ # inst_CLK_000_D1.Q & IPL_030_1_.Q
+ # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
+
+IPL_030_1_.AP = (!RST);
+
+IPL_030_1_.C = (CLK_OSZI);
+
+IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q
+ # inst_CLK_000_D1.Q & IPL_030_0_.Q
+ # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
+
+IPL_030_0_.AP = (!RST);
+
+IPL_030_0_.C = (CLK_OSZI);
+
!BG_000.D = (!BG_030 & CLK_030 & !BG_000.Q
- # AS_030 & !CPU_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_6_.Q
- # AS_030 & !CPU_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_7_.Q);
+ # AS_030 & !nEXP_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_6_.Q
+ # AS_030 & !nEXP_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_7_.Q);
BG_000.AP = (!RST);
BG_000.C = (CLK_OSZI);
BGACK_030.D = (BGACK_000 & BGACK_030.Q
- # BGACK_000 & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q);
+ # BGACK_000 & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
BGACK_030.AP = (!RST);
BGACK_030.C = (CLK_OSZI);
-IPL_030_1_.D = (IPL_030_1_.Q & !inst_CLK_000_D.Q
- # IPL_030_1_.Q & inst_CLK_000_DD.Q
- # IPL_1_ & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q);
-
-IPL_030_1_.AP = (!RST);
-
-IPL_030_1_.C = (CLK_OSZI);
-
-IPL_030_0_.D = (!inst_CLK_000_D.Q & IPL_030_0_.Q
- # inst_CLK_000_DD.Q & IPL_030_0_.Q
- # IPL_0_ & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q);
-
-IPL_030_0_.AP = (!RST);
-
-IPL_030_0_.C = (CLK_OSZI);
-
CLK_EXP.D = (inst_CLK_OUT_PRE.Q);
CLK_EXP.C = (CLK_OSZI);
@@ -265,16 +265,16 @@ DTACK.AP = (!RST);
DTACK.C = (CLK_OSZI);
-E.T = (E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q
- # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q
- # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q);
+E.T = (E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_2_.Q
+ # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q
+ # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q);
E.C = (CLK_OSZI);
VMA.AP = (!RST);
-VMA.T = (!E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & AS_000.Q & inst_CLK_000_D.Q & cpu_est_2_.Q
- # !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !inst_CLK_000_D.Q & cpu_est_2_.Q);
+VMA.T = (!E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & AS_000.Q & inst_CLK_000_D0.Q & cpu_est_2_.Q
+ # !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & cpu_est_2_.Q);
VMA.C = (CLK_OSZI);
@@ -282,21 +282,21 @@ RESET.D = (RST);
RESET.C = (CLK_OSZI);
-cpu_est_0_.D = (cpu_est_0_.Q & !inst_CLK_000_D.Q
- # cpu_est_0_.Q & inst_CLK_000_DD.Q
- # !cpu_est_0_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q);
+cpu_est_0_.D = (cpu_est_0_.Q & !inst_CLK_000_D0.Q
+ # cpu_est_0_.Q & inst_CLK_000_D1.Q
+ # !cpu_est_0_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
cpu_est_0_.C = (CLK_OSZI);
-cpu_est_1_.T = (E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q
- # !E.Q & cpu_est_0_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q
- # !E.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q
- # E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q);
+cpu_est_1_.T = (E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q
+ # !E.Q & cpu_est_0_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_2_.Q
+ # !E.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q
+ # E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q);
cpu_est_1_.C = (CLK_OSZI);
inst_AS_030_000_SYNC.D = (AS_030
- # CPU_SPACE & CLK_030
+ # !nEXP_SPACE & CLK_030
# !CLK_030 & inst_AS_030_000_SYNC.Q
# FC_1_ & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_);
@@ -305,7 +305,7 @@ inst_AS_030_000_SYNC.AP = (!RST);
inst_AS_030_000_SYNC.C = (CLK_OSZI);
!inst_DTACK_SYNC.D = (!AS_030 & !inst_DTACK_SYNC.Q
- # inst_VPA_D.Q & inst_CLK_000_D.Q & SM_AMIGA_3_.Q & !DTACK.PIN);
+ # inst_VPA_D.Q & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !DTACK.PIN);
inst_DTACK_SYNC.AP = (!RST);
@@ -316,28 +316,28 @@ inst_VPA_D.D = (VPA);
inst_VPA_D.C = (CLK_OSZI);
!inst_VPA_SYNC.D = (!AS_030 & !inst_VPA_SYNC.Q
- # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q);
+ # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D0.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q);
inst_VPA_SYNC.AP = (!RST);
inst_VPA_SYNC.C = (CLK_OSZI);
-inst_CLK_000_D.D = (CLK_000);
+inst_CLK_000_D0.D = (CLK_000);
-inst_CLK_000_D.C = (CLK_OSZI);
+inst_CLK_000_D0.C = (CLK_OSZI);
-inst_CLK_000_DD.D = (inst_CLK_000_D.Q);
+inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
-inst_CLK_000_DD.C = (CLK_OSZI);
+inst_CLK_000_D1.C = (CLK_OSZI);
inst_CLK_OUT_PRE.D = (!inst_CLK_OUT_PRE.Q & CLK_CNT_0_.Q
# inst_CLK_OUT_PRE.Q & !CLK_CNT_0_.Q);
inst_CLK_OUT_PRE.C = (CLK_OSZI);
-cpu_est_2_.D.X1 = (E.Q & cpu_est_0_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q
- # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q
- # !E.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q);
+cpu_est_2_.D.X1 = (E.Q & cpu_est_0_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q
+ # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q
+ # !E.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_2_.Q);
cpu_est_2_.D.X2 = (cpu_est_2_.Q);
@@ -349,14 +349,14 @@ CLK_CNT_0_.C = (CLK_OSZI);
SM_AMIGA_6_.AR = (!RST);
-!SM_AMIGA_6_.D = (inst_CLK_000_D.Q & !SM_AMIGA_6_.Q
+!SM_AMIGA_6_.D = (inst_CLK_000_D0.Q & !SM_AMIGA_6_.Q
# !SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q
- # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q);
+ # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
SM_AMIGA_6_.C = (CLK_OSZI);
-SM_AMIGA_7_.D = (inst_CLK_000_D.Q & SM_AMIGA_7_.Q
- # AS_000.Q & inst_CLK_000_D.Q & SM_AMIGA_0_.Q);
+SM_AMIGA_7_.D = (inst_CLK_000_D0.Q & SM_AMIGA_7_.Q
+ # AS_000.Q & inst_CLK_000_D0.Q & SM_AMIGA_0_.Q);
SM_AMIGA_7_.AP = (!RST);
@@ -364,47 +364,47 @@ SM_AMIGA_7_.C = (CLK_OSZI);
SM_AMIGA_1_.AR = (!RST);
-SM_AMIGA_1_.D = (inst_CLK_000_D.Q & SM_AMIGA_1_.Q
- # inst_CLK_000_D.Q & SM_AMIGA_2_.Q
- # !inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q);
+SM_AMIGA_1_.D = (inst_CLK_000_D1.Q & SM_AMIGA_1_.Q
+ # !inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q
+ # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q);
SM_AMIGA_1_.C = (CLK_OSZI);
SM_AMIGA_4_.AR = (!RST);
-SM_AMIGA_4_.D = (!inst_CLK_000_D.Q & SM_AMIGA_4_.Q
- # !inst_CLK_000_D.Q & SM_AMIGA_5_.Q);
+SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_4_.Q
+ # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q);
SM_AMIGA_4_.C = (CLK_OSZI);
SM_AMIGA_3_.AR = (!RST);
-SM_AMIGA_3_.D = (inst_CLK_000_D.Q & SM_AMIGA_4_.Q
- # inst_CLK_000_D.Q & SM_AMIGA_3_.Q
+SM_AMIGA_3_.D = (inst_CLK_000_D0.Q & SM_AMIGA_4_.Q
+ # inst_CLK_000_D0.Q & SM_AMIGA_3_.Q
# inst_DTACK_SYNC.Q & inst_VPA_SYNC.Q & SM_AMIGA_3_.Q);
SM_AMIGA_3_.C = (CLK_OSZI);
SM_AMIGA_5_.AR = (!RST);
-SM_AMIGA_5_.D = (inst_CLK_000_D.Q & SM_AMIGA_5_.Q
- # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q);
+SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_5_.Q
+ # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & SM_AMIGA_6_.Q);
SM_AMIGA_5_.C = (CLK_OSZI);
SM_AMIGA_2_.AR = (!RST);
-SM_AMIGA_2_.D = (!inst_CLK_000_D.Q & SM_AMIGA_2_.Q
- # !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & SM_AMIGA_3_.Q
- # !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & SM_AMIGA_3_.Q);
+SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
+ # !inst_DTACK_SYNC.Q & !inst_CLK_000_D0.Q & SM_AMIGA_3_.Q
+ # !inst_VPA_SYNC.Q & !inst_CLK_000_D0.Q & SM_AMIGA_3_.Q);
SM_AMIGA_2_.C = (CLK_OSZI);
SM_AMIGA_0_.AR = (!RST);
SM_AMIGA_0_.D = (!AS_000.Q & SM_AMIGA_0_.Q
- # !inst_CLK_000_D.Q & SM_AMIGA_0_.Q
- # !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q);
+ # !inst_CLK_000_D0.Q & SM_AMIGA_0_.Q
+ # !inst_CLK_000_D1.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q);
SM_AMIGA_0_.C = (CLK_OSZI);
diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti
index d0a5974..4a9a440 100644
--- a/Logic/68030_tk.fti
+++ b/Logic/68030_tk.fti
@@ -39,7 +39,6 @@ DATA LOCATION CLK_CNT_0_:H_6 // NOD
DATA LOCATION CLK_DIV_OUT:G_0_65 // OUT
DATA LOCATION CLK_EXP:B_0_10 // OUT
DATA LOCATION CLK_OSZI:*_*_61 // Cin
-DATA LOCATION CPU_SPACE:*_*_14 // INP
DATA LOCATION DSACK_0_:H_12_80 // OUT
DATA LOCATION DSACK_1_:H_8_81 // IO {RN_DSACK_1_}
DATA LOCATION DS_030:A_*_98 // INP
@@ -72,11 +71,11 @@ DATA LOCATION RST:*_*_86 // INP
DATA LOCATION RW:G_*_71 // INP
DATA LOCATION SIZE_0_:G_*_70 // INP
DATA LOCATION SIZE_1_:H_*_79 // INP
-DATA LOCATION SM_AMIGA_0_:H_13 // NOD
-DATA LOCATION SM_AMIGA_1_:H_2 // NOD
-DATA LOCATION SM_AMIGA_2_:G_8 // NOD
+DATA LOCATION SM_AMIGA_0_:H_2 // NOD
+DATA LOCATION SM_AMIGA_1_:G_12 // NOD
+DATA LOCATION SM_AMIGA_2_:G_1 // NOD
DATA LOCATION SM_AMIGA_3_:G_5 // NOD
-DATA LOCATION SM_AMIGA_4_:G_12 // NOD
+DATA LOCATION SM_AMIGA_4_:F_0 // NOD
DATA LOCATION SM_AMIGA_5_:A_0 // NOD
DATA LOCATION SM_AMIGA_6_:D_6 // NOD
DATA LOCATION SM_AMIGA_7_:H_9 // NOD
@@ -86,13 +85,14 @@ DATA LOCATION VPA:*_*_36 // INP
DATA LOCATION cpu_est_0_:D_14 // NOD
DATA LOCATION cpu_est_1_:D_2 // NOD
DATA LOCATION cpu_est_2_:D_10 // NOD
-DATA LOCATION inst_AS_030_000_SYNC:F_0 // NOD
-DATA LOCATION inst_CLK_000_D:H_1 // NOD
-DATA LOCATION inst_CLK_000_DD:D_13 // NOD
+DATA LOCATION inst_AS_030_000_SYNC:H_1 // NOD
+DATA LOCATION inst_CLK_000_D0:G_8 // NOD
+DATA LOCATION inst_CLK_000_D1:D_13 // NOD
DATA LOCATION inst_CLK_OUT_PRE:H_5 // NOD
DATA LOCATION inst_DTACK_SYNC:G_13 // NOD
-DATA LOCATION inst_VPA_D:G_1 // NOD
+DATA LOCATION inst_VPA_D:H_13 // NOD
DATA LOCATION inst_VPA_SYNC:G_9 // NOD
+DATA LOCATION nEXP_SPACE:*_*_14 // INP
DATA IO_DIR AMIGA_BUS_DATA_DIR:OUT
DATA IO_DIR AMIGA_BUS_ENABLE:OUT
DATA IO_DIR AMIGA_BUS_ENABLE_LOW:OUT
@@ -128,7 +128,6 @@ DATA IO_DIR CLK_030:IN
DATA IO_DIR CLK_DIV_OUT:OUT
DATA IO_DIR CLK_EXP:OUT
DATA IO_DIR CLK_OSZI:IN
-DATA IO_DIR CPU_SPACE:IN
DATA IO_DIR DSACK_0_:OUT
DATA IO_DIR DSACK_1_:BI
DATA IO_DIR DS_030:IN
@@ -152,23 +151,16 @@ DATA IO_DIR SIZE_1_:IN
DATA IO_DIR UDS_000:OUT
DATA IO_DIR VMA:OUT
DATA IO_DIR VPA:IN
+DATA IO_DIR nEXP_SPACE:IN
DATA GLB_CLOCK CLK_OSZI
-DATA PW_LEVEL A_21_:0
-DATA SLEW A_21_:0
-DATA PW_LEVEL A_20_:0
-DATA SLEW A_20_:0
-DATA PW_LEVEL SIZE_1_:0
-DATA SLEW SIZE_1_:0
-DATA PW_LEVEL A_19_:0
-DATA SLEW A_19_:0
-DATA PW_LEVEL A_18_:0
-DATA SLEW A_18_:0
-DATA PW_LEVEL A_31_:0
-DATA SLEW A_31_:0
DATA PW_LEVEL A_17_:0
DATA SLEW A_17_:0
DATA PW_LEVEL A_16_:0
DATA SLEW A_16_:0
+DATA PW_LEVEL SIZE_1_:0
+DATA SLEW SIZE_1_:0
+DATA PW_LEVEL A_31_:0
+DATA SLEW A_31_:0
DATA PW_LEVEL IPL_2_:0
DATA SLEW IPL_2_:0
DATA PW_LEVEL FC_1_:0
@@ -177,28 +169,28 @@ DATA PW_LEVEL AS_030:0
DATA SLEW AS_030:0
DATA PW_LEVEL DS_030:0
DATA SLEW DS_030:0
-DATA SLEW CPU_SPACE:0
+DATA PW_LEVEL A_0_:0
+DATA SLEW A_0_:0
+DATA SLEW nEXP_SPACE:0
DATA PW_LEVEL BERR:0
DATA SLEW BERR:0
DATA PW_LEVEL BG_030:0
DATA SLEW BG_030:0
-DATA PW_LEVEL A_0_:0
-DATA SLEW A_0_:0
-DATA PW_LEVEL BGACK_000:0
-DATA SLEW BGACK_000:0
-DATA SLEW CLK_030:0
DATA PW_LEVEL IPL_1_:0
DATA SLEW IPL_1_:0
-DATA SLEW CLK_000:0
DATA PW_LEVEL IPL_0_:0
DATA SLEW IPL_0_:0
-DATA SLEW CLK_OSZI:0
DATA PW_LEVEL DSACK_0_:0
DATA SLEW DSACK_0_:0
-DATA PW_LEVEL CLK_DIV_OUT:0
-DATA SLEW CLK_DIV_OUT:0
+DATA PW_LEVEL BGACK_000:0
+DATA SLEW BGACK_000:0
DATA PW_LEVEL FC_0_:0
DATA SLEW FC_0_:0
+DATA SLEW CLK_030:0
+DATA SLEW CLK_000:0
+DATA SLEW CLK_OSZI:0
+DATA PW_LEVEL CLK_DIV_OUT:0
+DATA SLEW CLK_DIV_OUT:0
DATA PW_LEVEL AVEC:0
DATA SLEW AVEC:0
DATA PW_LEVEL AVEC_EXP:0
@@ -235,6 +227,14 @@ DATA PW_LEVEL A_23_:0
DATA SLEW A_23_:0
DATA PW_LEVEL A_22_:0
DATA SLEW A_22_:0
+DATA PW_LEVEL A_21_:0
+DATA SLEW A_21_:0
+DATA PW_LEVEL A_20_:0
+DATA SLEW A_20_:0
+DATA PW_LEVEL A_19_:0
+DATA SLEW A_19_:0
+DATA PW_LEVEL A_18_:0
+DATA SLEW A_18_:0
DATA PW_LEVEL IPL_030_2_:0
DATA SLEW IPL_030_2_:0
DATA PW_LEVEL DSACK_1_:0
@@ -245,14 +245,14 @@ DATA PW_LEVEL UDS_000:0
DATA SLEW UDS_000:0
DATA PW_LEVEL LDS_000:0
DATA SLEW LDS_000:0
-DATA PW_LEVEL BG_000:0
-DATA SLEW BG_000:0
-DATA PW_LEVEL BGACK_030:0
-DATA SLEW BGACK_030:0
DATA PW_LEVEL IPL_030_1_:0
DATA SLEW IPL_030_1_:0
DATA PW_LEVEL IPL_030_0_:0
DATA SLEW IPL_030_0_:0
+DATA PW_LEVEL BG_000:0
+DATA SLEW BG_000:0
+DATA PW_LEVEL BGACK_030:0
+DATA SLEW BGACK_030:0
DATA PW_LEVEL CLK_EXP:0
DATA SLEW CLK_EXP:0
DATA PW_LEVEL FPU_CS:0
@@ -277,10 +277,10 @@ DATA PW_LEVEL inst_VPA_D:0
DATA SLEW inst_VPA_D:0
DATA PW_LEVEL inst_VPA_SYNC:0
DATA SLEW inst_VPA_SYNC:0
-DATA PW_LEVEL inst_CLK_000_D:0
-DATA SLEW inst_CLK_000_D:0
-DATA PW_LEVEL inst_CLK_000_DD:0
-DATA SLEW inst_CLK_000_DD:0
+DATA PW_LEVEL inst_CLK_000_D0:0
+DATA SLEW inst_CLK_000_D0:0
+DATA PW_LEVEL inst_CLK_000_D1:0
+DATA SLEW inst_CLK_000_D1:0
DATA PW_LEVEL inst_CLK_OUT_PRE:0
DATA SLEW inst_CLK_OUT_PRE:0
DATA PW_LEVEL cpu_est_2_:0
@@ -308,10 +308,10 @@ DATA PW_LEVEL RN_DSACK_1_:0
DATA PW_LEVEL RN_AS_000:0
DATA PW_LEVEL RN_UDS_000:0
DATA PW_LEVEL RN_LDS_000:0
-DATA PW_LEVEL RN_BG_000:0
-DATA PW_LEVEL RN_BGACK_030:0
DATA PW_LEVEL RN_IPL_030_1_:0
DATA PW_LEVEL RN_IPL_030_0_:0
+DATA PW_LEVEL RN_BG_000:0
+DATA PW_LEVEL RN_BGACK_030:0
DATA PW_LEVEL RN_FPU_CS:0
DATA PW_LEVEL RN_E:0
DATA PW_LEVEL RN_VMA:0
diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp
index b276e9a..b08563d 100644
--- a/Logic/68030_tk.grp
+++ b/Logic/68030_tk.grp
@@ -5,11 +5,11 @@ GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_
GROUP MACH_SEG_C AVEC_EXP AMIGA_BUS_ENABLE_LOW
GROUP MACH_SEG_D LDS_000 RN_LDS_000 UDS_000 RN_UDS_000 VMA RN_VMA BG_000
RN_BG_000 AS_000 RN_AS_000 cpu_est_1_ cpu_est_2_ SM_AMIGA_6_ DTACK
- cpu_est_0_ inst_CLK_000_DD AMIGA_BUS_ENABLE
+ cpu_est_0_ inst_CLK_000_D1 AMIGA_BUS_ENABLE
GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR
-GROUP MACH_SEG_F inst_AS_030_000_SYNC
-GROUP MACH_SEG_G inst_VPA_SYNC inst_DTACK_SYNC E RN_E SM_AMIGA_2_ SM_AMIGA_3_
- SM_AMIGA_4_ inst_VPA_D CLK_DIV_OUT
-GROUP MACH_SEG_H FPU_CS RN_FPU_CS DSACK_1_ RN_DSACK_1_ SM_AMIGA_0_ SM_AMIGA_7_
- SM_AMIGA_1_ BGACK_030 RN_BGACK_030 inst_CLK_OUT_PRE inst_CLK_000_D
+GROUP MACH_SEG_F SM_AMIGA_4_
+GROUP MACH_SEG_G inst_VPA_SYNC inst_DTACK_SYNC SM_AMIGA_2_ E RN_E SM_AMIGA_3_
+ SM_AMIGA_1_ inst_CLK_000_D0 CLK_DIV_OUT
+GROUP MACH_SEG_H inst_AS_030_000_SYNC FPU_CS RN_FPU_CS DSACK_1_ RN_DSACK_1_
+ SM_AMIGA_0_ SM_AMIGA_7_ BGACK_030 RN_BGACK_030 inst_CLK_OUT_PRE inst_VPA_D
CLK_CNT_0_ DSACK_0_
\ No newline at end of file
diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr
index 3d93bb9..06130dd 100644
--- a/Logic/68030_tk.ipr
+++ b/Logic/68030_tk.ipr
@@ -1 +1 @@
-6754<46>b[ðb4
\ No newline at end of file
+93:1176f=uNI
\ No newline at end of file
diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed
index af54237..c9c994e 100644
--- a/Logic/68030_tk.jed
+++ b/Logic/68030_tk.jed
@@ -10,7 +10,7 @@ AUTHOR:
PATTERN:
COMPANY:
REVISION:
-DATE: Thu May 15 23:02:50 2014
+DATE: Fri May 16 17:07:12 2014
ABEL mach447a
*
@@ -31,44 +31,45 @@ NOTE Spread Placement? Y *
NOTE Run Time Upper Bound in 15 minutes 0 *
NOTE Zero Hold Time For Input Registers? Y *
NOTE Table of pin names and numbers*
-NOTE PINS A_21_:94 A_20_:93 SIZE_1_:79 A_19_:97 A_18_:95*
-NOTE PINS A_31_:4 A_17_:59 A_16_:96 IPL_2_:68 FC_1_:58 AS_030:82*
-NOTE PINS DS_030:98 CPU_SPACE:14 BERR:41 BG_030:21 A_0_:69*
-NOTE PINS BGACK_000:28 CLK_030:64 IPL_1_:56 CLK_000:11 IPL_0_:67*
-NOTE PINS CLK_OSZI:61 DSACK_0_:80 CLK_DIV_OUT:65 FC_0_:57*
-NOTE PINS AVEC:92 AVEC_EXP:22 VPA:36 RST:86 RW:71 AMIGA_BUS_ENABLE:34*
-NOTE PINS AMIGA_BUS_DATA_DIR:48 AMIGA_BUS_ENABLE_LOW:20 CIIN:47*
-NOTE PINS SIZE_0_:70 A_30_:5 A_29_:6 A_28_:15 A_27_:16 A_26_:17*
-NOTE PINS A_25_:18 A_24_:19 A_23_:84 A_22_:85 IPL_030_2_:9*
-NOTE PINS DSACK_1_:81 AS_000:33 UDS_000:32 LDS_000:31 BG_000:29*
-NOTE PINS BGACK_030:83 IPL_030_1_:7 IPL_030_0_:8 CLK_EXP:10*
-NOTE PINS FPU_CS:78 DTACK:30 E:66 VMA:35 RESET:3 *
+NOTE PINS A_17_:59 A_16_:96 SIZE_1_:79 A_31_:4 IPL_2_:68*
+NOTE PINS FC_1_:58 AS_030:82 DS_030:98 A_0_:69 nEXP_SPACE:14*
+NOTE PINS BERR:41 BG_030:21 IPL_1_:56 IPL_0_:67 DSACK_0_:80*
+NOTE PINS BGACK_000:28 FC_0_:57 CLK_030:64 CLK_000:11 CLK_OSZI:61*
+NOTE PINS CLK_DIV_OUT:65 AVEC:92 AVEC_EXP:22 VPA:36 RST:86*
+NOTE PINS RW:71 AMIGA_BUS_ENABLE:34 AMIGA_BUS_DATA_DIR:48*
+NOTE PINS AMIGA_BUS_ENABLE_LOW:20 CIIN:47 SIZE_0_:70 A_30_:5*
+NOTE PINS A_29_:6 A_28_:15 A_27_:16 A_26_:17 A_25_:18 A_24_:19*
+NOTE PINS A_23_:84 A_22_:85 A_21_:94 A_20_:93 A_19_:97 A_18_:95*
+NOTE PINS IPL_030_2_:9 DSACK_1_:81 AS_000:33 UDS_000:32 LDS_000:31*
+NOTE PINS IPL_030_1_:7 IPL_030_0_:8 BG_000:29 BGACK_030:83*
+NOTE PINS CLK_EXP:10 FPU_CS:78 DTACK:30 E:66 VMA:35 RESET:3*
NOTE Table of node names and numbers*
NOTE NODES RN_IPL_030_2_:131 RN_DSACK_1_:281 RN_AS_000:181 *
-NOTE NODES RN_UDS_000:191 RN_LDS_000:185 RN_BG_000:175 RN_BGACK_030:275 *
-NOTE NODES RN_IPL_030_1_:143 RN_IPL_030_0_:137 RN_FPU_CS:269 *
-NOTE NODES RN_DTACK:173 RN_E:251 RN_VMA:179 cpu_est_0_:194 *
-NOTE NODES cpu_est_1_:176 inst_AS_030_000_SYNC:221 inst_DTACK_SYNC:265 *
-NOTE NODES inst_VPA_D:247 inst_VPA_SYNC:259 inst_CLK_000_D:271 *
-NOTE NODES inst_CLK_000_DD:193 inst_CLK_OUT_PRE:277 cpu_est_2_:188 *
-NOTE NODES CLK_CNT_0_:278 SM_AMIGA_6_:182 SM_AMIGA_7_:283 *
-NOTE NODES SM_AMIGA_1_:272 SM_AMIGA_4_:263 SM_AMIGA_3_:253 *
-NOTE NODES SM_AMIGA_5_:101 SM_AMIGA_2_:257 SM_AMIGA_0_:289 *
+NOTE NODES RN_UDS_000:191 RN_LDS_000:185 RN_IPL_030_1_:143 *
+NOTE NODES RN_IPL_030_0_:137 RN_BG_000:175 RN_BGACK_030:275 *
+NOTE NODES RN_FPU_CS:269 RN_DTACK:173 RN_E:251 RN_VMA:179 *
+NOTE NODES cpu_est_0_:194 cpu_est_1_:176 inst_AS_030_000_SYNC:271 *
+NOTE NODES inst_DTACK_SYNC:265 inst_VPA_D:289 inst_VPA_SYNC:259 *
+NOTE NODES inst_CLK_000_D0:257 inst_CLK_000_D1:193 inst_CLK_OUT_PRE:277 *
+NOTE NODES cpu_est_2_:188 CLK_CNT_0_:278 SM_AMIGA_6_:182 *
+NOTE NODES SM_AMIGA_7_:283 SM_AMIGA_1_:263 SM_AMIGA_4_:221 *
+NOTE NODES SM_AMIGA_3_:253 SM_AMIGA_5_:101 SM_AMIGA_2_:247 *
+NOTE NODES SM_AMIGA_0_:272 *
NOTE BLOCK 0 *
L000000
111111111111111111111111111111111111111111111111111111111111111111
111111111011111111111111111111111111111111111111111111111111111111
+ 111111111111111111111111111011111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111
- 111111111110111111111111111111111111111111111111111111111111111111
110111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111110111111111111111111111111111111111
101111111111111111111011111111011111111111111111111111111111111111*
L000594
000000000000000000000000000000000000000000000000000000000000000000*
-L000660 111011111110111111110111111111110111111111111111111111111111111111*
-L000726 111111111111111111110111111111011111111111111111111111111111111111*
+L000660 111011111111111111111011110111110111111111111111111111111111111111*
+L000726 111111111111111111111111110111011111111111111111111111111111111111*
L000792 000000000000000000000000000000000000000000000000000000000000000000*
L000858 000000000000000000000000000000000000000000000000000000000000000000*
L000924 000000000000000000000000000000000000000000000000000000000000000000*
@@ -185,13 +186,13 @@ NOTE BLOCK 1 *
L006762
111111111111111111111111011111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111110111111
- 111111101011111101111111111111111111111111111111111111111111111111
+ 111111101011111101111011111111111111111111111111111111111111111111
101111111111111111111111111111111111111111111111111111011111111111
111111111111111111111111111111111111111111111111111111111111111111
110111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111
111111111111111111111111111011111111111111111111111111111111111111
- 111111111111111111111011111111111111111111101111111111111111111111*
+ 111111111111111111111111111111111111111111101111111111111111111111*
L007356
111111111111111111111111111111111111111111111111111111111111111111*
L007422 111111111111111111111111110111111111111111111111111111111111111111*
@@ -218,9 +219,9 @@ L008676 111111111111111111111111111111111111111111111111111111111111111111*
L008742 111111111111111111111111111111111111111111111111111111111111111111*
L008808
111111111111111111111111111111111111111111111111111111111111111111*
-L008874 111111111111111111111011111111111111111111111111111111011111111111*
-L008940 110111111111111111111111111111111111111111111111111111011111111111*
-L009006 111011110111111111110111111111111111111111111111111111111111111111*
+L008874 111011110111111111110111111111111111111111111111111111111111111111*
+L008940 111111111111111111111011111111111111111111111111111111011111111111*
+L009006 110111111111111111111111111111111111111111111111111111011111111111*
L009072 000000000000000000000000000000000000000000000000000000000000000000*
L009138 000000000000000000000000000000000000000000000000000000000000000000*
L009204 111111111111111111111111111111111111111111111111111111111111111111*
@@ -266,9 +267,9 @@ L011580 111111111111111111111111111111111111111111111111111111111111111111*
L011646 111111111111111111111111111111111111111111111111111111111111111111*
L011712
000000000000000000000000000000000000000000000000000000000000000000*
-L011778 111111111111111111111011011111111111111111111111111111111111111111*
-L011844 110111111111111111111111011111111111111111111111111111111111111111*
-L011910 111011011111111111110111111111111111111111111111111111111111111111*
+L011778 111011011111111111110111111111111111111111111111111111111111111111*
+L011844 111111111111111111111011011111111111111111111111111111111111111111*
+L011910 110111111111111111111111011111111111111111111111111111111111111111*
L011976 000000000000000000000000000000000000000000000000000000000000000000*
L012042 000000000000000000000000000000000000000000000000000000000000000000*
L012108 111111111111111111111111111111111111111111111111111111111111111111*
@@ -437,49 +438,49 @@ L020258 11110111110101*
L020272 11111111111111*
NOTE BLOCK 3 *
L020286
- 111111111111111111111111111110111111111111111111111111111011111111
- 101111111111111110111111111111011111111111110111111111111110111111
- 111111111111111111111111111111111111101111111111111111111111111111
+ 111111111111111111111111111111111111111110111111111111111111111111
+ 101111110111111110111111111111011111111111111111111111111110111111
+ 111111111111111111111111111011111111101111111111111111111111111111
111110111111111111111111111111111111111111111111111111111111111111
- 111111111001111111110111111111111111111111111111111011111111111111
- 110111111111101111111101111111111111111101111111111111111111111111
- 111111111111111111111111111111110111111111111111111111101111111110
- 111111111111110111101111111111111111111111011110111111111111011111
- 111111011111111111111111101111111101111111111111101111111111111111*
+ 111111111111111111110111011111111111111111111111111011111111111111
+ 110111111111101011111101111111111111111111111111111111111111011111
+ 111111111101111111111111111111111111111111111111111111101111111110
+ 111111111111111111101111111101110111111111111110011111111111111111
+ 111111011111111111111111111111111101111011101111111111111111111111*
L020880
111111111111111111111111111111111111111111111111111111111111111111*
-L020946 111111111111111011111111111111111111111111111111111111111111111110*
+L020946 111111111111111111111111111111111111111111111111101111111111111110*
L021012 000000000000000000000000000000000000000000000000000000000000000000*
L021078 000000000000000000000000000000000000000000000000000000000000000000*
L021144 000000000000000000000000000000000000000000000000000000000000000000*
L021210 000000000000000000000000000000000000000000000000000000000000000000*
-L021276 111001101111111111111011011111111111111111111111111111111111111111*
-L021342 111010111111111111110111011111111111111101111111111111111111111111*
-L021408 111001011111111111110111011111111111111110111111111111111111111111*
-L021474 111010101111111111111111011111111111111110111111111111111111111111*
+L021276 111001101111111111111011110111111111111111111111111111111111111111*
+L021342 111010111111111111110111110111111111111111111111111111111111011111*
+L021408 111001011111111111110111110111111111111111111111111111111111101111*
+L021474 111010101111111111111111110111111111111111111111111111111111101111*
L021540 000000000000000000000000000000000000000000000000000000000000000000*
L021606
111111111111111111111111111111111111111111111111111111111111111111*
-L021672 111111111111111111011111111111101111111111111011111111111011011111*
+L021672 111111111011111111011111111111100111111110111111111111111111111111*
L021738 111111111111111111111111111111111111111111111111111111111101111111*
L021804 000000000000000000000000000000000000000000000000000000000000000000*
-L021870 111111111111111111011111111111101111111111111011111111011011111111*
-L021936 111111111111111111111111111111111110111111111011111111110111111111*
-L022002 111110011111110111111011011111111111111101101111111111111111111111*
-L022068 111110101011111111110111101111111111111101011111111111111111111111*
+L021870 111111111011111111011111111111101111111110111111111111011111111111*
+L021936 111111111011111111111111111111111110111101111111111111111111111111*
+L022002 111110011111111111111011110110111111111111111111011111111111011111*
+L022068 111110101111111011110111111001111111111111111111111111111111011111*
L022134 000000000000000000000000000000000000000000000000000000000000000000*
L022200 000000000000000000000000000000000000000000000000000000000000000000*
L022266 000000000000000000000000000000000000000000000000000000000000000000*
L022332
111111111111111111111111111111111111111111111101111111111111111111*
-L022398 111111111111111011101111111111111111111111111111111111111111111111*
-L022464 111011111111111111111111011111111111111111111111111011111111011111*
+L022398 111111111111111111101111111111111111111111111111101111111111111111*
+L022464 111011111111111111111111110111110111111011111111111111111111111111*
L022530 000000000000000000000000000000000000000000000000000000000000000000*
L022596 000000000000000000000000000000000000000000000000000000000000000000*
L022662 000000000000000000000000000000000000000000000000000000000000000000*
-L022728 111011111111111111111111011111111111111111111111111011111111111111*
-L022794 111111111111111111111111011111111111111111111111111111111111101111*
-L022860 111111111111111111111111111111111111111111111111111111101111101111*
+L022728 111011111111111111111111110111111111111011111111111111111111111111*
+L022794 111111111111111111111111110111111011111111111111111111111111111111*
+L022860 111111111111111111111111111111111011111111111111111111101111111111*
L022926 000000000000000000000000000000000000000000000000000000000000000000*
L022992 000000000000000000000000000000000000000000000000000000000000000000*
L023058
@@ -489,54 +490,54 @@ L023190 111111111111111111111111111111111111111111111111111111111111111111*
L023256 111111111111111111111111111111111111111111111111111111111111111111*
L023322 111111111111111111111111111111111111111111111111111111111111111111*
L023388 111111111111111111111111111111111111111111111111111111111111111111*
-L023454 111011111110011101111111011111111111111111111111111011111111011111*
-L023520 101011111110111101111111011111111111111111111111111011111111011111*
-L023586 111011111110111101111111011111111111011111111111111011111111011111*
-L023652 111111111101111111101111111111111011111111111111111111111111111111*
-L023718 111111111111111101101111111111111011111111111111110111111111111111*
+L023454 111011111111011101111111100111110111111011111111111111111111111111*
+L023520 101011111111111101111111100111110111111011111111111111111111111111*
+L023586 111011111111111101111111100111110111011011111111111111111111111111*
+L023652 111111111110111111101111011111111111111111111111111111111111111111*
+L023718 111111111110111101101111111111111111110111111111111111111111111111*
L023784
111111111111111111111111111111111111111111111101111111111111111111*
-L023850 111111111111111111101111101111111011111111111111111111111111111111*
-L023916 110111111111111101101111111111111011111111111111111111111111111111*
-L023982 111111111111111101101111111111111011111111111111111111111111101111*
-L024048 111111111110011110111111011101111111111111111111111111111111111111*
-L024114 101111111110111110111111011101111111111111111111111111111111111111*
-L024180 000000000000000000000000000000000000000000000000000000000000000000*
-L024246 111001111111111111110111011111111111111110111111111111111111111111*
-L024312 111011101111111111111011011111111111111110111111111111111111111111*
-L024378 111010101111111111110111011111111111111101111111111111111111111111*
+L023850 111111111110111111101111111011111111111111111111111111111111111111*
+L023916 110111111110111101101111111111111111111111111111111111111111111111*
+L023982 111111111110111101101111111111111011111111111111111111111111111111*
+L024048 111111111111011110111111100111111111111111111111110111111111111111*
+L024114 101111111111111110111111100111111111111111111111110111111111111111*
+L024180 111111111111111111111111111111101111111111111111111111111111111111*
+L024246 111001111111111111110111110111111111111111111111111111111111101111*
+L024312 111011101111111111111011110111111111111111111111111111111111101111*
+L024378 111010101111111111110111110111111111111111111111111111111111011111*
L024444 000000000000000000000000000000000000000000000000000000000000000000*
L024510
111111111111111111111111111111111111111111111110111111111111111111*
-L024576 111111111111111111111111111111111111111101111111111111111111111111*
+L024576 111111111111111111111111111111111111111111111111111111111111011111*
L024642 111111111111111111111111111111111111111111111111111111111101111111*
L024708 000000000000000000000000000000000000000000000000000000000000000000*
-L024774 111111111110111110111111011101111111011111111111111111111111111111*
-L024840 111111111111111110101111111110111011111111111111111111111111111111*
-L024906 111011111110111101111111011111111111101111111111111011111111011111*
-L024972 111111111101111111101110111111111111111111111111111111111111111111*
-L025038 111111111111111101101110111111111111111111111111110111111111111111*
-L025104 111111111111111111101110101111111111111111111111111111111111111111*
+L024774 111111111111111110111111100111111111011111111111110111111111111111*
+L024840 111111111110111110101111111111111111111111111111111011111111111111*
+L024906 111011111111111101111111100111110111101011111111111111111111111111*
+L024972 111111111111111111101110011111111111111111111111111111111111111111*
+L025038 111111111111111101101110111111111111110111111111111111111111111111*
+L025104 111111111111111111101110111011111111111111111111111111111111111111*
L025170 110111111111111101101110111111111111111111111111111111111111111111*
L025236
111111111111111111111111111111111111111111111111111111111111111111*
-L025302 111111111111111101101110111111111111111111111111111111111111101111*
-L025368 111111111110111110111111011101111111101111111111111111111111111111*
-L025434 111111111111111110101110111110111111111111111111111111111111111111*
+L025302 111111111111111101101110111111111011111111111111111111111111111111*
+L025368 111111111111111110111111100111111111101111111111110111111111111111*
+L025434 111111111111111110101110111111111111111111111111111011111111111111*
L025500 000000000000000000000000000000000000000000000000000000000000000000*
L025566 000000000000000000000000000000000000000000000000000000000000000000*
-L025632 111111111111111111111111011111111111111111111111111111111111111111*
+L025632 111111111111111111111111110111111111111111111111111111111111111111*
L025698 111111111111111111111111111111111111111111111111111111111101111111*
L025764 000000000000000000000000000000000000000000000000000000000000000000*
L025830 000000000000000000000000000000000000000000000000000000000000000000*
L025896 000000000000000000000000000000000000000000000000000000000000000000*
L025962
000000000000000000000000000000000000000000000000000000000000000000*
-L026028 111111111111111111110111101111111111111111111111111111111111111111*
+L026028 111111111111111111110111111011111111111111111111111111111111111111*
L026094 111111111111111111111111111111111111111111111111111111111101111111*
L026160 000000000000000000000000000000000000000000000000000000000000000000*
L026226 110111111111111111110111111111111111111111111111111111111111111111*
-L026292 111011111111111111111011011111111111111111111111111111111111111111*
+L026292 111011111111111111111011110111111111111111111111111111111111111111*
L026358 111111111111111111111111111111111111111111111111111111111111111111*
L026424 111111111111111111111111111111111111111111111111111111111111111111*
L026490 111111111111111111111111111111111111111111111111111111111111111111*
@@ -544,7 +545,7 @@ L026556 111111111111111111111111111111111111111111111111111111111111111111*
L026622 111111111111111111111111111111111111111111111111111111111111111111*
L026688
000000000000000000000000000000000000000000000000000000000000000000
- 111111111111111111111111111111111111111111111111101111111111111111*
+ 111111111111111111111111111111111111111111101111111111111111111111*
L026820 0010*
L026824 01100110010010*
L026838 11010110011110*
@@ -691,21 +692,21 @@ L033782 11110111110101*
L033796 11111111111111*
NOTE BLOCK 5 *
L033810
- 111111111111111111111111111111111111111110111111111111111111111111
- 111111111101111111111111111111111111111111111111111111111111111111
- 111111111111101111111111111111111111111111111111111111111111111111
- 111011111111111110111111111111111111111111111111111111111111111111
- 111111111111111111111111111111111111111111111111111011111111111111
- 111111110111111111111111011111111111111111111111111111111111111111
- 111111111111111111111101111111111101111111111111111111111111111111
- 111111111111111111101111111111111111111111111111111111111111111111
- 101111111111111111111111111111111111111111111111111111111111111111*
+ 111111111111111111111111111111111111111111111111111111111111111111
+ 111111111011111111111111111111111111111111111111111111111111111111
+ 111111111111111111111011111111111111111111111111111111111111111111
+ 111111111111111111111111111111111111111111111111111111111111111111
+ 111111111110111111111111111111111111111111111111111111111111111111
+ 111111111111111111111111111111111111111111111111111111111111111111
+ 111111111111111111111111111111111111111111111111111111111111111111
+ 111111111111111111111111111111111111111111111111111111111111111111
+ 101111111111111111111111111111011111111111111111111111111111111111*
L034404
000000000000000000000000000000000000000000000000000000000000000000*
-L034470 111111111111111111011111111111111111111111111111111111111111111111*
-L034536 111111111101111111111111111111111111111101111111111111111111111111*
-L034602 110111110111011101111110101111111110111101111111111111111111111111*
-L034668 111111111111111111111111111111111111111110111111110111111111111111*
+L034470 111111111101111111111011111111111111111111111111111111111111111111*
+L034536 111111111111111111111011111111011111111111111111111111111111111111*
+L034602 000000000000000000000000000000000000000000000000000000000000000000*
+L034668 000000000000000000000000000000000000000000000000000000000000000000*
L034734 000000000000000000000000000000000000000000000000000000000000000000*
L034800 111111111111111111111111111111111111111111111111111111111111111111*
L034866 111111111111111111111111111111111111111111111111111111111111111111*
@@ -797,8 +798,8 @@ L040014 111111111111111111111111111111111111111111111111111111111111111111*
L040080 111111111111111111111111111111111111111111111111111111111111111111*
L040146 111111111111111111111111111111111111111111111111111111111111111111*
L040212
- 000000000000000000000000000000000000000000000000000000000000000000
- 101111111111111111111111111111111111111111111111111111111111111111*
+ 101111111111111111111111111111111111111111111111111111111111111111
+ 000000000000000000000000000000000000000000000000000000000000000000*
L040344 0010*
L040348 10100110011110*
L040362 11011011111110*
@@ -818,27 +819,27 @@ L040544 11110111111111*
L040558 11111111111111*
NOTE BLOCK 6 *
L040572
- 111111111111111011111111101111111111111111111111111111111111111111
- 111111111111111111111111111111111111111111101111111111101111111111
- 111111111111111111111111111011111111111111111111111111111111111111
- 111111101111111111111110111111111111111111111111111111111111111111
- 111111111111111111111111111111111101111111111111101111111111111111
- 110101111111111111111111111111111111111111111111111111111111111111
- 111111111111111111111111111111111111111111111101111111111111111111
- 111111111011111111101111111101111111111111111111111111111111111111
- 101111111111111111110111111111010111111011111111111111111111111111*
+ 111111011111111111111111101111111111111111111110111111111111111111
+ 111111111011111111111011111111111111111111111111111111111111111111
+ 111111111111111111111111111111111111111111111111111111111011111111
+ 111111111111111111111110111111111111111111111011111111111111111111
+ 111111111110111111111111111111111101111111111111101111111111111111
+ 110101111111111011111111111111111111111111111111111111111111111111
+ 111111111111111111011111111111111111111111111111111111111111111111
+ 111111111111111111111111111001111111111011111111111111111111111111
+ 101111111111111111111111111111110111111111111111111111111111111111*
L041166
111111111111111111111111111111111111111111111111111111111111111111*
-L041232 111111110111111111111111111111111111111111111111111111111111111111*
+L041232 111111111111111111111111110111111111111111111111111111111111111111*
L041298 000000000000000000000000000000000000000000000000000000000000000000*
L041364 000000000000000000000000000000000000000000000000000000000000000000*
L041430 000000000000000000000000000000000000000000000000000000000000000000*
L041496 000000000000000000000000000000000000000000000000000000000000000000*
-L041562 111111111111111111110111111111111111111111111111111111111111111111*
-L041628 111111111111111111111111111111111111111111111111111111111111111111*
-L041694 111111111111111111111111111111111111111111111111111111111111111111*
-L041760 111111111111111111111111111111111111111111111111111111111111111111*
-L041826 111111111111111111111111111111111111111111111111111111111111111111*
+L041562 111111111111111111111111101111111111111111110111111111111011111111*
+L041628 111111110111111111111111111111111111111111111111111111111111111111*
+L041694 101111111111111111111111111111111111111111111111111111111111111111*
+L041760 111111111111111111111011111111111111111111110111111111111011111111*
+L041826 111111111111111111111111111111111111111111111111011111111011111111*
L041892
111111111111111111111111111111111111111111111111111111111111111111*
L041958 111111111111111111111111111111111111111111111111111111111111111111*
@@ -853,16 +854,16 @@ L042486 111111111111111111111111111111111111111111111111111111111111111111*
L042552 111111111111111111111111111111111111111111111111111111111111111111*
L042618
000000000000000000000000000000000000000000000000000000000000000000*
-L042684 111001111111111111111101111111110101110111111111111111111111111111*
-L042750 111010111111111111111110111111110101110111111111111111111111111111*
-L042816 111010111111111111111110111111111010110111111111111111111111111111*
+L042684 111001111111111111111101111111110101111111111111111111110111111111*
+L042750 111010111111111111111110111111110101111111111111111111110111111111*
+L042816 111010111111111111111110111111111010111111111111111111110111111111*
L042882 000000000000000000000000000000000000000000000000000000000000000000*
L042948 000000000000000000000000000000000000000000000000000000000000000000*
-L043014 111111111111110111111111111111111111110111111111111111111111111111*
-L043080 111111111111111111111111111111111111111111011111111111111111111111*
+L043014 111111111101111111111111111111111111111111111111111111110111111111*
+L043080 111111110111111111111111111111111111111111111111111111111111111111*
L043146 101111111111111111111111111111111111111111111111111111111111111111*
-L043212 111111011111111111111111011111111111111111111111111111011111111111*
-L043278 111111011111111111111111111111111111110111111111111111111111111111*
+L043212 111111111111111111110111011111111111111111110111111111111111111111*
+L043278 111111111111111111111111111111111111111111110111111111110111111111*
L043344
000000000000000000000000000000000000000000000000000000000000000000*
L043410 111111111111111111111111111111111111111111111111111111111111111111*
@@ -877,15 +878,15 @@ L043938 111111111111111111111111111111111111111111111111111111111111111111*
L044004 111111111111111111111111111111111111111111111111111111111111111111*
L044070
000000000000000000000000000000000000000000000000000000000000000000*
-L044136 111111011111111111111111101111111111111011111111111111111111111111*
-L044202 111111111111111111111111111111111111111111011111111111111111111111*
-L044268 101111111111111111111111111111111111111111111111111111111111111111*
-L044334 111111011111111111111111111111111111111011111111111111101111111111*
-L044400 111111111111111111111111110111111111111011111111111111111111111111*
-L044466 111111111111111111101111111111111111111111111111111111101111111111*
-L044532 111111111111111111111111111111111111111111011111111111111111111111*
+L044136 111111011111111111111111111111111111111111111111111111111111111111*
+L044202 111111111111111111111111111111111111111111111111111111111111111111*
+L044268 111111111111111111111111111111111111111111111111111111111111111111*
+L044334 111111111111111111111111111111111111111111111111111111111111111111*
+L044400 111111111111111111111111111111111111111111111111111111111111111111*
+L044466 111111111111111111111011111111111111111011111111111111111111111111*
+L044532 111111110111111111111111111111111111111111111111111111111111111111*
L044598 101111111111111111111111111111111111111111111111111111111111111111*
-L044664 111101011111111111111101111110111010110111111111101111111111111111*
+L044664 111101111111111011111101111110111010111111110111111111110111111111*
L044730 000000000000000000000000000000000000000000000000000000000000000000*
L044796
000000000000000000000000000000000000000000000000000000000000000000*
@@ -901,15 +902,15 @@ L045390 111111111111111111111111111111111111111111111111111111111111111111*
L045456 111111111111111111111111111111111111111111111111111111111111111111*
L045522
000000000000000000000000000000000000000000000000000000000000000000*
-L045588 111111111111110111111111111111111111111011111111111111111111111111*
-L045654 111111111111111111111111111111111111111111011111111111111111111111*
+L045588 110111111111111111111111111111111111111111111101111111111111111111*
+L045654 111111110111111111111111111111111111111111111111111111111111111111*
L045720 101111111111111111111111111111111111111111111111111111111111111111*
-L045786 111111111111111111111111111111011111111011111111111111111111111111*
-L045852 000000000000000000000000000000000000000000000000000000000000000000*
-L045918 111111111111111111101111101111111111111111111111111111111111111111*
-L045984 111111111111111111111111111111111111111111011111111111111111111111*
+L045786 111111111111111111111111111011111111111111111101111111111111111111*
+L045852 111111111111111111111111111111111111111111111111011111110111111111*
+L045918 111111111111111111111111101111111111111011111111111111111111111111*
+L045984 111111110111111111111111111111111111111111111111111111111111111111*
L046050 101111111111111111111111111111111111111111111111111111111111111111*
-L046116 111111011111111111111111111111111111110111111110011111111111111111*
+L046116 111111111111110111101111111111111111111111110111111111110111111111*
L046182 000000000000000000000000000000000000000000000000000000000000000000*
L046248
000000000000000000000000000000000000000000000000000000000000000000*
@@ -928,14 +929,14 @@ L046974
000000000000000000000000000000000000000000000000000000000000000000*
L047106 0010*
L047110 00100110010000*
-L047124 00010110011110*
+L047124 10101110001110*
L047138 11011111110100*
L047152 11111011111111*
L047166 10100111011000*
L047180 10101110000010*
L047194 11011111110001*
L047208 11111011110011*
-L047222 10101110000000*
+L047222 00110110010000*
L047236 11101100000010*
L047250 11011111110000*
L047264 11110011110011*
@@ -945,15 +946,15 @@ L047306 11011011110001*
L047320 11110111111110*
NOTE BLOCK 7 *
L047334
- 111111111111111111111111111101111111111110111111111111111111111111
- 111111111111111111111111111111011111111111101111111111111111111111
- 111111111111101111111111111011111111111111111111111111111111111111
+ 111111111111111011111111111111111111111110111111111111111111111111
+ 111111111001111111111111111111111111111111111111111111111111111111
+ 111111111111101111111111111111111111111111111111111111111011111111
111011111111111110111111111111111111111111111111111111111111111111
111111111111111111111111111111111111111111111111111111111111111111
- 111111111111111111111111011111111111011011111111111111111101111111
- 111111101110111111111101111111111101111111111111111111111111111111
- 111111111111111011101111111111111111111111111110011111101111111111
- 101111111011111111111011111111111111111111111111111111111111101111*
+ 111111111111111111111111011111111111011111111111111111111101111111
+ 111111101111111111111101111111111101111111111111111111101111111111
+ 111111111111111111101111111011111111111111101110011111111111111111
+ 101111111111111111110111111110111111111011111111111111111111101111*
L047928
000000000000000000000000000000000000000000000000000000000000000000*
L047994 110111111111011101101110101111111110011101111111111111111111111111*
@@ -961,16 +962,16 @@ L048060 111111111111111111101111111111111111111110111111111111111111101111*
L048126 000000000000000000000000000000000000000000000000000000000000000000*
L048192 000000000000000000000000000000000000000000000000000000000000000000*
L048258 000000000000000000000000000000000000000000000000000000000000000000*
-L048324 111111111111111111111111111101111111111111111111111111111111111111*
-L048390 111111111111111111111111111111111111111111011111111111111111111111*
-L048456 000000000000000000000000000000000000000000000000000000000000000000*
-L048522 000000000000000000000000000000000000000000000000000000000000000000*
+L048324 111111111111111111011111111111111111111111111111111111111111111111*
+L048390 111111111110111111111111111111111111111101111111111111111111111111*
+L048456 110111111111011101111110101111111110011101111111111111111111111111*
+L048522 111111111111111111111111111111111111110110111111111111111111111111*
L048588 000000000000000000000000000000000000000000000000000000000000000000*
L048654
000000000000000000000000000000000000000000000000000000000000000000*
-L048720 111111110111111111110111111111111111111111111111111111111111111111*
-L048786 111111111111111111110111110111111111111111111111111111111111111111*
-L048852 111111110111111111111111111011111111111111111111111111101111111111*
+L048720 111111111111110111111111110111111111111111111111111111111110111111*
+L048786 111111111111111111111111111101111111111111111111101111111111111111*
+L048852 111111111111111111111111111101111111111111111111111111111011111111*
L048918 000000000000000000000000000000000000000000000000000000000000000000*
L048984 000000000000000000000000000000000000000000000000000000000000000000*
L049050 111111111111111111111111111111111111111111111111111111111111111111*
@@ -981,19 +982,19 @@ L049314 111111111111111111111111111111111111111111111111111111111111111111*
L049380
111111111111111111111111111111111111111111111111111111111111111111*
L049446 111111111111111111111111111111111111011111111101111111111111111111*
-L049512 111111111111111111110111111111111111011111111111111111111110111111*
+L049512 111111111111111111111111111111111111011111111111111111110110111111*
L049578 000000000000000000000000000000000000000000000000000000000000000000*
L049644 000000000000000000000000000000000000000000000000000000000000000000*
L049710 000000000000000000000000000000000000000000000000000000000000000000*
-L049776 111111111111110111111111111111111111111111111111111111101111111111*
-L049842 111111111111111111111111111111111111111111011111111111111111111111*
+L049776 111111111111111111111111111011111111111111011111111111111111111111*
+L049842 111111110111111111111111111111111111111111111111111111111111111111*
L049908 000000000000000000000000000000000000000000000000000000000000000000*
-L049974 111111111111111011111111111111111111111111111111111111011111111111*
+L049974 111111111111111111111111110111111111111111101111111111111111111111*
L050040 000000000000000000000000000000000000000000000000000000000000000000*
L050106
000000000000000000000000000000000000000000000000000000000000000000*
-L050172 111111111111111011111111111111111111111111111111111111111111111111*
-L050238 111111111111111111111111111111111111111111011111111111111111111111*
+L050172 111111111111111111111111111111111111111111101111111111111111111111*
+L050238 111111110111111111111111111111111111111111111111111111111111111111*
L050304 000000000000000000000000000000000000000000000000000000000000000000*
L050370 111111111111111111111111111111111111111111111111111111111111111111*
L050436 111111111111111111111111111111111111111111111111111111111111111111*
@@ -1003,19 +1004,19 @@ L050634 111111111111111111111111111111111111111111111111111111111111111111*
L050700 111111111111111111111111111111111111111111111111111111111111111111*
L050766 111111111111111111111111111111111111111111111111111111111111111111*
L050832
- 111111111111111111111111111111101111111111111111111111111111111111*
-L050898 111111110111111111111011111111111111111111111111111111011111111111*
-L050964 111111101111111111101111111111111111111111111111111111111111111111*
+ 111111111101111111111111111111111111111111111111111111111111111111*
+L050898 111111101111111111101111111111111111111111111111111111111111111111*
+L050964 111111111111110111111111110111111111111111111111111111111110111111*
L051030 000000000000000000000000000000000000000000000000000000000000000000*
L051096 000000000000000000000000000000000000000000000000000000000000000000*
L051162 000000000000000000000000000000000000000000000000000000000000000000*
-L051228 111111111101111111110111111111111111111111111111111111111111111111*
-L051294 111111111111111111110111111111111111110111111111011111111111111111*
+L051228 111111111111111111111111111111111111111111111111111111010111111111*
+L051294 111111111111111111111111111101111111111111111111011111110111111111*
L051360 000000000000000000000000000000000000000000000000000000000000000000*
L051426 000000000000000000000000000000000000000000000000000000000000000000*
L051492 000000000000000000000000000000000000000000000000000000000000000000*
L051558
- 111111111111111111111111111111101111111111111111111111111111111111*
+ 111111111101111111111111111111111111111111111111111111111111111111*
L051624 111111111111111111111111111111111111111111111111111111111111111111*
L051690 111111111111111111111111111111111111111111111111111111111111111111*
L051756 111111111111111111111111111111111111111111111111111111111111111111*
@@ -1033,11 +1034,11 @@ L052416 111111111111111111111111111111111111111111111111111111111111111111*
L052482 111111111111111111111111111111111111111111111111111111111111111111*
L052548 111111111111111111111111111111111111111111111111111111111111111111*
L052614 111111111111111111111111111111111111111111111111111111111111111111*
-L052680 111111110111111111111011111111111111111111111111111111011111111111*
-L052746 111111111111111111111111111111111111110111111111101111111111111111*
-L052812 111111111111111111111011111111111111110111111111111111111111111111*
-L052878 000000000000000000000000000000000000000000000000000000000000000000*
-L052944 000000000000000000000000000000000000000000000000000000000000000000*
+L052680 111111111111111111110111111111111111111111111111111111111111111111*
+L052746 111111110111111111111111111111111111111111111111111111111111111111*
+L052812 000000000000000000000000000000000000000000000000000000000000000000*
+L052878 111111111111111111111111111111111111111111111111111111111111111111*
+L052944 111111111111111111111111111111111111111111111111111111111111111111*
L053010
111111111111111111111111111111111111111111111111111111111111111111*
L053076 111111111111111111111111111111111111111111111111111111111111111111*
@@ -1055,7 +1056,7 @@ L053736
101111111111111111111111111111111111111111111111111111111111111111*
L053868 0010*
L053872 11100110011000*
-L053886 00101110000010*
+L053886 10100110010010*
L053900 10100100010000*
L053914 11100011110011*
L053928 10100110010001*
@@ -1067,7 +1068,7 @@ L053998 10100110010011*
L054012 11011011110100*
L054026 11111111111110*
L054040 00110011111000*
-L054054 10100100010011*
+L054054 00001110000011*
L054068 11011011110100*
L054082 11111111111110*
E1
@@ -1089,6 +1090,6 @@ E1
00000000
1
*
-CDE1F*
+CF4AD*
U00000000000000000000000000000000*
-A145
+A5B2
diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco
index 967a9aa..344e44c 100644
--- a/Logic/68030_tk.lco
+++ b/Logic/68030_tk.lco
@@ -16,8 +16,8 @@ RCS = "$Revision: 1.2 $";
Parent = m4a5.lci;
SDS_File = m4a5.sds;
Design = 68030_tk.tt4;
-DATE = 5/15/14;
-TIME = 23:02:50;
+DATE = 5/16/14;
+TIME = 17:07:12;
Source_Format = Pure_VHDL;
Type = TT2;
Pre_Fit_Time = 1;
@@ -76,31 +76,27 @@ Usercode_Format = Hex;
[LOCATION ASSIGNMENTS]
Layer = OFF;
-A_21_ = pin,94,-,A,-;
-A_20_ = pin,93,-,A,-;
-SIZE_1_ = pin,79,-,H,-;
-A_19_ = pin,97,-,A,-;
-A_18_ = pin,95,-,A,-;
-A_31_ = pin,4,-,B,-;
A_17_ = pin,59,-,F,-;
A_16_ = pin,96,-,A,-;
+SIZE_1_ = pin,79,-,H,-;
+A_31_ = pin,4,-,B,-;
IPL_2_ = pin,68,-,G,-;
FC_1_ = pin,58,-,F,-;
AS_030 = pin,82,-,H,-;
DS_030 = pin,98,-,A,-;
-CPU_SPACE = pin,14,-,-,-;
+A_0_ = pin,69,-,G,-;
+nEXP_SPACE = pin,14,-,-,-;
BERR = pin,41,-,E,-;
BG_030 = pin,21,-,C,-;
-A_0_ = pin,69,-,G,-;
-BGACK_000 = pin,28,-,D,-;
-CLK_030 = pin,64,-,-,-;
IPL_1_ = pin,56,-,F,-;
-CLK_000 = pin,11,-,-,-;
IPL_0_ = pin,67,-,G,-;
-CLK_OSZI = pin,61,-,-,-;
DSACK_0_ = pin,80,-,H,-;
-CLK_DIV_OUT = pin,65,-,G,-;
+BGACK_000 = pin,28,-,D,-;
FC_0_ = pin,57,-,F,-;
+CLK_030 = pin,64,-,-,-;
+CLK_000 = pin,11,-,-,-;
+CLK_OSZI = pin,61,-,-,-;
+CLK_DIV_OUT = pin,65,-,G,-;
AVEC = pin,92,-,A,-;
AVEC_EXP = pin,22,-,C,-;
VPA = pin,36,-,-,-;
@@ -120,15 +116,19 @@ A_25_ = pin,18,-,C,-;
A_24_ = pin,19,-,C,-;
A_23_ = pin,84,-,H,-;
A_22_ = pin,85,-,H,-;
+A_21_ = pin,94,-,A,-;
+A_20_ = pin,93,-,A,-;
+A_19_ = pin,97,-,A,-;
+A_18_ = pin,95,-,A,-;
IPL_030_2_ = pin,9,-,B,-;
DSACK_1_ = pin,81,-,H,-;
AS_000 = pin,33,-,D,-;
UDS_000 = pin,32,-,D,-;
LDS_000 = pin,31,-,D,-;
-BG_000 = pin,29,-,D,-;
-BGACK_030 = pin,83,-,H,-;
IPL_030_1_ = pin,7,-,B,-;
IPL_030_0_ = pin,8,-,B,-;
+BG_000 = pin,29,-,D,-;
+BGACK_030 = pin,83,-,H,-;
CLK_EXP = pin,10,-,B,-;
FPU_CS = pin,78,-,H,-;
DTACK = pin,30,-,D,-;
@@ -137,23 +137,23 @@ VMA = pin,35,-,D,-;
RESET = pin,3,-,B,-;
cpu_est_0_ = node,-,-,D,14;
cpu_est_1_ = node,-,-,D,2;
-inst_AS_030_000_SYNC = node,-,-,F,0;
+inst_AS_030_000_SYNC = node,-,-,H,1;
inst_DTACK_SYNC = node,-,-,G,13;
-inst_VPA_D = node,-,-,G,1;
+inst_VPA_D = node,-,-,H,13;
inst_VPA_SYNC = node,-,-,G,9;
-inst_CLK_000_D = node,-,-,H,1;
-inst_CLK_000_DD = node,-,-,D,13;
+inst_CLK_000_D0 = node,-,-,G,8;
+inst_CLK_000_D1 = node,-,-,D,13;
inst_CLK_OUT_PRE = node,-,-,H,5;
cpu_est_2_ = node,-,-,D,10;
CLK_CNT_0_ = node,-,-,H,6;
SM_AMIGA_6_ = node,-,-,D,6;
SM_AMIGA_7_ = node,-,-,H,9;
-SM_AMIGA_1_ = node,-,-,H,2;
-SM_AMIGA_4_ = node,-,-,G,12;
+SM_AMIGA_1_ = node,-,-,G,12;
+SM_AMIGA_4_ = node,-,-,F,0;
SM_AMIGA_3_ = node,-,-,G,5;
SM_AMIGA_5_ = node,-,-,A,0;
-SM_AMIGA_2_ = node,-,-,G,8;
-SM_AMIGA_0_ = node,-,-,H,13;
+SM_AMIGA_2_ = node,-,-,G,1;
+SM_AMIGA_0_ = node,-,-,H,2;
[GROUP ASSIGNMENTS]
Layer = OFF;
diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out
index 6347986..69bdd83 100644
--- a/Logic/68030_tk.out
+++ b/Logic/68030_tk.out
@@ -49428,4 +49428,1845 @@
10 CLK_000 1 -1 -1 1 7 10 -1
5 A_29_ 1 -1 -1 1 4 5 -1
4 A_30_ 1 -1 -1 1 4 4 -1
- 3 A_31_ 1 -1 -1 1 4 3 -1
\ No newline at end of file
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+90 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 313 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 316 3 0 30 -1 12 0 21
+ 31 UDS_000 5 315 3 0 31 -1 8 0 21
+ 65 E 5 322 6 0 65 -1 3 0 21
+ 28 BG_000 5 317 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 312 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 318 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 321 7 0 77 -1 2 0 21
+ 34 VMA 5 323 3 0 34 -1 2 0 21
+ 32 AS_000 5 314 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 300 inst_CLK_000_DD 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20
+ 299 inst_CLK_000_D 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20
+ 295 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 4 0 21
+ 321 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 301 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 322 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 310 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 304 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 3 0 21
+ 302 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 293 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20
+ 323 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 318 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 314 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 309 SM_AMIGA_5_ 3 -1 0 2 0 6 -1 -1 2 0 21
+ 307 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20
+ 305 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 297 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21
+ 316 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 315 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 312 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 311 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21
+ 308 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 306 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 3 0 21
+ 313 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 298 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 296 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 303 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1
+ 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 4 3 5 6 7 81 -1
+ 63 CLK_030 1 -1 -1 3 3 5 7 63 -1
+ 13 CPU_SPACE 1 -1 -1 3 3 5 7 13 -1
+ 96 A_19_ 1 -1 -1 2 5 7 96 -1
+ 95 A_16_ 1 -1 -1 2 5 7 95 -1
+ 94 A_18_ 1 -1 -1 2 5 7 94 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 58 A_17_ 1 -1 -1 2 5 7 58 -1
+ 57 FC_1_ 1 -1 -1 2 5 7 57 -1
+ 56 FC_0_ 1 -1 -1 2 5 7 56 -1
+ 27 BGACK_000 1 -1 -1 2 5 7 27 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 6 35 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 7 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+90 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 313 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 316 3 0 30 -1 12 0 21
+ 31 UDS_000 5 315 3 0 31 -1 8 0 21
+ 65 E 5 322 6 0 65 -1 3 0 21
+ 28 BG_000 5 317 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 312 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 318 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 321 7 0 77 -1 2 0 21
+ 34 VMA 5 323 3 0 34 -1 2 0 21
+ 32 AS_000 5 314 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 300 inst_CLK_000_DD 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20
+ 299 inst_CLK_000_D 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20
+ 295 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 4 0 21
+ 321 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 301 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 294 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 322 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 310 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 304 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 3 0 21
+ 302 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 293 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20
+ 323 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 318 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 314 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 309 SM_AMIGA_5_ 3 -1 0 2 0 6 -1 -1 2 0 21
+ 307 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20
+ 305 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 297 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21
+ 316 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 315 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 317 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 312 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 311 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21
+ 308 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 306 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 3 0 21
+ 313 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 298 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 296 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 303 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1
+ 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 4 3 5 6 7 81 -1
+ 63 CLK_030 1 -1 -1 3 3 5 7 63 -1
+ 13 CPU_SPACE 1 -1 -1 3 3 5 7 13 -1
+ 96 A_19_ 1 -1 -1 2 5 7 96 -1
+ 95 A_16_ 1 -1 -1 2 5 7 95 -1
+ 94 A_18_ 1 -1 -1 2 5 7 94 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 58 A_17_ 1 -1 -1 2 5 7 58 -1
+ 57 FC_1_ 1 -1 -1 2 5 7 57 -1
+ 56 FC_0_ 1 -1 -1 2 5 7 56 -1
+ 27 BGACK_000 1 -1 -1 2 5 7 27 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 6 35 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 7 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+90 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 314 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 317 3 0 30 -1 12 0 21
+ 31 UDS_000 5 316 3 0 31 -1 8 0 21
+ 65 E 5 323 6 0 65 -1 3 0 21
+ 28 BG_000 5 318 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 313 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 321 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 320 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 322 7 0 77 -1 2 0 21
+ 34 VMA 5 324 3 0 34 -1 2 0 21
+ 32 AS_000 5 315 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 301 inst_CLK_000_DD 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20
+ 300 inst_CLK_000_D 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20
+ 296 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 4 0 21
+ 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 323 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 311 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 305 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20
+ 324 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 320 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 315 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 310 SM_AMIGA_5_ 3 -1 0 2 0 6 -1 -1 2 0 21
+ 308 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20
+ 306 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 298 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21
+ 317 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 316 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 321 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 318 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 313 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 312 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21
+ 309 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 307 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 3 0 21
+ 314 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 304 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1
+ 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 4 3 5 6 7 81 -1
+ 63 CLK_030 1 -1 -1 3 3 5 7 63 -1
+ 96 A_19_ 1 -1 -1 2 5 7 96 -1
+ 95 A_16_ 1 -1 -1 2 5 7 95 -1
+ 94 A_18_ 1 -1 -1 2 5 7 94 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 58 A_17_ 1 -1 -1 2 5 7 58 -1
+ 57 FC_1_ 1 -1 -1 2 5 7 57 -1
+ 56 FC_0_ 1 -1 -1 2 5 7 56 -1
+ 27 BGACK_000 1 -1 -1 2 5 7 27 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 6 35 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 7 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 3 3 5 7 -1 -1
+90 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 314 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 317 3 0 30 -1 12 0 21
+ 31 UDS_000 5 316 3 0 31 -1 8 0 21
+ 65 E 5 323 6 0 65 -1 3 0 21
+ 28 BG_000 5 320 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 313 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 321 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 322 7 0 77 -1 2 0 21
+ 34 VMA 5 324 3 0 34 -1 2 0 21
+ 32 AS_000 5 315 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 301 inst_CLK_000_DD 3 -1 3 5 1 3 5 6 7 -1 -1 1 0 20
+ 300 inst_CLK_000_D 3 -1 0 5 1 3 5 6 7 -1 -1 1 0 21
+ 296 inst_AS_030_000_SYNC 3 -1 7 3 3 5 7 -1 -1 4 0 21
+ 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 323 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 305 SM_AMIGA_6_ 3 -1 3 2 3 5 -1 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20
+ 324 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 321 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 315 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 312 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 2 0 20
+ 310 SM_AMIGA_5_ 3 -1 5 2 5 6 -1 -1 2 0 21
+ 308 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20
+ 306 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20
+ 317 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 316 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 320 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 313 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 311 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20
+ 309 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 307 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21
+ 314 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 304 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1
+ 85 RST 1 -1 -1 5 1 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 3 3 6 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 0 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1
+90 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 314 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 317 3 0 30 -1 12 0 21
+ 31 UDS_000 5 316 3 0 31 -1 8 0 21
+ 65 E 5 323 6 0 65 -1 3 0 21
+ 28 BG_000 5 320 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 313 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 321 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 322 7 0 77 -1 2 0 21
+ 34 VMA 5 324 3 0 34 -1 2 0 21
+ 32 AS_000 5 315 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 301 inst_CLK_000_DD 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20
+ 300 inst_CLK_000_D 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20
+ 296 inst_AS_030_000_SYNC 3 -1 7 3 0 3 7 -1 -1 4 0 21
+ 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 306 SM_AMIGA_7_ 3 -1 7 3 0 3 7 -1 -1 2 0 21
+ 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 323 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 309 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 305 SM_AMIGA_6_ 3 -1 0 2 0 3 -1 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20
+ 324 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 321 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 315 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 310 SM_AMIGA_5_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 307 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20
+ 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20
+ 317 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 316 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 320 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 313 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 312 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21
+ 311 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20
+ 308 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 314 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 304 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 4 1 3 6 7 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 81 AS_030 1 -1 -1 3 3 6 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 10 CLK_000 1 -1 -1 2 6 7 10 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1
+90 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 314 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 317 3 0 30 -1 12 0 21
+ 31 UDS_000 5 316 3 0 31 -1 8 0 21
+ 65 E 5 323 6 0 65 -1 3 0 21
+ 28 BG_000 5 320 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 313 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 321 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 322 7 0 77 -1 2 0 21
+ 34 VMA 5 324 3 0 34 -1 2 0 21
+ 32 AS_000 5 315 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 300 inst_CLK_000_D 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
+ 301 inst_CLK_000_DD 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20
+ 296 inst_AS_030_000_SYNC 3 -1 7 3 0 3 7 -1 -1 4 0 21
+ 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 308 SM_AMIGA_4_ 3 -1 5 3 3 5 6 -1 -1 2 0 21
+ 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 323 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 307 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 305 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20
+ 324 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 321 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 315 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 310 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 2 0 21
+ 306 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20
+ 317 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 316 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 320 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 313 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 312 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21
+ 311 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20
+ 309 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 314 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 304 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1
+ 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 3 3 6 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 6 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1
+90 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 314 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 5 29 -1 1 0 21
+ 30 LDS_000 5 319 3 0 30 -1 12 0 21
+ 31 UDS_000 5 317 3 0 31 -1 8 0 21
+ 65 E 5 323 6 0 65 -1 3 0 21
+ 28 BG_000 5 320 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 313 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 318 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 316 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 321 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 322 7 0 77 -1 2 0 21
+ 34 VMA 5 324 3 0 34 -1 2 0 21
+ 32 AS_000 5 315 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 300 inst_CLK_000_D 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
+ 301 inst_CLK_000_DD 3 -1 3 4 1 3 6 7 -1 -1 1 0 20
+ 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21
+ 295 cpu_est_1_ 3 -1 3 3 0 3 6 -1 -1 4 0 20
+ 323 RN_E 3 65 6 3 0 3 6 65 -1 3 0 21
+ 309 SM_AMIGA_3_ 3 -1 1 3 0 1 5 -1 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 3 0 3 6 -1 -1 3 1 20
+ 294 cpu_est_0_ 3 -1 3 3 0 3 6 -1 -1 3 0 20
+ 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 308 SM_AMIGA_4_ 3 -1 6 3 1 3 6 -1 -1 2 0 20
+ 298 inst_VPA_D 3 -1 7 3 0 3 5 -1 -1 1 0 20
+ 311 SM_AMIGA_2_ 3 -1 1 2 1 7 -1 -1 3 0 21
+ 305 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 3 0 21
+ 324 RN_VMA 3 34 3 2 0 3 34 -1 2 0 21
+ 321 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 315 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21
+ 307 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 2 0 21
+ 306 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20
+ 302 inst_CLK_OUT_PRE 3 -1 6 2 1 6 -1 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 0 2 0 1 -1 -1 2 0 21
+ 297 inst_DTACK_SYNC 3 -1 5 2 1 5 -1 -1 2 0 21
+ 304 CLK_CNT_0_ 3 -1 1 2 1 6 -1 -1 1 0 20
+ 319 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 317 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 320 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 318 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 316 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 313 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 312 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 3 0 20
+ 314 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 310 SM_AMIGA_5_ 3 -1 6 1 6 -1 -1 2 0 20
+ 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1
+ 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 6 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1
+93 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 317 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 320 3 0 30 -1 12 0 21
+ 31 UDS_000 5 319 3 0 31 -1 8 0 21
+ 65 E 5 324 6 0 65 -1 3 0 21
+ 28 BG_000 5 321 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 327 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 325 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 322 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 323 7 0 77 -1 2 0 21
+ 34 VMA 5 326 3 0 34 -1 2 0 21
+ 32 AS_000 5 318 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 301 inst_CLK_000_DD 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20
+ 300 inst_CLK_000_D 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20
+ 296 inst_AS_030_000_SYNC 3 -1 7 3 3 6 7 -1 -1 4 0 21
+ 294 cpu_est_0_ 3 -1 0 3 0 3 6 -1 -1 3 0 21
+ 323 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 318 RN_AS_000 3 32 3 3 3 6 7 32 -1 2 0 21
+ 308 SM_AMIGA_4_ 3 -1 7 3 3 6 7 -1 -1 2 0 21
+ 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 315 SM_AMIGA_0_ 3 -1 7 2 6 7 -1 -1 3 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 305 SM_AMIGA_6_ 3 -1 3 2 3 6 -1 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 326 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 313 SM_AMIGA_5_ 3 -1 6 2 6 7 -1 -1 2 0 20
+ 306 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20
+ 298 inst_VPA_D 3 -1 3 2 3 6 -1 -1 1 0 20
+ 320 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 319 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 307 CLK_000_CNT_2_ 3 -1 7 1 7 -1 -1 5 0 20
+ 312 CLK_000_CNT_1_ 3 -1 7 1 7 -1 -1 4 0 20
+ 327 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 325 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 310 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 3 0 21
+ 309 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 311 CLK_000_CNT_0_ 3 -1 7 1 7 -1 -1 2 0 20
+ 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 304 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1
+ 85 RST 1 -1 -1 4 1 3 6 7 85 -1
+ 81 AS_030 1 -1 -1 3 3 6 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 3 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 7 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1
+93 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 317 7 1 3 80 -1 3 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 320 3 0 30 -1 12 0 21
+ 31 UDS_000 5 319 3 0 31 -1 8 0 21
+ 65 E 5 324 6 0 65 -1 3 0 21
+ 28 BG_000 5 321 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 316 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 327 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 326 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 322 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 323 7 0 77 -1 2 0 21
+ 34 VMA 5 325 3 0 34 -1 2 0 21
+ 32 AS_000 5 318 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 300 inst_CLK_000_D 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20
+ 301 inst_CLK_000_DD 3 -1 7 4 1 3 6 7 -1 -1 1 0 20
+ 294 cpu_est_0_ 3 -1 7 3 3 6 7 -1 -1 3 0 20
+ 323 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 318 RN_AS_000 3 32 3 3 0 3 6 32 -1 2 0 21
+ 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 308 CLK_000_CNT_2_ 3 -1 7 2 6 7 -1 -1 5 0 20
+ 315 SM_AMIGA_0_ 3 -1 6 2 0 6 -1 -1 4 0 20
+ 312 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 4 0 20
+ 307 CLK_000_CNT_1_ 3 -1 7 2 6 7 -1 -1 4 0 20
+ 296 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21
+ 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 309 SM_AMIGA_4_ 3 -1 3 2 3 6 -1 -1 2 0 21
+ 306 SM_AMIGA_7_ 3 -1 0 2 0 3 -1 -1 2 0 21
+ 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20
+ 320 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 319 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 327 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 326 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 321 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 317 RN_DSACK_1_ 3 80 7 1 7 80 -1 3 0 21
+ 316 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 314 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20
+ 310 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 305 SM_AMIGA_6_ 3 -1 3 1 3 -1 -1 3 0 21
+ 313 SM_AMIGA_5_ 3 -1 3 1 3 -1 -1 2 0 21
+ 311 CLK_000_CNT_0_ 3 -1 7 1 7 -1 -1 2 0 20
+ 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 304 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 4 1 3 6 7 60 -1
+ 85 RST 1 -1 -1 5 0 1 3 6 7 85 -1
+ 81 AS_030 1 -1 -1 3 3 6 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 7 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1
+92 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 316 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 0 29 -1 1 0 21
+ 30 LDS_000 5 319 3 0 30 -1 12 0 21
+ 31 UDS_000 5 318 3 0 31 -1 8 0 21
+ 65 E 5 325 6 0 65 -1 3 0 21
+ 28 BG_000 5 320 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 315 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 323 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 321 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 322 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 324 7 0 77 -1 2 0 21
+ 34 VMA 5 326 3 0 34 -1 2 0 21
+ 32 AS_000 5 317 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 300 inst_CLK_000_D0 3 -1 0 6 0 1 3 5 6 7 -1 -1 1 0 20
+ 301 inst_CLK_000_D1 3 -1 3 4 1 3 6 7 -1 -1 1 0 20
+ 295 cpu_est_1_ 3 -1 3 3 3 5 6 -1 -1 4 0 20
+ 325 RN_E 3 65 6 3 3 5 6 65 -1 3 0 21
+ 310 SM_AMIGA_3_ 3 -1 6 3 0 5 6 -1 -1 3 0 20
+ 304 cpu_est_2_ 3 -1 6 3 3 5 6 -1 -1 3 1 21
+ 294 cpu_est_0_ 3 -1 3 3 3 5 6 -1 -1 3 0 20
+ 324 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 309 SM_AMIGA_4_ 3 -1 7 3 3 6 7 -1 -1 2 0 21
+ 303 inst_CLK_OUT_PRE 3 -1 6 3 1 6 7 -1 -1 2 0 21
+ 298 inst_VPA_D 3 -1 6 3 0 3 5 -1 -1 1 0 21
+ 296 inst_AS_030_000_SYNC 3 -1 7 2 3 7 -1 -1 4 0 21
+ 313 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 306 SM_AMIGA_6_ 3 -1 3 2 3 7 -1 -1 3 0 21
+ 326 RN_VMA 3 34 3 2 3 5 34 -1 2 0 21
+ 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 317 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 307 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 5 2 5 6 -1 -1 2 0 21
+ 297 inst_DTACK_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21
+ 319 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 318 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 323 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 321 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 320 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 315 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 314 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21
+ 311 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 3 0 21
+ 316 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 312 SM_AMIGA_5_ 3 -1 7 1 7 -1 -1 2 0 21
+ 308 inst_CLK_000_D2 3 -1 3 1 6 -1 -1 1 0 20
+ 305 CLK_CNT_0_ 3 -1 6 1 6 -1 -1 1 0 21
+ 302 inst_CLK_000_D3 3 -1 6 1 7 -1 -1 1 0 21
+ 60 CLK_OSZI 9 -1 5 0 1 3 5 6 60 -1
+ 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 4 0 3 5 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 6 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 0 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1
+91 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 315 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 318 3 0 30 -1 12 0 21
+ 31 UDS_000 5 317 3 0 31 -1 8 0 21
+ 65 E 5 324 6 0 65 -1 3 0 21
+ 28 BG_000 5 320 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 314 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 321 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 322 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 323 7 0 77 -1 2 0 21
+ 34 VMA 5 325 3 0 34 -1 2 0 21
+ 32 AS_000 5 316 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 300 inst_CLK_000_D0 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
+ 301 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20
+ 303 inst_CLK_OUT_PRE 3 -1 7 4 1 5 6 7 -1 -1 2 0 20
+ 296 inst_AS_030_000_SYNC 3 -1 7 3 0 3 7 -1 -1 4 0 21
+ 306 SM_AMIGA_6_ 3 -1 7 3 0 3 7 -1 -1 3 0 21
+ 323 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 324 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 312 SM_AMIGA_2_ 3 -1 6 2 5 6 -1 -1 3 0 20
+ 310 SM_AMIGA_1_ 3 -1 5 2 5 7 -1 -1 3 0 21
+ 304 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20
+ 325 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 322 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 316 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 311 SM_AMIGA_5_ 3 -1 0 2 0 6 -1 -1 2 0 21
+ 308 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20
+ 307 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 305 CLK_CNT_0_ 3 -1 6 2 6 7 -1 -1 1 0 21
+ 302 inst_CLK_000_D2 3 -1 3 2 5 7 -1 -1 1 0 20
+ 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20
+ 318 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 317 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 321 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 320 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 314 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 313 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21
+ 309 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 315 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1
+ 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 3 3 6 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 6 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1
+90 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 314 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 317 3 0 30 -1 12 0 21
+ 31 UDS_000 5 316 3 0 31 -1 8 0 21
+ 65 E 5 323 6 0 65 -1 3 0 21
+ 28 BG_000 5 320 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 313 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 321 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 322 7 0 77 -1 2 0 21
+ 34 VMA 5 324 3 0 34 -1 2 0 21
+ 32 AS_000 5 315 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 300 inst_CLK_000_D0 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
+ 301 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20
+ 296 inst_AS_030_000_SYNC 3 -1 7 3 0 3 7 -1 -1 4 0 21
+ 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 308 SM_AMIGA_4_ 3 -1 5 3 3 5 6 -1 -1 2 0 21
+ 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 323 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 307 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 305 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20
+ 324 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 321 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 315 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 310 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 2 0 21
+ 306 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20
+ 317 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 316 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 320 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 313 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 312 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21
+ 311 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20
+ 309 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 314 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 304 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1
+ 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 3 3 6 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 6 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1
+94 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 0 29 -1 1 0 21
+ 30 LDS_000 5 321 3 0 30 -1 12 0 21
+ 31 UDS_000 5 320 3 0 31 -1 8 0 21
+ 65 E 5 327 6 0 65 -1 3 0 21
+ 28 BG_000 5 322 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 325 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 324 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 323 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 326 7 0 77 -1 2 0 21
+ 34 VMA 5 328 3 0 34 -1 2 0 21
+ 32 AS_000 5 319 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 300 inst_CLK_000_D0 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 20
+ 301 inst_CLK_000_D1 3 -1 3 6 0 1 2 3 6 7 -1 -1 1 0 20
+ 296 inst_AS_030_000_SYNC 3 -1 7 4 0 2 3 7 -1 -1 4 0 21
+ 305 SM_AMIGA_6_ 3 -1 0 3 0 2 3 -1 -1 3 0 21
+ 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 319 RN_AS_000 3 32 3 3 3 5 6 32 -1 2 0 21
+ 306 SM_AMIGA_7_ 3 -1 5 3 0 3 5 -1 -1 2 0 21
+ 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 298 inst_VPA_D 3 -1 6 3 0 3 6 -1 -1 1 0 21
+ 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 327 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 316 SM_AMIGA_0_ 3 -1 6 2 5 6 -1 -1 3 0 20
+ 315 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 312 SM_AMIGA_3_ 3 -1 6 2 0 6 -1 -1 3 0 20
+ 307 SM_AMIGA_1_ 3 -1 7 2 6 7 -1 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20
+ 328 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 314 SM_AMIGA_5_ 3 -1 2 2 2 6 -1 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20
+ 297 inst_DTACK_SYNC 3 -1 0 2 0 6 -1 -1 2 0 21
+ 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 325 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 324 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 313 inst_CLK_000_D4 3 -1 5 1 6 -1 -1 1 0 20
+ 311 inst_CLK_000_D3 3 -1 7 1 5 -1 -1 1 0 20
+ 309 inst_CLK_000_D2 3 -1 3 1 7 -1 -1 1 0 20
+ 308 inst_CLK_000_D5 3 -1 6 1 7 -1 -1 1 0 21
+ 304 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 7 0 1 2 3 5 6 7 60 -1
+ 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 4 0 3 6 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 6 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 7 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1
+94 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 318 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 5 29 -1 1 0 21
+ 30 LDS_000 5 321 3 0 30 -1 12 0 21
+ 31 UDS_000 5 320 3 0 31 -1 8 0 21
+ 65 E 5 327 6 0 65 -1 3 0 21
+ 28 BG_000 5 322 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 317 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 325 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 324 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 323 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 326 7 0 77 -1 2 0 21
+ 34 VMA 5 328 3 0 34 -1 2 0 21
+ 32 AS_000 5 319 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 300 inst_CLK_000_D0 3 -1 7 7 0 1 2 3 5 6 7 -1 -1 1 0 20
+ 301 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20
+ 312 SM_AMIGA_3_ 3 -1 0 4 0 1 2 5 -1 -1 3 0 21
+ 296 inst_AS_030_000_SYNC 3 -1 7 3 0 3 7 -1 -1 4 0 21
+ 295 cpu_est_1_ 3 -1 3 3 2 3 6 -1 -1 4 0 20
+ 327 RN_E 3 65 6 3 2 3 6 65 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 3 2 3 6 -1 -1 3 1 20
+ 294 cpu_est_0_ 3 -1 6 3 2 3 6 -1 -1 3 0 21
+ 326 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 310 SM_AMIGA_4_ 3 -1 5 3 0 3 5 -1 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 2 3 0 1 2 -1 -1 2 0 21
+ 297 inst_DTACK_SYNC 3 -1 5 3 0 1 5 -1 -1 2 0 21
+ 298 inst_VPA_D 3 -1 6 3 2 3 5 -1 -1 1 0 21
+ 315 SM_AMIGA_2_ 3 -1 1 2 1 6 -1 -1 3 0 21
+ 307 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 305 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 3 0 21
+ 328 RN_VMA 3 34 3 2 2 3 34 -1 2 0 21
+ 323 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 319 RN_AS_000 3 32 3 2 3 6 32 -1 2 0 21
+ 314 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 2 0 21
+ 306 SM_AMIGA_7_ 3 -1 6 2 3 6 -1 -1 2 0 20
+ 302 inst_CLK_OUT_PRE 3 -1 1 2 1 6 -1 -1 2 0 20
+ 304 CLK_CNT_0_ 3 -1 7 2 1 7 -1 -1 1 0 20
+ 321 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 320 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 325 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 324 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 322 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 317 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 316 SM_AMIGA_0_ 3 -1 6 1 6 -1 -1 3 0 20
+ 318 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 313 inst_CLK_000_D4 3 -1 6 1 1 -1 -1 1 0 21
+ 311 inst_CLK_000_D3 3 -1 6 1 6 -1 -1 1 0 21
+ 309 inst_CLK_000_D2 3 -1 3 1 6 -1 -1 1 0 20
+ 308 inst_CLK_000_D5 3 -1 1 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 7 0 1 2 3 5 6 7 60 -1
+ 85 RST 1 -1 -1 7 0 1 2 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 4 2 3 5 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 6 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 7 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1
+90 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 314 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 317 3 0 30 -1 12 0 21
+ 31 UDS_000 5 316 3 0 31 -1 8 0 21
+ 65 E 5 323 6 0 65 -1 3 0 21
+ 28 BG_000 5 318 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 313 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 321 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 319 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 320 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 322 7 0 77 -1 2 0 21
+ 34 VMA 5 324 3 0 34 -1 2 0 21
+ 32 AS_000 5 315 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 301 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20
+ 300 inst_CLK_000_D0 3 -1 7 5 0 1 3 6 7 -1 -1 1 0 20
+ 296 inst_AS_030_000_SYNC 3 -1 5 3 0 3 5 -1 -1 4 0 21
+ 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 323 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 311 SM_AMIGA_2_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 305 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20
+ 324 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 320 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 315 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 310 SM_AMIGA_5_ 3 -1 0 2 0 6 -1 -1 2 0 21
+ 308 SM_AMIGA_4_ 3 -1 6 2 3 6 -1 -1 2 0 20
+ 306 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 298 inst_VPA_D 3 -1 6 2 3 6 -1 -1 1 0 21
+ 317 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 316 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 321 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 318 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 313 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 312 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21
+ 309 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 307 SM_AMIGA_1_ 3 -1 7 1 7 -1 -1 3 0 21
+ 314 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 304 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 5 0 1 3 6 7 60 -1
+ 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 4 3 5 6 7 81 -1
+ 63 CLK_030 1 -1 -1 3 3 5 7 63 -1
+ 96 A_19_ 1 -1 -1 2 5 7 96 -1
+ 95 A_16_ 1 -1 -1 2 5 7 95 -1
+ 94 A_18_ 1 -1 -1 2 5 7 94 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 58 A_17_ 1 -1 -1 2 5 7 58 -1
+ 57 FC_1_ 1 -1 -1 2 5 7 57 -1
+ 56 FC_0_ 1 -1 -1 2 5 7 56 -1
+ 27 BGACK_000 1 -1 -1 2 5 7 27 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 6 35 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 7 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 3 3 5 7 -1 -1
+90 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 314 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 317 3 0 30 -1 12 0 21
+ 31 UDS_000 5 316 3 0 31 -1 8 0 21
+ 65 E 5 323 6 0 65 -1 3 0 21
+ 28 BG_000 5 320 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 313 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 321 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 322 7 0 77 -1 2 0 21
+ 34 VMA 5 324 3 0 34 -1 2 0 21
+ 32 AS_000 5 315 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 300 inst_CLK_000_D0 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
+ 301 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20
+ 296 inst_AS_030_000_SYNC 3 -1 7 3 0 3 7 -1 -1 4 0 21
+ 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 308 SM_AMIGA_4_ 3 -1 5 3 3 5 6 -1 -1 2 0 21
+ 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 323 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 307 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 305 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20
+ 324 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 321 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 315 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 310 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 2 0 21
+ 306 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20
+ 317 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 316 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 320 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 313 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 312 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21
+ 311 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20
+ 309 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 314 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 304 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1
+ 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 3 3 6 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 6 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1
+90 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 314 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 317 3 0 30 -1 12 0 21
+ 31 UDS_000 5 316 3 0 31 -1 8 0 21
+ 65 E 5 323 6 0 65 -1 3 0 21
+ 28 BG_000 5 319 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 313 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 320 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 321 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 322 7 0 77 -1 2 0 21
+ 34 VMA 5 324 3 0 34 -1 2 0 21
+ 32 AS_000 5 315 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 300 inst_CLK_000_D0 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
+ 301 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20
+ 296 inst_AS_030_000_SYNC 3 -1 7 3 0 3 7 -1 -1 4 0 21
+ 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 308 SM_AMIGA_4_ 3 -1 5 3 3 5 6 -1 -1 2 0 21
+ 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 323 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 307 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 305 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20
+ 324 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 321 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 315 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 310 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 2 0 21
+ 306 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20
+ 317 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 316 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 320 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 319 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 313 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 312 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21
+ 311 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20
+ 309 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 314 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 304 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1
+ 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 3 3 6 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 6 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 3 3 4 7 -1 -1
+90 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 314 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 317 3 0 30 -1 12 0 21
+ 31 UDS_000 5 316 3 0 31 -1 8 0 21
+ 65 E 5 323 6 0 65 -1 3 0 21
+ 28 BG_000 5 320 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 313 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 321 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 322 7 0 77 -1 2 0 21
+ 34 VMA 5 324 3 0 34 -1 2 0 21
+ 32 AS_000 5 315 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 300 inst_CLK_000_D0 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
+ 301 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20
+ 296 inst_AS_030_000_SYNC 3 -1 7 3 0 3 7 -1 -1 4 0 21
+ 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 308 SM_AMIGA_4_ 3 -1 5 3 3 5 6 -1 -1 2 0 21
+ 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 323 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 307 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 305 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20
+ 324 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 321 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 315 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 310 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 2 0 21
+ 306 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20
+ 317 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 316 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 320 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 313 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 312 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21
+ 311 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20
+ 309 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 314 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 304 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1
+ 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 3 3 6 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 6 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1
+90 "number of signals after reading design file"
+
+"sig sig sig pair blk fan PT xor sync"
+"num name type sig num out pin node cnt PT type"
+"--- ---- ---- ---- --- --- --- ---- --- --- ----"
+
+ 80 DSACK_1_ 5 314 7 1 3 80 -1 2 0 21
+ 29 DTACK 5 -1 3 1 6 29 -1 1 0 21
+ 30 LDS_000 5 317 3 0 30 -1 12 0 21
+ 31 UDS_000 5 316 3 0 31 -1 8 0 21
+ 65 E 5 323 6 0 65 -1 3 0 21
+ 28 BG_000 5 320 3 0 28 -1 3 0 21
+ 8 IPL_030_2_ 5 313 1 0 8 -1 3 0 21
+ 7 IPL_030_0_ 5 319 1 0 7 -1 3 0 21
+ 6 IPL_030_1_ 5 318 1 0 6 -1 3 0 21
+ 82 BGACK_030 5 321 7 0 82 -1 2 0 21
+ 77 FPU_CS 5 322 7 0 77 -1 2 0 21
+ 34 VMA 5 324 3 0 34 -1 2 0 21
+ 32 AS_000 5 315 3 0 32 -1 2 0 21
+ 91 AVEC 0 0 0 91 -1 1 0 21
+ 79 DSACK_0_ 0 7 0 79 -1 1 0 21
+ 64 CLK_DIV_OUT 0 6 0 64 -1 1 0 21
+ 47 AMIGA_BUS_DATA_DIR 0 4 0 47 -1 1 0 21
+ 46 CIIN 0 4 0 46 -1 1 0 21
+ 40 BERR 0 4 0 40 -1 1 0 21
+ 33 AMIGA_BUS_ENABLE 0 3 0 33 -1 1 0 21
+ 21 AVEC_EXP 0 2 0 21 -1 1 0 21
+ 19 AMIGA_BUS_ENABLE_LOW 0 2 0 19 -1 1 0 21
+ 9 CLK_EXP 0 1 0 9 -1 1 0 20
+ 2 RESET 0 1 0 2 -1 1 0 20
+ 300 inst_CLK_000_D0 3 -1 6 6 0 1 3 5 6 7 -1 -1 1 0 21
+ 301 inst_CLK_000_D1 3 -1 3 5 0 1 3 6 7 -1 -1 1 0 20
+ 296 inst_AS_030_000_SYNC 3 -1 7 3 0 3 7 -1 -1 4 0 21
+ 322 RN_FPU_CS 3 77 7 3 2 4 7 77 -1 2 0 21
+ 308 SM_AMIGA_4_ 3 -1 5 3 3 5 6 -1 -1 2 0 21
+ 302 inst_CLK_OUT_PRE 3 -1 7 3 1 6 7 -1 -1 2 0 20
+ 295 cpu_est_1_ 3 -1 3 2 3 6 -1 -1 4 0 20
+ 323 RN_E 3 65 6 2 3 6 65 -1 3 0 21
+ 307 SM_AMIGA_1_ 3 -1 6 2 6 7 -1 -1 3 0 20
+ 305 SM_AMIGA_6_ 3 -1 3 2 0 3 -1 -1 3 0 21
+ 303 cpu_est_2_ 3 -1 3 2 3 6 -1 -1 3 1 20
+ 294 cpu_est_0_ 3 -1 3 2 3 6 -1 -1 3 0 20
+ 324 RN_VMA 3 34 3 2 3 6 34 -1 2 0 21
+ 321 RN_BGACK_030 3 82 7 2 3 7 82 -1 2 0 21
+ 315 RN_AS_000 3 32 3 2 3 7 32 -1 2 0 21
+ 310 SM_AMIGA_5_ 3 -1 0 2 0 5 -1 -1 2 0 21
+ 306 SM_AMIGA_7_ 3 -1 7 2 3 7 -1 -1 2 0 21
+ 298 inst_VPA_D 3 -1 7 2 3 6 -1 -1 1 0 20
+ 317 RN_LDS_000 3 30 3 1 3 30 -1 12 0 21
+ 316 RN_UDS_000 3 31 3 1 3 31 -1 8 0 21
+ 320 RN_BG_000 3 28 3 1 3 28 -1 3 0 21
+ 319 RN_IPL_030_0_ 3 7 1 1 1 7 -1 3 0 21
+ 318 RN_IPL_030_1_ 3 6 1 1 1 6 -1 3 0 21
+ 313 RN_IPL_030_2_ 3 8 1 1 1 8 -1 3 0 21
+ 312 SM_AMIGA_0_ 3 -1 7 1 7 -1 -1 3 0 21
+ 311 SM_AMIGA_2_ 3 -1 6 1 6 -1 -1 3 0 20
+ 309 SM_AMIGA_3_ 3 -1 6 1 6 -1 -1 3 0 20
+ 314 RN_DSACK_1_ 3 80 7 1 7 80 -1 2 0 21
+ 299 inst_VPA_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 297 inst_DTACK_SYNC 3 -1 6 1 6 -1 -1 2 0 20
+ 304 CLK_CNT_0_ 3 -1 7 1 7 -1 -1 1 0 20
+ 60 CLK_OSZI 9 -1 6 0 1 3 5 6 7 60 -1
+ 85 RST 1 -1 -1 6 0 1 3 5 6 7 85 -1
+ 81 AS_030 1 -1 -1 3 3 6 7 81 -1
+ 70 RW 1 -1 -1 2 3 4 70 -1
+ 63 CLK_030 1 -1 -1 2 3 7 63 -1
+ 97 DS_030 1 -1 -1 1 3 97 -1
+ 96 A_19_ 1 -1 -1 1 7 96 -1
+ 95 A_16_ 1 -1 -1 1 7 95 -1
+ 94 A_18_ 1 -1 -1 1 7 94 -1
+ 93 A_21_ 1 -1 -1 1 4 93 -1
+ 92 A_20_ 1 -1 -1 1 4 92 -1
+ 84 A_22_ 1 -1 -1 1 4 84 -1
+ 83 A_23_ 1 -1 -1 1 4 83 -1
+ 78 SIZE_1_ 1 -1 -1 1 3 78 -1
+ 69 SIZE_0_ 1 -1 -1 1 3 69 -1
+ 68 A_0_ 1 -1 -1 1 3 68 -1
+ 67 IPL_2_ 1 -1 -1 1 1 67 -1
+ 66 IPL_0_ 1 -1 -1 1 1 66 -1
+ 58 A_17_ 1 -1 -1 1 7 58 -1
+ 57 FC_1_ 1 -1 -1 1 7 57 -1
+ 56 FC_0_ 1 -1 -1 1 7 56 -1
+ 55 IPL_1_ 1 -1 -1 1 1 55 -1
+ 35 VPA 1 -1 -1 1 7 35 -1
+ 27 BGACK_000 1 -1 -1 1 7 27 -1
+ 20 BG_030 1 -1 -1 1 3 20 -1
+ 18 A_24_ 1 -1 -1 1 4 18 -1
+ 17 A_25_ 1 -1 -1 1 4 17 -1
+ 16 A_26_ 1 -1 -1 1 4 16 -1
+ 15 A_27_ 1 -1 -1 1 4 15 -1
+ 14 A_28_ 1 -1 -1 1 4 14 -1
+ 10 CLK_000 1 -1 -1 1 6 10 -1
+ 5 A_29_ 1 -1 -1 1 4 5 -1
+ 4 A_30_ 1 -1 -1 1 4 4 -1
+ 3 A_31_ 1 -1 -1 1 4 3 -1
+ 293 nEXP_SPACE 1 -1 -1 2 3 7 -1 -1
\ No newline at end of file
diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc
index 504648c..70b6a98 100644
--- a/Logic/68030_tk.plc
+++ b/Logic/68030_tk.plc
@@ -8,34 +8,30 @@
; Source file 68030_tk.tt4
; FITTER-generated Placements.
; DEVICE mach447a
-; DATE Thu May 15 23:02:50 2014
+; DATE Fri May 16 17:07:12 2014
-Pin 94 A_21_
-Pin 93 A_20_
-Pin 79 SIZE_1_
-Pin 97 A_19_
-Pin 95 A_18_
-Pin 4 A_31_
Pin 59 A_17_
Pin 96 A_16_
+Pin 79 SIZE_1_
+Pin 4 A_31_
Pin 68 IPL_2_
Pin 58 FC_1_
Pin 82 AS_030
Pin 98 DS_030
-Pin 14 CPU_SPACE
+Pin 69 A_0_
+Pin 14 nEXP_SPACE
Pin 41 BERR Comb ; S6=1 S9=1 Pair 203
Pin 21 BG_030
-Pin 69 A_0_
-Pin 28 BGACK_000
-Pin 64 CLK_030
Pin 56 IPL_1_
-Pin 11 CLK_000
Pin 67 IPL_0_
-Pin 61 CLK_OSZI
Pin 80 DSACK_0_ Comb ; S6=1 S9=1 Pair 287
-Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 245
+Pin 28 BGACK_000
Pin 57 FC_0_
+Pin 64 CLK_030
+Pin 11 CLK_000
+Pin 61 CLK_OSZI
+Pin 65 CLK_DIV_OUT Reg ; S6=1 S9=1 Pair 245
Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107
Pin 22 AVEC_EXP Comb ; S6=1 S9=1 Pair 149
Pin 36 VPA
@@ -55,15 +51,19 @@ Pin 18 A_25_
Pin 19 A_24_
Pin 84 A_23_
Pin 85 A_22_
+Pin 94 A_21_
+Pin 93 A_20_
+Pin 97 A_19_
+Pin 95 A_18_
Pin 9 IPL_030_2_ Reg ; S6=1 S9=1 Pair 131
Pin 81 DSACK_1_ Reg ; S6=1 S9=1 Pair 281
Pin 33 AS_000 Reg ; S6=1 S9=1 Pair 181
Pin 32 UDS_000 Reg ; S6=1 S9=1 Pair 191
Pin 31 LDS_000 Reg ; S6=1 S9=1 Pair 185
-Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175
-Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275
Pin 7 IPL_030_1_ Reg ; S6=1 S9=1 Pair 143
Pin 8 IPL_030_0_ Reg ; S6=1 S9=1 Pair 137
+Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175
+Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275
Pin 10 CLK_EXP Reg ; S6=1 S9=0 Pair 125
Pin 78 FPU_CS Reg ; S6=1 S9=1 Pair 269
Pin 30 DTACK Reg ; S6=1 S9=1 Pair 173
@@ -75,32 +75,32 @@ Node 281 RN_DSACK_1_ Reg ; S6=1 S9=1
Node 181 RN_AS_000 Reg ; S6=1 S9=1
Node 191 RN_UDS_000 Reg ; S6=1 S9=1
Node 185 RN_LDS_000 Reg ; S6=1 S9=1
-Node 175 RN_BG_000 Reg ; S6=1 S9=1
-Node 275 RN_BGACK_030 Reg ; S6=1 S9=1
Node 143 RN_IPL_030_1_ Reg ; S6=1 S9=1
Node 137 RN_IPL_030_0_ Reg ; S6=1 S9=1
+Node 175 RN_BG_000 Reg ; S6=1 S9=1
+Node 275 RN_BGACK_030 Reg ; S6=1 S9=1
Node 269 RN_FPU_CS Reg ; S6=1 S9=1
Node 173 RN_DTACK Reg ; S6=1 S9=1
Node 251 RN_E Reg ; S6=1 S9=1
Node 179 RN_VMA Reg ; S6=1 S9=1
Node 194 cpu_est_0_ Reg ; S6=1 S9=0
Node 176 cpu_est_1_ Reg ; S6=1 S9=0
-Node 221 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
+Node 271 inst_AS_030_000_SYNC Reg ; S6=1 S9=1
Node 265 inst_DTACK_SYNC Reg ; S6=0 S9=0
-Node 247 inst_VPA_D Reg ; S6=1 S9=1
+Node 289 inst_VPA_D Reg ; S6=1 S9=0
Node 259 inst_VPA_SYNC Reg ; S6=0 S9=0
-Node 271 inst_CLK_000_D Reg ; S6=1 S9=0
-Node 193 inst_CLK_000_DD Reg ; S6=1 S9=0
+Node 257 inst_CLK_000_D0 Reg ; S6=1 S9=1
+Node 193 inst_CLK_000_D1 Reg ; S6=1 S9=0
Node 277 inst_CLK_OUT_PRE Reg ; S6=1 S9=0
Node 188 cpu_est_2_ Reg ; S6=1 S9=0
Node 278 CLK_CNT_0_ Reg ; S6=1 S9=0
Node 182 SM_AMIGA_6_ Reg ; S6=0 S9=1
Node 283 SM_AMIGA_7_ Reg ; S6=1 S9=1
-Node 272 SM_AMIGA_1_ Reg ; S6=0 S9=1
-Node 263 SM_AMIGA_4_ Reg ; S6=1 S9=0
+Node 263 SM_AMIGA_1_ Reg ; S6=1 S9=0
+Node 221 SM_AMIGA_4_ Reg ; S6=1 S9=1
Node 253 SM_AMIGA_3_ Reg ; S6=1 S9=0
Node 101 SM_AMIGA_5_ Reg ; S6=1 S9=1
-Node 257 SM_AMIGA_2_ Reg ; S6=1 S9=0
-Node 289 SM_AMIGA_0_ Reg ; S6=0 S9=1
+Node 247 SM_AMIGA_2_ Reg ; S6=1 S9=0
+Node 272 SM_AMIGA_0_ Reg ; S6=0 S9=1
; Unused Pins & Nodes
; -> None Found.
diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd
index d4884f6..0013c47 100644
--- a/Logic/68030_tk.prd
+++ b/Logic/68030_tk.prd
@@ -5,8 +5,8 @@
|--------------------------------------------|
-Start: Thu May 15 23:02:49 2014
-End : Thu May 15 23:02:50 2014 $$$ Elapsed time: 00:00:01
+Start: Fri May 16 17:07:12 2014
+End : Fri May 16 17:07:12 2014 $$$ Elapsed time: 00:00:00
===========================================================================
Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4]
@@ -26,11 +26,11 @@ _|____|____|____|_______________|____|_____________|___|________________
2 | 16 | 2 | 2 => 100% | 8 | 8 => 100% | 33 | 1 => 3%
3 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 29 => 87%
4 | 16 | 3 | 3 => 100% | 8 | 3 => 37% | 33 | 14 => 42%
- 5 | 16 | 1 | 1 => 100% | 8 | 4 => 50% | 33 | 12 => 36%
+ 5 | 16 | 1 | 1 => 100% | 8 | 4 => 50% | 33 | 5 => 15%
6 | 16 | 8 | 8 => 100% | 8 | 7 => 87% | 33 | 20 => 60%
7 | 16 | 10 | 10 => 100% | 8 | 8 => 100% | 33 | 25 => 75%
---|----|----|------------|-------|------------|-----|------------------
- | Avg number of array inputs in used blocks : 14.88 => 45%
+ | Avg number of array inputs in used blocks : 14.00 => 42%
* Input/Clock Signal count: 35 -> placed: 35 = 100%
@@ -62,14 +62,14 @@ ___|__|__|____|____________________________________________________________
3| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW
4| 3| IO| 33|=> ....|....| AS_000
|=> Paired w/: RN_AS_000
- 5| 7|INP| 82|=> ...3|.567| AS_030
+ 5| 7|INP| 82|=> ...3|..67| AS_030
6| 0|OUT| 92|=> ....|....| AVEC
7| 2|OUT| 22|=> ....|....| AVEC_EXP
8| 6|INP| 69|=> ...3|....| A_0_
- 9| 0|INP| 96|=> ....|.5.7| A_16_
- 10| 5|INP| 59|=> ....|.5.7| A_17_
- 11| 0|INP| 95|=> ....|.5.7| A_18_
- 12| 0|INP| 97|=> ....|.5.7| A_19_
+ 9| 0|INP| 96|=> ....|...7| A_16_
+ 10| 5|INP| 59|=> ....|...7| A_17_
+ 11| 0|INP| 95|=> ....|...7| A_18_
+ 12| 0|INP| 97|=> ....|...7| A_19_
13| 0|INP| 93|=> ....|4...| A_20_
14| 0|INP| 94|=> ....|4...| A_21_
15| 7|INP| 85|=> ....|4...| A_22_
@@ -83,94 +83,94 @@ ___|__|__|____|____________________________________________________________
23| 1|INP| 5|=> ....|4...| A_30_
24| 1|INP| 4|=> ....|4...| A_31_
25| 4|OUT| 41|=> ....|....| BERR
- 26| 3|INP| 28|=> ....|.5.7| BGACK_000
+ 26| 3|INP| 28|=> ....|...7| BGACK_000
27| 7| IO| 83|=> ....|....| BGACK_030
|=> Paired w/: RN_BGACK_030
28| 3| IO| 29|=> ....|....| BG_000
|=> Paired w/: RN_BG_000
29| 2|INP| 21|=> ...3|....| BG_030
30| 4|OUT| 47|=> ....|....| CIIN
- 31| +|INP| 11|=> ....|...7| CLK_000
- 32| +|INP| 64|=> ...3|.5.7| CLK_030
+ 31| +|INP| 11|=> ....|..6.| CLK_000
+ 32| +|INP| 64|=> ...3|...7| CLK_030
33| 7|NOD| . |=> ....|...7| CLK_CNT_0_
34| 6|OUT| 65|=> ....|....| CLK_DIV_OUT
35| 1|OUT| 10|=> ....|....| CLK_EXP
- 36| +|Cin| 61|=> 01.3|..67| CLK_OSZI
- 37| +|INP| 14|=> ...3|.5.7| CPU_SPACE
- 38| 7|OUT| 80|=> ....|....| DSACK_0_
- 39| 7| IO| 81|=> ...3|....| DSACK_1_
+ 36| +|Cin| 61|=> 01.3|.567| CLK_OSZI
+ 37| 7|OUT| 80|=> ....|....| DSACK_0_
+ 38| 7| IO| 81|=> ...3|....| DSACK_1_
|=> Paired w/: RN_DSACK_1_
- 40| 0|INP| 98|=> ...3|....| DS_030
- 41| 3| IO| 30|=> ....|..6.| DTACK
- 42| 6| IO| 66|=> ....|....| E
+ 39| 0|INP| 98|=> ...3|....| DS_030
+ 40| 3| IO| 30|=> ....|..6.| DTACK
+ 41| 6| IO| 66|=> ....|....| E
|=> Paired w/: RN_E
- 43| 5|INP| 57|=> ....|.5.7| FC_0_
- 44| 5|INP| 58|=> ....|.5.7| FC_1_
- 45| 7| IO| 78|=> ....|....| FPU_CS
+ 42| 5|INP| 57|=> ....|...7| FC_0_
+ 43| 5|INP| 58|=> ....|...7| FC_1_
+ 44| 7| IO| 78|=> ....|....| FPU_CS
|=> Paired w/: RN_FPU_CS
- 46| 1| IO| 8|=> ....|....| IPL_030_0_
+ 45| 1| IO| 8|=> ....|....| IPL_030_0_
|=> Paired w/: RN_IPL_030_0_
- 47| 1| IO| 7|=> ....|....| IPL_030_1_
+ 46| 1| IO| 7|=> ....|....| IPL_030_1_
|=> Paired w/: RN_IPL_030_1_
- 48| 1| IO| 9|=> ....|....| IPL_030_2_
+ 47| 1| IO| 9|=> ....|....| IPL_030_2_
|=> Paired w/: RN_IPL_030_2_
- 49| 6|INP| 67|=> .1..|....| IPL_0_
- 50| 5|INP| 56|=> .1..|....| IPL_1_
- 51| 6|INP| 68|=> .1..|....| IPL_2_
- 52| 3| IO| 31|=> ....|....| LDS_000
+ 48| 6|INP| 67|=> .1..|....| IPL_0_
+ 49| 5|INP| 56|=> .1..|....| IPL_1_
+ 50| 6|INP| 68|=> .1..|....| IPL_2_
+ 51| 3| IO| 31|=> ....|....| LDS_000
|=> Paired w/: RN_LDS_000
- 53| 1|OUT| 3|=> ....|....| RESET
- 54| 3|NOD| . |=> ...3|...7| RN_AS_000
+ 52| 1|OUT| 3|=> ....|....| RESET
+ 53| 3|NOD| . |=> ...3|...7| RN_AS_000
|=> Paired w/: AS_000
- 55| 7|NOD| . |=> ...3|...7| RN_BGACK_030
+ 54| 7|NOD| . |=> ...3|...7| RN_BGACK_030
|=> Paired w/: BGACK_030
- 56| 3|NOD| . |=> ...3|....| RN_BG_000
+ 55| 3|NOD| . |=> ...3|....| RN_BG_000
|=> Paired w/: BG_000
- 57| 7|NOD| . |=> ....|...7| RN_DSACK_1_
+ 56| 7|NOD| . |=> ....|...7| RN_DSACK_1_
|=> Paired w/: DSACK_1_
- 58| 6|NOD| . |=> ...3|..6.| RN_E
+ 57| 6|NOD| . |=> ...3|..6.| RN_E
|=> Paired w/: E
- 59| 7|NOD| . |=> ..2.|4..7| RN_FPU_CS
+ 58| 7|NOD| . |=> ..2.|4..7| RN_FPU_CS
|=> Paired w/: FPU_CS
- 60| 1|NOD| . |=> .1..|....| RN_IPL_030_0_
+ 59| 1|NOD| . |=> .1..|....| RN_IPL_030_0_
|=> Paired w/: IPL_030_0_
- 61| 1|NOD| . |=> .1..|....| RN_IPL_030_1_
+ 60| 1|NOD| . |=> .1..|....| RN_IPL_030_1_
|=> Paired w/: IPL_030_1_
- 62| 1|NOD| . |=> .1..|....| RN_IPL_030_2_
+ 61| 1|NOD| . |=> .1..|....| RN_IPL_030_2_
|=> Paired w/: IPL_030_2_
- 63| 3|NOD| . |=> ...3|....| RN_LDS_000
+ 62| 3|NOD| . |=> ...3|....| RN_LDS_000
|=> Paired w/: LDS_000
- 64| 3|NOD| . |=> ...3|....| RN_UDS_000
+ 63| 3|NOD| . |=> ...3|....| RN_UDS_000
|=> Paired w/: UDS_000
- 65| 3|NOD| . |=> ...3|..6.| RN_VMA
+ 64| 3|NOD| . |=> ...3|..6.| RN_VMA
|=> Paired w/: VMA
- 66| +|INP| 86|=> 01.3|.567| RST
- 67| 6|INP| 71|=> ...3|4...| RW
- 68| 6|INP| 70|=> ...3|....| SIZE_0_
- 69| 7|INP| 79|=> ...3|....| SIZE_1_
- 70| 7|NOD| . |=> ....|...7| SM_AMIGA_0_
- 71| 7|NOD| . |=> ....|...7| SM_AMIGA_1_
- 72| 6|NOD| . |=> ....|..67| SM_AMIGA_2_
- 73| 6|NOD| . |=> ....|..6.| SM_AMIGA_3_
- 74| 6|NOD| . |=> ...3|..6.| SM_AMIGA_4_
- 75| 0|NOD| . |=> 0...|..6.| SM_AMIGA_5_
- 76| 3|NOD| . |=> 0..3|....| SM_AMIGA_6_
- 77| 7|NOD| . |=> ...3|...7| SM_AMIGA_7_
- 78| 3| IO| 32|=> ....|....| UDS_000
+ 65| +|INP| 86|=> 01.3|.567| RST
+ 66| 6|INP| 71|=> ...3|4...| RW
+ 67| 6|INP| 70|=> ...3|....| SIZE_0_
+ 68| 7|INP| 79|=> ...3|....| SIZE_1_
+ 69| 7|NOD| . |=> ....|...7| SM_AMIGA_0_
+ 70| 6|NOD| . |=> ....|..67| SM_AMIGA_1_
+ 71| 6|NOD| . |=> ....|..6.| SM_AMIGA_2_
+ 72| 6|NOD| . |=> ....|..6.| SM_AMIGA_3_
+ 73| 5|NOD| . |=> ...3|.56.| SM_AMIGA_4_
+ 74| 0|NOD| . |=> 0...|.5..| SM_AMIGA_5_
+ 75| 3|NOD| . |=> 0..3|....| SM_AMIGA_6_
+ 76| 7|NOD| . |=> ...3|...7| SM_AMIGA_7_
+ 77| 3| IO| 32|=> ....|....| UDS_000
|=> Paired w/: RN_UDS_000
- 79| 3| IO| 35|=> ....|....| VMA
+ 78| 3| IO| 35|=> ....|....| VMA
|=> Paired w/: RN_VMA
- 80| +|INP| 36|=> ....|..6.| VPA
- 81| 3|NOD| . |=> ...3|..6.| cpu_est_0_
- 82| 3|NOD| . |=> ...3|..6.| cpu_est_1_
- 83| 3|NOD| . |=> ...3|..6.| cpu_est_2_
- 84| 5|NOD| . |=> 0..3|.5..| inst_AS_030_000_SYNC
- 85| 7|NOD| . |=> 01.3|..67| inst_CLK_000_D
- 86| 3|NOD| . |=> 01.3|..67| inst_CLK_000_DD
- 87| 7|NOD| . |=> .1..|..67| inst_CLK_OUT_PRE
- 88| 6|NOD| . |=> ....|..6.| inst_DTACK_SYNC
- 89| 6|NOD| . |=> ...3|..6.| inst_VPA_D
- 90| 6|NOD| . |=> ....|..6.| inst_VPA_SYNC
+ 79| +|INP| 36|=> ....|...7| VPA
+ 80| 3|NOD| . |=> ...3|..6.| cpu_est_0_
+ 81| 3|NOD| . |=> ...3|..6.| cpu_est_1_
+ 82| 3|NOD| . |=> ...3|..6.| cpu_est_2_
+ 83| 7|NOD| . |=> 0..3|...7| inst_AS_030_000_SYNC
+ 84| 6|NOD| . |=> 01.3|.567| inst_CLK_000_D0
+ 85| 3|NOD| . |=> 01.3|..67| inst_CLK_000_D1
+ 86| 7|NOD| . |=> .1..|..67| inst_CLK_OUT_PRE
+ 87| 6|NOD| . |=> ....|..6.| inst_DTACK_SYNC
+ 88| 7|NOD| . |=> ...3|..6.| inst_VPA_D
+ 89| 6|NOD| . |=> ....|..6.| inst_VPA_SYNC
+ 90| +|INP| 14|=> ...3|...7| nEXP_SPACE
---------------------------------------------------------------------------
===========================================================================
< C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments >
@@ -192,7 +192,7 @@ ____|_____|_________|______________________________________________________
11 | CkIn | |*| CLK_000
12 | Vcc | | | (pwr/test)
13 | GND | | | (pwr/test)
- 14 | CkIn | |*| CPU_SPACE
+ 14 | CkIn | | | nEXP_SPACE
15 | I_O | 2_00|*| A_28_
16 | I_O | 2_01|*| A_27_
17 | I_O | 2_02|*| A_26_
@@ -451,19 +451,19 @@ IMX No. | +---- Block IO Pin or Macrocell Number
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
Mux00| Input Pin ( 86)| RST
-Mux01| Mcel 3 13 ( 193)| inst_CLK_000_DD
+Mux01| Mcel 3 13 ( 193)| inst_CLK_000_D1
Mux02| ... | ...
Mux03| ... | ...
Mux04| Input Pin ( 61)| CLK_OSZI
-Mux05| Mcel 5 0 ( 221)| inst_AS_030_000_SYNC
+Mux05| ... | ...
Mux06| ... | ...
Mux07| ... | ...
Mux08| ... | ...
Mux09| ... | ...
-Mux10| Mcel 7 1 ( 271)| inst_CLK_000_D
+Mux10| Mcel 7 1 ( 271)| inst_AS_030_000_SYNC
Mux11| ... | ...
Mux12| ... | ...
-Mux13| ... | ...
+Mux13| Mcel 6 8 ( 257)| inst_CLK_000_D0
Mux14| ... | ...
Mux15| Mcel 0 0 ( 101)| SM_AMIGA_5_
Mux16| Mcel 3 6 ( 182)| SM_AMIGA_6_
@@ -658,7 +658,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
Mux00| IOPin 6 2 ( 67)| IPL_0_
-Mux01| Mcel 3 13 ( 193)| inst_CLK_000_DD
+Mux01| Mcel 3 13 ( 193)| inst_CLK_000_D1
Mux02| ... | ...
Mux03| IOPin 5 4 ( 56)| IPL_1_
Mux04| IOPin 6 3 ( 68)| IPL_2_
@@ -667,7 +667,7 @@ Mux06| ... | ...
Mux07| ... | ...
Mux08| Mcel 1 8 ( 137)| RN_IPL_030_0_
Mux09| ... | ...
-Mux10| Mcel 7 1 ( 271)| inst_CLK_000_D
+Mux10| Mcel 6 8 ( 257)| inst_CLK_000_D0
Mux11| ... | ...
Mux12| Mcel 1 12 ( 143)| RN_IPL_030_1_
Mux13| Mcel 7 5 ( 277)| inst_CLK_OUT_PRE
@@ -918,7 +918,7 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________
10| cpu_est_2_|NOD| | A | 3 :+: 1| 2 to [ 8]| 1 XOR to [10]
11| | ? | | S | | 4 to [12]| 1 XOR free
12| UDS_000| IO| | S | 8 | 4 to [12]| 1 XOR to [12] as logic PT
-13|inst_CLK_000_DD|NOD| | A | 1 | 2 to [12]| 1 XOR to [13] for 1 PT sig
+13|inst_CLK_000_D1|NOD| | A | 1 | 2 to [12]| 1 XOR to [13] for 1 PT sig
14| cpu_est_0_|NOD| | A | 3 | 2 to [14]| 1 XOR to [14] as logic PT
15| | ? | | S | | 4 free | 1 XOR free
---------------------------------------------------------------------------
@@ -945,7 +945,7 @@ _|_________________|__|__|___|_____|_______________________________________
10| cpu_est_2_|NOD| | A | 3 :+: 1|=> can support up to [ 4] logic PT(s)
11| | ? | | S | |=> can support up to [ 1] logic PT(s)
12| UDS_000| IO| | S | 8 |=> can support up to [ 12] logic PT(s)
-13|inst_CLK_000_DD|NOD| | A | 1 |=> can support up to [ 6] logic PT(s)
+13|inst_CLK_000_D1|NOD| | A | 1 |=> can support up to [ 6] logic PT(s)
14| cpu_est_0_|NOD| | A | 3 |=> can support up to [ 8] logic PT(s)
15| | ? | | S | |=> can support up to [ 5] logic PT(s)
---------------------------------------------------------------------------
@@ -970,7 +970,7 @@ _|_________________|__|_____|____________________|________________________
10| cpu_est_2_|NOD| | => | 2 3 4 5 | 33 32 31 30
11| | | | => | 2 3 4 5 | 33 32 31 30
12| UDS_000| IO| | => |( 3) 4 5 6 |( 32) 31 30 29
-13|inst_CLK_000_DD|NOD| | => | 3 4 5 6 | 32 31 30 29
+13|inst_CLK_000_D1|NOD| | => | 3 4 5 6 | 32 31 30 29
14| cpu_est_0_|NOD| | => | 4 5 6 7 | 31 30 29 28
15| | | | => | 4 5 6 7 | 31 30 29 28
---------------------------------------------------------------------------
@@ -1057,7 +1057,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number
6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000]
[RegIn 6 |192| -| | ]
[MCell 12 |191|NOD RN_UDS_000| |*] paired w/[ UDS_000]
- [MCell 13 |193|NOD inst_CLK_000_DD| |*]
+ [MCell 13 |193|NOD inst_CLK_000_D1| |*]
7 [IOpin 7 | 28|INP BGACK_000|*|*]
[RegIn 7 |195| -| | ]
@@ -1071,36 +1071,36 @@ IMX No. | +---- Block IO Pin or Macrocell Number
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
Mux00| IOPin 6 5 ( 70)| SIZE_0_
-Mux01| Mcel 3 13 ( 193)| inst_CLK_000_DD
+Mux01| Mcel 3 13 ( 193)| inst_CLK_000_D1
Mux02| Mcel 6 4 ( 251)| RN_E
Mux03| Mcel 3 2 ( 176)| cpu_est_1_
-Mux04| Mcel 6 1 ( 247)| inst_VPA_D
-Mux05| IOPin 0 7 ( 98)| DS_030
+Mux04| IOPin 2 6 ( 21)| BG_030
+Mux05| Mcel 3 8 ( 185)| RN_LDS_000
Mux06| IOPin 7 6 ( 79)| SIZE_1_
-Mux07| Mcel 3 5 ( 181)| RN_AS_000
+Mux07| Mcel 7 13 ( 289)| inst_VPA_D
Mux08| IOPin 6 6 ( 71)| RW
Mux09| IOPin 7 3 ( 82)| AS_030
Mux10| Mcel 3 14 ( 194)| cpu_est_0_
Mux11| Mcel 3 12 ( 191)| RN_UDS_000
-Mux12| Mcel 7 1 ( 271)| inst_CLK_000_D
-Mux13| ... | ...
-Mux14| Mcel 6 12 ( 263)| SM_AMIGA_4_
-Mux15| Input Pin ( 14)| CPU_SPACE
-Mux16| Mcel 3 8 ( 185)| RN_LDS_000
+Mux12| IOPin 0 7 ( 98)| DS_030
+Mux13| Mcel 6 8 ( 257)| inst_CLK_000_D0
+Mux14| Mcel 3 4 ( 179)| RN_VMA
+Mux15| Input Pin ( 14)| nEXP_SPACE
+Mux16| Mcel 3 6 ( 182)| SM_AMIGA_6_
Mux17| Mcel 3 1 ( 175)| RN_BG_000
Mux18| IOPin 6 4 ( 69)| A_0_
-Mux19| ... | ...
-Mux20| Mcel 3 10 ( 188)| cpu_est_2_
-Mux21| Mcel 3 4 ( 179)| RN_VMA
-Mux22| IOPin 2 6 ( 21)| BG_030
+Mux19| Mcel 7 1 ( 271)| inst_AS_030_000_SYNC
+Mux20| Input Pin ( 64)| CLK_030
+Mux21| Input Pin ( 86)| RST
+Mux22| ... | ...
Mux23| Mcel 7 4 ( 275)| RN_BGACK_030
-Mux24| Input Pin ( 86)| RST
-Mux25| Mcel 5 0 ( 221)| inst_AS_030_000_SYNC
+Mux24| Mcel 3 5 ( 181)| RN_AS_000
+Mux25| Mcel 5 0 ( 221)| SM_AMIGA_4_
Mux26| ... | ...
Mux27| Mcel 7 9 ( 283)| SM_AMIGA_7_
-Mux28| Input Pin ( 64)| CLK_030
+Mux28| ... | ...
Mux29| Input Pin ( 61)| CLK_OSZI
-Mux30| Mcel 3 6 ( 182)| SM_AMIGA_6_
+Mux30| Mcel 3 10 ( 188)| cpu_est_2_
Mux31| ... | ...
Mux32| IOPin 7 4 ( 81)| DSACK_1_
---------------------------------------------------------------------------
@@ -1318,7 +1318,7 @@ Mux32| ... | ...
| Sig Type-+ | | | | | | | XOR to Mcell Assignment
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
- 0|inst_AS_030_000_SYNC|NOD| | S | 4 | 4 to [ 0]| 1 XOR free
+ 0| SM_AMIGA_4_|NOD| | S | 2 | 4 to [ 0]| 1 XOR free
1| | ? | | S | | 4 free | 1 XOR free
2| | ? | | S | | 4 free | 1 XOR free
3| | ? | | S | | 4 free | 1 XOR free
@@ -1345,7 +1345,7 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
- 0|inst_AS_030_000_SYNC|NOD| | S | 4 |=> can support up to [ 15] logic PT(s)
+ 0| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s)
1| | ? | | S | |=> can support up to [ 15] logic PT(s)
2| | ? | | S | |=> can support up to [ 20] logic PT(s)
3| | ? | | S | |=> can support up to [ 20] logic PT(s)
@@ -1370,7 +1370,7 @@ _|_________________|__|__|___|_____|_______________________________________
| Sig Type---+ | to | Block [ 5] IO Pin | Device Pin
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
- 0|inst_AS_030_000_SYNC|NOD| | => | 5 6 7 0 | 55 54 53 60
+ 0| SM_AMIGA_4_|NOD| | => | 5 6 7 0 | 55 54 53 60
1| | | | => | 5 6 7 0 | 55 54 53 60
2| | | | => | 6 7 0 1 | 54 53 60 59
3| | | | => | 6 7 0 1 | 54 53 60 59
@@ -1434,7 +1434,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number
---|-------|----|---|---|----------|------|-|------------------------------
0 [IOpin 0 | 60| -| | ]
[RegIn 0 |222| -| | ]
- [MCell 0 |221|NOD inst_AS_030_000_SYNC| |*]
+ [MCell 0 |221|NOD SM_AMIGA_4_| |*]
[MCell 1 |223| -| | ]
1 [IOpin 1 | 59|INP A_17_|*|*]
@@ -1479,31 +1479,31 @@ IMX No. | +---- Block IO Pin or Macrocell Number
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
Mux00| Input Pin ( 86)| RST
-Mux01| IOPin 5 2 ( 58)| FC_1_
+Mux01| ... | ...
Mux02| ... | ...
Mux03| ... | ...
-Mux04| IOPin 3 7 ( 28)| BGACK_000
-Mux05| Input Pin ( 14)| CPU_SPACE
-Mux06| IOPin 5 3 ( 57)| FC_0_
+Mux04| Input Pin ( 61)| CLK_OSZI
+Mux05| Mcel 5 0 ( 221)| SM_AMIGA_4_
+Mux06| ... | ...
Mux07| ... | ...
-Mux08| IOPin 5 1 ( 59)| A_17_
-Mux09| IOPin 7 3 ( 82)| AS_030
-Mux10| ... | ...
-Mux11| IOPin 0 5 ( 96)| A_16_
-Mux12| IOPin 0 6 ( 97)| A_19_
+Mux08| ... | ...
+Mux09| ... | ...
+Mux10| Mcel 6 8 ( 257)| inst_CLK_000_D0
+Mux11| ... | ...
+Mux12| ... | ...
Mux13| ... | ...
Mux14| ... | ...
-Mux15| ... | ...
+Mux15| Mcel 0 0 ( 101)| SM_AMIGA_5_
Mux16| ... | ...
-Mux17| IOPin 0 4 ( 95)| A_18_
+Mux17| ... | ...
Mux18| ... | ...
Mux19| ... | ...
-Mux20| Input Pin ( 64)| CLK_030
+Mux20| ... | ...
Mux21| ... | ...
Mux22| ... | ...
Mux23| ... | ...
Mux24| ... | ...
-Mux25| Mcel 5 0 ( 221)| inst_AS_030_000_SYNC
+Mux25| ... | ...
Mux26| ... | ...
Mux27| ... | ...
Mux28| ... | ...
@@ -1523,18 +1523,18 @@ Mux32| ... | ...
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
0| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig
- 1| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig
+ 1| SM_AMIGA_2_|NOD| | A | 3 | 2 to [ 1]| 1 XOR to [ 1] as logic PT
2| | ? | | S | | 4 free | 1 XOR free
3| | ? | | S | | 4 free | 1 XOR free
4| E| IO| | S | 3 | 4 to [ 4]| 1 XOR free
5| SM_AMIGA_3_|NOD| | A | 3 | 2 to [ 5]| 1 XOR to [ 5] as logic PT
6| | ? | | S | | 4 free | 1 XOR free
7| | ? | | S | | 4 free | 1 XOR free
- 8| SM_AMIGA_2_|NOD| | A | 3 | 2 to [ 8]| 1 XOR to [ 8] as logic PT
+ 8|inst_CLK_000_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig
9| inst_VPA_SYNC|NOD| | A | 2 | 2 to [ 9]| 1 XOR free
10| | ? | | S | | 4 free | 1 XOR free
11| | ? | | S | | 4 free | 1 XOR free
-12| SM_AMIGA_4_|NOD| | A | 2 | 2 to [12]| 1 XOR free
+12| SM_AMIGA_1_|NOD| | A | 3 | 2 to [12]| 1 XOR to [12] as logic PT
13|inst_DTACK_SYNC|NOD| | A | 2 | 2 to [13]| 1 XOR free
14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
@@ -1549,19 +1549,19 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
- 0| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 14] logic PT(s)
- 1| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 19] logic PT(s)
- 2| | ? | | S | |=> can support up to [ 14] logic PT(s)
+ 0| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 10] logic PT(s)
+ 1| SM_AMIGA_2_|NOD| | A | 3 |=> can support up to [ 17] logic PT(s)
+ 2| | ? | | S | |=> can support up to [ 10] logic PT(s)
3| | ? | | S | |=> can support up to [ 10] logic PT(s)
4| E| IO| | S | 3 |=> can support up to [ 15] logic PT(s)
5| SM_AMIGA_3_|NOD| | A | 3 |=> can support up to [ 13] logic PT(s)
- 6| | ? | | S | |=> can support up to [ 10] logic PT(s)
- 7| | ? | | S | |=> can support up to [ 10] logic PT(s)
- 8| SM_AMIGA_2_|NOD| | A | 3 |=> can support up to [ 13] logic PT(s)
- 9| inst_VPA_SYNC|NOD| | A | 2 |=> can support up to [ 13] logic PT(s)
+ 6| | ? | | S | |=> can support up to [ 14] logic PT(s)
+ 7| | ? | | S | |=> can support up to [ 14] logic PT(s)
+ 8|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 15] logic PT(s)
+ 9| inst_VPA_SYNC|NOD| | A | 2 |=> can support up to [ 17] logic PT(s)
10| | ? | | S | |=> can support up to [ 10] logic PT(s)
11| | ? | | S | |=> can support up to [ 10] logic PT(s)
-12| SM_AMIGA_4_|NOD| | A | 2 |=> can support up to [ 13] logic PT(s)
+12| SM_AMIGA_1_|NOD| | A | 3 |=> can support up to [ 13] logic PT(s)
13|inst_DTACK_SYNC|NOD| | A | 2 |=> can support up to [ 13] logic PT(s)
14| | ? | | S | |=> can support up to [ 10] logic PT(s)
15| | ? | | S | |=> can support up to [ 10] logic PT(s)
@@ -1575,18 +1575,18 @@ _|_________________|__|__|___|_____|_______________________________________
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65)
- 1| inst_VPA_D|NOD| | => | 5 6 7 0 | 70 71 72 65
+ 1| SM_AMIGA_2_|NOD| | => | 5 6 7 0 | 70 71 72 65
2| | | | => | 6 7 0 1 | 71 72 65 66
3| | | | => | 6 7 0 1 | 71 72 65 66
4| E| IO| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67
5| SM_AMIGA_3_|NOD| | => | 7 0 1 2 | 72 65 66 67
6| | | | => | 0 1 2 3 | 65 66 67 68
7| | | | => | 0 1 2 3 | 65 66 67 68
- 8| SM_AMIGA_2_|NOD| | => | 1 2 3 4 | 66 67 68 69
+ 8|inst_CLK_000_D0|NOD| | => | 1 2 3 4 | 66 67 68 69
9| inst_VPA_SYNC|NOD| | => | 1 2 3 4 | 66 67 68 69
10| | | | => | 2 3 4 5 | 67 68 69 70
11| | | | => | 2 3 4 5 | 67 68 69 70
-12| SM_AMIGA_4_|NOD| | => | 3 4 5 6 | 68 69 70 71
+12| SM_AMIGA_1_|NOD| | => | 3 4 5 6 | 68 69 70 71
13|inst_DTACK_SYNC|NOD| | => | 3 4 5 6 | 68 69 70 71
14| | | | => | 4 5 6 7 | 69 70 71 72
15| | | | => | 4 5 6 7 | 69 70 71 72
@@ -1640,7 +1640,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number
0 [IOpin 0 | 65|OUT CLK_DIV_OUT|*| ]
[RegIn 0 |246| -| | ]
[MCell 0 |245|OUT CLK_DIV_OUT| | ]
- [MCell 1 |247|NOD inst_VPA_D| |*]
+ [MCell 1 |247|NOD SM_AMIGA_2_| |*]
1 [IOpin 1 | 66| IO E|*| ] paired w/[ RN_E]
[RegIn 1 |249| -| | ]
@@ -1659,7 +1659,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number
4 [IOpin 4 | 69|INP A_0_|*|*]
[RegIn 4 |258| -| | ]
- [MCell 8 |257|NOD SM_AMIGA_2_| |*]
+ [MCell 8 |257|NOD inst_CLK_000_D0| |*]
[MCell 9 |259|NOD inst_VPA_SYNC| |*]
5 [IOpin 5 | 70|INP SIZE_0_|*|*]
@@ -1669,7 +1669,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number
6 [IOpin 6 | 71|INP RW|*|*]
[RegIn 6 |264| -| | ]
- [MCell 12 |263|NOD SM_AMIGA_4_| |*]
+ [MCell 12 |263|NOD SM_AMIGA_1_| |*]
[MCell 13 |265|NOD inst_DTACK_SYNC| |*]
7 [IOpin 7 | 72| -| | ]
@@ -1684,34 +1684,34 @@ IMX No. | +---- Block IO Pin or Macrocell Number
| Src (ABEL Node/Pin#) Signal
--|--|--------------------|---------------------------------------------------
Mux00| Input Pin ( 86)| RST
-Mux01| Mcel 3 13 ( 193)| inst_CLK_000_DD
+Mux01| Mcel 3 13 ( 193)| inst_CLK_000_D1
Mux02| Mcel 3 10 ( 188)| cpu_est_2_
-Mux03| Mcel 6 5 ( 253)| SM_AMIGA_3_
-Mux04| Mcel 7 5 ( 277)| inst_CLK_OUT_PRE
-Mux05| ... | ...
+Mux03| Input Pin ( 11)| CLK_000
+Mux04| Input Pin ( 61)| CLK_OSZI
+Mux05| Mcel 5 0 ( 221)| SM_AMIGA_4_
Mux06| ... | ...
-Mux07| Mcel 6 12 ( 263)| SM_AMIGA_4_
+Mux07| Mcel 7 13 ( 289)| inst_VPA_D
Mux08| ... | ...
-Mux09| IOPin 7 3 ( 82)| AS_030
-Mux10| Input Pin ( 36)| VPA
+Mux09| IOPin 3 5 ( 30)| DTACK
+Mux10| Mcel 6 9 ( 259)| inst_VPA_SYNC
Mux11| Mcel 6 4 ( 251)| RN_E
Mux12| Mcel 6 13 ( 265)| inst_DTACK_SYNC
-Mux13| Mcel 6 8 ( 257)| SM_AMIGA_2_
+Mux13| Mcel 7 5 ( 277)| inst_CLK_OUT_PRE
Mux14| Mcel 3 4 ( 179)| RN_VMA
-Mux15| Mcel 0 0 ( 101)| SM_AMIGA_5_
+Mux15| ... | ...
Mux16| Mcel 3 2 ( 176)| cpu_est_1_
Mux17| Mcel 3 14 ( 194)| cpu_est_0_
Mux18| ... | ...
-Mux19| Mcel 7 1 ( 271)| inst_CLK_000_D
+Mux19| IOPin 7 3 ( 82)| AS_030
Mux20| ... | ...
-Mux21| Input Pin ( 61)| CLK_OSZI
-Mux22| ... | ...
-Mux23| IOPin 3 5 ( 30)| DTACK
-Mux24| Mcel 6 1 ( 247)| inst_VPA_D
+Mux21| ... | ...
+Mux22| Mcel 6 5 ( 253)| SM_AMIGA_3_
+Mux23| Mcel 6 12 ( 263)| SM_AMIGA_1_
+Mux24| Mcel 6 1 ( 247)| SM_AMIGA_2_
Mux25| ... | ...
Mux26| ... | ...
-Mux27| Mcel 6 9 ( 259)| inst_VPA_SYNC
-Mux28| ... | ...
+Mux27| ... | ...
+Mux28| Mcel 6 8 ( 257)| inst_CLK_000_D0
Mux29| ... | ...
Mux30| ... | ...
Mux31| ... | ...
@@ -1728,8 +1728,8 @@ Mux32| ... | ...
| Signal Name | | | | | | | | |
_|_________________|__|__|___|_____|__|______|___|__________|______________
0| FPU_CS| IO| | S | 2 | 4 to [ 0]| 1 XOR free
- 1|inst_CLK_000_D|NOD| | A | 1 | 2 free | 1 XOR to [ 1] for 1 PT sig
- 2| SM_AMIGA_1_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free
+ 1|inst_AS_030_000_SYNC|NOD| | S | 4 | 4 to [ 1]| 1 XOR free
+ 2| SM_AMIGA_0_|NOD| | S | 3 | 4 to [ 2]| 1 XOR free
3| | ? | | S | | 4 free | 1 XOR free
4| BGACK_030| IO| | S | 2 | 4 to [ 4]| 1 XOR free
5|inst_CLK_OUT_PRE|NOD| | A | 2 | 2 to [ 5]| 1 XOR free
@@ -1740,7 +1740,7 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________
10| | ? | | S | | 4 free | 1 XOR free
11| | ? | | S | | 4 free | 1 XOR free
12| DSACK_0_|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig
-13| SM_AMIGA_0_|NOD| | S | 3 | 4 to [13]| 1 XOR free
+13| inst_VPA_D|NOD| | A | 1 | 2 free | 1 XOR to [13] for 1 PT sig
14| | ? | | S | | 4 free | 1 XOR free
15| | ? | | S | | 4 free | 1 XOR free
---------------------------------------------------------------------------
@@ -1754,9 +1754,9 @@ _|_________________|__|__|___|_____|__|______|___|__________|______________
| Sig Type-+ | | | |
| Signal Name | | | | | Maximum PT Capacity
_|_________________|__|__|___|_____|_______________________________________
- 0| FPU_CS| IO| | S | 2 |=> can support up to [ 7] logic PT(s)
- 1|inst_CLK_000_D|NOD| | A | 1 |=> can support up to [ 8] logic PT(s)
- 2| SM_AMIGA_1_|NOD| | S | 3 |=> can support up to [ 12] logic PT(s)
+ 0| FPU_CS| IO| | S | 2 |=> can support up to [ 5] logic PT(s)
+ 1|inst_AS_030_000_SYNC|NOD| | S | 4 |=> can support up to [ 10] logic PT(s)
+ 2| SM_AMIGA_0_|NOD| | S | 3 |=> can support up to [ 10] logic PT(s)
3| | ? | | S | |=> can support up to [ 5] logic PT(s)
4| BGACK_030| IO| | S | 2 |=> can support up to [ 12] logic PT(s)
5|inst_CLK_OUT_PRE|NOD| | A | 2 |=> can support up to [ 10] logic PT(s)
@@ -1765,10 +1765,10 @@ _|_________________|__|__|___|_____|_______________________________________
8| DSACK_1_| IO| | S | 2 |=> can support up to [ 15] logic PT(s)
9| SM_AMIGA_7_|NOD| | S | 2 |=> can support up to [ 15] logic PT(s)
10| | ? | | S | |=> can support up to [ 14] logic PT(s)
-11| | ? | | S | |=> can support up to [ 14] logic PT(s)
-12| DSACK_0_|OUT| | S | 1 |=> can support up to [ 15] logic PT(s)
-13| SM_AMIGA_0_|NOD| | S | 3 |=> can support up to [ 19] logic PT(s)
-14| | ? | | S | |=> can support up to [ 10] logic PT(s)
+11| | ? | | S | |=> can support up to [ 16] logic PT(s)
+12| DSACK_0_|OUT| | S | 1 |=> can support up to [ 17] logic PT(s)
+13| inst_VPA_D|NOD| | A | 1 |=> can support up to [ 17] logic PT(s)
+14| | ? | | S | |=> can support up to [ 12] logic PT(s)
15| | ? | | S | |=> can support up to [ 10] logic PT(s)
---------------------------------------------------------------------------
===========================================================================
@@ -1780,8 +1780,8 @@ _|_________________|__|__|___|_____|_______________________________________
| Signal Name | | pin | Numbers | Numbers
_|_________________|__|_____|____________________|________________________
0| FPU_CS| IO| | => | 5 6 ( 7) 0 | 80 79 ( 78) 85
- 1|inst_CLK_000_D|NOD| | => | 5 6 7 0 | 80 79 78 85
- 2| SM_AMIGA_1_|NOD| | => | 6 7 0 1 | 79 78 85 84
+ 1|inst_AS_030_000_SYNC|NOD| | => | 5 6 7 0 | 80 79 78 85
+ 2| SM_AMIGA_0_|NOD| | => | 6 7 0 1 | 79 78 85 84
3| | | | => | 6 7 0 1 | 79 78 85 84
4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83)
5|inst_CLK_OUT_PRE|NOD| | => | 7 0 1 2 | 78 85 84 83
@@ -1792,7 +1792,7 @@ _|_________________|__|_____|____________________|________________________
10| | | | => | 2 3 4 5 | 83 82 81 80
11| | | | => | 2 3 4 5 | 83 82 81 80
12| DSACK_0_|OUT| | => | 3 4 ( 5) 6 | 82 81 ( 80) 79
-13| SM_AMIGA_0_|NOD| | => | 3 4 5 6 | 82 81 80 79
+13| inst_VPA_D|NOD| | => | 3 4 5 6 | 82 81 80 79
14| | | | => | 4 5 6 7 | 81 80 79 78
15| | | | => | 4 5 6 7 | 81 80 79 78
---------------------------------------------------------------------------
@@ -1847,11 +1847,11 @@ IMX No. | +---- Block IO Pin or Macrocell Number
0 [IOpin 0 | 85|INP A_22_|*|*]
[RegIn 0 |270| -| | ]
[MCell 0 |269|NOD RN_FPU_CS| |*] paired w/[ FPU_CS]
- [MCell 1 |271|NOD inst_CLK_000_D| |*]
+ [MCell 1 |271|NOD inst_AS_030_000_SYNC| |*]
1 [IOpin 1 | 84|INP A_23_|*|*]
[RegIn 1 |273| -| | ]
- [MCell 2 |272|NOD SM_AMIGA_1_| |*]
+ [MCell 2 |272|NOD SM_AMIGA_0_| |*]
[MCell 3 |274| -| | ]
2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030]
@@ -1877,7 +1877,7 @@ IMX No. | +---- Block IO Pin or Macrocell Number
6 [IOpin 6 | 79|INP SIZE_1_|*|*]
[RegIn 6 |288| -| | ]
[MCell 12 |287|OUT DSACK_0_| | ]
- [MCell 13 |289|NOD SM_AMIGA_0_| |*]
+ [MCell 13 |289|NOD inst_VPA_D| |*]
7 [IOpin 7 | 78| IO FPU_CS|*| ] paired w/[ RN_FPU_CS]
[RegIn 7 |291| -| | ]
@@ -1894,32 +1894,32 @@ Mux00| Input Pin ( 86)| RST
Mux01| IOPin 5 2 ( 58)| FC_1_
Mux02| ... | ...
Mux03| Mcel 7 8 ( 281)| RN_DSACK_1_
-Mux04| Mcel 7 2 ( 272)| SM_AMIGA_1_
-Mux05| Mcel 7 9 ( 283)| SM_AMIGA_7_
+Mux04| Input Pin ( 61)| CLK_OSZI
+Mux05| Input Pin ( 14)| nEXP_SPACE
Mux06| IOPin 5 3 ( 57)| FC_0_
-Mux07| Mcel 7 6 ( 278)| CLK_CNT_0_
+Mux07| Mcel 6 12 ( 263)| SM_AMIGA_1_
Mux08| IOPin 5 1 ( 59)| A_17_
Mux09| IOPin 7 3 ( 82)| AS_030
-Mux10| Mcel 7 1 ( 271)| inst_CLK_000_D
+Mux10| Input Pin ( 36)| VPA
Mux11| IOPin 0 5 ( 96)| A_16_
Mux12| IOPin 0 6 ( 97)| A_19_
-Mux13| Mcel 6 8 ( 257)| SM_AMIGA_2_
-Mux14| Input Pin ( 11)| CLK_000
-Mux15| Input Pin ( 14)| CPU_SPACE
+Mux13| Mcel 7 5 ( 277)| inst_CLK_OUT_PRE
+Mux14| Mcel 7 2 ( 272)| SM_AMIGA_0_
+Mux15| ... | ...
Mux16| ... | ...
Mux17| IOPin 0 4 ( 95)| A_18_
Mux18| IOPin 3 7 ( 28)| BGACK_000
-Mux19| Mcel 7 13 ( 289)| SM_AMIGA_0_
+Mux19| Mcel 7 1 ( 271)| inst_AS_030_000_SYNC
Mux20| Input Pin ( 64)| CLK_030
-Mux21| Input Pin ( 61)| CLK_OSZI
+Mux21| Mcel 7 6 ( 278)| CLK_CNT_0_
Mux22| ... | ...
Mux23| Mcel 7 4 ( 275)| RN_BGACK_030
Mux24| Mcel 3 5 ( 181)| RN_AS_000
Mux25| ... | ...
Mux26| ... | ...
-Mux27| Mcel 7 5 ( 277)| inst_CLK_OUT_PRE
-Mux28| ... | ...
-Mux29| Mcel 3 13 ( 193)| inst_CLK_000_DD
+Mux27| Mcel 7 9 ( 283)| SM_AMIGA_7_
+Mux28| Mcel 6 8 ( 257)| inst_CLK_000_D0
+Mux29| Mcel 3 13 ( 193)| inst_CLK_000_D1
Mux30| Mcel 7 0 ( 269)| RN_FPU_CS
Mux31| ... | ...
Mux32| ... | ...
diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt
index cddfa87..914eedd 100644
--- a/Logic/68030_tk.rpt
+++ b/Logic/68030_tk.rpt
@@ -12,7 +12,7 @@ Project_Summary
Project Name : 68030_tk
Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic
-Project Fitted on : Thu May 15 23:02:50 2014
+Project Fitted on : Fri May 16 17:07:12 2014
Device : M4A5-128/64
Package : 100TQFP
@@ -58,7 +58,7 @@ Logic Macrocells 128 43 85 --> 33%
Input Registers 64 0 64 --> 0%
Unusable Macrocells .. 0 ..
-CSM Outputs/Total Block Inputs 264 119 145 --> 45%
+CSM Outputs/Total Block Inputs 264 112 152 --> 42%
Logical Product Terms 640 103 537 --> 16%
Product Term Clusters 128 37 91 --> 28%
@@ -76,9 +76,9 @@ Block B 11 8 0 5 0 11 11 13 Hi
Block C 1 8 0 2 0 14 2 16 Hi
Block D 29 8 0 12 0 4 44 3 Hi
Block E 14 3 0 3 0 13 3 16 Hi
-Block F 12 4 0 1 0 15 4 15 Hi
-Block G 20 7 0 8 0 8 17 10 Hi
-Block H 25 8 0 10 0 6 19 9 Hi
+Block F 5 4 0 1 0 15 2 15 Hi
+Block G 20 7 0 8 0 8 18 10 Hi
+Block H 25 8 0 10 0 6 20 9 Hi
---------------------------------------------------------------------------------
Four rightmost columns above reflect last status of the placement process.
@@ -180,7 +180,7 @@ Pin No| Type |Pad |Pin | Signal name
11 | CkIn | | * |CLK_000
12 | Vcc | | |
13 | GND | | |
-14 | CkIn | | * |CPU_SPACE
+14 | CkIn | | |nEXP_SPACE
15 | I_O | C0 | * |A_28_
16 | I_O | C1 | * |A_27_
17 | I_O | C2 | * |A_26_
@@ -287,12 +287,12 @@ Input_Signal_List
Pin r e O Input
Pin Blk PTs Type e s E Fanout Pwr Slew Signal
----------------------------------------------------------------------
- 82 H . I/O ---D-FGH Hi Fast AS_030
+ 82 H . I/O ---D--GH Hi Fast AS_030
69 G . I/O ---D---- Hi Fast A_0_
- 96 A . I/O -----F-H Hi Fast A_16_
- 59 F . I/O -----F-H Hi Fast A_17_
- 95 A . I/O -----F-H Hi Fast A_18_
- 97 A . I/O -----F-H Hi Fast A_19_
+ 96 A . I/O -------H Hi Fast A_16_
+ 59 F . I/O -------H Hi Fast A_17_
+ 95 A . I/O -------H Hi Fast A_18_
+ 97 A . I/O -------H Hi Fast A_19_
93 A . I/O ----E--- Hi Fast A_20_
94 A . I/O ----E--- Hi Fast A_21_
85 H . I/O ----E--- Hi Fast A_22_
@@ -305,22 +305,22 @@ Pin Blk PTs Type e s E Fanout Pwr Slew Signal
6 B . I/O ----E--- Hi Fast A_29_
5 B . I/O ----E--- Hi Fast A_30_
4 B . I/O ----E--- Hi Fast A_31_
- 28 D . I/O -----F-H Hi Fast BGACK_000
+ 28 D . I/O -------H Hi Fast BGACK_000
21 C . I/O ---D---- Hi Fast BG_030
98 A . I/O ---D---- Hi Fast DS_030
- 57 F . I/O -----F-H Hi Fast FC_0_
- 58 F . I/O -----F-H Hi Fast FC_1_
+ 57 F . I/O -------H Hi Fast FC_0_
+ 58 F . I/O -------H Hi Fast FC_1_
67 G . I/O -B------ Hi Fast IPL_0_
56 F . I/O -B------ Hi Fast IPL_1_
68 G . I/O -B------ Hi Fast IPL_2_
71 G . I/O ---DE--- Hi Fast RW
70 G . I/O ---D---- Hi Fast SIZE_0_
79 H . I/O ---D---- Hi Fast SIZE_1_
- 11 . . Ck/I -------H - Fast CLK_000
- 14 . . Ck/I ---D-F-H - Fast CPU_SPACE
- 36 . . Ded ------G- - Fast VPA
+ 11 . . Ck/I ------G- - Fast CLK_000
+ 14 . . Ck/I ---D---H - Fast nEXP_SPACE
+ 36 . . Ded -------H - Fast VPA
61 . . Ck/I AB-D-FGH - Fast CLK_OSZI
- 64 . . Ck/I ---D-F-H - Fast CLK_030
+ 64 . . Ck/I ---D---H - Fast CLK_030
86 . . Ded AB-D-FGH - Fast RST
----------------------------------------------------------------------
@@ -404,23 +404,23 @@ Buried_Signal_List
D8 D 12 DFF * * ---D---- Hi - RN_LDS_000 --> LDS_000
D12 D 8 DFF * * ---D---- Hi - RN_UDS_000 --> UDS_000
D4 D 2 TFF * * ---D--G- Hi - RN_VMA --> VMA
- H13 H 3 DFF * * -------H Hi Fast SM_AMIGA_0_
- H2 H 3 DFF * * -------H Hi Fast SM_AMIGA_1_
- G8 G 3 DFF * * ------GH Hi Fast SM_AMIGA_2_
+ H2 H 3 DFF * * -------H Hi Fast SM_AMIGA_0_
+ G12 G 3 DFF * * ------GH Hi Fast SM_AMIGA_1_
+ G1 G 3 DFF * * ------G- Hi Fast SM_AMIGA_2_
G5 G 3 DFF * * ------G- Hi Fast SM_AMIGA_3_
- G12 G 2 DFF * * ---D--G- Hi Fast SM_AMIGA_4_
- A0 A 2 DFF * * A-----G- Hi Fast SM_AMIGA_5_
+ F0 F 2 DFF * * ---D-FG- Hi Fast SM_AMIGA_4_
+ A0 A 2 DFF * * A----F-- Hi Fast SM_AMIGA_5_
D6 D 3 DFF * * A--D---- Hi Fast SM_AMIGA_6_
H9 H 2 DFF * * ---D---H Hi Fast SM_AMIGA_7_
D14 D 3 DFF * * ---D--G- Hi Fast cpu_est_0_
D2 D 4 TFF * * ---D--G- Hi Fast cpu_est_1_
D10 D 3 DFF * * ---D--G- Hi Fast cpu_est_2_
- F0 F 4 DFF * * A--D-F-- Hi Fast inst_AS_030_000_SYNC
- H1 H 1 DFF * * AB-D--GH Hi Fast inst_CLK_000_D
- D13 D 1 DFF * * AB-D--GH Hi Fast inst_CLK_000_DD
+ H1 H 4 DFF * * A--D---H Hi Fast inst_AS_030_000_SYNC
+ G8 G 1 DFF * * AB-D-FGH Hi Fast inst_CLK_000_D0
+ D13 D 1 DFF * * AB-D--GH Hi Fast inst_CLK_000_D1
H5 H 2 DFF * * -B----GH Hi Fast inst_CLK_OUT_PRE
G13 G 2 DFF * * ------G- Hi Fast inst_DTACK_SYNC
- G1 G 1 DFF * * ---D--G- Hi Fast inst_VPA_D
+ H13 H 1 DFF * * ---D--G- Hi Fast inst_VPA_D
G9 G 2 DFF * * ------G- Hi Fast inst_VPA_SYNC
----------------------------------------------------------------------
@@ -436,38 +436,34 @@ Signals_Fanout_List
~~~~~~~~~~~~~~~~~~~
Signal Source : Fanout List
-----------------------------------------------------------------------------
- A_21_{ B}: CIIN{ E}
- A_20_{ B}: CIIN{ E}
+ A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H}
+ A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H}
SIZE_1_{ I}: LDS_000{ D}
- A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ F}
- A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ F}
A_31_{ C}: CIIN{ E}
- A_17_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ F}
- A_16_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ F}
IPL_2_{ H}: IPL_030_2_{ B}
- FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ F}
+ FC_1_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H}
AS_030{ I}: DSACK_1_{ H} AS_000{ D} UDS_000{ D}
: LDS_000{ D} BG_000{ D} FPU_CS{ H}
- :inst_AS_030_000_SYNC{ F}inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G}
+ :inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G}
DS_030{ B}: UDS_000{ D} LDS_000{ D}
- CPU_SPACE{. }: DSACK_0_{ H} DSACK_1_{ H} BG_000{ D}
- :inst_AS_030_000_SYNC{ F}
- BG_030{ D}: BG_000{ D}
A_0_{ H}: UDS_000{ D} LDS_000{ D}
- BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ F}
- CLK_030{. }: BG_000{ D} FPU_CS{ H}inst_AS_030_000_SYNC{ F}
+ nEXP_SPACE{. }: DSACK_0_{ H}AMIGA_BUS_ENABLE{ D} DSACK_1_{ H}
+ : BG_000{ D}inst_AS_030_000_SYNC{ H}
+ BG_030{ D}: BG_000{ D}
IPL_1_{ G}: IPL_030_1_{ B}
- CLK_000{. }: inst_CLK_000_D{ H}
IPL_0_{ H}: IPL_030_0_{ B}
- FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ F}
- VPA{. }: inst_VPA_D{ G}
+ BGACK_000{ E}: BGACK_030{ H} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
+ FC_0_{ G}: FPU_CS{ H}inst_AS_030_000_SYNC{ H}
+ CLK_030{. }: BG_000{ D} FPU_CS{ H}inst_AS_030_000_SYNC{ H}
+ CLK_000{. }:inst_CLK_000_D0{ G}
+ VPA{. }: inst_VPA_D{ H}
RST{. }: IPL_030_2_{ B} DSACK_1_{ H} AS_000{ D}
- : UDS_000{ D} LDS_000{ D} BG_000{ D}
- : BGACK_030{ H} IPL_030_1_{ B} IPL_030_0_{ B}
+ : UDS_000{ D} LDS_000{ D} IPL_030_1_{ B}
+ : IPL_030_0_{ B} BG_000{ D} BGACK_030{ H}
: FPU_CS{ H} DTACK{ D} VMA{ D}
- : RESET{ B}inst_AS_030_000_SYNC{ F}inst_DTACK_SYNC{ G}
+ : RESET{ B}inst_AS_030_000_SYNC{ H}inst_DTACK_SYNC{ G}
: inst_VPA_SYNC{ G} SM_AMIGA_6_{ D} SM_AMIGA_7_{ H}
- : SM_AMIGA_1_{ H} SM_AMIGA_4_{ G} SM_AMIGA_3_{ G}
+ : SM_AMIGA_1_{ G} SM_AMIGA_4_{ F} SM_AMIGA_3_{ G}
: SM_AMIGA_5_{ A} SM_AMIGA_2_{ G} SM_AMIGA_0_{ H}
RW{ H}:AMIGA_BUS_DATA_DIR{ E} UDS_000{ D} LDS_000{ D}
SIZE_0_{ H}: LDS_000{ D}
@@ -480,6 +476,10 @@ Signal Source : Fanout List
A_24_{ D}: CIIN{ E}
A_23_{ I}: CIIN{ E}
A_22_{ I}: CIIN{ E}
+ A_21_{ B}: CIIN{ E}
+ A_20_{ B}: CIIN{ E}
+ A_19_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H}
+ A_18_{ B}: FPU_CS{ H}inst_AS_030_000_SYNC{ H}
RN_IPL_030_2_{ C}: IPL_030_2_{ B}
DSACK_1_{ I}: DTACK{ D}
RN_DSACK_1_{ I}: DSACK_1_{ H}
@@ -487,11 +487,11 @@ RN_DSACK_1_{ I}: DSACK_1_{ H}
: SM_AMIGA_7_{ H} SM_AMIGA_0_{ H}
RN_UDS_000{ E}: UDS_000{ D}
RN_LDS_000{ E}: LDS_000{ D}
+RN_IPL_030_1_{ C}: IPL_030_1_{ B}
+RN_IPL_030_0_{ C}: IPL_030_0_{ B}
RN_BG_000{ E}: BG_000{ D}
RN_BGACK_030{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D}
: BGACK_030{ H} DTACK{ D}
-RN_IPL_030_1_{ C}: IPL_030_1_{ B}
-RN_IPL_030_0_{ C}: IPL_030_0_{ B}
RN_FPU_CS{ I}: BERR{ E} AVEC_EXP{ C} FPU_CS{ H}
DTACK{ E}:inst_DTACK_SYNC{ G}
RN_E{ H}: E{ G} VMA{ D} cpu_est_1_{ D}
@@ -501,39 +501,40 @@ RN_IPL_030_0_{ C}: IPL_030_0_{ B}
: cpu_est_1_{ D} inst_VPA_SYNC{ G} cpu_est_2_{ D}
cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_1_{ D}
: inst_VPA_SYNC{ G} cpu_est_2_{ D}
-inst_AS_030_000_SYNC{ G}: AS_000{ D} UDS_000{ D} LDS_000{ D}
- :inst_AS_030_000_SYNC{ F} SM_AMIGA_6_{ D} SM_AMIGA_5_{ A}
+inst_AS_030_000_SYNC{ I}: AS_000{ D} UDS_000{ D} LDS_000{ D}
+ :inst_AS_030_000_SYNC{ H} SM_AMIGA_6_{ D} SM_AMIGA_5_{ A}
inst_DTACK_SYNC{ H}:inst_DTACK_SYNC{ G} SM_AMIGA_3_{ G} SM_AMIGA_2_{ G}
- inst_VPA_D{ H}: VMA{ D}inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G}
+ inst_VPA_D{ I}: VMA{ D}inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G}
inst_VPA_SYNC{ H}: inst_VPA_SYNC{ G} SM_AMIGA_3_{ G} SM_AMIGA_2_{ G}
-inst_CLK_000_D{ I}: IPL_030_2_{ B} DSACK_1_{ H} AS_000{ D}
- : UDS_000{ D} LDS_000{ D} BGACK_030{ H}
- : IPL_030_1_{ B} IPL_030_0_{ B} E{ G}
- : VMA{ D} cpu_est_0_{ D} cpu_est_1_{ D}
- :inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G}inst_CLK_000_DD{ D}
- : cpu_est_2_{ D} SM_AMIGA_6_{ D} SM_AMIGA_7_{ H}
- : SM_AMIGA_1_{ H} SM_AMIGA_4_{ G} SM_AMIGA_3_{ G}
- : SM_AMIGA_5_{ A} SM_AMIGA_2_{ G} SM_AMIGA_0_{ H}
-inst_CLK_000_DD{ E}: IPL_030_2_{ B} AS_000{ D} UDS_000{ D}
- : LDS_000{ D} BGACK_030{ H} IPL_030_1_{ B}
- : IPL_030_0_{ B} E{ G} cpu_est_0_{ D}
- : cpu_est_1_{ D} cpu_est_2_{ D} SM_AMIGA_6_{ D}
- : SM_AMIGA_5_{ A}
+inst_CLK_000_D0{ H}: IPL_030_2_{ B} AS_000{ D} UDS_000{ D}
+ : LDS_000{ D} IPL_030_1_{ B} IPL_030_0_{ B}
+ : BGACK_030{ H} E{ G} VMA{ D}
+ : cpu_est_0_{ D} cpu_est_1_{ D}inst_DTACK_SYNC{ G}
+ : inst_VPA_SYNC{ G}inst_CLK_000_D1{ D} cpu_est_2_{ D}
+ : SM_AMIGA_6_{ D} SM_AMIGA_7_{ H} SM_AMIGA_1_{ G}
+ : SM_AMIGA_4_{ F} SM_AMIGA_3_{ G} SM_AMIGA_5_{ A}
+ : SM_AMIGA_2_{ G} SM_AMIGA_0_{ H}
+inst_CLK_000_D1{ E}: IPL_030_2_{ B} DSACK_1_{ H} AS_000{ D}
+ : UDS_000{ D} LDS_000{ D} IPL_030_1_{ B}
+ : IPL_030_0_{ B} BGACK_030{ H} E{ G}
+ : cpu_est_0_{ D} cpu_est_1_{ D} cpu_est_2_{ D}
+ : SM_AMIGA_6_{ D} SM_AMIGA_1_{ G} SM_AMIGA_5_{ A}
+ : SM_AMIGA_0_{ H}
inst_CLK_OUT_PRE{ I}: CLK_DIV_OUT{ G} DSACK_1_{ H} CLK_EXP{ B}
- :inst_CLK_OUT_PRE{ H} SM_AMIGA_1_{ H} SM_AMIGA_0_{ H}
+ :inst_CLK_OUT_PRE{ H} SM_AMIGA_1_{ G} SM_AMIGA_0_{ H}
cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ D}
: inst_VPA_SYNC{ G} cpu_est_2_{ D}
CLK_CNT_0_{ I}:inst_CLK_OUT_PRE{ H} CLK_CNT_0_{ H}
SM_AMIGA_6_{ E}: AS_000{ D} UDS_000{ D} LDS_000{ D}
: BG_000{ D} SM_AMIGA_6_{ D} SM_AMIGA_5_{ A}
SM_AMIGA_7_{ I}: BG_000{ D} SM_AMIGA_6_{ D} SM_AMIGA_7_{ H}
-SM_AMIGA_1_{ I}: DSACK_1_{ H} SM_AMIGA_1_{ H} SM_AMIGA_0_{ H}
-SM_AMIGA_4_{ H}: UDS_000{ D} LDS_000{ D} SM_AMIGA_4_{ G}
+SM_AMIGA_1_{ H}: DSACK_1_{ H} SM_AMIGA_1_{ G} SM_AMIGA_0_{ H}
+SM_AMIGA_4_{ G}: UDS_000{ D} LDS_000{ D} SM_AMIGA_4_{ F}
: SM_AMIGA_3_{ G}
SM_AMIGA_3_{ H}:inst_DTACK_SYNC{ G} inst_VPA_SYNC{ G} SM_AMIGA_3_{ G}
: SM_AMIGA_2_{ G}
-SM_AMIGA_5_{ B}: SM_AMIGA_4_{ G} SM_AMIGA_5_{ A}
-SM_AMIGA_2_{ H}: SM_AMIGA_1_{ H} SM_AMIGA_2_{ G}
+SM_AMIGA_5_{ B}: SM_AMIGA_4_{ F} SM_AMIGA_5_{ A}
+SM_AMIGA_2_{ H}: SM_AMIGA_1_{ G} SM_AMIGA_2_{ G}
SM_AMIGA_0_{ I}: SM_AMIGA_7_{ H} SM_AMIGA_0_{ H}
-----------------------------------------------------------------------------
@@ -552,10 +553,10 @@ Equations :
+-----+-----+-----+-----+------------------------
| | | | | AVEC
| * | S | BS | BR | SM_AMIGA_5_
+| | | | | DS_030
| | | | | A_19_
| | | | | A_16_
| | | | | A_18_
-| | | | | DS_030
| | | | | A_21_
| | | | | A_20_
@@ -611,7 +612,7 @@ Equations :
| * | S | BS | BR | VMA
| * | S | BS | BR | AS_000
| | | | | AMIGA_BUS_ENABLE
-| * | A | | | inst_CLK_000_DD
+| * | A | | | inst_CLK_000_D1
| * | A | | | cpu_est_1_
| * | S | BR | BS | SM_AMIGA_6_
| * | A | | | cpu_est_2_
@@ -637,13 +638,13 @@ Equations :
Block F
-block level set pt : !RST
-block level reset pt : GND
+block level set pt : GND
+block level reset pt : !RST
Equations :
| | |Block|Block| Signal
| Reg |Mode |Set |Reset| Name
+-----+-----+-----+-----+------------------------
-| * | S | BS | BR | inst_AS_030_000_SYNC
+| * | S | BS | BR | SM_AMIGA_4_
| | | | | A_17_
| | | | | FC_1_
| | | | | FC_0_
@@ -659,10 +660,10 @@ Equations :
+-----+-----+-----+-----+------------------------
| * | S | BS | BR | E
| * | S | BS | BR | CLK_DIV_OUT
+| * | S | BS | BR | inst_CLK_000_D0
| * | S | BS | BR | RN_E
+| * | A | | | SM_AMIGA_1_
| * | A | | | SM_AMIGA_2_
-| * | A | | | SM_AMIGA_4_
-| * | S | BS | BR | inst_VPA_D
| * | A | | | SM_AMIGA_3_
| * | A | | | inst_VPA_SYNC
| * | A | | | inst_DTACK_SYNC
@@ -684,13 +685,13 @@ Equations :
| * | S | BS | BR | BGACK_030
| * | S | BS | BR | FPU_CS
| | | | | DSACK_0_
-| * | A | | | inst_CLK_000_D
+| * | S | BS | BR | inst_AS_030_000_SYNC
| * | S | BS | BR | RN_FPU_CS
| * | A | | | inst_CLK_OUT_PRE
| * | S | BS | BR | RN_BGACK_030
| * | S | BS | BR | SM_AMIGA_7_
+| * | A | | | inst_VPA_D
| * | S | BR | BS | SM_AMIGA_0_
-| * | S | BR | BS | SM_AMIGA_1_
| * | S | BS | BR | RN_DSACK_1_
| * | A | | | CLK_CNT_0_
| | | | | AS_030
@@ -714,19 +715,19 @@ BLOCK_A_LOGIC_ARRAY_FANIN
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx A0 RST pin 86 mx A17 ... ...
-mx A1 inst_CLK_000_DD mcell D13 mx A18 ... ...
+mx A1 inst_CLK_000_D1 mcell D13 mx A18 ... ...
mx A2 ... ... mx A19 ... ...
mx A3 ... ... mx A20 ... ...
mx A4 CLK_OSZI pin 61 mx A21 ... ...
-mx A5inst_AS_030_000_SYNC mcell F0 mx A22 ... ...
+mx A5 ... ... mx A22 ... ...
mx A6 ... ... mx A23 ... ...
mx A7 ... ... mx A24 ... ...
mx A8 ... ... mx A25 ... ...
mx A9 ... ... mx A26 ... ...
-mx A10 inst_CLK_000_D mcell H1 mx A27 ... ...
+mx A10inst_AS_030_000_SYNC mcell H1 mx A27 ... ...
mx A11 ... ... mx A28 ... ...
mx A12 ... ... mx A29 ... ...
-mx A13 ... ... mx A30 ... ...
+mx A13 inst_CLK_000_D0 mcell G8 mx A30 ... ...
mx A14 ... ... mx A31 ... ...
mx A15 SM_AMIGA_5_ mcell A0 mx A32 ... ...
mx A16 SM_AMIGA_6_ mcell D6
@@ -738,7 +739,7 @@ BLOCK_B_LOGIC_ARRAY_FANIN
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx B0 IPL_0_ pin 67 mx B17 ... ...
-mx B1 inst_CLK_000_DD mcell D13 mx B18 ... ...
+mx B1 inst_CLK_000_D1 mcell D13 mx B18 ... ...
mx B2 ... ... mx B19 ... ...
mx B3 IPL_1_ pin 56 mx B20 ... ...
mx B4 IPL_2_ pin 68 mx B21 RST pin 86
@@ -747,7 +748,7 @@ mx B6 ... ... mx B23 ... ...
mx B7 ... ... mx B24 ... ...
mx B8 RN_IPL_030_0_ mcell B8 mx B25 ... ...
mx B9 ... ... mx B26 ... ...
-mx B10 inst_CLK_000_D mcell H1 mx B27 RN_IPL_030_2_ mcell B4
+mx B10 inst_CLK_000_D0 mcell G8 mx B27 RN_IPL_030_2_ mcell B4
mx B11 ... ... mx B28 ... ...
mx B12 RN_IPL_030_1_ mcell B12 mx B29 CLK_OSZI pin 61
mx B13inst_CLK_OUT_PRE mcell H5 mx B30 ... ...
@@ -786,22 +787,22 @@ BLOCK_D_LOGIC_ARRAY_FANIN
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx D0 SIZE_0_ pin 70 mx D17 RN_BG_000 mcell D1
-mx D1 inst_CLK_000_DD mcell D13 mx D18 A_0_ pin 69
-mx D2 RN_E mcell G4 mx D19 ... ...
-mx D3 cpu_est_1_ mcell D2 mx D20 cpu_est_2_ mcell D10
-mx D4 inst_VPA_D mcell G1 mx D21 RN_VMA mcell D4
-mx D5 DS_030 pin 98 mx D22 BG_030 pin 21
+mx D1 inst_CLK_000_D1 mcell D13 mx D18 A_0_ pin 69
+mx D2 RN_E mcell G4 mx D19inst_AS_030_000_SYNC mcell H1
+mx D3 cpu_est_1_ mcell D2 mx D20 CLK_030 pin 64
+mx D4 BG_030 pin 21 mx D21 RST pin 86
+mx D5 RN_LDS_000 mcell D8 mx D22 ... ...
mx D6 SIZE_1_ pin 79 mx D23 RN_BGACK_030 mcell H4
-mx D7 RN_AS_000 mcell D5 mx D24 RST pin 86
-mx D8 RW pin 71 mx D25inst_AS_030_000_SYNC mcell F0
+mx D7 inst_VPA_D mcell H13 mx D24 RN_AS_000 mcell D5
+mx D8 RW pin 71 mx D25 SM_AMIGA_4_ mcell F0
mx D9 AS_030 pin 82 mx D26 ... ...
mx D10 cpu_est_0_ mcell D14 mx D27 SM_AMIGA_7_ mcell H9
-mx D11 RN_UDS_000 mcell D12 mx D28 CLK_030 pin 64
-mx D12 inst_CLK_000_D mcell H1 mx D29 CLK_OSZI pin 61
-mx D13 ... ... mx D30 SM_AMIGA_6_ mcell D6
-mx D14 SM_AMIGA_4_ mcell G12 mx D31 ... ...
-mx D15 CPU_SPACE pin 14 mx D32 DSACK_1_ pin 81
-mx D16 RN_LDS_000 mcell D8
+mx D11 RN_UDS_000 mcell D12 mx D28 ... ...
+mx D12 DS_030 pin 98 mx D29 CLK_OSZI pin 61
+mx D13 inst_CLK_000_D0 mcell G8 mx D30 cpu_est_2_ mcell D10
+mx D14 RN_VMA mcell D4 mx D31 ... ...
+mx D15 nEXP_SPACE pin 14 mx D32 DSACK_1_ pin 81
+mx D16 SM_AMIGA_6_ mcell D6
----------------------------------------------------------------------------
@@ -833,22 +834,22 @@ BLOCK_F_LOGIC_ARRAY_FANIN
~~~~~~~~~~~~~~~~~~~~~~~~~
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
-mx F0 RST pin 86 mx F17 A_18_ pin 95
-mx F1 FC_1_ pin 58 mx F18 ... ...
+mx F0 RST pin 86 mx F17 ... ...
+mx F1 ... ... mx F18 ... ...
mx F2 ... ... mx F19 ... ...
-mx F3 ... ... mx F20 CLK_030 pin 64
-mx F4 BGACK_000 pin 28 mx F21 ... ...
-mx F5 CPU_SPACE pin 14 mx F22 ... ...
-mx F6 FC_0_ pin 57 mx F23 ... ...
+mx F3 ... ... mx F20 ... ...
+mx F4 CLK_OSZI pin 61 mx F21 ... ...
+mx F5 SM_AMIGA_4_ mcell F0 mx F22 ... ...
+mx F6 ... ... mx F23 ... ...
mx F7 ... ... mx F24 ... ...
-mx F8 A_17_ pin 59 mx F25inst_AS_030_000_SYNC mcell F0
-mx F9 AS_030 pin 82 mx F26 ... ...
-mx F10 ... ... mx F27 ... ...
-mx F11 A_16_ pin 96 mx F28 ... ...
-mx F12 A_19_ pin 97 mx F29 ... ...
+mx F8 ... ... mx F25 ... ...
+mx F9 ... ... mx F26 ... ...
+mx F10 inst_CLK_000_D0 mcell G8 mx F27 ... ...
+mx F11 ... ... mx F28 ... ...
+mx F12 ... ... mx F29 ... ...
mx F13 ... ... mx F30 ... ...
mx F14 ... ... mx F31 ... ...
-mx F15 ... ... mx F32 ... ...
+mx F15 SM_AMIGA_5_ mcell A0 mx F32 ... ...
mx F16 ... ...
----------------------------------------------------------------------------
@@ -858,21 +859,21 @@ BLOCK_G_LOGIC_ARRAY_FANIN
CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx G0 RST pin 86 mx G17 cpu_est_0_ mcell D14
-mx G1 inst_CLK_000_DD mcell D13 mx G18 ... ...
-mx G2 cpu_est_2_ mcell D10 mx G19 inst_CLK_000_D mcell H1
-mx G3 SM_AMIGA_3_ mcell G5 mx G20 ... ...
-mx G4inst_CLK_OUT_PRE mcell H5 mx G21 CLK_OSZI pin 61
-mx G5 ... ... mx G22 ... ...
-mx G6 ... ... mx G23 DTACK pin 30
-mx G7 SM_AMIGA_4_ mcell G12 mx G24 inst_VPA_D mcell G1
+mx G1 inst_CLK_000_D1 mcell D13 mx G18 ... ...
+mx G2 cpu_est_2_ mcell D10 mx G19 AS_030 pin 82
+mx G3 CLK_000 pin 11 mx G20 ... ...
+mx G4 CLK_OSZI pin 61 mx G21 ... ...
+mx G5 SM_AMIGA_4_ mcell F0 mx G22 SM_AMIGA_3_ mcell G5
+mx G6 ... ... mx G23 SM_AMIGA_1_ mcell G12
+mx G7 inst_VPA_D mcell H13 mx G24 SM_AMIGA_2_ mcell G1
mx G8 ... ... mx G25 ... ...
-mx G9 AS_030 pin 82 mx G26 ... ...
-mx G10 VPA pin 36 mx G27 inst_VPA_SYNC mcell G9
-mx G11 RN_E mcell G4 mx G28 ... ...
+mx G9 DTACK pin 30 mx G26 ... ...
+mx G10 inst_VPA_SYNC mcell G9 mx G27 ... ...
+mx G11 RN_E mcell G4 mx G28 inst_CLK_000_D0 mcell G8
mx G12 inst_DTACK_SYNC mcell G13 mx G29 ... ...
-mx G13 SM_AMIGA_2_ mcell G8 mx G30 ... ...
+mx G13inst_CLK_OUT_PRE mcell H5 mx G30 ... ...
mx G14 RN_VMA mcell D4 mx G31 ... ...
-mx G15 SM_AMIGA_5_ mcell A0 mx G32 ... ...
+mx G15 ... ... mx G32 ... ...
mx G16 cpu_est_1_ mcell D2
----------------------------------------------------------------------------
@@ -883,20 +884,20 @@ CSM Signal Source CSM Signal Source
------------------------------------ ------------------------------------
mx H0 RST pin 86 mx H17 A_18_ pin 95
mx H1 FC_1_ pin 58 mx H18 BGACK_000 pin 28
-mx H2 ... ... mx H19 SM_AMIGA_0_ mcell H13
+mx H2 ... ... mx H19inst_AS_030_000_SYNC mcell H1
mx H3 RN_DSACK_1_ mcell H8 mx H20 CLK_030 pin 64
-mx H4 SM_AMIGA_1_ mcell H2 mx H21 CLK_OSZI pin 61
-mx H5 SM_AMIGA_7_ mcell H9 mx H22 ... ...
+mx H4 CLK_OSZI pin 61 mx H21 CLK_CNT_0_ mcell H6
+mx H5 nEXP_SPACE pin 14 mx H22 ... ...
mx H6 FC_0_ pin 57 mx H23 RN_BGACK_030 mcell H4
-mx H7 CLK_CNT_0_ mcell H6 mx H24 RN_AS_000 mcell D5
+mx H7 SM_AMIGA_1_ mcell G12 mx H24 RN_AS_000 mcell D5
mx H8 A_17_ pin 59 mx H25 ... ...
mx H9 AS_030 pin 82 mx H26 ... ...
-mx H10 inst_CLK_000_D mcell H1 mx H27inst_CLK_OUT_PRE mcell H5
-mx H11 A_16_ pin 96 mx H28 ... ...
-mx H12 A_19_ pin 97 mx H29 inst_CLK_000_DD mcell D13
-mx H13 SM_AMIGA_2_ mcell G8 mx H30 RN_FPU_CS mcell H0
-mx H14 CLK_000 pin 11 mx H31 ... ...
-mx H15 CPU_SPACE pin 14 mx H32 ... ...
+mx H10 VPA pin 36 mx H27 SM_AMIGA_7_ mcell H9
+mx H11 A_16_ pin 96 mx H28 inst_CLK_000_D0 mcell G8
+mx H12 A_19_ pin 97 mx H29 inst_CLK_000_D1 mcell D13
+mx H13inst_CLK_OUT_PRE mcell H5 mx H30 RN_FPU_CS mcell H0
+mx H14 SM_AMIGA_0_ mcell H2 mx H31 ... ...
+mx H15 ... ... mx H32 ... ...
mx H16 ... ...
----------------------------------------------------------------------------
@@ -921,7 +922,7 @@ PostFit_Equations
1 0 1 Pin AVEC
0 0 1 Pin AVEC_EXP
1 1 1 Pin AVEC_EXP.OE
- 0 0 1 Pin AMIGA_BUS_ENABLE
+ 1 1 1 Pin AMIGA_BUS_ENABLE
1 1 1 Pin AMIGA_BUS_DATA_DIR
1 0 1 Pin AMIGA_BUS_ENABLE_LOW
1 4 1 Pin CIIN
@@ -945,18 +946,18 @@ PostFit_Equations
12 12 1 Pin LDS_000.D-
1 1 1 Pin LDS_000.AP
1 1 1 Pin LDS_000.C
- 3 7 1 Pin BG_000.D-
- 1 1 1 Pin BG_000.AP
- 1 1 1 Pin BG_000.C
- 2 4 1 Pin BGACK_030.D
- 1 1 1 Pin BGACK_030.AP
- 1 1 1 Pin BGACK_030.C
3 4 1 Pin IPL_030_1_.D
1 1 1 Pin IPL_030_1_.AP
1 1 1 Pin IPL_030_1_.C
3 4 1 Pin IPL_030_0_.D
1 1 1 Pin IPL_030_0_.AP
1 1 1 Pin IPL_030_0_.C
+ 3 7 1 Pin BG_000.D-
+ 1 1 1 Pin BG_000.AP
+ 1 1 1 Pin BG_000.C
+ 2 4 1 Pin BGACK_030.D
+ 1 1 1 Pin BGACK_030.AP
+ 1 1 1 Pin BGACK_030.C
1 1 1 Pin CLK_EXP.D
1 1 1 Pin CLK_EXP.C
2 10 1 Pin FPU_CS.D-
@@ -988,10 +989,10 @@ PostFit_Equations
2 10 1 Node inst_VPA_SYNC.D-
1 1 1 Node inst_VPA_SYNC.AP
1 1 1 Node inst_VPA_SYNC.C
- 1 1 1 Node inst_CLK_000_D.D
- 1 1 1 Node inst_CLK_000_D.C
- 1 1 1 Node inst_CLK_000_DD.D
- 1 1 1 Node inst_CLK_000_DD.C
+ 1 1 1 Node inst_CLK_000_D0.D
+ 1 1 1 Node inst_CLK_000_D0.C
+ 1 1 1 Node inst_CLK_000_D1.D
+ 1 1 1 Node inst_CLK_000_D1.C
2 2 1 Node inst_CLK_OUT_PRE.D
1 1 1 Node inst_CLK_OUT_PRE.C
3 6 1 NodeX1 cpu_est_2_.D.X1
@@ -1006,7 +1007,7 @@ PostFit_Equations
1 1 1 Node SM_AMIGA_7_.AP
1 1 1 Node SM_AMIGA_7_.C
1 1 1 Node SM_AMIGA_1_.AR
- 3 4 1 Node SM_AMIGA_1_.D
+ 3 5 1 Node SM_AMIGA_1_.D
1 1 1 Node SM_AMIGA_1_.C
1 1 1 Node SM_AMIGA_4_.AR
2 3 1 Node SM_AMIGA_4_.D
@@ -1021,10 +1022,10 @@ PostFit_Equations
3 5 1 Node SM_AMIGA_2_.D
1 1 1 Node SM_AMIGA_2_.C
1 1 1 Node SM_AMIGA_0_.AR
- 3 5 1 Node SM_AMIGA_0_.D
+ 3 6 1 Node SM_AMIGA_0_.D
1 1 1 Node SM_AMIGA_0_.C
=========
- 167 P-Term Total: 167
+ 168 P-Term Total: 168
Total Pins: 59
Total Nodes: 19
Average P-Term/Output: 2
@@ -1038,7 +1039,7 @@ BERR.OE = (!FPU_CS.Q);
DSACK_0_ = (1);
-DSACK_0_.OE = (!CPU_SPACE);
+DSACK_0_.OE = (nEXP_SPACE);
CLK_DIV_OUT.D = (inst_CLK_OUT_PRE.Q);
@@ -1050,7 +1051,7 @@ AVEC_EXP = (0);
AVEC_EXP.OE = (!FPU_CS.Q);
-AMIGA_BUS_ENABLE = (0);
+AMIGA_BUS_ENABLE = (!nEXP_SPACE);
AMIGA_BUS_DATA_DIR = (!RW);
@@ -1060,18 +1061,18 @@ CIIN = (A_23_ & A_22_ & A_21_ & A_20_);
CIIN.OE = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_);
-IPL_030_2_.D = (IPL_030_2_.Q & !inst_CLK_000_D.Q
- # IPL_030_2_.Q & inst_CLK_000_DD.Q
- # IPL_2_ & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q);
+IPL_030_2_.D = (!inst_CLK_000_D0.Q & IPL_030_2_.Q
+ # inst_CLK_000_D1.Q & IPL_030_2_.Q
+ # IPL_2_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
IPL_030_2_.AP = (!RST);
IPL_030_2_.C = (CLK_OSZI);
-DSACK_1_.OE = (!CPU_SPACE);
+DSACK_1_.OE = (nEXP_SPACE);
!DSACK_1_.D = (!AS_030 & !DSACK_1_.Q
- # !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q);
+ # !inst_CLK_000_D1.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q);
DSACK_1_.AP = (!RST);
@@ -1080,7 +1081,7 @@ DSACK_1_.C = (CLK_OSZI);
AS_000.OE = (BGACK_030.Q);
!AS_000.D = (!AS_030 & !AS_000.Q
- # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q);
+ # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & SM_AMIGA_6_.Q);
AS_000.AP = (!RST);
@@ -1089,13 +1090,13 @@ AS_000.C = (CLK_OSZI);
UDS_000.OE = (BGACK_030.Q);
!UDS_000.D = (!AS_030 & DS_030 & !UDS_000.Q
- # !AS_030 & !inst_CLK_000_D.Q & !UDS_000.Q
+ # !AS_030 & !inst_CLK_000_D0.Q & !UDS_000.Q
# !AS_030 & RW & inst_AS_030_000_SYNC.Q & !UDS_000.Q
- # !AS_030 & RW & inst_CLK_000_DD.Q & !UDS_000.Q
+ # !AS_030 & RW & inst_CLK_000_D1.Q & !UDS_000.Q
# !AS_030 & RW & !SM_AMIGA_6_.Q & !UDS_000.Q
# !AS_030 & !RW & !UDS_000.Q & !SM_AMIGA_4_.Q
- # !DS_030 & !RW & !A_0_ & inst_CLK_000_D.Q & SM_AMIGA_4_.Q
- # !DS_030 & RW & !A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q);
+ # !DS_030 & !RW & !A_0_ & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q
+ # !DS_030 & RW & !A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & SM_AMIGA_6_.Q);
UDS_000.AP = (!RST);
@@ -1104,53 +1105,53 @@ UDS_000.C = (CLK_OSZI);
LDS_000.OE = (BGACK_030.Q);
!LDS_000.D = (!AS_030 & DS_030 & !LDS_000.Q
- # !AS_030 & !inst_CLK_000_D.Q & !LDS_000.Q
+ # !AS_030 & !inst_CLK_000_D0.Q & !LDS_000.Q
# !AS_030 & RW & inst_AS_030_000_SYNC.Q & !LDS_000.Q
- # !AS_030 & RW & inst_CLK_000_DD.Q & !LDS_000.Q
+ # !AS_030 & RW & inst_CLK_000_D1.Q & !LDS_000.Q
# !AS_030 & RW & !SM_AMIGA_6_.Q & !LDS_000.Q
# !AS_030 & !RW & !LDS_000.Q & !SM_AMIGA_4_.Q
- # SIZE_1_ & !DS_030 & !RW & inst_CLK_000_D.Q & SM_AMIGA_4_.Q
- # !DS_030 & !RW & !SIZE_0_ & inst_CLK_000_D.Q & SM_AMIGA_4_.Q
- # !DS_030 & !RW & A_0_ & inst_CLK_000_D.Q & SM_AMIGA_4_.Q
- # SIZE_1_ & !DS_030 & RW & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q
- # !DS_030 & RW & !SIZE_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q
- # !DS_030 & RW & A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q);
+ # SIZE_1_ & !DS_030 & !RW & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q
+ # !DS_030 & !RW & !SIZE_0_ & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q
+ # !DS_030 & !RW & A_0_ & inst_CLK_000_D0.Q & SM_AMIGA_4_.Q
+ # SIZE_1_ & !DS_030 & RW & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & SM_AMIGA_6_.Q
+ # !DS_030 & RW & !SIZE_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & SM_AMIGA_6_.Q
+ # !DS_030 & RW & A_0_ & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & SM_AMIGA_6_.Q);
LDS_000.AP = (!RST);
LDS_000.C = (CLK_OSZI);
+IPL_030_1_.D = (!inst_CLK_000_D0.Q & IPL_030_1_.Q
+ # inst_CLK_000_D1.Q & IPL_030_1_.Q
+ # IPL_1_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
+
+IPL_030_1_.AP = (!RST);
+
+IPL_030_1_.C = (CLK_OSZI);
+
+IPL_030_0_.D = (!inst_CLK_000_D0.Q & IPL_030_0_.Q
+ # inst_CLK_000_D1.Q & IPL_030_0_.Q
+ # IPL_0_ & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
+
+IPL_030_0_.AP = (!RST);
+
+IPL_030_0_.C = (CLK_OSZI);
+
!BG_000.D = (!BG_030 & CLK_030 & !BG_000.Q
- # AS_030 & !CPU_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_6_.Q
- # AS_030 & !CPU_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_7_.Q);
+ # AS_030 & !nEXP_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_6_.Q
+ # AS_030 & !nEXP_SPACE & !BG_030 & !CLK_030 & SM_AMIGA_7_.Q);
BG_000.AP = (!RST);
BG_000.C = (CLK_OSZI);
BGACK_030.D = (BGACK_000 & BGACK_030.Q
- # BGACK_000 & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q);
+ # BGACK_000 & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
BGACK_030.AP = (!RST);
BGACK_030.C = (CLK_OSZI);
-IPL_030_1_.D = (IPL_030_1_.Q & !inst_CLK_000_D.Q
- # IPL_030_1_.Q & inst_CLK_000_DD.Q
- # IPL_1_ & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q);
-
-IPL_030_1_.AP = (!RST);
-
-IPL_030_1_.C = (CLK_OSZI);
-
-IPL_030_0_.D = (!inst_CLK_000_D.Q & IPL_030_0_.Q
- # inst_CLK_000_DD.Q & IPL_030_0_.Q
- # IPL_0_ & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q);
-
-IPL_030_0_.AP = (!RST);
-
-IPL_030_0_.C = (CLK_OSZI);
-
CLK_EXP.D = (inst_CLK_OUT_PRE.Q);
CLK_EXP.C = (CLK_OSZI);
@@ -1170,16 +1171,16 @@ DTACK.AP = (!RST);
DTACK.C = (CLK_OSZI);
-E.T = (E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q
- # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q
- # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q);
+E.T = (E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_2_.Q
+ # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q
+ # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q);
E.C = (CLK_OSZI);
VMA.AP = (!RST);
-VMA.T = (!E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & AS_000.Q & inst_CLK_000_D.Q & cpu_est_2_.Q
- # !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !inst_CLK_000_D.Q & cpu_est_2_.Q);
+VMA.T = (!E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & AS_000.Q & inst_CLK_000_D0.Q & cpu_est_2_.Q
+ # !E.Q & VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !inst_CLK_000_D0.Q & cpu_est_2_.Q);
VMA.C = (CLK_OSZI);
@@ -1187,21 +1188,21 @@ RESET.D = (RST);
RESET.C = (CLK_OSZI);
-cpu_est_0_.D = (cpu_est_0_.Q & !inst_CLK_000_D.Q
- # cpu_est_0_.Q & inst_CLK_000_DD.Q
- # !cpu_est_0_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q);
+cpu_est_0_.D = (cpu_est_0_.Q & !inst_CLK_000_D0.Q
+ # cpu_est_0_.Q & inst_CLK_000_D1.Q
+ # !cpu_est_0_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
cpu_est_0_.C = (CLK_OSZI);
-cpu_est_1_.T = (E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q
- # !E.Q & cpu_est_0_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q
- # !E.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q
- # E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q);
+cpu_est_1_.T = (E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q
+ # !E.Q & cpu_est_0_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_2_.Q
+ # !E.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q
+ # E.Q & cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q);
cpu_est_1_.C = (CLK_OSZI);
inst_AS_030_000_SYNC.D = (AS_030
- # CPU_SPACE & CLK_030
+ # !nEXP_SPACE & CLK_030
# !CLK_030 & inst_AS_030_000_SYNC.Q
# FC_1_ & BGACK_000 & CLK_030 & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_);
@@ -1210,7 +1211,7 @@ inst_AS_030_000_SYNC.AP = (!RST);
inst_AS_030_000_SYNC.C = (CLK_OSZI);
!inst_DTACK_SYNC.D = (!AS_030 & !inst_DTACK_SYNC.Q
- # inst_VPA_D.Q & inst_CLK_000_D.Q & SM_AMIGA_3_.Q & !DTACK.PIN);
+ # inst_VPA_D.Q & inst_CLK_000_D0.Q & SM_AMIGA_3_.Q & !DTACK.PIN);
inst_DTACK_SYNC.AP = (!RST);
@@ -1221,28 +1222,28 @@ inst_VPA_D.D = (VPA);
inst_VPA_D.C = (CLK_OSZI);
!inst_VPA_SYNC.D = (!AS_030 & !inst_VPA_SYNC.Q
- # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q);
+ # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_D0.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q);
inst_VPA_SYNC.AP = (!RST);
inst_VPA_SYNC.C = (CLK_OSZI);
-inst_CLK_000_D.D = (CLK_000);
+inst_CLK_000_D0.D = (CLK_000);
-inst_CLK_000_D.C = (CLK_OSZI);
+inst_CLK_000_D0.C = (CLK_OSZI);
-inst_CLK_000_DD.D = (inst_CLK_000_D.Q);
+inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
-inst_CLK_000_DD.C = (CLK_OSZI);
+inst_CLK_000_D1.C = (CLK_OSZI);
inst_CLK_OUT_PRE.D = (!inst_CLK_OUT_PRE.Q & CLK_CNT_0_.Q
# inst_CLK_OUT_PRE.Q & !CLK_CNT_0_.Q);
inst_CLK_OUT_PRE.C = (CLK_OSZI);
-cpu_est_2_.D.X1 = (E.Q & cpu_est_0_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q
- # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & !cpu_est_2_.Q
- # !E.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & cpu_est_2_.Q);
+cpu_est_2_.D.X1 = (E.Q & cpu_est_0_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q
+ # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & !cpu_est_2_.Q
+ # !E.Q & cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & cpu_est_2_.Q);
cpu_est_2_.D.X2 = (cpu_est_2_.Q);
@@ -1254,14 +1255,14 @@ CLK_CNT_0_.C = (CLK_OSZI);
SM_AMIGA_6_.AR = (!RST);
-!SM_AMIGA_6_.D = (inst_CLK_000_D.Q & !SM_AMIGA_6_.Q
+!SM_AMIGA_6_.D = (inst_CLK_000_D0.Q & !SM_AMIGA_6_.Q
# !SM_AMIGA_6_.Q & !SM_AMIGA_7_.Q
- # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q);
+ # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q);
SM_AMIGA_6_.C = (CLK_OSZI);
-SM_AMIGA_7_.D = (inst_CLK_000_D.Q & SM_AMIGA_7_.Q
- # AS_000.Q & inst_CLK_000_D.Q & SM_AMIGA_0_.Q);
+SM_AMIGA_7_.D = (inst_CLK_000_D0.Q & SM_AMIGA_7_.Q
+ # AS_000.Q & inst_CLK_000_D0.Q & SM_AMIGA_0_.Q);
SM_AMIGA_7_.AP = (!RST);
@@ -1269,47 +1270,47 @@ SM_AMIGA_7_.C = (CLK_OSZI);
SM_AMIGA_1_.AR = (!RST);
-SM_AMIGA_1_.D = (inst_CLK_000_D.Q & SM_AMIGA_1_.Q
- # inst_CLK_000_D.Q & SM_AMIGA_2_.Q
- # !inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q);
+SM_AMIGA_1_.D = (inst_CLK_000_D1.Q & SM_AMIGA_1_.Q
+ # !inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q
+ # inst_CLK_000_D0.Q & SM_AMIGA_2_.Q);
SM_AMIGA_1_.C = (CLK_OSZI);
SM_AMIGA_4_.AR = (!RST);
-SM_AMIGA_4_.D = (!inst_CLK_000_D.Q & SM_AMIGA_4_.Q
- # !inst_CLK_000_D.Q & SM_AMIGA_5_.Q);
+SM_AMIGA_4_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_4_.Q
+ # !inst_CLK_000_D0.Q & SM_AMIGA_5_.Q);
SM_AMIGA_4_.C = (CLK_OSZI);
SM_AMIGA_3_.AR = (!RST);
-SM_AMIGA_3_.D = (inst_CLK_000_D.Q & SM_AMIGA_4_.Q
- # inst_CLK_000_D.Q & SM_AMIGA_3_.Q
+SM_AMIGA_3_.D = (inst_CLK_000_D0.Q & SM_AMIGA_4_.Q
+ # inst_CLK_000_D0.Q & SM_AMIGA_3_.Q
# inst_DTACK_SYNC.Q & inst_VPA_SYNC.Q & SM_AMIGA_3_.Q);
SM_AMIGA_3_.C = (CLK_OSZI);
SM_AMIGA_5_.AR = (!RST);
-SM_AMIGA_5_.D = (inst_CLK_000_D.Q & SM_AMIGA_5_.Q
- # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D.Q & !inst_CLK_000_DD.Q & SM_AMIGA_6_.Q);
+SM_AMIGA_5_.D = (inst_CLK_000_D0.Q & SM_AMIGA_5_.Q
+ # !inst_AS_030_000_SYNC.Q & inst_CLK_000_D0.Q & !inst_CLK_000_D1.Q & SM_AMIGA_6_.Q);
SM_AMIGA_5_.C = (CLK_OSZI);
SM_AMIGA_2_.AR = (!RST);
-SM_AMIGA_2_.D = (!inst_CLK_000_D.Q & SM_AMIGA_2_.Q
- # !inst_DTACK_SYNC.Q & !inst_CLK_000_D.Q & SM_AMIGA_3_.Q
- # !inst_VPA_SYNC.Q & !inst_CLK_000_D.Q & SM_AMIGA_3_.Q);
+SM_AMIGA_2_.D = (!inst_CLK_000_D0.Q & SM_AMIGA_2_.Q
+ # !inst_DTACK_SYNC.Q & !inst_CLK_000_D0.Q & SM_AMIGA_3_.Q
+ # !inst_VPA_SYNC.Q & !inst_CLK_000_D0.Q & SM_AMIGA_3_.Q);
SM_AMIGA_2_.C = (CLK_OSZI);
SM_AMIGA_0_.AR = (!RST);
SM_AMIGA_0_.D = (!AS_000.Q & SM_AMIGA_0_.Q
- # !inst_CLK_000_D.Q & SM_AMIGA_0_.Q
- # !inst_CLK_000_D.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q);
+ # !inst_CLK_000_D0.Q & SM_AMIGA_0_.Q
+ # !inst_CLK_000_D1.Q & inst_CLK_OUT_PRE.Q & SM_AMIGA_1_.Q);
SM_AMIGA_0_.C = (CLK_OSZI);
diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal
index 773fc3e..f248157 100644
--- a/Logic/68030_tk.tal
+++ b/Logic/68030_tk.tal
@@ -32,6 +32,7 @@ TCR, Clocked Output-to-Register Time,
TSU TCO TPD TCR
#passes #passes #passes #passes
SIGNAL NAME min max min max min max min max
+AMIGA_BUS_ENABLE .. .. .. .. 1 1 .. ..
AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. ..
CIIN .. .. .. .. 1 1 .. ..
IPL_030_2_ 1 1 0 0 .. .. 1 1
@@ -44,14 +45,14 @@ AMIGA_BUS_DATA_DIR .. .. .. .. 1 1 .. ..
RN_UDS_000 1 1 0 0 .. .. 1 1
LDS_000 1 1 0 0 .. .. 1 1
RN_LDS_000 1 1 0 0 .. .. 1 1
- BG_000 1 1 0 0 .. .. 1 1
- RN_BG_000 1 1 0 0 .. .. 1 1
- BGACK_030 1 1 0 0 .. .. 1 1
- RN_BGACK_030 1 1 0 0 .. .. 1 1
IPL_030_1_ 1 1 0 0 .. .. 1 1
RN_IPL_030_1_ 1 1 0 0 .. .. 1 1
IPL_030_0_ 1 1 0 0 .. .. 1 1
RN_IPL_030_0_ 1 1 0 0 .. .. 1 1
+ BG_000 1 1 0 0 .. .. 1 1
+ RN_BG_000 1 1 0 0 .. .. 1 1
+ BGACK_030 1 1 0 0 .. .. 1 1
+ RN_BGACK_030 1 1 0 0 .. .. 1 1
FPU_CS 1 1 0 0 .. .. 1 1
RN_FPU_CS 1 1 0 0 .. .. 1 1
DTACK 1 1 0 0 .. .. .. ..
@@ -66,8 +67,8 @@ inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 1
inst_DTACK_SYNC 1 1 .. .. .. .. 1 1
inst_VPA_D 1 1 .. .. .. .. 1 1
inst_VPA_SYNC 1 1 .. .. .. .. 1 1
- inst_CLK_000_D 1 1 .. .. .. .. 1 1
- inst_CLK_000_DD .. .. .. .. .. .. 1 1
+ inst_CLK_000_D0 1 1 .. .. .. .. 1 1
+ inst_CLK_000_D1 .. .. .. .. .. .. 1 1
inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1
cpu_est_2_ .. .. .. .. .. .. 1 1
CLK_CNT_0_ .. .. .. .. .. .. 1 1
diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2
index d1cc156..b021d93 100644
--- a/Logic/68030_tk.tt2
+++ b/Logic/68030_tk.tt2
@@ -1,168 +1,169 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
-#$ DATE Thu May 15 23:02:46 2014
+#$ DATE Fri May 16 17:07:08 2014
#$ MODULE 68030_tk
-#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BERR BG_030 A_0_ BGACK_000 CLK_030 IPL_1_ CLK_000 IPL_0_ CLK_OSZI DSACK_0_ CLK_DIV_OUT FC_0_ AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ CLK_EXP FPU_CS DTACK E VMA RESET
-#$ NODES 19 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_
+#$ PINS 59 A_17_ A_16_ SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 A_0_ nEXP_SPACE BERR BG_030 IPL_1_ IPL_0_ DSACK_0_ BGACK_000 FC_0_ CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 IPL_030_1_ IPL_030_0_ BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET
+#$ NODES 19 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_OUT_PRE cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_
.type fr
.i 68
.o 110
-.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ IPL_030_1_.Q IPL_030_2_.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q BG_000.Q IPL_030_0_.Q DSACK_1_.PIN DTACK.PIN
-.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR DSACK_1_.C DSACK_1_.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP AS_000.C AS_000.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000.C BG_000.AP DTACK.C DTACK.AP UDS_000.C UDS_000.AP CLK_CNT_0_.C inst_VPA_D.C inst_CLK_000_D.C RESET.C inst_CLK_000_DD.C CLK_EXP.C DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D IPL_030_1_.D IPL_030_2_.D BGACK_030.D FPU_CS.D E.T VMA.T cpu_est_0_.D cpu_est_1_.T AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D.D inst_CLK_000_DD.D inst_CLK_OUT_PRE.D cpu_est_2_.D RESET.D CLK_CNT_0_.D SM_AMIGA_6_.D SM_AMIGA_7_.D UDS_000.D LDS_000.D SM_AMIGA_1_.D DSACK_1_.D DTACK.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D BG_000.D CLK_EXP.D IPL_030_0_.D
-.p 273
+.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_OUT_PRE.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q DSACK_1_.PIN DTACK.PIN
+.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR DSACK_1_.C DSACK_1_.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP AS_000.C AS_000.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000.C BG_000.AP DTACK.C DTACK.AP UDS_000.C UDS_000.AP CLK_CNT_0_.C inst_VPA_D.C inst_CLK_000_D0.C RESET.C inst_CLK_000_D1.C CLK_EXP.C DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D FPU_CS.D E.T VMA.T cpu_est_0_.D cpu_est_1_.T AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D0.D inst_CLK_000_D1.D inst_CLK_OUT_PRE.D RESET.D cpu_est_2_.D CLK_CNT_0_.D SM_AMIGA_6_.D SM_AMIGA_7_.D UDS_000.D LDS_000.D DSACK_1_.D SM_AMIGA_1_.D DTACK.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D
+.p 277
-------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
-----11-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~
-------0------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
----0-----1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------1--1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
---------01---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----0----0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
-------1--0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
-----------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~
+----1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
+----11-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~
+------1------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------0------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~
+---0-----1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------0--1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------01---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----0----0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~
+------1--0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~
+----------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~
-----------1-------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~111111~1~1~1~1~1~1~1~1~111111~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~
--------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~
+------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
+-------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
-------------0------------------------------------------------------ ~~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------0----------------------------------------------------- ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-0--------------0000000--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------1111----------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------1-----------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------1------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------1-------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------1--------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1----11-----------------0010---1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
----------1------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------1----------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------0----------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----1----------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-----1-----------------------------------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-----1------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-----1-------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
-----1---------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
----------0----------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
-----1---------1-----------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~
--------------------------------------------11----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
-----1-----------------------------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-----1-----------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
+---------1-----------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------1------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------1-------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------1--------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---1----11-----------------0010---1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------1------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------1--------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------0-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------0--------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----1--------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
+----1---------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
+----1----------------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
+----1-----------------------------------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~
+----1-------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------0--------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
+----1---------1---------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~
+-----------------------------------------11------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----1---------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
+----1---------------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------------10----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------0-------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
+--------------------------------------1------1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------1-----1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------------1----1---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
+--------------------------------------------11---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
+----1-----------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~1~~~~~~~~11~~~~~~~~~~~~~
+---------------------------------------1------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------1----0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------------1--0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------------10--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------0-------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------1------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1-----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------1----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------------11-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
-----1-------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
-----1-------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~1~~~~~~~~11~~~~~~~~~~~
------------------------------------1------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------1-----------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------1----0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------------1--0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------------10------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-----1--------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
-----1---------1----------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~
------------------------------------1-------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------1------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------1-----1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
---1---------------------------------------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------1---------------------------------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------1---------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------1--------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
----------------------------------------1-1------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
------------------------------------------0------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------00-----10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
----------------------------------------1-00-----10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
-----1---------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
-------------------------------------------1--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
----------------------------------------00011----1--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------0--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
----------------------------------------0110---0-0--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------------1-1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
----------------------------------------0-1------10-1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------1-11-----10-1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----1----------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
------------------------------------------------1---0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
----------------------------------------1-11-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------0-11-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------0--0-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------0-00-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------------------0-1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
-----------------------------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
---------------------------------------------------1-0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
---------------------------------------------1--------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
-------------------------------------------------0----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
--------------------------------------------------1---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
---------------------------------------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
------0--------1----------------1------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
-0----0--------11---------------0------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
-----1------------------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
-----1---------1--------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~
--------------------------------------------1---------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------1-----1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
-------------------------------------------------0-----1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
----------0-------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
------1-------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
---------------1-----------------------------1----------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
+----1------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~1~~~~~~~~~~~~
+----1---------1--------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~
+---------------------------------------1-------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------1-----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--1-------------------------------------------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
+--------1-------------------------------------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------------------------------1-------------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
+---------------------------------1------------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
+-------------------------------------1-1------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
+---------------------------------------0------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------00-----10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
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@@ -175,111 +176,114 @@
------------------------0------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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+----------------------------------------------0------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
+-----------------------------------------------1-----------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
+-----------------------------------------0------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
+--------------------------------------------1-1-----------1--------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
.end
diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3
index 0467835..a9b3f77 100644
--- a/Logic/68030_tk.tt3
+++ b/Logic/68030_tk.tt3
@@ -1,168 +1,169 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
-#$ DATE Thu May 15 23:02:46 2014
+#$ DATE Fri May 16 17:07:08 2014
#$ MODULE 68030_tk
-#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BERR BG_030 A_0_ BGACK_000 CLK_030 IPL_1_ CLK_000 IPL_0_ CLK_OSZI DSACK_0_ CLK_DIV_OUT FC_0_ AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000 BGACK_030 IPL_030_1_ IPL_030_0_ CLK_EXP FPU_CS DTACK E VMA RESET
-#$ NODES 19 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_
+#$ PINS 59 A_17_ A_16_ SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 A_0_ nEXP_SPACE BERR BG_030 IPL_1_ IPL_0_ DSACK_0_ BGACK_000 FC_0_ CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 IPL_030_1_ IPL_030_0_ BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET
+#$ NODES 19 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_OUT_PRE cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ SM_AMIGA_1_ SM_AMIGA_4_ SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_
.type fr
.i 68
.o 110
-.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ IPL_030_1_.Q IPL_030_2_.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q BG_000.Q IPL_030_0_.Q DSACK_1_.PIN DTACK.PIN
-.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR DSACK_1_.C DSACK_1_.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP AS_000.C AS_000.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000.C BG_000.AP DTACK.C DTACK.AP UDS_000.C UDS_000.AP CLK_CNT_0_.C inst_VPA_D.C inst_CLK_000_D.C RESET.C inst_CLK_000_DD.C CLK_EXP.C DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D IPL_030_1_.D IPL_030_2_.D BGACK_030.D FPU_CS.D E.T VMA.T cpu_est_0_.D cpu_est_1_.T AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D.D inst_CLK_000_DD.D inst_CLK_OUT_PRE.D cpu_est_2_.D RESET.D CLK_CNT_0_.D SM_AMIGA_6_.D SM_AMIGA_7_.D UDS_000.D LDS_000.D SM_AMIGA_1_.D DSACK_1_.D DTACK.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D BG_000.D CLK_EXP.D IPL_030_0_.D
-.p 273
+.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_OUT_PRE.Q cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q DSACK_1_.PIN DTACK.PIN
+.ob BERR AVEC AVEC_EXP AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.C SM_AMIGA_0_.AR IPL_030_0_.C IPL_030_0_.AP IPL_030_1_.C IPL_030_1_.AP IPL_030_2_.C IPL_030_2_.AP SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_6_.C SM_AMIGA_6_.AR SM_AMIGA_5_.C SM_AMIGA_5_.AR SM_AMIGA_4_.C SM_AMIGA_4_.AR DSACK_1_.C DSACK_1_.AP VMA.C VMA.AP BGACK_030.C BGACK_030.AP inst_CLK_OUT_PRE.C cpu_est_0_.C cpu_est_1_.C cpu_est_2_.C E.C LDS_000.C LDS_000.AP inst_DTACK_SYNC.C inst_DTACK_SYNC.AP FPU_CS.C FPU_CS.AP inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP AS_000.C AS_000.AP inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000.C BG_000.AP DTACK.C DTACK.AP UDS_000.C UDS_000.AP CLK_CNT_0_.C inst_VPA_D.C inst_CLK_000_D0.C RESET.C inst_CLK_000_D1.C CLK_EXP.C DSACK_0_ DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE CLK_DIV_OUT.C CLK_DIV_OUT.D BGACK_030.D FPU_CS.D E.T VMA.T cpu_est_0_.D cpu_est_1_.T AS_000.D inst_AS_030_000_SYNC.D inst_DTACK_SYNC.D inst_VPA_D.D inst_VPA_SYNC.D inst_CLK_000_D0.D inst_CLK_000_D1.D inst_CLK_OUT_PRE.D RESET.D cpu_est_2_.D CLK_CNT_0_.D SM_AMIGA_6_.D SM_AMIGA_7_.D UDS_000.D LDS_000.D DSACK_1_.D SM_AMIGA_1_.D DTACK.D SM_AMIGA_4_.D SM_AMIGA_3_.D SM_AMIGA_5_.D SM_AMIGA_2_.D SM_AMIGA_0_.D BG_000.D CLK_EXP.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D
+.p 277
-------------------------------------------------------------------- ~1~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
-----11-------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~
-------0------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------1------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
----0-----1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------1--1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
---------01---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----0----0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
-------1--0---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
-----------1--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~
+----1--------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
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+---0-----1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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-----------1-------------------------------------------------------- ~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~111111~1~1~1~1~1~1~1~1~111111~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~
--------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~
+------------1------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
+-------------1------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
-------------0------------------------------------------------------ ~~~~~~~~1~1~1~1~1~1~1~1~1~1~1~1~1~1~~~~~~1~1~1~1~1~1~1~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------0----------------------------------------------------- ~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-0--------------0000000--------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------1111----------------------------------------- ~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------1-----------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------1------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------1-------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------1--------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----1----11-----------------0010---1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
----------1------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~111~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------1----------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------0----------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----1----------------------------------0---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-----1-----------------------------------1--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-----1------------------------------------1-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-----1-------------------------------------1------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------1------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
-----1---------------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
----------0----------------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~
-----1---------1-----------------------------1----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~
--------------------------------------------11----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
-----1-----------------------------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-----1-----------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
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---------------------------------------------10--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------0-------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------1------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1-----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------1----1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------------11-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~
-----1-------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
-----1-------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~1~~~~~~~~11~~~~~~~~~~~
------------------------------------1------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------1-----------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------1----0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------------1--0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------------10------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-----1--------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
-----1---------1----------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~
------------------------------------1-------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------1------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------1-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------1-----1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
---1---------------------------------------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------1---------------------------------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------1---------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------1--------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
----------------------------------------1-1------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
------------------------------------------0------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------00-----10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
----------------------------------------1-00-----10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
-----1---------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
-------------------------------------------1--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
----------------------------------------00011----1--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------0--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
----------------------------------------0110---0-0--1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------------1-1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~
----------------------------------------0-1------10-1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------1-11-----10-1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----1----------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
------------------------------------------------1---0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
----------------------------------------1-11-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------0-11-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------0--0-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------0-00-----10-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------------------0-1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
-----------------------------------------------------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
---------------------------------------------------1-0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~
---------------------------------------------1--------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
-------------------------------------------------0----1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
--------------------------------------------------1---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
---------------------------------------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
------0--------1----------------1------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
-0----0--------11---------------0------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
-----1------------------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
-----1---------1--------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~
--------------------------------------------1---------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------1-----1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
-------------------------------------------------0-----1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
----------0-------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
------1-------------------------------------------------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
---------------1-----------------------------1----------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
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+----1---------1--------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~
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+----1--------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------------1---0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
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+-----0--------1----------------1----------0---10---1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
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+----1---------1------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~
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+-----1------------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
+--------------1---------------------------1-----------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
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------------------------------------------------0------1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
---------------1----------------------------------1-----1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
---------------1--------------------------------------0-1------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
------1--------------------------------------------------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
---------------1-----------------------------1-----------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
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---------------1----------------------------------1------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
---------------1--------------------------------------0--1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
-------------------------------------------------1--------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~
-------------------------------------------------0-1------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
-----1----------------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
-------------------------------------------------1---------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
---------------------------------------------------0-------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
----------------------------------------------------------01--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
-------------------------------------------------1----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
------0--------0----------------1----------------1----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
-0----0--------01---------------0----------------1----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
-------------------------------------------------0----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~
-----1---------0--------------------------------------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~
---------------0----------------------------------------1---0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
---------------0-----------------------------------------1--0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
----------------------------------------------1-1------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
-------------------------------------------------1-----------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
----------------------------------------------0--0-----------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~
------------------------------------------------00-----------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~
-----1-------------------------------------------------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~
----------------------------------------------1--------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------------1------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------1------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
-------------------------------------------------0------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~
-------------------------------------------------1-------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~
-------------------------------------------------0-------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~
---------------------------------------------------0------1----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~
--------------------------------------------0-------------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
--------------------------------------------1----1--------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
-------------------------------------------------0--------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~
----------1------------------------------------------------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
-------------------------------------------------0----------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
--------------------------------------------------1---------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
-------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
-----1--------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------------1---------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------------------------------- 0~00~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----1---------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
+-------------------------------------------------------10----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~
+----------------------------------------------1----------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
+-----0--------0----------------1--------------1----------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
+0----0--------01---------------0--------------1----------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
+----------------------------------------------0----------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
+----1---------0------------------------------------------0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~
+--------------0--------------------------------------1---0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~
+--------------0---------------------------------------1--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~
+-------------------------------------------1-1------------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
+----------------------------------------------1-----------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~
+-------------------------------------------0--0-----------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
+---------------------------------------------00-----------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
+----1-----------------------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------------1--------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------------1------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------------------1------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~
+----------------------------------------------0------------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~
+----------------------------------------------1-------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~
+----------------------------------------------0-------------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~
+-----------------------------------------0-------------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
+-----------------------------------------1----1--------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~
+----------------------------------------------0--------------1------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~
+---------1----------------------------------------------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~
+----------------------------------------------0----------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
+-----------------------------------------------1---------------1---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~
+----------------------------------------------0-----------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
+-----------------------------------------------1----------------1--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~
+----------------------------------------------0------------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
+-----------------------------------------------1-----------------1-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1
+------------------------------------------------------------------1- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~
+----1--------------------------------------------------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------------1-----------------------1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------------------------------------- 0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-1------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------1------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------0----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----00-0--1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
-----0-0-01---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
-----------0--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~
+------1------------------------------------------------------------- ~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------0------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------0----------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---00-1--1---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
+----0-1-01---------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------0--------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
-----------0-------------------------------------------------------- ~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~000000~0~0~0~0~0~0~0~0~000000~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------0------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~
+------------0------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
-------------1------------------------------------------------------ ~~~~~~~~0~0~0~0~0~0~0~0~0~0~0~0~0~0~~~~~~0~0~0~0~0~0~0~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------0------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
+-------------0------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~
--------------1----------------------------------------------------- ~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------1--------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------1-------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
@@ -175,111 +176,114 @@
------------------------0------------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------0------------------------------------------ ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------0----------------------------------------- ~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----0-0--1-----------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
-----0-0--1------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
-----0-0--1-------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
-----0-0--1--------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
----10---11-----------------0010---1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----0-0--1------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------0------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------------1----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----0----0----------------------------0----------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------1---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-----------------------------------------01-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------01------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------1-10------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------00------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----0-1--1-----------------1---------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
+----0-1--1------------------1--------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
+----0-1--1-------------------0-------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
+----0-1--1--------------------1------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
+---10---11-----------------0010---1--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----0-1--1------------------------0--------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------1-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------0-------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~000~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------------1------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----0----0--------------------------0------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------1------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------------------------------------01---------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------01--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------1-10--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------00--------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----0------------------------------------0-------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----0----0--------------------------------0------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
----0--------------------------------------0------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
-----0----0----------------------------------0----------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~
----0----------------------------------------0---------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
-----0------------------------------------------0-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~
-----------------------------------------1-------1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------------1----1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
--------------------------------------------0----1------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~0~~~~~0~~~~~~~0~~~~~
------------------------------------0------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------0-----------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--------------------------------------0----------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------0------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------1-----0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------------0--0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
-----------------------------------------------1-0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------------00------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
--------------------------------------------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------0-------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------0------------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------------------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~
+--------------------------------------1-------1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------0----1--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------------------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~0~~~~~0~~~~~~~0~~~~~~~
+-----------------------------------0----------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------0------0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------------1-----0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------------0--0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
+--------------------------------------------1-0--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------------00--------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
+-----------------------------------------------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------0-----------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------0-------1-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-----------------------------------------1----11-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
+--0-------------------------------------------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
+--------------------------------0-------------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
+---------------------------------0------------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
+---------------------------------------1------10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------0-10-----10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
+------------------------------------------0---10-------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
+----------------------------------------------001------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
+------------------------------------------------0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
+-----------------------------------------1----1-0------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
-------------------------------------0-----------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------0-------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~
---0---------------------------------------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
---------------------------------0---------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------0--------------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
------------------------------------------1------10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------0-10-----10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
---------------------------------------------0---10------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
-------------------------------------------------0-1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
---------------------------------------------------0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
----------------------------------------0-----------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
------------------------------------------0---------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------0-0---------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------1--1--------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------------------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------1-----------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
----------------------------------------0--1--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~0~~~~~~~~~~~~~~~~~
------------------------------------------01--------0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
-------------------------------------------------0--0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
--------------------------------------------------1-0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
-----------------------------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
---------------------------------------------------1-1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
---------------------------------------------------0-0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
-----1-00-0-------------------------------------------1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
---------------------------------------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
-1----0--------1-----------------------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
------0--------10----------------------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
------0--------1----------------1------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
------0--------1----------------0------------0---10---1-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
-------------------------------------------------1----0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
-----1-00-0--------------------------------------------1------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
--------------------------------------------0----------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
------------------------------------------------------00------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
-----01-------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
-----0---------1-----------------------------1----------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
-----0-------------------------------------------0------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
-----0---------1----------------------------------1-----0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
-----0---------1--------------------------------------0-0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
-----01--------------------------------------------------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
-----0---------1-----------------------------1-----------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
-----0-------------------------------------------0-------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
-----0---------1----------------------------------1------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
-----0---------1--------------------------------------0--0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
-------------------------------------------------0-1------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
-----0-----------------------------------------------------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
-1----0--------0---------------------------------1----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
------0--------00--------------------------------1----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
------0--------0----------------1----------------1----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
------0--------0----------------0----------------1----------1-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
-----0---------0----------------------------------------0---0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
-----0---------0-----------------------------------------0--0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
----------------------------------------1000---0-1--1--------1------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------0-----------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
------------------------------------------------------------00------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
---------------------------------------------1----------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
--------------------------------------------------1-----------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
------------------------------------------------------0-------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
------------------------------------------------------------0-0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~
-------------------------------------------------0-------------1----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
----------------------------------------------1-1--------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
----------------------------------------------------------0----0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
-------------------------------------------------------------0-0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
-------------------------------------------------1--------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
---------------------------------------------------0------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
-------------------------------------------------------0--------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
----------------------------------------------------------0-----0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~
--------0-1------------------------------------------------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
-------------------------------------------------0----------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
--------------------------------------------------1---------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
--------------------------------------------0----------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
-----------------------------------------------1-1-----------1------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
+---------------------------------------0---------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------0-0---------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------1--1--------1------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------------------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------1-----------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------0--1--------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~0~~~~~~~~~~~~~~~~~~
+---------------------------------------01--------0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
+----------------------------------------------0--0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
+-----------------------------------------------1-0------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~
+--------------------------------------------------1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~
+------------------------------------------------1-1----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~
+------------------------------------------------0-0----------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~
+----1-00-0-----------------------------------------1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
+------------------------------------------0---10---1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~~~
+1----0--------1---------------------------0---10---1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
+-----0--------10--------------------------0---10---1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
+-----0--------1----------------1----------0---10---1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
+-----0--------1----------------0----------0---10---1---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
+----------------------------------------------1----0---------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
+----1-00-0------------------------------------------1--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
+-----------------------------------------0----------0--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
+---------------------------------------------------00--------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~
+----01-----------------------------------------------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
+----0---------1---------------------------1----------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
+----0-----------------------------------------0------0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
+----0---------1--------------------------------1-----0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
+----0---------1------------------------------------0-0-------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
+----01------------------------------------------------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
+----0---------1---------------------------1-----------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
+----0-----------------------------------------0-------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
+----0---------1--------------------------------1------0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
+----0---------1------------------------------------0--0------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
+----0--------------------------------------------------0------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
+-----------------------------------------------01-------1----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~
+-----------------------------------------1----1---------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
+----------------------------------------------0---------0----------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
+1----0--------0-------------------------------1----------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
+-----0--------00------------------------------1----------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
+-----0--------0----------------1--------------1----------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
+-----0--------0----------------0--------------1----------1---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
+----0---------0--------------------------------------0---0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~
+----0---------0---------------------------------------0--0---------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~
+-------------------------------------1000---0-1--1--------1--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~
+----------------------------------------------0-----------0--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
+---------------------------------------------------------00--------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~
+------------------------------------------1----------------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~
+-----------------------------------------------1-----------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~
+---------------------------------------------------0-------0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~
+---------------------------------------------------------0-0-------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~
+-------------------------------------------1-1--------------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
+-----------------------------------------------01-----------0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
+--------------------------------------------------------0---0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~
+----------------------------------------------------------0-0------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~
+-----------------------------------------------1-------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
+------------------------------------------------0------------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
+----------------------------------------------------0--------0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~
+--------------------------------------------------------0----0------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~
+-------0-1----------------------------------------------------0----- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~
+----------------------------------------------0----------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
+-----------------------------------------------1---------------0---- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~
+----------------------------------------------0-----------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
+-----------------------------------------------1----------------0--- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~
+----------------------------------------------0------------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
+-----------------------------------------------1-----------------0-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0
+-----------------------------------------0------------------------0- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~
+--------------------------------------------1-1-----------1--------0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~0~~~~~~~~~~~~~~~~~~~~~~~~~
.end
diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4
index 06d9777..da90562 100644
--- a/Logic/68030_tk.tt4
+++ b/Logic/68030_tk.tt4
@@ -1,41 +1,41 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
-#$ DATE Thu May 15 23:02:46 2014
+#$ DATE Fri May 16 17:07:08 2014
#$ MODULE BUS68030
-#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ FC_1_
- AS_030 DS_030 CPU_SPACE BERR BG_030 A_0_ BGACK_000 CLK_030 IPL_1_ CLK_000 IPL_0_
- CLK_OSZI DSACK_0_ CLK_DIV_OUT FC_0_ AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE
- AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_
- A_26_ A_25_ A_24_ A_23_ A_22_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000
- BGACK_030 IPL_030_1_ IPL_030_0_ CLK_EXP FPU_CS DTACK E VMA RESET
+#$ PINS 59 A_17_ A_16_ SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 A_0_ nEXP_SPACE
+ BERR BG_030 IPL_1_ IPL_0_ DSACK_0_ BGACK_000 FC_0_ CLK_030 CLK_000 CLK_OSZI
+ CLK_DIV_OUT AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR
+ AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_
+ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000
+ IPL_030_1_ IPL_030_0_ BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET
#$ NODES 19 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC
- inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE
+ inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_OUT_PRE
cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ SM_AMIGA_1_ SM_AMIGA_4_
SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_
.type f
.i 68
.o 111
-.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030
- CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_
- A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_
- IPL_030_1_.Q IPL_030_2_.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q
- cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q
- inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q
- cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q
- SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q
- SM_AMIGA_0_.Q BG_000.Q IPL_030_0_.Q DSACK_1_.PIN DTACK.PIN
+.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000
+ CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_
+ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_
+ BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q
+ inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q
+ inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_OUT_PRE.Q cpu_est_2_.Q CLK_CNT_0_.Q
+ SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_1_.Q
+ SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q BG_000.Q
+ IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q DSACK_1_.PIN DTACK.PIN
.ob BERR BERR.OE DSACK_0_ DSACK_0_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AVEC AVEC_EXP
AVEC_EXP.OE AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN
CIIN.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D% DSACK_1_.C
DSACK_1_.AP DSACK_1_.OE AS_000.D% AS_000.C AS_000.AP AS_000.OE UDS_000.D%
UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D% LDS_000.C LDS_000.AP LDS_000.OE
- BG_000.D% BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP IPL_030_1_.D
- IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP CLK_EXP.D
+ IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP
+ BG_000.D% BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D
CLK_EXP.C FPU_CS.D% FPU_CS.C FPU_CS.AP DTACK.D% DTACK.C DTACK.AP DTACK.OE E.T
E.C VMA.T VMA.C VMA.AP RESET.D RESET.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.T
cpu_est_1_.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C
inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D% inst_DTACK_SYNC.C inst_DTACK_SYNC.AP
inst_VPA_D.D inst_VPA_D.C inst_VPA_SYNC.D% inst_VPA_SYNC.C inst_VPA_SYNC.AP
- inst_CLK_000_D.D inst_CLK_000_D.C inst_CLK_000_DD.D inst_CLK_000_DD.C
+ inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D1.D inst_CLK_000_D1.C
inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C cpu_est_2_.D.X1 cpu_est_2_.D.X2
cpu_est_2_.C CLK_CNT_0_.D CLK_CNT_0_.C SM_AMIGA_6_.D% SM_AMIGA_6_.C
SM_AMIGA_6_.AR SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_1_.D
@@ -44,107 +44,108 @@
SM_AMIGA_5_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_0_.D
SM_AMIGA_0_.C SM_AMIGA_0_.AR
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.end
diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte
index 4ec737f..347e4cf 100644
--- a/Logic/68030_tk.tte
+++ b/Logic/68030_tk.tte
@@ -1,41 +1,41 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
-#$ DATE Thu May 15 23:02:46 2014
+#$ DATE Fri May 16 17:07:08 2014
#$ MODULE BUS68030
-#$ PINS 59 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_2_ FC_1_
- AS_030 DS_030 CPU_SPACE BERR BG_030 A_0_ BGACK_000 CLK_030 IPL_1_ CLK_000 IPL_0_
- CLK_OSZI DSACK_0_ CLK_DIV_OUT FC_0_ AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE
- AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_
- A_26_ A_25_ A_24_ A_23_ A_22_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000 BG_000
- BGACK_030 IPL_030_1_ IPL_030_0_ CLK_EXP FPU_CS DTACK E VMA RESET
+#$ PINS 59 A_17_ A_16_ SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 A_0_ nEXP_SPACE
+ BERR BG_030 IPL_1_ IPL_0_ DSACK_0_ BGACK_000 FC_0_ CLK_030 CLK_000 CLK_OSZI
+ CLK_DIV_OUT AVEC AVEC_EXP VPA RST RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR
+ AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_
+ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ IPL_030_2_ DSACK_1_ AS_000 UDS_000 LDS_000
+ IPL_030_1_ IPL_030_0_ BG_000 BGACK_030 CLK_EXP FPU_CS DTACK E VMA RESET
#$ NODES 19 cpu_est_0_ cpu_est_1_ inst_AS_030_000_SYNC inst_DTACK_SYNC
- inst_VPA_D inst_VPA_SYNC inst_CLK_000_D inst_CLK_000_DD inst_CLK_OUT_PRE
+ inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 inst_CLK_000_D1 inst_CLK_OUT_PRE
cpu_est_2_ CLK_CNT_0_ SM_AMIGA_6_ SM_AMIGA_7_ SM_AMIGA_1_ SM_AMIGA_4_
SM_AMIGA_3_ SM_AMIGA_5_ SM_AMIGA_2_ SM_AMIGA_0_
.type f
.i 68
.o 111
-.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 CPU_SPACE BG_030 BGACK_000 CLK_030
- CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_
- A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_
- IPL_030_1_.Q IPL_030_2_.Q BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q
- cpu_est_1_.Q AS_000.Q inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q
- inst_VPA_SYNC.Q inst_CLK_000_D.Q inst_CLK_000_DD.Q inst_CLK_OUT_PRE.Q
- cpu_est_2_.Q CLK_CNT_0_.Q SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q
- SM_AMIGA_1_.Q DSACK_1_.Q SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q
- SM_AMIGA_0_.Q BG_000.Q IPL_030_0_.Q DSACK_1_.PIN DTACK.PIN
+.ilb SIZE_1_ A_31_ IPL_2_ FC_1_ AS_030 DS_030 nEXP_SPACE BG_030 BGACK_000
+ CLK_030 CLK_000 CLK_OSZI VPA RST RW SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_
+ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_0_ IPL_1_ IPL_0_ FC_0_
+ BGACK_030.Q FPU_CS.Q E.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q AS_000.Q
+ inst_AS_030_000_SYNC.Q inst_DTACK_SYNC.Q inst_VPA_D.Q inst_VPA_SYNC.Q
+ inst_CLK_000_D0.Q inst_CLK_000_D1.Q inst_CLK_OUT_PRE.Q cpu_est_2_.Q CLK_CNT_0_.Q
+ SM_AMIGA_6_.Q SM_AMIGA_7_.Q UDS_000.Q LDS_000.Q DSACK_1_.Q SM_AMIGA_1_.Q
+ SM_AMIGA_4_.Q SM_AMIGA_3_.Q SM_AMIGA_5_.Q SM_AMIGA_2_.Q SM_AMIGA_0_.Q BG_000.Q
+ IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q DSACK_1_.PIN DTACK.PIN
.ob BERR BERR.OE DSACK_0_ DSACK_0_.OE CLK_DIV_OUT.D CLK_DIV_OUT.C AVEC AVEC_EXP
AVEC_EXP.OE AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN
CIIN.OE IPL_030_2_.D IPL_030_2_.C IPL_030_2_.AP DSACK_1_.D- DSACK_1_.C
DSACK_1_.AP DSACK_1_.OE AS_000.D- AS_000.C AS_000.AP AS_000.OE UDS_000.D-
UDS_000.C UDS_000.AP UDS_000.OE LDS_000.D- LDS_000.C LDS_000.AP LDS_000.OE
- BG_000.D- BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP IPL_030_1_.D
- IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP CLK_EXP.D
+ IPL_030_1_.D IPL_030_1_.C IPL_030_1_.AP IPL_030_0_.D IPL_030_0_.C IPL_030_0_.AP
+ BG_000.D- BG_000.C BG_000.AP BGACK_030.D BGACK_030.C BGACK_030.AP CLK_EXP.D
CLK_EXP.C FPU_CS.D- FPU_CS.C FPU_CS.AP DTACK.D- DTACK.C DTACK.AP DTACK.OE E.T
E.C VMA.T VMA.C VMA.AP RESET.D RESET.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.T
cpu_est_1_.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C
inst_AS_030_000_SYNC.AP inst_DTACK_SYNC.D- inst_DTACK_SYNC.C inst_DTACK_SYNC.AP
inst_VPA_D.D inst_VPA_D.C inst_VPA_SYNC.D- inst_VPA_SYNC.C inst_VPA_SYNC.AP
- inst_CLK_000_D.D inst_CLK_000_D.C inst_CLK_000_DD.D inst_CLK_000_DD.C
+ inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_D1.D inst_CLK_000_D1.C
inst_CLK_OUT_PRE.D inst_CLK_OUT_PRE.C cpu_est_2_.D.X1 cpu_est_2_.D.X2
cpu_est_2_.C CLK_CNT_0_.D CLK_CNT_0_.C SM_AMIGA_6_.D- SM_AMIGA_6_.C
SM_AMIGA_6_.AR SM_AMIGA_7_.D SM_AMIGA_7_.C SM_AMIGA_7_.AP SM_AMIGA_1_.D
@@ -44,107 +44,108 @@
SM_AMIGA_5_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_0_.D
SM_AMIGA_0_.C SM_AMIGA_0_.AR
.phase 111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
-.p 102
+.p 103
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+---------0--------------------------------1------------------------- 000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000
+----0--------------------------------------0------------------------ 000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000
+--------------------------------------------1-1-----------1--------0 000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000
------------1------------------------------------------------------- 000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000
-----0------------------------------------------0-------------------- 000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000
----------------------------------------1000---0-1--1--------1------- 000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000
+----0----------------------------------------0---------------------- 000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000
+-------------------------------------1000---0-1--1--------1--------- 000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000
----------1--------------------------------------------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000
-------------------------------------------------1------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000
---------------------------------------------------0-1--------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000
---------------------------------------------------1-0--------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000
----------------------------------------1-1------10-0---------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000
------------------------------------------00-----10-0---------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000
----------------------------------------0-10-----10-1---------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000
----------------------------------------------------1---------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000
-----------------------------------------------------0--------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000
---------------------------------------------0---10------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000
-------------------------------------------------1----0-------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000
------------------------------------------------------00------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000
-------------------------------------------------1-----1------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000
--------------------------------------------1----1--------------1---- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000
-------------------------------------------------1--------1---------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
-------------------------------------------------1-------------1----- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
---------------------------------------------------0------1----0----- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
-------------------------------------------------0----------1-------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000
-------------------------------------------------0------------1------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000
-------------------------------------------------1----------1-------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
----------------------------------------------1-1------------1------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
-------------------------------------------------1-----------1------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
-------------------------------------------------1------------1------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000
----------------------------------------------0--0-----------1------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
------------------------------------------------00-----------1------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
-------------------------------------------------0-------------1----- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
--------------------------------------------0-------------------1---- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
-------------------------------------------------0--------------1---- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
+----------------------------------------------1--------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000
+------------------------------------------------0-1----------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000
+------------------------------------------------1-0----------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000
+-------------------------------------1-1------10-0------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000
+---------------------------------------00-----10-0------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000
+-------------------------------------0-10-----10-1------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000
+-------------------------------------------------1------------------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000
+--------------------------------------------------0----------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000
+------------------------------------------0---10-------------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000
+----------------------------------------------1----0---------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000
+---------------------------------------------------00--------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000
+----------------------------------------------1-----1--------------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000
+-----------------------------------------1----1--------------1------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000
+-----------------------------------------------1--------1----------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
+------------------------------------------------0-------1----------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
+----------------------------------------------1-------------1------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
+----------------------------------------------0----------1---------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000
+----------------------------------------------0------------1-------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000
+----------------------------------------------1----------1---------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
+-------------------------------------------1-1------------1--------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
+----------------------------------------------1-----------1--------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
+----------------------------------------------1------------1-------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000
+-------------------------------------------0--0-----------1--------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
+---------------------------------------------00-----------1--------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
+----------------------------------------------0-------------1------- 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
+-----------------------------------------0-------------------1------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
+----------------------------------------------0--------------1------ 000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
.end
diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl
index 78564b3..7a19c18 100644
--- a/Logic/68030_tk.vcl
+++ b/Logic/68030_tk.vcl
@@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
-DATE = 5/15/14;
-TIME = 23:02:49;
+DATE = 5/16/14;
+TIME = 17:07:12;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;
@@ -155,14 +155,15 @@ AVEC_EXP = OUTPUT,22,2,-;
AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-;
CLK_EXP = OUTPUT,10,1,-;
RESET = OUTPUT,3,1,-;
-inst_CLK_000_DD = NODE,*,3,-;
-inst_CLK_000_D = NODE,*,7,-;
-inst_AS_030_000_SYNC = NODE,*,5,-;
+inst_CLK_000_D0 = NODE,*,6,-;
+inst_CLK_000_D1 = NODE,*,3,-;
+inst_AS_030_000_SYNC = NODE,*,7,-;
RN_FPU_CS = NODE,-1,7,-;
+SM_AMIGA_4_ = NODE,*,5,-;
inst_CLK_OUT_PRE = NODE,*,7,-;
cpu_est_1_ = NODE,*,3,-;
RN_E = NODE,-1,6,-;
-SM_AMIGA_2_ = NODE,*,6,-;
+SM_AMIGA_1_ = NODE,*,6,-;
SM_AMIGA_6_ = NODE,*,3,-;
cpu_est_2_ = NODE,*,3,-;
cpu_est_0_ = NODE,*,3,-;
@@ -170,18 +171,17 @@ RN_VMA = NODE,-1,3,-;
RN_BGACK_030 = NODE,-1,7,-;
RN_AS_000 = NODE,-1,3,-;
SM_AMIGA_5_ = NODE,*,0,-;
-SM_AMIGA_4_ = NODE,*,6,-;
SM_AMIGA_7_ = NODE,*,7,-;
-inst_VPA_D = NODE,*,6,-;
+inst_VPA_D = NODE,*,7,-;
RN_LDS_000 = NODE,-1,3,-;
RN_UDS_000 = NODE,-1,3,-;
+RN_BG_000 = NODE,-1,3,-;
RN_IPL_030_0_ = NODE,-1,1,-;
RN_IPL_030_1_ = NODE,-1,1,-;
-RN_BG_000 = NODE,-1,3,-;
RN_IPL_030_2_ = NODE,-1,1,-;
SM_AMIGA_0_ = NODE,*,7,-;
+SM_AMIGA_2_ = NODE,*,6,-;
SM_AMIGA_3_ = NODE,*,6,-;
-SM_AMIGA_1_ = NODE,*,7,-;
RN_DSACK_1_ = NODE,-1,7,-;
inst_VPA_SYNC = NODE,*,6,-;
inst_DTACK_SYNC = NODE,*,6,-;
diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco
index 7cab251..dcec33a 100644
--- a/Logic/68030_tk.vco
+++ b/Logic/68030_tk.vco
@@ -17,8 +17,8 @@ Parent = m4a5.lci;
SDS_file = m4a5.sds;
Design = 68030_tk.tt4;
Rev = 0.01;
-DATE = 5/15/14;
-TIME = 23:02:50;
+DATE = 5/16/14;
+TIME = 17:07:12;
Type = TT2;
Pre_Fit_Time = 1;
Source_Format = Pure_VHDL;
@@ -131,31 +131,27 @@ Usercode_Format = Hex;
[LOCATION ASSIGNMENT]
Layer = OFF;
-A_21_ = INPUT,94, A,-;
-A_20_ = INPUT,93, A,-;
-SIZE_1_ = INPUT,79, H,-;
-A_19_ = INPUT,97, A,-;
-A_18_ = INPUT,95, A,-;
-A_31_ = INPUT,4, B,-;
A_17_ = INPUT,59, F,-;
A_16_ = INPUT,96, A,-;
+SIZE_1_ = INPUT,79, H,-;
+A_31_ = INPUT,4, B,-;
IPL_2_ = INPUT,68, G,-;
FC_1_ = INPUT,58, F,-;
AS_030 = INPUT,82, H,-;
DS_030 = INPUT,98, A,-;
-CPU_SPACE = INPUT,14,-,-;
+A_0_ = INPUT,69, G,-;
+nEXP_SPACE = INPUT,14,-,-;
BERR = OUTPUT,41, E,-;
BG_030 = INPUT,21, C,-;
-A_0_ = INPUT,69, G,-;
-BGACK_000 = INPUT,28, D,-;
-CLK_030 = INPUT,64,-,-;
IPL_1_ = INPUT,56, F,-;
-CLK_000 = INPUT,11,-,-;
IPL_0_ = INPUT,67, G,-;
-CLK_OSZI = INPUT,61,-,-;
DSACK_0_ = OUTPUT,80, H,-;
-CLK_DIV_OUT = OUTPUT,65, G,-;
+BGACK_000 = INPUT,28, D,-;
FC_0_ = INPUT,57, F,-;
+CLK_030 = INPUT,64,-,-;
+CLK_000 = INPUT,11,-,-;
+CLK_OSZI = INPUT,61,-,-;
+CLK_DIV_OUT = OUTPUT,65, G,-;
AVEC = OUTPUT,92, A,-;
AVEC_EXP = OUTPUT,22, C,-;
VPA = INPUT,36,-,-;
@@ -175,15 +171,19 @@ A_25_ = INPUT,18, C,-;
A_24_ = INPUT,19, C,-;
A_23_ = INPUT,84, H,-;
A_22_ = INPUT,85, H,-;
+A_21_ = INPUT,94, A,-;
+A_20_ = INPUT,93, A,-;
+A_19_ = INPUT,97, A,-;
+A_18_ = INPUT,95, A,-;
IPL_030_2_ = OUTPUT,9, B,-;
DSACK_1_ = BIDIR,81, H,-;
AS_000 = OUTPUT,33, D,-;
UDS_000 = OUTPUT,32, D,-;
LDS_000 = OUTPUT,31, D,-;
-BG_000 = OUTPUT,29, D,-;
-BGACK_030 = OUTPUT,83, H,-;
IPL_030_1_ = OUTPUT,7, B,-;
IPL_030_0_ = OUTPUT,8, B,-;
+BG_000 = OUTPUT,29, D,-;
+BGACK_030 = OUTPUT,83, H,-;
CLK_EXP = OUTPUT,10, B,-;
FPU_CS = OUTPUT,78, H,-;
DTACK = BIDIR,30, D,-;
@@ -192,20 +192,20 @@ VMA = OUTPUT,35, D,-;
RESET = OUTPUT,3, B,-;
cpu_est_0_ = NODE,14, D,-;
cpu_est_1_ = NODE,2, D,-;
-inst_AS_030_000_SYNC = NODE,0, F,-;
+inst_AS_030_000_SYNC = NODE,1, H,-;
inst_DTACK_SYNC = NODE,13, G,-;
-inst_VPA_D = NODE,1, G,-;
+inst_VPA_D = NODE,13, H,-;
inst_VPA_SYNC = NODE,9, G,-;
-inst_CLK_000_D = NODE,1, H,-;
-inst_CLK_000_DD = NODE,13, D,-;
+inst_CLK_000_D0 = NODE,8, G,-;
+inst_CLK_000_D1 = NODE,13, D,-;
inst_CLK_OUT_PRE = NODE,5, H,-;
cpu_est_2_ = NODE,10, D,-;
CLK_CNT_0_ = NODE,6, H,-;
SM_AMIGA_6_ = NODE,6, D,-;
SM_AMIGA_7_ = NODE,9, H,-;
-SM_AMIGA_1_ = NODE,2, H,-;
-SM_AMIGA_4_ = NODE,12, G,-;
+SM_AMIGA_1_ = NODE,12, G,-;
+SM_AMIGA_4_ = NODE,0, F,-;
SM_AMIGA_3_ = NODE,5, G,-;
SM_AMIGA_5_ = NODE,0, A,-;
-SM_AMIGA_2_ = NODE,8, G,-;
-SM_AMIGA_0_ = NODE,13, H,-;
+SM_AMIGA_2_ = NODE,1, G,-;
+SM_AMIGA_0_ = NODE,2, H,-;
diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf
index f1cfaf0..5a79260 100644
--- a/Logic/68030_tk.xrf
+++ b/Logic/68030_tk.xrf
@@ -2,7 +2,7 @@ Signal Name Cross Reference File
ispLEVER Classic 1.7.00.05.28.13
-Design '68030_tk' created Thu May 15 23:02:46 2014
+Design '68030_tk' created Fri May 16 17:07:08 2014
LEGEND: '>' Functional Block Port Separator
diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0
index d5d0895..2df46a2 100644
--- a/Logic/BUS68030.bl0
+++ b/Logic/BUS68030.bl0
@@ -1,87 +1,87 @@
-#$ DATE Thu May 15 23:02:46 2014
+#$ DATE Fri May 16 17:07:08 2014
#$ TOOL EDIF2BLIF version IspLever 1.0
#$ MODULE bus68030
-#$ PINS 74 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ A_15_ A_14_ IPL_2_ A_13_ A_12_ DSACK_1_ A_11_ A_10_ FC_1_ A_9_ AS_030 A_8_ AS_000 A_7_ DS_030 A_6_ UDS_000 A_5_ LDS_000 A_4_ CPU_SPACE A_3_ BERR A_2_ BG_030 A_1_ BG_000 A_0_ BGACK_030 IPL_030_1_ BGACK_000 IPL_030_0_ CLK_030 IPL_1_ CLK_000 IPL_0_ CLK_OSZI DSACK_0_ CLK_DIV_OUT FC_0_ CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
-#$ NODES 344 IPL_030DFFSH_1_reg IPL_030DFFSH_2_reg ipl_c_0__n ipl_c_1__n inst_BGACK_030_INTreg inst_FPU_CS_INTreg ipl_c_2__n cpu_est_3_reg inst_VMA_INTreg gnd_n_n \
-# dsack_c_1__n cpu_est_0_ cpu_est_1_ DTACK_c inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D \
-# inst_CLK_000_DD inst_CLK_OUT_PRE RST_c vcc_n_n cpu_est_2_ RESETDFFreg CLK_CNT_0_ SM_AMIGA_6_ RW_c SM_AMIGA_7_ \
-# inst_UDS_000_INTreg fc_c_0__n inst_LDS_000_INTreg state_machine_un1_clk_030_n fc_c_1__n SM_AMIGA_1_ DSACK_INT_1_ inst_DTACK_DMA SM_AMIGA_4_ state_machine_un6_bgack_000_n \
-# SM_AMIGA_3_ N_99_i state_machine_un13_as_000_int_n un1_bg_030 N_101_i SM_AMIGA_5_ sm_amiga_ns_0_2__n SM_AMIGA_2_ N_107_i SM_AMIGA_0_ \
-# N_106_i sm_amiga_ns_0_5__n N_108_i N_109_i N_110_i sm_amiga_ns_0_7__n N_91_0 CLK_OUT_PRE_i N_94_0 state_machine_un8_clk_000_d_i_n \
-# state_machine_un13_clk_000_d_i_n cpu_est_0_0_ state_machine_un15_clk_000_d_0_n N_93_0 N_104_i N_105_i N_103_i CLK_OUT_PRE_0 state_machine_un60_clk_000_d_i_n state_machine_un17_clk_030_0_n \
-# un1_as_030_3_0 N_145_i clk_un4_clk_000_dd_n a_c_i_0__n clk_cpu_est_11_1__n state_machine_uds_000_int_8_0_n state_machine_un42_clk_030_n state_machine_lds_000_int_8_0_n N_102 state_machine_as_030_000_sync_3_2_n \
-# N_98 size_c_i_1__n N_97 state_machine_un34_clk_000_d_i_n N_100 N_131_i N_92 N_132_i N_112 N_122_i \
-# N_127 N_125_i N_125 N_126_i N_128 N_134_i N_129 N_133_i N_130 N_135_i \
-# N_168 clk_cpu_est_11_0_3__n N_171 N_130_i N_135_1 clk_cpu_est_11_0_1__n state_machine_un13_clk_000_d_2_n N_128_i clk_cpu_est_11_3__n un1_bg_030_0 \
-# N_135 N_97_i N_133 BG_030_c_i N_134 N_127_i N_132 N_129_i N_131 N_92_0 \
-# N_126 N_100_i state_machine_un34_clk_000_d_n N_112_i UDS_000_INT_0_sqmuxa UDS_000_INT_0_sqmuxa_1 clk_un4_clk_000_dd_i_n state_machine_as_030_000_sync_3_n state_machine_un6_bgack_000_0_n N_145 \
-# state_machine_un1_clk_030_0_n state_machine_lds_000_int_8_n clk_cpu_est_11_0_1_3__n state_machine_uds_000_int_8_n state_machine_un34_clk_000_d_i_1_n un1_as_030_4 state_machine_as_030_000_sync_3_2_1_n un1_as_030_3 N_168_1 DSACK_INT_1_sqmuxa \
-# N_168_2 state_machine_un17_clk_030_n N_168_3 state_machine_un60_clk_000_d_n N_168_4 DTACK_SYNC_1_sqmuxa N_168_5 DTACK_SYNC_1_sqmuxa_1 N_168_6 VPA_SYNC_1_sqmuxa \
-# N_171_1 VPA_SYNC_1_sqmuxa_1 N_171_2 N_103 un1_bg_030_0_1 N_104 un1_bg_030_0_2 N_93 clk_cpu_est_11_0_1_1__n N_105 \
-# clk_cpu_est_11_0_2_1__n VPA_SYNC_1_sqmuxa_1_0 state_machine_un42_clk_030_1_n state_machine_un15_clk_000_d_n state_machine_un42_clk_030_2_n state_machine_un13_clk_000_d_n state_machine_un42_clk_030_3_n state_machine_un8_clk_000_d_n state_machine_un42_clk_030_4_n state_machine_un8_clk_000_d_1_n \
-# state_machine_un42_clk_030_5_n state_machine_un13_clk_000_d_1_n N_132_1 N_107 N_131_1 N_94 UDS_000_INT_0_sqmuxa_1_0 N_91 UDS_000_INT_0_sqmuxa_2 N_110 \
-# UDS_000_INT_0_sqmuxa_1_1 N_108 UDS_000_INT_0_sqmuxa_1_2 N_109 UDS_000_INT_0_sqmuxa_1_3 N_106 DTACK_SYNC_1_sqmuxa_1_0 N_101 state_machine_un8_clk_000_d_1_0_n N_99 \
-# state_machine_un8_clk_000_d_2_n AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d_3_n RW_i state_machine_un13_clk_000_d_1_0_n N_102_i state_machine_un13_clk_000_d_2_0_n AS_000_INT_i VPA_SYNC_1_sqmuxa_1_1 dsack_i_1__n \
-# VPA_SYNC_1_sqmuxa_2 AS_030_i VPA_SYNC_1_sqmuxa_3 sm_amiga_i_7__n VPA_SYNC_1_sqmuxa_4 CLK_000_D_i N_107_1 sm_amiga_i_2__n N_98_1 sm_amiga_i_1__n \
-# as_000_int_0_un3_n state_machine_un13_clk_000_d_1_i_n as_000_int_0_un1_n VPA_D_i as_000_int_0_un0_n VMA_INT_i vma_int_0_un3_n cpu_est_i_0__n vma_int_0_un1_n cpu_est_i_1__n \
-# vma_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n state_machine_un8_clk_000_d_1_i_0_n uds_000_int_0_un1_n DTACK_i uds_000_int_0_un0_n sm_amiga_i_3__n dtack_sync_0_un3_n sm_amiga_i_4__n \
-# dtack_sync_0_un1_n sm_amiga_i_5__n dtack_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i vpa_sync_0_un3_n VPA_SYNC_1_sqmuxa_i vpa_sync_0_un1_n N_98_i vpa_sync_0_un0_n state_machine_un42_clk_030_i_n \
-# dsack_int_0_1__un3_n UDS_000_INT_0_sqmuxa_1_i dsack_int_0_1__un1_n UDS_000_INT_0_sqmuxa_i dsack_int_0_1__un0_n AS_030_000_SYNC_i as_030_000_sync_0_un3_n DS_030_i as_030_000_sync_0_un1_n cpu_est_i_2__n \
-# as_030_000_sync_0_un0_n state_machine_un13_clk_000_d_2_i_n fpu_cs_int_0_un3_n CLK_000_DD_i fpu_cs_int_0_un1_n sm_amiga_i_6__n fpu_cs_int_0_un0_n CLK_030_i lds_000_int_0_un3_n a_i_30__n \
-# lds_000_int_0_un1_n a_i_31__n lds_000_int_0_un0_n a_i_28__n cpu_est_0_3__un3_n a_i_29__n cpu_est_0_3__un1_n a_i_26__n cpu_est_0_3__un0_n a_i_27__n \
-# cpu_est_0_2__un3_n a_i_24__n cpu_est_0_2__un1_n a_i_25__n cpu_est_0_2__un0_n a_i_19__n bg_000_0_un3_n a_i_16__n bg_000_0_un1_n a_i_18__n \
-# bg_000_0_un0_n bgack_030_int_0_un3_n RST_i bgack_030_int_0_un1_n bgack_030_int_0_un0_n FPU_CS_INT_i cpu_est_0_1__un3_n CPU_SPACE_i cpu_est_0_1__un1_n BGACK_030_INT_i \
-# cpu_est_0_1__un0_n AS_030_c ipl_030_0_0__un3_n ipl_030_0_0__un1_n ipl_030_0_0__un0_n DS_030_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_2__un3_n \
-# size_c_0__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n a_15__n a_c_0__n a_14__n a_13__n a_12__n a_11__n \
-# a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n a_c_17__n a_4__n a_c_18__n \
-# a_3__n a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n a_c_23__n a_c_24__n a_c_25__n \
-# a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n CPU_SPACE_c BG_030_c BG_000DFFSHreg BGACK_000_c \
-# CLK_030_c CLK_OSZI_c CLK_OUT_INTreg IPL_030DFFSH_0_reg
+#$ PINS 74 A_17_ A_16_ SIZE_1_ A_15_ A_14_ A_31_ A_13_ A_12_ IPL_030_2_ A_11_ A_10_ IPL_2_ A_9_ A_8_ DSACK_1_ A_7_ A_6_ FC_1_ A_5_ AS_030 A_4_ AS_000 A_3_ DS_030 A_2_ UDS_000 A_1_ LDS_000 A_0_ nEXP_SPACE IPL_030_1_ BERR IPL_030_0_ BG_030 IPL_1_ BG_000 IPL_0_ BGACK_030 DSACK_0_ BGACK_000 FC_0_ CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_
+#$ NODES 340 ipl_c_0__n ipl_c_1__n ipl_c_2__n inst_BGACK_030_INTreg inst_FPU_CS_INTreg dsack_c_1__n cpu_est_3_reg inst_VMA_INTreg DTACK_c cpu_est_0_ \
+# cpu_est_1_ inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D0 RST_c inst_CLK_000_D1 inst_CLK_OUT_PRE \
+# RESETDFFreg vcc_n_n gnd_n_n RW_c cpu_est_2_ CLK_CNT_0_ fc_c_0__n SM_AMIGA_6_ SM_AMIGA_7_ fc_c_1__n \
+# inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ state_machine_un60_clk_000_d0_n SM_AMIGA_1_ inst_DTACK_DMA N_100_i SM_AMIGA_4_ sm_amiga_ns_0_2__n SM_AMIGA_3_ \
+# N_103_i DSACK_INT_1_sqmuxa N_104_i state_machine_un13_as_000_int_n VPA_SYNC_1_sqmuxa_1 N_106_i un1_as_030_4 N_105_i SM_AMIGA_5_ sm_amiga_ns_0_5__n \
+# SM_AMIGA_2_ N_107_i SM_AMIGA_0_ N_108_i state_machine_lds_000_int_8_n sm_amiga_ns_0_6__n state_machine_uds_000_int_8_n N_90_i N_93_0 N_128_i \
+# N_126_i N_127_i N_129_i clk_cpu_est_11_0_1__n N_133_i N_132_i N_134_i clk_cpu_est_11_0_3__n N_125_i cpu_est_0_0_ \
+# N_124_i N_130_i N_131_i N_121_i N_91_0 N_109_i sm_amiga_ns_0_7__n CLK_OUT_PRE_0 state_machine_un8_clk_000_d0_i_n state_machine_un13_clk_000_d0_i_n \
+# state_machine_un15_clk_000_d0_0_n BG_030_c_i state_machine_un1_clk_030_0_n clk_un4_clk_000_d1_n state_machine_un17_clk_030_0_n N_144 un1_as_030_3_0 N_101 state_machine_as_030_000_sync_3_2_n VPA_SYNC_1_sqmuxa \
+# N_96_i N_97 un1_bg_030_0 state_machine_un34_clk_000_d0_n clk_un4_clk_000_d1_i_n N_96 state_machine_un6_bgack_000_0_n N_102 N_98_i UDS_000_INT_0_sqmuxa \
+# UDS_000_INT_0_sqmuxa_1 N_111_i N_167 N_99_i N_170 N_92 N_92_0 N_91 state_machine_un34_clk_000_d0_i_n N_99 \
+# a_c_i_0__n N_111 size_c_i_1__n N_98 N_102_i state_machine_un6_bgack_000_n state_machine_un42_clk_030_n N_144_i DTACK_SYNC_1_sqmuxa state_machine_lds_000_int_8_0_n \
+# un1_bg_030 state_machine_uds_000_int_8_0_n state_machine_as_030_000_sync_3_n state_machine_un60_clk_000_d0_i_n DTACK_SYNC_1_sqmuxa_1 un1_bg_030_0_1 un1_as_030_3 un1_bg_030_0_2 state_machine_un17_clk_030_n state_machine_as_030_000_sync_3_2_1_n \
+# state_machine_un1_clk_030_n clk_cpu_est_11_0_1_3__n VPA_SYNC_1_sqmuxa_1_0 clk_cpu_est_11_0_1_1__n state_machine_un15_clk_000_d0_n clk_cpu_est_11_0_2_1__n state_machine_un13_clk_000_d0_n N_167_1 state_machine_un8_clk_000_d0_n N_167_2 \
+# N_109 N_167_3 state_machine_un13_clk_000_d0_1_n N_167_4 N_129 N_167_5 state_machine_un13_clk_000_d0_2_n N_167_6 N_130 N_170_1 \
+# N_131 N_170_2 N_124 UDS_000_INT_0_sqmuxa_1_1 N_125 UDS_000_INT_0_sqmuxa_1_2 N_134 UDS_000_INT_0_sqmuxa_1_3 N_134_1 UDS_000_INT_0_sqmuxa_1_0 \
+# N_106 UDS_000_INT_0_sqmuxa_2 clk_cpu_est_11_3__n state_machine_un34_clk_000_d0_i_1_n N_132 state_machine_un42_clk_030_1_n N_133 state_machine_un42_clk_030_2_n clk_cpu_est_11_1__n state_machine_un42_clk_030_3_n \
+# N_127 state_machine_un42_clk_030_4_n N_126 state_machine_un42_clk_030_5_n N_128 DTACK_SYNC_1_sqmuxa_1_0 N_93 N_130_1 N_90 N_131_1 \
+# N_107 state_machine_un8_clk_000_d0_1_n N_108 state_machine_un8_clk_000_d0_2_n N_105 state_machine_un8_clk_000_d0_3_n N_103 state_machine_un8_clk_000_d0_4_n N_104 state_machine_un13_clk_000_d0_1_0_n \
+# N_100 state_machine_un13_clk_000_d0_2_0_n AS_000_INT_1_sqmuxa VPA_SYNC_1_sqmuxa_1_1 RW_i VPA_SYNC_1_sqmuxa_2 nEXP_SPACE_i VPA_SYNC_1_sqmuxa_3 N_101_i VPA_SYNC_1_sqmuxa_4 \
+# AS_000_INT_i N_106_1 dsack_i_1__n cpu_est_0_3__un3_n AS_030_i cpu_est_0_3__un1_n CLK_000_D0_i cpu_est_0_3__un0_n sm_amiga_i_3__n cpu_est_0_1__un3_n \
+# sm_amiga_i_4__n cpu_est_0_1__un1_n CLK_000_D1_i cpu_est_0_1__un0_n cpu_est_i_0__n as_000_int_0_un3_n cpu_est_i_3__n as_000_int_0_un1_n cpu_est_i_2__n as_000_int_0_un0_n \
+# VPA_D_i bg_000_0_un3_n VMA_INT_i bg_000_0_un1_n cpu_est_i_1__n bg_000_0_un0_n state_machine_un13_clk_000_d0_2_i_n as_030_000_sync_0_un3_n state_machine_un13_clk_000_d0_1_i_n as_030_000_sync_0_un1_n \
+# DTACK_i as_030_000_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i fpu_cs_int_0_un3_n a_i_18__n fpu_cs_int_0_un1_n a_i_16__n fpu_cs_int_0_un0_n a_i_19__n dtack_sync_0_un3_n \
+# CLK_030_i dtack_sync_0_un1_n state_machine_un42_clk_030_i_n dtack_sync_0_un0_n sm_amiga_i_6__n vma_int_0_un3_n sm_amiga_i_7__n vma_int_0_un1_n AS_030_000_SYNC_i vma_int_0_un0_n \
+# DS_030_i cpu_est_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i cpu_est_0_2__un1_n UDS_000_INT_0_sqmuxa_i cpu_est_0_2__un0_n sm_amiga_i_5__n ipl_030_0_0__un3_n VPA_SYNC_1_sqmuxa_i ipl_030_0_0__un1_n \
+# N_97_i ipl_030_0_0__un0_n a_i_30__n ipl_030_0_1__un3_n a_i_31__n ipl_030_0_1__un1_n a_i_28__n ipl_030_0_1__un0_n a_i_29__n ipl_030_0_2__un3_n \
+# a_i_26__n ipl_030_0_2__un1_n a_i_27__n ipl_030_0_2__un0_n a_i_24__n bgack_030_int_0_un3_n a_i_25__n bgack_030_int_0_un1_n bgack_030_int_0_un0_n RST_i \
+# uds_000_int_0_un3_n uds_000_int_0_un1_n FPU_CS_INT_i uds_000_int_0_un0_n BGACK_030_INT_i lds_000_int_0_un3_n AS_030_c lds_000_int_0_un1_n lds_000_int_0_un0_n vpa_sync_0_un3_n \
+# DS_030_c vpa_sync_0_un1_n vpa_sync_0_un0_n dsack_int_0_1__un3_n dsack_int_0_1__un1_n size_c_0__n dsack_int_0_1__un0_n a_15__n size_c_1__n a_14__n \
+# a_c_0__n a_13__n a_12__n a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n \
+# a_5__n a_c_17__n a_4__n a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n \
+# a_c_22__n a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n \
+# nEXP_SPACE_c BG_030_c BG_000DFFSHreg BGACK_000_c CLK_030_c CLK_OSZI_c CLK_OUT_INTreg IPL_030DFFSH_0_reg IPL_030DFFSH_1_reg IPL_030DFFSH_2_reg \
+#
.model bus68030
-.inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF CPU_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF \
+.inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF \
CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \
A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF \
A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF \
- A_1_.BLIF A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF DSACK_0_.BLIF IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_2_reg.BLIF ipl_c_0__n.BLIF ipl_c_1__n.BLIF \
- inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF ipl_c_2__n.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF gnd_n_n.BLIF dsack_c_1__n.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
- DTACK_c.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF inst_CLK_OUT_PRE.BLIF \
- RST_c.BLIF vcc_n_n.BLIF cpu_est_2_.BLIF RESETDFFreg.BLIF CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF RW_c.BLIF SM_AMIGA_7_.BLIF inst_UDS_000_INTreg.BLIF \
- fc_c_0__n.BLIF inst_LDS_000_INTreg.BLIF state_machine_un1_clk_030_n.BLIF fc_c_1__n.BLIF SM_AMIGA_1_.BLIF DSACK_INT_1_.BLIF inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF state_machine_un6_bgack_000_n.BLIF \
- SM_AMIGA_3_.BLIF N_99_i.BLIF state_machine_un13_as_000_int_n.BLIF un1_bg_030.BLIF N_101_i.BLIF SM_AMIGA_5_.BLIF sm_amiga_ns_0_2__n.BLIF SM_AMIGA_2_.BLIF N_107_i.BLIF \
- SM_AMIGA_0_.BLIF N_106_i.BLIF sm_amiga_ns_0_5__n.BLIF N_108_i.BLIF N_109_i.BLIF N_110_i.BLIF sm_amiga_ns_0_7__n.BLIF N_91_0.BLIF CLK_OUT_PRE_i.BLIF \
- N_94_0.BLIF state_machine_un8_clk_000_d_i_n.BLIF state_machine_un13_clk_000_d_i_n.BLIF cpu_est_0_0_.BLIF state_machine_un15_clk_000_d_0_n.BLIF N_93_0.BLIF N_104_i.BLIF N_105_i.BLIF N_103_i.BLIF \
- CLK_OUT_PRE_0.BLIF state_machine_un60_clk_000_d_i_n.BLIF state_machine_un17_clk_030_0_n.BLIF un1_as_030_3_0.BLIF N_145_i.BLIF clk_un4_clk_000_dd_n.BLIF a_c_i_0__n.BLIF clk_cpu_est_11_1__n.BLIF state_machine_uds_000_int_8_0_n.BLIF \
- state_machine_un42_clk_030_n.BLIF state_machine_lds_000_int_8_0_n.BLIF N_102.BLIF state_machine_as_030_000_sync_3_2_n.BLIF N_98.BLIF size_c_i_1__n.BLIF N_97.BLIF state_machine_un34_clk_000_d_i_n.BLIF N_100.BLIF \
- N_131_i.BLIF N_92.BLIF N_132_i.BLIF N_112.BLIF N_122_i.BLIF N_127.BLIF N_125_i.BLIF N_125.BLIF N_126_i.BLIF \
- N_128.BLIF N_134_i.BLIF N_129.BLIF N_133_i.BLIF N_130.BLIF N_135_i.BLIF N_168.BLIF clk_cpu_est_11_0_3__n.BLIF N_171.BLIF \
- N_130_i.BLIF N_135_1.BLIF clk_cpu_est_11_0_1__n.BLIF state_machine_un13_clk_000_d_2_n.BLIF N_128_i.BLIF clk_cpu_est_11_3__n.BLIF un1_bg_030_0.BLIF N_135.BLIF N_97_i.BLIF \
- N_133.BLIF BG_030_c_i.BLIF N_134.BLIF N_127_i.BLIF N_132.BLIF N_129_i.BLIF N_131.BLIF N_92_0.BLIF N_126.BLIF \
- N_100_i.BLIF state_machine_un34_clk_000_d_n.BLIF N_112_i.BLIF UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_1.BLIF clk_un4_clk_000_dd_i_n.BLIF state_machine_as_030_000_sync_3_n.BLIF state_machine_un6_bgack_000_0_n.BLIF N_145.BLIF \
- state_machine_un1_clk_030_0_n.BLIF state_machine_lds_000_int_8_n.BLIF clk_cpu_est_11_0_1_3__n.BLIF state_machine_uds_000_int_8_n.BLIF state_machine_un34_clk_000_d_i_1_n.BLIF un1_as_030_4.BLIF state_machine_as_030_000_sync_3_2_1_n.BLIF un1_as_030_3.BLIF N_168_1.BLIF \
- DSACK_INT_1_sqmuxa.BLIF N_168_2.BLIF state_machine_un17_clk_030_n.BLIF N_168_3.BLIF state_machine_un60_clk_000_d_n.BLIF N_168_4.BLIF DTACK_SYNC_1_sqmuxa.BLIF N_168_5.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF \
- N_168_6.BLIF VPA_SYNC_1_sqmuxa.BLIF N_171_1.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_171_2.BLIF N_103.BLIF un1_bg_030_0_1.BLIF N_104.BLIF un1_bg_030_0_2.BLIF \
- N_93.BLIF clk_cpu_est_11_0_1_1__n.BLIF N_105.BLIF clk_cpu_est_11_0_2_1__n.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF state_machine_un42_clk_030_1_n.BLIF state_machine_un15_clk_000_d_n.BLIF state_machine_un42_clk_030_2_n.BLIF state_machine_un13_clk_000_d_n.BLIF \
- state_machine_un42_clk_030_3_n.BLIF state_machine_un8_clk_000_d_n.BLIF state_machine_un42_clk_030_4_n.BLIF state_machine_un8_clk_000_d_1_n.BLIF state_machine_un42_clk_030_5_n.BLIF state_machine_un13_clk_000_d_1_n.BLIF N_132_1.BLIF N_107.BLIF N_131_1.BLIF \
- N_94.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_91.BLIF UDS_000_INT_0_sqmuxa_2.BLIF N_110.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_108.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF N_109.BLIF \
- UDS_000_INT_0_sqmuxa_1_3.BLIF N_106.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF N_101.BLIF state_machine_un8_clk_000_d_1_0_n.BLIF N_99.BLIF state_machine_un8_clk_000_d_2_n.BLIF AS_000_INT_1_sqmuxa.BLIF state_machine_un8_clk_000_d_3_n.BLIF \
- RW_i.BLIF state_machine_un13_clk_000_d_1_0_n.BLIF N_102_i.BLIF state_machine_un13_clk_000_d_2_0_n.BLIF AS_000_INT_i.BLIF VPA_SYNC_1_sqmuxa_1_1.BLIF dsack_i_1__n.BLIF VPA_SYNC_1_sqmuxa_2.BLIF AS_030_i.BLIF \
- VPA_SYNC_1_sqmuxa_3.BLIF sm_amiga_i_7__n.BLIF VPA_SYNC_1_sqmuxa_4.BLIF CLK_000_D_i.BLIF N_107_1.BLIF sm_amiga_i_2__n.BLIF N_98_1.BLIF sm_amiga_i_1__n.BLIF as_000_int_0_un3_n.BLIF \
- state_machine_un13_clk_000_d_1_i_n.BLIF as_000_int_0_un1_n.BLIF VPA_D_i.BLIF as_000_int_0_un0_n.BLIF VMA_INT_i.BLIF vma_int_0_un3_n.BLIF cpu_est_i_0__n.BLIF vma_int_0_un1_n.BLIF cpu_est_i_1__n.BLIF \
- vma_int_0_un0_n.BLIF cpu_est_i_3__n.BLIF uds_000_int_0_un3_n.BLIF state_machine_un8_clk_000_d_1_i_0_n.BLIF uds_000_int_0_un1_n.BLIF DTACK_i.BLIF uds_000_int_0_un0_n.BLIF sm_amiga_i_3__n.BLIF dtack_sync_0_un3_n.BLIF \
- sm_amiga_i_4__n.BLIF dtack_sync_0_un1_n.BLIF sm_amiga_i_5__n.BLIF dtack_sync_0_un0_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un1_n.BLIF N_98_i.BLIF \
- vpa_sync_0_un0_n.BLIF state_machine_un42_clk_030_i_n.BLIF dsack_int_0_1__un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF dsack_int_0_1__un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF dsack_int_0_1__un0_n.BLIF AS_030_000_SYNC_i.BLIF as_030_000_sync_0_un3_n.BLIF \
- DS_030_i.BLIF as_030_000_sync_0_un1_n.BLIF cpu_est_i_2__n.BLIF as_030_000_sync_0_un0_n.BLIF state_machine_un13_clk_000_d_2_i_n.BLIF fpu_cs_int_0_un3_n.BLIF CLK_000_DD_i.BLIF fpu_cs_int_0_un1_n.BLIF sm_amiga_i_6__n.BLIF \
- fpu_cs_int_0_un0_n.BLIF CLK_030_i.BLIF lds_000_int_0_un3_n.BLIF a_i_30__n.BLIF lds_000_int_0_un1_n.BLIF a_i_31__n.BLIF lds_000_int_0_un0_n.BLIF a_i_28__n.BLIF cpu_est_0_3__un3_n.BLIF \
- a_i_29__n.BLIF cpu_est_0_3__un1_n.BLIF a_i_26__n.BLIF cpu_est_0_3__un0_n.BLIF a_i_27__n.BLIF cpu_est_0_2__un3_n.BLIF a_i_24__n.BLIF cpu_est_0_2__un1_n.BLIF a_i_25__n.BLIF \
- cpu_est_0_2__un0_n.BLIF a_i_19__n.BLIF bg_000_0_un3_n.BLIF a_i_16__n.BLIF bg_000_0_un1_n.BLIF a_i_18__n.BLIF bg_000_0_un0_n.BLIF bgack_030_int_0_un3_n.BLIF RST_i.BLIF \
- bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF FPU_CS_INT_i.BLIF cpu_est_0_1__un3_n.BLIF CPU_SPACE_i.BLIF cpu_est_0_1__un1_n.BLIF BGACK_030_INT_i.BLIF cpu_est_0_1__un0_n.BLIF AS_030_c.BLIF \
- ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF DS_030_c.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF ipl_030_0_2__un3_n.BLIF size_c_0__n.BLIF \
- ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF size_c_1__n.BLIF a_15__n.BLIF a_c_0__n.BLIF a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF \
- a_10__n.BLIF a_9__n.BLIF a_8__n.BLIF a_7__n.BLIF a_6__n.BLIF a_c_16__n.BLIF a_5__n.BLIF a_c_17__n.BLIF a_4__n.BLIF \
- a_c_18__n.BLIF a_3__n.BLIF a_c_19__n.BLIF a_2__n.BLIF a_c_20__n.BLIF a_1__n.BLIF a_c_21__n.BLIF a_c_22__n.BLIF a_c_23__n.BLIF \
- a_c_24__n.BLIF a_c_25__n.BLIF a_c_26__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF CPU_SPACE_c.BLIF \
- BG_030_c.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF CLK_OSZI_c.BLIF CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF DSACK_1_.PIN DTACK.PIN
+ A_1_.BLIF A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF DSACK_0_.BLIF ipl_c_0__n.BLIF ipl_c_1__n.BLIF ipl_c_2__n.BLIF inst_BGACK_030_INTreg.BLIF \
+ inst_FPU_CS_INTreg.BLIF dsack_c_1__n.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF DTACK_c.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \
+ inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF RST_c.BLIF inst_CLK_000_D1.BLIF inst_CLK_OUT_PRE.BLIF RESETDFFreg.BLIF vcc_n_n.BLIF \
+ gnd_n_n.BLIF RW_c.BLIF cpu_est_2_.BLIF CLK_CNT_0_.BLIF fc_c_0__n.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF fc_c_1__n.BLIF inst_UDS_000_INTreg.BLIF \
+ inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF state_machine_un60_clk_000_d0_n.BLIF SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF N_100_i.BLIF SM_AMIGA_4_.BLIF sm_amiga_ns_0_2__n.BLIF SM_AMIGA_3_.BLIF \
+ N_103_i.BLIF DSACK_INT_1_sqmuxa.BLIF N_104_i.BLIF state_machine_un13_as_000_int_n.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_106_i.BLIF un1_as_030_4.BLIF N_105_i.BLIF SM_AMIGA_5_.BLIF \
+ sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.BLIF N_107_i.BLIF SM_AMIGA_0_.BLIF N_108_i.BLIF state_machine_lds_000_int_8_n.BLIF sm_amiga_ns_0_6__n.BLIF state_machine_uds_000_int_8_n.BLIF N_90_i.BLIF \
+ N_93_0.BLIF N_128_i.BLIF N_126_i.BLIF N_127_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_1__n.BLIF N_133_i.BLIF N_132_i.BLIF N_134_i.BLIF \
+ clk_cpu_est_11_0_3__n.BLIF N_125_i.BLIF cpu_est_0_0_.BLIF N_124_i.BLIF N_130_i.BLIF N_131_i.BLIF N_121_i.BLIF N_91_0.BLIF N_109_i.BLIF \
+ sm_amiga_ns_0_7__n.BLIF CLK_OUT_PRE_0.BLIF state_machine_un8_clk_000_d0_i_n.BLIF state_machine_un13_clk_000_d0_i_n.BLIF state_machine_un15_clk_000_d0_0_n.BLIF BG_030_c_i.BLIF state_machine_un1_clk_030_0_n.BLIF clk_un4_clk_000_d1_n.BLIF state_machine_un17_clk_030_0_n.BLIF \
+ N_144.BLIF un1_as_030_3_0.BLIF N_101.BLIF state_machine_as_030_000_sync_3_2_n.BLIF VPA_SYNC_1_sqmuxa.BLIF N_96_i.BLIF N_97.BLIF un1_bg_030_0.BLIF state_machine_un34_clk_000_d0_n.BLIF \
+ clk_un4_clk_000_d1_i_n.BLIF N_96.BLIF state_machine_un6_bgack_000_0_n.BLIF N_102.BLIF N_98_i.BLIF UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_1.BLIF N_111_i.BLIF N_167.BLIF \
+ N_99_i.BLIF N_170.BLIF N_92.BLIF N_92_0.BLIF N_91.BLIF state_machine_un34_clk_000_d0_i_n.BLIF N_99.BLIF a_c_i_0__n.BLIF N_111.BLIF \
+ size_c_i_1__n.BLIF N_98.BLIF N_102_i.BLIF state_machine_un6_bgack_000_n.BLIF state_machine_un42_clk_030_n.BLIF N_144_i.BLIF DTACK_SYNC_1_sqmuxa.BLIF state_machine_lds_000_int_8_0_n.BLIF un1_bg_030.BLIF \
+ state_machine_uds_000_int_8_0_n.BLIF state_machine_as_030_000_sync_3_n.BLIF state_machine_un60_clk_000_d0_i_n.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF un1_bg_030_0_1.BLIF un1_as_030_3.BLIF un1_bg_030_0_2.BLIF state_machine_un17_clk_030_n.BLIF state_machine_as_030_000_sync_3_2_1_n.BLIF \
+ state_machine_un1_clk_030_n.BLIF clk_cpu_est_11_0_1_3__n.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF clk_cpu_est_11_0_1_1__n.BLIF state_machine_un15_clk_000_d0_n.BLIF clk_cpu_est_11_0_2_1__n.BLIF state_machine_un13_clk_000_d0_n.BLIF N_167_1.BLIF state_machine_un8_clk_000_d0_n.BLIF \
+ N_167_2.BLIF N_109.BLIF N_167_3.BLIF state_machine_un13_clk_000_d0_1_n.BLIF N_167_4.BLIF N_129.BLIF N_167_5.BLIF state_machine_un13_clk_000_d0_2_n.BLIF N_167_6.BLIF \
+ N_130.BLIF N_170_1.BLIF N_131.BLIF N_170_2.BLIF N_124.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_125.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF N_134.BLIF \
+ UDS_000_INT_0_sqmuxa_1_3.BLIF N_134_1.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_106.BLIF UDS_000_INT_0_sqmuxa_2.BLIF clk_cpu_est_11_3__n.BLIF state_machine_un34_clk_000_d0_i_1_n.BLIF N_132.BLIF state_machine_un42_clk_030_1_n.BLIF \
+ N_133.BLIF state_machine_un42_clk_030_2_n.BLIF clk_cpu_est_11_1__n.BLIF state_machine_un42_clk_030_3_n.BLIF N_127.BLIF state_machine_un42_clk_030_4_n.BLIF N_126.BLIF state_machine_un42_clk_030_5_n.BLIF N_128.BLIF \
+ DTACK_SYNC_1_sqmuxa_1_0.BLIF N_93.BLIF N_130_1.BLIF N_90.BLIF N_131_1.BLIF N_107.BLIF state_machine_un8_clk_000_d0_1_n.BLIF N_108.BLIF state_machine_un8_clk_000_d0_2_n.BLIF \
+ N_105.BLIF state_machine_un8_clk_000_d0_3_n.BLIF N_103.BLIF state_machine_un8_clk_000_d0_4_n.BLIF N_104.BLIF state_machine_un13_clk_000_d0_1_0_n.BLIF N_100.BLIF state_machine_un13_clk_000_d0_2_0_n.BLIF AS_000_INT_1_sqmuxa.BLIF \
+ VPA_SYNC_1_sqmuxa_1_1.BLIF RW_i.BLIF VPA_SYNC_1_sqmuxa_2.BLIF nEXP_SPACE_i.BLIF VPA_SYNC_1_sqmuxa_3.BLIF N_101_i.BLIF VPA_SYNC_1_sqmuxa_4.BLIF AS_000_INT_i.BLIF N_106_1.BLIF \
+ dsack_i_1__n.BLIF cpu_est_0_3__un3_n.BLIF AS_030_i.BLIF cpu_est_0_3__un1_n.BLIF CLK_000_D0_i.BLIF cpu_est_0_3__un0_n.BLIF sm_amiga_i_3__n.BLIF cpu_est_0_1__un3_n.BLIF sm_amiga_i_4__n.BLIF \
+ cpu_est_0_1__un1_n.BLIF CLK_000_D1_i.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_i_0__n.BLIF as_000_int_0_un3_n.BLIF cpu_est_i_3__n.BLIF as_000_int_0_un1_n.BLIF cpu_est_i_2__n.BLIF as_000_int_0_un0_n.BLIF \
+ VPA_D_i.BLIF bg_000_0_un3_n.BLIF VMA_INT_i.BLIF bg_000_0_un1_n.BLIF cpu_est_i_1__n.BLIF bg_000_0_un0_n.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF as_030_000_sync_0_un3_n.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF \
+ as_030_000_sync_0_un1_n.BLIF DTACK_i.BLIF as_030_000_sync_0_un0_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF fpu_cs_int_0_un3_n.BLIF a_i_18__n.BLIF fpu_cs_int_0_un1_n.BLIF a_i_16__n.BLIF fpu_cs_int_0_un0_n.BLIF \
+ a_i_19__n.BLIF dtack_sync_0_un3_n.BLIF CLK_030_i.BLIF dtack_sync_0_un1_n.BLIF state_machine_un42_clk_030_i_n.BLIF dtack_sync_0_un0_n.BLIF sm_amiga_i_6__n.BLIF vma_int_0_un3_n.BLIF sm_amiga_i_7__n.BLIF \
+ vma_int_0_un1_n.BLIF AS_030_000_SYNC_i.BLIF vma_int_0_un0_n.BLIF DS_030_i.BLIF cpu_est_0_2__un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF cpu_est_0_2__un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF cpu_est_0_2__un0_n.BLIF \
+ sm_amiga_i_5__n.BLIF ipl_030_0_0__un3_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF ipl_030_0_0__un1_n.BLIF N_97_i.BLIF ipl_030_0_0__un0_n.BLIF a_i_30__n.BLIF ipl_030_0_1__un3_n.BLIF a_i_31__n.BLIF \
+ ipl_030_0_1__un1_n.BLIF a_i_28__n.BLIF ipl_030_0_1__un0_n.BLIF a_i_29__n.BLIF ipl_030_0_2__un3_n.BLIF a_i_26__n.BLIF ipl_030_0_2__un1_n.BLIF a_i_27__n.BLIF ipl_030_0_2__un0_n.BLIF \
+ a_i_24__n.BLIF bgack_030_int_0_un3_n.BLIF a_i_25__n.BLIF bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF RST_i.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un1_n.BLIF FPU_CS_INT_i.BLIF \
+ uds_000_int_0_un0_n.BLIF BGACK_030_INT_i.BLIF lds_000_int_0_un3_n.BLIF AS_030_c.BLIF lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF vpa_sync_0_un3_n.BLIF DS_030_c.BLIF vpa_sync_0_un1_n.BLIF \
+ vpa_sync_0_un0_n.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF size_c_0__n.BLIF dsack_int_0_1__un0_n.BLIF a_15__n.BLIF size_c_1__n.BLIF a_14__n.BLIF a_c_0__n.BLIF \
+ a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF a_10__n.BLIF a_9__n.BLIF a_8__n.BLIF a_7__n.BLIF a_6__n.BLIF a_c_16__n.BLIF \
+ a_5__n.BLIF a_c_17__n.BLIF a_4__n.BLIF a_c_18__n.BLIF a_3__n.BLIF a_c_19__n.BLIF a_2__n.BLIF a_c_20__n.BLIF a_1__n.BLIF \
+ a_c_21__n.BLIF a_c_22__n.BLIF a_c_23__n.BLIF a_c_24__n.BLIF a_c_25__n.BLIF a_c_26__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF a_c_29__n.BLIF \
+ a_c_30__n.BLIF a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF CLK_OSZI_c.BLIF CLK_OUT_INTreg.BLIF \
+ IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_2_reg.BLIF DSACK_1_.PIN DTACK.PIN
.outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS AVEC \
AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_3_.D \
SM_AMIGA_3_.C SM_AMIGA_3_.AR SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_2_.AR SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_1_.AR SM_AMIGA_0_.D SM_AMIGA_0_.C SM_AMIGA_0_.AR \
@@ -91,42 +91,42 @@
cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_reg.D cpu_est_3_reg.C inst_LDS_000_INTreg.D inst_LDS_000_INTreg.C inst_LDS_000_INTreg.AP inst_DTACK_SYNC.D \
inst_DTACK_SYNC.C inst_DTACK_SYNC.AP inst_FPU_CS_INTreg.D inst_FPU_CS_INTreg.C inst_FPU_CS_INTreg.AP inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_030_000_SYNC.AP inst_AS_000_INTreg.D inst_AS_000_INTreg.C inst_AS_000_INTreg.AP \
inst_VPA_SYNC.D inst_VPA_SYNC.C inst_VPA_SYNC.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_UDS_000_INTreg.D inst_UDS_000_INTreg.C \
- inst_UDS_000_INTreg.AP CLK_CNT_0_.D CLK_CNT_0_.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C \
- CLK_OUT_INTreg.D CLK_OUT_INTreg.C CLK_OUT_PRE_0.X1 CLK_OUT_PRE_0.X2 cpu_est_0_0_.X1 cpu_est_0_0_.X2 DSACK_1_ DTACK DSACK_0_ ipl_c_0__n ipl_c_1__n ipl_c_2__n gnd_n_n dsack_c_1__n \
- DTACK_c RST_c vcc_n_n RW_c fc_c_0__n state_machine_un1_clk_030_n fc_c_1__n state_machine_un6_bgack_000_n N_99_i state_machine_un13_as_000_int_n un1_bg_030 \
- N_101_i sm_amiga_ns_0_2__n N_107_i N_106_i sm_amiga_ns_0_5__n N_108_i N_109_i N_110_i sm_amiga_ns_0_7__n N_91_0 CLK_OUT_PRE_i \
- N_94_0 state_machine_un8_clk_000_d_i_n state_machine_un13_clk_000_d_i_n state_machine_un15_clk_000_d_0_n N_93_0 N_104_i N_105_i N_103_i state_machine_un60_clk_000_d_i_n state_machine_un17_clk_030_0_n un1_as_030_3_0 \
- N_145_i clk_un4_clk_000_dd_n a_c_i_0__n clk_cpu_est_11_1__n state_machine_uds_000_int_8_0_n state_machine_un42_clk_030_n state_machine_lds_000_int_8_0_n N_102 state_machine_as_030_000_sync_3_2_n N_98 size_c_i_1__n \
- N_97 state_machine_un34_clk_000_d_i_n N_100 N_131_i N_92 N_132_i N_112 N_122_i N_127 N_125_i N_125 \
- N_126_i N_128 N_134_i N_129 N_133_i N_130 N_135_i N_168 clk_cpu_est_11_0_3__n N_171 N_130_i \
- N_135_1 clk_cpu_est_11_0_1__n state_machine_un13_clk_000_d_2_n N_128_i clk_cpu_est_11_3__n un1_bg_030_0 N_135 N_97_i N_133 BG_030_c_i N_134 \
- N_127_i N_132 N_129_i N_131 N_92_0 N_126 N_100_i state_machine_un34_clk_000_d_n N_112_i UDS_000_INT_0_sqmuxa UDS_000_INT_0_sqmuxa_1 \
- clk_un4_clk_000_dd_i_n state_machine_as_030_000_sync_3_n state_machine_un6_bgack_000_0_n N_145 state_machine_un1_clk_030_0_n state_machine_lds_000_int_8_n clk_cpu_est_11_0_1_3__n state_machine_uds_000_int_8_n state_machine_un34_clk_000_d_i_1_n un1_as_030_4 state_machine_as_030_000_sync_3_2_1_n \
- un1_as_030_3 N_168_1 DSACK_INT_1_sqmuxa N_168_2 state_machine_un17_clk_030_n N_168_3 state_machine_un60_clk_000_d_n N_168_4 DTACK_SYNC_1_sqmuxa N_168_5 DTACK_SYNC_1_sqmuxa_1 \
- N_168_6 VPA_SYNC_1_sqmuxa N_171_1 VPA_SYNC_1_sqmuxa_1 N_171_2 N_103 un1_bg_030_0_1 N_104 un1_bg_030_0_2 N_93 clk_cpu_est_11_0_1_1__n \
- N_105 clk_cpu_est_11_0_2_1__n VPA_SYNC_1_sqmuxa_1_0 state_machine_un42_clk_030_1_n state_machine_un15_clk_000_d_n state_machine_un42_clk_030_2_n state_machine_un13_clk_000_d_n state_machine_un42_clk_030_3_n state_machine_un8_clk_000_d_n state_machine_un42_clk_030_4_n state_machine_un8_clk_000_d_1_n \
- state_machine_un42_clk_030_5_n state_machine_un13_clk_000_d_1_n N_132_1 N_107 N_131_1 N_94 UDS_000_INT_0_sqmuxa_1_0 N_91 UDS_000_INT_0_sqmuxa_2 N_110 UDS_000_INT_0_sqmuxa_1_1 \
- N_108 UDS_000_INT_0_sqmuxa_1_2 N_109 UDS_000_INT_0_sqmuxa_1_3 N_106 DTACK_SYNC_1_sqmuxa_1_0 N_101 state_machine_un8_clk_000_d_1_0_n N_99 state_machine_un8_clk_000_d_2_n AS_000_INT_1_sqmuxa \
- state_machine_un8_clk_000_d_3_n RW_i state_machine_un13_clk_000_d_1_0_n N_102_i state_machine_un13_clk_000_d_2_0_n AS_000_INT_i VPA_SYNC_1_sqmuxa_1_1 dsack_i_1__n VPA_SYNC_1_sqmuxa_2 AS_030_i VPA_SYNC_1_sqmuxa_3 \
- sm_amiga_i_7__n VPA_SYNC_1_sqmuxa_4 CLK_000_D_i N_107_1 sm_amiga_i_2__n N_98_1 sm_amiga_i_1__n as_000_int_0_un3_n state_machine_un13_clk_000_d_1_i_n as_000_int_0_un1_n VPA_D_i \
- as_000_int_0_un0_n VMA_INT_i vma_int_0_un3_n cpu_est_i_0__n vma_int_0_un1_n cpu_est_i_1__n vma_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n state_machine_un8_clk_000_d_1_i_0_n uds_000_int_0_un1_n \
- DTACK_i uds_000_int_0_un0_n sm_amiga_i_3__n dtack_sync_0_un3_n sm_amiga_i_4__n dtack_sync_0_un1_n sm_amiga_i_5__n dtack_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i vpa_sync_0_un3_n VPA_SYNC_1_sqmuxa_i \
- vpa_sync_0_un1_n N_98_i vpa_sync_0_un0_n state_machine_un42_clk_030_i_n dsack_int_0_1__un3_n UDS_000_INT_0_sqmuxa_1_i dsack_int_0_1__un1_n UDS_000_INT_0_sqmuxa_i dsack_int_0_1__un0_n AS_030_000_SYNC_i as_030_000_sync_0_un3_n \
- DS_030_i as_030_000_sync_0_un1_n cpu_est_i_2__n as_030_000_sync_0_un0_n state_machine_un13_clk_000_d_2_i_n fpu_cs_int_0_un3_n CLK_000_DD_i fpu_cs_int_0_un1_n sm_amiga_i_6__n fpu_cs_int_0_un0_n CLK_030_i \
- lds_000_int_0_un3_n a_i_30__n lds_000_int_0_un1_n a_i_31__n lds_000_int_0_un0_n a_i_28__n cpu_est_0_3__un3_n a_i_29__n cpu_est_0_3__un1_n a_i_26__n cpu_est_0_3__un0_n \
- a_i_27__n cpu_est_0_2__un3_n a_i_24__n cpu_est_0_2__un1_n a_i_25__n cpu_est_0_2__un0_n a_i_19__n bg_000_0_un3_n a_i_16__n bg_000_0_un1_n a_i_18__n \
- bg_000_0_un0_n bgack_030_int_0_un3_n RST_i bgack_030_int_0_un1_n bgack_030_int_0_un0_n FPU_CS_INT_i cpu_est_0_1__un3_n CPU_SPACE_i cpu_est_0_1__un1_n BGACK_030_INT_i cpu_est_0_1__un0_n \
- AS_030_c ipl_030_0_0__un3_n ipl_030_0_0__un1_n ipl_030_0_0__un0_n DS_030_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n ipl_030_0_2__un1_n \
- ipl_030_0_2__un0_n size_c_1__n a_15__n a_c_0__n a_14__n a_13__n a_12__n a_11__n a_10__n a_9__n a_8__n \
- a_7__n a_6__n a_c_16__n a_5__n a_c_17__n a_4__n a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n \
- a_1__n a_c_21__n a_c_22__n a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n \
- a_c_31__n CPU_SPACE_c BG_030_c BGACK_000_c CLK_030_c CLK_OSZI_c DSACK_1_.OE DTACK.OE AS_000.OE \
- UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE AVEC_EXP.OE CIIN.OE
+ inst_UDS_000_INTreg.AP CLK_CNT_0_.D CLK_CNT_0_.C inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D RESETDFFreg.C inst_CLK_000_D1.D inst_CLK_000_D1.C \
+ CLK_OUT_INTreg.D CLK_OUT_INTreg.C cpu_est_0_0_.X1 cpu_est_0_0_.X2 CLK_OUT_PRE_0.X1 CLK_OUT_PRE_0.X2 DSACK_1_ DTACK DSACK_0_ ipl_c_0__n ipl_c_1__n ipl_c_2__n dsack_c_1__n DTACK_c \
+ RST_c vcc_n_n gnd_n_n RW_c fc_c_0__n fc_c_1__n state_machine_un60_clk_000_d0_n N_100_i sm_amiga_ns_0_2__n N_103_i DSACK_INT_1_sqmuxa \
+ N_104_i state_machine_un13_as_000_int_n VPA_SYNC_1_sqmuxa_1 N_106_i un1_as_030_4 N_105_i sm_amiga_ns_0_5__n N_107_i N_108_i state_machine_lds_000_int_8_n sm_amiga_ns_0_6__n \
+ state_machine_uds_000_int_8_n N_90_i N_93_0 N_128_i N_126_i N_127_i N_129_i clk_cpu_est_11_0_1__n N_133_i N_132_i N_134_i \
+ clk_cpu_est_11_0_3__n N_125_i N_124_i N_130_i N_131_i N_121_i N_91_0 N_109_i sm_amiga_ns_0_7__n state_machine_un8_clk_000_d0_i_n state_machine_un13_clk_000_d0_i_n \
+ state_machine_un15_clk_000_d0_0_n BG_030_c_i state_machine_un1_clk_030_0_n clk_un4_clk_000_d1_n state_machine_un17_clk_030_0_n N_144 un1_as_030_3_0 N_101 state_machine_as_030_000_sync_3_2_n VPA_SYNC_1_sqmuxa N_96_i \
+ N_97 un1_bg_030_0 state_machine_un34_clk_000_d0_n clk_un4_clk_000_d1_i_n N_96 state_machine_un6_bgack_000_0_n N_102 N_98_i UDS_000_INT_0_sqmuxa UDS_000_INT_0_sqmuxa_1 N_111_i \
+ N_167 N_99_i N_170 N_92 N_92_0 N_91 state_machine_un34_clk_000_d0_i_n N_99 a_c_i_0__n N_111 size_c_i_1__n \
+ N_98 N_102_i state_machine_un6_bgack_000_n state_machine_un42_clk_030_n N_144_i DTACK_SYNC_1_sqmuxa state_machine_lds_000_int_8_0_n un1_bg_030 state_machine_uds_000_int_8_0_n state_machine_as_030_000_sync_3_n state_machine_un60_clk_000_d0_i_n \
+ DTACK_SYNC_1_sqmuxa_1 un1_bg_030_0_1 un1_as_030_3 un1_bg_030_0_2 state_machine_un17_clk_030_n state_machine_as_030_000_sync_3_2_1_n state_machine_un1_clk_030_n clk_cpu_est_11_0_1_3__n VPA_SYNC_1_sqmuxa_1_0 clk_cpu_est_11_0_1_1__n state_machine_un15_clk_000_d0_n \
+ clk_cpu_est_11_0_2_1__n state_machine_un13_clk_000_d0_n N_167_1 state_machine_un8_clk_000_d0_n N_167_2 N_109 N_167_3 state_machine_un13_clk_000_d0_1_n N_167_4 N_129 N_167_5 \
+ state_machine_un13_clk_000_d0_2_n N_167_6 N_130 N_170_1 N_131 N_170_2 N_124 UDS_000_INT_0_sqmuxa_1_1 N_125 UDS_000_INT_0_sqmuxa_1_2 N_134 \
+ UDS_000_INT_0_sqmuxa_1_3 N_134_1 UDS_000_INT_0_sqmuxa_1_0 N_106 UDS_000_INT_0_sqmuxa_2 clk_cpu_est_11_3__n state_machine_un34_clk_000_d0_i_1_n N_132 state_machine_un42_clk_030_1_n N_133 state_machine_un42_clk_030_2_n \
+ clk_cpu_est_11_1__n state_machine_un42_clk_030_3_n N_127 state_machine_un42_clk_030_4_n N_126 state_machine_un42_clk_030_5_n N_128 DTACK_SYNC_1_sqmuxa_1_0 N_93 N_130_1 N_90 \
+ N_131_1 N_107 state_machine_un8_clk_000_d0_1_n N_108 state_machine_un8_clk_000_d0_2_n N_105 state_machine_un8_clk_000_d0_3_n N_103 state_machine_un8_clk_000_d0_4_n N_104 state_machine_un13_clk_000_d0_1_0_n \
+ N_100 state_machine_un13_clk_000_d0_2_0_n AS_000_INT_1_sqmuxa VPA_SYNC_1_sqmuxa_1_1 RW_i VPA_SYNC_1_sqmuxa_2 nEXP_SPACE_i VPA_SYNC_1_sqmuxa_3 N_101_i VPA_SYNC_1_sqmuxa_4 AS_000_INT_i \
+ N_106_1 dsack_i_1__n cpu_est_0_3__un3_n AS_030_i cpu_est_0_3__un1_n CLK_000_D0_i cpu_est_0_3__un0_n sm_amiga_i_3__n cpu_est_0_1__un3_n sm_amiga_i_4__n cpu_est_0_1__un1_n \
+ CLK_000_D1_i cpu_est_0_1__un0_n cpu_est_i_0__n as_000_int_0_un3_n cpu_est_i_3__n as_000_int_0_un1_n cpu_est_i_2__n as_000_int_0_un0_n VPA_D_i bg_000_0_un3_n VMA_INT_i \
+ bg_000_0_un1_n cpu_est_i_1__n bg_000_0_un0_n state_machine_un13_clk_000_d0_2_i_n as_030_000_sync_0_un3_n state_machine_un13_clk_000_d0_1_i_n as_030_000_sync_0_un1_n DTACK_i as_030_000_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i fpu_cs_int_0_un3_n \
+ a_i_18__n fpu_cs_int_0_un1_n a_i_16__n fpu_cs_int_0_un0_n a_i_19__n dtack_sync_0_un3_n CLK_030_i dtack_sync_0_un1_n state_machine_un42_clk_030_i_n dtack_sync_0_un0_n sm_amiga_i_6__n \
+ vma_int_0_un3_n sm_amiga_i_7__n vma_int_0_un1_n AS_030_000_SYNC_i vma_int_0_un0_n DS_030_i cpu_est_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i cpu_est_0_2__un1_n UDS_000_INT_0_sqmuxa_i cpu_est_0_2__un0_n \
+ sm_amiga_i_5__n ipl_030_0_0__un3_n VPA_SYNC_1_sqmuxa_i ipl_030_0_0__un1_n N_97_i ipl_030_0_0__un0_n a_i_30__n ipl_030_0_1__un3_n a_i_31__n ipl_030_0_1__un1_n a_i_28__n \
+ ipl_030_0_1__un0_n a_i_29__n ipl_030_0_2__un3_n a_i_26__n ipl_030_0_2__un1_n a_i_27__n ipl_030_0_2__un0_n a_i_24__n bgack_030_int_0_un3_n a_i_25__n bgack_030_int_0_un1_n \
+ bgack_030_int_0_un0_n RST_i uds_000_int_0_un3_n uds_000_int_0_un1_n FPU_CS_INT_i uds_000_int_0_un0_n BGACK_030_INT_i lds_000_int_0_un3_n AS_030_c lds_000_int_0_un1_n lds_000_int_0_un0_n \
+ vpa_sync_0_un3_n DS_030_c vpa_sync_0_un1_n vpa_sync_0_un0_n dsack_int_0_1__un3_n dsack_int_0_1__un1_n size_c_0__n dsack_int_0_1__un0_n a_15__n size_c_1__n a_14__n \
+ a_c_0__n a_13__n a_12__n a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n \
+ a_c_17__n a_4__n a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n a_c_23__n \
+ a_c_24__n a_c_25__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c BGACK_000_c \
+ CLK_030_c CLK_OSZI_c DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE \
+ AVEC_EXP.OE CIIN.OE
.names DSACK_INT_1_.BLIF DSACK_1_
1 1
.names DSACK_1_.PIN dsack_c_1__n
1 1
-.names CPU_SPACE_i.BLIF DSACK_1_.OE
+.names nEXP_SPACE_c.BLIF DSACK_1_.OE
1 1
.names inst_DTACK_DMA.BLIF DTACK
1 1
@@ -152,232 +152,168 @@
1 1
.names vcc_n_n.BLIF DSACK_0_
1 1
-.names CPU_SPACE_i.BLIF DSACK_0_.OE
+.names nEXP_SPACE_c.BLIF DSACK_0_.OE
1 1
.names gnd_n_n.BLIF AVEC_EXP
1 1
.names FPU_CS_INT_i.BLIF AVEC_EXP.OE
1 1
-.names N_171.BLIF CIIN
+.names N_170.BLIF CIIN
1 1
-.names N_168.BLIF CIIN.OE
+.names N_167.BLIF CIIN.OE
1 1
+.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n
+0 1
.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n
11 1
-.names N_102_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
+.names N_101_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
11 1
-.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C
-1 1
.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF inst_AS_000_INTreg.D
1- 1
-1 1
-.names RW_c.BLIF RW_i
-0 1
-.names RST_i.BLIF IPL_030DFFSH_2_reg.AP
-1 1
-.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF state_machine_un13_clk_000_d_1_n
-11 1
-.names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_94_0
-11 1
-.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_91_0
-11 1
-.names N_98_i.BLIF N_110_i.BLIF sm_amiga_ns_0_7__n
-11 1
.names CLK_OSZI_c.BLIF SM_AMIGA_7_.C
1 1
-.names N_108_i.BLIF N_109_i.BLIF SM_AMIGA_1_.D
-11 1
-.names N_106_i.BLIF N_107_i.BLIF sm_amiga_ns_0_5__n
-11 1
+.names RW_c.BLIF RW_i
+0 1
+.names nEXP_SPACE_c.BLIF nEXP_SPACE_i
+0 1
.names RST_i.BLIF SM_AMIGA_7_.AP
1 1
-.names N_101_i.BLIF N_102_i.BLIF sm_amiga_ns_0_2__n
+.names N_100_i.BLIF N_101_i.BLIF sm_amiga_ns_0_2__n
11 1
-.names inst_CLK_000_D.BLIF N_99_i.BLIF SM_AMIGA_7_.D
-11 1
-.names state_machine_un13_clk_000_d_1_n.BLIF state_machine_un13_clk_000_d_1_i_n
+.names inst_CLK_000_D1.BLIF CLK_000_D1_i
0 1
-.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d_1_i_n.BLIF N_110
+.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF clk_un4_clk_000_d1_n
+11 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_108
11 1
.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C
1 1
-.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n
-0 1
-.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
-0 1
+.names N_90.BLIF SM_AMIGA_1_.BLIF N_107
+11 1
+.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_105
+11 1
.names RST_i.BLIF SM_AMIGA_6_.AR
1 1
-.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_109
-11 1
-.names CLK_000_D_i.BLIF N_94.BLIF N_108
-11 1
-.names inst_CLK_000_D.BLIF CLK_000_D_i
-0 1
.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n
0 1
+.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
+0 1
+.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_104
+11 1
+.names inst_CLK_000_D0.BLIF CLK_000_D0_i
+0 1
.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C
1 1
-.names SM_AMIGA_3_.BLIF state_machine_un60_clk_000_d_i_n.BLIF N_93_0
+.names CLK_000_D0_i.BLIF N_93.BLIF N_103
+11 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF N_100
11 1
-.names DTACK_c.BLIF DTACK_i
-0 1
.names RST_i.BLIF SM_AMIGA_5_.AR
1 1
-.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0
+.names N_90_i.BLIF SM_AMIGA_1_.BLIF N_97
11 1
-.names state_machine_un8_clk_000_d_1_n.BLIF state_machine_un8_clk_000_d_1_i_0_n
+.names AS_030_c.BLIF AS_030_i
0 1
-.names state_machine_un15_clk_000_d_n.BLIF vma_int_0_un3_n
-0 1
-.names state_machine_un8_clk_000_d_1_i_0_n.BLIF state_machine_un15_clk_000_d_n.BLIF vma_int_0_un1_n
+.names AS_030_i.BLIF N_101_i.BLIF AS_000_INT_1_sqmuxa
+11 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0
11 1
.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C
1 1
-.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
+.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF state_machine_un13_clk_000_d0_1_n
+11 1
+.names N_125_i.BLIF cpu_est_i_2__n.BLIF N_133
11 1
-.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D
-1- 1
--1 1
.names RST_i.BLIF SM_AMIGA_4_.AR
1 1
-.names state_machine_un8_clk_000_d_i_n.BLIF state_machine_un13_clk_000_d_i_n.BLIF state_machine_un15_clk_000_d_0_n
+.names N_125.BLIF cpu_est_3_reg.BLIF N_132
11 1
-.names CLK_000_D_i.BLIF cpu_est_0_.BLIF state_machine_un8_clk_000_d_1_n
+.names N_124_i.BLIF cpu_est_0_.BLIF N_128
11 1
.names cpu_est_3_reg.BLIF cpu_est_i_3__n
0 1
-.names cpu_est_0_.BLIF cpu_est_i_0__n
+.names cpu_est_2_.BLIF cpu_est_i_2__n
0 1
.names CLK_OSZI_c.BLIF DSACK_INT_1_.C
1 1
-.names cpu_est_1_.BLIF cpu_est_i_1__n
-0 1
-.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_135_1
+.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_127
11 1
+.names cpu_est_0_.BLIF cpu_est_i_0__n
+0 1
.names RST_i.BLIF DSACK_INT_1_.AP
1 1
+.names N_124.BLIF cpu_est_i_0__n.BLIF N_126
+11 1
+.names SM_AMIGA_3_.BLIF state_machine_un60_clk_000_d0_i_n.BLIF N_93_0
+11 1
+.names CLK_000_D1_i.BLIF inst_CLK_OUT_PRE.BLIF N_90_i
+11 1
+.names N_107_i.BLIF N_108_i.BLIF sm_amiga_ns_0_6__n
+11 1
+.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C
+1 1
+.names N_105_i.BLIF N_106_i.BLIF sm_amiga_ns_0_5__n
+11 1
+.names N_103_i.BLIF N_104_i.BLIF SM_AMIGA_3_.D
+11 1
+.names RST_i.BLIF inst_VMA_INTreg.AP
+1 1
+.names N_97_i.BLIF N_109_i.BLIF sm_amiga_ns_0_7__n
+11 1
+.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_91_0
+11 1
+.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d0_2_n.BLIF N_129
+11 1
+.names N_130_i.BLIF N_131_i.BLIF N_121_i
+11 1
+.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C
+1 1
+.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_124_i
+11 1
+.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_125_i
+11 1
+.names RST_i.BLIF inst_BGACK_030_INTreg.AP
+1 1
+.names state_machine_un13_clk_000_d0_2_n.BLIF state_machine_un13_clk_000_d0_2_i_n
+0 1
+.names N_134_1.BLIF cpu_est_i_2__n.BLIF N_134
+11 1
+.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d0_2_n
+11 1
+.names cpu_est_1_.BLIF cpu_est_i_1__n
+0 1
+.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C
+1 1
+.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_134_1
+11 1
.names inst_VPA_D.BLIF VPA_D_i
0 1
.names inst_VMA_INTreg.BLIF VMA_INT_i
0 1
-.names un1_as_030_4.BLIF uds_000_int_0_un3_n
-0 1
-.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C
-1 1
-.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n
-11 1
-.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n
-11 1
-.names RST_i.BLIF inst_VMA_INTreg.AP
-1 1
-.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D
-1- 1
--1 1
-.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF state_machine_un60_clk_000_d_i_n
-11 1
-.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n
-0 1
-.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n
-11 1
-.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C
-1 1
-.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n
-11 1
-.names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D
-1- 1
--1 1
-.names RST_i.BLIF inst_BGACK_030_INTreg.AP
-1 1
-.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n
-0 1
-.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n
-11 1
-.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n
-11 1
-.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D
-1- 1
--1 1
-.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE.C
-1 1
-.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i
-0 1
-.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1
-11 1
-.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i
-0 1
-.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1
-11 1
.names CLK_OSZI_c.BLIF cpu_est_0_.C
1 1
-.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
+.names a_c_16__n.BLIF a_i_16__n
0 1
-.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_103
-11 1
-.names CLK_000_D_i.BLIF N_93.BLIF N_104
-11 1
-.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
+.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n
0 1
+.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n
+11 1
.names CLK_OSZI_c.BLIF cpu_est_1_.C
1 1
-.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_105
+.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
11 1
-.names CLK_000_D_i.BLIF N_103_i.BLIF SM_AMIGA_4_.D
-11 1
-.names N_104_i.BLIF N_105_i.BLIF SM_AMIGA_3_.D
-11 1
-.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i
-0 1
-.names CLK_OSZI_c.BLIF cpu_est_2_.C
-1 1
-.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i
-0 1
-.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_145
-11 1
-.names N_145_i.BLIF state_machine_un34_clk_000_d_n.BLIF state_machine_lds_000_int_8_0_n
-11 1
-.names a_c_i_0__n.BLIF N_145_i.BLIF state_machine_uds_000_int_8_0_n
-11 1
-.names CLK_OSZI_c.BLIF cpu_est_3_reg.C
-1 1
-.names AS_030_i.BLIF N_145.BLIF un1_as_030_4
-11 1
-.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n
-0 1
-.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_3_0
-11 1
-.names AS_030_i.BLIF N_98_i.BLIF DSACK_INT_1_sqmuxa
-11 1
-.names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C
-1 1
-.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n
-11 1
-.names N_98.BLIF N_98_i
-0 1
-.names RST_i.BLIF inst_LDS_000_INTreg.AP
-1 1
-.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n
-0 1
-.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n
-11 1
-.names N_98_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n
-11 1
-.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D
+.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D
1- 1
-1 1
-.names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C
-1 1
.names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n
0 1
-.names AS_030.BLIF AS_030_c
-1 1
.names state_machine_as_030_000_sync_3_n.BLIF state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n
11 1
-.names RST_i.BLIF inst_DTACK_SYNC.AP
+.names CLK_OSZI_c.BLIF cpu_est_2_.C
1 1
.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n
11 1
-.names DS_030.BLIF DS_030_c
-1 1
.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF inst_AS_030_000_SYNC.D
1- 1
-1 1
@@ -385,629 +321,685 @@
0 1
.names un1_as_030_3.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n
11 1
-.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C
-1 1
-.names SIZE_0_.BLIF size_c_0__n
+.names CLK_OSZI_c.BLIF cpu_est_3_reg.C
1 1
.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n
11 1
-.names SIZE_1_.BLIF size_c_1__n
-1 1
.names fpu_cs_int_0_un1_n.BLIF fpu_cs_int_0_un0_n.BLIF inst_FPU_CS_INTreg.D
1- 1
-1 1
-.names RST_i.BLIF inst_FPU_CS_INTreg.AP
-1 1
-.names A_0_.BLIF a_c_0__n
-1 1
-.names un1_as_030_4.BLIF lds_000_int_0_un3_n
+.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i
0 1
-.names A_16_.BLIF a_c_16__n
+.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n
+0 1
+.names CLK_OSZI_c.BLIF inst_LDS_000_INTreg.C
1 1
-.names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n
+.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n
11 1
-.names A_17_.BLIF a_c_17__n
-1 1
-.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n
+.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n
11 1
-.names A_18_.BLIF a_c_18__n
+.names RST_i.BLIF inst_LDS_000_INTreg.AP
1 1
-.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D
+.names dtack_sync_0_un1_n.BLIF dtack_sync_0_un0_n.BLIF inst_DTACK_SYNC.D
1- 1
-1 1
-.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
-1 1
-.names A_19_.BLIF a_c_19__n
-1 1
-.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d_2_n
-11 1
-.names A_20_.BLIF a_c_20__n
-1 1
-.names N_135_1.BLIF cpu_est_i_2__n.BLIF N_135
-11 1
-.names RST_i.BLIF inst_AS_030_000_SYNC.AP
-1 1
-.names A_21_.BLIF a_c_21__n
-1 1
-.names state_machine_un13_clk_000_d_2_n.BLIF state_machine_un13_clk_000_d_2_i_n
+.names DTACK_c.BLIF DTACK_i
0 1
-.names A_22_.BLIF a_c_22__n
-1 1
-.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_126_i
-11 1
-.names A_23_.BLIF a_c_23__n
-1 1
-.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_125_i
-11 1
-.names A_24_.BLIF a_c_24__n
-1 1
-.names N_131_i.BLIF N_132_i.BLIF N_122_i
-11 1
-.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C
-1 1
-.names A_25_.BLIF a_c_25__n
-1 1
-.names N_126_i.BLIF cpu_est_i_2__n.BLIF N_134
-11 1
-.names A_26_.BLIF a_c_26__n
-1 1
-.names N_126.BLIF cpu_est_3_reg.BLIF N_133
-11 1
-.names RST_i.BLIF inst_AS_000_INTreg.AP
-1 1
-.names A_27_.BLIF a_c_27__n
-1 1
-.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d_2_n.BLIF N_130
-11 1
-.names A_28_.BLIF a_c_28__n
-1 1
-.names cpu_est_2_.BLIF cpu_est_i_2__n
+.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n
0 1
-.names A_29_.BLIF a_c_29__n
-1 1
-.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_128
+.names N_124.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n
11 1
-.names A_30_.BLIF a_c_30__n
+.names CLK_OSZI_c.BLIF inst_DTACK_SYNC.C
1 1
-.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_3__un3_n
-0 1
-.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C
-1 1
-.names A_31_.BLIF a_c_31__n
-1 1
-.names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_3__un1_n
+.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
11 1
-.names CPU_SPACE.BLIF CPU_SPACE_c
-1 1
-.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n
-11 1
-.names RST_i.BLIF inst_VPA_SYNC.AP
-1 1
-.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D
+.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF inst_VMA_INTreg.D
1- 1
-1 1
-.names BG_030.BLIF BG_030_c
+.names RST_i.BLIF inst_DTACK_SYNC.AP
1 1
-.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_2__un3_n
+.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un3_n
0 1
-.names BG_000DFFSHreg.BLIF BG_000
-1 1
-.names N_122_i.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_2__un1_n
+.names N_121_i.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un1_n
11 1
-.names inst_BGACK_030_INTreg.BLIF BGACK_030
-1 1
.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n
11 1
-.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C
-1 1
-.names BGACK_000.BLIF BGACK_000_c
+.names AS_030.BLIF AS_030_c
1 1
.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D
1- 1
-1 1
-.names CLK_030.BLIF CLK_030_c
+.names CLK_OSZI_c.BLIF inst_FPU_CS_INTreg.C
1 1
-.names DS_030_c.BLIF DS_030_i
+.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un3_n
0 1
-.names RST_i.BLIF BG_000DFFSHreg.AP
+.names DS_030.BLIF DS_030_c
1 1
-.names CLK_000.BLIF inst_CLK_000_D.D
-1 1
-.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
-0 1
-.names CLK_OSZI.BLIF CLK_OSZI_c
-1 1
-.names CLK_030_c.BLIF CLK_030_i
-0 1
-.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
-1 1
-.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n
+.names ipl_c_0__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un1_n
11 1
-.names CLK_OUT_INTreg.BLIF CLK_EXP
+.names RST_i.BLIF inst_FPU_CS_INTreg.AP
1 1
-.names BGACK_000_c.BLIF clk_un4_clk_000_dd_i_n.BLIF state_machine_un6_bgack_000_0_n
-11 1
-.names CLK_OSZI_c.BLIF inst_DTACK_DMA.C
-1 1
-.names inst_FPU_CS_INTreg.BLIF FPU_CS
-1 1
-.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_97
-11 1
-.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_
-1 1
-.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
-0 1
-.names RST_i.BLIF inst_DTACK_DMA.AP
-1 1
-.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
-1 1
-.names N_92.BLIF sm_amiga_i_6__n.BLIF N_100
-11 1
-.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
-1 1
-.names N_112.BLIF SM_AMIGA_6_.BLIF N_102
-11 1
-.names IPL_0_.BLIF ipl_c_0__n
-1 1
-.names inst_CLK_000_DD.BLIF CLK_000_DD_i
-0 1
-.names IPL_1_.BLIF ipl_c_1__n
-1 1
-.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un4_clk_000_dd_n
-11 1
-.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C
-1 1
-.names IPL_2_.BLIF ipl_c_2__n
-1 1
-.names AS_030_000_SYNC_i.BLIF clk_un4_clk_000_dd_n.BLIF N_112
-11 1
-.names N_100_i.BLIF N_112_i.BLIF SM_AMIGA_6_.D
-11 1
-.names RST_i.BLIF inst_UDS_000_INTreg.AP
-1 1
-.names CLK_000_D_i.BLIF SM_AMIGA_7_.BLIF N_92_0
-11 1
-.names N_125.BLIF cpu_est_i_0__n.BLIF N_127
-11 1
-.names vcc_n_n.BLIF AVEC
-1 1
-.names N_125_i.BLIF cpu_est_0_.BLIF N_129
-11 1
-.names CLK_OSZI_c.BLIF CLK_CNT_0_.C
-1 1
-.names cpu_est_3_reg.BLIF E
-1 1
-.names a_c_16__n.BLIF a_i_16__n
-0 1
-.names VPA.BLIF inst_VPA_D.D
-1 1
-.names a_c_18__n.BLIF a_i_18__n
-0 1
-.names inst_VMA_INTreg.BLIF VMA
-1 1
-.names a_c_19__n.BLIF a_i_19__n
-0 1
-.names RST.BLIF RST_c
-1 1
-.names a_c_24__n.BLIF a_i_24__n
-0 1
-.names CLK_OSZI_c.BLIF inst_VPA_D.C
-1 1
-.names RESETDFFreg.BLIF RESET
-1 1
-.names a_c_25__n.BLIF a_i_25__n
-0 1
-.names RW.BLIF RW_c
-1 1
-.names a_c_26__n.BLIF a_i_26__n
-0 1
-.names FC_0_.BLIF fc_c_0__n
-1 1
-.names a_c_27__n.BLIF a_i_27__n
-0 1
-.names FC_1_.BLIF fc_c_1__n
-1 1
-.names a_c_28__n.BLIF a_i_28__n
-0 1
-.names CLK_OSZI_c.BLIF inst_CLK_000_D.C
-1 1
-.names gnd_n_n.BLIF AMIGA_BUS_ENABLE
-1 1
-.names a_c_29__n.BLIF a_i_29__n
-0 1
-.names RW_i.BLIF AMIGA_BUS_DATA_DIR
-1 1
-.names a_c_30__n.BLIF a_i_30__n
-0 1
-.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW
-1 1
-.names a_c_31__n.BLIF a_i_31__n
-0 1
-.names RST_c.BLIF RESETDFFreg.D
-1 1
-.names state_machine_un13_as_000_int_n.BLIF inst_DTACK_DMA.D
-0 1
-.names cpu_est_2_.BLIF cpu_est_i_1__n.BLIF state_machine_un8_clk_000_d_2_n
-11 1
-.names RST_c.BLIF RST_i
-0 1
-.names CLK_OSZI_c.BLIF RESETDFFreg.C
-1 1
-.names state_machine_un8_clk_000_d_1_0_n.BLIF state_machine_un8_clk_000_d_2_n.BLIF state_machine_un8_clk_000_d_3_n
-11 1
-.names CLK_CNT_0_.BLIF CLK_CNT_0_.D
-0 1
-.names state_machine_un8_clk_000_d_3_n.BLIF cpu_est_i_3__n.BLIF state_machine_un8_clk_000_d_n
-11 1
-.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
-0 1
-.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF state_machine_un13_clk_000_d_1_0_n
-11 1
-.names CPU_SPACE_c.BLIF CPU_SPACE_i
-0 1
-.names inst_CLK_000_D.BLIF inst_CLK_000_DD.D
-1 1
-.names state_machine_un13_clk_000_d_1_n.BLIF state_machine_un13_clk_000_d_2_n.BLIF state_machine_un13_clk_000_d_2_0_n
-11 1
-.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i
-0 1
-.names state_machine_un13_clk_000_d_1_0_n.BLIF state_machine_un13_clk_000_d_2_0_n.BLIF state_machine_un13_clk_000_d_n
-11 1
-.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n
-0 1
-.names CLK_OSZI_c.BLIF inst_CLK_000_DD.C
-1 1
-.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1
-11 1
-.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n
-11 1
-.names N_135_1.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_2
-11 1
-.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
-11 1
-.names VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_3
-11 1
-.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF BG_000DFFSHreg.D
-1- 1
--1 1
-.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D
-1 1
-.names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_4
-11 1
-.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n
-0 1
-.names VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa
-11 1
-.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n
-11 1
-.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C
-1 1
-.names CLK_000_D_i.BLIF SM_AMIGA_3_.BLIF N_107_1
-11 1
-.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n
-11 1
-.names N_107_1.BLIF state_machine_un60_clk_000_d_n.BLIF N_107
-11 1
-.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D
-1- 1
--1 1
-.names CLK_000_D_i.BLIF inst_CLK_OUT_PRE.BLIF N_98_1
-11 1
-.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_1__un3_n
-0 1
-.names CLK_CNT_0_.BLIF CLK_OUT_PRE_0.X1
-1 1
-.names N_98_1.BLIF SM_AMIGA_1_.BLIF N_98
-11 1
-.names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_1__un1_n
-11 1
-.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF state_machine_un42_clk_030_n
-11 1
-.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n
-11 1
-.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_0.X2
-1 1
-.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_132_1
-11 1
-.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D
-1- 1
--1 1
-.names N_132_1.BLIF cpu_est_i_2__n.BLIF N_132
-11 1
-.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_0__un3_n
-0 1
-.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_131_1
-11 1
-.names ipl_c_0__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_0__un1_n
-11 1
-.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_0_.X1
-1 1
-.names N_131_1.BLIF state_machine_un13_clk_000_d_2_i_n.BLIF N_131
-11 1
.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
11 1
-.names inst_CLK_000_D.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0
-11 1
.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D
1- 1
-1 1
+.names SIZE_0_.BLIF size_c_0__n
+1 1
+.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un3_n
+0 1
+.names SIZE_1_.BLIF size_c_1__n
+1 1
+.names ipl_c_1__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un1_n
+11 1
+.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
+1 1
+.names A_0_.BLIF a_c_0__n
+1 1
+.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
+11 1
+.names A_16_.BLIF a_c_16__n
+1 1
+.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D
+1- 1
+-1 1
+.names RST_i.BLIF inst_AS_030_000_SYNC.AP
+1 1
+.names A_17_.BLIF a_c_17__n
+1 1
+.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un3_n
+0 1
+.names A_18_.BLIF a_c_18__n
+1 1
+.names ipl_c_2__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un1_n
+11 1
+.names A_19_.BLIF a_c_19__n
+1 1
+.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
+11 1
+.names A_20_.BLIF a_c_20__n
+1 1
+.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D
+1- 1
+-1 1
+.names CLK_OSZI_c.BLIF inst_AS_000_INTreg.C
+1 1
+.names A_21_.BLIF a_c_21__n
+1 1
+.names state_machine_un8_clk_000_d0_i_n.BLIF state_machine_un13_clk_000_d0_i_n.BLIF state_machine_un15_clk_000_d0_0_n
+11 1
+.names A_22_.BLIF a_c_22__n
+1 1
+.names state_machine_un13_clk_000_d0_1_n.BLIF state_machine_un13_clk_000_d0_1_i_n
+0 1
+.names RST_i.BLIF inst_AS_000_INTreg.AP
+1 1
+.names A_23_.BLIF a_c_23__n
+1 1
+.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF N_109
+11 1
+.names A_24_.BLIF a_c_24__n
+1 1
+.names N_92.BLIF sm_amiga_i_6__n.BLIF N_99
+11 1
+.names A_25_.BLIF a_c_25__n
+1 1
+.names N_91.BLIF sm_amiga_i_7__n.BLIF N_98
+11 1
+.names A_26_.BLIF a_c_26__n
+1 1
+.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
+0 1
+.names CLK_OSZI_c.BLIF inst_VPA_SYNC.C
+1 1
+.names A_27_.BLIF a_c_27__n
+1 1
+.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
+0 1
+.names A_28_.BLIF a_c_28__n
+1 1
+.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_96
+11 1
+.names RST_i.BLIF inst_VPA_SYNC.AP
+1 1
+.names A_29_.BLIF a_c_29__n
+1 1
+.names BGACK_000_c.BLIF clk_un4_clk_000_d1_i_n.BLIF state_machine_un6_bgack_000_0_n
+11 1
+.names A_30_.BLIF a_c_30__n
+1 1
+.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n
+0 1
+.names A_31_.BLIF a_c_31__n
+1 1
+.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n
+11 1
+.names nEXP_SPACE.BLIF nEXP_SPACE_c
+1 1
+.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n
+11 1
+.names CLK_OSZI_c.BLIF BG_000DFFSHreg.C
+1 1
+.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF inst_BGACK_030_INTreg.D
+1- 1
+-1 1
+.names BG_030.BLIF BG_030_c
+1 1
+.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1
+11 1
+.names RST_i.BLIF BG_000DFFSHreg.AP
+1 1
+.names BG_000DFFSHreg.BLIF BG_000
+1 1
+.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n
+0 1
+.names inst_BGACK_030_INTreg.BLIF BGACK_030
+1 1
+.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_3_0
+11 1
+.names BGACK_000.BLIF BGACK_000_c
+1 1
+.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n
+11 1
+.names CLK_030.BLIF CLK_030_c
+1 1
+.names CLK_030_c.BLIF CLK_030_i
+0 1
+.names CLK_OSZI_c.BLIF inst_DTACK_DMA.C
+1 1
+.names CLK_000.BLIF inst_CLK_000_D0.D
+1 1
+.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n
+11 1
+.names CLK_OSZI.BLIF CLK_OSZI_c
+1 1
+.names a_c_19__n.BLIF a_i_19__n
+0 1
+.names RST_i.BLIF inst_DTACK_DMA.AP
+1 1
+.names CLK_OUT_INTreg.BLIF CLK_DIV_OUT
+1 1
+.names a_c_18__n.BLIF a_i_18__n
+0 1
+.names CLK_OUT_INTreg.BLIF CLK_EXP
+1 1
+.names a_c_i_0__n.BLIF N_144_i.BLIF state_machine_uds_000_int_8_0_n
+11 1
+.names inst_FPU_CS_INTreg.BLIF FPU_CS
+1 1
+.names N_144_i.BLIF state_machine_un34_clk_000_d0_n.BLIF state_machine_lds_000_int_8_0_n
+11 1
+.names IPL_030DFFSH_0_reg.BLIF IPL_030_0_
+1 1
+.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
+0 1
+.names CLK_OSZI_c.BLIF inst_UDS_000_INTreg.C
+1 1
+.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
+1 1
+.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_102
+11 1
+.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
+1 1
+.names CLK_000_D0_i.BLIF N_102_i.BLIF SM_AMIGA_4_.D
+11 1
+.names RST_i.BLIF inst_UDS_000_INTreg.AP
+1 1
+.names IPL_0_.BLIF ipl_c_0__n
+1 1
+.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i
+0 1
+.names IPL_1_.BLIF ipl_c_1__n
+1 1
+.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i
+0 1
+.names IPL_2_.BLIF ipl_c_2__n
+1 1
+.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_144
+11 1
+.names DS_030_c.BLIF DS_030_i
+0 1
+.names CLK_OSZI_c.BLIF CLK_CNT_0_.C
+1 1
+.names CLK_000_D0_i.BLIF SM_AMIGA_7_.BLIF N_92_0
+11 1
+.names N_99_i.BLIF N_111_i.BLIF SM_AMIGA_6_.D
+11 1
+.names vcc_n_n.BLIF AVEC
+1 1
+.names inst_CLK_000_D0.BLIF N_98_i.BLIF SM_AMIGA_7_.D
+11 1
+.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
+0 1
+.names CLK_OSZI_c.BLIF inst_VPA_D.C
+1 1
+.names cpu_est_3_reg.BLIF E
+1 1
+.names AS_030_000_SYNC_i.BLIF clk_un4_clk_000_d1_n.BLIF N_111
+11 1
+.names VPA.BLIF inst_VPA_D.D
+1 1
+.names N_111.BLIF SM_AMIGA_6_.BLIF N_101
+11 1
+.names inst_VMA_INTreg.BLIF VMA
+1 1
+.names a_c_24__n.BLIF a_i_24__n
+0 1
+.names RST.BLIF RST_c
+1 1
+.names a_c_25__n.BLIF a_i_25__n
+0 1
+.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C
+1 1
+.names RESETDFFreg.BLIF RESET
+1 1
+.names a_c_26__n.BLIF a_i_26__n
+0 1
+.names RW.BLIF RW_c
+1 1
+.names a_c_27__n.BLIF a_i_27__n
+0 1
+.names FC_0_.BLIF fc_c_0__n
+1 1
+.names a_c_28__n.BLIF a_i_28__n
+0 1
+.names RST_c.BLIF RESETDFFreg.D
+1 1
+.names FC_1_.BLIF fc_c_1__n
+1 1
+.names a_c_29__n.BLIF a_i_29__n
+0 1
+.names nEXP_SPACE_i.BLIF AMIGA_BUS_ENABLE
+1 1
+.names a_c_30__n.BLIF a_i_30__n
+0 1
+.names CLK_OSZI_c.BLIF RESETDFFreg.C
+1 1
+.names RW_i.BLIF AMIGA_BUS_DATA_DIR
+1 1
+.names a_c_31__n.BLIF a_i_31__n
+0 1
+.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW
+1 1
+.names N_97.BLIF N_97_i
+0 1
+.names AS_030_i.BLIF N_97_i.BLIF DSACK_INT_1_sqmuxa
+11 1
+.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
+1 1
+.names state_machine_un8_clk_000_d0_4_n.BLIF state_machine_un8_clk_000_d0_3_n.BLIF state_machine_un8_clk_000_d0_n
+11 1
+.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i
+0 1
+.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF state_machine_un13_clk_000_d0_1_0_n
+11 1
+.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1
+11 1
+.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C
+1 1
+.names state_machine_un13_clk_000_d0_1_n.BLIF state_machine_un13_clk_000_d0_2_n.BLIF state_machine_un13_clk_000_d0_2_0_n
+11 1
+.names AS_030_i.BLIF N_144.BLIF un1_as_030_4
+11 1
+.names state_machine_un13_clk_000_d0_1_0_n.BLIF state_machine_un13_clk_000_d0_2_0_n.BLIF state_machine_un13_clk_000_d0_n
+11 1
+.names state_machine_un13_as_000_int_n.BLIF inst_DTACK_DMA.D
+0 1
+.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1
+11 1
+.names RST_c.BLIF RST_i
+0 1
+.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D
+1 1
+.names N_134_1.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_2
+11 1
+.names CLK_CNT_0_.BLIF CLK_CNT_0_.D
+0 1
+.names VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_3
+11 1
+.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF state_machine_un60_clk_000_d0_i_n
+11 1
+.names CLK_OSZI_c.BLIF CLK_OUT_INTreg.C
+1 1
+.names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_4
+11 1
+.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
+0 1
+.names VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa
+11 1
+.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i
+0 1
+.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_106_1
+11 1
+.names un1_as_030_4.BLIF uds_000_int_0_un3_n
+0 1
+.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_0_.X1
+1 1
+.names N_106_1.BLIF state_machine_un60_clk_000_d0_n.BLIF N_106
+11 1
+.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n
+11 1
+.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n
+11 1
+.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n
+11 1
.names cpu_est_0_.BLIF cpu_est_0_0_.X2
1 1
-.names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2
+.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n
11 1
-.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_1__un3_n
+.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF inst_UDS_000_INTreg.D
+1- 1
+-1 1
+.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF state_machine_un42_clk_030_4_n
+11 1
+.names un1_as_030_4.BLIF lds_000_int_0_un3_n
0 1
-.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF UDS_000_INT_0_sqmuxa
+.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF state_machine_un42_clk_030_5_n
11 1
-.names ipl_c_1__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_1__un1_n
+.names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n
11 1
-.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1
+.names CLK_CNT_0_.BLIF CLK_OUT_PRE_0.X1
+1 1
+.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF state_machine_un42_clk_030_n
11 1
-.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
+.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n
+11 1
+.names DTACK_i.BLIF inst_VPA_D.BLIF DTACK_SYNC_1_sqmuxa_1_0
+11 1
+.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF inst_LDS_000_INTreg.D
+1- 1
+-1 1
+.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_0.X2
+1 1
+.names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa
+11 1
+.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n
+0 1
+.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_130_1
+11 1
+.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n
+11 1
+.names N_130_1.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF N_130
+11 1
+.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n
11 1
.names CLK_OUT_PRE_0.BLIF inst_CLK_OUT_PRE.D
1 1
-.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2
+.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_131_1
11 1
-.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF IPL_030DFFSH_1_reg.D
+.names vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF inst_VPA_SYNC.D
1- 1
-1 1
.names cpu_est_0_0_.BLIF cpu_est_0_.D
1 1
-.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF UDS_000_INT_0_sqmuxa_1_3
+.names N_131_1.BLIF cpu_est_i_2__n.BLIF N_131
11 1
-.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_2__un3_n
+.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n
0 1
-.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un4_clk_000_dd_n.BLIF UDS_000_INT_0_sqmuxa_1
+.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF state_machine_un8_clk_000_d0_1_n
11 1
-.names ipl_c_2__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_2__un1_n
+.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n
11 1
-.names DTACK_i.BLIF inst_VPA_D.BLIF DTACK_SYNC_1_sqmuxa_1_0
+.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d0_2_n
11 1
-.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
+.names N_97_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n
11 1
-.names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF DTACK_SYNC_1_sqmuxa
+.names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d0_3_n
11 1
-.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D
+.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D
1- 1
-1 1
-.names state_machine_un8_clk_000_d_1_n.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d_1_0_n
-11 1
-.names gnd_n_n
-.names N_168_5.BLIF N_168_6.BLIF N_168
+.names state_machine_un8_clk_000_d0_1_n.BLIF state_machine_un8_clk_000_d0_2_n.BLIF state_machine_un8_clk_000_d0_4_n
11 1
.names vcc_n_n
1
-.names a_c_20__n.BLIF a_c_21__n.BLIF N_171_1
+.names N_167_3.BLIF N_167_4.BLIF N_167_6
+11 1
+.names gnd_n_n
+.names N_167_5.BLIF N_167_6.BLIF N_167
11 1
.names A_15_.BLIF a_15__n
1 1
-.names a_c_22__n.BLIF a_c_23__n.BLIF N_171_2
+.names a_c_20__n.BLIF a_c_21__n.BLIF N_170_1
11 1
.names A_14_.BLIF a_14__n
1 1
-.names N_171_1.BLIF N_171_2.BLIF N_171
+.names a_c_22__n.BLIF a_c_23__n.BLIF N_170_2
11 1
.names A_13_.BLIF a_13__n
1 1
-.names AS_030_c.BLIF BG_030_c_i.BLIF un1_bg_030_0_1
+.names N_170_1.BLIF N_170_2.BLIF N_170
11 1
.names A_12_.BLIF a_12__n
1 1
-.names CPU_SPACE_i.BLIF N_97_i.BLIF un1_bg_030_0_2
+.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1
11 1
.names A_11_.BLIF a_11__n
1 1
-.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0
+.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2
11 1
.names A_10_.BLIF a_10__n
1 1
-.names N_127_i.BLIF N_128_i.BLIF clk_cpu_est_11_0_1_1__n
+.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF UDS_000_INT_0_sqmuxa_1_3
11 1
.names A_9_.BLIF a_9__n
1 1
-.names N_129_i.BLIF N_130_i.BLIF clk_cpu_est_11_0_2_1__n
+.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un4_clk_000_d1_n.BLIF UDS_000_INT_0_sqmuxa_1
11 1
.names A_8_.BLIF a_8__n
1 1
-.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF clk_cpu_est_11_0_1__n
+.names inst_CLK_000_D0.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0
11 1
.names A_7_.BLIF a_7__n
1 1
-.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n
+.names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2
11 1
.names A_6_.BLIF a_6__n
1 1
-.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n
+.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF UDS_000_INT_0_sqmuxa
11 1
.names A_5_.BLIF a_5__n
1 1
-.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n
+.names size_c_i_1__n.BLIF a_c_i_0__n.BLIF state_machine_un34_clk_000_d0_i_1_n
11 1
.names A_4_.BLIF a_4__n
1 1
-.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF state_machine_un42_clk_030_4_n
+.names state_machine_un34_clk_000_d0_i_1_n.BLIF size_c_0__n.BLIF state_machine_un34_clk_000_d0_i_n
11 1
.names A_3_.BLIF a_3__n
1 1
-.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF state_machine_un42_clk_030_5_n
+.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n
11 1
.names A_2_.BLIF a_2__n
1 1
-.names clk_un4_clk_000_dd_n.BLIF clk_un4_clk_000_dd_i_n
-0 1
+.names BG_030_c_i.BLIF N_96_i.BLIF un1_bg_030_0_1
+11 1
.names A_1_.BLIF a_1__n
1 1
-.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
-0 1
-.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n
-0 1
-.names N_135_i.BLIF N_133_i.BLIF clk_cpu_est_11_0_1_3__n
+.names AS_030_c.BLIF nEXP_SPACE_i.BLIF un1_bg_030_0_2
11 1
-.names clk_cpu_est_11_0_1_3__n.BLIF N_134_i.BLIF clk_cpu_est_11_0_3__n
+.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0
11 1
-.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un34_clk_000_d_i_1_n
-11 1
-.names state_machine_un34_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF state_machine_un34_clk_000_d_i_n
-11 1
-.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_2_1_n
+.names AS_030_i.BLIF nEXP_SPACE_c.BLIF state_machine_as_030_000_sync_3_2_1_n
11 1
.names state_machine_as_030_000_sync_3_2_1_n.BLIF state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n
11 1
-.names a_i_24__n.BLIF a_i_25__n.BLIF N_168_1
+.names N_134_i.BLIF N_132_i.BLIF clk_cpu_est_11_0_1_3__n
11 1
-.names a_i_26__n.BLIF a_i_27__n.BLIF N_168_2
+.names clk_cpu_est_11_0_1_3__n.BLIF N_133_i.BLIF clk_cpu_est_11_0_3__n
11 1
-.names a_i_28__n.BLIF a_i_29__n.BLIF N_168_3
+.names N_129_i.BLIF N_127_i.BLIF clk_cpu_est_11_0_1_1__n
11 1
-.names a_i_30__n.BLIF a_i_31__n.BLIF N_168_4
+.names N_126_i.BLIF N_128_i.BLIF clk_cpu_est_11_0_2_1__n
11 1
-.names N_168_1.BLIF N_168_2.BLIF N_168_5
+.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF clk_cpu_est_11_0_1__n
11 1
-.names N_168_3.BLIF N_168_4.BLIF N_168_6
+.names a_i_24__n.BLIF a_i_25__n.BLIF N_167_1
+11 1
+.names a_i_26__n.BLIF a_i_27__n.BLIF N_167_2
+11 1
+.names a_i_28__n.BLIF a_i_29__n.BLIF N_167_3
+11 1
+.names a_i_30__n.BLIF a_i_31__n.BLIF N_167_4
+11 1
+.names N_167_1.BLIF N_167_2.BLIF N_167_5
11 1
-.names N_134.BLIF N_134_i
-0 1
-.names N_133.BLIF N_133_i
-0 1
-.names N_135.BLIF N_135_i
-0 1
-.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n
-0 1
-.names N_130.BLIF N_130_i
-0 1
-.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n
-0 1
-.names N_128.BLIF N_128_i
-0 1
.names un1_bg_030_0.BLIF un1_bg_030
0 1
-.names N_97.BLIF N_97_i
+.names clk_un4_clk_000_d1_n.BLIF clk_un4_clk_000_d1_i_n
0 1
-.names BG_030_c.BLIF BG_030_c_i
+.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
0 1
-.names N_127.BLIF N_127_i
+.names N_98.BLIF N_98_i
0 1
-.names N_129.BLIF N_129_i
+.names N_111.BLIF N_111_i
+0 1
+.names N_99.BLIF N_99_i
0 1
.names N_92_0.BLIF N_92
0 1
-.names N_100.BLIF N_100_i
+.names state_machine_un34_clk_000_d0_i_n.BLIF state_machine_un34_clk_000_d0_n
0 1
-.names N_112.BLIF N_112_i
+.names a_c_0__n.BLIF a_c_i_0__n
0 1
-.names N_103.BLIF N_103_i
+.names size_c_1__n.BLIF size_c_i_1__n
0 1
-.names state_machine_un60_clk_000_d_i_n.BLIF state_machine_un60_clk_000_d_n
+.names N_102.BLIF N_102_i
0 1
+.names N_144.BLIF N_144_i
+0 1
+.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n
+0 1
+.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n
+0 1
+.names state_machine_un60_clk_000_d0_i_n.BLIF state_machine_un60_clk_000_d0_n
+0 1
+.names N_124_i.BLIF N_124
+0 1
+.names N_130.BLIF N_130_i
+0 1
+.names N_131.BLIF N_131_i
+0 1
+.names N_91_0.BLIF N_91
+0 1
+.names N_109.BLIF N_109_i
+0 1
+.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D
+0 1
+.names state_machine_un8_clk_000_d0_n.BLIF state_machine_un8_clk_000_d0_i_n
+0 1
+.names state_machine_un13_clk_000_d0_n.BLIF state_machine_un13_clk_000_d0_i_n
+0 1
+.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n
+0 1
+.names BG_030_c.BLIF BG_030_c_i
+0 1
+.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n
+0 1
+.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C
+1 1
.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n
0 1
.names un1_as_030_3_0.BLIF un1_as_030_3
0 1
-.names N_145.BLIF N_145_i
-0 1
-.names a_c_0__n.BLIF a_c_i_0__n
-0 1
-.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n
-0 1
-.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n
-0 1
-.names state_machine_as_030_000_sync_3_2_n.BLIF state_machine_as_030_000_sync_3_n
-0 1
-.names size_c_1__n.BLIF size_c_i_1__n
-0 1
-.names state_machine_un34_clk_000_d_i_n.BLIF state_machine_un34_clk_000_d_n
-0 1
-.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C
-1 1
-.names N_131.BLIF N_131_i
-0 1
-.names N_132.BLIF N_132_i
-0 1
.names RST_i.BLIF SM_AMIGA_3_.AR
1 1
-.names N_125_i.BLIF N_125
+.names state_machine_as_030_000_sync_3_2_n.BLIF state_machine_as_030_000_sync_3_n
0 1
-.names N_126_i.BLIF N_126
-0 1
-.names N_106.BLIF N_106_i
-0 1
-.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D
-0 1
-.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C
-1 1
-.names N_108.BLIF N_108_i
-0 1
-.names N_109.BLIF N_109_i
-0 1
-.names RST_i.BLIF SM_AMIGA_2_.AR
-1 1
-.names N_110.BLIF N_110_i
-0 1
-.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D
-0 1
-.names N_91_0.BLIF N_91
-0 1
-.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i
-0 1
-.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C
-1 1
-.names N_94_0.BLIF N_94
-0 1
-.names state_machine_un8_clk_000_d_n.BLIF state_machine_un8_clk_000_d_i_n
-0 1
-.names RST_i.BLIF SM_AMIGA_1_.AR
-1 1
-.names state_machine_un13_clk_000_d_n.BLIF state_machine_un13_clk_000_d_i_n
-0 1
-.names state_machine_un15_clk_000_d_0_n.BLIF state_machine_un15_clk_000_d_n
-0 1
-.names N_93_0.BLIF N_93
-0 1
-.names N_104.BLIF N_104_i
-0 1
-.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C
-1 1
-.names N_105.BLIF N_105_i
-0 1
-.names N_99.BLIF N_99_i
-0 1
-.names RST_i.BLIF SM_AMIGA_0_.AR
-1 1
-.names N_101.BLIF N_101_i
-0 1
-.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D
+.names N_96.BLIF N_96_i
0 1
.names N_107.BLIF N_107_i
0 1
-.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_106
-11 1
+.names N_108.BLIF N_108_i
+0 1
+.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C
+1 1
+.names sm_amiga_ns_0_6__n.BLIF SM_AMIGA_1_.D
+0 1
+.names N_90_i.BLIF N_90
+0 1
+.names RST_i.BLIF SM_AMIGA_2_.AR
+1 1
+.names N_93_0.BLIF N_93
+0 1
+.names N_128.BLIF N_128_i
+0 1
+.names N_126.BLIF N_126_i
+0 1
+.names N_127.BLIF N_127_i
+0 1
+.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C
+1 1
+.names N_129.BLIF N_129_i
+0 1
+.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n
+0 1
+.names RST_i.BLIF SM_AMIGA_1_.AR
+1 1
+.names N_133.BLIF N_133_i
+0 1
+.names N_132.BLIF N_132_i
+0 1
+.names N_134.BLIF N_134_i
+0 1
+.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n
+0 1
+.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C
+1 1
+.names N_125_i.BLIF N_125
+0 1
+.names N_100.BLIF N_100_i
+0 1
+.names RST_i.BLIF SM_AMIGA_0_.AR
+1 1
+.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D
+0 1
+.names N_103.BLIF N_103_i
+0 1
+.names N_104.BLIF N_104_i
+0 1
+.names N_106.BLIF N_106_i
+0 1
.names CLK_OSZI_c.BLIF IPL_030DFFSH_0_reg.C
1 1
-.names inst_CLK_000_D.BLIF SM_AMIGA_5_.BLIF N_101
-11 1
-.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
+.names N_105.BLIF N_105_i
+0 1
+.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D
0 1
.names RST_i.BLIF IPL_030DFFSH_0_reg.AP
1 1
-.names N_91.BLIF sm_amiga_i_7__n.BLIF N_99
-11 1
-.names AS_030_c.BLIF AS_030_i
-0 1
-.names AS_030_i.BLIF N_102_i.BLIF AS_000_INT_1_sqmuxa
-11 1
.names inst_AS_000_INTreg.BLIF AS_000_INT_i
0 1
-.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C
-1 1
.names dsack_c_1__n.BLIF dsack_i_1__n
0 1
.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un13_as_000_int_n
11 1
+.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un3_n
+0 1
+.names CLK_OSZI_c.BLIF IPL_030DFFSH_1_reg.C
+1 1
+.names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un1_n
+11 1
+.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n
+11 1
.names RST_i.BLIF IPL_030DFFSH_1_reg.AP
1 1
-.names N_102.BLIF N_102_i
+.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_reg.D
+1- 1
+-1 1
+.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un3_n
0 1
-.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n
+.names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un1_n
+11 1
+.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n
+11 1
+.names CLK_OSZI_c.BLIF IPL_030DFFSH_2_reg.C
+1 1
+.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D
+1- 1
+-1 1
+.names N_101.BLIF N_101_i
0 1
+.names RST_i.BLIF IPL_030DFFSH_2_reg.AP
+1 1
.end
diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1
index 9c85ea1..29ce7d1 100644
--- a/Logic/BUS68030.bl1
+++ b/Logic/BUS68030.bl1
@@ -1,200 +1,199 @@
#$ TOOL ispLEVER Classic 1.7.00.05.28.13
-#$ DATE Thu May 15 23:02:46 2014
+#$ DATE Fri May 16 17:07:08 2014
#$ MODULE bus68030
-#$ PINS 74 A_21_ A_20_ SIZE_1_ A_19_ A_18_ A_31_ A_17_ A_16_ IPL_030_2_ A_15_ A_14_ \
-# IPL_2_ A_13_ A_12_ DSACK_1_ A_11_ A_10_ FC_1_ A_9_ AS_030 A_8_ AS_000 A_7_ DS_030 A_6_ \
-# UDS_000 A_5_ LDS_000 A_4_ CPU_SPACE A_3_ BERR A_2_ BG_030 A_1_ BG_000 A_0_ BGACK_030 \
-# IPL_030_1_ BGACK_000 IPL_030_0_ CLK_030 IPL_1_ CLK_000 IPL_0_ CLK_OSZI DSACK_0_ \
-# CLK_DIV_OUT FC_0_ CLK_EXP FPU_CS DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW \
-# AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ \
-# A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
-#$ NODES 344 IPL_030DFFSH_1_reg IPL_030DFFSH_2_reg ipl_c_0__n ipl_c_1__n \
-# inst_BGACK_030_INTreg inst_FPU_CS_INTreg ipl_c_2__n cpu_est_3_reg inst_VMA_INTreg \
-# gnd_n_n dsack_c_1__n cpu_est_0_ cpu_est_1_ DTACK_c inst_AS_000_INTreg \
-# inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D inst_VPA_SYNC inst_CLK_000_D \
-# inst_CLK_000_DD inst_CLK_OUT_PRE RST_c vcc_n_n cpu_est_2_ RESETDFFreg CLK_CNT_0_ \
-# SM_AMIGA_6_ RW_c SM_AMIGA_7_ inst_UDS_000_INTreg fc_c_0__n inst_LDS_000_INTreg \
-# state_machine_un1_clk_030_n fc_c_1__n SM_AMIGA_1_ DSACK_INT_1_ inst_DTACK_DMA \
-# SM_AMIGA_4_ state_machine_un6_bgack_000_n SM_AMIGA_3_ N_99_i \
-# state_machine_un13_as_000_int_n un1_bg_030 N_101_i SM_AMIGA_5_ sm_amiga_ns_0_2__n \
-# SM_AMIGA_2_ N_107_i SM_AMIGA_0_ N_106_i sm_amiga_ns_0_5__n N_108_i N_109_i N_110_i \
-# sm_amiga_ns_0_7__n N_91_0 CLK_OUT_PRE_i N_94_0 state_machine_un8_clk_000_d_i_n \
-# state_machine_un13_clk_000_d_i_n cpu_est_0_0_ state_machine_un15_clk_000_d_0_n \
-# N_93_0 N_104_i N_105_i N_103_i CLK_OUT_PRE_0 state_machine_un60_clk_000_d_i_n \
-# state_machine_un17_clk_030_0_n un1_as_030_3_0 N_145_i clk_un4_clk_000_dd_n \
-# a_c_i_0__n clk_cpu_est_11_1__n state_machine_uds_000_int_8_0_n \
-# state_machine_un42_clk_030_n state_machine_lds_000_int_8_0_n N_102 \
-# state_machine_as_030_000_sync_3_2_n N_98 size_c_i_1__n N_97 \
-# state_machine_un34_clk_000_d_i_n N_100 N_131_i N_92 N_132_i N_112 N_122_i N_127 \
-# N_125_i N_125 N_126_i N_128 N_134_i N_129 N_133_i N_130 N_135_i N_168 \
-# clk_cpu_est_11_0_3__n N_171 N_130_i N_135_1 clk_cpu_est_11_0_1__n \
-# state_machine_un13_clk_000_d_2_n N_128_i clk_cpu_est_11_3__n un1_bg_030_0 N_135 \
-# N_97_i N_133 BG_030_c_i N_134 N_127_i N_132 N_129_i N_131 N_92_0 N_126 N_100_i \
-# state_machine_un34_clk_000_d_n N_112_i UDS_000_INT_0_sqmuxa \
-# UDS_000_INT_0_sqmuxa_1 clk_un4_clk_000_dd_i_n state_machine_as_030_000_sync_3_n \
-# state_machine_un6_bgack_000_0_n N_145 state_machine_un1_clk_030_0_n \
-# state_machine_lds_000_int_8_n clk_cpu_est_11_0_1_3__n \
-# state_machine_uds_000_int_8_n state_machine_un34_clk_000_d_i_1_n un1_as_030_4 \
-# state_machine_as_030_000_sync_3_2_1_n un1_as_030_3 N_168_1 DSACK_INT_1_sqmuxa \
-# N_168_2 state_machine_un17_clk_030_n N_168_3 state_machine_un60_clk_000_d_n \
-# N_168_4 DTACK_SYNC_1_sqmuxa N_168_5 DTACK_SYNC_1_sqmuxa_1 N_168_6 VPA_SYNC_1_sqmuxa \
-# N_171_1 VPA_SYNC_1_sqmuxa_1 N_171_2 N_103 un1_bg_030_0_1 N_104 un1_bg_030_0_2 N_93 \
-# clk_cpu_est_11_0_1_1__n N_105 clk_cpu_est_11_0_2_1__n VPA_SYNC_1_sqmuxa_1_0 \
-# state_machine_un42_clk_030_1_n state_machine_un15_clk_000_d_n \
-# state_machine_un42_clk_030_2_n state_machine_un13_clk_000_d_n \
-# state_machine_un42_clk_030_3_n state_machine_un8_clk_000_d_n \
-# state_machine_un42_clk_030_4_n state_machine_un8_clk_000_d_1_n \
-# state_machine_un42_clk_030_5_n state_machine_un13_clk_000_d_1_n N_132_1 N_107 \
-# N_131_1 N_94 UDS_000_INT_0_sqmuxa_1_0 N_91 UDS_000_INT_0_sqmuxa_2 N_110 \
-# UDS_000_INT_0_sqmuxa_1_1 N_108 UDS_000_INT_0_sqmuxa_1_2 N_109 \
-# UDS_000_INT_0_sqmuxa_1_3 N_106 DTACK_SYNC_1_sqmuxa_1_0 N_101 \
-# state_machine_un8_clk_000_d_1_0_n N_99 state_machine_un8_clk_000_d_2_n \
-# AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d_3_n RW_i \
-# state_machine_un13_clk_000_d_1_0_n N_102_i state_machine_un13_clk_000_d_2_0_n \
-# AS_000_INT_i VPA_SYNC_1_sqmuxa_1_1 dsack_i_1__n VPA_SYNC_1_sqmuxa_2 AS_030_i \
-# VPA_SYNC_1_sqmuxa_3 sm_amiga_i_7__n VPA_SYNC_1_sqmuxa_4 CLK_000_D_i N_107_1 \
-# sm_amiga_i_2__n N_98_1 sm_amiga_i_1__n as_000_int_0_un3_n \
-# state_machine_un13_clk_000_d_1_i_n as_000_int_0_un1_n VPA_D_i as_000_int_0_un0_n \
-# VMA_INT_i vma_int_0_un3_n cpu_est_i_0__n vma_int_0_un1_n cpu_est_i_1__n \
-# vma_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n \
-# state_machine_un8_clk_000_d_1_i_0_n uds_000_int_0_un1_n DTACK_i \
-# uds_000_int_0_un0_n sm_amiga_i_3__n dtack_sync_0_un3_n sm_amiga_i_4__n \
-# dtack_sync_0_un1_n sm_amiga_i_5__n dtack_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i \
-# vpa_sync_0_un3_n VPA_SYNC_1_sqmuxa_i vpa_sync_0_un1_n N_98_i vpa_sync_0_un0_n \
-# state_machine_un42_clk_030_i_n dsack_int_0_1__un3_n UDS_000_INT_0_sqmuxa_1_i \
-# dsack_int_0_1__un1_n UDS_000_INT_0_sqmuxa_i dsack_int_0_1__un0_n \
-# AS_030_000_SYNC_i as_030_000_sync_0_un3_n DS_030_i as_030_000_sync_0_un1_n \
-# cpu_est_i_2__n as_030_000_sync_0_un0_n state_machine_un13_clk_000_d_2_i_n \
-# fpu_cs_int_0_un3_n CLK_000_DD_i fpu_cs_int_0_un1_n sm_amiga_i_6__n \
-# fpu_cs_int_0_un0_n CLK_030_i lds_000_int_0_un3_n a_i_30__n lds_000_int_0_un1_n \
-# a_i_31__n lds_000_int_0_un0_n a_i_28__n cpu_est_0_3__un3_n a_i_29__n \
-# cpu_est_0_3__un1_n a_i_26__n cpu_est_0_3__un0_n a_i_27__n cpu_est_0_2__un3_n \
-# a_i_24__n cpu_est_0_2__un1_n a_i_25__n cpu_est_0_2__un0_n a_i_19__n bg_000_0_un3_n \
-# a_i_16__n bg_000_0_un1_n a_i_18__n bg_000_0_un0_n bgack_030_int_0_un3_n RST_i \
-# bgack_030_int_0_un1_n bgack_030_int_0_un0_n FPU_CS_INT_i cpu_est_0_1__un3_n \
-# CPU_SPACE_i cpu_est_0_1__un1_n BGACK_030_INT_i cpu_est_0_1__un0_n AS_030_c \
-# ipl_030_0_0__un3_n ipl_030_0_0__un1_n ipl_030_0_0__un0_n DS_030_c \
-# ipl_030_0_1__un3_n ipl_030_0_1__un1_n ipl_030_0_1__un0_n ipl_030_0_2__un3_n \
-# size_c_0__n ipl_030_0_2__un1_n ipl_030_0_2__un0_n size_c_1__n a_15__n a_c_0__n \
-# a_14__n a_13__n a_12__n a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n \
+#$ PINS 74 A_17_ A_16_ SIZE_1_ A_15_ A_14_ A_31_ A_13_ A_12_ IPL_030_2_ A_11_ A_10_ \
+# IPL_2_ A_9_ A_8_ DSACK_1_ A_7_ A_6_ FC_1_ A_5_ AS_030 A_4_ AS_000 A_3_ DS_030 A_2_ UDS_000 \
+# A_1_ LDS_000 A_0_ nEXP_SPACE IPL_030_1_ BERR IPL_030_0_ BG_030 IPL_1_ BG_000 IPL_0_ \
+# BGACK_030 DSACK_0_ BGACK_000 FC_0_ CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS \
+# DTACK AVEC AVEC_EXP E VPA VMA RST RESET RW AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
+# AMIGA_BUS_ENABLE_LOW CIIN SIZE_0_ A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ \
+# A_21_ A_20_ A_19_ A_18_
+#$ NODES 340 ipl_c_0__n ipl_c_1__n ipl_c_2__n inst_BGACK_030_INTreg \
+# inst_FPU_CS_INTreg dsack_c_1__n cpu_est_3_reg inst_VMA_INTreg DTACK_c cpu_est_0_ \
+# cpu_est_1_ inst_AS_000_INTreg inst_AS_030_000_SYNC inst_DTACK_SYNC inst_VPA_D \
+# inst_VPA_SYNC inst_CLK_000_D0 RST_c inst_CLK_000_D1 inst_CLK_OUT_PRE RESETDFFreg \
+# vcc_n_n gnd_n_n RW_c cpu_est_2_ CLK_CNT_0_ fc_c_0__n SM_AMIGA_6_ SM_AMIGA_7_ fc_c_1__n \
+# inst_UDS_000_INTreg inst_LDS_000_INTreg DSACK_INT_1_ \
+# state_machine_un60_clk_000_d0_n SM_AMIGA_1_ inst_DTACK_DMA N_100_i SM_AMIGA_4_ \
+# sm_amiga_ns_0_2__n SM_AMIGA_3_ N_103_i DSACK_INT_1_sqmuxa N_104_i \
+# state_machine_un13_as_000_int_n VPA_SYNC_1_sqmuxa_1 N_106_i un1_as_030_4 N_105_i \
+# SM_AMIGA_5_ sm_amiga_ns_0_5__n SM_AMIGA_2_ N_107_i SM_AMIGA_0_ N_108_i \
+# state_machine_lds_000_int_8_n sm_amiga_ns_0_6__n state_machine_uds_000_int_8_n \
+# N_90_i N_93_0 N_128_i N_126_i N_127_i N_129_i clk_cpu_est_11_0_1__n N_133_i N_132_i \
+# N_134_i clk_cpu_est_11_0_3__n N_125_i cpu_est_0_0_ N_124_i N_130_i N_131_i N_121_i \
+# N_91_0 N_109_i sm_amiga_ns_0_7__n CLK_OUT_PRE_0 state_machine_un8_clk_000_d0_i_n \
+# state_machine_un13_clk_000_d0_i_n state_machine_un15_clk_000_d0_0_n BG_030_c_i \
+# state_machine_un1_clk_030_0_n clk_un4_clk_000_d1_n \
+# state_machine_un17_clk_030_0_n N_144 un1_as_030_3_0 N_101 \
+# state_machine_as_030_000_sync_3_2_n VPA_SYNC_1_sqmuxa N_96_i N_97 un1_bg_030_0 \
+# state_machine_un34_clk_000_d0_n clk_un4_clk_000_d1_i_n N_96 \
+# state_machine_un6_bgack_000_0_n N_102 N_98_i UDS_000_INT_0_sqmuxa \
+# UDS_000_INT_0_sqmuxa_1 N_111_i N_167 N_99_i N_170 N_92 N_92_0 N_91 \
+# state_machine_un34_clk_000_d0_i_n N_99 a_c_i_0__n N_111 size_c_i_1__n N_98 N_102_i \
+# state_machine_un6_bgack_000_n state_machine_un42_clk_030_n N_144_i \
+# DTACK_SYNC_1_sqmuxa state_machine_lds_000_int_8_0_n un1_bg_030 \
+# state_machine_uds_000_int_8_0_n state_machine_as_030_000_sync_3_n \
+# state_machine_un60_clk_000_d0_i_n DTACK_SYNC_1_sqmuxa_1 un1_bg_030_0_1 \
+# un1_as_030_3 un1_bg_030_0_2 state_machine_un17_clk_030_n \
+# state_machine_as_030_000_sync_3_2_1_n state_machine_un1_clk_030_n \
+# clk_cpu_est_11_0_1_3__n VPA_SYNC_1_sqmuxa_1_0 clk_cpu_est_11_0_1_1__n \
+# state_machine_un15_clk_000_d0_n clk_cpu_est_11_0_2_1__n \
+# state_machine_un13_clk_000_d0_n N_167_1 state_machine_un8_clk_000_d0_n N_167_2 \
+# N_109 N_167_3 state_machine_un13_clk_000_d0_1_n N_167_4 N_129 N_167_5 \
+# state_machine_un13_clk_000_d0_2_n N_167_6 N_130 N_170_1 N_131 N_170_2 N_124 \
+# UDS_000_INT_0_sqmuxa_1_1 N_125 UDS_000_INT_0_sqmuxa_1_2 N_134 \
+# UDS_000_INT_0_sqmuxa_1_3 N_134_1 UDS_000_INT_0_sqmuxa_1_0 N_106 \
+# UDS_000_INT_0_sqmuxa_2 clk_cpu_est_11_3__n state_machine_un34_clk_000_d0_i_1_n \
+# N_132 state_machine_un42_clk_030_1_n N_133 state_machine_un42_clk_030_2_n \
+# clk_cpu_est_11_1__n state_machine_un42_clk_030_3_n N_127 \
+# state_machine_un42_clk_030_4_n N_126 state_machine_un42_clk_030_5_n N_128 \
+# DTACK_SYNC_1_sqmuxa_1_0 N_93 N_130_1 N_90 N_131_1 N_107 \
+# state_machine_un8_clk_000_d0_1_n N_108 state_machine_un8_clk_000_d0_2_n N_105 \
+# state_machine_un8_clk_000_d0_3_n N_103 state_machine_un8_clk_000_d0_4_n N_104 \
+# state_machine_un13_clk_000_d0_1_0_n N_100 state_machine_un13_clk_000_d0_2_0_n \
+# AS_000_INT_1_sqmuxa VPA_SYNC_1_sqmuxa_1_1 RW_i VPA_SYNC_1_sqmuxa_2 nEXP_SPACE_i \
+# VPA_SYNC_1_sqmuxa_3 N_101_i VPA_SYNC_1_sqmuxa_4 AS_000_INT_i N_106_1 dsack_i_1__n \
+# cpu_est_0_3__un3_n AS_030_i cpu_est_0_3__un1_n CLK_000_D0_i cpu_est_0_3__un0_n \
+# sm_amiga_i_3__n cpu_est_0_1__un3_n sm_amiga_i_4__n cpu_est_0_1__un1_n CLK_000_D1_i \
+# cpu_est_0_1__un0_n cpu_est_i_0__n as_000_int_0_un3_n cpu_est_i_3__n \
+# as_000_int_0_un1_n cpu_est_i_2__n as_000_int_0_un0_n VPA_D_i bg_000_0_un3_n \
+# VMA_INT_i bg_000_0_un1_n cpu_est_i_1__n bg_000_0_un0_n \
+# state_machine_un13_clk_000_d0_2_i_n as_030_000_sync_0_un3_n \
+# state_machine_un13_clk_000_d0_1_i_n as_030_000_sync_0_un1_n DTACK_i \
+# as_030_000_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i fpu_cs_int_0_un3_n a_i_18__n \
+# fpu_cs_int_0_un1_n a_i_16__n fpu_cs_int_0_un0_n a_i_19__n dtack_sync_0_un3_n \
+# CLK_030_i dtack_sync_0_un1_n state_machine_un42_clk_030_i_n dtack_sync_0_un0_n \
+# sm_amiga_i_6__n vma_int_0_un3_n sm_amiga_i_7__n vma_int_0_un1_n AS_030_000_SYNC_i \
+# vma_int_0_un0_n DS_030_i cpu_est_0_2__un3_n UDS_000_INT_0_sqmuxa_1_i \
+# cpu_est_0_2__un1_n UDS_000_INT_0_sqmuxa_i cpu_est_0_2__un0_n sm_amiga_i_5__n \
+# ipl_030_0_0__un3_n VPA_SYNC_1_sqmuxa_i ipl_030_0_0__un1_n N_97_i \
+# ipl_030_0_0__un0_n a_i_30__n ipl_030_0_1__un3_n a_i_31__n ipl_030_0_1__un1_n \
+# a_i_28__n ipl_030_0_1__un0_n a_i_29__n ipl_030_0_2__un3_n a_i_26__n \
+# ipl_030_0_2__un1_n a_i_27__n ipl_030_0_2__un0_n a_i_24__n bgack_030_int_0_un3_n \
+# a_i_25__n bgack_030_int_0_un1_n bgack_030_int_0_un0_n RST_i uds_000_int_0_un3_n \
+# uds_000_int_0_un1_n FPU_CS_INT_i uds_000_int_0_un0_n BGACK_030_INT_i \
+# lds_000_int_0_un3_n AS_030_c lds_000_int_0_un1_n lds_000_int_0_un0_n \
+# vpa_sync_0_un3_n DS_030_c vpa_sync_0_un1_n vpa_sync_0_un0_n dsack_int_0_1__un3_n \
+# dsack_int_0_1__un1_n size_c_0__n dsack_int_0_1__un0_n a_15__n size_c_1__n a_14__n \
+# a_c_0__n a_13__n a_12__n a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n \
# a_c_17__n a_4__n a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n \
# a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n a_c_30__n \
-# a_c_31__n CPU_SPACE_c BG_030_c BG_000DFFSHreg BGACK_000_c CLK_030_c CLK_OSZI_c \
-# CLK_OUT_INTreg IPL_030DFFSH_0_reg
+# a_c_31__n nEXP_SPACE_c BG_030_c BG_000DFFSHreg BGACK_000_c CLK_030_c CLK_OSZI_c \
+# CLK_OUT_INTreg IPL_030DFFSH_0_reg IPL_030DFFSH_1_reg IPL_030DFFSH_2_reg
.model bus68030
.inputs SIZE_1_.BLIF A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF AS_030.BLIF DS_030.BLIF \
-CPU_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \
+nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \
CLK_OSZI.BLIF VPA.BLIF RST.BLIF RW.BLIF SIZE_0_.BLIF A_30_.BLIF A_29_.BLIF \
A_28_.BLIF A_27_.BLIF A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF \
A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF \
A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF \
A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF A_1_.BLIF \
A_0_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF DSACK_1_.BLIF DTACK.BLIF \
-DSACK_0_.BLIF IPL_030DFFSH_1_reg.BLIF IPL_030DFFSH_2_reg.BLIF ipl_c_0__n.BLIF \
-ipl_c_1__n.BLIF inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF \
-ipl_c_2__n.BLIF cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF gnd_n_n.BLIF \
-dsack_c_1__n.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF DTACK_c.BLIF \
-inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF inst_DTACK_SYNC.BLIF \
-inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D.BLIF inst_CLK_000_DD.BLIF \
-inst_CLK_OUT_PRE.BLIF RST_c.BLIF vcc_n_n.BLIF cpu_est_2_.BLIF RESETDFFreg.BLIF \
-CLK_CNT_0_.BLIF SM_AMIGA_6_.BLIF RW_c.BLIF SM_AMIGA_7_.BLIF \
-inst_UDS_000_INTreg.BLIF fc_c_0__n.BLIF inst_LDS_000_INTreg.BLIF \
-state_machine_un1_clk_030_n.BLIF fc_c_1__n.BLIF SM_AMIGA_1_.BLIF \
-DSACK_INT_1_.BLIF inst_DTACK_DMA.BLIF SM_AMIGA_4_.BLIF \
-state_machine_un6_bgack_000_n.BLIF SM_AMIGA_3_.BLIF N_99_i.BLIF \
-state_machine_un13_as_000_int_n.BLIF un1_bg_030.BLIF N_101_i.BLIF \
-SM_AMIGA_5_.BLIF sm_amiga_ns_0_2__n.BLIF SM_AMIGA_2_.BLIF N_107_i.BLIF \
-SM_AMIGA_0_.BLIF N_106_i.BLIF sm_amiga_ns_0_5__n.BLIF N_108_i.BLIF \
-N_109_i.BLIF N_110_i.BLIF sm_amiga_ns_0_7__n.BLIF N_91_0.BLIF \
-CLK_OUT_PRE_i.BLIF N_94_0.BLIF state_machine_un8_clk_000_d_i_n.BLIF \
-state_machine_un13_clk_000_d_i_n.BLIF cpu_est_0_0_.BLIF \
-state_machine_un15_clk_000_d_0_n.BLIF N_93_0.BLIF N_104_i.BLIF N_105_i.BLIF \
-N_103_i.BLIF CLK_OUT_PRE_0.BLIF state_machine_un60_clk_000_d_i_n.BLIF \
-state_machine_un17_clk_030_0_n.BLIF un1_as_030_3_0.BLIF N_145_i.BLIF \
-clk_un4_clk_000_dd_n.BLIF a_c_i_0__n.BLIF clk_cpu_est_11_1__n.BLIF \
-state_machine_uds_000_int_8_0_n.BLIF state_machine_un42_clk_030_n.BLIF \
-state_machine_lds_000_int_8_0_n.BLIF N_102.BLIF \
-state_machine_as_030_000_sync_3_2_n.BLIF N_98.BLIF size_c_i_1__n.BLIF \
-N_97.BLIF state_machine_un34_clk_000_d_i_n.BLIF N_100.BLIF N_131_i.BLIF \
-N_92.BLIF N_132_i.BLIF N_112.BLIF N_122_i.BLIF N_127.BLIF N_125_i.BLIF \
-N_125.BLIF N_126_i.BLIF N_128.BLIF N_134_i.BLIF N_129.BLIF N_133_i.BLIF \
-N_130.BLIF N_135_i.BLIF N_168.BLIF clk_cpu_est_11_0_3__n.BLIF N_171.BLIF \
-N_130_i.BLIF N_135_1.BLIF clk_cpu_est_11_0_1__n.BLIF \
-state_machine_un13_clk_000_d_2_n.BLIF N_128_i.BLIF clk_cpu_est_11_3__n.BLIF \
-un1_bg_030_0.BLIF N_135.BLIF N_97_i.BLIF N_133.BLIF BG_030_c_i.BLIF N_134.BLIF \
-N_127_i.BLIF N_132.BLIF N_129_i.BLIF N_131.BLIF N_92_0.BLIF N_126.BLIF \
-N_100_i.BLIF state_machine_un34_clk_000_d_n.BLIF N_112_i.BLIF \
-UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_1.BLIF \
-clk_un4_clk_000_dd_i_n.BLIF state_machine_as_030_000_sync_3_n.BLIF \
-state_machine_un6_bgack_000_0_n.BLIF N_145.BLIF \
-state_machine_un1_clk_030_0_n.BLIF state_machine_lds_000_int_8_n.BLIF \
-clk_cpu_est_11_0_1_3__n.BLIF state_machine_uds_000_int_8_n.BLIF \
-state_machine_un34_clk_000_d_i_1_n.BLIF un1_as_030_4.BLIF \
-state_machine_as_030_000_sync_3_2_1_n.BLIF un1_as_030_3.BLIF N_168_1.BLIF \
-DSACK_INT_1_sqmuxa.BLIF N_168_2.BLIF state_machine_un17_clk_030_n.BLIF \
-N_168_3.BLIF state_machine_un60_clk_000_d_n.BLIF N_168_4.BLIF \
-DTACK_SYNC_1_sqmuxa.BLIF N_168_5.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF N_168_6.BLIF \
-VPA_SYNC_1_sqmuxa.BLIF N_171_1.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_171_2.BLIF \
-N_103.BLIF un1_bg_030_0_1.BLIF N_104.BLIF un1_bg_030_0_2.BLIF N_93.BLIF \
-clk_cpu_est_11_0_1_1__n.BLIF N_105.BLIF clk_cpu_est_11_0_2_1__n.BLIF \
-VPA_SYNC_1_sqmuxa_1_0.BLIF state_machine_un42_clk_030_1_n.BLIF \
-state_machine_un15_clk_000_d_n.BLIF state_machine_un42_clk_030_2_n.BLIF \
-state_machine_un13_clk_000_d_n.BLIF state_machine_un42_clk_030_3_n.BLIF \
-state_machine_un8_clk_000_d_n.BLIF state_machine_un42_clk_030_4_n.BLIF \
-state_machine_un8_clk_000_d_1_n.BLIF state_machine_un42_clk_030_5_n.BLIF \
-state_machine_un13_clk_000_d_1_n.BLIF N_132_1.BLIF N_107.BLIF N_131_1.BLIF \
-N_94.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_91.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \
-N_110.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_108.BLIF \
-UDS_000_INT_0_sqmuxa_1_2.BLIF N_109.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \
-N_106.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF N_101.BLIF \
-state_machine_un8_clk_000_d_1_0_n.BLIF N_99.BLIF \
-state_machine_un8_clk_000_d_2_n.BLIF AS_000_INT_1_sqmuxa.BLIF \
-state_machine_un8_clk_000_d_3_n.BLIF RW_i.BLIF \
-state_machine_un13_clk_000_d_1_0_n.BLIF N_102_i.BLIF \
-state_machine_un13_clk_000_d_2_0_n.BLIF AS_000_INT_i.BLIF \
-VPA_SYNC_1_sqmuxa_1_1.BLIF dsack_i_1__n.BLIF VPA_SYNC_1_sqmuxa_2.BLIF \
-AS_030_i.BLIF VPA_SYNC_1_sqmuxa_3.BLIF sm_amiga_i_7__n.BLIF \
-VPA_SYNC_1_sqmuxa_4.BLIF CLK_000_D_i.BLIF N_107_1.BLIF sm_amiga_i_2__n.BLIF \
-N_98_1.BLIF sm_amiga_i_1__n.BLIF as_000_int_0_un3_n.BLIF \
-state_machine_un13_clk_000_d_1_i_n.BLIF as_000_int_0_un1_n.BLIF VPA_D_i.BLIF \
-as_000_int_0_un0_n.BLIF VMA_INT_i.BLIF vma_int_0_un3_n.BLIF \
-cpu_est_i_0__n.BLIF vma_int_0_un1_n.BLIF cpu_est_i_1__n.BLIF \
-vma_int_0_un0_n.BLIF cpu_est_i_3__n.BLIF uds_000_int_0_un3_n.BLIF \
-state_machine_un8_clk_000_d_1_i_0_n.BLIF uds_000_int_0_un1_n.BLIF DTACK_i.BLIF \
-uds_000_int_0_un0_n.BLIF sm_amiga_i_3__n.BLIF dtack_sync_0_un3_n.BLIF \
-sm_amiga_i_4__n.BLIF dtack_sync_0_un1_n.BLIF sm_amiga_i_5__n.BLIF \
-dtack_sync_0_un0_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF \
-VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un1_n.BLIF N_98_i.BLIF \
-vpa_sync_0_un0_n.BLIF state_machine_un42_clk_030_i_n.BLIF \
-dsack_int_0_1__un3_n.BLIF UDS_000_INT_0_sqmuxa_1_i.BLIF \
-dsack_int_0_1__un1_n.BLIF UDS_000_INT_0_sqmuxa_i.BLIF \
-dsack_int_0_1__un0_n.BLIF AS_030_000_SYNC_i.BLIF as_030_000_sync_0_un3_n.BLIF \
-DS_030_i.BLIF as_030_000_sync_0_un1_n.BLIF cpu_est_i_2__n.BLIF \
-as_030_000_sync_0_un0_n.BLIF state_machine_un13_clk_000_d_2_i_n.BLIF \
-fpu_cs_int_0_un3_n.BLIF CLK_000_DD_i.BLIF fpu_cs_int_0_un1_n.BLIF \
-sm_amiga_i_6__n.BLIF fpu_cs_int_0_un0_n.BLIF CLK_030_i.BLIF \
-lds_000_int_0_un3_n.BLIF a_i_30__n.BLIF lds_000_int_0_un1_n.BLIF \
-a_i_31__n.BLIF lds_000_int_0_un0_n.BLIF a_i_28__n.BLIF cpu_est_0_3__un3_n.BLIF \
-a_i_29__n.BLIF cpu_est_0_3__un1_n.BLIF a_i_26__n.BLIF cpu_est_0_3__un0_n.BLIF \
-a_i_27__n.BLIF cpu_est_0_2__un3_n.BLIF a_i_24__n.BLIF cpu_est_0_2__un1_n.BLIF \
-a_i_25__n.BLIF cpu_est_0_2__un0_n.BLIF a_i_19__n.BLIF bg_000_0_un3_n.BLIF \
-a_i_16__n.BLIF bg_000_0_un1_n.BLIF a_i_18__n.BLIF bg_000_0_un0_n.BLIF \
-bgack_030_int_0_un3_n.BLIF RST_i.BLIF bgack_030_int_0_un1_n.BLIF \
-bgack_030_int_0_un0_n.BLIF FPU_CS_INT_i.BLIF cpu_est_0_1__un3_n.BLIF \
-CPU_SPACE_i.BLIF cpu_est_0_1__un1_n.BLIF BGACK_030_INT_i.BLIF \
-cpu_est_0_1__un0_n.BLIF AS_030_c.BLIF ipl_030_0_0__un3_n.BLIF \
-ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF DS_030_c.BLIF \
-ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF \
-ipl_030_0_2__un3_n.BLIF size_c_0__n.BLIF ipl_030_0_2__un1_n.BLIF \
-ipl_030_0_2__un0_n.BLIF size_c_1__n.BLIF a_15__n.BLIF a_c_0__n.BLIF \
-a_14__n.BLIF a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF a_10__n.BLIF a_9__n.BLIF \
+DSACK_0_.BLIF ipl_c_0__n.BLIF ipl_c_1__n.BLIF ipl_c_2__n.BLIF \
+inst_BGACK_030_INTreg.BLIF inst_FPU_CS_INTreg.BLIF dsack_c_1__n.BLIF \
+cpu_est_3_reg.BLIF inst_VMA_INTreg.BLIF DTACK_c.BLIF cpu_est_0_.BLIF \
+cpu_est_1_.BLIF inst_AS_000_INTreg.BLIF inst_AS_030_000_SYNC.BLIF \
+inst_DTACK_SYNC.BLIF inst_VPA_D.BLIF inst_VPA_SYNC.BLIF inst_CLK_000_D0.BLIF \
+RST_c.BLIF inst_CLK_000_D1.BLIF inst_CLK_OUT_PRE.BLIF RESETDFFreg.BLIF \
+vcc_n_n.BLIF gnd_n_n.BLIF RW_c.BLIF cpu_est_2_.BLIF CLK_CNT_0_.BLIF \
+fc_c_0__n.BLIF SM_AMIGA_6_.BLIF SM_AMIGA_7_.BLIF fc_c_1__n.BLIF \
+inst_UDS_000_INTreg.BLIF inst_LDS_000_INTreg.BLIF DSACK_INT_1_.BLIF \
+state_machine_un60_clk_000_d0_n.BLIF SM_AMIGA_1_.BLIF inst_DTACK_DMA.BLIF \
+N_100_i.BLIF SM_AMIGA_4_.BLIF sm_amiga_ns_0_2__n.BLIF SM_AMIGA_3_.BLIF \
+N_103_i.BLIF DSACK_INT_1_sqmuxa.BLIF N_104_i.BLIF \
+state_machine_un13_as_000_int_n.BLIF VPA_SYNC_1_sqmuxa_1.BLIF N_106_i.BLIF \
+un1_as_030_4.BLIF N_105_i.BLIF SM_AMIGA_5_.BLIF sm_amiga_ns_0_5__n.BLIF \
+SM_AMIGA_2_.BLIF N_107_i.BLIF SM_AMIGA_0_.BLIF N_108_i.BLIF \
+state_machine_lds_000_int_8_n.BLIF sm_amiga_ns_0_6__n.BLIF \
+state_machine_uds_000_int_8_n.BLIF N_90_i.BLIF N_93_0.BLIF N_128_i.BLIF \
+N_126_i.BLIF N_127_i.BLIF N_129_i.BLIF clk_cpu_est_11_0_1__n.BLIF N_133_i.BLIF \
+N_132_i.BLIF N_134_i.BLIF clk_cpu_est_11_0_3__n.BLIF N_125_i.BLIF \
+cpu_est_0_0_.BLIF N_124_i.BLIF N_130_i.BLIF N_131_i.BLIF N_121_i.BLIF \
+N_91_0.BLIF N_109_i.BLIF sm_amiga_ns_0_7__n.BLIF CLK_OUT_PRE_0.BLIF \
+state_machine_un8_clk_000_d0_i_n.BLIF state_machine_un13_clk_000_d0_i_n.BLIF \
+state_machine_un15_clk_000_d0_0_n.BLIF BG_030_c_i.BLIF \
+state_machine_un1_clk_030_0_n.BLIF clk_un4_clk_000_d1_n.BLIF \
+state_machine_un17_clk_030_0_n.BLIF N_144.BLIF un1_as_030_3_0.BLIF N_101.BLIF \
+state_machine_as_030_000_sync_3_2_n.BLIF VPA_SYNC_1_sqmuxa.BLIF N_96_i.BLIF \
+N_97.BLIF un1_bg_030_0.BLIF state_machine_un34_clk_000_d0_n.BLIF \
+clk_un4_clk_000_d1_i_n.BLIF N_96.BLIF state_machine_un6_bgack_000_0_n.BLIF \
+N_102.BLIF N_98_i.BLIF UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_1.BLIF \
+N_111_i.BLIF N_167.BLIF N_99_i.BLIF N_170.BLIF N_92.BLIF N_92_0.BLIF N_91.BLIF \
+state_machine_un34_clk_000_d0_i_n.BLIF N_99.BLIF a_c_i_0__n.BLIF N_111.BLIF \
+size_c_i_1__n.BLIF N_98.BLIF N_102_i.BLIF state_machine_un6_bgack_000_n.BLIF \
+state_machine_un42_clk_030_n.BLIF N_144_i.BLIF DTACK_SYNC_1_sqmuxa.BLIF \
+state_machine_lds_000_int_8_0_n.BLIF un1_bg_030.BLIF \
+state_machine_uds_000_int_8_0_n.BLIF state_machine_as_030_000_sync_3_n.BLIF \
+state_machine_un60_clk_000_d0_i_n.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF \
+un1_bg_030_0_1.BLIF un1_as_030_3.BLIF un1_bg_030_0_2.BLIF \
+state_machine_un17_clk_030_n.BLIF state_machine_as_030_000_sync_3_2_1_n.BLIF \
+state_machine_un1_clk_030_n.BLIF clk_cpu_est_11_0_1_3__n.BLIF \
+VPA_SYNC_1_sqmuxa_1_0.BLIF clk_cpu_est_11_0_1_1__n.BLIF \
+state_machine_un15_clk_000_d0_n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \
+state_machine_un13_clk_000_d0_n.BLIF N_167_1.BLIF \
+state_machine_un8_clk_000_d0_n.BLIF N_167_2.BLIF N_109.BLIF N_167_3.BLIF \
+state_machine_un13_clk_000_d0_1_n.BLIF N_167_4.BLIF N_129.BLIF N_167_5.BLIF \
+state_machine_un13_clk_000_d0_2_n.BLIF N_167_6.BLIF N_130.BLIF N_170_1.BLIF \
+N_131.BLIF N_170_2.BLIF N_124.BLIF UDS_000_INT_0_sqmuxa_1_1.BLIF N_125.BLIF \
+UDS_000_INT_0_sqmuxa_1_2.BLIF N_134.BLIF UDS_000_INT_0_sqmuxa_1_3.BLIF \
+N_134_1.BLIF UDS_000_INT_0_sqmuxa_1_0.BLIF N_106.BLIF \
+UDS_000_INT_0_sqmuxa_2.BLIF clk_cpu_est_11_3__n.BLIF \
+state_machine_un34_clk_000_d0_i_1_n.BLIF N_132.BLIF \
+state_machine_un42_clk_030_1_n.BLIF N_133.BLIF \
+state_machine_un42_clk_030_2_n.BLIF clk_cpu_est_11_1__n.BLIF \
+state_machine_un42_clk_030_3_n.BLIF N_127.BLIF \
+state_machine_un42_clk_030_4_n.BLIF N_126.BLIF \
+state_machine_un42_clk_030_5_n.BLIF N_128.BLIF DTACK_SYNC_1_sqmuxa_1_0.BLIF \
+N_93.BLIF N_130_1.BLIF N_90.BLIF N_131_1.BLIF N_107.BLIF \
+state_machine_un8_clk_000_d0_1_n.BLIF N_108.BLIF \
+state_machine_un8_clk_000_d0_2_n.BLIF N_105.BLIF \
+state_machine_un8_clk_000_d0_3_n.BLIF N_103.BLIF \
+state_machine_un8_clk_000_d0_4_n.BLIF N_104.BLIF \
+state_machine_un13_clk_000_d0_1_0_n.BLIF N_100.BLIF \
+state_machine_un13_clk_000_d0_2_0_n.BLIF AS_000_INT_1_sqmuxa.BLIF \
+VPA_SYNC_1_sqmuxa_1_1.BLIF RW_i.BLIF VPA_SYNC_1_sqmuxa_2.BLIF \
+nEXP_SPACE_i.BLIF VPA_SYNC_1_sqmuxa_3.BLIF N_101_i.BLIF \
+VPA_SYNC_1_sqmuxa_4.BLIF AS_000_INT_i.BLIF N_106_1.BLIF dsack_i_1__n.BLIF \
+cpu_est_0_3__un3_n.BLIF AS_030_i.BLIF cpu_est_0_3__un1_n.BLIF \
+CLK_000_D0_i.BLIF cpu_est_0_3__un0_n.BLIF sm_amiga_i_3__n.BLIF \
+cpu_est_0_1__un3_n.BLIF sm_amiga_i_4__n.BLIF cpu_est_0_1__un1_n.BLIF \
+CLK_000_D1_i.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_i_0__n.BLIF \
+as_000_int_0_un3_n.BLIF cpu_est_i_3__n.BLIF as_000_int_0_un1_n.BLIF \
+cpu_est_i_2__n.BLIF as_000_int_0_un0_n.BLIF VPA_D_i.BLIF bg_000_0_un3_n.BLIF \
+VMA_INT_i.BLIF bg_000_0_un1_n.BLIF cpu_est_i_1__n.BLIF bg_000_0_un0_n.BLIF \
+state_machine_un13_clk_000_d0_2_i_n.BLIF as_030_000_sync_0_un3_n.BLIF \
+state_machine_un13_clk_000_d0_1_i_n.BLIF as_030_000_sync_0_un1_n.BLIF \
+DTACK_i.BLIF as_030_000_sync_0_un0_n.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF \
+fpu_cs_int_0_un3_n.BLIF a_i_18__n.BLIF fpu_cs_int_0_un1_n.BLIF a_i_16__n.BLIF \
+fpu_cs_int_0_un0_n.BLIF a_i_19__n.BLIF dtack_sync_0_un3_n.BLIF CLK_030_i.BLIF \
+dtack_sync_0_un1_n.BLIF state_machine_un42_clk_030_i_n.BLIF \
+dtack_sync_0_un0_n.BLIF sm_amiga_i_6__n.BLIF vma_int_0_un3_n.BLIF \
+sm_amiga_i_7__n.BLIF vma_int_0_un1_n.BLIF AS_030_000_SYNC_i.BLIF \
+vma_int_0_un0_n.BLIF DS_030_i.BLIF cpu_est_0_2__un3_n.BLIF \
+UDS_000_INT_0_sqmuxa_1_i.BLIF cpu_est_0_2__un1_n.BLIF \
+UDS_000_INT_0_sqmuxa_i.BLIF cpu_est_0_2__un0_n.BLIF sm_amiga_i_5__n.BLIF \
+ipl_030_0_0__un3_n.BLIF VPA_SYNC_1_sqmuxa_i.BLIF ipl_030_0_0__un1_n.BLIF \
+N_97_i.BLIF ipl_030_0_0__un0_n.BLIF a_i_30__n.BLIF ipl_030_0_1__un3_n.BLIF \
+a_i_31__n.BLIF ipl_030_0_1__un1_n.BLIF a_i_28__n.BLIF ipl_030_0_1__un0_n.BLIF \
+a_i_29__n.BLIF ipl_030_0_2__un3_n.BLIF a_i_26__n.BLIF ipl_030_0_2__un1_n.BLIF \
+a_i_27__n.BLIF ipl_030_0_2__un0_n.BLIF a_i_24__n.BLIF \
+bgack_030_int_0_un3_n.BLIF a_i_25__n.BLIF bgack_030_int_0_un1_n.BLIF \
+bgack_030_int_0_un0_n.BLIF RST_i.BLIF uds_000_int_0_un3_n.BLIF \
+uds_000_int_0_un1_n.BLIF FPU_CS_INT_i.BLIF uds_000_int_0_un0_n.BLIF \
+BGACK_030_INT_i.BLIF lds_000_int_0_un3_n.BLIF AS_030_c.BLIF \
+lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF vpa_sync_0_un3_n.BLIF \
+DS_030_c.BLIF vpa_sync_0_un1_n.BLIF vpa_sync_0_un0_n.BLIF \
+dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un1_n.BLIF size_c_0__n.BLIF \
+dsack_int_0_1__un0_n.BLIF a_15__n.BLIF size_c_1__n.BLIF a_14__n.BLIF \
+a_c_0__n.BLIF a_13__n.BLIF a_12__n.BLIF a_11__n.BLIF a_10__n.BLIF a_9__n.BLIF \
a_8__n.BLIF a_7__n.BLIF a_6__n.BLIF a_c_16__n.BLIF a_5__n.BLIF a_c_17__n.BLIF \
a_4__n.BLIF a_c_18__n.BLIF a_3__n.BLIF a_c_19__n.BLIF a_2__n.BLIF \
a_c_20__n.BLIF a_1__n.BLIF a_c_21__n.BLIF a_c_22__n.BLIF a_c_23__n.BLIF \
a_c_24__n.BLIF a_c_25__n.BLIF a_c_26__n.BLIF a_c_27__n.BLIF a_c_28__n.BLIF \
-a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF CPU_SPACE_c.BLIF BG_030_c.BLIF \
+a_c_29__n.BLIF a_c_30__n.BLIF a_c_31__n.BLIF nEXP_SPACE_c.BLIF BG_030_c.BLIF \
BG_000DFFSHreg.BLIF BGACK_000_c.BLIF CLK_030_c.BLIF CLK_OSZI_c.BLIF \
-CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF
+CLK_OUT_INTreg.BLIF IPL_030DFFSH_0_reg.BLIF IPL_030DFFSH_1_reg.BLIF \
+IPL_030DFFSH_2_reg.BLIF DSACK_1_.PIN.BLIF DTACK.PIN.BLIF
.outputs IPL_030_2_ AS_000 UDS_000 LDS_000 BERR BG_000 BGACK_030 CLK_DIV_OUT \
CLK_EXP FPU_CS AVEC AVEC_EXP E VMA RESET AMIGA_BUS_ENABLE AMIGA_BUS_DATA_DIR \
AMIGA_BUS_ENABLE_LOW CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_3_.D SM_AMIGA_3_.C \
@@ -218,86 +217,84 @@ inst_AS_000_INTreg.C inst_AS_000_INTreg.AP inst_VPA_SYNC.D inst_VPA_SYNC.C \
inst_VPA_SYNC.AP BG_000DFFSHreg.D BG_000DFFSHreg.C BG_000DFFSHreg.AP \
inst_DTACK_DMA.D inst_DTACK_DMA.C inst_DTACK_DMA.AP inst_UDS_000_INTreg.D \
inst_UDS_000_INTreg.C inst_UDS_000_INTreg.AP CLK_CNT_0_.D CLK_CNT_0_.C \
-inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D.D inst_CLK_000_D.C RESETDFFreg.D \
-RESETDFFreg.C inst_CLK_000_DD.D inst_CLK_000_DD.C CLK_OUT_INTreg.D \
+inst_VPA_D.D inst_VPA_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C RESETDFFreg.D \
+RESETDFFreg.C inst_CLK_000_D1.D inst_CLK_000_D1.C CLK_OUT_INTreg.D \
CLK_OUT_INTreg.C DSACK_1_ DTACK DSACK_0_ ipl_c_0__n ipl_c_1__n ipl_c_2__n \
-gnd_n_n dsack_c_1__n DTACK_c RST_c vcc_n_n RW_c fc_c_0__n \
-state_machine_un1_clk_030_n fc_c_1__n state_machine_un6_bgack_000_n N_99_i \
-state_machine_un13_as_000_int_n un1_bg_030 N_101_i sm_amiga_ns_0_2__n N_107_i \
-N_106_i sm_amiga_ns_0_5__n N_108_i N_109_i N_110_i sm_amiga_ns_0_7__n N_91_0 \
-CLK_OUT_PRE_i N_94_0 state_machine_un8_clk_000_d_i_n \
-state_machine_un13_clk_000_d_i_n state_machine_un15_clk_000_d_0_n N_93_0 \
-N_104_i N_105_i N_103_i state_machine_un60_clk_000_d_i_n \
-state_machine_un17_clk_030_0_n un1_as_030_3_0 N_145_i clk_un4_clk_000_dd_n \
-a_c_i_0__n clk_cpu_est_11_1__n state_machine_uds_000_int_8_0_n \
-state_machine_un42_clk_030_n state_machine_lds_000_int_8_0_n N_102 \
-state_machine_as_030_000_sync_3_2_n N_98 size_c_i_1__n N_97 \
-state_machine_un34_clk_000_d_i_n N_100 N_131_i N_92 N_132_i N_112 N_122_i \
-N_127 N_125_i N_125 N_126_i N_128 N_134_i N_129 N_133_i N_130 N_135_i N_168 \
-clk_cpu_est_11_0_3__n N_171 N_130_i N_135_1 clk_cpu_est_11_0_1__n \
-state_machine_un13_clk_000_d_2_n N_128_i clk_cpu_est_11_3__n un1_bg_030_0 \
-N_135 N_97_i N_133 BG_030_c_i N_134 N_127_i N_132 N_129_i N_131 N_92_0 N_126 \
-N_100_i state_machine_un34_clk_000_d_n N_112_i UDS_000_INT_0_sqmuxa \
-UDS_000_INT_0_sqmuxa_1 clk_un4_clk_000_dd_i_n \
-state_machine_as_030_000_sync_3_n state_machine_un6_bgack_000_0_n N_145 \
-state_machine_un1_clk_030_0_n state_machine_lds_000_int_8_n \
-clk_cpu_est_11_0_1_3__n state_machine_uds_000_int_8_n \
-state_machine_un34_clk_000_d_i_1_n un1_as_030_4 \
-state_machine_as_030_000_sync_3_2_1_n un1_as_030_3 N_168_1 DSACK_INT_1_sqmuxa \
-N_168_2 state_machine_un17_clk_030_n N_168_3 state_machine_un60_clk_000_d_n \
-N_168_4 DTACK_SYNC_1_sqmuxa N_168_5 DTACK_SYNC_1_sqmuxa_1 N_168_6 \
-VPA_SYNC_1_sqmuxa N_171_1 VPA_SYNC_1_sqmuxa_1 N_171_2 N_103 un1_bg_030_0_1 \
-N_104 un1_bg_030_0_2 N_93 clk_cpu_est_11_0_1_1__n N_105 \
-clk_cpu_est_11_0_2_1__n VPA_SYNC_1_sqmuxa_1_0 state_machine_un42_clk_030_1_n \
-state_machine_un15_clk_000_d_n state_machine_un42_clk_030_2_n \
-state_machine_un13_clk_000_d_n state_machine_un42_clk_030_3_n \
-state_machine_un8_clk_000_d_n state_machine_un42_clk_030_4_n \
-state_machine_un8_clk_000_d_1_n state_machine_un42_clk_030_5_n \
-state_machine_un13_clk_000_d_1_n N_132_1 N_107 N_131_1 N_94 \
-UDS_000_INT_0_sqmuxa_1_0 N_91 UDS_000_INT_0_sqmuxa_2 N_110 \
-UDS_000_INT_0_sqmuxa_1_1 N_108 UDS_000_INT_0_sqmuxa_1_2 N_109 \
-UDS_000_INT_0_sqmuxa_1_3 N_106 DTACK_SYNC_1_sqmuxa_1_0 N_101 \
-state_machine_un8_clk_000_d_1_0_n N_99 state_machine_un8_clk_000_d_2_n \
-AS_000_INT_1_sqmuxa state_machine_un8_clk_000_d_3_n RW_i \
-state_machine_un13_clk_000_d_1_0_n N_102_i state_machine_un13_clk_000_d_2_0_n \
-AS_000_INT_i VPA_SYNC_1_sqmuxa_1_1 dsack_i_1__n VPA_SYNC_1_sqmuxa_2 AS_030_i \
-VPA_SYNC_1_sqmuxa_3 sm_amiga_i_7__n VPA_SYNC_1_sqmuxa_4 CLK_000_D_i N_107_1 \
-sm_amiga_i_2__n N_98_1 sm_amiga_i_1__n as_000_int_0_un3_n \
-state_machine_un13_clk_000_d_1_i_n as_000_int_0_un1_n VPA_D_i \
-as_000_int_0_un0_n VMA_INT_i vma_int_0_un3_n cpu_est_i_0__n vma_int_0_un1_n \
-cpu_est_i_1__n vma_int_0_un0_n cpu_est_i_3__n uds_000_int_0_un3_n \
-state_machine_un8_clk_000_d_1_i_0_n uds_000_int_0_un1_n DTACK_i \
-uds_000_int_0_un0_n sm_amiga_i_3__n dtack_sync_0_un3_n sm_amiga_i_4__n \
-dtack_sync_0_un1_n sm_amiga_i_5__n dtack_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i \
-vpa_sync_0_un3_n VPA_SYNC_1_sqmuxa_i vpa_sync_0_un1_n N_98_i vpa_sync_0_un0_n \
-state_machine_un42_clk_030_i_n dsack_int_0_1__un3_n UDS_000_INT_0_sqmuxa_1_i \
-dsack_int_0_1__un1_n UDS_000_INT_0_sqmuxa_i dsack_int_0_1__un0_n \
-AS_030_000_SYNC_i as_030_000_sync_0_un3_n DS_030_i as_030_000_sync_0_un1_n \
-cpu_est_i_2__n as_030_000_sync_0_un0_n state_machine_un13_clk_000_d_2_i_n \
-fpu_cs_int_0_un3_n CLK_000_DD_i fpu_cs_int_0_un1_n sm_amiga_i_6__n \
-fpu_cs_int_0_un0_n CLK_030_i lds_000_int_0_un3_n a_i_30__n lds_000_int_0_un1_n \
-a_i_31__n lds_000_int_0_un0_n a_i_28__n cpu_est_0_3__un3_n a_i_29__n \
-cpu_est_0_3__un1_n a_i_26__n cpu_est_0_3__un0_n a_i_27__n cpu_est_0_2__un3_n \
-a_i_24__n cpu_est_0_2__un1_n a_i_25__n cpu_est_0_2__un0_n a_i_19__n \
-bg_000_0_un3_n a_i_16__n bg_000_0_un1_n a_i_18__n bg_000_0_un0_n \
-bgack_030_int_0_un3_n RST_i bgack_030_int_0_un1_n bgack_030_int_0_un0_n \
-FPU_CS_INT_i cpu_est_0_1__un3_n CPU_SPACE_i cpu_est_0_1__un1_n BGACK_030_INT_i \
-cpu_est_0_1__un0_n AS_030_c ipl_030_0_0__un3_n ipl_030_0_0__un1_n \
-ipl_030_0_0__un0_n DS_030_c ipl_030_0_1__un3_n ipl_030_0_1__un1_n \
-ipl_030_0_1__un0_n ipl_030_0_2__un3_n size_c_0__n ipl_030_0_2__un1_n \
-ipl_030_0_2__un0_n size_c_1__n a_15__n a_c_0__n a_14__n a_13__n a_12__n \
-a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n a_c_17__n a_4__n \
-a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n \
+dsack_c_1__n DTACK_c RST_c vcc_n_n gnd_n_n RW_c fc_c_0__n fc_c_1__n \
+state_machine_un60_clk_000_d0_n N_100_i sm_amiga_ns_0_2__n N_103_i \
+DSACK_INT_1_sqmuxa N_104_i state_machine_un13_as_000_int_n VPA_SYNC_1_sqmuxa_1 \
+N_106_i un1_as_030_4 N_105_i sm_amiga_ns_0_5__n N_107_i N_108_i \
+state_machine_lds_000_int_8_n sm_amiga_ns_0_6__n state_machine_uds_000_int_8_n \
+N_90_i N_93_0 N_128_i N_126_i N_127_i N_129_i clk_cpu_est_11_0_1__n N_133_i \
+N_132_i N_134_i clk_cpu_est_11_0_3__n N_125_i N_124_i N_130_i N_131_i N_121_i \
+N_91_0 N_109_i sm_amiga_ns_0_7__n state_machine_un8_clk_000_d0_i_n \
+state_machine_un13_clk_000_d0_i_n state_machine_un15_clk_000_d0_0_n BG_030_c_i \
+state_machine_un1_clk_030_0_n clk_un4_clk_000_d1_n \
+state_machine_un17_clk_030_0_n N_144 un1_as_030_3_0 N_101 \
+state_machine_as_030_000_sync_3_2_n VPA_SYNC_1_sqmuxa N_96_i N_97 un1_bg_030_0 \
+state_machine_un34_clk_000_d0_n clk_un4_clk_000_d1_i_n N_96 \
+state_machine_un6_bgack_000_0_n N_102 N_98_i UDS_000_INT_0_sqmuxa \
+UDS_000_INT_0_sqmuxa_1 N_111_i N_167 N_99_i N_170 N_92 N_92_0 N_91 \
+state_machine_un34_clk_000_d0_i_n N_99 a_c_i_0__n N_111 size_c_i_1__n N_98 \
+N_102_i state_machine_un6_bgack_000_n state_machine_un42_clk_030_n N_144_i \
+DTACK_SYNC_1_sqmuxa state_machine_lds_000_int_8_0_n un1_bg_030 \
+state_machine_uds_000_int_8_0_n state_machine_as_030_000_sync_3_n \
+state_machine_un60_clk_000_d0_i_n DTACK_SYNC_1_sqmuxa_1 un1_bg_030_0_1 \
+un1_as_030_3 un1_bg_030_0_2 state_machine_un17_clk_030_n \
+state_machine_as_030_000_sync_3_2_1_n state_machine_un1_clk_030_n \
+clk_cpu_est_11_0_1_3__n VPA_SYNC_1_sqmuxa_1_0 clk_cpu_est_11_0_1_1__n \
+state_machine_un15_clk_000_d0_n clk_cpu_est_11_0_2_1__n \
+state_machine_un13_clk_000_d0_n N_167_1 state_machine_un8_clk_000_d0_n N_167_2 \
+N_109 N_167_3 state_machine_un13_clk_000_d0_1_n N_167_4 N_129 N_167_5 \
+state_machine_un13_clk_000_d0_2_n N_167_6 N_130 N_170_1 N_131 N_170_2 N_124 \
+UDS_000_INT_0_sqmuxa_1_1 N_125 UDS_000_INT_0_sqmuxa_1_2 N_134 \
+UDS_000_INT_0_sqmuxa_1_3 N_134_1 UDS_000_INT_0_sqmuxa_1_0 N_106 \
+UDS_000_INT_0_sqmuxa_2 clk_cpu_est_11_3__n state_machine_un34_clk_000_d0_i_1_n \
+N_132 state_machine_un42_clk_030_1_n N_133 state_machine_un42_clk_030_2_n \
+clk_cpu_est_11_1__n state_machine_un42_clk_030_3_n N_127 \
+state_machine_un42_clk_030_4_n N_126 state_machine_un42_clk_030_5_n N_128 \
+DTACK_SYNC_1_sqmuxa_1_0 N_93 N_130_1 N_90 N_131_1 N_107 \
+state_machine_un8_clk_000_d0_1_n N_108 state_machine_un8_clk_000_d0_2_n N_105 \
+state_machine_un8_clk_000_d0_3_n N_103 state_machine_un8_clk_000_d0_4_n N_104 \
+state_machine_un13_clk_000_d0_1_0_n N_100 state_machine_un13_clk_000_d0_2_0_n \
+AS_000_INT_1_sqmuxa VPA_SYNC_1_sqmuxa_1_1 RW_i VPA_SYNC_1_sqmuxa_2 \
+nEXP_SPACE_i VPA_SYNC_1_sqmuxa_3 N_101_i VPA_SYNC_1_sqmuxa_4 AS_000_INT_i \
+N_106_1 dsack_i_1__n cpu_est_0_3__un3_n AS_030_i cpu_est_0_3__un1_n \
+CLK_000_D0_i cpu_est_0_3__un0_n sm_amiga_i_3__n cpu_est_0_1__un3_n \
+sm_amiga_i_4__n cpu_est_0_1__un1_n CLK_000_D1_i cpu_est_0_1__un0_n \
+cpu_est_i_0__n as_000_int_0_un3_n cpu_est_i_3__n as_000_int_0_un1_n \
+cpu_est_i_2__n as_000_int_0_un0_n VPA_D_i bg_000_0_un3_n VMA_INT_i \
+bg_000_0_un1_n cpu_est_i_1__n bg_000_0_un0_n \
+state_machine_un13_clk_000_d0_2_i_n as_030_000_sync_0_un3_n \
+state_machine_un13_clk_000_d0_1_i_n as_030_000_sync_0_un1_n DTACK_i \
+as_030_000_sync_0_un0_n DTACK_SYNC_1_sqmuxa_i fpu_cs_int_0_un3_n a_i_18__n \
+fpu_cs_int_0_un1_n a_i_16__n fpu_cs_int_0_un0_n a_i_19__n dtack_sync_0_un3_n \
+CLK_030_i dtack_sync_0_un1_n state_machine_un42_clk_030_i_n dtack_sync_0_un0_n \
+sm_amiga_i_6__n vma_int_0_un3_n sm_amiga_i_7__n vma_int_0_un1_n \
+AS_030_000_SYNC_i vma_int_0_un0_n DS_030_i cpu_est_0_2__un3_n \
+UDS_000_INT_0_sqmuxa_1_i cpu_est_0_2__un1_n UDS_000_INT_0_sqmuxa_i \
+cpu_est_0_2__un0_n sm_amiga_i_5__n ipl_030_0_0__un3_n VPA_SYNC_1_sqmuxa_i \
+ipl_030_0_0__un1_n N_97_i ipl_030_0_0__un0_n a_i_30__n ipl_030_0_1__un3_n \
+a_i_31__n ipl_030_0_1__un1_n a_i_28__n ipl_030_0_1__un0_n a_i_29__n \
+ipl_030_0_2__un3_n a_i_26__n ipl_030_0_2__un1_n a_i_27__n ipl_030_0_2__un0_n \
+a_i_24__n bgack_030_int_0_un3_n a_i_25__n bgack_030_int_0_un1_n \
+bgack_030_int_0_un0_n RST_i uds_000_int_0_un3_n uds_000_int_0_un1_n \
+FPU_CS_INT_i uds_000_int_0_un0_n BGACK_030_INT_i lds_000_int_0_un3_n AS_030_c \
+lds_000_int_0_un1_n lds_000_int_0_un0_n vpa_sync_0_un3_n DS_030_c \
+vpa_sync_0_un1_n vpa_sync_0_un0_n dsack_int_0_1__un3_n dsack_int_0_1__un1_n \
+size_c_0__n dsack_int_0_1__un0_n a_15__n size_c_1__n a_14__n a_c_0__n a_13__n \
+a_12__n a_11__n a_10__n a_9__n a_8__n a_7__n a_6__n a_c_16__n a_5__n a_c_17__n \
+a_4__n a_c_18__n a_3__n a_c_19__n a_2__n a_c_20__n a_1__n a_c_21__n a_c_22__n \
a_c_23__n a_c_24__n a_c_25__n a_c_26__n a_c_27__n a_c_28__n a_c_29__n \
-a_c_30__n a_c_31__n CPU_SPACE_c BG_030_c BGACK_000_c CLK_030_c CLK_OSZI_c \
+a_c_30__n a_c_31__n nEXP_SPACE_c BG_030_c BGACK_000_c CLK_030_c CLK_OSZI_c \
DSACK_1_.OE DTACK.OE AS_000.OE UDS_000.OE LDS_000.OE BERR.OE DSACK_0_.OE \
AVEC_EXP.OE CIIN.OE cpu_est_0_0_ CLK_OUT_PRE_0
-.names N_104_i.BLIF N_105_i.BLIF SM_AMIGA_3_.D
+.names N_103_i.BLIF N_104_i.BLIF SM_AMIGA_3_.D
11 1
.names sm_amiga_ns_0_5__n.BLIF SM_AMIGA_2_.D
0 1
-.names N_108_i.BLIF N_109_i.BLIF SM_AMIGA_1_.D
-11 1
+.names sm_amiga_ns_0_6__n.BLIF SM_AMIGA_1_.D
+0 1
.names sm_amiga_ns_0_7__n.BLIF SM_AMIGA_0_.D
0 1
.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF IPL_030DFFSH_0_reg.D
@@ -309,13 +306,13 @@ AVEC_EXP.OE CIIN.OE cpu_est_0_0_ CLK_OUT_PRE_0
.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF IPL_030DFFSH_2_reg.D
1- 1
-1 1
-.names inst_CLK_000_D.BLIF N_99_i.BLIF SM_AMIGA_7_.D
+.names inst_CLK_000_D0.BLIF N_98_i.BLIF SM_AMIGA_7_.D
11 1
-.names N_100_i.BLIF N_112_i.BLIF SM_AMIGA_6_.D
+.names N_99_i.BLIF N_111_i.BLIF SM_AMIGA_6_.D
11 1
.names sm_amiga_ns_0_2__n.BLIF SM_AMIGA_5_.D
0 1
-.names CLK_000_D_i.BLIF N_103_i.BLIF SM_AMIGA_4_.D
+.names CLK_000_D0_i.BLIF N_102_i.BLIF SM_AMIGA_4_.D
11 1
.names dsack_int_0_1__un1_n.BLIF dsack_int_0_1__un0_n.BLIF DSACK_INT_1_.D
1- 1
@@ -365,516 +362,504 @@ inst_AS_030_000_SYNC.D
-1 1
.names CLK_CNT_0_.BLIF CLK_CNT_0_.D
0 1
-.names gnd_n_n
.names vcc_n_n
1
-.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n
+.names gnd_n_n
+.names state_machine_un60_clk_000_d0_i_n.BLIF state_machine_un60_clk_000_d0_n
0 1
-.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
+.names N_100.BLIF N_100_i
0 1
-.names N_99.BLIF N_99_i
-0 1
-.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un13_as_000_int_n
+.names N_100_i.BLIF N_101_i.BLIF sm_amiga_ns_0_2__n
11 1
-.names un1_bg_030_0.BLIF un1_bg_030
+.names N_103.BLIF N_103_i
0 1
-.names N_101.BLIF N_101_i
-0 1
-.names N_101_i.BLIF N_102_i.BLIF sm_amiga_ns_0_2__n
-11 1
-.names N_107.BLIF N_107_i
-0 1
-.names N_106.BLIF N_106_i
-0 1
-.names N_106_i.BLIF N_107_i.BLIF sm_amiga_ns_0_5__n
-11 1
-.names N_108.BLIF N_108_i
-0 1
-.names N_109.BLIF N_109_i
-0 1
-.names N_110.BLIF N_110_i
-0 1
-.names N_98_i.BLIF N_110_i.BLIF sm_amiga_ns_0_7__n
-11 1
-.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_91_0
-11 1
-.names inst_CLK_OUT_PRE.BLIF CLK_OUT_PRE_i
-0 1
-.names CLK_OUT_PRE_i.BLIF sm_amiga_i_2__n.BLIF N_94_0
-11 1
-.names state_machine_un8_clk_000_d_n.BLIF state_machine_un8_clk_000_d_i_n
-0 1
-.names state_machine_un13_clk_000_d_n.BLIF state_machine_un13_clk_000_d_i_n
-0 1
-.names state_machine_un8_clk_000_d_i_n.BLIF \
-state_machine_un13_clk_000_d_i_n.BLIF state_machine_un15_clk_000_d_0_n
-11 1
-.names SM_AMIGA_3_.BLIF state_machine_un60_clk_000_d_i_n.BLIF N_93_0
+.names AS_030_i.BLIF N_97_i.BLIF DSACK_INT_1_sqmuxa
11 1
.names N_104.BLIF N_104_i
0 1
+.names AS_000_INT_i.BLIF dsack_i_1__n.BLIF state_machine_un13_as_000_int_n
+11 1
+.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1
+11 1
+.names N_106.BLIF N_106_i
+0 1
+.names AS_030_i.BLIF N_144.BLIF un1_as_030_4
+11 1
.names N_105.BLIF N_105_i
0 1
-.names N_103.BLIF N_103_i
+.names N_105_i.BLIF N_106_i.BLIF sm_amiga_ns_0_5__n
+11 1
+.names N_107.BLIF N_107_i
0 1
-.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \
-state_machine_un60_clk_000_d_i_n
+.names N_108.BLIF N_108_i
+0 1
+.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n
+0 1
+.names N_107_i.BLIF N_108_i.BLIF sm_amiga_ns_0_6__n
+11 1
+.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n
+0 1
+.names CLK_000_D1_i.BLIF inst_CLK_OUT_PRE.BLIF N_90_i
+11 1
+.names SM_AMIGA_3_.BLIF state_machine_un60_clk_000_d0_i_n.BLIF N_93_0
+11 1
+.names N_128.BLIF N_128_i
+0 1
+.names N_126.BLIF N_126_i
+0 1
+.names N_127.BLIF N_127_i
+0 1
+.names N_129.BLIF N_129_i
+0 1
+.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \
+clk_cpu_est_11_0_1__n
+11 1
+.names N_133.BLIF N_133_i
+0 1
+.names N_132.BLIF N_132_i
+0 1
+.names N_134.BLIF N_134_i
+0 1
+.names clk_cpu_est_11_0_1_3__n.BLIF N_133_i.BLIF clk_cpu_est_11_0_3__n
+11 1
+.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_125_i
+11 1
+.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_124_i
+11 1
+.names N_130.BLIF N_130_i
+0 1
+.names N_131.BLIF N_131_i
+0 1
+.names N_130_i.BLIF N_131_i.BLIF N_121_i
+11 1
+.names inst_AS_000_INTreg.BLIF SM_AMIGA_0_.BLIF N_91_0
+11 1
+.names N_109.BLIF N_109_i
+0 1
+.names N_97_i.BLIF N_109_i.BLIF sm_amiga_ns_0_7__n
+11 1
+.names state_machine_un8_clk_000_d0_n.BLIF state_machine_un8_clk_000_d0_i_n
+0 1
+.names state_machine_un13_clk_000_d0_n.BLIF state_machine_un13_clk_000_d0_i_n
+0 1
+.names state_machine_un8_clk_000_d0_i_n.BLIF \
+state_machine_un13_clk_000_d0_i_n.BLIF state_machine_un15_clk_000_d0_0_n
+11 1
+.names BG_030_c.BLIF BG_030_c_i
+0 1
+.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n
+11 1
+.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF clk_un4_clk_000_d1_n
11 1
.names AS_030_i.BLIF CLK_030_i.BLIF state_machine_un17_clk_030_0_n
11 1
+.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_144
+11 1
.names AS_030_i.BLIF state_machine_un42_clk_030_n.BLIF un1_as_030_3_0
11 1
-.names N_145.BLIF N_145_i
-0 1
-.names inst_CLK_000_D.BLIF CLK_000_DD_i.BLIF clk_un4_clk_000_dd_n
-11 1
-.names a_c_0__n.BLIF a_c_i_0__n
-0 1
-.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n
-0 1
-.names a_c_i_0__n.BLIF N_145_i.BLIF state_machine_uds_000_int_8_0_n
-11 1
-.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF \
-state_machine_un42_clk_030_n
-11 1
-.names N_145_i.BLIF state_machine_un34_clk_000_d_n.BLIF \
-state_machine_lds_000_int_8_0_n
-11 1
-.names N_112.BLIF SM_AMIGA_6_.BLIF N_102
+.names N_111.BLIF SM_AMIGA_6_.BLIF N_101
11 1
.names state_machine_as_030_000_sync_3_2_1_n.BLIF \
state_machine_un42_clk_030_i_n.BLIF state_machine_as_030_000_sync_3_2_n
11 1
-.names N_98_1.BLIF SM_AMIGA_1_.BLIF N_98
+.names VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa
11 1
-.names size_c_1__n.BLIF size_c_i_1__n
+.names N_96.BLIF N_96_i
0 1
-.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_97
+.names N_90_i.BLIF SM_AMIGA_1_.BLIF N_97
11 1
-.names state_machine_un34_clk_000_d_i_1_n.BLIF size_c_i_1__n.BLIF \
-state_machine_un34_clk_000_d_i_n
-11 1
-.names N_92.BLIF sm_amiga_i_6__n.BLIF N_100
-11 1
-.names N_131.BLIF N_131_i
-0 1
-.names N_92_0.BLIF N_92
-0 1
-.names N_132.BLIF N_132_i
-0 1
-.names AS_030_000_SYNC_i.BLIF clk_un4_clk_000_dd_n.BLIF N_112
-11 1
-.names N_131_i.BLIF N_132_i.BLIF N_122_i
-11 1
-.names N_125.BLIF cpu_est_i_0__n.BLIF N_127
-11 1
-.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF N_125_i
-11 1
-.names N_125_i.BLIF N_125
-0 1
-.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_126_i
-11 1
-.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_128
-11 1
-.names N_134.BLIF N_134_i
-0 1
-.names N_125_i.BLIF cpu_est_0_.BLIF N_129
-11 1
-.names N_133.BLIF N_133_i
-0 1
-.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d_2_n.BLIF N_130
-11 1
-.names N_135.BLIF N_135_i
-0 1
-.names N_168_5.BLIF N_168_6.BLIF N_168
-11 1
-.names clk_cpu_est_11_0_1_3__n.BLIF N_134_i.BLIF clk_cpu_est_11_0_3__n
-11 1
-.names N_171_1.BLIF N_171_2.BLIF N_171
-11 1
-.names N_130.BLIF N_130_i
-0 1
-.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_135_1
-11 1
-.names clk_cpu_est_11_0_1_1__n.BLIF clk_cpu_est_11_0_2_1__n.BLIF \
-clk_cpu_est_11_0_1__n
-11 1
-.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d_2_n
-11 1
-.names N_128.BLIF N_128_i
-0 1
-.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n
-0 1
.names un1_bg_030_0_1.BLIF un1_bg_030_0_2.BLIF un1_bg_030_0
11 1
-.names N_135_1.BLIF cpu_est_i_2__n.BLIF N_135
+.names state_machine_un34_clk_000_d0_i_n.BLIF state_machine_un34_clk_000_d0_n
+0 1
+.names clk_un4_clk_000_d1_n.BLIF clk_un4_clk_000_d1_i_n
+0 1
+.names sm_amiga_i_6__n.BLIF sm_amiga_i_7__n.BLIF N_96
11 1
-.names N_97.BLIF N_97_i
-0 1
-.names N_126.BLIF cpu_est_3_reg.BLIF N_133
+.names BGACK_000_c.BLIF clk_un4_clk_000_d1_i_n.BLIF \
+state_machine_un6_bgack_000_0_n
11 1
-.names BG_030_c.BLIF BG_030_c_i
-0 1
-.names N_126_i.BLIF cpu_est_i_2__n.BLIF N_134
+.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_102
11 1
-.names N_127.BLIF N_127_i
-0 1
-.names N_132_1.BLIF cpu_est_i_2__n.BLIF N_132
-11 1
-.names N_129.BLIF N_129_i
-0 1
-.names N_131_1.BLIF state_machine_un13_clk_000_d_2_i_n.BLIF N_131
-11 1
-.names CLK_000_D_i.BLIF SM_AMIGA_7_.BLIF N_92_0
-11 1
-.names N_126_i.BLIF N_126
-0 1
-.names N_100.BLIF N_100_i
-0 1
-.names state_machine_un34_clk_000_d_i_n.BLIF state_machine_un34_clk_000_d_n
-0 1
-.names N_112.BLIF N_112_i
+.names N_98.BLIF N_98_i
0 1
.names UDS_000_INT_0_sqmuxa_1_0.BLIF UDS_000_INT_0_sqmuxa_2.BLIF \
UDS_000_INT_0_sqmuxa
11 1
-.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un4_clk_000_dd_n.BLIF \
+.names UDS_000_INT_0_sqmuxa_1_3.BLIF clk_un4_clk_000_d1_n.BLIF \
UDS_000_INT_0_sqmuxa_1
11 1
-.names clk_un4_clk_000_dd_n.BLIF clk_un4_clk_000_dd_i_n
+.names N_111.BLIF N_111_i
0 1
-.names state_machine_as_030_000_sync_3_2_n.BLIF \
-state_machine_as_030_000_sync_3_n
+.names N_167_5.BLIF N_167_6.BLIF N_167
+11 1
+.names N_99.BLIF N_99_i
0 1
-.names BGACK_000_c.BLIF clk_un4_clk_000_dd_i_n.BLIF \
-state_machine_un6_bgack_000_0_n
+.names N_170_1.BLIF N_170_2.BLIF N_170
11 1
-.names UDS_000_INT_0_sqmuxa_1_i.BLIF UDS_000_INT_0_sqmuxa_i.BLIF N_145
-11 1
-.names BG_030_c_i.BLIF CLK_030_c.BLIF state_machine_un1_clk_030_0_n
-11 1
-.names state_machine_lds_000_int_8_0_n.BLIF state_machine_lds_000_int_8_n
+.names N_92_0.BLIF N_92
0 1
-.names N_135_i.BLIF N_133_i.BLIF clk_cpu_est_11_0_1_3__n
-11 1
-.names state_machine_uds_000_int_8_0_n.BLIF state_machine_uds_000_int_8_n
-0 1
-.names size_c_0__n.BLIF a_c_i_0__n.BLIF state_machine_un34_clk_000_d_i_1_n
-11 1
-.names AS_030_i.BLIF N_145.BLIF un1_as_030_4
-11 1
-.names AS_030_i.BLIF CPU_SPACE_i.BLIF state_machine_as_030_000_sync_3_2_1_n
-11 1
-.names un1_as_030_3_0.BLIF un1_as_030_3
-0 1
-.names a_i_24__n.BLIF a_i_25__n.BLIF N_168_1
-11 1
-.names AS_030_i.BLIF N_98_i.BLIF DSACK_INT_1_sqmuxa
-11 1
-.names a_i_26__n.BLIF a_i_27__n.BLIF N_168_2
-11 1
-.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n
-0 1
-.names a_i_28__n.BLIF a_i_29__n.BLIF N_168_3
-11 1
-.names state_machine_un60_clk_000_d_i_n.BLIF state_machine_un60_clk_000_d_n
-0 1
-.names a_i_30__n.BLIF a_i_31__n.BLIF N_168_4
-11 1
-.names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \
-DTACK_SYNC_1_sqmuxa
-11 1
-.names N_168_1.BLIF N_168_2.BLIF N_168_5
-11 1
-.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1
-11 1
-.names N_168_3.BLIF N_168_4.BLIF N_168_6
-11 1
-.names VPA_SYNC_1_sqmuxa_4.BLIF VPA_SYNC_1_sqmuxa_3.BLIF VPA_SYNC_1_sqmuxa
-11 1
-.names a_c_20__n.BLIF a_c_21__n.BLIF N_171_1
-11 1
-.names AS_030_i.BLIF VPA_SYNC_1_sqmuxa_i.BLIF VPA_SYNC_1_sqmuxa_1
-11 1
-.names a_c_22__n.BLIF a_c_23__n.BLIF N_171_2
-11 1
-.names sm_amiga_i_4__n.BLIF sm_amiga_i_5__n.BLIF N_103
-11 1
-.names AS_030_c.BLIF BG_030_c_i.BLIF un1_bg_030_0_1
-11 1
-.names CLK_000_D_i.BLIF N_93.BLIF N_104
-11 1
-.names CPU_SPACE_i.BLIF N_97_i.BLIF un1_bg_030_0_2
-11 1
-.names N_93_0.BLIF N_93
-0 1
-.names N_127_i.BLIF N_128_i.BLIF clk_cpu_est_11_0_1_1__n
-11 1
-.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_105
-11 1
-.names N_129_i.BLIF N_130_i.BLIF clk_cpu_est_11_0_2_1__n
-11 1
-.names inst_CLK_000_D.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0
-11 1
-.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n
-11 1
-.names state_machine_un15_clk_000_d_0_n.BLIF state_machine_un15_clk_000_d_n
-0 1
-.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n
-11 1
-.names state_machine_un13_clk_000_d_1_0_n.BLIF \
-state_machine_un13_clk_000_d_2_0_n.BLIF state_machine_un13_clk_000_d_n
-11 1
-.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n
-11 1
-.names state_machine_un8_clk_000_d_3_n.BLIF cpu_est_i_3__n.BLIF \
-state_machine_un8_clk_000_d_n
-11 1
-.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF \
-state_machine_un42_clk_030_4_n
-11 1
-.names CLK_000_D_i.BLIF cpu_est_0_.BLIF state_machine_un8_clk_000_d_1_n
-11 1
-.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF \
-state_machine_un42_clk_030_5_n
-11 1
-.names inst_AS_000_INTreg.BLIF inst_CLK_000_D.BLIF \
-state_machine_un13_clk_000_d_1_n
-11 1
-.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_132_1
-11 1
-.names N_107_1.BLIF state_machine_un60_clk_000_d_n.BLIF N_107
-11 1
-.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_131_1
-11 1
-.names N_94_0.BLIF N_94
-0 1
-.names inst_CLK_000_D.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0
+.names CLK_000_D0_i.BLIF SM_AMIGA_7_.BLIF N_92_0
11 1
.names N_91_0.BLIF N_91
0 1
-.names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2
+.names state_machine_un34_clk_000_d0_i_1_n.BLIF size_c_0__n.BLIF \
+state_machine_un34_clk_000_d0_i_n
11 1
-.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d_1_i_n.BLIF N_110
+.names N_92.BLIF sm_amiga_i_6__n.BLIF N_99
11 1
+.names a_c_0__n.BLIF a_c_i_0__n
+0 1
+.names AS_030_000_SYNC_i.BLIF clk_un4_clk_000_d1_n.BLIF N_111
+11 1
+.names size_c_1__n.BLIF size_c_i_1__n
+0 1
+.names N_91.BLIF sm_amiga_i_7__n.BLIF N_98
+11 1
+.names N_102.BLIF N_102_i
+0 1
+.names state_machine_un6_bgack_000_0_n.BLIF state_machine_un6_bgack_000_n
+0 1
+.names state_machine_un42_clk_030_4_n.BLIF state_machine_un42_clk_030_5_n.BLIF \
+state_machine_un42_clk_030_n
+11 1
+.names N_144.BLIF N_144_i
+0 1
+.names DTACK_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF \
+DTACK_SYNC_1_sqmuxa
+11 1
+.names N_144_i.BLIF state_machine_un34_clk_000_d0_n.BLIF \
+state_machine_lds_000_int_8_0_n
+11 1
+.names un1_bg_030_0.BLIF un1_bg_030
+0 1
+.names a_c_i_0__n.BLIF N_144_i.BLIF state_machine_uds_000_int_8_0_n
+11 1
+.names state_machine_as_030_000_sync_3_2_n.BLIF \
+state_machine_as_030_000_sync_3_n
+0 1
+.names inst_DTACK_SYNC.BLIF inst_VPA_SYNC.BLIF \
+state_machine_un60_clk_000_d0_i_n
+11 1
+.names AS_030_i.BLIF DTACK_SYNC_1_sqmuxa_i.BLIF DTACK_SYNC_1_sqmuxa_1
+11 1
+.names BG_030_c_i.BLIF N_96_i.BLIF un1_bg_030_0_1
+11 1
+.names un1_as_030_3_0.BLIF un1_as_030_3
+0 1
+.names AS_030_c.BLIF nEXP_SPACE_i.BLIF un1_bg_030_0_2
+11 1
+.names state_machine_un17_clk_030_0_n.BLIF state_machine_un17_clk_030_n
+0 1
+.names AS_030_i.BLIF nEXP_SPACE_c.BLIF state_machine_as_030_000_sync_3_2_1_n
+11 1
+.names state_machine_un1_clk_030_0_n.BLIF state_machine_un1_clk_030_n
+0 1
+.names N_134_i.BLIF N_132_i.BLIF clk_cpu_est_11_0_1_3__n
+11 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_3_.BLIF VPA_SYNC_1_sqmuxa_1_0
+11 1
+.names N_129_i.BLIF N_127_i.BLIF clk_cpu_est_11_0_1_1__n
+11 1
+.names state_machine_un15_clk_000_d0_0_n.BLIF state_machine_un15_clk_000_d0_n
+0 1
+.names N_126_i.BLIF N_128_i.BLIF clk_cpu_est_11_0_2_1__n
+11 1
+.names state_machine_un13_clk_000_d0_1_0_n.BLIF \
+state_machine_un13_clk_000_d0_2_0_n.BLIF state_machine_un13_clk_000_d0_n
+11 1
+.names a_i_24__n.BLIF a_i_25__n.BLIF N_167_1
+11 1
+.names state_machine_un8_clk_000_d0_4_n.BLIF \
+state_machine_un8_clk_000_d0_3_n.BLIF state_machine_un8_clk_000_d0_n
+11 1
+.names a_i_26__n.BLIF a_i_27__n.BLIF N_167_2
+11 1
+.names SM_AMIGA_0_.BLIF state_machine_un13_clk_000_d0_1_i_n.BLIF N_109
+11 1
+.names a_i_28__n.BLIF a_i_29__n.BLIF N_167_3
+11 1
+.names inst_AS_000_INTreg.BLIF inst_CLK_000_D0.BLIF \
+state_machine_un13_clk_000_d0_1_n
+11 1
+.names a_i_30__n.BLIF a_i_31__n.BLIF N_167_4
+11 1
+.names cpu_est_3_reg.BLIF state_machine_un13_clk_000_d0_2_n.BLIF N_129
+11 1
+.names N_167_1.BLIF N_167_2.BLIF N_167_5
+11 1
+.names cpu_est_1_.BLIF cpu_est_2_.BLIF state_machine_un13_clk_000_d0_2_n
+11 1
+.names N_167_3.BLIF N_167_4.BLIF N_167_6
+11 1
+.names N_130_1.BLIF state_machine_un13_clk_000_d0_2_i_n.BLIF N_130
+11 1
+.names a_c_20__n.BLIF a_c_21__n.BLIF N_170_1
+11 1
+.names N_131_1.BLIF cpu_est_i_2__n.BLIF N_131
+11 1
+.names a_c_22__n.BLIF a_c_23__n.BLIF N_170_2
+11 1
+.names N_124_i.BLIF N_124
+0 1
.names AS_030_000_SYNC_i.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_1
11 1
-.names CLK_000_D_i.BLIF N_94.BLIF N_108
-11 1
+.names N_125_i.BLIF N_125
+0 1
.names RW_c.BLIF SM_AMIGA_6_.BLIF UDS_000_INT_0_sqmuxa_1_2
11 1
-.names sm_amiga_i_1__n.BLIF sm_amiga_i_2__n.BLIF N_109
+.names N_134_1.BLIF cpu_est_i_2__n.BLIF N_134
11 1
.names UDS_000_INT_0_sqmuxa_1_1.BLIF UDS_000_INT_0_sqmuxa_1_2.BLIF \
UDS_000_INT_0_sqmuxa_1_3
11 1
-.names CLK_000_D_i.BLIF SM_AMIGA_2_.BLIF N_106
+.names cpu_est_i_0__n.BLIF cpu_est_i_1__n.BLIF N_134_1
+11 1
+.names inst_CLK_000_D0.BLIF DS_030_i.BLIF UDS_000_INT_0_sqmuxa_1_0
+11 1
+.names N_106_1.BLIF state_machine_un60_clk_000_d0_n.BLIF N_106
+11 1
+.names RW_i.BLIF SM_AMIGA_4_.BLIF UDS_000_INT_0_sqmuxa_2
+11 1
+.names clk_cpu_est_11_0_3__n.BLIF clk_cpu_est_11_3__n
+0 1
+.names size_c_i_1__n.BLIF a_c_i_0__n.BLIF state_machine_un34_clk_000_d0_i_1_n
+11 1
+.names N_125.BLIF cpu_est_3_reg.BLIF N_132
+11 1
+.names a_c_17__n.BLIF a_i_16__n.BLIF state_machine_un42_clk_030_1_n
+11 1
+.names N_125_i.BLIF cpu_est_i_2__n.BLIF N_133
+11 1
+.names a_i_18__n.BLIF a_i_19__n.BLIF state_machine_un42_clk_030_2_n
+11 1
+.names clk_cpu_est_11_0_1__n.BLIF clk_cpu_est_11_1__n
+0 1
+.names fc_c_1__n.BLIF BGACK_000_c.BLIF state_machine_un42_clk_030_3_n
+11 1
+.names cpu_est_i_2__n.BLIF cpu_est_i_3__n.BLIF N_127
+11 1
+.names state_machine_un42_clk_030_1_n.BLIF state_machine_un42_clk_030_2_n.BLIF \
+state_machine_un42_clk_030_4_n
+11 1
+.names N_124.BLIF cpu_est_i_0__n.BLIF N_126
+11 1
+.names state_machine_un42_clk_030_3_n.BLIF fc_c_0__n.BLIF \
+state_machine_un42_clk_030_5_n
+11 1
+.names N_124_i.BLIF cpu_est_0_.BLIF N_128
11 1
.names DTACK_i.BLIF inst_VPA_D.BLIF DTACK_SYNC_1_sqmuxa_1_0
11 1
-.names inst_CLK_000_D.BLIF SM_AMIGA_5_.BLIF N_101
+.names N_93_0.BLIF N_93
+0 1
+.names cpu_est_0_.BLIF cpu_est_i_3__n.BLIF N_130_1
11 1
-.names state_machine_un8_clk_000_d_1_n.BLIF VPA_D_i.BLIF \
-state_machine_un8_clk_000_d_1_0_n
+.names N_90_i.BLIF N_90
+0 1
+.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_131_1
11 1
-.names N_91.BLIF sm_amiga_i_7__n.BLIF N_99
+.names N_90.BLIF SM_AMIGA_1_.BLIF N_107
11 1
-.names cpu_est_2_.BLIF cpu_est_i_1__n.BLIF state_machine_un8_clk_000_d_2_n
+.names cpu_est_i_1__n.BLIF cpu_est_i_3__n.BLIF \
+state_machine_un8_clk_000_d0_1_n
11 1
-.names AS_030_i.BLIF N_102_i.BLIF AS_000_INT_1_sqmuxa
+.names inst_CLK_000_D0.BLIF SM_AMIGA_2_.BLIF N_108
11 1
-.names state_machine_un8_clk_000_d_1_0_n.BLIF \
-state_machine_un8_clk_000_d_2_n.BLIF state_machine_un8_clk_000_d_3_n
+.names CLK_000_D0_i.BLIF VPA_D_i.BLIF state_machine_un8_clk_000_d0_2_n
+11 1
+.names CLK_000_D0_i.BLIF SM_AMIGA_2_.BLIF N_105
+11 1
+.names cpu_est_0_.BLIF cpu_est_2_.BLIF state_machine_un8_clk_000_d0_3_n
+11 1
+.names CLK_000_D0_i.BLIF N_93.BLIF N_103
+11 1
+.names state_machine_un8_clk_000_d0_1_n.BLIF \
+state_machine_un8_clk_000_d0_2_n.BLIF state_machine_un8_clk_000_d0_4_n
+11 1
+.names sm_amiga_i_3__n.BLIF sm_amiga_i_4__n.BLIF N_104
+11 1
+.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF \
+state_machine_un13_clk_000_d0_1_0_n
+11 1
+.names inst_CLK_000_D0.BLIF SM_AMIGA_5_.BLIF N_100
+11 1
+.names state_machine_un13_clk_000_d0_1_n.BLIF \
+state_machine_un13_clk_000_d0_2_n.BLIF state_machine_un13_clk_000_d0_2_0_n
+11 1
+.names AS_030_i.BLIF N_101_i.BLIF AS_000_INT_1_sqmuxa
+11 1
+.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1
11 1
.names RW_c.BLIF RW_i
0 1
-.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF \
-state_machine_un13_clk_000_d_1_0_n
+.names N_134_1.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_2
11 1
-.names N_102.BLIF N_102_i
-0 1
-.names state_machine_un13_clk_000_d_1_n.BLIF \
-state_machine_un13_clk_000_d_2_n.BLIF state_machine_un13_clk_000_d_2_0_n
-11 1
-.names inst_AS_000_INTreg.BLIF AS_000_INT_i
-0 1
-.names cpu_est_2_.BLIF cpu_est_3_reg.BLIF VPA_SYNC_1_sqmuxa_1_1
-11 1
-.names dsack_c_1__n.BLIF dsack_i_1__n
-0 1
-.names N_135_1.BLIF VMA_INT_i.BLIF VPA_SYNC_1_sqmuxa_2
-11 1
-.names AS_030_c.BLIF AS_030_i
+.names nEXP_SPACE_c.BLIF nEXP_SPACE_i
0 1
.names VPA_D_i.BLIF VPA_SYNC_1_sqmuxa_1_0.BLIF VPA_SYNC_1_sqmuxa_3
11 1
-.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
+.names N_101.BLIF N_101_i
0 1
.names VPA_SYNC_1_sqmuxa_1_1.BLIF VPA_SYNC_1_sqmuxa_2.BLIF VPA_SYNC_1_sqmuxa_4
11 1
-.names inst_CLK_000_D.BLIF CLK_000_D_i
+.names inst_AS_000_INTreg.BLIF AS_000_INT_i
0 1
-.names CLK_000_D_i.BLIF SM_AMIGA_3_.BLIF N_107_1
+.names CLK_000_D0_i.BLIF SM_AMIGA_3_.BLIF N_106_1
11 1
-.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n
+.names dsack_c_1__n.BLIF dsack_i_1__n
0 1
-.names CLK_000_D_i.BLIF inst_CLK_OUT_PRE.BLIF N_98_1
+.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un3_n
+0 1
+.names AS_030_c.BLIF AS_030_i
+0 1
+.names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_3__un1_n
11 1
-.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
+.names inst_CLK_000_D0.BLIF CLK_000_D0_i
0 1
-.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n
-0 1
-.names state_machine_un13_clk_000_d_1_n.BLIF \
-state_machine_un13_clk_000_d_1_i_n
-0 1
-.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n
-11 1
-.names inst_VPA_D.BLIF VPA_D_i
-0 1
-.names N_102_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
-11 1
-.names inst_VMA_INTreg.BLIF VMA_INT_i
-0 1
-.names state_machine_un15_clk_000_d_n.BLIF vma_int_0_un3_n
-0 1
-.names cpu_est_0_.BLIF cpu_est_i_0__n
-0 1
-.names state_machine_un8_clk_000_d_1_i_0_n.BLIF \
-state_machine_un15_clk_000_d_n.BLIF vma_int_0_un1_n
-11 1
-.names cpu_est_1_.BLIF cpu_est_i_1__n
-0 1
-.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
-11 1
-.names cpu_est_3_reg.BLIF cpu_est_i_3__n
-0 1
-.names un1_as_030_4.BLIF uds_000_int_0_un3_n
-0 1
-.names state_machine_un8_clk_000_d_1_n.BLIF \
-state_machine_un8_clk_000_d_1_i_0_n
-0 1
-.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n
-11 1
-.names DTACK_c.BLIF DTACK_i
-0 1
-.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF \
-uds_000_int_0_un0_n
+.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n
11 1
.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n
0 1
-.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n
+.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un3_n
0 1
.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
0 1
-.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n
+.names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_1__un1_n
11 1
-.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
+.names inst_CLK_000_D1.BLIF CLK_000_D1_i
0 1
-.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n
+.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n
11 1
-.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i
+.names cpu_est_0_.BLIF cpu_est_i_0__n
0 1
-.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n
+.names AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un3_n
0 1
-.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i
+.names cpu_est_3_reg.BLIF cpu_est_i_3__n
0 1
-.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n
+.names inst_AS_000_INTreg.BLIF AS_000_INT_1_sqmuxa.BLIF as_000_int_0_un1_n
11 1
-.names N_98.BLIF N_98_i
+.names cpu_est_2_.BLIF cpu_est_i_2__n
0 1
-.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n
+.names N_101_i.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
11 1
-.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n
+.names inst_VPA_D.BLIF VPA_D_i
0 1
-.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n
+.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n
0 1
-.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i
+.names inst_VMA_INTreg.BLIF VMA_INT_i
0 1
-.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n
+.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n
11 1
-.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i
+.names cpu_est_1_.BLIF cpu_est_i_1__n
0 1
-.names N_98_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n
+.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
11 1
-.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
+.names state_machine_un13_clk_000_d0_2_n.BLIF \
+state_machine_un13_clk_000_d0_2_i_n
0 1
.names state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un3_n
0 1
-.names DS_030_c.BLIF DS_030_i
+.names state_machine_un13_clk_000_d0_1_n.BLIF \
+state_machine_un13_clk_000_d0_1_i_n
0 1
.names state_machine_as_030_000_sync_3_n.BLIF \
state_machine_un17_clk_030_n.BLIF as_030_000_sync_0_un1_n
11 1
-.names cpu_est_2_.BLIF cpu_est_i_2__n
+.names DTACK_c.BLIF DTACK_i
0 1
.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \
as_030_000_sync_0_un0_n
11 1
-.names state_machine_un13_clk_000_d_2_n.BLIF \
-state_machine_un13_clk_000_d_2_i_n
+.names DTACK_SYNC_1_sqmuxa.BLIF DTACK_SYNC_1_sqmuxa_i
0 1
.names state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un3_n
0 1
-.names inst_CLK_000_DD.BLIF CLK_000_DD_i
+.names a_c_18__n.BLIF a_i_18__n
0 1
.names un1_as_030_3.BLIF state_machine_un17_clk_030_n.BLIF fpu_cs_int_0_un1_n
11 1
-.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
+.names a_c_16__n.BLIF a_i_16__n
0 1
.names inst_FPU_CS_INTreg.BLIF fpu_cs_int_0_un3_n.BLIF fpu_cs_int_0_un0_n
11 1
+.names a_c_19__n.BLIF a_i_19__n
+0 1
+.names DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un3_n
+0 1
.names CLK_030_c.BLIF CLK_030_i
0 1
-.names un1_as_030_4.BLIF lds_000_int_0_un3_n
-0 1
-.names a_c_30__n.BLIF a_i_30__n
-0 1
-.names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n
+.names inst_DTACK_SYNC.BLIF DTACK_SYNC_1_sqmuxa_1.BLIF dtack_sync_0_un1_n
11 1
-.names a_c_31__n.BLIF a_i_31__n
+.names state_machine_un42_clk_030_n.BLIF state_machine_un42_clk_030_i_n
0 1
-.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF \
-lds_000_int_0_un0_n
+.names DTACK_SYNC_1_sqmuxa_i.BLIF dtack_sync_0_un3_n.BLIF dtack_sync_0_un0_n
11 1
-.names a_c_28__n.BLIF a_i_28__n
+.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
0 1
-.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_3__un3_n
+.names state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un3_n
0 1
-.names a_c_29__n.BLIF a_i_29__n
+.names SM_AMIGA_7_.BLIF sm_amiga_i_7__n
0 1
-.names clk_cpu_est_11_3__n.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_3__un1_n
+.names N_124.BLIF state_machine_un15_clk_000_d0_n.BLIF vma_int_0_un1_n
11 1
-.names a_c_26__n.BLIF a_i_26__n
+.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
0 1
-.names cpu_est_3_reg.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n
+.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
11 1
-.names a_c_27__n.BLIF a_i_27__n
+.names DS_030_c.BLIF DS_030_i
0 1
-.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_2__un3_n
+.names clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un3_n
0 1
-.names a_c_24__n.BLIF a_i_24__n
+.names UDS_000_INT_0_sqmuxa_1.BLIF UDS_000_INT_0_sqmuxa_1_i
0 1
-.names N_122_i.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_2__un1_n
+.names N_121_i.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_2__un1_n
11 1
-.names a_c_25__n.BLIF a_i_25__n
+.names UDS_000_INT_0_sqmuxa.BLIF UDS_000_INT_0_sqmuxa_i
0 1
.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n
11 1
-.names a_c_19__n.BLIF a_i_19__n
+.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
0 1
-.names state_machine_un1_clk_030_n.BLIF bg_000_0_un3_n
+.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un3_n
0 1
-.names a_c_16__n.BLIF a_i_16__n
+.names VPA_SYNC_1_sqmuxa.BLIF VPA_SYNC_1_sqmuxa_i
0 1
-.names un1_bg_030.BLIF state_machine_un1_clk_030_n.BLIF bg_000_0_un1_n
+.names ipl_c_0__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_0__un1_n
11 1
-.names a_c_18__n.BLIF a_i_18__n
+.names N_97.BLIF N_97_i
0 1
-.names BG_000DFFSHreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
+.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
11 1
+.names a_c_30__n.BLIF a_i_30__n
+0 1
+.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un3_n
+0 1
+.names a_c_31__n.BLIF a_i_31__n
+0 1
+.names ipl_c_1__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_1__un1_n
+11 1
+.names a_c_28__n.BLIF a_i_28__n
+0 1
+.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
+11 1
+.names a_c_29__n.BLIF a_i_29__n
+0 1
+.names clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un3_n
+0 1
+.names a_c_26__n.BLIF a_i_26__n
+0 1
+.names ipl_c_2__n.BLIF clk_un4_clk_000_d1_n.BLIF ipl_030_0_2__un1_n
+11 1
+.names a_c_27__n.BLIF a_i_27__n
+0 1
+.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
+11 1
+.names a_c_24__n.BLIF a_i_24__n
+0 1
.names state_machine_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n
0 1
-.names RST_c.BLIF RST_i
+.names a_c_25__n.BLIF a_i_25__n
0 1
.names BGACK_000_c.BLIF state_machine_un6_bgack_000_n.BLIF \
bgack_030_int_0_un1_n
@@ -882,35 +867,37 @@ bgack_030_int_0_un1_n
.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \
bgack_030_int_0_un0_n
11 1
+.names RST_c.BLIF RST_i
+0 1
+.names un1_as_030_4.BLIF uds_000_int_0_un3_n
+0 1
+.names inst_UDS_000_INTreg.BLIF un1_as_030_4.BLIF uds_000_int_0_un1_n
+11 1
.names inst_FPU_CS_INTreg.BLIF FPU_CS_INT_i
0 1
-.names clk_un4_clk_000_dd_n.BLIF cpu_est_0_1__un3_n
-0 1
-.names CPU_SPACE_c.BLIF CPU_SPACE_i
-0 1
-.names clk_cpu_est_11_1__n.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_1__un1_n
+.names state_machine_uds_000_int_8_n.BLIF uds_000_int_0_un3_n.BLIF \
+uds_000_int_0_un0_n
11 1
.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
0 1
-.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n
-11 1
-.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_0__un3_n
+.names un1_as_030_4.BLIF lds_000_int_0_un3_n
0 1
-.names ipl_c_0__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_0__un1_n
+.names inst_LDS_000_INTreg.BLIF un1_as_030_4.BLIF lds_000_int_0_un1_n
11 1
-.names IPL_030DFFSH_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
+.names state_machine_lds_000_int_8_n.BLIF lds_000_int_0_un3_n.BLIF \
+lds_000_int_0_un0_n
11 1
-.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_1__un3_n
+.names VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un3_n
0 1
-.names ipl_c_1__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_1__un1_n
+.names inst_VPA_SYNC.BLIF VPA_SYNC_1_sqmuxa_1.BLIF vpa_sync_0_un1_n
11 1
-.names IPL_030DFFSH_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
+.names VPA_SYNC_1_sqmuxa_i.BLIF vpa_sync_0_un3_n.BLIF vpa_sync_0_un0_n
11 1
-.names clk_un4_clk_000_dd_n.BLIF ipl_030_0_2__un3_n
+.names DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un3_n
0 1
-.names ipl_c_2__n.BLIF clk_un4_clk_000_dd_n.BLIF ipl_030_0_2__un1_n
+.names DSACK_INT_1_.BLIF DSACK_INT_1_sqmuxa.BLIF dsack_int_0_1__un1_n
11 1
-.names IPL_030DFFSH_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
+.names N_97_i.BLIF dsack_int_0_1__un3_n.BLIF dsack_int_0_1__un0_n
11 1
.names IPL_030DFFSH_2_reg.BLIF IPL_030_2_
1 1
@@ -957,7 +944,7 @@ bgack_030_int_0_un0_n
.names RESETDFFreg.BLIF RESET
1 1
0 0
-.names gnd_n_n.BLIF AMIGA_BUS_ENABLE
+.names nEXP_SPACE_i.BLIF AMIGA_BUS_ENABLE
1 1
0 0
.names RW_i.BLIF AMIGA_BUS_DATA_DIR
@@ -966,7 +953,7 @@ bgack_030_int_0_un0_n
.names vcc_n_n.BLIF AMIGA_BUS_ENABLE_LOW
1 1
0 0
-.names N_171.BLIF CIIN
+.names N_170.BLIF CIIN
1 1
0 0
.names IPL_030DFFSH_1_reg.BLIF IPL_030_1_
@@ -1143,10 +1130,10 @@ bgack_030_int_0_un0_n
.names CLK_OSZI_c.BLIF inst_VPA_D.C
1 1
0 0
-.names CLK_000.BLIF inst_CLK_000_D.D
+.names CLK_000.BLIF inst_CLK_000_D0.D
1 1
0 0
-.names CLK_OSZI_c.BLIF inst_CLK_000_D.C
+.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C
1 1
0 0
.names RST_c.BLIF RESETDFFreg.D
@@ -1155,10 +1142,10 @@ bgack_030_int_0_un0_n
.names CLK_OSZI_c.BLIF RESETDFFreg.C
1 1
0 0
-.names inst_CLK_000_D.BLIF inst_CLK_000_DD.D
+.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
1 1
0 0
-.names CLK_OSZI_c.BLIF inst_CLK_000_DD.C
+.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C
1 1
0 0
.names inst_CLK_OUT_PRE.BLIF CLK_OUT_INTreg.D
@@ -1212,18 +1199,18 @@ bgack_030_int_0_un0_n
.names SIZE_0_.BLIF size_c_0__n
1 1
0 0
-.names SIZE_1_.BLIF size_c_1__n
-1 1
-0 0
.names A_15_.BLIF a_15__n
1 1
0 0
-.names A_0_.BLIF a_c_0__n
+.names SIZE_1_.BLIF size_c_1__n
1 1
0 0
.names A_14_.BLIF a_14__n
1 1
0 0
+.names A_0_.BLIF a_c_0__n
+1 1
+0 0
.names A_13_.BLIF a_13__n
1 1
0 0
@@ -1311,7 +1298,7 @@ bgack_030_int_0_un0_n
.names A_31_.BLIF a_c_31__n
1 1
0 0
-.names CPU_SPACE.BLIF CPU_SPACE_c
+.names nEXP_SPACE.BLIF nEXP_SPACE_c
1 1
0 0
.names BG_030.BLIF BG_030_c
@@ -1326,7 +1313,7 @@ bgack_030_int_0_un0_n
.names CLK_OSZI.BLIF CLK_OSZI_c
1 1
0 0
-.names CPU_SPACE_i.BLIF DSACK_1_.OE
+.names nEXP_SPACE_c.BLIF DSACK_1_.OE
1 1
0 0
.names BGACK_030_INT_i.BLIF DTACK.OE
@@ -1344,16 +1331,16 @@ bgack_030_int_0_un0_n
.names FPU_CS_INT_i.BLIF BERR.OE
1 1
0 0
-.names CPU_SPACE_i.BLIF DSACK_0_.OE
+.names nEXP_SPACE_c.BLIF DSACK_0_.OE
1 1
0 0
.names FPU_CS_INT_i.BLIF AVEC_EXP.OE
1 1
0 0
-.names N_168.BLIF CIIN.OE
+.names N_167.BLIF CIIN.OE
1 1
0 0
-.names cpu_est_0_.BLIF clk_un4_clk_000_dd_n.BLIF cpu_est_0_0_
+.names cpu_est_0_.BLIF clk_un4_clk_000_d1_n.BLIF cpu_est_0_0_
01 1
10 1
11 0
diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi
index a436852..556c3c3 100644
--- a/Logic/BUS68030.edi
+++ b/Logic/BUS68030.edi
@@ -4,7 +4,7 @@
(keywordMap (keywordLevel 0))
(status
(written
- (timeStamp 2014 5 15 23 2 41)
+ (timeStamp 2014 5 16 17 7 4)
(author "Synopsys, Inc.")
(program "Synplify Pro" (version "G-2012.09LC-SP1 , mapper maplat, Build 621R"))
)
@@ -129,7 +129,7 @@
(port DS_030 (direction INPUT))
(port UDS_000 (direction OUTPUT))
(port LDS_000 (direction OUTPUT))
- (port CPU_SPACE (direction INPUT))
+ (port nEXP_SPACE (direction INPUT))
(port BERR (direction OUTPUT))
(port BG_030 (direction INPUT))
(port BG_000 (direction OUTPUT))
@@ -216,11 +216,11 @@
)
(instance VPA_D (viewRef prim (cellRef DFF (libraryRef mach)))
)
- (instance CLK_000_D (viewRef prim (cellRef DFF (libraryRef mach)))
+ (instance CLK_000_D0 (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance RESETDFF (viewRef prim (cellRef DFF (libraryRef mach)))
)
- (instance CLK_000_DD (viewRef prim (cellRef DFF (libraryRef mach)))
+ (instance CLK_000_D1 (viewRef prim (cellRef DFF (libraryRef mach)))
)
(instance CLK_OUT_INT (viewRef prim (cellRef DFF (libraryRef mach)))
)
@@ -248,7 +248,7 @@
(instance (rename A_29 "A[29]") (viewRef prim (cellRef IBUF (libraryRef mach))) )
(instance (rename A_30 "A[30]") (viewRef prim (cellRef IBUF (libraryRef mach))) )
(instance (rename A_31 "A[31]") (viewRef prim (cellRef IBUF (libraryRef mach))) )
- (instance CPU_SPACE (viewRef prim (cellRef IBUF (libraryRef mach))) )
+ (instance nEXP_SPACE (viewRef prim (cellRef IBUF (libraryRef mach))) )
(instance BERR (viewRef prim (cellRef BUFTH (libraryRef mach))) )
(instance BG_030 (viewRef prim (cellRef IBUF (libraryRef mach))) )
(instance BG_000 (viewRef prim (cellRef OBUF (libraryRef mach))) )
@@ -283,12 +283,10 @@
(instance AMIGA_BUS_DATA_DIR (viewRef prim (cellRef OBUF (libraryRef mach))) )
(instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) )
(instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) )
- (instance (rename state_machine_un8_clk_000_d_2 "state_machine.un8_clk_000_d_2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un8_clk_000_d_3 "state_machine.un8_clk_000_d_3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un8_clk_000_d "state_machine.un8_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un13_clk_000_d_1_0 "state_machine.un13_clk_000_d_1_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un13_clk_000_d_2_0 "state_machine.un13_clk_000_d_2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un13_clk_000_d "state_machine.un13_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un8_clk_000_d0 "state_machine.un8_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un13_clk_000_d0_1_0 "state_machine.un13_clk_000_d0_1_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un13_clk_000_d0_2_0 "state_machine.un13_clk_000_d0_2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un13_clk_000_d0 "state_machine.un13_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance VPA_SYNC_1_sqmuxa_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance VPA_SYNC_1_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance VPA_SYNC_1_sqmuxa_3_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
@@ -296,189 +294,171 @@
(instance VPA_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename SM_AMIGA_ns_a2_0_1_5 "SM_AMIGA_ns_a2_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename SM_AMIGA_ns_a2_0_5 "SM_AMIGA_ns_a2_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un1_DSACK_INT_0_sqmuxa_i_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un1_DSACK_INT_0_sqmuxa_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un42_clk_030 "state_machine.un42_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_i_a4_0_1_2 "clk.cpu_est_11_i_a4_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_i_a4_0_2 "clk.cpu_est_11_i_a4_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_i_a4_1_2 "clk.cpu_est_11_i_a4_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_i_a4_2 "clk.cpu_est_11_i_a4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance UDS_000_INT_0_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance UDS_000_INT_0_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance UDS_000_INT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance UDS_000_INT_0_sqmuxa_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance UDS_000_INT_0_sqmuxa_1_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance UDS_000_INT_0_sqmuxa_1_3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance UDS_000_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance DTACK_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance DTACK_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un8_clk_000_d_1_0 "state_machine.un8_clk_000_d_1_0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un8_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un4_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un4_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un4_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un1_bg_030_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un1_bg_030_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un1_bg_030 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_1_1 "clk.cpu_est_11_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_2_1 "clk.cpu_est_11_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un42_clk_030_1 "state_machine.un42_clk_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename state_machine_un42_clk_030_2 "state_machine.un42_clk_030_2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename state_machine_un42_clk_030_3 "state_machine.un42_clk_030_3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename state_machine_un42_clk_030_4 "state_machine.un42_clk_030_4") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename state_machine_un42_clk_030_5 "state_machine.un42_clk_030_5") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_un4_clk_000_dd_i "clk.un4_clk_000_dd_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_un6_bgack_000_i "state_machine.un6_bgack_000_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_un1_clk_030_i "state_machine.un1_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un34_clk_000_d_1 "state_machine.un34_clk_000_d_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un34_clk_000_d "state_machine.un34_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un42_clk_030 "state_machine.un42_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance DTACK_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance DTACK_SYNC_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_i_a4_1_2 "clk.cpu_est_11_i_a4_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_i_a4_2 "clk.cpu_est_11_i_a4[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_i_a4_0_1_2 "clk.cpu_est_11_i_a4_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_i_a4_0_2 "clk.cpu_est_11_i_a4_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un8_clk_000_d0_1 "state_machine.un8_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un8_clk_000_d0_2 "state_machine.un8_clk_000_d0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un8_clk_000_d0_3 "state_machine.un8_clk_000_d0_3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un8_clk_000_d0_4 "state_machine.un8_clk_000_d0_4") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un8_ciin_6 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un8_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un4_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un4_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un4_ciin (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance UDS_000_INT_0_sqmuxa_1_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance UDS_000_INT_0_sqmuxa_1_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance UDS_000_INT_0_sqmuxa_1_3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance UDS_000_INT_0_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance UDS_000_INT_0_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance UDS_000_INT_0_sqmuxa_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance UDS_000_INT_0_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un34_clk_000_d0_1 "state_machine.un34_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un34_clk_000_d0 "state_machine.un34_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un42_clk_030_1 "state_machine.un42_clk_030_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_bg_030_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_bg_030_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_bg_030 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename state_machine_AS_030_000_SYNC_3_1 "state_machine.AS_030_000_SYNC_3_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename state_machine_AS_030_000_SYNC_3 "state_machine.AS_030_000_SYNC_3") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_1_1 "clk.cpu_est_11_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_2_1 "clk.cpu_est_11_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un8_ciin_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un8_ciin_2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un8_ciin_3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un8_ciin_4 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance un8_ciin_5 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un8_ciin_6 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance N_134_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_133_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_135_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_i_3 "clk.cpu_est_11_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_i_1 "clk.cpu_est_11_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_128_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance un1_bg_030_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_97_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_127_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_129_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename clk_un4_clk_000_d1_i "clk.un4_clk_000_d1_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un6_bgack_000_i "state_machine.un6_bgack_000_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_98_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_111_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_99_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename SM_AMIGA_ns_i_o2_i_1 "SM_AMIGA_ns_i_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_100_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_112_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_103_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_un60_clk_000_d_i_0 "state_machine.un60_clk_000_d_i_0") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un34_clk_000_d0_i_0 "state_machine.un34_clk_000_d0_i_0") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_102_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_144_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_LDS_000_INT_8_i "state_machine.LDS_000_INT_8_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_UDS_000_INT_8_i "state_machine.UDS_000_INT_8_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un60_clk_000_d0_i_0 "state_machine.un60_clk_000_d0_i_0") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_o4_i_1 "clk.cpu_est_11_0_o4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_130_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_131_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_o2_i_0 "SM_AMIGA_ns_i_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_109_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_7 "SM_AMIGA_ns_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un8_clk_000_d0_i "state_machine.un8_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un13_clk_000_d0_i "state_machine.un13_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un15_clk_000_d0_i "state_machine.un15_clk_000_d0_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un1_clk_030_i "state_machine.un1_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename state_machine_un17_clk_030_i "state_machine.un17_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance un1_as_030_3_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_145_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_c_i_0 "A_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_UDS_000_INT_8_i "state_machine.UDS_000_INT_8_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_LDS_000_INT_8_i "state_machine.LDS_000_INT_8_i") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename state_machine_AS_030_000_SYNC_3_i "state_machine.AS_030_000_SYNC_3_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_un34_clk_000_d_i_0 "state_machine.un34_clk_000_d_i_0") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_131_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_o4_i_1 "clk.cpu_est_11_0_o4_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_o4_i_3 "clk.cpu_est_11_0_o4_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_106_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_5 "SM_AMIGA_ns_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_108_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_109_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_110_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_7 "SM_AMIGA_ns_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_i_0 "SM_AMIGA_ns_i_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance CLK_OUT_PRE_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_i_6 "SM_AMIGA_ns_i_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_un8_clk_000_d_i "state_machine.un8_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_un13_clk_000_d_i "state_machine.un13_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_un15_clk_000_d_i "state_machine.un15_clk_000_d_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_i_4 "SM_AMIGA_ns_i_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_104_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_105_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_99_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance N_101_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_2 "SM_AMIGA_ns_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_96_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance N_107_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_a2_5 "SM_AMIGA_ns_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_a2_2 "SM_AMIGA_ns_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_a2_0 "SM_AMIGA_ns_i_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance AS_030_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance AS_000_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance N_108_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_6 "SM_AMIGA_ns_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_o2_i_6 "SM_AMIGA_ns_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_o2_i_4 "SM_AMIGA_ns_i_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_128_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_126_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_127_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_129_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_i_1 "clk.cpu_est_11_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_133_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_134_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_i_3 "clk.cpu_est_11_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_o4_i_3 "clk.cpu_est_11_0_o4_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_100_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_2 "SM_AMIGA_ns_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_103_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_104_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_106_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_105_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_5 "SM_AMIGA_ns_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance I_106 (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance I_104 (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename state_machine_un13_as_000_int "state_machine.un13_as_000_int") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance N_102_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance N_101_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
(instance RW_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_un13_clk_000_d_1 "state_machine.un13_clk_000_d_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_6 "SM_AMIGA_ns_i_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_0 "SM_AMIGA_ns_i_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_7 "SM_AMIGA_ns[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_6 "SM_AMIGA_ns_i[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_5 "SM_AMIGA_ns[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance nEXP_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename SM_AMIGA_ns_2 "SM_AMIGA_ns[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_0 "SM_AMIGA_ns_i[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un13_clk_000_d_1_i "state_machine.un13_clk_000_d_1_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_a2_7 "SM_AMIGA_ns_a2[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_a2_0_6 "SM_AMIGA_ns_i_a2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_a2_6 "SM_AMIGA_ns_i_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance CLK_000_D_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename clk_un4_clk_000_d1_0_a2 "clk.un4_clk_000_d1_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_a2_0_6 "SM_AMIGA_ns_a2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_a2_6 "SM_AMIGA_ns_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_a2_5 "SM_AMIGA_ns_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_4 "SM_AMIGA_ns_i_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance I_107 (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_a2_0_4 "SM_AMIGA_ns_i_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_a2_4 "SM_AMIGA_ns_i_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_a2_2 "SM_AMIGA_ns_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_DSACK_INT_0_sqmuxa_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_030_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance AS_000_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance VPA_SYNC_1_sqmuxa_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un8_clk_000_d_1_i "state_machine.un8_clk_000_d_1_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
- (instance (rename state_machine_un15_clk_000_d "state_machine.un15_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un8_clk_000_d_1 "state_machine.un8_clk_000_d_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un13_clk_000_d0_1 "state_machine.un13_clk_000_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_a4_0_3 "clk.cpu_est_11_0_a4_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_a4_3 "clk.cpu_est_11_0_a4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_a4_1_1 "clk.cpu_est_11_0_a4_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_a4_0_1 "clk.cpu_est_11_0_a4_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_a4_1 "clk.cpu_est_11_0_a4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_o2_4 "SM_AMIGA_ns_i_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_o2_6 "SM_AMIGA_ns_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_6 "SM_AMIGA_ns[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_5 "SM_AMIGA_ns[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_7 "SM_AMIGA_ns[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_o2_0 "SM_AMIGA_ns_i_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_a4_2_1 "clk.cpu_est_11_0_a4_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_i_2 "clk.cpu_est_11_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_o4_1 "clk.cpu_est_11_0_o4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_o4_3 "clk.cpu_est_11_0_o4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un13_clk_000_d0_2_i "state_machine.un13_clk_000_d0_2_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename clk_cpu_est_11_0_a4_1_3 "clk.cpu_est_11_0_a4_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un13_clk_000_d0_2 "state_machine.un13_clk_000_d0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance VPA_SYNC_1_sqmuxa_3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) )
(instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename cpu_est_0_0 "cpu_est_0[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) )
(instance CLK_OUT_PRE_0 (viewRef prim (cellRef XOR2 (libraryRef mach))) )
- (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
- (instance (rename state_machine_un60_clk_000_d "state_machine.un60_clk_000_d") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename DTACK_SYNC_0_r "DTACK_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename DTACK_SYNC_0_m "DTACK_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename DTACK_SYNC_0_n "DTACK_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename DTACK_SYNC_0_p "DTACK_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
- (instance (rename VPA_SYNC_0_r "VPA_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename VPA_SYNC_0_m "VPA_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename VPA_SYNC_0_n "VPA_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename VPA_SYNC_0_p "VPA_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
- (instance VPA_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance VPA_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance DTACK_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance DTACK_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_a2_3 "SM_AMIGA_ns_i_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_a2_4 "SM_AMIGA_ns_i_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_a2_0_4 "SM_AMIGA_ns_i_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_3 "SM_AMIGA_ns_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_4 "SM_AMIGA_ns_i[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance UDS_000_INT_0_sqmuxa_1_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance UDS_000_INT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance un1_as_030_4_93 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_LDS_000_INT_8 "state_machine.LDS_000_INT_8") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_UDS_000_INT_8 "state_machine.UDS_000_INT_8") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance un1_as_030_4 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un42_clk_030_i "state_machine.un42_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance un1_as_030_3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance DSACK_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un17_clk_030 "state_machine.un17_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance N_98_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename DSACK_INT_0_1__r "DSACK_INT_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename DSACK_INT_0_1__m "DSACK_INT_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename DSACK_INT_0_1__n "DSACK_INT_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename DSACK_INT_0_1__p "DSACK_INT_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
(instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
@@ -487,75 +467,20 @@
(instance (rename FPU_CS_INT_0_m "FPU_CS_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename FPU_CS_INT_0_n "FPU_CS_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename FPU_CS_INT_0_p "FPU_CS_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
- (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
- (instance (rename state_machine_un13_clk_000_d_2 "state_machine.un13_clk_000_d_2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_a4_1_3 "clk.cpu_est_11_0_a4_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un13_clk_000_d_2_i "state_machine.un13_clk_000_d_2_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_o4_3 "clk.cpu_est_11_0_o4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_o4_1 "clk.cpu_est_11_0_o4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_i_2 "clk.cpu_est_11_i[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_a4_0_3 "clk.cpu_est_11_0_a4_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_a4_3 "clk.cpu_est_11_0_a4[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_a4_2_1 "clk.cpu_est_11_0_a4_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_a4_0_1 "clk.cpu_est_11_0_a4_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance DTACK_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename DTACK_SYNC_0_r "DTACK_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename DTACK_SYNC_0_m "DTACK_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename DTACK_SYNC_0_n "DTACK_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename DTACK_SYNC_0_p "DTACK_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance I_105 (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
(instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
- (instance DS_030_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_un1_clk_030 "state_machine.un1_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename state_machine_un5_clk_030_i_a2 "state_machine.un5_clk_030_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_a2_1 "SM_AMIGA_ns_i_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_a2_0_2 "SM_AMIGA_ns_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance CLK_000_DD_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename clk_un4_clk_000_dd_0_a2 "clk.un4_clk_000_dd_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_a2_0_1 "SM_AMIGA_ns_i_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_1 "SM_AMIGA_ns_i[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename SM_AMIGA_ns_i_o2_1 "SM_AMIGA_ns_i_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_a4_1 "clk.cpu_est_11_0_a4[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename clk_cpu_est_11_0_a4_1_1 "clk.cpu_est_11_0_a4_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_0_0 "cpu_est_0[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) )
- (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_27 "A_i[27]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename state_machine_un13_as_000_int_i "state_machine.un13_as_000_int_i") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename CLK_CNT_i_0 "CLK_CNT_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance CPU_SPACE_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance FPU_CS_INT_i (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
- (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
- (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) )
- (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
- (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
(instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) )
(instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
@@ -568,10 +493,81 @@
(instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
(instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance (rename state_machine_un15_clk_000_d0 "state_machine.un15_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un13_clk_000_d0_1_i "state_machine.un13_clk_000_d0_1_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_a2_7 "SM_AMIGA_ns_a2[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_a2_1 "SM_AMIGA_ns_i_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_a2_0 "SM_AMIGA_ns_i_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un5_clk_030_i_a2 "state_machine.un5_clk_030_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance DTACK_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un42_clk_030_i "state_machine.un42_clk_030_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance un1_as_030_3 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un17_clk_030 "state_machine.un17_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un1_clk_030 "state_machine.un1_clk_030") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_UDS_000_INT_8 "state_machine.UDS_000_INT_8") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_LDS_000_INT_8 "state_machine.LDS_000_INT_8") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_a2_3 "SM_AMIGA_ns_i_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_3 "SM_AMIGA_ns_i[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance UDS_000_INT_0_sqmuxa_1_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance UDS_000_INT_0_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance un1_as_030_4_91 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance DS_030_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_o2_1 "SM_AMIGA_ns_i_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_1 "SM_AMIGA_ns_i[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_0 "SM_AMIGA_ns_i[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_i_a2_0_1 "SM_AMIGA_ns_i_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename SM_AMIGA_ns_a2_0_2 "SM_AMIGA_ns_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_27 "A_i[27]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance N_97_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance DSACK_INT_1_sqmuxa (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance VPA_SYNC_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance VPA_SYNC_1_sqmuxa_1 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance un1_as_030_4 (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename state_machine_un13_as_000_int_i "state_machine.un13_as_000_int_i") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename CLK_CNT_i_0 "CLK_CNT_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename state_machine_un60_clk_000_d0 "state_machine.un60_clk_000_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance FPU_CS_INT_i (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance (rename VPA_SYNC_0_r "VPA_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename VPA_SYNC_0_m "VPA_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename VPA_SYNC_0_n "VPA_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename VPA_SYNC_0_p "VPA_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
+ (instance (rename DSACK_INT_0_1__r "DSACK_INT_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) )
+ (instance (rename DSACK_INT_0_1__m "DSACK_INT_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename DSACK_INT_0_1__n "DSACK_INT_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) )
+ (instance (rename DSACK_INT_0_1__p "DSACK_INT_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) )
(net BGACK_030_INT (joined
(portRef Q (instanceRef BGACK_030_INT))
- (portRef I0 (instanceRef BGACK_030_INT_0_n))
(portRef I0 (instanceRef BGACK_030_INT_i))
+ (portRef I0 (instanceRef BGACK_030_INT_0_n))
(portRef OE (instanceRef AS_000))
(portRef I0 (instanceRef BGACK_030))
(portRef OE (instanceRef LDS_000))
@@ -585,45 +581,40 @@
))
(net (rename cpu_est_3 "cpu_est[3]") (joined
(portRef Q (instanceRef cpu_est_3))
- (portRef I0 (instanceRef cpu_est_0_3__n))
(portRef I0 (instanceRef clk_cpu_est_11_0_a4_2_1))
- (portRef I1 (instanceRef clk_cpu_est_11_0_a4_3))
(portRef I0 (instanceRef cpu_est_i_3))
+ (portRef I1 (instanceRef clk_cpu_est_11_0_a4_3))
+ (portRef I0 (instanceRef cpu_est_0_3__n))
(portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_1))
(portRef I0 (instanceRef E))
))
(net VMA_INT (joined
(portRef Q (instanceRef VMA_INT))
- (portRef I0 (instanceRef VMA_INT_i))
(portRef I0 (instanceRef VMA_INT_0_n))
+ (portRef I0 (instanceRef VMA_INT_i))
(portRef I0 (instanceRef VMA))
))
- (net GND (joined
- (portRef I0 (instanceRef AMIGA_BUS_ENABLE))
- (portRef I0 (instanceRef AVEC_EXP))
- (portRef I0 (instanceRef BERR))
- ))
(net (rename cpu_est_0 "cpu_est[0]") (joined
(portRef Q (instanceRef cpu_est_0))
(portRef I1 (instanceRef cpu_est_0_0))
- (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_1))
(portRef I0 (instanceRef clk_cpu_est_11_0_o4_3))
(portRef I0 (instanceRef cpu_est_i_0))
- (portRef I1 (instanceRef state_machine_un8_clk_000_d_1))
+ (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_1))
+ (portRef I0 (instanceRef state_machine_un8_clk_000_d0_3))
(portRef I0 (instanceRef clk_cpu_est_11_i_a4_1_2))
))
(net (rename cpu_est_1 "cpu_est[1]") (joined
(portRef Q (instanceRef cpu_est_1))
- (portRef I0 (instanceRef cpu_est_0_1__n))
- (portRef I1 (instanceRef clk_cpu_est_11_0_o4_3))
- (portRef I0 (instanceRef state_machine_un13_clk_000_d_2))
(portRef I0 (instanceRef cpu_est_i_1))
+ (portRef I0 (instanceRef state_machine_un13_clk_000_d0_2))
+ (portRef I1 (instanceRef clk_cpu_est_11_0_o4_3))
+ (portRef I0 (instanceRef cpu_est_0_1__n))
(portRef I0 (instanceRef clk_cpu_est_11_i_a4_0_1_2))
))
(net AS_000_INT (joined
(portRef Q (instanceRef AS_000_INT))
(portRef I0 (instanceRef SM_AMIGA_ns_i_o2_0))
- (portRef I0 (instanceRef state_machine_un13_clk_000_d_1))
+ (portRef I0 (instanceRef state_machine_un13_clk_000_d0_1))
(portRef I0 (instanceRef AS_000_INT_0_m))
(portRef I0 (instanceRef AS_000_INT_i))
(portRef I0 (instanceRef AS_000))
@@ -635,8 +626,8 @@
))
(net DTACK_SYNC (joined
(portRef Q (instanceRef DTACK_SYNC))
+ (portRef I0 (instanceRef state_machine_un60_clk_000_d0))
(portRef I0 (instanceRef DTACK_SYNC_0_m))
- (portRef I0 (instanceRef state_machine_un60_clk_000_d))
))
(net VPA_D (joined
(portRef Q (instanceRef VPA_D))
@@ -646,28 +637,28 @@
(net VPA_SYNC (joined
(portRef Q (instanceRef VPA_SYNC))
(portRef I0 (instanceRef VPA_SYNC_0_m))
- (portRef I1 (instanceRef state_machine_un60_clk_000_d))
+ (portRef I1 (instanceRef state_machine_un60_clk_000_d0))
))
- (net CLK_000_D (joined
- (portRef Q (instanceRef CLK_000_D))
- (portRef I0 (instanceRef clk_un4_clk_000_dd_0_a2))
- (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_0))
- (portRef I0 (instanceRef CLK_000_D_i))
+ (net CLK_000_D0 (joined
+ (portRef Q (instanceRef CLK_000_D0))
(portRef I0 (instanceRef SM_AMIGA_ns_i_0))
- (portRef I1 (instanceRef state_machine_un13_clk_000_d_1))
+ (portRef I1 (instanceRef state_machine_un13_clk_000_d0_1))
+ (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_0))
(portRef I0 (instanceRef SM_AMIGA_ns_a2_2))
+ (portRef I0 (instanceRef CLK_000_D0_i))
+ (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_6))
+ (portRef I0 (instanceRef clk_un4_clk_000_d1_0_a2))
(portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_0))
- (portRef D (instanceRef CLK_000_DD))
+ (portRef D (instanceRef CLK_000_D1))
))
- (net CLK_000_DD (joined
- (portRef Q (instanceRef CLK_000_DD))
- (portRef I0 (instanceRef CLK_000_DD_i))
+ (net CLK_000_D1 (joined
+ (portRef Q (instanceRef CLK_000_D1))
+ (portRef I0 (instanceRef CLK_000_D1_i))
))
(net CLK_OUT_PRE (joined
(portRef Q (instanceRef CLK_OUT_PRE))
(portRef I1 (instanceRef CLK_OUT_PRE_0))
- (portRef I0 (instanceRef CLK_OUT_PRE_i))
- (portRef I1 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2_1))
+ (portRef I1 (instanceRef SM_AMIGA_ns_o2_6))
(portRef D (instanceRef CLK_OUT_INT))
))
(net VCC (joined
@@ -675,13 +666,17 @@
(portRef I0 (instanceRef AVEC))
(portRef I0 (instanceRef DSACK_0))
))
+ (net GND (joined
+ (portRef I0 (instanceRef AVEC_EXP))
+ (portRef I0 (instanceRef BERR))
+ ))
(net (rename cpu_est_2 "cpu_est[2]") (joined
(portRef Q (instanceRef cpu_est_2))
(portRef I0 (instanceRef cpu_est_0_2__n))
+ (portRef I1 (instanceRef state_machine_un13_clk_000_d0_2))
(portRef I0 (instanceRef cpu_est_i_2))
- (portRef I1 (instanceRef state_machine_un13_clk_000_d_2))
+ (portRef I1 (instanceRef state_machine_un8_clk_000_d0_3))
(portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1_1))
- (portRef I0 (instanceRef state_machine_un8_clk_000_d_2))
))
(net (rename CLK_CNT_0 "CLK_CNT[0]") (joined
(portRef Q (instanceRef CLK_CNT_0))
@@ -709,21 +704,20 @@
(portRef I0 (instanceRef LDS_000_INT_0_m))
(portRef I0 (instanceRef LDS_000))
))
- (net (rename state_machine_un1_clk_030 "state_machine.un1_clk_030") (joined
- (portRef O (instanceRef state_machine_un1_clk_030_i))
- (portRef I1 (instanceRef BG_000_0_m))
- (portRef I0 (instanceRef BG_000_0_r))
- ))
- (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined
- (portRef Q (instanceRef SM_AMIGA_1))
- (portRef I0 (instanceRef SM_AMIGA_i_1))
- (portRef I1 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2))
- ))
(net (rename DSACK_INT_1 "DSACK_INT[1]") (joined
(portRef Q (instanceRef DSACK_INT_1))
(portRef I0 (instanceRef DSACK_INT_0_1__m))
(portRef I0 (instanceRef DSACK_1))
))
+ (net (rename state_machine_un60_clk_000_d0 "state_machine.un60_clk_000_d0") (joined
+ (portRef O (instanceRef state_machine_un60_clk_000_d0_i_0))
+ (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_5))
+ ))
+ (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined
+ (portRef Q (instanceRef SM_AMIGA_1))
+ (portRef I1 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2))
+ (portRef I1 (instanceRef SM_AMIGA_ns_a2_6))
+ ))
(net DTACK_DMA (joined
(portRef Q (instanceRef DTACK_DMA))
(portRef I0 (instanceRef DTACK))
@@ -733,25 +727,33 @@
(portRef I0 (instanceRef SM_AMIGA_i_4))
(portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_2))
))
- (net (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (joined
- (portRef O (instanceRef state_machine_un6_bgack_000_i))
- (portRef I1 (instanceRef BGACK_030_INT_0_m))
- (portRef I0 (instanceRef BGACK_030_INT_0_r))
- ))
(net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined
(portRef Q (instanceRef SM_AMIGA_3))
- (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_0))
(portRef I0 (instanceRef SM_AMIGA_ns_i_o2_4))
+ (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1_0))
(portRef I0 (instanceRef SM_AMIGA_i_3))
(portRef I1 (instanceRef SM_AMIGA_ns_a2_0_1_5))
))
+ (net DSACK_INT_1_sqmuxa (joined
+ (portRef O (instanceRef DSACK_INT_1_sqmuxa))
+ (portRef I1 (instanceRef DSACK_INT_0_1__m))
+ (portRef I0 (instanceRef DSACK_INT_0_1__r))
+ ))
(net (rename state_machine_un13_as_000_int "state_machine.un13_as_000_int") (joined
(portRef O (instanceRef state_machine_un13_as_000_int))
(portRef I0 (instanceRef state_machine_un13_as_000_int_i))
))
- (net un1_bg_030 (joined
- (portRef O (instanceRef un1_bg_030_i))
- (portRef I0 (instanceRef BG_000_0_m))
+ (net VPA_SYNC_1_sqmuxa_1 (joined
+ (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1))
+ (portRef I1 (instanceRef VPA_SYNC_0_m))
+ (portRef I0 (instanceRef VPA_SYNC_0_r))
+ ))
+ (net un1_as_030_4 (joined
+ (portRef O (instanceRef un1_as_030_4))
+ (portRef I1 (instanceRef LDS_000_INT_0_m))
+ (portRef I0 (instanceRef LDS_000_INT_0_r))
+ (portRef I1 (instanceRef UDS_000_INT_0_m))
+ (portRef I0 (instanceRef UDS_000_INT_0_r))
))
(net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined
(portRef Q (instanceRef SM_AMIGA_5))
@@ -760,14 +762,22 @@
))
(net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined
(portRef Q (instanceRef SM_AMIGA_2))
- (portRef I0 (instanceRef SM_AMIGA_i_2))
(portRef I1 (instanceRef SM_AMIGA_ns_a2_5))
+ (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_6))
))
(net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined
(portRef Q (instanceRef SM_AMIGA_0))
(portRef I0 (instanceRef SM_AMIGA_ns_a2_7))
(portRef I1 (instanceRef SM_AMIGA_ns_i_o2_0))
))
+ (net (rename state_machine_LDS_000_INT_8 "state_machine.LDS_000_INT_8") (joined
+ (portRef O (instanceRef state_machine_LDS_000_INT_8_i))
+ (portRef I0 (instanceRef LDS_000_INT_0_n))
+ ))
+ (net (rename state_machine_UDS_000_INT_8 "state_machine.UDS_000_INT_8") (joined
+ (portRef O (instanceRef state_machine_UDS_000_INT_8_i))
+ (portRef I0 (instanceRef UDS_000_INT_0_n))
+ ))
(net N_1 (joined
(portRef O (instanceRef UDS_000_INT_0_p))
(portRef D (instanceRef UDS_000_INT))
@@ -852,134 +862,62 @@
(portRef O (instanceRef SM_AMIGA_ns_i_5))
(portRef D (instanceRef SM_AMIGA_2))
))
+ (net (rename SM_AMIGA_ns_6 "SM_AMIGA_ns[6]") (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_6))
+ (portRef D (instanceRef SM_AMIGA_1))
+ ))
(net (rename SM_AMIGA_ns_7 "SM_AMIGA_ns[7]") (joined
(portRef O (instanceRef SM_AMIGA_ns_i_7))
(portRef D (instanceRef SM_AMIGA_0))
))
- (net (rename clk_un4_clk_000_dd "clk.un4_clk_000_dd") (joined
- (portRef O (instanceRef clk_un4_clk_000_dd_0_a2))
+ (net (rename clk_un4_clk_000_d1 "clk.un4_clk_000_d1") (joined
+ (portRef O (instanceRef clk_un4_clk_000_d1_0_a2))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_1))
(portRef I1 (instanceRef IPL_030_0_2__m))
(portRef I0 (instanceRef IPL_030_0_2__r))
(portRef I1 (instanceRef IPL_030_0_1__m))
(portRef I0 (instanceRef IPL_030_0_1__r))
(portRef I1 (instanceRef IPL_030_0_0__m))
(portRef I0 (instanceRef IPL_030_0_0__r))
- (portRef I1 (instanceRef cpu_est_0_1__m))
- (portRef I0 (instanceRef cpu_est_0_1__r))
- (portRef I0 (instanceRef cpu_est_0_0))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_1))
(portRef I1 (instanceRef cpu_est_0_2__m))
(portRef I0 (instanceRef cpu_est_0_2__r))
+ (portRef I0 (instanceRef cpu_est_0_0))
+ (portRef I1 (instanceRef cpu_est_0_1__m))
+ (portRef I0 (instanceRef cpu_est_0_1__r))
(portRef I1 (instanceRef cpu_est_0_3__m))
(portRef I0 (instanceRef cpu_est_0_3__r))
- (portRef I0 (instanceRef clk_un4_clk_000_dd_i))
+ (portRef I0 (instanceRef clk_un4_clk_000_d1_i))
(portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1))
))
- (net (rename clk_cpu_est_11_1 "clk.cpu_est_11[1]") (joined
- (portRef O (instanceRef clk_cpu_est_11_0_i_1))
- (portRef I0 (instanceRef cpu_est_0_1__m))
+ (net N_144 (joined
+ (portRef O (instanceRef un1_as_030_4_91))
+ (portRef I1 (instanceRef un1_as_030_4))
+ (portRef I0 (instanceRef N_144_i))
))
- (net (rename state_machine_un42_clk_030 "state_machine.un42_clk_030") (joined
- (portRef O (instanceRef state_machine_un42_clk_030))
- (portRef I1 (instanceRef un1_as_030_3))
- (portRef I0 (instanceRef state_machine_un42_clk_030_i))
- ))
- (net N_102 (joined
+ (net N_101 (joined
(portRef O (instanceRef SM_AMIGA_ns_a2_0_2))
- (portRef I0 (instanceRef N_102_i))
+ (portRef I0 (instanceRef N_101_i))
))
- (net N_98 (joined
- (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2))
- (portRef I0 (instanceRef N_98_i))
+ (net VPA_SYNC_1_sqmuxa (joined
+ (portRef O (instanceRef VPA_SYNC_1_sqmuxa))
+ (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_i))
))
(net N_97 (joined
- (portRef O (instanceRef state_machine_un5_clk_030_i_a2))
+ (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2))
(portRef I0 (instanceRef N_97_i))
))
- (net N_100 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a2_1))
- (portRef I0 (instanceRef N_100_i))
- ))
- (net N_92 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_1))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_1))
- ))
- (net N_112 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_1))
- (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_2))
- (portRef I0 (instanceRef N_112_i))
- ))
- (net N_127 (joined
- (portRef O (instanceRef clk_cpu_est_11_0_a4_1))
- (portRef I0 (instanceRef N_127_i))
- ))
- (net N_125 (joined
- (portRef O (instanceRef clk_cpu_est_11_0_o4_i_1))
- (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1))
- ))
- (net N_128 (joined
- (portRef O (instanceRef clk_cpu_est_11_0_a4_0_1))
- (portRef I0 (instanceRef N_128_i))
- ))
- (net N_129 (joined
- (portRef O (instanceRef clk_cpu_est_11_0_a4_1_1))
- (portRef I0 (instanceRef N_129_i))
- ))
- (net N_130 (joined
- (portRef O (instanceRef clk_cpu_est_11_0_a4_2_1))
- (portRef I0 (instanceRef N_130_i))
- ))
- (net N_168 (joined
- (portRef O (instanceRef un8_ciin))
- (portRef OE (instanceRef CIIN))
- ))
- (net N_171 (joined
- (portRef O (instanceRef un4_ciin))
- (portRef I0 (instanceRef CIIN))
- ))
- (net N_135_1 (joined
- (portRef O (instanceRef VPA_SYNC_1_sqmuxa_3))
- (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_3))
- (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_2))
- ))
- (net (rename state_machine_un13_clk_000_d_2 "state_machine.un13_clk_000_d_2") (joined
- (portRef O (instanceRef state_machine_un13_clk_000_d_2))
- (portRef I1 (instanceRef clk_cpu_est_11_0_a4_2_1))
- (portRef I0 (instanceRef state_machine_un13_clk_000_d_2_i))
- (portRef I1 (instanceRef state_machine_un13_clk_000_d_2_0))
- ))
- (net (rename clk_cpu_est_11_3 "clk.cpu_est_11[3]") (joined
- (portRef O (instanceRef clk_cpu_est_11_0_i_3))
- (portRef I0 (instanceRef cpu_est_0_3__m))
- ))
- (net N_135 (joined
- (portRef O (instanceRef clk_cpu_est_11_0_a4_1_3))
- (portRef I0 (instanceRef N_135_i))
- ))
- (net N_133 (joined
- (portRef O (instanceRef clk_cpu_est_11_0_a4_3))
- (portRef I0 (instanceRef N_133_i))
- ))
- (net N_134 (joined
- (portRef O (instanceRef clk_cpu_est_11_0_a4_0_3))
- (portRef I0 (instanceRef N_134_i))
- ))
- (net N_132 (joined
- (portRef O (instanceRef clk_cpu_est_11_i_a4_0_2))
- (portRef I0 (instanceRef N_132_i))
- ))
- (net N_131 (joined
- (portRef O (instanceRef clk_cpu_est_11_i_a4_2))
- (portRef I0 (instanceRef N_131_i))
- ))
- (net N_126 (joined
- (portRef O (instanceRef clk_cpu_est_11_0_o4_i_3))
- (portRef I0 (instanceRef clk_cpu_est_11_0_a4_3))
- ))
- (net (rename state_machine_un34_clk_000_d "state_machine.un34_clk_000_d") (joined
- (portRef O (instanceRef state_machine_un34_clk_000_d_i_0))
+ (net (rename state_machine_un34_clk_000_d0 "state_machine.un34_clk_000_d0") (joined
+ (portRef O (instanceRef state_machine_un34_clk_000_d0_i_0))
(portRef I1 (instanceRef state_machine_LDS_000_INT_8))
))
+ (net N_96 (joined
+ (portRef O (instanceRef state_machine_un5_clk_030_i_a2))
+ (portRef I0 (instanceRef N_96_i))
+ ))
+ (net N_102 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_a2_3))
+ (portRef I0 (instanceRef N_102_i))
+ ))
(net UDS_000_INT_0_sqmuxa (joined
(portRef O (instanceRef UDS_000_INT_0_sqmuxa))
(portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_i))
@@ -988,39 +926,66 @@
(portRef O (instanceRef UDS_000_INT_0_sqmuxa_1))
(portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_i))
))
+ (net N_167 (joined
+ (portRef O (instanceRef un8_ciin))
+ (portRef OE (instanceRef CIIN))
+ ))
+ (net N_170 (joined
+ (portRef O (instanceRef un4_ciin))
+ (portRef I0 (instanceRef CIIN))
+ ))
+ (net N_92 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_1))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_1))
+ ))
+ (net N_91 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_0))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0))
+ ))
+ (net N_99 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_a2_1))
+ (portRef I0 (instanceRef N_99_i))
+ ))
+ (net N_111 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_1))
+ (portRef I0 (instanceRef SM_AMIGA_ns_a2_0_2))
+ (portRef I0 (instanceRef N_111_i))
+ ))
+ (net N_98 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_a2_0))
+ (portRef I0 (instanceRef N_98_i))
+ ))
+ (net (rename state_machine_un6_bgack_000 "state_machine.un6_bgack_000") (joined
+ (portRef O (instanceRef state_machine_un6_bgack_000_i))
+ (portRef I1 (instanceRef BGACK_030_INT_0_m))
+ (portRef I0 (instanceRef BGACK_030_INT_0_r))
+ ))
+ (net (rename state_machine_un42_clk_030 "state_machine.un42_clk_030") (joined
+ (portRef O (instanceRef state_machine_un42_clk_030))
+ (portRef I1 (instanceRef un1_as_030_3))
+ (portRef I0 (instanceRef state_machine_un42_clk_030_i))
+ ))
+ (net DTACK_SYNC_1_sqmuxa (joined
+ (portRef O (instanceRef DTACK_SYNC_1_sqmuxa))
+ (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_i))
+ ))
+ (net un1_bg_030 (joined
+ (portRef O (instanceRef un1_bg_030_i))
+ (portRef I0 (instanceRef BG_000_0_m))
+ ))
(net (rename state_machine_AS_030_000_SYNC_3 "state_machine.AS_030_000_SYNC_3") (joined
(portRef O (instanceRef state_machine_AS_030_000_SYNC_3_i))
(portRef I0 (instanceRef AS_030_000_SYNC_0_m))
))
- (net N_145 (joined
- (portRef O (instanceRef un1_as_030_4_93))
- (portRef I1 (instanceRef un1_as_030_4))
- (portRef I0 (instanceRef N_145_i))
- ))
- (net (rename state_machine_LDS_000_INT_8 "state_machine.LDS_000_INT_8") (joined
- (portRef O (instanceRef state_machine_LDS_000_INT_8_i))
- (portRef I0 (instanceRef LDS_000_INT_0_n))
- ))
- (net (rename state_machine_UDS_000_INT_8 "state_machine.UDS_000_INT_8") (joined
- (portRef O (instanceRef state_machine_UDS_000_INT_8_i))
- (portRef I0 (instanceRef UDS_000_INT_0_n))
- ))
- (net un1_as_030_4 (joined
- (portRef O (instanceRef un1_as_030_4))
- (portRef I1 (instanceRef LDS_000_INT_0_m))
- (portRef I0 (instanceRef LDS_000_INT_0_r))
- (portRef I1 (instanceRef UDS_000_INT_0_m))
- (portRef I0 (instanceRef UDS_000_INT_0_r))
+ (net DTACK_SYNC_1_sqmuxa_1 (joined
+ (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1))
+ (portRef I1 (instanceRef DTACK_SYNC_0_m))
+ (portRef I0 (instanceRef DTACK_SYNC_0_r))
))
(net un1_as_030_3 (joined
(portRef O (instanceRef un1_as_030_3_i))
(portRef I0 (instanceRef FPU_CS_INT_0_m))
))
- (net DSACK_INT_1_sqmuxa (joined
- (portRef O (instanceRef DSACK_INT_1_sqmuxa))
- (portRef I1 (instanceRef DSACK_INT_0_1__m))
- (portRef I0 (instanceRef DSACK_INT_0_1__r))
- ))
(net (rename state_machine_un17_clk_030 "state_machine.un17_clk_030") (joined
(portRef O (instanceRef state_machine_un17_clk_030_i))
(portRef I1 (instanceRef FPU_CS_INT_0_m))
@@ -1028,107 +993,137 @@
(portRef I1 (instanceRef AS_030_000_SYNC_0_m))
(portRef I0 (instanceRef AS_030_000_SYNC_0_r))
))
- (net (rename state_machine_un60_clk_000_d "state_machine.un60_clk_000_d") (joined
- (portRef O (instanceRef state_machine_un60_clk_000_d_i_0))
- (portRef I1 (instanceRef SM_AMIGA_ns_a2_0_5))
- ))
- (net DTACK_SYNC_1_sqmuxa (joined
- (portRef O (instanceRef DTACK_SYNC_1_sqmuxa))
- (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_i))
- ))
- (net DTACK_SYNC_1_sqmuxa_1 (joined
- (portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1))
- (portRef I1 (instanceRef DTACK_SYNC_0_m))
- (portRef I0 (instanceRef DTACK_SYNC_0_r))
- ))
- (net VPA_SYNC_1_sqmuxa (joined
- (portRef O (instanceRef VPA_SYNC_1_sqmuxa))
- (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_i))
- ))
- (net VPA_SYNC_1_sqmuxa_1 (joined
- (portRef O (instanceRef VPA_SYNC_1_sqmuxa_1))
- (portRef I1 (instanceRef VPA_SYNC_0_m))
- (portRef I0 (instanceRef VPA_SYNC_0_r))
- ))
- (net N_103 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a2_3))
- (portRef I0 (instanceRef N_103_i))
- ))
- (net N_104 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a2_4))
- (portRef I0 (instanceRef N_104_i))
- ))
- (net N_93 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_4))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_4))
- ))
- (net N_105 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_4))
- (portRef I0 (instanceRef N_105_i))
+ (net (rename state_machine_un1_clk_030 "state_machine.un1_clk_030") (joined
+ (portRef O (instanceRef state_machine_un1_clk_030_i))
+ (portRef I1 (instanceRef BG_000_0_m))
+ (portRef I0 (instanceRef BG_000_0_r))
))
(net VPA_SYNC_1_sqmuxa_1_0 (joined
(portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_0))
(portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa))
(portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_3_0))
))
- (net (rename state_machine_un15_clk_000_d "state_machine.un15_clk_000_d") (joined
- (portRef O (instanceRef state_machine_un15_clk_000_d_i))
+ (net (rename state_machine_un15_clk_000_d0 "state_machine.un15_clk_000_d0") (joined
+ (portRef O (instanceRef state_machine_un15_clk_000_d0_i))
(portRef I1 (instanceRef VMA_INT_0_m))
(portRef I0 (instanceRef VMA_INT_0_r))
))
- (net (rename state_machine_un13_clk_000_d "state_machine.un13_clk_000_d") (joined
- (portRef O (instanceRef state_machine_un13_clk_000_d))
- (portRef I0 (instanceRef state_machine_un13_clk_000_d_i))
+ (net (rename state_machine_un13_clk_000_d0 "state_machine.un13_clk_000_d0") (joined
+ (portRef O (instanceRef state_machine_un13_clk_000_d0))
+ (portRef I0 (instanceRef state_machine_un13_clk_000_d0_i))
))
- (net (rename state_machine_un8_clk_000_d "state_machine.un8_clk_000_d") (joined
- (portRef O (instanceRef state_machine_un8_clk_000_d))
- (portRef I0 (instanceRef state_machine_un8_clk_000_d_i))
- ))
- (net (rename state_machine_un8_clk_000_d_1 "state_machine.un8_clk_000_d_1") (joined
- (portRef O (instanceRef state_machine_un8_clk_000_d_1))
- (portRef I0 (instanceRef state_machine_un8_clk_000_d_1_i))
- (portRef I0 (instanceRef state_machine_un8_clk_000_d_1_0))
- ))
- (net (rename state_machine_un13_clk_000_d_1 "state_machine.un13_clk_000_d_1") (joined
- (portRef O (instanceRef state_machine_un13_clk_000_d_1))
- (portRef I0 (instanceRef state_machine_un13_clk_000_d_1_i))
- (portRef I0 (instanceRef state_machine_un13_clk_000_d_2_0))
- ))
- (net N_107 (joined
- (portRef O (instanceRef SM_AMIGA_ns_a2_0_5))
- (portRef I0 (instanceRef N_107_i))
- ))
- (net N_94 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_6))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_6))
- ))
- (net N_91 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_0))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0))
- ))
- (net N_110 (joined
- (portRef O (instanceRef SM_AMIGA_ns_a2_7))
- (portRef I0 (instanceRef N_110_i))
- ))
- (net N_108 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a2_6))
- (portRef I0 (instanceRef N_108_i))
+ (net (rename state_machine_un8_clk_000_d0 "state_machine.un8_clk_000_d0") (joined
+ (portRef O (instanceRef state_machine_un8_clk_000_d0))
+ (portRef I0 (instanceRef state_machine_un8_clk_000_d0_i))
))
(net N_109 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_6))
+ (portRef O (instanceRef SM_AMIGA_ns_a2_7))
(portRef I0 (instanceRef N_109_i))
))
+ (net (rename state_machine_un13_clk_000_d0_1 "state_machine.un13_clk_000_d0_1") (joined
+ (portRef O (instanceRef state_machine_un13_clk_000_d0_1))
+ (portRef I0 (instanceRef state_machine_un13_clk_000_d0_1_i))
+ (portRef I0 (instanceRef state_machine_un13_clk_000_d0_2_0))
+ ))
+ (net N_129 (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_a4_2_1))
+ (portRef I0 (instanceRef N_129_i))
+ ))
+ (net (rename state_machine_un13_clk_000_d0_2 "state_machine.un13_clk_000_d0_2") (joined
+ (portRef O (instanceRef state_machine_un13_clk_000_d0_2))
+ (portRef I0 (instanceRef state_machine_un13_clk_000_d0_2_i))
+ (portRef I1 (instanceRef clk_cpu_est_11_0_a4_2_1))
+ (portRef I1 (instanceRef state_machine_un13_clk_000_d0_2_0))
+ ))
+ (net N_130 (joined
+ (portRef O (instanceRef clk_cpu_est_11_i_a4_2))
+ (portRef I0 (instanceRef N_130_i))
+ ))
+ (net N_131 (joined
+ (portRef O (instanceRef clk_cpu_est_11_i_a4_0_2))
+ (portRef I0 (instanceRef N_131_i))
+ ))
+ (net N_124 (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_o4_i_1))
+ (portRef I0 (instanceRef VMA_INT_0_m))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1))
+ ))
+ (net N_125 (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_o4_i_3))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_a4_3))
+ ))
+ (net N_134 (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_a4_1_3))
+ (portRef I0 (instanceRef N_134_i))
+ ))
+ (net N_134_1 (joined
+ (portRef O (instanceRef VPA_SYNC_1_sqmuxa_3))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_3))
+ (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_2))
+ ))
(net N_106 (joined
- (portRef O (instanceRef SM_AMIGA_ns_a2_5))
+ (portRef O (instanceRef SM_AMIGA_ns_a2_0_5))
(portRef I0 (instanceRef N_106_i))
))
- (net N_101 (joined
- (portRef O (instanceRef SM_AMIGA_ns_a2_2))
- (portRef I0 (instanceRef N_101_i))
+ (net (rename clk_cpu_est_11_3 "clk.cpu_est_11[3]") (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_i_3))
+ (portRef I0 (instanceRef cpu_est_0_3__m))
))
- (net N_99 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_a2_0))
- (portRef I0 (instanceRef N_99_i))
+ (net N_132 (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_a4_3))
+ (portRef I0 (instanceRef N_132_i))
+ ))
+ (net N_133 (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_a4_0_3))
+ (portRef I0 (instanceRef N_133_i))
+ ))
+ (net (rename clk_cpu_est_11_1 "clk.cpu_est_11[1]") (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_i_1))
+ (portRef I0 (instanceRef cpu_est_0_1__m))
+ ))
+ (net N_127 (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_a4_0_1))
+ (portRef I0 (instanceRef N_127_i))
+ ))
+ (net N_126 (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_a4_1))
+ (portRef I0 (instanceRef N_126_i))
+ ))
+ (net N_128 (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_a4_1_1))
+ (portRef I0 (instanceRef N_128_i))
+ ))
+ (net N_93 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_o2_i_4))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_4))
+ ))
+ (net N_90 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_o2_i_6))
+ (portRef I0 (instanceRef SM_AMIGA_ns_a2_6))
+ ))
+ (net N_107 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_a2_6))
+ (portRef I0 (instanceRef N_107_i))
+ ))
+ (net N_108 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_a2_0_6))
+ (portRef I0 (instanceRef N_108_i))
+ ))
+ (net N_105 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_a2_5))
+ (portRef I0 (instanceRef N_105_i))
+ ))
+ (net N_103 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_a2_4))
+ (portRef I0 (instanceRef N_103_i))
+ ))
+ (net N_104 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_a2_0_4))
+ (portRef I0 (instanceRef N_104_i))
+ ))
+ (net N_100 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_a2_2))
+ (portRef I0 (instanceRef N_100_i))
))
(net AS_000_INT_1_sqmuxa (joined
(portRef O (instanceRef AS_000_INT_1_sqmuxa))
@@ -1140,138 +1135,142 @@
(portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_2))
(portRef I0 (instanceRef AMIGA_BUS_DATA_DIR))
))
- (net N_102_i (joined
- (portRef O (instanceRef N_102_i))
+ (net nEXP_SPACE_i (joined
+ (portRef O (instanceRef nEXP_SPACE_i))
+ (portRef I1 (instanceRef un1_bg_030_2))
+ (portRef I0 (instanceRef AMIGA_BUS_ENABLE))
+ ))
+ (net N_101_i (joined
+ (portRef O (instanceRef N_101_i))
+ (portRef I1 (instanceRef AS_000_INT_1_sqmuxa))
(portRef I1 (instanceRef SM_AMIGA_ns_2))
(portRef I0 (instanceRef AS_000_INT_0_n))
- (portRef I1 (instanceRef AS_000_INT_1_sqmuxa))
))
(net AS_000_INT_i (joined
(portRef O (instanceRef AS_000_INT_i))
(portRef I0 (instanceRef state_machine_un13_as_000_int))
))
(net (rename DSACK_i_1 "DSACK_i[1]") (joined
- (portRef O (instanceRef I_106))
+ (portRef O (instanceRef I_104))
(portRef I1 (instanceRef state_machine_un13_as_000_int))
))
(net AS_030_i (joined
(portRef O (instanceRef AS_030_i))
- (portRef I0 (instanceRef state_machine_un17_clk_030))
- (portRef I0 (instanceRef DSACK_INT_1_sqmuxa))
- (portRef I0 (instanceRef un1_as_030_3))
(portRef I0 (instanceRef un1_as_030_4))
- (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1))
(portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_1))
+ (portRef I0 (instanceRef DSACK_INT_1_sqmuxa))
+ (portRef I0 (instanceRef state_machine_un17_clk_030))
+ (portRef I0 (instanceRef un1_as_030_3))
+ (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1))
(portRef I0 (instanceRef AS_000_INT_1_sqmuxa))
(portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3_1))
))
- (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined
- (portRef O (instanceRef SM_AMIGA_i_7))
- (portRef I1 (instanceRef state_machine_un5_clk_030_i_a2))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0))
- ))
- (net CLK_000_D_i (joined
- (portRef O (instanceRef CLK_000_D_i))
+ (net CLK_000_D0_i (joined
+ (portRef O (instanceRef CLK_000_D0_i))
(portRef I0 (instanceRef SM_AMIGA_ns_i_o2_1))
(portRef I0 (instanceRef SM_AMIGA_ns_i_3))
(portRef I0 (instanceRef SM_AMIGA_ns_i_a2_4))
- (portRef I0 (instanceRef state_machine_un8_clk_000_d_1))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_6))
(portRef I0 (instanceRef SM_AMIGA_ns_a2_5))
- (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2_1))
+ (portRef I0 (instanceRef state_machine_un8_clk_000_d0_2))
(portRef I0 (instanceRef SM_AMIGA_ns_a2_0_1_5))
))
- (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined
- (portRef O (instanceRef SM_AMIGA_i_2))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_6))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_6))
- ))
- (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined
- (portRef O (instanceRef SM_AMIGA_i_1))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_6))
- ))
- (net (rename state_machine_un13_clk_000_d_1_i "state_machine.un13_clk_000_d_1_i") (joined
- (portRef O (instanceRef state_machine_un13_clk_000_d_1_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_a2_7))
- ))
- (net VPA_D_i (joined
- (portRef O (instanceRef VPA_D_i))
- (portRef I1 (instanceRef state_machine_un8_clk_000_d_1_0))
- (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_3_0))
- ))
- (net VMA_INT_i (joined
- (portRef O (instanceRef VMA_INT_i))
- (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_2))
- ))
- (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined
- (portRef O (instanceRef cpu_est_i_0))
- (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1))
- (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_3))
- (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_1_2))
- (portRef I0 (instanceRef state_machine_un13_clk_000_d_1_0))
- ))
- (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined
- (portRef O (instanceRef cpu_est_i_1))
- (portRef I0 (instanceRef clk_cpu_est_11_0_o4_1))
- (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_3))
- (portRef I1 (instanceRef state_machine_un8_clk_000_d_2))
- ))
- (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined
- (portRef O (instanceRef cpu_est_i_3))
- (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_1))
- (portRef I1 (instanceRef clk_cpu_est_11_0_o4_1))
- (portRef I1 (instanceRef clk_cpu_est_11_i_a4_1_2))
- (portRef I1 (instanceRef state_machine_un13_clk_000_d_1_0))
- (portRef I1 (instanceRef state_machine_un8_clk_000_d))
- ))
- (net (rename state_machine_un8_clk_000_d_1_i_0 "state_machine.un8_clk_000_d_1_i_0") (joined
- (portRef O (instanceRef state_machine_un8_clk_000_d_1_i))
- (portRef I0 (instanceRef VMA_INT_0_m))
- ))
- (net DTACK_i (joined
- (portRef O (instanceRef I_107))
- (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_0))
- ))
(net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined
(portRef O (instanceRef SM_AMIGA_i_3))
(portRef I0 (instanceRef SM_AMIGA_ns_i_a2_0_4))
))
(net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined
(portRef O (instanceRef SM_AMIGA_i_4))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_4))
(portRef I0 (instanceRef SM_AMIGA_ns_i_a2_3))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0_4))
))
- (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined
- (portRef O (instanceRef SM_AMIGA_i_5))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_3))
+ (net CLK_000_D1_i (joined
+ (portRef O (instanceRef CLK_000_D1_i))
+ (portRef I0 (instanceRef SM_AMIGA_ns_o2_6))
+ (portRef I1 (instanceRef clk_un4_clk_000_d1_0_a2))
+ ))
+ (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined
+ (portRef O (instanceRef cpu_est_i_0))
+ (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_3))
+ (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1))
+ (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_1_2))
+ (portRef I0 (instanceRef state_machine_un13_clk_000_d0_1_0))
+ ))
+ (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined
+ (portRef O (instanceRef cpu_est_i_3))
+ (portRef I1 (instanceRef clk_cpu_est_11_0_o4_1))
+ (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_1))
+ (portRef I1 (instanceRef state_machine_un8_clk_000_d0_1))
+ (portRef I1 (instanceRef clk_cpu_est_11_i_a4_1_2))
+ (portRef I1 (instanceRef state_machine_un13_clk_000_d0_1_0))
+ ))
+ (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined
+ (portRef O (instanceRef cpu_est_i_2))
+ (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_3))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_a4_0_1))
+ (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_3))
+ (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_2))
+ ))
+ (net VPA_D_i (joined
+ (portRef O (instanceRef VPA_D_i))
+ (portRef I1 (instanceRef state_machine_un8_clk_000_d0_2))
+ (portRef I0 (instanceRef VPA_SYNC_1_sqmuxa_3_0))
+ ))
+ (net VMA_INT_i (joined
+ (portRef O (instanceRef VMA_INT_i))
+ (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_2))
+ ))
+ (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined
+ (portRef O (instanceRef cpu_est_i_1))
+ (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_3))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_o4_1))
+ (portRef I0 (instanceRef state_machine_un8_clk_000_d0_1))
+ ))
+ (net (rename state_machine_un13_clk_000_d0_2_i "state_machine.un13_clk_000_d0_2_i") (joined
+ (portRef O (instanceRef state_machine_un13_clk_000_d0_2_i))
+ (portRef I1 (instanceRef clk_cpu_est_11_i_a4_2))
+ ))
+ (net (rename state_machine_un13_clk_000_d0_1_i "state_machine.un13_clk_000_d0_1_i") (joined
+ (portRef O (instanceRef state_machine_un13_clk_000_d0_1_i))
+ (portRef I1 (instanceRef SM_AMIGA_ns_a2_7))
+ ))
+ (net DTACK_i (joined
+ (portRef O (instanceRef I_105))
+ (portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa_1_0))
))
(net DTACK_SYNC_1_sqmuxa_i (joined
(portRef O (instanceRef DTACK_SYNC_1_sqmuxa_i))
(portRef I1 (instanceRef DTACK_SYNC_1_sqmuxa_1))
(portRef I0 (instanceRef DTACK_SYNC_0_n))
))
- (net VPA_SYNC_1_sqmuxa_i (joined
- (portRef O (instanceRef VPA_SYNC_1_sqmuxa_i))
- (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1))
- (portRef I0 (instanceRef VPA_SYNC_0_n))
+ (net (rename A_i_18 "A_i[18]") (joined
+ (portRef O (instanceRef A_i_18))
+ (portRef I0 (instanceRef state_machine_un42_clk_030_2))
))
- (net N_98_i (joined
- (portRef O (instanceRef N_98_i))
- (portRef I0 (instanceRef DSACK_INT_0_1__n))
- (portRef I1 (instanceRef DSACK_INT_1_sqmuxa))
- (portRef I0 (instanceRef SM_AMIGA_ns_7))
+ (net (rename A_i_16 "A_i[16]") (joined
+ (portRef O (instanceRef A_i_16))
+ (portRef I1 (instanceRef state_machine_un42_clk_030_1))
+ ))
+ (net (rename A_i_19 "A_i[19]") (joined
+ (portRef O (instanceRef A_i_19))
+ (portRef I1 (instanceRef state_machine_un42_clk_030_2))
+ ))
+ (net CLK_030_i (joined
+ (portRef O (instanceRef CLK_030_i))
+ (portRef I1 (instanceRef state_machine_un17_clk_030))
))
(net (rename state_machine_un42_clk_030_i "state_machine.un42_clk_030_i") (joined
(portRef O (instanceRef state_machine_un42_clk_030_i))
(portRef I1 (instanceRef state_machine_AS_030_000_SYNC_3))
))
- (net UDS_000_INT_0_sqmuxa_1_i (joined
- (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_i))
- (portRef I0 (instanceRef un1_as_030_4_93))
+ (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined
+ (portRef O (instanceRef SM_AMIGA_i_6))
+ (portRef I0 (instanceRef state_machine_un5_clk_030_i_a2))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_1))
))
- (net UDS_000_INT_0_sqmuxa_i (joined
- (portRef O (instanceRef UDS_000_INT_0_sqmuxa_i))
- (portRef I1 (instanceRef un1_as_030_4_93))
+ (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined
+ (portRef O (instanceRef SM_AMIGA_i_7))
+ (portRef I1 (instanceRef state_machine_un5_clk_030_i_a2))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_0))
))
(net AS_030_000_SYNC_i (joined
(portRef O (instanceRef AS_030_000_SYNC_i))
@@ -1280,32 +1279,31 @@
))
(net DS_030_i (joined
(portRef O (instanceRef DS_030_i))
- (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_1))
(portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_0))
+ (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_1))
))
- (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined
- (portRef O (instanceRef cpu_est_i_2))
- (portRef I0 (instanceRef clk_cpu_est_11_0_a4_0_1))
- (portRef I1 (instanceRef clk_cpu_est_11_0_a4_0_3))
- (portRef I1 (instanceRef clk_cpu_est_11_0_a4_1_3))
- (portRef I1 (instanceRef clk_cpu_est_11_i_a4_0_2))
+ (net UDS_000_INT_0_sqmuxa_1_i (joined
+ (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_i))
+ (portRef I0 (instanceRef un1_as_030_4_91))
))
- (net (rename state_machine_un13_clk_000_d_2_i "state_machine.un13_clk_000_d_2_i") (joined
- (portRef O (instanceRef state_machine_un13_clk_000_d_2_i))
- (portRef I1 (instanceRef clk_cpu_est_11_i_a4_2))
+ (net UDS_000_INT_0_sqmuxa_i (joined
+ (portRef O (instanceRef UDS_000_INT_0_sqmuxa_i))
+ (portRef I1 (instanceRef un1_as_030_4_91))
))
- (net CLK_000_DD_i (joined
- (portRef O (instanceRef CLK_000_DD_i))
- (portRef I1 (instanceRef clk_un4_clk_000_dd_0_a2))
+ (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined
+ (portRef O (instanceRef SM_AMIGA_i_5))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_3))
))
- (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined
- (portRef O (instanceRef SM_AMIGA_i_6))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_a2_1))
- (portRef I0 (instanceRef state_machine_un5_clk_030_i_a2))
+ (net VPA_SYNC_1_sqmuxa_i (joined
+ (portRef O (instanceRef VPA_SYNC_1_sqmuxa_i))
+ (portRef I0 (instanceRef VPA_SYNC_0_n))
+ (portRef I1 (instanceRef VPA_SYNC_1_sqmuxa_1))
))
- (net CLK_030_i (joined
- (portRef O (instanceRef CLK_030_i))
- (portRef I1 (instanceRef state_machine_un17_clk_030))
+ (net N_97_i (joined
+ (portRef O (instanceRef N_97_i))
+ (portRef I0 (instanceRef DSACK_INT_0_1__n))
+ (portRef I1 (instanceRef DSACK_INT_1_sqmuxa))
+ (portRef I0 (instanceRef SM_AMIGA_ns_7))
))
(net (rename A_i_30 "A_i[30]") (joined
(portRef O (instanceRef A_i_30))
@@ -1339,18 +1337,6 @@
(portRef O (instanceRef A_i_25))
(portRef I1 (instanceRef un8_ciin_1))
))
- (net (rename A_i_19 "A_i[19]") (joined
- (portRef O (instanceRef A_i_19))
- (portRef I1 (instanceRef state_machine_un42_clk_030_2))
- ))
- (net (rename A_i_16 "A_i[16]") (joined
- (portRef O (instanceRef A_i_16))
- (portRef I1 (instanceRef state_machine_un42_clk_030_1))
- ))
- (net (rename A_i_18 "A_i[18]") (joined
- (portRef O (instanceRef A_i_18))
- (portRef I0 (instanceRef state_machine_un42_clk_030_2))
- ))
(net (rename CLK_CNT_i_0 "CLK_CNT_i[0]") (joined
(portRef O (instanceRef CLK_CNT_i_0))
(portRef D (instanceRef CLK_CNT_0))
@@ -1390,13 +1376,6 @@
(portRef OE (instanceRef AVEC_EXP))
(portRef OE (instanceRef BERR))
))
- (net CPU_SPACE_i (joined
- (portRef O (instanceRef CPU_SPACE_i))
- (portRef I1 (instanceRef state_machine_AS_030_000_SYNC_3_1))
- (portRef I0 (instanceRef un1_bg_030_2))
- (portRef OE (instanceRef DSACK_0))
- (portRef OE (instanceRef DSACK_1))
- ))
(net BGACK_030_INT_i (joined
(portRef O (instanceRef BGACK_030_INT_i))
(portRef OE (instanceRef DTACK))
@@ -1404,7 +1383,7 @@
(net AS_030_c (joined
(portRef O (instanceRef AS_030))
(portRef I0 (instanceRef AS_030_i))
- (portRef I0 (instanceRef un1_bg_030_1))
+ (portRef I0 (instanceRef un1_bg_030_2))
))
(net AS_030 (joined
(portRef AS_030)
@@ -1432,7 +1411,7 @@
))
(net (rename SIZE_c_0 "SIZE_c[0]") (joined
(portRef O (instanceRef SIZE_0))
- (portRef I0 (instanceRef state_machine_un34_clk_000_d_1))
+ (portRef I1 (instanceRef state_machine_un34_clk_000_d0))
))
(net (rename SIZE_0 "SIZE[0]") (joined
(portRef (member size 1))
@@ -1627,13 +1606,16 @@
(portRef (member a 0))
(portRef I0 (instanceRef A_31))
))
- (net CPU_SPACE_c (joined
- (portRef O (instanceRef CPU_SPACE))
- (portRef I0 (instanceRef CPU_SPACE_i))
+ (net nEXP_SPACE_c (joined
+ (portRef O (instanceRef nEXP_SPACE))
+ (portRef I0 (instanceRef nEXP_SPACE_i))
+ (portRef I1 (instanceRef state_machine_AS_030_000_SYNC_3_1))
+ (portRef OE (instanceRef DSACK_0))
+ (portRef OE (instanceRef DSACK_1))
))
- (net CPU_SPACE (joined
- (portRef CPU_SPACE)
- (portRef I0 (instanceRef CPU_SPACE))
+ (net nEXP_SPACE (joined
+ (portRef nEXP_SPACE)
+ (portRef I0 (instanceRef nEXP_SPACE))
))
(net BERR (joined
(portRef O (instanceRef BERR))
@@ -1681,7 +1663,7 @@
))
(net CLK_000_c (joined
(portRef O (instanceRef CLK_000))
- (portRef D (instanceRef CLK_000_D))
+ (portRef D (instanceRef CLK_000_D0))
))
(net CLK_000 (joined
(portRef CLK_000)
@@ -1693,8 +1675,8 @@
(portRef CLK (instanceRef AS_030_000_SYNC))
(portRef CLK (instanceRef BGACK_030_INT))
(portRef CLK (instanceRef BG_000DFFSH))
- (portRef CLK (instanceRef CLK_000_D))
- (portRef CLK (instanceRef CLK_000_DD))
+ (portRef CLK (instanceRef CLK_000_D0))
+ (portRef CLK (instanceRef CLK_000_D1))
(portRef CLK (instanceRef CLK_CNT_0))
(portRef CLK (instanceRef CLK_OUT_INT))
(portRef CLK (instanceRef CLK_OUT_PRE))
@@ -1802,7 +1784,7 @@
))
(net (rename DSACK_c_1 "DSACK_c[1]") (joined
(portRef O (instanceRef DSACK_1))
- (portRef I0 (instanceRef I_106))
+ (portRef I0 (instanceRef I_104))
))
(net (rename DSACK_1 "DSACK[1]") (joined
(portRef (member dsack 0))
@@ -1810,7 +1792,7 @@
))
(net DTACK_c (joined
(portRef O (instanceRef DTACK))
- (portRef I0 (instanceRef I_107))
+ (portRef I0 (instanceRef I_105))
))
(net DTACK (joined
(portRef IO (instanceRef DTACK))
@@ -1898,106 +1880,149 @@
(portRef O (instanceRef CIIN))
(portRef CIIN)
))
- (net N_99_i (joined
- (portRef O (instanceRef N_99_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_0))
- ))
- (net N_75_i (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_0))
- (portRef D (instanceRef SM_AMIGA_7))
- ))
- (net N_101_i (joined
- (portRef O (instanceRef N_101_i))
+ (net N_100_i (joined
+ (portRef O (instanceRef N_100_i))
(portRef I0 (instanceRef SM_AMIGA_ns_2))
))
(net (rename SM_AMIGA_ns_0_2 "SM_AMIGA_ns_0[2]") (joined
(portRef O (instanceRef SM_AMIGA_ns_2))
(portRef I0 (instanceRef SM_AMIGA_ns_i_2))
))
- (net N_107_i (joined
- (portRef O (instanceRef N_107_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_5))
- ))
- (net N_106_i (joined
- (portRef O (instanceRef N_106_i))
- (portRef I0 (instanceRef SM_AMIGA_ns_5))
- ))
- (net (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (joined
- (portRef O (instanceRef SM_AMIGA_ns_5))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_5))
- ))
- (net N_108_i (joined
- (portRef O (instanceRef N_108_i))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_6))
- ))
- (net N_109_i (joined
- (portRef O (instanceRef N_109_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_6))
- ))
- (net N_85_i (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_6))
- (portRef D (instanceRef SM_AMIGA_1))
- ))
- (net N_110_i (joined
- (portRef O (instanceRef N_110_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_7))
- ))
- (net (rename SM_AMIGA_ns_0_7 "SM_AMIGA_ns_0[7]") (joined
- (portRef O (instanceRef SM_AMIGA_ns_7))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_7))
- ))
- (net N_91_0 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_0))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_0))
- ))
- (net CLK_OUT_PRE_i (joined
- (portRef O (instanceRef CLK_OUT_PRE_i))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_6))
- ))
- (net N_94_0 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_6))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_6))
- ))
- (net (rename state_machine_un8_clk_000_d_i "state_machine.un8_clk_000_d_i") (joined
- (portRef O (instanceRef state_machine_un8_clk_000_d_i))
- (portRef I0 (instanceRef state_machine_un15_clk_000_d))
- ))
- (net (rename state_machine_un13_clk_000_d_i "state_machine.un13_clk_000_d_i") (joined
- (portRef O (instanceRef state_machine_un13_clk_000_d_i))
- (portRef I1 (instanceRef state_machine_un15_clk_000_d))
- ))
- (net (rename state_machine_un15_clk_000_d_0 "state_machine.un15_clk_000_d_0") (joined
- (portRef O (instanceRef state_machine_un15_clk_000_d))
- (portRef I0 (instanceRef state_machine_un15_clk_000_d_i))
- ))
- (net N_93_0 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_4))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_4))
+ (net N_103_i (joined
+ (portRef O (instanceRef N_103_i))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_4))
))
(net N_104_i (joined
(portRef O (instanceRef N_104_i))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_4))
- ))
- (net N_105_i (joined
- (portRef O (instanceRef N_105_i))
(portRef I1 (instanceRef SM_AMIGA_ns_i_4))
))
(net N_82_i (joined
(portRef O (instanceRef SM_AMIGA_ns_i_4))
(portRef D (instanceRef SM_AMIGA_3))
))
- (net N_103_i (joined
- (portRef O (instanceRef N_103_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_3))
+ (net N_106_i (joined
+ (portRef O (instanceRef N_106_i))
+ (portRef I1 (instanceRef SM_AMIGA_ns_5))
))
- (net N_80_i (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_3))
- (portRef D (instanceRef SM_AMIGA_4))
+ (net N_105_i (joined
+ (portRef O (instanceRef N_105_i))
+ (portRef I0 (instanceRef SM_AMIGA_ns_5))
))
- (net (rename state_machine_un60_clk_000_d_i "state_machine.un60_clk_000_d_i") (joined
- (portRef O (instanceRef state_machine_un60_clk_000_d))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_4))
- (portRef I0 (instanceRef state_machine_un60_clk_000_d_i_0))
+ (net (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (joined
+ (portRef O (instanceRef SM_AMIGA_ns_5))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_5))
+ ))
+ (net N_107_i (joined
+ (portRef O (instanceRef N_107_i))
+ (portRef I0 (instanceRef SM_AMIGA_ns_6))
+ ))
+ (net N_108_i (joined
+ (portRef O (instanceRef N_108_i))
+ (portRef I1 (instanceRef SM_AMIGA_ns_6))
+ ))
+ (net (rename SM_AMIGA_ns_0_6 "SM_AMIGA_ns_0[6]") (joined
+ (portRef O (instanceRef SM_AMIGA_ns_6))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_6))
+ ))
+ (net N_90_i (joined
+ (portRef O (instanceRef SM_AMIGA_ns_o2_6))
+ (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2))
+ (portRef I0 (instanceRef SM_AMIGA_ns_o2_i_6))
+ ))
+ (net N_93_0 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_o2_4))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_4))
+ ))
+ (net N_128_i (joined
+ (portRef O (instanceRef N_128_i))
+ (portRef I1 (instanceRef clk_cpu_est_11_0_2_1))
+ ))
+ (net N_126_i (joined
+ (portRef O (instanceRef N_126_i))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_2_1))
+ ))
+ (net N_127_i (joined
+ (portRef O (instanceRef N_127_i))
+ (portRef I1 (instanceRef clk_cpu_est_11_0_1_1))
+ ))
+ (net N_129_i (joined
+ (portRef O (instanceRef N_129_i))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_1_1))
+ ))
+ (net (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_1))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_i_1))
+ ))
+ (net N_133_i (joined
+ (portRef O (instanceRef N_133_i))
+ (portRef I1 (instanceRef clk_cpu_est_11_0_3))
+ ))
+ (net N_132_i (joined
+ (portRef O (instanceRef N_132_i))
+ (portRef I1 (instanceRef clk_cpu_est_11_0_1_3))
+ ))
+ (net N_134_i (joined
+ (portRef O (instanceRef N_134_i))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_1_3))
+ ))
+ (net (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_3))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_i_3))
+ ))
+ (net N_125_i (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_o4_3))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_a4_0_3))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_o4_i_3))
+ ))
+ (net N_124_i (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_o4_1))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_1))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_o4_i_1))
+ ))
+ (net N_130_i (joined
+ (portRef O (instanceRef N_130_i))
+ (portRef I0 (instanceRef clk_cpu_est_11_i_2))
+ ))
+ (net N_131_i (joined
+ (portRef O (instanceRef N_131_i))
+ (portRef I1 (instanceRef clk_cpu_est_11_i_2))
+ ))
+ (net N_121_i (joined
+ (portRef O (instanceRef clk_cpu_est_11_i_2))
+ (portRef I0 (instanceRef cpu_est_0_2__m))
+ ))
+ (net N_91_0 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_o2_0))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_0))
+ ))
+ (net N_109_i (joined
+ (portRef O (instanceRef N_109_i))
+ (portRef I1 (instanceRef SM_AMIGA_ns_7))
+ ))
+ (net (rename SM_AMIGA_ns_0_7 "SM_AMIGA_ns_0[7]") (joined
+ (portRef O (instanceRef SM_AMIGA_ns_7))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_7))
+ ))
+ (net (rename state_machine_un8_clk_000_d0_i "state_machine.un8_clk_000_d0_i") (joined
+ (portRef O (instanceRef state_machine_un8_clk_000_d0_i))
+ (portRef I0 (instanceRef state_machine_un15_clk_000_d0))
+ ))
+ (net (rename state_machine_un13_clk_000_d0_i "state_machine.un13_clk_000_d0_i") (joined
+ (portRef O (instanceRef state_machine_un13_clk_000_d0_i))
+ (portRef I1 (instanceRef state_machine_un15_clk_000_d0))
+ ))
+ (net (rename state_machine_un15_clk_000_d0_0 "state_machine.un15_clk_000_d0_0") (joined
+ (portRef O (instanceRef state_machine_un15_clk_000_d0))
+ (portRef I0 (instanceRef state_machine_un15_clk_000_d0_i))
+ ))
+ (net BG_030_c_i (joined
+ (portRef O (instanceRef BG_030_c_i))
+ (portRef I0 (instanceRef state_machine_un1_clk_030))
+ (portRef I0 (instanceRef un1_bg_030_1))
+ ))
+ (net (rename state_machine_un1_clk_030_0 "state_machine.un1_clk_030_0") (joined
+ (portRef O (instanceRef state_machine_un1_clk_030))
+ (portRef I0 (instanceRef state_machine_un1_clk_030_i))
))
(net (rename state_machine_un17_clk_030_0 "state_machine.un17_clk_030_0") (joined
(portRef O (instanceRef state_machine_un17_clk_030))
@@ -2007,178 +2032,88 @@
(portRef O (instanceRef un1_as_030_3))
(portRef I0 (instanceRef un1_as_030_3_i))
))
- (net N_145_i (joined
- (portRef O (instanceRef N_145_i))
- (portRef I1 (instanceRef state_machine_UDS_000_INT_8))
- (portRef I0 (instanceRef state_machine_LDS_000_INT_8))
- ))
- (net (rename A_c_i_0 "A_c_i[0]") (joined
- (portRef O (instanceRef A_c_i_0))
- (portRef I0 (instanceRef state_machine_UDS_000_INT_8))
- (portRef I1 (instanceRef state_machine_un34_clk_000_d_1))
- ))
- (net (rename state_machine_UDS_000_INT_8_0 "state_machine.UDS_000_INT_8_0") (joined
- (portRef O (instanceRef state_machine_UDS_000_INT_8))
- (portRef I0 (instanceRef state_machine_UDS_000_INT_8_i))
- ))
- (net (rename state_machine_LDS_000_INT_8_0 "state_machine.LDS_000_INT_8_0") (joined
- (portRef O (instanceRef state_machine_LDS_000_INT_8))
- (portRef I0 (instanceRef state_machine_LDS_000_INT_8_i))
- ))
(net (rename state_machine_AS_030_000_SYNC_3_2 "state_machine.AS_030_000_SYNC_3_2") (joined
(portRef O (instanceRef state_machine_AS_030_000_SYNC_3))
(portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3_i))
))
- (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined
- (portRef O (instanceRef SIZE_c_i_1))
- (portRef I1 (instanceRef state_machine_un34_clk_000_d))
- ))
- (net (rename state_machine_un34_clk_000_d_i "state_machine.un34_clk_000_d_i") (joined
- (portRef O (instanceRef state_machine_un34_clk_000_d))
- (portRef I0 (instanceRef state_machine_un34_clk_000_d_i_0))
- ))
- (net N_131_i (joined
- (portRef O (instanceRef N_131_i))
- (portRef I0 (instanceRef clk_cpu_est_11_i_2))
- ))
- (net N_132_i (joined
- (portRef O (instanceRef N_132_i))
- (portRef I1 (instanceRef clk_cpu_est_11_i_2))
- ))
- (net N_122_i (joined
- (portRef O (instanceRef clk_cpu_est_11_i_2))
- (portRef I0 (instanceRef cpu_est_0_2__m))
- ))
- (net N_125_i (joined
- (portRef O (instanceRef clk_cpu_est_11_0_o4_1))
- (portRef I0 (instanceRef clk_cpu_est_11_0_a4_1_1))
- (portRef I0 (instanceRef clk_cpu_est_11_0_o4_i_1))
- ))
- (net N_126_i (joined
- (portRef O (instanceRef clk_cpu_est_11_0_o4_3))
- (portRef I0 (instanceRef clk_cpu_est_11_0_a4_0_3))
- (portRef I0 (instanceRef clk_cpu_est_11_0_o4_i_3))
- ))
- (net N_134_i (joined
- (portRef O (instanceRef N_134_i))
- (portRef I1 (instanceRef clk_cpu_est_11_0_3))
- ))
- (net N_133_i (joined
- (portRef O (instanceRef N_133_i))
- (portRef I1 (instanceRef clk_cpu_est_11_0_1_3))
- ))
- (net N_135_i (joined
- (portRef O (instanceRef N_135_i))
- (portRef I0 (instanceRef clk_cpu_est_11_0_1_3))
- ))
- (net (rename clk_cpu_est_11_0_3 "clk.cpu_est_11_0[3]") (joined
- (portRef O (instanceRef clk_cpu_est_11_0_3))
- (portRef I0 (instanceRef clk_cpu_est_11_0_i_3))
- ))
- (net N_130_i (joined
- (portRef O (instanceRef N_130_i))
- (portRef I1 (instanceRef clk_cpu_est_11_0_2_1))
- ))
- (net (rename clk_cpu_est_11_0_1 "clk.cpu_est_11_0[1]") (joined
- (portRef O (instanceRef clk_cpu_est_11_0_1))
- (portRef I0 (instanceRef clk_cpu_est_11_0_i_1))
- ))
- (net N_128_i (joined
- (portRef O (instanceRef N_128_i))
- (portRef I1 (instanceRef clk_cpu_est_11_0_1_1))
+ (net N_96_i (joined
+ (portRef O (instanceRef N_96_i))
+ (portRef I1 (instanceRef un1_bg_030_1))
))
(net un1_bg_030_0 (joined
(portRef O (instanceRef un1_bg_030))
(portRef I0 (instanceRef un1_bg_030_i))
))
- (net N_97_i (joined
- (portRef O (instanceRef N_97_i))
- (portRef I1 (instanceRef un1_bg_030_2))
- ))
- (net BG_030_c_i (joined
- (portRef O (instanceRef BG_030_c_i))
- (portRef I0 (instanceRef state_machine_un1_clk_030))
- (portRef I1 (instanceRef un1_bg_030_1))
- ))
- (net N_127_i (joined
- (portRef O (instanceRef N_127_i))
- (portRef I0 (instanceRef clk_cpu_est_11_0_1_1))
- ))
- (net N_129_i (joined
- (portRef O (instanceRef N_129_i))
- (portRef I0 (instanceRef clk_cpu_est_11_0_2_1))
- ))
- (net N_92_0 (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_o2_1))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_1))
- ))
- (net N_100_i (joined
- (portRef O (instanceRef N_100_i))
- (portRef I0 (instanceRef SM_AMIGA_ns_i_1))
- ))
- (net N_112_i (joined
- (portRef O (instanceRef N_112_i))
- (portRef I1 (instanceRef SM_AMIGA_ns_i_1))
- ))
- (net N_77_i (joined
- (portRef O (instanceRef SM_AMIGA_ns_i_1))
- (portRef D (instanceRef SM_AMIGA_6))
- ))
- (net (rename clk_un4_clk_000_dd_i "clk.un4_clk_000_dd_i") (joined
- (portRef O (instanceRef clk_un4_clk_000_dd_i))
+ (net (rename clk_un4_clk_000_d1_i "clk.un4_clk_000_d1_i") (joined
+ (portRef O (instanceRef clk_un4_clk_000_d1_i))
(portRef I1 (instanceRef state_machine_un6_bgack_000))
))
(net (rename state_machine_un6_bgack_000_0 "state_machine.un6_bgack_000_0") (joined
(portRef O (instanceRef state_machine_un6_bgack_000))
(portRef I0 (instanceRef state_machine_un6_bgack_000_i))
))
- (net (rename state_machine_un1_clk_030_0 "state_machine.un1_clk_030_0") (joined
- (portRef O (instanceRef state_machine_un1_clk_030))
- (portRef I0 (instanceRef state_machine_un1_clk_030_i))
+ (net N_98_i (joined
+ (portRef O (instanceRef N_98_i))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_0))
))
- (net (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (joined
- (portRef O (instanceRef clk_cpu_est_11_0_1_3))
- (portRef I0 (instanceRef clk_cpu_est_11_0_3))
+ (net N_75_i (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_0))
+ (portRef D (instanceRef SM_AMIGA_7))
))
- (net (rename state_machine_un34_clk_000_d_i_1 "state_machine.un34_clk_000_d_i_1") (joined
- (portRef O (instanceRef state_machine_un34_clk_000_d_1))
- (portRef I0 (instanceRef state_machine_un34_clk_000_d))
+ (net N_111_i (joined
+ (portRef O (instanceRef N_111_i))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_1))
))
- (net (rename state_machine_AS_030_000_SYNC_3_2_1 "state_machine.AS_030_000_SYNC_3_2_1") (joined
- (portRef O (instanceRef state_machine_AS_030_000_SYNC_3_1))
- (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3))
+ (net N_99_i (joined
+ (portRef O (instanceRef N_99_i))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_1))
))
- (net N_168_1 (joined
- (portRef O (instanceRef un8_ciin_1))
- (portRef I0 (instanceRef un8_ciin_5))
+ (net N_77_i (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_1))
+ (portRef D (instanceRef SM_AMIGA_6))
))
- (net N_168_2 (joined
- (portRef O (instanceRef un8_ciin_2))
- (portRef I1 (instanceRef un8_ciin_5))
+ (net N_92_0 (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_o2_1))
+ (portRef I0 (instanceRef SM_AMIGA_ns_i_o2_i_1))
))
- (net N_168_3 (joined
- (portRef O (instanceRef un8_ciin_3))
- (portRef I0 (instanceRef un8_ciin_6))
+ (net (rename state_machine_un34_clk_000_d0_i "state_machine.un34_clk_000_d0_i") (joined
+ (portRef O (instanceRef state_machine_un34_clk_000_d0))
+ (portRef I0 (instanceRef state_machine_un34_clk_000_d0_i_0))
))
- (net N_168_4 (joined
- (portRef O (instanceRef un8_ciin_4))
- (portRef I1 (instanceRef un8_ciin_6))
+ (net (rename A_c_i_0 "A_c_i[0]") (joined
+ (portRef O (instanceRef A_c_i_0))
+ (portRef I0 (instanceRef state_machine_UDS_000_INT_8))
+ (portRef I1 (instanceRef state_machine_un34_clk_000_d0_1))
))
- (net N_168_5 (joined
- (portRef O (instanceRef un8_ciin_5))
- (portRef I0 (instanceRef un8_ciin))
+ (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined
+ (portRef O (instanceRef SIZE_c_i_1))
+ (portRef I0 (instanceRef state_machine_un34_clk_000_d0_1))
))
- (net N_168_6 (joined
- (portRef O (instanceRef un8_ciin_6))
- (portRef I1 (instanceRef un8_ciin))
+ (net N_102_i (joined
+ (portRef O (instanceRef N_102_i))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_3))
))
- (net N_171_1 (joined
- (portRef O (instanceRef un4_ciin_1))
- (portRef I0 (instanceRef un4_ciin))
+ (net N_80_i (joined
+ (portRef O (instanceRef SM_AMIGA_ns_i_3))
+ (portRef D (instanceRef SM_AMIGA_4))
))
- (net N_171_2 (joined
- (portRef O (instanceRef un4_ciin_2))
- (portRef I1 (instanceRef un4_ciin))
+ (net N_144_i (joined
+ (portRef O (instanceRef N_144_i))
+ (portRef I0 (instanceRef state_machine_LDS_000_INT_8))
+ (portRef I1 (instanceRef state_machine_UDS_000_INT_8))
+ ))
+ (net (rename state_machine_LDS_000_INT_8_0 "state_machine.LDS_000_INT_8_0") (joined
+ (portRef O (instanceRef state_machine_LDS_000_INT_8))
+ (portRef I0 (instanceRef state_machine_LDS_000_INT_8_i))
+ ))
+ (net (rename state_machine_UDS_000_INT_8_0 "state_machine.UDS_000_INT_8_0") (joined
+ (portRef O (instanceRef state_machine_UDS_000_INT_8))
+ (portRef I0 (instanceRef state_machine_UDS_000_INT_8_i))
+ ))
+ (net (rename state_machine_un60_clk_000_d0_i "state_machine.un60_clk_000_d0_i") (joined
+ (portRef O (instanceRef state_machine_un60_clk_000_d0))
+ (portRef I1 (instanceRef SM_AMIGA_ns_i_o2_4))
+ (portRef I0 (instanceRef state_machine_un60_clk_000_d0_i_0))
))
(net un1_bg_030_0_1 (joined
(portRef O (instanceRef un1_bg_030_1))
@@ -2188,6 +2123,14 @@
(portRef O (instanceRef un1_bg_030_2))
(portRef I1 (instanceRef un1_bg_030))
))
+ (net (rename state_machine_AS_030_000_SYNC_3_2_1 "state_machine.AS_030_000_SYNC_3_2_1") (joined
+ (portRef O (instanceRef state_machine_AS_030_000_SYNC_3_1))
+ (portRef I0 (instanceRef state_machine_AS_030_000_SYNC_3))
+ ))
+ (net (rename clk_cpu_est_11_0_1_3 "clk.cpu_est_11_0_1[3]") (joined
+ (portRef O (instanceRef clk_cpu_est_11_0_1_3))
+ (portRef I0 (instanceRef clk_cpu_est_11_0_3))
+ ))
(net (rename clk_cpu_est_11_0_1_1 "clk.cpu_est_11_0_1[1]") (joined
(portRef O (instanceRef clk_cpu_est_11_0_1_1))
(portRef I0 (instanceRef clk_cpu_est_11_0_1))
@@ -2196,6 +2139,62 @@
(portRef O (instanceRef clk_cpu_est_11_0_2_1))
(portRef I1 (instanceRef clk_cpu_est_11_0_1))
))
+ (net N_167_1 (joined
+ (portRef O (instanceRef un8_ciin_1))
+ (portRef I0 (instanceRef un8_ciin_5))
+ ))
+ (net N_167_2 (joined
+ (portRef O (instanceRef un8_ciin_2))
+ (portRef I1 (instanceRef un8_ciin_5))
+ ))
+ (net N_167_3 (joined
+ (portRef O (instanceRef un8_ciin_3))
+ (portRef I0 (instanceRef un8_ciin_6))
+ ))
+ (net N_167_4 (joined
+ (portRef O (instanceRef un8_ciin_4))
+ (portRef I1 (instanceRef un8_ciin_6))
+ ))
+ (net N_167_5 (joined
+ (portRef O (instanceRef un8_ciin_5))
+ (portRef I0 (instanceRef un8_ciin))
+ ))
+ (net N_167_6 (joined
+ (portRef O (instanceRef un8_ciin_6))
+ (portRef I1 (instanceRef un8_ciin))
+ ))
+ (net N_170_1 (joined
+ (portRef O (instanceRef un4_ciin_1))
+ (portRef I0 (instanceRef un4_ciin))
+ ))
+ (net N_170_2 (joined
+ (portRef O (instanceRef un4_ciin_2))
+ (portRef I1 (instanceRef un4_ciin))
+ ))
+ (net UDS_000_INT_0_sqmuxa_1_1 (joined
+ (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_1))
+ (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_3))
+ ))
+ (net UDS_000_INT_0_sqmuxa_1_2 (joined
+ (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_2))
+ (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_3))
+ ))
+ (net UDS_000_INT_0_sqmuxa_1_3 (joined
+ (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_3))
+ (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1))
+ ))
+ (net UDS_000_INT_0_sqmuxa_1_0 (joined
+ (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_0))
+ (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa))
+ ))
+ (net UDS_000_INT_0_sqmuxa_2 (joined
+ (portRef O (instanceRef UDS_000_INT_0_sqmuxa_2))
+ (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa))
+ ))
+ (net (rename state_machine_un34_clk_000_d0_i_1 "state_machine.un34_clk_000_d0_i_1") (joined
+ (portRef O (instanceRef state_machine_un34_clk_000_d0_1))
+ (portRef I0 (instanceRef state_machine_un34_clk_000_d0))
+ ))
(net (rename state_machine_un42_clk_030_1 "state_machine.un42_clk_030_1") (joined
(portRef O (instanceRef state_machine_un42_clk_030_1))
(portRef I0 (instanceRef state_machine_un42_clk_030_4))
@@ -2216,57 +2215,41 @@
(portRef O (instanceRef state_machine_un42_clk_030_5))
(portRef I1 (instanceRef state_machine_un42_clk_030))
))
- (net N_132_1 (joined
- (portRef O (instanceRef clk_cpu_est_11_i_a4_0_1_2))
- (portRef I0 (instanceRef clk_cpu_est_11_i_a4_0_2))
- ))
- (net N_131_1 (joined
- (portRef O (instanceRef clk_cpu_est_11_i_a4_1_2))
- (portRef I0 (instanceRef clk_cpu_est_11_i_a4_2))
- ))
- (net UDS_000_INT_0_sqmuxa_1_0 (joined
- (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_0))
- (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa))
- ))
- (net UDS_000_INT_0_sqmuxa_2 (joined
- (portRef O (instanceRef UDS_000_INT_0_sqmuxa_2))
- (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa))
- ))
- (net UDS_000_INT_0_sqmuxa_1_1 (joined
- (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_1))
- (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1_3))
- ))
- (net UDS_000_INT_0_sqmuxa_1_2 (joined
- (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_2))
- (portRef I1 (instanceRef UDS_000_INT_0_sqmuxa_1_3))
- ))
- (net UDS_000_INT_0_sqmuxa_1_3 (joined
- (portRef O (instanceRef UDS_000_INT_0_sqmuxa_1_3))
- (portRef I0 (instanceRef UDS_000_INT_0_sqmuxa_1))
- ))
(net DTACK_SYNC_1_sqmuxa_1_0 (joined
(portRef O (instanceRef DTACK_SYNC_1_sqmuxa_1_0))
(portRef I0 (instanceRef DTACK_SYNC_1_sqmuxa))
))
- (net (rename state_machine_un8_clk_000_d_1_0 "state_machine.un8_clk_000_d_1_0") (joined
- (portRef O (instanceRef state_machine_un8_clk_000_d_1_0))
- (portRef I0 (instanceRef state_machine_un8_clk_000_d_3))
+ (net N_130_1 (joined
+ (portRef O (instanceRef clk_cpu_est_11_i_a4_1_2))
+ (portRef I0 (instanceRef clk_cpu_est_11_i_a4_2))
))
- (net (rename state_machine_un8_clk_000_d_2 "state_machine.un8_clk_000_d_2") (joined
- (portRef O (instanceRef state_machine_un8_clk_000_d_2))
- (portRef I1 (instanceRef state_machine_un8_clk_000_d_3))
+ (net N_131_1 (joined
+ (portRef O (instanceRef clk_cpu_est_11_i_a4_0_1_2))
+ (portRef I0 (instanceRef clk_cpu_est_11_i_a4_0_2))
))
- (net (rename state_machine_un8_clk_000_d_3 "state_machine.un8_clk_000_d_3") (joined
- (portRef O (instanceRef state_machine_un8_clk_000_d_3))
- (portRef I0 (instanceRef state_machine_un8_clk_000_d))
+ (net (rename state_machine_un8_clk_000_d0_1 "state_machine.un8_clk_000_d0_1") (joined
+ (portRef O (instanceRef state_machine_un8_clk_000_d0_1))
+ (portRef I0 (instanceRef state_machine_un8_clk_000_d0_4))
))
- (net (rename state_machine_un13_clk_000_d_1_0 "state_machine.un13_clk_000_d_1_0") (joined
- (portRef O (instanceRef state_machine_un13_clk_000_d_1_0))
- (portRef I0 (instanceRef state_machine_un13_clk_000_d))
+ (net (rename state_machine_un8_clk_000_d0_2 "state_machine.un8_clk_000_d0_2") (joined
+ (portRef O (instanceRef state_machine_un8_clk_000_d0_2))
+ (portRef I1 (instanceRef state_machine_un8_clk_000_d0_4))
))
- (net (rename state_machine_un13_clk_000_d_2_0 "state_machine.un13_clk_000_d_2_0") (joined
- (portRef O (instanceRef state_machine_un13_clk_000_d_2_0))
- (portRef I1 (instanceRef state_machine_un13_clk_000_d))
+ (net (rename state_machine_un8_clk_000_d0_3 "state_machine.un8_clk_000_d0_3") (joined
+ (portRef O (instanceRef state_machine_un8_clk_000_d0_3))
+ (portRef I1 (instanceRef state_machine_un8_clk_000_d0))
+ ))
+ (net (rename state_machine_un8_clk_000_d0_4 "state_machine.un8_clk_000_d0_4") (joined
+ (portRef O (instanceRef state_machine_un8_clk_000_d0_4))
+ (portRef I0 (instanceRef state_machine_un8_clk_000_d0))
+ ))
+ (net (rename state_machine_un13_clk_000_d0_1_0 "state_machine.un13_clk_000_d0_1_0") (joined
+ (portRef O (instanceRef state_machine_un13_clk_000_d0_1_0))
+ (portRef I0 (instanceRef state_machine_un13_clk_000_d0))
+ ))
+ (net (rename state_machine_un13_clk_000_d0_2_0 "state_machine.un13_clk_000_d0_2_0") (joined
+ (portRef O (instanceRef state_machine_un13_clk_000_d0_2_0))
+ (portRef I1 (instanceRef state_machine_un13_clk_000_d0))
))
(net VPA_SYNC_1_sqmuxa_1_1 (joined
(portRef O (instanceRef VPA_SYNC_1_sqmuxa_1_1))
@@ -2284,13 +2267,33 @@
(portRef O (instanceRef VPA_SYNC_1_sqmuxa_4))
(portRef I0 (instanceRef VPA_SYNC_1_sqmuxa))
))
- (net N_107_1 (joined
+ (net N_106_1 (joined
(portRef O (instanceRef SM_AMIGA_ns_a2_0_1_5))
(portRef I0 (instanceRef SM_AMIGA_ns_a2_0_5))
))
- (net N_98_1 (joined
- (portRef O (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2_1))
- (portRef I0 (instanceRef un1_DSACK_INT_0_sqmuxa_i_a2))
+ (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined
+ (portRef O (instanceRef cpu_est_0_3__r))
+ (portRef I1 (instanceRef cpu_est_0_3__n))
+ ))
+ (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined
+ (portRef O (instanceRef cpu_est_0_3__m))
+ (portRef I0 (instanceRef cpu_est_0_3__p))
+ ))
+ (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined
+ (portRef O (instanceRef cpu_est_0_3__n))
+ (portRef I1 (instanceRef cpu_est_0_3__p))
+ ))
+ (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined
+ (portRef O (instanceRef cpu_est_0_1__r))
+ (portRef I1 (instanceRef cpu_est_0_1__n))
+ ))
+ (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined
+ (portRef O (instanceRef cpu_est_0_1__m))
+ (portRef I0 (instanceRef cpu_est_0_1__p))
+ ))
+ (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined
+ (portRef O (instanceRef cpu_est_0_1__n))
+ (portRef I1 (instanceRef cpu_est_0_1__p))
))
(net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined
(portRef O (instanceRef AS_000_INT_0_r))
@@ -2304,65 +2307,17 @@
(portRef O (instanceRef AS_000_INT_0_n))
(portRef I1 (instanceRef AS_000_INT_0_p))
))
- (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined
- (portRef O (instanceRef VMA_INT_0_r))
- (portRef I1 (instanceRef VMA_INT_0_n))
+ (net (rename BG_000_0_un3 "BG_000_0.un3") (joined
+ (portRef O (instanceRef BG_000_0_r))
+ (portRef I1 (instanceRef BG_000_0_n))
))
- (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined
- (portRef O (instanceRef VMA_INT_0_m))
- (portRef I0 (instanceRef VMA_INT_0_p))
+ (net (rename BG_000_0_un1 "BG_000_0.un1") (joined
+ (portRef O (instanceRef BG_000_0_m))
+ (portRef I0 (instanceRef BG_000_0_p))
))
- (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined
- (portRef O (instanceRef VMA_INT_0_n))
- (portRef I1 (instanceRef VMA_INT_0_p))
- ))
- (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined
- (portRef O (instanceRef UDS_000_INT_0_r))
- (portRef I1 (instanceRef UDS_000_INT_0_n))
- ))
- (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined
- (portRef O (instanceRef UDS_000_INT_0_m))
- (portRef I0 (instanceRef UDS_000_INT_0_p))
- ))
- (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined
- (portRef O (instanceRef UDS_000_INT_0_n))
- (portRef I1 (instanceRef UDS_000_INT_0_p))
- ))
- (net (rename DTACK_SYNC_0_un3 "DTACK_SYNC_0.un3") (joined
- (portRef O (instanceRef DTACK_SYNC_0_r))
- (portRef I1 (instanceRef DTACK_SYNC_0_n))
- ))
- (net (rename DTACK_SYNC_0_un1 "DTACK_SYNC_0.un1") (joined
- (portRef O (instanceRef DTACK_SYNC_0_m))
- (portRef I0 (instanceRef DTACK_SYNC_0_p))
- ))
- (net (rename DTACK_SYNC_0_un0 "DTACK_SYNC_0.un0") (joined
- (portRef O (instanceRef DTACK_SYNC_0_n))
- (portRef I1 (instanceRef DTACK_SYNC_0_p))
- ))
- (net (rename VPA_SYNC_0_un3 "VPA_SYNC_0.un3") (joined
- (portRef O (instanceRef VPA_SYNC_0_r))
- (portRef I1 (instanceRef VPA_SYNC_0_n))
- ))
- (net (rename VPA_SYNC_0_un1 "VPA_SYNC_0.un1") (joined
- (portRef O (instanceRef VPA_SYNC_0_m))
- (portRef I0 (instanceRef VPA_SYNC_0_p))
- ))
- (net (rename VPA_SYNC_0_un0 "VPA_SYNC_0.un0") (joined
- (portRef O (instanceRef VPA_SYNC_0_n))
- (portRef I1 (instanceRef VPA_SYNC_0_p))
- ))
- (net (rename DSACK_INT_0_1__un3 "DSACK_INT_0_1_.un3") (joined
- (portRef O (instanceRef DSACK_INT_0_1__r))
- (portRef I1 (instanceRef DSACK_INT_0_1__n))
- ))
- (net (rename DSACK_INT_0_1__un1 "DSACK_INT_0_1_.un1") (joined
- (portRef O (instanceRef DSACK_INT_0_1__m))
- (portRef I0 (instanceRef DSACK_INT_0_1__p))
- ))
- (net (rename DSACK_INT_0_1__un0 "DSACK_INT_0_1_.un0") (joined
- (portRef O (instanceRef DSACK_INT_0_1__n))
- (portRef I1 (instanceRef DSACK_INT_0_1__p))
+ (net (rename BG_000_0_un0 "BG_000_0.un0") (joined
+ (portRef O (instanceRef BG_000_0_n))
+ (portRef I1 (instanceRef BG_000_0_p))
))
(net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined
(portRef O (instanceRef AS_030_000_SYNC_0_r))
@@ -2388,29 +2343,29 @@
(portRef O (instanceRef FPU_CS_INT_0_n))
(portRef I1 (instanceRef FPU_CS_INT_0_p))
))
- (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined
- (portRef O (instanceRef LDS_000_INT_0_r))
- (portRef I1 (instanceRef LDS_000_INT_0_n))
+ (net (rename DTACK_SYNC_0_un3 "DTACK_SYNC_0.un3") (joined
+ (portRef O (instanceRef DTACK_SYNC_0_r))
+ (portRef I1 (instanceRef DTACK_SYNC_0_n))
))
- (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined
- (portRef O (instanceRef LDS_000_INT_0_m))
- (portRef I0 (instanceRef LDS_000_INT_0_p))
+ (net (rename DTACK_SYNC_0_un1 "DTACK_SYNC_0.un1") (joined
+ (portRef O (instanceRef DTACK_SYNC_0_m))
+ (portRef I0 (instanceRef DTACK_SYNC_0_p))
))
- (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined
- (portRef O (instanceRef LDS_000_INT_0_n))
- (portRef I1 (instanceRef LDS_000_INT_0_p))
+ (net (rename DTACK_SYNC_0_un0 "DTACK_SYNC_0.un0") (joined
+ (portRef O (instanceRef DTACK_SYNC_0_n))
+ (portRef I1 (instanceRef DTACK_SYNC_0_p))
))
- (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined
- (portRef O (instanceRef cpu_est_0_3__r))
- (portRef I1 (instanceRef cpu_est_0_3__n))
+ (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined
+ (portRef O (instanceRef VMA_INT_0_r))
+ (portRef I1 (instanceRef VMA_INT_0_n))
))
- (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined
- (portRef O (instanceRef cpu_est_0_3__m))
- (portRef I0 (instanceRef cpu_est_0_3__p))
+ (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined
+ (portRef O (instanceRef VMA_INT_0_m))
+ (portRef I0 (instanceRef VMA_INT_0_p))
))
- (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined
- (portRef O (instanceRef cpu_est_0_3__n))
- (portRef I1 (instanceRef cpu_est_0_3__p))
+ (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined
+ (portRef O (instanceRef VMA_INT_0_n))
+ (portRef I1 (instanceRef VMA_INT_0_p))
))
(net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined
(portRef O (instanceRef cpu_est_0_2__r))
@@ -2424,42 +2379,6 @@
(portRef O (instanceRef cpu_est_0_2__n))
(portRef I1 (instanceRef cpu_est_0_2__p))
))
- (net (rename BG_000_0_un3 "BG_000_0.un3") (joined
- (portRef O (instanceRef BG_000_0_r))
- (portRef I1 (instanceRef BG_000_0_n))
- ))
- (net (rename BG_000_0_un1 "BG_000_0.un1") (joined
- (portRef O (instanceRef BG_000_0_m))
- (portRef I0 (instanceRef BG_000_0_p))
- ))
- (net (rename BG_000_0_un0 "BG_000_0.un0") (joined
- (portRef O (instanceRef BG_000_0_n))
- (portRef I1 (instanceRef BG_000_0_p))
- ))
- (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined
- (portRef O (instanceRef BGACK_030_INT_0_r))
- (portRef I1 (instanceRef BGACK_030_INT_0_n))
- ))
- (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined
- (portRef O (instanceRef BGACK_030_INT_0_m))
- (portRef I0 (instanceRef BGACK_030_INT_0_p))
- ))
- (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined
- (portRef O (instanceRef BGACK_030_INT_0_n))
- (portRef I1 (instanceRef BGACK_030_INT_0_p))
- ))
- (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined
- (portRef O (instanceRef cpu_est_0_1__r))
- (portRef I1 (instanceRef cpu_est_0_1__n))
- ))
- (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined
- (portRef O (instanceRef cpu_est_0_1__m))
- (portRef I0 (instanceRef cpu_est_0_1__p))
- ))
- (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined
- (portRef O (instanceRef cpu_est_0_1__n))
- (portRef I1 (instanceRef cpu_est_0_1__p))
- ))
(net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined
(portRef O (instanceRef IPL_030_0_0__r))
(portRef I1 (instanceRef IPL_030_0_0__n))
@@ -2496,6 +2415,66 @@
(portRef O (instanceRef IPL_030_0_2__n))
(portRef I1 (instanceRef IPL_030_0_2__p))
))
+ (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined
+ (portRef O (instanceRef BGACK_030_INT_0_r))
+ (portRef I1 (instanceRef BGACK_030_INT_0_n))
+ ))
+ (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined
+ (portRef O (instanceRef BGACK_030_INT_0_m))
+ (portRef I0 (instanceRef BGACK_030_INT_0_p))
+ ))
+ (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined
+ (portRef O (instanceRef BGACK_030_INT_0_n))
+ (portRef I1 (instanceRef BGACK_030_INT_0_p))
+ ))
+ (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined
+ (portRef O (instanceRef UDS_000_INT_0_r))
+ (portRef I1 (instanceRef UDS_000_INT_0_n))
+ ))
+ (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined
+ (portRef O (instanceRef UDS_000_INT_0_m))
+ (portRef I0 (instanceRef UDS_000_INT_0_p))
+ ))
+ (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined
+ (portRef O (instanceRef UDS_000_INT_0_n))
+ (portRef I1 (instanceRef UDS_000_INT_0_p))
+ ))
+ (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined
+ (portRef O (instanceRef LDS_000_INT_0_r))
+ (portRef I1 (instanceRef LDS_000_INT_0_n))
+ ))
+ (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined
+ (portRef O (instanceRef LDS_000_INT_0_m))
+ (portRef I0 (instanceRef LDS_000_INT_0_p))
+ ))
+ (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined
+ (portRef O (instanceRef LDS_000_INT_0_n))
+ (portRef I1 (instanceRef LDS_000_INT_0_p))
+ ))
+ (net (rename VPA_SYNC_0_un3 "VPA_SYNC_0.un3") (joined
+ (portRef O (instanceRef VPA_SYNC_0_r))
+ (portRef I1 (instanceRef VPA_SYNC_0_n))
+ ))
+ (net (rename VPA_SYNC_0_un1 "VPA_SYNC_0.un1") (joined
+ (portRef O (instanceRef VPA_SYNC_0_m))
+ (portRef I0 (instanceRef VPA_SYNC_0_p))
+ ))
+ (net (rename VPA_SYNC_0_un0 "VPA_SYNC_0.un0") (joined
+ (portRef O (instanceRef VPA_SYNC_0_n))
+ (portRef I1 (instanceRef VPA_SYNC_0_p))
+ ))
+ (net (rename DSACK_INT_0_1__un3 "DSACK_INT_0_1_.un3") (joined
+ (portRef O (instanceRef DSACK_INT_0_1__r))
+ (portRef I1 (instanceRef DSACK_INT_0_1__n))
+ ))
+ (net (rename DSACK_INT_0_1__un1 "DSACK_INT_0_1_.un1") (joined
+ (portRef O (instanceRef DSACK_INT_0_1__m))
+ (portRef I0 (instanceRef DSACK_INT_0_1__p))
+ ))
+ (net (rename DSACK_INT_0_1__un0 "DSACK_INT_0_1_.un0") (joined
+ (portRef O (instanceRef DSACK_INT_0_1__n))
+ (portRef I1 (instanceRef DSACK_INT_0_1__p))
+ ))
)
(property orig_inst_of (string "BUS68030"))
)
diff --git a/Logic/BUS68030.naf b/Logic/BUS68030.naf
index 7804fc4..bd9707e 100644
--- a/Logic/BUS68030.naf
+++ b/Logic/BUS68030.naf
@@ -37,7 +37,7 @@ A[3] b
A[2] b
A[1] b
A[0] b
-CPU_SPACE i
+nEXP_SPACE i
BERR b
BG_030 i
BG_000 o
diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj
index 2780f25..b55d46f 100644
--- a/Logic/BUS68030.prj
+++ b/Logic/BUS68030.prj
@@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
-#-- Written on Thu May 15 23:02:39 2014
+#-- Written on Fri May 16 17:07:02 2014
#device options
diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm
index 881f675..c7b5230 100644
--- a/Logic/BUS68030.srm
+++ b/Logic/BUS68030.srm
@@ -244,8 +244,8 @@ RU@@::4646:4:q4:r:d4jq9Rr:d4jq9Rr:d4j
9;N3HRs_0DFosHMCNlR""q;H
NRs3FHHo8sHR'M0Fk'N;
HCR38NHVs$sNMCNlR''N;R
-H@:@U44n:::4ngu:Bzu_1qRB B_uz1Buq N;
-HsR30FD_sMHoNRlC"zBu_q1uB; "
+H@:@U44n:::4n4Mj: _Xu1Buq RMX1u_u qB;H
+NR03sDs_FHNoMl"CRMu X_q1uB; "
@FR@4U:(::44c(::)A ) RA)
);N3HRs_0DFosHMCNlR "A);)"
RNH3b#DFosH8RHs"FHMk;0"
@@ -314,101 +314,89 @@ RU@@::c646:c:Bc:QRQhBhQQ;H
NR03sDs_FHNoMl"CRBhQQ"o;
L1R7qrBij
9;N3LRLbH0F8s0H.sR;M
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-oR4h_;M
-NRN3#PMC_CV0_D#No46R.no;
-M_Rh.N;
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M#R3N_PCM_C0VoDN#.4R6
n;ohMR_
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-oR6h_;M
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-(;N3MR#CNP_0MC_NVDoR#4.;6n
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-RoMhd_4;M
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-RoMhg_4;M
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-oR4h_(
4;N3MR#CNP_0MC_NVDoR#4.;6n
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NRN3#PMC_CV0_D#No46R.no;
M1Rq_jjj_aQh_kj3M
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NRN3#PMC_CV0_D#No46R.no;
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-RNM3P#NCC_M0D_VN4o#Rn.6;M
-oRqev_aQh_kj3M
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-oR1z7_jjj_aQh_kj3M
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j;N3MR#CNP_0MC_NVDoR#4.;6n
-RoM7BaqiY_1hjB_3dkM;M
+RoMAjt_jjj_3dkM;M
NRN3#PMC_CV0_D#No46R.no;
-MaR7q_Bi1BYh_kj3M
+MtRA_jjj_kj3M
4;N3MR#CNP_0MC_NVDoR#4.;6n
-RoM7BaqiY_1hjB_3jkM;M
-NRN3#PMC_CV0_D#No46R.no;
-MuReqY_1hjB_3dkM;M
-NRN3#PMC_CV0_D#No46R.no;
-MuReqY_1hjB_34kM;M
-NRN3#PMC_CV0_D#No46R.no;
-MuReqY_1hjB_3jkM;M
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-M1R7q_BiQ_haj__43dkM;M
-NRN3#PMC_CV0_D#No46R.no;
-M1R7q_BiQ_haj__434kM;M
-NRN3#PMC_CV0_D#No46R.no;
-M1R7q_BiQ_haj__43jkM;M
+RoMAjt_jjj_3jkM;M
NRN3#PMC_CV0_D#No46R.no;
M1Rq_jjd_jjj_h1YB3_jk;Md
RNM3P#NCC_M0D_VN4o#Rn.6;M
@@ -422,17 +410,17 @@ oRzwu__B1Q_hajM3k4N;
M#R3N_PCM_C0VoDN#.4R6
n;owMRuBz_1h_Qa3_jk;Mj
RNM3P#NCC_M0D_VN4o#Rn.6;M
-oR1p7_jjj_aQh_kj3M
-d;N3MR#CNP_0MC_NVDoR#4.;6n
-RoMp_71j_jjQ_hajM3k4N;
+oRq7aB1i_Y_hBjM3kdN;
M#R3N_PCM_C0VoDN#.4R6
-n;opMR7j1_jQj_hja_3jkM;M
+n;o7MRaiqB_h1YB3_jk;M4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRq7aB1i_Y_hBjM3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oeMRvQq_hja_3dkM;M
NRN3#PMC_CV0_D#No46R.no;
-MbROk#_C0__jdk_3M
-d;N3MR#CNP_0MC_NVDoR#4.;6n
-RoMO_bkC_#0j__d34kM;M
-NRN3#PMC_CV0_D#No46R.no;
-MbROk#_C0__jdk_3M
+MvReqh_Qa3_jk;M4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRqev_aQh_kj3M
j;N3MR#CNP_0MC_NVDoR#4.;6n
RoMO_bkC_#0j__.3dkM;M
NRN3#PMC_CV0_D#No46R.no;
@@ -440,11 +428,23 @@ MbROk#_C0__j.k_3M
4;N3MR#CNP_0MC_NVDoR#4.;6n
RoMO_bkC_#0j__.3jkM;M
NRN3#PMC_CV0_D#No46R.no;
-MtRA_jjj_kj3M
+MuRQpd_jj__jjk_3M
d;N3MR#CNP_0MC_NVDoR#4.;6n
-RoMAjt_jjj_34kM;M
+RoMQ_upj_djj__j34kM;M
NRN3#PMC_CV0_D#No46R.no;
-MtRA_jjj_kj3M
+MuRQpd_jj__jjk_3M
+j;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMQ_upj_djj__43dkM;M
+NRN3#PMC_CV0_D#No46R.no;
+MuRQpd_jj__j4k_3M
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMQ_upj_djj__43jkM;M
+NRN3#PMC_CV0_D#No46R.no;
+MuRQpd_jj__j.k_3M
+d;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMQ_upj_djj__.34kM;M
+NRN3#PMC_CV0_D#No46R.no;
+MuRQpd_jj__j.k_3M
j;N3MR#CNP_0MC_NVDoR#4.;6n
RoMABtqid_jjh_Qa3_jk;Md
RNM3P#NCC_M0D_VN4o#Rn.6;M
@@ -452,47 +452,33 @@ oRqAtBji_dQj_hja_34kM;M
NRN3#PMC_CV0_D#No46R.no;
MtRAq_Bij_djQ_hajM3kjN;
M#R3N_PCM_C0VoDN#.4R6
-n;oOMRbCk_#j0__34_k;Md
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RNM3P#NCC_M0D_VN4o#Rn.6;M
-oRkOb_0C#_4j__M3k4N;
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M#R3N_PCM_C0VoDN#.4R6
-n;oOMRbCk_#j0__34_k;Mj
+n;opMR7j1_jQj_hja_34kM;M
+NRN3#PMC_CV0_D#No46R.no;
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RNM3P#NCC_M0D_VN4o#Rn.6;M
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RNM3P#NCC_M0D_VN4o#Rn.6;M
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RNM3P#NCC_M0D_VN4o#Rn.6;M
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-n;oQMRujp_djj__34_k;Mj
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RNM3P#NCC_M0D_VN4o#Rn.6;M
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RNM3P#NCC_M0D_VN4o#Rn.6;M
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-b@:@44::44+:.4V.:NCD#R:fjjNRVDR#CV#NDChRt7b;
-RU@@:n4(:4.:(dn:+:4.1qv_vqQtr(j:9jRf:ojRE0F#R_1vqtvQq:rj(h9R_,.jh4_.,.h_._,h.hd,_,.ch6_.,.h_n_,h.
-(;N3HRsC0D_R0F4N;
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-s@:@U.:gUcg:.Uc:.+:4.1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtqdS9
-Tv=1_Qqvtdqr97
-S=Uh_.
-_HSiBp=iBp_Zm1Q
-_OS))=1Ha_;H
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+oRq71BQi_hja__34_k;Mj
+RNM3P#NCC_M0D_VN4o#Rn.6;R
+b@:@44::44+:.40.:sRkCfjj:Rk0sCsR0keCRB
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+@bR@4U:(.n::n4(:4d+.v:1_Qqvtjqr:R(9fjj:RFoE#10Rvv_qQrtqj9:(R.h_j_,h.h4,_,..hd_.,.h_c_,h.h6,_,.nh(_.;H
NR03sD0C_F;R4
RNH#_$MV_#lH"8R(n4(.n4(4
";N3HRs_0DFosHMCNlRv"1_Qqvt;q"
@@ -501,10 +487,10 @@ NR#3VlF_0#"0R1qv_vqQtR;U"
RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j4jsjj4Rjjjj4sjj4R4jjjjjjjj4s444Rjjjjjjj4;s"
RNH3lV#_HFsolMNC1R"vv_qQ"tq;H
NR#3Vl0_#Ns0CC4oR;H
-NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9
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+";s@R@Uj:d.::cd:j..4c+.v:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9rd
=ST1qv_vqQtr
-.9S17=vv_qQ_tqM6#r9B
+d9Sh7=__U.HB
SpBi=pmi_1_ZQO)
S=a)1_
H;N3HRsC0D_R0F4N;
@@ -516,10 +502,10 @@ HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjj
HVR3#Fl_sMHoNRlC"_1vqtvQq
";N3HRV_#l#00NCosCR
4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R
-s@:@Ud:4cc4:dcd:.+:4.1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtq4S9
-Tv=1_Qqvt4qr97
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+Tv=1_Qqvt.qr97
+S=_1vqtvQq#_Mr
+69SiBp=iBp_Zm1Q
_OS))=1Ha_;H
NR03sD0C_F;R4
RNH#_$MV_#lH"8R(n4(.n4(4
@@ -530,9 +516,9 @@ RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j
RNH3lV#_HFsolMNC1R"vv_qQ"tq;H
NR#3Vl0_#Ns0CC4oR;H
NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9
-';s@R@U4:dg::cd:4g.4.+.v:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9rj
+';s@R@U4:dU::cd:4U.4d+.v:1_Qqvtjqr:R(9fjj:ROlNEwR7wR)]blsHR_1vqtvQq9r4
=ST1qv_vqQtr
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+49S17=vv_qQ_tqMn#r9B
SpBi=pmi_1_ZQO)
S=a)1_
H;N3HRsC0D_R0F4N;
@@ -544,58 +530,58 @@ HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjj
HVR3#Fl_sMHoNRlC"_1vqtvQq
";N3HRV_#l#00NCosCR
4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R
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-Tu=Qpd_jjr_OjS9
-7_=h4Sn
-B=piB_pimQ1Z_SO
-11=)a;_H
-RNH3Ds0_HFsolMNCQR"ujp_d;j"
-RNH3VkMs_NOHCM8G;Rj
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-S=pQu_jjd_4Or97
-S=4h_(B
-SpBi=pmi_1_ZQO1
-S=a)1_
-H;N3HRs_0DFosHMCNlRu"Qpd_jj
-";N3HRksMVNHO_MG8CR
-4;s@R@Uj:4..:6:.4j:+664Q.:ujp_d.jr:Rj9fjj:ROlNEwR7wR1]blsHRpQu_jjd71ww]9r.
-=STQ_upj_djO9r.
-=S7hU_4
+s@:@Ud:.dc.:dd.:.+:4.1qv_vqQtr(j:9jRf:ljRNROE7)ww]sRbH1lRvv_qQrtqjS9
+Tv=1_Qqvtjqr97
+S=_1vqtvQq#_Mr
+(9SiBp=iBp_Zm1Q
+_OS))=1Ha_;H
+NR03sD0C_F;R4
+RNH#_$MV_#lH"8R(n4(.n4(4
+";N3HRs_0DFosHMCNlRv"1_Qqvt;q"
+RNH3lV#_FVslR#0"_1vqtvQq"Rd;H
+NR#3VlF_0#"0R1qv_vqQtR;U"
+RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j4jsjj4Rjjjj4sjj4R4jjjjjjjj4s444Rjjjjjjj4;s"
+RNH3lV#_HFsolMNC1R"vv_qQ"tq;H
+NR#3Vl0_#Ns0CC4oR;H
+NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9
+';s@R@Uj:4..:6:.4j:+664Q.:ujp_d.jr:Rj9fjj:ROlNEwR7wR1]blsHRpQu_jjd71ww]9rj
+=STQ_upj_djO9rj
+=S7hn_4
pSBip=Bi1_mZOQ_
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HsR30FD_sMHoNRlC"pQu_jjd"N;
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+=S7h(_(_SH
B=piB_pimQ1Z_SO
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RNH3Ds0CF_0R
@@ -608,8 +594,8 @@ RNH3lV#_#0F01R"vv_qQRtqU
RNH3lV#_N#00CCso;R4
RNH3HFso#HM0lMNC1R'vv_qQrtqj9:('s;
RU@@:..U:.c:U..:j.+4:_1vqtvQq:rj(f9RjR:jlENORw7w)b]RsRHl1qv_vqQtr
-c9S1T=vv_qQrtqcS9
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pSBip=Bi1_mZOQ_
=S))_1aHN;
HsR30_DC04FR;H
@@ -621,306 +607,320 @@ NR#3VlN_0L#DC0jR"j4jRjjjjjsjjjRj4jj4jjjjjsjj4R4jjjjjjj4sj4jRjjj4jj4jsjjjRj4jjjsj
NR#3Vls_FHNoMl"CR1qv_vqQt"N;
HVR3##l_0CN0sRCo4N;
HFR3sHHoMM#0NRlC'_1vqtvQq:rj(;9'
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-RU@@:.4j::6.4:j.646+.v:eqh_QajRf:ljRNROE71ww]sRbHelRvQq_hSa
-Tv=eqh_Qa7
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-";N3HR#_$MH0MHPRND";4"
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-(;s@R@Uj:4..:6:.4j:+664A.:tiqB_jjd_aQhR:fjjNRlO7ERw]w1RHbsltRAq_Bij_djQ
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-RU@@:U4j::d.4:jUd4c+.b:Ok#_C0:rdjf9RjR:jlENORw7wRHbslbROk#_C09r4
-=STO_bkCr#04S9
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-=S7hc_4
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+=ST7B1qih_Qa9r4
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B=piB_pimQ1Z_SO
11=)a;_H
-RNH3Ds0_HFsolMNCwR"uBz_1h_Qa
-";N3HR#_$MH0MHPRND";4"
-RNH3_HMDbFFR
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NR$3#MM_HHN0PD4R""s;
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+=S7h6_4
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RNH3M#$_HHM0DPNR""4;H
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_OS)1=1Ha_;H
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pSBip=Bi1_mZOQ_
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SpBi=pmi_1_ZQO1
S=a)1_
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";N3HR#_$MH0MHPRND";4"
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-4;s@R@U4:4(::.4:4(d.+4:iBp_aBhrRj9fjj:ROlNEwR7wsRbHBlRpBi_hjar9T
-S=iBp_aBhr
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H#R3$HM_MPH0N"DR4
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H#R3$HM_MPH0N"DR4
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-S=iBp_u X_SO
-7p=Biz_ma)_u B
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+=S7h
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-4SQ=kOb_0C#_4j__M3kjs;
-R:fjjNRlOQERhbeRsRHlQ_upj_djj__j3Ss
-mu=Qpd_jj__jjk_3MSd
+4nS=QjQ_upj_djj__j34kM
+4SQ=pQu_jjd_jj__M3kjs;
+R:fjjNRlOQERhbeRsRHlQ_upj_djj__43Ss
+mu=Qpd_jj__j4k_3MSd
QOj=D3 \k_McO_D j_jj8
-8;sjRf:ljRNROEq.h7RHbsluRQpd_jj__jjl_3
-=SmQ_upj_djj__j34kM
-jSQ=pQu_jOr9Q
-S4D=O k\3MOc_Dj _j8j_8s;
-R:fjjNRlOqERhR7.blsHRpQu_jjd_jj__
-3MSQm=ujp_djj__3j_k
-MjS=QjQ_upj_djO9rj
-4SQ=pQu_jjd_jj__M3kds;
-R:fjjNRlOmER)b.RsRHlQ_upj_djj__j3Sb
-m_=h4Sn
-QQj=ujp_djj__3j_k
-M4S=Q4Q_upj_djj__j3jkM;R
-sfjj:ROlNEhRQesRbHQlRujp_djj__34_sm
-S=pQu_jjd_4j__M3kdQ
-SjD=O k\3MOc_Dj _j8j_8s;
+4;sjRf:ljRNROEq.h7RHbsluRQpd_jj__j4l_3
+=SmQ_upj_djj__434kM
+jSQ=pQu_4Or9Q
+S4D=O k\3MOc_Dj _j8j_4s;
R:fjjNRlOqERhR7.blsHRpQu_jjd_4j__
-3lSQm=ujp_djj__34_k
-M4S=QjQ_upO9r4
-4SQ= OD\M3kcD_O j_jj8_8;R
-sfjj:ROlNEhRq7b.RsRHlQ_upj_djj__43SM
-mu=Qpd_jj__j4k_3MSj
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+4SQ=pQu_jjd_4j__M3kds;
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+m_=h4S(
+QQj=ujp_djj__34_k
+M4S=Q4Q_upj_djj__43jkM;R
+sfjj:ROlNEhRQesRbHQlRujp_djj__3._sm
+S=pQu_jjd_.j__M3kdQ
+SjD=O k\3MOc_Dj _j8j_4s;
+R:fjjNRlOqERhR7.blsHRpQu_jjd_.j__
+3lSQm=ujp_djj__3._k
+M4S=QjQ_upO9r.
+4SQ= OD\M3kcD_O j_jj4_8;R
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QQj=ujp_dOj_r
-49S=Q4Q_upj_djj__43dkM;R
-sfjj:ROlNE)Rm.sRbHQlRujp_djj__34_bm
-S=4h_(Q
-Sju=Qpd_jj__j4k_3MS4
-QQ4=ujp_djj__34_k;Mj
-fsRjR:jlENOReQhRHbsluRQpd_jj__j.s_3
-=SmQ_upj_djj__.3dkM
-jSQ= OD\M3kcD_O j_jj8_8;R
-sfjj:ROlNEhRq7b.RsRHlQ_upj_djj__.3Sl
-mu=Qpd_jj__j.k_3MS4
-QQj=uOp_r
-.9S=Q4O\D 3ckM_ OD_jjj_;88
-fsRjR:jlENOR7qh.sRbHQlRujp_djj__3._Mm
-S=pQu_jjd_.j__M3kjQ
-Sju=Qpd_jjr_O.S9
-QQ4=ujp_djj__3._k;Md
-fsRjR:jlENOR.m)RHbsluRQpd_jj__j.b_3
-=SmhU_4
-jSQ=pQu_jjd_.j__M3k4Q
-S4u=Qpd_jj__j.k_3M
-j;
+.9S=Q4Q_upj_djj__.3dkM;R
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+Sju=Qpd_jj__j.k_3MS4
+QQ4=ujp_djj__3._k;Mj
+fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\M3k4O6_Dj _j8j_jm
+S=N#00lC_NHOEM3C\k6M4_ OD_jjj__8jjQ
+Sj0=#N_0ClENOH\MC3UkM_ OD_jjj__8jHQ
+S40=#N_0ClENOH\MC34kMdD_O j_jjj_8_
+H;sjRf:ljRNROEQRheblsHRN#00lC_NHOEM3C\kdM4_ OD_jjj__8j4
+_HS#m=0CN0_OlNECHM\M3k4Od_Dj _j8j_j__4HQ
+Sj0=#N_0ClENOH\MC34kMdD_O j_jjj_8_
+4;sjRf:ljRNROEq.h7RHbslvR1_QqvtMq_#._Nr
+(9Shm=_g4j
+jSQ=_1vqtvQq9rj
+4SQ=N#00lC_NHOEM3C\kdM4_ OD_jjj__8j4;_H
+fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMH#__rN.4S9
+m_=hgSg
+Qhj=_
+g.S=Q41qv_vqQt_nHr9s;
+R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M_NH_.9rj
+=SmhU_g
+jSQ=gh_4Q
+S4v=1_QqvtHq_r;(9
+fsRjR:jlENOReQhRHbslvR1_QqvtHq_r
+n9S1m=vv_qQ_tqH9rn
+jSQ=_1vqtvQq9rn;R
+sfjj:ROlNEhRQesRbH1lRvv_qQ_tqH9r(
+=Sm1qv_vqQt_(Hr9Q
+Sjv=1_Qqvt(qr9s;
+R:fjjNRlOqERhR7.blsHRN#00lC_NHOEM3C\k_M6O_D j_djH._N
+=Smhn_g
+jSQ=_1vqtvQqr_HnS9
+Q14=vv_qQ_tqH9r(;R
+sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3MLn_o NO_jjj
+=Sm#00NCN_lOMEHCk\3MLn_o NO_jjj_Sj
+QAj=tiqB_jjj_SO
+QO4=D3 \k_McO_D j_jj8H4_;R
+sfjj:ROlNEhRQesRbHAlRtiqB_jjd_aQh_sj3
+=SmABtqid_jjh_Qa3_jk
+MdS=Qj#00NCN_lOMEHCk\3MLn_o NO_jjj;R
+sfjj:ROlNEhRq7b.RsRHlABtqid_jjh_Qa3_jlm
+S=qAtBji_dQj_hja_34kM
+jSQ=qAtBji_jOj_
+4SQ=N#00lC_NHOEM3C\k_MnLOoN j_jjs;
+R:fjjNRlOqERhR7.blsHRqAtBji_dQj_hja_3SM
+mt=Aq_Bij_djQ_hajM3kjQ
+Sjt=Aq_Bij_djQ
+haS=Q4ABtqid_jjh_Qa3_jk;Md
+fsRjR:jlENOR.m)RHbsltRAq_Bij_djQ_haj
+3bShm=_
+44S=QjABtqid_jjh_Qa3_jk
+M4S=Q4ABtqid_jjh_Qa3_jk;Mj
+fsRjR:jlENOR7qh.sRbH7lRaiqB_h1YB__4#kJlG4N_
+=Sm7BaqiY_1h4B__l#Jk_GN4Q
+Sj1=q_jjd_SH
+Q74=aiqB_h1YB__4#kJlGHN_;R
+sfjj:ROlNEhRQesRbH#lR0CN0_OlNECHM\M3kcO._Dj _dHj_
+=Sm#00NCN_lOMEHCk\3M_c.O_D j_djHQ
+Sj0=#N_0ClENOH\MC3ckM.D_O d_jjs;
+R:fjjNRlOqERhR7.blsHR4kM__N#j_djdm
+S=4kM__N#j_djd
+_jS=Qjqj1_dHj_
+4SQ=N#00lC_NHOEM3C\k.Mc_ OD_jjd;R
+sfjj:ROlNEhRq7b.RsRHl#00NCN_lOMEHCk\3M_4(O_D j
+djS#m=0CN0_OlNECHM\M3k4O(_Dj _djj_
+jSQ=_q1j_djHQ
+S4p=Bid_jj;_H
+fsRjR:jlENOReQhRHbslpRBid_jj
+_HSBm=pji_dHj_
+jSQ=iBp_jjd_
+O;sjRf:ljRNROEq.h7RHbsl0R#N_0ClENOH\MC34kM_ OD_jjd
+=Sm#00NCN_lOMEHCk\3MO4_Dj _djj_
+jSQ=_Atj_djO
+_HS=Q4B_pij_djOs;
+R:fjjNRlOQERhbeRsRHlqr_H4
+g9Sqm=_4HrgS9
+Qqj=_4Org
+9;sjRf:ljRNROEQRheblsHRHq_r94U
+=Smqr_H4
+U9S=Qjqr_O4;U9
+fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\73z1j_jjh_Qa
+_US#m=0CN0_OlNECHM\73z1j_jjh_Qa__UjQ
+Sj_=qOr_HjS9
+Qh4=_c4c_
+H;sjRf:ljRNROEq.h7RHbsl0R#N_0ClENOH\MC31p7_jjj_aQh_SU
+m0=#N_0ClENOH\MC31p7_jjj_aQh_jU_
+jSQ=4h_cHc_
+4SQ=N#00lC_NHOEM3C\kcMd_ OD_jjj_;8j
+fsRjR:jlENOReQhRHbslvR1_QqvtHq_r
+69S1m=vv_qQ_tqH9r6
+jSQ=_1vqtvQq9r6;R
+sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#H._Nr
+d9Shm=_.4j
+jSQ=_1vqtvQqr_HcS9
+Q14=vv_qQ_tqH9r6;R
+sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#H9rd
+=Smhj_U_SH
+QBj=pji_j7j_j
+_HS=Q4hj_4.;_H
+fsRjR:jlENOReQhRHbsl7Rz1j_jjh_Qa__j#kJlG4N__SH
+m7=z1j_jjh_Qa__j#kJlG4N__SH
+Qzj=7j1_jQj_hja__l#Jk_GN4s;
+R:fjjNRlOQERhbeRsRHlz_71j_jjQ_hajJ_#lNkG_SH
+m7=z1j_jjh_Qa__j#kJlGHN_
+jSQ=1z7_jjj_aQh_#j_JGlkNs;
+R:fjjNRlOqERhR7.blsHR4kM__N#j_djc4_g
+=Smhc_4cQ
+Sj7=z1j_jjh_Qa__j#kJlG4N__SH
+Qz4=7j1_jQj_hja__l#Jk_GNHs;
+R:fjjNRlOQERhbeRsRHl7j1_dHj_
+=Sm7j1_dHj_
+jSQ=_71j_djOs;
+R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M_FH_.9r4
+=Smh._g_Sj
+QBj=pji_j7j_j
+_HS=Q41qv_vqQtr;(9
+fsRjR:jlENOR7qh.sRbH1lRvv_qQ_tqMH#_r
+49Shm=__((HQ
+Sj_=hgHg_
+4SQ=4h_4H4_;R
+sfjj:ROlNEhRq7b.RsRHl1qv_vqQt__M#H9rj
+=Smh6_(_SH
+QBj=pji_j7j_jQ
+S4_=hgHU_;R
+sfjj:ROlNEhRQesRbHqlR1d_jjj_jjY_1hHB_
+=Smqj1_djj_j1j_Y_hBHQ
+Sj1=q_jjd_jjj_h1YBs;
+R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M_NH_.r_j4S9
+m_=h4
+44S=Qjqj1_djj_j1j_Y_hBHQ
+S4D=O k\3MOc_Dj _j8j_4s;
+R:fjjNRlOqERhR7.blsHR_1vqtvQq#_M__N.j9r.
+=Smhj_44Q
+Sj_=h4
+44S=Q41qv_vqQtr;n9
+fsRjR:jlENOReQhRHbsl_RqHcr.9m
+S=Hq_r9.c
+jSQ=Oq_r9.c;R
+sfjj:ROlNEhRQesRbHqlR_.Hr6S9
+m_=qH6r.9Q
+Sj_=qO6r.9s;
+R:fjjNRlOQERhbeRsRHlqr_H.
+n9Sqm=_.HrnS9
+Qqj=_.Orn
+9;sjRf:ljRNROEQRheblsHRHq_r9.(
+=Smqr_H.
+(9S=Qjqr_O.;(9
+fsRjR:jlENOReQhRHbsl_RqHUr.9m
+S=Hq_r9.U
+jSQ=Oq_r9.U;R
+sfjj:ROlNEhRQesRbHqlR_.HrgS9
+m_=qHgr.9Q
+Sj_=qOgr.9s;
+R:fjjNRlOQERhbeRsRHlqr_Hd
+j9Sqm=_dHrjS9
+Qqj=_dOrj
+9;sjRf:ljRNROEQRheblsHRHq_r9d4
+=Smqr_Hd
+49S=Qjqr_Od;49
+fsRjR:jlENOReQhRHbsl_RhgH(_
+=Smh(_g_SH
+Qhj=_;g(
+fsRjR:jlENOR7qh.sRbH7lR1iqB_aQh_#4_JGlkNm
+S=q71BQi_h4a__l#Jk
+GNS=Qjqj1_dHj_
+4SQ=gh_(;_H
+fsRjR:jlENOReQhRHbsluReqY_1h4B__l#Jk_GNHm
+S=qeu_h1YB__4#kJlGHN_
+jSQ=qeu_h1YB__4#kJlG
+N;sjRf:ljRNROEq.h7RHbsluReqY_1h4B__l#Jk_GN4m
+S=qeu_h1YB__4#kJlG4N_
+jSQ=_q1j_djHQ
+S4u=eqY_1h4B__l#Jk_GNHs;
+R:fjjNRlOqERhR7.blsHR4kM__N#j_djcm
+S=4kM__N#j_djcQ
+Sj1=q_jjd_SH
+Qh4=_c4c;R
+sfjj:ROlNEhRQesRbH#lR0CN0_OlNECHM\M3k4Nd_#j_jjM_H0
+_HS#m=0CN0_OlNECHM\M3k4Nd_#j_jjM_H0
+_HS=Qj#00NCN_lOMEHCk\3M_4dNj#_jHj_M
+0;sjRf:ljRNROEQRheblsHRa)1_SH
+m1=)a
+_HS=Qj)_1aOs;
+R:fjjNRlOQERhbeRsRHlB_piB_haH9rj
+=SmB_piB_haH9rj
+jSQ=iBp_aBhr;j9
+fsRjR:jlENOR7qh.sRbH#lR0CN0_OlNECHM\M3knOj_Dj _j8j_jm
+S=N#00lC_NHOEM3C\kjMn_ OD_jjj__8jHQ
+Sja=7q_Bi1BYh
+4SQ=qeu_h1YBs;
+R:fjjNRlOQERhbeRsRHlABtqid_jjh_Qa
+_HSAm=tiqB_jjd_aQh_SH
+QAj=tiqB_jjd_aQh;R
+sfjj:ROlNEhRQesRbHwlRuBz_1h_Qa
+_HSwm=uBz_1h_Qa
+_HS=Qjw_uzBQ1_h
+a;sjRf:ljRNROEQRheblsHR1z7_jjj_aQh_sj3
+=Smz_71j_jjQ_hajM3kdQ
+SjM=k4#_N_jjd_
+c;sjRf:ljRNROEq.h7RHbsl7Rz1j_jjh_Qa3_jlm
+S=1z7_jjj_aQh_kj3MS4
+Qzj=7j1_jQj_hSa
+Qk4=MN4_#d_jj;_c
+fsRjR:jlENOR7qh.sRbHzlR7j1_jQj_hja_3SM
+m7=z1j_jjh_Qa3_jk
+MjS=Qj#00NCN_lOMEHCz\37j1_jQj_hUa_
+4SQ=1z7_jjj_aQh_kj3M
+d;sjRf:ljRNROEmR).blsHR1z7_jjj_aQh_bj3
+=Smh
+_4S=Qjz_71j_jjQ_hajM3k4Q
+S47=z1j_jjh_Qa3_jk;Mj
+fsRjR:jlENOReQhRHbsl7Rp1j_jjh_Qa3_jsm
+S=1p7_jjj_aQh_kj3MSd
+Qkj=MN4_#d_jj;_c
+fsRjR:jlENOR7qh.sRbHplR7j1_jQj_hja_3Sl
+m7=p1j_jjh_Qa3_jk
+M4S=Qjp_71j_jjQ
+haS=Q4k_M4Nj#_dcj_;R
+sfjj:ROlNEhRq7b.RsRHlp_71j_jjQ_haj
+3MSpm=7j1_jQj_hja_3jkM
+jSQ=N#00lC_NHOEM3C\p_71j_jjQ_haUQ
+S47=p1j_jjh_Qa3_jk;Md
+fsRjR:jlENOR.m)RHbsl7Rp1j_jjh_Qa3_jbm
+S=.h_
+jSQ=1p7_jjj_aQh_kj3MS4
+Qp4=7j1_jQj_hja_3jkM;R
+sfjj:ROlNEhRQesRbHelRu1q_Y_hBj
+3sSem=u1q_Y_hBjM3kdQ
+Sju=eqY_1h4B__l#Jk_GN4s;
+R:fjjNRlOqERhR7.blsHRqeu_h1YB3_jlm
+S=qeu_h1YB3_jk
+M4S=Qje_uq1BYh
+4SQ=qeu_h1YB__4#kJlG4N_;R
+sfjj:ROlNEhRq7b.RsRHle_uq1BYh_Mj3
+=Sme_uq1BYh_kj3MSj
+Qej=u1q_Y_hB4J_#lNkG_SH
+Qe4=u1q_Y_hBjM3kds;
+R:fjjNRlOmER)b.RsRHle_uq1BYh_bj3
+=Smh
+_(S=Qje_uq1BYh_kj3MS4
+Qe4=u1q_Y_hBjM3kjs;
+R:fjjNRlOQERhbeRsRHl7B1qih_Qa__j4s_3
+=Sm7B1qih_Qa__j4k_3MSd
+Q7j=1iqB_aQh_#4_JGlkNs;
+R:fjjNRlOqERhR7.blsHRq71BQi_hja__34_lm
+S=q71BQi_hja__34_k
+M4S=Qj7B1qih_Qa9r4
+4SQ=q71BQi_h4a__l#Jk;GN
+fsRjR:jlENOR7qh.sRbH7lR1iqB_aQh_4j__
+3MS7m=1iqB_aQh_4j__M3kjQ
+Sj_=hgH(_
+4SQ=q71BQi_hja__34_k;Md
+fsRjR:jlENOR.m)RHbsl1R7q_BiQ_haj__43Sb
+m_=hgQ
+Sj1=7q_BiQ_haj__434kM
+4SQ=q71BQi_hja__34_k;Mj
diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr
index 4254163..3566d12 100644
--- a/Logic/BUS68030.srr
+++ b/Logic/BUS68030.srr
@@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
-#Thu May 15 23:02:39 2014
+#Fri May 16 17:07:02 2014
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
@N|Running in 64-bit mode
@@ -18,16 +18,19 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed -
VHDL syntax check successful!
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":6:7:6:14|Synthesizing work.bus68030.behavioral
-@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":106:7:106:15|Signal clk_030_d is undriven
+@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":105:7:105:15|Signal clk_030_d is undriven
Post processing for work.bus68030.behavioral
@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Pruning register CLK_REF(1 downto 0)
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Pruning register cpu_est_d(3 downto 0)
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Pruning register CLK_000_CNT(3 downto 0)
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":111:32:111:34|Pruning register cpu_est_d(3 downto 0)
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":110:32:110:34|Pruning register CLK_000_D5
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":109:32:109:34|Pruning register CLK_000_D4
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Pruning register CLK_000_D3
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":107:32:107:34|Pruning register CLK_000_D2
@W: CL190 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:52:102:55|Optimizing register bit DSACK_INT(0) to a constant 1
@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":102:52:102:55|Pruning register bit 0 of DSACK_INT(1 downto 0)
-@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:2:117:3|Register bit CLK_CNT(1) is always 0, optimizing ...
-@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":117:2:117:3|Pruning register bit 1 of CLK_CNT(1 downto 0)
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":108:32:108:34|Trying to extract state machine for register cpu_est
+@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":120:2:120:3|Register bit CLK_CNT(1) is always 0, optimizing ...
+@W: CL260 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":120:2:120:3|Pruning register bit 1 of CLK_CNT(1 downto 0)
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":111:32:111:34|Trying to extract state machine for register cpu_est
@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Trying to extract state machine for register SM_AMIGA
Extracted state machine for register SM_AMIGA
State machine has 8 reachable states with original encodings of:
@@ -42,7 +45,7 @@ State machine has 8 reachable states with original encodings of:
@W: CL249 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":176:2:176:3|Initial value is not supported on state machine SM_AMIGA
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu May 15 23:02:39 2014
+# Fri May 16 17:07:02 2014
###########################################################]
Map & Optimize Report
@@ -73,8 +76,8 @@ IBUF 35 uses
BUFTH 7 uses
OBUF 15 uses
BI_DIR 2 uses
-AND2 147 uses
-INV 119 uses
+AND2 146 uses
+INV 116 uses
OR2 17 uses
XOR2 2 uses
@@ -86,6 +89,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 95MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Thu May 15 23:02:41 2014
+# Fri May 16 17:07:04 2014
###########################################################]
diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs
index db16274..aff0e22 100644
Binary files a/Logic/BUS68030.srs and b/Logic/BUS68030.srs differ
diff --git a/Logic/Programming.xcf b/Logic/Programming.xcf
index 6f34ca5..4445d57 100644
--- a/Logic/Programming.xcf
+++ b/Logic/Programming.xcf
@@ -18,9 +18,9 @@
1
0
- C:\Users\Matze\Amiga\Hardwarehacks\68030-TK\Logic\68030_tk.jed
- 04/26/14 13:40:41
- 0x04D9
+ C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed
+ 05/16/14 11:08:27
+ 0xB88F
Erase,Program,Verify