diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd index ace6c00..b9299da 100644 --- a/Logic/68030-68000-bus.vhd +++ b/Logic/68030-68000-bus.vhd @@ -326,7 +326,7 @@ begin DSACK1_INT <= '1'; AS_000_INT <= '1'; DS_000_ENABLE <= '0'; - + RW_000_INT <= '1'; elsif( --CLK_030 = '1' AND --68030 has a valid AS on high clocks AS_030_D0 = '0' AND --as set BGACK_000='1' AND --no dma -cycle @@ -494,7 +494,7 @@ begin -- bus drivers AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT; - AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' AND AMIGA_BUS_ENABLE_INT ='0' ELSE + AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' ELSE '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE '1'; AMIGA_BUS_ENABLE_LOW <= '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' ELSE diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl index 35b3132..99f7a55 100644 --- a/Logic/68030_TK.tcl +++ b/Logic/68030_TK.tcl @@ -279512,3 +279512,719 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6 ########## Tcl recorder end at 10/05/14 21:32:32 ########### + +########## Tcl recorder starts at 10/09/14 13:40:38 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/09/14 13:40:38 ########### + + +########## Tcl recorder starts at 10/10/14 22:35:33 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/14 22:35:33 ########### + + +########## Tcl recorder starts at 10/10/14 22:35:33 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/14 22:35:33 ########### + + +########## Tcl recorder starts at 10/10/14 22:38:12 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/14 22:38:12 ########### + + +########## Tcl recorder starts at 10/10/14 22:38:12 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/14 22:38:12 ########### + + +########## Tcl recorder starts at 10/10/14 22:39:56 ########## + +# Commands to make the Process: +# Hierarchy +if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/14 22:39:56 ########### + + +########## Tcl recorder starts at 10/10/14 22:39:56 ########## + +# Commands to make the Process: +# JEDEC File +if [catch {open BUS68030.cmd w} rspFile] { + puts stderr "Cannot create response file BUS68030.cmd: $rspFile" +} else { + puts $rspFile "STYFILENAME: 68030_tk.sty +PROJECT: BUS68030 +WORKING_PATH: \"$proj_dir\" +MODULE: BUS68030 +VHDL_FILE_LIST: 68030-68000-bus.vhd +OUTPUT_FILE_NAME: BUS68030 +SUFFIX_NAME: edi +PART: M4A5-128/64-10VC +" + close $rspFile +} +if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete BUS68030.cmd +if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [catch {open 68030_tk.rsp w} rspFile] { + puts stderr "Cannot create response file 68030_tk.rsp: $rspFile" +} else { + puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" +" + close $rspFile +} +if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +file delete 68030_tk.rsp +if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} +if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] { + return +} else { + vwait done + if [checkResult $done] { + return + } +} + +########## Tcl recorder end at 10/10/14 22:39:56 ########### + diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf index f843dbd..b714b57 100644 --- a/Logic/68030_tk.crf +++ b/Logic/68030_tk.crf @@ -1,7 +1,7 @@ // Signal Name Cross Reference File // ispLEVER Classic 1.7.00.05.28.13 -// Design '68030_tk' created Sun Oct 05 21:32:39 2014 +// Design '68030_tk' created Fri Oct 10 22:40:03 2014 // LEGEND: '>' Functional Block Port Separator diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp new file mode 100644 index 0000000..79f4d0f --- /dev/null +++ b/Logic/68030_tk.grp @@ -0,0 +1,29 @@ + +GROUP MACH_SEG_A DS_030 RN_DS_030 inst_CLK_030_H inst_LDS_000_INT inst_AMIGA_BUS_ENABLE_DMA_HIGH + inst_AMIGA_BUS_ENABLE_DMA_LOW inst_UDS_000_INT AVEC CLK_000_N_SYNC_11_ + CLK_000_P_SYNC_2_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_8_ +GROUP MACH_SEG_B RESET RN_RESET IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ + IPL_030_2_ RN_IPL_030_2_ RESET_DLY_7_ RESET_DLY_6_ inst_nEXP_SPACE_D0 + CLK_EXP CLK_000_P_SYNC_1_ CLK_000_P_SYNC_4_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_5_ + +GROUP MACH_SEG_C SM_AMIGA_6_ inst_DS_000_ENABLE inst_AS_000_INT SM_AMIGA_4_ + SM_AMIGA_1_ SM_AMIGA_5_ AMIGA_BUS_ENABLE_LOW sm_amiga_ns_0_3_0__n + inst_CLK_000_PE CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ + +GROUP MACH_SEG_D AMIGA_ADDR_ENABLE RN_AMIGA_ADDR_ENABLE VMA RN_VMA BG_000 + RN_BG_000 inst_DTACK_D0 LDS_000 UDS_000 DTACK AMIGA_BUS_ENABLE_HIGH + cpu_est_1_ cpu_est_2_ cpu_est_0_ inst_CLK_000_D0 CLK_000_N_SYNC_4_ + inst_CLK_000_NE_D0 +GROUP MACH_SEG_E CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 CLK_000_P_SYNC_0_ + CLK_000_N_SYNC_0_ inst_CLK_000_NE CLK_000_N_SYNC_9_ inst_CLK_000_D1 + +GROUP MACH_SEG_F SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_7_ RESET_DLY_4_ RESET_DLY_3_ + RESET_DLY_2_ RESET_DLY_1_ RESET_DLY_0_ SM_AMIGA_0_ inst_VPA_D CLK_000_P_SYNC_8_ + CLK_000_N_SYNC_7_ CLK_OUT_PRE_Dreg inst_CLK_OUT_PRE_50 inst_CLK_OUT_PRE + +GROUP MACH_SEG_G RW RN_RW A0 RESET_DLY_5_ inst_AS_000_DMA SIZE_DMA_1_ SIZE_DMA_0_ + E RN_E SIZE_0_ CLK_DIV_OUT CLK_000_P_SYNC_9_ CLK_000_P_SYNC_3_ CLK_000_N_SYNC_1_ + CLK_000_N_SYNC_3_ +GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 BGACK_030 RN_BGACK_030 + inst_AS_030_000_SYNC inst_DS_030_D0 inst_AS_030_D0 inst_BGACK_030_INT_D + FPU_CS SIZE_1_ AS_030 CLK_000_N_SYNC_10_ \ No newline at end of file diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr index 4a1ff2f..1a812ef 100644 Binary files a/Logic/68030_tk.ipr and b/Logic/68030_tk.ipr differ diff --git a/Logic/68030_tk.jed b/Logic/68030_tk.jed new file mode 100644 index 0000000..c2c67b9 --- /dev/null +++ b/Logic/68030_tk.jed @@ -0,0 +1,1115 @@ +|--------------------------------------------| +|- ispLEVER Fitter Report File -| +|- Version 1.7.00.05.28.13 -| +|- (c)Copyright, Lattice Semiconductor 2002 -| +|--------------------------------------------| + + +TITLE: +AUTHOR: +PATTERN: +COMPANY: +REVISION: +DATE: Fri Oct 10 22:40:09 2014 + +ABEL mach447a + * +QP100* +QF54096* +G0*F0* +NOTE Part Number : M4A5-128/64-10VC * +NOTE Handling of Preplacements No Change * +NOTE Use placement data from 68030_tk.vct * +NOTE Global clocks routable as PT clocks? N * +NOTE 22V10/MACH1XX/2XX S/R Compatibility? Y * +NOTE SET/RESET treated as DONT_CARE? Y * +NOTE Reduce Unforced Global Clocks? N * +NOTE Iterate between partitioning and place/route? Y * +NOTE Balanced partitioning? Y * +NOTE Reduce Routes Per Placement? N * +NOTE Spread Placement? Y * +NOTE Run Time Upper Bound in 15 minutes 0 * +NOTE Zero Hold Time For Input Registers? Y * +NOTE Table of pin names and numbers* +NOTE PINS A_27_:16 A_26_:17 SIZE_1_:79 A_25_:18 A_24_:19* +NOTE PINS A_31_:4 A_23_:85 A_22_:84 A_21_:94 A_20_:93 IPL_2_:68* +NOTE PINS A_19_:97 A_18_:95 FC_1_:58 A_17_:59 AS_030:82 A_16_:96* +NOTE PINS AS_000:42 IPL_1_:56 UDS_000:32 IPL_0_:67 LDS_000:31* +NOTE PINS FC_0_:57 A1:60 nEXP_SPACE:14 BERR:41 BG_030:21* +NOTE PINS BGACK_000:28 CLK_030:64 CLK_000:11 CLK_OSZI:61* +NOTE PINS CLK_DIV_OUT:65 CLK_EXP:10 FPU_CS:78 FPU_SENSE:91* +NOTE PINS DTACK:30 AVEC:92 VPA:36 RST:86 AMIGA_BUS_DATA_DIR:48* +NOTE PINS AMIGA_BUS_ENABLE_LOW:20 AMIGA_BUS_ENABLE_HIGH:34* +NOTE PINS CIIN:47 SIZE_0_:70 A_30_:5 A_29_:6 A_28_:15 IPL_030_2_:9* +NOTE PINS IPL_030_1_:7 RW_000:80 IPL_030_0_:8 DS_030:98 A0:69* +NOTE PINS BG_000:29 BGACK_030:83 DSACK1:81 E:66 VMA:35 RESET:3* +NOTE PINS RW:71 AMIGA_ADDR_ENABLE:33 * +NOTE Table of node names and numbers* +NOTE NODES RN_SIZE_1_:271 RN_AS_030:281 RN_AS_000:203 RN_UDS_000:185 * +NOTE NODES RN_LDS_000:191 RN_BERR:197 RN_DTACK:173 RN_SIZE_0_:263 * +NOTE NODES RN_IPL_030_2_:131 RN_IPL_030_1_:143 RN_RW_000:269 * +NOTE NODES RN_IPL_030_0_:137 RN_DS_030:101 RN_A0:257 RN_BG_000:175 * +NOTE NODES RN_BGACK_030:275 RN_DSACK1:287 RN_E:251 RN_VMA:179 * +NOTE NODES RN_RESET:125 RN_RW:245 RN_AMIGA_ADDR_ENABLE:181 * +NOTE NODES cpu_est_0_:182 cpu_est_1_:193 inst_AS_000_INT:163 * +NOTE NODES inst_AMIGA_BUS_ENABLE_DMA_HIGH:121 inst_AMIGA_BUS_ENABLE_DMA_LOW:115 * +NOTE NODES inst_AS_030_D0:283 inst_nEXP_SPACE_D0:133 inst_DS_030_D0:284 * +NOTE NODES inst_AS_030_000_SYNC:289 inst_BGACK_030_INT_D:278 * +NOTE NODES inst_AS_000_DMA:253 SIZE_DMA_0_:248 SIZE_DMA_1_:259 * +NOTE NODES inst_VPA_D:236 inst_UDS_000_INT:119 inst_LDS_000_INT:113 * +NOTE NODES inst_DTACK_D0:184 RESET_DLY_7_:146 inst_CLK_OUT_PRE_50:238 * +NOTE NODES inst_CLK_000_D1:205 inst_CLK_000_D0:194 sm_amiga_ns_0_3_0__n:169 * +NOTE NODES SM_AMIGA_7_:221 inst_CLK_OUT_PRE:232 inst_CLK_000_PE:155 * +NOTE NODES CLK_000_P_SYNC_9_:250 inst_CLK_000_NE:209 CLK_000_N_SYNC_11_:116 * +NOTE NODES cpu_est_2_:176 inst_CLK_000_NE_D0:188 SM_AMIGA_6_:167 * +NOTE NODES SM_AMIGA_4_:157 SM_AMIGA_0_:227 inst_CLK_030_H:109 * +NOTE NODES CLK_000_P_SYNC_0_:206 CLK_000_P_SYNC_1_:140 CLK_000_P_SYNC_2_:110 * +NOTE NODES CLK_000_P_SYNC_3_:266 CLK_000_P_SYNC_4_:134 CLK_000_P_SYNC_5_:170 * +NOTE NODES CLK_000_P_SYNC_6_:164 CLK_000_P_SYNC_7_:158 CLK_000_P_SYNC_8_:226 * +NOTE NODES CLK_000_N_SYNC_0_:200 CLK_000_N_SYNC_1_:260 CLK_000_N_SYNC_2_:128 * +NOTE NODES CLK_000_N_SYNC_3_:254 CLK_000_N_SYNC_4_:178 CLK_000_N_SYNC_5_:145 * +NOTE NODES CLK_000_N_SYNC_6_:104 CLK_000_N_SYNC_7_:242 CLK_000_N_SYNC_8_:103 * +NOTE NODES CLK_000_N_SYNC_9_:217 CLK_000_N_SYNC_10_:272 * +NOTE NODES RESET_DLY_0_:241 RESET_DLY_1_:235 RESET_DLY_2_:229 * +NOTE NODES RESET_DLY_3_:223 RESET_DLY_4_:239 RESET_DLY_5_:265 * +NOTE NODES RESET_DLY_6_:139 inst_DS_000_ENABLE:151 SM_AMIGA_1_:161 * +NOTE NODES SM_AMIGA_5_:152 SM_AMIGA_3_:224 SM_AMIGA_2_:230 * +NOTE NODES CLK_OUT_PRE_Dreg:233 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11110011111111* +E1 +1 +00000000 +1 +00000010 +1 +00000000 +1 +00000000 +1 +00000001 +1 +00000000 +1 +00000000 +1 +00000000 +1 +* +C83EE* +U00000000000000000000000000000000* +14B2 diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco new file mode 100644 index 0000000..1a2885b --- /dev/null +++ b/Logic/68030_tk.lco @@ -0,0 +1,254 @@ +[DEVICE] +Family = M4A5; +PartType = M4A5-128/64; +Package = 100TQFP; +PartNumber = M4A5-128/64-10VC; +Speed = -10; +Operating_condition = COM; +EN_Segment = No; +Pin_MC_1to1 = No; +EN_PinReserve_IO = Yes; +EN_PinReserve_BIDIR = Yes; +Voltage = 5.0; + +[REVISION] +RCS = "$Revision: 1.2 $"; +Parent = m4a5.lci; +SDS_File = m4a5.sds; +Design = 68030_tk.tt4; +DATE = 10/10/14; +TIME = 22:40:09; +Source_Format = Pure_VHDL; +Type = TT2; +Pre_Fit_Time = 1; + +[IGNORE ASSIGNMENTS] +Pin_Assignments = No; +Pin_Keep_Block = No; +Pin_Keep_Segment = No; +Group_Assignments = No; +Macrocell_Assignments = No; +Macrocell_Keep_Block = No; +Macrocell_Keep_Segment = No; +Pin_Reservation = No; +Block_Reservation = No; +Segment_Reservation = No; +Timing_Constraints = No; + +[CLEAR ASSIGNMENTS] +Pin_Assignments = No; +Pin_Keep_Block = No; +Pin_Keep_Segment = No; +Group_Assignments = No; +Macrocell_Assignments = No; +Macrocell_Keep_Block = No; +Macrocell_Keep_Segment = No; +Pin_Reservation = No; +Block_Reservation = No; +Segment_Reservation = No; +Timing_Constraints = No; + +[BACKANNOTATE ASSIGNMENTS] +Pin_Block = No; +Pin_Macrocell_Block = No; +Routing = No; + +[GLOBAL CONSTRAINTS] +Max_PTerm_Split = 16; +Max_PTerm_Collapse = 16; +Max_Pin_Percent = 100; +Max_Macrocell_Percent = 100; +Max_GLB_Input_Percent = 100; +Max_Seg_In_Percent = 100; +Logic_Reduction = Yes; +XOR_Synthesis = Yes; +DT_Synthesis = No; +Node_Collapse = Yes; +Run_Time = 0; +Set_Reset_Dont_Care = Yes; +Clock_Optimize = No; +In_Reg_Optimize = Yes; +Balanced_Partitioning = Yes; +Device_max_fanin = 33; +Device_max_pterms = 20; +Usercode = 0; +Usercode_Format = Hex; + +[LOCATION ASSIGNMENTS] +Layer = OFF; +A_27_ = pin,16,-,C,-; +A_26_ = pin,17,-,C,-; +SIZE_1_ = pin,79,-,H,-; +A_25_ = pin,18,-,C,-; +A_24_ = pin,19,-,C,-; +A_31_ = pin,4,-,B,-; +A_23_ = pin,85,-,H,-; +A_22_ = pin,84,-,H,-; +A_21_ = pin,94,-,A,-; +A_20_ = pin,93,-,A,-; +IPL_2_ = pin,68,-,G,-; +A_19_ = pin,97,-,A,-; +A_18_ = pin,95,-,A,-; +FC_1_ = pin,58,-,F,-; +A_17_ = pin,59,-,F,-; +AS_030 = pin,82,-,H,-; +A_16_ = pin,96,-,A,-; +AS_000 = pin,42,-,E,-; +IPL_1_ = pin,56,-,F,-; +UDS_000 = pin,32,-,D,-; +IPL_0_ = pin,67,-,G,-; +LDS_000 = pin,31,-,D,-; +FC_0_ = pin,57,-,F,-; +A1 = pin,60,-,F,-; +nEXP_SPACE = pin,14,-,-,-; +BERR = pin,41,-,E,-; +BG_030 = pin,21,-,C,-; +BGACK_000 = pin,28,-,D,-; +CLK_030 = pin,64,-,-,-; +CLK_000 = pin,11,-,-,-; +CLK_OSZI = pin,61,-,-,-; +CLK_DIV_OUT = pin,65,-,G,-; +CLK_EXP = pin,10,-,B,-; +FPU_CS = pin,78,-,H,-; +FPU_SENSE = pin,91,-,A,-; +DTACK = pin,30,-,D,-; +AVEC = pin,92,-,A,-; +VPA = pin,36,-,-,-; +RST = pin,86,-,-,-; +AMIGA_BUS_DATA_DIR = pin,48,-,E,-; +AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-; +AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-; +CIIN = pin,47,-,E,-; +SIZE_0_ = pin,70,-,G,-; +A_30_ = pin,5,-,B,-; +A_29_ = pin,6,-,B,-; +A_28_ = pin,15,-,C,-; +IPL_030_2_ = pin,9,-,B,-; +IPL_030_1_ = pin,7,-,B,-; +RW_000 = pin,80,-,H,-; +IPL_030_0_ = pin,8,-,B,-; +DS_030 = pin,98,-,A,-; +A0 = pin,69,-,G,-; +BG_000 = pin,29,-,D,-; +BGACK_030 = pin,83,-,H,-; +DSACK1 = pin,81,-,H,-; +E = pin,66,-,G,-; +VMA = pin,35,-,D,-; +RESET = pin,3,-,B,-; +RW = pin,71,-,G,-; +AMIGA_ADDR_ENABLE = pin,33,-,D,-; +cpu_est_0_ = node,-,-,D,6; +cpu_est_1_ = node,-,-,D,13; +inst_AS_000_INT = node,-,-,C,9; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,A,13; +inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,A,9; +inst_AS_030_D0 = node,-,-,H,9; +inst_nEXP_SPACE_D0 = node,-,-,B,5; +inst_DS_030_D0 = node,-,-,H,10; +inst_AS_030_000_SYNC = node,-,-,H,13; +inst_BGACK_030_INT_D = node,-,-,H,6; +inst_AS_000_DMA = node,-,-,G,5; +SIZE_DMA_0_ = node,-,-,G,2; +SIZE_DMA_1_ = node,-,-,G,9; +inst_VPA_D = node,-,-,F,10; +inst_UDS_000_INT = node,-,-,A,12; +inst_LDS_000_INT = node,-,-,A,8; +inst_DTACK_D0 = node,-,-,D,7; +RESET_DLY_7_ = node,-,-,B,14; +inst_CLK_OUT_PRE_50 = node,-,-,F,11; +inst_CLK_000_D1 = node,-,-,E,5; +inst_CLK_000_D0 = node,-,-,D,14; +sm_amiga_ns_0_3_0__n = node,-,-,C,13; +SM_AMIGA_7_ = node,-,-,F,0; +inst_CLK_OUT_PRE = node,-,-,F,7; +inst_CLK_000_PE = node,-,-,C,4; +CLK_000_P_SYNC_9_ = node,-,-,G,3; +inst_CLK_000_NE = node,-,-,E,8; +CLK_000_N_SYNC_11_ = node,-,-,A,10; +cpu_est_2_ = node,-,-,D,2; +inst_CLK_000_NE_D0 = node,-,-,D,10; +SM_AMIGA_6_ = node,-,-,C,12; +SM_AMIGA_4_ = node,-,-,C,5; +SM_AMIGA_0_ = node,-,-,F,4; +inst_CLK_030_H = node,-,-,A,5; +CLK_000_P_SYNC_0_ = node,-,-,E,6; +CLK_000_P_SYNC_1_ = node,-,-,B,10; +CLK_000_P_SYNC_2_ = node,-,-,A,6; +CLK_000_P_SYNC_3_ = node,-,-,G,14; +CLK_000_P_SYNC_4_ = node,-,-,B,6; +CLK_000_P_SYNC_5_ = node,-,-,C,14; +CLK_000_P_SYNC_6_ = node,-,-,C,10; +CLK_000_P_SYNC_7_ = node,-,-,C,6; +CLK_000_P_SYNC_8_ = node,-,-,F,3; +CLK_000_N_SYNC_0_ = node,-,-,E,2; +CLK_000_N_SYNC_1_ = node,-,-,G,10; +CLK_000_N_SYNC_2_ = node,-,-,B,2; +CLK_000_N_SYNC_3_ = node,-,-,G,6; +CLK_000_N_SYNC_4_ = node,-,-,D,3; +CLK_000_N_SYNC_5_ = node,-,-,B,13; +CLK_000_N_SYNC_6_ = node,-,-,A,2; +CLK_000_N_SYNC_7_ = node,-,-,F,14; +CLK_000_N_SYNC_8_ = node,-,-,A,1; +CLK_000_N_SYNC_9_ = node,-,-,E,13; +CLK_000_N_SYNC_10_ = node,-,-,H,2; +RESET_DLY_0_ = node,-,-,F,13; +RESET_DLY_1_ = node,-,-,F,9; +RESET_DLY_2_ = node,-,-,F,5; +RESET_DLY_3_ = node,-,-,F,1; +RESET_DLY_4_ = node,-,-,F,12; +RESET_DLY_5_ = node,-,-,G,13; +RESET_DLY_6_ = node,-,-,B,9; +inst_DS_000_ENABLE = node,-,-,C,1; +SM_AMIGA_1_ = node,-,-,C,8; +SM_AMIGA_5_ = node,-,-,C,2; +SM_AMIGA_3_ = node,-,-,F,2; +SM_AMIGA_2_ = node,-,-,F,6; +CLK_OUT_PRE_Dreg = node,-,-,F,8; +CIIN_0 = node,-,-,E,9; + +[GROUP ASSIGNMENTS] +Layer = OFF; + +[RESOURCE RESERVATIONS] +Layer = OFF; + +[SLEWRATE] +Default = SLOW; +FAST = AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH,AVEC,BG_000,LDS_000,UDS_000,DTACK,RW_000,AS_000,CLK_DIV_OUT,CLK_EXP,FPU_CS,AS_030,RW,SIZE_1_,SIZE_0_,BGACK_030,IPL_030_0_,IPL_030_1_,IPL_030_2_,RESET,CIIN,DS_030,BERR,A0,DSACK1; + +[PULLUP] +Default = Up; + +[NETLIST/DELAY FORMAT] +Delay_File = SDF; +Netlist = VHDL; + +[OSM BYPASS] + +[FITTER REPORT FORMAT] +Fitter_Options = Yes; +Pinout_Diagram = No; +Pinout_Listing = Yes; +Detailed_Block_Segment_Summary = Yes; +Input_Signal_List = Yes; +Output_Signal_List = Yes; +Bidir_Signal_List = Yes; +Node_Signal_List = Yes; +Signal_Fanout_List = Yes; +Block_Segment_Fanin_List = Yes; +Postfit_Eqn = Yes; +Prefit_Eqn = Yes; +Page_Break = Yes; + +[POWER] +Powerlevel = Low,High; +Default = High; +Low = H,G,F,E,D,C,B,A; +Type = GLB; + +[SOURCE CONSTRAINT OPTION] + +[TIMING ANALYZER] +Last_source=; +Last_source_type=Fmax; + diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc new file mode 100644 index 0000000..44572f7 --- /dev/null +++ b/Logic/68030_tk.plc @@ -0,0 +1,166 @@ +|--------------------------------------------| +|- ispLEVER Fitter Report File -| +|- Version 1.7.00.05.28.13 -| +|- (c)Copyright, Lattice Semiconductor 2002 -| +|--------------------------------------------| + + +; Source file 68030_tk.tt4 +; FITTER-generated Placements. +; DEVICE mach447a +; DATE Fri Oct 10 22:40:09 2014 + + +Pin 16 A_27_ +Pin 17 A_26_ +Pin 79 SIZE_1_ Comb ; S6=1 S9=1 Pair 271 +Pin 18 A_25_ +Pin 19 A_24_ +Pin 4 A_31_ +Pin 85 A_23_ +Pin 84 A_22_ +Pin 94 A_21_ +Pin 93 A_20_ +Pin 68 IPL_2_ +Pin 97 A_19_ +Pin 95 A_18_ +Pin 58 FC_1_ +Pin 59 A_17_ +Pin 82 AS_030 Comb ; S6=1 S9=1 Pair 281 +Pin 96 A_16_ +Pin 42 AS_000 Comb ; S6=1 S9=1 Pair 203 +Pin 56 IPL_1_ +Pin 32 UDS_000 Comb ; S6=1 S9=1 Pair 185 +Pin 67 IPL_0_ +Pin 31 LDS_000 Comb ; S6=1 S9=1 Pair 191 +Pin 57 FC_0_ +Pin 60 A1 +Pin 14 nEXP_SPACE +Pin 41 BERR Comb ; S6=1 S9=1 Pair 197 +Pin 21 BG_030 +Pin 28 BGACK_000 +Pin 64 CLK_030 +Pin 11 CLK_000 +Pin 61 CLK_OSZI +Pin 65 CLK_DIV_OUT Comb ; S6=1 S9=1 Pair 247 +Pin 10 CLK_EXP Comb ; S6=1 S9=1 Pair 127 +Pin 78 FPU_CS Comb ; S6=1 S9=1 Pair 277 +Pin 91 FPU_SENSE +Pin 30 DTACK Comb ; S6=1 S9=1 Pair 173 +Pin 92 AVEC Comb ; S6=1 S9=1 Pair 107 +Pin 36 VPA +Pin 86 RST +Pin 48 AMIGA_BUS_DATA_DIR Comb ; S6=1 S9=1 Pair 199 +Pin 20 AMIGA_BUS_ENABLE_LOW Comb ; S6=1 S9=1 Pair 149 +Pin 34 AMIGA_BUS_ENABLE_HIGH Comb ; S6=1 S9=1 Pair 187 +Pin 47 CIIN Comb ; S6=1 S9=1 Pair 215 +Pin 70 SIZE_0_ Comb ; S6=1 S9=1 Pair 263 +Pin 5 A_30_ +Pin 6 A_29_ +Pin 15 A_28_ +Pin 9 IPL_030_2_ Reg ; S6=0 S9=1 Pair 131 +Pin 7 IPL_030_1_ Reg ; S6=0 S9=1 Pair 143 +Pin 80 RW_000 Reg ; S6=1 S9=1 Pair 269 +Pin 8 IPL_030_0_ Reg ; S6=0 S9=1 Pair 137 +Pin 98 DS_030 Reg ; S6=1 S9=1 Pair 101 +Pin 69 A0 Reg ; S6=1 S9=1 Pair 257 +Pin 29 BG_000 Reg ; S6=1 S9=1 Pair 175 +Pin 83 BGACK_030 Reg ; S6=1 S9=1 Pair 275 +Pin 81 DSACK1 Reg ; S6=1 S9=1 Pair 287 +Pin 66 E Reg ; S6=1 S9=1 Pair 251 +Pin 35 VMA Reg ; S6=1 S9=1 Pair 179 +Pin 3 RESET Reg ; S6=1 S9=1 Pair 125 +Pin 71 RW Reg ; S6=1 S9=1 Pair 245 +Pin 33 AMIGA_ADDR_ENABLE Reg ; S6=1 S9=1 Pair 181 +Node 271 RN_SIZE_1_ Comb ; S6=1 S9=1 +Node 281 RN_AS_030 Comb ; S6=1 S9=1 +Node 203 RN_AS_000 Comb ; S6=1 S9=1 +Node 185 RN_UDS_000 Comb ; S6=1 S9=1 +Node 191 RN_LDS_000 Comb ; S6=1 S9=1 +Node 197 RN_BERR Comb ; S6=1 S9=1 +Node 173 RN_DTACK Comb ; S6=1 S9=1 +Node 263 RN_SIZE_0_ Comb ; S6=1 S9=1 +Node 131 RN_IPL_030_2_ Reg ; S6=0 S9=1 +Node 143 RN_IPL_030_1_ Reg ; S6=0 S9=1 +Node 269 RN_RW_000 Reg ; S6=1 S9=1 +Node 137 RN_IPL_030_0_ Reg ; S6=0 S9=1 +Node 101 RN_DS_030 Reg ; S6=1 S9=1 +Node 257 RN_A0 Reg ; S6=1 S9=1 +Node 175 RN_BG_000 Reg ; S6=1 S9=1 +Node 275 RN_BGACK_030 Reg ; S6=1 S9=1 +Node 287 RN_DSACK1 Reg ; S6=1 S9=1 +Node 251 RN_E Reg ; S6=1 S9=1 +Node 179 RN_VMA Reg ; S6=1 S9=1 +Node 125 RN_RESET Reg ; S6=1 S9=1 +Node 245 RN_RW Reg ; S6=1 S9=1 +Node 181 RN_AMIGA_ADDR_ENABLE Reg ; S6=1 S9=1 +Node 182 cpu_est_0_ Reg ; S6=1 S9=1 +Node 193 cpu_est_1_ Reg ; S6=1 S9=1 +Node 163 inst_AS_000_INT Reg ; S6=0 S9=1 +Node 121 inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg ; S6=1 S9=1 +Node 115 inst_AMIGA_BUS_ENABLE_DMA_LOW Reg ; S6=1 S9=1 +Node 283 inst_AS_030_D0 Reg ; S6=1 S9=1 +Node 133 inst_nEXP_SPACE_D0 Reg ; S6=0 S9=1 +Node 284 inst_DS_030_D0 Reg ; S6=1 S9=1 +Node 289 inst_AS_030_000_SYNC Reg ; S6=1 S9=1 +Node 278 inst_BGACK_030_INT_D Reg ; S6=1 S9=1 +Node 253 inst_AS_000_DMA Reg ; S6=1 S9=1 +Node 248 SIZE_DMA_0_ Reg ; S6=1 S9=1 +Node 259 SIZE_DMA_1_ Reg ; S6=1 S9=1 +Node 236 inst_VPA_D Reg ; S6=0 S9=1 +Node 119 inst_UDS_000_INT Reg ; S6=1 S9=1 +Node 113 inst_LDS_000_INT Reg ; S6=1 S9=1 +Node 184 inst_DTACK_D0 Reg ; S6=1 S9=1 +Node 146 RESET_DLY_7_ Reg ; S6=1 S9=1 +Node 238 inst_CLK_OUT_PRE_50 Reg ; S6=1 S9=1 +Node 205 inst_CLK_000_D1 Reg ; S6=1 S9=1 +Node 194 inst_CLK_000_D0 Reg ; S6=1 S9=1 +Node 169 sm_amiga_ns_0_3_0__n Comb ; S6=1 S9=1 +Node 221 SM_AMIGA_7_ Reg ; S6=0 S9=1 +Node 232 inst_CLK_OUT_PRE Reg ; S6=1 S9=1 +Node 155 inst_CLK_000_PE Reg ; S6=1 S9=1 +Node 250 CLK_000_P_SYNC_9_ Reg ; S6=1 S9=1 +Node 209 inst_CLK_000_NE Reg ; S6=1 S9=1 +Node 116 CLK_000_N_SYNC_11_ Reg ; S6=1 S9=1 +Node 176 cpu_est_2_ Reg ; S6=1 S9=1 +Node 188 inst_CLK_000_NE_D0 Reg ; S6=1 S9=1 +Node 167 SM_AMIGA_6_ Reg ; S6=1 S9=1 +Node 157 SM_AMIGA_4_ Reg ; S6=1 S9=1 +Node 227 SM_AMIGA_0_ Reg ; S6=1 S9=1 +Node 109 inst_CLK_030_H Reg ; S6=0 S9=1 +Node 206 CLK_000_P_SYNC_0_ Reg ; S6=1 S9=1 +Node 140 CLK_000_P_SYNC_1_ Reg ; S6=1 S9=1 +Node 110 CLK_000_P_SYNC_2_ Reg ; S6=1 S9=1 +Node 266 CLK_000_P_SYNC_3_ Reg ; S6=1 S9=1 +Node 134 CLK_000_P_SYNC_4_ Reg ; S6=1 S9=1 +Node 170 CLK_000_P_SYNC_5_ Reg ; S6=1 S9=1 +Node 164 CLK_000_P_SYNC_6_ Reg ; S6=1 S9=1 +Node 158 CLK_000_P_SYNC_7_ Reg ; S6=1 S9=1 +Node 226 CLK_000_P_SYNC_8_ Reg ; S6=1 S9=1 +Node 200 CLK_000_N_SYNC_0_ Reg ; S6=1 S9=1 +Node 260 CLK_000_N_SYNC_1_ Reg ; S6=1 S9=1 +Node 128 CLK_000_N_SYNC_2_ Reg ; S6=1 S9=1 +Node 254 CLK_000_N_SYNC_3_ Reg ; S6=1 S9=1 +Node 178 CLK_000_N_SYNC_4_ Reg ; S6=1 S9=1 +Node 145 CLK_000_N_SYNC_5_ Reg ; S6=1 S9=1 +Node 104 CLK_000_N_SYNC_6_ Reg ; S6=1 S9=1 +Node 242 CLK_000_N_SYNC_7_ Reg ; S6=1 S9=1 +Node 103 CLK_000_N_SYNC_8_ Reg ; S6=1 S9=1 +Node 217 CLK_000_N_SYNC_9_ Reg ; S6=1 S9=1 +Node 272 CLK_000_N_SYNC_10_ Reg ; S6=1 S9=1 +Node 241 RESET_DLY_0_ Reg ; S6=1 S9=1 +Node 235 RESET_DLY_1_ Reg ; S6=1 S9=1 +Node 229 RESET_DLY_2_ Reg ; S6=1 S9=1 +Node 223 RESET_DLY_3_ Reg ; S6=1 S9=1 +Node 239 RESET_DLY_4_ Reg ; S6=1 S9=1 +Node 265 RESET_DLY_5_ Reg ; S6=0 S9=1 +Node 139 RESET_DLY_6_ Reg ; S6=1 S9=1 +Node 151 inst_DS_000_ENABLE Reg ; S6=1 S9=1 +Node 161 SM_AMIGA_1_ Reg ; S6=1 S9=1 +Node 152 SM_AMIGA_5_ Reg ; S6=1 S9=1 +Node 224 SM_AMIGA_3_ Reg ; S6=1 S9=1 +Node 230 SM_AMIGA_2_ Reg ; S6=1 S9=1 +Node 233 CLK_OUT_PRE_Dreg Reg ; S6=1 S9=1 +Node 211 CIIN_0 Comb ; S6=1 S9=1 +; Unused Pins & Nodes +; -> None Found. diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd new file mode 100644 index 0000000..677f152 --- /dev/null +++ b/Logic/68030_tk.prd @@ -0,0 +1,1981 @@ +|--------------------------------------------| +|- ispLEVER Fitter Report File -| +|- Version 1.7.00.05.28.13 -| +|- (c)Copyright, Lattice Semiconductor 2002 -| +|--------------------------------------------| + + +Start: Fri Oct 10 22:40:08 2014 +End : Fri Oct 10 22:40:09 2014 $$$ Elapsed time: 00:00:01 +=========================================================================== +Part [C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4] + +* Place/Route options (keycode = 540674) + = Spread Placement: ON + = No. Routing Attempts/Placement 2 + +* Placement Completion + + +- Block +------- IO Pins Available + | +- Macrocells Available | +-- IO Pins Used + | | +- Signals to Place | | +----- Logic Array Inputs + | | | +- Placed | | | +- Array Inputs Used +_|____|____|____|_______________|____|_____________|___|________________ + 0 | 16 | 11 | 11 => 100% | 8 | 8 => 100% | 33 | 23 => 69% + 1 | 16 | 12 | 12 => 100% | 8 | 8 => 100% | 33 | 28 => 84% + 2 | 16 | 12 | 12 => 100% | 8 | 7 => 87% | 33 | 26 => 78% + 3 | 16 | 14 | 14 => 100% | 8 | 8 => 100% | 33 | 31 => 93% + 4 | 16 | 10 | 10 => 100% | 8 | 4 => 50% | 33 | 32 => 96% + 5 | 16 | 15 | 15 => 100% | 8 | 5 => 62% | 33 | 28 => 84% + 6 | 16 | 13 | 13 => 100% | 8 | 7 => 87% | 33 | 28 => 84% + 7 | 16 | 11 | 11 => 100% | 8 | 8 => 100% | 33 | 31 => 93% +---|----|----|------------|-------|------------|-----|------------------ + | Avg number of array inputs in used blocks : 28.38 => 85% + +* Input/Clock Signal count: 31 -> placed: 31 = 100% + + Resources Available Used +----------------------------------------------------------------- + Input Pins : 2 2 => 100% + I/O Pins : 64 55 => 85% + Clock Only Pins : 0 0 => 0% + Clock/Input Pins : 4 4 => 100% + Logic Blocks : 8 8 => 100% + Macrocells : 128 98 => 76% + PT Clusters : 128 50 => 39% + - Single PT Clusters : 128 53 => 41% + Input Registers : 0 + +* Routing Completion: 100% +* Attempts: Place [ 142] Route [ 0] +=========================================================================== + Signal Fanout Table +=========================================================================== + +- Signal Number + | +- Block Location ('+' for dedicated inputs) + | | +- Sig Type + | | | +- Signal-to-Pin Assignment + | | | | Fanout to Logic Blocks Signal Name +___|__|__|____|____________________________________________________________ + 1| 6| IO| 69|=> 0...|....| A0 + 2| 5|INP| 60|=> 0...|....| A1 + 3| 3| IO| 33|=> ....|....| AMIGA_ADDR_ENABLE + |=> Paired w/: RN_AMIGA_ADDR_ENABLE + 4| 4|OUT| 48|=> ....|....| AMIGA_BUS_DATA_DIR + 5| 3|OUT| 34|=> ....|....| AMIGA_BUS_ENABLE_HIGH + 6| 2|OUT| 20|=> ....|....| AMIGA_BUS_ENABLE_LOW + 7| 4| IO| 42|=> 0...|4.6.| AS_000 + 8| 7| IO| 82|=> ....|4..7| AS_030 + 9| 0|OUT| 92|=> ....|....| AVEC + 10| 0|INP| 96|=> ....|4..7| A_16_ + 11| 5|INP| 59|=> ....|4..7| A_17_ + 12| 0|INP| 95|=> ....|4..7| A_18_ + 13| 0|INP| 97|=> ....|4..7| A_19_ + 14| 0|INP| 93|=> ....|4...| A_20_ + 15| 0|INP| 94|=> ....|4...| A_21_ + 16| 7|INP| 84|=> ....|4...| A_22_ + 17| 7|INP| 85|=> ....|4...| A_23_ + 18| 2|INP| 19|=> ....|4...| A_24_ + 19| 2|INP| 18|=> ....|4...| A_25_ + 20| 2|INP| 17|=> ....|4...| A_26_ + 21| 2|INP| 16|=> ....|4...| A_27_ + 22| 2|INP| 15|=> ....|4...| A_28_ + 23| 1|INP| 6|=> ....|4...| A_29_ + 24| 1|INP| 5|=> ....|4...| A_30_ + 25| 1|INP| 4|=> ....|4...| A_31_ + 26| 4| IO| 41|=> ..2.|.5.7| BERR + 27| 3|INP| 28|=> ....|4..7| BGACK_000 + 28| 7| IO| 83|=> ....|....| BGACK_030 + |=> Paired w/: RN_BGACK_030 + 29| 3| IO| 29|=> ....|....| BG_000 + |=> Paired w/: RN_BG_000 + 30| 2|INP| 21|=> ...3|....| BG_030 + 31| 4|OUT| 47|=> ....|....| CIIN + 32| 4|NOD| . |=> ....|4...| CIIN_0 + 33| +|INP| 11|=> ...3|....| CLK_000 + 34| 4|NOD| . |=> ....|..6.| CLK_000_N_SYNC_0_ + 35| 7|NOD| . |=> 0...|....| CLK_000_N_SYNC_10_ + 36| 0|NOD| . |=> ....|4...| CLK_000_N_SYNC_11_ + 37| 6|NOD| . |=> .1..|....| CLK_000_N_SYNC_1_ + 38| 1|NOD| . |=> ....|..6.| CLK_000_N_SYNC_2_ + 39| 6|NOD| . |=> ...3|....| CLK_000_N_SYNC_3_ + 40| 3|NOD| . |=> .1..|....| CLK_000_N_SYNC_4_ + 41| 1|NOD| . |=> 0...|....| CLK_000_N_SYNC_5_ + 42| 0|NOD| . |=> ....|.5..| CLK_000_N_SYNC_6_ + 43| 5|NOD| . |=> 0...|....| CLK_000_N_SYNC_7_ + 44| 0|NOD| . |=> ....|4..7| CLK_000_N_SYNC_8_ + 45| 4|NOD| . |=> ....|...7| CLK_000_N_SYNC_9_ + 46| 4|NOD| . |=> .1..|....| CLK_000_P_SYNC_0_ + 47| 1|NOD| . |=> 0...|....| CLK_000_P_SYNC_1_ + 48| 0|NOD| . |=> ....|..6.| CLK_000_P_SYNC_2_ + 49| 6|NOD| . |=> .1..|....| CLK_000_P_SYNC_3_ + 50| 1|NOD| . |=> ..2.|....| CLK_000_P_SYNC_4_ + 51| 2|NOD| . |=> ..2.|....| CLK_000_P_SYNC_5_ + 52| 2|NOD| . |=> ..2.|....| CLK_000_P_SYNC_6_ + 53| 2|NOD| . |=> ....|.5..| CLK_000_P_SYNC_7_ + 54| 5|NOD| . |=> ....|..6.| CLK_000_P_SYNC_8_ + 55| 6|NOD| . |=> ..2.|....| CLK_000_P_SYNC_9_ + 56| +|INP| 64|=> 0...|..67| CLK_030 + 57| 6|OUT| 65|=> ....|....| CLK_DIV_OUT + 58| 1|OUT| 10|=> ....|....| CLK_EXP + 59| +|Cin| 61|=> ....|....| CLK_OSZI + 60| 5|NOD| . |=> .1..|..67| CLK_OUT_PRE_Dreg + 61| 7| IO| 81|=> ...3|....| DSACK1 + |=> Paired w/: RN_DSACK1 + 62| 0| IO| 98|=> ...3|...7| DS_030 + |=> Paired w/: RN_DS_030 + 63| 3| IO| 30|=> ...3|....| DTACK + 64| 6| IO| 66|=> ....|....| E + |=> Paired w/: RN_E + 65| 5|INP| 57|=> ....|4..7| FC_0_ + 66| 5|INP| 58|=> ....|4..7| FC_1_ + 67| 7|OUT| 78|=> ....|....| FPU_CS + 68| 0|INP| 91|=> ....|4..7| FPU_SENSE + 69| 1| IO| 8|=> ....|....| IPL_030_0_ + |=> Paired w/: RN_IPL_030_0_ + 70| 1| IO| 7|=> ....|....| IPL_030_1_ + |=> Paired w/: RN_IPL_030_1_ + 71| 1| IO| 9|=> ....|....| IPL_030_2_ + |=> Paired w/: RN_IPL_030_2_ + 72| 6|INP| 67|=> .1..|....| IPL_0_ + 73| 5|INP| 56|=> .1..|....| IPL_1_ + 74| 6|INP| 68|=> .1..|....| IPL_2_ + 75| 3| IO| 31|=> 0...|..6.| LDS_000 + 76| 1| IO| 3|=> ....|....| RESET + |=> Paired w/: RN_RESET + 77| 5|NOD| . |=> .1..|.56.| RESET_DLY_0_ + 78| 5|NOD| . |=> .1..|.56.| RESET_DLY_1_ + 79| 5|NOD| . |=> .1..|.56.| RESET_DLY_2_ + 80| 5|NOD| . |=> .1..|.56.| RESET_DLY_3_ + 81| 5|NOD| . |=> .1..|.56.| RESET_DLY_4_ + 82| 6|NOD| . |=> .1..|..6.| RESET_DLY_5_ + 83| 1|NOD| . |=> .1..|....| RESET_DLY_6_ + 84| 1|NOD| . |=> .1..|....| RESET_DLY_7_ + 85| 3|NOD| . |=> ...3|....| RN_AMIGA_ADDR_ENABLE + |=> Paired w/: AMIGA_ADDR_ENABLE + 86| 7|NOD| . |=> 0.23|4.67| RN_BGACK_030 + |=> Paired w/: BGACK_030 + 87| 3|NOD| . |=> ...3|....| RN_BG_000 + |=> Paired w/: BG_000 + 88| 7|NOD| . |=> ....|...7| RN_DSACK1 + |=> Paired w/: DSACK1 + 89| 0|NOD| . |=> 0...|....| RN_DS_030 + |=> Paired w/: DS_030 + 90| 6|NOD| . |=> .1.3|.56.| RN_E + |=> Paired w/: E + 91| 1|NOD| . |=> .1..|....| RN_IPL_030_0_ + |=> Paired w/: IPL_030_0_ + 92| 1|NOD| . |=> .1..|....| RN_IPL_030_1_ + |=> Paired w/: IPL_030_1_ + 93| 1|NOD| . |=> .1..|....| RN_IPL_030_2_ + |=> Paired w/: IPL_030_2_ + 94| 1|NOD| . |=> .1..|....| RN_RESET + |=> Paired w/: RESET + 95| 6|NOD| . |=> ....|..6.| RN_RW + |=> Paired w/: RW + 96| 7|NOD| . |=> ....|...7| RN_RW_000 + |=> Paired w/: RW_000 + 97| 3|NOD| . |=> ...3|.5..| RN_VMA + |=> Paired w/: VMA + 98| +|INP| 86|=> 0123|.567| RST + 99| 6| IO| 71|=> ..2.|...7| RW + |=> Paired w/: RN_RW + 100| 7| IO| 80|=> 0...|4.6.| RW_000 + |=> Paired w/: RN_RW_000 + 101| 6| IO| 70|=> 0...|....| SIZE_0_ + 102| 7| IO| 79|=> 0...|....| SIZE_1_ + 103| 6|NOD| . |=> ....|..67| SIZE_DMA_0_ + 104| 6|NOD| . |=> ....|..67| SIZE_DMA_1_ + 105| 5|NOD| . |=> ..2.|.5.7| SM_AMIGA_0_ + 106| 2|NOD| . |=> ..2.|.5.7| SM_AMIGA_1_ + 107| 5|NOD| . |=> ..2.|.5..| SM_AMIGA_2_ + 108| 5|NOD| . |=> ..2.|.5..| SM_AMIGA_3_ + 109| 2|NOD| . |=> ..2.|.5..| SM_AMIGA_4_ + 110| 2|NOD| . |=> ..2.|....| SM_AMIGA_5_ + 111| 2|NOD| . |=> 0.2.|...7| SM_AMIGA_6_ + 112| 5|NOD| . |=> ..23|...7| SM_AMIGA_7_ + 113| 3| IO| 32|=> 0...|..6.| UDS_000 + 114| 3| IO| 35|=> ....|....| VMA + |=> Paired w/: RN_VMA + 115| +|INP| 36|=> ....|.5..| VPA + 116| 3|NOD| . |=> .1.3|.56.| cpu_est_0_ + 117| 3|NOD| . |=> .1.3|.56.| cpu_est_1_ + 118| 3|NOD| . |=> .1.3|.56.| cpu_est_2_ + 119| 0|NOD| . |=> ...3|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH + 120| 0|NOD| . |=> ..2.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW + 121| 6|NOD| . |=> 0..3|..67| inst_AS_000_DMA + 122| 2|NOD| . |=> ..2.|4...| inst_AS_000_INT + 123| 7|NOD| . |=> ..23|...7| inst_AS_030_000_SYNC + 124| 7|NOD| . |=> ..23|4..7| inst_AS_030_D0 + 125| 7|NOD| . |=> ...3|....| inst_BGACK_030_INT_D + 126| 3|NOD| . |=> ..23|4...| inst_CLK_000_D0 + 127| 4|NOD| . |=> ..23|4...| inst_CLK_000_D1 + 128| 4|NOD| . |=> .123|.5..| inst_CLK_000_NE + 129| 3|NOD| . |=> .1.3|.56.| inst_CLK_000_NE_D0 + 130| 2|NOD| . |=> ..23|.5.7| inst_CLK_000_PE + 131| 0|NOD| . |=> 0...|....| inst_CLK_030_H + 132| 5|NOD| . |=> ....|.5..| inst_CLK_OUT_PRE + 133| 5|NOD| . |=> ....|.5..| inst_CLK_OUT_PRE_50 + 134| 2|NOD| . |=> ..23|....| inst_DS_000_ENABLE + 135| 7|NOD| . |=> 0...|....| inst_DS_030_D0 + 136| 3|NOD| . |=> ....|.5..| inst_DTACK_D0 + 137| 0|NOD| . |=> 0..3|....| inst_LDS_000_INT + 138| 0|NOD| . |=> 0..3|....| inst_UDS_000_INT + 139| 5|NOD| . |=> ...3|.5..| inst_VPA_D + 140| 1|NOD| . |=> 0.23|4.67| inst_nEXP_SPACE_D0 + 141| +|INP| 14|=> .1..|....| nEXP_SPACE + 142| 2|NOD| . |=> ....|.5..| sm_amiga_ns_0_3_0__n +--------------------------------------------------------------------------- +=========================================================================== + < C:/Program Files (x86)/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments > +=========================================================================== + +- Device Pin No + | Pin Type +- Signal Fixed (*) + | | | Signal Name +____|_____|_________|______________________________________________________ + 1 | GND | | | (pwr/test) + 2 | JTAG | | | (pwr/test) + 3 | I_O | 1_07|*| RESET + 4 | I_O | 1_06|*| A_31_ + 5 | I_O | 1_05|*| A_30_ + 6 | I_O | 1_04|*| A_29_ + 7 | I_O | 1_03|*| IPL_030_1_ + 8 | I_O | 1_02|*| IPL_030_0_ + 9 | I_O | 1_01|*| IPL_030_2_ + 10 | I_O | 1_00|*| CLK_EXP + 11 | CkIn | |*| CLK_000 + 12 | Vcc | | | (pwr/test) + 13 | GND | | | (pwr/test) + 14 | CkIn | |*| nEXP_SPACE + 15 | I_O | 2_00|*| A_28_ + 16 | I_O | 2_01|*| A_27_ + 17 | I_O | 2_02|*| A_26_ + 18 | I_O | 2_03|*| A_25_ + 19 | I_O | 2_04|*| A_24_ + 20 | I_O | 2_05|*| AMIGA_BUS_ENABLE_LOW + 21 | I_O | 2_06|*| BG_030 + 22 | I_O | 2_07| | - + 23 | JTAG | | | (pwr/test) + 24 | JTAG | | | (pwr/test) + 25 | GND | | | (pwr/test) + 26 | GND | | | (pwr/test) + 27 | GND | | | (pwr/test) + 28 | I_O | 3_07|*| BGACK_000 + 29 | I_O | 3_06|*| BG_000 + 30 | I_O | 3_05|*| DTACK + 31 | I_O | 3_04|*| LDS_000 + 32 | I_O | 3_03|*| UDS_000 + 33 | I_O | 3_02|*| AMIGA_ADDR_ENABLE + 34 | I_O | 3_01|*| AMIGA_BUS_ENABLE_HIGH + 35 | I_O | 3_00|*| VMA + 36 | Inp | |*| VPA + 37 | Vcc | | | (pwr/test) + 38 | GND | | | (pwr/test) + 39 | GND | | | (pwr/test) + 40 | Vcc | | | (pwr/test) + 41 | I_O | 4_00|*| BERR + 42 | I_O | 4_01|*| AS_000 + 43 | I_O | 4_02| | - + 44 | I_O | 4_03| | - + 45 | I_O | 4_04| | - + 46 | I_O | 4_05| | - + 47 | I_O | 4_06|*| CIIN + 48 | I_O | 4_07|*| AMIGA_BUS_DATA_DIR + 49 | GND | | | (pwr/test) + 50 | GND | | | (pwr/test) + 51 | GND | | | (pwr/test) + 52 | JTAG | | | (pwr/test) + 53 | I_O | 5_07| | - + 54 | I_O | 5_06| | - + 55 | I_O | 5_05| | - + 56 | I_O | 5_04|*| IPL_1_ + 57 | I_O | 5_03|*| FC_0_ + 58 | I_O | 5_02|*| FC_1_ + 59 | I_O | 5_01|*| A_17_ + 60 | I_O | 5_00|*| A1 + 61 | CkIn | |*| CLK_OSZI + 62 | Vcc | | | (pwr/test) + 63 | GND | | | (pwr/test) + 64 | CkIn | |*| CLK_030 + 65 | I_O | 6_00|*| CLK_DIV_OUT + 66 | I_O | 6_01|*| E + 67 | I_O | 6_02|*| IPL_0_ + 68 | I_O | 6_03|*| IPL_2_ + 69 | I_O | 6_04|*| A0 + 70 | I_O | 6_05|*| SIZE_0_ + 71 | I_O | 6_06|*| RW + 72 | I_O | 6_07| | - + 73 | JTAG | | | (pwr/test) + 74 | JTAG | | | (pwr/test) + 75 | GND | | | (pwr/test) + 76 | GND | | | (pwr/test) + 77 | GND | | | (pwr/test) + 78 | I_O | 7_07|*| FPU_CS + 79 | I_O | 7_06|*| SIZE_1_ + 80 | I_O | 7_05|*| RW_000 + 81 | I_O | 7_04|*| DSACK1 + 82 | I_O | 7_03|*| AS_030 + 83 | I_O | 7_02|*| BGACK_030 + 84 | I_O | 7_01|*| A_22_ + 85 | I_O | 7_00|*| A_23_ + 86 | Inp | |*| RST + 87 | Vcc | | | (pwr/test) + 88 | GND | | | (pwr/test) + 89 | GND | | | (pwr/test) + 90 | Vcc | | | (pwr/test) + 91 | I_O | 0_00|*| FPU_SENSE + 92 | I_O | 0_01|*| AVEC + 93 | I_O | 0_02|*| A_20_ + 94 | I_O | 0_03|*| A_21_ + 95 | I_O | 0_04|*| A_18_ + 96 | I_O | 0_05|*| A_16_ + 97 | I_O | 0_06|*| A_19_ + 98 | I_O | 0_07|*| DS_030 + 99 | GND | | | (pwr/test) + 100 | GND | | | (pwr/test) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0| DS_030| IO| | S | 7 | 4 to [ 0]| 1 XOR to [ 0] as logic PT + 1|CLK_000_N_SYNC_8_|NOD| | S | 1 | 4 to [ 0]| 1 XOR to [ 1] for 1 PT sig + 2|CLK_000_N_SYNC_6_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 free | 1 XOR free + 4| AVEC|OUT| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 5|inst_CLK_030_H|NOD| | S | 4 | 4 to [ 5]| 1 XOR free + 6|CLK_000_P_SYNC_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7| | ? | | S | | 4 free | 1 XOR free + 8|inst_LDS_000_INT|NOD| | S | 3 | 4 to [ 8]| 1 XOR free + 9|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 | 4 to [ 9]| 1 XOR free +10|CLK_000_N_SYNC_11_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11| | ? | | S | | 4 free | 1 XOR free +12|inst_UDS_000_INT|NOD| | S | 3 | 4 to [12]| 1 XOR free +13|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 | 4 to [13]| 1 XOR free +14| | ? | | S | | 4 free | 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0| DS_030| IO| | S | 7 |=> can support up to [ 13] logic PT(s) + 1|CLK_000_N_SYNC_8_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 2|CLK_000_N_SYNC_6_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 13] logic PT(s) + 4| AVEC|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) + 5|inst_CLK_030_H|NOD| | S | 4 |=> can support up to [ 18] logic PT(s) + 6|CLK_000_P_SYNC_2_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 9] logic PT(s) + 8|inst_LDS_000_INT|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) + 9|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) +10|CLK_000_N_SYNC_11_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 9] logic PT(s) +12|inst_UDS_000_INT|NOD| | S | 3 |=> can support up to [ 15] logic PT(s) +13|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 0] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0| DS_030| IO| | => | 5 6 ( 7) 0 | 96 97 ( 98) 91 + 1|CLK_000_N_SYNC_8_|NOD| | => | 5 6 7 0 | 96 97 98 91 + 2|CLK_000_N_SYNC_6_|NOD| | => | 6 7 0 1 | 97 98 91 92 + 3| | | | => | 6 7 0 1 | 97 98 91 92 + 4| AVEC|OUT| | => | 7 0 ( 1) 2 | 98 91 ( 92) 93 + 5|inst_CLK_030_H|NOD| | => | 7 0 1 2 | 98 91 92 93 + 6|CLK_000_P_SYNC_2_|NOD| | => | 0 1 2 3 | 91 92 93 94 + 7| | | | => | 0 1 2 3 | 91 92 93 94 + 8|inst_LDS_000_INT|NOD| | => | 1 2 3 4 | 92 93 94 95 + 9|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => | 1 2 3 4 | 92 93 94 95 +10|CLK_000_N_SYNC_11_|NOD| | => | 2 3 4 5 | 93 94 95 96 +11| | | | => | 2 3 4 5 | 93 94 95 96 +12|inst_UDS_000_INT|NOD| | => | 3 4 5 6 | 94 95 96 97 +13|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => | 3 4 5 6 | 94 95 96 97 +14| | | | => | 4 5 6 7 | 95 96 97 98 +15| | | | => | 4 5 6 7 | 95 96 97 98 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| FPU_SENSE|INP|*| 91| => | 0 1 2 3 4 5 6 7 + 1| AVEC|OUT|*| 92| => | 2 3 ( 4) 5 6 7 8 9 + 2| A_20_|INP|*| 93| => | 4 5 6 7 8 9 10 11 + 3| A_21_|INP|*| 94| => | 6 7 8 9 10 11 12 13 + 4| A_18_|INP|*| 95| => | 8 9 10 11 12 13 14 15 + 5| A_16_|INP|*| 96| => | 10 11 12 13 14 15 0 1 + 6| A_19_|INP|*| 97| => | 12 13 14 15 0 1 2 3 + 7| DS_030| IO|*| 98| => | 14 15 ( 0) 1 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| FPU_SENSE|INP|*| 91| => | Input macrocell [ -] + 1| AVEC|OUT|*| 92| => | Input macrocell [ -] + 2| A_20_|INP|*| 93| => | Input macrocell [ -] + 3| A_21_|INP|*| 94| => | Input macrocell [ -] + 4| A_18_|INP|*| 95| => | Input macrocell [ -] + 5| A_16_|INP|*| 96| => | Input macrocell [ -] + 6| A_19_|INP|*| 97| => | Input macrocell [ -] + 7| DS_030| IO|*| 98| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_DS_030] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 91|INP FPU_SENSE|*|*] + [RegIn 0 |102| -| | ] + [MCell 0 |101|NOD RN_DS_030| |*] paired w/[ DS_030] + [MCell 1 |103|NOD CLK_000_N_SYNC_8_| |*] + + 1 [IOpin 1 | 92|OUT AVEC|*| ] + [RegIn 1 |105| -| | ] + [MCell 2 |104|NOD CLK_000_N_SYNC_6_| |*] + [MCell 3 |106| -| | ] + + 2 [IOpin 2 | 93|INP A_20_|*|*] + [RegIn 2 |108| -| | ] + [MCell 4 |107|OUT AVEC| | ] + [MCell 5 |109|NOD inst_CLK_030_H| |*] + + 3 [IOpin 3 | 94|INP A_21_|*|*] + [RegIn 3 |111| -| | ] + [MCell 6 |110|NOD CLK_000_P_SYNC_2_| |*] + [MCell 7 |112| -| | ] + + 4 [IOpin 4 | 95|INP A_18_|*|*] + [RegIn 4 |114| -| | ] + [MCell 8 |113|NOD inst_LDS_000_INT| |*] + [MCell 9 |115|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*] + + 5 [IOpin 5 | 96|INP A_16_|*|*] + [RegIn 5 |117| -| | ] + [MCell 10 |116|NOD CLK_000_N_SYNC_11_| |*] + [MCell 11 |118| -| | ] + + 6 [IOpin 6 | 97|INP A_19_|*|*] + [RegIn 6 |120| -| | ] + [MCell 12 |119|NOD inst_UDS_000_INT| |*] + [MCell 13 |121|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*] + + 7 [IOpin 7 | 98| IO DS_030|*|*] paired w/[ RN_DS_030] + [RegIn 7 |123| -| | ] + [MCell 14 |122| -| | ] + [MCell 15 |124| -| | ] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 0] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| IOPin 6 4 ( 69)| A0 +Mux01| ... | ... +Mux02| Mcel 0 5 ( 109)| inst_CLK_030_H +Mux03| IOPin 5 0 ( 60)| A1 +Mux04| Mcel 2 12 ( 167)| SM_AMIGA_6_ +Mux05| ... | ... +Mux06| IOPin 7 5 ( 80)| RW_000 +Mux07| ... | ... +Mux08| IOPin 3 3 ( 32)| UDS_000 +Mux09| Mcel 0 12 ( 119)| inst_UDS_000_INT +Mux10| Mcel 1 13 ( 145)| CLK_000_N_SYNC_5_ +Mux11| ... | ... +Mux12| Mcel 1 10 ( 140)| CLK_000_P_SYNC_1_ +Mux13| ... | ... +Mux14| Mcel 7 2 ( 272)| CLK_000_N_SYNC_10_ +Mux15| Mcel 0 0 ( 101)| RN_DS_030 +Mux16| IOPin 4 1 ( 42)| AS_000 +Mux17| IOPin 6 5 ( 70)| SIZE_0_ +Mux18| Mcel 7 10 ( 284)| inst_DS_030_D0 +Mux19| ... | ... +Mux20| IOPin 7 6 ( 79)| SIZE_1_ +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 6 5 ( 253)| inst_AS_000_DMA +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux24| Mcel 5 14 ( 242)| CLK_000_N_SYNC_7_ +Mux25| ... | ... +Mux26| ... | ... +Mux27| IOPin 3 4 ( 31)| LDS_000 +Mux28| Input Pin ( 64)| CLK_030 +Mux29| ... | ... +Mux30| Mcel 0 8 ( 113)| inst_LDS_000_INT +Mux31| Mcel 1 5 ( 133)| inst_nEXP_SPACE_D0 +Mux32| ... | ... +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 1] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0| RESET| IO| | S | 2 | 4 to [ 0]| 1 XOR free + 1| CLK_EXP|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2|CLK_000_N_SYNC_2_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 free | 1 XOR free + 4| IPL_030_2_| IO| | S | 2 | 4 to [ 4]| 1 XOR free + 5|inst_nEXP_SPACE_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 6|CLK_000_P_SYNC_4_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7| | ? | | S | | 4 free | 1 XOR free + 8| IPL_030_0_| IO| | S | 2 | 4 to [ 8]| 1 XOR free + 9| RESET_DLY_6_|NOD| | S | 1 :+: 1| 4 to [ 9]| 1 XOR to [ 9] +10|CLK_000_P_SYNC_1_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11| | ? | | S | | 4 free | 1 XOR free +12| IPL_030_1_| IO| | S | 2 | 4 to [12]| 1 XOR free +13|CLK_000_N_SYNC_5_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +14| RESET_DLY_7_|NOD| | S | 1 :+: 1| 4 to [14]| 1 XOR to [14] +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 1] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0| RESET| IO| | S | 2 |=> can support up to [ 13] logic PT(s) + 1| CLK_EXP|OUT| | S | 1 |=> can support up to [ 14] logic PT(s) + 2|CLK_000_N_SYNC_2_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 13] logic PT(s) + 4| IPL_030_2_| IO| | S | 2 |=> can support up to [ 18] logic PT(s) + 5|inst_nEXP_SPACE_D0|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 6|CLK_000_P_SYNC_4_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 7| | ? | | S | |=> can support up to [ 9] logic PT(s) + 8| IPL_030_0_| IO| | S | 2 |=> can support up to [ 14] logic PT(s) + 9| RESET_DLY_6_|NOD| | S | 1 :+: 1|=> can support up to [ 13] logic PT(s) +10|CLK_000_P_SYNC_1_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +11| | ? | | S | |=> can support up to [ 13] logic PT(s) +12| IPL_030_1_| IO| | S | 2 |=> can support up to [ 14] logic PT(s) +13|CLK_000_N_SYNC_5_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +14| RESET_DLY_7_|NOD| | S | 1 :+: 1|=> can support up to [ 13] logic PT(s) +15| | ? | | S | |=> can support up to [ 5] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 1] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 1] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0| RESET| IO| | => | 5 6 ( 7) 0 | 5 4 ( 3) 10 + 1| CLK_EXP|OUT| | => | 5 6 7 ( 0)| 5 4 3 ( 10) + 2|CLK_000_N_SYNC_2_|NOD| | => | 6 7 0 1 | 4 3 10 9 + 3| | | | => | 6 7 0 1 | 4 3 10 9 + 4| IPL_030_2_| IO| | => | 7 0 ( 1) 2 | 3 10 ( 9) 8 + 5|inst_nEXP_SPACE_D0|NOD| | => | 7 0 1 2 | 3 10 9 8 + 6|CLK_000_P_SYNC_4_|NOD| | => | 0 1 2 3 | 10 9 8 7 + 7| | | | => | 0 1 2 3 | 10 9 8 7 + 8| IPL_030_0_| IO| | => | 1 ( 2) 3 4 | 9 ( 8) 7 6 + 9| RESET_DLY_6_|NOD| | => | 1 2 3 4 | 9 8 7 6 +10|CLK_000_P_SYNC_1_|NOD| | => | 2 3 4 5 | 8 7 6 5 +11| | | | => | 2 3 4 5 | 8 7 6 5 +12| IPL_030_1_| IO| | => |( 3) 4 5 6 |( 7) 6 5 4 +13|CLK_000_N_SYNC_5_|NOD| | => | 3 4 5 6 | 7 6 5 4 +14| RESET_DLY_7_|NOD| | => | 4 5 6 7 | 6 5 4 3 +15| | | | => | 4 5 6 7 | 6 5 4 3 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 1] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| CLK_EXP|OUT|*| 10| => | 0 ( 1) 2 3 4 5 6 7 + 1| IPL_030_2_| IO|*| 9| => | 2 3 ( 4) 5 6 7 8 9 + 2| IPL_030_0_| IO|*| 8| => | 4 5 6 7 ( 8) 9 10 11 + 3| IPL_030_1_| IO|*| 7| => | 6 7 8 9 10 11 (12) 13 + 4| A_29_|INP|*| 6| => | 8 9 10 11 12 13 14 15 + 5| A_30_|INP|*| 5| => | 10 11 12 13 14 15 0 1 + 6| A_31_|INP|*| 4| => | 12 13 14 15 0 1 2 3 + 7| RESET| IO|*| 3| => | 14 15 ( 0) 1 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 1] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| CLK_EXP|OUT|*| 10| => | Input macrocell [ -] + 1| IPL_030_2_| IO|*| 9| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_IPL_030_2_] + 2| IPL_030_0_| IO|*| 8| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_IPL_030_0_] + 3| IPL_030_1_| IO|*| 7| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_IPL_030_1_] + 4| A_29_|INP|*| 6| => | Input macrocell [ -] + 5| A_30_|INP|*| 5| => | Input macrocell [ -] + 6| A_31_|INP|*| 4| => | Input macrocell [ -] + 7| RESET| IO|*| 3| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_RESET] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 1] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 10|OUT CLK_EXP|*| ] + [RegIn 0 |126| -| | ] + [MCell 0 |125|NOD RN_RESET| |*] paired w/[ RESET] + [MCell 1 |127|OUT CLK_EXP| | ] + + 1 [IOpin 1 | 9| IO IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_] + [RegIn 1 |129| -| | ] + [MCell 2 |128|NOD CLK_000_N_SYNC_2_| |*] + [MCell 3 |130| -| | ] + + 2 [IOpin 2 | 8| IO IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_] + [RegIn 2 |132| -| | ] + [MCell 4 |131|NOD RN_IPL_030_2_| |*] paired w/[ IPL_030_2_] + [MCell 5 |133|NOD inst_nEXP_SPACE_D0| |*] + + 3 [IOpin 3 | 7| IO IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_] + [RegIn 3 |135| -| | ] + [MCell 6 |134|NOD CLK_000_P_SYNC_4_| |*] + [MCell 7 |136| -| | ] + + 4 [IOpin 4 | 6|INP A_29_|*|*] + [RegIn 4 |138| -| | ] + [MCell 8 |137|NOD RN_IPL_030_0_| |*] paired w/[ IPL_030_0_] + [MCell 9 |139|NOD RESET_DLY_6_| |*] + + 5 [IOpin 5 | 5|INP A_30_|*|*] + [RegIn 5 |141| -| | ] + [MCell 10 |140|NOD CLK_000_P_SYNC_1_| |*] + [MCell 11 |142| -| | ] + + 6 [IOpin 6 | 4|INP A_31_|*|*] + [RegIn 6 |144| -| | ] + [MCell 12 |143|NOD RN_IPL_030_1_| |*] paired w/[ IPL_030_1_] + [MCell 13 |145|NOD CLK_000_N_SYNC_5_| |*] + + 7 [IOpin 7 | 3| IO RESET|*| ] paired w/[ RN_RESET] + [RegIn 7 |147| -| | ] + [MCell 14 |146|NOD RESET_DLY_7_| |*] + [MCell 15 |148| -| | ] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 1] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| IOPin 6 2 ( 67)| IPL_0_ +Mux01| Mcel 5 12 ( 239)| RESET_DLY_4_ +Mux02| Mcel 3 10 ( 188)| inst_CLK_000_NE_D0 +Mux03| IOPin 5 4 ( 56)| IPL_1_ +Mux04| Mcel 3 6 ( 182)| cpu_est_0_ +Mux05| Mcel 6 10 ( 260)| CLK_000_N_SYNC_1_ +Mux06| Mcel 5 13 ( 241)| RESET_DLY_0_ +Mux07| ... | ... +Mux08| Mcel 4 8 ( 209)| inst_CLK_000_NE +Mux09| Mcel 6 13 ( 265)| RESET_DLY_5_ +Mux10| Mcel 6 14 ( 266)| CLK_000_P_SYNC_3_ +Mux11| Mcel 6 4 ( 251)| RN_E +Mux12| Mcel 1 12 ( 143)| RN_IPL_030_1_ +Mux13| Mcel 3 3 ( 178)| CLK_000_N_SYNC_4_ +Mux14| Mcel 5 5 ( 229)| RESET_DLY_2_ +Mux15| Input Pin ( 14)| nEXP_SPACE +Mux16| Mcel 1 9 ( 139)| RESET_DLY_6_ +Mux17| Mcel 1 8 ( 137)| RN_IPL_030_0_ +Mux18| Mcel 5 9 ( 235)| RESET_DLY_1_ +Mux19| Mcel 4 6 ( 206)| CLK_000_P_SYNC_0_ +Mux20| Mcel 1 14 ( 146)| RESET_DLY_7_ +Mux21| Input Pin ( 86)| RST +Mux22| IOPin 6 3 ( 68)| IPL_2_ +Mux23| ... | ... +Mux24| ... | ... +Mux25| ... | ... +Mux26| Mcel 1 0 ( 125)| RN_RESET +Mux27| Mcel 1 4 ( 131)| RN_IPL_030_2_ +Mux28| Mcel 3 2 ( 176)| cpu_est_2_ +Mux29| Mcel 3 13 ( 193)| cpu_est_1_ +Mux30| Mcel 5 1 ( 223)| RESET_DLY_3_ +Mux31| ... | ... +Mux32| Mcel 5 8 ( 233)| CLK_OUT_PRE_Dreg +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 2] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1|inst_DS_000_ENABLE|NOD| | S | 3 | 4 to [ 1]| 1 XOR free + 2| SM_AMIGA_5_|NOD| | S | 2 | 4 to [ 2]| 1 XOR free + 3| | ? | | S | | 4 free | 1 XOR free + 4|inst_CLK_000_PE|NOD| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 5| SM_AMIGA_4_|NOD| | S | 2 | 4 to [ 5]| 1 XOR free + 6|CLK_000_P_SYNC_7_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7| | ? | | S | | 4 free | 1 XOR free + 8| SM_AMIGA_1_|NOD| | S | 2 | 4 to [ 8]| 1 XOR free + 9|inst_AS_000_INT|NOD| | S | 2 | 4 to [ 9]| 1 XOR free +10|CLK_000_P_SYNC_6_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11| | ? | | S | | 4 to [12]| 1 XOR free +12| SM_AMIGA_6_|NOD| | S | 2 | 4 to [13]| 1 XOR free +13|sm_amiga_ns_0_3_0__n|NOD| | S |11 | 4 to [13]| 1 XOR to [13] as logic PT +14|CLK_000_P_SYNC_5_|NOD| | S | 1 | 4 to [13]| 1 XOR to [14] for 1 PT sig +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 2] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1 |=> can support up to [ 5] logic PT(s) + 1|inst_DS_000_ENABLE|NOD| | S | 3 |=> can support up to [ 14] logic PT(s) + 2| SM_AMIGA_5_|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 9] logic PT(s) + 4|inst_CLK_000_PE|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 5| SM_AMIGA_4_|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) + 6|CLK_000_P_SYNC_7_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) + 7| | ? | | S | |=> can support up to [ 9] logic PT(s) + 8| SM_AMIGA_1_|NOD| | S | 2 |=> can support up to [ 14] logic PT(s) + 9|inst_AS_000_INT|NOD| | S | 2 |=> can support up to [ 9] logic PT(s) +10|CLK_000_P_SYNC_6_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) +11| | ? | | S | |=> can support up to [ 5] logic PT(s) +12| SM_AMIGA_6_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) +13|sm_amiga_ns_0_3_0__n|NOD| | S |11 |=> can support up to [ 19] logic PT(s) +14|CLK_000_P_SYNC_5_|NOD| | S | 1 |=> can support up to [ 6] logic PT(s) +15| | ? | | S | |=> can support up to [ 5] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 2] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 2] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0|AMIGA_BUS_ENABLE_LOW|OUT| | => |( 5) 6 7 0 |( 20) 21 22 15 + 1|inst_DS_000_ENABLE|NOD| | => | 5 6 7 0 | 20 21 22 15 + 2| SM_AMIGA_5_|NOD| | => | 6 7 0 1 | 21 22 15 16 + 3| | | | => | 6 7 0 1 | 21 22 15 16 + 4|inst_CLK_000_PE|NOD| | => | 7 0 1 2 | 22 15 16 17 + 5| SM_AMIGA_4_|NOD| | => | 7 0 1 2 | 22 15 16 17 + 6|CLK_000_P_SYNC_7_|NOD| | => | 0 1 2 3 | 15 16 17 18 + 7| | | | => | 0 1 2 3 | 15 16 17 18 + 8| SM_AMIGA_1_|NOD| | => | 1 2 3 4 | 16 17 18 19 + 9|inst_AS_000_INT|NOD| | => | 1 2 3 4 | 16 17 18 19 +10|CLK_000_P_SYNC_6_|NOD| | => | 2 3 4 5 | 17 18 19 20 +11| | | | => | 2 3 4 5 | 17 18 19 20 +12| SM_AMIGA_6_|NOD| | => | 3 4 5 6 | 18 19 20 21 +13|sm_amiga_ns_0_3_0__n|NOD| | => | 3 4 5 6 | 18 19 20 21 +14|CLK_000_P_SYNC_5_|NOD| | => | 4 5 6 7 | 19 20 21 22 +15| | | | => | 4 5 6 7 | 19 20 21 22 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 2] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| A_28_|INP|*| 15| => | 0 1 2 3 4 5 6 7 + 1| A_27_|INP|*| 16| => | 2 3 4 5 6 7 8 9 + 2| A_26_|INP|*| 17| => | 4 5 6 7 8 9 10 11 + 3| A_25_|INP|*| 18| => | 6 7 8 9 10 11 12 13 + 4| A_24_|INP|*| 19| => | 8 9 10 11 12 13 14 15 + 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | 10 11 12 13 14 15 ( 0) 1 + 6| BG_030|INP|*| 21| => | 12 13 14 15 0 1 2 3 + 7| | | | 22| => | 14 15 0 1 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 2] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| A_28_|INP|*| 15| => | Input macrocell [ -] + 1| A_27_|INP|*| 16| => | Input macrocell [ -] + 2| A_26_|INP|*| 17| => | Input macrocell [ -] + 3| A_25_|INP|*| 18| => | Input macrocell [ -] + 4| A_24_|INP|*| 19| => | Input macrocell [ -] + 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | Input macrocell [ -] + 6| BG_030|INP|*| 21| => | Input macrocell [ -] + 7| | | | 22| => | Input macrocell [ -] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 2] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 15|INP A_28_|*|*] + [RegIn 0 |150| -| | ] + [MCell 0 |149|OUT AMIGA_BUS_ENABLE_LOW| | ] + [MCell 1 |151|NOD inst_DS_000_ENABLE| |*] + + 1 [IOpin 1 | 16|INP A_27_|*|*] + [RegIn 1 |153| -| | ] + [MCell 2 |152|NOD SM_AMIGA_5_| |*] + [MCell 3 |154| -| | ] + + 2 [IOpin 2 | 17|INP A_26_|*|*] + [RegIn 2 |156| -| | ] + [MCell 4 |155|NOD inst_CLK_000_PE| |*] + [MCell 5 |157|NOD SM_AMIGA_4_| |*] + + 3 [IOpin 3 | 18|INP A_25_|*|*] + [RegIn 3 |159| -| | ] + [MCell 6 |158|NOD CLK_000_P_SYNC_7_| |*] + [MCell 7 |160| -| | ] + + 4 [IOpin 4 | 19|INP A_24_|*|*] + [RegIn 4 |162| -| | ] + [MCell 8 |161|NOD SM_AMIGA_1_| |*] + [MCell 9 |163|NOD inst_AS_000_INT| |*] + + 5 [IOpin 5 | 20|OUT AMIGA_BUS_ENABLE_LOW|*| ] + [RegIn 5 |165| -| | ] + [MCell 10 |164|NOD CLK_000_P_SYNC_6_| |*] + [MCell 11 |166| -| | ] + + 6 [IOpin 6 | 21|INP BG_030|*|*] + [RegIn 6 |168| -| | ] + [MCell 12 |167|NOD SM_AMIGA_6_| |*] + [MCell 13 |169|NOD sm_amiga_ns_0_3_0__n| |*] + + 7 [IOpin 7 | 22| -| | ] + [RegIn 7 |171| -| | ] + [MCell 14 |170|NOD CLK_000_P_SYNC_5_| |*] + [MCell 15 |172| -| | ] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 2] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Input Pin ( 86)| RST +Mux01| Mcel 2 1 ( 151)| inst_DS_000_ENABLE +Mux02| Mcel 1 6 ( 134)| CLK_000_P_SYNC_4_ +Mux03| Mcel 2 9 ( 163)| inst_AS_000_INT +Mux04| Mcel 2 12 ( 167)| SM_AMIGA_6_ +Mux05| Mcel 6 3 ( 250)| CLK_000_P_SYNC_9_ +Mux06| Mcel 2 4 ( 155)| inst_CLK_000_PE +Mux07| Mcel 2 14 ( 170)| CLK_000_P_SYNC_5_ +Mux08| IOPin 6 6 ( 71)| RW +Mux09| Mcel 5 2 ( 224)| SM_AMIGA_3_ +Mux10| Mcel 3 14 ( 194)| inst_CLK_000_D0 +Mux11| Mcel 5 6 ( 230)| SM_AMIGA_2_ +Mux12| ... | ... +Mux13| ... | ... +Mux14| Mcel 4 5 ( 205)| inst_CLK_000_D1 +Mux15| Mcel 2 5 ( 157)| SM_AMIGA_4_ +Mux16| Mcel 2 8 ( 161)| SM_AMIGA_1_ +Mux17| IOPin 4 0 ( 41)| BERR +Mux18| Mcel 2 10 ( 164)| CLK_000_P_SYNC_6_ +Mux19| Mcel 0 9 ( 115)| inst_AMIGA_BUS_ENABLE_DMA_LOW +Mux20| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux21| ... | ... +Mux22| Mcel 2 2 ( 152)| SM_AMIGA_5_ +Mux23| ... | ... +Mux24| ... | ... +Mux25| Mcel 5 0 ( 221)| SM_AMIGA_7_ +Mux26| ... | ... +Mux27| Mcel 7 9 ( 283)| inst_AS_030_D0 +Mux28| Mcel 7 13 ( 289)| inst_AS_030_000_SYNC +Mux29| Mcel 5 4 ( 227)| SM_AMIGA_0_ +Mux30| Mcel 4 8 ( 209)| inst_CLK_000_NE +Mux31| Mcel 1 5 ( 133)| inst_nEXP_SPACE_D0 +Mux32| ... | ... +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 3] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0| DTACK| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1| BG_000| IO| | S | 2 | 4 to [ 1]| 1 XOR free + 2| cpu_est_2_|NOD| | S | 4 | 4 to [ 2]| 1 XOR free + 3|CLK_000_N_SYNC_4_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 4| VMA| IO| | S | 3 :+: 1| 4 to [ 4]| 1 XOR to [ 4] + 5|AMIGA_ADDR_ENABLE| IO| | S | 3 | 4 to [ 5]| 1 XOR free + 6| cpu_est_0_|NOD| | S | 2 | 4 to [ 6]| 1 XOR free + 7| inst_DTACK_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 8| UDS_000| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig +10|inst_CLK_000_NE_D0|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11| | ? | | S | | 4 free | 1 XOR free +12| LDS_000| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13| cpu_est_1_|NOD| | S | 5 | 4 to [13]| 1 XOR to [13] as logic PT +14|inst_CLK_000_D0|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 3] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0| DTACK| IO| | S | 1 |=> can support up to [ 5] logic PT(s) + 1| BG_000| IO| | S | 2 |=> can support up to [ 13] logic PT(s) + 2| cpu_est_2_|NOD| | S | 4 |=> can support up to [ 9] logic PT(s) + 3|CLK_000_N_SYNC_4_|NOD| | S | 1 |=> can support up to [ 5] logic PT(s) + 4| VMA| IO| | S | 3 :+: 1|=> can support up to [ 8] logic PT(s) + 5|AMIGA_ADDR_ENABLE| IO| | S | 3 |=> can support up to [ 9] logic PT(s) + 6| cpu_est_0_|NOD| | S | 2 |=> can support up to [ 13] logic PT(s) + 7| inst_DTACK_D0|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 8| UDS_000| IO| | S | 1 |=> can support up to [ 17] logic PT(s) + 9|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 1 |=> can support up to [ 18] logic PT(s) +10|inst_CLK_000_NE_D0|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) +11| | ? | | S | |=> can support up to [ 13] logic PT(s) +12| LDS_000| IO| | S | 1 |=> can support up to [ 14] logic PT(s) +13| cpu_est_1_|NOD| | S | 5 |=> can support up to [ 18] logic PT(s) +14|inst_CLK_000_D0|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 9] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 3] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 3] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0| DTACK| IO| | => |( 5) 6 7 0 |( 30) 29 28 35 + 1| BG_000| IO| | => | 5 ( 6) 7 0 | 30 ( 29) 28 35 + 2| cpu_est_2_|NOD| | => | 6 7 0 1 | 29 28 35 34 + 3|CLK_000_N_SYNC_4_|NOD| | => | 6 7 0 1 | 29 28 35 34 + 4| VMA| IO| | => | 7 ( 0) 1 2 | 28 ( 35) 34 33 + 5|AMIGA_ADDR_ENABLE| IO| | => | 7 0 1 ( 2)| 28 35 34 ( 33) + 6| cpu_est_0_|NOD| | => | 0 1 2 3 | 35 34 33 32 + 7| inst_DTACK_D0|NOD| | => | 0 1 2 3 | 35 34 33 32 + 8| UDS_000| IO| | => | 1 2 ( 3) 4 | 34 33 ( 32) 31 + 9|AMIGA_BUS_ENABLE_HIGH|OUT| | => |( 1) 2 3 4 |( 34) 33 32 31 +10|inst_CLK_000_NE_D0|NOD| | => | 2 3 4 5 | 33 32 31 30 +11| | | | => | 2 3 4 5 | 33 32 31 30 +12| LDS_000| IO| | => | 3 ( 4) 5 6 | 32 ( 31) 30 29 +13| cpu_est_1_|NOD| | => | 3 4 5 6 | 32 31 30 29 +14|inst_CLK_000_D0|NOD| | => | 4 5 6 7 | 31 30 29 28 +15| | | | => | 4 5 6 7 | 31 30 29 28 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 3] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| VMA| IO|*| 35| => | 0 1 2 3 ( 4) 5 6 7 + 1|AMIGA_BUS_ENABLE_HIGH|OUT|*| 34| => | 2 3 4 5 6 7 8 ( 9) + 2|AMIGA_ADDR_ENABLE| IO|*| 33| => | 4 ( 5) 6 7 8 9 10 11 + 3| UDS_000| IO|*| 32| => | 6 7 ( 8) 9 10 11 12 13 + 4| LDS_000| IO|*| 31| => | 8 9 10 11 (12) 13 14 15 + 5| DTACK| IO|*| 30| => | 10 11 12 13 14 15 ( 0) 1 + 6| BG_000| IO|*| 29| => | 12 13 14 15 0 ( 1) 2 3 + 7| BGACK_000|INP|*| 28| => | 14 15 0 1 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 3] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| VMA| IO|*| 35| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_VMA] + 1|AMIGA_BUS_ENABLE_HIGH|OUT|*| 34| => | Input macrocell [ -] + 2|AMIGA_ADDR_ENABLE| IO|*| 33| => | Input macrocell [ -] + | | | | | | IO paired w/ node [RN_AMIGA_ADDR_ENABLE] + 3| UDS_000| IO|*| 32| => | Input macrocell [ -] + 4| LDS_000| IO|*| 31| => | Input macrocell [ -] + 5| DTACK| IO|*| 30| => | Input macrocell [ -] + 6| BG_000| IO|*| 29| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_BG_000] + 7| BGACK_000|INP|*| 28| => | Input macrocell [ -] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 3] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 35| IO VMA|*| ] paired w/[ RN_VMA] + [RegIn 0 |174| -| | ] + [MCell 0 |173| IO DTACK| | ] + [MCell 1 |175|NOD RN_BG_000| |*] paired w/[ BG_000] + + 1 [IOpin 1 | 34|OUT AMIGA_BUS_ENABLE_HIGH|*| ] + [RegIn 1 |177| -| | ] + [MCell 2 |176|NOD cpu_est_2_| |*] + [MCell 3 |178|NOD CLK_000_N_SYNC_4_| |*] + + 2 [IOpin 2 | 33| IO AMIGA_ADDR_ENABLE|*| ] paired w/[RN_AMIGA_ADDR_ENABLE] + [RegIn 2 |180| -| | ] + [MCell 4 |179|NOD RN_VMA| |*] paired w/[ VMA] + [MCell 5 |181|NOD RN_AMIGA_ADDR_ENABLE| |*] paired w/[AMIGA_ADDR_ENABLE] + + 3 [IOpin 3 | 32| IO UDS_000|*|*] + [RegIn 3 |183| -| | ] + [MCell 6 |182|NOD cpu_est_0_| |*] + [MCell 7 |184|NOD inst_DTACK_D0| |*] + + 4 [IOpin 4 | 31| IO LDS_000|*|*] + [RegIn 4 |186| -| | ] + [MCell 8 |185| IO UDS_000| | ] + [MCell 9 |187|OUT AMIGA_BUS_ENABLE_HIGH| | ] + + 5 [IOpin 5 | 30| IO DTACK|*|*] + [RegIn 5 |189| -| | ] + [MCell 10 |188|NOD inst_CLK_000_NE_D0| |*] + [MCell 11 |190| -| | ] + + 6 [IOpin 6 | 29| IO BG_000|*| ] paired w/[ RN_BG_000] + [RegIn 6 |192| -| | ] + [MCell 12 |191| IO LDS_000| | ] + [MCell 13 |193|NOD cpu_est_1_| |*] + + 7 [IOpin 7 | 28|INP BGACK_000|*|*] + [RegIn 7 |195| -| | ] + [MCell 14 |194|NOD inst_CLK_000_D0| |*] + [MCell 15 |196| -| | ] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 3] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Mcel 1 5 ( 133)| inst_nEXP_SPACE_D0 +Mux01| Mcel 2 1 ( 151)| inst_DS_000_ENABLE +Mux02| Mcel 6 4 ( 251)| RN_E +Mux03| Input Pin ( 11)| CLK_000 +Mux04| IOPin 2 6 ( 21)| BG_030 +Mux05| Mcel 6 6 ( 254)| CLK_000_N_SYNC_3_ +Mux06| Mcel 2 4 ( 155)| inst_CLK_000_PE +Mux07| Mcel 7 6 ( 278)| inst_BGACK_030_INT_D +Mux08| Mcel 4 8 ( 209)| inst_CLK_000_NE +Mux09| IOPin 3 5 ( 30)| DTACK +Mux10| Mcel 3 14 ( 194)| inst_CLK_000_D0 +Mux11| Mcel 3 5 ( 181)| RN_AMIGA_ADDR_ENABLE +Mux12| IOPin 0 7 ( 98)| DS_030 +Mux13| ... | ... +Mux14| Mcel 3 4 ( 179)| RN_VMA +Mux15| Mcel 0 12 ( 119)| inst_UDS_000_INT +Mux16| Mcel 3 2 ( 176)| cpu_est_2_ +Mux17| Mcel 3 1 ( 175)| RN_BG_000 +Mux18| Mcel 0 8 ( 113)| inst_LDS_000_INT +Mux19| Mcel 5 10 ( 236)| inst_VPA_D +Mux20| Mcel 3 10 ( 188)| inst_CLK_000_NE_D0 +Mux21| Input Pin ( 86)| RST +Mux22| Mcel 6 5 ( 253)| inst_AS_000_DMA +Mux23| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux24| ... | ... +Mux25| Mcel 0 13 ( 121)| inst_AMIGA_BUS_ENABLE_DMA_HIGH +Mux26| Mcel 4 5 ( 205)| inst_CLK_000_D1 +Mux27| Mcel 7 9 ( 283)| inst_AS_030_D0 +Mux28| Mcel 7 13 ( 289)| inst_AS_030_000_SYNC +Mux29| Mcel 3 13 ( 193)| cpu_est_1_ +Mux30| Mcel 3 6 ( 182)| cpu_est_0_ +Mux31| Mcel 5 0 ( 221)| SM_AMIGA_7_ +Mux32| IOPin 7 4 ( 81)| DSACK1 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 4] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0| BERR| IO| | S | 1 | 4 free | 1 XOR to [ 0] for 1 PT sig + 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 | 4 to [ 1]| 1 XOR free + 2|CLK_000_N_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 free | 1 XOR free + 4| AS_000| IO| | S | 1 | 4 free | 1 XOR to [ 4] for 1 PT sig + 5|inst_CLK_000_D1|NOD| | S | 1 | 4 free | 1 XOR to [ 5] for 1 PT sig + 6|CLK_000_P_SYNC_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7| | ? | | S | | 4 free | 1 XOR free + 8|inst_CLK_000_NE|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9| CIIN_0|NOD| | S | 3 | 4 to [ 9]| 1 XOR free +10| | ? | | S | | 4 free | 1 XOR free +11| | ? | | S | | 4 free | 1 XOR free +12| CIIN|OUT| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13|CLK_000_N_SYNC_9_|NOD| | S | 1 | 4 free | 1 XOR to [13] for 1 PT sig +14| | ? | | S | | 4 free | 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 4] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0| BERR| IO| | S | 1 |=> can support up to [ 9] logic PT(s) + 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2 |=> can support up to [ 18] logic PT(s) + 2|CLK_000_N_SYNC_0_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 3| | ? | | S | |=> can support up to [ 17] logic PT(s) + 4| AS_000| IO| | S | 1 |=> can support up to [ 18] logic PT(s) + 5|inst_CLK_000_D1|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 6|CLK_000_P_SYNC_0_|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) + 7| | ? | | S | |=> can support up to [ 13] logic PT(s) + 8|inst_CLK_000_NE|NOD| | S | 1 |=> can support up to [ 15] logic PT(s) + 9| CIIN_0|NOD| | S | 3 |=> can support up to [ 19] logic PT(s) +10| | ? | | S | |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 18] logic PT(s) +12| CIIN|OUT| | S | 1 |=> can support up to [ 19] logic PT(s) +13|CLK_000_N_SYNC_9_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) +14| | ? | | S | |=> can support up to [ 14] logic PT(s) +15| | ? | | S | |=> can support up to [ 10] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 4] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 4] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0| BERR| IO| | => | 5 6 7 ( 0)| 46 47 48 ( 41) + 1|AMIGA_BUS_DATA_DIR|OUT| | => | 5 6 ( 7) 0 | 46 47 ( 48) 41 + 2|CLK_000_N_SYNC_0_|NOD| | => | 6 7 0 1 | 47 48 41 42 + 3| | | | => | 6 7 0 1 | 47 48 41 42 + 4| AS_000| IO| | => | 7 0 ( 1) 2 | 48 41 ( 42) 43 + 5|inst_CLK_000_D1|NOD| | => | 7 0 1 2 | 48 41 42 43 + 6|CLK_000_P_SYNC_0_|NOD| | => | 0 1 2 3 | 41 42 43 44 + 7| | | | => | 0 1 2 3 | 41 42 43 44 + 8|inst_CLK_000_NE|NOD| | => | 1 2 3 4 | 42 43 44 45 + 9| CIIN_0|NOD| | => | 1 2 3 4 | 42 43 44 45 +10| | | | => | 2 3 4 5 | 43 44 45 46 +11| | | | => | 2 3 4 5 | 43 44 45 46 +12| CIIN|OUT| | => | 3 4 5 ( 6)| 44 45 46 ( 47) +13|CLK_000_N_SYNC_9_|NOD| | => | 3 4 5 6 | 44 45 46 47 +14| | | | => | 4 5 6 7 | 45 46 47 48 +15| | | | => | 4 5 6 7 | 45 46 47 48 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 4] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| BERR| IO|*| 41| => | ( 0) 1 2 3 4 5 6 7 + 1| AS_000| IO|*| 42| => | 2 3 ( 4) 5 6 7 8 9 + 2| | | | 43| => | 4 5 6 7 8 9 10 11 + 3| | | | 44| => | 6 7 8 9 10 11 12 13 + 4| | | | 45| => | 8 9 10 11 12 13 14 15 + 5| | | | 46| => | 10 11 12 13 14 15 0 1 + 6| CIIN|OUT|*| 47| => | (12) 13 14 15 0 1 2 3 + 7|AMIGA_BUS_DATA_DIR|OUT|*| 48| => | 14 15 0 ( 1) 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 4] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| BERR| IO|*| 41| => | Input macrocell [ -] + 1| AS_000| IO|*| 42| => | Input macrocell [ -] + 2| | | | 43| => | Input macrocell [ -] + 3| | | | 44| => | Input macrocell [ -] + 4| | | | 45| => | Input macrocell [ -] + 5| | | | 46| => | Input macrocell [ -] + 6| CIIN|OUT|*| 47| => | Input macrocell [ -] + 7|AMIGA_BUS_DATA_DIR|OUT|*| 48| => | Input macrocell [ -] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 4] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 41| IO BERR|*|*] + [RegIn 0 |198| -| | ] + [MCell 0 |197| IO BERR| | ] + [MCell 1 |199|OUT AMIGA_BUS_DATA_DIR| | ] + + 1 [IOpin 1 | 42| IO AS_000|*|*] + [RegIn 1 |201| -| | ] + [MCell 2 |200|NOD CLK_000_N_SYNC_0_| |*] + [MCell 3 |202| -| | ] + + 2 [IOpin 2 | 43| -| | ] + [RegIn 2 |204| -| | ] + [MCell 4 |203| IO AS_000| | ] + [MCell 5 |205|NOD inst_CLK_000_D1| |*] + + 3 [IOpin 3 | 44| -| | ] + [RegIn 3 |207| -| | ] + [MCell 6 |206|NOD CLK_000_P_SYNC_0_| |*] + [MCell 7 |208| -| | ] + + 4 [IOpin 4 | 45| -| | ] + [RegIn 4 |210| -| | ] + [MCell 8 |209|NOD inst_CLK_000_NE| |*] + [MCell 9 |211|NOD CIIN_0| |*] + + 5 [IOpin 5 | 46| -| | ] + [RegIn 5 |213| -| | ] + [MCell 10 |212| -| | ] + [MCell 11 |214| -| | ] + + 6 [IOpin 6 | 47|OUT CIIN|*| ] + [RegIn 6 |216| -| | ] + [MCell 12 |215|OUT CIIN| | ] + [MCell 13 |217|NOD CLK_000_N_SYNC_9_| |*] + + 7 [IOpin 7 | 48|OUT AMIGA_BUS_DATA_DIR|*| ] + [RegIn 7 |219| -| | ] + [MCell 14 |218| -| | ] + [MCell 15 |220| -| | ] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 4] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux01| IOPin 5 2 ( 58)| FC_1_ +Mux02| Mcel 4 9 ( 211)| CIIN_0 +Mux03| IOPin 2 1 ( 16)| A_27_ +Mux04| IOPin 1 4 ( 6)| A_29_ +Mux05| IOPin 2 4 ( 19)| A_24_ +Mux06| IOPin 7 5 ( 80)| RW_000 +Mux07| IOPin 2 0 ( 15)| A_28_ +Mux08| IOPin 0 0 ( 91)| FPU_SENSE +Mux09| IOPin 7 3 ( 82)| AS_030 +Mux10| Mcel 3 14 ( 194)| inst_CLK_000_D0 +Mux11| IOPin 0 5 ( 96)| A_16_ +Mux12| IOPin 0 6 ( 97)| A_19_ +Mux13| IOPin 5 1 ( 59)| A_17_ +Mux14| Mcel 0 10 ( 116)| CLK_000_N_SYNC_11_ +Mux15| IOPin 0 3 ( 94)| A_21_ +Mux16| IOPin 4 1 ( 42)| AS_000 +Mux17| IOPin 2 2 ( 17)| A_26_ +Mux18| IOPin 3 7 ( 28)| BGACK_000 +Mux19| IOPin 1 5 ( 5)| A_30_ +Mux20| IOPin 7 1 ( 84)| A_22_ +Mux21| Mcel 0 1 ( 103)| CLK_000_N_SYNC_8_ +Mux22| IOPin 2 3 ( 18)| A_25_ +Mux23| Mcel 2 9 ( 163)| inst_AS_000_INT +Mux24| IOPin 5 3 ( 57)| FC_0_ +Mux25| IOPin 1 6 ( 4)| A_31_ +Mux26| Mcel 4 5 ( 205)| inst_CLK_000_D1 +Mux27| Mcel 7 9 ( 283)| inst_AS_030_D0 +Mux28| Mcel 1 5 ( 133)| inst_nEXP_SPACE_D0 +Mux29| IOPin 0 2 ( 93)| A_20_ +Mux30| ... | ... +Mux31| IOPin 0 4 ( 95)| A_18_ +Mux32| IOPin 7 0 ( 85)| A_23_ +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0| SM_AMIGA_7_|NOD| | S | 4 | 4 to [ 0]| 1 XOR free + 1| RESET_DLY_3_|NOD| | S | 1 :+: 1| 4 to [ 1]| 1 XOR to [ 1] + 2| SM_AMIGA_3_|NOD| | S | 6 :+: 1| 4 to [ 2]| 1 XOR to [ 2] + 3|CLK_000_P_SYNC_8_|NOD| | S | 1 | 4 to [ 2]| 1 XOR to [ 3] for 1 PT sig + 4| SM_AMIGA_0_|NOD| | S | 2 | 4 to [ 4]| 1 XOR free + 5| RESET_DLY_2_|NOD| | S | 1 :+: 1| 4 to [ 5]| 1 XOR to [ 5] + 6| SM_AMIGA_2_|NOD| | S | 3 | 4 to [ 6]| 1 XOR free + 7|inst_CLK_OUT_PRE|NOD| | S | 1 | 4 free | 1 XOR to [ 7] for 1 PT sig + 8|CLK_OUT_PRE_Dreg|NOD| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9| RESET_DLY_1_|NOD| | S | 1 :+: 1| 4 to [ 9]| 1 XOR to [ 9] +10| inst_VPA_D|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11|inst_CLK_OUT_PRE_50|NOD| | S | 1 | 4 free | 1 XOR to [11] for 1 PT sig +12| RESET_DLY_4_|NOD| | S | 1 :+: 1| 4 to [12]| 1 XOR to [12] +13| RESET_DLY_0_|NOD| | S | 1 :+: 1| 4 to [13]| 1 XOR to [13] +14|CLK_000_N_SYNC_7_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0| SM_AMIGA_7_|NOD| | S | 4 |=> can support up to [ 5] logic PT(s) + 1| RESET_DLY_3_|NOD| | S | 1 :+: 1|=> can support up to [ 4] logic PT(s) + 2| SM_AMIGA_3_|NOD| | S | 6 :+: 1|=> can support up to [ 8] logic PT(s) + 3|CLK_000_P_SYNC_8_|NOD| | S | 1 |=> can support up to [ 1] logic PT(s) + 4| SM_AMIGA_0_|NOD| | S | 2 |=> can support up to [ 5] logic PT(s) + 5| RESET_DLY_2_|NOD| | S | 1 :+: 1|=> can support up to [ 8] logic PT(s) + 6| SM_AMIGA_2_|NOD| | S | 3 |=> can support up to [ 13] logic PT(s) + 7|inst_CLK_OUT_PRE|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 8|CLK_OUT_PRE_Dreg|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 9| RESET_DLY_1_|NOD| | S | 1 :+: 1|=> can support up to [ 16] logic PT(s) +10| inst_VPA_D|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) +11|inst_CLK_OUT_PRE_50|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) +12| RESET_DLY_4_|NOD| | S | 1 :+: 1|=> can support up to [ 12] logic PT(s) +13| RESET_DLY_0_|NOD| | S | 1 :+: 1|=> can support up to [ 13] logic PT(s) +14|CLK_000_N_SYNC_7_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 9] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 5] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0| SM_AMIGA_7_|NOD| | => | 5 6 7 0 | 55 54 53 60 + 1| RESET_DLY_3_|NOD| | => | 5 6 7 0 | 55 54 53 60 + 2| SM_AMIGA_3_|NOD| | => | 6 7 0 1 | 54 53 60 59 + 3|CLK_000_P_SYNC_8_|NOD| | => | 6 7 0 1 | 54 53 60 59 + 4| SM_AMIGA_0_|NOD| | => | 7 0 1 2 | 53 60 59 58 + 5| RESET_DLY_2_|NOD| | => | 7 0 1 2 | 53 60 59 58 + 6| SM_AMIGA_2_|NOD| | => | 0 1 2 3 | 60 59 58 57 + 7|inst_CLK_OUT_PRE|NOD| | => | 0 1 2 3 | 60 59 58 57 + 8|CLK_OUT_PRE_Dreg|NOD| | => | 1 2 3 4 | 59 58 57 56 + 9| RESET_DLY_1_|NOD| | => | 1 2 3 4 | 59 58 57 56 +10| inst_VPA_D|NOD| | => | 2 3 4 5 | 58 57 56 55 +11|inst_CLK_OUT_PRE_50|NOD| | => | 2 3 4 5 | 58 57 56 55 +12| RESET_DLY_4_|NOD| | => | 3 4 5 6 | 57 56 55 54 +13| RESET_DLY_0_|NOD| | => | 3 4 5 6 | 57 56 55 54 +14|CLK_000_N_SYNC_7_|NOD| | => | 4 5 6 7 | 56 55 54 53 +15| | | | => | 4 5 6 7 | 56 55 54 53 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| A1|INP|*| 60| => | 0 1 2 3 4 5 6 7 + 1| A_17_|INP|*| 59| => | 2 3 4 5 6 7 8 9 + 2| FC_1_|INP|*| 58| => | 4 5 6 7 8 9 10 11 + 3| FC_0_|INP|*| 57| => | 6 7 8 9 10 11 12 13 + 4| IPL_1_|INP|*| 56| => | 8 9 10 11 12 13 14 15 + 5| | | | 55| => | 10 11 12 13 14 15 0 1 + 6| | | | 54| => | 12 13 14 15 0 1 2 3 + 7| | | | 53| => | 14 15 0 1 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| A1|INP|*| 60| => | Input macrocell [ -] + 1| A_17_|INP|*| 59| => | Input macrocell [ -] + 2| FC_1_|INP|*| 58| => | Input macrocell [ -] + 3| FC_0_|INP|*| 57| => | Input macrocell [ -] + 4| IPL_1_|INP|*| 56| => | Input macrocell [ -] + 5| | | | 55| => | Input macrocell [ -] + 6| | | | 54| => | Input macrocell [ -] + 7| | | | 53| => | Input macrocell [ -] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 60|INP A1|*|*] + [RegIn 0 |222| -| | ] + [MCell 0 |221|NOD SM_AMIGA_7_| |*] + [MCell 1 |223|NOD RESET_DLY_3_| |*] + + 1 [IOpin 1 | 59|INP A_17_|*|*] + [RegIn 1 |225| -| | ] + [MCell 2 |224|NOD SM_AMIGA_3_| |*] + [MCell 3 |226|NOD CLK_000_P_SYNC_8_| |*] + + 2 [IOpin 2 | 58|INP FC_1_|*|*] + [RegIn 2 |228| -| | ] + [MCell 4 |227|NOD SM_AMIGA_0_| |*] + [MCell 5 |229|NOD RESET_DLY_2_| |*] + + 3 [IOpin 3 | 57|INP FC_0_|*|*] + [RegIn 3 |231| -| | ] + [MCell 6 |230|NOD SM_AMIGA_2_| |*] + [MCell 7 |232|NOD inst_CLK_OUT_PRE| |*] + + 4 [IOpin 4 | 56|INP IPL_1_|*|*] + [RegIn 4 |234| -| | ] + [MCell 8 |233|NOD CLK_OUT_PRE_Dreg| |*] + [MCell 9 |235|NOD RESET_DLY_1_| |*] + + 5 [IOpin 5 | 55| -| | ] + [RegIn 5 |237| -| | ] + [MCell 10 |236|NOD inst_VPA_D| |*] + [MCell 11 |238|NOD inst_CLK_OUT_PRE_50| |*] + + 6 [IOpin 6 | 54| -| | ] + [RegIn 6 |240| -| | ] + [MCell 12 |239|NOD RESET_DLY_4_| |*] + [MCell 13 |241|NOD RESET_DLY_0_| |*] + + 7 [IOpin 7 | 53| -| | ] + [RegIn 7 |243| -| | ] + [MCell 14 |242|NOD CLK_000_N_SYNC_7_| |*] + [MCell 15 |244| -| | ] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 5] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Mcel 0 2 ( 104)| CLK_000_N_SYNC_6_ +Mux01| Mcel 3 13 ( 193)| cpu_est_1_ +Mux02| Mcel 5 10 ( 236)| inst_VPA_D +Mux03| Mcel 5 11 ( 238)| inst_CLK_OUT_PRE_50 +Mux04| Mcel 3 6 ( 182)| cpu_est_0_ +Mux05| ... | ... +Mux06| Mcel 2 4 ( 155)| inst_CLK_000_PE +Mux07| Mcel 2 8 ( 161)| SM_AMIGA_1_ +Mux08| Mcel 4 8 ( 209)| inst_CLK_000_NE +Mux09| Mcel 2 6 ( 158)| CLK_000_P_SYNC_7_ +Mux10| Input Pin ( 36)| VPA +Mux11| Mcel 2 13 ( 169)| sm_amiga_ns_0_3_0__n +Mux12| ... | ... +Mux13| Mcel 3 7 ( 184)| inst_DTACK_D0 +Mux14| Mcel 3 4 ( 179)| RN_VMA +Mux15| Mcel 2 5 ( 157)| SM_AMIGA_4_ +Mux16| Mcel 3 2 ( 176)| cpu_est_2_ +Mux17| IOPin 4 0 ( 41)| BERR +Mux18| Mcel 5 9 ( 235)| RESET_DLY_1_ +Mux19| Mcel 5 6 ( 230)| SM_AMIGA_2_ +Mux20| Mcel 3 10 ( 188)| inst_CLK_000_NE_D0 +Mux21| Mcel 6 4 ( 251)| RN_E +Mux22| Mcel 5 13 ( 241)| RESET_DLY_0_ +Mux23| ... | ... +Mux24| Input Pin ( 86)| RST +Mux25| Mcel 5 7 ( 232)| inst_CLK_OUT_PRE +Mux26| ... | ... +Mux27| Mcel 5 5 ( 229)| RESET_DLY_2_ +Mux28| Mcel 5 2 ( 224)| SM_AMIGA_3_ +Mux29| Mcel 5 4 ( 227)| SM_AMIGA_0_ +Mux30| Mcel 5 1 ( 223)| RESET_DLY_3_ +Mux31| Mcel 5 12 ( 239)| RESET_DLY_4_ +Mux32| ... | ... +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 6] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0| RW| IO| | S | 4 | 4 to [ 0]| 1 XOR free + 1| CLK_DIV_OUT|OUT| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2| SIZE_DMA_0_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3|CLK_000_P_SYNC_9_|NOD| | S | 1 | 4 free | 1 XOR to [ 3] for 1 PT sig + 4| E| IO| | S | 3 :+: 1| 4 to [ 4]| 1 XOR to [ 4] + 5|inst_AS_000_DMA|NOD| | S | 4 | 4 to [ 5]| 1 XOR free + 6|CLK_000_N_SYNC_3_|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7| | ? | | S | | 4 free | 1 XOR free + 8| A0| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9| SIZE_DMA_1_|NOD| | S | 2 | 4 to [ 9]| 1 XOR free +10|CLK_000_N_SYNC_1_|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11| | ? | | S | | 4 free | 1 XOR free +12| SIZE_0_| IO| | S | 1 | 4 free | 1 XOR to [12] for 1 PT sig +13| RESET_DLY_5_|NOD| | S | 1 :+: 1| 4 to [13]| 1 XOR to [13] +14|CLK_000_P_SYNC_3_|NOD| | S | 1 | 4 free | 1 XOR to [14] for 1 PT sig +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 6] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0| RW| IO| | S | 4 |=> can support up to [ 13] logic PT(s) + 1| CLK_DIV_OUT|OUT| | S | 1 |=> can support up to [ 13] logic PT(s) + 2| SIZE_DMA_0_|NOD| | S | 1 |=> can support up to [ 13] logic PT(s) + 3|CLK_000_P_SYNC_9_|NOD| | S | 1 |=> can support up to [ 9] logic PT(s) + 4| E| IO| | S | 3 :+: 1|=> can support up to [ 12] logic PT(s) + 5|inst_AS_000_DMA|NOD| | S | 4 |=> can support up to [ 14] logic PT(s) + 6|CLK_000_N_SYNC_3_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 7| | ? | | S | |=> can support up to [ 13] logic PT(s) + 8| A0| IO| | S | 1 |=> can support up to [ 14] logic PT(s) + 9| SIZE_DMA_1_|NOD| | S | 2 |=> can support up to [ 18] logic PT(s) +10|CLK_000_N_SYNC_1_|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 13] logic PT(s) +12| SIZE_0_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) +13| RESET_DLY_5_|NOD| | S | 1 :+: 1|=> can support up to [ 17] logic PT(s) +14|CLK_000_P_SYNC_3_|NOD| | S | 1 |=> can support up to [ 10] logic PT(s) +15| | ? | | S | |=> can support up to [ 9] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 6] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 6] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0| RW| IO| | => | 5 ( 6) 7 0 | 70 ( 71) 72 65 + 1| CLK_DIV_OUT|OUT| | => | 5 6 7 ( 0)| 70 71 72 ( 65) + 2| SIZE_DMA_0_|NOD| | => | 6 7 0 1 | 71 72 65 66 + 3|CLK_000_P_SYNC_9_|NOD| | => | 6 7 0 1 | 71 72 65 66 + 4| E| IO| | => | 7 0 ( 1) 2 | 72 65 ( 66) 67 + 5|inst_AS_000_DMA|NOD| | => | 7 0 1 2 | 72 65 66 67 + 6|CLK_000_N_SYNC_3_|NOD| | => | 0 1 2 3 | 65 66 67 68 + 7| | | | => | 0 1 2 3 | 65 66 67 68 + 8| A0| IO| | => | 1 2 3 ( 4)| 66 67 68 ( 69) + 9| SIZE_DMA_1_|NOD| | => | 1 2 3 4 | 66 67 68 69 +10|CLK_000_N_SYNC_1_|NOD| | => | 2 3 4 5 | 67 68 69 70 +11| | | | => | 2 3 4 5 | 67 68 69 70 +12| SIZE_0_| IO| | => | 3 4 ( 5) 6 | 68 69 ( 70) 71 +13| RESET_DLY_5_|NOD| | => | 3 4 5 6 | 68 69 70 71 +14|CLK_000_P_SYNC_3_|NOD| | => | 4 5 6 7 | 69 70 71 72 +15| | | | => | 4 5 6 7 | 69 70 71 72 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 6] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| CLK_DIV_OUT|OUT|*| 65| => | 0 ( 1) 2 3 4 5 6 7 + 1| E| IO|*| 66| => | 2 3 ( 4) 5 6 7 8 9 + 2| IPL_0_|INP|*| 67| => | 4 5 6 7 8 9 10 11 + 3| IPL_2_|INP|*| 68| => | 6 7 8 9 10 11 12 13 + 4| A0| IO|*| 69| => | ( 8) 9 10 11 12 13 14 15 + 5| SIZE_0_| IO|*| 70| => | 10 11 (12) 13 14 15 0 1 + 6| RW| IO|*| 71| => | 12 13 14 15 ( 0) 1 2 3 + 7| | | | 72| => | 14 15 0 1 2 3 4 5 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 6] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| CLK_DIV_OUT|OUT|*| 65| => | Input macrocell [ -] + 1| E| IO|*| 66| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_E] + 2| IPL_0_|INP|*| 67| => | Input macrocell [ -] + 3| IPL_2_|INP|*| 68| => | Input macrocell [ -] + 4| A0| IO|*| 69| => | Input macrocell [ -] + 5| SIZE_0_| IO|*| 70| => | Input macrocell [ -] + 6| RW| IO|*| 71| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_RW] + 7| | | | 72| => | Input macrocell [ -] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 6] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 65|OUT CLK_DIV_OUT|*| ] + [RegIn 0 |246| -| | ] + [MCell 0 |245|NOD RN_RW| |*] paired w/[ RW] + [MCell 1 |247|OUT CLK_DIV_OUT| | ] + + 1 [IOpin 1 | 66| IO E|*| ] paired w/[ RN_E] + [RegIn 1 |249| -| | ] + [MCell 2 |248|NOD SIZE_DMA_0_| |*] + [MCell 3 |250|NOD CLK_000_P_SYNC_9_| |*] + + 2 [IOpin 2 | 67|INP IPL_0_|*|*] + [RegIn 2 |252| -| | ] + [MCell 4 |251|NOD RN_E| |*] paired w/[ E] + [MCell 5 |253|NOD inst_AS_000_DMA| |*] + + 3 [IOpin 3 | 68|INP IPL_2_|*|*] + [RegIn 3 |255| -| | ] + [MCell 6 |254|NOD CLK_000_N_SYNC_3_| |*] + [MCell 7 |256| -| | ] + + 4 [IOpin 4 | 69| IO A0|*|*] + [RegIn 4 |258| -| | ] + [MCell 8 |257| IO A0| | ] + [MCell 9 |259|NOD SIZE_DMA_1_| |*] + + 5 [IOpin 5 | 70| IO SIZE_0_|*|*] + [RegIn 5 |261| -| | ] + [MCell 10 |260|NOD CLK_000_N_SYNC_1_| |*] + [MCell 11 |262| -| | ] + + 6 [IOpin 6 | 71| IO RW|*|*] paired w/[ RN_RW] + [RegIn 6 |264| -| | ] + [MCell 12 |263| IO SIZE_0_| | ] + [MCell 13 |265|NOD RESET_DLY_5_| |*] + + 7 [IOpin 7 | 72| -| | ] + [RegIn 7 |267| -| | ] + [MCell 14 |266|NOD CLK_000_P_SYNC_3_| |*] + [MCell 15 |268| -| | ] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 6] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux01| Mcel 5 9 ( 235)| RESET_DLY_1_ +Mux02| Mcel 3 10 ( 188)| inst_CLK_000_NE_D0 +Mux03| Mcel 4 2 ( 200)| CLK_000_N_SYNC_0_ +Mux04| Mcel 3 6 ( 182)| cpu_est_0_ +Mux05| ... | ... +Mux06| IOPin 7 5 ( 80)| RW_000 +Mux07| Mcel 5 3 ( 226)| CLK_000_P_SYNC_8_ +Mux08| IOPin 3 3 ( 32)| UDS_000 +Mux09| Mcel 6 13 ( 265)| RESET_DLY_5_ +Mux10| Mcel 0 6 ( 110)| CLK_000_P_SYNC_2_ +Mux11| Mcel 6 4 ( 251)| RN_E +Mux12| Mcel 6 9 ( 259)| SIZE_DMA_1_ +Mux13| ... | ... +Mux14| Mcel 5 5 ( 229)| RESET_DLY_2_ +Mux15| Mcel 5 13 ( 241)| RESET_DLY_0_ +Mux16| Mcel 3 2 ( 176)| cpu_est_2_ +Mux17| Mcel 6 0 ( 245)| RN_RW +Mux18| Mcel 1 2 ( 128)| CLK_000_N_SYNC_2_ +Mux19| ... | ... +Mux20| Input Pin ( 64)| CLK_030 +Mux21| Mcel 3 13 ( 193)| cpu_est_1_ +Mux22| Mcel 6 5 ( 253)| inst_AS_000_DMA +Mux23| Mcel 6 2 ( 248)| SIZE_DMA_0_ +Mux24| Input Pin ( 86)| RST +Mux25| ... | ... +Mux26| IOPin 4 1 ( 42)| AS_000 +Mux27| IOPin 3 4 ( 31)| LDS_000 +Mux28| Mcel 1 5 ( 133)| inst_nEXP_SPACE_D0 +Mux29| ... | ... +Mux30| Mcel 5 1 ( 223)| RESET_DLY_3_ +Mux31| Mcel 5 12 ( 239)| RESET_DLY_4_ +Mux32| Mcel 5 8 ( 233)| CLK_OUT_PRE_Dreg +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 7] > Macrocell (MCell) Cluster Assignments +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ +--- Macrocell PT Cluster Size + | Sync/Async-------+ | | | Cluster to Mcell Assignment + | Node Fixed(*)----+ | | | | | +- XOR PT Size + | Sig Type-+ | | | | | | | XOR to Mcell Assignment + | Signal Name | | | | | | | | | +_|_________________|__|__|___|_____|__|______|___|__________|______________ + 0| RW_000| IO| | S | 3 | 4 to [ 0]| 1 XOR free + 1| SIZE_1_| IO| | S | 1 | 4 free | 1 XOR to [ 1] for 1 PT sig + 2|CLK_000_N_SYNC_10_|NOD| | S | 1 | 4 free | 1 XOR to [ 2] for 1 PT sig + 3| | ? | | S | | 4 free | 1 XOR free + 4| BGACK_030| IO| | S | 2 | 4 free | 1 XOR free + 5| FPU_CS|OUT| | S | 1 | 4 to [ 4]| 1 XOR to [ 5] for 1 PT sig + 6|inst_BGACK_030_INT_D|NOD| | S | 1 | 4 free | 1 XOR to [ 6] for 1 PT sig + 7| | ? | | S | | 4 free | 1 XOR free + 8| AS_030| IO| | S | 1 | 4 free | 1 XOR to [ 8] for 1 PT sig + 9|inst_AS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [ 9] for 1 PT sig +10|inst_DS_030_D0|NOD| | S | 1 | 4 free | 1 XOR to [10] for 1 PT sig +11| | ? | | S | | 4 free | 1 XOR free +12| DSACK1| IO| | S | 4 | 4 to [12]| 1 XOR free +13|inst_AS_030_000_SYNC|NOD| | S | 6 | 4 to [13]| 1 XOR to [13] as logic PT +14| | ? | | S | | 4 to [13]| 1 XOR free +15| | ? | | S | | 4 free | 1 XOR free +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 7] > Maximum PT Capacity +=========================================================================== + + Macrocell Number + | PT Requirements------ Logic XOR+ + | Sync/Async-------+ | | + | Node Fixed(*)----+ | | | + | Sig Type-+ | | | | + | Signal Name | | | | | Maximum PT Capacity +_|_________________|__|__|___|_____|_______________________________________ + 0| RW_000| IO| | S | 3 |=> can support up to [ 13] logic PT(s) + 1| SIZE_1_| IO| | S | 1 |=> can support up to [ 14] logic PT(s) + 2|CLK_000_N_SYNC_10_|NOD| | S | 1 |=> can support up to [ 19] logic PT(s) + 3| | ? | | S | |=> can support up to [ 14] logic PT(s) + 4| BGACK_030| IO| | S | 2 |=> can support up to [ 18] logic PT(s) + 5| FPU_CS|OUT| | S | 1 |=> can support up to [ 15] logic PT(s) + 6|inst_BGACK_030_INT_D|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) + 7| | ? | | S | |=> can support up to [ 17] logic PT(s) + 8| AS_030| IO| | S | 1 |=> can support up to [ 18] logic PT(s) + 9|inst_AS_030_D0|NOD| | S | 1 |=> can support up to [ 18] logic PT(s) +10|inst_DS_030_D0|NOD| | S | 1 |=> can support up to [ 14] logic PT(s) +11| | ? | | S | |=> can support up to [ 9] logic PT(s) +12| DSACK1| IO| | S | 4 |=> can support up to [ 10] logic PT(s) +13|inst_AS_030_000_SYNC|NOD| | S | 6 |=> can support up to [ 15] logic PT(s) +14| | ? | | S | |=> can support up to [ 6] logic PT(s) +15| | ? | | S | |=> can support up to [ 5] logic PT(s) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 7] > Node-Pin Assignments +=========================================================================== + + Macrocell Number + | Node Fixed(*)------+ + | Sig Type---+ | to | Block [ 7] IO Pin | Device Pin + | Signal Name | | pin | Numbers | Numbers +_|_________________|__|_____|____________________|________________________ + 0| RW_000| IO| | => |( 5) 6 7 0 |( 80) 79 78 85 + 1| SIZE_1_| IO| | => | 5 ( 6) 7 0 | 80 ( 79) 78 85 + 2|CLK_000_N_SYNC_10_|NOD| | => | 6 7 0 1 | 79 78 85 84 + 3| | | | => | 6 7 0 1 | 79 78 85 84 + 4| BGACK_030| IO| | => | 7 0 1 ( 2)| 78 85 84 ( 83) + 5| FPU_CS|OUT| | => |( 7) 0 1 2 |( 78) 85 84 83 + 6|inst_BGACK_030_INT_D|NOD| | => | 0 1 2 3 | 85 84 83 82 + 7| | | | => | 0 1 2 3 | 85 84 83 82 + 8| AS_030| IO| | => | 1 2 ( 3) 4 | 84 83 ( 82) 81 + 9|inst_AS_030_D0|NOD| | => | 1 2 3 4 | 84 83 82 81 +10|inst_DS_030_D0|NOD| | => | 2 3 4 5 | 83 82 81 80 +11| | | | => | 2 3 4 5 | 83 82 81 80 +12| DSACK1| IO| | => | 3 ( 4) 5 6 | 82 ( 81) 80 79 +13|inst_AS_030_000_SYNC|NOD| | => | 3 4 5 6 | 82 81 80 79 +14| | | | => | 4 5 6 7 | 81 80 79 78 +15| | | | => | 4 5 6 7 | 81 80 79 78 +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 7] > IO-to-Node Pin Mapping +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Node Destinations Via Output Matrix +_|_________________|__|___|_____|___________________________________________ + 0| A_23_|INP|*| 85| => | 0 1 2 3 4 5 6 7 + 1| A_22_|INP|*| 84| => | 2 3 4 5 6 7 8 9 + 2| BGACK_030| IO|*| 83| => | ( 4) 5 6 7 8 9 10 11 + 3| AS_030| IO|*| 82| => | 6 7 ( 8) 9 10 11 12 13 + 4| DSACK1| IO|*| 81| => | 8 9 10 11 (12) 13 14 15 + 5| RW_000| IO|*| 80| => | 10 11 12 13 14 15 ( 0) 1 + 6| SIZE_1_| IO|*| 79| => | 12 13 14 15 0 ( 1) 2 3 + 7| FPU_CS|OUT|*| 78| => | 14 15 0 1 2 3 4 ( 5) +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 7] > IO/Node and IO/Input Macrocell Pairing Table +=========================================================================== + +- Block IO Pin + | Device Pin No.--------+ + | Pin Fixed(*)----+ | + | Sig Type--+ | | | + | Signal Name | | | | Input Macrocell and Node Pairs +_|_________________|__|___|_____|__________________________________________ + 0| A_23_|INP|*| 85| => | Input macrocell [ -] + 1| A_22_|INP|*| 84| => | Input macrocell [ -] + 2| BGACK_030| IO|*| 83| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_BGACK_030] + 3| AS_030| IO|*| 82| => | Input macrocell [ -] + 4| DSACK1| IO|*| 81| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_DSACK1] + 5| RW_000| IO|*| 80| => | Input macrocell [ -] + | | | | | | IO paired w/ node [ RN_RW_000] + 6| SIZE_1_| IO|*| 79| => | Input macrocell [ -] + 7| FPU_CS|OUT|*| 78| => | Input macrocell [ -] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 7] > Input Multiplexer (IMX) Assignments +=========================================================================== + +----- IO pin/Input Register, or Macrocell +IMX No. | +---- Block IO Pin or Macrocell Number + | | | ABEL Node/ +-- Signal using the Pin or Macrocell + | | | Pin Number | +- Signal Fixed (*) to Pin/Mcell + | | | | Sig Type | | +- Feedback Required (*) +---|-------|----|---|---|----------|------|-|------------------------------ + 0 [IOpin 0 | 85|INP A_23_|*|*] + [RegIn 0 |270| -| | ] + [MCell 0 |269|NOD RN_RW_000| |*] paired w/[ RW_000] + [MCell 1 |271| IO SIZE_1_| | ] + + 1 [IOpin 1 | 84|INP A_22_|*|*] + [RegIn 1 |273| -| | ] + [MCell 2 |272|NOD CLK_000_N_SYNC_10_| |*] + [MCell 3 |274| -| | ] + + 2 [IOpin 2 | 83| IO BGACK_030|*| ] paired w/[ RN_BGACK_030] + [RegIn 2 |276| -| | ] + [MCell 4 |275|NOD RN_BGACK_030| |*] paired w/[ BGACK_030] + [MCell 5 |277|OUT FPU_CS| | ] + + 3 [IOpin 3 | 82| IO AS_030|*|*] + [RegIn 3 |279| -| | ] + [MCell 6 |278|NOD inst_BGACK_030_INT_D| |*] + [MCell 7 |280| -| | ] + + 4 [IOpin 4 | 81| IO DSACK1|*|*] paired w/[ RN_DSACK1] + [RegIn 4 |282| -| | ] + [MCell 8 |281| IO AS_030| | ] + [MCell 9 |283|NOD inst_AS_030_D0| |*] + + 5 [IOpin 5 | 80| IO RW_000|*|*] paired w/[ RN_RW_000] + [RegIn 5 |285| -| | ] + [MCell 10 |284|NOD inst_DS_030_D0| |*] + [MCell 11 |286| -| | ] + + 6 [IOpin 6 | 79| IO SIZE_1_|*|*] + [RegIn 6 |288| -| | ] + [MCell 12 |287|NOD RN_DSACK1| |*] paired w/[ DSACK1] + [MCell 13 |289|NOD inst_AS_030_000_SYNC| |*] + + 7 [IOpin 7 | 78|OUT FPU_CS|*| ] + [RegIn 7 |291| -| | ] + [MCell 14 |290| -| | ] + [MCell 15 |292| -| | ] +--------------------------------------------------------------------------- +=========================================================================== + < Block [ 7] > Logic Array Fan-in +=========================================================================== + +- Central Switch Matrix No. + | Src (ABEL Node/Pin#) Signal +--|--|--------------------|--------------------------------------------------- +Mux00| Mcel 7 4 ( 275)| RN_BGACK_030 +Mux01| IOPin 4 0 ( 41)| BERR +Mux02| Mcel 5 8 ( 233)| CLK_OUT_PRE_Dreg +Mux03| Mcel 6 5 ( 253)| inst_AS_000_DMA +Mux04| Mcel 2 12 ( 167)| SM_AMIGA_6_ +Mux05| Mcel 7 9 ( 283)| inst_AS_030_D0 +Mux06| IOPin 5 3 ( 57)| FC_0_ +Mux07| Mcel 7 13 ( 289)| inst_AS_030_000_SYNC +Mux08| IOPin 0 0 ( 91)| FPU_SENSE +Mux09| Mcel 0 1 ( 103)| CLK_000_N_SYNC_8_ +Mux10| Mcel 6 9 ( 259)| SIZE_DMA_1_ +Mux11| IOPin 6 6 ( 71)| RW +Mux12| IOPin 5 2 ( 58)| FC_1_ +Mux13| IOPin 5 1 ( 59)| A_17_ +Mux14| Mcel 5 4 ( 227)| SM_AMIGA_0_ +Mux15| Mcel 7 12 ( 287)| RN_DSACK1 +Mux16| Mcel 2 8 ( 161)| SM_AMIGA_1_ +Mux17| IOPin 0 4 ( 95)| A_18_ +Mux18| IOPin 0 7 ( 98)| DS_030 +Mux19| IOPin 7 3 ( 82)| AS_030 +Mux20| Input Pin ( 64)| CLK_030 +Mux21| Input Pin ( 86)| RST +Mux22| ... | ... +Mux23| Mcel 4 13 ( 217)| CLK_000_N_SYNC_9_ +Mux24| ... | ... +Mux25| Mcel 5 0 ( 221)| SM_AMIGA_7_ +Mux26| IOPin 0 5 ( 96)| A_16_ +Mux27| IOPin 0 6 ( 97)| A_19_ +Mux28| Mcel 1 5 ( 133)| inst_nEXP_SPACE_D0 +Mux29| Mcel 2 4 ( 155)| inst_CLK_000_PE +Mux30| Mcel 7 0 ( 269)| RN_RW_000 +Mux31| Mcel 6 2 ( 248)| SIZE_DMA_0_ +Mux32| IOPin 3 7 ( 28)| BGACK_000 +--------------------------------------------------------------------------- \ No newline at end of file diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt new file mode 100644 index 0000000..212fda6 --- /dev/null +++ b/Logic/68030_tk.rpt @@ -0,0 +1,1978 @@ +|--------------------------------------------| +|- ispLEVER Fitter Report File -| +|- Version 1.7.00.05.28.13 -| +|- (c)Copyright, Lattice Semiconductor 2002 -| +|--------------------------------------------| + + + + +Project_Summary +~~~~~~~~~~~~~~~ + +Project Name : 68030_tk +Project Path : C:\Users\Matze\Documents\GitHub\68030tk\Logic +Project Fitted on : Fri Oct 10 22:40:09 2014 + +Device : M4A5-128/64 +Package : 100TQFP +Speed : -10 +Partnumber : M4A5-128/64-10VC +Source Format : Pure_VHDL + + +// Project '68030_tk' was Fitted Successfully! // + + +Compilation_Times +~~~~~~~~~~~~~~~~~ +Reading/DRC 0 sec +Partition 0 sec +Place 0 sec +Route 0 sec +Jedec/Report generation 0 sec + -------- +Fitter 00:00:00 + + +Design_Summary +~~~~~~~~~~~~~~ + Total Input Pins : 31 + Total Output Pins : 17 + Total Bidir I/O Pins : 13 + Total Flip-Flops : 80 + Total Product Terms : 181 + Total Reserved Pins : 0 + Total Reserved Blocks : 0 + + +Device_Resource_Summary +~~~~~~~~~~~~~~~~~~~~~~~ + Total + Available Used Available Utilization +Dedicated Pins + Input-Only Pins 2 2 0 --> 100% + Clock/Input Pins 4 4 0 --> 100% +I/O Pins 64 55 9 --> 85% +Logic Macrocells 128 98 30 --> 76% + Input Registers 64 0 64 --> 0% + Unusable Macrocells .. 0 .. + +CSM Outputs/Total Block Inputs 264 227 37 --> 85% +Logical Product Terms 640 192 448 --> 30% +Product Term Clusters 128 50 78 --> 39% + + +Blocks_Resource_Summary +~~~~~~~~~~~~~~~~~~~~~~~ + # of PT + I/O Inp Macrocells Macrocells logic clusters + Fanin Pins Reg Used Unusable available PTs available Pwr +--------------------------------------------------------------------------------- +Maximum 33 8 8 -- -- 16 80 16 - +--------------------------------------------------------------------------------- +Block A 23 8 0 11 0 5 26 9 Lo +Block B 28 8 0 12 0 4 18 10 Lo +Block C 26 7 0 12 0 4 29 7 Lo +Block D 31 8 0 14 0 2 28 10 Lo +Block E 32 4 0 10 0 6 13 14 Lo +Block F 28 5 0 15 0 1 32 6 Lo +Block G 28 7 0 13 0 3 24 11 Lo +Block H 31 8 0 11 0 5 22 11 Lo +--------------------------------------------------------------------------------- + + Four rightmost columns above reflect last status of the placement process. + Pwr (Power) : Hi = High + Lo = Low. + + +Optimizer_and_Fitter_Options +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Pin Assignment : Yes +Group Assignment : No +Pin Reservation : No (1) +Block Reservation : No + +@Ignore_Project_Constraints : + Pin Assignments : No + Keep Block Assignment -- + Keep Segment Assignment -- + Group Assignments : No + Macrocell Assignment : No + Keep Block Assignment -- + Keep Segment Assignment -- + +@Backannotate_Project_Constraints + Pin Assignments : No + Pin And Block Assignments : No + Pin, Macrocell and Block : No + +@Timing_Constraints : No + +@Global_Project_Optimization : + Balanced Partitioning : Yes + Spread Placement : Yes + + Note : + Pack Design : + Balanced Partitioning = No + Spread Placement = No + Spread Design : + Balanced Partitioning = Yes + Spread Placement = Yes + +@Logic_Synthesis : + Logic Reduction : Yes + Node Collapsing : Yes + D/T Synthesis : No + Clock Optimization : No + Input Register Optimization : Yes + XOR Synthesis : Yes + Max. P-Term for Collapsing : 16 + Max. P-Term for Splitting : 16 + Max. Equation Fanin : 32 + Keep Xor : Yes + +@Utilization_options + Max. % of macrocells used : 100 + Max. % of block inputs used : 100 + Max. % of segment lines used : --- + Max. % of macrocells used : --- + + +@Import_Source_Constraint_Option No + +@Zero_Hold_Time Yes + +@Pull_up Yes + +@User_Signature #H0 + +@Output_Slew_Rate Default = Slow(2) + +@Power Default = High(2) + + +Device Options: + 1 : Reserved unused I/Os can be independently driven to Low or High, and does not + follow the drive level set for the Global Configure Unused I/O Option. + 2 : For user-specified constraints on individual signals, refer to the Output, + Bidir and Burried Signal Lists. + + + + +Pinout_Listing +~~~~~~~~~~~~~~ + | Pin |Blk |Assigned| +Pin No| Type |Pad |Pin | Signal name +--------------------------------------------------------------- + 1 | GND | | | + 2 | JTAG | | | + 3 | I_O | B7 | * |RESET +4 | I_O | B6 | * |A_31_ +5 | I_O | B5 | * |A_30_ +6 | I_O | B4 | * |A_29_ +7 | I_O | B3 | * |IPL_030_1_ +8 | I_O | B2 | * |IPL_030_0_ +9 | I_O | B1 | * |IPL_030_2_ +10 | I_O | B0 | * |CLK_EXP +11 | CkIn | | * |CLK_000 +12 | Vcc | | | +13 | GND | | | +14 | CkIn | | * |nEXP_SPACE +15 | I_O | C0 | * |A_28_ +16 | I_O | C1 | * |A_27_ +17 | I_O | C2 | * |A_26_ +18 | I_O | C3 | * |A_25_ +19 | I_O | C4 | * |A_24_ +20 | I_O | C5 | * |AMIGA_BUS_ENABLE_LOW +21 | I_O | C6 | * |BG_030 +22 | I_O | C7 | | +23 | JTAG | | | +24 | JTAG | | | +25 | GND | | | +26 | GND | | | +27 | GND | | | +28 | I_O | D7 | * |BGACK_000 +29 | I_O | D6 | * |BG_000 +30 | I_O | D5 | * |DTACK +31 | I_O | D4 | * |LDS_000 +32 | I_O | D3 | * |UDS_000 +33 | I_O | D2 | * |AMIGA_ADDR_ENABLE +34 | I_O | D1 | * |AMIGA_BUS_ENABLE_HIGH +35 | I_O | D0 | * |VMA +36 | Inp | | * |VPA +37 | Vcc | | | +38 | GND | | | +39 | GND | | | +40 | Vcc | | | +41 | I_O | E0 | * |BERR +42 | I_O | E1 | * |AS_000 +43 | I_O | E2 | | +44 | I_O | E3 | | +45 | I_O | E4 | | +46 | I_O | E5 | | +47 | I_O | E6 | * |CIIN +48 | I_O | E7 | * |AMIGA_BUS_DATA_DIR +49 | GND | | | +50 | GND | | | +51 | GND | | | +52 | JTAG | | | +53 | I_O | F7 | | +54 | I_O | F6 | | +55 | I_O | F5 | | +56 | I_O | F4 | * |IPL_1_ +57 | I_O | F3 | * |FC_0_ +58 | I_O | F2 | * |FC_1_ +59 | I_O | F1 | * |A_17_ +60 | I_O | F0 | * |A1 +61 | CkIn | | * |CLK_OSZI +62 | Vcc | | | +63 | GND | | | +64 | CkIn | | * |CLK_030 +65 | I_O | G0 | * |CLK_DIV_OUT +66 | I_O | G1 | * |E +67 | I_O | G2 | * |IPL_0_ +68 | I_O | G3 | * |IPL_2_ +69 | I_O | G4 | * |A0 +70 | I_O | G5 | * |SIZE_0_ +71 | I_O | G6 | * |RW +72 | I_O | G7 | | +73 | JTAG | | | +74 | JTAG | | | +75 | GND | | | +76 | GND | | | +77 | GND | | | +78 | I_O | H7 | * |FPU_CS +79 | I_O | H6 | * |SIZE_1_ +80 | I_O | H5 | * |RW_000 +81 | I_O | H4 | * |DSACK1 +82 | I_O | H3 | * |AS_030 +83 | I_O | H2 | * |BGACK_030 +84 | I_O | H1 | * |A_22_ +85 | I_O | H0 | * |A_23_ +86 | Inp | | * |RST +87 | Vcc | | | +88 | GND | | | +89 | GND | | | +90 | Vcc | | | +91 | I_O | A0 | * |FPU_SENSE +92 | I_O | A1 | * |AVEC +93 | I_O | A2 | * |A_20_ +94 | I_O | A3 | * |A_21_ +95 | I_O | A4 | * |A_18_ +96 | I_O | A5 | * |A_16_ +97 | I_O | A6 | * |A_19_ +98 | I_O | A7 | * |DS_030 +99 | GND | | | +100 | GND | | | + +--------------------------------------------------------------------------- + + Blk Pad : This notation refers to the Block I/O pad number in the device. + Assigned Pin : user or dedicated input assignment (E.g. Clock pins). + Pin Type : + CkIn : Dedicated input or clock pin + CLK : Dedicated clock pin + INP : Dedicated input pin + JTAG : JTAG Control and test pin + NC : No connected + + + +Input_Signal_List +~~~~~~~~~~~~~~~~~ + P R + Pin r e O Input +Pin Blk PTs Type e s E Fanout Pwr Slew Signal +---------------------------------------------------------------------- + 60 F . I/O A------- Low Slow A1 + 96 A . I/O ----E--H Low Slow A_16_ + 59 F . I/O ----E--H Low Slow A_17_ + 95 A . I/O ----E--H Low Slow A_18_ + 97 A . I/O ----E--H Low Slow A_19_ + 93 A . I/O ----E--- Low Slow A_20_ + 94 A . I/O ----E--- Low Slow A_21_ + 84 H . I/O ----E--- Low Slow A_22_ + 85 H . I/O ----E--- Low Slow A_23_ + 19 C . I/O ----E--- Low Slow A_24_ + 18 C . I/O ----E--- Low Slow A_25_ + 17 C . I/O ----E--- Low Slow A_26_ + 16 C . I/O ----E--- Low Slow A_27_ + 15 C . I/O ----E--- Low Slow A_28_ + 6 B . I/O ----E--- Low Slow A_29_ + 5 B . I/O ----E--- Low Slow A_30_ + 4 B . I/O ----E--- Low Slow A_31_ + 28 D . I/O ----E--H Low Slow BGACK_000 + 21 C . I/O ---D---- Low Slow BG_030 + 57 F . I/O ----E--H Low Slow FC_0_ + 58 F . I/O ----E--H Low Slow FC_1_ + 91 A . I/O ----E--H Low Slow FPU_SENSE + 67 G . I/O -B------ Low Slow IPL_0_ + 56 F . I/O -B------ Low Slow IPL_1_ + 68 G . I/O -B------ Low Slow IPL_2_ + 11 . . Ck/I ---D---- - Slow CLK_000 + 14 . . Ck/I -B------ - Slow nEXP_SPACE + 36 . . Ded -----F-- - Slow VPA + 61 . . Ck/I ABCDEFGH - Slow CLK_OSZI + 64 . . Ck/I A-----GH - Slow CLK_030 + 86 . . Ded ABCD-FGH - Slow RST +---------------------------------------------------------------------- + + Power : Hi = High + MH = Medium High + ML = Medium Low + Lo = Low + + + +Output_Signal_List +~~~~~~~~~~~~~~~~~~ + P R + Pin r e O Output +Pin Blk PTs Type e s E Fanout Pwr Slew Signal +---------------------------------------------------------------------- + 33 D 3 DFF * -------- Low Fast AMIGA_ADDR_ENABLE + 48 E 2 COM -------- Low Fast AMIGA_BUS_DATA_DIR + 34 D 1 COM -------- Low Fast AMIGA_BUS_ENABLE_HIGH + 20 C 1 COM -------- Low Fast AMIGA_BUS_ENABLE_LOW + 92 A 1 COM -------- Low Fast AVEC + 83 H 2 DFF * -------- Low Fast BGACK_030 + 29 D 2 DFF * -------- Low Fast BG_000 + 47 E 1 COM -------- Low Fast CIIN + 65 G 1 COM -------- Low Fast CLK_DIV_OUT + 10 B 1 COM -------- Low Fast CLK_EXP + 66 G 3 DFF -------- Low Slow E + 78 H 1 COM -------- Low Fast FPU_CS + 8 B 2 DFF * -------- Low Fast IPL_030_0_ + 7 B 2 DFF * -------- Low Fast IPL_030_1_ + 9 B 2 DFF * -------- Low Fast IPL_030_2_ + 3 B 2 DFF * -------- Low Fast RESET + 35 D 3 DFF * -------- Low Slow VMA +---------------------------------------------------------------------- + + Power : Hi = High + MH = Medium High + ML = Medium Low + Lo = Low + + + +Bidir_Signal_List +~~~~~~~~~~~~~~~~~ + P R + Pin r e O Bidir +Pin Blk PTs Type e s E Fanout Pwr Slew Signal +---------------------------------------------------------------------- + 69 G 1 DFF * A------- Low Fast A0 + 42 E 1 COM A---E-G- Low Fast AS_000 + 82 H 1 COM ----E--H Low Fast AS_030 + 41 E 1 COM --C--F-H Low Fast BERR + 81 H 4 DFF * ---D---- Low Fast DSACK1 + 98 A 7 DFF * ---D---H Low Fast DS_030 + 30 D 1 COM ---D---- Low Fast DTACK + 31 D 1 COM A-----G- Low Fast LDS_000 + 71 G 4 DFF * --C----H Low Fast RW + 80 H 3 DFF * A---E-G- Low Fast RW_000 + 70 G 1 COM A------- Low Fast SIZE_0_ + 79 H 1 COM A------- Low Fast SIZE_1_ + 32 D 1 COM A-----G- Low Fast UDS_000 +---------------------------------------------------------------------- + + Power : Hi = High + MH = Medium High + ML = Medium Low + Lo = Low + + + +Buried_Signal_List +~~~~~~~~~~~~~~~~~~ + P R + Pin r e O Node +#Mc Blk PTs Type e s E Fanout Pwr Slew Signal +---------------------------------------------------------------------- + E9 E 3 COM ----E--- Low Slow CIIN_0 + E2 E 1 DFF ------G- Low Slow CLK_000_N_SYNC_0_ + H2 H 1 DFF A------- Low Slow CLK_000_N_SYNC_10_ + A10 A 1 DFF ----E--- Low Slow CLK_000_N_SYNC_11_ + G10 G 1 DFF -B------ Low Slow CLK_000_N_SYNC_1_ + B2 B 1 DFF ------G- Low Slow CLK_000_N_SYNC_2_ + G6 G 1 DFF ---D---- Low Slow CLK_000_N_SYNC_3_ + D3 D 1 DFF -B------ Low Slow CLK_000_N_SYNC_4_ + B13 B 1 DFF A------- Low Slow CLK_000_N_SYNC_5_ + A2 A 1 DFF -----F-- Low Slow CLK_000_N_SYNC_6_ + F14 F 1 DFF A------- Low Slow CLK_000_N_SYNC_7_ + A1 A 1 DFF ----E--H Low Slow CLK_000_N_SYNC_8_ + E13 E 1 DFF -------H Low Slow CLK_000_N_SYNC_9_ + E6 E 1 DFF -B------ Low Slow CLK_000_P_SYNC_0_ + B10 B 1 DFF A------- Low Slow CLK_000_P_SYNC_1_ + A6 A 1 DFF ------G- Low Slow CLK_000_P_SYNC_2_ + G14 G 1 DFF -B------ Low Slow CLK_000_P_SYNC_3_ + B6 B 1 DFF --C----- Low Slow CLK_000_P_SYNC_4_ + C14 C 1 DFF --C----- Low Slow CLK_000_P_SYNC_5_ + C10 C 1 DFF --C----- Low Slow CLK_000_P_SYNC_6_ + C6 C 1 DFF -----F-- Low Slow CLK_000_P_SYNC_7_ + F3 F 1 DFF ------G- Low Slow CLK_000_P_SYNC_8_ + G3 G 1 DFF --C----- Low Slow CLK_000_P_SYNC_9_ + F8 F 1 DFF -B----GH Low Slow CLK_OUT_PRE_Dreg + F13 F 1 DFF * -B---FG- Low Slow RESET_DLY_0_ + F9 F 1 DFF * -B---FG- Low Slow RESET_DLY_1_ + F5 F 1 DFF * -B---FG- Low Slow RESET_DLY_2_ + F1 F 1 DFF * -B---FG- Low Slow RESET_DLY_3_ + F12 F 1 DFF * -B---FG- Low Slow RESET_DLY_4_ + G13 G 1 DFF * -B----G- Low Slow RESET_DLY_5_ + B9 B 1 DFF * -B------ Low Slow RESET_DLY_6_ + B14 B 1 DFF * -B------ Low Slow RESET_DLY_7_ + D5 D 3 DFF * ---D---- Low - RN_AMIGA_ADDR_ENABLE --> AMIGA_ADDR_ENABLE + H4 H 2 DFF * A-CDE-GH Low - RN_BGACK_030 --> BGACK_030 + D1 D 2 DFF * ---D---- Low - RN_BG_000 --> BG_000 + H12 H 4 DFF * -------H Low - RN_DSACK1 --> DSACK1 + A0 A 7 DFF * A------- Low - RN_DS_030 --> DS_030 + G4 G 3 DFF -B-D-FG- Low - RN_E --> E + B8 B 2 DFF * -B------ Low - RN_IPL_030_0_ --> IPL_030_0_ + B12 B 2 DFF * -B------ Low - RN_IPL_030_1_ --> IPL_030_1_ + B4 B 2 DFF * -B------ Low - RN_IPL_030_2_ --> IPL_030_2_ + B0 B 2 DFF * -B------ Low - RN_RESET --> RESET + G0 G 4 DFF * ------G- Low - RN_RW --> RW + H0 H 3 DFF * -------H Low - RN_RW_000 --> RW_000 + D4 D 3 DFF * ---D-F-- Low - RN_VMA --> VMA + G2 G 1 DFF * ------GH Low Slow SIZE_DMA_0_ + G9 G 2 DFF * ------GH Low Slow SIZE_DMA_1_ + F4 F 2 DFF * --C--F-H Low Slow SM_AMIGA_0_ + C8 C 2 DFF * --C--F-H Low Slow SM_AMIGA_1_ + F6 F 3 DFF * --C--F-- Low Slow SM_AMIGA_2_ + F2 F 6 DFF * --C--F-- Low Slow SM_AMIGA_3_ + C5 C 2 DFF * --C--F-- Low Slow SM_AMIGA_4_ + C2 C 2 DFF * --C----- Low Slow SM_AMIGA_5_ + C12 C 2 DFF * A-C----H Low Slow SM_AMIGA_6_ + F0 F 4 DFF * --CD---H Low Slow SM_AMIGA_7_ + D6 D 2 DFF -B-D-FG- Low Slow cpu_est_0_ + D13 D 5 DFF -B-D-FG- Low Slow cpu_est_1_ + D2 D 4 DFF -B-D-FG- Low Slow cpu_est_2_ + A13 A 2 DFF * ---D---- Low Slow inst_AMIGA_BUS_ENABLE_DMA_HIGH + A9 A 2 DFF * --C----- Low Slow inst_AMIGA_BUS_ENABLE_DMA_LOW + G5 G 4 DFF * A--D--GH Low Slow inst_AS_000_DMA + C9 C 2 DFF * --C-E--- Low Slow inst_AS_000_INT + H13 H 6 DFF * --CD---H Low Slow inst_AS_030_000_SYNC + H9 H 1 DFF * --CDE--H Low Slow inst_AS_030_D0 + H6 H 1 DFF * ---D---- Low Slow inst_BGACK_030_INT_D + D14 D 1 DFF --CDE--- Low Slow inst_CLK_000_D0 + E5 E 1 DFF --CDE--- Low Slow inst_CLK_000_D1 + E8 E 1 DFF -BCD-F-- Low Slow inst_CLK_000_NE + D10 D 1 DFF -B-D-FG- Low Slow inst_CLK_000_NE_D0 + C4 C 1 DFF --CD-F-H Low Slow inst_CLK_000_PE + A5 A 4 DFF * A------- Low Slow inst_CLK_030_H + F7 F 1 DFF -----F-- Low Slow inst_CLK_OUT_PRE + F11 F 1 DFF -----F-- Low Slow inst_CLK_OUT_PRE_50 + C1 C 3 DFF * --CD---- Low Slow inst_DS_000_ENABLE + H10 H 1 DFF * A------- Low Slow inst_DS_030_D0 + D7 D 1 DFF * -----F-- Low Slow inst_DTACK_D0 + A8 A 3 DFF * A--D---- Low Slow inst_LDS_000_INT + A12 A 3 DFF * A--D---- Low Slow inst_UDS_000_INT + F10 F 1 DFF * ---D-F-- Low Slow inst_VPA_D + B5 B 1 DFF * A-CDE-GH Low Slow inst_nEXP_SPACE_D0 + C13 C 11 COM -----F-- Low Slow sm_amiga_ns_0_3_0__n +---------------------------------------------------------------------- + + Power : Hi = High + MH = Medium High + ML = Medium Low + Lo = Low + + + + +Signals_Fanout_List +~~~~~~~~~~~~~~~~~~~ +Signal Source : Fanout List +----------------------------------------------------------------------------- + A_27_{ D}: CIIN{ E} CIIN_0{ E} + A_26_{ D}: CIIN{ E} CIIN_0{ E} + SIZE_1_{ I}:inst_LDS_000_INT{ A} + A_25_{ D}: CIIN{ E} CIIN_0{ E} + A_24_{ D}: CIIN{ E} CIIN_0{ E} + A_31_{ C}: CIIN{ E} CIIN_0{ E} + A_23_{ I}: CIIN{ E} CIIN_0{ E} + A_22_{ I}: CIIN{ E} CIIN_0{ E} + A_21_{ B}: CIIN{ E} CIIN_0{ E} + A_20_{ B}: CIIN{ E} CIIN_0{ E} + IPL_2_{ H}: IPL_030_2_{ B} + A_19_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_18_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + FC_1_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A_17_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + AS_030{ I}: AS_000{ E} BERR{ E} FPU_CS{ H} + : inst_AS_030_D0{ H} CIIN_0{ E} + A_16_{ B}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + AS_000{ F}:AMIGA_BUS_DATA_DIR{ E} DS_030{ A} A0{ G} + : RW{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ A} + :inst_AS_000_DMA{ G} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} + : inst_CLK_030_H{ A} + IPL_1_{ G}: IPL_030_1_{ B} + UDS_000{ E}: DS_030{ A} A0{ G} RW{ G} + :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ A}inst_AS_000_DMA{ G} + : SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} inst_CLK_030_H{ A} + IPL_0_{ H}: IPL_030_0_{ B} + LDS_000{ E}: DS_030{ A} A0{ G} RW{ G} + :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ A}inst_AS_000_DMA{ G} + : SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} inst_CLK_030_H{ A} + FC_0_{ G}: BERR{ E} FPU_CS{ H}inst_AS_030_000_SYNC{ H} + A1{ G}:inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ A} + nEXP_SPACE{. }:inst_nEXP_SPACE_D0{ B} + BERR{ F}: RW_000{ H} DSACK1{ H}inst_AS_000_INT{ C} + :inst_AS_030_000_SYNC{ H}sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_7_{ F} + : SM_AMIGA_6_{ C} SM_AMIGA_4_{ C} SM_AMIGA_0_{ F} + :inst_DS_000_ENABLE{ C} SM_AMIGA_1_{ C} SM_AMIGA_5_{ C} + : SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + BG_030{ D}: BG_000{ D} + BGACK_000{ E}: BERR{ E} FPU_CS{ H} BGACK_030{ H} + :inst_AS_030_000_SYNC{ H} + CLK_030{. }: DS_030{ A} DSACK1{ H} RW{ G} + :inst_AS_000_DMA{ G} inst_CLK_030_H{ A} + CLK_000{. }:inst_CLK_000_D0{ D} + FPU_SENSE{ B}: BERR{ E} FPU_CS{ H} + DTACK{ E}: inst_DTACK_D0{ D} + VPA{. }: inst_VPA_D{ F} + RST{. }: IPL_030_2_{ B} IPL_030_1_{ B} RW_000{ H} + : IPL_030_0_{ B} DS_030{ A} A0{ G} + : BG_000{ D} BGACK_030{ H} DSACK1{ H} + : VMA{ D} RESET{ B} RW{ G} + :AMIGA_ADDR_ENABLE{ D}inst_AS_000_INT{ C}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A} + :inst_AMIGA_BUS_ENABLE_DMA_LOW{ A} inst_AS_030_D0{ H}inst_nEXP_SPACE_D0{ B} + : inst_DS_030_D0{ H}inst_AS_030_000_SYNC{ H}inst_BGACK_030_INT_D{ H} + :inst_AS_000_DMA{ G} SIZE_DMA_0_{ G} SIZE_DMA_1_{ G} + : inst_VPA_D{ F}inst_UDS_000_INT{ A}inst_LDS_000_INT{ A} + : inst_DTACK_D0{ D} RESET_DLY_7_{ B} SM_AMIGA_7_{ F} + : SM_AMIGA_6_{ C} SM_AMIGA_4_{ C} SM_AMIGA_0_{ F} + : inst_CLK_030_H{ A} RESET_DLY_0_{ F} RESET_DLY_1_{ F} + : RESET_DLY_2_{ F} RESET_DLY_3_{ F} RESET_DLY_4_{ F} + : RESET_DLY_5_{ G} RESET_DLY_6_{ B}inst_DS_000_ENABLE{ C} + : SM_AMIGA_1_{ C} SM_AMIGA_5_{ C} SM_AMIGA_3_{ F} + : SM_AMIGA_2_{ F} + SIZE_0_{ H}:inst_LDS_000_INT{ A} + A_30_{ C}: CIIN{ E} CIIN_0{ E} + A_29_{ C}: CIIN{ E} CIIN_0{ E} + A_28_{ D}: CIIN{ E} CIIN_0{ E} +RN_IPL_030_2_{ C}: IPL_030_2_{ B} +RN_IPL_030_1_{ C}: IPL_030_1_{ B} + RW_000{ I}:AMIGA_BUS_DATA_DIR{ E} DS_030{ A} RW{ G} + RN_RW_000{ I}: RW_000{ H} +RN_IPL_030_0_{ C}: IPL_030_0_{ B} + DS_030{ B}: UDS_000{ D} LDS_000{ D} inst_DS_030_D0{ H} + RN_DS_030{ B}: DS_030{ A} + A0{ H}:inst_UDS_000_INT{ A}inst_LDS_000_INT{ A} + RN_BG_000{ E}: BG_000{ D} +RN_BGACK_030{ I}: SIZE_1_{ H} AS_030{ H} AS_000{ E} + : UDS_000{ D} LDS_000{ D} DTACK{ D} + :AMIGA_BUS_DATA_DIR{ E}AMIGA_BUS_ENABLE_LOW{ C}AMIGA_BUS_ENABLE_HIGH{ D} + : SIZE_0_{ G} RW_000{ H} DS_030{ A} + : A0{ G} BGACK_030{ H} RW{ G} + :AMIGA_ADDR_ENABLE{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ A}inst_AMIGA_BUS_ENABLE_DMA_LOW{ A} + :inst_BGACK_030_INT_D{ H}inst_AS_000_DMA{ G} SIZE_DMA_0_{ G} + : SIZE_DMA_1_{ G} inst_CLK_030_H{ A} + DSACK1{ I}: DTACK{ D} + RN_DSACK1{ I}: DSACK1{ H} + RN_E{ H}: E{ G} VMA{ D} cpu_est_1_{ D} + : RESET_DLY_7_{ B} SM_AMIGA_7_{ F} cpu_est_2_{ D} + : RESET_DLY_0_{ F} RESET_DLY_1_{ F} RESET_DLY_2_{ F} + : RESET_DLY_3_{ F} RESET_DLY_4_{ F} RESET_DLY_5_{ G} + : RESET_DLY_6_{ B} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} + RN_VMA{ E}: VMA{ D} SM_AMIGA_7_{ F} SM_AMIGA_3_{ F} + : SM_AMIGA_2_{ F} + RN_RESET{ C}: RESET{ B} + RW{ H}: RW_000{ H}inst_DS_000_ENABLE{ C} + RN_RW{ H}: RW{ G} +RN_AMIGA_ADDR_ENABLE{ E}:AMIGA_ADDR_ENABLE{ D} + cpu_est_0_{ E}: E{ G} VMA{ D} cpu_est_0_{ D} + : cpu_est_1_{ D} RESET_DLY_7_{ B} SM_AMIGA_7_{ F} + : cpu_est_2_{ D} RESET_DLY_0_{ F} RESET_DLY_1_{ F} + : RESET_DLY_2_{ F} RESET_DLY_3_{ F} RESET_DLY_4_{ F} + : RESET_DLY_5_{ G} RESET_DLY_6_{ B} SM_AMIGA_3_{ F} + : SM_AMIGA_2_{ F} + cpu_est_1_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} + : RESET_DLY_7_{ B} SM_AMIGA_7_{ F} cpu_est_2_{ D} + : RESET_DLY_0_{ F} RESET_DLY_1_{ F} RESET_DLY_2_{ F} + : RESET_DLY_3_{ F} RESET_DLY_4_{ F} RESET_DLY_5_{ G} + : RESET_DLY_6_{ B} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} +inst_AS_000_INT{ D}: AS_000{ E}inst_AS_000_INT{ C} +inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}:AMIGA_BUS_ENABLE_HIGH{ D} +inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}:AMIGA_BUS_ENABLE_LOW{ C} +inst_AS_030_D0{ I}: CIIN{ E} RW_000{ H} BG_000{ D} + : DSACK1{ H}inst_AS_000_INT{ C}inst_AS_030_000_SYNC{ H} + :inst_DS_000_ENABLE{ C} CIIN_0{ E} +inst_nEXP_SPACE_D0{ C}: SIZE_1_{ H} AS_030{ H} DTACK{ D} + :AMIGA_BUS_DATA_DIR{ E} SIZE_0_{ G} DS_030{ A} + : A0{ G} BG_000{ D} DSACK1{ H} + :AMIGA_ADDR_ENABLE{ D}inst_AS_030_000_SYNC{ H}sm_amiga_ns_0_3_0__n{ C} + : SM_AMIGA_6_{ C} CIIN_0{ E} +inst_DS_030_D0{ I}:inst_UDS_000_INT{ A}inst_LDS_000_INT{ A} +inst_AS_030_000_SYNC{ I}:AMIGA_ADDR_ENABLE{ D}inst_AS_030_000_SYNC{ H}sm_amiga_ns_0_3_0__n{ C} + : SM_AMIGA_6_{ C} +inst_BGACK_030_INT_D{ I}:AMIGA_ADDR_ENABLE{ D} +inst_AS_000_DMA{ H}: SIZE_1_{ H} AS_030{ H} DTACK{ D} + : SIZE_0_{ G} DS_030{ A} A0{ G} + :inst_AS_000_DMA{ G} inst_CLK_030_H{ A} +SIZE_DMA_0_{ H}: SIZE_1_{ H} SIZE_0_{ G} +SIZE_DMA_1_{ H}: SIZE_1_{ H} SIZE_0_{ G} + inst_VPA_D{ G}: VMA{ D} SM_AMIGA_7_{ F} SM_AMIGA_3_{ F} + : SM_AMIGA_2_{ F} +inst_UDS_000_INT{ B}: UDS_000{ D}inst_UDS_000_INT{ A} +inst_LDS_000_INT{ B}: LDS_000{ D}inst_LDS_000_INT{ A} +inst_DTACK_D0{ E}: SM_AMIGA_7_{ F} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} +RESET_DLY_7_{ C}: RESET{ B} RESET_DLY_7_{ B} +inst_CLK_OUT_PRE_50{ G}:inst_CLK_OUT_PRE_50{ F}inst_CLK_OUT_PRE{ F} +inst_CLK_000_D1{ F}:AMIGA_ADDR_ENABLE{ D}sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_6_{ C} + :CLK_000_P_SYNC_0_{ E}CLK_000_N_SYNC_0_{ E} +inst_CLK_000_D0{ E}: BG_000{ D}AMIGA_ADDR_ENABLE{ D}inst_CLK_000_D1{ E} + :sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_6_{ C}CLK_000_P_SYNC_0_{ E} + :CLK_000_N_SYNC_0_{ E} +sm_amiga_ns_0_3_0__n{ D}: SM_AMIGA_7_{ F} +SM_AMIGA_7_{ G}: RW_000{ H}AMIGA_ADDR_ENABLE{ D}inst_AS_030_000_SYNC{ H} + : SM_AMIGA_6_{ C} +inst_CLK_OUT_PRE{ G}:CLK_OUT_PRE_Dreg{ F} +inst_CLK_000_PE{ D}: RW_000{ H} BGACK_030{ H} VMA{ D} + :inst_AS_000_INT{ C}sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_6_{ C} + : SM_AMIGA_4_{ C} SM_AMIGA_0_{ F}inst_DS_000_ENABLE{ C} + : SM_AMIGA_1_{ C} SM_AMIGA_5_{ C} SM_AMIGA_3_{ F} + : SM_AMIGA_2_{ F} +CLK_000_P_SYNC_9_{ H}:inst_CLK_000_PE{ C} +inst_CLK_000_NE{ F}: IPL_030_2_{ B} IPL_030_1_{ B} IPL_030_0_{ B} + : VMA{ D}sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_7_{ F} + :inst_CLK_000_NE_D0{ D} SM_AMIGA_4_{ C} SM_AMIGA_0_{ F} + : SM_AMIGA_1_{ C} SM_AMIGA_5_{ C} SM_AMIGA_3_{ F} + : SM_AMIGA_2_{ F} +CLK_000_N_SYNC_11_{ B}:inst_CLK_000_NE{ E} + cpu_est_2_{ E}: E{ G} VMA{ D} cpu_est_1_{ D} + : RESET_DLY_7_{ B} SM_AMIGA_7_{ F} cpu_est_2_{ D} + : RESET_DLY_0_{ F} RESET_DLY_1_{ F} RESET_DLY_2_{ F} + : RESET_DLY_3_{ F} RESET_DLY_4_{ F} RESET_DLY_5_{ G} + : RESET_DLY_6_{ B} SM_AMIGA_3_{ F} SM_AMIGA_2_{ F} +inst_CLK_000_NE_D0{ E}: E{ G} cpu_est_0_{ D} cpu_est_1_{ D} + : RESET_DLY_7_{ B} cpu_est_2_{ D} RESET_DLY_0_{ F} + : RESET_DLY_1_{ F} RESET_DLY_2_{ F} RESET_DLY_3_{ F} + : RESET_DLY_4_{ F} RESET_DLY_5_{ G} RESET_DLY_6_{ B} +SM_AMIGA_6_{ D}: RW_000{ H}inst_AS_000_INT{ C}inst_UDS_000_INT{ A} + :inst_LDS_000_INT{ A}sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_6_{ C} + :inst_DS_000_ENABLE{ C} SM_AMIGA_5_{ C} +SM_AMIGA_4_{ D}:sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_4_{ C}inst_DS_000_ENABLE{ C} + : SM_AMIGA_3_{ F} +SM_AMIGA_0_{ G}: RW_000{ H}sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_0_{ F} +inst_CLK_030_H{ B}: DS_030{ A} inst_CLK_030_H{ A} +CLK_000_P_SYNC_0_{ F}:CLK_000_P_SYNC_1_{ B} +CLK_000_P_SYNC_1_{ C}:CLK_000_P_SYNC_2_{ A} +CLK_000_P_SYNC_2_{ B}:CLK_000_P_SYNC_3_{ G} +CLK_000_P_SYNC_3_{ H}:CLK_000_P_SYNC_4_{ B} +CLK_000_P_SYNC_4_{ C}:CLK_000_P_SYNC_5_{ C} +CLK_000_P_SYNC_5_{ D}:CLK_000_P_SYNC_6_{ C} +CLK_000_P_SYNC_6_{ D}:CLK_000_P_SYNC_7_{ C} +CLK_000_P_SYNC_7_{ D}:CLK_000_P_SYNC_8_{ F} +CLK_000_P_SYNC_8_{ G}:CLK_000_P_SYNC_9_{ G} +CLK_000_N_SYNC_0_{ F}:CLK_000_N_SYNC_1_{ G} +CLK_000_N_SYNC_1_{ H}:CLK_000_N_SYNC_2_{ B} +CLK_000_N_SYNC_2_{ C}:CLK_000_N_SYNC_3_{ G} +CLK_000_N_SYNC_3_{ H}:CLK_000_N_SYNC_4_{ D} +CLK_000_N_SYNC_4_{ E}:CLK_000_N_SYNC_5_{ B} +CLK_000_N_SYNC_5_{ C}:CLK_000_N_SYNC_6_{ A} +CLK_000_N_SYNC_6_{ B}:CLK_000_N_SYNC_7_{ F} +CLK_000_N_SYNC_7_{ G}:CLK_000_N_SYNC_8_{ A} +CLK_000_N_SYNC_8_{ B}: DSACK1{ H}CLK_000_N_SYNC_9_{ E} +CLK_000_N_SYNC_9_{ F}: DSACK1{ H}CLK_000_N_SYNC_10_{ H} +CLK_000_N_SYNC_10_{ I}:CLK_000_N_SYNC_11_{ A} +RESET_DLY_0_{ G}: RESET{ B} RESET_DLY_7_{ B} RESET_DLY_0_{ F} + : RESET_DLY_1_{ F} RESET_DLY_2_{ F} RESET_DLY_3_{ F} + : RESET_DLY_4_{ F} RESET_DLY_5_{ G} RESET_DLY_6_{ B} +RESET_DLY_1_{ G}: RESET{ B} RESET_DLY_7_{ B} RESET_DLY_1_{ F} + : RESET_DLY_2_{ F} RESET_DLY_3_{ F} RESET_DLY_4_{ F} + : RESET_DLY_5_{ G} RESET_DLY_6_{ B} +RESET_DLY_2_{ G}: RESET{ B} RESET_DLY_7_{ B} RESET_DLY_2_{ F} + : RESET_DLY_3_{ F} RESET_DLY_4_{ F} RESET_DLY_5_{ G} + : RESET_DLY_6_{ B} +RESET_DLY_3_{ G}: RESET{ B} RESET_DLY_7_{ B} RESET_DLY_3_{ F} + : RESET_DLY_4_{ F} RESET_DLY_5_{ G} RESET_DLY_6_{ B} +RESET_DLY_4_{ G}: RESET{ B} RESET_DLY_7_{ B} RESET_DLY_4_{ F} + : RESET_DLY_5_{ G} RESET_DLY_6_{ B} +RESET_DLY_5_{ H}: RESET{ B} RESET_DLY_7_{ B} RESET_DLY_5_{ G} + : RESET_DLY_6_{ B} +RESET_DLY_6_{ C}: RESET{ B} RESET_DLY_7_{ B} RESET_DLY_6_{ B} +inst_DS_000_ENABLE{ D}: UDS_000{ D} LDS_000{ D}inst_DS_000_ENABLE{ C} +SM_AMIGA_1_{ D}: DSACK1{ H}sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_0_{ F} + : SM_AMIGA_1_{ C} +SM_AMIGA_5_{ D}:sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_4_{ C} SM_AMIGA_5_{ C} +SM_AMIGA_3_{ G}:sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_7_{ F} SM_AMIGA_3_{ F} + : SM_AMIGA_2_{ F} +SM_AMIGA_2_{ G}:sm_amiga_ns_0_3_0__n{ C} SM_AMIGA_1_{ C} SM_AMIGA_2_{ F} +CLK_OUT_PRE_Dreg{ G}: CLK_DIV_OUT{ G} CLK_EXP{ B} DSACK1{ H} + CIIN_0{ F}: CIIN{ E} +----------------------------------------------------------------------------- + + {.} : Indicates block location of signal + + +Set_Reset_Summary +~~~~~~~~~~~~~~~~~ + +Block A +block level set pt : !RST +block level reset pt : +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| * | S | BS | BR | DS_030 +| | | | | AVEC +| * | S | BS | BR | inst_LDS_000_INT +| * | S | BS | BR | inst_UDS_000_INT +| * | S | BR | BR | CLK_000_N_SYNC_8_ +| * | S | BS | BR | RN_DS_030 +| * | S | BR | BS | inst_CLK_030_H +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_LOW +| * | S | BS | BR | inst_AMIGA_BUS_ENABLE_DMA_HIGH +| * | S | BR | BR | CLK_000_N_SYNC_6_ +| * | S | BR | BR | CLK_000_P_SYNC_2_ +| * | S | BR | BR | CLK_000_N_SYNC_11_ +| | | | | A_19_ +| | | | | A_16_ +| | | | | A_18_ +| | | | | FPU_SENSE +| | | | | A_21_ +| | | | | A_20_ + + +Block B +block level set pt : +block level reset pt : !RST +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| * | S | BR | BS | IPL_030_2_ +| * | S | BR | BS | IPL_030_0_ +| * | S | BR | BS | IPL_030_1_ +| * | S | BS | BR | RESET +| | | | | CLK_EXP +| * | S | BR | BS | inst_nEXP_SPACE_D0 +| * | S | BS | BR | RN_RESET +| * | S | BR | BS | RN_IPL_030_0_ +| * | S | BR | BS | RN_IPL_030_1_ +| * | S | BR | BS | RN_IPL_030_2_ +| * | S | BS | BR | RESET_DLY_6_ +| * | S | BS | BS | CLK_000_N_SYNC_5_ +| * | S | BS | BS | CLK_000_N_SYNC_2_ +| * | S | BS | BS | CLK_000_P_SYNC_4_ +| * | S | BS | BS | CLK_000_P_SYNC_1_ +| * | S | BS | BR | RESET_DLY_7_ +| | | | | A_29_ +| | | | | A_30_ +| | | | | A_31_ + + +Block C +block level set pt : +block level reset pt : !RST +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| | | | | AMIGA_BUS_ENABLE_LOW +| * | S | BS | BS | inst_CLK_000_PE +| * | S | BS | BR | SM_AMIGA_1_ +| * | S | BS | BR | SM_AMIGA_6_ +| * | S | BS | BR | inst_DS_000_ENABLE +| * | S | BS | BR | SM_AMIGA_4_ +| * | S | BR | BS | inst_AS_000_INT +| | | | | sm_amiga_ns_0_3_0__n +| * | S | BS | BR | SM_AMIGA_5_ +| * | S | BS | BS | CLK_000_P_SYNC_7_ +| * | S | BS | BS | CLK_000_P_SYNC_6_ +| * | S | BS | BS | CLK_000_P_SYNC_5_ +| | | | | BG_030 +| | | | | A_24_ +| | | | | A_25_ +| | | | | A_26_ +| | | | | A_27_ +| | | | | A_28_ + + +Block D +block level set pt : !RST +block level reset pt : +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| | | | | UDS_000 +| | | | | LDS_000 +| | | | | DTACK +| * | S | BS | BR | VMA +| * | S | BS | BR | AMIGA_ADDR_ENABLE +| * | S | BS | BR | BG_000 +| | | | | AMIGA_BUS_ENABLE_HIGH +| * | S | BR | BR | cpu_est_1_ +| * | S | BR | BR | cpu_est_2_ +| * | S | BR | BR | cpu_est_0_ +| * | S | BR | BR | inst_CLK_000_NE_D0 +| * | S | BR | BR | inst_CLK_000_D0 +| * | S | BS | BR | RN_VMA +| * | S | BS | BR | RN_AMIGA_ADDR_ENABLE +| * | S | BS | BR | RN_BG_000 +| * | S | BR | BR | CLK_000_N_SYNC_4_ +| * | S | BS | BR | inst_DTACK_D0 +| | | | | BGACK_000 + + +Block E +block level set pt : +block level reset pt : +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| | | | | AS_000 +| | | | | BERR +| | | | | AMIGA_BUS_DATA_DIR +| | | | | CIIN +| * | S | BS | BR | inst_CLK_000_NE +| * | S | BS | BR | inst_CLK_000_D1 +| | | | | CIIN_0 +| * | S | BS | BR | CLK_000_N_SYNC_9_ +| * | S | BS | BR | CLK_000_N_SYNC_0_ +| * | S | BS | BR | CLK_000_P_SYNC_0_ + + +Block F +block level set pt : +block level reset pt : !RST +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| * | S | BR | BS | SM_AMIGA_7_ +| * | S | BS | BR | SM_AMIGA_0_ +| * | S | BS | BS | CLK_OUT_PRE_Dreg +| * | S | BS | BR | RESET_DLY_4_ +| * | S | BS | BR | RESET_DLY_3_ +| * | S | BS | BR | RESET_DLY_2_ +| * | S | BS | BR | RESET_DLY_1_ +| * | S | BS | BR | RESET_DLY_0_ +| * | S | BS | BR | SM_AMIGA_3_ +| * | S | BS | BR | SM_AMIGA_2_ +| * | S | BR | BS | inst_VPA_D +| * | S | BS | BS | CLK_000_N_SYNC_7_ +| * | S | BS | BS | CLK_000_P_SYNC_8_ +| * | S | BS | BS | inst_CLK_OUT_PRE +| * | S | BS | BS | inst_CLK_OUT_PRE_50 +| | | | | A_17_ +| | | | | FC_1_ +| | | | | FC_0_ +| | | | | A1 +| | | | | IPL_1_ + + +Block G +block level set pt : !RST +block level reset pt : +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| * | S | BS | BR | RW +| | | | | SIZE_0_ +| * | S | BS | BR | A0 +| * | S | BR | BR | E +| | | | | CLK_DIV_OUT +| * | S | BS | BR | inst_AS_000_DMA +| * | S | BR | BR | RN_E +| * | S | BS | BR | SIZE_DMA_1_ +| * | S | BR | BS | RESET_DLY_5_ +| * | S | BS | BR | SIZE_DMA_0_ +| * | S | BS | BR | RN_RW +| * | S | BR | BR | CLK_000_N_SYNC_3_ +| * | S | BR | BR | CLK_000_N_SYNC_1_ +| * | S | BR | BR | CLK_000_P_SYNC_3_ +| * | S | BR | BR | CLK_000_P_SYNC_9_ +| | | | | IPL_2_ +| | | | | IPL_0_ + + +Block H +block level set pt : !RST +block level reset pt : +Equations : +| | |Block|Block| Signal +| Reg |Mode |Set |Reset| Name ++-----+-----+-----+-----+------------------------ +| * | S | BS | BR | RW_000 +| | | | | AS_030 +| * | S | BS | BR | DSACK1 +| | | | | SIZE_1_ +| * | S | BS | BR | BGACK_030 +| | | | | FPU_CS +| * | S | BS | BR | RN_BGACK_030 +| * | S | BS | BR | inst_AS_030_D0 +| * | S | BS | BR | inst_AS_030_000_SYNC +| * | S | BS | BR | RN_DSACK1 +| * | S | BS | BR | RN_RW_000 +| * | S | BR | BR | CLK_000_N_SYNC_10_ +| * | S | BS | BR | inst_BGACK_030_INT_D +| * | S | BS | BR | inst_DS_030_D0 +| | | | | A_23_ +| | | | | A_22_ + + + (S) means the macrocell is configured in synchronous mode + i.e. it uses the block-level set and reset pt. + (A) means the macrocell is configured in asynchronous mode + i.e. it can have its independant set or reset pt. + (BS) means the block-level set pt is selected. + (BR) means the block-level reset pt is selected. + + + + +BLOCK_A_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx A0 A0 pin 69 mx A17 SIZE_0_ pin 70 +mx A1 ... ... mx A18 inst_DS_030_D0 mcell H10 +mx A2 inst_CLK_030_H mcell A5 mx A19 ... ... +mx A3 A1 pin 60 mx A20 SIZE_1_ pin 79 +mx A4 SM_AMIGA_6_ mcell C12 mx A21 RST pin 86 +mx A5 ... ... mx A22 inst_AS_000_DMA mcell G5 +mx A6 RW_000 pin 80 mx A23 RN_BGACK_030 mcell H4 +mx A7 ... ... mx A24CLK_000_N_SYNC_7_ mcell F14 +mx A8 UDS_000 pin 32 mx A25 ... ... +mx A9inst_UDS_000_INT mcell A12 mx A26 ... ... +mx A10CLK_000_N_SYNC_5_ mcell B13 mx A27 LDS_000 pin 31 +mx A11 ... ... mx A28 CLK_030 pin 64 +mx A12CLK_000_P_SYNC_1_ mcell B10 mx A29 ... ... +mx A13 ... ... mx A30inst_LDS_000_INT mcell A8 +mx A14CLK_000_N_SYNC_10_ mcell H2 mx A31inst_nEXP_SPACE_D0 mcell B5 +mx A15 RN_DS_030 mcell A0 mx A32 ... ... +mx A16 AS_000 pin 42 +---------------------------------------------------------------------------- + + +BLOCK_B_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx B0 IPL_0_ pin 67 mx B17 RN_IPL_030_0_ mcell B8 +mx B1 RESET_DLY_4_ mcell F12 mx B18 RESET_DLY_1_ mcell F9 +mx B2inst_CLK_000_NE_D0 mcell D10 mx B19CLK_000_P_SYNC_0_ mcell E6 +mx B3 IPL_1_ pin 56 mx B20 RESET_DLY_7_ mcell B14 +mx B4 cpu_est_0_ mcell D6 mx B21 RST pin 86 +mx B5CLK_000_N_SYNC_1_ mcell G10 mx B22 IPL_2_ pin 68 +mx B6 RESET_DLY_0_ mcell F13 mx B23 ... ... +mx B7 ... ... mx B24 ... ... +mx B8 inst_CLK_000_NE mcell E8 mx B25 ... ... +mx B9 RESET_DLY_5_ mcell G13 mx B26 RN_RESET mcell B0 +mx B10CLK_000_P_SYNC_3_ mcell G14 mx B27 RN_IPL_030_2_ mcell B4 +mx B11 RN_E mcell G4 mx B28 cpu_est_2_ mcell D2 +mx B12 RN_IPL_030_1_ mcell B12 mx B29 cpu_est_1_ mcell D13 +mx B13CLK_000_N_SYNC_4_ mcell D3 mx B30 RESET_DLY_3_ mcell F1 +mx B14 RESET_DLY_2_ mcell F5 mx B31 ... ... +mx B15 nEXP_SPACE pin 14 mx B32CLK_OUT_PRE_Dreg mcell F8 +mx B16 RESET_DLY_6_ mcell B9 +---------------------------------------------------------------------------- + + +BLOCK_C_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx C0 RST pin 86 mx C17 BERR pin 41 +mx C1inst_DS_000_ENABLE mcell C1 mx C18CLK_000_P_SYNC_6_ mcell C10 +mx C2CLK_000_P_SYNC_4_ mcell B6 mx C19inst_AMIGA_BUS_ENABLE_DMA_LOW mcell A9 +mx C3 inst_AS_000_INT mcell C9 mx C20 RN_BGACK_030 mcell H4 +mx C4 SM_AMIGA_6_ mcell C12 mx C21 ... ... +mx C5CLK_000_P_SYNC_9_ mcell G3 mx C22 SM_AMIGA_5_ mcell C2 +mx C6 inst_CLK_000_PE mcell C4 mx C23 ... ... +mx C7CLK_000_P_SYNC_5_ mcell C14 mx C24 ... ... +mx C8 RW pin 71 mx C25 SM_AMIGA_7_ mcell F0 +mx C9 SM_AMIGA_3_ mcell F2 mx C26 ... ... +mx C10 inst_CLK_000_D0 mcell D14 mx C27 inst_AS_030_D0 mcell H9 +mx C11 SM_AMIGA_2_ mcell F6 mx C28inst_AS_030_000_SYNC mcell H13 +mx C12 ... ... mx C29 SM_AMIGA_0_ mcell F4 +mx C13 ... ... mx C30 inst_CLK_000_NE mcell E8 +mx C14 inst_CLK_000_D1 mcell E5 mx C31inst_nEXP_SPACE_D0 mcell B5 +mx C15 SM_AMIGA_4_ mcell C5 mx C32 ... ... +mx C16 SM_AMIGA_1_ mcell C8 +---------------------------------------------------------------------------- + + +BLOCK_D_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx D0inst_nEXP_SPACE_D0 mcell B5 mx D17 RN_BG_000 mcell D1 +mx D1inst_DS_000_ENABLE mcell C1 mx D18inst_LDS_000_INT mcell A8 +mx D2 RN_E mcell G4 mx D19 inst_VPA_D mcell F10 +mx D3 CLK_000 pin 11 mx D20inst_CLK_000_NE_D0 mcell D10 +mx D4 BG_030 pin 21 mx D21 RST pin 86 +mx D5CLK_000_N_SYNC_3_ mcell G6 mx D22 inst_AS_000_DMA mcell G5 +mx D6 inst_CLK_000_PE mcell C4 mx D23 RN_BGACK_030 mcell H4 +mx D7inst_BGACK_030_INT_D mcell H6 mx D24 ... ... +mx D8 inst_CLK_000_NE mcell E8 mx D25inst_AMIGA_BUS_ENABLE_DMA_HIGH mcell A13 +mx D9 DTACK pin 30 mx D26 inst_CLK_000_D1 mcell E5 +mx D10 inst_CLK_000_D0 mcell D14 mx D27 inst_AS_030_D0 mcell H9 +mx D11RN_AMIGA_ADDR_ENABLE mcell D5 mx D28inst_AS_030_000_SYNC mcell H13 +mx D12 DS_030 pin 98 mx D29 cpu_est_1_ mcell D13 +mx D13 ... ... mx D30 cpu_est_0_ mcell D6 +mx D14 RN_VMA mcell D4 mx D31 SM_AMIGA_7_ mcell F0 +mx D15inst_UDS_000_INT mcell A12 mx D32 DSACK1 pin 81 +mx D16 cpu_est_2_ mcell D2 +---------------------------------------------------------------------------- + + +BLOCK_E_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx E0 RN_BGACK_030 mcell H4 mx E17 A_26_ pin 17 +mx E1 FC_1_ pin 58 mx E18 BGACK_000 pin 28 +mx E2 CIIN_0 mcell E9 mx E19 A_30_ pin 5 +mx E3 A_27_ pin 16 mx E20 A_22_ pin 84 +mx E4 A_29_ pin 6 mx E21CLK_000_N_SYNC_8_ mcell A1 +mx E5 A_24_ pin 19 mx E22 A_25_ pin 18 +mx E6 RW_000 pin 80 mx E23 inst_AS_000_INT mcell C9 +mx E7 A_28_ pin 15 mx E24 FC_0_ pin 57 +mx E8 FPU_SENSE pin 91 mx E25 A_31_ pin 4 +mx E9 AS_030 pin 82 mx E26 inst_CLK_000_D1 mcell E5 +mx E10 inst_CLK_000_D0 mcell D14 mx E27 inst_AS_030_D0 mcell H9 +mx E11 A_16_ pin 96 mx E28inst_nEXP_SPACE_D0 mcell B5 +mx E12 A_19_ pin 97 mx E29 A_20_ pin 93 +mx E13 A_17_ pin 59 mx E30 ... ... +mx E14CLK_000_N_SYNC_11_ mcell A10 mx E31 A_18_ pin 95 +mx E15 A_21_ pin 94 mx E32 A_23_ pin 85 +mx E16 AS_000 pin 42 +---------------------------------------------------------------------------- + + +BLOCK_F_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx F0CLK_000_N_SYNC_6_ mcell A2 mx F17 BERR pin 41 +mx F1 cpu_est_1_ mcell D13 mx F18 RESET_DLY_1_ mcell F9 +mx F2 inst_VPA_D mcell F10 mx F19 SM_AMIGA_2_ mcell F6 +mx F3inst_CLK_OUT_PRE_50 mcell F11 mx F20inst_CLK_000_NE_D0 mcell D10 +mx F4 cpu_est_0_ mcell D6 mx F21 RN_E mcell G4 +mx F5 ... ... mx F22 RESET_DLY_0_ mcell F13 +mx F6 inst_CLK_000_PE mcell C4 mx F23 ... ... +mx F7 SM_AMIGA_1_ mcell C8 mx F24 RST pin 86 +mx F8 inst_CLK_000_NE mcell E8 mx F25inst_CLK_OUT_PRE mcell F7 +mx F9CLK_000_P_SYNC_7_ mcell C6 mx F26 ... ... +mx F10 VPA pin 36 mx F27 RESET_DLY_2_ mcell F5 +mx F11sm_amiga_ns_0_3_0__n mcell C13 mx F28 SM_AMIGA_3_ mcell F2 +mx F12 ... ... mx F29 SM_AMIGA_0_ mcell F4 +mx F13 inst_DTACK_D0 mcell D7 mx F30 RESET_DLY_3_ mcell F1 +mx F14 RN_VMA mcell D4 mx F31 RESET_DLY_4_ mcell F12 +mx F15 SM_AMIGA_4_ mcell C5 mx F32 ... ... +mx F16 cpu_est_2_ mcell D2 +---------------------------------------------------------------------------- + + +BLOCK_G_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx G0 RN_BGACK_030 mcell H4 mx G17 RN_RW mcell G0 +mx G1 RESET_DLY_1_ mcell F9 mx G18CLK_000_N_SYNC_2_ mcell B2 +mx G2inst_CLK_000_NE_D0 mcell D10 mx G19 ... ... +mx G3CLK_000_N_SYNC_0_ mcell E2 mx G20 CLK_030 pin 64 +mx G4 cpu_est_0_ mcell D6 mx G21 cpu_est_1_ mcell D13 +mx G5 ... ... mx G22 inst_AS_000_DMA mcell G5 +mx G6 RW_000 pin 80 mx G23 SIZE_DMA_0_ mcell G2 +mx G7CLK_000_P_SYNC_8_ mcell F3 mx G24 RST pin 86 +mx G8 UDS_000 pin 32 mx G25 ... ... +mx G9 RESET_DLY_5_ mcell G13 mx G26 AS_000 pin 42 +mx G10CLK_000_P_SYNC_2_ mcell A6 mx G27 LDS_000 pin 31 +mx G11 RN_E mcell G4 mx G28inst_nEXP_SPACE_D0 mcell B5 +mx G12 SIZE_DMA_1_ mcell G9 mx G29 ... ... +mx G13 ... ... mx G30 RESET_DLY_3_ mcell F1 +mx G14 RESET_DLY_2_ mcell F5 mx G31 RESET_DLY_4_ mcell F12 +mx G15 RESET_DLY_0_ mcell F13 mx G32CLK_OUT_PRE_Dreg mcell F8 +mx G16 cpu_est_2_ mcell D2 +---------------------------------------------------------------------------- + + +BLOCK_H_LOGIC_ARRAY_FANIN +~~~~~~~~~~~~~~~~~~~~~~~~~ +CSM Signal Source CSM Signal Source +------------------------------------ ------------------------------------ +mx H0 RN_BGACK_030 mcell H4 mx H17 A_18_ pin 95 +mx H1 BERR pin 41 mx H18 DS_030 pin 98 +mx H2CLK_OUT_PRE_Dreg mcell F8 mx H19 AS_030 pin 82 +mx H3 inst_AS_000_DMA mcell G5 mx H20 CLK_030 pin 64 +mx H4 SM_AMIGA_6_ mcell C12 mx H21 RST pin 86 +mx H5 inst_AS_030_D0 mcell H9 mx H22 ... ... +mx H6 FC_0_ pin 57 mx H23CLK_000_N_SYNC_9_ mcell E13 +mx H7inst_AS_030_000_SYNC mcell H13 mx H24 ... ... +mx H8 FPU_SENSE pin 91 mx H25 SM_AMIGA_7_ mcell F0 +mx H9CLK_000_N_SYNC_8_ mcell A1 mx H26 A_16_ pin 96 +mx H10 SIZE_DMA_1_ mcell G9 mx H27 A_19_ pin 97 +mx H11 RW pin 71 mx H28inst_nEXP_SPACE_D0 mcell B5 +mx H12 FC_1_ pin 58 mx H29 inst_CLK_000_PE mcell C4 +mx H13 A_17_ pin 59 mx H30 RN_RW_000 mcell H0 +mx H14 SM_AMIGA_0_ mcell F4 mx H31 SIZE_DMA_0_ mcell G2 +mx H15 RN_DSACK1 mcell H12 mx H32 BGACK_000 pin 28 +mx H16 SM_AMIGA_1_ mcell C8 +---------------------------------------------------------------------------- + + CSM indicates the mux inputs from the Central Switch Matrix. + Source indicates where the signal comes from (pin or macrocell). + + + + +PostFit_Equations +~~~~~~~~~~~~~~~~~ + + + P-Terms Fan-in Fan-out Type Name (attributes) +--------- ------ ------- ---- ----------------- + 1 2 1 Pin SIZE_1_- + 1 3 1 Pin SIZE_1_.OE + 0 0 1 Pin AS_030 + 1 3 1 Pin AS_030.OE + 1 2 1 Pin AS_000- + 1 1 1 Pin AS_000.OE + 1 3 1 Pin UDS_000- + 1 1 1 Pin UDS_000.OE + 1 3 1 Pin LDS_000- + 1 1 1 Pin LDS_000.OE + 0 0 1 Pin BERR + 1 9 1 Pin BERR.OE + 1 1 1 Pin CLK_DIV_OUT + 1 1 1 Pin CLK_EXP + 1 9 1 Pin FPU_CS- + 1 1 1 Pin DTACK + 1 3 1 Pin DTACK.OE + 1 0 1 Pin AVEC + 2 4 1 Pin AMIGA_BUS_DATA_DIR + 1 2 1 Pin AMIGA_BUS_ENABLE_LOW- + 1 2 1 Pin AMIGA_BUS_ENABLE_HIGH + 1 13 1 Pin CIIN + 1 1 1 Pin CIIN.OE + 1 2 1 Pin SIZE_0_- + 1 3 1 Pin SIZE_0_.OE + 2 3 1 Pin IPL_030_2_.D + 1 1 1 Pin IPL_030_2_.AP + 1 1 1 Pin IPL_030_2_.C + 2 3 1 Pin IPL_030_1_.D + 1 1 1 Pin IPL_030_1_.AP + 1 1 1 Pin IPL_030_1_.C + 1 1 1 Pin RW_000.OE + 3 8 1 Pin RW_000.D- + 1 1 1 Pin RW_000.AP + 1 1 1 Pin RW_000.C + 2 3 1 Pin IPL_030_0_.D + 1 1 1 Pin IPL_030_0_.AP + 1 1 1 Pin IPL_030_0_.C + 1 3 1 Pin DS_030.OE + 7 9 1 Pin DS_030.D + 1 1 1 Pin DS_030.AP + 1 1 1 Pin DS_030.C + 1 3 1 Pin A0.OE + 1 4 1 Pin A0.D + 1 1 1 Pin A0.AP + 1 1 1 Pin A0.C + 2 5 1 Pin BG_000.D- + 1 1 1 Pin BG_000.AP + 1 1 1 Pin BG_000.C + 2 3 1 Pin BGACK_030.D + 1 1 1 Pin BGACK_030.AP + 1 1 1 Pin BGACK_030.C + 1 1 1 Pin DSACK1.OE + 4 8 1 Pin DSACK1.D- + 1 1 1 Pin DSACK1.AP + 1 1 1 Pin DSACK1.C + 3 5 1 PinX1 E.D.X1 + 1 5 1 PinX2 E.D.X2 + 1 1 1 Pin E.C + 3 8 1 PinX1 VMA.D.X1 + 1 2 1 PinX2 VMA.D.X2 + 1 1 1 Pin VMA.AP + 1 1 1 Pin VMA.C + 1 1 1 Pin RESET.AR + 2 9 1 Pin RESET.D + 1 1 1 Pin RESET.C + 1 1 1 Pin RW.OE + 4 7 1 Pin RW.D- + 1 1 1 Pin RW.AP + 1 1 1 Pin RW.C + 3 8 1 Pin AMIGA_ADDR_ENABLE.D- + 1 1 1 Pin AMIGA_ADDR_ENABLE.AP + 1 1 1 Pin AMIGA_ADDR_ENABLE.C + 2 2 1 Node cpu_est_0_.D + 1 1 1 Node cpu_est_0_.C + 5 5 1 Node cpu_est_1_.D- + 1 1 1 Node cpu_est_1_.C + 2 5 1 Node inst_AS_000_INT.D- + 1 1 1 Node inst_AS_000_INT.AP + 1 1 1 Node inst_AS_000_INT.C + 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- + 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.AP + 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_HIGH.C + 2 5 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.D- + 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.AP + 1 1 1 Node inst_AMIGA_BUS_ENABLE_DMA_LOW.C + 1 1 1 Node inst_AS_030_D0.D + 1 1 1 Node inst_AS_030_D0.AP + 1 1 1 Node inst_AS_030_D0.C + 1 1 1 Node inst_nEXP_SPACE_D0.D + 1 1 1 Node inst_nEXP_SPACE_D0.AP + 1 1 1 Node inst_nEXP_SPACE_D0.C + 1 1 1 Node inst_DS_030_D0.D + 1 1 1 Node inst_DS_030_D0.AP + 1 1 1 Node inst_DS_030_D0.C + 6 12 1 Node inst_AS_030_000_SYNC.D + 1 1 1 Node inst_AS_030_000_SYNC.AP + 1 1 1 Node inst_AS_030_000_SYNC.C + 1 1 1 Node inst_BGACK_030_INT_D.D + 1 1 1 Node inst_BGACK_030_INT_D.AP + 1 1 1 Node inst_BGACK_030_INT_D.C + 4 6 1 Node inst_AS_000_DMA.D + 1 1 1 Node inst_AS_000_DMA.AP + 1 1 1 Node inst_AS_000_DMA.C + 1 4 1 Node SIZE_DMA_0_.D- + 1 1 1 Node SIZE_DMA_0_.AP + 1 1 1 Node SIZE_DMA_0_.C + 2 4 1 Node SIZE_DMA_1_.D- + 1 1 1 Node SIZE_DMA_1_.AP + 1 1 1 Node SIZE_DMA_1_.C + 1 1 1 Node inst_VPA_D.D + 1 1 1 Node inst_VPA_D.AP + 1 1 1 Node inst_VPA_D.C + 3 4 1 Node inst_UDS_000_INT.D + 1 1 1 Node inst_UDS_000_INT.AP + 1 1 1 Node inst_UDS_000_INT.C + 3 6 1 Node inst_LDS_000_INT.D + 1 1 1 Node inst_LDS_000_INT.AP + 1 1 1 Node inst_LDS_000_INT.C + 1 1 1 Node inst_DTACK_D0.D + 1 1 1 Node inst_DTACK_D0.AP + 1 1 1 Node inst_DTACK_D0.C + 1 12 1 NodeX1 RESET_DLY_7_.D.X1 + 1 1 1 NodeX2 RESET_DLY_7_.D.X2 + 1 1 1 Node RESET_DLY_7_.AR + 1 1 1 Node RESET_DLY_7_.C + 1 1 1 Node inst_CLK_OUT_PRE_50.D + 1 1 1 Node inst_CLK_OUT_PRE_50.C + 1 1 1 Node inst_CLK_000_D1.D + 1 1 1 Node inst_CLK_000_D1.C + 1 1 1 Node inst_CLK_000_D0.D + 1 1 1 Node inst_CLK_000_D0.C + 11 14 1 Node sm_amiga_ns_0_3_0__n- + 4 11 1 Node SM_AMIGA_7_.D- + 1 1 1 Node SM_AMIGA_7_.AP + 1 1 1 Node SM_AMIGA_7_.C + 1 1 1 Node inst_CLK_OUT_PRE.D + 1 1 1 Node inst_CLK_OUT_PRE.C + 1 1 1 Node inst_CLK_000_PE.D + 1 1 1 Node inst_CLK_000_PE.C + 1 1 1 Node CLK_000_P_SYNC_9_.D + 1 1 1 Node CLK_000_P_SYNC_9_.C + 1 1 1 Node inst_CLK_000_NE.D + 1 1 1 Node inst_CLK_000_NE.C + 1 1 1 Node CLK_000_N_SYNC_11_.D + 1 1 1 Node CLK_000_N_SYNC_11_.C + 4 5 1 Node cpu_est_2_.D + 1 1 1 Node cpu_est_2_.C + 1 1 1 Node inst_CLK_000_NE_D0.D + 1 1 1 Node inst_CLK_000_NE_D0.C + 1 1 1 Node SM_AMIGA_6_.AR + 2 8 1 Node SM_AMIGA_6_.D + 1 1 1 Node SM_AMIGA_6_.C + 1 1 1 Node SM_AMIGA_4_.AR + 2 5 1 Node SM_AMIGA_4_.D + 1 1 1 Node SM_AMIGA_4_.C + 1 1 1 Node SM_AMIGA_0_.AR + 2 5 1 Node SM_AMIGA_0_.D + 1 1 1 Node SM_AMIGA_0_.C + 1 1 1 Node inst_CLK_030_H.AR + 4 7 1 Node inst_CLK_030_H.D + 1 1 1 Node inst_CLK_030_H.C + 1 2 1 Node CLK_000_P_SYNC_0_.D + 1 1 1 Node CLK_000_P_SYNC_0_.C + 1 1 1 Node CLK_000_P_SYNC_1_.D + 1 1 1 Node CLK_000_P_SYNC_1_.C + 1 1 1 Node CLK_000_P_SYNC_2_.D + 1 1 1 Node CLK_000_P_SYNC_2_.C + 1 1 1 Node CLK_000_P_SYNC_3_.D + 1 1 1 Node CLK_000_P_SYNC_3_.C + 1 1 1 Node CLK_000_P_SYNC_4_.D + 1 1 1 Node CLK_000_P_SYNC_4_.C + 1 1 1 Node CLK_000_P_SYNC_5_.D + 1 1 1 Node CLK_000_P_SYNC_5_.C + 1 1 1 Node CLK_000_P_SYNC_6_.D + 1 1 1 Node CLK_000_P_SYNC_6_.C + 1 1 1 Node CLK_000_P_SYNC_7_.D + 1 1 1 Node CLK_000_P_SYNC_7_.C + 1 1 1 Node CLK_000_P_SYNC_8_.D + 1 1 1 Node CLK_000_P_SYNC_8_.C + 1 2 1 Node CLK_000_N_SYNC_0_.D + 1 1 1 Node CLK_000_N_SYNC_0_.C + 1 1 1 Node CLK_000_N_SYNC_1_.D + 1 1 1 Node CLK_000_N_SYNC_1_.C + 1 1 1 Node CLK_000_N_SYNC_2_.D + 1 1 1 Node CLK_000_N_SYNC_2_.C + 1 1 1 Node CLK_000_N_SYNC_3_.D + 1 1 1 Node CLK_000_N_SYNC_3_.C + 1 1 1 Node CLK_000_N_SYNC_4_.D + 1 1 1 Node CLK_000_N_SYNC_4_.C + 1 1 1 Node CLK_000_N_SYNC_5_.D + 1 1 1 Node CLK_000_N_SYNC_5_.C + 1 1 1 Node CLK_000_N_SYNC_6_.D + 1 1 1 Node CLK_000_N_SYNC_6_.C + 1 1 1 Node CLK_000_N_SYNC_7_.D + 1 1 1 Node CLK_000_N_SYNC_7_.C + 1 1 1 Node CLK_000_N_SYNC_8_.D + 1 1 1 Node CLK_000_N_SYNC_8_.C + 1 1 1 Node CLK_000_N_SYNC_9_.D + 1 1 1 Node CLK_000_N_SYNC_9_.C + 1 1 1 Node CLK_000_N_SYNC_10_.D + 1 1 1 Node CLK_000_N_SYNC_10_.C + 1 5 1 NodeX1 RESET_DLY_0_.D.X1 + 1 1 1 NodeX2 RESET_DLY_0_.D.X2 + 1 1 1 Node RESET_DLY_0_.AR + 1 1 1 Node RESET_DLY_0_.C + 1 6 1 NodeX1 RESET_DLY_1_.D.X1 + 1 1 1 NodeX2 RESET_DLY_1_.D.X2 + 1 1 1 Node RESET_DLY_1_.AR + 1 1 1 Node RESET_DLY_1_.C + 1 7 1 NodeX1 RESET_DLY_2_.D.X1 + 1 1 1 NodeX2 RESET_DLY_2_.D.X2 + 1 1 1 Node RESET_DLY_2_.AR + 1 1 1 Node RESET_DLY_2_.C + 1 8 1 NodeX1 RESET_DLY_3_.D.X1 + 1 1 1 NodeX2 RESET_DLY_3_.D.X2 + 1 1 1 Node RESET_DLY_3_.AR + 1 1 1 Node RESET_DLY_3_.C + 1 9 1 NodeX1 RESET_DLY_4_.D.X1 + 1 1 1 NodeX2 RESET_DLY_4_.D.X2 + 1 1 1 Node RESET_DLY_4_.AR + 1 1 1 Node RESET_DLY_4_.C + 1 10 1 NodeX1 RESET_DLY_5_.D.X1 + 1 1 1 NodeX2 RESET_DLY_5_.D.X2 + 1 1 1 Node RESET_DLY_5_.AR + 1 1 1 Node RESET_DLY_5_.C + 1 11 1 NodeX1 RESET_DLY_6_.D.X1 + 1 1 1 NodeX2 RESET_DLY_6_.D.X2 + 1 1 1 Node RESET_DLY_6_.AR + 1 1 1 Node RESET_DLY_6_.C + 1 1 1 Node inst_DS_000_ENABLE.AR + 3 7 1 Node inst_DS_000_ENABLE.D + 1 1 1 Node inst_DS_000_ENABLE.C + 1 1 1 Node SM_AMIGA_1_.AR + 2 5 1 Node SM_AMIGA_1_.D + 1 1 1 Node SM_AMIGA_1_.C + 1 1 1 Node SM_AMIGA_5_.AR + 2 5 1 Node SM_AMIGA_5_.D + 1 1 1 Node SM_AMIGA_5_.C + 6 12 1 NodeX1 SM_AMIGA_3_.D.X1 + 1 2 1 NodeX2 SM_AMIGA_3_.D.X2 + 1 1 1 Node SM_AMIGA_3_.AR + 1 1 1 Node SM_AMIGA_3_.C + 1 1 1 Node SM_AMIGA_2_.AR + 3 12 1 Node SM_AMIGA_2_.D + 1 1 1 Node SM_AMIGA_2_.C + 1 1 1 Node CLK_OUT_PRE_Dreg.D + 1 1 1 Node CLK_OUT_PRE_Dreg.C + 3 15 1 Node CIIN_0 +========= + 330 P-Term Total: 330 + Total Pins: 61 + Total Nodes: 68 + Average P-Term/Output: 1 + + +Equations: + +!SIZE_1_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q); + +SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0.Q & !inst_AS_000_DMA.Q); + +AS_030 = (0); + +AS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0.Q & !inst_AS_000_DMA.Q); + +!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN); + +AS_000.OE = (BGACK_030.Q); + +!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN); + +UDS_000.OE = (BGACK_030.Q); + +!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q & !DS_030.PIN); + +LDS_000.OE = (BGACK_030.Q); + +BERR = (0); + +BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); + +CLK_DIV_OUT = (CLK_OUT_PRE_Dreg.Q); + +CLK_EXP = (CLK_OUT_PRE_Dreg.Q); + +!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN); + +DTACK = (DSACK1.PIN); + +DTACK.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0.Q & !inst_AS_000_DMA.Q); + +AVEC = (1); + +AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN + # !BGACK_030.Q & !inst_nEXP_SPACE_D0.Q & !AS_000.PIN & RW_000.PIN); + +!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q); + +AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q); + +CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q); + +CIIN.OE = (CIIN_0); + +!SIZE_0_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q); + +SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0.Q & !inst_AS_000_DMA.Q); + +IPL_030_2_.D = (IPL_2_ & inst_CLK_000_NE.Q + # !inst_CLK_000_NE.Q & IPL_030_2_.Q); + +IPL_030_2_.AP = (!RST); + +IPL_030_2_.C = (CLK_OSZI); + +IPL_030_1_.D = (IPL_1_ & inst_CLK_000_NE.Q + # !inst_CLK_000_NE.Q & IPL_030_1_.Q); + +IPL_030_1_.AP = (!RST); + +IPL_030_1_.C = (CLK_OSZI); + +RW_000.OE = (BGACK_030.Q); + +!RW_000.D = (inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & !RW.PIN + # !inst_AS_030_D0.Q & !SM_AMIGA_7_.Q & !inst_CLK_000_PE.Q & !RW_000.Q & BERR.PIN + # !inst_AS_030_D0.Q & !SM_AMIGA_7_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & BERR.PIN); + +RW_000.AP = (!RST); + +RW_000.C = (CLK_OSZI); + +IPL_030_0_.D = (IPL_0_ & inst_CLK_000_NE.Q + # !inst_CLK_000_NE.Q & IPL_030_0_.Q); + +IPL_030_0_.AP = (!RST); + +IPL_030_0_.C = (CLK_OSZI); + +DS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0.Q & !inst_AS_000_DMA.Q); + +DS_030.D = (BGACK_030.Q + # AS_000.PIN + # inst_AS_000_DMA.Q & RW_000.PIN + # UDS_000.PIN & LDS_000.PIN + # CLK_030 & inst_AS_000_DMA.Q & inst_CLK_030_H.Q + # !CLK_030 & DS_030.Q & !RW_000.PIN + # !inst_CLK_030_H.Q & DS_030.Q & !RW_000.PIN); + +DS_030.AP = (!RST); + +DS_030.C = (CLK_OSZI); + +A0.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0.Q & !inst_AS_000_DMA.Q); + +A0.D = (!BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN); + +A0.AP = (!RST); + +A0.C = (CLK_OSZI); + +!BG_000.D = (!BG_030 & !BG_000.Q + # !BG_030 & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0.Q & inst_CLK_000_D0.Q); + +BG_000.AP = (!RST); + +BG_000.C = (CLK_OSZI); + +BGACK_030.D = (BGACK_000 & BGACK_030.Q + # BGACK_000 & inst_CLK_000_PE.Q); + +BGACK_030.AP = (!RST); + +BGACK_030.C = (CLK_OSZI); + +DSACK1.OE = (inst_nEXP_SPACE_D0.Q); + +!DSACK1.D = (CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q + # !CLK_030 & CLK_000_N_SYNC_8_.Q & SM_AMIGA_1_.Q + # CLK_000_N_SYNC_8_.Q & SM_AMIGA_1_.Q & CLK_OUT_PRE_Dreg.Q + # !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN); + +DSACK1.AP = (!RST); + +DSACK1.C = (CLK_OSZI); + +E.D.X1 = (E.Q + # cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q + # !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q); + +E.D.X2 = (E.Q & cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q); + +E.C = (CLK_OSZI); + +VMA.D.X1 = (E.Q & VMA.Q + # !E.Q & !VMA.Q & !cpu_est_0_.Q & cpu_est_1_.Q & inst_CLK_000_PE.Q & cpu_est_2_.Q + # VMA.Q & cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q); + +VMA.D.X2 = (!E.Q & VMA.Q); + +VMA.AP = (!RST); + +VMA.C = (CLK_OSZI); + +RESET.AR = (!RST); + +RESET.D = (RESET.Q + # !RESET_DLY_7_.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q & RESET_DLY_4_.Q & RESET_DLY_5_.Q & RESET_DLY_6_.Q); + +RESET.C = (CLK_OSZI); + +RW.OE = (!BGACK_030.Q); + +!RW.D = (!CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !UDS_000.PIN + # CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !UDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !RW.Q & !AS_000.PIN & !LDS_000.PIN + # CLK_030 & !BGACK_030.Q & !AS_000.PIN & !RW_000.PIN & !LDS_000.PIN); + +RW.AP = (!RST); + +RW.C = (CLK_OSZI); + +!AMIGA_ADDR_ENABLE.D = (!BGACK_030.Q + # !AMIGA_ADDR_ENABLE.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_7_.Q + # inst_nEXP_SPACE_D0.Q & !inst_AS_030_000_SYNC.Q & inst_BGACK_030_INT_D.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & SM_AMIGA_7_.Q); + +AMIGA_ADDR_ENABLE.AP = (!RST); + +AMIGA_ADDR_ENABLE.C = (CLK_OSZI); + +cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q + # cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q); + +cpu_est_0_.C = (CLK_OSZI); + +!cpu_est_1_.D = (!cpu_est_1_.Q & !inst_CLK_000_NE_D0.Q + # E.Q & cpu_est_0_.Q & !cpu_est_1_.Q + # !E.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & cpu_est_2_.Q + # E.Q & cpu_est_0_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q + # !E.Q & cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q); + +cpu_est_1_.C = (CLK_OSZI); + +!inst_AS_000_INT.D = (inst_CLK_000_PE.Q & SM_AMIGA_6_.Q + # !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN); + +inst_AS_000_INT.AP = (!RST); + +inst_AS_000_INT.C = (CLK_OSZI); + +!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (!A1 & !BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN + # !A1 & !BGACK_030.Q & !AS_000.PIN & !LDS_000.PIN); + +inst_AMIGA_BUS_ENABLE_DMA_HIGH.AP = (!RST); + +inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI); + +!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (A1 & !BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN + # A1 & !BGACK_030.Q & !AS_000.PIN & !LDS_000.PIN); + +inst_AMIGA_BUS_ENABLE_DMA_LOW.AP = (!RST); + +inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI); + +inst_AS_030_D0.D = (AS_030.PIN); + +inst_AS_030_D0.AP = (!RST); + +inst_AS_030_D0.C = (CLK_OSZI); + +inst_nEXP_SPACE_D0.D = (nEXP_SPACE); + +inst_nEXP_SPACE_D0.AP = (!RST); + +inst_nEXP_SPACE_D0.C = (CLK_OSZI); + +inst_DS_030_D0.D = (DS_030.PIN); + +inst_DS_030_D0.AP = (!RST); + +inst_DS_030_D0.C = (CLK_OSZI); + +inst_AS_030_000_SYNC.D = (inst_AS_030_D0.Q + # !BERR.PIN + # !BGACK_000 & inst_AS_030_000_SYNC.Q + # !inst_nEXP_SPACE_D0.Q & inst_AS_030_000_SYNC.Q + # inst_AS_030_000_SYNC.Q & !SM_AMIGA_7_.Q + # FC_1_ & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & inst_AS_030_000_SYNC.Q); + +inst_AS_030_000_SYNC.AP = (!RST); + +inst_AS_030_000_SYNC.C = (CLK_OSZI); + +inst_BGACK_030_INT_D.D = (BGACK_030.Q); + +inst_BGACK_030_INT_D.AP = (!RST); + +inst_BGACK_030_INT_D.C = (CLK_OSZI); + +inst_AS_000_DMA.D = (BGACK_030.Q + # AS_000.PIN + # !CLK_030 & inst_AS_000_DMA.Q + # UDS_000.PIN & LDS_000.PIN); + +inst_AS_000_DMA.AP = (!RST); + +inst_AS_000_DMA.C = (CLK_OSZI); + +!SIZE_DMA_0_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & !LDS_000.PIN); + +SIZE_DMA_0_.AP = (!RST); + +SIZE_DMA_0_.C = (CLK_OSZI); + +!SIZE_DMA_1_.D = (!BGACK_030.Q & !AS_000.PIN & !UDS_000.PIN & LDS_000.PIN + # !BGACK_030.Q & !AS_000.PIN & UDS_000.PIN & !LDS_000.PIN); + +SIZE_DMA_1_.AP = (!RST); + +SIZE_DMA_1_.C = (CLK_OSZI); + +inst_VPA_D.D = (VPA); + +inst_VPA_D.AP = (!RST); + +inst_VPA_D.C = (CLK_OSZI); + +inst_UDS_000_INT.D = (inst_DS_030_D0.Q & inst_UDS_000_INT.Q + # inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q + # !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & A0.PIN); + +inst_UDS_000_INT.AP = (!RST); + +inst_UDS_000_INT.C = (CLK_OSZI); + +inst_LDS_000_INT.D = (inst_DS_030_D0.Q & inst_LDS_000_INT.Q + # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q + # !inst_DS_030_D0.Q & SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN); + +inst_LDS_000_INT.AP = (!RST); + +inst_LDS_000_INT.C = (CLK_OSZI); + +inst_DTACK_D0.D = (DTACK.PIN); + +inst_DTACK_D0.AP = (!RST); + +inst_DTACK_D0.C = (CLK_OSZI); + +RESET_DLY_7_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q & RESET_DLY_4_.Q & RESET_DLY_5_.Q & RESET_DLY_6_.Q); + +RESET_DLY_7_.D.X2 = (RESET_DLY_7_.Q); + +RESET_DLY_7_.AR = (!RST); + +RESET_DLY_7_.C = (CLK_OSZI); + +inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q); + +inst_CLK_OUT_PRE_50.C = (CLK_OSZI); + +inst_CLK_000_D1.D = (inst_CLK_000_D0.Q); + +inst_CLK_000_D1.C = (CLK_OSZI); + +inst_CLK_000_D0.D = (CLK_000); + +inst_CLK_000_D0.C = (CLK_OSZI); + +!sm_amiga_ns_0_3_0__n = (inst_CLK_000_PE.Q & SM_AMIGA_0_.Q + # SM_AMIGA_0_.Q & !BERR.PIN + # !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & !BERR.PIN + # !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !BERR.PIN + # !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & !BERR.PIN + # !inst_CLK_000_NE.Q & SM_AMIGA_5_.Q & !BERR.PIN + # !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & !BERR.PIN + # !inst_nEXP_SPACE_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q + # inst_AS_030_000_SYNC.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q + # !inst_CLK_000_D1.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q + # inst_CLK_000_D0.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_5_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q); + +!SM_AMIGA_7_.D = (sm_amiga_ns_0_3_0__n & !SM_AMIGA_3_.Q + # sm_amiga_ns_0_3_0__n & BERR.PIN + # inst_VPA_D.Q & !inst_DTACK_D0.Q & sm_amiga_ns_0_3_0__n & inst_CLK_000_NE.Q + # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & sm_amiga_ns_0_3_0__n & inst_CLK_000_NE.Q & cpu_est_2_.Q); + +SM_AMIGA_7_.AP = (!RST); + +SM_AMIGA_7_.C = (CLK_OSZI); + +inst_CLK_OUT_PRE.D = (inst_CLK_OUT_PRE_50.Q); + +inst_CLK_OUT_PRE.C = (CLK_OSZI); + +inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q); + +inst_CLK_000_PE.C = (CLK_OSZI); + +CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q); + +CLK_000_P_SYNC_9_.C = (CLK_OSZI); + +inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q); + +inst_CLK_000_NE.C = (CLK_OSZI); + +CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q); + +CLK_000_N_SYNC_11_.C = (CLK_OSZI); + +cpu_est_2_.D = (cpu_est_1_.Q & cpu_est_2_.Q + # cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q + # E.Q & cpu_est_0_.Q & inst_CLK_000_NE_D0.Q + # !cpu_est_0_.Q & !cpu_est_1_.Q & inst_CLK_000_NE_D0.Q); + +cpu_est_2_.C = (CLK_OSZI); + +inst_CLK_000_NE_D0.D = (inst_CLK_000_NE.Q); + +inst_CLK_000_NE_D0.C = (CLK_OSZI); + +SM_AMIGA_6_.AR = (!RST); + +SM_AMIGA_6_.D = (!inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN + # inst_nEXP_SPACE_D0.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & SM_AMIGA_7_.Q); + +SM_AMIGA_6_.C = (CLK_OSZI); + +SM_AMIGA_4_.AR = (!RST); + +SM_AMIGA_4_.D = (inst_CLK_000_NE.Q & SM_AMIGA_5_.Q + # !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & BERR.PIN); + +SM_AMIGA_4_.C = (CLK_OSZI); + +SM_AMIGA_0_.AR = (!RST); + +SM_AMIGA_0_.D = (inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & SM_AMIGA_1_.Q + # !inst_CLK_000_PE.Q & SM_AMIGA_0_.Q & BERR.PIN); + +SM_AMIGA_0_.C = (CLK_OSZI); + +inst_CLK_030_H.AR = (!RST); + +inst_CLK_030_H.D = (!BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN + # !BGACK_030.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !inst_AS_000_DMA.Q & !AS_000.PIN & !UDS_000.PIN + # !CLK_030 & !BGACK_030.Q & !inst_AS_000_DMA.Q & !AS_000.PIN & !LDS_000.PIN); + +inst_CLK_030_H.C = (CLK_OSZI); + +CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q); + +CLK_000_P_SYNC_0_.C = (CLK_OSZI); + +CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q); + +CLK_000_P_SYNC_1_.C = (CLK_OSZI); + +CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q); + +CLK_000_P_SYNC_2_.C = (CLK_OSZI); + +CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q); + +CLK_000_P_SYNC_3_.C = (CLK_OSZI); + +CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q); + +CLK_000_P_SYNC_4_.C = (CLK_OSZI); + +CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q); + +CLK_000_P_SYNC_5_.C = (CLK_OSZI); + +CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q); + +CLK_000_P_SYNC_6_.C = (CLK_OSZI); + +CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q); + +CLK_000_P_SYNC_7_.C = (CLK_OSZI); + +CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q); + +CLK_000_P_SYNC_8_.C = (CLK_OSZI); + +CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q); + +CLK_000_N_SYNC_0_.C = (CLK_OSZI); + +CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q); + +CLK_000_N_SYNC_1_.C = (CLK_OSZI); + +CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q); + +CLK_000_N_SYNC_2_.C = (CLK_OSZI); + +CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q); + +CLK_000_N_SYNC_3_.C = (CLK_OSZI); + +CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q); + +CLK_000_N_SYNC_4_.C = (CLK_OSZI); + +CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q); + +CLK_000_N_SYNC_5_.C = (CLK_OSZI); + +CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q); + +CLK_000_N_SYNC_6_.C = (CLK_OSZI); + +CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q); + +CLK_000_N_SYNC_7_.C = (CLK_OSZI); + +CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q); + +CLK_000_N_SYNC_8_.C = (CLK_OSZI); + +CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q); + +CLK_000_N_SYNC_9_.C = (CLK_OSZI); + +CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q); + +CLK_000_N_SYNC_10_.C = (CLK_OSZI); + +RESET_DLY_0_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q); + +RESET_DLY_0_.D.X2 = (RESET_DLY_0_.Q); + +RESET_DLY_0_.AR = (!RST); + +RESET_DLY_0_.C = (CLK_OSZI); + +RESET_DLY_1_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q); + +RESET_DLY_1_.D.X2 = (RESET_DLY_1_.Q); + +RESET_DLY_1_.AR = (!RST); + +RESET_DLY_1_.C = (CLK_OSZI); + +RESET_DLY_2_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q); + +RESET_DLY_2_.D.X2 = (RESET_DLY_2_.Q); + +RESET_DLY_2_.AR = (!RST); + +RESET_DLY_2_.C = (CLK_OSZI); + +RESET_DLY_3_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q); + +RESET_DLY_3_.D.X2 = (RESET_DLY_3_.Q); + +RESET_DLY_3_.AR = (!RST); + +RESET_DLY_3_.C = (CLK_OSZI); + +RESET_DLY_4_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q); + +RESET_DLY_4_.D.X2 = (RESET_DLY_4_.Q); + +RESET_DLY_4_.AR = (!RST); + +RESET_DLY_4_.C = (CLK_OSZI); + +RESET_DLY_5_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q & RESET_DLY_4_.Q); + +RESET_DLY_5_.D.X2 = (RESET_DLY_5_.Q); + +RESET_DLY_5_.AR = (!RST); + +RESET_DLY_5_.C = (CLK_OSZI); + +RESET_DLY_6_.D.X1 = (!E.Q & !cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q & RESET_DLY_0_.Q & RESET_DLY_1_.Q & RESET_DLY_2_.Q & RESET_DLY_3_.Q & RESET_DLY_4_.Q & RESET_DLY_5_.Q); + +RESET_DLY_6_.D.X2 = (RESET_DLY_6_.Q); + +RESET_DLY_6_.AR = (!RST); + +RESET_DLY_6_.C = (CLK_OSZI); + +inst_DS_000_ENABLE.AR = (!RST); + +inst_DS_000_ENABLE.D = (inst_CLK_000_PE.Q & SM_AMIGA_4_.Q + # !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN + # inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & RW.PIN); + +inst_DS_000_ENABLE.C = (CLK_OSZI); + +SM_AMIGA_1_.AR = (!RST); + +SM_AMIGA_1_.D = (inst_CLK_000_PE.Q & SM_AMIGA_2_.Q + # !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & BERR.PIN); + +SM_AMIGA_1_.C = (CLK_OSZI); + +SM_AMIGA_5_.AR = (!RST); + +SM_AMIGA_5_.D = (inst_CLK_000_PE.Q & SM_AMIGA_6_.Q + # !inst_CLK_000_NE.Q & SM_AMIGA_5_.Q & BERR.PIN); + +SM_AMIGA_5_.C = (CLK_OSZI); + +SM_AMIGA_3_.D.X1 = (inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q + # inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !BERR.PIN + # inst_VPA_D.Q & !inst_DTACK_D0.Q & !inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q & BERR.PIN + # inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q & BERR.PIN + # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & !inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q & BERR.PIN + # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q & BERR.PIN); + +SM_AMIGA_3_.D.X2 = (SM_AMIGA_3_.Q & BERR.PIN); + +SM_AMIGA_3_.AR = (!RST); + +SM_AMIGA_3_.C = (CLK_OSZI); + +SM_AMIGA_2_.AR = (!RST); + +SM_AMIGA_2_.D = (!inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN + # inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE.Q & SM_AMIGA_3_.Q + # E.Q & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q & cpu_est_2_.Q & SM_AMIGA_3_.Q); + +SM_AMIGA_2_.C = (CLK_OSZI); + +CLK_OUT_PRE_Dreg.D = (inst_CLK_OUT_PRE.Q); + +CLK_OUT_PRE_Dreg.C = (CLK_OSZI); + +CIIN_0 = (inst_nEXP_SPACE_D0.Q & AS_030.PIN + # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & inst_nEXP_SPACE_D0.Q + # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q); + + +Reverse-Polarity Equations: + diff --git a/Logic/68030_tk.svl b/Logic/68030_tk.svl new file mode 100644 index 0000000..579ba2b --- /dev/null +++ b/Logic/68030_tk.svl @@ -0,0 +1,2 @@ +Part Number: M4A5-128/64-10VC +Need not generate svf file according to the constraints, exit diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal new file mode 100644 index 0000000..d267728 --- /dev/null +++ b/Logic/68030_tk.tal @@ -0,0 +1,136 @@ + + +Design Name = 68030_tk.tt4 +~~~~~~~~~~~~~~~~~~~~~~~~~~ + + +******************* +* TIMING ANALYSIS * +******************* + +Timing Analysis KEY: +One unit of delay time is equivalent to one pass + through the Central Switch Matrix. +.. Delay ( in this column ) not applicable to the indicated signal. +TSU, Set-Up Time ( 0 for input-paired signals ), + represents the number of switch matrix passes between + an input pin and a register setup before clock. + TSU is reported on the register. +TCO, Clocked Output-to-Pin Time ( 0 for output-paired signals ), + represents the number of switch matrix passes between + a clocked register and an output pin. + TCO is reported on the register. +TPD, Propagation Delay Time ( calculated only for combinatorial eqns.), + represents the number of switch matrix passes between + an input pin and an output pin. + TPD is reported on the output pin. +TCR, Clocked Output-to-Register Time, + represents the number of switch matrix passes between + a clocked register and the register it drives ( before clock ). + TCR is reported on the driving register. + + TSU TCO TPD TCR + #passes #passes #passes #passes +SIGNAL NAME min max min max min max min max +AMIGA_BUS_DATA_DIR .. .. .. .. 1 2 .. .. + DS_030 1 2 0 0 .. .. 1 1 + RN_DS_030 1 2 0 0 .. .. 1 1 + A0 1 2 0 0 .. .. .. .. + RW 1 2 0 0 .. .. 1 1 + RN_RW 1 2 0 0 .. .. 1 1 + inst_AS_000_INT 1 1 1 2 .. .. 2 2 +inst_AMIGA_BUS_ENABLE_DMA_HIGH 1 2 1 1 .. .. .. .. +inst_AMIGA_BUS_ENABLE_DMA_LOW 1 2 1 1 .. .. .. .. +inst_nEXP_SPACE_D0 1 1 1 1 .. .. 1 2 +inst_AS_030_000_SYNC 1 1 .. .. .. .. 1 2 + inst_AS_000_DMA 1 2 .. .. .. .. 1 1 + SIZE_DMA_0_ 1 2 1 1 .. .. 2 2 + SIZE_DMA_1_ 1 2 1 1 .. .. 2 2 +inst_UDS_000_INT 1 1 1 1 .. .. 2 2 +inst_LDS_000_INT 1 1 1 1 .. .. 2 2 + inst_DTACK_D0 1 2 .. .. .. .. 1 1 + inst_CLK_000_D1 .. .. .. .. .. .. 1 2 + inst_CLK_000_D0 1 1 .. .. .. .. 1 2 + SM_AMIGA_7_ 1 2 .. .. .. .. 1 1 + inst_CLK_000_PE .. .. .. .. .. .. 1 2 + inst_CLK_000_NE .. .. .. .. .. .. 1 2 + SM_AMIGA_6_ 1 1 .. .. .. .. 1 2 + SM_AMIGA_4_ 1 1 .. .. .. .. 1 2 + SM_AMIGA_0_ 1 1 .. .. .. .. 1 2 + inst_CLK_030_H 1 2 .. .. .. .. 1 1 +inst_DS_000_ENABLE 1 1 1 1 .. .. 2 2 + SM_AMIGA_1_ 1 1 .. .. .. .. 1 2 + SM_AMIGA_5_ 1 1 .. .. .. .. 1 2 + SM_AMIGA_3_ 1 1 .. .. .. .. 1 2 + SM_AMIGA_2_ 1 1 .. .. .. .. 1 2 + AS_000 .. .. .. .. 1 1 .. .. + UDS_000 .. .. .. .. 1 1 .. .. + LDS_000 .. .. .. .. 1 1 .. .. + FPU_CS .. .. .. .. 1 1 .. .. + DTACK .. .. .. .. 1 1 .. .. + CIIN .. .. .. .. 1 1 .. .. + IPL_030_2_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_2_ 1 1 0 0 .. .. 1 1 + IPL_030_1_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_1_ 1 1 0 0 .. .. 1 1 + RW_000 1 1 0 0 .. .. 1 1 + RN_RW_000 1 1 0 0 .. .. 1 1 + IPL_030_0_ 1 1 0 0 .. .. 1 1 + RN_IPL_030_0_ 1 1 0 0 .. .. 1 1 + BG_000 1 1 0 0 .. .. 1 1 + RN_BG_000 1 1 0 0 .. .. 1 1 + BGACK_030 1 1 0 1 .. .. 1 1 + RN_BGACK_030 1 1 0 1 .. .. 1 1 + DSACK1 1 1 0 0 .. .. 1 1 + RN_DSACK1 1 1 0 0 .. .. 1 1 + E .. .. 0 0 .. .. 1 1 + RN_E .. .. 0 0 .. .. 1 1 + VMA .. .. 0 0 .. .. 1 1 + RN_VMA .. .. 0 0 .. .. 1 1 + RESET .. .. 0 0 .. .. 1 1 + RN_RESET .. .. 0 0 .. .. 1 1 +AMIGA_ADDR_ENABLE .. .. 0 0 .. .. 1 1 +RN_AMIGA_ADDR_ENABLE .. .. 0 0 .. .. 1 1 + cpu_est_0_ .. .. .. .. .. .. 1 1 + cpu_est_1_ .. .. .. .. .. .. 1 1 + inst_AS_030_D0 1 1 1 1 .. .. 1 1 + inst_DS_030_D0 1 1 .. .. .. .. 1 1 +inst_BGACK_030_INT_D .. .. .. .. .. .. 1 1 + inst_VPA_D 1 1 .. .. .. .. 1 1 + RESET_DLY_7_ .. .. .. .. .. .. 1 1 +inst_CLK_OUT_PRE_50 .. .. .. .. .. .. 1 1 +sm_amiga_ns_0_3_0__n .. .. .. .. 1 1 .. .. +inst_CLK_OUT_PRE .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_9_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_11_ .. .. .. .. .. .. 1 1 + cpu_est_2_ .. .. .. .. .. .. 1 1 +inst_CLK_000_NE_D0 .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_0_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_1_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_2_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_3_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_4_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_5_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_6_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_7_ .. .. .. .. .. .. 1 1 +CLK_000_P_SYNC_8_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_0_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_1_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_2_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_3_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_4_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_5_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_6_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_7_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_8_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_9_ .. .. .. .. .. .. 1 1 +CLK_000_N_SYNC_10_ .. .. .. .. .. .. 1 1 + RESET_DLY_0_ .. .. .. .. .. .. 1 1 + RESET_DLY_1_ .. .. .. .. .. .. 1 1 + RESET_DLY_2_ .. .. .. .. .. .. 1 1 + RESET_DLY_3_ .. .. .. .. .. .. 1 1 + RESET_DLY_4_ .. .. .. .. .. .. 1 1 + RESET_DLY_5_ .. .. .. .. .. .. 1 1 + RESET_DLY_6_ .. .. .. .. .. .. 1 1 +CLK_OUT_PRE_Dreg .. .. 1 1 .. .. 1 1 + CIIN_0 .. .. .. .. 1 1 .. .. \ No newline at end of file diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco new file mode 100644 index 0000000..700b889 --- /dev/null +++ b/Logic/68030_tk.vco @@ -0,0 +1,269 @@ +[DEVICE] + +Family = M4A5; +PartType = M4A5-128/64; +Package = 100TQFP; +PartNumber = M4A5-128/64-10VC; +Speed = -10; +Operating_condition = COM; +EN_Segment = NO; +Pin_MC_1to1 = NO; +Voltage = 5.0; + +[REVISION] + +RCS = "$Revision: 1.2 $"; +Parent = m4a5.lci; +SDS_file = m4a5.sds; +Design = 68030_tk.tt4; +Rev = 0.01; +DATE = 10/10/14; +TIME = 22:40:09; +Type = TT2; +Pre_Fit_Time = 1; +Source_Format = Pure_VHDL; + +[IGNORE ASSIGNMENTS] + +Pin_Assignments = NO; +Pin_Keep_Block = NO; +Pin_Keep_Segment = NO; +Group_Assignments = NO; +Macrocell_Assignments = NO; +Macrocell_Keep_Block = NO; +Macrocell_Keep_Segment = NO; +Pin_Reservation = NO; +Timing_Constraints = NO; +Block_Reservation = NO; +Segment_Reservation = NO; +Ignore_Source_Location = NO; +Ignore_Source_Optimization = NO; +Ignore_Source_Timing = NO; + +[CLEAR ASSIGNMENTS] + +Pin_Assignments = NO; +Pin_Keep_Block = NO; +Pin_Keep_Segment = NO; +Group_Assignments = NO; +Macrocell_Assignments = NO; +Macrocell_Keep_Block = NO; +Macrocell_Keep_Segment = NO; +Pin_Reservation = NO; +Timing_Constraints = NO; +Block_Reservation = NO; +Segment_Reservation = NO; +Ignore_Source_Location = NO; +Ignore_Source_Optimization = NO; +Ignore_Source_Timing = NO; + +[BACKANNOTATE NETLIST] + +Netlist = VHDL; +Delay_File = SDF; +Generic_VCC = ; +Generic_GND = ; + +[BACKANNOTATE ASSIGNMENTS] + +Pin_Assignment = NO; +Pin_Block = NO; +Pin_Macrocell_Block = NO; +Routing = NO; + +[GLOBAL PROJECT OPTIMIZATION] + +Balanced_Partitioning = YES; +Spread_Placement = YES; +Max_Pin_Percent = 100; +Max_Macrocell_Percent = 100; +Max_Inter_Seg_Percent = 100; +Max_Seg_In_Percent = 100; +Max_Blk_In_Percent = 100; + +[FITTER REPORT FORMAT] + +Fitter_Options = YES; +Pinout_Diagram = NO; +Pinout_Listing = YES; +Detailed_Block_Segment_Summary = YES; +Input_Signal_List = YES; +Output_Signal_List = YES; +Bidir_Signal_List = YES; +Node_Signal_List = YES; +Signal_Fanout_List = YES; +Block_Segment_Fanin_List = YES; +Prefit_Eqn = YES; +Postfit_Eqn = YES; +Page_Break = YES; + +[OPTIMIZATION OPTIONS] + +Logic_Reduction = YES; +Max_PTerm_Split = 16; +Max_PTerm_Collapse = 16; +XOR_Synthesis = YES; +Node_Collapse = Yes; +DT_Synthesis = No; + +[FITTER GLOBAL OPTIONS] + +Run_Time = 0; +Set_Reset_Dont_Care = YES; +In_Reg_Optimize = YES; +Clock_Optimize = NO; +Conf_Unused_IOs = OUT_LOW; + +[POWER] +Powerlevel = Low, High; +Default = High; +Low = 8, H, G, F, E, D, C, B, A; +Type = GLB; + +[HARDWARE DEVICE OPTIONS] +Zero_Hold_Time = Yes; +Signature_Word = 0; +Pull_up = Yes; +Out_Slew_Rate = SLOW, FAST, 28, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, AMIGA_ADDR_ENABLE, + AMIGA_BUS_ENABLE_HIGH, AVEC, BG_000, LDS_000, UDS_000, DTACK, RW_000, AS_000, + CLK_DIV_OUT, CLK_EXP, FPU_CS, AS_030, RW, SIZE_1_, SIZE_0_, BGACK_030, + IPL_030_0_, IPL_030_1_, IPL_030_2_, RESET, CIIN, DS_030, BERR, A0, DSACK1; +Device_max_fanin = 33; +Device_max_pterms = 20; +Usercode_Format = Hex; + +[PIN RESERVATIONS] +layer = OFF; + +[LOCATION ASSIGNMENT] + +Layer = OFF; +A_27_ = INPUT,16, C,-; +A_26_ = INPUT,17, C,-; +SIZE_1_ = BIDIR,79, H,-; +A_25_ = INPUT,18, C,-; +A_24_ = INPUT,19, C,-; +A_31_ = INPUT,4, B,-; +A_23_ = INPUT,85, H,-; +A_22_ = INPUT,84, H,-; +A_21_ = INPUT,94, A,-; +A_20_ = INPUT,93, A,-; +IPL_2_ = INPUT,68, G,-; +A_19_ = INPUT,97, A,-; +A_18_ = INPUT,95, A,-; +FC_1_ = INPUT,58, F,-; +A_17_ = INPUT,59, F,-; +AS_030 = BIDIR,82, H,-; +A_16_ = INPUT,96, A,-; +AS_000 = BIDIR,42, E,-; +IPL_1_ = INPUT,56, F,-; +UDS_000 = BIDIR,32, D,-; +IPL_0_ = INPUT,67, G,-; +LDS_000 = BIDIR,31, D,-; +FC_0_ = INPUT,57, F,-; +A1 = INPUT,60, F,-; +nEXP_SPACE = INPUT,14,-,-; +BERR = BIDIR,41, E,-; +BG_030 = INPUT,21, C,-; +BGACK_000 = INPUT,28, D,-; +CLK_030 = INPUT,64,-,-; +CLK_000 = INPUT,11,-,-; +CLK_OSZI = INPUT,61,-,-; +CLK_DIV_OUT = OUTPUT,65, G,-; +CLK_EXP = OUTPUT,10, B,-; +FPU_CS = OUTPUT,78, H,-; +FPU_SENSE = INPUT,91, A,-; +DTACK = BIDIR,30, D,-; +AVEC = OUTPUT,92, A,-; +VPA = INPUT,36,-,-; +RST = INPUT,86,-,-; +AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-; +AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-; +AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-; +CIIN = OUTPUT,47, E,-; +SIZE_0_ = BIDIR,70, G,-; +A_30_ = INPUT,5, B,-; +A_29_ = INPUT,6, B,-; +A_28_ = INPUT,15, C,-; +IPL_030_2_ = OUTPUT,9, B,-; +IPL_030_1_ = OUTPUT,7, B,-; +RW_000 = BIDIR,80, H,-; +IPL_030_0_ = OUTPUT,8, B,-; +DS_030 = BIDIR,98, A,-; +A0 = BIDIR,69, G,-; +BG_000 = OUTPUT,29, D,-; +BGACK_030 = OUTPUT,83, H,-; +DSACK1 = BIDIR,81, H,-; +E = OUTPUT,66, G,-; +VMA = OUTPUT,35, D,-; +RESET = OUTPUT,3, B,-; +RW = BIDIR,71, G,-; +AMIGA_ADDR_ENABLE = OUTPUT,33, D,-; +cpu_est_0_ = NODE,6, D,-; +cpu_est_1_ = NODE,13, D,-; +inst_AS_000_INT = NODE,9, C,-; +inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,13, A,-; +inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,9, A,-; +inst_AS_030_D0 = NODE,9, H,-; +inst_nEXP_SPACE_D0 = NODE,5, B,-; +inst_DS_030_D0 = NODE,10, H,-; +inst_AS_030_000_SYNC = NODE,13, H,-; +inst_BGACK_030_INT_D = NODE,6, H,-; +inst_AS_000_DMA = NODE,5, G,-; +SIZE_DMA_0_ = NODE,2, G,-; +SIZE_DMA_1_ = NODE,9, G,-; +inst_VPA_D = NODE,10, F,-; +inst_UDS_000_INT = NODE,12, A,-; +inst_LDS_000_INT = NODE,8, A,-; +inst_DTACK_D0 = NODE,7, D,-; +RESET_DLY_7_ = NODE,14, B,-; +inst_CLK_OUT_PRE_50 = NODE,11, F,-; +inst_CLK_000_D1 = NODE,5, E,-; +inst_CLK_000_D0 = NODE,14, D,-; +sm_amiga_ns_0_3_0__n = NODE,13, C,-; +SM_AMIGA_7_ = NODE,0, F,-; +inst_CLK_OUT_PRE = NODE,7, F,-; +inst_CLK_000_PE = NODE,4, C,-; +CLK_000_P_SYNC_9_ = NODE,3, G,-; +inst_CLK_000_NE = NODE,8, E,-; +CLK_000_N_SYNC_11_ = NODE,10, A,-; +cpu_est_2_ = NODE,2, D,-; +inst_CLK_000_NE_D0 = NODE,10, D,-; +SM_AMIGA_6_ = NODE,12, C,-; +SM_AMIGA_4_ = NODE,5, C,-; +SM_AMIGA_0_ = NODE,4, F,-; +inst_CLK_030_H = NODE,5, A,-; +CLK_000_P_SYNC_0_ = NODE,6, E,-; +CLK_000_P_SYNC_1_ = NODE,10, B,-; +CLK_000_P_SYNC_2_ = NODE,6, A,-; +CLK_000_P_SYNC_3_ = NODE,14, G,-; +CLK_000_P_SYNC_4_ = NODE,6, B,-; +CLK_000_P_SYNC_5_ = NODE,14, C,-; +CLK_000_P_SYNC_6_ = NODE,10, C,-; +CLK_000_P_SYNC_7_ = NODE,6, C,-; +CLK_000_P_SYNC_8_ = NODE,3, F,-; +CLK_000_N_SYNC_0_ = NODE,2, E,-; +CLK_000_N_SYNC_1_ = NODE,10, G,-; +CLK_000_N_SYNC_2_ = NODE,2, B,-; +CLK_000_N_SYNC_3_ = NODE,6, G,-; +CLK_000_N_SYNC_4_ = NODE,3, D,-; +CLK_000_N_SYNC_5_ = NODE,13, B,-; +CLK_000_N_SYNC_6_ = NODE,2, A,-; +CLK_000_N_SYNC_7_ = NODE,14, F,-; +CLK_000_N_SYNC_8_ = NODE,1, A,-; +CLK_000_N_SYNC_9_ = NODE,13, E,-; +CLK_000_N_SYNC_10_ = NODE,2, H,-; +RESET_DLY_0_ = NODE,13, F,-; +RESET_DLY_1_ = NODE,9, F,-; +RESET_DLY_2_ = NODE,5, F,-; +RESET_DLY_3_ = NODE,1, F,-; +RESET_DLY_4_ = NODE,12, F,-; +RESET_DLY_5_ = NODE,13, G,-; +RESET_DLY_6_ = NODE,9, B,-; +inst_DS_000_ENABLE = NODE,1, C,-; +SM_AMIGA_1_ = NODE,8, C,-; +SM_AMIGA_5_ = NODE,2, C,-; +SM_AMIGA_3_ = NODE,2, F,-; +SM_AMIGA_2_ = NODE,6, F,-; +CLK_OUT_PRE_Dreg = NODE,8, F,-; +CIIN_0 = NODE,9, E,-; diff --git a/Logic/68030_tk.vct b/Logic/68030_tk.vct new file mode 100644 index 0000000..3586c79 --- /dev/null +++ b/Logic/68030_tk.vct @@ -0,0 +1,219 @@ +[DEVICE] +Family = M4A5; +PartType = M4A5-128/64; +Package = 100TQFP; +PartNumber = M4A5-128/64-10VC; +Speed = -10; +Operating_condition = COM; +EN_Segment = No; +Pin_MC_1to1 = No; +EN_PinReserve_IO = Yes; +EN_PinReserve_BIDIR = Yes; +Voltage = 5.0; + +[REVISION] +RCS = "$Revision: 1.2 $"; +Parent = m4a5.lci; +SDS_File = m4a5.sds; +DATE = 10/02/2014; +TIME = 23:53:03; +Source_Format = Pure_VHDL; +Type = TT2; +Pre_Fit_Time = 1; + +[IGNORE ASSIGNMENTS] +Pin_Assignments = No; +Pin_Keep_Block = No; +Pin_Keep_Segment = No; +Group_Assignments = No; +Macrocell_Assignments = No; +Macrocell_Keep_Block = No; +Macrocell_Keep_Segment = No; +Pin_Reservation = No; +Block_Reservation = No; +Segment_Reservation = No; +Timing_Constraints = No; + +[CLEAR ASSIGNMENTS] +Pin_Assignments = No; +Pin_Keep_Block = No; +Pin_Keep_Segment = No; +Group_Assignments = No; +Macrocell_Assignments = No; +Macrocell_Keep_Block = No; +Macrocell_Keep_Segment = No; +Pin_Reservation = No; +Block_Reservation = No; +Segment_Reservation = No; +Timing_Constraints = No; + +[BACKANNOTATE ASSIGNMENTS] +Pin_Block = No; +Pin_Macrocell_Block = No; +Routing = No; + +[GLOBAL PROJECT OPTIMIZATION] +Balanced_Partitioning = Yes; +Spread_Placement = Yes; +Max_Pin_Percent = 100; +Max_Macrocell_Percent = 100; +Max_Blk_In_Percent = 100; + +[OPTIMIZATION OPTIONS] +Logic_Reduction = Yes; +Max_PTerm_Split = 16; +Max_PTerm_Collapse = 16; +XOR_Synthesis = Yes; +EN_XOR_Synthesis = Yes; +XOR_Gate = Yes; +Node_Collapse = Yes; +Keep_XOR = Yes; +DT_Synthesis = No; +Clock_PTerm = Min; +Reset_PTerm = On; +Preset_PTerm = On; +Clock_Enable_PTerm = On; +Output_Enable_PTerm = On; +EN_DT_Synthesis = Yes; +Cluster_PTerm = 5; +FF_inv = No; +EN_Use_CE = No; +Use_CE = No; +Use_Internal_COM_FB = Yes; +EN_use_Internal_COM_FB = Yes; +Set_Reset_Swap = No; +EN_Set_Reset_Swap = No; +Density = No; +DeMorgan = Yes; +T_FF = Yes; +Max_Symbols = 32; + +[FITTER GLOBAL OPTIONS] +Run_Time = 0; +Set_Reset_Dont_Care = Yes; +EN_Set_Reset_Dont_Care = Yes; +In_Reg_Optimize = Yes; +EN_In_Reg_Optimize = No; +Clock_Optimize = No; +Global_Clock_As_Pterm = No; +Show_Iterations = No; +Routing_Attempts = 2; +Conf_Unused_IOs = Out_Low; + +[HARDWARE DEVICE OPTIONS] +Zero_Hold_Time = Yes; +Signature_Word = 0; +Pull_up = Yes; +Out_Slew_Rate = SLOW,FAST,28,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH,AVEC,BG_000,LDS_000,UDS_000,DTACK,RW_000,AS_000,CLK_DIV_OUT,CLK_EXP,FPU_CS,AS_030,RW,SIZE_1_,SIZE_0_,BGACK_030,IPL_030_0_,IPL_030_1_,IPL_030_2_,RESET,CIIN,DS_030,BERR,A0,DSACK1; +Device_max_fanin = 33; +Device_max_pterms = 20; +Usercode_Format = Hex; + +[PIN RESERVATIONS] +Layer = OFF; + +[LOCATION ASSIGNMENT] +Layer = OFF; +AS_030 = input,82,H,-; +A_16_ = input,96,A,-; +A_17_ = input,59,F,-; +A_18_ = input,95,A,-; +A_19_ = input,97,A,-; +BGACK_000 = input,28,D,-; +BG_030 = input,21,C,-; +CLK_000 = input,11,-,-; +CLK_030 = input,64,-,-; +CLK_OSZI = input,61,-,-; +FC_0_ = input,57,F,-; +FC_1_ = input,58,F,-; +IPL_0_ = input,67,G,-; +IPL_1_ = input,56,F,-; +IPL_2_ = input,68,G,-; +RST = input,86,-,-; +RW = input,71,G,-; +SIZE_1_ = input,79,H,-; +SIZE_0_ = input,70,G,-; +VPA = input,36,-,-; +AVEC = input,92,A,-; +BGACK_030 = input,83,H,-; +BG_000 = input,29,D,-; +CLK_DIV_OUT = input,65,G,-; +CLK_EXP = input,10,B,-; +E = input,66,G,-; +FPU_CS = input,78,H,-; +IPL_030_0_ = input,8,B,-; +IPL_030_1_ = input,7,B,-; +IPL_030_2_ = input,9,B,-; +LDS_000 = input,31,D,-; +UDS_000 = input,32,D,-; +DTACK = input,30,D,-; +RESET = input,3,B,-; +AMIGA_BUS_DATA_DIR = input,48,E,-; +AMIGA_BUS_ENABLE_LOW = input,20,C,-; +CIIN = input,47,E,-; +A_20_ = input,93,A,-; +A_21_ = input,94,A,-; +A_22_ = input,84,H,-; +A_24_ = input,19,C,-; +A_25_ = input,18,C,-; +A_26_ = input,17,C,-; +A_27_ = input,16,C,-; +A_28_ = input,15,C,-; +A_29_ = input,6,B,-; +A_30_ = input,5,B,-; +A_31_ = input,4,B,-; +DS_030 = input,98,A,-; +BERR = input,41,E,-; +nEXP_SPACE = input,14,-,-; +A0 = input,69,G,-; +DSACK1 = input,81,H,-; +RW_000 = input,80,H,-; +AS_000 = input,42,E,-; +AMIGA_ADDR_ENABLE = input,33,D,-; +AMIGA_BUS_ENABLE_HIGH = input,34,D,-; +A_23_ = input,85,H,-; +FPU_SENSE = input,91,A,-; +A1 = input,60,F,-; +VMA = input,35,D,-; + +[GROUP ASSIGNMENT] +Layer = OFF; + +[SPACE RESERVATIONS] +Layer = OFF; + +[BACKANNOTATE NETLIST] +Delay_File = SDF; +Netlist = VHDL; +VCC_GND = Cell; + +[FITTER REPORT FORMAT] +Fitter_Options = Yes; +Pinout_Diagram = No; +Pinout_Listing = Yes; +Detailed_Block_Segment_Summary = Yes; +Input_Signal_List = Yes; +Output_Signal_List = Yes; +Bidir_Signal_List = Yes; +Node_Signal_List = Yes; +Signal_Fanout_List = Yes; +Block_Segment_Fanin_List = Yes; +Postfit_Eqn = Yes; +Page_Break = Yes; + +[POWER] +Powerlevel = Low,High; +Default = High; +Low = 8,H,G,F,E,D,C,B,A; +Type = GLB; + +[SOURCE CONSTRAINT OPTION] +Import_source_constraint = Yes; +Disable_warning_message = No; + +[TIMING ANALYZER] +Last_source=; +Last_source_type=Fmax; + +[INPUT REGISTERS] + diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf new file mode 100644 index 0000000..f4fccac --- /dev/null +++ b/Logic/68030_tk.xrf @@ -0,0 +1,16 @@ +Signal Name Cross Reference File + +ispLEVER Classic 1.7.00.05.28.13 + +Design '68030_tk' created Fri Oct 10 22:40:03 2014 + + + LEGEND: '>' Functional Block Port Separator + '/' Hierarchy Path Separator + '@' Automatically Generated Node + + +Short Name Hierarchical Name +---------- ----------------- + + *** Shortened names not required for this design. *** diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi new file mode 100644 index 0000000..4458785 --- /dev/null +++ b/Logic/BUS68030.edi @@ -0,0 +1,3753 @@ +(edif BUS68030 + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timeStamp 2014 10 10 22 39 58) + (author "Synopsys, Inc.") + (program "Synplify Pro" (version "G-2012.09LC-SP1 , mapper maplat, Build 621R")) + ) + ) + (external mach + (edifLevel 0) + (technology (numberDefinition )) + (cell AND2 (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + ) + ) + ) + (cell BI_DIR (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port IO (direction INOUT)) + (port OE (direction INPUT)) + ) + ) + ) + (cell BUFTH (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port OE (direction INPUT)) + ) + ) + ) + (cell DFF (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port Q (direction OUTPUT)) + (port D (direction INPUT)) + (port CLK (direction INPUT)) + ) + ) + ) + (cell DFFRH (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port Q (direction OUTPUT)) + (port D (direction INPUT)) + (port CLK (direction INPUT)) + (port R (direction INPUT)) + ) + ) + ) + (cell DFFSH (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port Q (direction OUTPUT)) + (port D (direction INPUT)) + (port CLK (direction INPUT)) + (port S (direction INPUT)) + ) + ) + ) + (cell IBUF (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + ) + ) + ) + (cell INV (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + ) + ) + ) + (cell OBUF (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + ) + ) + ) + (cell OR2 (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + ) + ) + ) + (cell XOR2 (cellType GENERIC) + (view prim (viewType NETLIST) + (interface + (port O (direction OUTPUT)) + (port I0 (direction INPUT)) + (port I1 (direction INPUT)) + ) + ) + ) + ) + (library work + (edifLevel 0) + (technology (numberDefinition )) + (cell BUS68030 (cellType GENERIC) + (view behavioral (viewType NETLIST) + (interface + (port (array (rename size "SIZE(1:0)") 2) (direction INOUT)) + (port (array (rename a "A(31:16)") 16) (direction INPUT)) + (port (array (rename ipl_030 "IPL_030(2:0)") 3) (direction OUTPUT)) + (port (array (rename ipl "IPL(2:0)") 3) (direction INPUT)) + (port (array (rename fc "FC(1:0)") 2) (direction INPUT)) + (port AS_030 (direction INOUT)) + (port AS_000 (direction INOUT)) + (port RW_000 (direction INOUT)) + (port DS_030 (direction INOUT)) + (port UDS_000 (direction INOUT)) + (port LDS_000 (direction INOUT)) + (port A0 (direction INOUT)) + (port A1 (direction INPUT)) + (port nEXP_SPACE (direction INPUT)) + (port BERR (direction INOUT)) + (port BG_030 (direction INPUT)) + (port BG_000 (direction OUTPUT)) + (port BGACK_030 (direction OUTPUT)) + (port BGACK_000 (direction INPUT)) + (port CLK_030 (direction INPUT)) + (port CLK_000 (direction INPUT)) + (port CLK_OSZI (direction INPUT)) + (port CLK_DIV_OUT (direction OUTPUT)) + (port CLK_EXP (direction OUTPUT)) + (port FPU_CS (direction OUTPUT)) + (port FPU_SENSE (direction INPUT)) + (port DSACK1 (direction INOUT)) + (port DTACK (direction INOUT)) + (port AVEC (direction OUTPUT)) + (port E (direction OUTPUT)) + (port VPA (direction INPUT)) + (port VMA (direction OUTPUT)) + (port RST (direction INPUT)) + (port RESET (direction OUTPUT)) + (port RW (direction INOUT)) + (port AMIGA_ADDR_ENABLE (direction OUTPUT)) + (port AMIGA_BUS_DATA_DIR (direction OUTPUT)) + (port AMIGA_BUS_ENABLE_LOW (direction OUTPUT)) + (port AMIGA_BUS_ENABLE_HIGH (direction OUTPUT)) + (port CIIN (direction OUTPUT)) + ) + (contents + (instance (rename SM_AMIGA_1 "SM_AMIGA[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename IPL_030DFFSH_0 "IPL_030DFFSH[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename IPL_030DFFSH_1 "IPL_030DFFSH[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename IPL_030DFFSH_2 "IPL_030DFFSH[2]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_7 "SM_AMIGA[7]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SM_AMIGA_2 "SM_AMIGA[2]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename RESET_DLY_1 "RESET_DLY[1]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename RESET_DLY_2 "RESET_DLY[2]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename RESET_DLY_3 "RESET_DLY[3]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename RESET_DLY_4 "RESET_DLY[4]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename RESET_DLY_5 "RESET_DLY[5]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename RESET_DLY_6 "RESET_DLY[6]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename RESET_DLY_7 "RESET_DLY[7]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename SIZE_DMA_0 "SIZE_DMA[0]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename SIZE_DMA_1 "SIZE_DMA[1]") (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_8 "CLK_000_P_SYNC[8]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_0 "CLK_000_N_SYNC[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_1 "CLK_000_N_SYNC[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_2 "CLK_000_N_SYNC[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_3 "CLK_000_N_SYNC[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_4 "CLK_000_N_SYNC[4]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_5 "CLK_000_N_SYNC[5]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_6 "CLK_000_N_SYNC[6]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_7 "CLK_000_N_SYNC[7]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename RESET_DLY_0 "RESET_DLY[0]") (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_1 "CLK_000_P_SYNC[1]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_2 "CLK_000_P_SYNC[2]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_3 "CLK_000_P_SYNC[3]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_4 "CLK_000_P_SYNC[4]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_5 "CLK_000_P_SYNC[5]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_6 "CLK_000_P_SYNC[6]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance (rename CLK_000_P_SYNC_7 "CLK_000_P_SYNC[7]") (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AMIGA_BUS_ENABLE_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance LDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance VMA_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance UDS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance RESETDFFRH (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance BG_000DFFSH (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance BGACK_030_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance DS_000_ENABLE (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance DSACK1_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance RW_000_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance DS_000_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance AS_000_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance CLK_030_H (viewRef prim (cellRef DFFRH (libraryRef mach))) + ) + (instance AS_030_000_SYNC (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance A0_DMA (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance AMIGA_BUS_ENABLE_DMA_HIGH (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance AMIGA_BUS_ENABLE_DMA_LOW (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance RW_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance AS_000_INT (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance DS_030_D0 (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance AS_030_D0 (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance DTACK_D0 (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance CLK_OUT_PRE (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_000_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_000_PE (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_000_NE (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance nEXP_SPACE_D0 (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance BGACK_030_INT_D (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance CLK_OUT_PRE_50 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance VPA_D (viewRef prim (cellRef DFFSH (libraryRef mach))) + ) + (instance CLK_000_D1 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_000_NE_D0 (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance CLK_OUT_PRE_D (viewRef prim (cellRef DFF (libraryRef mach))) + ) + (instance AS_030 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance AS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance RW_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance DS_030 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance UDS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance LDS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename SIZE_0 "SIZE[0]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename SIZE_1 "SIZE[1]") (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename A_16 "A[16]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_17 "A[17]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_18 "A[18]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_19 "A[19]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_20 "A[20]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_21 "A[21]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_22 "A[22]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_23 "A[23]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_24 "A[24]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_25 "A[25]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_26 "A[26]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_27 "A[27]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_28 "A[28]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_29 "A[29]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_30 "A[30]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename A_31 "A[31]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance A0 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance A1 (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance nEXP_SPACE (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance BERR (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance BG_030 (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance BG_000 (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance BGACK_030 (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance BGACK_000 (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance CLK_030 (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance CLK_000 (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance CLK_OSZI (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance CLK_DIV_OUT (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance CLK_EXP (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance FPU_CS (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance FPU_SENSE (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename IPL_030_0 "IPL_030[0]") (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance (rename IPL_030_1 "IPL_030[1]") (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance (rename IPL_030_2 "IPL_030[2]") (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance (rename IPL_0 "IPL[0]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename IPL_1 "IPL[1]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename IPL_2 "IPL[2]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance DSACK1 (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance DTACK (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance AVEC (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance E (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance VPA (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance VMA (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance RST (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance RESET (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance RW (viewRef prim (cellRef BI_DIR (libraryRef mach))) ) + (instance (rename FC_0 "FC[0]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance (rename FC_1 "FC[1]") (viewRef prim (cellRef IBUF (libraryRef mach))) ) + (instance AMIGA_ADDR_ENABLE (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_HIGH (viewRef prim (cellRef OBUF (libraryRef mach))) ) + (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_0_a2_0_2 "pos_clk.cpu_est_11_i_0_a2_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_0_a2_1_2 "pos_clk.cpu_est_11_i_0_a2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_0_a2_2 "pos_clk.cpu_est_11_i_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_0_1_6 "SM_AMIGA_ns_0_0_a2_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_0_6 "SM_AMIGA_ns_0_0_a2_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_1_0_4 "SM_AMIGA_ns_0_0_a2_1_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_4 "SM_AMIGA_ns_0_0_a2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_1_2 "SM_AMIGA_ns_0_0_a2_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_2 "SM_AMIGA_ns_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_bg_030_0_0_a2_1 "state_machine.un8_bg_030_0_0_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_bg_030_0_0_a2 "state_machine.un8_bg_030_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un3_dtack_i_a2_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un3_dtack_i_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_A0_DMA_2_0_a2_1_a2_1 "state_machine.A0_DMA_2_0_a2_1_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_A0_DMA_2_0_a2_1_a2 "state_machine.A0_DMA_2_0_a2_1_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_0_a2_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_0_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_0_a2_0_1_2 "pos_clk.cpu_est_11_i_0_a2_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_1_sqmuxa_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_INT_1_sqmuxa_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_INT_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_1_3 "pos_clk.cpu_est_11_0_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_3 "pos_clk.cpu_est_11_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_1_1_0 "SM_AMIGA_ns_0_0_a2_1_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_1_0 "SM_AMIGA_ns_0_0_a2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_0_1_0 "SM_AMIGA_ns_0_0_a2_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_0_0 "SM_AMIGA_ns_0_0_a2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_1_0_0 "SM_AMIGA_ns_0_0_a2_1_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_0 "SM_AMIGA_ns_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_2_2_0 "SM_AMIGA_ns_0_0_a2_2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_2_3_0 "SM_AMIGA_ns_0_0_a2_2_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_2_0 "SM_AMIGA_ns_0_0_a2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_AS_030_D0_2_0_i_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_AS_030_D0_2_0_i_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_AS_030_D0_2_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_pe_0_a2_0_1 "state_machine.un10_clk_000_pe_0_a2_0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_pe_0_a2_0_2 "state_machine.un10_clk_000_pe_0_a2_0_2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_pe_0_a2_0 "state_machine.un10_clk_000_pe_0_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_0_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_0_0_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_0_0_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_0_0_a2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_0_0_a2_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_0_0_a2_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_pe_0_o2 "state_machine.un10_clk_000_pe_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_o2_1_1_0 "SM_AMIGA_ns_0_0_o2_1_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_o2_1_0 "SM_AMIGA_ns_0_0_o2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_1_0 "SM_AMIGA_ns_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_2_0 "SM_AMIGA_ns_0_0_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_3_0 "SM_AMIGA_ns_0_0_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_0 "SM_AMIGA_ns_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_1_1 "pos_clk.cpu_est_11_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_2_1 "pos_clk.cpu_est_11_0_0_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_1 "pos_clk.cpu_est_11_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un22_berr_0_a2_0_a2_1_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un22_berr_0_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_2_1_0 "SM_AMIGA_ns_0_0_a2_2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2_0_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance m10_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance m10_0_a2_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance m10_0_a2_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance m10_0_a2_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance m10_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_1_1_4 "SM_AMIGA_ns_0_0_a2_1_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_1_2_4 "SM_AMIGA_ns_0_0_a2_1_2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_1_4 "SM_AMIGA_ns_0_0_a2_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_o2_1_0_0 "SM_AMIGA_ns_0_0_o2_1_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_o2_0 "SM_AMIGA_ns_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i_0_o2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_pe_0_o2_1 "state_machine.un10_clk_000_pe_0_o2_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance A0_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance m8_e_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance m8_e_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance m8_e_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance m8_e_4 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance m8_e_5 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance m8_e_6 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance m8_e (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un11_ds_030_d0_1 "state_machine.un11_ds_030_d0_1") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un11_ds_030_d0 "state_machine.un11_ds_030_d0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2_0_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2_0_2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un21_fpu_cs_0_a2_0_3 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_198_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un5_ciin_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance m12_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_193_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_194_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_185_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_186_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_i_3 "pos_clk.cpu_est_11_0_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_178_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_181_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_176_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_177_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_pe_0_i "state_machine.un10_clk_000_pe_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_175_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RESET_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_260_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_i_1 "SM_AMIGA_ns_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_294_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_SIZE_DMA_5_0_0_i_1 "state_machine.SIZE_DMA_5_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_AMIGA_BUS_ENABLE_DMA_HIGH_2_0_0_i "state_machine.AMIGA_BUS_ENABLE_DMA_HIGH_2_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_AMIGA_BUS_ENABLE_DMA_LOW_2_0_0_i "state_machine.AMIGA_BUS_ENABLE_DMA_LOW_2_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_DS_000_DMA_3_0_0_i "state_machine.DS_000_DMA_3_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_257_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_0_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_256_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_254_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un8_bg_030_0_0_i "state_machine.un8_bg_030_0_0_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_265_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_266_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_i_6 "SM_AMIGA_ns_0_0_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_263_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_264_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_i_5 "SM_AMIGA_ns_0_0_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_235_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_262_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_i_4 "SM_AMIGA_ns_0_0_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_233_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_234_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_i_3 "SM_AMIGA_ns_0_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_232_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_i_2 "SM_AMIGA_ns_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_231_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_o2_i_3 "pos_clk.cpu_est_11_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_286_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_1_sqmuxa_1_i_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_275_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_AS_030_D0_2_0_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_4_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_as_030_d0_2_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_274_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_000_DMA_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_273_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_INT_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_270_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_272_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_267_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_a2_1_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_291_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_4_0_a2_1_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_o2_2_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_EXP_c_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_a2_1_o2_0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_o2_i_4 "SM_AMIGA_ns_0_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_0_o2_i_7 "SM_AMIGA_ns_i_0_0_o2_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_287_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_288_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_o2_0_i_4 "SM_AMIGA_ns_0_0_o2_0_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_o2_i_0 "SM_AMIGA_ns_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_0_o2_0_i_7 "SM_AMIGA_ns_i_0_0_o2_0_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_20_mux_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance m12_i_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RW_000_INT_1_sqmuxa_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_o2_1_i_0 "SM_AMIGA_ns_0_0_o2_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_o2_i_1 "pos_clk.cpu_est_11_0_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_0_o2_i_2 "pos_clk.cpu_est_11_i_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_o2_0_i_0 "SM_AMIGA_ns_0_0_o2_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename reset_delay_machine_un24_clk_000_ne_d0_0_o2_i "reset_delay_machine.un24_clk_000_ne_d0_0_o2_i") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename CLK_000_N_SYNC_i_9 "CLK_000_N_SYNC_i[9]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_292_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_i_1 "pos_clk.cpu_est_11_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_184_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_298_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_182_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_183_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_282_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_i_0 "SM_AMIGA_ns_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_269_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_281_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_276_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_279_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RESET_DLY_i_7 "RESET_DLY_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_amiga_bus_enable_low_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un21_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_99_0_x2 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_101_0_x2 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_103_0_x2 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_105_0_x2 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_107_0_x2 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance G_109_0_x2 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_x2_3 "pos_clk.cpu_est_11_0_0_x2[3]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_0_x2_0 "cpu_est_0_0_x2[0]") (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_184 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un22_berr_0_a2_0_a2_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_169_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_o2_2_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_4_0_a2_1_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_a2_1_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename reset_delay_machine_un24_clk_000_ne_d0_0_o2 "reset_delay_machine.un24_clk_000_ne_d0_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_o2_0_0 "SM_AMIGA_ns_0_0_o2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_0_o2_2 "pos_clk.cpu_est_11_i_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_o2_1 "pos_clk.cpu_est_11_0_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_INT_1_sqmuxa_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance m12_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_NE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_0_o2_0_7 "SM_AMIGA_ns_i_0_0_o2_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_97_0_x2 (viewRef prim (cellRef XOR2 (libraryRef mach))) ) + (instance un1_as_030_d0_2_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_AS_030_D0_2_0_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_1_sqmuxa_1_i_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_pe_0_o2_0 "state_machine.un10_clk_000_pe_0_o2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_o2_3 "pos_clk.cpu_est_11_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CLK_000_N_SYNC_2_0_o2_i_o2_0 "pos_clk.CLK_000_N_SYNC_2_0_o2_i_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance nEXP_SPACE_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_o2_0_4 "SM_AMIGA_ns_0_0_o2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_0_o2_7 "SM_AMIGA_ns_i_0_0_o2[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_o2_4 "SM_AMIGA_ns_0_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_a2_1_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_185 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_0_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_DS_000_DMA_3_0_0 "state_machine.DS_000_DMA_3_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance A1_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_AMIGA_BUS_ENABLE_DMA_LOW_2_0_0 "state_machine.AMIGA_BUS_ENABLE_DMA_LOW_2_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_AMIGA_BUS_ENABLE_DMA_HIGH_2_0_0 "state_machine.AMIGA_BUS_ENABLE_DMA_HIGH_2_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_SIZE_DMA_5_0_0_1 "state_machine.SIZE_DMA_5_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_1 "SM_AMIGA_ns_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_2 "SM_AMIGA_ns_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_3 "SM_AMIGA_ns_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_4 "SM_AMIGA_ns_0_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_5 "SM_AMIGA_ns_0_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_6 "SM_AMIGA_ns_0_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_0_7 "SM_AMIGA_ns_i_0_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_SIZE_DMA_5_0_0_a2_1 "state_machine.SIZE_DMA_5_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_186 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_A0_DMA_2_0_a2_1_a2_0 "state_machine.A0_DMA_2_0_a2_1_a2_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_a2_2_1 "pos_clk.cpu_est_11_0_0_a2_2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RESET_0_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_pe_0 "state_machine.un10_clk_000_pe_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_i_0_2 "pos_clk.cpu_est_11_i_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_95_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance m12_i (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_CLK_000_P_SYNC_2_0_a2_i_0 "pos_clk.CLK_000_P_SYNC_2_0_a2_i[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un8_bg_030_0_0 "state_machine.un8_bg_030_0_0") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_bgack_030_int_d_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_0_a2_7 "SM_AMIGA_ns_i_0_0_a2[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_i_0_0_a2_0_7 "SM_AMIGA_ns_i_0_0_a2_0[7]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_189 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AMIGA_BUS_DATA_DIR_0_0_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance RW_000_INT_1_sqmuxa_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DS_000_DMA_1_sqmuxa_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance CLK_000_PE_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance AS_000_DMA_1_sqmuxa_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_2_4 "SM_AMIGA_ns_0_0_a2_2[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_4_0_a2_1_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_a2_1_a2_0 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_109_i_i_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_187 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_188 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_un3_ds_030_d0_i_i_a2 "state_machine.un3_ds_030_d0_i_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un2_as_000_i_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_bgack_030_int_d_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_030_H_0_sqmuxa_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_1 "SM_AMIGA_ns_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_0_1 "SM_AMIGA_ns_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_3 "SM_AMIGA_ns_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_0_3 "SM_AMIGA_ns_0_0_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_0_4 "SM_AMIGA_ns_0_0_a2_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_5 "SM_AMIGA_ns_0_0_a2[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_0_5 "SM_AMIGA_ns_0_0_a2_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_ns_0_0_a2_6 "SM_AMIGA_ns_0_0_a2[6]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_a2_0_3 "pos_clk.cpu_est_11_0_0_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RESET_DLY_i_0 "RESET_DLY_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_95_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance m12_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un4_bgack_000_i_a2_0_a2 "state_machine.un4_bgack_000_i_a2_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un7_amiga_bus_enable_high_i_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance AMIGA_BUS_ENABLE_DMA_LOW_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un1_amiga_bus_enable_low_0_a2_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un1_SM_AMIGA_0_sqmuxa_4_0_a2_1_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance DSACK1_INT_1_sqmuxa_i_a2_1_a2 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance I_190 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename state_machine_RW_000_INT_5_i_a2_0_a2 "state_machine.RW_000_INT_5_i_a2_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_SIZE_DMA_5_i_a2_0_a2_0 "state_machine.SIZE_DMA_5_i_a2_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance un4_lds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_uds_000 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un6_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un8_size (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename state_machine_un10_clk_000_pe_0_a2 "state_machine.un10_clk_000_pe_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_a2_1 "pos_clk.cpu_est_11_0_0_a2[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_a2_0_1 "pos_clk.cpu_est_11_0_0_a2_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_a2_1_1 "pos_clk.cpu_est_11_0_0_a2_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_172_i_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename pos_clk_cpu_est_11_0_0_a2_3 "pos_clk.cpu_est_11_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_106 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_108 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_27 "A_i[27]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance I_192 (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_lds_000_1 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance RST_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance G_96 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_98 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_100 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_102 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance G_104 (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance N_135_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_r "DS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename CLK_030_H_0_r "CLK_030_H_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename CLK_030_H_0_m "CLK_030_H_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_030_H_0_n "CLK_030_H_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename CLK_030_H_0_p "CLK_030_H_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_INT_0_r "AMIGA_BUS_ENABLE_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_INT_0_m "AMIGA_BUS_ENABLE_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_INT_0_n "AMIGA_BUS_ENABLE_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AMIGA_BUS_ENABLE_INT_0_p "AMIGA_BUS_ENABLE_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance un6_size_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un8_size_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_255_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_uds_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance un4_lds_000_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance N_134_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_165_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_r "DS_000_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_m "DS_000_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_n "DS_000_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DS_000_ENABLE_0_p "DS_000_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance N_132_i (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename DSACK1_INT_0_p "DSACK1_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_r "RW_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_m "RW_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_n "RW_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach))) ) + (instance (rename RW_000_DMA_0_p "RW_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach))) ) + (net BGACK_030_INT (joined + (portRef Q (instanceRef BGACK_030_INT)) + (portRef I0 (instanceRef BGACK_030_INT_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a2)) + (portRef I0 (instanceRef un1_bgack_030_int_d_i_0)) + (portRef I0 (instanceRef BGACK_030_INT_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_0_a2_0_a2_1)) + (portRef OE (instanceRef AS_000)) + (portRef I0 (instanceRef BGACK_030)) + (portRef D (instanceRef BGACK_030_INT_D)) + (portRef OE (instanceRef LDS_000)) + (portRef OE (instanceRef RW_000)) + (portRef OE (instanceRef UDS_000)) + )) + (net VCC (joined + (portRef I0 (instanceRef AVEC)) + )) + (net (rename cpu_est_3 "cpu_est[3]") (joined + (portRef Q (instanceRef cpu_est_3)) + (portRef I0 (instanceRef cpu_est_0_3__n)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_a2_1_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_a2_0_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_o2_3)) + (portRef I0 (instanceRef cpu_est_i_3)) + (portRef I0 (instanceRef E)) + )) + (net VMA_INT (joined + (portRef Q (instanceRef VMA_INT)) + (portRef I0 (instanceRef VMA_INT_0_n)) + (portRef I0 (instanceRef VMA_INT_i)) + (portRef I0 (instanceRef VMA)) + )) + (net AMIGA_BUS_ENABLE_INT (joined + (portRef Q (instanceRef AMIGA_BUS_ENABLE_INT)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_0_m)) + (portRef I0 (instanceRef AMIGA_ADDR_ENABLE)) + )) + (net (rename cpu_est_0 "cpu_est[0]") (joined + (portRef Q (instanceRef cpu_est_0)) + (portRef I0 (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_a2_2_1)) + (portRef I1 (instanceRef cpu_est_0_0_x2_0)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_x2_3)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_0_a2_1_2)) + )) + (net (rename cpu_est_1 "cpu_est[1]") (joined + (portRef Q (instanceRef cpu_est_1)) + (portRef I0 (instanceRef cpu_est_0_1__n)) + (portRef I0 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_i_0_o2_2)) + (portRef I0 (instanceRef cpu_est_i_1)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_x2_3)) + (portRef I1 (instanceRef state_machine_un10_clk_000_pe_0_o2_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_i_0_a2_0_1_2)) + )) + (net AS_000_INT (joined + (portRef Q (instanceRef AS_000_INT)) + (portRef I0 (instanceRef AS_000_INT_0_n)) + (portRef I0 (instanceRef AS_000_INT_i)) + )) + (net AMIGA_BUS_ENABLE_DMA_HIGH (joined + (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) + (portRef I0 (instanceRef un7_amiga_bus_enable_high_i_a2_0_a2)) + )) + (net AMIGA_BUS_ENABLE_DMA_LOW (joined + (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) + )) + (net AS_030_D0 (joined + (portRef Q (instanceRef AS_030_D0)) + (portRef I0 (instanceRef AS_030_D0_i)) + (portRef I0 (instanceRef state_machine_un8_bg_030_0_0_a2_1)) + )) + (net nEXP_SPACE_D0 (joined + (portRef Q (instanceRef nEXP_SPACE_D0)) + (portRef I1 (instanceRef m12_i_a2)) + (portRef I0 (instanceRef nEXP_SPACE_D0_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_o2_0)) + (portRef I1 (instanceRef un1_AS_030_D0_2_0_i_a2_2)) + (portRef I1 (instanceRef state_machine_un8_bg_030_0_0_a2)) + (portRef OE (instanceRef DSACK1)) + )) + (net DS_030_D0 (joined + (portRef Q (instanceRef DS_030_D0)) + (portRef I0 (instanceRef DS_030_D0_i)) + )) + (net AS_030_000_SYNC (joined + (portRef Q (instanceRef AS_030_000_SYNC)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_n)) + (portRef I0 (instanceRef AS_030_000_SYNC_i)) + )) + (net BGACK_030_INT_D (joined + (portRef Q (instanceRef BGACK_030_INT_D)) + (portRef I0 (instanceRef un1_bgack_030_int_d_i_0_a2)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_0_a2_0_a2_1)) + )) + (net AS_000_DMA (joined + (portRef Q (instanceRef AS_000_DMA)) + (portRef I0 (instanceRef AS_000_DMA_0_n)) + (portRef I0 (instanceRef AS_000_DMA_i)) + )) + (net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined + (portRef Q (instanceRef SIZE_DMA_0)) + (portRef I0 (instanceRef un8_size)) + (portRef I0 (instanceRef SIZE_DMA_i_0)) + )) + (net (rename SIZE_DMA_1 "SIZE_DMA[1]") (joined + (portRef Q (instanceRef SIZE_DMA_1)) + (portRef I0 (instanceRef SIZE_DMA_i_1)) + (portRef I0 (instanceRef un6_size)) + )) + (net VPA_D (joined + (portRef Q (instanceRef VPA_D)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_2_4)) + (portRef I0 (instanceRef VPA_D_i)) + )) + (net UDS_000_INT (joined + (portRef Q (instanceRef UDS_000_INT)) + (portRef I0 (instanceRef UDS_000_INT_0_n)) + (portRef I0 (instanceRef UDS_000_INT_i)) + )) + (net LDS_000_INT (joined + (portRef Q (instanceRef LDS_000_INT)) + (portRef I0 (instanceRef LDS_000_INT_0_n)) + (portRef I0 (instanceRef LDS_000_INT_i)) + )) + (net DTACK_D0 (joined + (portRef Q (instanceRef DTACK_D0)) + (portRef I0 (instanceRef DTACK_D0_i)) + )) + (net (rename RESET_DLY_7 "RESET_DLY[7]") (joined + (portRef Q (instanceRef RESET_DLY_7)) + (portRef I1 (instanceRef G_109_0_x2)) + (portRef I0 (instanceRef RESET_DLY_i_7)) + )) + (net CLK_OUT_PRE_50 (joined + (portRef Q (instanceRef CLK_OUT_PRE_50)) + (portRef I0 (instanceRef CLK_OUT_PRE_50_i)) + (portRef D (instanceRef CLK_OUT_PRE)) + )) + (net CLK_000_D1 (joined + (portRef Q (instanceRef CLK_000_D1)) + (portRef I1 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_o2_i_o2_0)) + (portRef I0 (instanceRef CLK_000_D1_i)) + )) + (net CLK_000_D0 (joined + (portRef Q (instanceRef CLK_000_D0)) + (portRef I0 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_i_0)) + (portRef I0 (instanceRef CLK_000_D0_i)) + (portRef I1 (instanceRef state_machine_un8_bg_030_0_0_a2_1)) + (portRef D (instanceRef CLK_000_D1)) + )) + (net (rename SM_AMIGA_7 "SM_AMIGA[7]") (joined + (portRef Q (instanceRef SM_AMIGA_7)) + (portRef I0 (instanceRef SM_AMIGA_i_7)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_0_1)) + (portRef I0 (instanceRef un1_AS_030_D0_2_0_i_a2_2)) + )) + (net GND (joined + (portRef I0 (instanceRef AS_030)) + (portRef I0 (instanceRef BERR)) + )) + (net CLK_OUT_PRE (joined + (portRef Q (instanceRef CLK_OUT_PRE)) + (portRef D (instanceRef CLK_OUT_PRE_D)) + )) + (net CLK_000_PE (joined + (portRef Q (instanceRef CLK_000_PE)) + (portRef I0 (instanceRef state_machine_un10_clk_000_pe_0_a2)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_4_0_a2_1_a2)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_0_4)) + (portRef I0 (instanceRef N_109_i_i_a2_0_a2)) + (portRef I0 (instanceRef CLK_000_PE_i)) + (portRef I0 (instanceRef RW_000_INT_1_sqmuxa_i_0_a2)) + )) + (net (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_9)) + (portRef D (instanceRef CLK_000_PE)) + )) + (net CLK_000_NE (joined + (portRef Q (instanceRef CLK_000_NE)) + (portRef I1 (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef IPL_030_0_2__m)) + (portRef I0 (instanceRef IPL_030_0_2__r)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_0_o2_0_7)) + (portRef I0 (instanceRef CLK_000_NE_i)) + (portRef I0 (instanceRef state_machine_un10_clk_000_pe_0_a2_0_1)) + (portRef D (instanceRef CLK_000_NE_D0)) + )) + (net (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_11)) + (portRef D (instanceRef CLK_000_NE)) + )) + (net (rename cpu_est_2 "cpu_est[2]") (joined + (portRef Q (instanceRef cpu_est_2)) + (portRef I0 (instanceRef cpu_est_0_2__n)) + (portRef I0 (instanceRef state_machine_un10_clk_000_pe_0_o2_0)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_0_o2_2)) + (portRef I0 (instanceRef cpu_est_i_2)) + (portRef I1 (instanceRef state_machine_un10_clk_000_pe_0_a2_0_2)) + )) + (net CLK_000_NE_D0 (joined + (portRef Q (instanceRef CLK_000_NE_D0)) + (portRef I1 (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_0_3__r)) + (portRef I1 (instanceRef cpu_est_0_2__m)) + (portRef I0 (instanceRef cpu_est_0_2__r)) + (portRef I1 (instanceRef cpu_est_0_1__m)) + (portRef I0 (instanceRef cpu_est_0_1__r)) + (portRef I0 (instanceRef reset_delay_machine_un24_clk_000_ne_d0_0_o2)) + (portRef I0 (instanceRef cpu_est_0_0_x2_0)) + )) + (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined + (portRef Q (instanceRef SM_AMIGA_6)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_1)) + (portRef I1 (instanceRef state_machine_un3_ds_030_d0_i_i_a2)) + (portRef I1 (instanceRef N_109_i_i_a2_0_a2)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_4_0_a2_1_a2_0)) + (portRef I0 (instanceRef SM_AMIGA_i_6)) + )) + (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined + (portRef Q (instanceRef SM_AMIGA_4)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_0_4)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_0_3)) + (portRef I0 (instanceRef SM_AMIGA_i_4)) + )) + (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined + (portRef Q (instanceRef SM_AMIGA_0)) + (portRef I1 (instanceRef RW_000_INT_1_sqmuxa_i_0_a2)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_0_a2_0_7)) + (portRef I0 (instanceRef SM_AMIGA_i_0)) + )) + (net CLK_030_H (joined + (portRef Q (instanceRef CLK_030_H)) + (portRef I0 (instanceRef CLK_030_H_0_n)) + (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_i_0_a2)) + )) + (net RW_000_INT (joined + (portRef Q (instanceRef RW_000_INT)) + (portRef I0 (instanceRef RW_000_INT_0_n)) + (portRef I0 (instanceRef RW_000)) + )) + (net DSACK1_INT (joined + (portRef Q (instanceRef DSACK1_INT)) + (portRef I0 (instanceRef DSACK1_INT_0_n)) + (portRef I0 (instanceRef DSACK1)) + )) + (net un1_amiga_bus_enable_low (joined + (portRef O (instanceRef un1_amiga_bus_enable_low_0_a2_0_a2)) + (portRef I0 (instanceRef un1_amiga_bus_enable_low_i)) + )) + (net un6_size (joined + (portRef O (instanceRef un6_size)) + (portRef I0 (instanceRef un6_size_i)) + )) + (net un8_size (joined + (portRef O (instanceRef un8_size)) + (portRef I0 (instanceRef un8_size_i)) + )) + (net RW_000_DMA (joined + (portRef Q (instanceRef RW_000_DMA)) + (portRef I0 (instanceRef RW_000_DMA_0_n)) + (portRef I0 (instanceRef RW)) + )) + (net (rename state_machine_un8_bg_030 "state_machine.un8_bg_030") (joined + (portRef O (instanceRef state_machine_un8_bg_030_0_0_i)) + (portRef I1 (instanceRef BG_000_0_m)) + (portRef I0 (instanceRef BG_000_0_r)) + )) + (net (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_0)) + (portRef D (instanceRef CLK_000_P_SYNC_1)) + )) + (net (rename CLK_000_P_SYNC_1 "CLK_000_P_SYNC[1]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_1)) + (portRef D (instanceRef CLK_000_P_SYNC_2)) + )) + (net (rename CLK_000_P_SYNC_2 "CLK_000_P_SYNC[2]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_2)) + (portRef D (instanceRef CLK_000_P_SYNC_3)) + )) + (net (rename CLK_000_P_SYNC_3 "CLK_000_P_SYNC[3]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_3)) + (portRef D (instanceRef CLK_000_P_SYNC_4)) + )) + (net (rename CLK_000_P_SYNC_4 "CLK_000_P_SYNC[4]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_4)) + (portRef D (instanceRef CLK_000_P_SYNC_5)) + )) + (net (rename CLK_000_P_SYNC_5 "CLK_000_P_SYNC[5]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_5)) + (portRef D (instanceRef CLK_000_P_SYNC_6)) + )) + (net (rename CLK_000_P_SYNC_6 "CLK_000_P_SYNC[6]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_6)) + (portRef D (instanceRef CLK_000_P_SYNC_7)) + )) + (net (rename CLK_000_P_SYNC_7 "CLK_000_P_SYNC[7]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_7)) + (portRef D (instanceRef CLK_000_P_SYNC_8)) + )) + (net (rename CLK_000_P_SYNC_8 "CLK_000_P_SYNC[8]") (joined + (portRef Q (instanceRef CLK_000_P_SYNC_8)) + (portRef D (instanceRef CLK_000_P_SYNC_9)) + )) + (net (rename CLK_000_N_SYNC_0 "CLK_000_N_SYNC[0]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_0)) + (portRef D (instanceRef CLK_000_N_SYNC_1)) + )) + (net (rename CLK_000_N_SYNC_1 "CLK_000_N_SYNC[1]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_1)) + (portRef D (instanceRef CLK_000_N_SYNC_2)) + )) + (net (rename CLK_000_N_SYNC_2 "CLK_000_N_SYNC[2]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_2)) + (portRef D (instanceRef CLK_000_N_SYNC_3)) + )) + (net (rename CLK_000_N_SYNC_3 "CLK_000_N_SYNC[3]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_3)) + (portRef D (instanceRef CLK_000_N_SYNC_4)) + )) + (net (rename CLK_000_N_SYNC_4 "CLK_000_N_SYNC[4]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_4)) + (portRef D (instanceRef CLK_000_N_SYNC_5)) + )) + (net (rename CLK_000_N_SYNC_5 "CLK_000_N_SYNC[5]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_5)) + (portRef D (instanceRef CLK_000_N_SYNC_6)) + )) + (net (rename CLK_000_N_SYNC_6 "CLK_000_N_SYNC[6]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_6)) + (portRef D (instanceRef CLK_000_N_SYNC_7)) + )) + (net (rename CLK_000_N_SYNC_7 "CLK_000_N_SYNC[7]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_7)) + (portRef D (instanceRef CLK_000_N_SYNC_8)) + )) + (net (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_8)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_a2_1_a2_0)) + (portRef D (instanceRef CLK_000_N_SYNC_9)) + )) + (net (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_9)) + (portRef I0 (instanceRef CLK_000_N_SYNC_i_9)) + (portRef D (instanceRef CLK_000_N_SYNC_10)) + )) + (net (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (joined + (portRef Q (instanceRef CLK_000_N_SYNC_10)) + (portRef D (instanceRef CLK_000_N_SYNC_11)) + )) + (net (rename RESET_DLY_0 "RESET_DLY[0]") (joined + (portRef Q (instanceRef RESET_DLY_0)) + (portRef I1 (instanceRef G_96)) + (portRef I0 (instanceRef RESET_DLY_i_0)) + (portRef I0 (instanceRef RESET_0_0_a2_1)) + )) + (net (rename RESET_DLY_1 "RESET_DLY[1]") (joined + (portRef Q (instanceRef RESET_DLY_1)) + (portRef I1 (instanceRef G_98)) + (portRef I1 (instanceRef G_97_0_x2)) + (portRef I1 (instanceRef RESET_0_0_a2_1)) + )) + (net (rename RESET_DLY_2 "RESET_DLY[2]") (joined + (portRef Q (instanceRef RESET_DLY_2)) + (portRef I1 (instanceRef G_100)) + (portRef I1 (instanceRef G_99_0_x2)) + (portRef I0 (instanceRef RESET_0_0_a2_2)) + )) + (net (rename RESET_DLY_3 "RESET_DLY[3]") (joined + (portRef Q (instanceRef RESET_DLY_3)) + (portRef I1 (instanceRef G_102)) + (portRef I1 (instanceRef G_101_0_x2)) + (portRef I1 (instanceRef RESET_0_0_a2_2)) + )) + (net (rename RESET_DLY_4 "RESET_DLY[4]") (joined + (portRef Q (instanceRef RESET_DLY_4)) + (portRef I1 (instanceRef G_104)) + (portRef I1 (instanceRef G_103_0_x2)) + (portRef I0 (instanceRef RESET_0_0_a2_3)) + )) + (net (rename RESET_DLY_5 "RESET_DLY[5]") (joined + (portRef Q (instanceRef RESET_DLY_5)) + (portRef I1 (instanceRef G_106)) + (portRef I1 (instanceRef G_105_0_x2)) + (portRef I1 (instanceRef RESET_0_0_a2_3)) + )) + (net (rename RESET_DLY_6 "RESET_DLY[6]") (joined + (portRef Q (instanceRef RESET_DLY_6)) + (portRef I1 (instanceRef G_108)) + (portRef I1 (instanceRef G_107_0_x2)) + (portRef I0 (instanceRef RESET_0_0_a2_4)) + )) + (net un5_ciin (joined + (portRef O (instanceRef m10_0_a2)) + (portRef I0 (instanceRef un5_ciin_i)) + (portRef I0 (instanceRef CIIN)) + )) + (net DS_000_DMA (joined + (portRef Q (instanceRef DS_000_DMA)) + (portRef I0 (instanceRef DS_000_DMA_0_n)) + (portRef I0 (instanceRef DS_030)) + )) + (net A0_DMA (joined + (portRef Q (instanceRef A0_DMA)) + (portRef I0 (instanceRef A0)) + )) + (net un1_SM_AMIGA_0_sqmuxa_4 (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_4_0_a2_1_a2)) + (portRef I0 (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_4_i)) + )) + (net AMIGA_BUS_ENABLE_INT_1_sqmuxa_1 (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_0_a2_0_a2)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_0_r)) + )) + (net (rename state_machine_un10_clk_000_pe "state_machine.un10_clk_000_pe") (joined + (portRef O (instanceRef state_machine_un10_clk_000_pe_0_i)) + (portRef I1 (instanceRef VMA_INT_0_m)) + (portRef I0 (instanceRef VMA_INT_0_r)) + )) + (net un4_uds_000 (joined + (portRef O (instanceRef un4_uds_000)) + (portRef I0 (instanceRef un4_uds_000_i)) + )) + (net DS_000_ENABLE (joined + (portRef Q (instanceRef DS_000_ENABLE)) + (portRef I0 (instanceRef DS_000_ENABLE_0_n)) + (portRef I0 (instanceRef un4_lds_000_1)) + )) + (net un4_lds_000 (joined + (portRef O (instanceRef un4_lds_000)) + (portRef I0 (instanceRef un4_lds_000_i)) + )) + (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined + (portRef Q (instanceRef SM_AMIGA_1)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_a2_1_a2)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_0_o2_0_7)) + (portRef I0 (instanceRef SM_AMIGA_i_1)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_0_6)) + )) + (net un21_fpu_cs (joined + (portRef O (instanceRef un21_fpu_cs_0_a2_0_a2)) + (portRef I0 (instanceRef un21_fpu_cs_i)) + )) + (net un22_berr (joined + (portRef O (instanceRef un22_berr_0_a2_0_a2)) + (portRef OE (instanceRef BERR)) + )) + (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined + (portRef Q (instanceRef SM_AMIGA_5)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_3)) + (portRef I0 (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_2)) + )) + (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined + (portRef Q (instanceRef SM_AMIGA_3)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_5)) + (portRef I0 (instanceRef SM_AMIGA_i_3)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_1_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_4)) + )) + (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined + (portRef Q (instanceRef SM_AMIGA_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_6)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_0_5)) + (portRef I0 (instanceRef SM_AMIGA_i_2)) + )) + (net (rename state_machine_un3_as_030_d0 "state_machine.un3_as_030_d0") (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_o2_2_o2_i)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_m)) + )) + (net (rename state_machine_AMIGA_BUS_ENABLE_DMA_LOW_2 "state_machine.AMIGA_BUS_ENABLE_DMA_LOW_2") (joined + (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_DMA_LOW_2_0_0_i)) + (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) + )) + (net (rename state_machine_AMIGA_BUS_ENABLE_DMA_HIGH_2 "state_machine.AMIGA_BUS_ENABLE_DMA_HIGH_2") (joined + (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_DMA_HIGH_2_0_0_i)) + (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) + )) + (net (rename state_machine_A0_DMA_2 "state_machine.A0_DMA_2") (joined + (portRef O (instanceRef state_machine_A0_DMA_2_0_a2_1_a2)) + (portRef D (instanceRef A0_DMA)) + )) + (net (rename state_machine_DS_000_DMA_3 "state_machine.DS_000_DMA_3") (joined + (portRef O (instanceRef state_machine_DS_000_DMA_3_0_0_i)) + (portRef I0 (instanceRef DS_000_DMA_0_m)) + )) + (net (rename state_machine_RW_000_DMA_3 "state_machine.RW_000_DMA_3") (joined + (portRef O (instanceRef DS_000_DMA_1_sqmuxa_1_i_0_0_i)) + (portRef I0 (instanceRef RW_000_DMA_0_m)) + )) + (net (rename state_machine_SIZE_DMA_5_1 "state_machine.SIZE_DMA_5[1]") (joined + (portRef O (instanceRef state_machine_SIZE_DMA_5_0_0_i_1)) + (portRef D (instanceRef SIZE_DMA_1)) + )) + (net N_1 (joined + (portRef O (instanceRef RW_000_INT_0_p)) + (portRef D (instanceRef RW_000_INT)) + )) + (net N_2 (joined + (portRef O (instanceRef AS_000_INT_0_p)) + (portRef D (instanceRef AS_000_INT)) + )) + (net N_3 (joined + (portRef O (instanceRef DS_000_ENABLE_0_p)) + (portRef D (instanceRef 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)) + (net N_13 (joined + (portRef O (instanceRef UDS_000_INT_0_p)) + (portRef D (instanceRef UDS_000_INT)) + )) + (net N_14 (joined + (portRef O (instanceRef RESET_0_0_i)) + (portRef D (instanceRef RESETDFFRH)) + )) + (net N_15 (joined + (portRef O (instanceRef BG_000_0_p)) + (portRef D (instanceRef BG_000DFFSH)) + )) + (net N_16 (joined + (portRef O (instanceRef BGACK_030_INT_0_p)) + (portRef D (instanceRef BGACK_030_INT)) + )) + (net N_18 (joined + (portRef O (instanceRef cpu_est_0_1__p)) + (portRef D (instanceRef cpu_est_1)) + )) + (net N_19 (joined + (portRef O (instanceRef cpu_est_0_2__p)) + (portRef D (instanceRef cpu_est_2)) + )) + (net N_20 (joined + (portRef O (instanceRef cpu_est_0_3__p)) + (portRef D (instanceRef cpu_est_3)) + )) + (net N_21 (joined + (portRef O (instanceRef IPL_030_0_0__p)) + (portRef D (instanceRef IPL_030DFFSH_0)) + )) + (net N_22 (joined + (portRef O (instanceRef IPL_030_0_1__p)) + (portRef D (instanceRef IPL_030DFFSH_1)) + )) + (net N_23 (joined + (portRef O (instanceRef IPL_030_0_2__p)) + (portRef D (instanceRef IPL_030DFFSH_2)) + )) + (net (rename SM_AMIGA_ns_0 "SM_AMIGA_ns[0]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_i_0)) + (portRef D (instanceRef SM_AMIGA_7)) + )) + (net (rename SM_AMIGA_ns_1 "SM_AMIGA_ns[1]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_i_1)) + (portRef D (instanceRef SM_AMIGA_6)) + )) + (net (rename SM_AMIGA_ns_2 "SM_AMIGA_ns[2]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_i_2)) + (portRef D (instanceRef SM_AMIGA_5)) + )) + (net (rename SM_AMIGA_ns_3 "SM_AMIGA_ns[3]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_i_3)) + (portRef D (instanceRef SM_AMIGA_4)) + )) + (net (rename SM_AMIGA_ns_4 "SM_AMIGA_ns[4]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_i_4)) + (portRef D (instanceRef SM_AMIGA_3)) + )) + (net (rename SM_AMIGA_ns_5 "SM_AMIGA_ns[5]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_i_5)) + (portRef D (instanceRef SM_AMIGA_2)) + )) + (net (rename SM_AMIGA_ns_6 "SM_AMIGA_ns[6]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_i_6)) + (portRef D (instanceRef SM_AMIGA_1)) + )) + (net (rename pos_clk_cpu_est_11_1 "pos_clk.cpu_est_11[1]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_i_1)) + (portRef I0 (instanceRef cpu_est_0_1__m)) + )) + (net (rename pos_clk_cpu_est_11_3 "pos_clk.cpu_est_11[3]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_i_3)) + (portRef I0 (instanceRef cpu_est_0_3__m)) + )) + (net N_194 (joined + (portRef O (instanceRef G_96)) + (portRef I0 (instanceRef G_98)) + (portRef I0 (instanceRef G_97_0_x2)) + (portRef I0 (instanceRef N_194_i)) + )) + (net N_152 (joined + (portRef O (instanceRef G_98)) + (portRef I0 (instanceRef G_100)) + (portRef I0 (instanceRef G_99_0_x2)) + )) + (net N_154 (joined + (portRef O (instanceRef G_100)) + (portRef I0 (instanceRef G_102)) + (portRef I0 (instanceRef G_101_0_x2)) + )) + (net N_156 (joined + (portRef O (instanceRef G_102)) + (portRef I0 (instanceRef G_104)) + (portRef I0 (instanceRef G_103_0_x2)) + )) + (net N_158 (joined + (portRef O (instanceRef G_104)) + (portRef I0 (instanceRef G_106)) + (portRef I0 (instanceRef G_105_0_x2)) + )) + (net N_160 (joined + (portRef O (instanceRef G_106)) + (portRef I0 (instanceRef G_108)) + (portRef I0 (instanceRef G_107_0_x2)) + )) + (net N_162 (joined + (portRef O (instanceRef G_108)) + (portRef I0 (instanceRef G_109_0_x2)) + )) + (net (rename state_machine_un8_bgack_030_int_i_0 "state_machine.un8_bgack_030_int_i_0") (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_0_o2_i)) + (portRef I0 (instanceRef AS_000_DMA_0_m)) + )) + (net un4_uds_000_1 (joined + (portRef O (instanceRef un4_lds_000_1)) + (portRef I1 (instanceRef un4_uds_000)) + (portRef I1 (instanceRef un4_lds_000)) + )) + (net N_191 (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_0_i)) + (portRef I1 (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW_000_DMA_0_r)) + (portRef I1 (instanceRef AS_000_DMA_0_m)) + (portRef I0 (instanceRef AS_000_DMA_0_r)) + )) + (net N_192 (joined + (portRef O (instanceRef CLK_030_H_0_sqmuxa_i_0_i)) + (portRef I1 (instanceRef CLK_030_H_0_m)) + (portRef I0 (instanceRef CLK_030_H_0_r)) + )) + (net N_33 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_i)) + (portRef I1 (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_0_r)) + )) + (net N_56 (joined + (portRef O (instanceRef RW_000_INT_1_sqmuxa_i_0_i)) + (portRef I1 (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_r)) + )) + (net N_58 (joined + (portRef O (instanceRef DS_000_DMA_1_sqmuxa_i_0_i)) + (portRef I1 (instanceRef DS_000_DMA_0_m)) + (portRef I0 (instanceRef DS_000_DMA_0_r)) + )) + (net N_61 (joined + (portRef O (instanceRef un1_as_030_d0_2_i_0_i)) + (portRef I1 (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef DS_000_ENABLE_0_r)) + )) + (net N_83 (joined + (portRef O (instanceRef RW_000_INT_1_sqmuxa_i_0_o2_i)) + (portRef I1 (instanceRef AS_000_INT_0_m)) + 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(net N_267 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_0_a2_7)) + (portRef I0 (instanceRef N_267_i)) + )) + (net N_269 (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_0_a2_0_7)) + (portRef I0 (instanceRef N_269_i)) + )) + (net N_270 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a2)) + (portRef I0 (instanceRef N_270_i)) + )) + (net N_272 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a2_0)) + (portRef I0 (instanceRef N_272_i)) + )) + (net N_273 (joined + (portRef O (instanceRef RW_000_INT_1_sqmuxa_i_0_a2)) + (portRef I0 (instanceRef N_273_i)) + )) + (net N_274 (joined + (portRef O (instanceRef DS_000_DMA_1_sqmuxa_i_0_a2)) + (portRef I0 (instanceRef N_274_i)) + )) + (net N_275 (joined + (portRef O (instanceRef un1_AS_030_D0_2_0_i_a2)) + (portRef I0 (instanceRef N_275_i)) + )) + (net N_276 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_a2_0)) + (portRef I0 (instanceRef N_276_i)) + )) + (net N_279 (joined + (portRef O (instanceRef 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state_machine_SIZE_DMA_5_i_a2_0_a2_0)) + (portRef I0 (instanceRef N_294_i)) + )) + (net N_296 (joined + (portRef O (instanceRef state_machine_A0_DMA_2_0_a2_1_a2_0)) + (portRef I1 (instanceRef state_machine_SIZE_DMA_5_i_a2_0_a2_0)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a2_0_1)) + (portRef I1 (instanceRef state_machine_A0_DMA_2_0_a2_1_a2)) + )) + (net N_298 (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_a2_2_1)) + (portRef I0 (instanceRef N_298_i)) + (portRef I1 (instanceRef state_machine_un10_clk_000_pe_0_a2_0_1)) + )) + (net N_127_i (joined + (portRef O (instanceRef G_97_0_x2)) + (portRef D (instanceRef RESET_DLY_1)) + )) + (net N_129_i (joined + (portRef O (instanceRef G_99_0_x2)) + (portRef D (instanceRef RESET_DLY_2)) + )) + (net N_130_i (joined + (portRef O (instanceRef G_101_0_x2)) + (portRef D (instanceRef RESET_DLY_3)) + )) + (net N_163_i (joined + (portRef O (instanceRef G_103_0_x2)) + (portRef D (instanceRef RESET_DLY_4)) + )) + (net N_164_i (joined + (portRef O (instanceRef G_105_0_x2)) + (portRef D (instanceRef RESET_DLY_5)) + )) + (net N_168_i (joined + (portRef O (instanceRef G_107_0_x2)) + (portRef D (instanceRef RESET_DLY_6)) + )) + (net N_170_i (joined + (portRef O (instanceRef G_109_0_x2)) + (portRef D (instanceRef RESET_DLY_7)) + )) + (net N_172_i (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_x2_3)) + (portRef I0 (instanceRef N_172_i_i)) + )) + (net N_173_i (joined + (portRef O (instanceRef cpu_est_0_0_x2_0)) + (portRef D (instanceRef cpu_est_0)) + )) + (net un22_berr_1 (joined + (portRef O (instanceRef un22_berr_0_a2_0_a2_1)) + (portRef I0 (instanceRef un22_berr_0_a2_0_a2_1_0)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2_0_a2)) + )) + (net N_20_mux (joined + (portRef O (instanceRef m8_e)) + (portRef I0 (instanceRef N_20_mux_i)) + (portRef I1 (instanceRef m10_0_a2_1)) + )) + (net N_169 (joined + (portRef O (instanceRef un21_fpu_cs_0_a2_0)) + (portRef I0 (instanceRef N_169_i)) + (portRef I1 (instanceRef un22_berr_0_a2_0_a2)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2_0_a2_1)) + )) + (net un1_amiga_bus_enable_low_i (joined + (portRef O (instanceRef un1_amiga_bus_enable_low_i)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_LOW)) + )) + (net un21_fpu_cs_i (joined + (portRef O (instanceRef un21_fpu_cs_i)) + (portRef I0 (instanceRef FPU_CS)) + )) + (net (rename RESET_DLY_i_7 "RESET_DLY_i[7]") (joined + (portRef O (instanceRef RESET_DLY_i_7)) + (portRef I1 (instanceRef RESET_0_0_a2_4)) + )) + (net VPA_D_i (joined + (portRef O (instanceRef VPA_D_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_1_2_4)) + (portRef I0 (instanceRef state_machine_un10_clk_000_pe_0_a2_0_2)) + )) + (net N_169_i (joined + (portRef O (instanceRef N_169_i)) + (portRef I1 (instanceRef un1_AS_030_D0_2_0_i_a2_1)) + )) + (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined + (portRef O (instanceRef SM_AMIGA_i_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_0_a2_7)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_2_2_0)) + )) + (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined + (portRef O (instanceRef SM_AMIGA_i_3)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_2_0)) + )) + (net AS_030_i (joined + (portRef O (instanceRef I_184)) + (portRef I1 (instanceRef un2_as_000_i_0_i_a2)) + (portRef I0 (instanceRef m12_i_o2)) + (portRef I0 (instanceRef un22_berr_0_a2_0_a2_1)) + )) + (net FPU_SENSE_i (joined + (portRef O (instanceRef FPU_SENSE_i)) + (portRef I0 (instanceRef un21_fpu_cs_0_a2_0_a2_1)) + )) + (net CLK_000_NE_i (joined + (portRef O (instanceRef CLK_000_NE_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_0_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_1_2)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_0_1_6)) + )) + (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined + (portRef O (instanceRef SM_AMIGA_i_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_o2_0_0)) + )) + (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined + (portRef O (instanceRef cpu_est_i_1)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_o2_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_o2_1)) + )) + (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined + (portRef O (instanceRef cpu_est_i_2)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_a2_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_a2_0_1)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_0_a2_0_2)) + )) + (net BERR_i (joined + (portRef O (instanceRef I_185)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_1_0_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_1_1_0)) + )) + (net CLK_030_i (joined + (portRef O (instanceRef CLK_030_i)) + (portRef I1 (instanceRef CLK_030_H_0_sqmuxa_i_0_a2)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_0)) + )) + (net nEXP_SPACE_D0_i (joined + (portRef O (instanceRef nEXP_SPACE_D0_i)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a2_0)) + (portRef I1 (instanceRef un3_dtack_i_a2_0_a2)) + )) + (net CLK_000_D1_i (joined + (portRef O (instanceRef CLK_000_D1_i)) + (portRef I1 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_i_0)) + )) + (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined + (portRef O (instanceRef cpu_est_i_3)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_a2_0_1)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_o2_1)) + (portRef I1 (instanceRef state_machine_un10_clk_000_pe_0_o2)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_0_a2_2)) + )) + (net A1_i (joined + (portRef O (instanceRef A1_i)) + (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_DMA_HIGH_2_0_0)) + )) + (net BGACK_030_INT_i (joined + (portRef O (instanceRef BGACK_030_INT_i)) + (portRef I1 (instanceRef un1_amiga_bus_enable_low_0_a2_0_a2)) + (portRef I1 (instanceRef un7_amiga_bus_enable_high_i_a2_0_a2)) + (portRef I1 (instanceRef state_machine_A0_DMA_2_0_a2_1_a2_0)) + (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i_0_o2)) + (portRef I1 (instanceRef un3_dtack_i_a2_0_a2_1)) + (portRef OE (instanceRef RW)) + )) + (net CLK_000_D0_i (joined + (portRef O (instanceRef CLK_000_D0_i)) + (portRef I0 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_o2_i_o2_0)) + )) + (net AS_000_i (joined + (portRef O (instanceRef I_186)) + (portRef I0 (instanceRef state_machine_A0_DMA_2_0_a2_1_a2_0)) + (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i_0_o2_1)) + )) + (net LDS_000_i (joined + (portRef O (instanceRef I_187)) + (portRef I0 (instanceRef state_machine_SIZE_DMA_5_0_0_a2_1)) + (portRef I1 (instanceRef state_machine_A0_DMA_2_0_a2_1_a2_1)) + )) + (net UDS_000_i (joined + (portRef O (instanceRef I_188)) + (portRef I1 (instanceRef state_machine_SIZE_DMA_5_0_0_a2_1)) + )) + (net DTACK_D0_i (joined + (portRef O (instanceRef DTACK_D0_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_2_4)) + )) + (net CLK_000_PE_i (joined + (portRef O (instanceRef CLK_000_PE_i)) + (portRef I1 (instanceRef state_machine_un4_bgack_000_i_a2_0_a2)) + (portRef I1 (instanceRef SM_AMIGA_ns_i_0_0_o2_7)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_0)) + )) + (net RW_000_i (joined + (portRef O (instanceRef I_189)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a2)) + (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_1_i_0_0)) + (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_i_0_1)) + )) + (net AS_000_DMA_i (joined + (portRef O (instanceRef AS_000_DMA_i)) + (portRef I0 (instanceRef CLK_030_H_0_sqmuxa_i_0_a2)) + (portRef I0 (instanceRef state_machine_DS_000_DMA_3_0_0)) + (portRef I0 (instanceRef un3_dtack_i_a2_0_a2_1)) + )) + (net AS_000_INT_i (joined + (portRef O (instanceRef AS_000_INT_i)) + (portRef I0 (instanceRef un2_as_000_i_0_i_a2)) + )) + (net DS_030_D0_i (joined + (portRef O (instanceRef DS_030_D0_i)) + (portRef I0 (instanceRef state_machine_un3_ds_030_d0_i_i_a2)) + )) + (net RW_i (joined + (portRef O (instanceRef I_190)) + (portRef I1 (instanceRef state_machine_RW_000_INT_5_i_a2_0_a2)) + )) + (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined + (portRef O (instanceRef SM_AMIGA_i_7)) + (portRef I1 (instanceRef RW_000_INT_1_sqmuxa_i_0)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_1_sqmuxa_1_0_a2_0_a2)) + )) + (net AMIGA_BUS_ENABLE_DMA_LOW_i (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i)) + (portRef I0 (instanceRef un1_amiga_bus_enable_low_0_a2_0_a2)) + )) + (net AS_030_D0_i (joined + (portRef O (instanceRef AS_030_D0_i)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_o2_2_o2)) + (portRef I0 (instanceRef m10_0_a2_2)) + )) + (net (rename RESET_DLY_i_0 "RESET_DLY_i[0]") (joined + (portRef O (instanceRef RESET_DLY_i_0)) + (portRef I1 (instanceRef G_95_i_a2)) + )) + (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined + (portRef O (instanceRef cpu_est_i_0)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_a2_1)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_a2_0_3)) + (portRef I1 (instanceRef state_machine_un10_clk_000_pe_0_o2_0)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_0_a2_0_1_2)) + )) + (net N_172_i_i (joined + (portRef O (instanceRef N_172_i_i)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_a2_3)) + )) + (net (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (joined + (portRef O (instanceRef SIZE_DMA_i_1)) + (portRef I1 (instanceRef un8_size)) + )) + (net (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (joined + (portRef O (instanceRef SIZE_DMA_i_0)) + (portRef I1 (instanceRef un6_size)) + )) + (net (rename A_i_16 "A_i[16]") (joined + (portRef O (instanceRef A_i_16)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2_0_2)) + )) + (net UDS_000_INT_i (joined + (portRef O (instanceRef UDS_000_INT_i)) + (portRef I0 (instanceRef un4_uds_000)) + )) + (net LDS_000_INT_i (joined + (portRef O (instanceRef LDS_000_INT_i)) + (portRef I0 (instanceRef un4_lds_000)) + )) + (net DS_030_i (joined + (portRef O (instanceRef I_192)) + (portRef I1 (instanceRef un4_lds_000_1)) + )) + (net (rename A_i_31 "A_i[31]") (joined + (portRef O (instanceRef A_i_31)) + (portRef I1 (instanceRef m8_e_4)) + )) + (net (rename A_i_24 "A_i[24]") (joined + (portRef O (instanceRef A_i_24)) + (portRef I0 (instanceRef m8_e_1)) + )) + (net (rename A_i_25 "A_i[25]") (joined + (portRef O (instanceRef A_i_25)) + (portRef I1 (instanceRef m8_e_1)) + )) + (net (rename A_i_26 "A_i[26]") (joined + (portRef O (instanceRef A_i_26)) + (portRef I0 (instanceRef m8_e_2)) + )) + (net (rename A_i_27 "A_i[27]") (joined + (portRef O (instanceRef A_i_27)) + (portRef I1 (instanceRef m8_e_2)) + )) + (net (rename A_i_28 "A_i[28]") (joined + (portRef O (instanceRef A_i_28)) + (portRef I0 (instanceRef m8_e_3)) + )) + (net (rename A_i_29 "A_i[29]") (joined + (portRef O (instanceRef A_i_29)) + (portRef I1 (instanceRef m8_e_3)) + )) + (net (rename A_i_30 "A_i[30]") (joined + (portRef O (instanceRef A_i_30)) + (portRef I0 (instanceRef m8_e_4)) + )) + (net (rename A_i_18 "A_i[18]") (joined + (portRef O (instanceRef A_i_18)) + (portRef I0 (instanceRef un21_fpu_cs_0_a2_0_3)) + )) + (net (rename A_i_19 "A_i[19]") (joined + (portRef O (instanceRef A_i_19)) + (portRef I1 (instanceRef un21_fpu_cs_0_a2_0_3)) + )) + (net RST_i (joined + (portRef O (instanceRef RST_i)) + (portRef S (instanceRef A0_DMA)) + (portRef S (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH)) + (portRef S (instanceRef AMIGA_BUS_ENABLE_DMA_LOW)) + (portRef S (instanceRef AMIGA_BUS_ENABLE_INT)) + (portRef S (instanceRef AS_000_DMA)) + (portRef S (instanceRef AS_000_INT)) + (portRef S (instanceRef AS_030_000_SYNC)) + (portRef S (instanceRef AS_030_D0)) + (portRef S (instanceRef BGACK_030_INT)) + (portRef S (instanceRef BGACK_030_INT_D)) + (portRef S (instanceRef BG_000DFFSH)) + (portRef R (instanceRef CLK_030_H)) + (portRef S (instanceRef DSACK1_INT)) + (portRef S (instanceRef DS_000_DMA)) + (portRef R (instanceRef DS_000_ENABLE)) + (portRef S (instanceRef DS_030_D0)) + (portRef S (instanceRef DTACK_D0)) + (portRef S (instanceRef IPL_030DFFSH_0)) + (portRef S (instanceRef IPL_030DFFSH_1)) + (portRef S (instanceRef IPL_030DFFSH_2)) + (portRef S (instanceRef LDS_000_INT)) + (portRef R (instanceRef RESETDFFRH)) + (portRef R (instanceRef RESET_DLY_0)) + (portRef R (instanceRef RESET_DLY_1)) + (portRef R (instanceRef RESET_DLY_2)) + (portRef R (instanceRef RESET_DLY_3)) + (portRef R (instanceRef RESET_DLY_4)) + (portRef R (instanceRef RESET_DLY_5)) + (portRef R (instanceRef RESET_DLY_6)) + (portRef R (instanceRef RESET_DLY_7)) + (portRef S (instanceRef RW_000_DMA)) + (portRef S (instanceRef RW_000_INT)) + (portRef S (instanceRef SIZE_DMA_0)) + (portRef S (instanceRef SIZE_DMA_1)) + (portRef R (instanceRef SM_AMIGA_0)) + (portRef R (instanceRef SM_AMIGA_1)) + (portRef R (instanceRef SM_AMIGA_2)) + (portRef R (instanceRef SM_AMIGA_3)) + (portRef R (instanceRef SM_AMIGA_4)) + (portRef R (instanceRef SM_AMIGA_5)) + (portRef R (instanceRef SM_AMIGA_6)) + (portRef S (instanceRef SM_AMIGA_7)) + (portRef S (instanceRef UDS_000_INT)) + (portRef S (instanceRef VMA_INT)) + (portRef S (instanceRef VPA_D)) + (portRef S (instanceRef nEXP_SPACE_D0)) + )) + (net CLK_OUT_PRE_50_i (joined + (portRef O (instanceRef CLK_OUT_PRE_50_i)) + (portRef D (instanceRef CLK_OUT_PRE_50)) + )) + (net N_135_i (joined + (portRef O (instanceRef N_135_i)) + (portRef D (instanceRef SIZE_DMA_0)) + )) + (net N_132_i (joined + (portRef O (instanceRef N_132_i)) + (portRef I0 (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0)) + )) + (net N_165_i (joined + (portRef O (instanceRef N_165_i)) + (portRef I0 (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_2)) + (portRef I0 (instanceRef RW_000_INT_1_sqmuxa_i_0_o2)) + )) + (net N_134_i (joined + (portRef O (instanceRef N_134_i)) + (portRef I0 (instanceRef RW_000_INT_0_m)) + )) + (net un4_lds_000_i (joined + (portRef O (instanceRef un4_lds_000_i)) + (portRef I0 (instanceRef LDS_000)) + )) + (net un4_uds_000_i (joined + (portRef O (instanceRef un4_uds_000_i)) + (portRef I0 (instanceRef UDS_000)) + )) + (net N_255_i (joined + (portRef O (instanceRef N_255_i)) + (portRef I0 (instanceRef AS_000)) + )) + (net un8_size_i (joined + (portRef O (instanceRef un8_size_i)) + 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pos_clk_cpu_est_11_0_0_a2_2_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_o2_i_1)) + )) + (net N_115_i (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_0_o2_2)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_a2_1_1)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_i_0_o2_i_2)) + )) + (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined + (portRef O (instanceRef SM_AMIGA_i_4)) + (portRef I1 (instanceRef un1_SM_AMIGA_0_sqmuxa_4_0_a2_1_o2)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_o2_1_1_0)) + )) + (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined + (portRef O (instanceRef SM_AMIGA_i_6)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_o2_1_0)) + )) + (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined + (portRef O (instanceRef SM_AMIGA_i_5)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_o2_0_0)) + )) + (net N_113_i (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_o2_0_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_o2_0_i_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_2_1_0)) + )) + (net N_112_i (joined + (portRef O (instanceRef reset_delay_machine_un24_clk_000_ne_d0_0_o2)) + (portRef I0 (instanceRef G_96)) + (portRef I0 (instanceRef reset_delay_machine_un24_clk_000_ne_d0_0_o2_i)) + )) + (net (rename CLK_000_N_SYNC_i_9 "CLK_000_N_SYNC_i[9]") (joined + (portRef O (instanceRef CLK_000_N_SYNC_i_9)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_a2_1_o2)) + )) + (net N_292_i (joined + (portRef O (instanceRef N_292_i)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_a2_1_o2)) + )) + (net N_111_0 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_a2_1_o2)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_a2_1_o2_i)) + )) + (net N_110_i (joined + (portRef O (instanceRef state_machine_un10_clk_000_pe_0_o2)) + (portRef I1 (instanceRef state_machine_un10_clk_000_pe_0_a2)) + (portRef I1 (instanceRef reset_delay_machine_un24_clk_000_ne_d0_0_o2)) + )) + (net N_291_i (joined + (portRef O (instanceRef N_291_i)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_4_0_a2_1_o2)) + )) + (net N_109_0 (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_4_0_a2_1_o2)) + (portRef I0 (instanceRef un1_SM_AMIGA_0_sqmuxa_4_0_a2_1_o2_i)) + )) + (net (rename state_machine_un3_as_030_d0_i "state_machine.un3_as_030_d0_i") (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_o2_2_o2)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0)) + (portRef I1 (instanceRef un1_AS_030_D0_2_0_i)) + (portRef I0 (instanceRef un1_as_030_d0_2_i_0)) + (portRef I1 (instanceRef RW_000_INT_1_sqmuxa_i_0_o2)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_o2_2_o2_i)) + )) + (net CLK_EXP_c_i (joined + (portRef O (instanceRef CLK_EXP_c_i)) + (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_a2_1_o2_0)) + )) + (net N_106_0 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_a2_1_o2_0)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_a2_1_o2_0_i)) + )) + (net N_105_i (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_o2_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_o2_i_4)) + )) + (net N_104_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_0_o2_7)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_0_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_0_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_0_o2_i_7)) + )) + (net (rename state_machine_un8_bgack_030_int_i_0_i "state_machine.un8_bgack_030_int_i_0_i") (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_0_o2)) + (portRef I0 (instanceRef CLK_030_H_0_m)) + (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_i_0)) + (portRef I1 (instanceRef state_machine_SIZE_DMA_5_0_0_1)) + (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_DMA_HIGH_2_0_0)) + (portRef I1 (instanceRef state_machine_AMIGA_BUS_ENABLE_DMA_LOW_2_0_0)) + (portRef I1 (instanceRef state_machine_DS_000_DMA_3_0_0)) + (portRef I1 (instanceRef CLK_030_H_0_sqmuxa_i_0)) + (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_1_i_0_0)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_0_o2_i)) + (portRef I1 (instanceRef DS_000_DMA_1_sqmuxa_i_0)) + )) + (net N_287_i (joined + (portRef O (instanceRef N_287_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_o2_0_4)) + )) + (net N_288_i (joined + (portRef O (instanceRef N_288_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_o2_0_4)) + )) + (net N_102_i (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_o2_0_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_o2_0_i_4)) + )) + (net VMA_INT_i (joined + (portRef O (instanceRef VMA_INT_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_1_2_4)) + )) + (net N_100_i (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_o2_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_0_1)) + (portRef I1 (instanceRef un1_bgack_030_int_d_i_0_a2)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_o2_i_0)) + )) + (net AS_030_000_SYNC_i (joined + (portRef O (instanceRef AS_030_000_SYNC_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_o2_1_0_0)) + )) + (net N_97_i (joined + (portRef O (instanceRef pos_clk_CLK_000_N_SYNC_2_0_o2_i_o2_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_o2_1_0_0)) + (portRef D (instanceRef CLK_000_N_SYNC_0)) + )) + (net N_96_i (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_o2_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_o2_i_3)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_a2_1_1_4)) + )) + (net N_95_i (joined + (portRef O (instanceRef state_machine_un10_clk_000_pe_0_o2_0)) + (portRef I0 (instanceRef state_machine_un10_clk_000_pe_0_o2_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_1_1_4)) + )) + (net N_286_i (joined + (portRef O (instanceRef N_286_i)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_0_o2_1)) + )) + (net (rename state_machine_RW_000_DMA_3_0 "state_machine.RW_000_DMA_3_0") (joined + (portRef O (instanceRef DS_000_DMA_1_sqmuxa_1_i_0_0)) + (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_1_i_0_0_i)) + )) + (net N_275_i (joined + (portRef O (instanceRef N_275_i)) + (portRef I0 (instanceRef un1_AS_030_D0_2_0_i)) + )) + (net N_74_0 (joined + (portRef O (instanceRef un1_AS_030_D0_2_0_i)) + (portRef I0 (instanceRef un1_AS_030_D0_2_0_i_i)) + )) + (net un1_SM_AMIGA_0_sqmuxa_4_i (joined + (portRef O (instanceRef un1_SM_AMIGA_0_sqmuxa_4_i)) + (portRef I1 (instanceRef un1_as_030_d0_2_i_0)) + )) + (net N_61_0 (joined + (portRef O (instanceRef un1_as_030_d0_2_i_0)) + (portRef I0 (instanceRef un1_as_030_d0_2_i_0_i)) + )) + (net N_274_i (joined + (portRef O (instanceRef N_274_i)) + (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_i_0_1)) + )) + (net N_58_0 (joined + (portRef O (instanceRef DS_000_DMA_1_sqmuxa_i_0)) + (portRef I0 (instanceRef DS_000_DMA_1_sqmuxa_i_0_i)) + )) + (net N_273_i (joined + (portRef O (instanceRef N_273_i)) + (portRef I1 (instanceRef RW_000_INT_1_sqmuxa_i_0_1)) + )) + (net N_56_0 (joined + (portRef O (instanceRef RW_000_INT_1_sqmuxa_i_0)) + (portRef I0 (instanceRef RW_000_INT_1_sqmuxa_i_0_i)) + )) + (net N_270_i (joined + (portRef O (instanceRef N_270_i)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0)) + )) + (net N_272_i (joined + (portRef O (instanceRef N_272_i)) + (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0)) + )) + (net AMIGA_BUS_DATA_DIR_c_0 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_i)) + )) + (net N_267_i (joined + (portRef O (instanceRef N_267_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_i_0_0_7)) + )) + (net N_85_i (joined + (portRef O (instanceRef SM_AMIGA_ns_i_0_0_7)) + (portRef D (instanceRef SM_AMIGA_0)) + )) + (net N_265_i (joined + (portRef O (instanceRef N_265_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_6)) + )) + (net N_266_i (joined + (portRef O (instanceRef N_266_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_6)) + )) + (net (rename SM_AMIGA_ns_0_6 "SM_AMIGA_ns_0[6]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_i_6)) + )) + (net N_263_i (joined + (portRef O (instanceRef N_263_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_5)) + )) + (net N_264_i (joined + (portRef O (instanceRef N_264_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_5)) + )) + (net (rename SM_AMIGA_ns_0_5 "SM_AMIGA_ns_0[5]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_5)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_i_5)) + )) + (net N_235_i (joined + (portRef O (instanceRef N_235_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_4)) + )) + (net N_262_i (joined + (portRef O (instanceRef N_262_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_4)) + )) + (net (rename SM_AMIGA_ns_0_4 "SM_AMIGA_ns_0[4]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_i_4)) + )) + (net N_233_i (joined + (portRef O (instanceRef N_233_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_3)) + )) + (net N_234_i (joined + (portRef O (instanceRef N_234_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_3)) + )) + (net (rename SM_AMIGA_ns_0_3 "SM_AMIGA_ns_0[3]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_3)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_i_3)) + )) + (net N_232_i (joined + (portRef O (instanceRef N_232_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_2)) + )) + (net (rename SM_AMIGA_ns_0_2 "SM_AMIGA_ns_0[2]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_2)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_i_2)) + )) + (net N_231_i (joined + (portRef O (instanceRef N_231_i)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_1)) + )) + (net N_260_i (joined + (portRef O (instanceRef N_260_i)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_1)) + )) + (net (rename SM_AMIGA_ns_0_1 "SM_AMIGA_ns_0[1]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_1)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_i_1)) + )) + (net N_294_i (joined + (portRef O (instanceRef N_294_i)) + (portRef I0 (instanceRef state_machine_SIZE_DMA_5_0_0_1)) + )) + (net (rename state_machine_SIZE_DMA_5_0_1 "state_machine.SIZE_DMA_5_0[1]") (joined + (portRef O (instanceRef state_machine_SIZE_DMA_5_0_0_1)) + (portRef I0 (instanceRef state_machine_SIZE_DMA_5_0_0_i_1)) + )) + (net (rename state_machine_AMIGA_BUS_ENABLE_DMA_HIGH_2_0 "state_machine.AMIGA_BUS_ENABLE_DMA_HIGH_2_0") (joined + (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_DMA_HIGH_2_0_0)) + (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_DMA_HIGH_2_0_0_i)) + )) + (net (rename state_machine_AMIGA_BUS_ENABLE_DMA_LOW_2_0 "state_machine.AMIGA_BUS_ENABLE_DMA_LOW_2_0") (joined + (portRef O (instanceRef state_machine_AMIGA_BUS_ENABLE_DMA_LOW_2_0_0)) + (portRef I0 (instanceRef state_machine_AMIGA_BUS_ENABLE_DMA_LOW_2_0_0_i)) + )) + (net (rename state_machine_DS_000_DMA_3_0 "state_machine.DS_000_DMA_3_0") (joined + (portRef O (instanceRef state_machine_DS_000_DMA_3_0_0)) + (portRef I0 (instanceRef state_machine_DS_000_DMA_3_0_0_i)) + )) + (net N_33_0 (joined + (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0)) + (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_i)) + )) + (net N_257_i (joined + (portRef O (instanceRef N_257_i)) + (portRef I0 (instanceRef CLK_030_H_0_sqmuxa_i_0)) + )) + (net N_192_0 (joined + (portRef O (instanceRef CLK_030_H_0_sqmuxa_i_0)) + (portRef I0 (instanceRef CLK_030_H_0_sqmuxa_i_0_i)) + )) + (net N_191_0 (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_0)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_0_i)) + )) + (net N_256_i (joined + (portRef O (instanceRef N_256_i)) + (portRef I1 (instanceRef un1_bgack_030_int_d_i_0)) + )) + (net N_190_i (joined + (portRef O (instanceRef un1_bgack_030_int_d_i_0)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_0_n)) + )) + (net BG_030_c_i (joined + (portRef O (instanceRef BG_030_c_i)) + (portRef I0 (instanceRef state_machine_un8_bg_030_0_0)) + )) + (net N_254_i (joined + (portRef O (instanceRef N_254_i)) + (portRef I1 (instanceRef state_machine_un8_bg_030_0_0)) + )) + (net (rename state_machine_un8_bg_030_0 "state_machine.un8_bg_030_0") (joined + (portRef O (instanceRef state_machine_un8_bg_030_0_0)) + (portRef I0 (instanceRef state_machine_un8_bg_030_0_0_i)) + )) + (net N_238_i (joined + (portRef O (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_i_0)) + (portRef D (instanceRef CLK_000_P_SYNC_0)) + )) + (net N_198_i (joined + (portRef O (instanceRef N_198_i)) + (portRef I0 (instanceRef m12_i)) + )) + (net un5_ciin_i (joined + (portRef O (instanceRef un5_ciin_i)) + (portRef I1 (instanceRef m12_i)) + )) + (net N_237_0 (joined + (portRef O (instanceRef m12_i)) + (portRef I0 (instanceRef m12_i_i)) + )) + (net N_193_i (joined + (portRef O (instanceRef N_193_i)) + (portRef I0 (instanceRef G_95_i)) + )) + (net N_194_i (joined + (portRef O (instanceRef N_194_i)) + (portRef I1 (instanceRef G_95_i)) + )) + (net N_236_i (joined + (portRef O (instanceRef G_95_i)) + (portRef D (instanceRef RESET_DLY_0)) + )) + (net N_185_i (joined + (portRef O (instanceRef N_185_i)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_0_0_3)) + )) + (net N_186_i (joined + (portRef O (instanceRef N_186_i)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_1_3)) + )) + (net (rename pos_clk_cpu_est_11_0_3 "pos_clk.cpu_est_11_0[3]") (joined + (portRef O (instanceRef pos_clk_cpu_est_11_0_0_3)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_0_0_i_3)) + )) + (net N_178_i (joined + (portRef O (instanceRef N_178_i)) + (portRef I0 (instanceRef pos_clk_cpu_est_11_i_0_2)) + )) + (net N_181_i (joined + (portRef O (instanceRef N_181_i)) + (portRef I1 (instanceRef pos_clk_cpu_est_11_i_0_2)) + )) + (net N_133_i (joined + (portRef O (instanceRef pos_clk_cpu_est_11_i_0_2)) + (portRef I0 (instanceRef cpu_est_0_2__m)) + )) + (net N_176_i (joined + (portRef O (instanceRef N_176_i)) + (portRef I0 (instanceRef state_machine_un10_clk_000_pe_0)) + )) + (net N_177_i (joined + (portRef O (instanceRef N_177_i)) + (portRef I1 (instanceRef state_machine_un10_clk_000_pe_0)) + )) + (net (rename state_machine_un10_clk_000_pe_0 "state_machine.un10_clk_000_pe_0") (joined + (portRef O (instanceRef state_machine_un10_clk_000_pe_0)) + (portRef I0 (instanceRef state_machine_un10_clk_000_pe_0_i)) + )) + (net N_175_i (joined + (portRef O (instanceRef N_175_i)) + (portRef I0 (instanceRef RESET_0_0)) + )) + (net RESET_c_i (joined + (portRef O (instanceRef RESET_c_i)) + (portRef I1 (instanceRef RESET_0_0)) + )) + (net N_14_0 (joined + (portRef O (instanceRef RESET_0_0)) + (portRef I0 (instanceRef RESET_0_0_i)) + )) + (net (rename state_machine_un11_ds_030_d0_i "state_machine.un11_ds_030_d0_i") (joined + (portRef O (instanceRef state_machine_un11_ds_030_d0)) + (portRef I0 (instanceRef LDS_000_INT_0_m)) + )) + (net A0_c_i (joined + (portRef O (instanceRef A0_c_i)) + (portRef I1 (instanceRef state_machine_un11_ds_030_d0_1)) + )) + (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined + (portRef O (instanceRef SIZE_c_i_1)) + (portRef I0 (instanceRef state_machine_un11_ds_030_d0_1)) + )) + (net N_20_mux_1 (joined + (portRef O (instanceRef m8_e_1)) + (portRef I0 (instanceRef m8_e_5)) + )) + (net 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(portRef I0 (instanceRef SM_AMIGA_ns_0_0_o2_0)) + )) + (net (rename state_machine_un8_bgack_030_int_i_0_i_1 "state_machine.un8_bgack_030_int_i_0_i_1") (joined + (portRef O (instanceRef AS_000_DMA_1_sqmuxa_i_0_o2_1)) + (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_i_0_o2)) + )) + (net N_110_i_1 (joined + (portRef O (instanceRef state_machine_un10_clk_000_pe_0_o2_1)) + (portRef I0 (instanceRef state_machine_un10_clk_000_pe_0_o2)) + )) + (net N_117_i_1 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_o2_1_1_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_o2_1_0)) + )) + (net (rename SM_AMIGA_ns_0_1_0 "SM_AMIGA_ns_0_1[0]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_3_0)) + )) + (net (rename SM_AMIGA_ns_0_2_0 "SM_AMIGA_ns_0_2[0]") (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_2_0)) + (portRef I1 (instanceRef SM_AMIGA_ns_0_0_3_0)) + )) + (net (rename SM_AMIGA_ns_0_3_0 "SM_AMIGA_ns_0_3[0]") (joined + (portRef O (instanceRef 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(net N_282_3 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_a2_2_3_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_2_0)) + )) + (net N_275_1 (joined + (portRef O (instanceRef un1_AS_030_D0_2_0_i_a2_1)) + (portRef I0 (instanceRef un1_AS_030_D0_2_0_i_a2)) + )) + (net N_275_2 (joined + (portRef O (instanceRef un1_AS_030_D0_2_0_i_a2_2)) + (portRef I1 (instanceRef un1_AS_030_D0_2_0_i_a2)) + )) + (net N_177_1 (joined + (portRef O (instanceRef state_machine_un10_clk_000_pe_0_a2_0_1)) + (portRef I0 (instanceRef state_machine_un10_clk_000_pe_0_a2_0)) + )) + (net N_177_2 (joined + (portRef O (instanceRef state_machine_un10_clk_000_pe_0_a2_0_2)) + (portRef I1 (instanceRef state_machine_un10_clk_000_pe_0_a2_0)) + )) + (net N_175_1 (joined + (portRef O (instanceRef RESET_0_0_a2_1)) + (portRef I0 (instanceRef RESET_0_0_a2_5)) + )) + (net N_175_2 (joined + (portRef O (instanceRef RESET_0_0_a2_2)) + (portRef I1 (instanceRef RESET_0_0_a2_5)) + )) + (net N_175_3 (joined + (portRef O (instanceRef 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)) + (net N_279_1 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_a2_0_1_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_0_0)) + )) + (net N_276_1 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_a2_1_0_0)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_0)) + )) + (net N_272_1 (joined + (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a2_0_1)) + (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a2_0)) + )) + (net N_266_1 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_a2_0_1_6)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_0_6)) + )) + (net N_235_1 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_a2_1_0_4)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_4)) + )) + (net N_232_1 (joined + (portRef O (instanceRef SM_AMIGA_ns_0_0_a2_1_2)) + (portRef I0 (instanceRef SM_AMIGA_ns_0_0_a2_2)) + )) + (net N_254_1 (joined + (portRef O (instanceRef state_machine_un8_bg_030_0_0_a2_1)) + (portRef I0 (instanceRef state_machine_un8_bg_030_0_0_a2)) + )) + (net N_159_1 (joined + (portRef O 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)) + (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined + (portRef O (instanceRef AS_000_DMA_0_n)) + (portRef I1 (instanceRef AS_000_DMA_0_p)) + )) + (net (rename CLK_030_H_0_un3 "CLK_030_H_0.un3") (joined + (portRef O (instanceRef CLK_030_H_0_r)) + (portRef I1 (instanceRef CLK_030_H_0_n)) + )) + (net (rename CLK_030_H_0_un1 "CLK_030_H_0.un1") (joined + (portRef O (instanceRef CLK_030_H_0_m)) + (portRef I0 (instanceRef CLK_030_H_0_p)) + )) + (net (rename CLK_030_H_0_un0 "CLK_030_H_0.un0") (joined + (portRef O (instanceRef CLK_030_H_0_n)) + (portRef I1 (instanceRef CLK_030_H_0_p)) + )) + (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_r)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_n)) + )) + (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_m)) + (portRef I0 (instanceRef AS_030_000_SYNC_0_p)) + )) + (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined + (portRef O (instanceRef AS_030_000_SYNC_0_n)) + (portRef I1 (instanceRef AS_030_000_SYNC_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_INT_0_un3 "AMIGA_BUS_ENABLE_INT_0.un3") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_0_r)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_0_n)) + )) + (net (rename AMIGA_BUS_ENABLE_INT_0_un1 "AMIGA_BUS_ENABLE_INT_0.un1") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_0_m)) + (portRef I0 (instanceRef AMIGA_BUS_ENABLE_INT_0_p)) + )) + (net (rename AMIGA_BUS_ENABLE_INT_0_un0 "AMIGA_BUS_ENABLE_INT_0.un0") (joined + (portRef O (instanceRef AMIGA_BUS_ENABLE_INT_0_n)) + (portRef I1 (instanceRef AMIGA_BUS_ENABLE_INT_0_p)) + )) + (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined + (portRef O (instanceRef LDS_000_INT_0_r)) + (portRef I1 (instanceRef LDS_000_INT_0_n)) + )) + (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined + (portRef O (instanceRef LDS_000_INT_0_m)) + (portRef I0 (instanceRef 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(instanceRef cpu_est_0_3__n)) + )) + (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined + (portRef O (instanceRef cpu_est_0_3__m)) + (portRef I0 (instanceRef cpu_est_0_3__p)) + )) + (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined + (portRef O (instanceRef cpu_est_0_3__n)) + (portRef I1 (instanceRef cpu_est_0_3__p)) + )) + (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined + (portRef O (instanceRef IPL_030_0_0__r)) + (portRef I1 (instanceRef IPL_030_0_0__n)) + )) + (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined + (portRef O (instanceRef IPL_030_0_0__m)) + (portRef I0 (instanceRef IPL_030_0_0__p)) + )) + (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined + (portRef O (instanceRef IPL_030_0_0__n)) + (portRef I1 (instanceRef IPL_030_0_0__p)) + )) + (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined + (portRef O (instanceRef IPL_030_0_1__r)) + (portRef I1 (instanceRef IPL_030_0_1__n)) + )) + (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined + (portRef O (instanceRef IPL_030_0_1__m)) + (portRef I0 (instanceRef IPL_030_0_1__p)) + )) + (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined + (portRef O (instanceRef IPL_030_0_1__n)) + (portRef I1 (instanceRef IPL_030_0_1__p)) + )) + (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined + (portRef O (instanceRef RW_000_INT_0_r)) + (portRef I1 (instanceRef RW_000_INT_0_n)) + )) + (net (rename RW_000_INT_0_un1 "RW_000_INT_0.un1") (joined + (portRef O (instanceRef RW_000_INT_0_m)) + (portRef I0 (instanceRef RW_000_INT_0_p)) + )) + (net (rename RW_000_INT_0_un0 "RW_000_INT_0.un0") (joined + (portRef O (instanceRef RW_000_INT_0_n)) + (portRef I1 (instanceRef RW_000_INT_0_p)) + )) + (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined + (portRef O (instanceRef AS_000_INT_0_r)) + (portRef I1 (instanceRef AS_000_INT_0_n)) + )) + (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined + (portRef O (instanceRef AS_000_INT_0_m)) + (portRef I0 (instanceRef AS_000_INT_0_p)) + )) + (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined + (portRef O (instanceRef AS_000_INT_0_n)) + (portRef I1 (instanceRef AS_000_INT_0_p)) + )) + (net (rename DS_000_ENABLE_0_un3 "DS_000_ENABLE_0.un3") (joined + (portRef O (instanceRef DS_000_ENABLE_0_r)) + (portRef I1 (instanceRef DS_000_ENABLE_0_n)) + )) + (net (rename DS_000_ENABLE_0_un1 "DS_000_ENABLE_0.un1") (joined + (portRef O (instanceRef DS_000_ENABLE_0_m)) + (portRef I0 (instanceRef DS_000_ENABLE_0_p)) + )) + (net (rename DS_000_ENABLE_0_un0 "DS_000_ENABLE_0.un0") (joined + (portRef O (instanceRef DS_000_ENABLE_0_n)) + (portRef I1 (instanceRef DS_000_ENABLE_0_p)) + )) + (net (rename DSACK1_INT_0_un3 "DSACK1_INT_0.un3") (joined + (portRef O (instanceRef DSACK1_INT_0_r)) + (portRef I1 (instanceRef DSACK1_INT_0_n)) + )) + (net (rename DSACK1_INT_0_un1 "DSACK1_INT_0.un1") (joined + (portRef O (instanceRef DSACK1_INT_0_m)) + (portRef I0 (instanceRef DSACK1_INT_0_p)) + )) + (net (rename DSACK1_INT_0_un0 "DSACK1_INT_0.un0") (joined + (portRef O (instanceRef DSACK1_INT_0_n)) + (portRef I1 (instanceRef DSACK1_INT_0_p)) + )) + (net (rename RW_000_DMA_0_un3 "RW_000_DMA_0.un3") (joined + (portRef O (instanceRef RW_000_DMA_0_r)) + (portRef I1 (instanceRef RW_000_DMA_0_n)) + )) + (net (rename RW_000_DMA_0_un1 "RW_000_DMA_0.un1") (joined + (portRef O (instanceRef RW_000_DMA_0_m)) + (portRef I0 (instanceRef RW_000_DMA_0_p)) + )) + (net (rename RW_000_DMA_0_un0 "RW_000_DMA_0.un0") (joined + (portRef O (instanceRef RW_000_DMA_0_n)) + (portRef I1 (instanceRef RW_000_DMA_0_p)) + )) + ) + (property orig_inst_of (string "BUS68030")) + ) + ) + ) + (design BUS68030 (cellRef BUS68030 (libraryRef work))) +) diff --git a/Logic/BUS68030.naf b/Logic/BUS68030.naf new file mode 100644 index 0000000..dc824e3 --- /dev/null +++ b/Logic/BUS68030.naf @@ -0,0 +1,61 @@ +AS_030 b +AS_000 b +RW_000 b +DS_030 b +UDS_000 b +LDS_000 b +SIZE[1] b +SIZE[0] b +A[31] i +A[30] i +A[29] i +A[28] i +A[27] i +A[26] i +A[25] i +A[24] i +A[23] i +A[22] i +A[21] i +A[20] i +A[19] i +A[18] i +A[17] i +A[16] i +A0 b +A1 i +nEXP_SPACE i +BERR b +BG_030 i +BG_000 o +BGACK_030 o +BGACK_000 i +CLK_030 i +CLK_000 i +CLK_OSZI i +CLK_DIV_OUT o +CLK_EXP o +FPU_CS o +FPU_SENSE i +IPL_030[2] o +IPL_030[1] o +IPL_030[0] o +IPL[2] i +IPL[1] i +IPL[0] i +DSACK1 b +DTACK b +AVEC o +E o +VPA i +VMA o +RST i +RESET o +RW b +FC[1] i +FC[0] i +AMIGA_ADDR_ENABLE o +AMIGA_BUS_DATA_DIR o +AMIGA_BUS_ENABLE_LOW o +AMIGA_BUS_ENABLE_HIGH o +CIIN o diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj index 1c22fe1..dae865c 100644 --- a/Logic/BUS68030.prj +++ b/Logic/BUS68030.prj @@ -1,6 +1,6 @@ #-- Lattice Semiconductor Corporation Ltd. #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj -#-- Written on Sun Oct 05 21:32:32 2014 +#-- Written on Fri Oct 10 22:39:56 2014 #device options diff --git a/Logic/bus68030.srf b/Logic/bus68030.srf index 7b43ca1..2886f78 100644 --- a/Logic/bus68030.srf +++ b/Logic/bus68030.srf @@ -6,7 +6,7 @@ #Implementation: logic $ Start of Compile -#Sun Oct 05 21:32:33 2014 +#Fri Oct 10 22:39:57 2014 Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013 @N|Running in 64-bit mode @@ -16,6 +16,7 @@ Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentatio @N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030. File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling VHDL syntax check successful! +File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral @W: CD604 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":217:5:217:18|OTHERS clause is not synthesized @W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_33 is undriven @@ -46,7 +47,7 @@ State machine has 8 reachable states with original encodings of: 111 @END Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sun Oct 05 21:32:33 2014 +# Fri Oct 10 22:39:57 2014 ###########################################################] Map & Optimize Report @@ -70,17 +71,17 @@ original code -> new code Resource Usage Report Simple gate primitives: -DFFSH 28 uses DFFRH 18 uses +DFFSH 28 uses DFF 34 uses BI_DIR 13 uses IBUF 31 uses OBUF 16 uses BUFTH 1 use -AND2 231 uses -INV 181 uses -OR2 23 uses +AND2 228 uses +INV 189 uses XOR2 9 uses +OR2 21 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -90,6 +91,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sun Oct 05 21:32:34 2014 +# Fri Oct 10 22:39:58 2014 ###########################################################] diff --git a/Logic/run_options.txt b/Logic/run_options.txt index 32dc283..bcd07cf 100644 --- a/Logic/run_options.txt +++ b/Logic/run_options.txt @@ -1,7 +1,7 @@ #-- Synopsys, Inc. #-- Version G-2012.09LC-SP1 #-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt -#-- Written on Sun Oct 05 21:32:33 2014 +#-- Written on Fri Oct 10 22:39:56 2014 #project files diff --git a/Logic/syndos.env b/Logic/syndos.env new file mode 100644 index 0000000..68b352e --- /dev/null +++ b/Logic/syndos.env @@ -0,0 +1,39 @@ +ABEL5DEV=C:\Program Files (x86)\ispLever\ispcpld\lib5 +DIOEDA_ABEL5DEV=C:\Program Files (x86)\ispLever\ispcpld\lib5 +DIOEDA_ActiveHDL=C:\Program Files (x86)\ispLever\active-hdl\BIN +DIOEDA_ActiveHDLPath=C:\Program Files (x86)\ispLever\active-hdl\BIN +DIOEDA_AppNotes=C:\Program Files (x86)\ispLever\ispcpld\bin +DIOEDA_Bin=C:\Program Files (x86)\ispLever\ispcpld\bin +DIOEDA_Config=C:\Program Files (x86)\ispLever\ispcpld\config +DIOEDA_CONTEXT=ispLEVER CLASSIC +DIOEDA_DSPPATH=C:\Program Files (x86)\ispLever\ispLeverDSP +DIOEDA_EPICPATH=C:\Program Files (x86)\ispLever\ispfpga\bin\nt +DIOEDA_Examples=C:\Program Files (x86)\ispLever\examples +DIOEDA_FPGABinPath=C:\Program Files (x86)\ispLever\ispfpga\bin\nt +DIOEDA_FPGAPath=C:\Program Files (x86)\ispLever\ispfpga +DIOEDA_HDLExplorer=C:\Program Files (x86)\ispLever\hdle\win32 +DIOEDA_INI=C:\lsc_env +DIOEDA_ispVM=C:\Program Files (x86)\ispLever\ispvmsystem +DIOEDA_ispVMSystem=C:\Program Files (x86)\ispLever\ispvmsystem +DIOEDA_License=C:\Program Files (x86)\ispLever\license +DIOEDA_MachPath=C:\Program Files (x86)\ispLever\ispcpld\bin +DIOEDA_Manuals=C:\Program Files (x86)\ispLever\ispcpld\manuals +DIOEDA_ModelSim=C:\Program Files (x86)\ispLever\modelsim\win32loem +DIOEDA_ModelsimPath=C:\Program Files (x86)\ispLever\modelsim\win32loem +DIOEDA_PDSPath=C:\Program Files (x86)\ispLever\ispcomp +DIOEDA_Precision=C:\isptools\precision +DIOEDA_PrecisionPath=C:\isptools\precision +DIOEDA_ProductName=ispLEVER +DIOEDA_ProductPrefix=SYN +DIOEDA_ProductTitle=ispLEVER +DIOEDA_ProductType=1.7.00.05.28.13_LS_HDL_BASE_PC_N +DIOEDA_ProductVersion=1.7.00.05 +DIOEDA_ProgramFolder=Lattice Semiconductor ispLEVER Classic 1.7 +DIOEDA_Root=C:\Program Files (x86)\ispLever\ispcpld +DIOEDA_Spectrum=C:\isptools\spectrum +DIOEDA_SpectrumPath=C:\isptools\spectrum +DIOEDA_Synplify=C:\Program Files (x86)\ispLever\synpbase +DIOEDA_SynplifyPath=C:\Program Files (x86)\ispLever\synpbase +DIOEDA_Tutorial=C:\Program Files (x86)\ispLever\ispcpld\tutorial +DIOPRODUCT=ispLEVER +PATH=C:\Program Files (x86)\ispLever\ispcpld\bin diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr index 75b195e..cfc4c38 100644 --- a/Logic/synlog/bus68030_fpga_mapper.srr +++ b/Logic/synlog/bus68030_fpga_mapper.srr @@ -17,17 +17,17 @@ original code -> new code Resource Usage Report Simple gate primitives: -DFFSH 28 uses DFFRH 18 uses +DFFSH 28 uses DFF 34 uses BI_DIR 13 uses IBUF 31 uses OBUF 16 uses BUFTH 1 use -AND2 231 uses -INV 181 uses -OR2 23 uses +AND2 228 uses +INV 189 uses XOR2 9 uses +OR2 21 uses @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis. @@ -37,6 +37,6 @@ Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime -# Sun Oct 05 21:32:34 2014 +# Fri Oct 10 22:39:58 2014 ###########################################################] diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml index 450a376..4015ce5 100644 --- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml +++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml @@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t - - 1412537553 + 1412973597 \ No newline at end of file diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml index 70e92d0..b17d28f 100644 --- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml +++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml @@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the 96MB -1412537554 +1412973598 diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml index 180f360..047a82b 100644 --- a/Logic/syntmp/run_option.xml +++ b/Logic/syntmp/run_option.xml @@ -3,7 +3,7 @@ Synopsys, Inc. Version G-2012.09LC-SP1 Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml - Written on Sun Oct 05 21:32:33 2014 + Written on Fri Oct 10 22:39:57 2014 --> diff --git a/Logic/synwork/BUS68030_compiler.fdep b/Logic/synwork/BUS68030_compiler.fdep index 4de4e07..ee4b59a 100644 --- a/Logic/synwork/BUS68030_compiler.fdep +++ b/Logic/synwork/BUS68030_compiler.fdep @@ -10,7 +10,7 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412537547 +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412973591 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) diff --git a/Logic/synwork/BUS68030_compiler.fdeporig b/Logic/synwork/BUS68030_compiler.fdeporig index fdf9749..274cdd1 100644 --- a/Logic/synwork/BUS68030_compiler.fdeporig +++ b/Logic/synwork/BUS68030_compiler.fdeporig @@ -10,7 +10,7 @@ #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328 #CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328 -#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412537547 +#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412973591 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl # Dependency Lists (Uses list) diff --git a/Logic/synwork/BUS68030_compiler.srs b/Logic/synwork/BUS68030_compiler.srs index 673a0f4..6c8e38e 100644 Binary files a/Logic/synwork/BUS68030_compiler.srs and b/Logic/synwork/BUS68030_compiler.srs differ