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Tristating Data was a bad idea

This commit is contained in:
MHeinrichs 2014-10-07 19:58:39 +02:00
parent fb249c6203
commit 419cf9809f
17 changed files with 395 additions and 31 deletions
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10
Logic/68030-68000-bus.vhd
View File

@ -232,7 +232,7 @@ begin
RESET_DLY <= "00000000";
elsif(rising_edge(CLK_OSZI)) then
--reset delay: wait 128 E-Clocks!
if(CLK_000_NE_D0 = '1' and cpu_est = E1 and RESET = '0') then
if(CLK_000_NE_D0 = '1' and cpu_est = E1) then
RESET_DLY <= RESET_DLY +1;
end if;
end if;
@ -493,11 +493,11 @@ begin
-- bus drivers
AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT WHEN AS_030='0' ELSE '1';
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' AND AMIGA_BUS_ENABLE_INT ='0' AND AS_030='0' ELSE
'0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' AND AS_000_DMA='0' ELSE
AMIGA_ADDR_ENABLE <= AMIGA_BUS_ENABLE_INT;
AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' AND AMIGA_BUS_ENABLE_INT ='0' ELSE
'0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE
'1';
AMIGA_BUS_ENABLE_LOW <= '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' AND AS_000_DMA='0' ELSE
AMIGA_BUS_ENABLE_LOW <= '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0' ELSE
'1';

366
Logic/68030_TK.tcl
View File

@ -279146,3 +279146,369 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6
########## Tcl recorder end at 10/05/14 00:12:34 ###########
########## Tcl recorder starts at 10/05/14 21:30:23 ##########
# Commands to make the Process:
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
########## Tcl recorder end at 10/05/14 21:30:23 ###########
########## Tcl recorder starts at 10/05/14 21:30:24 ##########
# Commands to make the Process:
# JEDEC File
if [catch {open BUS68030.cmd w} rspFile] {
puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
} else {
puts $rspFile "STYFILENAME: 68030_tk.sty
PROJECT: BUS68030
WORKING_PATH: \"$proj_dir\"
MODULE: BUS68030
VHDL_FILE_LIST: 68030-68000-bus.vhd
OUTPUT_FILE_NAME: BUS68030
SUFFIX_NAME: edi
PART: M4A5-128/64-10VC
"
close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
file delete BUS68030.cmd
if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [catch {open 68030_tk.rsp w} rspFile] {
puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
} else {
puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
"
close $rspFile
}
if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
file delete 68030_tk.rsp
if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
########## Tcl recorder end at 10/05/14 21:30:24 ###########
########## Tcl recorder starts at 10/05/14 21:32:32 ##########
# Commands to make the Process:
# Hierarchy
if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
########## Tcl recorder end at 10/05/14 21:32:32 ###########
########## Tcl recorder starts at 10/05/14 21:32:32 ##########
# Commands to make the Process:
# JEDEC File
if [catch {open BUS68030.cmd w} rspFile] {
puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
} else {
puts $rspFile "STYFILENAME: 68030_tk.sty
PROJECT: BUS68030
WORKING_PATH: \"$proj_dir\"
MODULE: BUS68030
VHDL_FILE_LIST: 68030-68000-bus.vhd
OUTPUT_FILE_NAME: BUS68030
SUFFIX_NAME: edi
PART: M4A5-128/64-10VC
"
close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
file delete BUS68030.cmd
if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires -err automake.err -family"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\" -err \"automake.err\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/impsrc\" -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt 68030_tk.b2_"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3 @68030_tk.b2_"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft 68030_tk.d0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err @68030_tk.d0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit 68030_tk.l0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030 @68030_tk.l0"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [catch {open 68030_tk.rsp w} rspFile] {
puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
} else {
puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\"
"
close $rspFile
}
if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
file delete 68030_tk.rsp
if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
return
} else {
vwait done
if [checkResult $done] {
return
}
}
########## Tcl recorder end at 10/05/14 21:32:32 ###########

2
Logic/68030_tk.crf
View File

@ -1,7 +1,7 @@
// Signal Name Cross Reference File
// ispLEVER Classic 1.7.00.05.28.13
// Design '68030_tk' created Sun Oct 05 00:12:41 2014
// Design '68030_tk' created Sun Oct 05 21:32:39 2014
// LEGEND: '>' Functional Block Port Separator

BIN
Logic/68030_tk.ipr
View File

Binary file not shown.

2
Logic/BUS68030.prj
View File

@ -1,6 +1,6 @@
#-- Lattice Semiconductor Corporation Ltd.
#-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
#-- Written on Sun Oct 05 00:12:34 2014
#-- Written on Sun Oct 05 21:32:32 2014
#device options

4
Logic/Programming.xcf
View File

@ -19,8 +19,8 @@
<BScanVal>0</BScanVal>
</Bypass>
<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
<FileTime>10/05/14 00:12:48</FileTime>
<JedecChecksum>0x0375</JedecChecksum>
<FileTime>10/05/14 21:32:45</FileTime>
<JedecChecksum>0x4FC8</JedecChecksum>
<Operation>Erase,Program,Verify</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>

15
Logic/bus68030.srf
View File

@ -6,7 +6,7 @@
#Implementation: logic
$ Start of Compile
#Sun Oct 05 00:12:35 2014
#Sun Oct 05 21:32:33 2014
Synopsys VHDL Compiler, version comp201209rcp1, Build 283R, built Mar 19 2013
@N|Running in 64-bit mode
@ -15,7 +15,6 @@ Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentatio
@N: CD720 :"C:\Program Files (x86)\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
@W: CD266 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":235:47:235:51|reset is not readable. This may cause a simulation mismatch.
VHDL syntax check successful!
@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral
@W: CD604 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":217:5:217:18|OTHERS clause is not synthesized
@ -47,7 +46,7 @@ State machine has 8 reachable states with original encodings of:
111
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Oct 05 00:12:35 2014
# Sun Oct 05 21:32:33 2014
###########################################################]
Map & Optimize Report
@ -71,16 +70,16 @@ original code -> new code
Resource Usage Report
Simple gate primitives:
DFFSH 28 uses
DFFRH 18 uses
DFF 34 uses
DFFSH 28 uses
BI_DIR 13 uses
IBUF 31 uses
OBUF 16 uses
BUFTH 1 use
AND2 244 uses
INV 186 uses
OR2 21 uses
AND2 231 uses
INV 181 uses
OR2 23 uses
XOR2 9 uses
@ -91,6 +90,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Oct 05 00:12:36 2014
# Sun Oct 05 21:32:34 2014
###########################################################]

2
Logic/run_options.txt
View File

@ -1,7 +1,7 @@
#-- Synopsys, Inc.
#-- Version G-2012.09LC-SP1
#-- Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
#-- Written on Sun Oct 05 00:12:35 2014
#-- Written on Sun Oct 05 21:32:33 2014
#project files

10
Logic/synlog/bus68030_fpga_mapper.srr
View File

@ -17,16 +17,16 @@ original code -> new code
Resource Usage Report
Simple gate primitives:
DFFSH 28 uses
DFFRH 18 uses
DFF 34 uses
DFFSH 28 uses
BI_DIR 13 uses
IBUF 31 uses
OBUF 16 uses
BUFTH 1 use
AND2 244 uses
INV 186 uses
OR2 21 uses
AND2 231 uses
INV 181 uses
OR2 23 uses
XOR2 9 uses
@ -37,6 +37,6 @@ Mapper successful!
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 31MB peak: 96MB)
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Oct 05 00:12:36 2014
# Sun Oct 05 21:32:34 2014
###########################################################]

2
Logic/synlog/report/BUS68030_compiler_errors.txt
View File

@ -1,3 +1,3 @@
@E: CD255 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":496:50:496:50|No identifier "as" in scope
@E: CG103 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":498:68:498:71|Expecting expression
@E|Parse errors encountered - exiting

4
Logic/synlog/report/BUS68030_compiler_runstatus.xml
View File

@ -18,7 +18,7 @@ The file contains the job information from compiler to be displayed as part of t
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
</info>
<info name="Warnings">
<data>15</data>
<data>14</data>
<report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
</info>
<info name="Errors">
@ -35,7 +35,7 @@ The file contains the job information from compiler to be displayed as part of t
<data>-</data>
</info>
<info name="Date &amp;Time">
<data type="timestamp">1412460755</data>
<data type="timestamp">1412537553</data>
</info>
</job_info>
</job_run_status>

1
Logic/synlog/report/BUS68030_compiler_warnings.txt
View File

@ -1,4 +1,3 @@
@W: CD266 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":235:47:235:51|reset is not readable. This may cause a simulation mismatch.
@W: CD604 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":217:5:217:18|OTHERS clause is not synthesized
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":125:7:125:20|Signal clk_out_pre_33 is undriven
@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:22|Signal clk_out_pre_33_d is undriven

2
Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
View File

@ -39,7 +39,7 @@ The file contains the job information from mapper to be displayed as part of the
<data>96MB</data>
</info>
<info name="Date &amp; Time">
<data type="timestamp">1412460756</data>
<data type="timestamp">1412537554</data>
</info>
</job_info>
</job_run_status>

2
Logic/syntmp/run_option.xml
View File

@ -3,7 +3,7 @@
Synopsys, Inc.
Version G-2012.09LC-SP1
Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
Written on Sun Oct 05 00:12:35 2014
Written on Sun Oct 05 21:32:33 2014
-->

2
Logic/synwork/BUS68030_compiler.fdep
View File

@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412460751
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412537547
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

2
Logic/synwork/BUS68030_compiler.fdeporig
View File

@ -10,7 +10,7 @@
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1363694328
#CUR:"C:\\Program Files (x86)\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1363694328
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412460751
#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1412537547
0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
# Dependency Lists (Uses list)

BIN
Logic/synwork/BUS68030_compiler.srs
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