diff --git a/Logic/68030-68000-bus-2.vhd b/Logic/68030-68000-bus-2.vhd
new file mode 100644
index 0000000..f8934ff
--- /dev/null
+++ b/Logic/68030-68000-bus-2.vhd
@@ -0,0 +1,609 @@
+-- Copyright: Matthias Heinrichs 2014
+-- Free for non-comercial use
+-- No warranty just for fun
+-- If you want to earn money with this code, ask me first!
+
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity BUS68030 is
+
+port( 
+	AS_030: inout std_logic ;
+	AS_000: inout std_logic ;
+	RW_000: inout std_logic ;
+	DS_030: inout std_logic ;
+	UDS_000: inout std_logic;
+	LDS_000: inout std_logic;
+	SIZE: inout std_logic_vector ( 1 downto 0 );
+	A: in std_logic_vector ( 31 downto 2 );
+	A0: inout std_logic;
+	A1: in std_logic;
+	nEXP_SPACE: in std_logic ;
+	BERR: inout std_logic ;
+	BG_030: in std_logic ;
+	BG_000: out std_logic ;
+	BGACK_030: out std_logic ;
+	BGACK_000: in std_logic ;
+	CLK_030: in std_logic ;
+	CLK_000: in std_logic ;
+	CLK_OSZI: in std_logic ;
+	CLK_DIV_OUT: out std_logic ;
+	CLK_EXP: out std_logic	; 
+	FPU_CS: out std_logic ;
+	FPU_SENSE: in std_logic ;
+	IPL_030: out std_logic_vector ( 2 downto 0 );
+	IPL: in std_logic_vector ( 2 downto 0 );
+	DSACK1: inout std_logic;
+	DTACK: inout std_logic ;
+	AVEC: out std_logic ;
+	E: out std_logic ;
+	VPA: in std_logic ;
+	VMA: out std_logic ;
+	RST: in std_logic ;
+	RESET: inout std_logic ;
+	RW: inout std_logic ;
+--	D: inout std_logic_vector ( 31 downto 28 );
+	FC: in std_logic_vector ( 1 downto 0 );
+	AMIGA_ADDR_ENABLE: out std_logic ;
+	AMIGA_BUS_DATA_DIR: out std_logic ;
+	AMIGA_BUS_ENABLE_LOW: out std_logic;
+	AMIGA_BUS_ENABLE_HIGH: out std_logic;
+	CIIN: out std_logic
+	);
+end BUS68030;
+
+architecture Behavioral of BUS68030 is
+
+
+
+
+TYPE SM_E IS (
+				E1,
+				E2,
+				E3,
+				E4,
+				E5,
+				E6,
+				E7,
+				E8,
+				E9,
+				E10
+				);
+
+
+
+signal cpu_est : SM_E;
+
+TYPE SM_68000 IS (
+				IDLE_P,
+				IDLE_N,
+				AS_SET_P,
+				AS_SET_N,
+				SAMPLE_DTACK_P,
+				DATA_FETCH_N,
+				DATA_FETCH_P,
+				END_CYCLE_N
+				);
+
+
+signal SM_AMIGA : SM_68000;
+  
+--signal	Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
+signal	AS_000_INT:STD_LOGIC		:= '1';
+signal	RW_000_INT:STD_LOGIC		:= '1';
+signal	AMIGA_BUS_ENABLE_INT:STD_LOGIC		:= '1';
+signal	AMIGA_BUS_ENABLE_DMA_HIGH:STD_LOGIC		:= '1';
+signal	AMIGA_BUS_ENABLE_DMA_LOW:STD_LOGIC		:= '1';
+signal	AS_030_D0:STD_LOGIC			:= '1';
+signal	nEXP_SPACE_D0:STD_LOGIC		:= '0';
+signal	DS_030_D0:STD_LOGIC			:= '1';
+signal	AS_030_000_SYNC:STD_LOGIC	:= '1';
+signal	BGACK_030_INT:STD_LOGIC		:= '1';
+signal	BGACK_030_INT_D:STD_LOGIC	:= '1';
+signal	BGACK_030_INT_PRE:STD_LOGIC	:= '1';
+signal	AS_000_DMA:STD_LOGIC		:= '1';
+signal	DS_000_DMA:STD_LOGIC		:= '1';
+signal	RW_000_DMA:STD_LOGIC		:= '1';
+signal  CYCLE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) 	:= "00";
+signal  SIZE_DMA: STD_LOGIC_VECTOR ( 1 downto 0 ) 	:= "11";
+signal  IPL_D0: STD_LOGIC_VECTOR ( 2 downto 0 ) 	:= "111";
+signal	A0_DMA: STD_LOGIC			:= '1';
+signal	VMA_INT: STD_LOGIC			:= '1';
+signal	VPA_D: STD_LOGIC			:= '1';
+signal	UDS_000_INT: STD_LOGIC		:= '1';
+signal	LDS_000_INT: STD_LOGIC		:= '1';
+signal	DS_000_ENABLE: STD_LOGIC	:= '0';
+signal  DSACK1_INT: STD_LOGIC		:= '1';
+signal	CLK_OUT_PRE_50: STD_LOGIC	:= '1';
+signal	CLK_OUT_PRE_25: STD_LOGIC	:= '1';
+signal	CLK_OUT_PRE: STD_LOGIC		:= '1';
+signal	CLK_OUT_PRE_D: STD_LOGIC	:= '1';
+signal	CLK_OUT_INT: STD_LOGIC		:= '1';
+signal	CLK_030_H: STD_LOGIC		:= '1';
+signal	CLK_000_D0: STD_LOGIC 		:= '1';
+signal	CLK_000_D1: STD_LOGIC 		:= '1';
+signal	CLK_000_D2: STD_LOGIC 		:= '1';
+signal	CLK_000_D3: STD_LOGIC 		:= '1';
+signal	CLK_000_D4: STD_LOGIC 		:= '1';
+signal	CLK_000_P_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) 	:= "0000000000000";
+signal	CLK_000_N_SYNC: STD_LOGIC_VECTOR ( 12 downto 0 ) 	:= "0000000000000";
+signal	CLK_000_PE: STD_LOGIC 		:= '0';
+signal	CLK_000_NE: STD_LOGIC 		:= '0';
+signal	CLK_000_NE_D0: STD_LOGIC 		:= '0';
+signal	DTACK_D0: STD_LOGIC 		:= '1';
+signal  RESET_OUT: STD_LOGIC 		:= '0';
+signal	CLK_030_D0: STD_LOGIC 		:= '0';
+--signal  NO_RESET: STD_LOGIC 		:= '0';
+signal	RST_DLY: STD_LOGIC_VECTOR ( 2 downto 0 ) 	:= "000";
+--signal	RST_DLY_AMIGA: STD_LOGIC_VECTOR ( 7 downto 0 ) 	:= "00000000";
+--signal  RESET_OUT_AMIGA: STD_LOGIC 		:= '0';
+begin
+
+	--pos edge clock process
+	--no ansynchronious reset! the reset is sampled synchroniously
+	--this mut be because of the e-clock: The E-Clock has to run CONSTANTLY 
+	--or the Amiga will fail to boot from a reset. 
+	--However a compilation with no resets on thEe-Clock and resets on other signals does not work, either!
+	pos_clk: process(CLK_OSZI)
+	begin
+		if(rising_edge(CLK_OSZI)) then
+			--clk generation :
+			CLK_030_D0 <=CLK_030;
+		  CLK_OUT_PRE_50	<=	not CLK_OUT_PRE_50;		  
+		  if(CLK_OUT_PRE_50 = '1' )then
+		  	CLK_OUT_PRE_25<=	not CLK_OUT_PRE_25;		    
+		  end if;
+						
+			
+			--here the clock is selected
+			CLK_OUT_PRE_D 	<= CLK_OUT_PRE_50;
+			
+			-- the external clock to the processor is generated here
+			CLK_OUT_INT	<= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
+			--delayed Clocks and signals for edge detection
+			CLK_000_D0 	<= CLK_000;
+			CLK_000_D1 	<= CLK_000_D0;
+			CLK_000_D2 	<= CLK_000_D1;
+			CLK_000_D3 	<= CLK_000_D2;
+			CLK_000_D4 	<= CLK_000_D3;
+
+			--shift registers for edge detection
+			CLK_000_P_SYNC( 12 downto 1 ) 	<= CLK_000_P_SYNC( 11 downto 0 );
+			CLK_000_P_SYNC(0)				<= CLK_000_D0 AND NOT CLK_000_D1;
+			CLK_000_N_SYNC( 12 downto 1 ) 	<= CLK_000_N_SYNC( 11 downto 0 );
+			CLK_000_N_SYNC(0)				<= NOT CLK_000_D0 AND CLK_000_D1;
+			
+			-- values are determined empiracally for 7.09 MHz Clock
+			-- since the clock is not symmetrically these values differ!
+			CLK_000_PE <= CLK_000_P_SYNC(9);
+			CLK_000_NE <= CLK_000_N_SYNC(11);
+			CLK_000_NE_D0 <= CLK_000_NE;
+			
+			-- e-clock is changed on the FALLING edge!
+
+			if(CLK_000_NE_D0 = '1' ) then
+			--if(CLK_000_D0='0' AND CLK_000_D1='1') then
+				case (cpu_est) is
+					when E1 => cpu_est <= E2 ; 
+					when E2 => cpu_est <= E3 ;
+					when E3 => cpu_est <= E4;
+					when E4  => cpu_est <= E5 ;
+					when E5  => cpu_est <= E6 ;
+					when E6  => cpu_est <= E7 ;
+					when E7  => cpu_est <= E8 ;
+					when E8  => cpu_est <= E9 ;
+					when E9  => cpu_est <= E10;
+					when E10 => cpu_est <= E1 ;
+				end case;
+			end if;
+			
+			--this is a statemachine to propagate an internal reset to the amiga
+			--if(	(RESET = '0' and RESET_OUT = '1') or RST_DLY_AMIGA /= "11111111") then --reset condition from the tk-board
+			--	if(RST_DLY_AMIGA = "11111111") then --start of reset
+			--		RESET_OUT_AMIGA <= '1';
+			--		RST_DLY_AMIGA <= "00000000";
+			--	else
+			--		RST_DLY_AMIGA <= RST_DLY_AMIGA+1;
+			--	end if;					
+			--else
+			--	RST_DLY_AMIGA	<= "11111111";
+			--	RESET_OUT_AMIGA <= '0';
+			--end if;
+
+			
+			--the statemachine
+			if(RST = '0' ) then
+				VPA_D			<= '1';
+				DTACK_D0		<= '1';
+				SM_AMIGA		<= IDLE_P;
+				AS_000_INT 		<= '1';
+				RW_000_INT		<= '1';
+				RW_000_DMA		<= '1';
+				AS_030_000_SYNC <= '1';
+				UDS_000_INT		<= '1';
+				LDS_000_INT		<= '1';
+				DS_000_ENABLE	<= '0';
+				VMA_INT			<= '1';
+				BG_000			<= '1';
+				BGACK_030_INT	<= '1';
+				BGACK_030_INT_D <= '1';
+				BGACK_030_INT_PRE<= '1';
+				DSACK1_INT		<= '1';
+				IPL_D0			<= "111";
+				IPL_030			<= "111";
+				AS_000_DMA		<= '1';
+				DS_000_DMA		<= '1';
+				SIZE_DMA		<= "11";
+				A0_DMA			<= '1';
+				AMIGA_BUS_ENABLE_INT <= '1';
+				AMIGA_BUS_ENABLE_DMA_HIGH <= '1';
+				AMIGA_BUS_ENABLE_DMA_LOW <= '1';
+				AS_030_D0		<= '1';
+				nEXP_SPACE_D0	<= '1';
+				DS_030_D0		<= '1';
+				CLK_030_H		<= '0';	
+				CYCLE_DMA		<= "00";
+				RST_DLY			<= "000";
+				RESET_OUT 		<= '0';
+			else 
+				
+				if(CLK_000_NE='1')then
+					if(RST_DLY="111")then
+						RESET_OUT 		<= '1';
+					else
+						RST_DLY <= RST_DLY+1;						
+					end if;
+				end if;
+
+				--now: 68000 state machine and signals
+				
+				--buffering signals
+				AS_030_D0 <= AS_030;
+				nEXP_SPACE_D0 <= nEXP_SPACE;
+				DS_030_D0 <= DS_030;
+				DTACK_D0	<= DTACK;
+				VPA_D 		<= VPA;
+	
+
+				--bgack is simple: assert as soon as Amiga asserts but hold bg_ack for one amiga-clock 
+				if(BGACK_000='0') then
+					BGACK_030_INT	<= '0';
+				elsif (	BGACK_000='1' 
+						AND CLK_000_PE='1'
+						AND AS_000 = '1' --the amiga AS can be still active while bgack is deasserted, so wait for this signal too!
+						--AND CLK_000_D0='1' and CLK_000_D1='0'
+						) then -- BGACK_000 is high here!
+					BGACK_030_INT_PRE<= '1';
+					BGACK_030_INT 	<= BGACK_030_INT_PRE; --hold this signal high until 7m clock goes low
+				end if;
+				BGACK_030_INT_D <= BGACK_030_INT;
+	
+				
+	
+				--bus grant only in idle state
+				if(BG_030= '1')then
+					BG_000	<= '1';
+				elsif(	BG_030= '0' --AND (SM_AMIGA 	= IDLE_P)
+						and nEXP_SPACE_D0 = '1' and AS_030_D0='1'
+						and CLK_000_D0='1' 
+						--and CLK_000_D0='1' AND CLK_000_D1='0'  
+						) then --bus granted no local access and no AS_030 running!
+						BG_000 	<= '0';
+				end if;
+	
+			
+				--interrupt buffering to avoid ghost interrupts
+				--if(CLK_000_NE='1')then
+				--if(CLK_000_D0='0' and CLK_000_D1='1')then
+					IPL_D0<=IPL;			
+					if(IPL = IPL_D0)then
+						IPL_030<=IPL;
+					end if;
+				--end if;
+			
+				-- as030-sampling and FPU-Select
+	
+				
+				if(AS_030_D0 ='1' or BERR='0') then -- "async" reset of various signals
+					AS_030_000_SYNC <= '1';
+					DSACK1_INT		<= '1';
+					AS_000_INT  	<= '1';
+					DS_000_ENABLE	<= '0';
+					--RW_000_INT		<= '1';	
+				elsif(	--CLK_030  		= '1'  AND --68030 has a valid AS on high clocks					
+						AS_030_D0			= '0'  AND --as set
+						BGACK_030_INT='1' AND 
+						BGACK_030_INT_D='1' AND --no dma -cycle
+						NOT (FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0') AND --FPU-Select
+						nEXP_SPACE_D0 ='1' and --not an expansion space cycle
+						SM_AMIGA = IDLE_P --last amiga cycle terminated
+						) then
+						AS_030_000_SYNC <= '0';					
+				end if;
+				
+	
+				-- VMA generation
+				if(CLK_000_NE='1' AND VPA_D='0' AND cpu_est = E4)then --assert
+				--if(CLK_000_D0='0' AND CLK_000_D1='1' AND VPA_D='0' AND cpu_est = E4)then --assert
+					VMA_INT <= '0';
+				elsif(CLK_000_PE='1' AND cpu_est=E1)then --deassert
+					VMA_INT <= '1';										
+				end if;
+				
+				--uds/lds precalculation
+				if (SM_AMIGA = IDLE_N) then --DS: set udl/lds 	
+					if(A0='0') then
+						UDS_000_INT <= '0';
+					else
+						UDS_000_INT <= '1';
+					end if;
+					if((A0='1' OR SIZE(0)='0' OR SIZE(1)='1')) then
+						LDS_000_INT <= '0';
+					else
+						LDS_000_INT <= '1';
+					end if;
+				end if;
+	
+	
+				--Amiga statemachine
+	
+				if(BERR='0')then --"async" reset on errors
+					SM_AMIGA<=IDLE_P;
+				end if;
+	
+				case (SM_AMIGA) is
+					when IDLE_P 	 => --68000:S0 wait for a falling edge
+						RW_000_INT		<= '1';		
+						AMIGA_BUS_ENABLE_INT <= CLK_000_D1;
+						if( CLK_000_D0='0' and CLK_000_D1= '1' and AS_030_000_SYNC = '0' and nEXP_SPACE_D0 ='1')then -- if this a delayed expansion space detection, do not start an amiga cycle!
+							SM_AMIGA<=IDLE_N;  --go to s1
+						end if;
+					when IDLE_N 	 => --68000:S1 place Adress on bus and wait for rising edge, on a rising CLK_000 look for a amiga adressrobe
+						AMIGA_BUS_ENABLE_INT <= '0' ;--for now: allways on for amiga
+						if(CLK_000_PE='1')then --go to s2
+						--if(CLK_000_D0='1')then --go to s2
+							SM_AMIGA <= AS_SET_P; --as for amiga set! 
+						end if;
+					when AS_SET_P	 => --68000:S2 Amiga cycle starts here: since AS is asserted during transition to this state we simply wait here
+						RW_000_INT <= RW;						
+						AS_000_INT <= '0';
+						if (RW='1' ) then --read: set udl/lds 	
+							DS_000_ENABLE	<= '1';
+						end if;
+						if(CLK_000_NE='1')then --go to s3
+						--if(CLK_000_D0='0')then --go to s3
+							SM_AMIGA<=AS_SET_N; 
+						end if;
+					when AS_SET_N	 => --68000:S3: nothing happens here; on a transition to s4: assert uds/lds on write 
+						
+						if(CLK_000_PE='1')then --go to s4
+						--if(CLK_000_D0='1')then --go to s4
+							-- set DS-Enable without respect to rw: this simplifies the life for the syntesizer
+							DS_000_ENABLE	<= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late 				 
+							SM_AMIGA <= SAMPLE_DTACK_P; 
+						end if;
+					when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
+						DS_000_ENABLE	<= '1';
+						if(	CLK_000_NE_D0='1' and --falling edge
+						--if(	CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge
+							((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
+							(VPA_D='0' AND cpu_est=E9 AND VMA_INT='0')) --VPA end cycle
+							)then --go to s5
+							SM_AMIGA<=DATA_FETCH_N;
+						end if;
+					when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
+						DS_000_ENABLE	<= '1';
+						if(CLK_000_PE = '1')then --go to s6
+						--if(CLK_000_D0='1')then --go to s6
+							SM_AMIGA<=DATA_FETCH_P;
+						end if;
+					when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
+						DS_000_ENABLE	<= '1';
+						if( (CLK_000_N_SYNC( 8)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
+							(CLK_000_N_SYNC(9)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
+							DSACK1_INT <='0'; 
+						end if;
+						--if( CLK_000_D3 ='1' AND CLK_000_D4 = '0' ) then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
+						--	DSACK1_INT <='0'; 
+						--end if;
+						if( CLK_000_NE ='1') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
+						--if( CLK_000_D0 ='0') then --go to s7 next 030-clock is high: dsack is sampled at the falling edge
+							--DSACK1_INT <='0'; 
+							SM_AMIGA<=END_CYCLE_N;
+						end if;
+					when END_CYCLE_N =>--68000:S7: Latch/Store data. Wait here for new cycle and go to IDLE on high clock
+						if(CLK_000_PE='1')then --go to s0	
+						--if(CLK_000_D0='1')then --go to s0																	
+							SM_AMIGA<=IDLE_P;	
+							RW_000_INT		<= '1';	
+							--AMIGA_BUS_ENABLE_INT <= '1';					
+						end if;
+				end case;
+	
+				--dma stuff
+				if(BGACK_030_INT='0')then			
+					--switch amiga bus on for DMA-Cycles
+					AMIGA_BUS_ENABLE_INT <= '0' ;
+					--set some signals NOT linked to AS_000='0'
+					RW_000_DMA	<= RW_000;
+					-- now determine the size: if both uds and lds is set its 16 bit else 8 bit!
+					if(UDS_000='0' and LDS_000='0') then
+						SIZE_DMA		<= "10"; --16bit
+					else
+						SIZE_DMA		<= "01"; --8 bit
+					end if;
+					--now calculate the offset: 
+					--if uds is set low, a0 is so too.
+					--if only lds is set a1 is high
+					--therefore a1 = uds 
+					--great! life is simple here!
+					A0_DMA <= UDS_000;		
+					--A1 is set by the amiga side													
+					--here  we determine the upper or lower half of the databus
+					AMIGA_BUS_ENABLE_DMA_HIGH 	<= A1;
+					AMIGA_BUS_ENABLE_DMA_LOW 	<= not A1;				
+	
+				elsif(BGACK_030_INT_D='0' and BGACK_030_INT='1')then			
+					AMIGA_BUS_ENABLE_INT <= '1' ;
+					RW_000_DMA		<= '1';	
+					SIZE_DMA		<= "00";
+					A0_DMA			<= '0';	
+					AMIGA_BUS_ENABLE_DMA_HIGH 	<= '1';
+					AMIGA_BUS_ENABLE_DMA_LOW 	<= '1';				
+				end if;
+						
+				if(BGACK_030_INT='0' and AS_000='0')then 
+					-- an 68000-memory cycle is three positive edges long!
+					if(CLK_000_P_SYNC(10)='1')then
+						CYCLE_DMA <= CYCLE_DMA+1;
+					end if;
+				else
+					CYCLE_DMA		<= "00";
+				end if;		
+											
+				--as can only be done if we know the uds/lds!
+				if(	BGACK_030_INT='0'
+					and AS_000='0' 
+					and(UDS_000='0' or LDS_000='0')
+					and (					
+						--CYCLE_DMA ="00" or
+						CYCLE_DMA ="01"
+						or CYCLE_DMA ="10"
+						--or CYCLE_DMA ="11"
+						)				
+					)then 
+					--set AS_000
+					if( CLK_030='1') then 
+						AS_000_DMA 	<= '0'; --sampled on rising edges!					
+					end if;
+					
+					--delayed clock for write cycle
+					if(AS_000_DMA = '0' and CLK_030='0')then
+						CLK_030_H		<= '1';
+					end if;
+					
+					if(RW_000='1') then
+						DS_000_DMA	<='0';
+					elsif(RW_000='0' and CLK_030_H = '1' and CLK_030='1')then
+						DS_000_DMA	<=AS_000_DMA; -- write: one clock delayed!
+					end if;					
+				else
+					AS_000_DMA		<= '1';
+					DS_000_DMA		<= '1';
+					CLK_030_H		<= '0';		
+				end if;		
+			end if;					
+		end if;
+	end process pos_clk;
+
+	--output clock assignment
+	CLK_DIV_OUT	<= CLK_OUT_INT;
+	CLK_EXP		<= CLK_OUT_INT;
+	--CLK_DIV_OUT	<= 'Z';
+	--CLK_EXP		<= CLK_030;
+
+
+	
+	RESET	<= 'Z' when RESET_OUT ='1' else '0';
+	--RST		<= '0' when RESET_OUT_AMIGA = '1' else 'Z';
+	--RESET	<=  RESET_OUT;
+
+	-- bus drivers
+	--AMIGA_ADDR_ENABLE	<= AMIGA_BUS_ENABLE_INT;
+	AMIGA_ADDR_ENABLE	<= '0';
+	AMIGA_BUS_ENABLE_HIGH <= '0' WHEN BGACK_030_INT ='1' and not (SM_AMIGA = IDLE_P) ELSE 
+							 '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_HIGH = '0' ELSE
+							 '1';
+	AMIGA_BUS_ENABLE_LOW <=  '0' WHEN BGACK_030_INT ='0' AND AMIGA_BUS_ENABLE_DMA_LOW = '0'   ELSE
+							 '1';  
+	
+	
+	AMIGA_BUS_DATA_DIR 	 <= '1' WHEN (RW_000='0' AND BGACK_030_INT ='1') ELSE --Amiga WRITE
+							'0' WHEN (RW_000='1' AND BGACK_030_INT ='1') ELSE --Amiga READ
+							'1' WHEN (RW_000='1' AND BGACK_030_INT ='0' AND nEXP_SPACE_D0 = '0' AND AS_000 = '0') ELSE --DMA READ to expansion space
+							'0' WHEN (RW_000='0' AND BGACK_030_INT ='0' AND AS_000 = '0') ELSE --DMA WRITE to expansion space
+							'0'; --Point towarts TK
+	
+	
+	--dma stuff
+	DTACK	<= 	'Z';
+	--DTACK	<= 	'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
+	--			'0' when DSACK1 ='0' else 
+	--		   	'1';
+	AS_030	<= 	'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' or RESET_OUT ='0' else
+			   	'0' when AS_000_DMA ='0' and AS_000 ='0' else 
+			   	'1';
+	DS_030	<= 	'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' or RESET_OUT ='0' else
+				'0' when DS_000_DMA ='0' and AS_000 ='0' else 
+			   	'1';
+	A0		<= 	'Z' when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' or RESET_OUT ='0' else
+				'0' when A0_DMA ='0' else 
+			   	'1';
+	SIZE	<= 	"ZZ" when BGACK_030_INT ='1' OR nEXP_SPACE_D0 = '1' else
+				"10" when SIZE_DMA ="10" else 
+			   	"01" when SIZE_DMA ="01" else
+			   	"00";
+	--rw
+	RW		<= 	'Z' when BGACK_030_INT ='1' or RESET_OUT ='0' else
+				'0' when RW_000_DMA ='0' else 
+			   	'1';
+	
+	BGACK_030	<= BGACK_030_INT;	
+
+	--fpu
+	FPU_CS		<=	'0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='0'
+					else '1';
+	
+	--if no copro is installed:
+	BERR		<=	'0' when AS_030 ='0' and FC(1)='1' and FC(0)='1' and A(19)='0' and A(18)='0' and A(17)='1' and A(16)='0' AND BGACK_000='1' AND FPU_SENSE ='1'
+					else 'Z';
+	--BERR		<=	'Z';
+
+
+
+	--cache inhibit:  Tristate for expansion (it decides) and off for the Amiga 
+	CIIN <= '1' WHEN A(31 downto 20) = x"00F" and AS_030_D0 ='0' ELSE -- Enable for Kick-rom
+			'Z' WHEN nEXP_SPACE_D0 = '0' ELSE --Tristate for expansion (it decides)
+			'0'; --off for the Amiga
+		
+	--e and VMA		
+	E		<= '1' when 
+							cpu_est = E7 or
+							cpu_est = E8 or
+							cpu_est = E9 or
+							cpu_est = E10 						
+						else '0';
+	VMA		<= VMA_INT;
+	
+	
+	--AVEC
+	AVEC 	<=	'1';
+		
+	--as and uds/lds
+	AS_000	<=  'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else
+				'0' when AS_000_INT ='0' and AS_030 ='0' else 
+			   	'1';
+	RW_000	<=  'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else
+				'0' when RW_000_INT ='0' else 
+			   	'1';
+
+	UDS_000	<=  'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else -- output on cpu cycle
+			    --'1' when DS_000_ENABLE ='0' else 
+				'0' when UDS_000_INT ='0' and DS_000_ENABLE ='1' else -- datastrobe not ready jet
+			   	'1';
+	LDS_000	<= 	'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else -- output on cpu cycle
+			   	--'1' when DS_000_ENABLE ='0' else 
+				'0' when LDS_000_INT ='0' and DS_000_ENABLE ='1' else -- datastrobe not ready jet
+			   	'1';
+
+	--dsack
+	DSACK1	<= 	'Z' when nEXP_SPACE_D0 = '0' else -- output on amiga cycle
+				'0' when DSACK1_INT ='0' else 
+			   	'1';
+	
+end Behavioral;
\ No newline at end of file
diff --git a/Logic/68030-68000-bus.vhd b/Logic/68030-68000-bus.vhd
index 41bdf8d..dc6c66d 100644
--- a/Logic/68030-68000-bus.vhd
+++ b/Logic/68030-68000-bus.vhd
@@ -60,40 +60,38 @@ end BUS68030;
 architecture Behavioral of BUS68030 is
 
 
-subtype ESTATE is std_logic_vector(3 downto 0);
-  
-constant E1  : ESTATE := "0110";
-constant E2  : ESTATE := "0111";  
-constant E3  : ESTATE := "0100";  
-constant E4  : ESTATE := "0101";  
-constant E5  : ESTATE := "0010";  
-constant E6  : ESTATE := "0011";  
-constant E7  : ESTATE := "1010";  
-constant E8  : ESTATE := "1011";  
-constant E9  : ESTATE := "1100";  
-constant E10 : ESTATE := "1111";
--- Illegal states  
-constant E20 : ESTATE := "0000";  
-constant E4a : ESTATE := "0001";  
-constant E21 : ESTATE := "1000";  
-constant E22 : ESTATE := "1001";  
-constant E23 : ESTATE := "1101";  
-constant E24 : ESTATE := "1110";  
 
-signal cpu_est : ESTATE;
 
-subtype AMIGA_STATE is std_logic_vector(2 downto 0);
-  
-constant IDLE_P		 : AMIGA_STATE := "000";
-constant IDLE_N		 : AMIGA_STATE := "001";
-constant AS_SET_P	 : AMIGA_STATE := "010";  
-constant AS_SET_N	 : AMIGA_STATE := "011";  
-constant SAMPLE_DTACK_P: AMIGA_STATE := "100";  
-constant DATA_FETCH_N: AMIGA_STATE := "101";  
-constant DATA_FETCH_P : AMIGA_STATE := "110";  
-constant END_CYCLE_N : AMIGA_STATE := "111";  
+TYPE SM_E IS (
+				E1,
+				E2,
+				E3,
+				E4,
+				E5,
+				E6,
+				E7,
+				E8,
+				E9,
+				E10
+				);
 
-signal SM_AMIGA : AMIGA_STATE;
+
+
+signal cpu_est : SM_E;
+
+TYPE SM_68000 IS (
+				IDLE_P,
+				IDLE_N,
+				AS_SET_P,
+				AS_SET_N,
+				SAMPLE_DTACK_P,
+				DATA_FETCH_N,
+				DATA_FETCH_P,
+				END_CYCLE_N
+				);
+
+
+signal SM_AMIGA : SM_68000;
   
 --signal	Dout:STD_LOGIC_VECTOR(3 downto 0) := "0000";
 signal	AS_000_INT:STD_LOGIC		:= '1';
@@ -122,10 +120,11 @@ signal	LDS_000_INT: STD_LOGIC		:= '1';
 signal	DS_000_ENABLE: STD_LOGIC	:= '0';
 signal  DSACK1_INT: STD_LOGIC		:= '1';
 signal	CLK_OUT_PRE_50: STD_LOGIC	:= '1';
-signal	CLK_OUT_PRE_50_D: STD_LOGIC	:= '1';
+signal	CLK_OUT_PRE_25: STD_LOGIC	:= '1';
 signal	CLK_OUT_PRE: STD_LOGIC		:= '1';
 signal	CLK_OUT_PRE_D: STD_LOGIC	:= '1';
 signal	CLK_OUT_INT: STD_LOGIC		:= '1';
+signal	CLK_OUT_EXP_INT: STD_LOGIC		:= '1';
 signal	CLK_030_H: STD_LOGIC		:= '1';
 signal	CLK_000_D0: STD_LOGIC 		:= '1';
 signal	CLK_000_D1: STD_LOGIC 		:= '1';
@@ -156,15 +155,18 @@ begin
 		if(rising_edge(CLK_OSZI)) then
 			--clk generation :
 			CLK_030_D0 <=CLK_030;
-		    CLK_OUT_PRE_50	<=	not CLK_OUT_PRE_50;
-		    CLK_OUT_PRE_50_D<=	CLK_OUT_PRE_50;		    
+		  CLK_OUT_PRE_50	<=	not CLK_OUT_PRE_50;		  
+		  if(CLK_OUT_PRE_50 = '1' )then
+		  	CLK_OUT_PRE_25<=	not CLK_OUT_PRE_25;		    
+		  end if;
 						
 			
 			--here the clock is selected
-			CLK_OUT_PRE_D 	<= CLK_OUT_PRE_50;
+			CLK_OUT_PRE_D 	<= CLK_OUT_PRE_25;
 			
 			-- the external clock to the processor is generated here
 			CLK_OUT_INT	<= CLK_OUT_PRE_D; --this way we know the clock of the next state: Its like looking in the future, cool!
+			CLK_OUT_EXP_INT <= CLK_OUT_PRE_50;
 			--delayed Clocks and signals for edge detection
 			CLK_000_D0 	<= CLK_000;
 			CLK_000_D1 	<= CLK_000_D0;
@@ -199,15 +201,6 @@ begin
 					when E8  => cpu_est <= E9 ;
 					when E9  => cpu_est <= E10;
 					when E10 => cpu_est <= E1 ;
-					-- Illegal states
-					when E4a => cpu_est <= E5 ;
-					when E20 => cpu_est <= E10;
-					when E21 => cpu_est <= E10;
-					when E22 => cpu_est <= E9 ;
-					when E23 => cpu_est <= E9 ;
-					when E24 => cpu_est <= E10;
-					when others =>
-						null;
 				end case;
 			end if;
 			
@@ -345,7 +338,7 @@ begin
 				end if;
 				
 				--uds/lds precalculation
-				if (DS_030_D0 = '0' AND SM_AMIGA = IDLE_N) then --DS: set udl/lds 	
+				if (SM_AMIGA = IDLE_N) then --DS: set udl/lds 	
 					if(A0='0') then
 						UDS_000_INT <= '0';
 					else
@@ -393,10 +386,11 @@ begin
 						if(CLK_000_PE='1')then --go to s4
 						--if(CLK_000_D0='1')then --go to s4
 							-- set DS-Enable without respect to rw: this simplifies the life for the syntesizer
+							DS_000_ENABLE	<= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late 				 
 							SM_AMIGA <= SAMPLE_DTACK_P; 
 						end if;
 					when SAMPLE_DTACK_P=> --68000:S4 wait for dtack or VMA
-						DS_000_ENABLE	<= '1';--write: set udl/lds earlier than in the specs. this does not seem to harm anything and is saver, than sampling uds/lds too late 				 
+						DS_000_ENABLE	<= '1';
 						if(	CLK_000_NE_D0='1' and --falling edge
 						--if(	CLK_000_D0 = '0' and CLK_000_D1='1' and --falling edge
 							((VPA_D = '1' AND DTACK_D0='0') OR --DTACK end cycle
@@ -405,11 +399,13 @@ begin
 							SM_AMIGA<=DATA_FETCH_N;
 						end if;
 					when DATA_FETCH_N=> --68000:S5 nothing happens here just wait for positive clock
+						DS_000_ENABLE	<= '1';
 						if(CLK_000_PE = '1')then --go to s6
 						--if(CLK_000_D0='1')then --go to s6
 							SM_AMIGA<=DATA_FETCH_P;
 						end if;
 					when DATA_FETCH_P => --68000:S6: READ: here comes the data on the bus!
+						DS_000_ENABLE	<= '1';
 						if( (CLK_000_N_SYNC( 9)='1' AND not (CLK_030 ='1' and CLK_OUT_PRE_D='0')) OR
 							(CLK_000_N_SYNC(10)='1' )) then --go to s7 next 030-clock is not a falling edge: dsack is sampled at the falling edge
 							DSACK1_INT <='0'; 
@@ -508,10 +504,10 @@ begin
 	end process pos_clk;
 
 	--output clock assignment
-	--CLK_DIV_OUT	<= CLK_OUT_INT;
-	--CLK_EXP		<= CLK_OUT_INT;
-	CLK_DIV_OUT	<= 'Z';
-	CLK_EXP		<= CLK_030;
+	CLK_DIV_OUT	<= CLK_OUT_INT;
+	CLK_EXP		<= not CLK_OUT_EXP_INT;
+	--CLK_DIV_OUT	<= 'Z';
+	--CLK_EXP		<= CLK_030;
 
 
 	
@@ -578,7 +574,12 @@ begin
 			'0'; --off for the Amiga
 		
 	--e and VMA		
-	E		<= cpu_est(3);
+	E		<= '1' when 
+							cpu_est = E7 or
+							cpu_est = E8 or
+							cpu_est = E9 or
+							cpu_est = E10 						
+						else '0';
 	VMA		<= VMA_INT;
 	
 	
@@ -595,11 +596,11 @@ begin
 
 	UDS_000	<=  'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else -- output on cpu cycle
 			    --'1' when DS_000_ENABLE ='0' else 
-				'0' when UDS_000_INT ='0' and DS_000_ENABLE ='1' and DS_030 ='0' else -- datastrobe not ready jet
+				'0' when UDS_000_INT ='0' and DS_000_ENABLE ='1' else -- datastrobe not ready jet
 			   	'1';
 	LDS_000	<= 	'Z' when BGACK_030_INT ='0' or RESET_OUT ='0' else -- output on cpu cycle
 			   	--'1' when DS_000_ENABLE ='0' else 
-				'0' when LDS_000_INT ='0' and DS_000_ENABLE ='1' and DS_030 ='0' else -- datastrobe not ready jet
+				'0' when LDS_000_INT ='0' and DS_000_ENABLE ='1' else -- datastrobe not ready jet
 			   	'1';
 
 	--dsack
diff --git a/Logic/68030_TK.cmi b/Logic/68030_TK.cmi
index 2ce0769..22dd140 100644
--- a/Logic/68030_TK.cmi
+++ b/Logic/68030_TK.cmi
@@ -3,7 +3,7 @@ MAIN_WINDOW_POSITION=2,26,1922,1041
 LEFT_PANE_WIDTH=634
 CHILD_FRAME_STATE=Maximal
 CHILD_WINDOW_SIZE=1920,789
-CHILD_WINDOW_POS=-8,-30
+CHILD_WINDOW_POS=-8,-31
 [GUI SETTING]
 Remember_Setting=1
 Open_PV_Opt=2
diff --git a/Logic/68030_TK.tcl b/Logic/68030_TK.tcl
index 55d4357..3c1f52d 100644
--- a/Logic/68030_TK.tcl
+++ b/Logic/68030_TK.tcl
@@ -344210,3 +344210,6974 @@ if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 6
 
 ########## Tcl recorder end at 10/10/15 21:59:34 ###########
 
+
+########## Tcl recorder starts at 01/23/16 13:53:30 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 13:53:30 ###########
+
+
+########## Tcl recorder starts at 01/23/16 13:53:31 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 13:53:31 ###########
+
+
+########## Tcl recorder starts at 01/23/16 13:59:12 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 13:59:12 ###########
+
+
+########## Tcl recorder starts at 01/23/16 13:59:12 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 13:59:12 ###########
+
+
+########## Tcl recorder starts at 01/23/16 13:59:51 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 13:59:51 ###########
+
+
+########## Tcl recorder starts at 01/23/16 13:59:51 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 13:59:51 ###########
+
+
+########## Tcl recorder starts at 01/23/16 14:00:34 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 14:00:34 ###########
+
+
+########## Tcl recorder starts at 01/23/16 14:00:34 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 14:00:34 ###########
+
+
+########## Tcl recorder starts at 01/23/16 14:01:12 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 14:01:12 ###########
+
+
+########## Tcl recorder starts at 01/23/16 14:01:12 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 14:01:12 ###########
+
+
+########## Tcl recorder starts at 01/23/16 14:02:50 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 14:02:50 ###########
+
+
+########## Tcl recorder starts at 01/23/16 14:02:50 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 14:02:50 ###########
+
+
+########## Tcl recorder starts at 01/23/16 14:04:13 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 14:04:13 ###########
+
+
+########## Tcl recorder starts at 01/23/16 14:04:13 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 14:04:13 ###########
+
+
+########## Tcl recorder starts at 01/23/16 14:07:16 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 14:07:16 ###########
+
+
+########## Tcl recorder starts at 01/23/16 14:07:16 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 14:07:16 ###########
+
+
+########## Tcl recorder starts at 01/23/16 14:10:11 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 14:10:11 ###########
+
+
+########## Tcl recorder starts at 01/23/16 14:10:11 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 14:10:11 ###########
+
+
+########## Tcl recorder starts at 01/23/16 14:14:43 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 14:14:43 ###########
+
+
+########## Tcl recorder starts at 01/23/16 14:14:43 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 14:14:43 ###########
+
+
+########## Tcl recorder starts at 01/23/16 16:44:03 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 16:44:03 ###########
+
+
+########## Tcl recorder starts at 01/23/16 16:44:04 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 16:44:04 ###########
+
+
+########## Tcl recorder starts at 01/23/16 16:45:44 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 16:45:44 ###########
+
+
+########## Tcl recorder starts at 01/23/16 16:45:44 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 16:45:44 ###########
+
+
+########## Tcl recorder starts at 01/23/16 17:53:48 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 17:53:48 ###########
+
+
+########## Tcl recorder starts at 01/23/16 17:53:48 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 17:53:48 ###########
+
+
+########## Tcl recorder starts at 01/23/16 18:00:19 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 18:00:19 ###########
+
+
+########## Tcl recorder starts at 01/23/16 18:00:19 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 18:00:19 ###########
+
+
+########## Tcl recorder starts at 01/23/16 18:42:33 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 18:42:33 ###########
+
+
+########## Tcl recorder starts at 01/23/16 18:42:33 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 18:42:33 ###########
+
+
+########## Tcl recorder starts at 01/23/16 18:46:07 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 18:46:07 ###########
+
+
+########## Tcl recorder starts at 01/23/16 18:46:07 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 18:46:07 ###########
+
+
+########## Tcl recorder starts at 01/23/16 18:51:19 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 18:51:19 ###########
+
+
+########## Tcl recorder starts at 01/23/16 18:51:19 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/23/16 18:51:19 ###########
+
+
+########## Tcl recorder starts at 01/24/16 09:01:17 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 09:01:17 ###########
+
+
+########## Tcl recorder starts at 01/24/16 09:01:18 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 09:01:18 ###########
+
+
+########## Tcl recorder starts at 01/24/16 09:56:08 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 09:56:08 ###########
+
+
+########## Tcl recorder starts at 01/24/16 09:56:08 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 09:56:08 ###########
+
+
+########## Tcl recorder starts at 01/24/16 09:57:10 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 09:57:10 ###########
+
+
+########## Tcl recorder starts at 01/24/16 09:57:11 ##########
+
+# Commands to make the Process: 
+# Post-Fit Pinouts
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+# Application to view the Process: 
+# Post-Fit Pinouts
+if [catch {open lattice_cmd.rs2 w} rspFile] {
+	puts stderr "Cannot create response file lattice_cmd.rs2: $rspFile"
+} else {
+	puts $rspFile "-src 68030_tk.tt4 -type PLA -devfile \"$install_dir/ispcpld/dat/mach4a/mach447ace.dev\" -postfit -lci 68030_tk.lco
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/lciedit\" @lattice_cmd.rs2"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 09:57:11 ###########
+
+
+########## Tcl recorder starts at 01/24/16 09:59:07 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 09:59:07 ###########
+
+
+########## Tcl recorder starts at 01/24/16 09:59:08 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 09:59:08 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:00:12 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:00:12 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:00:13 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:00:13 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:08:28 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:08:28 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:08:28 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:08:28 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:08:46 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:08:46 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:08:46 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:08:46 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:10:20 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:10:20 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:10:20 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:10:20 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:11:05 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:11:05 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:11:05 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:11:05 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:12:33 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:12:33 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:12:33 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:12:33 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:13:37 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:13:37 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:13:38 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:13:38 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:15:09 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:15:09 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:15:09 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:15:09 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:16:18 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:16:18 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:16:18 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:16:18 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:17:36 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:17:36 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:17:37 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:17:37 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:18:43 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:18:43 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:18:43 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:18:43 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:19:22 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:19:22 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:19:23 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:19:23 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:21:40 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:21:40 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:21:40 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:21:40 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:22:49 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:22:49 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:22:49 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:22:49 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:41:53 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:41:53 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:41:53 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:41:53 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:44:02 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:44:02 ###########
+
+
+########## Tcl recorder starts at 01/24/16 10:44:02 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 10:44:02 ###########
+
+
+########## Tcl recorder starts at 01/24/16 16:20:39 ##########
+
+# Commands to make the Process: 
+# Hierarchy
+if [runCmd "\"$cpld_bin/vhd2jhd\" 68030-68000-bus.vhd -o 68030-68000-bus.jhd -m \"$install_dir/ispcpld/generic/lib/vhd/location.map\" -p \"$install_dir/ispcpld/generic/lib\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 16:20:39 ###########
+
+
+########## Tcl recorder starts at 01/24/16 16:20:40 ##########
+
+# Commands to make the Process: 
+# JEDEC File
+if [catch {open BUS68030.cmd w} rspFile] {
+	puts stderr "Cannot create response file BUS68030.cmd: $rspFile"
+} else {
+	puts $rspFile "STYFILENAME: 68030_tk.sty
+PROJECT: BUS68030
+WORKING_PATH: \"$proj_dir\"
+MODULE: BUS68030
+VHDL_FILE_LIST: 68030-68000-bus.vhd
+OUTPUT_FILE_NAME: BUS68030
+SUFFIX_NAME: edi
+PART: M4A5-128/64-10VC
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/Synpwrap\" -e BUS68030 -target mach -pro "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete BUS68030.cmd
+if [runCmd "\"$cpld_bin/edif2blf\" -edf BUS68030.edi -out BUS68030.bl0 -err automake.err -log BUS68030.log -prj 68030_tk -lib \"$install_dir/ispcpld/dat/mach.edn\" -net_Vcc VCC -net_GND GND -nbx -dse -tlw -cvt YES -xor"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" BUS68030.bl0 -collapse none -reduce none -keepwires  -err automake.err -family"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblflink\" \"BUS68030.bl1\" -o \"68030_tk.bl2\" -omod \"68030_tk\"  -err \"automake.err\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/impsrc\"  -prj 68030_tk -lci 68030_tk.lct -log 68030_tk.imp -err automake.err -tti 68030_tk.bl2 -dir $proj_dir"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -blifopt  68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mblifopt\" 68030_tk.bl2 -sweep -mergefb -err automake.err -o 68030_tk.bl3  @68030_tk.b2_"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -diofft  68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/mdiofft\" 68030_tk.bl3 -pla -family AMDMACH -idev van -o 68030_tk.tt2 -oxrf 68030_tk.xrf -err automake.err  @68030_tk.d0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/tt2tott3\" -prj 68030_tk -dir $proj_dir -log 68030_tk.log -tti 68030_tk.tt2 -tto 68030_tk.tt3"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/abelvci\" -vci 68030_tk.lct -dev mach4a -prefit  68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/prefit\" -inp 68030_tk.tt3 -out 68030_tk.tt4 -err automake.err -log 68030_tk.log -percent 68030_tk.tte -mod BUS68030  @68030_tk.l0"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/blif2eqn\" 68030_tk.tte -o 68030_tk.eq3 -use_short -err automake.err "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/lci2vci\" -lci 68030_tk.lct -out 68030_tk.vct -log 68030_tk.l2v"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [catch {open 68030_tk.rsp w} rspFile] {
+	puts stderr "Cannot create response file 68030_tk.rsp: $rspFile"
+} else {
+	puts $rspFile "-inp \"68030_tk.tt4\" -vci \"68030_tk.vct\" -log \"68030_tk.log\" -eqn \"68030_tk.eq3\" -dev mach447a -dat \"$install_dir/ispcpld/dat/mach4a/\" -msg \"$install_dir/ispcpld/dat/\" -err automake.err -tmv \"NoInput.tmv\" 
+"
+	close $rspFile
+}
+if [runCmd "\"$cpld_bin/machfitr\" \"@68030_tk.rsp\""] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+file delete 68030_tk.rsp
+if [runCmd "\"$cpld_bin/lci2vci\" -vci 68030_tk.vco -out 68030_tk.lco -log 68030_tk.v2l"] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+if [runCmd "\"$cpld_bin/synsvf\" -exe \"$install_dir/ispvmsystem/ispufw\" -prj 68030_tk -if 68030_tk.jed -j2s -log 68030_tk.svl "] {
+	return
+} else {
+	vwait done
+	if [checkResult $done] {
+		return
+	}
+}
+
+########## Tcl recorder end at 01/24/16 16:20:40 ###########
+
diff --git a/Logic/68030_tk - DMA-Working@50MHz-060.jed b/Logic/68030_tk - DMA-Working@50MHz-060.jed
deleted file mode 100644
index 6a35f64..0000000
--- a/Logic/68030_tk - DMA-Working@50MHz-060.jed	
+++ /dev/null
@@ -1,1112 +0,0 @@
-|--------------------------------------------|
-|- ispLEVER Fitter Report File              -|
-|- Version 1.8.00.04.29.14                       -|
-|- (c)Copyright, Lattice Semiconductor 2002 -|
-|--------------------------------------------|
-
-
-TITLE:     
-AUTHOR:    
-PATTERN:   
-COMPANY:   
-REVISION:  
-DATE:     Mon Mar 23 21:55:17 2015
-
-ABEL mach447a
- *
-QP100*
-QF54096*
-G0*F0*
-NOTE  Part Number : M4A5-128/64-10VC *
-NOTE  Handling of Preplacements  No Change *
-NOTE  Use placement data from  68030_tk.vct *
-NOTE  Global clocks routable as PT clocks?  N *
-NOTE  22V10/MACH1XX/2XX S/R Compatibility?  Y *
-NOTE  SET/RESET treated as DONT_CARE?  N *
-NOTE  Reduce Unforced Global Clocks?  N *
-NOTE  Iterate between partitioning and place/route?  Y *
-NOTE  Balanced partitioning?  Y *
-NOTE  Reduce Routes Per Placement?  N *
-NOTE  Spread Placement?  Y *
-NOTE  Run Time Upper Bound in 15 minutes  0 *
-NOTE  Zero Hold Time For Input Registers?  Y *
-NOTE Table of pin names and numbers*
-NOTE PINS A_17_:59 A_16_:96 SIZE_1_:79 A_31_:4 IPL_2_:68*
-NOTE PINS FC_1_:58 AS_030:82 AS_000:42 DS_030:98 UDS_000:32*
-NOTE PINS LDS_000:31 A1:60 IPL_1_:56 nEXP_SPACE:14 IPL_0_:67*
-NOTE PINS BERR:41 FC_0_:57 BG_030:21 BGACK_000:28 CLK_030:64*
-NOTE PINS CLK_000:11 CLK_OSZI:61 CLK_DIV_OUT:65 CLK_EXP:10*
-NOTE PINS FPU_CS:78 FPU_SENSE:91 DTACK:30 AVEC:92 VPA:36*
-NOTE PINS RST:86 AMIGA_ADDR_ENABLE:33 AMIGA_BUS_DATA_DIR:48*
-NOTE PINS AMIGA_BUS_ENABLE_LOW:20 AMIGA_BUS_ENABLE_HIGH:34*
-NOTE PINS CIIN:47 SIZE_0_:70 A_30_:5 A_29_:6 A_28_:15 A_27_:16*
-NOTE PINS A_26_:17 A_25_:18 A_24_:19 A_23_:85 A_22_:84 A_21_:94*
-NOTE PINS A_20_:93 A_19_:97 A_18_:95 IPL_030_2_:9 RW_000:80*
-NOTE PINS IPL_030_1_:7 A0:69 IPL_030_0_:8 BG_000:29 BGACK_030:83*
-NOTE PINS DSACK1:81 E:66 VMA:35 RESET:3 RW:71 *
-NOTE Table of node names and numbers*
-NOTE NODES RN_SIZE_1_:287 RN_AS_030:281 RN_AS_000:203 RN_DS_030:101 *
-NOTE NODES RN_UDS_000:185 RN_LDS_000:191 RN_BERR:197 RN_SIZE_0_:263 *
-NOTE NODES RN_IPL_030_2_:131 RN_RW_000:269 RN_IPL_030_1_:143 *
-NOTE NODES RN_A0:257 RN_IPL_030_0_:137 RN_BG_000:175 RN_BGACK_030:275 *
-NOTE NODES RN_DSACK1:283 RN_E:251 RN_VMA:173 RN_RESET:127 *
-NOTE NODES RN_RW:245 cpu_est_0_:193 cpu_est_1_:187 inst_AS_000_INT:139 *
-NOTE NODES SM_AMIGA_5_:227 inst_AMIGA_BUS_ENABLE_DMA_LOW:248 *
-NOTE NODES inst_AS_030_D0:277 inst_nEXP_SPACE_D0reg:155 *
-NOTE NODES inst_DS_030_D0:194 inst_AS_030_000_SYNC:241 inst_BGACK_030_INT_D:289 *
-NOTE NODES inst_AS_000_DMA:113 inst_DS_000_DMA:109 CYCLE_DMA_0_:104 *
-NOTE NODES CYCLE_DMA_1_:121 SIZE_DMA_0_:259 SIZE_DMA_1_:253 *
-NOTE NODES inst_VPA_D:163 inst_UDS_000_INT:103 inst_LDS_000_INT:119 *
-NOTE NODES inst_CLK_OUT_PRE_D:217 inst_DTACK_D0:130 inst_CLK_OUT_PRE_50:211 *
-NOTE NODES inst_CLK_000_D1:205 inst_CLK_000_D0:182 inst_CLK_000_PE:161 *
-NOTE NODES CLK_000_P_SYNC_9_:122 inst_CLK_000_NE:239 CLK_000_N_SYNC_11_:278 *
-NOTE NODES cpu_est_2_:151 SM_AMIGA_3_:167 inst_CLK_000_NE_D0:176 *
-NOTE NODES SM_AMIGA_0_:233 inst_AMIGA_BUS_ENABLE_DMA_HIGH:265 *
-NOTE NODES SM_AMIGA_6_:235 CLK_000_P_SYNC_0_:230 CLK_000_P_SYNC_1_:154 *
-NOTE NODES CLK_000_P_SYNC_2_:250 CLK_000_P_SYNC_3_:266 CLK_000_P_SYNC_4_:170 *
-NOTE NODES CLK_000_P_SYNC_5_:260 CLK_000_P_SYNC_6_:146 CLK_000_P_SYNC_7_:140 *
-NOTE NODES CLK_000_P_SYNC_8_:134 CLK_000_N_SYNC_0_:224 CLK_000_N_SYNC_1_:188 *
-NOTE NODES CLK_000_N_SYNC_2_:254 CLK_000_N_SYNC_3_:116 CLK_000_N_SYNC_4_:164 *
-NOTE NODES CLK_000_N_SYNC_5_:128 CLK_000_N_SYNC_6_:158 CLK_000_N_SYNC_7_:145 *
-NOTE NODES CLK_000_N_SYNC_8_:110 CLK_000_N_SYNC_9_:152 CLK_000_N_SYNC_10_:272 *
-NOTE NODES inst_CLK_030_H:115 SM_AMIGA_1_:229 SM_AMIGA_4_:223 *
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diff --git a/Logic/68030_tk.b2_ b/Logic/68030_tk.b2_
new file mode 100644
index 0000000..4ef6a67
--- /dev/null
+++ b/Logic/68030_tk.b2_
@@ -0,0 +1 @@
+ -collapse all -pterms 16 -nmax 32 -clust 5 -reduce bypin choose -xorsyn -dev M4A5_clk
diff --git a/Logic/68030_tk.bl2 b/Logic/68030_tk.bl2
new file mode 100644
index 0000000..6922127
--- /dev/null
+++ b/Logic/68030_tk.bl2
@@ -0,0 +1,2325 @@
+#$ TOOL ispLEVER Classic 1.8.00.04.29.14
+#$ DATE Sun Jan 24 16:20:54 2016
+#$ MODULE 68030_tk
+#$ PINS 75 A_9_ A_8_ SIZE_1_ A_7_ A_6_ A_31_ A_5_ A_4_ IPL_030_2_ A_3_ A_2_ IPL_2_ \
+#  IPL_030_1_ IPL_030_0_ FC_1_ IPL_1_ AS_030 IPL_0_ AS_000 FC_0_ RW_000 DS_030 UDS_000 \
+#  LDS_000 A0 A1 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI \
+#  CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW \
+#  AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR SIZE_0_ AMIGA_BUS_ENABLE_LOW A_30_ \
+#  AMIGA_BUS_ENABLE_HIGH A_29_ CIIN A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ \
+#  A_19_ A_18_ A_17_ A_16_ A_15_ A_14_ A_13_ A_12_ A_11_ A_10_
+#$ NODES 681 N_184 N_184_0 rw_000_dma_0_un1_n N_180 N_185_0 rw_000_dma_0_un0_n N_179 \
+#  UDS_000_c_i a0_dma_0_un3_n pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2 LDS_000_c_i \
+#  a0_dma_0_un1_n N_312 N_173_i a0_dma_0_un0_n N_270 N_358_0 \
+#  amiga_bus_enable_dma_low_0_un3_n inst_BGACK_030_INTreg N_357 N_239_i \
+#  amiga_bus_enable_dma_low_0_un1_n inst_CLK_OUT_INTreg N_354 \
+#  pos_clk_size_dma_6_0_1__n amiga_bus_enable_dma_low_0_un0_n vcc_n_n N_227 N_238_i \
+#  amiga_bus_enable_dma_high_0_un3_n un5_e N_378 pos_clk_size_dma_6_0_0__n \
+#  amiga_bus_enable_dma_high_0_un1_n inst_VMA_INTreg N_29 N_237_i \
+#  amiga_bus_enable_dma_high_0_un0_n gnd_n_n N_28 N_236_i cpu_est_0_2__un3_n \
+#  un1_amiga_bus_enable_low N_3 AMIGA_BUS_DATA_DIR_c_0 cpu_est_0_2__un1_n un3_size N_5 \
+#  N_331_i cpu_est_0_2__un0_n un4_size N_7 pos_clk_un6_bgack_000_0_n \
+#  cpu_est_0_3__un3_n un4_uds_000 N_190_i N_356_0 cpu_est_0_3__un1_n un4_lds_000 \
+#  un1_amiga_bus_enable_low_i N_352_0 cpu_est_0_3__un0_n un5_ciin un21_fpu_cs_i N_8_i \
+#  ipl_030_0_0__un3_n un4_as_000 CLK_OUT_EXP_INT_i N_46_0 ipl_030_0_0__un1_n \
+#  un1_SM_AMIGA_5 AS_000_i N_10_i ipl_030_0_0__un0_n un21_fpu_cs DS_000_DMA_i N_44_0 \
+#  rw_000_int_0_un3_n un22_berr sm_amiga_i_5__n N_19_i rw_000_int_0_un1_n un6_ds_030 \
+#  sm_amiga_i_6__n N_41_0 rw_000_int_0_un0_n cpu_est_0_ sm_amiga_i_0__n N_20_i \
+#  uds_000_int_0_un3_n cpu_est_1_ CLK_000_NE_i N_40_0 uds_000_int_0_un1_n cpu_est_2_ \
+#  sm_amiga_i_4__n N_24_i uds_000_int_0_un0_n cpu_est_3_ RW_000_i N_36_0 \
+#  vma_int_0_un3_n inst_AS_000_INT sm_amiga_i_2__n N_25_i vma_int_0_un1_n SM_AMIGA_5_ \
+#  CLK_000_D0_i N_35_0 vma_int_0_un0_n inst_AMIGA_BUS_ENABLE_DMA_LOW BERR_i \
+#  bg_000_0_un3_n inst_AS_030_D0 sm_amiga_i_1__n N_198_i bg_000_0_un1_n \
+#  inst_nEXP_SPACE_D0reg CLK_000_PE_i N_243_2_i bg_000_0_un0_n inst_AS_030_000_SYNC \
+#  N_410_i_0 N_196_i cpu_est_0_1__un3_n inst_BGACK_030_INT_D sm_amiga_i_i_7__n N_195_i \
+#  cpu_est_0_1__un1_n inst_AS_000_DMA AS_030_i cpu_est_0_1__un0_n inst_DS_000_DMA \
+#  FPU_SENSE_i N_201_i dsack1_int_0_un3_n CYCLE_DMA_0_ nEXP_SPACE_D0_i N_200_i \
+#  dsack1_int_0_un1_n CYCLE_DMA_1_ BGACK_030_INT_i N_199_i dsack1_int_0_un0_n \
+#  SIZE_DMA_0_ AMIGA_BUS_ENABLE_DMA_HIGH_i N_182_0 ds_000_enable_0_un3_n SIZE_DMA_1_ \
+#  A1_i N_158_i ds_000_enable_0_un1_n inst_VPA_D CLK_030_H_i N_148_i \
+#  ds_000_enable_0_un0_n inst_UDS_000_INT a_i_16__n N_307_i lds_000_int_0_un3_n \
+#  inst_LDS_000_INT a_i_18__n N_143_0 lds_000_int_0_un1_n inst_CLK_OUT_PRE_D a_i_19__n \
+#  N_217_i lds_000_int_0_un0_n inst_DTACK_D0 N_114_i N_235_i a_15__n inst_RESET_OUT \
+#  N_113_i inst_CLK_OUT_PRE_50 AS_000_INT_i N_210_i a_14__n inst_CLK_OUT_PRE_25 \
+#  AMIGA_BUS_ENABLE_DMA_LOW_i inst_CLK_000_D1 rst_dly_i_2__n N_207_i a_13__n \
+#  inst_CLK_000_D0 rst_dly_i_0__n N_208_i inst_CLK_000_PE rst_dly_i_1__n N_206_i \
+#  a_12__n inst_CLK_OUT_EXP_INT RESET_OUT_i CLK_000_P_SYNC_9_ size_dma_i_1__n N_313_i \
+#  a_11__n inst_CLK_000_NE size_dma_i_0__n N_211_i CLK_000_N_SYNC_11_ AS_030_D0_i \
+#  N_212_i a_10__n IPL_D0_0_ a_i_24__n N_183_0 IPL_D0_1_ sm_amiga_i_3__n N_181_0 a_9__n \
+#  IPL_D0_2_ cpu_est_i_3__n N_178_0 inst_CLK_000_NE_D0 cpu_est_i_0__n N_69_0 a_8__n \
+#  SM_AMIGA_0_ VPA_D_i N_329_i inst_AMIGA_BUS_ENABLE_DMA_HIGH cpu_est_i_1__n N_176_i \
+#  a_7__n inst_DSACK1_INTreg CLK_030_i N_175_0 pos_clk_ipl_n CLK_000_D1_i N_174_0 a_6__n \
+#  SM_AMIGA_4_ cpu_est_i_2__n N_171_0 inst_DS_000_ENABLE DTACK_D0_i un1_SM_AMIGA_5_i \
+#  a_5__n RST_DLY_0_ RW_i N_324_i RST_DLY_1_ a_i_31__n N_326_i a_4__n RST_DLY_2_ a_i_29__n \
+#  N_168_i pos_clk_un8_bg_030_n a_i_30__n VMA_INT_i a_3__n CLK_000_P_SYNC_0_ a_i_27__n \
+#  N_165_i CLK_000_P_SYNC_1_ a_i_28__n N_164_i a_2__n CLK_000_P_SYNC_2_ a_i_25__n \
+#  N_162_i CLK_000_P_SYNC_3_ a_i_26__n clk_000_n_sync_i_10__n CLK_000_P_SYNC_4_ \
+#  N_213_i N_321_i CLK_000_P_SYNC_5_ N_214_i N_159_0 CLK_000_P_SYNC_6_ N_215_i N_318_i \
+#  CLK_000_P_SYNC_7_ N_156_i CLK_000_P_SYNC_8_ DS_000_ENABLE_1_sqmuxa_i N_155_i \
+#  CLK_000_N_SYNC_0_ N_98_i N_154_i CLK_000_N_SYNC_1_ un6_ds_030_i CLK_OUT_PRE_D_i \
+#  CLK_000_N_SYNC_2_ un4_as_000_i N_152_0 CLK_000_N_SYNC_3_ un4_lds_000_i N_150_i \
+#  CLK_000_N_SYNC_4_ un4_uds_000_i AS_030_000_SYNC_i CLK_000_N_SYNC_5_ LDS_000_INT_i \
+#  N_147_i CLK_000_N_SYNC_6_ UDS_000_INT_i N_145_i CLK_000_N_SYNC_7_ AS_030_c N_281_i \
+#  CLK_000_N_SYNC_8_ N_302_i CLK_000_N_SYNC_9_ AS_000_c CLK_000_N_SYNC_10_ N_279_i \
+#  inst_RW_000_INT RW_000_c N_280_i inst_RW_000_DMA un5_e_0 pos_clk_un7_clk_000_pe_n \
+#  N_278_i inst_A0_DMA UDS_000_c cpu_est_2_0_3__n SM_AMIGA_6_ N_277_i \
+#  DS_000_ENABLE_1_sqmuxa LDS_000_c N_348_i inst_CLK_030_H cpu_est_2_0_2__n \
+#  SM_AMIGA_1_ size_c_0__n N_128_i SM_AMIGA_3_ N_193_i SM_AMIGA_2_ size_c_1__n N_241_i \
+#  pos_clk_un3_as_030_d0_n DS_000_ENABLE_1_sqmuxa_1 N_240_i N_4 N_124_0 N_6 N_269_0 \
+#  un5_ciin_i N_61_0 un1_as_030_i N_17 N_228_i N_18 N_355_0 N_21 N_226_i N_22 N_26 N_224_i \
+#  N_27 N_225_i CLK_OUT_PRE_25_0 N_282_0 N_221_i N_222_i N_219_i N_220_i N_283_0 N_216_i \
+#  N_218_i cpu_est_2_0_1__n N_373_i N_375_i pos_clk_un7_clk_000_pe_0_n N_188_i \
+#  a_c_16__n N_205_i a_c_17__n pos_clk_un8_sm_amiga_i_n A0_c_i a_c_18__n size_c_i_1__n \
+#  N_27_i a_c_19__n N_31_0 ipl_c_i_0__n a_c_20__n N_52_0 N_4_i a_c_21__n N_49_0 N_17_i \
+#  SM_AMIGA_i_7_ a_c_22__n N_43_0 N_124 N_18_i cpu_est_2_1__n a_c_23__n N_42_0 \
+#  cpu_est_2_2__n N_21_i cpu_est_2_3__n a_c_24__n N_39_0 G_134 N_22_i G_135 a_c_25__n \
+#  N_38_0 G_136 N_26_i N_269 a_c_26__n N_34_0 N_61 BG_030_c_i a_c_27__n \
+#  pos_clk_un8_bg_030_0_n N_98 N_161_i_1 a_c_28__n N_161_i_2 \
+#  pos_clk_un8_sm_amiga_i_1_n N_355 a_c_29__n N_324_1 N_324_2 N_128 a_c_30__n N_150_i_1 \
+#  N_137 un1_SM_AMIGA_5_i_1 N_145 a_c_31__n un1_SM_AMIGA_5_i_2 N_148 N_138_i_1 N_150 A0_c \
+#  N_138_i_2 N_152 N_146_i_1 N_154 A1_c N_146_i_2 N_156 N_146_i_3 N_159 nEXP_SPACE_c \
+#  N_220_1 N_161 N_220_2 N_165 BERR_c N_375_1 N_168 N_375_2 N_171 BG_030_c N_373_1 N_174 \
+#  N_373_2 N_175 BG_000DFFreg N_210_1 N_178 N_210_2 N_181 N_210_3 N_183 BGACK_000_c \
+#  un5_ciin_1 N_188 un5_ciin_2 N_190 CLK_030_c un5_ciin_3 N_193 un5_ciin_4 N_195 \
+#  un5_ciin_5 N_200 un5_ciin_6 N_205 CLK_OSZI_c un5_ciin_7 N_206 un5_ciin_8 N_207 \
+#  un5_ciin_9 N_208 un5_ciin_10 N_210 un5_ciin_11 N_211 FPU_SENSE_c N_302_1 N_212 \
+#  N_244_i_1 N_373 IPL_030DFF_0_reg N_244_i_2 N_375 N_243_i_1 N_216 IPL_030DFF_1_reg \
+#  N_410_1 N_218 N_410_2 N_219 IPL_030DFF_2_reg N_410_3 N_220 N_410_4 N_221 ipl_c_0__n \
+#  N_237_1 N_222 N_237_2 N_224 ipl_c_1__n un21_fpu_cs_1 N_225 un22_berr_1_0 N_226 \
+#  ipl_c_2__n N_233_1 N_228 N_233_2 N_230 N_245_i_1 N_231 DTACK_c N_128_i_1 N_240 N_134_i_1 \
+#  N_241 N_124_0_1 N_277 N_267_i_1 N_278 VPA_c N_268_i_1 N_279 N_355_0_1 N_280 N_353_i_1 \
+#  N_281 RST_c N_140_i_1 N_302 N_142_i_1 N_313 N_280_1 N_318 RW_c N_225_1 N_321 N_224_1 N_324 \
+#  fc_c_0__n N_219_1 N_326 N_218_1 N_329 fc_c_1__n N_212_1 N_332 N_208_1 N_348 N_207_1 \
+#  cpu_est_0_0_x2_0_x2_0_ AMIGA_BUS_DATA_DIR_c N_200_1 pos_clk_CYCLE_DMA_5_0_i_0_x2 \
+#  N_195_1 pos_clk_CYCLE_DMA_5_1_i_0_x2 pos_clk_ipl_1_n N_235 ipl_030_0_1__un3_n N_196 \
+#  ipl_030_0_1__un1_n N_143 N_7_i ipl_030_0_1__un0_n N_158 N_47_0 \
+#  as_030_000_sync_0_un3_n N_198 N_5_i as_030_000_sync_0_un1_n N_199 N_48_0 \
+#  as_030_000_sync_0_un0_n N_307 N_3_i as_000_int_0_un3_n N_201 N_50_0 \
+#  as_000_int_0_un1_n N_182 nEXP_SPACE_c_i as_000_int_0_un0_n N_243_2 N_55_0 \
+#  ds_000_dma_0_un3_n N_8 VPA_c_i ds_000_dma_0_un1_n N_356 N_56_0 ds_000_dma_0_un0_n \
+#  N_10 DTACK_c_i ipl_030_0_2__un3_n pos_clk_un6_bgack_000_n N_57_0 ipl_030_0_2__un1_n \
+#  N_19 ipl_c_i_1__n ipl_030_0_2__un0_n N_352 N_53_0 \
+#  un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n N_327 ipl_c_i_2__n \
+#  un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n N_20 N_54_0 \
+#  un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n pos_clk_a0_dma_3_n N_28_i \
+#  sm_amiga_srsts_i_0_0_m3_1__un3_n N_24 N_32_0 sm_amiga_srsts_i_0_0_m3_1__un1_n \
+#  N_113 N_29_i sm_amiga_srsts_i_0_0_m3_1__un0_n N_25 N_33_0 \
+#  sm_amiga_srsts_i_0_0_m3_5__un3_n N_114 N_378_i sm_amiga_srsts_i_0_0_m3_5__un1_n \
+#  pos_clk_size_dma_6_0__n sm_amiga_srsts_i_0_0_m3_5__un0_n N_232 \
+#  size_dma_0_0__un3_n pos_clk_size_dma_6_1__n N_227_i size_dma_0_0__un1_n N_410 \
+#  N_354_0 size_dma_0_0__un0_n N_185 N_233_i size_dma_0_1__un3_n N_236 N_357_0 \
+#  size_dma_0_1__un1_n N_238 N_270_0 size_dma_0_1__un0_n N_173 AS_000_DMA_i \
+#  as_000_dma_0_un3_n N_239 N_137_0 as_000_dma_0_un1_n N_331 N_312_i as_000_dma_0_un0_n \
+#  N_237 pos_clk_un3_as_030_d0_i_n bgack_030_int_0_un3_n un22_berr_1 N_161_i \
+#  bgack_030_int_0_un1_n N_233 N_179_0 bgack_030_int_0_un0_n N_209 N_180_0 \
+#  rw_000_dma_0_un3_n
+.model bus68030
+.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
+BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \
+DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \
+A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
+A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF \
+A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF \
+A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \
+SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF \
+A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_184.BLIF N_184_0.BLIF \
+rw_000_dma_0_un1_n.BLIF N_180.BLIF N_185_0.BLIF rw_000_dma_0_un0_n.BLIF \
+N_179.BLIF UDS_000_c_i.BLIF a0_dma_0_un3_n.BLIF \
+pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2.BLIF LDS_000_c_i.BLIF \
+a0_dma_0_un1_n.BLIF N_312.BLIF N_173_i.BLIF a0_dma_0_un0_n.BLIF N_270.BLIF \
+N_358_0.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF inst_BGACK_030_INTreg.BLIF \
+N_357.BLIF N_239_i.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF \
+inst_CLK_OUT_INTreg.BLIF N_354.BLIF pos_clk_size_dma_6_0_1__n.BLIF \
+amiga_bus_enable_dma_low_0_un0_n.BLIF vcc_n_n.BLIF N_227.BLIF N_238_i.BLIF \
+amiga_bus_enable_dma_high_0_un3_n.BLIF un5_e.BLIF N_378.BLIF \
+pos_clk_size_dma_6_0_0__n.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF \
+inst_VMA_INTreg.BLIF N_29.BLIF N_237_i.BLIF \
+amiga_bus_enable_dma_high_0_un0_n.BLIF gnd_n_n.BLIF N_28.BLIF N_236_i.BLIF \
+cpu_est_0_2__un3_n.BLIF un1_amiga_bus_enable_low.BLIF N_3.BLIF \
+AMIGA_BUS_DATA_DIR_c_0.BLIF cpu_est_0_2__un1_n.BLIF un3_size.BLIF N_5.BLIF \
+N_331_i.BLIF cpu_est_0_2__un0_n.BLIF un4_size.BLIF N_7.BLIF \
+pos_clk_un6_bgack_000_0_n.BLIF cpu_est_0_3__un3_n.BLIF un4_uds_000.BLIF \
+N_190_i.BLIF N_356_0.BLIF cpu_est_0_3__un1_n.BLIF un4_lds_000.BLIF \
+un1_amiga_bus_enable_low_i.BLIF N_352_0.BLIF cpu_est_0_3__un0_n.BLIF \
+un5_ciin.BLIF un21_fpu_cs_i.BLIF N_8_i.BLIF ipl_030_0_0__un3_n.BLIF \
+un4_as_000.BLIF CLK_OUT_EXP_INT_i.BLIF N_46_0.BLIF ipl_030_0_0__un1_n.BLIF \
+un1_SM_AMIGA_5.BLIF AS_000_i.BLIF N_10_i.BLIF ipl_030_0_0__un0_n.BLIF \
+un21_fpu_cs.BLIF DS_000_DMA_i.BLIF N_44_0.BLIF rw_000_int_0_un3_n.BLIF \
+un22_berr.BLIF sm_amiga_i_5__n.BLIF N_19_i.BLIF rw_000_int_0_un1_n.BLIF \
+un6_ds_030.BLIF sm_amiga_i_6__n.BLIF N_41_0.BLIF rw_000_int_0_un0_n.BLIF \
+cpu_est_0_.BLIF sm_amiga_i_0__n.BLIF N_20_i.BLIF uds_000_int_0_un3_n.BLIF \
+cpu_est_1_.BLIF CLK_000_NE_i.BLIF N_40_0.BLIF uds_000_int_0_un1_n.BLIF \
+cpu_est_2_.BLIF sm_amiga_i_4__n.BLIF N_24_i.BLIF uds_000_int_0_un0_n.BLIF \
+cpu_est_3_.BLIF RW_000_i.BLIF N_36_0.BLIF vma_int_0_un3_n.BLIF \
+inst_AS_000_INT.BLIF sm_amiga_i_2__n.BLIF N_25_i.BLIF vma_int_0_un1_n.BLIF \
+SM_AMIGA_5_.BLIF CLK_000_D0_i.BLIF N_35_0.BLIF vma_int_0_un0_n.BLIF \
+inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF BERR_i.BLIF bg_000_0_un3_n.BLIF \
+inst_AS_030_D0.BLIF sm_amiga_i_1__n.BLIF N_198_i.BLIF bg_000_0_un1_n.BLIF \
+inst_nEXP_SPACE_D0reg.BLIF CLK_000_PE_i.BLIF N_243_2_i.BLIF \
+bg_000_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF N_410_i_0.BLIF N_196_i.BLIF \
+cpu_est_0_1__un3_n.BLIF inst_BGACK_030_INT_D.BLIF sm_amiga_i_i_7__n.BLIF \
+N_195_i.BLIF cpu_est_0_1__un1_n.BLIF inst_AS_000_DMA.BLIF AS_030_i.BLIF \
+cpu_est_0_1__un0_n.BLIF inst_DS_000_DMA.BLIF FPU_SENSE_i.BLIF N_201_i.BLIF \
+dsack1_int_0_un3_n.BLIF CYCLE_DMA_0_.BLIF nEXP_SPACE_D0_i.BLIF N_200_i.BLIF \
+dsack1_int_0_un1_n.BLIF CYCLE_DMA_1_.BLIF BGACK_030_INT_i.BLIF N_199_i.BLIF \
+dsack1_int_0_un0_n.BLIF SIZE_DMA_0_.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \
+N_182_0.BLIF ds_000_enable_0_un3_n.BLIF SIZE_DMA_1_.BLIF A1_i.BLIF \
+N_158_i.BLIF ds_000_enable_0_un1_n.BLIF inst_VPA_D.BLIF CLK_030_H_i.BLIF \
+N_148_i.BLIF ds_000_enable_0_un0_n.BLIF inst_UDS_000_INT.BLIF a_i_16__n.BLIF \
+N_307_i.BLIF lds_000_int_0_un3_n.BLIF inst_LDS_000_INT.BLIF a_i_18__n.BLIF \
+N_143_0.BLIF lds_000_int_0_un1_n.BLIF inst_CLK_OUT_PRE_D.BLIF a_i_19__n.BLIF \
+N_217_i.BLIF lds_000_int_0_un0_n.BLIF inst_DTACK_D0.BLIF N_114_i.BLIF \
+N_235_i.BLIF a_15__n.BLIF inst_RESET_OUT.BLIF N_113_i.BLIF \
+inst_CLK_OUT_PRE_50.BLIF AS_000_INT_i.BLIF N_210_i.BLIF a_14__n.BLIF \
+inst_CLK_OUT_PRE_25.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF inst_CLK_000_D1.BLIF \
+rst_dly_i_2__n.BLIF N_207_i.BLIF a_13__n.BLIF inst_CLK_000_D0.BLIF \
+rst_dly_i_0__n.BLIF N_208_i.BLIF inst_CLK_000_PE.BLIF rst_dly_i_1__n.BLIF \
+N_206_i.BLIF a_12__n.BLIF inst_CLK_OUT_EXP_INT.BLIF RESET_OUT_i.BLIF \
+CLK_000_P_SYNC_9_.BLIF size_dma_i_1__n.BLIF N_313_i.BLIF a_11__n.BLIF \
+inst_CLK_000_NE.BLIF size_dma_i_0__n.BLIF N_211_i.BLIF CLK_000_N_SYNC_11_.BLIF \
+AS_030_D0_i.BLIF N_212_i.BLIF a_10__n.BLIF IPL_D0_0_.BLIF a_i_24__n.BLIF \
+N_183_0.BLIF IPL_D0_1_.BLIF sm_amiga_i_3__n.BLIF N_181_0.BLIF a_9__n.BLIF \
+IPL_D0_2_.BLIF cpu_est_i_3__n.BLIF N_178_0.BLIF inst_CLK_000_NE_D0.BLIF \
+cpu_est_i_0__n.BLIF N_69_0.BLIF a_8__n.BLIF SM_AMIGA_0_.BLIF VPA_D_i.BLIF \
+N_329_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF cpu_est_i_1__n.BLIF \
+N_176_i.BLIF a_7__n.BLIF inst_DSACK1_INTreg.BLIF CLK_030_i.BLIF N_175_0.BLIF \
+pos_clk_ipl_n.BLIF CLK_000_D1_i.BLIF N_174_0.BLIF a_6__n.BLIF SM_AMIGA_4_.BLIF \
+cpu_est_i_2__n.BLIF N_171_0.BLIF inst_DS_000_ENABLE.BLIF DTACK_D0_i.BLIF \
+un1_SM_AMIGA_5_i.BLIF a_5__n.BLIF RST_DLY_0_.BLIF RW_i.BLIF N_324_i.BLIF \
+RST_DLY_1_.BLIF a_i_31__n.BLIF N_326_i.BLIF a_4__n.BLIF RST_DLY_2_.BLIF \
+a_i_29__n.BLIF N_168_i.BLIF pos_clk_un8_bg_030_n.BLIF a_i_30__n.BLIF \
+VMA_INT_i.BLIF a_3__n.BLIF CLK_000_P_SYNC_0_.BLIF a_i_27__n.BLIF N_165_i.BLIF \
+CLK_000_P_SYNC_1_.BLIF a_i_28__n.BLIF N_164_i.BLIF a_2__n.BLIF \
+CLK_000_P_SYNC_2_.BLIF a_i_25__n.BLIF N_162_i.BLIF CLK_000_P_SYNC_3_.BLIF \
+a_i_26__n.BLIF clk_000_n_sync_i_10__n.BLIF CLK_000_P_SYNC_4_.BLIF N_213_i.BLIF \
+N_321_i.BLIF CLK_000_P_SYNC_5_.BLIF N_214_i.BLIF N_159_0.BLIF \
+CLK_000_P_SYNC_6_.BLIF N_215_i.BLIF N_318_i.BLIF CLK_000_P_SYNC_7_.BLIF \
+N_156_i.BLIF CLK_000_P_SYNC_8_.BLIF DS_000_ENABLE_1_sqmuxa_i.BLIF N_155_i.BLIF \
+CLK_000_N_SYNC_0_.BLIF N_98_i.BLIF N_154_i.BLIF CLK_000_N_SYNC_1_.BLIF \
+un6_ds_030_i.BLIF CLK_OUT_PRE_D_i.BLIF CLK_000_N_SYNC_2_.BLIF \
+un4_as_000_i.BLIF N_152_0.BLIF CLK_000_N_SYNC_3_.BLIF un4_lds_000_i.BLIF \
+N_150_i.BLIF CLK_000_N_SYNC_4_.BLIF un4_uds_000_i.BLIF AS_030_000_SYNC_i.BLIF \
+CLK_000_N_SYNC_5_.BLIF LDS_000_INT_i.BLIF N_147_i.BLIF CLK_000_N_SYNC_6_.BLIF \
+UDS_000_INT_i.BLIF N_145_i.BLIF CLK_000_N_SYNC_7_.BLIF AS_030_c.BLIF \
+N_281_i.BLIF CLK_000_N_SYNC_8_.BLIF N_302_i.BLIF CLK_000_N_SYNC_9_.BLIF \
+AS_000_c.BLIF CLK_000_N_SYNC_10_.BLIF N_279_i.BLIF inst_RW_000_INT.BLIF \
+RW_000_c.BLIF N_280_i.BLIF inst_RW_000_DMA.BLIF un5_e_0.BLIF \
+pos_clk_un7_clk_000_pe_n.BLIF N_278_i.BLIF inst_A0_DMA.BLIF UDS_000_c.BLIF \
+cpu_est_2_0_3__n.BLIF SM_AMIGA_6_.BLIF N_277_i.BLIF \
+DS_000_ENABLE_1_sqmuxa.BLIF LDS_000_c.BLIF N_348_i.BLIF inst_CLK_030_H.BLIF \
+cpu_est_2_0_2__n.BLIF SM_AMIGA_1_.BLIF size_c_0__n.BLIF N_128_i.BLIF \
+SM_AMIGA_3_.BLIF N_193_i.BLIF SM_AMIGA_2_.BLIF size_c_1__n.BLIF N_241_i.BLIF \
+pos_clk_un3_as_030_d0_n.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF N_240_i.BLIF \
+N_4.BLIF N_124_0.BLIF N_6.BLIF N_269_0.BLIF un5_ciin_i.BLIF N_61_0.BLIF \
+un1_as_030_i.BLIF N_17.BLIF N_228_i.BLIF N_18.BLIF N_355_0.BLIF N_21.BLIF \
+N_226_i.BLIF N_22.BLIF N_26.BLIF N_224_i.BLIF N_27.BLIF N_225_i.BLIF \
+CLK_OUT_PRE_25_0.BLIF N_282_0.BLIF N_221_i.BLIF N_222_i.BLIF N_219_i.BLIF \
+N_220_i.BLIF N_283_0.BLIF N_216_i.BLIF N_218_i.BLIF cpu_est_2_0_1__n.BLIF \
+N_373_i.BLIF N_375_i.BLIF pos_clk_un7_clk_000_pe_0_n.BLIF N_188_i.BLIF \
+a_c_16__n.BLIF N_205_i.BLIF a_c_17__n.BLIF pos_clk_un8_sm_amiga_i_n.BLIF \
+A0_c_i.BLIF a_c_18__n.BLIF size_c_i_1__n.BLIF N_27_i.BLIF a_c_19__n.BLIF \
+N_31_0.BLIF ipl_c_i_0__n.BLIF a_c_20__n.BLIF N_52_0.BLIF N_4_i.BLIF \
+a_c_21__n.BLIF N_49_0.BLIF N_17_i.BLIF SM_AMIGA_i_7_.BLIF a_c_22__n.BLIF \
+N_43_0.BLIF N_124.BLIF N_18_i.BLIF cpu_est_2_1__n.BLIF a_c_23__n.BLIF \
+N_42_0.BLIF cpu_est_2_2__n.BLIF N_21_i.BLIF cpu_est_2_3__n.BLIF a_c_24__n.BLIF \
+N_39_0.BLIF G_134.BLIF N_22_i.BLIF G_135.BLIF a_c_25__n.BLIF N_38_0.BLIF \
+G_136.BLIF N_26_i.BLIF N_269.BLIF a_c_26__n.BLIF N_34_0.BLIF N_61.BLIF \
+BG_030_c_i.BLIF a_c_27__n.BLIF pos_clk_un8_bg_030_0_n.BLIF N_98.BLIF \
+N_161_i_1.BLIF a_c_28__n.BLIF N_161_i_2.BLIF pos_clk_un8_sm_amiga_i_1_n.BLIF \
+N_355.BLIF a_c_29__n.BLIF N_324_1.BLIF N_324_2.BLIF N_128.BLIF a_c_30__n.BLIF \
+N_150_i_1.BLIF N_137.BLIF un1_SM_AMIGA_5_i_1.BLIF N_145.BLIF a_c_31__n.BLIF \
+un1_SM_AMIGA_5_i_2.BLIF N_148.BLIF N_138_i_1.BLIF N_150.BLIF A0_c.BLIF \
+N_138_i_2.BLIF N_152.BLIF N_146_i_1.BLIF N_154.BLIF A1_c.BLIF N_146_i_2.BLIF \
+N_156.BLIF N_146_i_3.BLIF N_159.BLIF nEXP_SPACE_c.BLIF N_220_1.BLIF N_161.BLIF \
+N_220_2.BLIF N_165.BLIF BERR_c.BLIF N_375_1.BLIF N_168.BLIF N_375_2.BLIF \
+N_171.BLIF BG_030_c.BLIF N_373_1.BLIF N_174.BLIF N_373_2.BLIF N_175.BLIF \
+BG_000DFFreg.BLIF N_210_1.BLIF N_178.BLIF N_210_2.BLIF N_181.BLIF N_210_3.BLIF \
+N_183.BLIF BGACK_000_c.BLIF un5_ciin_1.BLIF N_188.BLIF un5_ciin_2.BLIF \
+N_190.BLIF CLK_030_c.BLIF un5_ciin_3.BLIF N_193.BLIF un5_ciin_4.BLIF \
+N_195.BLIF un5_ciin_5.BLIF N_200.BLIF un5_ciin_6.BLIF N_205.BLIF \
+CLK_OSZI_c.BLIF un5_ciin_7.BLIF N_206.BLIF un5_ciin_8.BLIF N_207.BLIF \
+un5_ciin_9.BLIF N_208.BLIF un5_ciin_10.BLIF N_210.BLIF un5_ciin_11.BLIF \
+N_211.BLIF FPU_SENSE_c.BLIF N_302_1.BLIF N_212.BLIF N_244_i_1.BLIF N_373.BLIF \
+IPL_030DFF_0_reg.BLIF N_244_i_2.BLIF N_375.BLIF N_243_i_1.BLIF N_216.BLIF \
+IPL_030DFF_1_reg.BLIF N_410_1.BLIF N_218.BLIF N_410_2.BLIF N_219.BLIF \
+IPL_030DFF_2_reg.BLIF N_410_3.BLIF N_220.BLIF N_410_4.BLIF N_221.BLIF \
+ipl_c_0__n.BLIF N_237_1.BLIF N_222.BLIF N_237_2.BLIF N_224.BLIF \
+ipl_c_1__n.BLIF un21_fpu_cs_1.BLIF N_225.BLIF un22_berr_1_0.BLIF N_226.BLIF \
+ipl_c_2__n.BLIF N_233_1.BLIF N_228.BLIF N_233_2.BLIF N_230.BLIF N_245_i_1.BLIF \
+N_231.BLIF DTACK_c.BLIF N_128_i_1.BLIF N_240.BLIF N_134_i_1.BLIF N_241.BLIF \
+N_124_0_1.BLIF N_277.BLIF N_267_i_1.BLIF N_278.BLIF VPA_c.BLIF N_268_i_1.BLIF \
+N_279.BLIF N_355_0_1.BLIF N_280.BLIF N_353_i_1.BLIF N_281.BLIF RST_c.BLIF \
+N_140_i_1.BLIF N_302.BLIF N_142_i_1.BLIF N_313.BLIF N_280_1.BLIF N_318.BLIF \
+RW_c.BLIF N_225_1.BLIF N_321.BLIF N_224_1.BLIF N_324.BLIF fc_c_0__n.BLIF \
+N_219_1.BLIF N_326.BLIF N_218_1.BLIF N_329.BLIF fc_c_1__n.BLIF N_212_1.BLIF \
+N_332.BLIF N_208_1.BLIF N_348.BLIF N_207_1.BLIF cpu_est_0_0_x2_0_x2_0_.BLIF \
+AMIGA_BUS_DATA_DIR_c.BLIF N_200_1.BLIF pos_clk_CYCLE_DMA_5_0_i_0_x2.BLIF \
+N_195_1.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF pos_clk_ipl_1_n.BLIF N_235.BLIF \
+ipl_030_0_1__un3_n.BLIF N_196.BLIF ipl_030_0_1__un1_n.BLIF N_143.BLIF \
+N_7_i.BLIF ipl_030_0_1__un0_n.BLIF N_158.BLIF N_47_0.BLIF \
+as_030_000_sync_0_un3_n.BLIF N_198.BLIF N_5_i.BLIF \
+as_030_000_sync_0_un1_n.BLIF N_199.BLIF N_48_0.BLIF \
+as_030_000_sync_0_un0_n.BLIF N_307.BLIF N_3_i.BLIF as_000_int_0_un3_n.BLIF \
+N_201.BLIF N_50_0.BLIF as_000_int_0_un1_n.BLIF N_182.BLIF nEXP_SPACE_c_i.BLIF \
+as_000_int_0_un0_n.BLIF N_243_2.BLIF N_55_0.BLIF ds_000_dma_0_un3_n.BLIF \
+N_8.BLIF VPA_c_i.BLIF ds_000_dma_0_un1_n.BLIF N_356.BLIF N_56_0.BLIF \
+ds_000_dma_0_un0_n.BLIF N_10.BLIF DTACK_c_i.BLIF ipl_030_0_2__un3_n.BLIF \
+pos_clk_un6_bgack_000_n.BLIF N_57_0.BLIF ipl_030_0_2__un1_n.BLIF N_19.BLIF \
+ipl_c_i_1__n.BLIF ipl_030_0_2__un0_n.BLIF N_352.BLIF N_53_0.BLIF \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n.BLIF N_327.BLIF \
+ipl_c_i_2__n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n.BLIF \
+N_20.BLIF N_54_0.BLIF un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n.BLIF \
+pos_clk_a0_dma_3_n.BLIF N_28_i.BLIF sm_amiga_srsts_i_0_0_m3_1__un3_n.BLIF \
+N_24.BLIF N_32_0.BLIF sm_amiga_srsts_i_0_0_m3_1__un1_n.BLIF N_113.BLIF \
+N_29_i.BLIF sm_amiga_srsts_i_0_0_m3_1__un0_n.BLIF N_25.BLIF N_33_0.BLIF \
+sm_amiga_srsts_i_0_0_m3_5__un3_n.BLIF N_114.BLIF N_378_i.BLIF \
+sm_amiga_srsts_i_0_0_m3_5__un1_n.BLIF pos_clk_size_dma_6_0__n.BLIF \
+sm_amiga_srsts_i_0_0_m3_5__un0_n.BLIF N_232.BLIF size_dma_0_0__un3_n.BLIF \
+pos_clk_size_dma_6_1__n.BLIF N_227_i.BLIF size_dma_0_0__un1_n.BLIF N_410.BLIF \
+N_354_0.BLIF size_dma_0_0__un0_n.BLIF N_185.BLIF N_233_i.BLIF \
+size_dma_0_1__un3_n.BLIF N_236.BLIF N_357_0.BLIF size_dma_0_1__un1_n.BLIF \
+N_238.BLIF N_270_0.BLIF size_dma_0_1__un0_n.BLIF N_173.BLIF AS_000_DMA_i.BLIF \
+as_000_dma_0_un3_n.BLIF N_239.BLIF N_137_0.BLIF as_000_dma_0_un1_n.BLIF \
+N_331.BLIF N_312_i.BLIF as_000_dma_0_un0_n.BLIF N_237.BLIF \
+pos_clk_un3_as_030_d0_i_n.BLIF bgack_030_int_0_un3_n.BLIF un22_berr_1.BLIF \
+N_161_i.BLIF bgack_030_int_0_un1_n.BLIF N_233.BLIF N_179_0.BLIF \
+bgack_030_int_0_un0_n.BLIF N_209.BLIF N_180_0.BLIF rw_000_dma_0_un3_n.BLIF \
+AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF \
+LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF \
+RW.PIN.BLIF
+.outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \
+AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
+AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \
+SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \
+SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D \
+SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \
+cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D \
+IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \
+IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \
+IPL_D0_2_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \
+CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \
+CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \
+CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \
+CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \
+CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \
+SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \
+CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \
+CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C \
+CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.D \
+CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C \
+CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D \
+CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C \
+CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D \
+CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C \
+CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D \
+CLK_000_N_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \
+RST_DLY_2_.D RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C \
+inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_RW_000_DMA.D inst_RW_000_DMA.C \
+inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \
+inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \
+inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
+inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \
+inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \
+inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C \
+inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C \
+inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C \
+BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \
+inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \
+inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \
+inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \
+inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_NE.D \
+inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \
+inst_CLK_OUT_INTreg.D inst_CLK_OUT_INTreg.C inst_CLK_000_D1.D \
+inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \
+inst_CLK_OUT_EXP_INT.D inst_CLK_OUT_EXP_INT.C inst_CLK_OUT_PRE_D.D \
+inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D \
+inst_CLK_000_PE.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 LDS_000 A0 BERR RW \
+SIZE_0_ N_184 N_184_0 rw_000_dma_0_un1_n N_180 N_185_0 rw_000_dma_0_un0_n \
+N_179 UDS_000_c_i a0_dma_0_un3_n LDS_000_c_i a0_dma_0_un1_n N_312 N_173_i \
+a0_dma_0_un0_n N_270 N_358_0 amiga_bus_enable_dma_low_0_un3_n N_357 N_239_i \
+amiga_bus_enable_dma_low_0_un1_n N_354 pos_clk_size_dma_6_0_1__n \
+amiga_bus_enable_dma_low_0_un0_n vcc_n_n N_227 N_238_i \
+amiga_bus_enable_dma_high_0_un3_n un5_e N_378 pos_clk_size_dma_6_0_0__n \
+amiga_bus_enable_dma_high_0_un1_n N_29 N_237_i \
+amiga_bus_enable_dma_high_0_un0_n gnd_n_n N_28 N_236_i cpu_est_0_2__un3_n \
+un1_amiga_bus_enable_low N_3 AMIGA_BUS_DATA_DIR_c_0 cpu_est_0_2__un1_n \
+un3_size N_5 N_331_i cpu_est_0_2__un0_n un4_size N_7 pos_clk_un6_bgack_000_0_n \
+cpu_est_0_3__un3_n un4_uds_000 N_190_i N_356_0 cpu_est_0_3__un1_n un4_lds_000 \
+un1_amiga_bus_enable_low_i N_352_0 cpu_est_0_3__un0_n un5_ciin un21_fpu_cs_i \
+N_8_i ipl_030_0_0__un3_n un4_as_000 CLK_OUT_EXP_INT_i N_46_0 \
+ipl_030_0_0__un1_n un1_SM_AMIGA_5 AS_000_i N_10_i ipl_030_0_0__un0_n \
+un21_fpu_cs DS_000_DMA_i N_44_0 rw_000_int_0_un3_n un22_berr sm_amiga_i_5__n \
+N_19_i rw_000_int_0_un1_n un6_ds_030 sm_amiga_i_6__n N_41_0 rw_000_int_0_un0_n \
+sm_amiga_i_0__n N_20_i uds_000_int_0_un3_n CLK_000_NE_i N_40_0 \
+uds_000_int_0_un1_n sm_amiga_i_4__n N_24_i uds_000_int_0_un0_n RW_000_i N_36_0 \
+vma_int_0_un3_n sm_amiga_i_2__n N_25_i vma_int_0_un1_n CLK_000_D0_i N_35_0 \
+vma_int_0_un0_n BERR_i bg_000_0_un3_n sm_amiga_i_1__n N_198_i bg_000_0_un1_n \
+CLK_000_PE_i N_243_2_i bg_000_0_un0_n N_410_i_0 N_196_i cpu_est_0_1__un3_n \
+sm_amiga_i_i_7__n N_195_i cpu_est_0_1__un1_n AS_030_i cpu_est_0_1__un0_n \
+FPU_SENSE_i N_201_i dsack1_int_0_un3_n nEXP_SPACE_D0_i N_200_i \
+dsack1_int_0_un1_n BGACK_030_INT_i N_199_i dsack1_int_0_un0_n \
+AMIGA_BUS_ENABLE_DMA_HIGH_i N_182_0 ds_000_enable_0_un3_n A1_i N_158_i \
+ds_000_enable_0_un1_n CLK_030_H_i N_148_i ds_000_enable_0_un0_n a_i_16__n \
+N_307_i lds_000_int_0_un3_n a_i_18__n N_143_0 lds_000_int_0_un1_n a_i_19__n \
+N_217_i lds_000_int_0_un0_n N_114_i N_235_i a_15__n N_113_i AS_000_INT_i \
+N_210_i a_14__n AMIGA_BUS_ENABLE_DMA_LOW_i rst_dly_i_2__n N_207_i a_13__n \
+rst_dly_i_0__n N_208_i rst_dly_i_1__n N_206_i a_12__n RESET_OUT_i \
+size_dma_i_1__n N_313_i a_11__n size_dma_i_0__n N_211_i AS_030_D0_i N_212_i \
+a_10__n a_i_24__n N_183_0 sm_amiga_i_3__n N_181_0 a_9__n cpu_est_i_3__n \
+N_178_0 cpu_est_i_0__n N_69_0 a_8__n VPA_D_i N_329_i cpu_est_i_1__n N_176_i \
+a_7__n CLK_030_i N_175_0 pos_clk_ipl_n CLK_000_D1_i N_174_0 a_6__n \
+cpu_est_i_2__n N_171_0 DTACK_D0_i un1_SM_AMIGA_5_i a_5__n RW_i N_324_i \
+a_i_31__n N_326_i a_4__n a_i_29__n N_168_i pos_clk_un8_bg_030_n a_i_30__n \
+VMA_INT_i a_3__n a_i_27__n N_165_i a_i_28__n N_164_i a_2__n a_i_25__n N_162_i \
+a_i_26__n clk_000_n_sync_i_10__n N_213_i N_321_i N_214_i N_159_0 N_215_i \
+N_318_i N_156_i DS_000_ENABLE_1_sqmuxa_i N_155_i N_98_i N_154_i un6_ds_030_i \
+CLK_OUT_PRE_D_i un4_as_000_i N_152_0 un4_lds_000_i N_150_i un4_uds_000_i \
+AS_030_000_SYNC_i LDS_000_INT_i N_147_i UDS_000_INT_i N_145_i AS_030_c N_281_i \
+N_302_i AS_000_c N_279_i RW_000_c N_280_i un5_e_0 pos_clk_un7_clk_000_pe_n \
+N_278_i UDS_000_c cpu_est_2_0_3__n N_277_i DS_000_ENABLE_1_sqmuxa LDS_000_c \
+N_348_i cpu_est_2_0_2__n size_c_0__n N_128_i N_193_i size_c_1__n N_241_i \
+pos_clk_un3_as_030_d0_n DS_000_ENABLE_1_sqmuxa_1 N_240_i N_4 N_124_0 N_6 \
+N_269_0 un5_ciin_i N_61_0 un1_as_030_i N_17 N_228_i N_18 N_355_0 N_21 N_226_i \
+N_22 N_26 N_224_i N_27 N_225_i N_282_0 N_221_i N_222_i N_219_i N_220_i N_283_0 \
+N_216_i N_218_i cpu_est_2_0_1__n N_373_i N_375_i pos_clk_un7_clk_000_pe_0_n \
+N_188_i a_c_16__n N_205_i a_c_17__n pos_clk_un8_sm_amiga_i_n A0_c_i a_c_18__n \
+size_c_i_1__n N_27_i a_c_19__n N_31_0 ipl_c_i_0__n a_c_20__n N_52_0 N_4_i \
+a_c_21__n N_49_0 N_17_i a_c_22__n N_43_0 N_124 N_18_i cpu_est_2_1__n a_c_23__n \
+N_42_0 cpu_est_2_2__n N_21_i cpu_est_2_3__n a_c_24__n N_39_0 N_22_i a_c_25__n \
+N_38_0 N_26_i N_269 a_c_26__n N_34_0 N_61 BG_030_c_i a_c_27__n \
+pos_clk_un8_bg_030_0_n N_98 N_161_i_1 a_c_28__n N_161_i_2 \
+pos_clk_un8_sm_amiga_i_1_n N_355 a_c_29__n N_324_1 N_324_2 N_128 a_c_30__n \
+N_150_i_1 N_137 un1_SM_AMIGA_5_i_1 N_145 a_c_31__n un1_SM_AMIGA_5_i_2 N_148 \
+N_138_i_1 N_150 A0_c N_138_i_2 N_152 N_146_i_1 N_154 A1_c N_146_i_2 N_156 \
+N_146_i_3 N_159 nEXP_SPACE_c N_220_1 N_161 N_220_2 N_165 BERR_c N_375_1 N_168 \
+N_375_2 N_171 BG_030_c N_373_1 N_174 N_373_2 N_175 N_210_1 N_178 N_210_2 N_181 \
+N_210_3 N_183 BGACK_000_c un5_ciin_1 N_188 un5_ciin_2 N_190 CLK_030_c \
+un5_ciin_3 N_193 un5_ciin_4 N_195 un5_ciin_5 N_200 un5_ciin_6 N_205 CLK_OSZI_c \
+un5_ciin_7 N_206 un5_ciin_8 N_207 un5_ciin_9 N_208 un5_ciin_10 N_210 \
+un5_ciin_11 N_211 FPU_SENSE_c N_302_1 N_212 N_244_i_1 N_373 N_244_i_2 N_375 \
+N_243_i_1 N_216 N_410_1 N_218 N_410_2 N_219 N_410_3 N_220 N_410_4 N_221 \
+ipl_c_0__n N_237_1 N_222 N_237_2 N_224 ipl_c_1__n un21_fpu_cs_1 N_225 \
+un22_berr_1_0 N_226 ipl_c_2__n N_233_1 N_228 N_233_2 N_230 N_245_i_1 N_231 \
+DTACK_c N_128_i_1 N_240 N_134_i_1 N_241 N_124_0_1 N_277 N_267_i_1 N_278 VPA_c \
+N_268_i_1 N_279 N_355_0_1 N_280 N_353_i_1 N_281 RST_c N_140_i_1 N_302 \
+N_142_i_1 N_313 N_280_1 N_318 RW_c N_225_1 N_321 N_224_1 N_324 fc_c_0__n \
+N_219_1 N_326 N_218_1 N_329 fc_c_1__n N_212_1 N_332 N_208_1 N_348 N_207_1 \
+AMIGA_BUS_DATA_DIR_c N_200_1 N_195_1 pos_clk_ipl_1_n N_235 ipl_030_0_1__un3_n \
+N_196 ipl_030_0_1__un1_n N_143 N_7_i ipl_030_0_1__un0_n N_158 N_47_0 \
+as_030_000_sync_0_un3_n N_198 N_5_i as_030_000_sync_0_un1_n N_199 N_48_0 \
+as_030_000_sync_0_un0_n N_307 N_3_i as_000_int_0_un3_n N_201 N_50_0 \
+as_000_int_0_un1_n N_182 nEXP_SPACE_c_i as_000_int_0_un0_n N_243_2 N_55_0 \
+ds_000_dma_0_un3_n N_8 VPA_c_i ds_000_dma_0_un1_n N_356 N_56_0 \
+ds_000_dma_0_un0_n N_10 DTACK_c_i ipl_030_0_2__un3_n pos_clk_un6_bgack_000_n \
+N_57_0 ipl_030_0_2__un1_n N_19 ipl_c_i_1__n ipl_030_0_2__un0_n N_352 N_53_0 \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n N_327 ipl_c_i_2__n \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n N_20 N_54_0 \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n pos_clk_a0_dma_3_n N_28_i \
+sm_amiga_srsts_i_0_0_m3_1__un3_n N_24 N_32_0 sm_amiga_srsts_i_0_0_m3_1__un1_n \
+N_113 N_29_i sm_amiga_srsts_i_0_0_m3_1__un0_n N_25 N_33_0 \
+sm_amiga_srsts_i_0_0_m3_5__un3_n N_114 N_378_i \
+sm_amiga_srsts_i_0_0_m3_5__un1_n pos_clk_size_dma_6_0__n \
+sm_amiga_srsts_i_0_0_m3_5__un0_n N_232 size_dma_0_0__un3_n \
+pos_clk_size_dma_6_1__n N_227_i size_dma_0_0__un1_n N_410 N_354_0 \
+size_dma_0_0__un0_n N_185 N_233_i size_dma_0_1__un3_n N_236 N_357_0 \
+size_dma_0_1__un1_n N_238 N_270_0 size_dma_0_1__un0_n N_173 AS_000_DMA_i \
+as_000_dma_0_un3_n N_239 N_137_0 as_000_dma_0_un1_n N_331 N_312_i \
+as_000_dma_0_un0_n N_237 pos_clk_un3_as_030_d0_i_n bgack_030_int_0_un3_n \
+un22_berr_1 N_161_i bgack_030_int_0_un1_n N_233 N_179_0 bgack_030_int_0_un0_n \
+N_209 N_180_0 rw_000_dma_0_un3_n AS_030.OE AS_000.OE RW_000.OE UDS_000.OE \
+LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE \
+RESET.OE CIIN.OE pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2 CLK_OUT_PRE_25_0 \
+G_134 G_135 G_136 cpu_est_0_0_x2_0_x2_0_ pos_clk_CYCLE_DMA_5_0_i_0_x2 \
+pos_clk_CYCLE_DMA_5_1_i_0_x2
+.names N_146_i_3.BLIF N_210_i.BLIF SM_AMIGA_i_7_.D
+11 1
+.names N_282_0.BLIF SM_AMIGA_6_.D
+0 1
+.names N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D
+11 1
+.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D
+11 1
+.names N_138_i_1.BLIF N_138_i_2.BLIF SM_AMIGA_3_.D
+11 1
+.names N_283_0.BLIF SM_AMIGA_2_.D
+0 1
+.names N_134_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D
+11 1
+.names N_176_i.BLIF N_378_i.BLIF SM_AMIGA_0_.D
+11 1
+.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D
+1- 1
+-1 1
+.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D
+1- 1
+-1 1
+.names N_31_0.BLIF IPL_030DFF_0_reg.D
+0 1
+.names N_32_0.BLIF IPL_030DFF_1_reg.D
+0 1
+.names N_33_0.BLIF IPL_030DFF_2_reg.D
+0 1
+.names N_52_0.BLIF IPL_D0_0_.D
+0 1
+.names N_53_0.BLIF IPL_D0_1_.D
+0 1
+.names N_54_0.BLIF IPL_D0_2_.D
+0 1
+.names N_268_i_1.BLIF N_69_0.BLIF CYCLE_DMA_0_.D
+11 1
+.names N_267_i_1.BLIF N_69_0.BLIF CYCLE_DMA_1_.D
+11 1
+.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D
+1- 1
+-1 1
+.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D
+1- 1
+-1 1
+.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D
+1- 1
+-1 1
+.names N_245_i_1.BLIF RST_c.BLIF RST_DLY_0_.D
+11 1
+.names N_244_i_1.BLIF N_244_i_2.BLIF RST_DLY_1_.D
+11 1
+.names N_243_i_1.BLIF N_196_i.BLIF RST_DLY_2_.D
+11 1
+.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D
+11 1
+.names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D
+11 1
+.names N_41_0.BLIF inst_RW_000_DMA.D
+0 1
+.names N_42_0.BLIF inst_RW_000_INT.D
+0 1
+.names N_43_0.BLIF inst_LDS_000_INT.D
+0 1
+.names N_44_0.BLIF inst_BGACK_030_INTreg.D
+0 1
+.names N_46_0.BLIF inst_AS_000_DMA.D
+0 1
+.names N_47_0.BLIF inst_AS_030_000_SYNC.D
+0 1
+.names N_48_0.BLIF inst_AS_000_INT.D
+0 1
+.names N_49_0.BLIF inst_DSACK1_INTreg.D
+0 1
+.names N_50_0.BLIF inst_DS_000_DMA.D
+0 1
+.names N_358_0.BLIF inst_AS_030_D0.D
+0 1
+.names N_55_0.BLIF inst_nEXP_SPACE_D0reg.D
+0 1
+.names N_56_0.BLIF inst_VPA_D.D
+0 1
+.names N_57_0.BLIF inst_DTACK_D0.D
+0 1
+.names N_353_i_1.BLIF RST_c.BLIF inst_CLK_030_H.D
+11 1
+.names N_235_i.BLIF RST_c.BLIF inst_RESET_OUT.D
+11 1
+.names N_34_0.BLIF BG_000DFFreg.D
+0 1
+.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D
+0 1
+.names N_36_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D
+0 1
+.names N_38_0.BLIF inst_VMA_INTreg.D
+0 1
+.names N_39_0.BLIF inst_UDS_000_INT.D
+0 1
+.names N_40_0.BLIF inst_A0_DMA.D
+0 1
+.names N_69_0.BLIF inst_BGACK_030_INT_D.D
+0 1
+.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
+0 1
+.names N_184_0.BLIF N_184
+0 1
+.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_184_0
+11 1
+.names inst_RW_000_DMA.BLIF N_327.BLIF rw_000_dma_0_un1_n
+11 1
+.names N_180_0.BLIF N_180
+0 1
+.names AS_000_DMA_i.BLIF CLK_030_i.BLIF N_185_0
+11 1
+.names N_352.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n
+11 1
+.names N_179_0.BLIF N_179
+0 1
+.names UDS_000_c.BLIF UDS_000_c_i
+0 1
+.names N_327.BLIF a0_dma_0_un3_n
+0 1
+.names LDS_000_c.BLIF LDS_000_c_i
+0 1
+.names inst_A0_DMA.BLIF N_327.BLIF a0_dma_0_un1_n
+11 1
+.names LDS_000_c.BLIF UDS_000_c.BLIF N_312
+11 1
+.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_173_i
+11 1
+.names pos_clk_a0_dma_3_n.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n
+11 1
+.names N_270_0.BLIF N_270
+0 1
+.names AS_030_i.BLIF RST_c.BLIF N_358_0
+11 1
+.names N_327.BLIF amiga_bus_enable_dma_low_0_un3_n
+0 1
+.names N_357_0.BLIF N_357
+0 1
+.names N_239.BLIF N_239_i
+0 1
+.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_327.BLIF \
+amiga_bus_enable_dma_low_0_un1_n
+11 1
+.names N_354_0.BLIF N_354
+0 1
+.names N_239_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n
+11 1
+.names N_113_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF \
+amiga_bus_enable_dma_low_0_un0_n
+11 1
+.names vcc_n_n
+ 1
+.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_227
+11 1
+.names N_238.BLIF N_238_i
+0 1
+.names N_327.BLIF amiga_bus_enable_dma_high_0_un3_n
+0 1
+.names un5_e_0.BLIF un5_e
+0 1
+.names N_184.BLIF sm_amiga_i_0__n.BLIF N_378
+11 1
+.names N_238_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n
+11 1
+.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_327.BLIF \
+amiga_bus_enable_dma_high_0_un1_n
+11 1
+.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29
+1- 1
+-1 1
+.names N_237.BLIF N_237_i
+0 1
+.names N_114_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF \
+amiga_bus_enable_dma_high_0_un0_n
+11 1
+.names gnd_n_n
+.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28
+1- 1
+-1 1
+.names N_236.BLIF N_236_i
+0 1
+.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n
+0 1
+.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \
+un1_amiga_bus_enable_low
+11 1
+.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3
+1- 1
+-1 1
+.names N_236_i.BLIF N_237_i.BLIF AMIGA_BUS_DATA_DIR_c_0
+11 1
+.names cpu_est_2_2__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n
+11 1
+.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size
+11 1
+.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_5
+1- 1
+-1 1
+.names N_331.BLIF N_331_i
+0 1
+.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n
+11 1
+.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size
+11 1
+.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_7
+1- 1
+-1 1
+.names BGACK_000_c.BLIF N_331_i.BLIF pos_clk_un6_bgack_000_0_n
+11 1
+.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n
+0 1
+.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un4_uds_000
+11 1
+.names N_190.BLIF N_190_i
+0 1
+.names CLK_030_i.BLIF N_161_i.BLIF N_356_0
+11 1
+.names cpu_est_2_3__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n
+11 1
+.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un4_lds_000
+11 1
+.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i
+0 1
+.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_352_0
+11 1
+.names cpu_est_3_.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n
+11 1
+.names un5_ciin_10.BLIF un5_ciin_11.BLIF un5_ciin
+11 1
+.names un21_fpu_cs.BLIF un21_fpu_cs_i
+0 1
+.names N_8.BLIF N_8_i
+0 1
+.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n
+0 1
+.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000
+11 1
+.names inst_CLK_OUT_EXP_INT.BLIF CLK_OUT_EXP_INT_i
+0 1
+.names N_8_i.BLIF RST_c.BLIF N_46_0
+11 1
+.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n
+11 1
+.names un1_SM_AMIGA_5_i.BLIF un1_SM_AMIGA_5
+0 1
+.names AS_000_c.BLIF AS_000_i
+0 1
+.names N_10.BLIF N_10_i
+0 1
+.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
+11 1
+.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs
+11 1
+.names inst_DS_000_DMA.BLIF DS_000_DMA_i
+0 1
+.names N_10_i.BLIF RST_c.BLIF N_44_0
+11 1
+.names N_124.BLIF rw_000_int_0_un3_n
+0 1
+.names un22_berr_1_0.BLIF FPU_SENSE_c.BLIF un22_berr
+11 1
+.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
+0 1
+.names N_19.BLIF N_19_i
+0 1
+.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_124.BLIF rw_000_int_0_un1_n
+11 1
+.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030
+11 1
+.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
+0 1
+.names N_19_i.BLIF RST_c.BLIF N_41_0
+11 1
+.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n
+11 1
+.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n
+0 1
+.names N_20.BLIF N_20_i
+0 1
+.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n
+0 1
+.names inst_CLK_000_NE.BLIF CLK_000_NE_i
+0 1
+.names N_20_i.BLIF RST_c.BLIF N_40_0
+11 1
+.names A0_c.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n
+11 1
+.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
+0 1
+.names N_24.BLIF N_24_i
+0 1
+.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n
+11 1
+.names RW_000_c.BLIF RW_000_i
+0 1
+.names N_24_i.BLIF RST_c.BLIF N_36_0
+11 1
+.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n
+0 1
+.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n
+0 1
+.names N_25.BLIF N_25_i
+0 1
+.names cpu_est_i_1__n.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n
+11 1
+.names inst_CLK_000_D0.BLIF CLK_000_D0_i
+0 1
+.names N_25_i.BLIF RST_c.BLIF N_35_0
+11 1
+.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
+11 1
+.names BERR_c.BLIF BERR_i
+0 1
+.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n
+0 1
+.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
+0 1
+.names N_198.BLIF N_198_i
+0 1
+.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n
+11 1
+.names inst_CLK_000_PE.BLIF CLK_000_PE_i
+0 1
+.names N_198_i.BLIF RST_c.BLIF N_243_2_i
+11 1
+.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
+11 1
+.names N_410.BLIF N_410_i_0
+0 1
+.names N_196.BLIF N_196_i
+0 1
+.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n
+0 1
+.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n
+0 1
+.names N_195.BLIF N_195_i
+0 1
+.names cpu_est_2_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n
+11 1
+.names AS_030_c.BLIF AS_030_i
+0 1
+.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n
+11 1
+.names FPU_SENSE_c.BLIF FPU_SENSE_i
+0 1
+.names N_201.BLIF N_201_i
+0 1
+.names N_269.BLIF dsack1_int_0_un3_n
+0 1
+.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i
+0 1
+.names N_200.BLIF N_200_i
+0 1
+.names N_98_i.BLIF N_269.BLIF dsack1_int_0_un1_n
+11 1
+.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
+0 1
+.names N_199.BLIF N_199_i
+0 1
+.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n
+11 1
+.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i
+0 1
+.names inst_CLK_000_NE.BLIF N_158_i.BLIF N_182_0
+11 1
+.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n
+0 1
+.names A1_c.BLIF A1_i
+0 1
+.names N_148_i.BLIF RST_DLY_2_.BLIF N_158_i
+11 1
+.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF \
+ds_000_enable_0_un1_n
+11 1
+.names inst_CLK_030_H.BLIF CLK_030_H_i
+0 1
+.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_148_i
+11 1
+.names un1_SM_AMIGA_5_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n
+11 1
+.names a_c_16__n.BLIF a_i_16__n
+0 1
+.names N_307.BLIF N_307_i
+0 1
+.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n
+0 1
+.names a_c_18__n.BLIF a_i_18__n
+0 1
+.names N_307_i.BLIF RST_c.BLIF N_143_0
+11 1
+.names pos_clk_un8_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n
+11 1
+.names a_c_19__n.BLIF a_i_19__n
+0 1
+.names N_158.BLIF RST_c.BLIF N_217_i
+11 1
+.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n
+11 1
+.names N_114.BLIF N_114_i
+0 1
+.names N_235.BLIF N_235_i
+0 1
+.names N_113.BLIF N_113_i
+0 1
+.names inst_AS_000_INT.BLIF AS_000_INT_i
+0 1
+.names N_210.BLIF N_210_i
+0 1
+.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i
+0 1
+.names RST_DLY_2_.BLIF rst_dly_i_2__n
+0 1
+.names N_207.BLIF N_207_i
+0 1
+.names RST_DLY_0_.BLIF rst_dly_i_0__n
+0 1
+.names N_208.BLIF N_208_i
+0 1
+.names RST_DLY_1_.BLIF rst_dly_i_1__n
+0 1
+.names N_206.BLIF N_206_i
+0 1
+.names inst_RESET_OUT.BLIF RESET_OUT_i
+0 1
+.names SIZE_DMA_1_.BLIF size_dma_i_1__n
+0 1
+.names N_313.BLIF N_313_i
+0 1
+.names SIZE_DMA_0_.BLIF size_dma_i_0__n
+0 1
+.names N_211.BLIF N_211_i
+0 1
+.names inst_AS_030_D0.BLIF AS_030_D0_i
+0 1
+.names N_212.BLIF N_212_i
+0 1
+.names a_c_24__n.BLIF a_i_24__n
+0 1
+.names inst_CLK_000_PE.BLIF SM_AMIGA_4_.BLIF N_183_0
+11 1
+.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n
+0 1
+.names inst_CLK_000_NE_D0.BLIF N_168.BLIF N_181_0
+11 1
+.names cpu_est_3_.BLIF cpu_est_i_3__n
+0 1
+.names N_145_i.BLIF SM_AMIGA_4_.BLIF N_178_0
+11 1
+.names cpu_est_0_.BLIF cpu_est_i_0__n
+0 1
+.names BGACK_030_INT_i.BLIF RST_c.BLIF N_69_0
+11 1
+.names inst_VPA_D.BLIF VPA_D_i
+0 1
+.names N_329.BLIF N_329_i
+0 1
+.names cpu_est_1_.BLIF cpu_est_i_1__n
+0 1
+.names N_329_i.BLIF RST_c.BLIF N_176_i
+11 1
+.names CLK_030_c.BLIF CLK_030_i
+0 1
+.names N_145.BLIF sm_amiga_i_3__n.BLIF N_175_0
+11 1
+.names pos_clk_ipl_1_n.BLIF N_214_i.BLIF pos_clk_ipl_n
+11 1
+.names inst_CLK_000_D1.BLIF CLK_000_D1_i
+0 1
+.names N_145.BLIF SM_AMIGA_i_7_.BLIF N_174_0
+11 1
+.names cpu_est_2_.BLIF cpu_est_i_2__n
+0 1
+.names N_164_i.BLIF sm_amiga_i_6__n.BLIF N_171_0
+11 1
+.names inst_DTACK_D0.BLIF DTACK_D0_i
+0 1
+.names un1_SM_AMIGA_5_i_1.BLIF un1_SM_AMIGA_5_i_2.BLIF un1_SM_AMIGA_5_i
+11 1
+.names RW_c.BLIF RW_i
+0 1
+.names N_324.BLIF N_324_i
+0 1
+.names a_c_31__n.BLIF a_i_31__n
+0 1
+.names N_326.BLIF N_326_i
+0 1
+.names a_c_29__n.BLIF a_i_29__n
+0 1
+.names N_324_i.BLIF N_326_i.BLIF N_168_i
+11 1
+.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n
+0 1
+.names a_c_30__n.BLIF a_i_30__n
+0 1
+.names inst_VMA_INTreg.BLIF VMA_INT_i
+0 1
+.names a_c_27__n.BLIF a_i_27__n
+0 1
+.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_165_i
+11 1
+.names a_c_28__n.BLIF a_i_28__n
+0 1
+.names sm_amiga_i_2__n.BLIF sm_amiga_i_4__n.BLIF N_164_i
+11 1
+.names a_c_25__n.BLIF a_i_25__n
+0 1
+.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_162_i
+11 1
+.names a_c_26__n.BLIF a_i_26__n
+0 1
+.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n
+0 1
+.names G_134.BLIF N_213_i
+0 1
+.names N_321.BLIF N_321_i
+0 1
+.names G_135.BLIF N_214_i
+0 1
+.names clk_000_n_sync_i_10__n.BLIF N_321_i.BLIF N_159_0
+11 1
+.names G_136.BLIF N_215_i
+0 1
+.names N_318.BLIF N_318_i
+0 1
+.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_156_i
+11 1
+.names DS_000_ENABLE_1_sqmuxa.BLIF DS_000_ENABLE_1_sqmuxa_i
+0 1
+.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_155_i
+11 1
+.names N_98.BLIF N_98_i
+0 1
+.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_154_i
+11 1
+.names un6_ds_030.BLIF un6_ds_030_i
+0 1
+.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i
+0 1
+.names un4_as_000.BLIF un4_as_000_i
+0 1
+.names CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_152_0
+11 1
+.names un4_lds_000.BLIF un4_lds_000_i
+0 1
+.names N_150_i_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_150_i
+11 1
+.names un4_uds_000.BLIF un4_uds_000_i
+0 1
+.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
+0 1
+.names inst_LDS_000_INT.BLIF LDS_000_INT_i
+0 1
+.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_147_i
+11 1
+.names inst_UDS_000_INT.BLIF UDS_000_INT_i
+0 1
+.names BERR_c.BLIF CLK_000_PE_i.BLIF N_145_i
+11 1
+.names N_281.BLIF N_281_i
+0 1
+.names N_302.BLIF N_302_i
+0 1
+.names N_279.BLIF N_279_i
+0 1
+.names N_280.BLIF N_280_i
+0 1
+.names N_279_i.BLIF N_280_i.BLIF un5_e_0
+11 1
+.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n
+0 1
+.names N_278.BLIF N_278_i
+0 1
+.names N_154.BLIF N_278_i.BLIF cpu_est_2_0_3__n
+11 1
+.names N_277.BLIF N_277_i
+0 1
+.names RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa
+11 1
+.names N_348.BLIF N_348_i
+0 1
+.names N_277_i.BLIF N_348_i.BLIF cpu_est_2_0_2__n
+11 1
+.names N_128_i_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_128_i
+11 1
+.names N_193.BLIF N_193_i
+0 1
+.names N_241.BLIF N_241_i
+0 1
+.names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n
+0 1
+.names pos_clk_un3_as_030_d0_i_n.BLIF un1_SM_AMIGA_5.BLIF \
+DS_000_ENABLE_1_sqmuxa_1
+11 1
+.names N_240.BLIF N_240_i
+0 1
+.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_4
+1- 1
+-1 1
+.names N_124_0_1.BLIF SM_AMIGA_i_7_.BLIF N_124_0
+11 1
+.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6
+1- 1
+-1 1
+.names N_98_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_269_0
+11 1
+.names un5_ciin.BLIF un5_ciin_i
+0 1
+.names nEXP_SPACE_D0_i.BLIF un5_ciin_i.BLIF N_61_0
+11 1
+.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF un1_as_030_i
+11 1
+.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_17
+1- 1
+-1 1
+.names N_228.BLIF N_228_i
+0 1
+.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_18
+1- 1
+-1 1
+.names N_355_0_1.BLIF RW_000_i.BLIF N_355_0
+11 1
+.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21
+1- 1
+-1 1
+.names N_226.BLIF N_226_i
+0 1
+.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_22
+1- 1
+-1 1
+.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26
+1- 1
+-1 1
+.names N_224.BLIF N_224_i
+0 1
+.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27
+1- 1
+-1 1
+.names N_225.BLIF N_225_i
+0 1
+.names N_224_i.BLIF N_225_i.BLIF N_282_0
+11 1
+.names N_221.BLIF N_221_i
+0 1
+.names N_222.BLIF N_222_i
+0 1
+.names N_219.BLIF N_219_i
+0 1
+.names N_220.BLIF N_220_i
+0 1
+.names N_219_i.BLIF N_220_i.BLIF N_283_0
+11 1
+.names N_216.BLIF N_216_i
+0 1
+.names N_218.BLIF N_218_i
+0 1
+.names N_216_i.BLIF N_218_i.BLIF cpu_est_2_0_1__n
+11 1
+.names N_373.BLIF N_373_i
+0 1
+.names N_375.BLIF N_375_i
+0 1
+.names N_373_i.BLIF N_375_i.BLIF pos_clk_un7_clk_000_pe_0_n
+11 1
+.names N_188.BLIF N_188_i
+0 1
+.names N_205.BLIF N_205_i
+0 1
+.names pos_clk_un8_sm_amiga_i_1_n.BLIF size_c_0__n.BLIF \
+pos_clk_un8_sm_amiga_i_n
+11 1
+.names A0_c.BLIF A0_c_i
+0 1
+.names size_c_1__n.BLIF size_c_i_1__n
+0 1
+.names N_27.BLIF N_27_i
+0 1
+.names N_27_i.BLIF RST_c.BLIF N_31_0
+11 1
+.names ipl_c_0__n.BLIF ipl_c_i_0__n
+0 1
+.names ipl_c_i_0__n.BLIF RST_c.BLIF N_52_0
+11 1
+.names N_4.BLIF N_4_i
+0 1
+.names N_4_i.BLIF RST_c.BLIF N_49_0
+11 1
+.names N_17.BLIF N_17_i
+0 1
+.names N_17_i.BLIF RST_c.BLIF N_43_0
+11 1
+.names N_124_0.BLIF N_124
+0 1
+.names N_18.BLIF N_18_i
+0 1
+.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n
+0 1
+.names N_18_i.BLIF RST_c.BLIF N_42_0
+11 1
+.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n
+0 1
+.names N_21.BLIF N_21_i
+0 1
+.names cpu_est_2_0_3__n.BLIF cpu_est_2_3__n
+0 1
+.names N_21_i.BLIF RST_c.BLIF N_39_0
+11 1
+.names N_22.BLIF N_22_i
+0 1
+.names N_22_i.BLIF RST_c.BLIF N_38_0
+11 1
+.names N_26.BLIF N_26_i
+0 1
+.names N_269_0.BLIF N_269
+0 1
+.names N_26_i.BLIF RST_c.BLIF N_34_0
+11 1
+.names N_61_0.BLIF N_61
+0 1
+.names BG_030_c.BLIF BG_030_c_i
+0 1
+.names BG_030_c_i.BLIF N_128.BLIF pos_clk_un8_bg_030_0_n
+11 1
+.names N_159.BLIF SM_AMIGA_1_.BLIF N_98
+11 1
+.names AS_000_i.BLIF pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2.BLIF N_161_i_1
+11 1
+.names BGACK_030_INT_i.BLIF N_312_i.BLIF N_161_i_2
+11 1
+.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un8_sm_amiga_i_1_n
+11 1
+.names N_355_0.BLIF N_355
+0 1
+.names N_154_i.BLIF N_155_i.BLIF N_324_1
+11 1
+.names VMA_INT_i.BLIF VPA_D_i.BLIF N_324_2
+11 1
+.names N_128_i.BLIF N_128
+0 1
+.names AS_030_000_SYNC_i.BLIF N_147_i.BLIF N_150_i_1
+11 1
+.names N_137_0.BLIF N_137
+0 1
+.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_162_i.BLIF un1_SM_AMIGA_5_i_1
+11 1
+.names N_145_i.BLIF N_145
+0 1
+.names N_318_i.BLIF SM_AMIGA_i_7_.BLIF un1_SM_AMIGA_5_i_2
+11 1
+.names N_148_i.BLIF N_148
+0 1
+.names N_211_i.BLIF N_212_i.BLIF N_138_i_1
+11 1
+.names N_150_i.BLIF N_150
+0 1
+.names N_313_i.BLIF RST_c.BLIF N_138_i_2
+11 1
+.names N_152_0.BLIF N_152
+0 1
+.names N_176_i.BLIF N_206_i.BLIF N_146_i_1
+11 1
+.names N_154_i.BLIF N_154
+0 1
+.names N_207_i.BLIF N_208_i.BLIF N_146_i_2
+11 1
+.names N_156_i.BLIF N_156
+0 1
+.names N_146_i_1.BLIF N_146_i_2.BLIF N_146_i_3
+11 1
+.names N_159_0.BLIF N_159
+0 1
+.names inst_CLK_000_NE_D0.BLIF N_168.BLIF N_220_1
+11 1
+.names N_161_i.BLIF N_161
+0 1
+.names RST_c.BLIF SM_AMIGA_3_.BLIF N_220_2
+11 1
+.names N_165_i.BLIF N_165
+0 1
+.names inst_CLK_000_NE.BLIF N_348.BLIF N_375_1
+11 1
+.names N_168_i.BLIF N_168
+0 1
+.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_375_2
+11 1
+.names N_171_0.BLIF N_171
+0 1
+.names inst_CLK_000_PE.BLIF N_155_i.BLIF N_373_1
+11 1
+.names N_174_0.BLIF N_174
+0 1
+.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_373_2
+11 1
+.names N_175_0.BLIF N_175
+0 1
+.names N_150.BLIF N_162_i.BLIF N_210_1
+11 1
+.names N_178_0.BLIF N_178
+0 1
+.names N_164_i.BLIF N_165_i.BLIF N_210_2
+11 1
+.names N_181_0.BLIF N_181
+0 1
+.names N_210_1.BLIF N_210_2.BLIF N_210_3
+11 1
+.names N_183_0.BLIF N_183
+0 1
+.names AS_030_D0_i.BLIF a_c_20__n.BLIF un5_ciin_1
+11 1
+.names sm_amiga_srsts_i_0_0_m3_5__un1_n.BLIF \
+sm_amiga_srsts_i_0_0_m3_5__un0_n.BLIF N_188
+1- 1
+-1 1
+.names a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2
+11 1
+.names un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n.BLIF \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n.BLIF N_190
+1- 1
+-1 1
+.names a_c_23__n.BLIF a_i_24__n.BLIF un5_ciin_3
+11 1
+.names sm_amiga_srsts_i_0_0_m3_1__un1_n.BLIF \
+sm_amiga_srsts_i_0_0_m3_1__un0_n.BLIF N_193
+1- 1
+-1 1
+.names a_i_25__n.BLIF a_i_26__n.BLIF un5_ciin_4
+11 1
+.names N_195_1.BLIF rst_dly_i_2__n.BLIF N_195
+11 1
+.names a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5
+11 1
+.names N_200_1.BLIF rst_dly_i_1__n.BLIF N_200
+11 1
+.names a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6
+11 1
+.names N_180.BLIF sm_amiga_i_6__n.BLIF N_205
+11 1
+.names un5_ciin_1.BLIF un5_ciin_2.BLIF un5_ciin_7
+11 1
+.names N_181.BLIF N_313.BLIF N_206
+11 1
+.names un5_ciin_3.BLIF un5_ciin_4.BLIF un5_ciin_8
+11 1
+.names N_207_1.BLIF CLK_000_PE_i.BLIF N_207
+11 1
+.names un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9
+11 1
+.names N_208_1.BLIF CLK_000_NE_i.BLIF N_208
+11 1
+.names un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10
+11 1
+.names N_210_3.BLIF sm_amiga_i_3__n.BLIF N_210
+11 1
+.names un5_ciin_9.BLIF a_i_30__n.BLIF un5_ciin_11
+11 1
+.names N_183.BLIF sm_amiga_i_3__n.BLIF N_211
+11 1
+.names CLK_000_NE_i.BLIF rst_dly_i_0__n.BLIF N_302_1
+11 1
+.names N_212_1.BLIF sm_amiga_i_4__n.BLIF N_212
+11 1
+.names N_199_i.BLIF N_200_i.BLIF N_244_i_1
+11 1
+.names N_373_1.BLIF N_373_2.BLIF N_373
+11 1
+.names N_201_i.BLIF RST_c.BLIF N_244_i_2
+11 1
+.names N_375_1.BLIF N_375_2.BLIF N_375
+11 1
+.names N_243_2_i.BLIF N_195_i.BLIF N_243_i_1
+11 1
+.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_216
+11 1
+.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_410_1
+11 1
+.names N_218_1.BLIF cpu_est_i_3__n.BLIF N_218
+11 1
+.names a_c_17__n.BLIF a_i_16__n.BLIF N_410_2
+11 1
+.names N_219_1.BLIF SM_AMIGA_2_.BLIF N_219
+11 1
+.names a_i_18__n.BLIF a_i_19__n.BLIF N_410_3
+11 1
+.names N_220_1.BLIF N_220_2.BLIF N_220
+11 1
+.names N_410_1.BLIF N_410_2.BLIF N_410_4
+11 1
+.names N_178.BLIF sm_amiga_i_5__n.BLIF N_221
+11 1
+.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_237_1
+11 1
+.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_222
+11 1
+.names RW_000_c.BLIF nEXP_SPACE_D0_i.BLIF N_237_2
+11 1
+.names N_224_1.BLIF SM_AMIGA_6_.BLIF N_224
+11 1
+.names AS_030_i.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1
+11 1
+.names N_225_1.BLIF sm_amiga_i_i_7__n.BLIF N_225
+11 1
+.names un22_berr_1.BLIF AS_030_i.BLIF un22_berr_1_0
+11 1
+.names CLK_030_H_i.BLIF N_185.BLIF N_226
+11 1
+.names N_327.BLIF N_410_i_0.BLIF N_233_1
+11 1
+.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_228
+11 1
+.names sm_amiga_i_i_7__n.BLIF inst_nEXP_SPACE_D0reg.BLIF N_233_2
+11 1
+.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF N_230
+11 1
+.names N_281_i.BLIF N_302_i.BLIF N_245_i_1
+11 1
+.names N_332.BLIF nEXP_SPACE_D0_i.BLIF N_231
+11 1
+.names inst_AS_030_D0.BLIF inst_CLK_000_D0.BLIF N_128_i_1
+11 1
+.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_240
+11 1
+.names N_193_i.BLIF N_241_i.BLIF N_134_i_1
+11 1
+.names N_179.BLIF sm_amiga_i_2__n.BLIF N_241
+11 1
+.names N_240_i.BLIF sm_amiga_i_5__n.BLIF N_124_0_1
+11 1
+.names N_156.BLIF cpu_est_2_.BLIF N_277
+11 1
+.names pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF AS_000_i.BLIF N_267_i_1
+11 1
+.names N_156_i.BLIF cpu_est_2_.BLIF N_278
+11 1
+.names pos_clk_CYCLE_DMA_5_0_i_0_x2.BLIF AS_000_i.BLIF N_268_i_1
+11 1
+.names N_155_i.BLIF cpu_est_3_.BLIF N_279
+11 1
+.names N_161_i.BLIF N_228_i.BLIF N_355_0_1
+11 1
+.names N_280_1.BLIF cpu_est_i_3__n.BLIF N_280
+11 1
+.names N_161_i.BLIF N_226_i.BLIF N_353_i_1
+11 1
+.names N_143.BLIF RST_DLY_0_.BLIF N_281
+11 1
+.names N_221_i.BLIF N_222_i.BLIF N_140_i_1
+11 1
+.names N_302_1.BLIF RST_c.BLIF N_302
+11 1
+.names N_188_i.BLIF N_205_i.BLIF N_142_i_1
+11 1
+.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_313
+11 1
+.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_280_1
+11 1
+.names CLK_000_PE_i.BLIF SM_AMIGA_4_.BLIF N_318
+11 1
+.names N_150_i.BLIF RST_c.BLIF N_225_1
+11 1
+.names CLK_000_N_SYNC_9_.BLIF N_152.BLIF N_321
+11 1
+.names N_174.BLIF RST_c.BLIF N_224_1
+11 1
+.names N_324_1.BLIF N_324_2.BLIF N_324
+11 1
+.names N_175.BLIF RST_c.BLIF N_219_1
+11 1
+.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_326
+11 1
+.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_218_1
+11 1
+.names N_145.BLIF SM_AMIGA_0_.BLIF N_329
+11 1
+.names inst_CLK_000_NE_D0.BLIF N_168.BLIF N_212_1
+11 1
+.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_332
+11 1
+.names N_165.BLIF BERR_i.BLIF N_208_1
+11 1
+.names N_156_i.BLIF cpu_est_i_2__n.BLIF N_348
+11 1
+.names N_171.BLIF BERR_i.BLIF N_207_1
+11 1
+.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c
+0 1
+.names N_217_i.BLIF rst_dly_i_0__n.BLIF N_200_1
+11 1
+.names N_148.BLIF N_217_i.BLIF N_195_1
+11 1
+.names N_215_i.BLIF N_213_i.BLIF pos_clk_ipl_1_n
+11 1
+.names N_182.BLIF RESET_OUT_i.BLIF N_235
+11 1
+.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n
+0 1
+.names N_158_i.BLIF N_243_2.BLIF N_196
+11 1
+.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n
+11 1
+.names N_143_0.BLIF N_143
+0 1
+.names N_7.BLIF N_7_i
+0 1
+.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
+11 1
+.names N_158_i.BLIF N_158
+0 1
+.names N_7_i.BLIF RST_c.BLIF N_47_0
+11 1
+.names N_357.BLIF as_030_000_sync_0_un3_n
+0 1
+.names CLK_000_NE_i.BLIF rst_dly_i_2__n.BLIF N_198
+11 1
+.names N_5.BLIF N_5_i
+0 1
+.names pos_clk_un3_as_030_d0_n.BLIF N_357.BLIF as_030_000_sync_0_un1_n
+11 1
+.names N_148_i.BLIF N_307.BLIF N_199
+11 1
+.names N_5_i.BLIF RST_c.BLIF N_48_0
+11 1
+.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \
+as_030_000_sync_0_un0_n
+11 1
+.names inst_CLK_000_NE.BLIF N_158.BLIF N_307
+11 1
+.names N_3.BLIF N_3_i
+0 1
+.names N_270.BLIF as_000_int_0_un3_n
+0 1
+.names CLK_000_NE_i.BLIF rst_dly_i_1__n.BLIF N_201
+11 1
+.names N_3_i.BLIF RST_c.BLIF N_50_0
+11 1
+.names sm_amiga_i_5__n.BLIF N_270.BLIF as_000_int_0_un1_n
+11 1
+.names N_182_0.BLIF N_182
+0 1
+.names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i
+0 1
+.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
+11 1
+.names N_243_2_i.BLIF N_243_2
+0 1
+.names RST_c.BLIF nEXP_SPACE_c_i.BLIF N_55_0
+11 1
+.names N_355.BLIF ds_000_dma_0_un3_n
+0 1
+.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_8
+1- 1
+-1 1
+.names VPA_c.BLIF VPA_c_i
+0 1
+.names N_354.BLIF N_355.BLIF ds_000_dma_0_un1_n
+11 1
+.names N_356_0.BLIF N_356
+0 1
+.names RST_c.BLIF VPA_c_i.BLIF N_56_0
+11 1
+.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n
+11 1
+.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_10
+1- 1
+-1 1
+.names DTACK_c.BLIF DTACK_c_i
+0 1
+.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n
+0 1
+.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n
+0 1
+.names DTACK_c_i.BLIF RST_c.BLIF N_57_0
+11 1
+.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n
+11 1
+.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19
+1- 1
+-1 1
+.names ipl_c_1__n.BLIF ipl_c_i_1__n
+0 1
+.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
+11 1
+.names N_352_0.BLIF N_352
+0 1
+.names ipl_c_i_1__n.BLIF RST_c.BLIF N_53_0
+11 1
+.names inst_BGACK_030_INTreg.BLIF \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n
+0 1
+.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_327
+11 1
+.names ipl_c_2__n.BLIF ipl_c_i_2__n
+0 1
+.names SM_AMIGA_i_7_.BLIF inst_BGACK_030_INTreg.BLIF \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n
+11 1
+.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20
+1- 1
+-1 1
+.names ipl_c_i_2__n.BLIF RST_c.BLIF N_54_0
+11 1
+.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n.BLIF \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n
+11 1
+.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n
+11 1
+.names N_28.BLIF N_28_i
+0 1
+.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_0_m3_1__un3_n
+0 1
+.names amiga_bus_enable_dma_low_0_un1_n.BLIF \
+amiga_bus_enable_dma_low_0_un0_n.BLIF N_24
+1- 1
+-1 1
+.names N_28_i.BLIF RST_c.BLIF N_32_0
+11 1
+.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_0_m3_1__un1_n
+11 1
+.names A1_c.BLIF BGACK_030_INT_i.BLIF N_113
+11 1
+.names N_29.BLIF N_29_i
+0 1
+.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_0_m3_1__un3_n.BLIF \
+sm_amiga_srsts_i_0_0_m3_1__un0_n
+11 1
+.names amiga_bus_enable_dma_high_0_un1_n.BLIF \
+amiga_bus_enable_dma_high_0_un0_n.BLIF N_25
+1- 1
+-1 1
+.names N_29_i.BLIF RST_c.BLIF N_33_0
+11 1
+.names SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m3_5__un3_n
+0 1
+.names A1_i.BLIF BGACK_030_INT_i.BLIF N_114
+11 1
+.names N_378.BLIF N_378_i
+0 1
+.names BERR_i.BLIF SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m3_5__un1_n
+11 1
+.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n
+0 1
+.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_0_m3_5__un3_n.BLIF \
+sm_amiga_srsts_i_0_0_m3_5__un0_n
+11 1
+.names N_327.BLIF RST_c.BLIF N_232
+11 1
+.names N_232.BLIF size_dma_0_0__un3_n
+0 1
+.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n
+0 1
+.names N_227.BLIF N_227_i
+0 1
+.names SIZE_DMA_0_.BLIF N_232.BLIF size_dma_0_0__un1_n
+11 1
+.names N_410_4.BLIF N_410_3.BLIF N_410
+11 1
+.names N_161_i.BLIF N_227_i.BLIF N_354_0
+11 1
+.names pos_clk_size_dma_6_0__n.BLIF size_dma_0_0__un3_n.BLIF \
+size_dma_0_0__un0_n
+11 1
+.names N_185_0.BLIF N_185
+0 1
+.names N_233.BLIF N_233_i
+0 1
+.names N_232.BLIF size_dma_0_1__un3_n
+0 1
+.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_236
+11 1
+.names N_233_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_357_0
+11 1
+.names SIZE_DMA_1_.BLIF N_232.BLIF size_dma_0_1__un1_n
+11 1
+.names BGACK_030_INT_i.BLIF N_173.BLIF N_238
+11 1
+.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_270_0
+11 1
+.names pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF \
+size_dma_0_1__un0_n
+11 1
+.names N_173_i.BLIF N_173
+0 1
+.names inst_AS_000_DMA.BLIF AS_000_DMA_i
+0 1
+.names N_356.BLIF as_000_dma_0_un3_n
+0 1
+.names BGACK_030_INT_i.BLIF N_173_i.BLIF N_239
+11 1
+.names AS_000_DMA_i.BLIF AS_000_i.BLIF N_137_0
+11 1
+.names N_161.BLIF N_356.BLIF as_000_dma_0_un1_n
+11 1
+.names AS_000_c.BLIF inst_CLK_000_PE.BLIF N_331
+11 1
+.names N_312.BLIF N_312_i
+0 1
+.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n
+11 1
+.names N_237_1.BLIF N_237_2.BLIF N_237
+11 1
+.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n
+11 1
+.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n
+0 1
+.names BGACK_000_c.BLIF N_410.BLIF un22_berr_1
+11 1
+.names N_161_i_1.BLIF N_161_i_2.BLIF N_161_i
+11 1
+.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n
+11 1
+.names N_233_1.BLIF N_233_2.BLIF N_233
+11 1
+.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_179_0
+11 1
+.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \
+bgack_030_int_0_un0_n
+11 1
+.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_209
+11 1
+.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_180_0
+11 1
+.names N_327.BLIF rw_000_dma_0_un3_n
+0 1
+.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \
+pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2
+01 1
+10 1
+11 0
+00 0
+.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF CLK_OUT_PRE_25_0
+01 1
+10 1
+11 0
+00 0
+.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_134
+01 1
+10 1
+11 0
+00 0
+.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_135
+01 1
+10 1
+11 0
+00 0
+.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_136
+01 1
+10 1
+11 0
+00 0
+.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_x2_0_
+01 1
+10 1
+11 0
+00 0
+.names CYCLE_DMA_0_.BLIF inst_CLK_000_PE.BLIF pos_clk_CYCLE_DMA_5_0_i_0_x2
+01 1
+10 1
+11 0
+00 0
+.names CYCLE_DMA_1_.BLIF N_209.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2
+01 1
+10 1
+11 0
+00 0
+.names IPL_030DFF_2_reg.BLIF IPL_030_2_
+1 1
+0 0
+.names un6_ds_030_i.BLIF DS_030
+1 1
+0 0
+.names BG_000DFFreg.BLIF BG_000
+1 1
+0 0
+.names inst_BGACK_030_INTreg.BLIF BGACK_030
+1 1
+0 0
+.names inst_CLK_OUT_INTreg.BLIF CLK_DIV_OUT
+1 1
+0 0
+.names CLK_OUT_EXP_INT_i.BLIF CLK_EXP
+1 1
+0 0
+.names un21_fpu_cs_i.BLIF FPU_CS
+1 1
+0 0
+.names inst_DSACK1_INTreg.BLIF DSACK1
+1 1
+0 0
+.names vcc_n_n.BLIF AVEC
+1 1
+0 0
+.names un5_e.BLIF E
+1 1
+0 0
+.names inst_VMA_INTreg.BLIF VMA
+1 1
+0 0
+.names gnd_n_n.BLIF RESET
+1 1
+0 0
+.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE
+1 1
+0 0
+.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR
+1 1
+0 0
+.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW
+1 1
+0 0
+.names N_190_i.BLIF AMIGA_BUS_ENABLE_HIGH
+1 1
+0 0
+.names un5_ciin.BLIF CIIN
+1 1
+0 0
+.names IPL_030DFF_1_reg.BLIF IPL_030_1_
+1 1
+0 0
+.names IPL_030DFF_0_reg.BLIF IPL_030_0_
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF cpu_est_2_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF cpu_est_3_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF IPL_D0_0_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF IPL_D0_1_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF IPL_D0_2_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C
+1 1
+0 0
+.names cpu_est_0_0_x2_0_x2_0_.BLIF cpu_est_0_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF cpu_est_0_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF cpu_est_1_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C
+1 1
+0 0
+.names N_147_i.BLIF CLK_000_N_SYNC_0_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF RST_DLY_0_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF RST_DLY_1_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF RST_DLY_2_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_RW_000_INT.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_AS_000_INT.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_AS_030_D0.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_nEXP_SPACE_D0reg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_VPA_D.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_DTACK_D0.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_030_H.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_RESET_OUT.C
+1 1
+0 0
+.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF BG_000DFFreg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_A0_DMA.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C
+1 1
+0 0
+.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C
+1 1
+0 0
+.names inst_CLK_OUT_PRE_D.BLIF inst_CLK_OUT_INTreg.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_OUT_INTreg.C
+1 1
+0 0
+.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C
+1 1
+0 0
+.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C
+1 1
+0 0
+.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_EXP_INT.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_OUT_EXP_INT.C
+1 1
+0 0
+.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_D.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C
+1 1
+0 0
+.names CLK_000.BLIF inst_CLK_000_D0.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C
+1 1
+0 0
+.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_000_PE.C
+1 1
+0 0
+.names un3_size.BLIF SIZE_1_
+1 1
+0 0
+.names N_137.BLIF AS_030
+1 1
+0 0
+.names un4_as_000_i.BLIF AS_000
+1 1
+0 0
+.names inst_RW_000_INT.BLIF RW_000
+1 1
+0 0
+.names un4_uds_000_i.BLIF UDS_000
+1 1
+0 0
+.names un4_lds_000_i.BLIF LDS_000
+1 1
+0 0
+.names inst_A0_DMA.BLIF A0
+1 1
+0 0
+.names gnd_n_n.BLIF BERR
+1 1
+0 0
+.names inst_RW_000_DMA.BLIF RW
+1 1
+0 0
+.names un4_size.BLIF SIZE_0_
+1 1
+0 0
+.names A_15_.BLIF a_15__n
+1 1
+0 0
+.names A_14_.BLIF a_14__n
+1 1
+0 0
+.names A_13_.BLIF a_13__n
+1 1
+0 0
+.names A_12_.BLIF a_12__n
+1 1
+0 0
+.names A_11_.BLIF a_11__n
+1 1
+0 0
+.names A_10_.BLIF a_10__n
+1 1
+0 0
+.names A_9_.BLIF a_9__n
+1 1
+0 0
+.names A_8_.BLIF a_8__n
+1 1
+0 0
+.names A_7_.BLIF a_7__n
+1 1
+0 0
+.names A_6_.BLIF a_6__n
+1 1
+0 0
+.names A_5_.BLIF a_5__n
+1 1
+0 0
+.names A_4_.BLIF a_4__n
+1 1
+0 0
+.names A_3_.BLIF a_3__n
+1 1
+0 0
+.names A_2_.BLIF a_2__n
+1 1
+0 0
+.names AS_030.PIN.BLIF AS_030_c
+1 1
+0 0
+.names AS_000.PIN.BLIF AS_000_c
+1 1
+0 0
+.names RW_000.PIN.BLIF RW_000_c
+1 1
+0 0
+.names UDS_000.PIN.BLIF UDS_000_c
+1 1
+0 0
+.names LDS_000.PIN.BLIF LDS_000_c
+1 1
+0 0
+.names SIZE_0_.PIN.BLIF size_c_0__n
+1 1
+0 0
+.names SIZE_1_.PIN.BLIF size_c_1__n
+1 1
+0 0
+.names A_16_.BLIF a_c_16__n
+1 1
+0 0
+.names A_17_.BLIF a_c_17__n
+1 1
+0 0
+.names A_18_.BLIF a_c_18__n
+1 1
+0 0
+.names A_19_.BLIF a_c_19__n
+1 1
+0 0
+.names A_20_.BLIF a_c_20__n
+1 1
+0 0
+.names A_21_.BLIF a_c_21__n
+1 1
+0 0
+.names A_22_.BLIF a_c_22__n
+1 1
+0 0
+.names A_23_.BLIF a_c_23__n
+1 1
+0 0
+.names A_24_.BLIF a_c_24__n
+1 1
+0 0
+.names A_25_.BLIF a_c_25__n
+1 1
+0 0
+.names A_26_.BLIF a_c_26__n
+1 1
+0 0
+.names A_27_.BLIF a_c_27__n
+1 1
+0 0
+.names A_28_.BLIF a_c_28__n
+1 1
+0 0
+.names A_29_.BLIF a_c_29__n
+1 1
+0 0
+.names A_30_.BLIF a_c_30__n
+1 1
+0 0
+.names A_31_.BLIF a_c_31__n
+1 1
+0 0
+.names A0.PIN.BLIF A0_c
+1 1
+0 0
+.names A1.BLIF A1_c
+1 1
+0 0
+.names nEXP_SPACE.BLIF nEXP_SPACE_c
+1 1
+0 0
+.names BERR.PIN.BLIF BERR_c
+1 1
+0 0
+.names BG_030.BLIF BG_030_c
+1 1
+0 0
+.names BGACK_000.BLIF BGACK_000_c
+1 1
+0 0
+.names CLK_030.BLIF CLK_030_c
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_OSZI_c
+1 1
+0 0
+.names FPU_SENSE.BLIF FPU_SENSE_c
+1 1
+0 0
+.names IPL_0_.BLIF ipl_c_0__n
+1 1
+0 0
+.names IPL_1_.BLIF ipl_c_1__n
+1 1
+0 0
+.names IPL_2_.BLIF ipl_c_2__n
+1 1
+0 0
+.names DTACK.BLIF DTACK_c
+1 1
+0 0
+.names VPA.BLIF VPA_c
+1 1
+0 0
+.names RST.BLIF RST_c
+1 1
+0 0
+.names RW.PIN.BLIF RW_c
+1 1
+0 0
+.names FC_0_.BLIF fc_c_0__n
+1 1
+0 0
+.names FC_1_.BLIF fc_c_1__n
+1 1
+0 0
+.names N_231.BLIF AS_030.OE
+1 1
+0 0
+.names N_230.BLIF AS_000.OE
+1 1
+0 0
+.names N_230.BLIF RW_000.OE
+1 1
+0 0
+.names N_230.BLIF UDS_000.OE
+1 1
+0 0
+.names N_230.BLIF LDS_000.OE
+1 1
+0 0
+.names un1_as_030_i.BLIF SIZE_0_.OE
+1 1
+0 0
+.names un1_as_030_i.BLIF SIZE_1_.OE
+1 1
+0 0
+.names N_231.BLIF A0.OE
+1 1
+0 0
+.names un22_berr.BLIF BERR.OE
+1 1
+0 0
+.names N_332.BLIF RW.OE
+1 1
+0 0
+.names N_231.BLIF DS_030.OE
+1 1
+0 0
+.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE
+1 1
+0 0
+.names RESET_OUT_i.BLIF RESET.OE
+1 1
+0 0
+.names N_61.BLIF CIIN.OE
+1 1
+0 0
+.end
diff --git a/Logic/68030_tk.bl3 b/Logic/68030_tk.bl3
new file mode 100644
index 0000000..404ce35
--- /dev/null
+++ b/Logic/68030_tk.bl3
@@ -0,0 +1,1245 @@
+#$ TOOL ispLEVER Classic 1.8.00.04.29.14
+#$ DATE Sun Jan 24 16:20:54 2016
+#$ MODULE 68030_tk
+#$ PINS 61 SIZE_1_ A_31_ IPL_030_2_ IPL_2_ IPL_030_1_ IPL_030_0_ FC_1_ IPL_1_ AS_030 \
+#  IPL_0_ AS_000 FC_0_ RW_000 DS_030 UDS_000 LDS_000 A0 A1 nEXP_SPACE BERR BG_030 BG_000 \
+#  BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE \
+#  DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR SIZE_0_ \
+#  AMIGA_BUS_ENABLE_LOW A_30_ AMIGA_BUS_ENABLE_HIGH A_29_ CIIN A_28_ A_27_ A_26_ A_25_ \
+#  A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_
+#$ NODES 81 inst_BGACK_030_INTreg inst_CLK_OUT_INTreg inst_VMA_INTreg cpu_est_0_ \
+#  cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AS_000_INT SM_AMIGA_5_ \
+#  inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg \
+#  inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA \
+#  CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT \
+#  inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT \
+#  inst_CLK_OUT_PRE_50 N_210_i inst_CLK_OUT_PRE_25 inst_CLK_000_D1 inst_CLK_000_D0 \
+#  inst_CLK_000_PE inst_CLK_OUT_EXP_INT CLK_000_P_SYNC_9_ inst_CLK_000_NE \
+#  CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ \
+#  inst_AMIGA_BUS_ENABLE_DMA_HIGH inst_DSACK1_INTreg SM_AMIGA_4_ inst_DS_000_ENABLE \
+#  RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ \
+#  CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ \
+#  CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ \
+#  CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ \
+#  CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ \
+#  CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ inst_RW_000_INT inst_RW_000_DMA inst_A0_DMA \
+#  SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ \
+#  BG_000DFFreg IPL_030DFF_0_reg IPL_030DFF_1_reg IPL_030DFF_2_reg
+.model bus68030
+.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
+BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \
+DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \
+A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
+A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \
+inst_BGACK_030_INTreg.BLIF inst_CLK_OUT_INTreg.BLIF inst_VMA_INTreg.BLIF \
+cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
+inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \
+inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \
+inst_BGACK_030_INT_D.BLIF inst_AS_000_DMA.BLIF inst_DS_000_DMA.BLIF \
+CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF \
+inst_VPA_D.BLIF inst_UDS_000_INT.BLIF inst_LDS_000_INT.BLIF \
+inst_CLK_OUT_PRE_D.BLIF inst_DTACK_D0.BLIF inst_RESET_OUT.BLIF \
+inst_CLK_OUT_PRE_50.BLIF N_210_i.BLIF inst_CLK_OUT_PRE_25.BLIF \
+inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF \
+inst_CLK_OUT_EXP_INT.BLIF CLK_000_P_SYNC_9_.BLIF inst_CLK_000_NE.BLIF \
+CLK_000_N_SYNC_11_.BLIF IPL_D0_0_.BLIF IPL_D0_1_.BLIF IPL_D0_2_.BLIF \
+inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \
+inst_DSACK1_INTreg.BLIF SM_AMIGA_4_.BLIF inst_DS_000_ENABLE.BLIF \
+RST_DLY_0_.BLIF RST_DLY_1_.BLIF RST_DLY_2_.BLIF CLK_000_P_SYNC_0_.BLIF \
+CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.BLIF \
+CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.BLIF \
+CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.BLIF CLK_000_N_SYNC_0_.BLIF \
+CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.BLIF \
+CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.BLIF \
+CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.BLIF \
+CLK_000_N_SYNC_10_.BLIF inst_RW_000_INT.BLIF inst_RW_000_DMA.BLIF \
+inst_A0_DMA.BLIF SM_AMIGA_6_.BLIF inst_CLK_030_H.BLIF SM_AMIGA_1_.BLIF \
+SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF SM_AMIGA_i_7_.BLIF BG_000DFFreg.BLIF \
+IPL_030DFF_0_reg.BLIF IPL_030DFF_1_reg.BLIF IPL_030DFF_2_reg.BLIF \
+AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF \
+LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF \
+RW.PIN.BLIF
+.outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \
+AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
+AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \
+SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \
+SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C \
+SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_2_.D \
+cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C \
+IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D IPL_030DFF_2_reg.C \
+IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C \
+CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \
+CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \
+CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \
+CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \
+CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \
+CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \
+SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \
+CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \
+CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C \
+CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.D \
+CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C \
+CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D \
+CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C \
+CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D \
+CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C \
+CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D \
+CLK_000_N_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \
+RST_DLY_2_.D RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C \
+inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_RW_000_DMA.D inst_RW_000_DMA.C \
+inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \
+inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \
+inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
+inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \
+inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \
+inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C \
+inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.D \
+inst_RESET_OUT.C inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C BG_000DFFreg.D \
+BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \
+inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \
+inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \
+inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \
+inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_NE.D \
+inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \
+inst_CLK_OUT_INTreg.D inst_CLK_OUT_INTreg.C inst_CLK_000_D1.D \
+inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \
+inst_CLK_OUT_EXP_INT.D inst_CLK_OUT_EXP_INT.C inst_CLK_OUT_PRE_D.D \
+inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D \
+inst_CLK_000_PE.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 LDS_000 A0 BERR RW \
+SIZE_0_ N_210_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE \
+SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE \
+inst_CLK_030_H.D.X1 inst_CLK_030_H.D.X2 SM_AMIGA_3_.D.X1 SM_AMIGA_3_.D.X2
+.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
+cpu_est_2_.BLIF cpu_est_3_.BLIF SM_AMIGA_5_.BLIF inst_VPA_D.BLIF \
+inst_DTACK_D0.BLIF N_210_i.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
+inst_CLK_000_NE_D0.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_6_.BLIF \
+SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF BERR.PIN.BLIF \
+SM_AMIGA_i_7_.D
+10000100-1--10000-0- 1
+100001-0-1-11000--0- 1
+10000100-11-10--0--- 1
+100001-0-11110------ 1
+1-----0101--10000-0- 1
+1------101-11000--0- 1
+1-----0--1---000000- 1
+1-----01011-10--0--- 1
+1--------1-1-000-00- 1
+1------1011110------ 1
+1-----0--11--0--00-- 1
+1--------111-0---0-- 1
+1--------10--------1 1
+1--------1---0-----1 1
+-------11--------1-0 0
+----------1--1------ 0
+-----0-0---------1-0 0
+----1--0---------1-0 0
+---1---0---------1-0 0
+--1----0---------1-0 0
+-1-----0---------1-0 0
+-----------0----1--0 0
+------1----0-------0 0
+----------0-------10 0
+----------0----1---0 0
+----------0---1----0 0
+------------0----1-0 0
+---------0---------- 0
+0------------------- 0
+-------------1-----0 0
+.names RST.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \
+inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF inst_CLK_000_PE.BLIF \
+SM_AMIGA_6_.BLIF SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF SM_AMIGA_6_.D
+11010--0- 1
+1----01-1 1
+1-----10- 1
+-----1-1- 0
+----1-0-- 0
+---0--0-- 0
+--1---0-- 0
+-0----0-- 0
+------01- 0
+0-------- 0
+-------10 0
+.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
+SM_AMIGA_6_.BLIF BERR.PIN.BLIF SM_AMIGA_5_.D
+101-1- 1
+11-0-1 1
+11--11 1
+---10- 0
+-00--- 0
+-0--0- 0
+-1---0 0
+0----- 0
+.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF \
+SM_AMIGA_4_.BLIF BERR.PIN.BLIF SM_AMIGA_4_.D
+1-0-11 1
+11-1-- 1
+11--1- 1
+---00- 0
+-01--- 0
+-0--0- 0
+0----- 0
+-0---0 0
+.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
+cpu_est_2_.BLIF cpu_est_3_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
+inst_CLK_000_PE.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF \
+BERR.PIN.BLIF SM_AMIGA_2_.D
+1000010--11-- 1
+1-----10-11-- 1
+1-------0--11 1
+1---------11- 1
+------11---0- 0
+--------1-0-- 0
+-----00----0- 0
+----1-0----0- 0
+---1--0----0- 0
+--1---0----0- 0
+-1----0----0- 0
+---------0-0- 0
+----------00- 0
+0------------ 0
+----------0-0 0
+.names RST.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF \
+SM_AMIGA_2_.BLIF BERR.PIN.BLIF SM_AMIGA_1_.D
+11-01- 1
+1-01-1 1
+1--111 1
+--1-0- 0
+-0-0-- 0
+---00- 0
+---1-0 0
+0----- 0
+.names RST.BLIF inst_CLK_000_PE.BLIF inst_CLK_000_NE.BLIF SM_AMIGA_0_.BLIF \
+SM_AMIGA_1_.BLIF BERR.PIN.BLIF SM_AMIGA_0_.D
+1-101- 1
+10-1-1 1
+-1-1-- 0
+---00- 0
+--00-- 0
+---1-0 0
+0----- 0
+.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF inst_CLK_000_NE_D0.BLIF \
+cpu_est_2_.D
+1101 1
+-01- 1
+0-1- 1
+--10 1
+1111 0
+-00- 0
+0-0- 0
+--00 0
+.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF \
+inst_CLK_000_NE_D0.BLIF cpu_est_3_.D
+111-1 1
+0--1- 1
+---10 1
+0--0- 0
+1-0-1 0
+10--1 0
+---00 0
+.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
+IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_0_reg.BLIF IPL_030DFF_0_reg.D
+0-01100- 1
+0-11110- 1
+1-01101- 1
+1-11111- 1
+1-----01 1
+0-----11 1
+--1--0-1 1
+--0--1-1 1
+---1---1 1
+----1--1 1
+-0------ 1
+0100000- 0
+0110010- 0
+1100001- 0
+1110011- 0
+11----00 0
+01----10 0
+-11--0-0 0
+-10--1-0 0
+-1--0--0 0
+-1-0---0 0
+.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
+IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_1_reg.BLIF IPL_030DFF_1_reg.D
+0-10010- 1
+0-11110- 1
+1-10011- 1
+1-11111- 1
+1-----01 1
+0-----11 1
+--1----1 1
+-----1-1 1
+---10--1 1
+---01--1 1
+-0------ 1
+0100000- 0
+0101100- 0
+1100001- 0
+1101101- 0
+11----00 0
+01----10 0
+-1-10--0 0
+-1-01--0 0
+-1---0-0 0
+-10----0 0
+.names IPL_2_.BLIF RST.BLIF IPL_1_.BLIF IPL_0_.BLIF IPL_D0_0_.BLIF \
+IPL_D0_1_.BLIF IPL_D0_2_.BLIF IPL_030DFF_2_reg.BLIF IPL_030DFF_2_reg.D
+1-00001- 1
+1-01101- 1
+1-10011- 1
+1-11111- 1
+1------1 1
+------11 1
+--1--0-1 1
+--0--1-1 1
+---10--1 1
+---01--1 1
+-0------ 1
+0100000- 0
+0101100- 0
+0110010- 0
+0111110- 0
+-11--0-0 0
+-10--1-0 0
+-1-10--0 0
+-1-01--0 0
+-1----00 0
+01-----0 0
+.names RST.BLIF IPL_0_.BLIF IPL_D0_0_.D
+0- 1
+-1 1
+10 0
+.names RST.BLIF IPL_1_.BLIF IPL_D0_1_.D
+0- 1
+-1 1
+10 0
+.names IPL_2_.BLIF RST.BLIF IPL_D0_2_.D
+1- 1
+-0 1
+01 0
+.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF \
+inst_CLK_000_PE.BLIF AS_000.PIN.BLIF CYCLE_DMA_0_.D
+10100 1
+10010 1
+--00- 0
+--11- 0
+-1--- 0
+0---- 0
+----1 0
+.names RST.BLIF inst_BGACK_030_INTreg.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \
+inst_CLK_000_PE.BLIF AS_000.PIN.BLIF CYCLE_DMA_1_.D
+101010 1
+10-100 1
+1001-0 1
+--111- 0
+---00- 0
+--00-- 0
+-1---- 0
+0----- 0
+-----1 0
+.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
+SIZE_DMA_0_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_0_.D
+-111-- 1
+-0--1- 1
+0----- 1
+-0---1 1
+10--00 0
+11-0-- 0
+110--- 0
+.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
+SIZE_DMA_1_.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF SIZE_DMA_1_.D
+-111-- 1
+-0--00 1
+0----- 1
+10--1- 0
+11-0-- 0
+110--- 0
+10---1 0
+.names cpu_est_0_.BLIF cpu_est_1_.BLIF cpu_est_3_.BLIF inst_CLK_000_NE_D0.BLIF \
+cpu_est_1_.D
+1001 1
+01-- 1
+-1-0 1
+-01- 0
+11-1 0
+00-- 0
+-0-0 0
+.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
+RST_DLY_2_.BLIF RST_DLY_0_.D
+1-111 1
+110-- 1
+101-- 1
+-110- 0
+-00-- 0
+-11-0 0
+0---- 0
+.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
+RST_DLY_2_.BLIF RST_DLY_1_.D
+1--11 1
+1110- 1
+1-01- 1
+10-1- 1
+-1110 0
+--00- 0
+-0-0- 0
+0---- 0
+.names RST.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF RST_DLY_1_.BLIF \
+RST_DLY_2_.BLIF RST_DLY_2_.D
+1111- 1
+1---1 1
+0---- 0
+---00 0
+--0-0 0
+-0--0 0
+.names inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF CLK_000_P_SYNC_0_.D
+01 1
+1- 0
+-0 0
+.names RST.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF inst_CLK_000_PE.BLIF \
+SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF inst_DS_000_ENABLE.BLIF SM_AMIGA_6_.BLIF \
+SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF RW.PIN.BLIF inst_DS_000_ENABLE.D
+10--00-01-- 1
+10-10--01-- 1
+1-0---1--1- 1
+1---00-01-1 1
+1--10--01-1 1
+---0-1---0- 0
+---0-10---- 0
+--10-1----- 0
+-1-------00 0
+-1----0---0 0
+-11-------0 0
+--------00- 0
+-------1-0- 0
+----1----0- 0
+------0-0-- 0
+--1-----0-- 0
+------01--- 0
+--1----1--- 0
+----1-0---- 0
+--1-1------ 0
+0---------- 0
+.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
+inst_RW_000_DMA.BLIF RW_000.PIN.BLIF inst_RW_000_DMA.D
+-1-1- 1
+-10-- 1
+0---- 1
+-0--1 1
+1110- 0
+10--0 0
+.names RST.BLIF SM_AMIGA_5_.BLIF inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF \
+inst_RW_000_INT.BLIF SM_AMIGA_i_7_.BLIF RW.PIN.BLIF inst_RW_000_INT.D
+-0--1-- 1
+-011--- 1
+-0---0- 1
+0------ 1
+-1----1 1
+10-001- 0
+100-01- 0
+11----0 0
+.names RST.BLIF inst_LDS_000_INT.BLIF SM_AMIGA_6_.BLIF SIZE_0_.PIN.BLIF \
+SIZE_1_.PIN.BLIF A0.PIN.BLIF inst_LDS_000_INT.D
+--1100 1
+-10--- 1
+0----- 1
+100--- 0
+1-1-1- 0
+1-10-- 0
+1-1--1 0
+.names BGACK_000.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_000_PE.BLIF \
+AS_000.PIN.BLIF inst_BGACK_030_INTreg.D
+1-1-- 1
+1--11 1
+-0--- 1
+-100- 0
+-10-0 0
+01--- 0
+.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
+CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF AS_000.PIN.BLIF UDS_000.PIN.BLIF \
+LDS_000.PIN.BLIF inst_AS_000_DMA.D
+----00--- 1
+----11--- 1
+0--1----- 1
+------1-- 1
+--1------ 1
+-0------- 1
+-------11 1
+-1001000- 0
+110-1000- 0
+-1000100- 0
+110-0100- 0
+-100100-0 0
+110-100-0 0
+-100010-0 0
+110-010-0 0
+.names FC_1_.BLIF RST.BLIF A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF \
+FC_0_.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_030_D0.BLIF \
+inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF inst_BGACK_030_INT_D.BLIF \
+SM_AMIGA_i_7_.BLIF BERR.PIN.BLIF inst_AS_030_000_SYNC.D
+1-00101---1--- 1
+----------1-1- 1
+----------10-- 1
+---------01--- 1
+-------0--1--- 1
+--------1----- 1
+-0------------ 1
+-------------0 1
+-1----0101-101 0
+-1---1-101-101 0
+-1--0--101-101 0
+-1-1---101-101 0
+-11----101-101 0
+01-----101-101 0
+-1------0-0--1 0
+.names RST.BLIF inst_AS_000_INT.BLIF SM_AMIGA_5_.BLIF inst_AS_030_D0.BLIF \
+BERR.PIN.BLIF inst_AS_000_INT.D
+-10-- 1
+--01- 1
+0---- 1
+--0-0 1
+10-01 0
+1-1-- 0
+.names CLK_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_CLK_OUT_PRE_D.BLIF \
+inst_DSACK1_INTreg.BLIF CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.BLIF \
+SM_AMIGA_1_.BLIF BERR.PIN.BLIF inst_DSACK1_INTreg.D
+1--01-0-- 1
+----100-- 1
+1-10--0-- 1
+1--0--0-0 1
+----1--0- 1
+--1--00-- 1
+-----00-0 1
+--1----0- 1
+-0------- 1
+-------00 1
+-10-0---1 0
+-1-1-1-1- 0
+01---1-1- 0
+-1----11- 0
+.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
+inst_DS_000_DMA.BLIF CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF \
+AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF LDS_000.PIN.BLIF \
+inst_DS_000_DMA.D
+1--1---1-0-- 1
+----1--0-0-- 1
+0---1----0-- 1
+-----00----- 1
+-----11----- 1
+--------1--- 1
+--1--------- 1
+-0---------- 1
+----------11 1
+1100-1010-0- 0
+1100-0110-0- 0
+1100-1010--0 0
+1100-0110--0 0
+-10-01000-0- 0
+-10-00100-0- 0
+010-010-0-0- 0
+010-001-0-0- 0
+-10-01000--0 0
+-10-00100--0 0
+010-010-0--0 0
+010-001-0--0 0
+-10--10-010- 0
+-10--01-010- 0
+-10--10-01-0 0
+-10--01-01-0 0
+.names RST.BLIF AS_030.PIN.BLIF inst_AS_030_D0.D
+0- 1
+-1 1
+10 0
+.names nEXP_SPACE.BLIF RST.BLIF inst_nEXP_SPACE_D0reg.D
+1- 1
+-0 1
+01 0
+.names VPA.BLIF RST.BLIF inst_VPA_D.D
+1- 1
+-0 1
+01 0
+.names DTACK.BLIF RST.BLIF inst_DTACK_D0.D
+1- 1
+-0 1
+01 0
+.names RST.BLIF inst_RESET_OUT.BLIF inst_CLK_000_NE.BLIF RST_DLY_0_.BLIF \
+RST_DLY_1_.BLIF RST_DLY_2_.BLIF inst_RESET_OUT.D
+1-1111 1
+11---- 1
+-0--0- 0
+-0-0-- 0
+-00--- 0
+0----- 0
+-0---0 0
+.names BG_030.BLIF RST.BLIF inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF \
+inst_CLK_000_D0.BLIF BG_000DFFreg.BLIF BG_000DFFreg.D
+----01 1
+---0-1 1
+--0--1 1
+-0---- 1
+1----- 1
+01111- 0
+01---0 0
+.names A1.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
+inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D
+--1-1 1
+1-0-- 1
+--10- 1
+-0--- 1
+-1110 0
+010-- 0
+.names A1.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF \
+inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF inst_BGACK_030_INT_D.BLIF \
+inst_AMIGA_BUS_ENABLE_DMA_LOW.D
+--11- 1
+0-0-- 1
+--1-0 1
+-0--- 1
+-1101 0
+110-- 0
+.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
+cpu_est_2_.BLIF cpu_est_3_.BLIF inst_VPA_D.BLIF inst_CLK_000_PE.BLIF \
+inst_CLK_000_NE.BLIF inst_VMA_INTreg.D
+--0000-1- 1
+-1----1-- 1
+-1-0----- 1
+-10------ 1
+-1------0 1
+0-------- 1
+-1---1--- 1
+-1--1---- 1
+1-11000-1 0
+10-----0- 0
+10---1--- 0
+10--1---- 0
+10-1----- 0
+101------ 0
+.names RST.BLIF inst_UDS_000_INT.BLIF SM_AMIGA_6_.BLIF A0.PIN.BLIF \
+inst_UDS_000_INT.D
+-10- 1
+0--- 1
+--11 1
+100- 0
+1-10 0
+.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF \
+inst_A0_DMA.BLIF UDS_000.PIN.BLIF inst_A0_DMA.D
+-111- 1
+0---- 1
+-0--1 1
+11-0- 0
+110-- 0
+10--0 0
+.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.D
+0- 1
+-1 1
+10 0
+.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
+0 1
+1 0
+.names SM_AMIGA_5_.BLIF inst_nEXP_SPACE_D0reg.BLIF inst_AS_030_000_SYNC.BLIF \
+inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF SM_AMIGA_0_.BLIF SM_AMIGA_4_.BLIF \
+SM_AMIGA_6_.BLIF SM_AMIGA_1_.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_2_.BLIF N_210_i
+-1010------ 1
+---------1- 1
+--------1-- 1
+-------1--- 1
+------1---- 1
+-----1----- 1
+1---------- 1
+----------1 1
+0---1000000 0
+0--0-000000 0
+0-1--000000 0
+00---000000 0
+.names IPL_030DFF_2_reg.BLIF IPL_030_2_
+1 1
+0 0
+.names inst_DS_000_DMA.BLIF AS_000.PIN.BLIF DS_030
+1- 1
+-1 1
+00 0
+.names BG_000DFFreg.BLIF BG_000
+1 1
+0 0
+.names inst_BGACK_030_INTreg.BLIF BGACK_030
+1 1
+0 0
+.names inst_CLK_OUT_INTreg.BLIF CLK_DIV_OUT
+1 1
+0 0
+.names inst_CLK_OUT_EXP_INT.BLIF CLK_EXP
+0 1
+1 0
+.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_19_.BLIF A_18_.BLIF \
+A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF FPU_CS
+-------0- 1
+------1-- 1
+-----0--- 1
+----1---- 1
+---1----- 1
+--1------ 1
+-0------- 1
+0-------- 1
+--------1 1
+110001010 0
+.names inst_DSACK1_INTreg.BLIF DSACK1
+1 1
+0 0
+.names AVEC
+ 1
+.names cpu_est_1_.BLIF cpu_est_2_.BLIF cpu_est_3_.BLIF E
+110 1
+001 1
+-00 0
+1-1 0
+01- 0
+.names inst_VMA_INTreg.BLIF VMA
+1 1
+0 0
+.names RESET
+ 0
+.names AMIGA_ADDR_ENABLE
+ 0
+.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF AS_000.PIN.BLIF \
+RW_000.PIN.BLIF AMIGA_BUS_DATA_DIR
+0001 1
+1--0 1
+-1-1 0
+--11 0
+0--0 0
+1--1 0
+.names inst_BGACK_030_INTreg.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF \
+AMIGA_BUS_ENABLE_LOW
+1- 1
+-1 1
+00 0
+.names inst_BGACK_030_INTreg.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF \
+SM_AMIGA_i_7_.BLIF AMIGA_BUS_ENABLE_HIGH
+01- 1
+1-0 1
+00- 0
+1-1 0
+.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
+A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
+inst_AS_030_D0.BLIF CIIN
+0000000011110 1
+-----------0- 0
+----------0-- 0
+---------0--- 0
+--------0---- 0
+-------1----- 0
+------1------ 0
+-----1------- 0
+----1-------- 0
+---1--------- 0
+--1---------- 0
+-1----------- 0
+1------------ 0
+------------1 0
+.names IPL_030DFF_1_reg.BLIF IPL_030_1_
+1 1
+0 0
+.names IPL_030DFF_0_reg.BLIF IPL_030_0_
+1 1
+0 0
+.names CLK_OSZI.BLIF SM_AMIGA_i_7_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF SM_AMIGA_6_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF SM_AMIGA_5_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF SM_AMIGA_4_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF SM_AMIGA_3_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF SM_AMIGA_2_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF SM_AMIGA_1_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF SM_AMIGA_0_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF cpu_est_2_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF cpu_est_3_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF IPL_030DFF_0_reg.C
+1 1
+0 0
+.names CLK_OSZI.BLIF IPL_030DFF_1_reg.C
+1 1
+0 0
+.names CLK_OSZI.BLIF IPL_030DFF_2_reg.C
+1 1
+0 0
+.names CLK_OSZI.BLIF IPL_D0_0_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF IPL_D0_1_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF IPL_D0_2_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_5_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_6_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_7_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_8_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_9_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_10_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_11_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF CYCLE_DMA_0_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF CYCLE_DMA_1_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF SIZE_DMA_0_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF SIZE_DMA_1_.C
+1 1
+0 0
+.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_.D
+10 1
+01 1
+00 0
+11 0
+.names CLK_OSZI.BLIF cpu_est_0_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF cpu_est_1_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_P_SYNC_1_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_P_SYNC_2_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_P_SYNC_3_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_P_SYNC_4_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_P_SYNC_5_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_P_SYNC_6_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_P_SYNC_7_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_P_SYNC_8_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_P_SYNC_9_.C
+1 1
+0 0
+.names inst_CLK_000_D1.BLIF inst_CLK_000_D0.BLIF CLK_000_N_SYNC_0_.D
+10 1
+0- 0
+-1 0
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_0_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_1_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_2_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_3_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_N_SYNC_4_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF RST_DLY_0_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF RST_DLY_1_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF RST_DLY_2_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_000_P_SYNC_0_.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_DS_000_ENABLE.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_RW_000_DMA.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_RW_000_INT.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_LDS_000_INT.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_BGACK_030_INTreg.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_AS_000_DMA.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_AS_030_000_SYNC.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_AS_000_INT.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_DSACK1_INTreg.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_DS_000_DMA.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_AS_030_D0.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_nEXP_SPACE_D0reg.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_VPA_D.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_DTACK_D0.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_CLK_030_H.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_RESET_OUT.C
+1 1
+0 0
+.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_25.D
+10 1
+01 1
+00 0
+11 0
+.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_25.C
+1 1
+0 0
+.names CLK_OSZI.BLIF BG_000DFFreg.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_VMA_INTreg.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_UDS_000_INT.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_A0_DMA.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_BGACK_030_INT_D.C
+1 1
+0 0
+.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_CLK_000_NE.C
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_50.C
+1 1
+0 0
+.names inst_CLK_OUT_PRE_D.BLIF inst_CLK_OUT_INTreg.D
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_CLK_OUT_INTreg.C
+1 1
+0 0
+.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_CLK_000_D1.C
+1 1
+0 0
+.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_CLK_000_NE_D0.C
+1 1
+0 0
+.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_EXP_INT.D
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_CLK_OUT_EXP_INT.C
+1 1
+0 0
+.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_D.D
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_CLK_OUT_PRE_D.C
+1 1
+0 0
+.names CLK_000.BLIF inst_CLK_000_D0.D
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_CLK_000_D0.C
+1 1
+0 0
+.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D
+1 1
+0 0
+.names CLK_OSZI.BLIF inst_CLK_000_PE.C
+1 1
+0 0
+.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_1_
+01 1
+1- 0
+-0 0
+.names inst_AS_000_DMA.BLIF AS_000.PIN.BLIF AS_030
+1- 1
+-1 1
+00 0
+.names inst_AS_000_INT.BLIF AS_030.PIN.BLIF AS_000
+1- 1
+-1 1
+00 0
+.names inst_RW_000_INT.BLIF RW_000
+1 1
+0 0
+.names inst_UDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF UDS_000
+1- 1
+-0 1
+01 0
+.names inst_LDS_000_INT.BLIF inst_DS_000_ENABLE.BLIF LDS_000
+1- 1
+-0 1
+01 0
+.names inst_A0_DMA.BLIF A0
+1 1
+0 0
+.names BERR
+ 0
+.names inst_RW_000_DMA.BLIF RW
+1 1
+0 0
+.names SIZE_DMA_0_.BLIF SIZE_DMA_1_.BLIF SIZE_0_
+10 1
+0- 0
+-1 0
+.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF \
+inst_RESET_OUT.BLIF AS_030.OE
+001 1
+-1- 0
+1-- 0
+--0 0
+.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF AS_000.OE
+11 1
+0- 0
+-0 0
+.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF RW_000.OE
+11 1
+0- 0
+-0 0
+.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF UDS_000.OE
+11 1
+0- 0
+-0 0
+.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF LDS_000.OE
+11 1
+0- 0
+-0 0
+.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF SIZE_0_.OE
+00 1
+1- 0
+-1 0
+.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF SIZE_1_.OE
+00 1
+1- 0
+-1 0
+.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF \
+inst_RESET_OUT.BLIF A0.OE
+001 1
+-1- 0
+1-- 0
+--0 0
+.names FC_1_.BLIF BGACK_000.BLIF FPU_SENSE.BLIF A_19_.BLIF A_18_.BLIF \
+A_17_.BLIF A_16_.BLIF FC_0_.BLIF AS_030.PIN.BLIF BERR.OE
+111001010 1
+-------0- 0
+------1-- 0
+-----0--- 0
+----1---- 0
+---1----- 0
+--0------ 0
+-0------- 0
+0-------- 0
+--------1 0
+.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF RW.OE
+01 1
+1- 0
+-0 0
+.names inst_BGACK_030_INTreg.BLIF inst_nEXP_SPACE_D0reg.BLIF \
+inst_RESET_OUT.BLIF DS_030.OE
+001 1
+-1- 0
+1-- 0
+--0 0
+.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE
+1 1
+0 0
+.names inst_RESET_OUT.BLIF RESET.OE
+0 1
+1 0
+.names A_31_.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF A_26_.BLIF \
+A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
+inst_AS_030_D0.BLIF inst_nEXP_SPACE_D0reg.BLIF CIIN.OE
+0000000011110- 1
+-------------1 1
+------------10 0
+-----------0-0 0
+----------0--0 0
+---------0---0 0
+--------0----0 0
+-------1-----0 0
+------1------0 0
+-----1-------0 0
+----1--------0 0
+---1---------0 0
+--1----------0 0
+-1-----------0 0
+1------------0 0
+.names RST.BLIF inst_BGACK_030_INTreg.BLIF inst_CLK_030_H.D.X1
+10 1
+0- 0
+-1 0
+.names CLK_030.BLIF RST.BLIF inst_BGACK_030_INTreg.BLIF inst_AS_000_DMA.BLIF \
+CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF inst_CLK_030_H.BLIF AS_000.PIN.BLIF \
+UDS_000.PIN.BLIF LDS_000.PIN.BLIF inst_CLK_030_H.D.X2
+-10-00---- 1
+-10----1-- 1
+110---0--- 1
+-101--0--- 1
+-10-----11 1
+-10-11---- 1
+-0-------- 0
+--1------- 0
+----01100- 0
+----10100- 0
+----0110-0 0
+----1010-0 0
+0--001-00- 0
+0--010-00- 0
+0--001-0-0 0
+0--010-0-0 0
+.names RST.BLIF SM_AMIGA_3_.BLIF SM_AMIGA_3_.D.X1
+11 1
+0- 0
+-0 0
+.names RST.BLIF inst_VMA_INTreg.BLIF cpu_est_0_.BLIF cpu_est_1_.BLIF \
+cpu_est_2_.BLIF cpu_est_3_.BLIF inst_VPA_D.BLIF inst_DTACK_D0.BLIF \
+inst_CLK_000_PE.BLIF inst_CLK_000_NE_D0.BLIF SM_AMIGA_4_.BLIF SM_AMIGA_3_.BLIF \
+BERR.PIN.BLIF SM_AMIGA_3_.D.X2
+1-------1-10- 1
+1----------10 1
+1000010--101- 1
+1-----10-101- 1
+0------------ 0
+--------0--0- 0
+----------00- 0
+---------0-11 0
+----------111 0
+-1----0----11 0
+--1---0----11 0
+---1--0----11 0
+----1-0----11 0
+-----00----11 0
+------11---11 0
+.end
diff --git a/Logic/68030_tk.crf b/Logic/68030_tk.crf
index 243eaa6..2bc3d13 100644
--- a/Logic/68030_tk.crf
+++ b/Logic/68030_tk.crf
@@ -1,7 +1,7 @@
 // Signal Name Cross Reference File
 // ispLEVER Classic 1.8.00.04.29.14
 
-// Design '68030_tk' created Sat Oct 10 21:59:48 2015
+// Design '68030_tk' created Sun Jan 24 16:20:54 2016
 
 
 // LEGEND:  '>'  Functional Block Port Separator
diff --git a/Logic/68030_tk.d0 b/Logic/68030_tk.d0
new file mode 100644
index 0000000..0541d3b
--- /dev/null
+++ b/Logic/68030_tk.d0
@@ -0,0 +1 @@
+ -dev mach4a_DT_NCE  -clust 5
diff --git a/Logic/68030_tk.eq3 b/Logic/68030_tk.eq3
new file mode 100644
index 0000000..a9568d1
--- /dev/null
+++ b/Logic/68030_tk.eq3
@@ -0,0 +1,739 @@
+ ispLEVER Classic 1.8.00.04.29.14 Linked Equations File
+Copyright(C), 1992-2014, Lattice Semiconductor Corp.
+All Rights Reserved.
+
+Design bus68030 created  Sun Jan 24 16:20:54 2016
+
+
+ P-Terms   Fan-in  Fan-out  Type  Name (attributes)
+---------  ------  -------  ----  -----------------
+   1          2        1    Pin   SIZE_1_ 
+   1          2        1    Pin   SIZE_1_.OE 
+   1          2        1    Pin   AS_030- 
+   1          3        1    Pin   AS_030.OE 
+   1          2        1    Pin   AS_000- 
+   1          2        1    Pin   AS_000.OE 
+   1          2        1    Pin   DS_030- 
+   1          3        1    Pin   DS_030.OE 
+   1          2        1    Pin   UDS_000- 
+   1          2        1    Pin   UDS_000.OE 
+   1          2        1    Pin   LDS_000- 
+   1          2        1    Pin   LDS_000.OE 
+   0          0        1    Pin   BERR 
+   1          9        1    Pin   BERR.OE 
+   1          1        1    Pin   CLK_EXP 
+   1          9        1    Pin   FPU_CS- 
+   1          0        1    Pin   AVEC 
+   2          3        1    Pin   E 
+   0          0        1    Pin   RESET 
+   1          1        1    Pin   RESET.OE 
+   0          0        1    Pin   AMIGA_ADDR_ENABLE 
+   2          4        1    Pin   AMIGA_BUS_DATA_DIR 
+   1          2        1    Pin   SIZE_0_ 
+   1          2        1    Pin   SIZE_0_.OE 
+   1          2        1    Pin   AMIGA_BUS_ENABLE_LOW- 
+   2          3        1    Pin   AMIGA_BUS_ENABLE_HIGH 
+   1         13        1    Pin   CIIN 
+   1          1        1    Pin   CIIN.OE 
+  10          8        1    Pin   IPL_030_2_.D- 
+   1          1        1    Pin   IPL_030_2_.C 
+  10          8        1    Pin   IPL_030_1_.D- 
+   1          1        1    Pin   IPL_030_1_.C 
+  10          8        1    Pin   IPL_030_0_.D- 
+   1          1        1    Pin   IPL_030_0_.C 
+   1          2        1    Pin   RW_000.OE 
+   3          7        1    Pin   RW_000.D- 
+   1          1        1    Pin   RW_000.C 
+   1          3        1    Pin   A0.OE 
+   3          5        1    Pin   A0.D 
+   1          1        1    Pin   A0.C 
+   2          6        1    Pin   BG_000.D- 
+   1          1        1    Pin   BG_000.C 
+   3          5        1    Pin   BGACK_030.D 
+   1          1        1    Pin   BGACK_030.C 
+   1          1        1    Pin   CLK_DIV_OUT.D 
+   1          1        1    Pin   CLK_DIV_OUT.C 
+   1          1        1    Pin   DSACK1.OE 
+   4          9        1    Pin   DSACK1.D- 
+   1          1        1    Pin   DSACK1.C 
+   3          9        1    Pin   VMA.T 
+   1          1        1    Pin   VMA.C 
+   1          2        1    Pin   RW.OE 
+   2          5        1    Pin   RW.D- 
+   1          1        1    Pin   RW.C 
+   2          2        1    Node  cpu_est_0_.D 
+   1          1        1    Node  cpu_est_0_.C 
+   3          4        1    Node  cpu_est_1_.D 
+   1          1        1    Node  cpu_est_1_.C 
+   4          4        1    Node  cpu_est_2_.D 
+   1          1        1    Node  cpu_est_2_.C 
+   3          5        1    Node  cpu_est_3_.D 
+   1          1        1    Node  cpu_est_3_.C 
+   2          5        1    Node  inst_AS_000_INT.D- 
+   1          1        1    Node  inst_AS_000_INT.C 
+   3          6        1    Node  SM_AMIGA_5_.D 
+   1          1        1    Node  SM_AMIGA_5_.C 
+   2          5        1    Node  inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 
+   1          1        1    Node  inst_AMIGA_BUS_ENABLE_DMA_LOW.C 
+   1          2        1    Node  inst_AS_030_D0.D- 
+   1          1        1    Node  inst_AS_030_D0.C 
+   1          2        1    Node  inst_nEXP_SPACE_D0reg.D- 
+   1          1        1    Node  inst_nEXP_SPACE_D0reg.C 
+   7         14        1    Node  inst_AS_030_000_SYNC.D- 
+   1          1        1    Node  inst_AS_030_000_SYNC.C 
+   1          2        1    Node  inst_BGACK_030_INT_D.D- 
+   1          1        1    Node  inst_BGACK_030_INT_D.C 
+   7          9        1    Node  inst_AS_000_DMA.D 
+   1          1        1    Node  inst_AS_000_DMA.C 
+   9         12        1    Node  inst_DS_000_DMA.D 
+   1          1        1    Node  inst_DS_000_DMA.C 
+   2          5        1    Node  CYCLE_DMA_0_.D 
+   1          1        1    Node  CYCLE_DMA_0_.C 
+   3          6        1    Node  CYCLE_DMA_1_.D 
+   1          1        1    Node  CYCLE_DMA_1_.C 
+   3          6        1    Node  SIZE_DMA_0_.D- 
+   1          1        1    Node  SIZE_DMA_0_.C 
+   3          6        1    Node  SIZE_DMA_1_.D 
+   1          1        1    Node  SIZE_DMA_1_.C 
+   1          2        1    Node  inst_VPA_D.D- 
+   1          1        1    Node  inst_VPA_D.C 
+   2          4        1    Node  inst_UDS_000_INT.D- 
+   1          1        1    Node  inst_UDS_000_INT.C 
+   3          6        1    Node  inst_LDS_000_INT.D 
+   1          1        1    Node  inst_LDS_000_INT.C 
+   1          1        1    Node  inst_CLK_OUT_PRE_D.D 
+   1          1        1    Node  inst_CLK_OUT_PRE_D.C 
+   1          2        1    Node  inst_DTACK_D0.D- 
+   1          1        1    Node  inst_DTACK_D0.C 
+   2          6        1    Node  inst_RESET_OUT.D 
+   1          1        1    Node  inst_RESET_OUT.C 
+   1          1        1    Node  inst_CLK_OUT_PRE_50.D 
+   1          1        1    Node  inst_CLK_OUT_PRE_50.C 
+   4         11        1    Node  N_210_i- 
+   2          2        1    Node  inst_CLK_OUT_PRE_25.D 
+   1          1        1    Node  inst_CLK_OUT_PRE_25.C 
+   1          1        1    Node  inst_CLK_000_D1.D 
+   1          1        1    Node  inst_CLK_000_D1.C 
+   1          1        1    Node  inst_CLK_000_D0.D 
+   1          1        1    Node  inst_CLK_000_D0.C 
+   1          1        1    Node  inst_CLK_000_PE.D 
+   1          1        1    Node  inst_CLK_000_PE.C 
+   1          1        1    Node  inst_CLK_OUT_EXP_INT.D 
+   1          1        1    Node  inst_CLK_OUT_EXP_INT.C 
+   1          1        1    Node  CLK_000_P_SYNC_9_.D 
+   1          1        1    Node  CLK_000_P_SYNC_9_.C 
+   1          1        1    Node  inst_CLK_000_NE.D 
+   1          1        1    Node  inst_CLK_000_NE.C 
+   1          1        1    Node  CLK_000_N_SYNC_11_.D 
+   1          1        1    Node  CLK_000_N_SYNC_11_.C 
+   1          2        1    Node  IPL_D0_0_.D- 
+   1          1        1    Node  IPL_D0_0_.C 
+   1          2        1    Node  IPL_D0_1_.D- 
+   1          1        1    Node  IPL_D0_1_.C 
+   1          2        1    Node  IPL_D0_2_.D- 
+   1          1        1    Node  IPL_D0_2_.C 
+   1          1        1    Node  inst_CLK_000_NE_D0.D 
+   1          1        1    Node  inst_CLK_000_NE_D0.C 
+   2          6        1    Node  SM_AMIGA_0_.D 
+   1          1        1    Node  SM_AMIGA_0_.C 
+   2          5        1    Node  inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- 
+   1          1        1    Node  inst_AMIGA_BUS_ENABLE_DMA_HIGH.C 
+   3          6        1    Node  SM_AMIGA_4_.D 
+   1          1        1    Node  SM_AMIGA_4_.C 
+   5         11        1    Node  inst_DS_000_ENABLE.D 
+   1          1        1    Node  inst_DS_000_ENABLE.C 
+   3          5        1    Node  RST_DLY_0_.D 
+   1          1        1    Node  RST_DLY_0_.C 
+   4          5        1    Node  RST_DLY_1_.D 
+   1          1        1    Node  RST_DLY_1_.C 
+   2          5        1    Node  RST_DLY_2_.D 
+   1          1        1    Node  RST_DLY_2_.C 
+   1          2        1    Node  CLK_000_P_SYNC_0_.D 
+   1          1        1    Node  CLK_000_P_SYNC_0_.C 
+   1          1        1    Node  CLK_000_P_SYNC_1_.D 
+   1          1        1    Node  CLK_000_P_SYNC_1_.C 
+   1          1        1    Node  CLK_000_P_SYNC_2_.D 
+   1          1        1    Node  CLK_000_P_SYNC_2_.C 
+   1          1        1    Node  CLK_000_P_SYNC_3_.D 
+   1          1        1    Node  CLK_000_P_SYNC_3_.C 
+   1          1        1    Node  CLK_000_P_SYNC_4_.D 
+   1          1        1    Node  CLK_000_P_SYNC_4_.C 
+   1          1        1    Node  CLK_000_P_SYNC_5_.D 
+   1          1        1    Node  CLK_000_P_SYNC_5_.C 
+   1          1        1    Node  CLK_000_P_SYNC_6_.D 
+   1          1        1    Node  CLK_000_P_SYNC_6_.C 
+   1          1        1    Node  CLK_000_P_SYNC_7_.D 
+   1          1        1    Node  CLK_000_P_SYNC_7_.C 
+   1          1        1    Node  CLK_000_P_SYNC_8_.D 
+   1          1        1    Node  CLK_000_P_SYNC_8_.C 
+   1          2        1    Node  CLK_000_N_SYNC_0_.D 
+   1          1        1    Node  CLK_000_N_SYNC_0_.C 
+   1          1        1    Node  CLK_000_N_SYNC_1_.D 
+   1          1        1    Node  CLK_000_N_SYNC_1_.C 
+   1          1        1    Node  CLK_000_N_SYNC_2_.D 
+   1          1        1    Node  CLK_000_N_SYNC_2_.C 
+   1          1        1    Node  CLK_000_N_SYNC_3_.D 
+   1          1        1    Node  CLK_000_N_SYNC_3_.C 
+   1          1        1    Node  CLK_000_N_SYNC_4_.D 
+   1          1        1    Node  CLK_000_N_SYNC_4_.C 
+   1          1        1    Node  CLK_000_N_SYNC_5_.D 
+   1          1        1    Node  CLK_000_N_SYNC_5_.C 
+   1          1        1    Node  CLK_000_N_SYNC_6_.D 
+   1          1        1    Node  CLK_000_N_SYNC_6_.C 
+   1          1        1    Node  CLK_000_N_SYNC_7_.D 
+   1          1        1    Node  CLK_000_N_SYNC_7_.C 
+   1          1        1    Node  CLK_000_N_SYNC_8_.D 
+   1          1        1    Node  CLK_000_N_SYNC_8_.C 
+   1          1        1    Node  CLK_000_N_SYNC_9_.D 
+   1          1        1    Node  CLK_000_N_SYNC_9_.C 
+   1          1        1    Node  CLK_000_N_SYNC_10_.D 
+   1          1        1    Node  CLK_000_N_SYNC_10_.C 
+   3          9        1    Node  SM_AMIGA_6_.D 
+   1          1        1    Node  SM_AMIGA_6_.C 
+   8         10        1    Node  inst_CLK_030_H.D 
+   1          1        1    Node  inst_CLK_030_H.C 
+   3          6        1    Node  SM_AMIGA_1_.D 
+   1          1        1    Node  SM_AMIGA_1_.C 
+   5         13        1    Node  SM_AMIGA_3_.T 
+   1          1        1    Node  SM_AMIGA_3_.C 
+   4         13        1    Node  SM_AMIGA_2_.D 
+   1          1        1    Node  SM_AMIGA_2_.C 
+  14         20        1    Node  SM_AMIGA_i_7_.D 
+   1          1        1    Node  SM_AMIGA_i_7_.C 
+   2         14        1    Node  CIIN_0 
+=========
+ 327                 P-Term Total: 327
+                       Total Pins: 61
+                      Total Nodes: 71
+            Average P-Term/Output: 2
+
+
+Equations:
+
+SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);
+
+SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
+
+!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN);
+
+AS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q);
+
+!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);
+
+AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
+
+!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN);
+
+DS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q);
+
+!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q);
+
+UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
+
+!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q);
+
+LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
+
+BERR = (0);
+
+BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
+
+CLK_EXP = (!inst_CLK_OUT_EXP_INT.Q);
+
+!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
+
+AVEC = (1);
+
+E = (!cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q
+     # cpu_est_1_.Q & cpu_est_2_.Q & !cpu_est_3_.Q);
+
+RESET = (0);
+
+RESET.OE = (!inst_RESET_OUT.Q);
+
+AMIGA_ADDR_ENABLE = (0);
+
+AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
+     # !BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & !AS_000.PIN & RW_000.PIN);
+
+SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
+
+SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
+
+!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q);
+
+AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q
+     # BGACK_030.Q & !SM_AMIGA_i_7_.Q);
+
+CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
+
+CIIN.OE = (CIIN_0);
+
+!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q
+     # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q
+     # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q
+     # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q
+     # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q
+     # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q
+     # !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
+     # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
+     # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
+     # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
+
+IPL_030_2_.C = (CLK_OSZI);
+
+!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q
+     # RST & !IPL_D0_1_.Q & !IPL_030_1_.Q
+     # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q
+     # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q
+     # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q
+     # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q
+     # IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
+     # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
+     # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
+     # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
+
+IPL_030_1_.C = (CLK_OSZI);
+
+!IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q
+     # RST & !IPL_D0_0_.Q & !IPL_030_0_.Q
+     # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q
+     # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q
+     # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q
+     # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q
+     # IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q
+     # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
+     # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
+     # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
+
+IPL_030_0_.C = (CLK_OSZI);
+
+RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
+
+!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN
+     # RST & !SM_AMIGA_5_.Q & !inst_CLK_000_PE.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
+     # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q);
+
+RW_000.C = (CLK_OSZI);
+
+A0.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q);
+
+A0.D = (!RST
+     # !BGACK_030.Q & UDS_000.PIN
+     # BGACK_030.Q & inst_BGACK_030_INT_D.Q & A0.Q);
+
+A0.C = (CLK_OSZI);
+
+!BG_000.D = (!BG_030 & RST & !BG_000.Q
+     # !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_CLK_000_D0.Q);
+
+BG_000.C = (CLK_OSZI);
+
+BGACK_030.D = (!RST
+     # BGACK_000 & BGACK_030.Q
+     # BGACK_000 & inst_CLK_000_PE.Q & AS_000.PIN);
+
+BGACK_030.C = (CLK_OSZI);
+
+CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
+
+CLK_DIV_OUT.C = (CLK_OSZI);
+
+DSACK1.OE = (inst_nEXP_SPACE_D0reg.Q);
+
+!DSACK1.D = (RST & CLK_000_N_SYNC_10_.Q & SM_AMIGA_1_.Q
+     # !CLK_030 & RST & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
+     # RST & inst_CLK_OUT_PRE_D.Q & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
+     # RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN);
+
+DSACK1.C = (CLK_OSZI);
+
+VMA.T = (!RST & !VMA.Q
+     # !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & inst_CLK_000_PE.Q
+     # RST & VMA.Q & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q);
+
+VMA.C = (CLK_OSZI);
+
+RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q);
+
+!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN
+     # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q);
+
+RW.C = (CLK_OSZI);
+
+cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
+     # cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q);
+
+cpu_est_0_.C = (CLK_OSZI);
+
+cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q
+     # cpu_est_1_.Q & !inst_CLK_000_NE_D0.Q
+     # cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_3_.Q & inst_CLK_000_NE_D0.Q);
+
+cpu_est_1_.C = (CLK_OSZI);
+
+cpu_est_2_.D = (!cpu_est_0_.Q & cpu_est_2_.Q
+     # !cpu_est_1_.Q & cpu_est_2_.Q
+     # cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q
+     # cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
+
+cpu_est_2_.C = (CLK_OSZI);
+
+cpu_est_3_.D = (!cpu_est_0_.Q & cpu_est_3_.Q
+     # cpu_est_3_.Q & !inst_CLK_000_NE_D0.Q
+     # cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
+
+cpu_est_3_.C = (CLK_OSZI);
+
+!inst_AS_000_INT.D = (RST & SM_AMIGA_5_.Q
+     # RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN);
+
+inst_AS_000_INT.C = (CLK_OSZI);
+
+SM_AMIGA_5_.D = (RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & SM_AMIGA_6_.Q
+     # RST & SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & BERR.PIN
+     # RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN);
+
+SM_AMIGA_5_.C = (CLK_OSZI);
+
+!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (A1 & RST & !BGACK_030.Q
+     # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q);
+
+inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI);
+
+!inst_AS_030_D0.D = (RST & !AS_030.PIN);
+
+inst_AS_030_D0.C = (CLK_OSZI);
+
+!inst_nEXP_SPACE_D0reg.D = (!nEXP_SPACE & RST);
+
+inst_nEXP_SPACE_D0reg.C = (CLK_OSZI);
+
+!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_D0.Q & !inst_AS_030_000_SYNC.Q & BERR.PIN
+     # !FC_1_ & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
+     # RST & A_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
+     # RST & A_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
+     # RST & !A_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
+     # RST & A_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
+     # RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN);
+
+inst_AS_030_000_SYNC.C = (CLK_OSZI);
+
+!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q);
+
+inst_BGACK_030_INT_D.C = (CLK_OSZI);
+
+inst_AS_000_DMA.D = (!RST
+     # BGACK_030.Q
+     # AS_000.PIN
+     # !CLK_030 & inst_AS_000_DMA.Q
+     # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
+     # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
+     # UDS_000.PIN & LDS_000.PIN);
+
+inst_AS_000_DMA.C = (CLK_OSZI);
+
+inst_DS_000_DMA.D = (!RST
+     # BGACK_030.Q
+     # AS_000.PIN
+     # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
+     # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
+     # UDS_000.PIN & LDS_000.PIN
+     # !CLK_030 & inst_DS_000_DMA.Q & !RW_000.PIN
+     # inst_DS_000_DMA.Q & !inst_CLK_030_H.Q & !RW_000.PIN
+     # CLK_030 & inst_AS_000_DMA.Q & inst_CLK_030_H.Q & !RW_000.PIN);
+
+inst_DS_000_DMA.C = (CLK_OSZI);
+
+CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & inst_CLK_000_PE.Q & !AS_000.PIN
+     # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN);
+
+CYCLE_DMA_0_.C = (CLK_OSZI);
+
+CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
+     # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN
+     # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_000_PE.Q & !AS_000.PIN);
+
+CYCLE_DMA_1_.C = (CLK_OSZI);
+
+!SIZE_DMA_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q
+     # RST & BGACK_030.Q & !SIZE_DMA_0_.Q
+     # RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
+
+SIZE_DMA_0_.C = (CLK_OSZI);
+
+SIZE_DMA_1_.D = (!RST
+     # BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_DMA_1_.Q
+     # !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
+
+SIZE_DMA_1_.C = (CLK_OSZI);
+
+!inst_VPA_D.D = (!VPA & RST);
+
+inst_VPA_D.C = (CLK_OSZI);
+
+!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q
+     # RST & SM_AMIGA_6_.Q & !A0.PIN);
+
+inst_UDS_000_INT.C = (CLK_OSZI);
+
+inst_LDS_000_INT.D = (!RST
+     # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q
+     # SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN);
+
+inst_LDS_000_INT.C = (CLK_OSZI);
+
+inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_25.Q);
+
+inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
+
+!inst_DTACK_D0.D = (!DTACK & RST);
+
+inst_DTACK_D0.C = (CLK_OSZI);
+
+inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q
+     # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q);
+
+inst_RESET_OUT.C = (CLK_OSZI);
+
+inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
+
+inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
+
+!N_210_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
+     # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
+     # !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
+     # !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);
+
+inst_CLK_OUT_PRE_25.D = (!inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q
+     # inst_CLK_OUT_PRE_50.Q & !inst_CLK_OUT_PRE_25.Q);
+
+inst_CLK_OUT_PRE_25.C = (CLK_OSZI);
+
+inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
+
+inst_CLK_000_D1.C = (CLK_OSZI);
+
+inst_CLK_000_D0.D = (CLK_000);
+
+inst_CLK_000_D0.C = (CLK_OSZI);
+
+inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q);
+
+inst_CLK_000_PE.C = (CLK_OSZI);
+
+inst_CLK_OUT_EXP_INT.D = (inst_CLK_OUT_PRE_50.Q);
+
+inst_CLK_OUT_EXP_INT.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q);
+
+CLK_000_P_SYNC_9_.C = (CLK_OSZI);
+
+inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q);
+
+inst_CLK_000_NE.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q);
+
+CLK_000_N_SYNC_11_.C = (CLK_OSZI);
+
+!IPL_D0_0_.D = (RST & !IPL_0_);
+
+IPL_D0_0_.C = (CLK_OSZI);
+
+!IPL_D0_1_.D = (RST & !IPL_1_);
+
+IPL_D0_1_.C = (CLK_OSZI);
+
+!IPL_D0_2_.D = (!IPL_2_ & RST);
+
+IPL_D0_2_.C = (CLK_OSZI);
+
+inst_CLK_000_NE_D0.D = (inst_CLK_000_NE.Q);
+
+inst_CLK_000_NE_D0.C = (CLK_OSZI);
+
+SM_AMIGA_0_.D = (RST & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & SM_AMIGA_1_.Q
+     # RST & !inst_CLK_000_PE.Q & SM_AMIGA_0_.Q & BERR.PIN);
+
+SM_AMIGA_0_.C = (CLK_OSZI);
+
+!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (!A1 & RST & !BGACK_030.Q
+     # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
+
+inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);
+
+SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & inst_CLK_000_NE.Q
+     # RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q
+     # RST & !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & BERR.PIN);
+
+SM_AMIGA_4_.C = (CLK_OSZI);
+
+inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN
+     # RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q
+     # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q
+     # RST & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN
+     # RST & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN);
+
+inst_DS_000_ENABLE.C = (CLK_OSZI);
+
+RST_DLY_0_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_0_.Q
+     # RST & inst_CLK_000_NE.Q & !RST_DLY_0_.Q
+     # RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q);
+
+RST_DLY_0_.C = (CLK_OSZI);
+
+RST_DLY_1_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_1_.Q
+     # RST & !RST_DLY_0_.Q & RST_DLY_1_.Q
+     # RST & RST_DLY_1_.Q & RST_DLY_2_.Q
+     # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q);
+
+RST_DLY_1_.C = (CLK_OSZI);
+
+RST_DLY_2_.D = (RST & RST_DLY_2_.Q
+     # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q);
+
+RST_DLY_2_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q);
+
+CLK_000_P_SYNC_0_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q);
+
+CLK_000_P_SYNC_1_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q);
+
+CLK_000_P_SYNC_2_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q);
+
+CLK_000_P_SYNC_3_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q);
+
+CLK_000_P_SYNC_4_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q);
+
+CLK_000_P_SYNC_5_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q);
+
+CLK_000_P_SYNC_6_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q);
+
+CLK_000_P_SYNC_7_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q);
+
+CLK_000_P_SYNC_8_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q);
+
+CLK_000_N_SYNC_0_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q);
+
+CLK_000_N_SYNC_1_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q);
+
+CLK_000_N_SYNC_2_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q);
+
+CLK_000_N_SYNC_3_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q);
+
+CLK_000_N_SYNC_4_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q);
+
+CLK_000_N_SYNC_5_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q);
+
+CLK_000_N_SYNC_6_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q);
+
+CLK_000_N_SYNC_7_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q);
+
+CLK_000_N_SYNC_8_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q);
+
+CLK_000_N_SYNC_9_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q);
+
+CLK_000_N_SYNC_10_.C = (CLK_OSZI);
+
+SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q
+     # RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN
+     # RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & !SM_AMIGA_i_7_.Q);
+
+SM_AMIGA_6_.C = (CLK_OSZI);
+
+inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
+     # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
+     # RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
+     # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
+     # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
+     # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
+     # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN
+     # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN);
+
+inst_CLK_030_H.C = (CLK_OSZI);
+
+SM_AMIGA_1_.D = (RST & inst_CLK_000_PE.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q
+     # RST & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & BERR.PIN
+     # RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q & BERR.PIN);
+
+SM_AMIGA_1_.C = (CLK_OSZI);
+
+SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q
+     # SM_AMIGA_3_.Q & !BERR.PIN
+     # RST & inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
+     # inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q
+     # !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q);
+
+SM_AMIGA_3_.C = (CLK_OSZI);
+
+SM_AMIGA_2_.D = (RST & SM_AMIGA_3_.Q & SM_AMIGA_2_.Q
+     # RST & !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN
+     # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q
+     # RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q);
+
+SM_AMIGA_2_.C = (CLK_OSZI);
+
+SM_AMIGA_i_7_.D = (RST & N_210_i & !inst_CLK_000_PE.Q & BERR.PIN
+     # RST & N_210_i & !SM_AMIGA_0_.Q & BERR.PIN
+     # RST & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_3_.Q
+     # RST & !SM_AMIGA_5_.Q & N_210_i & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q
+     # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
+     # RST & N_210_i & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
+     # RST & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
+     # RST & !SM_AMIGA_5_.Q & N_210_i & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
+     # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_210_i & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q
+     # RST & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_210_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q
+     # RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
+     # RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
+     # RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & N_210_i & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q
+     # RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & N_210_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q);
+
+SM_AMIGA_i_7_.C = (CLK_OSZI);
+
+CIIN_0 = (inst_nEXP_SPACE_D0reg.Q
+     # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
+
+
+Reverse-Polarity Equations:
+
diff --git a/Logic/68030_tk.err b/Logic/68030_tk.err
new file mode 100644
index 0000000..e69de29
diff --git a/Logic/68030_tk.fti b/Logic/68030_tk.fti
new file mode 100644
index 0000000..c4c4638
--- /dev/null
+++ b/Logic/68030_tk.fti
@@ -0,0 +1,478 @@
+#PLAFILE 68030_tk.tt4
+#DATE    03/16/2015
+#DESIGN  <no design name>
+#DEVICE  mach447a
+
+DATA LOCATION A0:G_8_69	//  IO {RN_A0}
+DATA LOCATION A1:F_*_60	// INP
+DATA LOCATION AMIGA_ADDR_ENABLE:D_5_33	// OUT
+DATA LOCATION AMIGA_BUS_DATA_DIR:E_1_48	// OUT
+DATA LOCATION AMIGA_BUS_ENABLE_HIGH:D_4_34	// OUT
+DATA LOCATION AMIGA_BUS_ENABLE_LOW:C_0_20	// OUT
+DATA LOCATION AS_000:E_4_42	//  IO
+DATA LOCATION AS_030:H_8_82	//  IO
+DATA LOCATION AVEC:A_4_92	// OUT
+DATA LOCATION A_16_:A_*_96	// INP
+DATA LOCATION A_17_:F_*_59	// INP
+DATA LOCATION A_18_:A_*_95	// INP
+DATA LOCATION A_19_:A_*_97	// INP
+DATA LOCATION A_20_:A_*_93	// INP
+DATA LOCATION A_21_:A_*_94	// INP
+DATA LOCATION A_22_:H_*_84	// INP
+DATA LOCATION A_23_:H_*_85	// INP
+DATA LOCATION A_24_:C_*_19	// INP
+DATA LOCATION A_25_:C_*_18	// INP
+DATA LOCATION A_26_:C_*_17	// INP
+DATA LOCATION A_27_:C_*_16	// INP
+DATA LOCATION A_28_:C_*_15	// INP
+DATA LOCATION A_29_:B_*_6	// INP
+DATA LOCATION A_30_:B_*_5	// INP
+DATA LOCATION A_31_:B_*_4	// INP
+DATA LOCATION BERR:E_0_41	//  IO
+DATA LOCATION BGACK_000:D_*_28	// INP
+DATA LOCATION BGACK_030:H_4_83	//  IO {RN_BGACK_030}
+DATA LOCATION BG_000:D_1_29	//  IO {RN_BG_000}
+DATA LOCATION BG_030:C_*_21	// INP
+DATA LOCATION CIIN:E_12_47	// OUT
+DATA LOCATION CIIN_0:E_9	// NOD
+DATA LOCATION CLK_000:*_*_11	// INP
+DATA LOCATION CLK_000_N_SYNC_0_:G_11	// NOD
+DATA LOCATION CLK_000_N_SYNC_10_:H_2	// NOD
+DATA LOCATION CLK_000_N_SYNC_11_:H_6	// NOD
+DATA LOCATION CLK_000_N_SYNC_1_:F_2	// NOD
+DATA LOCATION CLK_000_N_SYNC_2_:F_13	// NOD
+DATA LOCATION CLK_000_N_SYNC_3_:D_15	// NOD
+DATA LOCATION CLK_000_N_SYNC_4_:D_11	// NOD
+DATA LOCATION CLK_000_N_SYNC_5_:A_14	// NOD
+DATA LOCATION CLK_000_N_SYNC_6_:A_10	// NOD
+DATA LOCATION CLK_000_N_SYNC_7_:G_7	// NOD
+DATA LOCATION CLK_000_N_SYNC_8_:B_2	// NOD
+DATA LOCATION CLK_000_N_SYNC_9_:D_7	// NOD
+DATA LOCATION CLK_000_P_SYNC_0_:B_3	// NOD
+DATA LOCATION CLK_000_P_SYNC_1_:B_14	// NOD
+DATA LOCATION CLK_000_P_SYNC_2_:F_14	// NOD
+DATA LOCATION CLK_000_P_SYNC_3_:F_10	// NOD
+DATA LOCATION CLK_000_P_SYNC_4_:E_13	// NOD
+DATA LOCATION CLK_000_P_SYNC_5_:B_10	// NOD
+DATA LOCATION CLK_000_P_SYNC_6_:F_6	// NOD
+DATA LOCATION CLK_000_P_SYNC_7_:B_6	// NOD
+DATA LOCATION CLK_000_P_SYNC_8_:G_15	// NOD
+DATA LOCATION CLK_000_P_SYNC_9_:F_3	// NOD
+DATA LOCATION CLK_030:*_*_64	// INP
+DATA LOCATION CLK_DIV_OUT:G_1_65	// OUT
+DATA LOCATION CLK_EXP:B_0_10	// OUT
+DATA LOCATION CLK_OSZI:*_*_61	// Cin
+DATA LOCATION CYCLE_DMA_0_:A_6	// NOD
+DATA LOCATION CYCLE_DMA_1_:A_2	// NOD
+DATA LOCATION DSACK1:H_9_81	//  IO {RN_DSACK1}
+DATA LOCATION DS_030:A_0_98	// OUT
+DATA LOCATION DTACK:D_*_30	// INP
+DATA LOCATION E:G_4_66	// OUT
+DATA LOCATION FC_0_:F_*_57	// INP
+DATA LOCATION FC_1_:F_*_58	// INP
+DATA LOCATION FPU_CS:H_1_78	// OUT
+DATA LOCATION FPU_SENSE:A_*_91	// INP
+DATA LOCATION IPL_030_0_:B_8_8	//  IO {RN_IPL_030_0_}
+DATA LOCATION IPL_030_1_:B_12_7	//  IO {RN_IPL_030_1_}
+DATA LOCATION IPL_030_2_:B_4_9	//  IO {RN_IPL_030_2_}
+DATA LOCATION IPL_0_:G_*_67	// INP
+DATA LOCATION IPL_1_:F_*_56	// INP
+DATA LOCATION IPL_2_:G_*_68	// INP
+DATA LOCATION IPL_D0_0_:B_15	// NOD
+DATA LOCATION IPL_D0_1_:B_11	// NOD
+DATA LOCATION IPL_D0_2_:B_7	// NOD
+DATA LOCATION LDS_000:D_12_31	//  IO
+DATA LOCATION N_210_i:C_9	// NOD
+DATA LOCATION RESET:B_1_3	// OUT
+DATA LOCATION RN_A0:G_8	// NOD {A0}
+DATA LOCATION RN_BGACK_030:H_4	// NOD {BGACK_030}
+DATA LOCATION RN_BG_000:D_1	// NOD {BG_000}
+DATA LOCATION RN_DSACK1:H_9	// NOD {DSACK1}
+DATA LOCATION RN_IPL_030_0_:B_8	// NOD {IPL_030_0_}
+DATA LOCATION RN_IPL_030_1_:B_12	// NOD {IPL_030_1_}
+DATA LOCATION RN_IPL_030_2_:B_4	// NOD {IPL_030_2_}
+DATA LOCATION RN_RW:G_0	// NOD {RW}
+DATA LOCATION RN_RW_000:H_0	// NOD {RW_000}
+DATA LOCATION RN_VMA:D_0	// NOD {VMA}
+DATA LOCATION RST:*_*_86	// INP
+DATA LOCATION RST_DLY_0_:G_14	// NOD
+DATA LOCATION RST_DLY_1_:G_10	// NOD
+DATA LOCATION RST_DLY_2_:G_3	// NOD
+DATA LOCATION RW:G_0_71	//  IO {RN_RW}
+DATA LOCATION RW_000:H_0_80	//  IO {RN_RW_000}
+DATA LOCATION SIZE_0_:G_12_70	//  IO
+DATA LOCATION SIZE_1_:H_12_79	//  IO
+DATA LOCATION SIZE_DMA_0_:G_2	// NOD
+DATA LOCATION SIZE_DMA_1_:G_13	// NOD
+DATA LOCATION SM_AMIGA_0_:F_1	// NOD
+DATA LOCATION SM_AMIGA_1_:A_8	// NOD
+DATA LOCATION SM_AMIGA_2_:F_12	// NOD
+DATA LOCATION SM_AMIGA_3_:F_5	// NOD
+DATA LOCATION SM_AMIGA_4_:F_9	// NOD
+DATA LOCATION SM_AMIGA_5_:F_4	// NOD
+DATA LOCATION SM_AMIGA_6_:C_4	// NOD
+DATA LOCATION SM_AMIGA_i_7_:F_8	// NOD
+DATA LOCATION UDS_000:D_8_32	//  IO
+DATA LOCATION VMA:D_0_35	//  IO {RN_VMA}
+DATA LOCATION VPA:*_*_36	// INP
+DATA LOCATION cpu_est_0_:D_10	// NOD
+DATA LOCATION cpu_est_1_:D_6	// NOD
+DATA LOCATION cpu_est_2_:D_13	// NOD
+DATA LOCATION cpu_est_3_:D_2	// NOD
+DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_HIGH:B_5	// NOD
+DATA LOCATION inst_AMIGA_BUS_ENABLE_DMA_LOW:B_9	// NOD
+DATA LOCATION inst_AS_000_DMA:A_12	// NOD
+DATA LOCATION inst_AS_000_INT:B_13	// NOD
+DATA LOCATION inst_AS_030_000_SYNC:C_5	// NOD
+DATA LOCATION inst_AS_030_D0:H_13	// NOD
+DATA LOCATION inst_BGACK_030_INT_D:E_8	// NOD
+DATA LOCATION inst_CLK_000_D0:D_9	// NOD
+DATA LOCATION inst_CLK_000_D1:C_8	// NOD
+DATA LOCATION inst_CLK_000_NE:G_9	// NOD
+DATA LOCATION inst_CLK_000_NE_D0:D_14	// NOD
+DATA LOCATION inst_CLK_000_PE:F_0	// NOD
+DATA LOCATION inst_CLK_030_H:A_13	// NOD
+DATA LOCATION inst_CLK_OUT_EXP_INT:E_2	// NOD
+DATA LOCATION inst_CLK_OUT_PRE_25:G_6	// NOD
+DATA LOCATION inst_CLK_OUT_PRE_50:E_5	// NOD
+DATA LOCATION inst_CLK_OUT_PRE_D:D_3	// NOD
+DATA LOCATION inst_DS_000_DMA:A_9	// NOD
+DATA LOCATION inst_DS_000_ENABLE:C_12	// NOD
+DATA LOCATION inst_DTACK_D0:A_3	// NOD
+DATA LOCATION inst_LDS_000_INT:A_1	// NOD
+DATA LOCATION inst_RESET_OUT:G_5	// NOD
+DATA LOCATION inst_UDS_000_INT:A_5	// NOD
+DATA LOCATION inst_VPA_D:C_1	// NOD
+DATA LOCATION inst_nEXP_SPACE_D0reg:H_5	// NOD
+DATA LOCATION nEXP_SPACE:*_*_14	// INP
+DATA IO_DIR   A0:BI
+DATA IO_DIR   A1:IN
+DATA IO_DIR   AMIGA_ADDR_ENABLE:OUT
+DATA IO_DIR   AMIGA_BUS_DATA_DIR:OUT
+DATA IO_DIR   AMIGA_BUS_ENABLE_HIGH:OUT
+DATA IO_DIR   AMIGA_BUS_ENABLE_LOW:OUT
+DATA IO_DIR   AS_000:BI
+DATA IO_DIR   AS_030:BI
+DATA IO_DIR   AVEC:OUT
+DATA IO_DIR   A_16_:IN
+DATA IO_DIR   A_17_:IN
+DATA IO_DIR   A_18_:IN
+DATA IO_DIR   A_19_:IN
+DATA IO_DIR   A_20_:IN
+DATA IO_DIR   A_21_:IN
+DATA IO_DIR   A_22_:IN
+DATA IO_DIR   A_23_:IN
+DATA IO_DIR   A_24_:IN
+DATA IO_DIR   A_25_:IN
+DATA IO_DIR   A_26_:IN
+DATA IO_DIR   A_27_:IN
+DATA IO_DIR   A_28_:IN
+DATA IO_DIR   A_29_:IN
+DATA IO_DIR   A_30_:IN
+DATA IO_DIR   A_31_:IN
+DATA IO_DIR   BERR:BI
+DATA IO_DIR   BGACK_000:IN
+DATA IO_DIR   BGACK_030:OUT
+DATA IO_DIR   BG_000:OUT
+DATA IO_DIR   BG_030:IN
+DATA IO_DIR   CIIN:OUT
+DATA IO_DIR   CLK_000:IN
+DATA IO_DIR   CLK_030:IN
+DATA IO_DIR   CLK_DIV_OUT:OUT
+DATA IO_DIR   CLK_EXP:OUT
+DATA IO_DIR   CLK_OSZI:IN
+DATA IO_DIR   DSACK1:OUT
+DATA IO_DIR   DS_030:OUT
+DATA IO_DIR   DTACK:IN
+DATA IO_DIR   E:OUT
+DATA IO_DIR   FC_0_:IN
+DATA IO_DIR   FC_1_:IN
+DATA IO_DIR   FPU_CS:OUT
+DATA IO_DIR   FPU_SENSE:IN
+DATA IO_DIR   IPL_030_0_:OUT
+DATA IO_DIR   IPL_030_1_:OUT
+DATA IO_DIR   IPL_030_2_:OUT
+DATA IO_DIR   IPL_0_:IN
+DATA IO_DIR   IPL_1_:IN
+DATA IO_DIR   IPL_2_:IN
+DATA IO_DIR   LDS_000:BI
+DATA IO_DIR   RESET:OUT
+DATA IO_DIR   RST:IN
+DATA IO_DIR   RW:BI
+DATA IO_DIR   RW_000:BI
+DATA IO_DIR   SIZE_0_:BI
+DATA IO_DIR   SIZE_1_:BI
+DATA IO_DIR   UDS_000:BI
+DATA IO_DIR   VMA:OUT
+DATA IO_DIR   VPA:IN
+DATA IO_DIR   nEXP_SPACE:IN
+DATA GLB_CLOCK  CLK_OSZI
+DATA PW_LEVEL  SIZE_1_:1
+DATA SLEW      SIZE_1_:1
+DATA PW_LEVEL  A_31_:1
+DATA SLEW      A_31_:1
+DATA PW_LEVEL  IPL_2_:1
+DATA SLEW      IPL_2_:1
+DATA PW_LEVEL  FC_1_:1
+DATA SLEW      FC_1_:1
+DATA PW_LEVEL  IPL_1_:1
+DATA SLEW      IPL_1_:1
+DATA PW_LEVEL  AS_030:1
+DATA SLEW      AS_030:1
+DATA PW_LEVEL  IPL_0_:1
+DATA SLEW      IPL_0_:1
+DATA PW_LEVEL  AS_000:1
+DATA SLEW      AS_000:1
+DATA PW_LEVEL  FC_0_:1
+DATA SLEW      FC_0_:1
+DATA PW_LEVEL  DS_030:1
+DATA SLEW      DS_030:1
+DATA PW_LEVEL  UDS_000:1
+DATA SLEW      UDS_000:1
+DATA PW_LEVEL  LDS_000:1
+DATA SLEW      LDS_000:1
+DATA PW_LEVEL  A1:1
+DATA SLEW      A1:1
+DATA SLEW      nEXP_SPACE:1
+DATA PW_LEVEL  BERR:1
+DATA SLEW      BERR:1
+DATA PW_LEVEL  BG_030:1
+DATA SLEW      BG_030:1
+DATA PW_LEVEL  BGACK_000:1
+DATA SLEW      BGACK_000:1
+DATA SLEW      CLK_030:1
+DATA SLEW      CLK_000:1
+DATA SLEW      CLK_OSZI:1
+DATA PW_LEVEL  CLK_EXP:1
+DATA SLEW      CLK_EXP:0
+DATA PW_LEVEL  FPU_CS:1
+DATA SLEW      FPU_CS:0
+DATA PW_LEVEL  FPU_SENSE:1
+DATA SLEW      FPU_SENSE:1
+DATA PW_LEVEL  DTACK:1
+DATA SLEW      DTACK:1
+DATA PW_LEVEL  AVEC:1
+DATA SLEW      AVEC:1
+DATA PW_LEVEL  E:1
+DATA SLEW      E:1
+DATA SLEW      VPA:1
+DATA SLEW      RST:1
+DATA PW_LEVEL  RESET:1
+DATA SLEW      RESET:1
+DATA PW_LEVEL  AMIGA_ADDR_ENABLE:1
+DATA SLEW      AMIGA_ADDR_ENABLE:0
+DATA PW_LEVEL  AMIGA_BUS_DATA_DIR:1
+DATA SLEW      AMIGA_BUS_DATA_DIR:0
+DATA PW_LEVEL  SIZE_0_:1
+DATA SLEW      SIZE_0_:1
+DATA PW_LEVEL  AMIGA_BUS_ENABLE_LOW:1
+DATA SLEW      AMIGA_BUS_ENABLE_LOW:0
+DATA PW_LEVEL  A_30_:1
+DATA SLEW      A_30_:1
+DATA PW_LEVEL  AMIGA_BUS_ENABLE_HIGH:1
+DATA SLEW      AMIGA_BUS_ENABLE_HIGH:0
+DATA PW_LEVEL  A_29_:1
+DATA SLEW      A_29_:1
+DATA PW_LEVEL  CIIN:1
+DATA SLEW      CIIN:1
+DATA PW_LEVEL  A_28_:1
+DATA SLEW      A_28_:1
+DATA PW_LEVEL  A_27_:1
+DATA SLEW      A_27_:1
+DATA PW_LEVEL  A_26_:1
+DATA SLEW      A_26_:1
+DATA PW_LEVEL  A_25_:1
+DATA SLEW      A_25_:1
+DATA PW_LEVEL  A_24_:1
+DATA SLEW      A_24_:1
+DATA PW_LEVEL  A_23_:1
+DATA SLEW      A_23_:1
+DATA PW_LEVEL  A_22_:1
+DATA SLEW      A_22_:1
+DATA PW_LEVEL  A_21_:1
+DATA SLEW      A_21_:1
+DATA PW_LEVEL  A_20_:1
+DATA SLEW      A_20_:1
+DATA PW_LEVEL  A_19_:1
+DATA SLEW      A_19_:1
+DATA PW_LEVEL  A_18_:1
+DATA SLEW      A_18_:1
+DATA PW_LEVEL  A_17_:1
+DATA SLEW      A_17_:1
+DATA PW_LEVEL  A_16_:1
+DATA SLEW      A_16_:1
+DATA PW_LEVEL  IPL_030_2_:1
+DATA SLEW      IPL_030_2_:1
+DATA PW_LEVEL  IPL_030_1_:1
+DATA SLEW      IPL_030_1_:1
+DATA PW_LEVEL  IPL_030_0_:1
+DATA SLEW      IPL_030_0_:1
+DATA PW_LEVEL  RW_000:1
+DATA SLEW      RW_000:1
+DATA PW_LEVEL  A0:1
+DATA SLEW      A0:1
+DATA PW_LEVEL  BG_000:1
+DATA SLEW      BG_000:1
+DATA PW_LEVEL  BGACK_030:1
+DATA SLEW      BGACK_030:1
+DATA PW_LEVEL  CLK_DIV_OUT:1
+DATA SLEW      CLK_DIV_OUT:0
+DATA PW_LEVEL  DSACK1:1
+DATA SLEW      DSACK1:1
+DATA PW_LEVEL  VMA:1
+DATA SLEW      VMA:1
+DATA PW_LEVEL  RW:1
+DATA SLEW      RW:1
+DATA PW_LEVEL  cpu_est_0_:1
+DATA SLEW      cpu_est_0_:1
+DATA PW_LEVEL  cpu_est_1_:1
+DATA SLEW      cpu_est_1_:1
+DATA PW_LEVEL  cpu_est_2_:1
+DATA SLEW      cpu_est_2_:1
+DATA PW_LEVEL  cpu_est_3_:1
+DATA SLEW      cpu_est_3_:1
+DATA PW_LEVEL  inst_AS_000_INT:1
+DATA SLEW      inst_AS_000_INT:1
+DATA PW_LEVEL  SM_AMIGA_5_:1
+DATA SLEW      SM_AMIGA_5_:1
+DATA PW_LEVEL  inst_AMIGA_BUS_ENABLE_DMA_LOW:1
+DATA SLEW      inst_AMIGA_BUS_ENABLE_DMA_LOW:1
+DATA PW_LEVEL  inst_AS_030_D0:1
+DATA SLEW      inst_AS_030_D0:1
+DATA PW_LEVEL  inst_nEXP_SPACE_D0reg:1
+DATA SLEW      inst_nEXP_SPACE_D0reg:1
+DATA PW_LEVEL  inst_AS_030_000_SYNC:1
+DATA SLEW      inst_AS_030_000_SYNC:1
+DATA PW_LEVEL  inst_BGACK_030_INT_D:1
+DATA SLEW      inst_BGACK_030_INT_D:1
+DATA PW_LEVEL  inst_AS_000_DMA:1
+DATA SLEW      inst_AS_000_DMA:1
+DATA PW_LEVEL  inst_DS_000_DMA:1
+DATA SLEW      inst_DS_000_DMA:1
+DATA PW_LEVEL  CYCLE_DMA_0_:1
+DATA SLEW      CYCLE_DMA_0_:1
+DATA PW_LEVEL  CYCLE_DMA_1_:1
+DATA SLEW      CYCLE_DMA_1_:1
+DATA PW_LEVEL  SIZE_DMA_0_:1
+DATA SLEW      SIZE_DMA_0_:1
+DATA PW_LEVEL  SIZE_DMA_1_:1
+DATA SLEW      SIZE_DMA_1_:1
+DATA PW_LEVEL  inst_VPA_D:1
+DATA SLEW      inst_VPA_D:1
+DATA PW_LEVEL  inst_UDS_000_INT:1
+DATA SLEW      inst_UDS_000_INT:1
+DATA PW_LEVEL  inst_LDS_000_INT:1
+DATA SLEW      inst_LDS_000_INT:1
+DATA PW_LEVEL  inst_CLK_OUT_PRE_D:1
+DATA SLEW      inst_CLK_OUT_PRE_D:1
+DATA PW_LEVEL  inst_DTACK_D0:1
+DATA SLEW      inst_DTACK_D0:1
+DATA PW_LEVEL  inst_RESET_OUT:1
+DATA SLEW      inst_RESET_OUT:1
+DATA PW_LEVEL  inst_CLK_OUT_PRE_50:1
+DATA SLEW      inst_CLK_OUT_PRE_50:1
+DATA PW_LEVEL  N_210_i:1
+DATA SLEW      N_210_i:1
+DATA PW_LEVEL  inst_CLK_OUT_PRE_25:1
+DATA SLEW      inst_CLK_OUT_PRE_25:1
+DATA PW_LEVEL  inst_CLK_000_D1:1
+DATA SLEW      inst_CLK_000_D1:1
+DATA PW_LEVEL  inst_CLK_000_D0:1
+DATA SLEW      inst_CLK_000_D0:1
+DATA PW_LEVEL  inst_CLK_000_PE:1
+DATA SLEW      inst_CLK_000_PE:1
+DATA PW_LEVEL  inst_CLK_OUT_EXP_INT:1
+DATA SLEW      inst_CLK_OUT_EXP_INT:1
+DATA PW_LEVEL  CLK_000_P_SYNC_9_:1
+DATA SLEW      CLK_000_P_SYNC_9_:1
+DATA PW_LEVEL  inst_CLK_000_NE:1
+DATA SLEW      inst_CLK_000_NE:1
+DATA PW_LEVEL  CLK_000_N_SYNC_11_:1
+DATA SLEW      CLK_000_N_SYNC_11_:1
+DATA PW_LEVEL  IPL_D0_0_:1
+DATA SLEW      IPL_D0_0_:1
+DATA PW_LEVEL  IPL_D0_1_:1
+DATA SLEW      IPL_D0_1_:1
+DATA PW_LEVEL  IPL_D0_2_:1
+DATA SLEW      IPL_D0_2_:1
+DATA PW_LEVEL  inst_CLK_000_NE_D0:1
+DATA SLEW      inst_CLK_000_NE_D0:1
+DATA PW_LEVEL  SM_AMIGA_0_:1
+DATA SLEW      SM_AMIGA_0_:1
+DATA PW_LEVEL  inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
+DATA SLEW      inst_AMIGA_BUS_ENABLE_DMA_HIGH:1
+DATA PW_LEVEL  SM_AMIGA_4_:1
+DATA SLEW      SM_AMIGA_4_:1
+DATA PW_LEVEL  inst_DS_000_ENABLE:1
+DATA SLEW      inst_DS_000_ENABLE:1
+DATA PW_LEVEL  RST_DLY_0_:1
+DATA SLEW      RST_DLY_0_:1
+DATA PW_LEVEL  RST_DLY_1_:1
+DATA SLEW      RST_DLY_1_:1
+DATA PW_LEVEL  RST_DLY_2_:1
+DATA SLEW      RST_DLY_2_:1
+DATA PW_LEVEL  CLK_000_P_SYNC_0_:1
+DATA SLEW      CLK_000_P_SYNC_0_:1
+DATA PW_LEVEL  CLK_000_P_SYNC_1_:1
+DATA SLEW      CLK_000_P_SYNC_1_:1
+DATA PW_LEVEL  CLK_000_P_SYNC_2_:1
+DATA SLEW      CLK_000_P_SYNC_2_:1
+DATA PW_LEVEL  CLK_000_P_SYNC_3_:1
+DATA SLEW      CLK_000_P_SYNC_3_:1
+DATA PW_LEVEL  CLK_000_P_SYNC_4_:1
+DATA SLEW      CLK_000_P_SYNC_4_:1
+DATA PW_LEVEL  CLK_000_P_SYNC_5_:1
+DATA SLEW      CLK_000_P_SYNC_5_:1
+DATA PW_LEVEL  CLK_000_P_SYNC_6_:1
+DATA SLEW      CLK_000_P_SYNC_6_:1
+DATA PW_LEVEL  CLK_000_P_SYNC_7_:1
+DATA SLEW      CLK_000_P_SYNC_7_:1
+DATA PW_LEVEL  CLK_000_P_SYNC_8_:1
+DATA SLEW      CLK_000_P_SYNC_8_:1
+DATA PW_LEVEL  CLK_000_N_SYNC_0_:1
+DATA SLEW      CLK_000_N_SYNC_0_:1
+DATA PW_LEVEL  CLK_000_N_SYNC_1_:1
+DATA SLEW      CLK_000_N_SYNC_1_:1
+DATA PW_LEVEL  CLK_000_N_SYNC_2_:1
+DATA SLEW      CLK_000_N_SYNC_2_:1
+DATA PW_LEVEL  CLK_000_N_SYNC_3_:1
+DATA SLEW      CLK_000_N_SYNC_3_:1
+DATA PW_LEVEL  CLK_000_N_SYNC_4_:1
+DATA SLEW      CLK_000_N_SYNC_4_:1
+DATA PW_LEVEL  CLK_000_N_SYNC_5_:1
+DATA SLEW      CLK_000_N_SYNC_5_:1
+DATA PW_LEVEL  CLK_000_N_SYNC_6_:1
+DATA SLEW      CLK_000_N_SYNC_6_:1
+DATA PW_LEVEL  CLK_000_N_SYNC_7_:1
+DATA SLEW      CLK_000_N_SYNC_7_:1
+DATA PW_LEVEL  CLK_000_N_SYNC_8_:1
+DATA SLEW      CLK_000_N_SYNC_8_:1
+DATA PW_LEVEL  CLK_000_N_SYNC_9_:1
+DATA SLEW      CLK_000_N_SYNC_9_:1
+DATA PW_LEVEL  CLK_000_N_SYNC_10_:1
+DATA SLEW      CLK_000_N_SYNC_10_:1
+DATA PW_LEVEL  SM_AMIGA_6_:1
+DATA SLEW      SM_AMIGA_6_:1
+DATA PW_LEVEL  inst_CLK_030_H:1
+DATA SLEW      inst_CLK_030_H:1
+DATA PW_LEVEL  SM_AMIGA_1_:1
+DATA SLEW      SM_AMIGA_1_:1
+DATA PW_LEVEL  SM_AMIGA_3_:1
+DATA SLEW      SM_AMIGA_3_:1
+DATA PW_LEVEL  SM_AMIGA_2_:1
+DATA SLEW      SM_AMIGA_2_:1
+DATA PW_LEVEL  SM_AMIGA_i_7_:1
+DATA SLEW      SM_AMIGA_i_7_:1
+DATA PW_LEVEL  CIIN_0:1
+DATA SLEW      CIIN_0:1
+DATA PW_LEVEL  RN_IPL_030_2_:1
+DATA PW_LEVEL  RN_IPL_030_1_:1
+DATA PW_LEVEL  RN_IPL_030_0_:1
+DATA PW_LEVEL  RN_RW_000:1
+DATA PW_LEVEL  RN_A0:1
+DATA PW_LEVEL  RN_BG_000:1
+DATA PW_LEVEL  RN_BGACK_030:1
+DATA PW_LEVEL  RN_DSACK1:1
+DATA PW_LEVEL  RN_VMA:1
+DATA PW_LEVEL  RN_RW:1
+END
diff --git a/Logic/68030_tk.grp b/Logic/68030_tk.grp
new file mode 100644
index 0000000..2c8100d
--- /dev/null
+++ b/Logic/68030_tk.grp
@@ -0,0 +1,27 @@
+
+GROUP MACH_SEG_A inst_DS_000_DMA inst_CLK_030_H inst_AS_000_DMA inst_LDS_000_INT 
+      SM_AMIGA_1_ CYCLE_DMA_1_ CYCLE_DMA_0_ inst_UDS_000_INT inst_DTACK_D0 
+      CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ DS_030 AVEC 
+GROUP MACH_SEG_B IPL_030_1_ RN_IPL_030_1_ IPL_030_0_ RN_IPL_030_0_ IPL_030_2_ 
+      RN_IPL_030_2_ inst_AS_000_INT inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AMIGA_BUS_ENABLE_DMA_HIGH 
+      CLK_000_P_SYNC_0_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ CLK_000_P_SYNC_1_ 
+      CLK_000_P_SYNC_5_ CLK_000_P_SYNC_7_ CLK_000_N_SYNC_8_ CLK_EXP RESET 
+      
+GROUP MACH_SEG_C inst_AS_030_000_SYNC inst_DS_000_ENABLE SM_AMIGA_6_ inst_VPA_D 
+      inst_CLK_000_D1 AMIGA_BUS_ENABLE_LOW N_210_i 
+GROUP MACH_SEG_D VMA RN_VMA BG_000 RN_BG_000 cpu_est_3_ cpu_est_1_ cpu_est_2_ 
+      cpu_est_0_ inst_CLK_000_D0 CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_9_ 
+      inst_CLK_OUT_PRE_D inst_CLK_000_NE_D0 LDS_000 UDS_000 AMIGA_BUS_ENABLE_HIGH 
+      AMIGA_ADDR_ENABLE 
+GROUP MACH_SEG_E inst_BGACK_030_INT_D CLK_000_P_SYNC_4_ inst_CLK_OUT_PRE_50 
+      inst_CLK_OUT_EXP_INT CIIN BERR AMIGA_BUS_DATA_DIR AS_000 CIIN_0 
+GROUP MACH_SEG_F SM_AMIGA_i_7_ SM_AMIGA_2_ SM_AMIGA_3_ SM_AMIGA_0_ SM_AMIGA_4_ 
+      SM_AMIGA_5_ inst_CLK_000_PE CLK_000_P_SYNC_9_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ 
+      CLK_000_P_SYNC_6_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ 
+GROUP MACH_SEG_G A0 RN_A0 RW RN_RW CLK_DIV_OUT inst_RESET_OUT SIZE_DMA_0_ 
+      SIZE_DMA_1_ RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ inst_CLK_OUT_PRE_25 
+      CLK_000_N_SYNC_0_ inst_CLK_000_NE CLK_000_P_SYNC_8_ CLK_000_N_SYNC_7_ 
+      SIZE_0_ E 
+GROUP MACH_SEG_H DSACK1 RN_DSACK1 RW_000 RN_RW_000 BGACK_030 RN_BGACK_030 
+      inst_nEXP_SPACE_D0reg inst_AS_030_D0 CLK_000_N_SYNC_11_ CLK_000_N_SYNC_10_ 
+      FPU_CS AS_030 SIZE_1_ 
\ No newline at end of file
diff --git a/Logic/68030_tk.imp b/Logic/68030_tk.imp
new file mode 100644
index 0000000..18a49d6
--- /dev/null
+++ b/Logic/68030_tk.imp
@@ -0,0 +1,2 @@
+No pin assignment or valid property.
+No source constraints were imported.
\ No newline at end of file
diff --git a/Logic/68030_tk.ipr b/Logic/68030_tk.ipr
index c427f8d..06941ba 100644
--- a/Logic/68030_tk.ipr
+++ b/Logic/68030_tk.ipr
@@ -1 +1,2 @@
-<LATTICE_ENCRYPTED_BLIF>9934402)2BPold/
\ No newline at end of file
+<LATTICE_ENCRYPTED_BLIF>44:;035
:/
+i,
\ No newline at end of file
diff --git a/Logic/68030_tk - DMA-Working@50MHz.jed b/Logic/68030_tk.jed
similarity index 53%
rename from Logic/68030_tk - DMA-Working@50MHz.jed
rename to Logic/68030_tk.jed
index 239890f..92654bb 100644
--- a/Logic/68030_tk - DMA-Working@50MHz.jed	
+++ b/Logic/68030_tk.jed
@@ -10,7 +10,7 @@ AUTHOR:
 PATTERN:   
 COMPANY:   
 REVISION:  
-DATE:     Sat Mar 28 22:02:55 2015
+DATE:     Sun Jan 24 16:20:59 2016
 
 ABEL mach447a
  *
@@ -31,78 +31,81 @@ NOTE  Spread Placement?  Y *
 NOTE  Run Time Upper Bound in 15 minutes  0 *
 NOTE  Zero Hold Time For Input Registers?  Y *
 NOTE Table of pin names and numbers*
-NOTE PINS SIZE_1_:79 IPL_1_:56 A_31_:4 IPL_0_:67 FC_0_:57*
-NOTE PINS IPL_2_:68 FC_1_:58 AS_030:82 AS_000:42 DS_030:98*
+NOTE PINS SIZE_1_:79 A_31_:4 IPL_2_:68 FC_1_:58 IPL_1_:56*
+NOTE PINS AS_030:82 IPL_0_:67 AS_000:42 FC_0_:57 DS_030:98*
 NOTE PINS UDS_000:32 LDS_000:31 A1:60 nEXP_SPACE:14 BERR:41*
 NOTE PINS BG_030:21 BGACK_000:28 CLK_030:64 CLK_000:11 CLK_OSZI:61*
-NOTE PINS CLK_DIV_OUT:65 FPU_CS:78 FPU_SENSE:91 DTACK:30*
-NOTE PINS AVEC:92 SIZE_0_:70 VPA:36 A_30_:5 A_29_:6 RST:86*
-NOTE PINS A_28_:15 A_27_:16 A_26_:17 AMIGA_ADDR_ENABLE:33*
-NOTE PINS A_25_:18 AMIGA_BUS_DATA_DIR:48 A_24_:19 AMIGA_BUS_ENABLE_LOW:20*
-NOTE PINS A_23_:85 AMIGA_BUS_ENABLE_HIGH:34 A_22_:84 CIIN:47*
-NOTE PINS A_21_:94 A_20_:93 A_19_:97 A_18_:95 A_17_:59 A_16_:96*
-NOTE PINS IPL_030_1_:7 IPL_030_0_:8 IPL_030_2_:9 RW_000:80*
-NOTE PINS A0:69 BG_000:29 BGACK_030:83 CLK_EXP:10 DSACK1:81*
-NOTE PINS E:66 VMA:35 RESET:3 RW:71 *
+NOTE PINS CLK_EXP:10 FPU_CS:78 FPU_SENSE:91 DTACK:30 AVEC:92*
+NOTE PINS E:66 VPA:36 RST:86 RESET:3 AMIGA_ADDR_ENABLE:33*
+NOTE PINS AMIGA_BUS_DATA_DIR:48 SIZE_0_:70 AMIGA_BUS_ENABLE_LOW:20*
+NOTE PINS A_30_:5 AMIGA_BUS_ENABLE_HIGH:34 A_29_:6 CIIN:47*
+NOTE PINS A_28_:15 A_27_:16 A_26_:17 A_25_:18 A_24_:19 A_23_:85*
+NOTE PINS A_22_:84 A_21_:94 A_20_:93 A_19_:97 A_18_:95 A_17_:59*
+NOTE PINS A_16_:96 IPL_030_2_:9 IPL_030_1_:7 IPL_030_0_:8*
+NOTE PINS RW_000:80 A0:69 BG_000:29 BGACK_030:83 CLK_DIV_OUT:65*
+NOTE PINS DSACK1:81 VMA:35 RW:71 *
 NOTE Table of node names and numbers*
-NOTE NODES RN_SIZE_1_:287 RN_AS_030:281 RN_AS_000:203 RN_DS_030:101 *
-NOTE NODES RN_UDS_000:185 RN_LDS_000:191 RN_BERR:197 RN_SIZE_0_:263 *
-NOTE NODES RN_IPL_030_1_:143 RN_IPL_030_0_:137 RN_IPL_030_2_:131 *
-NOTE NODES RN_RW_000:269 RN_A0:257 RN_BG_000:175 RN_BGACK_030:275 *
-NOTE NODES RN_DSACK1:283 RN_E:251 RN_VMA:173 RN_RESET:127 *
-NOTE NODES RN_RW:245 cpu_est_0_:259 cpu_est_1_:182 inst_AS_000_INT:223 *
-NOTE NODES SM_AMIGA_5_:133 inst_AMIGA_BUS_ENABLE_DMA_LOW:239 *
-NOTE NODES inst_AS_030_D0:277 inst_nEXP_SPACE_D0reg:187 *
-NOTE NODES inst_DS_030_D0:109 inst_AS_030_000_SYNC:227 inst_BGACK_030_INT_D:289 *
+NOTE NODES RN_SIZE_1_:287 RN_AS_030:281 RN_AS_000:203 RN_UDS_000:185 *
+NOTE NODES RN_LDS_000:191 RN_BERR:197 RN_SIZE_0_:263 RN_IPL_030_2_:131 *
+NOTE NODES RN_IPL_030_1_:143 RN_IPL_030_0_:137 RN_RW_000:269 *
+NOTE NODES RN_A0:257 RN_BG_000:175 RN_BGACK_030:275 RN_DSACK1:283 *
+NOTE NODES RN_VMA:173 RN_RW:245 cpu_est_0_:188 cpu_est_1_:182 *
+NOTE NODES cpu_est_2_:193 cpu_est_3_:176 inst_AS_000_INT:145 *
+NOTE NODES SM_AMIGA_5_:227 inst_AMIGA_BUS_ENABLE_DMA_LOW:139 *
+NOTE NODES inst_AS_030_D0:289 inst_nEXP_SPACE_D0reg:277 *
+NOTE NODES inst_AS_030_000_SYNC:157 inst_BGACK_030_INT_D:209 *
 NOTE NODES inst_AS_000_DMA:119 inst_DS_000_DMA:115 CYCLE_DMA_0_:110 *
-NOTE NODES CYCLE_DMA_1_:104 SIZE_DMA_0_:254 SIZE_DMA_1_:248 *
-NOTE NODES inst_VPA_D:103 inst_UDS_000_INT:157 inst_LDS_000_INT:265 *
-NOTE NODES inst_CLK_OUT_PRE_D:209 inst_DTACK_D0:256 inst_CLK_OUT_PRE_50:217 *
-NOTE NODES inst_CLK_000_D1:178 inst_CLK_000_D0:229 inst_CLK_000_PE:193 *
-NOTE NODES CLK_000_P_SYNC_9_:112 inst_CLK_000_NE:176 CLK_000_N_SYNC_11_:278 *
-NOTE NODES cpu_est_2_:253 SM_AMIGA_3_:167 inst_CLK_000_NE_D0:221 *
-NOTE NODES SM_AMIGA_0_:145 inst_AMIGA_BUS_ENABLE_DMA_HIGH:233 *
-NOTE NODES SM_AMIGA_6_:139 CLK_000_P_SYNC_0_:142 CLK_000_P_SYNC_1_:250 *
-NOTE NODES CLK_000_P_SYNC_2_:266 CLK_000_P_SYNC_3_:163 CLK_000_P_SYNC_4_:194 *
-NOTE NODES CLK_000_P_SYNC_5_:188 CLK_000_P_SYNC_6_:230 CLK_000_P_SYNC_7_:211 *
-NOTE NODES CLK_000_P_SYNC_8_:260 CLK_000_N_SYNC_0_:136 CLK_000_N_SYNC_1_:130 *
-NOTE NODES CLK_000_N_SYNC_2_:146 CLK_000_N_SYNC_3_:224 CLK_000_N_SYNC_4_:106 *
-NOTE NODES CLK_000_N_SYNC_5_:241 CLK_000_N_SYNC_6_:235 CLK_000_N_SYNC_7_:122 *
-NOTE NODES CLK_000_N_SYNC_8_:140 CLK_000_N_SYNC_9_:116 CLK_000_N_SYNC_10_:272 *
-NOTE NODES inst_CLK_030_H:121 SM_AMIGA_1_:113 SM_AMIGA_4_:128 *
-NOTE NODES N_125_i_2:134 SM_AMIGA_2_:161 inst_DS_000_ENABLE:151 *
-NOTE NODES SM_AMIGA_i_7_:155 CIIN_0:205 *
+NOTE NODES CYCLE_DMA_1_:104 SIZE_DMA_0_:248 SIZE_DMA_1_:265 *
+NOTE NODES inst_VPA_D:151 inst_UDS_000_INT:109 inst_LDS_000_INT:103 *
+NOTE NODES inst_CLK_OUT_PRE_D:178 inst_DTACK_D0:106 inst_RESET_OUT:253 *
+NOTE NODES inst_CLK_OUT_PRE_50:205 N_210_i:163 inst_CLK_OUT_PRE_25:254 *
+NOTE NODES inst_CLK_000_D1:161 inst_CLK_000_D0:187 inst_CLK_000_PE:221 *
+NOTE NODES inst_CLK_OUT_EXP_INT:200 CLK_000_P_SYNC_9_:226 *
+NOTE NODES inst_CLK_000_NE:259 CLK_000_N_SYNC_11_:278 IPL_D0_0_:148 *
+NOTE NODES IPL_D0_1_:142 IPL_D0_2_:136 inst_CLK_000_NE_D0:194 *
+NOTE NODES SM_AMIGA_0_:223 inst_AMIGA_BUS_ENABLE_DMA_HIGH:133 *
+NOTE NODES SM_AMIGA_4_:235 inst_DS_000_ENABLE:167 RST_DLY_0_:266 *
+NOTE NODES RST_DLY_1_:260 RST_DLY_2_:250 CLK_000_P_SYNC_0_:130 *
+NOTE NODES CLK_000_P_SYNC_1_:146 CLK_000_P_SYNC_2_:242 CLK_000_P_SYNC_3_:236 *
+NOTE NODES CLK_000_P_SYNC_4_:217 CLK_000_P_SYNC_5_:140 CLK_000_P_SYNC_6_:230 *
+NOTE NODES CLK_000_P_SYNC_7_:134 CLK_000_P_SYNC_8_:268 CLK_000_N_SYNC_0_:262 *
+NOTE NODES CLK_000_N_SYNC_1_:224 CLK_000_N_SYNC_2_:241 CLK_000_N_SYNC_3_:196 *
+NOTE NODES CLK_000_N_SYNC_4_:190 CLK_000_N_SYNC_5_:122 CLK_000_N_SYNC_6_:116 *
+NOTE NODES CLK_000_N_SYNC_7_:256 CLK_000_N_SYNC_8_:128 CLK_000_N_SYNC_9_:184 *
+NOTE NODES CLK_000_N_SYNC_10_:272 SM_AMIGA_6_:155 inst_CLK_030_H:121 *
+NOTE NODES SM_AMIGA_1_:113 SM_AMIGA_3_:229 SM_AMIGA_2_:239 *
+NOTE NODES SM_AMIGA_i_7_:233 CIIN_0:211 *
 NOTE  BLOCK 0 *
 L000000
-        111111111011111111111111111111111111111111111111111111111111111111
-        111001111110111111111111111111111111111111111111111111111111111111
-        111111111111110111111111111111111111111111111111111111111111111111
-        111111111111111111101111111111111111111111111111111111111111111111
-        111111111111111111111111111111011111011111111111111111111111111111
-        111111111111111111111111111111111111111111011111010111111111111111
-        111111011111101111110111011111111111110111111111111111011111111111
-        111111111111111101111111111111111111111110111111111111111111111111
-        101111111111111111111111110111110110111111110111111110111111111111*
+        111011111011111111111111111111111111111111111111111111111111111111
+        111111111111111111111111111110111111111111111111111111101111111111
+        101111111111111111111111111111111111111111111111111111111111111111
+        111111111111011111111111111111111111111111111111111111111111111110
+        111111011110111111111111111111111111111111111111111111111111111111
+        111111111111111111111111111111011111110110111111110111111111111111
+        111101111111111111010111111111111111111111111111011111111011011111
+        111111111111111101111111111011111111011111111110111111111111111111
+        111111111111111111111111011111111010111111100111111111111111111111*
 L000594
         000000000000000000000000000000000000000000000000000000000000000000*
-L000660 111111111111111111111111111111111111111011111111111110111111111111*
+L000660 111110111111111111111111111111111011111111111111111111111111111111*
 L000726 000000000000000000000000000000000000000000000000000000000000000000*
 L000792 000000000000000000000000000000000000000000000000000000000000000000*
 L000858 000000000000000000000000000000000000000000000000000000000000000000*
 L000924 000000000000000000000000000000000000000000000000000000000000000000*
-L000990 011111111111111111111111111011111111111111111111111111111111111111*
-L001056 000000000000000000000000000000000000000000000000000000000000000000*
-L001122 000000000000000000000000000000000000000000000000000000000000000000*
+L000990 111111111111111111111111111111111111111111101111111111111111111111*
+L001056 111111111111101111111111011111111111111111111111111111111111111111*
+L001122 101111111111011111111111111101111111111110111111111111111111111111*
 L001188 000000000000000000000000000000000000000000000000000000000000000000*
 L001254 000000000000000000000000000000000000000000000000000000000000000000*
 L001320
         111111111111111111111111111111111111111111111111111111111111111111*
-L001386 011111111111111111111011111111111111111110110111111110111111111111*
-L001452 011111111111111111110111111111111111111110011011111110111111111111*
-L001518 011111111111111111111111111111111111111110100111111110111111111111*
+L001386 111111111111111111111011111111111011111111010110111111111111111111*
+L001452 111111111101111111110111111111111011111111011010111111111111111111*
+L001518 111111111110111111111111111111111011111111010110111111111111111111*
 L001584 000000000000000000000000000000000000000000000000000000000000000000*
 L001650 000000000000000000000000000000000000000000000000000000000000000000*
-L001716 111111111111111111011111111111111111111111111111111111111111111111*
+L001716 111111111111111111101111111111111111111111011111111111111111111111*
 L001782 000000000000000000000000000000000000000000000000000000000000000000*
 L001848 000000000000000000000000000000000000000000000000000000000000000000*
 L001914 000000000000000000000000000000000000000000000000000000000000000000*
@@ -114,65 +117,65 @@ L002178 000000000000000000000000000000000000000000000000000000000000000000*
 L002244 000000000000000000000000000000000000000000000000000000000000000000*
 L002310 000000000000000000000000000000000000000000000000000000000000000000*
 L002376 000000000000000000000000000000000000000000000000000000000000000000*
-L002442 011111111111111111111111111111111111101111111111111111111111111111*
-L002508 000000000000000000000000000000000000000000000000000000000000000000*
+L002442 111111111111101111111111111111111111101111011111111111111111111111*
+L002508 101111111111011111111111111111111111111111011111111111111111111111*
 L002574 000000000000000000000000000000000000000000000000000000000000000000*
 L002640 000000000000000000000000000000000000000000000000000000000000000000*
 L002706 000000000000000000000000000000000000000000000000000000000000000000*
 L002772
         000000000000000000000000000000000000000000000000000000000000000000*
-L002838 011111111111111111111011111111111111111110011111111110111111111111*
-L002904 011111111111111111110111111111111111111110101111111110111111111111*
+L002838 111111111101111111111011111111111011111111011110111111111111111111*
+L002904 111111111110111111110111111111111011111111011110111111111111111111*
 L002970 000000000000000000000000000000000000000000000000000000000000000000*
 L003036 000000000000000000000000000000000000000000000000000000000000000000*
 L003102 000000000000000000000000000000000000000000000000000000000000000000*
-L003168 111111111101111111111111111111111111111111111111111111111111111111*
-L003234 000000000000000000000000000000000000000000000000000000000000000000*
-L003300 000000000000000000000000000000000000000000000000000000000000000000*
-L003366 000000000000000000000000000000000000000000000000000000000000000000*
-L003432 000000000000000000000000000000000000000000000000000000000000000000*
+L003168 111111111111111111111111111111111111111111111111111111111111111111*
+L003234 111111111111111111111111111111111111111111111111111111111111111111*
+L003300 111111111111111111111111111111111111111111111111111111111111111111*
+L003366 111111111111111111111111111111111111111111111111111111111111111111*
+L003432 111111111111111111111111111111111111111111111111111111111111111111*
 L003498
         000000000000000000000000000000000000000000000000000000000000000000*
-L003564 011111101111110111111111111111111111111111011111111111111111111111*
-L003630 011111011111111111111111111111111001111111111111111111111111111111*
-L003696 011111011111110111111111111111111101111111111111111111111111111111*
+L003564 110111111101111111111111111111111111111111011111111111111111101111*
+L003630 111111111111111111111111111111111101111111011111111111101111011111*
+L003696 110111111111111111111111111111111101111111011111111111111111011111*
 L003762 000000000000000000000000000000000000000000000000000000000000000000*
 L003828 000000000000000000000000000000000000000000000000000000000000000000*
-L003894 101111111111111111111111111111111111111111111111111111111111111111*
-L003960 111111111111111111111111111111111111111101111111111111111111111111*
+L003894 111111111111111111111111111111111111111111101111111111111111111111*
+L003960 111111111111111111111111111111111111111111111101111111111111111111*
 L004026 111111111111111111110111111111111111111111110111111111111111111111*
 L004092 111111111111111111111011111111111111111111111011111111111111111111*
-L004158 111111111111111111111111111111111111111111111111111101111111111111*
+L004158 111111111111111111111111111111110111111111111111111111111111111111*
 L004224
         000000000000000000000000000000000000000000000000000000000000000000*
-L004290 111101111111111111111111111111111111111111111111111111111111111111*
-L004356 111111111111111101111111111111111111111111111111111111011111111111*
-L004422 111111111011101111111111111111111111110111111111111111111111111111*
-L004488 111111110111101111111111111111111111111111111111010111111111111111*
-L004554 111111111111101111111111111111111111110111111111111011111111111111*
-L004620 101111111111111111111111111111111111111111111111111111111111111111*
-L004686 111111111111111111111111111111111111111101111111111111111111111111*
-L004752 111111111011111111111111111111111111111111111111011111111111111111*
+L004290 111111011111111111111111111111111111111111111111111111111111111111*
+L004356 111111111111111101111111111111111111111111111111011111111111111111*
+L004422 111101111011111111111111111111111111111111111111111111111011111111*
+L004488 111111110111111111111111111111011111111111111111110111111011111111*
+L004554 111101111111111111111111111111111111111111111111111011111011111111*
+L004620 111111111111111111111111111111111111111111101111111111111111111111*
+L004686 111111111111111111111111111111111111111111111101111111111111111111*
+L004752 111111111011111111111111111111011111111111111111111111111111111111*
 L004818 111111111111111111110111111111111111111111110111111111111111111111*
 L004884 111111111111111111111011111111111111111111111011111111111111111111*
 L004950
         000000000000000000000000000000000000000000000000000000000000000000*
-L005016 111111111111111111111111111111111111111111111111111101111111111111*
-L005082 111111111111111101111111111111111111111111111111111111011111111111*
+L005016 111111111111111111111111111111110111111111111111111111111111111111*
+L005082 111111111111111101111111111111111111111111111111011111111111111111*
 L005148 000000000000000000000000000000000000000000000000000000000000000000*
 L005214 000000000000000000000000000000000000000000000000000000000000000000*
 L005280 000000000000000000000000000000000000000000000000000000000000000000*
-L005346 011111111011111110111011111111111111111110110111101110111111111111*
-L005412 011111111011111110110111111111111111111110111011101110111111111111*
-L005478 011111111111111110111011111111111111111110110111110110111111111111*
-L005544 011111111111111110110111111111111111111110111011110110111111111111*
-L005610 011111111011111111111011111111111111111110110111101110101111111111*
+L005346 111111111011111110111011111111101011111111010110111111111111111111*
+L005412 111111111011111110110111111111101011111111011010111111111111111111*
+L005478 111111111111111110111011111111111011111111010110110111111111111111*
+L005544 111111111111111110110111111111111011111111011010110111111111111111*
+L005610 111111111011111111111011111111101011111111010110101111111111111111*
 L005676
-        111111111111111111111111101111011111111110111111111111111111111111*
-L005742 110111111111111111111111111111111111111111111111111111111111111111*
-L005808 011111111011111111110111111111111111111110111011101110101111111111*
-L005874 011111111111111111111011111111111111111110110111110110101111111111*
-L005940 011111111111111111110111111111111111111110111011110110101111111111*
+        111111111111111111111111111011111111111111111110111111111111111101*
+L005742 111111111111111111111111111111111111110111111111111111111111111111*
+L005808 111111111011111111110111111111101011111111011010101111111111111111*
+L005874 111111111111111111111011111111111011111111010110100111111111111111*
+L005940 111111111111111111110111111111111011111111011010100111111111111111*
 L006006 000000000000000000000000000000000000000000000000000000000000000000*
 L006072 111111111111111111111111111111111111111111111111111111111111111111*
 L006138 111111111111111111111111111111111111111111111111111111111111111111*
@@ -184,171 +187,171 @@ L006402
         000000000000000000000000000000000000000000000000000000000000000000*
 L006534 0010*
 L006538 01100011111000*
-L006552 01100110010011*
+L006552 10100110010011*
 L006566 10100110010101*
-L006580 00100110011111*
+L006580 01100110011111*
 L006594 00101111111000*
-L006608 01100110010010*
+L006608 11100110010010*
 L006622 10100110010000*
-L006636 00100110010011*
+L006636 11100011110011*
 L006650 10100110010000*
 L006664 10100110010010*
 L006678 00110110010000*
-L006692 11011011110011*
+L006692 11011111110011*
 L006706 10100110010001*
 L006720 10100110010011*
 L006734 00110110010100*
-L006748 11101111110010*
+L006748 11100011111111*
 NOTE  BLOCK 1 *
 L006762
-        111111111111111111110111011111011111111111111111111111111111111111
-        111111111111011111111111111111111111111111111111111111111111111111
-        111111101011110101101111111111111111111111111111011111111111110111
-        101111111101111111111111111101111111011111111111111111011110111111
-        111111111111111111111111111111111111111101111111111111111111111111
-        110111111111111111111111111111111111111111111111111111111111111111
-        111111111111111111111111111111111011111111111111110111111111011111
-        111111111111111111111111110111111111111111111111111111111111111111
-        111111111111111111111111111111111110111111101111111111110111111111*
+        111111111111111111110111111111111111111111111111111101011111111111
+        111111111111010111111111111111111111111111111111111111111111111111
+        111111111011111111111110101111111101111111101111011111110101111111
+        111111111101111111111111111110111011111111111011111111111111011111
+        111111101111111111111111111111111111111111111111111111111111111111
+        111110111111111111111111111111111111111011111111111111111111111111
+        111111111111111110111111111111111111111111111111110111111111111111
+        111111111111111111111111111111111111111110111111111111111111111111
+        101011111111111111111111111111101111111111111111111111111111111111*
 L007356
         111111111111111111111111111111111111111111111111111111111111111111*
-L007422 111111111111111111111111111111110111111111111111111111111111111111*
+L007422 111111111111111111111111111111101111111111111111111111111111111111*
 L007488 000000000000000000000000000000000000000000000000000000000000000000*
 L007554 000000000000000000000000000000000000000000000000000000000000000000*
 L007620 000000000000000000000000000000000000000000000000000000000000000000*
 L007686 000000000000000000000000000000000000000000000000000000000000000000*
-L007752 111111111111111111111111111111111111111111011111111111111111111111*
+L007752 000000000000000000000000000000000000000000000000000000000000000000*
 L007818 000000000000000000000000000000000000000000000000000000000000000000*
 L007884 000000000000000000000000000000000000000000000000000000000000000000*
 L007950 000000000000000000000000000000000000000000000000000000000000000000*
 L008016 000000000000000000000000000000000000000000000000000000000000000000*
 L008082
         111111111111111111111111111111111111111111111111111111111111111111*
-L008148 111111111111111111111111111111111111111111011111111111110111110111*
-L008214 111111111111111111111111111111111111011111011111111111111111110111*
-L008280 111011111111111111111111111111111101011111011111111111111111111111*
+L008148 111111111111111111111111011111111111111111111111111111111111111111*
+L008214 000000000000000000000000000000000000000000000000000000000000000000*
+L008280 000000000000000000000000000000000000000000000000000000000000000000*
 L008346 000000000000000000000000000000000000000000000000000000000000000000*
 L008412 000000000000000000000000000000000000000000000000000000000000000000*
-L008478 111111111111111111111111111111111111111111111111011111111111111111*
+L008478 111111111111111111111111111111111111111111111111110111111110111111*
 L008544 000000000000000000000000000000000000000000000000000000000000000000*
 L008610 000000000000000000000000000000000000000000000000000000000000000000*
 L008676 000000000000000000000000000000000000000000000000000000000000000000*
 L008742 000000000000000000000000000000000000000000000000000000000000000000*
 L008808
         111111111111111111111111111111111111111111111111111111111111111111*
-L008874 111111111011111111111111111111111111111111011111111111110111111111*
-L008940 111111111111111111111111111111111111111111011111111111101011111111*
-L009006 000000000000000000000000000000000000000000000000000000000000000000*
-L009072 000000000000000000000000000000000000000000000000000000000000000000*
-L009138 000000000000000000000000000000000000000000000000000000000000000000*
-L009204 110111111111011111111111111111111111111111011111111111111111111011*
-L009270 111111111111111111111111111111111101111111011111111111111011110111*
-L009336 111111111111011111111111111111111101111111011111111111111111110111*
-L009402 000000000000000000000000000000000000000000000000000000000000000000*
-L009468 000000000000000000000000000000000000000000000000000000000000000000*
+L008874 011111111011110111111111111111110111111111011111101111011111111111*
+L008940 011111111011110111111111111111111011111111011111101111101111111111*
+L009006 011111111011111011111111111111110111111111101111101111011111111111*
+L009072 011111111011111011111111111111111011111111101111101111101111111111*
+L009138 011111111011111111111111111111111111111111111111111111111111101111*
+L009204 011111111111111111111111111111111011111111111111111111011111101111*
+L009270 011111111111111111111111111111110111111111111111111111101111101111*
+L009336 011111111111110111111111111111111111111111101111111111111111101111*
+L009402 011111111111111011111111111111111111111111011111111111111111101111*
+L009468 011111111111111111111111111111111111111111111111101111111111101111*
 L009534
         111111111111111111111111111111111111111111111111111111111111111111*
-L009600 111111111111101011111011111111101111101111111111111011111111101011*
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 L010128 000000000000000000000000000000000000000000000000000000000000000000*
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 L010260
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 L010986
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 L011580 000000000000000000000000000000000000000000000000000000000000000000*
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 L011712
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 L012438
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 L012504 111111111101111111111111111111111111111111111111111111111111111111*
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 L013412 11100110011000*
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 NOTE  BLOCK 2 *
 L013524
-        111011110111111111111110111111111111111111011111111111111111111111
-        111111111111011110111011111111111111111111111111111111111111111111
-        111111111111111111111111101111100111111111111101111111110111111111
-        111110101111110111111111111111111111111111111111110111111111111111
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-        111111111111111111111111111111111111111111111111111111111111111111
-        111111111111111111111111111011111111011110111111111111111111011111
-        101111111111111111011111111111111110111111111111111101111111111111*
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+        111110111111111111101111111111111111111111111111101111111101111111
+        111111111111110110111011101101111111111111111111111111111111111111
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 L014118
         000000000000000000000000000000000000000000000000000000000000000000*
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 L014250 000000000000000000000000000000000000000000000000000000000000000000*
 L014316 000000000000000000000000000000000000000000000000000000000000000000*
 L014382 000000000000000000000000000000000000000000000000000000000000000000*
 L014448 000000000000000000000000000000000000000000000000000000000000000000*
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 L014844
         000000000000000000000000000000000000000000000000000000000000000000*
 L014910 111111111111111111111111111111111111111111111111111111111111111111*
@@ -363,21 +366,21 @@ L015438 111111111111111111111111111111111111111111111111111111111111111111*
 L015504 111111111111111111111111111111111111111111111111111111111111111111*
 L015570
         000000000000000000000000000000000000000000000000000000000000000000*
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 L016296
         000000000000000000000000000000000000000000000000000000000000000000*
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 L016560 000000000000000000000000000000000000000000000000000000000000000000*
 L016626 000000000000000000000000000000000000000000000000000000000000000000*
 L016692 111111111111111111111111111111111111111111111111111111111111111111*
@@ -387,16 +390,16 @@ L016890 111111111111111111111111111111111111111111111111111111111111111111*
 L016956 111111111111111111111111111111111111111111111111111111111111111111*
 L017022
         000000000000000000000000000000000000000000000000000000000000000000*
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 L017748
         111111111111111111111111111111111111111111111111111111111111111111*
 L017814 111111111111111111111111111111111111111111111111111111111111111111*
@@ -411,11 +414,11 @@ L018342 111111111111111111111111111111111111111111111111111111111111111111*
 L018408 111111111111111111111111111111111111111111111111111111111111111111*
 L018474
         000000000000000000000000000000000000000000000000000000000000000000*
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 L018870 111111111111111111111111111111111111111111111111111111111111111111*
 L018936 111111111111111111111111111111111111111111111111111111111111111111*
 L019002 111111111111111111111111111111111111111111111111111111111111111111*
@@ -438,60 +441,60 @@ L019926
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 L020058 0010*
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 L020090 11010011110001*
 L020104 11111111110011*
 L020118 10100110010000*
 L020132 11100110010011*
-L020146 11000011110000*
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 L020160 11111111110010*
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 L020272 11111111111110*
 NOTE  BLOCK 3 *
 L020286
-        111111111111111111101111111111111111111111111111111111111111111111
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-        110111111111111111111111111111111111111111111111111111111111111111
-        111111111111111111111111011111111111111101111111111111111111111111
-        111111111111111111111111111011110111111111111110111111111111101111
-        101111111111111111111111111111111101011111011111111111110111111111*
+        111111111111101111111111111101011111111111111111111111111111111111
+        111111110111111111111111101111111111111111111111111111111111111111
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+        111111111111111111111111111111111111111001011111111111111111111111
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 L020880
         111111111111111111111111111111111111111111111111111111111111111111*
-L020946 101111111111111111111111111111111111101111111111111111111111111111*
-L021012 110111111111111111111110111111110111101111111111111111101111111101*
-L021078 011111111111111111111110111111111011011111101111111111010111111101*
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 L021144 000000000000000000000000000000000000000000000000000000000000000000*
 L021210 000000000000000000000000000000000000000000000000000000000000000000*
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 L021342 011111111011111111111111111111111110111111111111111111111111111111*
 L021408 000000000000000000000000000000000000000000000000000000000000000000*
 L021474 000000000000000000000000000000000000000000000000000000000000000000*
 L021540 000000000000000000000000000000000000000000000000000000000000000000*
 L021606
         111111111111111111111111111111111111111111111111111111111111111111*
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 L021870 000000000000000000000000000000000000000000000000000000000000000000*
 L021936 000000000000000000000000000000000000000000000000000000000000000000*
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 L022068 000000000000000000000000000000000000000000000000000000000000000000*
 L022134 000000000000000000000000000000000000000000000000000000000000000000*
 L022200 000000000000000000000000000000000000000000000000000000000000000000*
 L022266 000000000000000000000000000000000000000000000000000000000000000000*
 L022332
         111111111111111111111111111111111111111111111111111111111111111111*
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 L022530 000000000000000000000000000000000000000000000000000000000000000000*
 L022596 000000000000000000000000000000000000000000000000000000000000000000*
 L022662 000000000000000000000000000000000000000000000000000000000000000000*
@@ -501,111 +504,111 @@ L022860 000000000000000000000000000000000000000000000000000000000000000000*
 L022926 000000000000000000000000000000000000000000000000000000000000000000*
 L022992 000000000000000000000000000000000000000000000000000000000000000000*
 L023058
-        111111111111111101111111111111111111111111111101111111111111111111*
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-L023322 111111111111111111111101111111111111111111111111110111011111111110*
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 L023784
-        111111111111111101111111111111111111111111111101111111111111111111*
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-L024048 111111111111111111111111111111111111111111111111111111111111111111*
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-L024246 111111111111111111111111111111111111111111111111111111111111111111*
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 L024510
         000000000000000000000000000000000000000000000000000000000000000000*
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 L025236
         111111111111111111111111111111111111111111111111111111111111111111*
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 L026688
         000000000000000000000000000000000000000000000000000000000000000000
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 L026820 0010*
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 L026838 11100110011110*
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 L026866 00100110011111*
 L026880 10101011111001*
 L026894 00100011111111*
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 NOTE  BLOCK 4 *
 L027048
-        111111111111111111111111111111111111111111111111111111111111111111
-        110111111111111111011111111111111111111111111111111111111111111111
-        111111011101111111111111110111111111111011111111101111111111111111
-        111111111111111111111111101111111101111111011111111111101111111111
-        111111111111110111111011111111111111111111111101111111111111111111
-        111110111111011111111111111111111111011111111111111111111111111111
-        111111111111111111111111111111111111111111111111110101111011110111
-        101111111011111111111111111110011111111111111111111111111101111110
-        111111111111111110111101111111111011111110111111111111111111111111*
+        111111111111111111110111111111111111111111111111111111111111111111
+        111111111111111111011111111111111111111011111111110111111111111111
+        111111111101111111111111010111111111111111111111101111111111111111
+        111011011111111111111111111111111101111111111011111111101111111111
+        111111111111110111111111111111111111111111111111111111111111111111
+        111111111111011111111111111111111111011111111111111111111011111111
+        111110111111111111111111111111111111111111101111111101111111110111
+        111111111011111111111111111110011111111111111110111111111101111110
+        101111111111111110111101111111111011111110111111111111111111111111*
 L027642
-        111111111111101111111101011111111111011111111111011110011111111010*
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 L027708 000000000000000000000000000000000000000000000000000000000000000000*
 L027774 000000000000000000000000000000000000000000000000000000000000000000*
 L027840 000000000000000000000000000000000000000000000000000000000000000000*
 L027906 000000000000000000000000000000000000000000000000000000000000000000*
 L027972 000000000000000000000000000000000000000000000000000000000000000000*
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 L028170 000000000000000000000000000000000000000000000000000000000000000000*
 L028236 000000000000000000000000000000000000000000000000000000000000000000*
 L028302 000000000000000000000000000000000000000000000000000000000000000000*
 L028368
-        011111111111111111111111111111111111111111111101111111111111111111*
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 L028500 111111111111111111111111111111111111111111111111111111111111111111*
 L028566 111111111111111111111111111111111111111111111111111111111111111111*
 L028632 111111111111111111111111111111111111111111111111111111111111111111*
@@ -622,11 +625,11 @@ L029226 111111111111111111111111111111111111111111111111111111111111111111*
 L029292 111111111111111111111111111111111111111111111111111111111111111111*
 L029358 111111111111111111111111111111111111111111111111111111111111111111*
 L029424 111111111111111111111111111111111111111111111111111111111111111111*
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 L029820
         000000000000000000000000000000000000000000000000000000000000000000*
 L029886 111111111111111111111111111111111111111111111111111111111111111111*
@@ -641,16 +644,16 @@ L030414 111111111111111111111111111111111111111111111111111111111111111111*
 L030480 111111111111111111111111111111111111111111111111111111111111111111*
 L030546
         000000000000000000000000000000000000000000000000000000000000000000*
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 L030678 111111111111111111111111111111111111111111111111111111111111111111*
 L030744 111111111111111111111111111111111111111111111111111111111111111111*
 L030810 111111111111111111111111111111111111111111111111111111111111111111*
 L030876 111111111111111111111111111111111111111111111111111111111111111111*
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-L031008 111111111111111111111111111111111111111111111111111111111111111111*
-L031074 111111111111111111111111111111111111111111111111111111111111111111*
-L031140 111111111111111111111111111111111111111111111111111111111111111111*
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 L031272
         000000000000000000000000000000000000000000000000000000000000000000*
 L031338 111111111111111111111111111111111111111111111111111111111111111111*
@@ -664,13 +667,13 @@ L031800 111111111111111111111111111111111111111111111111111111111111111111*
 L031866 111111111111111111111111111111111111111111111111111111111111111111*
 L031932 111111111111111111111111111111111111111111111111111111111111111111*
 L031998
-        111111111111111111111111111101111111111111111111111111111111111111*
-L032064 111011101010111001101111111011011110111101101111111111111101111111*
+        111101111111111111111111111111111111111111111111111111111111111111*
+L032064 111111101110111001101111101011011110111101111111111011111001111111*
 L032130 111111111111111111111111111111111111111111111111111111111111111111*
 L032196 111111111111111111111111111111111111111111111111111111111111111111*
 L032262 111111111111111111111111111111111111111111111111111111111111111111*
 L032328 111111111111111111111111111111111111111111111111111111111111111111*
-L032394 111110111111111111111111111111111111111111111111111111111111111111*
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 L032460 111111111111111111111111111111111111111111111111111111111111111111*
 L032526 111111111111111111111111111111111111111111111111111111111111111111*
 L032592 111111111111111111111111111111111111111111111111111111111111111111*
@@ -693,70 +696,70 @@ L033450
 L033582 0010*
 L033586 00100011110000*
 L033600 10101111110011*
-L033614 11011011110100*
-L033628 11110011110010*
-L033642 01111111111001*
-L033656 10101011111111*
-L033670 11011111110000*
-L033684 11111011111111*
-L033698 00110110010000*
-L033712 00000110011110*
-L033726 11011111110001*
+L033614 00010110010100*
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+L033642 01111011111000*
+L033656 00000110011111*
+L033670 11011011110000*
+L033684 11110011111110*
+L033698 01110110010001*
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 L033740 11110011111110*
-L033754 00111011110000*
-L033768 00000110011110*
-L033782 11010111111101*
-L033796 11111111111110*
+L033754 00111011110001*
+L033768 00000110011111*
+L033782 11010111111100*
+L033796 11111111111111*
 NOTE  BLOCK 5 *
 L033810
-        111111011111111111011111111111101111111111111111111111111111111011
-        111111111111111111111111111111111111111111111111111111111111111111
-        111111111111111111111111111111111110111110111111111111110111111111
-        111111111111111110111111101110111111111111111111111111111101111111
-        111111111111111111111010111111111111111111111111111111111111111111
-        111101111111011111111111111111111111111011111111111111111111111111
-        111111110111110111111111111111111111111111111111111101111111111111
-        111111111111111111111111111011111111111111111110110111111111111111
-        101011111111111111111111111111110111111111111111111111111111111111*
+        111011111111111110111111111111111111101101111111111111111111111111
+        111111111111111111101011010111111111111111111111111111111111111110
+        111111111111111111111111111111111111111111111111111111101111111111
+        111111111111111011111111111110101111111111111111111111111101111111
+        111111111110111111111111111111111101111111110111111111111111101111
+        111101111111111111111111111111111111111111011111111111111111111111
+        111111011111111111111111111111111111111111111111111111111111111111
+        111111110111011111111111111111111111111111111111111111111111111111
+        101111111111111111111111111111110111111111111111111001111111111111*
 L034404
         000000000000000000000000000000000000000000000000000000000000000000*
-L034470 111111111111111111111111111111110111111111111111111111111111111111*
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 L034536 000000000000000000000000000000000000000000000000000000000000000000*
 L034602 000000000000000000000000000000000000000000000000000000000000000000*
 L034668 000000000000000000000000000000000000000000000000000000000000000000*
 L034734 000000000000000000000000000000000000000000000000000000000000000000*
-L034800 011111111111111111111111111111111111111111111111111111110111111111*
-L034866 010111111111111111111011111011111111111111111111111111111111111111*
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 L034932 000000000000000000000000000000000000000000000000000000000000000000*
 L034998 000000000000000000000000000000000000000000000000000000000000000000*
 L035064 000000000000000000000000000000000000000000000000000000000000000000*
 L035130
         000000000000000000000000000000000000000000000000000000000000000000*
 L035196 111111111111111111011111111111111111111111111111111111111111111111*
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-L035460 111111111111111111111111111111111111111111111111111111111111111111*
-L035526 111111111111111111111111111111111111111111111111111111111111111111*
-L035592 111111111111111111111111111111111111111111111111111111111111111111*
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 L035856
         000000000000000000000000000000000000000000000000000000000000000000*
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-L036054 010111111111010111111111111011111111110111111101111111111110111111*
-L036120 010111110111110111111111111011111111110111111101111111111110111111*
-L036186 010111111111110110111111111011111111110111111101111111111110111111*
-L036252 111111011111111111111111111111111111111111111111111111111111111111*
-L036318 010111111111110111111111111011111111110111111101111101111110111111*
-L036384 010111111111110111111111111011111110110111111101111111111110111111*
-L036450 000000000000000000000000000000000000000000000000000000000000000000*
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 L036582
         000000000000000000000000000000000000000000000000000000000000000000*
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 L036714 111111111111111111111111111111111111111111111111111111111111111111*
 L036780 111111111111111111111111111111111111111111111111111111111111111111*
 L036846 111111111111111111111111111111111111111111111111111111111111111111*
@@ -768,43 +771,43 @@ L037176 111111111111111111111111111111111111111111111111111111111111111111*
 L037242 111111111111111111111111111111111111111111111111111111111111111111*
 L037308
         000000000000000000000000000000000000000000000000000000000000000000*
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+L037836 011011111111101111110111110111111101111111110111111111111110101110*
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 L038034
         000000000000000000000000000000000000000000000000000000000000000000*
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 L038760
         000000000000000000000000000000000000000000000000000000000000000000*
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 L039090 000000000000000000000000000000000000000000000000000000000000000000*
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 L039222 111111111111111111111111111111111111111111111111111111111111111111*
 L039288 111111111111111111111111111111111111111111111111111111111111111111*
 L039354 111111111111111111111111111111111111111111111111111111111111111111*
 L039420 111111111111111111111111111111111111111111111111111111111111111111*
 L039486
         000000000000000000000000000000000000000000000000000000000000000000*
-L039552 111111111111111111111111111111111111111111111111111111111111111111*
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 L039618 111111111111111111111111111111111111111111111111111111111111111111*
 L039684 111111111111111111111111111111111111111111111111111111111111111111*
 L039750 111111111111111111111111111111111111111111111111111111111111111111*
@@ -819,174 +822,174 @@ L040212
         000000000000000000000000000000000000000000000000000000000000000000*
 L040344 0010*
 L040348 00100110011110*
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 L040432 00010110011110*
-L040446 11101111110011*
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-L040488 11011011111110*
-L040502 11111111111110*
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+L040502 11000011111111*
+L040516 10100110011110*
+L040530 00000110011110*
+L040544 00010110011111*
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 NOTE  BLOCK 6 *
 L040572
-        111111111111111111101111111111111111111111111111111111111111111111
-        111111111111110111111011111110111111111111111111111111111111110111
-        101111111111111111111111111011111111111111111111111111111110111111
-        111111101010111111111110111111111111111111111111111111111111111111
-        111111111111111111111111111111011110111111111111111011111111111111
-        111111111111111111111111111111111111111011111111111111101111111111
-        111110111111101111111111011111111111111111111101011111111111101111
-        111111111111111101111111111111110111011110111111111111111111111111
-        111111111111111111111111111111111111111111101111111111111111111111*
+        111111111111111111111011101111111111111111111111111111111111111111
+        111111111111111111111111111111111111111111111011111111101111111111
+        111101111110111111111111111011111111111111111111111111111101111111
+        111111111111111111111111111111111111111111111110101111111111111110
+        111111111111111111111111111111111110111111111111111111111111111111
+        110111111111111111111111111101111111111111111111111111111111111111
+        011111111111101111111111111111111011111111111111110111111111111111
+        111111101011111001011111111111111111111110111111111111111111011111
+        111111111111111111111111111111111111111111101111111111110111111111*
 L041166
         111111111111111111111111111111111111111111111111111111111111111111*
-L041232 111111111111111111111111111111111110110101011111111111111111111111*
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 L041298 111111111111101111111111111111111111111110011111111111111111111111*
 L041364 000000000000000000000000000000000000000000000000000000000000000000*
 L041430 000000000000000000000000000000000000000000000000000000000000000000*
 L041496 000000000000000000000000000000000000000000000000000000000000000000*
-L041562 111111111111111111111111111111111111111111111111111111111111011111*
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 L041628 000000000000000000000000000000000000000000000000000000000000000000*
 L041694 000000000000000000000000000000000000000000000000000000000000000000*
 L041760 000000000000000000000000000000000000000000000000000000000000000000*
 L041826 000000000000000000000000000000000000000000000000000000000000000000*
 L041892
         111111111111111111111111111111111111111111111111111111111111111111*
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-L042090 111111111111111110111111111111111111111110111111101111111111111111*
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 L042156 000000000000000000000000000000000000000000000000000000000000000000*
 L042222 000000000000000000000000000000000000000000000000000000000000000000*
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 L042420 000000000000000000000000000000000000000000000000000000000000000000*
 L042486 000000000000000000000000000000000000000000000000000000000000000000*
 L042552 000000000000000000000000000000000000000000000000000000000000000000*
 L042618
         000000000000000000000000000000000000000000000000000000000000000000*
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-L042882 111111101111111111111011111111111011111111111111110111111111111111*
-L042948 111111111111111111111101111111111111111111111111111011111111111111*
-L043014 111111011111111111111111111111110111111111111111111111111111111111*
-L043080 111111111111111111110101111111111111111111111111110111111111111111*
-L043146 111111111111111111111011111111111011111111111111110111111111111111*
-L043212 111111011111111111111111111111111111111111111111111011111111111111*
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 L043278 000000000000000000000000000000000000000000000000000000000000000000*
 L043344
         000000000000000000000000000000000000000000000000000000000000000000*
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 L043608 000000000000000000000000000000000000000000000000000000000000000000*
 L043674 000000000000000000000000000000000000000000000000000000000000000000*
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 L043806 000000000000000000000000000000000000000000000000000000000000000000*
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 L044004 000000000000000000000000000000000000000000000000000000000000000000*
 L044070
-        111111111111111111111111101111011111111110111111111111111111111111*
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 L044136 111111111111111111111111111111111111111111101111111111111111111111*
-L044202 111111111111111111111111110111111111110101111111111111111111111111*
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 L044268 111111111111111101111111111111111111111110111111111111111111111111*
 L044334 000000000000000000000000000000000000000000000000000000000000000000*
 L044400 000000000000000000000000000000000000000000000000000000000000000000*
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 L044598 000000000000000000000000000000000000000000000000000000000000000000*
 L044664 000000000000000000000000000000000000000000000000000000000000000000*
 L044730 000000000000000000000000000000000000000000000000000000000000000000*
 L044796
-        111111111111111111111111101111111111111110111111111111111111111111*
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-L045258 111111111111111111111111111111111111111111111111111111111111111111*
-L045324 111111111111111111111111111111111111111111111111111111111111111111*
-L045390 111111111111111111111111111111111111111111111111111111111111111111*
-L045456 111111111111111111111111111111111111111111111111111111111111111111*
+        111111111011111111111111111111111111111110111111111111111111111111*
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 L045522
-        111111111111111111111111111111011111111110111111111111111111111111*
-L045588 111111111011111111111111111111111111111111111111111111111101111111*
-L045654 111111111111111111111111111111111111111111111111111111111111111111*
-L045720 111111111111111111111111111111111111111111111111111111111111111111*
-L045786 111111111111111111111111111111111111111111111111111111111111111111*
-L045852 111111111111111111111111111111111111111111111111111111111111111111*
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 L045918 111111111111111111111111111111111111111111101111111111111111111111*
-L045984 111111111111111111011111111111111111011111111111111111111111111111*
-L046050 111111111111111111011111111111111111111111111111111111111111111011*
-L046116 101111111111111111111111111101111111101111111111111111101111110111*
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 L046182 000000000000000000000000000000000000000000000000000000000000000000*
 L046248
         000000000000000000000000000000000000000000000000000000000000000000*
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 L046974
         000000000000000000000000000000000000000000000000000000000000000000
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 L047106 0010*
 L047110 11100110011000*
 L047124 00100110011110*
-L047138 10100110010100*
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 L047180 10100110010011*
-L047194 11100110010000*
-L047208 01100110010010*
-L047222 10100110010000*
-L047236 10100110010011*
-L047250 00010110010101*
-L047264 11101111110011*
-L047278 00110011110010*
-L047292 10100110010010*
-L047306 00010110010000*
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+L047278 00100011110010*
+L047292 10100110010011*
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 NOTE  BLOCK 7 *
 L047334
-        111111111011111111110111111111111111111111111111111111111111111111
-        111111111111111111111111111111111111111111111111111011111111111111
-        111111111111111111111111111111111111111111111111101111110110111111
-        111111111111011110111111101111111111111111111111111111111111111011
-        111111111111111111111111111111011111111111111111111111111111111111
-        111111111111111111011111111111111111011111010111111111011111111111
-        111111011110110111111111111111111001111111111111111101111111111111
-        111111111111111111111111111011111111111010111111111111111111111111
-        101010111111111111111101111110111111111111111110111111111111111111*
+        111111111111111111111111111111111111111111111111111011111011111111
+        111111111111111111111110111111111111111111011111111111111111111111
+        111110111111111111111111111111111110111111111111111111111111111111
+        111111101111111111111111101111111111111111111110111111101110111111
+        111111111111111111111011111111111111111111111111111111111111111011
+        111111111111011011111111111111011111111111111111111111111111111101
+        111111110110111101111111111111111111011111111111111101111111111111
+        111111111111111111101111111011111111111110110111111111111111111111
+        101011111111111111111111111110111011110111111111111111111111101111*
 L047928
         000000000000000000000000000000000000000000000000000000000000000000*
-L047994 011111111111011111111111111111111111111111101110111111111011111111*
-L048060 011111111111011111111011111111111111111111111110111111111011111111*
-L048126 011111111111111111111111111111111111111111111111111011110111111111*
+L047994 011101111111111111111111111111111111111111111111111111111110101011*
+L048060 011101111111111111111011111111111111111111111111111111111110101111*
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 L048192 000000000000000000000000000000000000000000000000000000000000000000*
 L048258 000000000000000000000000000000000000000000000000000000000000000000*
-L048324 111111111111111101111110011111111110011011111111011110101111111111*
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 L048390 000000000000000000000000000000000000000000000000000000000000000000*
 L048456 000000000000000000000000000000000000000000000000000000000000000000*
 L048522 000000000000000000000000000000000000000000000000000000000000000000*
 L048588 000000000000000000000000000000000000000000000000000000000000000000*
 L048654
         000000000000000000000000000000000000000000000000000000000000000000*
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 L048786 111111111111111111111111111111111111111111111111111111111111111111*
 L048852 111111111111111111111111111111111111111111111111111111111111111111*
 L048918 111111111111111111111111111111111111111111111111111111111111111111*
@@ -998,18 +1001,18 @@ L049248 111111111111111111111111111111111111111111111111111111111111111111*
 L049314 111111111111111111111111111111111111111111111111111111111111111111*
 L049380
         111111111111111111111111111111111111111111111111111111111111111111*
-L049446 011111111111111111111111111111111111101111111111111111111111111111*
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-L049578 000000000000000000000000000000000000000000000000000000000000000000*
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 L049644 000000000000000000000000000000000000000000000000000000000000000000*
 L049710 000000000000000000000000000000000000000000000000000000000000000000*
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 L049842 111111111111111111111111111111111111111111111111111111111111111111*
 L049908 111111111111111111111111111111111111111111111111111111111111111111*
 L049974 111111111111111111111111111111111111111111111111111111111111111111*
 L050040 111111111111111111111111111111111111111111111111111111111111111111*
 L050106
-        111111111111111011111111111111011111111110111111111111111111111111*
+        111111011111111111111111111011111111111110111111111111111111111111*
 L050172 111111111111111111111111111101111111111111111111111111111111111111*
 L050238 111111111111111111111111111111111111111111111111111111111111111111*
 L050304 111111111111111111111111111111111111111111111111111111111111111111*
@@ -1021,19 +1024,19 @@ L050634 111111111111111111111111111111111111111111111111111111111111111111*
 L050700 111111111111111111111111111111111111111111111111111111111111111111*
 L050766 111111111111111111111111111111111111111111111111111111111111111111*
 L050832
-        111111111111110111111111111111111111111111111111111111111111111111*
-L050898 111110111111111111101111111111111111111111111111111111111111111111*
+        111111111111111111111111110111111111111111111111111111111111111111*
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 L050964 111111111111111111111111111111111111111111111111111111111111111111*
 L051030 111111111111111111111111111111111111111111111111111111111111111111*
 L051096 111111111111111111111111111111111111111111111111111111111111111111*
 L051162 111111111111111111111111111111111111111111111111111111111111111111*
-L051228 011111011011111111111111111111111111111111110111111111111111111111*
-L051294 011111011111111111111111111111110111111111110111111111111111111111*
-L051360 011111011111111111111111111101111111111111111111111111111111111111*
-L051426 010111111110111111111111111011111111111111111111111111111111111111*
+L051228 011111111111111101111111111111111111011111111111111111111011111111*
+L051294 011111111111111101111111111111111111011111110111111111111111111111*
+L051360 011111111111111111111111111101111111011111111111111111111111111111*
+L051426 010111111110111011111111111111111111111111111111111111111111111111*
 L051492 000000000000000000000000000000000000000000000000000000000000000000*
 L051558
-        111111111111111111111111111111011111111101111111111111111111111111*
+        111111011111111111111111111111111111111101111111111111111111111111*
 L051624 111111111111111111111111111111111111111111111111111111111111111111*
 L051690 111111111111111111111111111111111111111111111111111111111111111111*
 L051756 111111111111111111111111111111111111111111111111111111111111111111*
@@ -1045,13 +1048,13 @@ L052086 111111111111111111111111111111111111111111111111111111111111111111*
 L052152 111111111111111111111111111111111111111111111111111111111111111111*
 L052218 111111111111111111111111111111111111111111111111111111111111111111*
 L052284
-        111111111111111011111111111111111111111110111111111111111111111111*
-L052350 111111111111111111111111111111111111111111111111111111111110110111*
+        111111111111111111111111111011111111111110111111111111111111111111*
+L052350 111111111111111111111111111111111111111111111110110111111111111111*
 L052416 111111111111111111111111111111111111111111111111111111111111111111*
 L052482 111111111111111111111111111111111111111111111111111111111111111111*
 L052548 111111111111111111111111111111111111111111111111111111111111111111*
 L052614 111111111111111111111111111111111111111111111111111111111111111111*
-L052680 011111111111111111111111111111111111111110111111111111111111111111*
+L052680 011111111111111111101111111111111111111111111111111111111111111111*
 L052746 111111111111111111111111111111111111111111111111111111111111111111*
 L052812 111111111111111111111111111111111111111111111111111111111111111111*
 L052878 111111111111111111111111111111111111111111111111111111111111111111*
@@ -1076,7 +1079,7 @@ L053872 11100110011100*
 L053886 01101011110010*
 L053900 00010110010001*
 L053914 11101011110011*
-L053928 11100110010000*
+L053928 10100110010000*
 L053942 01000110011110*
 L053956 00010110010101*
 L053970 11100011110011*
@@ -1107,6 +1110,6 @@ E1
 10000010
 1
 *
-C6247*
+CD907*
 U00000000000000000000000000000000*
-E062
+FFAA
diff --git a/Logic/68030_tk.l0 b/Logic/68030_tk.l0
new file mode 100644
index 0000000..0bb3cee
--- /dev/null
+++ b/Logic/68030_tk.l0
@@ -0,0 +1 @@
+ -ck Min -ce On -ar On -ap On -oe On -split 16 -clust 5 -xor on -speed -ifb yes -sr no -device M4A5
diff --git a/Logic/68030_tk.l2v b/Logic/68030_tk.l2v
new file mode 100644
index 0000000..e69de29
diff --git a/Logic/68030_tk.lco b/Logic/68030_tk.lco
new file mode 100644
index 0000000..738c901
--- /dev/null
+++ b/Logic/68030_tk.lco
@@ -0,0 +1,257 @@
+[DEVICE]
+Family = M4A5;
+PartType = M4A5-128/64;
+Package = 100TQFP;
+PartNumber = M4A5-128/64-10VC;
+Speed = -10;
+Operating_condition = COM;
+EN_Segment = No;
+Pin_MC_1to1 = No;
+EN_PinReserve_IO = Yes;
+EN_PinReserve_BIDIR = Yes;
+Voltage = 5.0;
+
+[REVISION]
+RCS = "$Revision: 1.2 $";
+Parent = m4a5.lci;
+SDS_File = m4a5.sds;
+Design = 68030_tk.tt4;
+DATE = 1/24/16;
+TIME = 16:20:59;
+Source_Format = Pure_VHDL;
+Type = TT2;
+Pre_Fit_Time = 1;
+
+[IGNORE ASSIGNMENTS]
+Pin_Assignments = No;
+Pin_Keep_Block = No;
+Pin_Keep_Segment = No;
+Group_Assignments = No;
+Macrocell_Assignments = No;
+Macrocell_Keep_Block = No;
+Macrocell_Keep_Segment = No;
+Pin_Reservation = No;
+Block_Reservation = No;
+Segment_Reservation = No;
+Timing_Constraints = No;
+
+[CLEAR ASSIGNMENTS]
+Pin_Assignments = No;
+Pin_Keep_Block = No;
+Pin_Keep_Segment = No;
+Group_Assignments = No;
+Macrocell_Assignments = No;
+Macrocell_Keep_Block = No;
+Macrocell_Keep_Segment = No;
+Pin_Reservation = No;
+Block_Reservation = No;
+Segment_Reservation = No;
+Timing_Constraints = No;
+
+[BACKANNOTATE ASSIGNMENTS]
+Pin_Block = No;
+Pin_Macrocell_Block = No;
+Routing = No;
+
+[GLOBAL CONSTRAINTS]
+Max_PTerm_Split = 16;
+Max_PTerm_Collapse = 16;
+Max_Pin_Percent = 100;
+Max_Macrocell_Percent = 100;
+Max_GLB_Input_Percent = 100;
+Max_Seg_In_Percent = 100;
+Logic_Reduction = Yes;
+XOR_Synthesis = Yes;
+DT_Synthesis = Yes;
+Node_Collapse = Yes;
+Run_Time = 0;
+Set_Reset_Dont_Care = No;
+Clock_Optimize = No;
+In_Reg_Optimize = Yes;
+Balanced_Partitioning = Yes;
+Device_max_fanin = 33;
+Device_max_pterms = 20;
+Usercode = 0;
+Usercode_Format = Hex;
+
+[LOCATION ASSIGNMENTS]
+Layer = OFF;
+SIZE_1_ = pin,79,-,H,-;
+A_31_ = pin,4,-,B,-;
+IPL_2_ = pin,68,-,G,-;
+FC_1_ = pin,58,-,F,-;
+IPL_1_ = pin,56,-,F,-;
+AS_030 = pin,82,-,H,-;
+IPL_0_ = pin,67,-,G,-;
+AS_000 = pin,42,-,E,-;
+FC_0_ = pin,57,-,F,-;
+DS_030 = pin,98,-,A,-;
+UDS_000 = pin,32,-,D,-;
+LDS_000 = pin,31,-,D,-;
+A1 = pin,60,-,F,-;
+nEXP_SPACE = pin,14,-,-,-;
+BERR = pin,41,-,E,-;
+BG_030 = pin,21,-,C,-;
+BGACK_000 = pin,28,-,D,-;
+CLK_030 = pin,64,-,-,-;
+CLK_000 = pin,11,-,-,-;
+CLK_OSZI = pin,61,-,-,-;
+CLK_EXP = pin,10,-,B,-;
+FPU_CS = pin,78,-,H,-;
+FPU_SENSE = pin,91,-,A,-;
+DTACK = pin,30,-,D,-;
+AVEC = pin,92,-,A,-;
+E = pin,66,-,G,-;
+VPA = pin,36,-,-,-;
+RST = pin,86,-,-,-;
+RESET = pin,3,-,B,-;
+AMIGA_ADDR_ENABLE = pin,33,-,D,-;
+AMIGA_BUS_DATA_DIR = pin,48,-,E,-;
+SIZE_0_ = pin,70,-,G,-;
+AMIGA_BUS_ENABLE_LOW = pin,20,-,C,-;
+A_30_ = pin,5,-,B,-;
+AMIGA_BUS_ENABLE_HIGH = pin,34,-,D,-;
+A_29_ = pin,6,-,B,-;
+CIIN = pin,47,-,E,-;
+A_28_ = pin,15,-,C,-;
+A_27_ = pin,16,-,C,-;
+A_26_ = pin,17,-,C,-;
+A_25_ = pin,18,-,C,-;
+A_24_ = pin,19,-,C,-;
+A_23_ = pin,85,-,H,-;
+A_22_ = pin,84,-,H,-;
+A_21_ = pin,94,-,A,-;
+A_20_ = pin,93,-,A,-;
+A_19_ = pin,97,-,A,-;
+A_18_ = pin,95,-,A,-;
+A_17_ = pin,59,-,F,-;
+A_16_ = pin,96,-,A,-;
+IPL_030_2_ = pin,9,-,B,-;
+IPL_030_1_ = pin,7,-,B,-;
+IPL_030_0_ = pin,8,-,B,-;
+RW_000 = pin,80,-,H,-;
+A0 = pin,69,-,G,-;
+BG_000 = pin,29,-,D,-;
+BGACK_030 = pin,83,-,H,-;
+CLK_DIV_OUT = pin,65,-,G,-;
+DSACK1 = pin,81,-,H,-;
+VMA = pin,35,-,D,-;
+RW = pin,71,-,G,-;
+cpu_est_0_ = node,-,-,D,10;
+cpu_est_1_ = node,-,-,D,6;
+cpu_est_2_ = node,-,-,D,13;
+cpu_est_3_ = node,-,-,D,2;
+inst_AS_000_INT = node,-,-,B,13;
+SM_AMIGA_5_ = node,-,-,F,4;
+inst_AMIGA_BUS_ENABLE_DMA_LOW = node,-,-,B,9;
+inst_AS_030_D0 = node,-,-,H,13;
+inst_nEXP_SPACE_D0reg = node,-,-,H,5;
+inst_AS_030_000_SYNC = node,-,-,C,5;
+inst_BGACK_030_INT_D = node,-,-,E,8;
+inst_AS_000_DMA = node,-,-,A,12;
+inst_DS_000_DMA = node,-,-,A,9;
+CYCLE_DMA_0_ = node,-,-,A,6;
+CYCLE_DMA_1_ = node,-,-,A,2;
+SIZE_DMA_0_ = node,-,-,G,2;
+SIZE_DMA_1_ = node,-,-,G,13;
+inst_VPA_D = node,-,-,C,1;
+inst_UDS_000_INT = node,-,-,A,5;
+inst_LDS_000_INT = node,-,-,A,1;
+inst_CLK_OUT_PRE_D = node,-,-,D,3;
+inst_DTACK_D0 = node,-,-,A,3;
+inst_RESET_OUT = node,-,-,G,5;
+inst_CLK_OUT_PRE_50 = node,-,-,E,5;
+N_210_i = node,-,-,C,9;
+inst_CLK_OUT_PRE_25 = node,-,-,G,6;
+inst_CLK_000_D1 = node,-,-,C,8;
+inst_CLK_000_D0 = node,-,-,D,9;
+inst_CLK_000_PE = node,-,-,F,0;
+inst_CLK_OUT_EXP_INT = node,-,-,E,2;
+CLK_000_P_SYNC_9_ = node,-,-,F,3;
+inst_CLK_000_NE = node,-,-,G,9;
+CLK_000_N_SYNC_11_ = node,-,-,H,6;
+IPL_D0_0_ = node,-,-,B,15;
+IPL_D0_1_ = node,-,-,B,11;
+IPL_D0_2_ = node,-,-,B,7;
+inst_CLK_000_NE_D0 = node,-,-,D,14;
+SM_AMIGA_0_ = node,-,-,F,1;
+inst_AMIGA_BUS_ENABLE_DMA_HIGH = node,-,-,B,5;
+SM_AMIGA_4_ = node,-,-,F,9;
+inst_DS_000_ENABLE = node,-,-,C,12;
+RST_DLY_0_ = node,-,-,G,14;
+RST_DLY_1_ = node,-,-,G,10;
+RST_DLY_2_ = node,-,-,G,3;
+CLK_000_P_SYNC_0_ = node,-,-,B,3;
+CLK_000_P_SYNC_1_ = node,-,-,B,14;
+CLK_000_P_SYNC_2_ = node,-,-,F,14;
+CLK_000_P_SYNC_3_ = node,-,-,F,10;
+CLK_000_P_SYNC_4_ = node,-,-,E,13;
+CLK_000_P_SYNC_5_ = node,-,-,B,10;
+CLK_000_P_SYNC_6_ = node,-,-,F,6;
+CLK_000_P_SYNC_7_ = node,-,-,B,6;
+CLK_000_P_SYNC_8_ = node,-,-,G,15;
+CLK_000_N_SYNC_0_ = node,-,-,G,11;
+CLK_000_N_SYNC_1_ = node,-,-,F,2;
+CLK_000_N_SYNC_2_ = node,-,-,F,13;
+CLK_000_N_SYNC_3_ = node,-,-,D,15;
+CLK_000_N_SYNC_4_ = node,-,-,D,11;
+CLK_000_N_SYNC_5_ = node,-,-,A,14;
+CLK_000_N_SYNC_6_ = node,-,-,A,10;
+CLK_000_N_SYNC_7_ = node,-,-,G,7;
+CLK_000_N_SYNC_8_ = node,-,-,B,2;
+CLK_000_N_SYNC_9_ = node,-,-,D,7;
+CLK_000_N_SYNC_10_ = node,-,-,H,2;
+SM_AMIGA_6_ = node,-,-,C,4;
+inst_CLK_030_H = node,-,-,A,13;
+SM_AMIGA_1_ = node,-,-,A,8;
+SM_AMIGA_3_ = node,-,-,F,5;
+SM_AMIGA_2_ = node,-,-,F,12;
+SM_AMIGA_i_7_ = node,-,-,F,8;
+CIIN_0 = node,-,-,E,9;
+
+[GROUP ASSIGNMENTS]
+Layer = OFF;
+
+[RESOURCE RESERVATIONS]
+Layer = OFF;
+
+[SLEWRATE]
+Default = SLOW;
+FAST =  CLK_DIV_OUT,CLK_EXP,FPU_CS,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH;
+
+[PULLUP]
+Default = Up;
+
+[NETLIST/DELAY FORMAT]
+Delay_File = SDF;
+Netlist = VHDL;
+
+[OSM BYPASS]
+
+[FITTER REPORT FORMAT]
+Fitter_Options = Yes;
+Pinout_Diagram = No;
+Pinout_Listing = Yes;
+Detailed_Block_Segment_Summary = Yes;
+Input_Signal_List = Yes;
+Output_Signal_List = Yes;
+Bidir_Signal_List = Yes;
+Node_Signal_List = Yes;
+Signal_Fanout_List = Yes;
+Block_Segment_Fanin_List = Yes;
+Postfit_Eqn = Yes;
+Prefit_Eqn = Yes;
+Page_Break = Yes;
+
+[POWER]
+Powerlevel =  Low,High;
+Default = High;
+Low =  H,G,F,E,D,C,B,A;
+Type = GLB;
+
+[SOURCE CONSTRAINT OPTION]
+
+[TIMING ANALYZER]
+Last_source=;
+Last_source_type=Fmax;
+
diff --git a/Logic/68030_tk.out b/Logic/68030_tk.out
new file mode 100644
index 0000000..9ab8bd6
--- /dev/null
+++ b/Logic/68030_tk.out
@@ -0,0 +1,1614 @@
+
+141 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  40       BERR  5   -1   4   4     1  2        5     7  40   -1   1   0   21
+  79     RW_000  5  363   7   3  0           4     6     79   -1   3   0   21
+  41     AS_000  5   -1   4   3  0           4        7  41   -1   1   0   21
+  68         A0  5  364   6   2  0                 6     68   -1   3   0   21
+  70         RW  5  372   6   2     1                 7  70   -1   2   0   21
+  81     AS_030  5   -1   7   2              4        7  81   -1   1   0   21
+  31    UDS_000  5   -1   3   2  0                 6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   2  0                 6     30   -1   1   0   21
+  97     DS_030  5   -1   0   1           3              97   -1   1   0   21
+  78    SIZE_1_  5   -1   7   1  0                       78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1  0                       69   -1   1   0   21
+   8 IPL_030_2_  5  362   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  366   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  365   1   0                           6   -1  10   0   21
+  65          E  5  370   6   0                          65   -1   5   0   21
+  80     DSACK1  5  369   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  368   7   0                          82   -1   3   0   21
+  34        VMA  5  371   3   0                          34   -1   3   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  367   3   0                          28   -1   2   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+   2      RESET  0        1   0                           2   -1   1   0   21
+ 368 RN_BGACK_030  3   82   7   7  0     2  3  4  5  6  7  82   -1   3   0   21
+ 314 inst_RESET_OUT  3   -1   3   6  0  1     3  4     6  7  -1   -1   2   0   21
+ 299 inst_nEXP_SPACE_D0reg  3   -1   1   6  0        3  4  5  6  7  -1   -1   1   0   21
+ 318 inst_CLK_000_PE  3   -1   2   5  0     2  3     5     7  -1   -1   1   0   21
+ 298 inst_AS_030_D0  3   -1   7   5     1     3  4  5     7  -1   -1   1   0   21
+ 317 inst_CLK_000_D0  3   -1   0   4     1     3  4  5        -1   -1   1   0   21
+ 360 SM_AMIGA_i_7_  3   -1   5   3           3     5     7  -1   -1  14   0   21
+ 370       RN_E  3   65   6   3        2  3        6     65   -1   5   0   21
+ 326 SM_AMIGA_3_  3   -1   2   3     1  2        5        -1   -1   5   0   21
+ 294 cpu_est_1_  3   -1   6   3        2  3        6     -1   -1   5   0   21
+ 322 cpu_est_2_  3   -1   2   3        2  3        6     -1   -1   4   0   21
+ 330 SM_AMIGA_6_  3   -1   5   3  0              5  6     -1   -1   3   0   21
+ 296 SM_AMIGA_5_  3   -1   5   3     1           5     7  -1   -1   3   0   21
+ 293 cpu_est_0_  3   -1   6   3        2  3        6     -1   -1   2   0   21
+ 327 inst_CLK_000_NE_D0  3   -1   0   3        2        5  6     -1   -1   1   0   21
+ 320 inst_CLK_000_NE  3   -1   0   3  0        3     5        -1   -1   1   0   21
+ 302 inst_BGACK_030_INT_D  3   -1   7   3        2        5  6     -1   -1   1   0   21
+ 303 inst_AS_000_DMA  3   -1   0   2  0                    7  -1   -1   7   0   21
+ 357 SM_AMIGA_2_  3   -1   2   2        2        5        -1   -1   4   0   21
+ 311 inst_LDS_000_INT  3   -1   0   2  0        3              -1   -1   4   0   21
+ 371     RN_VMA  3   34   3   2        2  3              34   -1   3   0   21
+ 358 inst_DS_000_ENABLE  3   -1   1   2     1     3              -1   -1   3   0   21
+ 356 SM_AMIGA_4_  3   -1   5   2        2        5        -1   -1   3   0   21
+ 355 SM_AMIGA_1_  3   -1   5   2                 5     7  -1   -1   3   0   21
+ 310 inst_UDS_000_INT  3   -1   6   2           3        6     -1   -1   3   0   21
+ 308 SIZE_DMA_1_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 307 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 329 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   6   2           3        6     -1   -1   2   0   21
+ 328 SM_AMIGA_0_  3   -1   5   2                 5     7  -1   -1   2   0   21
+ 295 inst_AS_000_INT  3   -1   1   2     1        4           -1   -1   2   0   21
+ 316 inst_CLK_000_D1  3   -1   4   2     1           5        -1   -1   1   0   21
+ 309 inst_VPA_D  3   -1   3   2        2  3              -1   -1   1   0   21
+ 300 inst_DS_030_D0  3   -1   3   2  0                 6     -1   -1   1   0   21
+ 366 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 365 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 362 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 304 inst_DS_000_DMA  3   -1   0   1  0                       -1   -1   9   0   21
+ 354 inst_CLK_030_H  3   -1   0   1  0                       -1   -1   8   0   21
+ 301 inst_AS_030_000_SYNC  3   -1   5   1                 5        -1   -1   7   0   21
+ 369  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 332 RST_DLY_1_  3   -1   3   1           3              -1   -1   4   0   21
+ 364      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 363  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 331 RST_DLY_0_  3   -1   3   1           3              -1   -1   3   0   21
+ 306 CYCLE_DMA_1_  3   -1   0   1  0                       -1   -1   3   0   21
+ 372      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 367  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 361     CIIN_0  3   -1   4   1              4           -1   -1   2   0   21
+ 359     N_61_i  3   -1   2   1                 5        -1   -1   2   0   21
+ 333 RST_DLY_2_  3   -1   3   1           3              -1   -1   2   0   21
+ 305 CYCLE_DMA_0_  3   -1   0   1  0                       -1   -1   2   0   21
+ 297 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   2   1        2                 -1   -1   2   0   21
+ 353 CLK_000_N_SYNC_10_  3   -1   7   1                       7  -1   -1   1   0   21
+ 352 CLK_000_N_SYNC_9_  3   -1   0   1                       7  -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_8_  3   -1   2   1  0                       -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_7_  3   -1   6   1        2                 -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_6_  3   -1   2   1                    6     -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_5_  3   -1   3   1        2                 -1   -1   1   0   21
+ 347 CLK_000_N_SYNC_4_  3   -1   2   1           3              -1   -1   1   0   21
+ 346 CLK_000_N_SYNC_3_  3   -1   6   1        2                 -1   -1   1   0   21
+ 345 CLK_000_N_SYNC_2_  3   -1   1   1                    6     -1   -1   1   0   21
+ 344 CLK_000_N_SYNC_1_  3   -1   1   1     1                    -1   -1   1   0   21
+ 343 CLK_000_N_SYNC_0_  3   -1   1   1     1                    -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_8_  3   -1   1   1  0                       -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_7_  3   -1   5   1     1                    -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_6_  3   -1   5   1                 5        -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_5_  3   -1   1   1                 5        -1   -1   1   0   21
+ 338 CLK_000_P_SYNC_4_  3   -1   4   1     1                    -1   -1   1   0   21
+ 337 CLK_000_P_SYNC_3_  3   -1   2   1              4           -1   -1   1   0   21
+ 336 CLK_000_P_SYNC_2_  3   -1   2   1        2                 -1   -1   1   0   21
+ 335 CLK_000_P_SYNC_1_  3   -1   6   1        2                 -1   -1   1   0   21
+ 334 CLK_000_P_SYNC_0_  3   -1   5   1                    6     -1   -1   1   0   21
+ 325  IPL_D0_2_  3   -1   2   1     1                    -1   -1   1   0   21
+ 324  IPL_D0_1_  3   -1   1   1     1                    -1   -1   1   0   21
+ 323  IPL_D0_0_  3   -1   2   1     1                    -1   -1   1   0   21
+ 321 CLK_000_N_SYNC_11_  3   -1   7   1  0                       -1   -1   1   0   21
+ 319 CLK_000_P_SYNC_9_  3   -1   0   1        2                 -1   -1   1   0   21
+ 315 inst_CLK_OUT_PRE_50  3   -1   4   1              4           -1   -1   1   0   21
+ 313 inst_DTACK_D0  3   -1   0   1        2                 -1   -1   1   0   21
+ 312 inst_CLK_OUT_PRE_D  3   -1   4   1                       7  -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   7  0  1  2  3     5  6  7  85   -1
+  96      A_19_  1   -1  -1   3              4  5     7  96   -1
+  95      A_16_  1   -1  -1   3              4  5     7  95   -1
+  94      A_18_  1   -1  -1   3              4  5     7  94   -1
+  63    CLK_030  1   -1  -1   3  0  1                 7  63   -1
+  58      A_17_  1   -1  -1   3              4  5     7  58   -1
+  57      FC_1_  1   -1  -1   3              4  5     7  57   -1
+  56      FC_0_  1   -1  -1   3              4  5     7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  67     IPL_2_  1   -1  -1   2     1  2                 67   -1
+  66     IPL_0_  1   -1  -1   2     1  2                 66   -1
+  59         A1  1   -1  -1   2        2           6     59   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  93      A_21_  1   -1  -1   1              4           93   -1
+  92      A_20_  1   -1  -1   1              4           92   -1
+  84      A_23_  1   -1  -1   1              4           84   -1
+  83      A_22_  1   -1  -1   1              4           83   -1
+  55     IPL_1_  1   -1  -1   1     1                    55   -1
+  35        VPA  1   -1  -1   1           3              35   -1
+  29      DTACK  1   -1  -1   1  0                       29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1     1                    13   -1
+  10    CLK_000  1   -1  -1   1  0                       10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
+141 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  40       BERR  5   -1   4   5  0  1  2        5     7  40   -1   1   0   21
+  79     RW_000  5  363   7   3  0           4     6     79   -1   3   0   21
+  41     AS_000  5   -1   4   3  0           4        7  41   -1   1   0   21
+  70         RW  5  372   6   2     1                 7  70   -1   2   0   21
+  81     AS_030  5   -1   7   2              4        7  81   -1   1   0   21
+  31    UDS_000  5   -1   3   2  0                 6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   2  0                 6     30   -1   1   0   21
+  68         A0  5  366   6   1        2                 68   -1   3   0   21
+  97     DS_030  5   -1   0   1           3              97   -1   1   0   21
+  78    SIZE_1_  5   -1   7   1        2                 78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1        2                 69   -1   1   0   21
+   8 IPL_030_2_  5  362   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  365   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  364   1   0                           6   -1  10   0   21
+  65          E  5  370   6   0                          65   -1   5   0   21
+  80     DSACK1  5  369   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  368   7   0                          82   -1   3   0   21
+  34        VMA  5  371   3   0                          34   -1   3   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  367   3   0                          28   -1   2   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+   2      RESET  0        1   0                           2   -1   1   0   21
+ 368 RN_BGACK_030  3   82   7   7  0     2  3  4  5  6  7  82   -1   3   0   21
+ 315 inst_RESET_OUT  3   -1   6   6  0  1     3  4     6  7  -1   -1   2   0   21
+ 321 inst_CLK_000_NE  3   -1   0   6  0  1  2  3     5  6     -1   -1   1   0   21
+ 300 inst_nEXP_SPACE_D0reg  3   -1   5   6  0        3  4  5  6  7  -1   -1   1   0   21
+ 319 inst_CLK_000_PE  3   -1   3   5  0     2  3     5     7  -1   -1   1   0   21
+ 299 inst_AS_030_D0  3   -1   7   5     1     3  4  5     7  -1   -1   1   0   21
+ 356 SM_AMIGA_1_  3   -1   2   4  0     2        5     7  -1   -1   3   0   21
+ 297 SM_AMIGA_5_  3   -1   5   4     1  2        5     7  -1   -1   3   0   21
+ 329 SM_AMIGA_0_  3   -1   0   4  0     2        5     7  -1   -1   2   0   21
+ 360 SM_AMIGA_i_7_  3   -1   2   3           3     5     7  -1   -1  14   0   21
+ 370       RN_E  3   65   6   3        2  3        6     65   -1   5   0   21
+ 327 SM_AMIGA_3_  3   -1   2   3     1  2        5        -1   -1   5   0   21
+ 295 cpu_est_1_  3   -1   3   3        2  3        6     -1   -1   5   0   21
+ 323 cpu_est_2_  3   -1   2   3        2  3        6     -1   -1   4   0   21
+ 294 cpu_est_0_  3   -1   3   3        2  3        6     -1   -1   2   0   21
+ 328 inst_CLK_000_NE_D0  3   -1   3   3        2  3        6     -1   -1   1   0   21
+ 318 inst_CLK_000_D0  3   -1   1   3           3  4  5        -1   -1   1   0   21
+ 313 inst_CLK_OUT_PRE_D  3   -1   0   3     1              6  7  -1   -1   1   0   21
+ 303 inst_BGACK_030_INT_D  3   -1   7   3  0              5  6     -1   -1   1   0   21
+ 304 inst_AS_000_DMA  3   -1   0   2  0                    7  -1   -1   7   0   21
+ 358 SM_AMIGA_2_  3   -1   2   2        2        5        -1   -1   4   0   21
+ 333 RST_DLY_1_  3   -1   1   2     1              6     -1   -1   4   0   21
+ 312 inst_LDS_000_INT  3   -1   2   2        2  3              -1   -1   4   0   21
+ 371     RN_VMA  3   34   3   2        2  3              34   -1   3   0   21
+ 359 inst_DS_000_ENABLE  3   -1   1   2     1     3              -1   -1   3   0   21
+ 357 SM_AMIGA_4_  3   -1   5   2        2        5        -1   -1   3   0   21
+ 332 RST_DLY_0_  3   -1   1   2     1              6     -1   -1   3   0   21
+ 331 SM_AMIGA_6_  3   -1   5   2        2        5        -1   -1   3   0   21
+ 311 inst_UDS_000_INT  3   -1   2   2        2  3              -1   -1   3   0   21
+ 309 SIZE_DMA_1_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 308 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 334 RST_DLY_2_  3   -1   6   2     1              6     -1   -1   2   0   21
+ 330 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   0   2  0        3              -1   -1   2   0   21
+ 298 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   0   2  0     2                 -1   -1   2   0   21
+ 296 inst_AS_000_INT  3   -1   1   2     1        4           -1   -1   2   0   21
+ 317 inst_CLK_000_D1  3   -1   4   2              4  5        -1   -1   1   0   21
+ 316 inst_CLK_OUT_PRE_50  3   -1   3   2  0        3              -1   -1   1   0   21
+ 310 inst_VPA_D  3   -1   3   2        2  3              -1   -1   1   0   21
+ 365 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 364 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 362 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 305 inst_DS_000_DMA  3   -1   0   1  0                       -1   -1   9   0   21
+ 355 inst_CLK_030_H  3   -1   0   1  0                       -1   -1   8   0   21
+ 302 inst_AS_030_000_SYNC  3   -1   5   1                 5        -1   -1   7   0   21
+ 369  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 293      N_301  3   -1   5   1        2                 -1   -1   4   0   21
+ 366      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 363  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 307 CYCLE_DMA_1_  3   -1   0   1  0                       -1   -1   3   0   21
+ 372      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 367  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 361     CIIN_0  3   -1   4   1              4           -1   -1   2   0   21
+ 306 CYCLE_DMA_0_  3   -1   0   1  0                       -1   -1   2   0   21
+ 354 CLK_000_N_SYNC_10_  3   -1   7   1                       7  -1   -1   1   0   21
+ 353 CLK_000_N_SYNC_9_  3   -1   1   1                       7  -1   -1   1   0   21
+ 352 CLK_000_N_SYNC_8_  3   -1   6   1     1                    -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_7_  3   -1   3   1                    6     -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_6_  3   -1   0   1           3              -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_5_  3   -1   1   1  0                       -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_4_  3   -1   6   1     1                    -1   -1   1   0   21
+ 347 CLK_000_N_SYNC_3_  3   -1   5   1                    6     -1   -1   1   0   21
+ 346 CLK_000_N_SYNC_2_  3   -1   6   1                 5        -1   -1   1   0   21
+ 345 CLK_000_N_SYNC_1_  3   -1   1   1                    6     -1   -1   1   0   21
+ 344 CLK_000_N_SYNC_0_  3   -1   4   1     1                    -1   -1   1   0   21
+ 343 CLK_000_P_SYNC_8_  3   -1   2   1     1                    -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_7_  3   -1   5   1        2                 -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_6_  3   -1   1   1                 5        -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_5_  3   -1   0   1     1                    -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_4_  3   -1   4   1  0                       -1   -1   1   0   21
+ 338 CLK_000_P_SYNC_3_  3   -1   3   1              4           -1   -1   1   0   21
+ 337 CLK_000_P_SYNC_2_  3   -1   0   1           3              -1   -1   1   0   21
+ 336 CLK_000_P_SYNC_1_  3   -1   6   1  0                       -1   -1   1   0   21
+ 335 CLK_000_P_SYNC_0_  3   -1   4   1                    6     -1   -1   1   0   21
+ 326  IPL_D0_2_  3   -1   1   1     1                    -1   -1   1   0   21
+ 325  IPL_D0_1_  3   -1   6   1     1                    -1   -1   1   0   21
+ 324  IPL_D0_0_  3   -1   6   1     1                    -1   -1   1   0   21
+ 322 CLK_000_N_SYNC_11_  3   -1   7   1  0                       -1   -1   1   0   21
+ 320 CLK_000_P_SYNC_9_  3   -1   1   1           3              -1   -1   1   0   21
+ 314 inst_DTACK_D0  3   -1   5   1        2                 -1   -1   1   0   21
+ 301 inst_DS_030_D0  3   -1   3   1        2                 -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   7  0  1  2  3     5  6  7  85   -1
+  96      A_19_  1   -1  -1   3              4  5     7  96   -1
+  95      A_16_  1   -1  -1   3              4  5     7  95   -1
+  94      A_18_  1   -1  -1   3              4  5     7  94   -1
+  58      A_17_  1   -1  -1   3              4  5     7  58   -1
+  57      FC_1_  1   -1  -1   3              4  5     7  57   -1
+  56      FC_0_  1   -1  -1   3              4  5     7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  66     IPL_0_  1   -1  -1   2     1              6     66   -1
+  63    CLK_030  1   -1  -1   2  0                    7  63   -1
+  55     IPL_1_  1   -1  -1   2     1              6     55   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  93      A_21_  1   -1  -1   1              4           93   -1
+  92      A_20_  1   -1  -1   1              4           92   -1
+  84      A_23_  1   -1  -1   1              4           84   -1
+  83      A_22_  1   -1  -1   1              4           83   -1
+  67     IPL_2_  1   -1  -1   1     1                    67   -1
+  59         A1  1   -1  -1   1  0                       59   -1
+  35        VPA  1   -1  -1   1           3              35   -1
+  29      DTACK  1   -1  -1   1                 5        29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1                 5        13   -1
+  10    CLK_000  1   -1  -1   1     1                    10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
+141 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  41     AS_000  5   -1   4   4  0     2     4        7  41   -1   1   0   21
+  40       BERR  5   -1   4   4  0     2        5     7  40   -1   1   0   21
+  79     RW_000  5  366   7   3  0           4     6     79   -1   3   0   21
+  70         RW  5  372   6   2  0                    7  70   -1   2   0   21
+  81     AS_030  5   -1   7   2              4        7  81   -1   1   0   21
+  31    UDS_000  5   -1   3   2  0                 6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   2  0                 6     30   -1   1   0   21
+  68         A0  5  367   6   1     1                    68   -1   3   0   21
+  97     DS_030  5   -1   0   1           3              97   -1   1   0   21
+  78    SIZE_1_  5   -1   7   1     1                    78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1     1                    69   -1   1   0   21
+   8 IPL_030_2_  5  365   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  364   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  363   1   0                           6   -1  10   0   21
+  80     DSACK1  5  370   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  369   7   0                          82   -1   3   0   21
+  34        VMA  5  371   3   0                          34   -1   3   0   21
+  65          E  0        6   0                          65   -1   2   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  368   3   0                          28   -1   2   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+   2      RESET  0        1   0                           2   -1   1   0   21
+ 369 RN_BGACK_030  3   82   7   7  0     2  3  4  5  6  7  82   -1   3   0   21
+ 316 inst_RESET_OUT  3   -1   0   6  0  1     3  4     6  7  -1   -1   2   0   21
+ 301 inst_nEXP_SPACE_D0reg  3   -1   6   6  0        3  4  5  6  7  -1   -1   1   0   21
+ 320 inst_CLK_000_PE  3   -1   3   5  0     2  3     5     7  -1   -1   1   0   21
+ 300 inst_AS_030_D0  3   -1   7   5  0        3  4  5     7  -1   -1   1   0   21
+ 322 inst_CLK_000_NE  3   -1   6   4  0     2  3     5        -1   -1   1   0   21
+ 361 SM_AMIGA_i_7_  3   -1   5   3           3     5     7  -1   -1  13   0   21
+ 327 SM_AMIGA_3_  3   -1   2   3  0     2        5        -1   -1   5   0   21
+ 294 cpu_est_2_  3   -1   2   3        2  3        6     -1   -1   4   0   21
+ 357 SM_AMIGA_1_  3   -1   5   3        2        5     7  -1   -1   3   0   21
+ 298 SM_AMIGA_5_  3   -1   5   3  0              5     7  -1   -1   3   0   21
+ 295 cpu_est_3_  3   -1   3   3        2  3        6     -1   -1   3   0   21
+ 293 cpu_est_1_  3   -1   2   3        2  3        6     -1   -1   3   0   21
+ 329 SM_AMIGA_0_  3   -1   2   3        2        5     7  -1   -1   2   0   21
+ 314 inst_CLK_OUT_PRE_D  3   -1   4   3     1              6  7  -1   -1   1   0   21
+ 304 inst_BGACK_030_INT_D  3   -1   7   3        2        5  6     -1   -1   1   0   21
+ 305 inst_AS_000_DMA  3   -1   0   2  0                    7  -1   -1   7   0   21
+ 359 SM_AMIGA_2_  3   -1   2   2        2        5        -1   -1   4   0   21
+ 313 inst_LDS_000_INT  3   -1   1   2     1     3              -1   -1   4   0   21
+ 371     RN_VMA  3   34   3   2        2  3              34   -1   3   0   21
+ 360 inst_DS_000_ENABLE  3   -1   0   2  0        3              -1   -1   3   0   21
+ 358 SM_AMIGA_4_  3   -1   5   2        2        5        -1   -1   3   0   21
+ 332 SM_AMIGA_6_  3   -1   5   2     1           5        -1   -1   3   0   21
+ 312 inst_UDS_000_INT  3   -1   1   2     1     3              -1   -1   3   0   21
+ 310 SIZE_DMA_1_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 309 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 330 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   6   2           3        6     -1   -1   2   0   21
+ 307 CYCLE_DMA_0_  3   -1   2   2  0     2                 -1   -1   2   0   21
+ 297 inst_AS_000_INT  3   -1   5   2              4  5        -1   -1   2   0   21
+ 296 cpu_est_0_  3   -1   2   2        2  3              -1   -1   2   0   21
+ 328 inst_CLK_000_NE_D0  3   -1   3   2        2  3              -1   -1   1   0   21
+ 319 inst_CLK_000_D0  3   -1   1   2           3     5        -1   -1   1   0   21
+ 318 inst_CLK_000_D1  3   -1   5   2           3     5        -1   -1   1   0   21
+ 311 inst_VPA_D  3   -1   0   2        2  3              -1   -1   1   0   21
+ 365 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 364 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 363 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 306 inst_DS_000_DMA  3   -1   0   1  0                       -1   -1   9   0   21
+ 356 inst_CLK_030_H  3   -1   0   1  0                       -1   -1   8   0   21
+ 303 inst_AS_030_000_SYNC  3   -1   5   1                 5        -1   -1   7   0   21
+ 370  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 334 RST_DLY_1_  3   -1   0   1  0                       -1   -1   4   0   21
+ 367      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 366  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 333 RST_DLY_0_  3   -1   0   1  0                       -1   -1   3   0   21
+ 308 CYCLE_DMA_1_  3   -1   0   1  0                       -1   -1   3   0   21
+ 372      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 368  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 362     CIIN_0  3   -1   4   1              4           -1   -1   2   0   21
+ 335 RST_DLY_2_  3   -1   0   1  0                       -1   -1   2   0   21
+ 331    N_270_i  3   -1   2   1                 5        -1   -1   2   0   21
+ 299 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   2   1        2                 -1   -1   2   0   21
+ 355 CLK_000_N_SYNC_10_  3   -1   7   1                       7  -1   -1   1   0   21
+ 354 CLK_000_N_SYNC_9_  3   -1   3   1                       7  -1   -1   1   0   21
+ 353 CLK_000_N_SYNC_8_  3   -1   2   1           3              -1   -1   1   0   21
+ 352 CLK_000_N_SYNC_7_  3   -1   3   1        2                 -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_6_  3   -1   6   1           3              -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_5_  3   -1   6   1                    6     -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_4_  3   -1   1   1                    6     -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_3_  3   -1   2   1     1                    -1   -1   1   0   21
+ 347 CLK_000_N_SYNC_2_  3   -1   2   1        2                 -1   -1   1   0   21
+ 346 CLK_000_N_SYNC_1_  3   -1   1   1        2                 -1   -1   1   0   21
+ 345 CLK_000_N_SYNC_0_  3   -1   5   1     1                    -1   -1   1   0   21
+ 344 CLK_000_P_SYNC_8_  3   -1   1   1        2                 -1   -1   1   0   21
+ 343 CLK_000_P_SYNC_7_  3   -1   0   1     1                    -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_6_  3   -1   4   1  0                       -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_5_  3   -1   0   1              4           -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_4_  3   -1   3   1  0                       -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_3_  3   -1   4   1           3              -1   -1   1   0   21
+ 338 CLK_000_P_SYNC_2_  3   -1   5   1              4           -1   -1   1   0   21
+ 337 CLK_000_P_SYNC_1_  3   -1   6   1                 5        -1   -1   1   0   21
+ 336 CLK_000_P_SYNC_0_  3   -1   3   1                    6     -1   -1   1   0   21
+ 326  IPL_D0_2_  3   -1   1   1     1                    -1   -1   1   0   21
+ 325  IPL_D0_1_  3   -1   1   1     1                    -1   -1   1   0   21
+ 324  IPL_D0_0_  3   -1   1   1     1                    -1   -1   1   0   21
+ 323 CLK_000_N_SYNC_11_  3   -1   7   1                    6     -1   -1   1   0   21
+ 321 CLK_000_P_SYNC_9_  3   -1   2   1           3              -1   -1   1   0   21
+ 317 inst_CLK_OUT_PRE_50  3   -1   4   1              4           -1   -1   1   0   21
+ 315 inst_DTACK_D0  3   -1   6   1        2                 -1   -1   1   0   21
+ 302 inst_DS_030_D0  3   -1   3   1     1                    -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   7  0  1  2  3     5  6  7  85   -1
+  96      A_19_  1   -1  -1   3              4  5     7  96   -1
+  95      A_16_  1   -1  -1   3              4  5     7  95   -1
+  94      A_18_  1   -1  -1   3              4  5     7  94   -1
+  58      A_17_  1   -1  -1   3              4  5     7  58   -1
+  57      FC_1_  1   -1  -1   3              4  5     7  57   -1
+  56      FC_0_  1   -1  -1   3              4  5     7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  63    CLK_030  1   -1  -1   2  0                    7  63   -1
+  59         A1  1   -1  -1   2        2           6     59   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  93      A_21_  1   -1  -1   1              4           93   -1
+  92      A_20_  1   -1  -1   1              4           92   -1
+  84      A_23_  1   -1  -1   1              4           84   -1
+  83      A_22_  1   -1  -1   1              4           83   -1
+  67     IPL_2_  1   -1  -1   1     1                    67   -1
+  66     IPL_0_  1   -1  -1   1     1                    66   -1
+  55     IPL_1_  1   -1  -1   1     1                    55   -1
+  35        VPA  1   -1  -1   1  0                       35   -1
+  29      DTACK  1   -1  -1   1                    6     29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1                    6     13   -1
+  10    CLK_000  1   -1  -1   1     1                    10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
+140 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  40       BERR  5   -1   4   4        2        5  6  7  40   -1   1   0   21
+  79     RW_000  5  365   7   3  0           4     6     79   -1   3   0   21
+  81     AS_030  5   -1   7   3           3  4        7  81   -1   1   0   21
+  41     AS_000  5   -1   4   3  0           4        7  41   -1   1   0   21
+  70         RW  5  371   6   2        2              7  70   -1   2   0   21
+  31    UDS_000  5   -1   3   2  0                 6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   2  0                 6     30   -1   1   0   21
+  68         A0  5  366   6   1  0                       68   -1   3   0   21
+  78    SIZE_1_  5   -1   7   1  0                       78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1  0                       69   -1   1   0   21
+   8 IPL_030_2_  5  362   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  364   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  363   1   0                           6   -1  10   0   21
+  80     DSACK1  5  369   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  368   7   0                          82   -1   3   0   21
+  34        VMA  5  370   3   0                          34   -1   3   0   21
+  65          E  0        6   0                          65   -1   2   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  367   3   0                          28   -1   2   0   21
+  97     DS_030  0        0   0                          97   -1   1   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+   2      RESET  0        1   0                           2   -1   1   0   21
+ 368 RN_BGACK_030  3   82   7   7  0     2  3  4  5  6  7  82   -1   3   0   21
+ 301 inst_nEXP_SPACE_D0reg  3   -1   5   7  0  1     3  4  5  6  7  -1   -1   1   0   21
+ 316 inst_RESET_OUT  3   -1   1   6  0  1     3  4     6  7  -1   -1   2   0   21
+ 320 inst_CLK_000_PE  3   -1   6   6  0     2  3     5  6  7  -1   -1   1   0   21
+ 300 inst_AS_030_D0  3   -1   3   5        2  3  4  5     7  -1   -1   1   0   21
+ 357 SM_AMIGA_1_  3   -1   2   4     1  2           6  7  -1   -1   3   0   21
+ 355 SM_AMIGA_6_  3   -1   5   4  0  1  2        5        -1   -1   3   0   21
+ 298 SM_AMIGA_5_  3   -1   2   4     1  2        5     7  -1   -1   3   0   21
+ 329 SM_AMIGA_0_  3   -1   6   4     1  2           6  7  -1   -1   2   0   21
+ 322 inst_CLK_000_NE  3   -1   3   4     1  2  3        6     -1   -1   1   0   21
+ 360 SM_AMIGA_i_7_  3   -1   2   3           3     5     7  -1   -1  14   0   21
+ 293 cpu_est_2_  3   -1   3   3        2  3        6     -1   -1   4   0   21
+ 296 cpu_est_1_  3   -1   2   3        2  3        6     -1   -1   3   0   21
+ 294 cpu_est_3_  3   -1   3   3        2  3        6     -1   -1   3   0   21
+ 319 inst_CLK_000_D0  3   -1   0   3     1     3     5        -1   -1   1   0   21
+ 314 inst_CLK_OUT_PRE_D  3   -1   4   3     1              6  7  -1   -1   1   0   21
+ 305 inst_AS_000_DMA  3   -1   0   2  0                    7  -1   -1   7   0   21
+ 303 inst_AS_030_000_SYNC  3   -1   5   2     1           5        -1   -1   7   0   21
+ 327 SM_AMIGA_3_  3   -1   2   2     1  2                 -1   -1   5   0   21
+ 359 SM_AMIGA_2_  3   -1   2   2     1  2                 -1   -1   4   0   21
+ 370     RN_VMA  3   34   3   2        2  3              34   -1   3   0   21
+ 358 SM_AMIGA_4_  3   -1   2   2     1  2                 -1   -1   3   0   21
+ 331 inst_DS_000_ENABLE  3   -1   2   2        2  3              -1   -1   3   0   21
+ 313 inst_LDS_000_INT  3   -1   0   2  0        3              -1   -1   3   0   21
+ 310 SIZE_DMA_1_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 309 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 330 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   5   2           3     5        -1   -1   2   0   21
+ 312 inst_UDS_000_INT  3   -1   0   2  0        3              -1   -1   2   0   21
+ 299 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   5   2        2        5        -1   -1   2   0   21
+ 297 inst_AS_000_INT  3   -1   5   2              4  5        -1   -1   2   0   21
+ 295 cpu_est_0_  3   -1   3   2        2  3              -1   -1   2   0   21
+ 328 inst_CLK_000_NE_D0  3   -1   3   2        2  3              -1   -1   1   0   21
+ 318 inst_CLK_000_D1  3   -1   5   2     1           5        -1   -1   1   0   21
+ 311 inst_VPA_D  3   -1   6   2        2  3              -1   -1   1   0   21
+ 304 inst_BGACK_030_INT_D  3   -1   7   2                 5  6     -1   -1   1   0   21
+ 364 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 363 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 362 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 306 inst_DS_000_DMA  3   -1   0   1  0                       -1   -1   9   0   21
+ 356 inst_CLK_030_H  3   -1   0   1  0                       -1   -1   8   0   21
+ 369  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 333 RST_DLY_1_  3   -1   1   1     1                    -1   -1   4   0   21
+ 302    N_218_i  3   -1   1   1        2                 -1   -1   4   0   21
+ 366      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 365  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 332 RST_DLY_0_  3   -1   1   1     1                    -1   -1   3   0   21
+ 308 CYCLE_DMA_1_  3   -1   0   1  0                       -1   -1   3   0   21
+ 371      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 367  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 361     CIIN_0  3   -1   4   1              4           -1   -1   2   0   21
+ 334 RST_DLY_2_  3   -1   1   1     1                    -1   -1   2   0   21
+ 307 CYCLE_DMA_0_  3   -1   0   1  0                       -1   -1   2   0   21
+ 354 CLK_000_N_SYNC_10_  3   -1   7   1                       7  -1   -1   1   0   21
+ 353 CLK_000_N_SYNC_9_  3   -1   0   1                       7  -1   -1   1   0   21
+ 352 CLK_000_N_SYNC_8_  3   -1   2   1  0                       -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_7_  3   -1   4   1        2                 -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_6_  3   -1   7   1              4           -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_5_  3   -1   1   1                       7  -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_4_  3   -1   6   1     1                    -1   -1   1   0   21
+ 347 CLK_000_N_SYNC_3_  3   -1   1   1                    6     -1   -1   1   0   21
+ 346 CLK_000_N_SYNC_2_  3   -1   5   1     1                    -1   -1   1   0   21
+ 345 CLK_000_N_SYNC_1_  3   -1   6   1                 5        -1   -1   1   0   21
+ 344 CLK_000_N_SYNC_0_  3   -1   5   1                    6     -1   -1   1   0   21
+ 343 CLK_000_P_SYNC_8_  3   -1   4   1                    6     -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_7_  3   -1   3   1              4           -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_6_  3   -1   3   1           3              -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_5_  3   -1   0   1           3              -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_4_  3   -1   6   1  0                       -1   -1   1   0   21
+ 338 CLK_000_P_SYNC_3_  3   -1   3   1                    6     -1   -1   1   0   21
+ 337 CLK_000_P_SYNC_2_  3   -1   0   1           3              -1   -1   1   0   21
+ 336 CLK_000_P_SYNC_1_  3   -1   6   1  0                       -1   -1   1   0   21
+ 335 CLK_000_P_SYNC_0_  3   -1   1   1                    6     -1   -1   1   0   21
+ 326  IPL_D0_2_  3   -1   5   1     1                    -1   -1   1   0   21
+ 325  IPL_D0_1_  3   -1   1   1     1                    -1   -1   1   0   21
+ 324  IPL_D0_0_  3   -1   1   1     1                    -1   -1   1   0   21
+ 323 CLK_000_N_SYNC_11_  3   -1   7   1           3              -1   -1   1   0   21
+ 321 CLK_000_P_SYNC_9_  3   -1   6   1                    6     -1   -1   1   0   21
+ 317 inst_CLK_OUT_PRE_50  3   -1   4   1              4           -1   -1   1   0   21
+ 315 inst_DTACK_D0  3   -1   6   1        2                 -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   7  0  1  2  3     5  6  7  85   -1
+  96      A_19_  1   -1  -1   3              4  5     7  96   -1
+  95      A_16_  1   -1  -1   3              4  5     7  95   -1
+  94      A_18_  1   -1  -1   3              4  5     7  94   -1
+  58      A_17_  1   -1  -1   3              4  5     7  58   -1
+  57      FC_1_  1   -1  -1   3              4  5     7  57   -1
+  56      FC_0_  1   -1  -1   3              4  5     7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  67     IPL_2_  1   -1  -1   2     1           5        67   -1
+  63    CLK_030  1   -1  -1   2  0                    7  63   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  93      A_21_  1   -1  -1   1              4           93   -1
+  92      A_20_  1   -1  -1   1              4           92   -1
+  84      A_23_  1   -1  -1   1              4           84   -1
+  83      A_22_  1   -1  -1   1              4           83   -1
+  66     IPL_0_  1   -1  -1   1     1                    66   -1
+  59         A1  1   -1  -1   1                 5        59   -1
+  55     IPL_1_  1   -1  -1   1     1                    55   -1
+  35        VPA  1   -1  -1   1                    6     35   -1
+  29      DTACK  1   -1  -1   1                    6     29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1                 5        13   -1
+  10    CLK_000  1   -1  -1   1  0                       10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
+140 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  40       BERR  5   -1   4   4        2        5  6  7  40   -1   1   0   21
+  79     RW_000  5  365   7   3  0           4     6     79   -1   3   0   21
+  81     AS_030  5   -1   7   3           3  4        7  81   -1   1   0   21
+  41     AS_000  5   -1   4   3  0           4        7  41   -1   1   0   21
+  70         RW  5  371   6   2        2              7  70   -1   2   0   21
+  31    UDS_000  5   -1   3   2  0                 6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   2  0                 6     30   -1   1   0   21
+  68         A0  5  366   6   1  0                       68   -1   3   0   21
+  78    SIZE_1_  5   -1   7   1  0                       78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1  0                       69   -1   1   0   21
+   8 IPL_030_2_  5  362   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  364   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  363   1   0                           6   -1  10   0   21
+  80     DSACK1  5  369   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  368   7   0                          82   -1   3   0   21
+  34        VMA  5  370   3   0                          34   -1   3   0   21
+  65          E  0        6   0                          65   -1   2   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  367   3   0                          28   -1   2   0   21
+  97     DS_030  0        0   0                          97   -1   1   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+   2      RESET  0        1   0                           2   -1   1   0   21
+ 368 RN_BGACK_030  3   82   7   7  0     2  3  4  5  6  7  82   -1   3   0   21
+ 301 inst_nEXP_SPACE_D0reg  3   -1   5   7  0  1     3  4  5  6  7  -1   -1   1   0   21
+ 316 inst_RESET_OUT  3   -1   1   6  0  1     3  4     6  7  -1   -1   2   0   21
+ 320 inst_CLK_000_PE  3   -1   6   6  0     2  3     5  6  7  -1   -1   1   0   21
+ 300 inst_AS_030_D0  3   -1   3   5        2  3  4  5     7  -1   -1   1   0   21
+ 357 SM_AMIGA_1_  3   -1   2   4     1  2           6  7  -1   -1   3   0   21
+ 355 SM_AMIGA_6_  3   -1   5   4  0  1  2        5        -1   -1   3   0   21
+ 298 SM_AMIGA_5_  3   -1   2   4     1  2        5     7  -1   -1   3   0   21
+ 329 SM_AMIGA_0_  3   -1   6   4     1  2           6  7  -1   -1   2   0   21
+ 322 inst_CLK_000_NE  3   -1   3   4     1  2  3        6     -1   -1   1   0   21
+ 360 SM_AMIGA_i_7_  3   -1   2   3           3     5     7  -1   -1  14   0   21
+ 293 cpu_est_2_  3   -1   3   3        2  3        6     -1   -1   4   0   21
+ 296 cpu_est_1_  3   -1   2   3        2  3        6     -1   -1   3   0   21
+ 294 cpu_est_3_  3   -1   3   3        2  3        6     -1   -1   3   0   21
+ 319 inst_CLK_000_D0  3   -1   0   3     1     3     5        -1   -1   1   0   21
+ 314 inst_CLK_OUT_PRE_D  3   -1   4   3     1              6  7  -1   -1   1   0   21
+ 305 inst_AS_000_DMA  3   -1   0   2  0                    7  -1   -1   7   0   21
+ 303 inst_AS_030_000_SYNC  3   -1   5   2     1           5        -1   -1   7   0   21
+ 327 SM_AMIGA_3_  3   -1   2   2     1  2                 -1   -1   5   0   21
+ 359 SM_AMIGA_2_  3   -1   2   2     1  2                 -1   -1   4   0   21
+ 370     RN_VMA  3   34   3   2        2  3              34   -1   3   0   21
+ 358 SM_AMIGA_4_  3   -1   2   2     1  2                 -1   -1   3   0   21
+ 331 inst_DS_000_ENABLE  3   -1   2   2        2  3              -1   -1   3   0   21
+ 313 inst_LDS_000_INT  3   -1   0   2  0        3              -1   -1   3   0   21
+ 310 SIZE_DMA_1_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 309 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 330 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   5   2           3     5        -1   -1   2   0   21
+ 312 inst_UDS_000_INT  3   -1   0   2  0        3              -1   -1   2   0   21
+ 299 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   5   2        2        5        -1   -1   2   0   21
+ 297 inst_AS_000_INT  3   -1   5   2              4  5        -1   -1   2   0   21
+ 295 cpu_est_0_  3   -1   3   2        2  3              -1   -1   2   0   21
+ 328 inst_CLK_000_NE_D0  3   -1   3   2        2  3              -1   -1   1   0   21
+ 318 inst_CLK_000_D1  3   -1   5   2     1           5        -1   -1   1   0   21
+ 311 inst_VPA_D  3   -1   6   2        2  3              -1   -1   1   0   21
+ 304 inst_BGACK_030_INT_D  3   -1   7   2                 5  6     -1   -1   1   0   21
+ 364 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 363 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 362 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 306 inst_DS_000_DMA  3   -1   0   1  0                       -1   -1   9   0   21
+ 356 inst_CLK_030_H  3   -1   0   1  0                       -1   -1   8   0   21
+ 369  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 333 RST_DLY_1_  3   -1   1   1     1                    -1   -1   4   0   21
+ 302    N_218_i  3   -1   1   1        2                 -1   -1   4   0   21
+ 366      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 365  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 332 RST_DLY_0_  3   -1   1   1     1                    -1   -1   3   0   21
+ 308 CYCLE_DMA_1_  3   -1   0   1  0                       -1   -1   3   0   21
+ 371      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 367  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 361     CIIN_0  3   -1   4   1              4           -1   -1   2   0   21
+ 334 RST_DLY_2_  3   -1   1   1     1                    -1   -1   2   0   21
+ 307 CYCLE_DMA_0_  3   -1   0   1  0                       -1   -1   2   0   21
+ 354 CLK_000_N_SYNC_10_  3   -1   7   1                       7  -1   -1   1   0   21
+ 353 CLK_000_N_SYNC_9_  3   -1   0   1                       7  -1   -1   1   0   21
+ 352 CLK_000_N_SYNC_8_  3   -1   2   1  0                       -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_7_  3   -1   4   1        2                 -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_6_  3   -1   7   1              4           -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_5_  3   -1   1   1                       7  -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_4_  3   -1   6   1     1                    -1   -1   1   0   21
+ 347 CLK_000_N_SYNC_3_  3   -1   1   1                    6     -1   -1   1   0   21
+ 346 CLK_000_N_SYNC_2_  3   -1   5   1     1                    -1   -1   1   0   21
+ 345 CLK_000_N_SYNC_1_  3   -1   6   1                 5        -1   -1   1   0   21
+ 344 CLK_000_N_SYNC_0_  3   -1   5   1                    6     -1   -1   1   0   21
+ 343 CLK_000_P_SYNC_8_  3   -1   4   1                    6     -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_7_  3   -1   3   1              4           -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_6_  3   -1   3   1           3              -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_5_  3   -1   0   1           3              -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_4_  3   -1   6   1  0                       -1   -1   1   0   21
+ 338 CLK_000_P_SYNC_3_  3   -1   3   1                    6     -1   -1   1   0   21
+ 337 CLK_000_P_SYNC_2_  3   -1   0   1           3              -1   -1   1   0   21
+ 336 CLK_000_P_SYNC_1_  3   -1   6   1  0                       -1   -1   1   0   21
+ 335 CLK_000_P_SYNC_0_  3   -1   1   1                    6     -1   -1   1   0   21
+ 326  IPL_D0_2_  3   -1   5   1     1                    -1   -1   1   0   21
+ 325  IPL_D0_1_  3   -1   1   1     1                    -1   -1   1   0   21
+ 324  IPL_D0_0_  3   -1   1   1     1                    -1   -1   1   0   21
+ 323 CLK_000_N_SYNC_11_  3   -1   7   1           3              -1   -1   1   0   21
+ 321 CLK_000_P_SYNC_9_  3   -1   6   1                    6     -1   -1   1   0   21
+ 317 inst_CLK_OUT_PRE_50  3   -1   4   1              4           -1   -1   1   0   21
+ 315 inst_DTACK_D0  3   -1   6   1        2                 -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   7  0  1  2  3     5  6  7  85   -1
+  96      A_19_  1   -1  -1   3              4  5     7  96   -1
+  95      A_16_  1   -1  -1   3              4  5     7  95   -1
+  94      A_18_  1   -1  -1   3              4  5     7  94   -1
+  58      A_17_  1   -1  -1   3              4  5     7  58   -1
+  57      FC_1_  1   -1  -1   3              4  5     7  57   -1
+  56      FC_0_  1   -1  -1   3              4  5     7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  67     IPL_2_  1   -1  -1   2     1           5        67   -1
+  63    CLK_030  1   -1  -1   2  0                    7  63   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  93      A_21_  1   -1  -1   1              4           93   -1
+  92      A_20_  1   -1  -1   1              4           92   -1
+  84      A_23_  1   -1  -1   1              4           84   -1
+  83      A_22_  1   -1  -1   1              4           83   -1
+  66     IPL_0_  1   -1  -1   1     1                    66   -1
+  59         A1  1   -1  -1   1                 5        59   -1
+  55     IPL_1_  1   -1  -1   1     1                    55   -1
+  35        VPA  1   -1  -1   1                    6     35   -1
+  29      DTACK  1   -1  -1   1                    6     29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1                 5        13   -1
+  10    CLK_000  1   -1  -1   1  0                       10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
+140 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  41     AS_000  5   -1   4   5  0  1  2     4        7  41   -1   1   0   21
+  79     RW_000  5  365   7   3  0           4     6     79   -1   3   0   21
+  40       BERR  5   -1   4   3        2        5     7  40   -1   1   0   21
+  70         RW  5  371   6   2        2              7  70   -1   2   0   21
+  81     AS_030  5   -1   7   2              4        7  81   -1   1   0   21
+  31    UDS_000  5   -1   3   2  0                 6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   2  0                 6     30   -1   1   0   21
+  68         A0  5  366   6   1  0                       68   -1   3   0   21
+  78    SIZE_1_  5   -1   7   1  0                       78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1  0                       69   -1   1   0   21
+   8 IPL_030_2_  5  362   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  364   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  363   1   0                           6   -1  10   0   21
+  80     DSACK1  5  369   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  368   7   0                          82   -1   3   0   21
+  34        VMA  5  370   3   0                          34   -1   3   0   21
+  65          E  0        6   0                          65   -1   2   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  367   3   0                          28   -1   2   0   21
+  97     DS_030  0        0   0                          97   -1   1   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+   2      RESET  0        1   0                           2   -1   1   0   21
+ 368 RN_BGACK_030  3   82   7   7  0  1  2  3  4     6  7  82   -1   3   0   21
+ 302 inst_nEXP_SPACE_D0reg  3   -1   0   7  0     2  3  4  5  6  7  -1   -1   1   0   21
+ 316 inst_RESET_OUT  3   -1   3   6  0  1     3  4     6  7  -1   -1   2   0   21
+ 320 inst_CLK_000_PE  3   -1   6   5     1  2  3     5     7  -1   -1   1   0   21
+ 360 SM_AMIGA_i_7_  3   -1   5   4        2  3     5     7  -1   -1  14   0   21
+ 301 inst_AS_030_D0  3   -1   7   4        2  3  4        7  -1   -1   1   0   21
+ 294 cpu_est_2_  3   -1   3   3           3     5  6     -1   -1   4   0   21
+ 355 SM_AMIGA_6_  3   -1   5   3  0     2        5        -1   -1   3   0   21
+ 299 SM_AMIGA_5_  3   -1   5   3        2        5     7  -1   -1   3   0   21
+ 297 cpu_est_1_  3   -1   3   3           3     5  6     -1   -1   3   0   21
+ 295 cpu_est_3_  3   -1   5   3           3     5  6     -1   -1   3   0   21
+ 328 SM_AMIGA_0_  3   -1   5   3        2        5     7  -1   -1   2   0   21
+ 307 CYCLE_DMA_0_  3   -1   1   3  0  1  2                 -1   -1   2   0   21
+ 319 inst_CLK_000_D0  3   -1   1   3           3  4  5        -1   -1   1   0   21
+ 314 inst_CLK_OUT_PRE_D  3   -1   0   3     1              6  7  -1   -1   1   0   21
+ 304 inst_BGACK_030_INT_D  3   -1   7   3     1  2           6     -1   -1   1   0   21
+ 305 inst_AS_000_DMA  3   -1   0   2  0                    7  -1   -1   7   0   21
+ 303 inst_AS_030_000_SYNC  3   -1   2   2        2        5        -1   -1   7   0   21
+ 331 inst_DS_000_ENABLE  3   -1   2   2        2  3              -1   -1   5   0   21
+ 370     RN_VMA  3   34   3   2           3     5        34   -1   3   0   21
+ 357 SM_AMIGA_1_  3   -1   5   2                 5     7  -1   -1   3   0   21
+ 330 SM_AMIGA_4_  3   -1   5   2        2        5        -1   -1   3   0   21
+ 313 inst_LDS_000_INT  3   -1   0   2  0        3              -1   -1   3   0   21
+ 310 SIZE_DMA_1_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 309 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 308 CYCLE_DMA_1_  3   -1   2   2  0     2                 -1   -1   3   0   21
+ 329 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   1   2     1     3              -1   -1   2   0   21
+ 312 inst_UDS_000_INT  3   -1   0   2  0        3              -1   -1   2   0   21
+ 300 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   1   2     1  2                 -1   -1   2   0   21
+ 298 inst_AS_000_INT  3   -1   2   2        2     4           -1   -1   2   0   21
+ 296 cpu_est_0_  3   -1   3   2           3     5        -1   -1   2   0   21
+ 327 inst_CLK_000_NE_D0  3   -1   3   2           3     5        -1   -1   1   0   21
+ 322 inst_CLK_000_NE  3   -1   6   2           3     5        -1   -1   1   0   21
+ 318 inst_CLK_000_D1  3   -1   4   2              4  5        -1   -1   1   0   21
+ 317 inst_CLK_OUT_PRE_50  3   -1   5   2  0              5        -1   -1   1   0   21
+ 311 inst_VPA_D  3   -1   5   2           3     5        -1   -1   1   0   21
+ 364 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 363 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 362 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 306 inst_DS_000_DMA  3   -1   0   1  0                       -1   -1   9   0   21
+ 356 inst_CLK_030_H  3   -1   0   1  0                       -1   -1   8   0   21
+ 358 SM_AMIGA_3_  3   -1   5   1                 5        -1   -1   5   0   21
+ 369  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 359 SM_AMIGA_2_  3   -1   5   1                 5        -1   -1   4   0   21
+ 333 RST_DLY_1_  3   -1   3   1           3              -1   -1   4   0   21
+ 293    N_317_i  3   -1   5   1                 5        -1   -1   4   0   21
+ 366      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 365  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 332 RST_DLY_0_  3   -1   3   1           3              -1   -1   3   0   21
+ 371      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 367  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 361     CIIN_0  3   -1   4   1              4           -1   -1   2   0   21
+ 334 RST_DLY_2_  3   -1   3   1           3              -1   -1   2   0   21
+ 354 CLK_000_N_SYNC_10_  3   -1   7   1     1                    -1   -1   1   0   21
+ 353 CLK_000_N_SYNC_9_  3   -1   7   1                       7  -1   -1   1   0   21
+ 352 CLK_000_N_SYNC_8_  3   -1   0   1                       7  -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_7_  3   -1   0   1  0                       -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_6_  3   -1   5   1  0                       -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_5_  3   -1   6   1                 5        -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_4_  3   -1   3   1                    6     -1   -1   1   0   21
+ 347 CLK_000_N_SYNC_3_  3   -1   1   1           3              -1   -1   1   0   21
+ 346 CLK_000_N_SYNC_2_  3   -1   1   1     1                    -1   -1   1   0   21
+ 345 CLK_000_N_SYNC_1_  3   -1   1   1     1                    -1   -1   1   0   21
+ 344 CLK_000_N_SYNC_0_  3   -1   4   1     1                    -1   -1   1   0   21
+ 343 CLK_000_P_SYNC_8_  3   -1   0   1                    6     -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_7_  3   -1   6   1  0                       -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_6_  3   -1   1   1                    6     -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_5_  3   -1   0   1     1                    -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_4_  3   -1   6   1  0                       -1   -1   1   0   21
+ 338 CLK_000_P_SYNC_3_  3   -1   6   1                    6     -1   -1   1   0   21
+ 337 CLK_000_P_SYNC_2_  3   -1   4   1                    6     -1   -1   1   0   21
+ 336 CLK_000_P_SYNC_1_  3   -1   6   1              4           -1   -1   1   0   21
+ 335 CLK_000_P_SYNC_0_  3   -1   4   1                    6     -1   -1   1   0   21
+ 326  IPL_D0_2_  3   -1   1   1     1                    -1   -1   1   0   21
+ 325  IPL_D0_1_  3   -1   3   1     1                    -1   -1   1   0   21
+ 324  IPL_D0_0_  3   -1   6   1     1                    -1   -1   1   0   21
+ 323 CLK_000_N_SYNC_11_  3   -1   1   1                    6     -1   -1   1   0   21
+ 321 CLK_000_P_SYNC_9_  3   -1   6   1                    6     -1   -1   1   0   21
+ 315 inst_DTACK_D0  3   -1   1   1                 5        -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   7  0  1  2  3     5  6  7  85   -1
+  96      A_19_  1   -1  -1   3        2     4        7  96   -1
+  95      A_16_  1   -1  -1   3        2     4        7  95   -1
+  94      A_18_  1   -1  -1   3        2     4        7  94   -1
+  58      A_17_  1   -1  -1   3        2     4        7  58   -1
+  57      FC_1_  1   -1  -1   3        2     4        7  57   -1
+  56      FC_0_  1   -1  -1   3        2     4        7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  66     IPL_0_  1   -1  -1   2     1              6     66   -1
+  63    CLK_030  1   -1  -1   2  0                    7  63   -1
+  55     IPL_1_  1   -1  -1   2     1     3              55   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  93      A_21_  1   -1  -1   1              4           93   -1
+  92      A_20_  1   -1  -1   1              4           92   -1
+  84      A_23_  1   -1  -1   1              4           84   -1
+  83      A_22_  1   -1  -1   1              4           83   -1
+  67     IPL_2_  1   -1  -1   1     1                    67   -1
+  59         A1  1   -1  -1   1     1                    59   -1
+  35        VPA  1   -1  -1   1                 5        35   -1
+  29      DTACK  1   -1  -1   1     1                    29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1  0                       13   -1
+  10    CLK_000  1   -1  -1   1     1                    10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
+140 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  41     AS_000  5   -1   4   5  0  1  2     4        7  41   -1   1   0   21
+  79     RW_000  5  365   7   3  0           4     6     79   -1   3   0   21
+  40       BERR  5   -1   4   3        2        5     7  40   -1   1   0   21
+  70         RW  5  371   6   2        2              7  70   -1   2   0   21
+  81     AS_030  5   -1   7   2              4        7  81   -1   1   0   21
+  31    UDS_000  5   -1   3   2  0                 6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   2  0                 6     30   -1   1   0   21
+  68         A0  5  366   6   1  0                       68   -1   3   0   21
+  78    SIZE_1_  5   -1   7   1  0                       78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1  0                       69   -1   1   0   21
+   8 IPL_030_2_  5  362   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  364   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  363   1   0                           6   -1  10   0   21
+  80     DSACK1  5  369   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  368   7   0                          82   -1   3   0   21
+  34        VMA  5  370   3   0                          34   -1   3   0   21
+  65          E  0        6   0                          65   -1   2   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  367   3   0                          28   -1   2   0   21
+  97     DS_030  0        0   0                          97   -1   1   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+   2      RESET  0        1   0                           2   -1   1   0   21
+ 368 RN_BGACK_030  3   82   7   7  0  1  2  3  4     6  7  82   -1   3   0   21
+ 302 inst_nEXP_SPACE_D0reg  3   -1   0   7  0     2  3  4  5  6  7  -1   -1   1   0   21
+ 316 inst_RESET_OUT  3   -1   3   6  0  1     3  4     6  7  -1   -1   2   0   21
+ 320 inst_CLK_000_PE  3   -1   6   5     1  2  3     5     7  -1   -1   1   0   21
+ 360 SM_AMIGA_i_7_  3   -1   5   4        2  3     5     7  -1   -1  14   0   21
+ 301 inst_AS_030_D0  3   -1   7   4        2  3  4        7  -1   -1   1   0   21
+ 294 cpu_est_2_  3   -1   3   3           3     5  6     -1   -1   4   0   21
+ 355 SM_AMIGA_6_  3   -1   5   3  0     2        5        -1   -1   3   0   21
+ 299 SM_AMIGA_5_  3   -1   5   3        2        5     7  -1   -1   3   0   21
+ 297 cpu_est_1_  3   -1   3   3           3     5  6     -1   -1   3   0   21
+ 295 cpu_est_3_  3   -1   5   3           3     5  6     -1   -1   3   0   21
+ 328 SM_AMIGA_0_  3   -1   5   3        2        5     7  -1   -1   2   0   21
+ 307 CYCLE_DMA_0_  3   -1   1   3  0  1  2                 -1   -1   2   0   21
+ 319 inst_CLK_000_D0  3   -1   1   3           3  4  5        -1   -1   1   0   21
+ 314 inst_CLK_OUT_PRE_D  3   -1   0   3     1              6  7  -1   -1   1   0   21
+ 304 inst_BGACK_030_INT_D  3   -1   7   3     1  2           6     -1   -1   1   0   21
+ 305 inst_AS_000_DMA  3   -1   0   2  0                    7  -1   -1   7   0   21
+ 303 inst_AS_030_000_SYNC  3   -1   2   2        2        5        -1   -1   7   0   21
+ 331 inst_DS_000_ENABLE  3   -1   2   2        2  3              -1   -1   5   0   21
+ 370     RN_VMA  3   34   3   2           3     5        34   -1   3   0   21
+ 357 SM_AMIGA_1_  3   -1   5   2                 5     7  -1   -1   3   0   21
+ 330 SM_AMIGA_4_  3   -1   5   2        2        5        -1   -1   3   0   21
+ 313 inst_LDS_000_INT  3   -1   0   2  0        3              -1   -1   3   0   21
+ 310 SIZE_DMA_1_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 309 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 308 CYCLE_DMA_1_  3   -1   2   2  0     2                 -1   -1   3   0   21
+ 329 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   1   2     1     3              -1   -1   2   0   21
+ 312 inst_UDS_000_INT  3   -1   0   2  0        3              -1   -1   2   0   21
+ 300 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   1   2     1  2                 -1   -1   2   0   21
+ 298 inst_AS_000_INT  3   -1   2   2        2     4           -1   -1   2   0   21
+ 296 cpu_est_0_  3   -1   3   2           3     5        -1   -1   2   0   21
+ 327 inst_CLK_000_NE_D0  3   -1   3   2           3     5        -1   -1   1   0   21
+ 322 inst_CLK_000_NE  3   -1   6   2           3     5        -1   -1   1   0   21
+ 318 inst_CLK_000_D1  3   -1   4   2              4  5        -1   -1   1   0   21
+ 317 inst_CLK_OUT_PRE_50  3   -1   5   2  0              5        -1   -1   1   0   21
+ 311 inst_VPA_D  3   -1   5   2           3     5        -1   -1   1   0   21
+ 364 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 363 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 362 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 306 inst_DS_000_DMA  3   -1   0   1  0                       -1   -1   9   0   21
+ 356 inst_CLK_030_H  3   -1   0   1  0                       -1   -1   8   0   21
+ 358 SM_AMIGA_3_  3   -1   5   1                 5        -1   -1   5   0   21
+ 369  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 359 SM_AMIGA_2_  3   -1   5   1                 5        -1   -1   4   0   21
+ 333 RST_DLY_1_  3   -1   3   1           3              -1   -1   4   0   21
+ 293    N_317_i  3   -1   5   1                 5        -1   -1   4   0   21
+ 366      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 365  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 332 RST_DLY_0_  3   -1   3   1           3              -1   -1   3   0   21
+ 371      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 367  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 361     CIIN_0  3   -1   4   1              4           -1   -1   2   0   21
+ 334 RST_DLY_2_  3   -1   3   1           3              -1   -1   2   0   21
+ 354 CLK_000_N_SYNC_10_  3   -1   7   1                       7  -1   -1   1   0   21
+ 353 CLK_000_N_SYNC_9_  3   -1   0   1                       7  -1   -1   1   0   21
+ 352 CLK_000_N_SYNC_8_  3   -1   0   1  0                       -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_7_  3   -1   5   1  0                       -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_6_  3   -1   6   1                 5        -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_5_  3   -1   3   1                    6     -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_4_  3   -1   1   1           3              -1   -1   1   0   21
+ 347 CLK_000_N_SYNC_3_  3   -1   1   1     1                    -1   -1   1   0   21
+ 346 CLK_000_N_SYNC_2_  3   -1   1   1     1                    -1   -1   1   0   21
+ 345 CLK_000_N_SYNC_1_  3   -1   0   1     1                    -1   -1   1   0   21
+ 344 CLK_000_N_SYNC_0_  3   -1   4   1  0                       -1   -1   1   0   21
+ 343 CLK_000_P_SYNC_8_  3   -1   6   1                    6     -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_7_  3   -1   1   1                    6     -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_6_  3   -1   0   1     1                    -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_5_  3   -1   6   1  0                       -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_4_  3   -1   6   1                    6     -1   -1   1   0   21
+ 338 CLK_000_P_SYNC_3_  3   -1   4   1                    6     -1   -1   1   0   21
+ 337 CLK_000_P_SYNC_2_  3   -1   6   1              4           -1   -1   1   0   21
+ 336 CLK_000_P_SYNC_1_  3   -1   1   1                    6     -1   -1   1   0   21
+ 335 CLK_000_P_SYNC_0_  3   -1   4   1     1                    -1   -1   1   0   21
+ 326  IPL_D0_2_  3   -1   1   1     1                    -1   -1   1   0   21
+ 325  IPL_D0_1_  3   -1   3   1     1                    -1   -1   1   0   21
+ 324  IPL_D0_0_  3   -1   6   1     1                    -1   -1   1   0   21
+ 323 CLK_000_N_SYNC_11_  3   -1   7   1                    6     -1   -1   1   0   21
+ 321 CLK_000_P_SYNC_9_  3   -1   6   1                    6     -1   -1   1   0   21
+ 315 inst_DTACK_D0  3   -1   1   1                 5        -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   7  0  1  2  3     5  6  7  85   -1
+  96      A_19_  1   -1  -1   3        2     4        7  96   -1
+  95      A_16_  1   -1  -1   3        2     4        7  95   -1
+  94      A_18_  1   -1  -1   3        2     4        7  94   -1
+  58      A_17_  1   -1  -1   3        2     4        7  58   -1
+  57      FC_1_  1   -1  -1   3        2     4        7  57   -1
+  56      FC_0_  1   -1  -1   3        2     4        7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  66     IPL_0_  1   -1  -1   2     1              6     66   -1
+  63    CLK_030  1   -1  -1   2  0                    7  63   -1
+  55     IPL_1_  1   -1  -1   2     1     3              55   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  93      A_21_  1   -1  -1   1              4           93   -1
+  92      A_20_  1   -1  -1   1              4           92   -1
+  84      A_23_  1   -1  -1   1              4           84   -1
+  83      A_22_  1   -1  -1   1              4           83   -1
+  67     IPL_2_  1   -1  -1   1     1                    67   -1
+  59         A1  1   -1  -1   1     1                    59   -1
+  35        VPA  1   -1  -1   1                 5        35   -1
+  29      DTACK  1   -1  -1   1     1                    29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1  0                       13   -1
+  10    CLK_000  1   -1  -1   1     1                    10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
+140 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  41     AS_000  5   -1   4   5  0  1  2     4        7  41   -1   1   0   21
+  79     RW_000  5  365   7   3  0           4     6     79   -1   3   0   21
+  40       BERR  5   -1   4   3        2        5     7  40   -1   1   0   21
+  70         RW  5  371   6   2        2              7  70   -1   2   0   21
+  81     AS_030  5   -1   7   2              4        7  81   -1   1   0   21
+  31    UDS_000  5   -1   3   2  0                 6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   2  0                 6     30   -1   1   0   21
+  68         A0  5  366   6   1  0                       68   -1   3   0   21
+  78    SIZE_1_  5   -1   7   1  0                       78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1  0                       69   -1   1   0   21
+   8 IPL_030_2_  5  362   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  364   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  363   1   0                           6   -1  10   0   21
+  80     DSACK1  5  369   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  368   7   0                          82   -1   3   0   21
+  34        VMA  5  370   3   0                          34   -1   3   0   21
+  65          E  0        6   0                          65   -1   2   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  367   3   0                          28   -1   2   0   21
+  97     DS_030  0        0   0                          97   -1   1   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+   2      RESET  0        1   0                           2   -1   1   0   21
+ 368 RN_BGACK_030  3   82   7   7  0  1  2  3  4     6  7  82   -1   3   0   21
+ 302 inst_nEXP_SPACE_D0reg  3   -1   0   7  0     2  3  4  5  6  7  -1   -1   1   0   21
+ 316 inst_RESET_OUT  3   -1   3   6  0  1     3  4     6  7  -1   -1   2   0   21
+ 320 inst_CLK_000_PE  3   -1   6   5     1  2  3     5     7  -1   -1   1   0   21
+ 360 SM_AMIGA_i_7_  3   -1   5   4        2  3     5     7  -1   -1  14   0   21
+ 301 inst_AS_030_D0  3   -1   7   4        2  3  4        7  -1   -1   1   0   21
+ 294 cpu_est_2_  3   -1   3   3           3     5  6     -1   -1   4   0   21
+ 355 SM_AMIGA_6_  3   -1   5   3  0     2        5        -1   -1   3   0   21
+ 299 SM_AMIGA_5_  3   -1   5   3        2        5     7  -1   -1   3   0   21
+ 297 cpu_est_1_  3   -1   3   3           3     5  6     -1   -1   3   0   21
+ 295 cpu_est_3_  3   -1   5   3           3     5  6     -1   -1   3   0   21
+ 328 SM_AMIGA_0_  3   -1   5   3        2        5     7  -1   -1   2   0   21
+ 307 CYCLE_DMA_0_  3   -1   1   3  0  1  2                 -1   -1   2   0   21
+ 319 inst_CLK_000_D0  3   -1   1   3           3  4  5        -1   -1   1   0   21
+ 314 inst_CLK_OUT_PRE_D  3   -1   0   3     1              6  7  -1   -1   1   0   21
+ 304 inst_BGACK_030_INT_D  3   -1   7   3     1  2           6     -1   -1   1   0   21
+ 305 inst_AS_000_DMA  3   -1   0   2  0                    7  -1   -1   7   0   21
+ 303 inst_AS_030_000_SYNC  3   -1   2   2        2        5        -1   -1   7   0   21
+ 331 inst_DS_000_ENABLE  3   -1   2   2        2  3              -1   -1   5   0   21
+ 370     RN_VMA  3   34   3   2           3     5        34   -1   3   0   21
+ 357 SM_AMIGA_1_  3   -1   5   2                 5     7  -1   -1   3   0   21
+ 330 SM_AMIGA_4_  3   -1   5   2        2        5        -1   -1   3   0   21
+ 313 inst_LDS_000_INT  3   -1   0   2  0        3              -1   -1   3   0   21
+ 310 SIZE_DMA_1_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 309 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 308 CYCLE_DMA_1_  3   -1   2   2  0     2                 -1   -1   3   0   21
+ 329 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   1   2     1     3              -1   -1   2   0   21
+ 312 inst_UDS_000_INT  3   -1   0   2  0        3              -1   -1   2   0   21
+ 300 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   1   2     1  2                 -1   -1   2   0   21
+ 298 inst_AS_000_INT  3   -1   2   2        2     4           -1   -1   2   0   21
+ 296 cpu_est_0_  3   -1   3   2           3     5        -1   -1   2   0   21
+ 327 inst_CLK_000_NE_D0  3   -1   3   2           3     5        -1   -1   1   0   21
+ 322 inst_CLK_000_NE  3   -1   6   2           3     5        -1   -1   1   0   21
+ 318 inst_CLK_000_D1  3   -1   4   2              4  5        -1   -1   1   0   21
+ 317 inst_CLK_OUT_PRE_50  3   -1   5   2  0              5        -1   -1   1   0   21
+ 311 inst_VPA_D  3   -1   5   2           3     5        -1   -1   1   0   21
+ 364 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 363 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 362 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 306 inst_DS_000_DMA  3   -1   0   1  0                       -1   -1   9   0   21
+ 356 inst_CLK_030_H  3   -1   0   1  0                       -1   -1   8   0   21
+ 358 SM_AMIGA_3_  3   -1   5   1                 5        -1   -1   5   0   21
+ 369  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 359 SM_AMIGA_2_  3   -1   5   1                 5        -1   -1   4   0   21
+ 333 RST_DLY_1_  3   -1   3   1           3              -1   -1   4   0   21
+ 293    N_317_i  3   -1   5   1                 5        -1   -1   4   0   21
+ 366      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 365  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 332 RST_DLY_0_  3   -1   3   1           3              -1   -1   3   0   21
+ 371      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 367  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 361     CIIN_0  3   -1   4   1              4           -1   -1   2   0   21
+ 334 RST_DLY_2_  3   -1   3   1           3              -1   -1   2   0   21
+ 354 CLK_000_N_SYNC_10_  3   -1   7   1                       7  -1   -1   1   0   21
+ 353 CLK_000_N_SYNC_9_  3   -1   0   1                       7  -1   -1   1   0   21
+ 352 CLK_000_N_SYNC_8_  3   -1   0   1  0                       -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_7_  3   -1   5   1  0                       -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_6_  3   -1   6   1                 5        -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_5_  3   -1   3   1                    6     -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_4_  3   -1   1   1           3              -1   -1   1   0   21
+ 347 CLK_000_N_SYNC_3_  3   -1   1   1     1                    -1   -1   1   0   21
+ 346 CLK_000_N_SYNC_2_  3   -1   1   1     1                    -1   -1   1   0   21
+ 345 CLK_000_N_SYNC_1_  3   -1   0   1     1                    -1   -1   1   0   21
+ 344 CLK_000_N_SYNC_0_  3   -1   4   1  0                       -1   -1   1   0   21
+ 343 CLK_000_P_SYNC_8_  3   -1   6   1                    6     -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_7_  3   -1   1   1                    6     -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_6_  3   -1   0   1     1                    -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_5_  3   -1   6   1  0                       -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_4_  3   -1   6   1                    6     -1   -1   1   0   21
+ 338 CLK_000_P_SYNC_3_  3   -1   4   1                    6     -1   -1   1   0   21
+ 337 CLK_000_P_SYNC_2_  3   -1   6   1              4           -1   -1   1   0   21
+ 336 CLK_000_P_SYNC_1_  3   -1   1   1                    6     -1   -1   1   0   21
+ 335 CLK_000_P_SYNC_0_  3   -1   4   1     1                    -1   -1   1   0   21
+ 326  IPL_D0_2_  3   -1   1   1     1                    -1   -1   1   0   21
+ 325  IPL_D0_1_  3   -1   3   1     1                    -1   -1   1   0   21
+ 324  IPL_D0_0_  3   -1   6   1     1                    -1   -1   1   0   21
+ 323 CLK_000_N_SYNC_11_  3   -1   7   1                    6     -1   -1   1   0   21
+ 321 CLK_000_P_SYNC_9_  3   -1   6   1                    6     -1   -1   1   0   21
+ 315 inst_DTACK_D0  3   -1   1   1                 5        -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   7  0  1  2  3     5  6  7  85   -1
+  96      A_19_  1   -1  -1   3        2     4        7  96   -1
+  95      A_16_  1   -1  -1   3        2     4        7  95   -1
+  94      A_18_  1   -1  -1   3        2     4        7  94   -1
+  58      A_17_  1   -1  -1   3        2     4        7  58   -1
+  57      FC_1_  1   -1  -1   3        2     4        7  57   -1
+  56      FC_0_  1   -1  -1   3        2     4        7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  66     IPL_0_  1   -1  -1   2     1              6     66   -1
+  63    CLK_030  1   -1  -1   2  0                    7  63   -1
+  55     IPL_1_  1   -1  -1   2     1     3              55   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  93      A_21_  1   -1  -1   1              4           93   -1
+  92      A_20_  1   -1  -1   1              4           92   -1
+  84      A_23_  1   -1  -1   1              4           84   -1
+  83      A_22_  1   -1  -1   1              4           83   -1
+  67     IPL_2_  1   -1  -1   1     1                    67   -1
+  59         A1  1   -1  -1   1     1                    59   -1
+  35        VPA  1   -1  -1   1                 5        35   -1
+  29      DTACK  1   -1  -1   1     1                    29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1  0                       13   -1
+  10    CLK_000  1   -1  -1   1     1                    10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
+141 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  40       BERR  5   -1   4   4  0     2        5     7  40   -1   1   0   21
+  79     RW_000  5  366   7   3  0           4     6     79   -1   3   0   21
+  41     AS_000  5   -1   4   3  0           4        7  41   -1   1   0   21
+  70         RW  5  372   6   2                 5     7  70   -1   2   0   21
+  81     AS_030  5   -1   7   2              4        7  81   -1   1   0   21
+  31    UDS_000  5   -1   3   2  0                 6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   2  0                 6     30   -1   1   0   21
+  68         A0  5  367   6   1     1                    68   -1   3   0   21
+  78    SIZE_1_  5   -1   7   1     1                    78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1     1                    69   -1   1   0   21
+   8 IPL_030_2_  5  363   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  365   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  364   1   0                           6   -1  10   0   21
+  80     DSACK1  5  370   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  369   7   0                          82   -1   3   0   21
+  34        VMA  5  371   3   0                          34   -1   3   0   21
+  65          E  0        6   0                          65   -1   2   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  368   3   0                          28   -1   2   0   21
+  97     DS_030  0        0   0                          97   -1   1   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+   2      RESET  0        1   0                           2   -1   1   0   21
+ 369 RN_BGACK_030  3   82   7   7  0     2  3  4  5  6  7  82   -1   3   0   21
+ 315 inst_RESET_OUT  3   -1   5   7  0  1     3  4  5  6  7  -1   -1   2   0   21
+ 301 inst_nEXP_SPACE_D0reg  3   -1   5   7  0     2  3  4  5  6  7  -1   -1   1   0   21
+ 320 inst_CLK_000_PE  3   -1   1   5  0     2  3     5     7  -1   -1   1   0   21
+ 300 inst_AS_030_D0  3   -1   7   5  0        3  4  5     7  -1   -1   1   0   21
+ 361 SM_AMIGA_i_7_  3   -1   2   4        2  3     5     7  -1   -1  14   0   21
+ 298 SM_AMIGA_5_  3   -1   2   4  0     2        5     7  -1   -1   3   0   21
+ 322 inst_CLK_000_NE  3   -1   4   4  0     2  3     5        -1   -1   1   0   21
+ 294 cpu_est_2_  3   -1   6   3        2  3        6     -1   -1   4   0   21
+ 355 SM_AMIGA_6_  3   -1   2   3     1  2        5        -1   -1   3   0   21
+ 330 SM_AMIGA_4_  3   -1   0   3  0     2        5        -1   -1   3   0   21
+ 295 cpu_est_3_  3   -1   2   3        2  3        6     -1   -1   3   0   21
+ 293 cpu_est_1_  3   -1   2   3        2  3        6     -1   -1   3   0   21
+ 328 SM_AMIGA_0_  3   -1   2   3        2        5     7  -1   -1   2   0   21
+ 296 cpu_est_0_  3   -1   2   3        2  3        6     -1   -1   2   0   21
+ 319 inst_CLK_000_D0  3   -1   0   3        2  3  4           -1   -1   1   0   21
+ 313 inst_CLK_OUT_PRE_D  3   -1   3   3     1              6  7  -1   -1   1   0   21
+ 304 inst_AS_000_DMA  3   -1   0   2  0                    7  -1   -1   7   0   21
+ 302 inst_AS_030_000_SYNC  3   -1   5   2        2        5        -1   -1   7   0   21
+ 331 inst_DS_000_ENABLE  3   -1   5   2           3     5        -1   -1   5   0   21
+ 371     RN_VMA  3   34   3   2        2  3              34   -1   3   0   21
+ 357 SM_AMIGA_1_  3   -1   2   2        2              7  -1   -1   3   0   21
+ 312 inst_LDS_000_INT  3   -1   1   2     1     3              -1   -1   3   0   21
+ 309 SIZE_DMA_1_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 308 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 329 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   6   2           3        6     -1   -1   2   0   21
+ 317 inst_CLK_OUT_PRE_25  3   -1   6   2           3        6     -1   -1   2   0   21
+ 311 inst_UDS_000_INT  3   -1   1   2     1     3              -1   -1   2   0   21
+ 299 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   6   2        2           6     -1   -1   2   0   21
+ 297 inst_AS_000_INT  3   -1   0   2  0           4           -1   -1   2   0   21
+ 327 inst_CLK_000_NE_D0  3   -1   5   2        2           6     -1   -1   1   0   21
+ 318 inst_CLK_000_D1  3   -1   4   2        2     4           -1   -1   1   0   21
+ 316 inst_CLK_OUT_PRE_50  3   -1   5   2                 5  6     -1   -1   1   0   21
+ 310 inst_VPA_D  3   -1   3   2        2  3              -1   -1   1   0   21
+ 303 inst_BGACK_030_INT_D  3   -1   7   2                 5  6     -1   -1   1   0   21
+ 365 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 364 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 363 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 305 inst_DS_000_DMA  3   -1   0   1  0                       -1   -1   9   0   21
+ 356 inst_CLK_030_H  3   -1   0   1  0                       -1   -1   8   0   21
+ 358 SM_AMIGA_3_  3   -1   2   1        2                 -1   -1   5   0   21
+ 370  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 359 SM_AMIGA_2_  3   -1   2   1        2                 -1   -1   4   0   21
+ 333 RST_DLY_1_  3   -1   5   1                 5        -1   -1   4   0   21
+ 367      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 366  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 332 RST_DLY_0_  3   -1   5   1                 5        -1   -1   3   0   21
+ 307 CYCLE_DMA_1_  3   -1   0   1  0                       -1   -1   3   0   21
+ 372      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 368  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 362     CIIN_0  3   -1   4   1              4           -1   -1   2   0   21
+ 360    N_199_i  3   -1   2   1        2                 -1   -1   2   0   21
+ 334 RST_DLY_2_  3   -1   5   1                 5        -1   -1   2   0   21
+ 306 CYCLE_DMA_0_  3   -1   0   1  0                       -1   -1   2   0   21
+ 354 CLK_000_N_SYNC_10_  3   -1   7   1                       7  -1   -1   1   0   21
+ 353 CLK_000_N_SYNC_9_  3   -1   0   1                       7  -1   -1   1   0   21
+ 352 CLK_000_N_SYNC_8_  3   -1   3   1  0                       -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_7_  3   -1   3   1           3              -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_6_  3   -1   5   1           3              -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_5_  3   -1   2   1                 5        -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_4_  3   -1   1   1        2                 -1   -1   1   0   21
+ 347 CLK_000_N_SYNC_3_  3   -1   1   1     1                    -1   -1   1   0   21
+ 346 CLK_000_N_SYNC_2_  3   -1   1   1     1                    -1   -1   1   0   21
+ 345 CLK_000_N_SYNC_1_  3   -1   0   1     1                    -1   -1   1   0   21
+ 344 CLK_000_N_SYNC_0_  3   -1   4   1  0                       -1   -1   1   0   21
+ 343 CLK_000_P_SYNC_8_  3   -1   1   1                    6     -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_7_  3   -1   3   1     1                    -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_6_  3   -1   6   1           3              -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_5_  3   -1   3   1                    6     -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_4_  3   -1   1   1           3              -1   -1   1   0   21
+ 338 CLK_000_P_SYNC_3_  3   -1   1   1     1                    -1   -1   1   0   21
+ 337 CLK_000_P_SYNC_2_  3   -1   3   1     1                    -1   -1   1   0   21
+ 336 CLK_000_P_SYNC_1_  3   -1   0   1           3              -1   -1   1   0   21
+ 335 CLK_000_P_SYNC_0_  3   -1   4   1  0                       -1   -1   1   0   21
+ 326  IPL_D0_2_  3   -1   3   1     1                    -1   -1   1   0   21
+ 325  IPL_D0_1_  3   -1   2   1     1                    -1   -1   1   0   21
+ 324  IPL_D0_0_  3   -1   0   1     1                    -1   -1   1   0   21
+ 323 CLK_000_N_SYNC_11_  3   -1   7   1              4           -1   -1   1   0   21
+ 321 CLK_000_P_SYNC_9_  3   -1   6   1     1                    -1   -1   1   0   21
+ 314 inst_DTACK_D0  3   -1   6   1        2                 -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   7  0  1  2  3     5  6  7  85   -1
+  96      A_19_  1   -1  -1   3              4  5     7  96   -1
+  95      A_16_  1   -1  -1   3              4  5     7  95   -1
+  94      A_18_  1   -1  -1   3              4  5     7  94   -1
+  58      A_17_  1   -1  -1   3              4  5     7  58   -1
+  57      FC_1_  1   -1  -1   3              4  5     7  57   -1
+  56      FC_0_  1   -1  -1   3              4  5     7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  67     IPL_2_  1   -1  -1   2     1     3              67   -1
+  66     IPL_0_  1   -1  -1   2  0  1                    66   -1
+  63    CLK_030  1   -1  -1   2  0                    7  63   -1
+  55     IPL_1_  1   -1  -1   2     1  2                 55   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  93      A_21_  1   -1  -1   1              4           93   -1
+  92      A_20_  1   -1  -1   1              4           92   -1
+  84      A_23_  1   -1  -1   1              4           84   -1
+  83      A_22_  1   -1  -1   1              4           83   -1
+  59         A1  1   -1  -1   1                    6     59   -1
+  35        VPA  1   -1  -1   1           3              35   -1
+  29      DTACK  1   -1  -1   1                    6     29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1                 5        13   -1
+  10    CLK_000  1   -1  -1   1  0                       10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
+141 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  41     AS_000  5   -1   4   4  0           4     6  7  41   -1   1   0   21
+  40       BERR  5   -1   4   4  0     2        5     7  40   -1   1   0   21
+  79     RW_000  5  366   7   2              4     6     79   -1   3   0   21
+  70         RW  5  372   6   2        2              7  70   -1   2   0   21
+  81     AS_030  5   -1   7   2              4        7  81   -1   1   0   21
+  68         A0  5  367   6   1  0                       68   -1   3   0   21
+  78    SIZE_1_  5   -1   7   1  0                       78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1  0                       69   -1   1   0   21
+  31    UDS_000  5   -1   3   1                    6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   1                    6     30   -1   1   0   21
+   8 IPL_030_2_  5  363   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  365   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  364   1   0                           6   -1  10   0   21
+  80     DSACK1  5  370   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  369   7   0                          82   -1   3   0   21
+  34        VMA  5  371   3   0                          34   -1   3   0   21
+  65          E  0        6   0                          65   -1   2   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  368   3   0                          28   -1   2   0   21
+  97     DS_030  0        0   0                          97   -1   1   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+   2      RESET  0        1   0                           2   -1   1   0   21
+ 369 RN_BGACK_030  3   82   7   7  0  1  2  3  4     6  7  82   -1   3   0   21
+ 302 inst_nEXP_SPACE_D0reg  3   -1   3   7  0     2  3  4  5  6  7  -1   -1   1   0   21
+ 316 inst_RESET_OUT  3   -1   1   6  0  1     3  4     6  7  -1   -1   2   0   21
+ 321 inst_CLK_000_PE  3   -1   6   5        2  3     5  6  7  -1   -1   1   0   21
+ 301 inst_AS_030_D0  3   -1   7   5  0     2  3  4        7  -1   -1   1   0   21
+ 299 SM_AMIGA_5_  3   -1   5   4  0     2        5     7  -1   -1   3   0   21
+ 320 inst_CLK_000_D0  3   -1   0   4  0     2  3     5        -1   -1   1   0   21
+ 361 SM_AMIGA_i_7_  3   -1   5   3        2  3           7  -1   -1  14   0   21
+ 295 cpu_est_2_  3   -1   3   3           3     5  6     -1   -1   4   0   21
+ 356 SM_AMIGA_6_  3   -1   2   3  0     2        5        -1   -1   3   0   21
+ 296 cpu_est_3_  3   -1   5   3           3     5  6     -1   -1   3   0   21
+ 294 cpu_est_1_  3   -1   3   3           3     5  6     -1   -1   3   0   21
+ 329 SM_AMIGA_0_  3   -1   5   3        2        5     7  -1   -1   2   0   21
+ 323 inst_CLK_000_NE  3   -1   4   3     1     3     5        -1   -1   1   0   21
+ 319 inst_CLK_000_D1  3   -1   3   3  0     2        5        -1   -1   1   0   21
+ 317 inst_CLK_OUT_PRE_50  3   -1   4   3  0  1        4           -1   -1   1   0   21
+ 304 inst_BGACK_030_INT_D  3   -1   7   3     1  2           6     -1   -1   1   0   21
+ 306 inst_DS_000_DMA  3   -1   6   2  0                 6     -1   -1   9   0   21
+ 305 inst_AS_000_DMA  3   -1   6   2                    6  7  -1   -1   7   0   21
+ 303 inst_AS_030_000_SYNC  3   -1   2   2        2        5        -1   -1   7   0   21
+ 332 inst_DS_000_ENABLE  3   -1   2   2        2  3              -1   -1   5   0   21
+ 371     RN_VMA  3   34   3   2           3     5        34   -1   3   0   21
+ 358 SM_AMIGA_1_  3   -1   5   2                 5     7  -1   -1   3   0   21
+ 331 SM_AMIGA_4_  3   -1   5   2        2        5        -1   -1   3   0   21
+ 313 inst_LDS_000_INT  3   -1   0   2  0        3              -1   -1   3   0   21
+ 310 SIZE_DMA_1_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 309 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 330 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   1   2     1     3              -1   -1   2   0   21
+ 318 inst_CLK_OUT_PRE_25  3   -1   0   2  0        3              -1   -1   2   0   21
+ 312 inst_UDS_000_INT  3   -1   0   2  0        3              -1   -1   2   0   21
+ 300 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   1   2     1  2                 -1   -1   2   0   21
+ 298 inst_AS_000_INT  3   -1   0   2  0           4           -1   -1   2   0   21
+ 297 cpu_est_0_  3   -1   3   2           3     5        -1   -1   2   0   21
+ 328 inst_CLK_000_NE_D0  3   -1   3   2           3     5        -1   -1   1   0   21
+ 314 inst_CLK_OUT_PRE_D  3   -1   3   2                    6  7  -1   -1   1   0   21
+ 311 inst_VPA_D  3   -1   1   2           3     5        -1   -1   1   0   21
+ 365 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 364 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 363 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 357 inst_CLK_030_H  3   -1   6   1                    6     -1   -1   8   0   21
+ 359 SM_AMIGA_3_  3   -1   5   1                 5        -1   -1   5   0   21
+ 370  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 360 SM_AMIGA_2_  3   -1   5   1                 5        -1   -1   4   0   21
+ 334 RST_DLY_1_  3   -1   1   1     1                    -1   -1   4   0   21
+ 293    N_201_i  3   -1   5   1                 5        -1   -1   4   0   21
+ 367      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 366  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 333 RST_DLY_0_  3   -1   1   1     1                    -1   -1   3   0   21
+ 308 CYCLE_DMA_1_  3   -1   6   1                    6     -1   -1   3   0   21
+ 372      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 368  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 362     CIIN_0  3   -1   4   1              4           -1   -1   2   0   21
+ 335 RST_DLY_2_  3   -1   1   1     1                    -1   -1   2   0   21
+ 307 CYCLE_DMA_0_  3   -1   6   1                    6     -1   -1   2   0   21
+ 355 CLK_000_N_SYNC_10_  3   -1   7   1                       7  -1   -1   1   0   21
+ 354 CLK_000_N_SYNC_9_  3   -1   0   1                       7  -1   -1   1   0   21
+ 353 CLK_000_N_SYNC_8_  3   -1   3   1  0                       -1   -1   1   0   21
+ 352 CLK_000_N_SYNC_7_  3   -1   1   1           3              -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_6_  3   -1   1   1     1                    -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_5_  3   -1   3   1     1                    -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_4_  3   -1   0   1           3              -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_3_  3   -1   6   1  0                       -1   -1   1   0   21
+ 347 CLK_000_N_SYNC_2_  3   -1   6   1                    6     -1   -1   1   0   21
+ 346 CLK_000_N_SYNC_1_  3   -1   6   1                    6     -1   -1   1   0   21
+ 345 CLK_000_N_SYNC_0_  3   -1   5   1                    6     -1   -1   1   0   21
+ 344 CLK_000_P_SYNC_8_  3   -1   1   1  0                       -1   -1   1   0   21
+ 343 CLK_000_P_SYNC_7_  3   -1   5   1     1                    -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_6_  3   -1   4   1                 5        -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_5_  3   -1   0   1              4           -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_4_  3   -1   3   1  0                       -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_3_  3   -1   2   1           3              -1   -1   1   0   21
+ 338 CLK_000_P_SYNC_2_  3   -1   5   1        2                 -1   -1   1   0   21
+ 337 CLK_000_P_SYNC_1_  3   -1   4   1                 5        -1   -1   1   0   21
+ 336 CLK_000_P_SYNC_0_  3   -1   0   1              4           -1   -1   1   0   21
+ 327  IPL_D0_2_  3   -1   0   1     1                    -1   -1   1   0   21
+ 326  IPL_D0_1_  3   -1   5   1     1                    -1   -1   1   0   21
+ 325  IPL_D0_0_  3   -1   2   1     1                    -1   -1   1   0   21
+ 324 CLK_000_N_SYNC_11_  3   -1   7   1              4           -1   -1   1   0   21
+ 322 CLK_000_P_SYNC_9_  3   -1   0   1                    6     -1   -1   1   0   21
+ 315 inst_DTACK_D0  3   -1   1   1                 5        -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   7  0  1  2  3     5  6  7  85   -1
+  96      A_19_  1   -1  -1   3        2     4        7  96   -1
+  95      A_16_  1   -1  -1   3        2     4        7  95   -1
+  94      A_18_  1   -1  -1   3        2     4        7  94   -1
+  58      A_17_  1   -1  -1   3        2     4        7  58   -1
+  57      FC_1_  1   -1  -1   3        2     4        7  57   -1
+  56      FC_0_  1   -1  -1   3        2     4        7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  67     IPL_2_  1   -1  -1   2  0  1                    67   -1
+  66     IPL_0_  1   -1  -1   2     1  2                 66   -1
+  63    CLK_030  1   -1  -1   2                    6  7  63   -1
+  55     IPL_1_  1   -1  -1   2     1           5        55   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  93      A_21_  1   -1  -1   1              4           93   -1
+  92      A_20_  1   -1  -1   1              4           92   -1
+  84      A_23_  1   -1  -1   1              4           84   -1
+  83      A_22_  1   -1  -1   1              4           83   -1
+  59         A1  1   -1  -1   1     1                    59   -1
+  35        VPA  1   -1  -1   1     1                    35   -1
+  29      DTACK  1   -1  -1   1     1                    29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1           3              13   -1
+  10    CLK_000  1   -1  -1   1  0                       10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
+142 "number of signals after reading design file"
+
+"sig    sig    sig pair blk fan                                   PT xor sync"
+"num   name   type  sig num out                         pin node cnt  PT type"
+"---   ----   ---- ---- --- ---                         --- ---- --- --- ----"
+
+  40       BERR  5   -1   4   5  0  1  2        5     7  40   -1   1   0   21
+  79     RW_000  5  367   7   3  0           4     6     79   -1   3   0   21
+  41     AS_000  5   -1   4   3  0           4        7  41   -1   1   0   21
+  70         RW  5  373   6   2        2              7  70   -1   2   0   21
+  81     AS_030  5   -1   7   2              4        7  81   -1   1   0   21
+  31    UDS_000  5   -1   3   2  0                 6     31   -1   1   0   21
+  30    LDS_000  5   -1   3   2  0                 6     30   -1   1   0   21
+  68         A0  5  368   6   1  0                       68   -1   3   0   21
+  78    SIZE_1_  5   -1   7   1  0                       78   -1   1   0   21
+  69    SIZE_0_  5   -1   6   1  0                       69   -1   1   0   21
+   8 IPL_030_2_  5  364   1   0                           8   -1  10   0   21
+   7 IPL_030_0_  5  366   1   0                           7   -1  10   0   21
+   6 IPL_030_1_  5  365   1   0                           6   -1  10   0   21
+  80     DSACK1  5  371   7   0                          80   -1   4   0   21
+  82  BGACK_030  5  370   7   0                          82   -1   3   0   21
+  34        VMA  5  372   3   0                          34   -1   3   0   21
+  65          E  0        6   0                          65   -1   2   0   21
+  47 AMIGA_BUS_DATA_DIR  0        4   0                          47   -1   2   0   21
+  33 AMIGA_BUS_ENABLE_HIGH  0        3   0                          33   -1   2   0   21
+  28     BG_000  5  369   3   0                          28   -1   2   0   21
+  97     DS_030  0        0   0                          97   -1   1   0   21
+  91       AVEC  0        0   0                          91   -1   1   0   21
+  77     FPU_CS  0        7   0                          77   -1   1   0   21
+  64 CLK_DIV_OUT  0        6   0                          64   -1   1   0   21
+  46       CIIN  0        4   0                          46   -1   1   0   21
+  32 AMIGA_ADDR_ENABLE  0        3   0                          32   -1   1   0   21
+  19 AMIGA_BUS_ENABLE_LOW  0        2   0                          19   -1   1   0   21
+   9    CLK_EXP  0        1   0                           9   -1   1   0   21
+   2      RESET  0        1   0                           2   -1   1   0   21
+ 370 RN_BGACK_030  3   82   7   7  0  1  2  3  4     6  7  82   -1   3   0   21
+ 315 inst_RESET_OUT  3   -1   6   6  0  1     3  4     6  7  -1   -1   2   0   21
+ 301 inst_nEXP_SPACE_D0reg  3   -1   7   6  0     2  3  4     6  7  -1   -1   1   0   21
+ 321 inst_CLK_000_PE  3   -1   5   5  0     2  3     5     7  -1   -1   1   0   21
+ 300 inst_AS_030_D0  3   -1   7   5     1  2  3  4        7  -1   -1   1   0   21
+ 359 SM_AMIGA_1_  3   -1   0   4  0     2        5     7  -1   -1   3   0   21
+ 298 SM_AMIGA_5_  3   -1   5   4     1  2        5     7  -1   -1   3   0   21
+ 324 inst_CLK_000_NE  3   -1   6   4  0        3     5  6     -1   -1   1   0   21
+ 320 inst_CLK_000_D0  3   -1   3   4     1  2  3        6     -1   -1   1   0   21
+ 362 SM_AMIGA_i_7_  3   -1   5   3        2  3           7  -1   -1  14   0   21
+ 361 SM_AMIGA_2_  3   -1   5   3  0     2        5        -1   -1   4   0   21
+ 295 cpu_est_2_  3   -1   3   3           3     5  6     -1   -1   4   0   21
+ 357 SM_AMIGA_6_  3   -1   2   3  0     2        5        -1   -1   3   0   21
+ 296 cpu_est_3_  3   -1   3   3           3     5  6     -1   -1   3   0   21
+ 294 cpu_est_1_  3   -1   3   3           3     5  6     -1   -1   3   0   21
+ 330 SM_AMIGA_0_  3   -1   5   3        2        5     7  -1   -1   2   0   21
+ 319 inst_CLK_000_D1  3   -1   2   3     1  2           6     -1   -1   1   0   21
+ 303 inst_BGACK_030_INT_D  3   -1   4   3     1  2           6     -1   -1   1   0   21
+ 304 inst_AS_000_DMA  3   -1   0   2  0                    7  -1   -1   7   0   21
+ 360 SM_AMIGA_3_  3   -1   5   2        2        5        -1   -1   5   0   21
+ 333 inst_DS_000_ENABLE  3   -1   2   2        2  3              -1   -1   5   0   21
+ 372     RN_VMA  3   34   3   2           3     5        34   -1   3   0   21
+ 332 SM_AMIGA_4_  3   -1   5   2        2        5        -1   -1   3   0   21
+ 312 inst_LDS_000_INT  3   -1   0   2  0        3              -1   -1   3   0   21
+ 309 SIZE_DMA_1_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 308 SIZE_DMA_0_  3   -1   6   2                    6  7  -1   -1   3   0   21
+ 331 inst_AMIGA_BUS_ENABLE_DMA_HIGH  3   -1   1   2     1     3              -1   -1   2   0   21
+ 318 inst_CLK_OUT_PRE_25  3   -1   6   2           3        6     -1   -1   2   0   21
+ 311 inst_UDS_000_INT  3   -1   0   2  0        3              -1   -1   2   0   21
+ 299 inst_AMIGA_BUS_ENABLE_DMA_LOW  3   -1   1   2     1  2                 -1   -1   2   0   21
+ 297 inst_AS_000_INT  3   -1   1   2     1        4           -1   -1   2   0   21
+ 293 cpu_est_0_  3   -1   3   2           3     5        -1   -1   2   0   21
+ 329 inst_CLK_000_NE_D0  3   -1   3   2           3     5        -1   -1   1   0   21
+ 316 inst_CLK_OUT_PRE_50  3   -1   4   2              4     6     -1   -1   1   0   21
+ 313 inst_CLK_OUT_PRE_D  3   -1   3   2                    6  7  -1   -1   1   0   21
+ 310 inst_VPA_D  3   -1   2   2           3     5        -1   -1   1   0   21
+ 366 RN_IPL_030_0_  3    7   1   1     1                     7   -1  10   0   21
+ 365 RN_IPL_030_1_  3    6   1   1     1                     6   -1  10   0   21
+ 364 RN_IPL_030_2_  3    8   1   1     1                     8   -1  10   0   21
+ 305 inst_DS_000_DMA  3   -1   0   1  0                       -1   -1   9   0   21
+ 358 inst_CLK_030_H  3   -1   0   1  0                       -1   -1   8   0   21
+ 302 inst_AS_030_000_SYNC  3   -1   2   1        2                 -1   -1   7   0   21
+ 371  RN_DSACK1  3   80   7   1                       7  80   -1   4   0   21
+ 335 RST_DLY_1_  3   -1   6   1                    6     -1   -1   4   0   21
+ 317    N_210_i  3   -1   2   1                 5        -1   -1   4   0   21
+ 368      RN_A0  3   68   6   1                    6     68   -1   3   0   21
+ 367  RN_RW_000  3   79   7   1                       7  79   -1   3   0   21
+ 334 RST_DLY_0_  3   -1   6   1                    6     -1   -1   3   0   21
+ 307 CYCLE_DMA_1_  3   -1   0   1  0                       -1   -1   3   0   21
+ 373      RN_RW  3   70   6   1                    6     70   -1   2   0   21
+ 369  RN_BG_000  3   28   3   1           3              28   -1   2   0   21
+ 363     CIIN_0  3   -1   4   1              4           -1   -1   2   0   21
+ 336 RST_DLY_2_  3   -1   6   1                    6     -1   -1   2   0   21
+ 306 CYCLE_DMA_0_  3   -1   0   1  0                       -1   -1   2   0   21
+ 356 CLK_000_N_SYNC_10_  3   -1   7   1                       7  -1   -1   1   0   21
+ 355 CLK_000_N_SYNC_9_  3   -1   3   1                       7  -1   -1   1   0   21
+ 354 CLK_000_N_SYNC_8_  3   -1   1   1           3              -1   -1   1   0   21
+ 353 CLK_000_N_SYNC_7_  3   -1   6   1     1                    -1   -1   1   0   21
+ 352 CLK_000_N_SYNC_6_  3   -1   0   1                    6     -1   -1   1   0   21
+ 351 CLK_000_N_SYNC_5_  3   -1   0   1  0                       -1   -1   1   0   21
+ 350 CLK_000_N_SYNC_4_  3   -1   3   1  0                       -1   -1   1   0   21
+ 349 CLK_000_N_SYNC_3_  3   -1   3   1           3              -1   -1   1   0   21
+ 348 CLK_000_N_SYNC_2_  3   -1   5   1           3              -1   -1   1   0   21
+ 347 CLK_000_N_SYNC_1_  3   -1   5   1                 5        -1   -1   1   0   21
+ 346 CLK_000_N_SYNC_0_  3   -1   6   1                 5        -1   -1   1   0   21
+ 345 CLK_000_P_SYNC_8_  3   -1   6   1                 5        -1   -1   1   0   21
+ 344 CLK_000_P_SYNC_7_  3   -1   1   1                    6     -1   -1   1   0   21
+ 343 CLK_000_P_SYNC_6_  3   -1   5   1     1                    -1   -1   1   0   21
+ 342 CLK_000_P_SYNC_5_  3   -1   1   1                 5        -1   -1   1   0   21
+ 341 CLK_000_P_SYNC_4_  3   -1   4   1     1                    -1   -1   1   0   21
+ 340 CLK_000_P_SYNC_3_  3   -1   5   1              4           -1   -1   1   0   21
+ 339 CLK_000_P_SYNC_2_  3   -1   5   1                 5        -1   -1   1   0   21
+ 338 CLK_000_P_SYNC_1_  3   -1   1   1                 5        -1   -1   1   0   21
+ 337 CLK_000_P_SYNC_0_  3   -1   1   1     1                    -1   -1   1   0   21
+ 328  IPL_D0_2_  3   -1   1   1     1                    -1   -1   1   0   21
+ 327  IPL_D0_1_  3   -1   1   1     1                    -1   -1   1   0   21
+ 326  IPL_D0_0_  3   -1   1   1     1                    -1   -1   1   0   21
+ 325 CLK_000_N_SYNC_11_  3   -1   7   1                    6     -1   -1   1   0   21
+ 323 CLK_000_P_SYNC_9_  3   -1   5   1                 5        -1   -1   1   0   21
+ 322 inst_CLK_OUT_EXP_INT  3   -1   4   1     1                    -1   -1   1   0   21
+ 314 inst_DTACK_D0  3   -1   0   1                 5        -1   -1   1   0   21
+  60   CLK_OSZI  9       -1   0                          60   -1
+  85        RST  1   -1  -1   8  0  1  2  3  4  5  6  7  85   -1
+  96      A_19_  1   -1  -1   3        2     4        7  96   -1
+  95      A_16_  1   -1  -1   3        2     4        7  95   -1
+  94      A_18_  1   -1  -1   3        2     4        7  94   -1
+  58      A_17_  1   -1  -1   3        2     4        7  58   -1
+  57      FC_1_  1   -1  -1   3        2     4        7  57   -1
+  56      FC_0_  1   -1  -1   3        2     4        7  56   -1
+  90  FPU_SENSE  1   -1  -1   2              4        7  90   -1
+  63    CLK_030  1   -1  -1   2  0                    7  63   -1
+  27  BGACK_000  1   -1  -1   2              4        7  27   -1
+  93      A_21_  1   -1  -1   1              4           93   -1
+  92      A_20_  1   -1  -1   1              4           92   -1
+  84      A_23_  1   -1  -1   1              4           84   -1
+  83      A_22_  1   -1  -1   1              4           83   -1
+  67     IPL_2_  1   -1  -1   1     1                    67   -1
+  66     IPL_0_  1   -1  -1   1     1                    66   -1
+  59         A1  1   -1  -1   1     1                    59   -1
+  55     IPL_1_  1   -1  -1   1     1                    55   -1
+  35        VPA  1   -1  -1   1        2                 35   -1
+  29      DTACK  1   -1  -1   1  0                       29   -1
+  20     BG_030  1   -1  -1   1           3              20   -1
+  18      A_24_  1   -1  -1   1              4           18   -1
+  17      A_25_  1   -1  -1   1              4           17   -1
+  16      A_26_  1   -1  -1   1              4           16   -1
+  15      A_27_  1   -1  -1   1              4           15   -1
+  14      A_28_  1   -1  -1   1              4           14   -1
+  13 nEXP_SPACE  1   -1  -1   1                       7  13   -1
+  10    CLK_000  1   -1  -1   1           3              10   -1
+   5      A_29_  1   -1  -1   1              4            5   -1
+   4      A_30_  1   -1  -1   1              4            4   -1
+   3      A_31_  1   -1  -1   1              4            3   -1
\ No newline at end of file
diff --git a/Logic/68030_tk.plc b/Logic/68030_tk.plc
new file mode 100644
index 0000000..f06f05c
--- /dev/null
+++ b/Logic/68030_tk.plc
@@ -0,0 +1,164 @@
+|--------------------------------------------|
+|- ispLEVER Fitter Report File              -|
+|- Version 1.8.00.04.29.14                       -|
+|- (c)Copyright, Lattice Semiconductor 2002 -|
+|--------------------------------------------|
+
+
+; Source file 68030_tk.tt4
+; FITTER-generated Placements.
+; DEVICE   mach447a
+; DATE     Sun Jan 24 16:20:59 2016
+
+
+Pin   79  SIZE_1_ Comb ; S6=1  S9=1  Pair 287
+Pin   4  A_31_
+Pin   68  IPL_2_
+Pin   58  FC_1_
+Pin   56  IPL_1_
+Pin   82  AS_030 Comb ; S6=1  S9=1  Pair 281
+Pin   67  IPL_0_
+Pin   42  AS_000 Comb ; S6=1  S9=1  Pair 203
+Pin   57  FC_0_
+Pin   98  DS_030 Comb ; S6=1  S9=1  Pair 101
+Pin   32  UDS_000 Comb ; S6=1  S9=1  Pair 185
+Pin   31  LDS_000 Comb ; S6=1  S9=1  Pair 191
+Pin   60  A1
+Pin   14  nEXP_SPACE
+Pin   41  BERR Comb ; S6=1  S9=1  Pair 197
+Pin   21  BG_030
+Pin   28  BGACK_000
+Pin   64  CLK_030
+Pin   11  CLK_000
+Pin   61  CLK_OSZI
+Pin   10  CLK_EXP Comb ; S6=1  S9=1  Pair 125
+Pin   78  FPU_CS Comb ; S6=1  S9=1  Pair 271
+Pin   91  FPU_SENSE
+Pin   30  DTACK
+Pin   92  AVEC Comb ; S6=1  S9=1  Pair 107
+Pin   66  E Comb ; S6=1  S9=1  Pair 251
+Pin   36  VPA
+Pin   86  RST
+Pin   3  RESET Comb ; S6=1  S9=1  Pair 127
+Pin   33  AMIGA_ADDR_ENABLE Comb ; S6=1  S9=1  Pair 181
+Pin   48  AMIGA_BUS_DATA_DIR Comb ; S6=1  S9=1  Pair 199
+Pin   70  SIZE_0_ Comb ; S6=1  S9=1  Pair 263
+Pin   20  AMIGA_BUS_ENABLE_LOW Comb ; S6=1  S9=1  Pair 149
+Pin   5  A_30_
+Pin   34  AMIGA_BUS_ENABLE_HIGH Comb ; S6=1  S9=1  Pair 179
+Pin   6  A_29_
+Pin   47  CIIN Comb ; S6=1  S9=1  Pair 215
+Pin   15  A_28_
+Pin   16  A_27_
+Pin   17  A_26_
+Pin   18  A_25_
+Pin   19  A_24_
+Pin   85  A_23_
+Pin   84  A_22_
+Pin   94  A_21_
+Pin   93  A_20_
+Pin   97  A_19_
+Pin   95  A_18_
+Pin   59  A_17_
+Pin   96  A_16_
+Pin   9  IPL_030_2_ Reg  ; S6=1  S9=1  Pair 131
+Pin   7  IPL_030_1_ Reg  ; S6=1  S9=1  Pair 143
+Pin   8  IPL_030_0_ Reg  ; S6=1  S9=1  Pair 137
+Pin   80  RW_000 Reg  ; S6=1  S9=1  Pair 269
+Pin   69  A0 Reg  ; S6=1  S9=1  Pair 257
+Pin   29  BG_000 Reg  ; S6=1  S9=1  Pair 175
+Pin   83  BGACK_030 Reg  ; S6=1  S9=1  Pair 275
+Pin   65  CLK_DIV_OUT Reg  ; S6=1  S9=1  Pair 247
+Pin   81  DSACK1 Reg  ; S6=1  S9=1  Pair 283
+Pin   35  VMA Reg  ; S6=1  S9=1  Pair 173
+Pin   71  RW Reg  ; S6=1  S9=1  Pair 245
+Node  287  RN_SIZE_1_ Comb ; S6=1  S9=1 
+Node  281  RN_AS_030 Comb ; S6=1  S9=1 
+Node  203  RN_AS_000 Comb ; S6=1  S9=1 
+Node  185  RN_UDS_000 Comb ; S6=1  S9=1 
+Node  191  RN_LDS_000 Comb ; S6=1  S9=1 
+Node  197  RN_BERR Comb ; S6=1  S9=1 
+Node  263  RN_SIZE_0_ Comb ; S6=1  S9=1 
+Node  131  RN_IPL_030_2_ Reg  ; S6=1  S9=1 
+Node  143  RN_IPL_030_1_ Reg  ; S6=1  S9=1 
+Node  137  RN_IPL_030_0_ Reg  ; S6=1  S9=1 
+Node  269  RN_RW_000 Reg  ; S6=1  S9=1 
+Node  257  RN_A0 Reg  ; S6=1  S9=1 
+Node  175  RN_BG_000 Reg  ; S6=1  S9=1 
+Node  275  RN_BGACK_030 Reg  ; S6=1  S9=1 
+Node  283  RN_DSACK1 Reg  ; S6=1  S9=1 
+Node  173  RN_VMA Reg  ; S6=1  S9=1 
+Node  245  RN_RW Reg  ; S6=1  S9=1 
+Node  188  cpu_est_0_ Reg  ; S6=1  S9=1 
+Node  182  cpu_est_1_ Reg  ; S6=1  S9=1 
+Node  193  cpu_est_2_ Reg  ; S6=1  S9=1 
+Node  176  cpu_est_3_ Reg  ; S6=1  S9=1 
+Node  145  inst_AS_000_INT Reg  ; S6=1  S9=1 
+Node  227  SM_AMIGA_5_ Reg  ; S6=1  S9=1 
+Node  139  inst_AMIGA_BUS_ENABLE_DMA_LOW Reg  ; S6=1  S9=1 
+Node  289  inst_AS_030_D0 Reg  ; S6=1  S9=1 
+Node  277  inst_nEXP_SPACE_D0reg Reg  ; S6=1  S9=1 
+Node  157  inst_AS_030_000_SYNC Reg  ; S6=1  S9=1 
+Node  209  inst_BGACK_030_INT_D Reg  ; S6=1  S9=1 
+Node  119  inst_AS_000_DMA Reg  ; S6=1  S9=1 
+Node  115  inst_DS_000_DMA Reg  ; S6=1  S9=1 
+Node  110  CYCLE_DMA_0_ Reg  ; S6=1  S9=1 
+Node  104  CYCLE_DMA_1_ Reg  ; S6=1  S9=1 
+Node  248  SIZE_DMA_0_ Reg  ; S6=1  S9=1 
+Node  265  SIZE_DMA_1_ Reg  ; S6=1  S9=1 
+Node  151  inst_VPA_D Reg  ; S6=1  S9=1 
+Node  109  inst_UDS_000_INT Reg  ; S6=1  S9=1 
+Node  103  inst_LDS_000_INT Reg  ; S6=1  S9=1 
+Node  178  inst_CLK_OUT_PRE_D Reg  ; S6=1  S9=1 
+Node  106  inst_DTACK_D0 Reg  ; S6=1  S9=1 
+Node  253  inst_RESET_OUT Reg  ; S6=1  S9=1 
+Node  205  inst_CLK_OUT_PRE_50 Reg  ; S6=1  S9=1 
+Node  163  N_210_i Comb ; S6=1  S9=1 
+Node  254  inst_CLK_OUT_PRE_25 Reg  ; S6=1  S9=1 
+Node  161  inst_CLK_000_D1 Reg  ; S6=1  S9=1 
+Node  187  inst_CLK_000_D0 Reg  ; S6=1  S9=1 
+Node  221  inst_CLK_000_PE Reg  ; S6=1  S9=1 
+Node  200  inst_CLK_OUT_EXP_INT Reg  ; S6=1  S9=1 
+Node  226  CLK_000_P_SYNC_9_ Reg  ; S6=1  S9=1 
+Node  259  inst_CLK_000_NE Reg  ; S6=1  S9=1 
+Node  278  CLK_000_N_SYNC_11_ Reg  ; S6=1  S9=1 
+Node  148  IPL_D0_0_ Reg  ; S6=1  S9=1 
+Node  142  IPL_D0_1_ Reg  ; S6=1  S9=1 
+Node  136  IPL_D0_2_ Reg  ; S6=1  S9=1 
+Node  194  inst_CLK_000_NE_D0 Reg  ; S6=1  S9=1 
+Node  223  SM_AMIGA_0_ Reg  ; S6=1  S9=1 
+Node  133  inst_AMIGA_BUS_ENABLE_DMA_HIGH Reg  ; S6=1  S9=1 
+Node  235  SM_AMIGA_4_ Reg  ; S6=1  S9=1 
+Node  167  inst_DS_000_ENABLE Reg  ; S6=1  S9=1 
+Node  266  RST_DLY_0_ Reg  ; S6=1  S9=1 
+Node  260  RST_DLY_1_ Reg  ; S6=1  S9=1 
+Node  250  RST_DLY_2_ Reg  ; S6=1  S9=1 
+Node  130  CLK_000_P_SYNC_0_ Reg  ; S6=1  S9=1 
+Node  146  CLK_000_P_SYNC_1_ Reg  ; S6=1  S9=1 
+Node  242  CLK_000_P_SYNC_2_ Reg  ; S6=1  S9=1 
+Node  236  CLK_000_P_SYNC_3_ Reg  ; S6=1  S9=1 
+Node  217  CLK_000_P_SYNC_4_ Reg  ; S6=1  S9=1 
+Node  140  CLK_000_P_SYNC_5_ Reg  ; S6=1  S9=1 
+Node  230  CLK_000_P_SYNC_6_ Reg  ; S6=1  S9=1 
+Node  134  CLK_000_P_SYNC_7_ Reg  ; S6=1  S9=1 
+Node  268  CLK_000_P_SYNC_8_ Reg  ; S6=1  S9=1 
+Node  262  CLK_000_N_SYNC_0_ Reg  ; S6=1  S9=1 
+Node  224  CLK_000_N_SYNC_1_ Reg  ; S6=1  S9=1 
+Node  241  CLK_000_N_SYNC_2_ Reg  ; S6=1  S9=1 
+Node  196  CLK_000_N_SYNC_3_ Reg  ; S6=1  S9=1 
+Node  190  CLK_000_N_SYNC_4_ Reg  ; S6=1  S9=1 
+Node  122  CLK_000_N_SYNC_5_ Reg  ; S6=1  S9=1 
+Node  116  CLK_000_N_SYNC_6_ Reg  ; S6=1  S9=1 
+Node  256  CLK_000_N_SYNC_7_ Reg  ; S6=1  S9=1 
+Node  128  CLK_000_N_SYNC_8_ Reg  ; S6=1  S9=1 
+Node  184  CLK_000_N_SYNC_9_ Reg  ; S6=1  S9=1 
+Node  272  CLK_000_N_SYNC_10_ Reg  ; S6=1  S9=1 
+Node  155  SM_AMIGA_6_ Reg  ; S6=1  S9=1 
+Node  121  inst_CLK_030_H Reg  ; S6=1  S9=1 
+Node  113  SM_AMIGA_1_ Reg  ; S6=1  S9=1 
+Node  229  SM_AMIGA_3_ Reg  ; S6=1  S9=1 
+Node  239  SM_AMIGA_2_ Reg  ; S6=1  S9=1 
+Node  233  SM_AMIGA_i_7_ Reg  ; S6=1  S9=1 
+Node  211  CIIN_0 Comb ; S6=1  S9=1 
+; Unused Pins & Nodes
+; -> None Found.
diff --git a/Logic/68030_tk.prd b/Logic/68030_tk.prd
new file mode 100644
index 0000000..faa569a
--- /dev/null
+++ b/Logic/68030_tk.prd
@@ -0,0 +1,1972 @@
+|--------------------------------------------|
+|- ispLEVER Fitter Report File              -|
+|- Version 1.8.00.04.29.14                       -|
+|- (c)Copyright, Lattice Semiconductor 2002 -|
+|--------------------------------------------|
+
+
+Start: Sun Jan 24 16:20:59 2016
+End  : Sun Jan 24 16:20:59 2016    $$$ Elapsed time: 00:00:00
+===========================================================================
+Part [C:/ispLever/ispcpld/dat/mach4a/mach447a] Design [68030_tk.tt4]
+
+* Place/Route options (keycode = 540674)
+	= Spread Placement:			      ON
+	= No. Routing Attempts/Placement	       2
+
+* Placement Completion
+
+ +- Block                       +------- IO Pins Available
+ |    +- Macrocells Available   |    +-- IO Pins Used
+ |    |    +- Signals to Place  |    |             +----- Logic Array Inputs
+ |    |    |    +- Placed       |    |             |   +- Array Inputs Used
+_|____|____|____|_______________|____|_____________|___|________________
+ 0 | 16 | 13 | 13 => 100% |     8 |  8 => 100% |  33 | 28    =>  84%
+ 1 | 16 | 16 | 16 => 100% |     8 |  8 => 100% |  33 | 27    =>  81%
+ 2 | 16 |  7 |  7 => 100% |     8 |  7 =>  87% |  33 | 28    =>  84%
+ 3 | 16 | 16 | 16 => 100% |     8 |  8 => 100% |  33 | 27    =>  81%
+ 4 | 16 |  9 |  9 => 100% |     8 |  4 =>  50% |  33 | 32    =>  96%
+ 5 | 16 | 13 | 13 => 100% |     8 |  5 =>  62% |  33 | 27    =>  81%
+ 6 | 16 | 16 | 16 => 100% |     8 |  7 =>  87% |  33 | 27    =>  81%
+ 7 | 16 | 10 | 10 => 100% |     8 |  8 => 100% |  33 | 32    =>  96%
+---|----|----|------------|-------|------------|-----|------------------
+        | Avg number of array inputs in used blocks :  28.50 =>  86%
+
+* Input/Clock Signal count:  32 -> placed:  32 = 100%
+
+          Resources           Available   Used
+-----------------------------------------------------------------
+	Input Pins            :   2        2    => 100%
+	I/O Pins              :  64       55    =>  85%
+	Clock Only Pins       :   0        0    =>   0%
+	Clock/Input Pins      :   4        4    => 100%
+	Logic Blocks          :   8        8    => 100%
+	Macrocells            : 128      100    =>  78%
+	PT Clusters           : 128       55    =>  42%
+	 - Single PT Clusters : 128       54    =>  42%
+	Input Registers       :            0
+
+* Routing Completion: 100%
+* Attempts: Place [     142] Route [       0]
+===========================================================================
+	Signal Fanout Table
+===========================================================================
+   +- Signal Number
+   |  +- Block Location ('+' for dedicated inputs)
+   |  |  +- Sig Type
+   |  |  |    +- Signal-to-Pin Assignment
+   |  |  |    |    Fanout to Logic Blocks               Signal Name
+___|__|__|____|____________________________________________________________
+   1| 6| IO|  69|=> 0...|....| A0
+		|=> Paired w/: RN_A0
+   2| 5|INP|  60|=> .1..|....| A1
+   3| 3|OUT|  33|=> ....|....| AMIGA_ADDR_ENABLE
+   4| 4|OUT|  48|=> ....|....| AMIGA_BUS_DATA_DIR
+   5| 3|OUT|  34|=> ....|....| AMIGA_BUS_ENABLE_HIGH
+   6| 2|OUT|  20|=> ....|....| AMIGA_BUS_ENABLE_LOW
+   7| 4| IO|  42|=> 0...|4..7| AS_000
+   8| 7| IO|  82|=> ....|4..7| AS_030
+   9| 0|OUT|  92|=> ....|....| AVEC
+  10| 0|INP|  96|=> ..2.|4..7| A_16_
+  11| 5|INP|  59|=> ..2.|4..7| A_17_
+  12| 0|INP|  95|=> ..2.|4..7| A_18_
+  13| 0|INP|  97|=> ..2.|4..7| A_19_
+  14| 0|INP|  93|=> ....|4...| A_20_
+  15| 0|INP|  94|=> ....|4...| A_21_
+  16| 7|INP|  84|=> ....|4...| A_22_
+  17| 7|INP|  85|=> ....|4...| A_23_
+  18| 2|INP|  19|=> ....|4...| A_24_
+  19| 2|INP|  18|=> ....|4...| A_25_
+  20| 2|INP|  17|=> ....|4...| A_26_
+  21| 2|INP|  16|=> ....|4...| A_27_
+  22| 2|INP|  15|=> ....|4...| A_28_
+  23| 1|INP|   6|=> ....|4...| A_29_
+  24| 1|INP|   5|=> ....|4...| A_30_
+  25| 1|INP|   4|=> ....|4...| A_31_
+  26| 4| IO|  41|=> 012.|.5.7| BERR
+  27| 3|INP|  28|=> ....|4..7| BGACK_000
+  28| 7| IO|  83|=> ....|....| BGACK_030
+		|=> Paired w/: RN_BGACK_030
+  29| 3| IO|  29|=> ....|....| BG_000
+		|=> Paired w/: RN_BG_000
+  30| 2|INP|  21|=> ...3|....| BG_030
+  31| 4|OUT|  47|=> ....|....| CIIN
+  32| 4|NOD|  . |=> ....|4...| CIIN_0
+  33| +|INP|  11|=> ...3|....| CLK_000
+  34| 6|NOD|  . |=> ....|.5..| CLK_000_N_SYNC_0_
+  35| 7|NOD|  . |=> ....|...7| CLK_000_N_SYNC_10_
+  36| 7|NOD|  . |=> ....|..6.| CLK_000_N_SYNC_11_
+  37| 5|NOD|  . |=> ....|.5..| CLK_000_N_SYNC_1_
+  38| 5|NOD|  . |=> ...3|....| CLK_000_N_SYNC_2_
+  39| 3|NOD|  . |=> ...3|....| CLK_000_N_SYNC_3_
+  40| 3|NOD|  . |=> 0...|....| CLK_000_N_SYNC_4_
+  41| 0|NOD|  . |=> 0...|....| CLK_000_N_SYNC_5_
+  42| 0|NOD|  . |=> ....|..6.| CLK_000_N_SYNC_6_
+  43| 6|NOD|  . |=> .1..|....| CLK_000_N_SYNC_7_
+  44| 1|NOD|  . |=> ...3|....| CLK_000_N_SYNC_8_
+  45| 3|NOD|  . |=> ....|...7| CLK_000_N_SYNC_9_
+  46| 1|NOD|  . |=> .1..|....| CLK_000_P_SYNC_0_
+  47| 1|NOD|  . |=> ....|.5..| CLK_000_P_SYNC_1_
+  48| 5|NOD|  . |=> ....|.5..| CLK_000_P_SYNC_2_
+  49| 5|NOD|  . |=> ....|4...| CLK_000_P_SYNC_3_
+  50| 4|NOD|  . |=> .1..|....| CLK_000_P_SYNC_4_
+  51| 1|NOD|  . |=> ....|.5..| CLK_000_P_SYNC_5_
+  52| 5|NOD|  . |=> .1..|....| CLK_000_P_SYNC_6_
+  53| 1|NOD|  . |=> ....|..6.| CLK_000_P_SYNC_7_
+  54| 6|NOD|  . |=> ....|.5..| CLK_000_P_SYNC_8_
+  55| 5|NOD|  . |=> ....|.5..| CLK_000_P_SYNC_9_
+  56| +|INP|  64|=> 0...|...7| CLK_030
+  57| 6|OUT|  65|=> ....|....| CLK_DIV_OUT
+  58| 1|OUT|  10|=> ....|....| CLK_EXP
+  59| +|Cin|  61|=> ....|....| CLK_OSZI
+  60| 0|NOD|  . |=> 0...|....| CYCLE_DMA_0_
+  61| 0|NOD|  . |=> 0...|....| CYCLE_DMA_1_
+  62| 7| IO|  81|=> ....|....| DSACK1
+		|=> Paired w/: RN_DSACK1
+  63| 0|OUT|  98|=> ....|....| DS_030
+  64| 3|INP|  30|=> 0...|....| DTACK
+  65| 6|OUT|  66|=> ....|....| E
+  66| 5|INP|  57|=> ..2.|4..7| FC_0_
+  67| 5|INP|  58|=> ..2.|4..7| FC_1_
+  68| 7|OUT|  78|=> ....|....| FPU_CS
+  69| 0|INP|  91|=> ....|4..7| FPU_SENSE
+  70| 1| IO|   8|=> ....|....| IPL_030_0_
+		|=> Paired w/: RN_IPL_030_0_
+  71| 1| IO|   7|=> ....|....| IPL_030_1_
+		|=> Paired w/: RN_IPL_030_1_
+  72| 1| IO|   9|=> ....|....| IPL_030_2_
+		|=> Paired w/: RN_IPL_030_2_
+  73| 6|INP|  67|=> .1..|....| IPL_0_
+  74| 5|INP|  56|=> .1..|....| IPL_1_
+  75| 6|INP|  68|=> .1..|....| IPL_2_
+  76| 1|NOD|  . |=> .1..|....| IPL_D0_0_
+  77| 1|NOD|  . |=> .1..|....| IPL_D0_1_
+  78| 1|NOD|  . |=> .1..|....| IPL_D0_2_
+  79| 3| IO|  31|=> 0...|..6.| LDS_000
+  80| 2|NOD|  . |=> ....|.5..| N_210_i
+  81| 1|OUT|   3|=> ....|....| RESET
+  82| 6|NOD|  . |=> ....|..6.| RN_A0
+		|=> Paired w/: A0
+  83| 7|NOD|  . |=> 0123|4.67| RN_BGACK_030
+		|=> Paired w/: BGACK_030
+  84| 3|NOD|  . |=> ...3|....| RN_BG_000
+		|=> Paired w/: BG_000
+  85| 7|NOD|  . |=> ....|...7| RN_DSACK1
+		|=> Paired w/: DSACK1
+  86| 1|NOD|  . |=> .1..|....| RN_IPL_030_0_
+		|=> Paired w/: IPL_030_0_
+  87| 1|NOD|  . |=> .1..|....| RN_IPL_030_1_
+		|=> Paired w/: IPL_030_1_
+  88| 1|NOD|  . |=> .1..|....| RN_IPL_030_2_
+		|=> Paired w/: IPL_030_2_
+  89| 6|NOD|  . |=> ....|..6.| RN_RW
+		|=> Paired w/: RW
+  90| 7|NOD|  . |=> ....|...7| RN_RW_000
+		|=> Paired w/: RW_000
+  91| 3|NOD|  . |=> ...3|.5..| RN_VMA
+		|=> Paired w/: VMA
+  92| +|INP|  86|=> 0123|4567| RST
+  93| 6|NOD|  . |=> ....|..6.| RST_DLY_0_
+  94| 6|NOD|  . |=> ....|..6.| RST_DLY_1_
+  95| 6|NOD|  . |=> ....|..6.| RST_DLY_2_
+  96| 6| IO|  71|=> ..2.|...7| RW
+		|=> Paired w/: RN_RW
+  97| 7| IO|  80|=> 0...|4.6.| RW_000
+		|=> Paired w/: RN_RW_000
+  98| 6| IO|  70|=> 0...|....| SIZE_0_
+  99| 7| IO|  79|=> 0...|....| SIZE_1_
+ 100| 6|NOD|  . |=> ....|..67| SIZE_DMA_0_
+ 101| 6|NOD|  . |=> ....|..67| SIZE_DMA_1_
+ 102| 5|NOD|  . |=> ..2.|.5.7| SM_AMIGA_0_
+ 103| 0|NOD|  . |=> 0.2.|.5.7| SM_AMIGA_1_
+ 104| 5|NOD|  . |=> 0.2.|.5..| SM_AMIGA_2_
+ 105| 5|NOD|  . |=> ..2.|.5..| SM_AMIGA_3_
+ 106| 5|NOD|  . |=> ..2.|.5..| SM_AMIGA_4_
+ 107| 5|NOD|  . |=> .12.|.5.7| SM_AMIGA_5_
+ 108| 2|NOD|  . |=> 0.2.|.5..| SM_AMIGA_6_
+ 109| 5|NOD|  . |=> ..23|...7| SM_AMIGA_i_7_
+ 110| 3| IO|  32|=> 0...|..6.| UDS_000
+ 111| 3| IO|  35|=> ....|....| VMA
+		|=> Paired w/: RN_VMA
+ 112| +|INP|  36|=> ..2.|....| VPA
+ 113| 3|NOD|  . |=> ...3|.5..| cpu_est_0_
+ 114| 3|NOD|  . |=> ...3|.56.| cpu_est_1_
+ 115| 3|NOD|  . |=> ...3|.56.| cpu_est_2_
+ 116| 3|NOD|  . |=> ...3|.56.| cpu_est_3_
+ 117| 1|NOD|  . |=> .1.3|....| inst_AMIGA_BUS_ENABLE_DMA_HIGH
+ 118| 1|NOD|  . |=> .12.|....| inst_AMIGA_BUS_ENABLE_DMA_LOW
+ 119| 0|NOD|  . |=> 0...|...7| inst_AS_000_DMA
+ 120| 1|NOD|  . |=> .1..|4...| inst_AS_000_INT
+ 121| 2|NOD|  . |=> ..2.|....| inst_AS_030_000_SYNC
+ 122| 7|NOD|  . |=> .123|4..7| inst_AS_030_D0
+ 123| 4|NOD|  . |=> .12.|..6.| inst_BGACK_030_INT_D
+ 124| 3|NOD|  . |=> .123|..6.| inst_CLK_000_D0
+ 125| 2|NOD|  . |=> .12.|..6.| inst_CLK_000_D1
+ 126| 6|NOD|  . |=> 0..3|.56.| inst_CLK_000_NE
+ 127| 3|NOD|  . |=> ...3|.5..| inst_CLK_000_NE_D0
+ 128| 5|NOD|  . |=> 0.23|.5.7| inst_CLK_000_PE
+ 129| 0|NOD|  . |=> 0...|....| inst_CLK_030_H
+ 130| 4|NOD|  . |=> .1..|....| inst_CLK_OUT_EXP_INT
+ 131| 6|NOD|  . |=> ...3|..6.| inst_CLK_OUT_PRE_25
+ 132| 4|NOD|  . |=> ....|4.6.| inst_CLK_OUT_PRE_50
+ 133| 3|NOD|  . |=> ....|..67| inst_CLK_OUT_PRE_D
+ 134| 0|NOD|  . |=> 0...|....| inst_DS_000_DMA
+ 135| 2|NOD|  . |=> ..23|....| inst_DS_000_ENABLE
+ 136| 0|NOD|  . |=> ....|.5..| inst_DTACK_D0
+ 137| 0|NOD|  . |=> 0..3|....| inst_LDS_000_INT
+ 138| 6|NOD|  . |=> 01.3|4.67| inst_RESET_OUT
+ 139| 0|NOD|  . |=> 0..3|....| inst_UDS_000_INT
+ 140| 2|NOD|  . |=> ...3|.5..| inst_VPA_D
+ 141| 7|NOD|  . |=> 0.23|4.67| inst_nEXP_SPACE_D0reg
+ 142| +|INP|  14|=> ....|...7| nEXP_SPACE
+---------------------------------------------------------------------------
+===========================================================================
+	< C:/ispLever/ispcpld/dat/mach4a/mach447a Device Pin Assignments >
+===========================================================================
+    +- Device Pin No
+    |   Pin Type    +- Signal Fixed (*)
+    |     |         |   Signal Name
+____|_____|_________|______________________________________________________
+    1 |  GND |     | |    (pwr/test)
+    2 | JTAG |     | |    (pwr/test)
+    3 |  I_O | 1_07|*| RESET
+    4 |  I_O | 1_06|*| A_31_
+    5 |  I_O | 1_05|*| A_30_
+    6 |  I_O | 1_04|*| A_29_
+    7 |  I_O | 1_03|*| IPL_030_1_
+    8 |  I_O | 1_02|*| IPL_030_0_
+    9 |  I_O | 1_01|*| IPL_030_2_
+   10 |  I_O | 1_00|*| CLK_EXP
+   11 | CkIn |     |*| CLK_000
+   12 |  Vcc |     | |    (pwr/test)
+   13 |  GND |     | |    (pwr/test)
+   14 | CkIn |     |*| nEXP_SPACE
+   15 |  I_O | 2_00|*| A_28_
+   16 |  I_O | 2_01|*| A_27_
+   17 |  I_O | 2_02|*| A_26_
+   18 |  I_O | 2_03|*| A_25_
+   19 |  I_O | 2_04|*| A_24_
+   20 |  I_O | 2_05|*| AMIGA_BUS_ENABLE_LOW
+   21 |  I_O | 2_06|*| BG_030
+   22 |  I_O | 2_07| |        -
+   23 | JTAG |     | |    (pwr/test)
+   24 | JTAG |     | |    (pwr/test)
+   25 |  GND |     | |    (pwr/test)
+   26 |  GND |     | |    (pwr/test)
+   27 |  GND |     | |    (pwr/test)
+   28 |  I_O | 3_07|*| BGACK_000
+   29 |  I_O | 3_06|*| BG_000
+   30 |  I_O | 3_05|*| DTACK
+   31 |  I_O | 3_04|*| LDS_000
+   32 |  I_O | 3_03|*| UDS_000
+   33 |  I_O | 3_02|*| AMIGA_ADDR_ENABLE
+   34 |  I_O | 3_01|*| AMIGA_BUS_ENABLE_HIGH
+   35 |  I_O | 3_00|*| VMA
+   36 |  Inp |     |*| VPA
+   37 |  Vcc |     | |    (pwr/test)
+   38 |  GND |     | |    (pwr/test)
+   39 |  GND |     | |    (pwr/test)
+   40 |  Vcc |     | |    (pwr/test)
+   41 |  I_O | 4_00|*| BERR
+   42 |  I_O | 4_01|*| AS_000
+   43 |  I_O | 4_02| |        -
+   44 |  I_O | 4_03| |        -
+   45 |  I_O | 4_04| |        -
+   46 |  I_O | 4_05| |        -
+   47 |  I_O | 4_06|*| CIIN
+   48 |  I_O | 4_07|*| AMIGA_BUS_DATA_DIR
+   49 |  GND |     | |    (pwr/test)
+   50 |  GND |     | |    (pwr/test)
+   51 |  GND |     | |    (pwr/test)
+   52 | JTAG |     | |    (pwr/test)
+   53 |  I_O | 5_07| |        -
+   54 |  I_O | 5_06| |        -
+   55 |  I_O | 5_05| |        -
+   56 |  I_O | 5_04|*| IPL_1_
+   57 |  I_O | 5_03|*| FC_0_
+   58 |  I_O | 5_02|*| FC_1_
+   59 |  I_O | 5_01|*| A_17_
+   60 |  I_O | 5_00|*| A1
+   61 | CkIn |     |*| CLK_OSZI
+   62 |  Vcc |     | |    (pwr/test)
+   63 |  GND |     | |    (pwr/test)
+   64 | CkIn |     |*| CLK_030
+   65 |  I_O | 6_00|*| CLK_DIV_OUT
+   66 |  I_O | 6_01|*| E
+   67 |  I_O | 6_02|*| IPL_0_
+   68 |  I_O | 6_03|*| IPL_2_
+   69 |  I_O | 6_04|*| A0
+   70 |  I_O | 6_05|*| SIZE_0_
+   71 |  I_O | 6_06|*| RW
+   72 |  I_O | 6_07| |        -
+   73 | JTAG |     | |    (pwr/test)
+   74 | JTAG |     | |    (pwr/test)
+   75 |  GND |     | |    (pwr/test)
+   76 |  GND |     | |    (pwr/test)
+   77 |  GND |     | |    (pwr/test)
+   78 |  I_O | 7_07|*| FPU_CS
+   79 |  I_O | 7_06|*| SIZE_1_
+   80 |  I_O | 7_05|*| RW_000
+   81 |  I_O | 7_04|*| DSACK1
+   82 |  I_O | 7_03|*| AS_030
+   83 |  I_O | 7_02|*| BGACK_030
+   84 |  I_O | 7_01|*| A_22_
+   85 |  I_O | 7_00|*| A_23_
+   86 |  Inp |     |*| RST
+   87 |  Vcc |     | |    (pwr/test)
+   88 |  GND |     | |    (pwr/test)
+   89 |  GND |     | |    (pwr/test)
+   90 |  Vcc |     | |    (pwr/test)
+   91 |  I_O | 0_00|*| FPU_SENSE
+   92 |  I_O | 0_01|*| AVEC
+   93 |  I_O | 0_02|*| A_20_
+   94 |  I_O | 0_03|*| A_21_
+   95 |  I_O | 0_04|*| A_18_
+   96 |  I_O | 0_05|*| A_16_
+   97 |  I_O | 0_06|*| A_19_
+   98 |  I_O | 0_07|*| DS_030
+   99 |  GND |     | |    (pwr/test)
+  100 |  GND |     | |    (pwr/test)
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 0] >	Macrocell (MCell) Cluster Assignments
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+  +--- Macrocell PT Cluster Size
+ |      Sync/Async-------+   |     |  |    Cluster to Mcell Assignment
+ |   Node Fixed(*)----+  |   |     |  |      |   +- XOR PT Size
+ |        Sig Type-+  |  |   |     |  |      |   |  XOR to Mcell Assignment
+ |  Signal Name    |  |  |   |     |  |      |   |          |
+_|_________________|__|__|___|_____|__|______|___|__________|______________
+ 0|        DS_030|OUT| | S | 1      | 4 free   | 1 XOR to [ 0] for 1 PT sig
+ 1|inst_LDS_000_INT|NOD| | S | 3      | 4 to [ 1]| 1 XOR free
+ 2|  CYCLE_DMA_1_|NOD| | S | 3      | 4 to [ 2]| 1 XOR free
+ 3| inst_DTACK_D0|NOD| | S | 1      | 4 free   | 1 XOR to [ 3] for 1 PT sig
+ 4|          AVEC|OUT| | S | 1      | 4 free   | 1 XOR to [ 4] for 1 PT sig
+ 5|inst_UDS_000_INT|NOD| | S | 2      | 4 to [ 5]| 1 XOR free
+ 6|  CYCLE_DMA_0_|NOD| | S | 2      | 4 to [ 6]| 1 XOR free
+ 7|              | ? | | S |        | 4 free   | 1 XOR free
+ 8|   SM_AMIGA_1_|NOD| | S | 3      | 4 to [ 8]| 1 XOR free
+ 9|inst_DS_000_DMA|NOD| | S | 9      | 4 to [ 9]| 1 XOR to [ 9] as logic PT
+10|CLK_000_N_SYNC_6_|NOD| | S | 1      | 4 to [ 9]| 1 XOR to [10] for 1 PT sig
+11|              | ? | | S |        | 4 to [12]| 1 XOR free
+12|inst_AS_000_DMA|NOD| | S | 7      | 4 to [12]| 1 XOR to [12] as logic PT
+13|inst_CLK_030_H|NOD| | S | 8      | 4 to [13]| 1 XOR to [13] as logic PT
+14|CLK_000_N_SYNC_5_|NOD| | S | 1      | 4 to [13]| 1 XOR to [14] for 1 PT sig
+15|              | ? | | S |        | 4 free   | 1 XOR free
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 0] >	Maximum PT Capacity
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+
+ |      Sync/Async-------+   |     |
+ |   Node Fixed(*)----+  |   |     |
+ |        Sig Type-+  |  |   |     |
+ |  Signal Name    |  |  |   |     |     Maximum PT Capacity
+_|_________________|__|__|___|_____|_______________________________________
+ 0|        DS_030|OUT| | S | 1      |=> can support up to [  5] logic PT(s)
+ 1|inst_LDS_000_INT|NOD| | S | 3      |=> can support up to [ 13] logic PT(s)
+ 2|  CYCLE_DMA_1_|NOD| | S | 3      |=> can support up to [ 13] logic PT(s)
+ 3| inst_DTACK_D0|NOD| | S | 1      |=> can support up to [  9] logic PT(s)
+ 4|          AVEC|OUT| | S | 1      |=> can support up to [  9] logic PT(s)
+ 5|inst_UDS_000_INT|NOD| | S | 2      |=> can support up to [ 14] logic PT(s)
+ 6|  CYCLE_DMA_0_|NOD| | S | 2      |=> can support up to [ 10] logic PT(s)
+ 7|              | ? | | S |        |=> can support up to [  5] logic PT(s)
+ 8|   SM_AMIGA_1_|NOD| | S | 3      |=> can support up to [ 10] logic PT(s)
+ 9|inst_DS_000_DMA|NOD| | S | 9      |=> can support up to [  9] logic PT(s)
+10|CLK_000_N_SYNC_6_|NOD| | S | 1      |=> can support up to [  1] logic PT(s)
+11|              | ? | | S |        |=> can support up to [  1] logic PT(s)
+12|inst_AS_000_DMA|NOD| | S | 7      |=> can support up to [ 10] logic PT(s)
+13|inst_CLK_030_H|NOD| | S | 8      |=> can support up to [ 14] logic PT(s)
+14|CLK_000_N_SYNC_5_|NOD| | S | 1      |=> can support up to [  6] logic PT(s)
+15|              | ? | | S |        |=> can support up to [  5] logic PT(s)
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 0] >	Node-Pin Assignments
+===========================================================================
+ + Macrocell Number
+ | Node Fixed(*)------+
+ |      Sig Type---+  |  to | Block [ 0] IO Pin  |   Device Pin
+ |  Signal Name    |  | pin |      Numbers       |     Numbers
+_|_________________|__|_____|____________________|________________________
+ 0|        DS_030|OUT| | => |   5    6 (  7)   0 |  96   97 ( 98)  91 
+ 1|inst_LDS_000_INT|NOD| | => |   5    6    7    0 |  96   97   98   91 
+ 2|  CYCLE_DMA_1_|NOD| | => |   6    7    0    1 |  97   98   91   92 
+ 3| inst_DTACK_D0|NOD| | => |   6    7    0    1 |  97   98   91   92 
+ 4|          AVEC|OUT| | => |   7    0 (  1)   2 |  98   91 ( 92)  93 
+ 5|inst_UDS_000_INT|NOD| | => |   7    0    1    2 |  98   91   92   93 
+ 6|  CYCLE_DMA_0_|NOD| | => |   0    1    2    3 |  91   92   93   94 
+ 7|              |   | | => |   0    1    2    3 |  91   92   93   94 
+ 8|   SM_AMIGA_1_|NOD| | => |   1    2    3    4 |  92   93   94   95 
+ 9|inst_DS_000_DMA|NOD| | => |   1    2    3    4 |  92   93   94   95 
+10|CLK_000_N_SYNC_6_|NOD| | => |   2    3    4    5 |  93   94   95   96 
+11|              |   | | => |   2    3    4    5 |  93   94   95   96 
+12|inst_AS_000_DMA|NOD| | => |   3    4    5    6 |  94   95   96   97 
+13|inst_CLK_030_H|NOD| | => |   3    4    5    6 |  94   95   96   97 
+14|CLK_000_N_SYNC_5_|NOD| | => |   4    5    6    7 |  95   96   97   98 
+15|              |   | | => |   4    5    6    7 |  95   96   97   98 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 0] >	IO-to-Node Pin Mapping
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Node Destinations Via Output Matrix
+_|_________________|__|___|_____|___________________________________________
+ 0|     FPU_SENSE|INP|*| 91| => |   0    1    2    3    4    5    6    7 
+ 1|          AVEC|OUT|*| 92| => |   2    3  ( 4)   5    6    7    8    9 
+ 2|         A_20_|INP|*| 93| => |   4    5    6    7    8    9   10   11 
+ 3|         A_21_|INP|*| 94| => |   6    7    8    9   10   11   12   13 
+ 4|         A_18_|INP|*| 95| => |   8    9   10   11   12   13   14   15 
+ 5|         A_16_|INP|*| 96| => |  10   11   12   13   14   15    0    1 
+ 6|         A_19_|INP|*| 97| => |  12   13   14   15    0    1    2    3 
+ 7|        DS_030|OUT|*| 98| => |  14   15  ( 0)   1    2    3    4    5 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 0] >	IO/Node and IO/Input Macrocell Pairing Table
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Input Macrocell and Node Pairs
+_|_________________|__|___|_____|__________________________________________
+ 0|     FPU_SENSE|INP|*| 91| => | Input macrocell   [             -]
+ 1|          AVEC|OUT|*| 92| => | Input macrocell   [             -]
+ 2|         A_20_|INP|*| 93| => | Input macrocell   [             -]
+ 3|         A_21_|INP|*| 94| => | Input macrocell   [             -]
+ 4|         A_18_|INP|*| 95| => | Input macrocell   [             -]
+ 5|         A_16_|INP|*| 96| => | Input macrocell   [             -]
+ 6|         A_19_|INP|*| 97| => | Input macrocell   [             -]
+ 7|        DS_030|OUT|*| 98| => | Input macrocell   [             -]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 0] >	Input Multiplexer (IMX) Assignments
+===========================================================================
+           +----- IO pin/Input Register, or Macrocell
+IMX No.    |    +---- Block IO Pin or Macrocell Number
+   |       |    |  ABEL Node/      +-- Signal using the Pin or Macrocell
+   |       |    |  Pin Number      |      +- Signal Fixed (*) to Pin/Mcell
+   |       |    |   |  Sig Type    |      | +- Feedback Required (*)
+---|-------|----|---|---|----------|------|-|------------------------------
+   0	[IOpin  0 | 91|INP      FPU_SENSE|*|*]
+	[RegIn  0 |102|                 -| | ]
+	[MCell  0 |101|OUT         DS_030| | ]
+	[MCell  1 |103|NOD inst_LDS_000_INT| |*]
+
+   1	[IOpin  1 | 92|OUT           AVEC|*| ]
+	[RegIn  1 |105|                 -| | ]
+	[MCell  2 |104|NOD   CYCLE_DMA_1_| |*]
+	[MCell  3 |106|NOD  inst_DTACK_D0| |*]
+
+   2	[IOpin  2 | 93|INP          A_20_|*|*]
+	[RegIn  2 |108|                 -| | ]
+	[MCell  4 |107|OUT           AVEC| | ]
+	[MCell  5 |109|NOD inst_UDS_000_INT| |*]
+
+   3	[IOpin  3 | 94|INP          A_21_|*|*]
+	[RegIn  3 |111|                 -| | ]
+	[MCell  6 |110|NOD   CYCLE_DMA_0_| |*]
+	[MCell  7 |112|                 -| | ]
+
+   4	[IOpin  4 | 95|INP          A_18_|*|*]
+	[RegIn  4 |114|                 -| | ]
+	[MCell  8 |113|NOD    SM_AMIGA_1_| |*]
+	[MCell  9 |115|NOD inst_DS_000_DMA| |*]
+
+   5	[IOpin  5 | 96|INP          A_16_|*|*]
+	[RegIn  5 |117|                 -| | ]
+	[MCell 10 |116|NOD CLK_000_N_SYNC_6_| |*]
+	[MCell 11 |118|                 -| | ]
+
+   6	[IOpin  6 | 97|INP          A_19_|*|*]
+	[RegIn  6 |120|                 -| | ]
+	[MCell 12 |119|NOD inst_AS_000_DMA| |*]
+	[MCell 13 |121|NOD inst_CLK_030_H| |*]
+
+   7	[IOpin  7 | 98|OUT         DS_030|*| ]
+	[RegIn  7 |123|                 -| | ]
+	[MCell 14 |122|NOD CLK_000_N_SYNC_5_| |*]
+	[MCell 15 |124|                 -| | ]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 0] >	Logic Array Fan-in
+===========================================================================
+  +- Central Switch Matrix No.
+  |   Src (ABEL Node/Pin#)   Signal
+--|--|--------------------|---------------------------------------------------
+Mux00| IOPin  6  4  (  69)|   A0
+Mux01|  Mcel  5 12  ( 239)|   SM_AMIGA_2_
+Mux02|  Mcel  0  9  ( 115)|   inst_DS_000_DMA
+Mux03|  Mcel  0 14  ( 122)|   CLK_000_N_SYNC_5_
+Mux04|  Input Pin   (  64)|   CLK_030
+Mux05|  Mcel  5  0  ( 221)|   inst_CLK_000_PE
+Mux06|  Mcel  2  4  ( 155)|   SM_AMIGA_6_
+Mux07|          ...       |      ...
+Mux08| IOPin  3  3  (  32)|   UDS_000
+Mux09| IOPin  3  5  (  30)|   DTACK
+Mux10|  Mcel  0  6  ( 110)|   CYCLE_DMA_0_
+Mux11|          ...       |      ...
+Mux12|  Mcel  0  1  ( 103)|   inst_LDS_000_INT
+Mux13|  Mcel  7  5  ( 277)|   inst_nEXP_SPACE_D0reg
+Mux14| IOPin  6  5  (  70)|   SIZE_0_
+Mux15|  Mcel  0 12  ( 119)|   inst_AS_000_DMA
+Mux16| IOPin  4  1  (  42)|   AS_000
+Mux17| IOPin  4  0  (  41)|   BERR
+Mux18|  Mcel  0  5  ( 109)|   inst_UDS_000_INT
+Mux19|  Mcel  3 11  ( 190)|   CLK_000_N_SYNC_4_
+Mux20| IOPin  7  6  (  79)|   SIZE_1_
+Mux21|  Input Pin   (  86)|   RST
+Mux22|  Mcel  0  2  ( 104)|   CYCLE_DMA_1_
+Mux23|  Mcel  7  4  ( 275)|   RN_BGACK_030
+Mux24| IOPin  3  4  (  31)|   LDS_000
+Mux25|  Mcel  0 13  ( 121)|   inst_CLK_030_H
+Mux26|          ...       |      ...
+Mux27|  Mcel  6  9  ( 259)|   inst_CLK_000_NE
+Mux28| IOPin  7  5  (  80)|   RW_000
+Mux29|          ...       |      ...
+Mux30|  Mcel  0  8  ( 113)|   SM_AMIGA_1_
+Mux31|          ...       |      ...
+Mux32|  Mcel  6  5  ( 253)|   inst_RESET_OUT
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 1] >	Macrocell (MCell) Cluster Assignments
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+  +--- Macrocell PT Cluster Size
+ |      Sync/Async-------+   |     |  |    Cluster to Mcell Assignment
+ |   Node Fixed(*)----+  |   |     |  |      |   +- XOR PT Size
+ |        Sig Type-+  |  |   |     |  |      |   |  XOR to Mcell Assignment
+ |  Signal Name    |  |  |   |     |  |      |   |          |
+_|_________________|__|__|___|_____|__|______|___|__________|______________
+ 0|       CLK_EXP|OUT| | S | 1      | 4 free   | 1 XOR to [ 0] for 1 PT sig
+ 1|         RESET|OUT| | S | 1      | 4 free   | 1 XOR to [ 1] for 1 PT sig
+ 2|CLK_000_N_SYNC_8_|NOD| | S | 1      | 4 free   | 1 XOR to [ 2] for 1 PT sig
+ 3|CLK_000_P_SYNC_0_|NOD| | S | 1      | 4 free   | 1 XOR to [ 3] for 1 PT sig
+ 4|    IPL_030_2_| IO| | S |10      | 4 to [ 4]| 1 XOR to [ 4] as logic PT
+ 5|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2      | 4 to [ 4]| 1 XOR to [ 4] as logic PT
+ 6|CLK_000_P_SYNC_7_|NOD| | S | 1      | 4 free   | 1 XOR to [ 6] for 1 PT sig
+ 7|     IPL_D0_2_|NOD| | S | 1      | 4 to [ 5]| 1 XOR to [ 7] for 1 PT sig
+ 8|    IPL_030_0_| IO| | S |10      | 4 to [ 8]| 1 XOR to [ 8] as logic PT
+ 9|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2      | 4 to [ 8]| 1 XOR to [ 8] as logic PT
+10|CLK_000_P_SYNC_5_|NOD| | S | 1      | 4 free   | 1 XOR to [10] for 1 PT sig
+11|     IPL_D0_1_|NOD| | S | 1      | 4 to [ 9]| 1 XOR to [11] for 1 PT sig
+12|    IPL_030_1_| IO| | S |10      | 4 to [12]| 1 XOR to [12] as logic PT
+13|inst_AS_000_INT|NOD| | S | 2      | 4 to [12]| 1 XOR to [12] as logic PT
+14|CLK_000_P_SYNC_1_|NOD| | S | 1      | 4 free   | 1 XOR to [14] for 1 PT sig
+15|     IPL_D0_0_|NOD| | S | 1      | 4 to [13]| 1 XOR to [15] for 1 PT sig
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 1] >	Maximum PT Capacity
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+
+ |      Sync/Async-------+   |     |
+ |   Node Fixed(*)----+  |   |     |
+ |        Sig Type-+  |  |   |     |
+ |  Signal Name    |  |  |   |     |     Maximum PT Capacity
+_|_________________|__|__|___|_____|_______________________________________
+ 0|       CLK_EXP|OUT| | S | 1      |=> can support up to [ 13] logic PT(s)
+ 1|         RESET|OUT| | S | 1      |=> can support up to [ 17] logic PT(s)
+ 2|CLK_000_N_SYNC_8_|NOD| | S | 1      |=> can support up to [ 13] logic PT(s)
+ 3|CLK_000_P_SYNC_0_|NOD| | S | 1      |=> can support up to [  9] logic PT(s)
+ 4|    IPL_030_2_| IO| | S |10      |=> can support up to [ 18] logic PT(s)
+ 5|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | S | 2      |=> can support up to [  8] logic PT(s)
+ 6|CLK_000_P_SYNC_7_|NOD| | S | 1      |=> can support up to [  5] logic PT(s)
+ 7|     IPL_D0_2_|NOD| | S | 1      |=> can support up to [  5] logic PT(s)
+ 8|    IPL_030_0_| IO| | S |10      |=> can support up to [ 14] logic PT(s)
+ 9|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | S | 2      |=> can support up to [  8] logic PT(s)
+10|CLK_000_P_SYNC_5_|NOD| | S | 1      |=> can support up to [  5] logic PT(s)
+11|     IPL_D0_1_|NOD| | S | 1      |=> can support up to [  5] logic PT(s)
+12|    IPL_030_1_| IO| | S |10      |=> can support up to [ 14] logic PT(s)
+13|inst_AS_000_INT|NOD| | S | 2      |=> can support up to [  8] logic PT(s)
+14|CLK_000_P_SYNC_1_|NOD| | S | 1      |=> can support up to [  5] logic PT(s)
+15|     IPL_D0_0_|NOD| | S | 1      |=> can support up to [  5] logic PT(s)
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 1] >	Node-Pin Assignments
+===========================================================================
+ + Macrocell Number
+ | Node Fixed(*)------+
+ |      Sig Type---+  |  to | Block [ 1] IO Pin  |   Device Pin
+ |  Signal Name    |  | pin |      Numbers       |     Numbers
+_|_________________|__|_____|____________________|________________________
+ 0|       CLK_EXP|OUT| | => |   5    6    7 (  0)|   5    4    3 ( 10)
+ 1|         RESET|OUT| | => |   5    6 (  7)   0 |   5    4 (  3)  10 
+ 2|CLK_000_N_SYNC_8_|NOD| | => |   6    7    0    1 |   4    3   10    9 
+ 3|CLK_000_P_SYNC_0_|NOD| | => |   6    7    0    1 |   4    3   10    9 
+ 4|    IPL_030_2_| IO| | => |   7    0 (  1)   2 |   3   10 (  9)   8 
+ 5|inst_AMIGA_BUS_ENABLE_DMA_HIGH|NOD| | => |   7    0    1    2 |   3   10    9    8 
+ 6|CLK_000_P_SYNC_7_|NOD| | => |   0    1    2    3 |  10    9    8    7 
+ 7|     IPL_D0_2_|NOD| | => |   0    1    2    3 |  10    9    8    7 
+ 8|    IPL_030_0_| IO| | => |   1 (  2)   3    4 |   9 (  8)   7    6 
+ 9|inst_AMIGA_BUS_ENABLE_DMA_LOW|NOD| | => |   1    2    3    4 |   9    8    7    6 
+10|CLK_000_P_SYNC_5_|NOD| | => |   2    3    4    5 |   8    7    6    5 
+11|     IPL_D0_1_|NOD| | => |   2    3    4    5 |   8    7    6    5 
+12|    IPL_030_1_| IO| | => |(  3)   4    5    6 |(  7)   6    5    4 
+13|inst_AS_000_INT|NOD| | => |   3    4    5    6 |   7    6    5    4 
+14|CLK_000_P_SYNC_1_|NOD| | => |   4    5    6    7 |   6    5    4    3 
+15|     IPL_D0_0_|NOD| | => |   4    5    6    7 |   6    5    4    3 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 1] >	IO-to-Node Pin Mapping
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Node Destinations Via Output Matrix
+_|_________________|__|___|_____|___________________________________________
+ 0|       CLK_EXP|OUT|*| 10| => | ( 0)   1    2    3    4    5    6    7 
+ 1|    IPL_030_2_| IO|*|  9| => |   2    3  ( 4)   5    6    7    8    9 
+ 2|    IPL_030_0_| IO|*|  8| => |   4    5    6    7  ( 8)   9   10   11 
+ 3|    IPL_030_1_| IO|*|  7| => |   6    7    8    9   10   11  (12)  13 
+ 4|         A_29_|INP|*|  6| => |   8    9   10   11   12   13   14   15 
+ 5|         A_30_|INP|*|  5| => |  10   11   12   13   14   15    0    1 
+ 6|         A_31_|INP|*|  4| => |  12   13   14   15    0    1    2    3 
+ 7|         RESET|OUT|*|  3| => |  14   15    0  ( 1)   2    3    4    5 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 1] >	IO/Node and IO/Input Macrocell Pairing Table
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Input Macrocell and Node Pairs
+_|_________________|__|___|_____|__________________________________________
+ 0|       CLK_EXP|OUT|*| 10| => | Input macrocell   [             -]
+ 1|    IPL_030_2_| IO|*|  9| => | Input macrocell   [             -]
+  |              |   | |   |    | IO paired w/ node [ RN_IPL_030_2_]
+ 2|    IPL_030_0_| IO|*|  8| => | Input macrocell   [             -]
+  |              |   | |   |    | IO paired w/ node [ RN_IPL_030_0_]
+ 3|    IPL_030_1_| IO|*|  7| => | Input macrocell   [             -]
+  |              |   | |   |    | IO paired w/ node [ RN_IPL_030_1_]
+ 4|         A_29_|INP|*|  6| => | Input macrocell   [             -]
+ 5|         A_30_|INP|*|  5| => | Input macrocell   [             -]
+ 6|         A_31_|INP|*|  4| => | Input macrocell   [             -]
+ 7|         RESET|OUT|*|  3| => | Input macrocell   [             -]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 1] >	Input Multiplexer (IMX) Assignments
+===========================================================================
+           +----- IO pin/Input Register, or Macrocell
+IMX No.    |    +---- Block IO Pin or Macrocell Number
+   |       |    |  ABEL Node/      +-- Signal using the Pin or Macrocell
+   |       |    |  Pin Number      |      +- Signal Fixed (*) to Pin/Mcell
+   |       |    |   |  Sig Type    |      | +- Feedback Required (*)
+---|-------|----|---|---|----------|------|-|------------------------------
+   0	[IOpin  0 | 10|OUT        CLK_EXP|*| ]
+	[RegIn  0 |126|                 -| | ]
+	[MCell  0 |125|OUT        CLK_EXP| | ]
+	[MCell  1 |127|OUT          RESET| | ]
+
+   1	[IOpin  1 |  9| IO     IPL_030_2_|*| ] paired w/[ RN_IPL_030_2_]
+	[RegIn  1 |129|                 -| | ]
+	[MCell  2 |128|NOD CLK_000_N_SYNC_8_| |*]
+	[MCell  3 |130|NOD CLK_000_P_SYNC_0_| |*]
+
+   2	[IOpin  2 |  8| IO     IPL_030_0_|*| ] paired w/[ RN_IPL_030_0_]
+	[RegIn  2 |132|                 -| | ]
+	[MCell  4 |131|NOD  RN_IPL_030_2_| |*] paired w/[    IPL_030_2_]
+	[MCell  5 |133|NOD inst_AMIGA_BUS_ENABLE_DMA_HIGH| |*]
+
+   3	[IOpin  3 |  7| IO     IPL_030_1_|*| ] paired w/[ RN_IPL_030_1_]
+	[RegIn  3 |135|                 -| | ]
+	[MCell  6 |134|NOD CLK_000_P_SYNC_7_| |*]
+	[MCell  7 |136|NOD      IPL_D0_2_| |*]
+
+   4	[IOpin  4 |  6|INP          A_29_|*|*]
+	[RegIn  4 |138|                 -| | ]
+	[MCell  8 |137|NOD  RN_IPL_030_0_| |*] paired w/[    IPL_030_0_]
+	[MCell  9 |139|NOD inst_AMIGA_BUS_ENABLE_DMA_LOW| |*]
+
+   5	[IOpin  5 |  5|INP          A_30_|*|*]
+	[RegIn  5 |141|                 -| | ]
+	[MCell 10 |140|NOD CLK_000_P_SYNC_5_| |*]
+	[MCell 11 |142|NOD      IPL_D0_1_| |*]
+
+   6	[IOpin  6 |  4|INP          A_31_|*|*]
+	[RegIn  6 |144|                 -| | ]
+	[MCell 12 |143|NOD  RN_IPL_030_1_| |*] paired w/[    IPL_030_1_]
+	[MCell 13 |145|NOD inst_AS_000_INT| |*]
+
+   7	[IOpin  7 |  3|OUT          RESET|*| ]
+	[RegIn  7 |147|                 -| | ]
+	[MCell 14 |146|NOD CLK_000_P_SYNC_1_| |*]
+	[MCell 15 |148|NOD      IPL_D0_0_| |*]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 1] >	Logic Array Fan-in
+===========================================================================
+  +- Central Switch Matrix No.
+  |   Src (ABEL Node/Pin#)   Signal
+--|--|--------------------|---------------------------------------------------
+Mux00|  Input Pin   (  86)|   RST
+Mux01| IOPin  4  0  (  41)|   BERR
+Mux02|  Mcel  4 13  ( 217)|   CLK_000_P_SYNC_4_
+Mux03| IOPin  5  0  (  60)|   A1
+Mux04| IOPin  6  3  (  68)|   IPL_2_
+Mux05|  Mcel  1  3  ( 130)|   CLK_000_P_SYNC_0_
+Mux06|  Mcel  1  9  ( 139)|   inst_AMIGA_BUS_ENABLE_DMA_LOW
+Mux07|  Mcel  1 11  ( 142)|   IPL_D0_1_
+Mux08|  Mcel  4  8  ( 209)|   inst_BGACK_030_INT_D
+Mux09|          ...       |      ...
+Mux10|  Mcel  1 13  ( 145)|   inst_AS_000_INT
+Mux11|  Mcel  5  6  ( 230)|   CLK_000_P_SYNC_6_
+Mux12|  Mcel  6  7  ( 256)|   CLK_000_N_SYNC_7_
+Mux13|          ...       |      ...
+Mux14|  Mcel  5  4  ( 227)|   SM_AMIGA_5_
+Mux15|  Mcel  4  2  ( 200)|   inst_CLK_OUT_EXP_INT
+Mux16| IOPin  6  2  (  67)|   IPL_0_
+Mux17|  Mcel  1  8  ( 137)|   RN_IPL_030_0_
+Mux18|          ...       |      ...
+Mux19|  Mcel  7 13  ( 289)|   inst_AS_030_D0
+Mux20|  Mcel  7  4  ( 275)|   RN_BGACK_030
+Mux21| IOPin  5  4  (  56)|   IPL_1_
+Mux22|  Mcel  6  5  ( 253)|   inst_RESET_OUT
+Mux23|          ...       |      ...
+Mux24|  Mcel  1  7  ( 136)|   IPL_D0_2_
+Mux25|  Mcel  3  9  ( 187)|   inst_CLK_000_D0
+Mux26|  Mcel  1 12  ( 143)|   RN_IPL_030_1_
+Mux27|  Mcel  1 15  ( 148)|   IPL_D0_0_
+Mux28|  Mcel  1  5  ( 133)|   inst_AMIGA_BUS_ENABLE_DMA_HIGH
+Mux29|  Mcel  2  8  ( 161)|   inst_CLK_000_D1
+Mux30|  Mcel  1  4  ( 131)|   RN_IPL_030_2_
+Mux31|          ...       |      ...
+Mux32|          ...       |      ...
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 2] >	Macrocell (MCell) Cluster Assignments
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+  +--- Macrocell PT Cluster Size
+ |      Sync/Async-------+   |     |  |    Cluster to Mcell Assignment
+ |   Node Fixed(*)----+  |   |     |  |      |   +- XOR PT Size
+ |        Sig Type-+  |  |   |     |  |      |   |  XOR to Mcell Assignment
+ |  Signal Name    |  |  |   |     |  |      |   |          |
+_|_________________|__|__|___|_____|__|______|___|__________|______________
+ 0|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1      | 4 free   | 1 XOR to [ 0] for 1 PT sig
+ 1|    inst_VPA_D|NOD| | S | 1      | 4 free   | 1 XOR to [ 1] for 1 PT sig
+ 2|              | ? | | S |        | 4 free   | 1 XOR free
+ 3|              | ? | | S |        | 4 free   | 1 XOR free
+ 4|   SM_AMIGA_6_|NOD| | S | 3      | 4 to [ 4]| 1 XOR free
+ 5|inst_AS_030_000_SYNC|NOD| | S | 7      | 4 to [ 5]| 1 XOR to [ 5] as logic PT
+ 6|              | ? | | S |        | 4 to [ 5]| 1 XOR free
+ 7|              | ? | | S |        | 4 free   | 1 XOR free
+ 8|inst_CLK_000_D1|NOD| | S | 1      | 4 free   | 1 XOR to [ 8] for 1 PT sig
+ 9|       N_210_i|NOD| | S | 4      | 4 to [ 9]| 1 XOR free
+10|              | ? | | S |        | 4 free   | 1 XOR free
+11|              | ? | | S |        | 4 free   | 1 XOR free
+12|inst_DS_000_ENABLE|NOD| | S | 5      | 4 to [12]| 1 XOR to [12] as logic PT
+13|              | ? | | S |        | 4 free   | 1 XOR free
+14|              | ? | | S |        | 4 free   | 1 XOR free
+15|              | ? | | S |        | 4 free   | 1 XOR free
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 2] >	Maximum PT Capacity
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+
+ |      Sync/Async-------+   |     |
+ |   Node Fixed(*)----+  |   |     |
+ |        Sig Type-+  |  |   |     |
+ |  Signal Name    |  |  |   |     |     Maximum PT Capacity
+_|_________________|__|__|___|_____|_______________________________________
+ 0|AMIGA_BUS_ENABLE_LOW|OUT| | S | 1      |=> can support up to [ 14] logic PT(s)
+ 1|    inst_VPA_D|NOD| | S | 1      |=> can support up to [ 19] logic PT(s)
+ 2|              | ? | | S |        |=> can support up to [ 14] logic PT(s)
+ 3|              | ? | | S |        |=> can support up to [ 10] logic PT(s)
+ 4|   SM_AMIGA_6_|NOD| | S | 3      |=> can support up to [ 10] logic PT(s)
+ 5|inst_AS_030_000_SYNC|NOD| | S | 7      |=> can support up to [ 15] logic PT(s)
+ 6|              | ? | | S |        |=> can support up to [ 10] logic PT(s)
+ 7|              | ? | | S |        |=> can support up to [  9] logic PT(s)
+ 8|inst_CLK_000_D1|NOD| | S | 1      |=> can support up to [ 15] logic PT(s)
+ 9|       N_210_i|NOD| | S | 4      |=> can support up to [ 19] logic PT(s)
+10|              | ? | | S |        |=> can support up to [ 10] logic PT(s)
+11|              | ? | | S |        |=> can support up to [ 15] logic PT(s)
+12|inst_DS_000_ENABLE|NOD| | S | 5      |=> can support up to [ 20] logic PT(s)
+13|              | ? | | S |        |=> can support up to [ 15] logic PT(s)
+14|              | ? | | S |        |=> can support up to [ 15] logic PT(s)
+15|              | ? | | S |        |=> can support up to [ 10] logic PT(s)
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 2] >	Node-Pin Assignments
+===========================================================================
+ + Macrocell Number
+ | Node Fixed(*)------+
+ |      Sig Type---+  |  to | Block [ 2] IO Pin  |   Device Pin
+ |  Signal Name    |  | pin |      Numbers       |     Numbers
+_|_________________|__|_____|____________________|________________________
+ 0|AMIGA_BUS_ENABLE_LOW|OUT| | => |(  5)   6    7    0 |( 20)  21   22   15 
+ 1|    inst_VPA_D|NOD| | => |   5    6    7    0 |  20   21   22   15 
+ 2|              |   | | => |   6    7    0    1 |  21   22   15   16 
+ 3|              |   | | => |   6    7    0    1 |  21   22   15   16 
+ 4|   SM_AMIGA_6_|NOD| | => |   7    0    1    2 |  22   15   16   17 
+ 5|inst_AS_030_000_SYNC|NOD| | => |   7    0    1    2 |  22   15   16   17 
+ 6|              |   | | => |   0    1    2    3 |  15   16   17   18 
+ 7|              |   | | => |   0    1    2    3 |  15   16   17   18 
+ 8|inst_CLK_000_D1|NOD| | => |   1    2    3    4 |  16   17   18   19 
+ 9|       N_210_i|NOD| | => |   1    2    3    4 |  16   17   18   19 
+10|              |   | | => |   2    3    4    5 |  17   18   19   20 
+11|              |   | | => |   2    3    4    5 |  17   18   19   20 
+12|inst_DS_000_ENABLE|NOD| | => |   3    4    5    6 |  18   19   20   21 
+13|              |   | | => |   3    4    5    6 |  18   19   20   21 
+14|              |   | | => |   4    5    6    7 |  19   20   21   22 
+15|              |   | | => |   4    5    6    7 |  19   20   21   22 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 2] >	IO-to-Node Pin Mapping
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Node Destinations Via Output Matrix
+_|_________________|__|___|_____|___________________________________________
+ 0|         A_28_|INP|*| 15| => |   0    1    2    3    4    5    6    7 
+ 1|         A_27_|INP|*| 16| => |   2    3    4    5    6    7    8    9 
+ 2|         A_26_|INP|*| 17| => |   4    5    6    7    8    9   10   11 
+ 3|         A_25_|INP|*| 18| => |   6    7    8    9   10   11   12   13 
+ 4|         A_24_|INP|*| 19| => |   8    9   10   11   12   13   14   15 
+ 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => |  10   11   12   13   14   15  ( 0)   1 
+ 6|        BG_030|INP|*| 21| => |  12   13   14   15    0    1    2    3 
+ 7|              |   | | 22| => |  14   15    0    1    2    3    4    5 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 2] >	IO/Node and IO/Input Macrocell Pairing Table
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Input Macrocell and Node Pairs
+_|_________________|__|___|_____|__________________________________________
+ 0|         A_28_|INP|*| 15| => | Input macrocell   [             -]
+ 1|         A_27_|INP|*| 16| => | Input macrocell   [             -]
+ 2|         A_26_|INP|*| 17| => | Input macrocell   [             -]
+ 3|         A_25_|INP|*| 18| => | Input macrocell   [             -]
+ 4|         A_24_|INP|*| 19| => | Input macrocell   [             -]
+ 5|AMIGA_BUS_ENABLE_LOW|OUT|*| 20| => | Input macrocell   [             -]
+ 6|        BG_030|INP|*| 21| => | Input macrocell   [             -]
+ 7|              |   | | 22| => | Input macrocell   [             -]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 2] >	Input Multiplexer (IMX) Assignments
+===========================================================================
+           +----- IO pin/Input Register, or Macrocell
+IMX No.    |    +---- Block IO Pin or Macrocell Number
+   |       |    |  ABEL Node/      +-- Signal using the Pin or Macrocell
+   |       |    |  Pin Number      |      +- Signal Fixed (*) to Pin/Mcell
+   |       |    |   |  Sig Type    |      | +- Feedback Required (*)
+---|-------|----|---|---|----------|------|-|------------------------------
+   0	[IOpin  0 | 15|INP          A_28_|*|*]
+	[RegIn  0 |150|                 -| | ]
+	[MCell  0 |149|OUT AMIGA_BUS_ENABLE_LOW| | ]
+	[MCell  1 |151|NOD     inst_VPA_D| |*]
+
+   1	[IOpin  1 | 16|INP          A_27_|*|*]
+	[RegIn  1 |153|                 -| | ]
+	[MCell  2 |152|                 -| | ]
+	[MCell  3 |154|                 -| | ]
+
+   2	[IOpin  2 | 17|INP          A_26_|*|*]
+	[RegIn  2 |156|                 -| | ]
+	[MCell  4 |155|NOD    SM_AMIGA_6_| |*]
+	[MCell  5 |157|NOD inst_AS_030_000_SYNC| |*]
+
+   3	[IOpin  3 | 18|INP          A_25_|*|*]
+	[RegIn  3 |159|                 -| | ]
+	[MCell  6 |158|                 -| | ]
+	[MCell  7 |160|                 -| | ]
+
+   4	[IOpin  4 | 19|INP          A_24_|*|*]
+	[RegIn  4 |162|                 -| | ]
+	[MCell  8 |161|NOD inst_CLK_000_D1| |*]
+	[MCell  9 |163|NOD        N_210_i| |*]
+
+   5	[IOpin  5 | 20|OUT AMIGA_BUS_ENABLE_LOW|*| ]
+	[RegIn  5 |165|                 -| | ]
+	[MCell 10 |164|                 -| | ]
+	[MCell 11 |166|                 -| | ]
+
+   6	[IOpin  6 | 21|INP         BG_030|*|*]
+	[RegIn  6 |168|                 -| | ]
+	[MCell 12 |167|NOD inst_DS_000_ENABLE| |*]
+	[MCell 13 |169|                 -| | ]
+
+   7	[IOpin  7 | 22|                 -| | ]
+	[RegIn  7 |171|                 -| | ]
+	[MCell 14 |170|                 -| | ]
+	[MCell 15 |172|                 -| | ]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 2] >	Logic Array Fan-in
+===========================================================================
+  +- Central Switch Matrix No.
+  |   Src (ABEL Node/Pin#)   Signal
+--|--|--------------------|---------------------------------------------------
+Mux00|  Mcel  7  4  ( 275)|   RN_BGACK_030
+Mux01| IOPin  4  0  (  41)|   BERR
+Mux02|  Mcel  5  8  ( 233)|   SM_AMIGA_i_7_
+Mux03|  Mcel  0  8  ( 113)|   SM_AMIGA_1_
+Mux04|  Mcel  2 12  ( 167)|   inst_DS_000_ENABLE
+Mux05|  Mcel  5  0  ( 221)|   inst_CLK_000_PE
+Mux06| IOPin  0  6  (  97)|   A_19_
+Mux07|  Mcel  2  5  ( 157)|   inst_AS_030_000_SYNC
+Mux08| IOPin  5  1  (  59)|   A_17_
+Mux09|  Mcel  5  5  ( 229)|   SM_AMIGA_3_
+Mux10|  Mcel  5  4  ( 227)|   SM_AMIGA_5_
+Mux11| IOPin  6  6  (  71)|   RW
+Mux12| IOPin  5  2  (  58)|   FC_1_
+Mux13|  Mcel  7  5  ( 277)|   inst_nEXP_SPACE_D0reg
+Mux14|  Mcel  2  4  ( 155)|   SM_AMIGA_6_
+Mux15|  Mcel  5  1  ( 223)|   SM_AMIGA_0_
+Mux16|  Mcel  1  9  ( 139)|   inst_AMIGA_BUS_ENABLE_DMA_LOW
+Mux17|  Mcel  5 12  ( 239)|   SM_AMIGA_2_
+Mux18|  Mcel  5  9  ( 235)|   SM_AMIGA_4_
+Mux19|  Mcel  7 13  ( 289)|   inst_AS_030_D0
+Mux20|  Input Pin   (  36)|   VPA
+Mux21|  Input Pin   (  86)|   RST
+Mux22|          ...       |      ...
+Mux23|          ...       |      ...
+Mux24| IOPin  5  3  (  57)|   FC_0_
+Mux25|  Mcel  3  9  ( 187)|   inst_CLK_000_D0
+Mux26| IOPin  0  5  (  96)|   A_16_
+Mux27|          ...       |      ...
+Mux28|          ...       |      ...
+Mux29|  Mcel  2  8  ( 161)|   inst_CLK_000_D1
+Mux30|  Mcel  4  8  ( 209)|   inst_BGACK_030_INT_D
+Mux31| IOPin  0  4  (  95)|   A_18_
+Mux32|          ...       |      ...
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 3] >	Macrocell (MCell) Cluster Assignments
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+  +--- Macrocell PT Cluster Size
+ |      Sync/Async-------+   |     |  |    Cluster to Mcell Assignment
+ |   Node Fixed(*)----+  |   |     |  |      |   +- XOR PT Size
+ |        Sig Type-+  |  |   |     |  |      |   |  XOR to Mcell Assignment
+ |  Signal Name    |  |  |   |     |  |      |   |          |
+_|_________________|__|__|___|_____|__|______|___|__________|______________
+ 0|           VMA| IO| | S | 3      | 4 to [ 0]| 1 XOR free
+ 1|        BG_000| IO| | S | 2      | 4 to [ 1]| 1 XOR free
+ 2|    cpu_est_3_|NOD| | S | 3      | 4 to [ 2]| 1 XOR free
+ 3|inst_CLK_OUT_PRE_D|NOD| | S | 1      | 4 free   | 1 XOR to [ 3] for 1 PT sig
+ 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2      | 4 to [ 4]| 1 XOR free
+ 5|AMIGA_ADDR_ENABLE|OUT| | S | 1      | 4 free   | 1 XOR to [ 5] for 1 PT sig
+ 6|    cpu_est_1_|NOD| | S | 3      | 4 to [ 6]| 1 XOR free
+ 7|CLK_000_N_SYNC_9_|NOD| | S | 1      | 4 free   | 1 XOR to [ 7] for 1 PT sig
+ 8|       UDS_000| IO| | S | 1      | 4 free   | 1 XOR to [ 8] for 1 PT sig
+ 9|inst_CLK_000_D0|NOD| | S | 1      | 4 free   | 1 XOR to [ 9] for 1 PT sig
+10|    cpu_est_0_|NOD| | S | 2      | 4 to [10]| 1 XOR free
+11|CLK_000_N_SYNC_4_|NOD| | S | 1      | 4 free   | 1 XOR to [11] for 1 PT sig
+12|       LDS_000| IO| | S | 1      | 4 free   | 1 XOR to [12] for 1 PT sig
+13|    cpu_est_2_|NOD| | S | 4      | 4 to [13]| 1 XOR free
+14|inst_CLK_000_NE_D0|NOD| | S | 1      | 4 free   | 1 XOR to [14] for 1 PT sig
+15|CLK_000_N_SYNC_3_|NOD| | S | 1      | 4 free   | 1 XOR to [15] for 1 PT sig
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 3] >	Maximum PT Capacity
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+
+ |      Sync/Async-------+   |     |
+ |   Node Fixed(*)----+  |   |     |
+ |        Sig Type-+  |  |   |     |
+ |  Signal Name    |  |  |   |     |     Maximum PT Capacity
+_|_________________|__|__|___|_____|_______________________________________
+ 0|           VMA| IO| | S | 3      |=> can support up to [  5] logic PT(s)
+ 1|        BG_000| IO| | S | 2      |=> can support up to [  9] logic PT(s)
+ 2|    cpu_est_3_|NOD| | S | 3      |=> can support up to [  9] logic PT(s)
+ 3|inst_CLK_OUT_PRE_D|NOD| | S | 1      |=> can support up to [  9] logic PT(s)
+ 4|AMIGA_BUS_ENABLE_HIGH|OUT| | S | 2      |=> can support up to [ 13] logic PT(s)
+ 5|AMIGA_ADDR_ENABLE|OUT| | S | 1      |=> can support up to [  9] logic PT(s)
+ 6|    cpu_est_1_|NOD| | S | 3      |=> can support up to [ 17] logic PT(s)
+ 7|CLK_000_N_SYNC_9_|NOD| | S | 1      |=> can support up to [ 13] logic PT(s)
+ 8|       UDS_000| IO| | S | 1      |=> can support up to [ 13] logic PT(s)
+ 9|inst_CLK_000_D0|NOD| | S | 1      |=> can support up to [ 13] logic PT(s)
+10|    cpu_est_0_|NOD| | S | 2      |=> can support up to [ 17] logic PT(s)
+11|CLK_000_N_SYNC_4_|NOD| | S | 1      |=> can support up to [  9] logic PT(s)
+12|       LDS_000| IO| | S | 1      |=> can support up to [ 13] logic PT(s)
+13|    cpu_est_2_|NOD| | S | 4      |=> can support up to [ 17] logic PT(s)
+14|inst_CLK_000_NE_D0|NOD| | S | 1      |=> can support up to [  9] logic PT(s)
+15|CLK_000_N_SYNC_3_|NOD| | S | 1      |=> can support up to [  9] logic PT(s)
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 3] >	Node-Pin Assignments
+===========================================================================
+ + Macrocell Number
+ | Node Fixed(*)------+
+ |      Sig Type---+  |  to | Block [ 3] IO Pin  |   Device Pin
+ |  Signal Name    |  | pin |      Numbers       |     Numbers
+_|_________________|__|_____|____________________|________________________
+ 0|           VMA| IO| | => |   5    6    7 (  0)|  30   29   28 ( 35)
+ 1|        BG_000| IO| | => |   5 (  6)   7    0 |  30 ( 29)  28   35 
+ 2|    cpu_est_3_|NOD| | => |   6    7    0    1 |  29   28   35   34 
+ 3|inst_CLK_OUT_PRE_D|NOD| | => |   6    7    0    1 |  29   28   35   34 
+ 4|AMIGA_BUS_ENABLE_HIGH|OUT| | => |   7    0 (  1)   2 |  28   35 ( 34)  33 
+ 5|AMIGA_ADDR_ENABLE|OUT| | => |   7    0    1 (  2)|  28   35   34 ( 33)
+ 6|    cpu_est_1_|NOD| | => |   0    1    2    3 |  35   34   33   32 
+ 7|CLK_000_N_SYNC_9_|NOD| | => |   0    1    2    3 |  35   34   33   32 
+ 8|       UDS_000| IO| | => |   1    2 (  3)   4 |  34   33 ( 32)  31 
+ 9|inst_CLK_000_D0|NOD| | => |   1    2    3    4 |  34   33   32   31 
+10|    cpu_est_0_|NOD| | => |   2    3    4    5 |  33   32   31   30 
+11|CLK_000_N_SYNC_4_|NOD| | => |   2    3    4    5 |  33   32   31   30 
+12|       LDS_000| IO| | => |   3 (  4)   5    6 |  32 ( 31)  30   29 
+13|    cpu_est_2_|NOD| | => |   3    4    5    6 |  32   31   30   29 
+14|inst_CLK_000_NE_D0|NOD| | => |   4    5    6    7 |  31   30   29   28 
+15|CLK_000_N_SYNC_3_|NOD| | => |   4    5    6    7 |  31   30   29   28 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 3] >	IO-to-Node Pin Mapping
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Node Destinations Via Output Matrix
+_|_________________|__|___|_____|___________________________________________
+ 0|           VMA| IO|*| 35| => | ( 0)   1    2    3    4    5    6    7 
+ 1|AMIGA_BUS_ENABLE_HIGH|OUT|*| 34| => |   2    3  ( 4)   5    6    7    8    9 
+ 2|AMIGA_ADDR_ENABLE|OUT|*| 33| => |   4  ( 5)   6    7    8    9   10   11 
+ 3|       UDS_000| IO|*| 32| => |   6    7  ( 8)   9   10   11   12   13 
+ 4|       LDS_000| IO|*| 31| => |   8    9   10   11  (12)  13   14   15 
+ 5|         DTACK|INP|*| 30| => |  10   11   12   13   14   15    0    1 
+ 6|        BG_000| IO|*| 29| => |  12   13   14   15    0  ( 1)   2    3 
+ 7|     BGACK_000|INP|*| 28| => |  14   15    0    1    2    3    4    5 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 3] >	IO/Node and IO/Input Macrocell Pairing Table
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Input Macrocell and Node Pairs
+_|_________________|__|___|_____|__________________________________________
+ 0|           VMA| IO|*| 35| => | Input macrocell   [             -]
+  |              |   | |   |    | IO paired w/ node [        RN_VMA]
+ 1|AMIGA_BUS_ENABLE_HIGH|OUT|*| 34| => | Input macrocell   [             -]
+ 2|AMIGA_ADDR_ENABLE|OUT|*| 33| => | Input macrocell   [             -]
+ 3|       UDS_000| IO|*| 32| => | Input macrocell   [             -]
+ 4|       LDS_000| IO|*| 31| => | Input macrocell   [             -]
+ 5|         DTACK|INP|*| 30| => | Input macrocell   [             -]
+ 6|        BG_000| IO|*| 29| => | Input macrocell   [             -]
+  |              |   | |   |    | IO paired w/ node [     RN_BG_000]
+ 7|     BGACK_000|INP|*| 28| => | Input macrocell   [             -]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 3] >	Input Multiplexer (IMX) Assignments
+===========================================================================
+           +----- IO pin/Input Register, or Macrocell
+IMX No.    |    +---- Block IO Pin or Macrocell Number
+   |       |    |  ABEL Node/      +-- Signal using the Pin or Macrocell
+   |       |    |  Pin Number      |      +- Signal Fixed (*) to Pin/Mcell
+   |       |    |   |  Sig Type    |      | +- Feedback Required (*)
+---|-------|----|---|---|----------|------|-|------------------------------
+   0	[IOpin  0 | 35| IO            VMA|*| ] paired w/[        RN_VMA]
+	[RegIn  0 |174|                 -| | ]
+	[MCell  0 |173|NOD         RN_VMA| |*] paired w/[           VMA]
+	[MCell  1 |175|NOD      RN_BG_000| |*] paired w/[        BG_000]
+
+   1	[IOpin  1 | 34|OUT AMIGA_BUS_ENABLE_HIGH|*| ]
+	[RegIn  1 |177|                 -| | ]
+	[MCell  2 |176|NOD     cpu_est_3_| |*]
+	[MCell  3 |178|NOD inst_CLK_OUT_PRE_D| |*]
+
+   2	[IOpin  2 | 33|OUT AMIGA_ADDR_ENABLE|*| ]
+	[RegIn  2 |180|                 -| | ]
+	[MCell  4 |179|OUT AMIGA_BUS_ENABLE_HIGH| | ]
+	[MCell  5 |181|OUT AMIGA_ADDR_ENABLE| | ]
+
+   3	[IOpin  3 | 32| IO        UDS_000|*|*]
+	[RegIn  3 |183|                 -| | ]
+	[MCell  6 |182|NOD     cpu_est_1_| |*]
+	[MCell  7 |184|NOD CLK_000_N_SYNC_9_| |*]
+
+   4	[IOpin  4 | 31| IO        LDS_000|*|*]
+	[RegIn  4 |186|                 -| | ]
+	[MCell  8 |185| IO        UDS_000| | ]
+	[MCell  9 |187|NOD inst_CLK_000_D0| |*]
+
+   5	[IOpin  5 | 30|INP          DTACK|*|*]
+	[RegIn  5 |189|                 -| | ]
+	[MCell 10 |188|NOD     cpu_est_0_| |*]
+	[MCell 11 |190|NOD CLK_000_N_SYNC_4_| |*]
+
+   6	[IOpin  6 | 29| IO         BG_000|*| ] paired w/[     RN_BG_000]
+	[RegIn  6 |192|                 -| | ]
+	[MCell 12 |191| IO        LDS_000| | ]
+	[MCell 13 |193|NOD     cpu_est_2_| |*]
+
+   7	[IOpin  7 | 28|INP      BGACK_000|*|*]
+	[RegIn  7 |195|                 -| | ]
+	[MCell 14 |194|NOD inst_CLK_000_NE_D0| |*]
+	[MCell 15 |196|NOD CLK_000_N_SYNC_3_| |*]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 3] >	Logic Array Fan-in
+===========================================================================
+  +- Central Switch Matrix No.
+  |   Src (ABEL Node/Pin#)   Signal
+--|--|--------------------|---------------------------------------------------
+Mux00|  Input Pin   (  86)|   RST
+Mux01|  Mcel  2  1  ( 151)|   inst_VPA_D
+Mux02|  Mcel  3 15  ( 196)|   CLK_000_N_SYNC_3_
+Mux03|  Mcel  3  2  ( 176)|   cpu_est_3_
+Mux04| IOPin  2  6  (  21)|   BG_030
+Mux05|  Mcel  6  6  ( 254)|   inst_CLK_OUT_PRE_25
+Mux06|  Mcel  5 13  ( 241)|   CLK_000_N_SYNC_2_
+Mux07|  Mcel  3  9  ( 187)|   inst_CLK_000_D0
+Mux08|          ...       |      ...
+Mux09|  Mcel  0  1  ( 103)|   inst_LDS_000_INT
+Mux10|  Mcel  1  2  ( 128)|   CLK_000_N_SYNC_8_
+Mux11|          ...       |      ...
+Mux12|  Mcel  6  9  ( 259)|   inst_CLK_000_NE
+Mux13|  Mcel  7  5  ( 277)|   inst_nEXP_SPACE_D0reg
+Mux14|  Input Pin   (  11)|   CLK_000
+Mux15|  Mcel  2 12  ( 167)|   inst_DS_000_ENABLE
+Mux16|  Mcel  3  6  ( 182)|   cpu_est_1_
+Mux17|  Mcel  3  1  ( 175)|   RN_BG_000
+Mux18|  Mcel  0  5  ( 109)|   inst_UDS_000_INT
+Mux19|  Mcel  7 13  ( 289)|   inst_AS_030_D0
+Mux20|  Mcel  3 10  ( 188)|   cpu_est_0_
+Mux21|  Mcel  3 13  ( 193)|   cpu_est_2_
+Mux22|  Mcel  6  5  ( 253)|   inst_RESET_OUT
+Mux23|  Mcel  7  4  ( 275)|   RN_BGACK_030
+Mux24|  Mcel  3 14  ( 194)|   inst_CLK_000_NE_D0
+Mux25|  Mcel  5  0  ( 221)|   inst_CLK_000_PE
+Mux26|  Mcel  3  0  ( 173)|   RN_VMA
+Mux27|          ...       |      ...
+Mux28|  Mcel  1  5  ( 133)|   inst_AMIGA_BUS_ENABLE_DMA_HIGH
+Mux29|          ...       |      ...
+Mux30|          ...       |      ...
+Mux31|          ...       |      ...
+Mux32|  Mcel  5  8  ( 233)|   SM_AMIGA_i_7_
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 4] >	Macrocell (MCell) Cluster Assignments
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+  +--- Macrocell PT Cluster Size
+ |      Sync/Async-------+   |     |  |    Cluster to Mcell Assignment
+ |   Node Fixed(*)----+  |   |     |  |      |   +- XOR PT Size
+ |        Sig Type-+  |  |   |     |  |      |   |  XOR to Mcell Assignment
+ |  Signal Name    |  |  |   |     |  |      |   |          |
+_|_________________|__|__|___|_____|__|______|___|__________|______________
+ 0|          BERR| IO| | S | 1      | 4 free   | 1 XOR to [ 0] for 1 PT sig
+ 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2      | 4 to [ 1]| 1 XOR free
+ 2|inst_CLK_OUT_EXP_INT|NOD| | S | 1      | 4 free   | 1 XOR to [ 2] for 1 PT sig
+ 3|              | ? | | S |        | 4 free   | 1 XOR free
+ 4|        AS_000| IO| | S | 1      | 4 free   | 1 XOR to [ 4] for 1 PT sig
+ 5|inst_CLK_OUT_PRE_50|NOD| | S | 1      | 4 free   | 1 XOR to [ 5] for 1 PT sig
+ 6|              | ? | | S |        | 4 free   | 1 XOR free
+ 7|              | ? | | S |        | 4 free   | 1 XOR free
+ 8|inst_BGACK_030_INT_D|NOD| | S | 1      | 4 free   | 1 XOR to [ 8] for 1 PT sig
+ 9|        CIIN_0|NOD| | S | 2      | 4 to [ 9]| 1 XOR free
+10|              | ? | | S |        | 4 free   | 1 XOR free
+11|              | ? | | S |        | 4 free   | 1 XOR free
+12|          CIIN|OUT| | S | 1      | 4 free   | 1 XOR to [12] for 1 PT sig
+13|CLK_000_P_SYNC_4_|NOD| | S | 1      | 4 free   | 1 XOR to [13] for 1 PT sig
+14|              | ? | | S |        | 4 free   | 1 XOR free
+15|              | ? | | S |        | 4 free   | 1 XOR free
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 4] >	Maximum PT Capacity
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+
+ |      Sync/Async-------+   |     |
+ |   Node Fixed(*)----+  |   |     |
+ |        Sig Type-+  |  |   |     |
+ |  Signal Name    |  |  |   |     |     Maximum PT Capacity
+_|_________________|__|__|___|_____|_______________________________________
+ 0|          BERR| IO| | S | 1      |=> can support up to [  9] logic PT(s)
+ 1|AMIGA_BUS_DATA_DIR|OUT| | S | 2      |=> can support up to [ 18] logic PT(s)
+ 2|inst_CLK_OUT_EXP_INT|NOD| | S | 1      |=> can support up to [ 14] logic PT(s)
+ 3|              | ? | | S |        |=> can support up to [ 17] logic PT(s)
+ 4|        AS_000| IO| | S | 1      |=> can support up to [ 19] logic PT(s)
+ 5|inst_CLK_OUT_PRE_50|NOD| | S | 1      |=> can support up to [ 19] logic PT(s)
+ 6|              | ? | | S |        |=> can support up to [ 18] logic PT(s)
+ 7|              | ? | | S |        |=> can support up to [ 14] logic PT(s)
+ 8|inst_BGACK_030_INT_D|NOD| | S | 1      |=> can support up to [ 15] logic PT(s)
+ 9|        CIIN_0|NOD| | S | 2      |=> can support up to [ 19] logic PT(s)
+10|              | ? | | S |        |=> can support up to [ 14] logic PT(s)
+11|              | ? | | S |        |=> can support up to [ 18] logic PT(s)
+12|          CIIN|OUT| | S | 1      |=> can support up to [ 19] logic PT(s)
+13|CLK_000_P_SYNC_4_|NOD| | S | 1      |=> can support up to [ 19] logic PT(s)
+14|              | ? | | S |        |=> can support up to [ 14] logic PT(s)
+15|              | ? | | S |        |=> can support up to [ 10] logic PT(s)
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 4] >	Node-Pin Assignments
+===========================================================================
+ + Macrocell Number
+ | Node Fixed(*)------+
+ |      Sig Type---+  |  to | Block [ 4] IO Pin  |   Device Pin
+ |  Signal Name    |  | pin |      Numbers       |     Numbers
+_|_________________|__|_____|____________________|________________________
+ 0|          BERR| IO| | => |   5    6    7 (  0)|  46   47   48 ( 41)
+ 1|AMIGA_BUS_DATA_DIR|OUT| | => |   5    6 (  7)   0 |  46   47 ( 48)  41 
+ 2|inst_CLK_OUT_EXP_INT|NOD| | => |   6    7    0    1 |  47   48   41   42 
+ 3|              |   | | => |   6    7    0    1 |  47   48   41   42 
+ 4|        AS_000| IO| | => |   7    0 (  1)   2 |  48   41 ( 42)  43 
+ 5|inst_CLK_OUT_PRE_50|NOD| | => |   7    0    1    2 |  48   41   42   43 
+ 6|              |   | | => |   0    1    2    3 |  41   42   43   44 
+ 7|              |   | | => |   0    1    2    3 |  41   42   43   44 
+ 8|inst_BGACK_030_INT_D|NOD| | => |   1    2    3    4 |  42   43   44   45 
+ 9|        CIIN_0|NOD| | => |   1    2    3    4 |  42   43   44   45 
+10|              |   | | => |   2    3    4    5 |  43   44   45   46 
+11|              |   | | => |   2    3    4    5 |  43   44   45   46 
+12|          CIIN|OUT| | => |   3    4    5 (  6)|  44   45   46 ( 47)
+13|CLK_000_P_SYNC_4_|NOD| | => |   3    4    5    6 |  44   45   46   47 
+14|              |   | | => |   4    5    6    7 |  45   46   47   48 
+15|              |   | | => |   4    5    6    7 |  45   46   47   48 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 4] >	IO-to-Node Pin Mapping
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Node Destinations Via Output Matrix
+_|_________________|__|___|_____|___________________________________________
+ 0|          BERR| IO|*| 41| => | ( 0)   1    2    3    4    5    6    7 
+ 1|        AS_000| IO|*| 42| => |   2    3  ( 4)   5    6    7    8    9 
+ 2|              |   | | 43| => |   4    5    6    7    8    9   10   11 
+ 3|              |   | | 44| => |   6    7    8    9   10   11   12   13 
+ 4|              |   | | 45| => |   8    9   10   11   12   13   14   15 
+ 5|              |   | | 46| => |  10   11   12   13   14   15    0    1 
+ 6|          CIIN|OUT|*| 47| => | (12)  13   14   15    0    1    2    3 
+ 7|AMIGA_BUS_DATA_DIR|OUT|*| 48| => |  14   15    0  ( 1)   2    3    4    5 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 4] >	IO/Node and IO/Input Macrocell Pairing Table
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Input Macrocell and Node Pairs
+_|_________________|__|___|_____|__________________________________________
+ 0|          BERR| IO|*| 41| => | Input macrocell   [             -]
+ 1|        AS_000| IO|*| 42| => | Input macrocell   [             -]
+ 2|              |   | | 43| => | Input macrocell   [             -]
+ 3|              |   | | 44| => | Input macrocell   [             -]
+ 4|              |   | | 45| => | Input macrocell   [             -]
+ 5|              |   | | 46| => | Input macrocell   [             -]
+ 6|          CIIN|OUT|*| 47| => | Input macrocell   [             -]
+ 7|AMIGA_BUS_DATA_DIR|OUT|*| 48| => | Input macrocell   [             -]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 4] >	Input Multiplexer (IMX) Assignments
+===========================================================================
+           +----- IO pin/Input Register, or Macrocell
+IMX No.    |    +---- Block IO Pin or Macrocell Number
+   |       |    |  ABEL Node/      +-- Signal using the Pin or Macrocell
+   |       |    |  Pin Number      |      +- Signal Fixed (*) to Pin/Mcell
+   |       |    |   |  Sig Type    |      | +- Feedback Required (*)
+---|-------|----|---|---|----------|------|-|------------------------------
+   0	[IOpin  0 | 41| IO           BERR|*|*]
+	[RegIn  0 |198|                 -| | ]
+	[MCell  0 |197| IO           BERR| | ]
+	[MCell  1 |199|OUT AMIGA_BUS_DATA_DIR| | ]
+
+   1	[IOpin  1 | 42| IO         AS_000|*|*]
+	[RegIn  1 |201|                 -| | ]
+	[MCell  2 |200|NOD inst_CLK_OUT_EXP_INT| |*]
+	[MCell  3 |202|                 -| | ]
+
+   2	[IOpin  2 | 43|                 -| | ]
+	[RegIn  2 |204|                 -| | ]
+	[MCell  4 |203| IO         AS_000| | ]
+	[MCell  5 |205|NOD inst_CLK_OUT_PRE_50| |*]
+
+   3	[IOpin  3 | 44|                 -| | ]
+	[RegIn  3 |207|                 -| | ]
+	[MCell  6 |206|                 -| | ]
+	[MCell  7 |208|                 -| | ]
+
+   4	[IOpin  4 | 45|                 -| | ]
+	[RegIn  4 |210|                 -| | ]
+	[MCell  8 |209|NOD inst_BGACK_030_INT_D| |*]
+	[MCell  9 |211|NOD         CIIN_0| |*]
+
+   5	[IOpin  5 | 46|                 -| | ]
+	[RegIn  5 |213|                 -| | ]
+	[MCell 10 |212|                 -| | ]
+	[MCell 11 |214|                 -| | ]
+
+   6	[IOpin  6 | 47|OUT           CIIN|*| ]
+	[RegIn  6 |216|                 -| | ]
+	[MCell 12 |215|OUT           CIIN| | ]
+	[MCell 13 |217|NOD CLK_000_P_SYNC_4_| |*]
+
+   7	[IOpin  7 | 48|OUT AMIGA_BUS_DATA_DIR|*| ]
+	[RegIn  7 |219|                 -| | ]
+	[MCell 14 |218|                 -| | ]
+	[MCell 15 |220|                 -| | ]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 4] >	Logic Array Fan-in
+===========================================================================
+  +- Central Switch Matrix No.
+  |   Src (ABEL Node/Pin#)   Signal
+--|--|--------------------|---------------------------------------------------
+Mux00|  Input Pin   (  86)|   RST
+Mux01| IOPin  5  2  (  58)|   FC_1_
+Mux02|  Mcel  4  9  ( 211)|   CIIN_0
+Mux03| IOPin  2  1  (  16)|   A_27_
+Mux04|  Mcel  7  5  ( 277)|   inst_nEXP_SPACE_D0reg
+Mux05| IOPin  2  4  (  19)|   A_24_
+Mux06| IOPin  0  6  (  97)|   A_19_
+Mux07| IOPin  2  0  (  15)|   A_28_
+Mux08| IOPin  7  0  (  85)|   A_23_
+Mux09| IOPin  1  5  (   5)|   A_30_
+Mux10|  Mcel  1 13  ( 145)|   inst_AS_000_INT
+Mux11| IOPin  0  0  (  91)|   FPU_SENSE
+Mux12| IOPin  2  3  (  18)|   A_25_
+Mux13| IOPin  1  4  (   6)|   A_29_
+Mux14|  Mcel  4  5  ( 205)|   inst_CLK_OUT_PRE_50
+Mux15| IOPin  0  3  (  94)|   A_21_
+Mux16| IOPin  4  1  (  42)|   AS_000
+Mux17| IOPin  2  2  (  17)|   A_26_
+Mux18| IOPin  3  7  (  28)|   BGACK_000
+Mux19|  Mcel  5 10  ( 236)|   CLK_000_P_SYNC_3_
+Mux20| IOPin  7  1  (  84)|   A_22_
+Mux21| IOPin  7  5  (  80)|   RW_000
+Mux22|  Mcel  6  5  ( 253)|   inst_RESET_OUT
+Mux23|  Mcel  7  4  ( 275)|   RN_BGACK_030
+Mux24| IOPin  5  3  (  57)|   FC_0_
+Mux25| IOPin  1  6  (   4)|   A_31_
+Mux26| IOPin  0  5  (  96)|   A_16_
+Mux27| IOPin  5  1  (  59)|   A_17_
+Mux28|  Mcel  7 13  ( 289)|   inst_AS_030_D0
+Mux29| IOPin  0  2  (  93)|   A_20_
+Mux30|          ...       |      ...
+Mux31| IOPin  0  4  (  95)|   A_18_
+Mux32| IOPin  7  3  (  82)|   AS_030
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 5] >	Macrocell (MCell) Cluster Assignments
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+  +--- Macrocell PT Cluster Size
+ |      Sync/Async-------+   |     |  |    Cluster to Mcell Assignment
+ |   Node Fixed(*)----+  |   |     |  |      |   +- XOR PT Size
+ |        Sig Type-+  |  |   |     |  |      |   |  XOR to Mcell Assignment
+ |  Signal Name    |  |  |   |     |  |      |   |          |
+_|_________________|__|__|___|_____|__|______|___|__________|______________
+ 0|inst_CLK_000_PE|NOD| | S | 1      | 4 free   | 1 XOR to [ 0] for 1 PT sig
+ 1|   SM_AMIGA_0_|NOD| | S | 2      | 4 to [ 1]| 1 XOR free
+ 2|CLK_000_N_SYNC_1_|NOD| | S | 1      | 4 free   | 1 XOR to [ 2] for 1 PT sig
+ 3|CLK_000_P_SYNC_9_|NOD| | S | 1      | 4 free   | 1 XOR to [ 3] for 1 PT sig
+ 4|   SM_AMIGA_5_|NOD| | S | 3      | 4 to [ 4]| 1 XOR free
+ 5|   SM_AMIGA_3_|NOD| | S | 5      | 4 to [ 5]| 1 XOR to [ 5] as logic PT
+ 6|CLK_000_P_SYNC_6_|NOD| | S | 1      | 4 free   | 1 XOR to [ 6] for 1 PT sig
+ 7|              | ? | | S |        | 4 free   | 1 XOR free
+ 8| SM_AMIGA_i_7_|NOD| | S |14      | 4 to [ 8]| 1 XOR to [ 8] as logic PT
+ 9|   SM_AMIGA_4_|NOD| | S | 3      | 4 to [ 8]| 1 XOR to [ 8] as logic PT
+10|CLK_000_P_SYNC_3_|NOD| | S | 1      | 4 to [ 8]| 1 XOR to [10] for 1 PT sig
+11|              | ? | | S |        | 4 to [ 9]| 1 XOR free
+12|   SM_AMIGA_2_|NOD| | S | 4      | 4 to [12]| 1 XOR free
+13|CLK_000_N_SYNC_2_|NOD| | S | 1      | 4 free   | 1 XOR to [13] for 1 PT sig
+14|CLK_000_P_SYNC_2_|NOD| | S | 1      | 4 free   | 1 XOR to [14] for 1 PT sig
+15|              | ? | | S |        | 4 free   | 1 XOR free
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 5] >	Maximum PT Capacity
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+
+ |      Sync/Async-------+   |     |
+ |   Node Fixed(*)----+  |   |     |
+ |        Sig Type-+  |  |   |     |
+ |  Signal Name    |  |  |   |     |     Maximum PT Capacity
+_|_________________|__|__|___|_____|_______________________________________
+ 0|inst_CLK_000_PE|NOD| | S | 1      |=> can support up to [  9] logic PT(s)
+ 1|   SM_AMIGA_0_|NOD| | S | 2      |=> can support up to [ 17] logic PT(s)
+ 2|CLK_000_N_SYNC_1_|NOD| | S | 1      |=> can support up to [  9] logic PT(s)
+ 3|CLK_000_P_SYNC_9_|NOD| | S | 1      |=> can support up to [  9] logic PT(s)
+ 4|   SM_AMIGA_5_|NOD| | S | 3      |=> can support up to [ 13] logic PT(s)
+ 5|   SM_AMIGA_3_|NOD| | S | 5      |=> can support up to [ 14] logic PT(s)
+ 6|CLK_000_P_SYNC_6_|NOD| | S | 1      |=> can support up to [ 10] logic PT(s)
+ 7|              | ? | | S |        |=> can support up to [  9] logic PT(s)
+ 8| SM_AMIGA_i_7_|NOD| | S |14      |=> can support up to [ 19] logic PT(s)
+ 9|   SM_AMIGA_4_|NOD| | S | 3      |=> can support up to [  5] logic PT(s)
+10|CLK_000_P_SYNC_3_|NOD| | S | 1      |=> can support up to [  1] logic PT(s)
+11|              | ? | | S |        |=> can support up to [  5] logic PT(s)
+12|   SM_AMIGA_2_|NOD| | S | 4      |=> can support up to [ 13] logic PT(s)
+13|CLK_000_N_SYNC_2_|NOD| | S | 1      |=> can support up to [ 14] logic PT(s)
+14|CLK_000_P_SYNC_2_|NOD| | S | 1      |=> can support up to [ 14] logic PT(s)
+15|              | ? | | S |        |=> can support up to [  9] logic PT(s)
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 5] >	Node-Pin Assignments
+===========================================================================
+ + Macrocell Number
+ | Node Fixed(*)------+
+ |      Sig Type---+  |  to | Block [ 5] IO Pin  |   Device Pin
+ |  Signal Name    |  | pin |      Numbers       |     Numbers
+_|_________________|__|_____|____________________|________________________
+ 0|inst_CLK_000_PE|NOD| | => |   5    6    7    0 |  55   54   53   60 
+ 1|   SM_AMIGA_0_|NOD| | => |   5    6    7    0 |  55   54   53   60 
+ 2|CLK_000_N_SYNC_1_|NOD| | => |   6    7    0    1 |  54   53   60   59 
+ 3|CLK_000_P_SYNC_9_|NOD| | => |   6    7    0    1 |  54   53   60   59 
+ 4|   SM_AMIGA_5_|NOD| | => |   7    0    1    2 |  53   60   59   58 
+ 5|   SM_AMIGA_3_|NOD| | => |   7    0    1    2 |  53   60   59   58 
+ 6|CLK_000_P_SYNC_6_|NOD| | => |   0    1    2    3 |  60   59   58   57 
+ 7|              |   | | => |   0    1    2    3 |  60   59   58   57 
+ 8| SM_AMIGA_i_7_|NOD| | => |   1    2    3    4 |  59   58   57   56 
+ 9|   SM_AMIGA_4_|NOD| | => |   1    2    3    4 |  59   58   57   56 
+10|CLK_000_P_SYNC_3_|NOD| | => |   2    3    4    5 |  58   57   56   55 
+11|              |   | | => |   2    3    4    5 |  58   57   56   55 
+12|   SM_AMIGA_2_|NOD| | => |   3    4    5    6 |  57   56   55   54 
+13|CLK_000_N_SYNC_2_|NOD| | => |   3    4    5    6 |  57   56   55   54 
+14|CLK_000_P_SYNC_2_|NOD| | => |   4    5    6    7 |  56   55   54   53 
+15|              |   | | => |   4    5    6    7 |  56   55   54   53 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 5] >	IO-to-Node Pin Mapping
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Node Destinations Via Output Matrix
+_|_________________|__|___|_____|___________________________________________
+ 0|            A1|INP|*| 60| => |   0    1    2    3    4    5    6    7 
+ 1|         A_17_|INP|*| 59| => |   2    3    4    5    6    7    8    9 
+ 2|         FC_1_|INP|*| 58| => |   4    5    6    7    8    9   10   11 
+ 3|         FC_0_|INP|*| 57| => |   6    7    8    9   10   11   12   13 
+ 4|        IPL_1_|INP|*| 56| => |   8    9   10   11   12   13   14   15 
+ 5|              |   | | 55| => |  10   11   12   13   14   15    0    1 
+ 6|              |   | | 54| => |  12   13   14   15    0    1    2    3 
+ 7|              |   | | 53| => |  14   15    0    1    2    3    4    5 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 5] >	IO/Node and IO/Input Macrocell Pairing Table
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Input Macrocell and Node Pairs
+_|_________________|__|___|_____|__________________________________________
+ 0|            A1|INP|*| 60| => | Input macrocell   [             -]
+ 1|         A_17_|INP|*| 59| => | Input macrocell   [             -]
+ 2|         FC_1_|INP|*| 58| => | Input macrocell   [             -]
+ 3|         FC_0_|INP|*| 57| => | Input macrocell   [             -]
+ 4|        IPL_1_|INP|*| 56| => | Input macrocell   [             -]
+ 5|              |   | | 55| => | Input macrocell   [             -]
+ 6|              |   | | 54| => | Input macrocell   [             -]
+ 7|              |   | | 53| => | Input macrocell   [             -]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 5] >	Input Multiplexer (IMX) Assignments
+===========================================================================
+           +----- IO pin/Input Register, or Macrocell
+IMX No.    |    +---- Block IO Pin or Macrocell Number
+   |       |    |  ABEL Node/      +-- Signal using the Pin or Macrocell
+   |       |    |  Pin Number      |      +- Signal Fixed (*) to Pin/Mcell
+   |       |    |   |  Sig Type    |      | +- Feedback Required (*)
+---|-------|----|---|---|----------|------|-|------------------------------
+   0	[IOpin  0 | 60|INP             A1|*|*]
+	[RegIn  0 |222|                 -| | ]
+	[MCell  0 |221|NOD inst_CLK_000_PE| |*]
+	[MCell  1 |223|NOD    SM_AMIGA_0_| |*]
+
+   1	[IOpin  1 | 59|INP          A_17_|*|*]
+	[RegIn  1 |225|                 -| | ]
+	[MCell  2 |224|NOD CLK_000_N_SYNC_1_| |*]
+	[MCell  3 |226|NOD CLK_000_P_SYNC_9_| |*]
+
+   2	[IOpin  2 | 58|INP          FC_1_|*|*]
+	[RegIn  2 |228|                 -| | ]
+	[MCell  4 |227|NOD    SM_AMIGA_5_| |*]
+	[MCell  5 |229|NOD    SM_AMIGA_3_| |*]
+
+   3	[IOpin  3 | 57|INP          FC_0_|*|*]
+	[RegIn  3 |231|                 -| | ]
+	[MCell  6 |230|NOD CLK_000_P_SYNC_6_| |*]
+	[MCell  7 |232|                 -| | ]
+
+   4	[IOpin  4 | 56|INP         IPL_1_|*|*]
+	[RegIn  4 |234|                 -| | ]
+	[MCell  8 |233|NOD  SM_AMIGA_i_7_| |*]
+	[MCell  9 |235|NOD    SM_AMIGA_4_| |*]
+
+   5	[IOpin  5 | 55|                 -| | ]
+	[RegIn  5 |237|                 -| | ]
+	[MCell 10 |236|NOD CLK_000_P_SYNC_3_| |*]
+	[MCell 11 |238|                 -| | ]
+
+   6	[IOpin  6 | 54|                 -| | ]
+	[RegIn  6 |240|                 -| | ]
+	[MCell 12 |239|NOD    SM_AMIGA_2_| |*]
+	[MCell 13 |241|NOD CLK_000_N_SYNC_2_| |*]
+
+   7	[IOpin  7 | 53|                 -| | ]
+	[RegIn  7 |243|                 -| | ]
+	[MCell 14 |242|NOD CLK_000_P_SYNC_2_| |*]
+	[MCell 15 |244|                 -| | ]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 5] >	Logic Array Fan-in
+===========================================================================
+  +- Central Switch Matrix No.
+  |   Src (ABEL Node/Pin#)   Signal
+--|--|--------------------|---------------------------------------------------
+Mux00|  Input Pin   (  86)|   RST
+Mux01|  Mcel  5 12  ( 239)|   SM_AMIGA_2_
+Mux02|  Mcel  3 10  ( 188)|   cpu_est_0_
+Mux03|  Mcel  0  8  ( 113)|   SM_AMIGA_1_
+Mux04|  Mcel  3  6  ( 182)|   cpu_est_1_
+Mux05|  Mcel  5  0  ( 221)|   inst_CLK_000_PE
+Mux06|  Mcel  0  3  ( 106)|   inst_DTACK_D0
+Mux07|  Mcel  5  3  ( 226)|   CLK_000_P_SYNC_9_
+Mux08|  Mcel  5 14  ( 242)|   CLK_000_P_SYNC_2_
+Mux09|  Mcel  6 11  ( 262)|   CLK_000_N_SYNC_0_
+Mux10|  Mcel  6  9  ( 259)|   inst_CLK_000_NE
+Mux11|          ...       |      ...
+Mux12|  Mcel  1 10  ( 140)|   CLK_000_P_SYNC_5_
+Mux13|  Mcel  2  9  ( 163)|   N_210_i
+Mux14|  Mcel  5  4  ( 227)|   SM_AMIGA_5_
+Mux15|  Mcel  5  2  ( 224)|   CLK_000_N_SYNC_1_
+Mux16|  Mcel  3  2  ( 176)|   cpu_est_3_
+Mux17|  Mcel  3 14  ( 194)|   inst_CLK_000_NE_D0
+Mux18|  Mcel  6 15  ( 268)|   CLK_000_P_SYNC_8_
+Mux19|          ...       |      ...
+Mux20|  Mcel  1 14  ( 146)|   CLK_000_P_SYNC_1_
+Mux21|  Mcel  3 13  ( 193)|   cpu_est_2_
+Mux22|  Mcel  2  1  ( 151)|   inst_VPA_D
+Mux23|          ...       |      ...
+Mux24|          ...       |      ...
+Mux25| IOPin  4  0  (  41)|   BERR
+Mux26|  Mcel  3  0  ( 173)|   RN_VMA
+Mux27|  Mcel  5  5  ( 229)|   SM_AMIGA_3_
+Mux28|          ...       |      ...
+Mux29|  Mcel  2  4  ( 155)|   SM_AMIGA_6_
+Mux30|  Mcel  5  1  ( 223)|   SM_AMIGA_0_
+Mux31|          ...       |      ...
+Mux32|  Mcel  5  9  ( 235)|   SM_AMIGA_4_
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 6] >	Macrocell (MCell) Cluster Assignments
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+  +--- Macrocell PT Cluster Size
+ |      Sync/Async-------+   |     |  |    Cluster to Mcell Assignment
+ |   Node Fixed(*)----+  |   |     |  |      |   +- XOR PT Size
+ |        Sig Type-+  |  |   |     |  |      |   |  XOR to Mcell Assignment
+ |  Signal Name    |  |  |   |     |  |      |   |          |
+_|_________________|__|__|___|_____|__|______|___|__________|______________
+ 0|            RW| IO| | S | 2      | 4 to [ 0]| 1 XOR free
+ 1|   CLK_DIV_OUT|OUT| | S | 1      | 4 free   | 1 XOR to [ 1] for 1 PT sig
+ 2|   SIZE_DMA_0_|NOD| | S | 3      | 4 to [ 2]| 1 XOR free
+ 3|    RST_DLY_2_|NOD| | S | 2      | 4 to [ 3]| 1 XOR free
+ 4|             E|OUT| | S | 2      | 4 to [ 4]| 1 XOR free
+ 5|inst_RESET_OUT|NOD| | S | 2      | 4 to [ 5]| 1 XOR free
+ 6|inst_CLK_OUT_PRE_25|NOD| | S | 2      | 4 to [ 6]| 1 XOR free
+ 7|CLK_000_N_SYNC_7_|NOD| | S | 1      | 4 free   | 1 XOR to [ 7] for 1 PT sig
+ 8|            A0| IO| | S | 3      | 4 to [ 8]| 1 XOR free
+ 9|inst_CLK_000_NE|NOD| | S | 1      | 4 free   | 1 XOR to [ 9] for 1 PT sig
+10|    RST_DLY_1_|NOD| | S | 4      | 4 to [10]| 1 XOR free
+11|CLK_000_N_SYNC_0_|NOD| | S | 1      | 4 free   | 1 XOR to [11] for 1 PT sig
+12|       SIZE_0_| IO| | S | 1      | 4 free   | 1 XOR to [12] for 1 PT sig
+13|   SIZE_DMA_1_|NOD| | S | 3      | 4 to [13]| 1 XOR free
+14|    RST_DLY_0_|NOD| | S | 3      | 4 to [14]| 1 XOR free
+15|CLK_000_P_SYNC_8_|NOD| | S | 1      | 4 free   | 1 XOR to [15] for 1 PT sig
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 6] >	Maximum PT Capacity
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+
+ |      Sync/Async-------+   |     |
+ |   Node Fixed(*)----+  |   |     |
+ |        Sig Type-+  |  |   |     |
+ |  Signal Name    |  |  |   |     |     Maximum PT Capacity
+_|_________________|__|__|___|_____|_______________________________________
+ 0|            RW| IO| | S | 2      |=> can support up to [  9] logic PT(s)
+ 1|   CLK_DIV_OUT|OUT| | S | 1      |=> can support up to [  5] logic PT(s)
+ 2|   SIZE_DMA_0_|NOD| | S | 3      |=> can support up to [  9] logic PT(s)
+ 3|    RST_DLY_2_|NOD| | S | 2      |=> can support up to [  5] logic PT(s)
+ 4|             E|OUT| | S | 2      |=> can support up to [  5] logic PT(s)
+ 5|inst_RESET_OUT|NOD| | S | 2      |=> can support up to [  9] logic PT(s)
+ 6|inst_CLK_OUT_PRE_25|NOD| | S | 2      |=> can support up to [  9] logic PT(s)
+ 7|CLK_000_N_SYNC_7_|NOD| | S | 1      |=> can support up to [  9] logic PT(s)
+ 8|            A0| IO| | S | 3      |=> can support up to [ 13] logic PT(s)
+ 9|inst_CLK_000_NE|NOD| | S | 1      |=> can support up to [  9] logic PT(s)
+10|    RST_DLY_1_|NOD| | S | 4      |=> can support up to [ 17] logic PT(s)
+11|CLK_000_N_SYNC_0_|NOD| | S | 1      |=> can support up to [  9] logic PT(s)
+12|       SIZE_0_| IO| | S | 1      |=> can support up to [  9] logic PT(s)
+13|   SIZE_DMA_1_|NOD| | S | 3      |=> can support up to [ 13] logic PT(s)
+14|    RST_DLY_0_|NOD| | S | 3      |=> can support up to [  9] logic PT(s)
+15|CLK_000_P_SYNC_8_|NOD| | S | 1      |=> can support up to [  5] logic PT(s)
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 6] >	Node-Pin Assignments
+===========================================================================
+ + Macrocell Number
+ | Node Fixed(*)------+
+ |      Sig Type---+  |  to | Block [ 6] IO Pin  |   Device Pin
+ |  Signal Name    |  | pin |      Numbers       |     Numbers
+_|_________________|__|_____|____________________|________________________
+ 0|            RW| IO| | => |   5 (  6)   7    0 |  70 ( 71)  72   65 
+ 1|   CLK_DIV_OUT|OUT| | => |   5    6    7 (  0)|  70   71   72 ( 65)
+ 2|   SIZE_DMA_0_|NOD| | => |   6    7    0    1 |  71   72   65   66 
+ 3|    RST_DLY_2_|NOD| | => |   6    7    0    1 |  71   72   65   66 
+ 4|             E|OUT| | => |   7    0 (  1)   2 |  72   65 ( 66)  67 
+ 5|inst_RESET_OUT|NOD| | => |   7    0    1    2 |  72   65   66   67 
+ 6|inst_CLK_OUT_PRE_25|NOD| | => |   0    1    2    3 |  65   66   67   68 
+ 7|CLK_000_N_SYNC_7_|NOD| | => |   0    1    2    3 |  65   66   67   68 
+ 8|            A0| IO| | => |   1    2    3 (  4)|  66   67   68 ( 69)
+ 9|inst_CLK_000_NE|NOD| | => |   1    2    3    4 |  66   67   68   69 
+10|    RST_DLY_1_|NOD| | => |   2    3    4    5 |  67   68   69   70 
+11|CLK_000_N_SYNC_0_|NOD| | => |   2    3    4    5 |  67   68   69   70 
+12|       SIZE_0_| IO| | => |   3    4 (  5)   6 |  68   69 ( 70)  71 
+13|   SIZE_DMA_1_|NOD| | => |   3    4    5    6 |  68   69   70   71 
+14|    RST_DLY_0_|NOD| | => |   4    5    6    7 |  69   70   71   72 
+15|CLK_000_P_SYNC_8_|NOD| | => |   4    5    6    7 |  69   70   71   72 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 6] >	IO-to-Node Pin Mapping
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Node Destinations Via Output Matrix
+_|_________________|__|___|_____|___________________________________________
+ 0|   CLK_DIV_OUT|OUT|*| 65| => |   0  ( 1)   2    3    4    5    6    7 
+ 1|             E|OUT|*| 66| => |   2    3  ( 4)   5    6    7    8    9 
+ 2|        IPL_0_|INP|*| 67| => |   4    5    6    7    8    9   10   11 
+ 3|        IPL_2_|INP|*| 68| => |   6    7    8    9   10   11   12   13 
+ 4|            A0| IO|*| 69| => | ( 8)   9   10   11   12   13   14   15 
+ 5|       SIZE_0_| IO|*| 70| => |  10   11  (12)  13   14   15    0    1 
+ 6|            RW| IO|*| 71| => |  12   13   14   15  ( 0)   1    2    3 
+ 7|              |   | | 72| => |  14   15    0    1    2    3    4    5 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 6] >	IO/Node and IO/Input Macrocell Pairing Table
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Input Macrocell and Node Pairs
+_|_________________|__|___|_____|__________________________________________
+ 0|   CLK_DIV_OUT|OUT|*| 65| => | Input macrocell   [             -]
+ 1|             E|OUT|*| 66| => | Input macrocell   [             -]
+ 2|        IPL_0_|INP|*| 67| => | Input macrocell   [             -]
+ 3|        IPL_2_|INP|*| 68| => | Input macrocell   [             -]
+ 4|            A0| IO|*| 69| => | Input macrocell   [             -]
+  |              |   | |   |    | IO paired w/ node [         RN_A0]
+ 5|       SIZE_0_| IO|*| 70| => | Input macrocell   [             -]
+ 6|            RW| IO|*| 71| => | Input macrocell   [             -]
+  |              |   | |   |    | IO paired w/ node [         RN_RW]
+ 7|              |   | | 72| => | Input macrocell   [             -]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 6] >	Input Multiplexer (IMX) Assignments
+===========================================================================
+           +----- IO pin/Input Register, or Macrocell
+IMX No.    |    +---- Block IO Pin or Macrocell Number
+   |       |    |  ABEL Node/      +-- Signal using the Pin or Macrocell
+   |       |    |  Pin Number      |      +- Signal Fixed (*) to Pin/Mcell
+   |       |    |   |  Sig Type    |      | +- Feedback Required (*)
+---|-------|----|---|---|----------|------|-|------------------------------
+   0	[IOpin  0 | 65|OUT    CLK_DIV_OUT|*| ]
+	[RegIn  0 |246|                 -| | ]
+	[MCell  0 |245|NOD          RN_RW| |*] paired w/[            RW]
+	[MCell  1 |247|OUT    CLK_DIV_OUT| | ]
+
+   1	[IOpin  1 | 66|OUT              E|*| ]
+	[RegIn  1 |249|                 -| | ]
+	[MCell  2 |248|NOD    SIZE_DMA_0_| |*]
+	[MCell  3 |250|NOD     RST_DLY_2_| |*]
+
+   2	[IOpin  2 | 67|INP         IPL_0_|*|*]
+	[RegIn  2 |252|                 -| | ]
+	[MCell  4 |251|OUT              E| | ]
+	[MCell  5 |253|NOD inst_RESET_OUT| |*]
+
+   3	[IOpin  3 | 68|INP         IPL_2_|*|*]
+	[RegIn  3 |255|                 -| | ]
+	[MCell  6 |254|NOD inst_CLK_OUT_PRE_25| |*]
+	[MCell  7 |256|NOD CLK_000_N_SYNC_7_| |*]
+
+   4	[IOpin  4 | 69| IO             A0|*|*] paired w/[         RN_A0]
+	[RegIn  4 |258|                 -| | ]
+	[MCell  8 |257|NOD          RN_A0| |*] paired w/[            A0]
+	[MCell  9 |259|NOD inst_CLK_000_NE| |*]
+
+   5	[IOpin  5 | 70| IO        SIZE_0_|*|*]
+	[RegIn  5 |261|                 -| | ]
+	[MCell 10 |260|NOD     RST_DLY_1_| |*]
+	[MCell 11 |262|NOD CLK_000_N_SYNC_0_| |*]
+
+   6	[IOpin  6 | 71| IO             RW|*|*] paired w/[         RN_RW]
+	[RegIn  6 |264|                 -| | ]
+	[MCell 12 |263| IO        SIZE_0_| | ]
+	[MCell 13 |265|NOD    SIZE_DMA_1_| |*]
+
+   7	[IOpin  7 | 72|                 -| | ]
+	[RegIn  7 |267|                 -| | ]
+	[MCell 14 |266|NOD     RST_DLY_0_| |*]
+	[MCell 15 |268|NOD CLK_000_P_SYNC_8_| |*]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 6] >	Logic Array Fan-in
+===========================================================================
+  +- Central Switch Matrix No.
+  |   Src (ABEL Node/Pin#)   Signal
+--|--|--------------------|---------------------------------------------------
+Mux00| IOPin  3  4  (  31)|   LDS_000
+Mux01|  Mcel  3 13  ( 193)|   cpu_est_2_
+Mux02|  Mcel  1  6  ( 134)|   CLK_000_P_SYNC_7_
+Mux03|  Mcel  4  5  ( 205)|   inst_CLK_OUT_PRE_50
+Mux04|  Mcel  7  5  ( 277)|   inst_nEXP_SPACE_D0reg
+Mux05|  Mcel  6  6  ( 254)|   inst_CLK_OUT_PRE_25
+Mux06| IOPin  7  5  (  80)|   RW_000
+Mux07|  Mcel  7  6  ( 278)|   CLK_000_N_SYNC_11_
+Mux08| IOPin  3  3  (  32)|   UDS_000
+Mux09|  Mcel  3  3  ( 178)|   inst_CLK_OUT_PRE_D
+Mux10|  Mcel  6 14  ( 266)|   RST_DLY_0_
+Mux11|          ...       |      ...
+Mux12|  Mcel  6 13  ( 265)|   SIZE_DMA_1_
+Mux13|  Mcel  6  8  ( 257)|   RN_A0
+Mux14|  Mcel  0 10  ( 116)|   CLK_000_N_SYNC_6_
+Mux15|          ...       |      ...
+Mux16|  Mcel  4  8  ( 209)|   inst_BGACK_030_INT_D
+Mux17|  Mcel  6  0  ( 245)|   RN_RW
+Mux18|          ...       |      ...
+Mux19|          ...       |      ...
+Mux20|  Mcel  7  4  ( 275)|   RN_BGACK_030
+Mux21|  Input Pin   (  86)|   RST
+Mux22|  Mcel  6 10  ( 260)|   RST_DLY_1_
+Mux23|  Mcel  6  2  ( 248)|   SIZE_DMA_0_
+Mux24|  Mcel  6  3  ( 250)|   RST_DLY_2_
+Mux25|  Mcel  3  9  ( 187)|   inst_CLK_000_D0
+Mux26|          ...       |      ...
+Mux27|  Mcel  6  9  ( 259)|   inst_CLK_000_NE
+Mux28|  Mcel  3  2  ( 176)|   cpu_est_3_
+Mux29|  Mcel  2  8  ( 161)|   inst_CLK_000_D1
+Mux30|  Mcel  3  6  ( 182)|   cpu_est_1_
+Mux31|          ...       |      ...
+Mux32|  Mcel  6  5  ( 253)|   inst_RESET_OUT
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 7] >	Macrocell (MCell) Cluster Assignments
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+  +--- Macrocell PT Cluster Size
+ |      Sync/Async-------+   |     |  |    Cluster to Mcell Assignment
+ |   Node Fixed(*)----+  |   |     |  |      |   +- XOR PT Size
+ |        Sig Type-+  |  |   |     |  |      |   |  XOR to Mcell Assignment
+ |  Signal Name    |  |  |   |     |  |      |   |          |
+_|_________________|__|__|___|_____|__|______|___|__________|______________
+ 0|        RW_000| IO| | S | 3      | 4 to [ 0]| 1 XOR free
+ 1|        FPU_CS|OUT| | S | 1      | 4 free   | 1 XOR to [ 1] for 1 PT sig
+ 2|CLK_000_N_SYNC_10_|NOD| | S | 1      | 4 free   | 1 XOR to [ 2] for 1 PT sig
+ 3|              | ? | | S |        | 4 free   | 1 XOR free
+ 4|     BGACK_030| IO| | S | 3      | 4 to [ 4]| 1 XOR free
+ 5|inst_nEXP_SPACE_D0reg|NOD| | S | 1      | 4 free   | 1 XOR to [ 5] for 1 PT sig
+ 6|CLK_000_N_SYNC_11_|NOD| | S | 1      | 4 free   | 1 XOR to [ 6] for 1 PT sig
+ 7|              | ? | | S |        | 4 free   | 1 XOR free
+ 8|        AS_030| IO| | S | 1      | 4 free   | 1 XOR to [ 8] for 1 PT sig
+ 9|        DSACK1| IO| | S | 4      | 4 to [ 9]| 1 XOR free
+10|              | ? | | S |        | 4 free   | 1 XOR free
+11|              | ? | | S |        | 4 free   | 1 XOR free
+12|       SIZE_1_| IO| | S | 1      | 4 free   | 1 XOR to [12] for 1 PT sig
+13|inst_AS_030_D0|NOD| | S | 1      | 4 free   | 1 XOR to [13] for 1 PT sig
+14|              | ? | | S |        | 4 free   | 1 XOR free
+15|              | ? | | S |        | 4 free   | 1 XOR free
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 7] >	Maximum PT Capacity
+===========================================================================
+ + Macrocell Number
+ | PT Requirements------ Logic  XOR+
+ |      Sync/Async-------+   |     |
+ |   Node Fixed(*)----+  |   |     |
+ |        Sig Type-+  |  |   |     |
+ |  Signal Name    |  |  |   |     |     Maximum PT Capacity
+_|_________________|__|__|___|_____|_______________________________________
+ 0|        RW_000| IO| | S | 3      |=> can support up to [ 13] logic PT(s)
+ 1|        FPU_CS|OUT| | S | 1      |=> can support up to [ 14] logic PT(s)
+ 2|CLK_000_N_SYNC_10_|NOD| | S | 1      |=> can support up to [ 14] logic PT(s)
+ 3|              | ? | | S |        |=> can support up to [ 13] logic PT(s)
+ 4|     BGACK_030| IO| | S | 3      |=> can support up to [ 18] logic PT(s)
+ 5|inst_nEXP_SPACE_D0reg|NOD| | S | 1      |=> can support up to [ 14] logic PT(s)
+ 6|CLK_000_N_SYNC_11_|NOD| | S | 1      |=> can support up to [ 18] logic PT(s)
+ 7|              | ? | | S |        |=> can support up to [ 13] logic PT(s)
+ 8|        AS_030| IO| | S | 1      |=> can support up to [ 15] logic PT(s)
+ 9|        DSACK1| IO| | S | 4      |=> can support up to [ 19] logic PT(s)
+10|              | ? | | S |        |=> can support up to [ 14] logic PT(s)
+11|              | ? | | S |        |=> can support up to [ 18] logic PT(s)
+12|       SIZE_1_| IO| | S | 1      |=> can support up to [ 19] logic PT(s)
+13|inst_AS_030_D0|NOD| | S | 1      |=> can support up to [ 19] logic PT(s)
+14|              | ? | | S |        |=> can support up to [ 14] logic PT(s)
+15|              | ? | | S |        |=> can support up to [ 10] logic PT(s)
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 7] >	Node-Pin Assignments
+===========================================================================
+ + Macrocell Number
+ | Node Fixed(*)------+
+ |      Sig Type---+  |  to | Block [ 7] IO Pin  |   Device Pin
+ |  Signal Name    |  | pin |      Numbers       |     Numbers
+_|_________________|__|_____|____________________|________________________
+ 0|        RW_000| IO| | => |(  5)   6    7    0 |( 80)  79   78   85 
+ 1|        FPU_CS|OUT| | => |   5    6 (  7)   0 |  80   79 ( 78)  85 
+ 2|CLK_000_N_SYNC_10_|NOD| | => |   6    7    0    1 |  79   78   85   84 
+ 3|              |   | | => |   6    7    0    1 |  79   78   85   84 
+ 4|     BGACK_030| IO| | => |   7    0    1 (  2)|  78   85   84 ( 83)
+ 5|inst_nEXP_SPACE_D0reg|NOD| | => |   7    0    1    2 |  78   85   84   83 
+ 6|CLK_000_N_SYNC_11_|NOD| | => |   0    1    2    3 |  85   84   83   82 
+ 7|              |   | | => |   0    1    2    3 |  85   84   83   82 
+ 8|        AS_030| IO| | => |   1    2 (  3)   4 |  84   83 ( 82)  81 
+ 9|        DSACK1| IO| | => |   1    2    3 (  4)|  84   83   82 ( 81)
+10|              |   | | => |   2    3    4    5 |  83   82   81   80 
+11|              |   | | => |   2    3    4    5 |  83   82   81   80 
+12|       SIZE_1_| IO| | => |   3    4    5 (  6)|  82   81   80 ( 79)
+13|inst_AS_030_D0|NOD| | => |   3    4    5    6 |  82   81   80   79 
+14|              |   | | => |   4    5    6    7 |  81   80   79   78 
+15|              |   | | => |   4    5    6    7 |  81   80   79   78 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 7] >	IO-to-Node Pin Mapping
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Node Destinations Via Output Matrix
+_|_________________|__|___|_____|___________________________________________
+ 0|         A_23_|INP|*| 85| => |   0    1    2    3    4    5    6    7 
+ 1|         A_22_|INP|*| 84| => |   2    3    4    5    6    7    8    9 
+ 2|     BGACK_030| IO|*| 83| => | ( 4)   5    6    7    8    9   10   11 
+ 3|        AS_030| IO|*| 82| => |   6    7  ( 8)   9   10   11   12   13 
+ 4|        DSACK1| IO|*| 81| => |   8  ( 9)  10   11   12   13   14   15 
+ 5|        RW_000| IO|*| 80| => |  10   11   12   13   14   15  ( 0)   1 
+ 6|       SIZE_1_| IO|*| 79| => | (12)  13   14   15    0    1    2    3 
+ 7|        FPU_CS|OUT|*| 78| => |  14   15    0  ( 1)   2    3    4    5 
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 7] >	IO/Node and IO/Input Macrocell Pairing Table
+===========================================================================
+ +- Block IO Pin
+ |  Device Pin No.--------+
+ |    Pin Fixed(*)----+   |
+ |       Sig Type--+  |   |     |
+ |     Signal Name |  |   |     |  Input Macrocell and Node Pairs
+_|_________________|__|___|_____|__________________________________________
+ 0|         A_23_|INP|*| 85| => | Input macrocell   [             -]
+ 1|         A_22_|INP|*| 84| => | Input macrocell   [             -]
+ 2|     BGACK_030| IO|*| 83| => | Input macrocell   [             -]
+  |              |   | |   |    | IO paired w/ node [  RN_BGACK_030]
+ 3|        AS_030| IO|*| 82| => | Input macrocell   [             -]
+ 4|        DSACK1| IO|*| 81| => | Input macrocell   [             -]
+  |              |   | |   |    | IO paired w/ node [     RN_DSACK1]
+ 5|        RW_000| IO|*| 80| => | Input macrocell   [             -]
+  |              |   | |   |    | IO paired w/ node [     RN_RW_000]
+ 6|       SIZE_1_| IO|*| 79| => | Input macrocell   [             -]
+ 7|        FPU_CS|OUT|*| 78| => | Input macrocell   [             -]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 7] >	Input Multiplexer (IMX) Assignments
+===========================================================================
+           +----- IO pin/Input Register, or Macrocell
+IMX No.    |    +---- Block IO Pin or Macrocell Number
+   |       |    |  ABEL Node/      +-- Signal using the Pin or Macrocell
+   |       |    |  Pin Number      |      +- Signal Fixed (*) to Pin/Mcell
+   |       |    |   |  Sig Type    |      | +- Feedback Required (*)
+---|-------|----|---|---|----------|------|-|------------------------------
+   0	[IOpin  0 | 85|INP          A_23_|*|*]
+	[RegIn  0 |270|                 -| | ]
+	[MCell  0 |269|NOD      RN_RW_000| |*] paired w/[        RW_000]
+	[MCell  1 |271|OUT         FPU_CS| | ]
+
+   1	[IOpin  1 | 84|INP          A_22_|*|*]
+	[RegIn  1 |273|                 -| | ]
+	[MCell  2 |272|NOD CLK_000_N_SYNC_10_| |*]
+	[MCell  3 |274|                 -| | ]
+
+   2	[IOpin  2 | 83| IO      BGACK_030|*| ] paired w/[  RN_BGACK_030]
+	[RegIn  2 |276|                 -| | ]
+	[MCell  4 |275|NOD   RN_BGACK_030| |*] paired w/[     BGACK_030]
+	[MCell  5 |277|NOD inst_nEXP_SPACE_D0reg| |*]
+
+   3	[IOpin  3 | 82| IO         AS_030|*|*]
+	[RegIn  3 |279|                 -| | ]
+	[MCell  6 |278|NOD CLK_000_N_SYNC_11_| |*]
+	[MCell  7 |280|                 -| | ]
+
+   4	[IOpin  4 | 81| IO         DSACK1|*| ] paired w/[     RN_DSACK1]
+	[RegIn  4 |282|                 -| | ]
+	[MCell  8 |281| IO         AS_030| | ]
+	[MCell  9 |283|NOD      RN_DSACK1| |*] paired w/[        DSACK1]
+
+   5	[IOpin  5 | 80| IO         RW_000|*|*] paired w/[     RN_RW_000]
+	[RegIn  5 |285|                 -| | ]
+	[MCell 10 |284|                 -| | ]
+	[MCell 11 |286|                 -| | ]
+
+   6	[IOpin  6 | 79| IO        SIZE_1_|*|*]
+	[RegIn  6 |288|                 -| | ]
+	[MCell 12 |287| IO        SIZE_1_| | ]
+	[MCell 13 |289|NOD inst_AS_030_D0| |*]
+
+   7	[IOpin  7 | 78|OUT         FPU_CS|*| ]
+	[RegIn  7 |291|                 -| | ]
+	[MCell 14 |290|                 -| | ]
+	[MCell 15 |292|                 -| | ]
+---------------------------------------------------------------------------
+===========================================================================
+	< Block [ 7] >	Logic Array Fan-in
+===========================================================================
+  +- Central Switch Matrix No.
+  |   Src (ABEL Node/Pin#)   Signal
+--|--|--------------------|---------------------------------------------------
+Mux00|  Input Pin   (  86)|   RST
+Mux01| IOPin  4  0  (  41)|   BERR
+Mux02|  Mcel  5  8  ( 233)|   SM_AMIGA_i_7_
+Mux03|  Mcel  6  5  ( 253)|   inst_RESET_OUT
+Mux04| IOPin  0  4  (  95)|   A_18_
+Mux05|  Mcel  7  9  ( 283)|   RN_DSACK1
+Mux06| IOPin  0  6  (  97)|   A_19_
+Mux07|  Mcel  7 13  ( 289)|   inst_AS_030_D0
+Mux08|  Mcel  3  7  ( 184)|   CLK_000_N_SYNC_9_
+Mux09| IOPin  7  3  (  82)|   AS_030
+Mux10|  Mcel  5  1  ( 223)|   SM_AMIGA_0_
+Mux11| IOPin  6  6  (  71)|   RW
+Mux12| IOPin  5  2  (  58)|   FC_1_
+Mux13|  Mcel  7  5  ( 277)|   inst_nEXP_SPACE_D0reg
+Mux14|  Mcel  7  2  ( 272)|   CLK_000_N_SYNC_10_
+Mux15|  Mcel  0 12  ( 119)|   inst_AS_000_DMA
+Mux16| IOPin  4  1  (  42)|   AS_000
+Mux17| IOPin  5  3  (  57)|   FC_0_
+Mux18|  Mcel  0  8  ( 113)|   SM_AMIGA_1_
+Mux19| IOPin  0  0  (  91)|   FPU_SENSE
+Mux20|  Mcel  7  4  ( 275)|   RN_BGACK_030
+Mux21|  Input Pin   (  14)|   nEXP_SPACE
+Mux22|  Mcel  3  3  ( 178)|   inst_CLK_OUT_PRE_D
+Mux23|  Mcel  6  2  ( 248)|   SIZE_DMA_0_
+Mux24|          ...       |      ...
+Mux25|  Mcel  6 13  ( 265)|   SIZE_DMA_1_
+Mux26| IOPin  0  5  (  96)|   A_16_
+Mux27| IOPin  5  1  (  59)|   A_17_
+Mux28|  Input Pin   (  64)|   CLK_030
+Mux29|  Mcel  5  4  ( 227)|   SM_AMIGA_5_
+Mux30|  Mcel  7  0  ( 269)|   RN_RW_000
+Mux31|  Mcel  5  0  ( 221)|   inst_CLK_000_PE
+Mux32| IOPin  3  7  (  28)|   BGACK_000
+---------------------------------------------------------------------------
\ No newline at end of file
diff --git a/Logic/68030_tk.rpt b/Logic/68030_tk.rpt
new file mode 100644
index 0000000..4982a66
--- /dev/null
+++ b/Logic/68030_tk.rpt
@@ -0,0 +1,1852 @@
+|--------------------------------------------|
+|- ispLEVER Fitter Report File              -|
+|- Version 1.8.00.04.29.14                       -|
+|- (c)Copyright, Lattice Semiconductor 2002 -|
+|--------------------------------------------|
+
+
+
+
+Project_Summary
+~~~~~~~~~~~~~~~
+
+Project Name :          68030_tk
+Project Path :          C:\Users\Matze\Documents\GitHub\68030tk\Logic
+Project Fitted on :     Sun Jan 24 16:20:59 2016
+
+Device :                M4A5-128/64
+Package :               100TQFP
+Speed :                 -10
+Partnumber :            M4A5-128/64-10VC
+Source Format :         Pure_VHDL
+
+
+// Project '68030_tk' was Fitted Successfully! //
+
+
+Compilation_Times
+~~~~~~~~~~~~~~~~~
+Reading/DRC                                   0 sec
+Partition                                     0 sec
+Place                                         0 sec
+Route                                         0 sec
+Jedec/Report generation                       0 sec
+                                         --------
+Fitter                                   00:00:00
+
+
+Design_Summary
+~~~~~~~~~~~~~~
+  Total Input Pins :                 32
+  Total Output Pins :                19
+  Total Bidir I/O Pins :             10
+  Total Flip-Flops :                 80
+  Total Product Terms :             236
+  Total Reserved Pins :               0
+  Total Reserved Blocks :             0
+
+
+Device_Resource_Summary
+~~~~~~~~~~~~~~~~~~~~~~~
+                                 Total
+                               Available  Used  Available  Utilization
+Dedicated Pins
+  Input-Only Pins                 2        2      0    -->   100%
+  Clock/Input Pins                4        4      0    -->   100%
+I/O Pins                         64       55      9    -->    85%
+Logic Macrocells                128      100     28    -->    78%
+  Input Registers                64        0     64    -->     0%
+  Unusable Macrocells            ..        0     ..
+
+CSM Outputs/Total Block Inputs  264      228     36    -->    86%
+Logical Product Terms           640      236    404    -->    36%
+Product Term Clusters           128       55     73    -->    42%
+
+
+Blocks_Resource_Summary
+~~~~~~~~~~~~~~~~~~~~~~~
+                                                                  # of PT  
+                   I/O    Inp    Macrocells   Macrocells   logic  clusters 
+          Fanin    Pins   Reg   Used Unusable  available    PTs   available  Pwr
+---------------------------------------------------------------------------------
+Maximum     33      8      8     --     --         16       80       16       -
+---------------------------------------------------------------------------------
+Block  A    28      8      0     13      0          3       42        5       Lo 
+Block  B    27      8      0     16      0          0       46        7       Lo 
+Block  C    28      7      0      7      0          9       22       11       Lo 
+Block  D    27      8      0     16      0          0       28        9       Lo 
+Block  E    32      4      0      9      0          7       11       14       Lo 
+Block  F    27      5      0     13      0          3       38        8       Lo 
+Block  G    27      7      0     16      0          0       32        6       Lo 
+Block  H    32      8      0     10      0          6       17       13       Lo 
+---------------------------------------------------------------------------------
+
+<Note> Four rightmost columns above reflect last status of the placement process.
+<Note> Pwr (Power) : Hi = High
+                     Lo = Low.
+
+
+Optimizer_and_Fitter_Options
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Pin Assignment :                       Yes
+Group Assignment :                     No
+Pin Reservation :                      No (1)
+Block Reservation :                    No
+
+@Ignore_Project_Constraints :
+  Pin Assignments :                    No
+      Keep Block Assignment            --
+      Keep Segment Assignment          --
+  Group Assignments :                  No
+  Macrocell Assignment :               No
+      Keep Block Assignment            --
+      Keep Segment Assignment          --
+
+@Backannotate_Project_Constraints
+  Pin Assignments :                    No
+  Pin And Block Assignments :          No
+  Pin, Macrocell and Block :           No
+
+@Timing_Constraints :                  No
+
+@Global_Project_Optimization :
+  Balanced Partitioning :              Yes
+  Spread Placement :                   Yes
+
+  Note :
+    Pack Design :
+       Balanced Partitioning = No
+       Spread Placement      = No
+    Spread Design :
+       Balanced Partitioning = Yes
+       Spread Placement      = Yes
+
+@Logic_Synthesis :
+  Logic Reduction :                    Yes
+  Node Collapsing :                    Yes
+  D/T Synthesis :                      Yes
+  Clock Optimization :                 No
+  Input Register Optimization :        Yes
+  XOR Synthesis :                      Yes
+  Max. P-Term for Collapsing :         16
+  Max. P-Term for Splitting :          16
+  Max. Equation Fanin :                32
+  Keep Xor :                           Yes
+
+@Utilization_options
+  Max. % of macrocells used :          100
+  Max. % of block inputs used :        100
+  Max. % of segment lines used :       ---
+  Max. % of macrocells used :          ---
+
+
+@Import_Source_Constraint_Option       No
+
+@Zero_Hold_Time                        Yes
+
+@Pull_up                               Yes
+
+@User_Signature                        #H0
+
+@Output_Slew_Rate                      Default = Slow(2)
+
+@Power                                 Default = High(2)
+
+
+Device Options:
+<Note> 1 : Reserved unused I/Os can be independently driven to Low or High, and does not
+           follow the drive level set for the Global Configure Unused I/O Option.
+<Note> 2 : For user-specified constraints on individual signals, refer to the Output, 
+           Bidir and Burried Signal Lists.
+
+
+
+
+Pinout_Listing
+~~~~~~~~~~~~~~
+      | Pin  |Blk |Assigned|
+Pin No| Type |Pad |Pin     | Signal name
+---------------------------------------------------------------
+    1 |  GND |    |        |
+    2 | JTAG |    |        |
+    3 |  I_O | B7 |   *    |RESET
+4     |  I_O | B6 |   *    |A_31_
+5     |  I_O | B5 |   *    |A_30_
+6     |  I_O | B4 |   *    |A_29_
+7     |  I_O | B3 |   *    |IPL_030_1_
+8     |  I_O | B2 |   *    |IPL_030_0_
+9     |  I_O | B1 |   *    |IPL_030_2_
+10    |  I_O | B0 |   *    |CLK_EXP
+11    | CkIn |    |   *    |CLK_000
+12    |  Vcc |    |        |
+13    |  GND |    |        |
+14    | CkIn |    |   *    |nEXP_SPACE
+15    |  I_O | C0 |   *    |A_28_
+16    |  I_O | C1 |   *    |A_27_
+17    |  I_O | C2 |   *    |A_26_
+18    |  I_O | C3 |   *    |A_25_
+19    |  I_O | C4 |   *    |A_24_
+20    |  I_O | C5 |   *    |AMIGA_BUS_ENABLE_LOW
+21    |  I_O | C6 |   *    |BG_030
+22    |  I_O | C7 |        |
+23    | JTAG |    |        |
+24    | JTAG |    |        |
+25    |  GND |    |        |
+26    |  GND |    |        |
+27    |  GND |    |        |
+28    |  I_O | D7 |   *    |BGACK_000
+29    |  I_O | D6 |   *    |BG_000
+30    |  I_O | D5 |   *    |DTACK
+31    |  I_O | D4 |   *    |LDS_000
+32    |  I_O | D3 |   *    |UDS_000
+33    |  I_O | D2 |   *    |AMIGA_ADDR_ENABLE
+34    |  I_O | D1 |   *    |AMIGA_BUS_ENABLE_HIGH
+35    |  I_O | D0 |   *    |VMA
+36    |  Inp |    |   *    |VPA
+37    |  Vcc |    |        |
+38    |  GND |    |        |
+39    |  GND |    |        |
+40    |  Vcc |    |        |
+41    |  I_O | E0 |   *    |BERR
+42    |  I_O | E1 |   *    |AS_000
+43    |  I_O | E2 |        |
+44    |  I_O | E3 |        |
+45    |  I_O | E4 |        |
+46    |  I_O | E5 |        |
+47    |  I_O | E6 |   *    |CIIN
+48    |  I_O | E7 |   *    |AMIGA_BUS_DATA_DIR
+49    |  GND |    |        |
+50    |  GND |    |        |
+51    |  GND |    |        |
+52    | JTAG |    |        |
+53    |  I_O | F7 |        |
+54    |  I_O | F6 |        |
+55    |  I_O | F5 |        |
+56    |  I_O | F4 |   *    |IPL_1_
+57    |  I_O | F3 |   *    |FC_0_
+58    |  I_O | F2 |   *    |FC_1_
+59    |  I_O | F1 |   *    |A_17_
+60    |  I_O | F0 |   *    |A1
+61    | CkIn |    |   *    |CLK_OSZI
+62    |  Vcc |    |        |
+63    |  GND |    |        |
+64    | CkIn |    |   *    |CLK_030
+65    |  I_O | G0 |   *    |CLK_DIV_OUT
+66    |  I_O | G1 |   *    |E
+67    |  I_O | G2 |   *    |IPL_0_
+68    |  I_O | G3 |   *    |IPL_2_
+69    |  I_O | G4 |   *    |A0
+70    |  I_O | G5 |   *    |SIZE_0_
+71    |  I_O | G6 |   *    |RW
+72    |  I_O | G7 |        |
+73    | JTAG |    |        |
+74    | JTAG |    |        |
+75    |  GND |    |        |
+76    |  GND |    |        |
+77    |  GND |    |        |
+78    |  I_O | H7 |   *    |FPU_CS
+79    |  I_O | H6 |   *    |SIZE_1_
+80    |  I_O | H5 |   *    |RW_000
+81    |  I_O | H4 |   *    |DSACK1
+82    |  I_O | H3 |   *    |AS_030
+83    |  I_O | H2 |   *    |BGACK_030
+84    |  I_O | H1 |   *    |A_22_
+85    |  I_O | H0 |   *    |A_23_
+86    |  Inp |    |   *    |RST
+87    |  Vcc |    |        |
+88    |  GND |    |        |
+89    |  GND |    |        |
+90    |  Vcc |    |        |
+91    |  I_O | A0 |   *    |FPU_SENSE
+92    |  I_O | A1 |   *    |AVEC
+93    |  I_O | A2 |   *    |A_20_
+94    |  I_O | A3 |   *    |A_21_
+95    |  I_O | A4 |   *    |A_18_
+96    |  I_O | A5 |   *    |A_16_
+97    |  I_O | A6 |   *    |A_19_
+98    |  I_O | A7 |   *    |DS_030
+99    |  GND |    |        |
+100   |  GND |    |        |
+
+---------------------------------------------------------------------------
+
+<Note> Blk Pad : This notation refers to the Block I/O pad number in the device.
+<Note> Assigned Pin : user or dedicated input assignment (E.g. Clock pins).
+<Note> Pin Type : 
+           CkIn : Dedicated input or clock pin 
+           CLK  : Dedicated clock pin
+           INP  : Dedicated input pin
+           JTAG : JTAG Control and test pin
+           NC   : No connected
+
+
+
+Input_Signal_List
+~~~~~~~~~~~~~~~~~
+                 P R
+            Pin  r e O   Input 
+Pin Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
+----------------------------------------------------------------------
+ 60  F   .  I/O          -B------  Low Slow      A1   
+ 96  A   .  I/O          --C-E--H  Low Slow      A_16_   
+ 59  F   .  I/O          --C-E--H  Low Slow      A_17_   
+ 95  A   .  I/O          --C-E--H  Low Slow      A_18_   
+ 97  A   .  I/O          --C-E--H  Low Slow      A_19_   
+ 93  A   .  I/O          ----E---  Low Slow      A_20_   
+ 94  A   .  I/O          ----E---  Low Slow      A_21_   
+ 84  H   .  I/O          ----E---  Low Slow      A_22_   
+ 85  H   .  I/O          ----E---  Low Slow      A_23_   
+ 19  C   .  I/O          ----E---  Low Slow      A_24_   
+ 18  C   .  I/O          ----E---  Low Slow      A_25_   
+ 17  C   .  I/O          ----E---  Low Slow      A_26_   
+ 16  C   .  I/O          ----E---  Low Slow      A_27_   
+ 15  C   .  I/O          ----E---  Low Slow      A_28_   
+  6  B   .  I/O          ----E---  Low Slow      A_29_   
+  5  B   .  I/O          ----E---  Low Slow      A_30_   
+  4  B   .  I/O          ----E---  Low Slow      A_31_   
+ 28  D   .  I/O          ----E--H  Low Slow      BGACK_000   
+ 21  C   .  I/O          ---D----  Low Slow      BG_030   
+ 30  D   .  I/O          A-------  Low Slow      DTACK   
+ 57  F   .  I/O          --C-E--H  Low Slow      FC_0_   
+ 58  F   .  I/O          --C-E--H  Low Slow      FC_1_   
+ 91  A   .  I/O          ----E--H  Low Slow      FPU_SENSE   
+ 67  G   .  I/O          -B------  Low Slow      IPL_0_   
+ 56  F   .  I/O          -B------  Low Slow      IPL_1_   
+ 68  G   .  I/O          -B------  Low Slow      IPL_2_   
+ 11  .   . Ck/I          ---D----   -  Slow      CLK_000   
+ 14  .   . Ck/I          -------H   -  Slow      nEXP_SPACE   
+ 36  .   .  Ded          --C-----   -  Slow      VPA   
+ 61  .   . Ck/I          ABCDEFGH   -  Slow      CLK_OSZI   
+ 64  .   . Ck/I          A------H   -  Slow      CLK_030   
+ 86  .   .  Ded          ABCDEFGH   -  Slow      RST   
+----------------------------------------------------------------------
+
+<Note> Power : Hi = High
+               MH = Medium High
+               ML = Medium Low
+               Lo = Low
+
+
+
+Output_Signal_List
+~~~~~~~~~~~~~~~~~~
+                 P R
+            Pin  r e O   Output 
+Pin Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
+----------------------------------------------------------------------
+ 33  D   1  COM          --------  Low Fast      AMIGA_ADDR_ENABLE   
+ 48  E   2  COM          --------  Low Fast      AMIGA_BUS_DATA_DIR   
+ 34  D   2  COM          --------  Low Fast      AMIGA_BUS_ENABLE_HIGH   
+ 20  C   1  COM          --------  Low Fast      AMIGA_BUS_ENABLE_LOW   
+ 92  A   1  COM          --------  Low Slow      AVEC   
+ 83  H   3  DFF  * *     --------  Low Slow      BGACK_030   
+ 29  D   2  DFF  * *     --------  Low Slow      BG_000   
+ 47  E   1  COM          --------  Low Slow      CIIN   
+ 65  G   1  DFF  * *     --------  Low Fast      CLK_DIV_OUT   
+ 10  B   1  COM          --------  Low Fast      CLK_EXP   
+ 81  H   4  DFF  * *     --------  Low Slow      DSACK1   
+ 98  A   1  COM          --------  Low Slow      DS_030   
+ 66  G   2  COM          --------  Low Slow      E   
+ 78  H   1  COM          --------  Low Fast      FPU_CS   
+  8  B  10  DFF  * *     --------  Low Slow      IPL_030_0_   
+  7  B  10  DFF  * *     --------  Low Slow      IPL_030_1_   
+  9  B  10  DFF  * *     --------  Low Slow      IPL_030_2_   
+  3  B   1  COM          --------  Low Slow      RESET   
+ 35  D   3  TFF  * *     --------  Low Slow      VMA   
+----------------------------------------------------------------------
+
+<Note> Power : Hi = High
+               MH = Medium High
+               ML = Medium Low
+               Lo = Low
+
+
+
+Bidir_Signal_List
+~~~~~~~~~~~~~~~~~
+                 P R
+            Pin  r e O   Bidir 
+Pin Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
+----------------------------------------------------------------------
+ 69  G   3  DFF  * *     A-------  Low Slow      A0   
+ 42  E   1  COM          A---E--H  Low Slow      AS_000   
+ 82  H   1  COM          ----E--H  Low Slow      AS_030   
+ 41  E   1  COM          ABC--F-H  Low Slow      BERR   
+ 31  D   1  COM          A-----G-  Low Slow      LDS_000   
+ 71  G   2  DFF  * *     --C----H  Low Slow      RW   
+ 80  H   3  DFF  * *     A---E-G-  Low Slow      RW_000   
+ 70  G   1  COM          A-------  Low Slow      SIZE_0_   
+ 79  H   1  COM          A-------  Low Slow      SIZE_1_   
+ 32  D   1  COM          A-----G-  Low Slow      UDS_000   
+----------------------------------------------------------------------
+
+<Note> Power : Hi = High
+               MH = Medium High
+               ML = Medium Low
+               Lo = Low
+
+
+
+Buried_Signal_List
+~~~~~~~~~~~~~~~~~~
+                 P R
+            Pin  r e O   Node 
+#Mc Blk PTs Type e s E   Fanout    Pwr Slew      Signal 
+----------------------------------------------------------------------
+ E9  E   2  COM          ----E---  Low Slow      CIIN_0   
+ G11  G   1  DFF  * *     -----F--  Low Slow      CLK_000_N_SYNC_0_   
+ H2  H   1  DFF  * *     -------H  Low Slow      CLK_000_N_SYNC_10_   
+ H6  H   1  DFF  * *     ------G-  Low Slow      CLK_000_N_SYNC_11_   
+ F2  F   1  DFF  * *     -----F--  Low Slow      CLK_000_N_SYNC_1_   
+ F13  F   1  DFF  * *     ---D----  Low Slow      CLK_000_N_SYNC_2_   
+ D15  D   1  DFF  * *     ---D----  Low Slow      CLK_000_N_SYNC_3_   
+ D11  D   1  DFF  * *     A-------  Low Slow      CLK_000_N_SYNC_4_   
+ A14  A   1  DFF  * *     A-------  Low Slow      CLK_000_N_SYNC_5_   
+ A10  A   1  DFF  * *     ------G-  Low Slow      CLK_000_N_SYNC_6_   
+ G7  G   1  DFF  * *     -B------  Low Slow      CLK_000_N_SYNC_7_   
+ B2  B   1  DFF  * *     ---D----  Low Slow      CLK_000_N_SYNC_8_   
+ D7  D   1  DFF  * *     -------H  Low Slow      CLK_000_N_SYNC_9_   
+ B3  B   1  DFF  * *     -B------  Low Slow      CLK_000_P_SYNC_0_   
+ B14  B   1  DFF  * *     -----F--  Low Slow      CLK_000_P_SYNC_1_   
+ F14  F   1  DFF  * *     -----F--  Low Slow      CLK_000_P_SYNC_2_   
+ F10  F   1  DFF  * *     ----E---  Low Slow      CLK_000_P_SYNC_3_   
+ E13  E   1  DFF  * *     -B------  Low Slow      CLK_000_P_SYNC_4_   
+ B10  B   1  DFF  * *     -----F--  Low Slow      CLK_000_P_SYNC_5_   
+ F6  F   1  DFF  * *     -B------  Low Slow      CLK_000_P_SYNC_6_   
+ B6  B   1  DFF  * *     ------G-  Low Slow      CLK_000_P_SYNC_7_   
+ G15  G   1  DFF  * *     -----F--  Low Slow      CLK_000_P_SYNC_8_   
+ F3  F   1  DFF  * *     -----F--  Low Slow      CLK_000_P_SYNC_9_   
+ A6  A   2  DFF  * *     A-------  Low Slow      CYCLE_DMA_0_   
+ A2  A   3  DFF  * *     A-------  Low Slow      CYCLE_DMA_1_   
+ B15  B   1  DFF  * *     -B------  Low Slow      IPL_D0_0_   
+ B11  B   1  DFF  * *     -B------  Low Slow      IPL_D0_1_   
+ B7  B   1  DFF  * *     -B------  Low Slow      IPL_D0_2_   
+ C9  C   4  COM          -----F--  Low Slow      N_210_i   
+ G8  G   3  DFF  * *     ------G-  Low  -        RN_A0   --> A0
+ H4  H   3  DFF  * *     ABCDE-GH  Low  -        RN_BGACK_030   --> BGACK_030
+ D1  D   2  DFF  * *     ---D----  Low  -        RN_BG_000   --> BG_000
+ H9  H   4  DFF  * *     -------H  Low  -        RN_DSACK1   --> DSACK1
+ B8  B  10  DFF  * *     -B------  Low  -        RN_IPL_030_0_   --> IPL_030_0_
+ B12  B  10  DFF  * *     -B------  Low  -        RN_IPL_030_1_   --> IPL_030_1_
+ B4  B  10  DFF  * *     -B------  Low  -        RN_IPL_030_2_   --> IPL_030_2_
+ G0  G   2  DFF  * *     ------G-  Low  -        RN_RW   --> RW
+ H0  H   3  DFF  * *     -------H  Low  -        RN_RW_000   --> RW_000
+ D0  D   3  TFF  * *     ---D-F--  Low  -        RN_VMA   --> VMA
+ G14  G   3  DFF  * *     ------G-  Low Slow      RST_DLY_0_   
+ G10  G   4  DFF  * *     ------G-  Low Slow      RST_DLY_1_   
+ G3  G   2  DFF  * *     ------G-  Low Slow      RST_DLY_2_   
+ G2  G   3  DFF  * *     ------GH  Low Slow      SIZE_DMA_0_   
+ G13  G   3  DFF  * *     ------GH  Low Slow      SIZE_DMA_1_   
+ F1  F   2  DFF  * *     --C--F-H  Low Slow      SM_AMIGA_0_   
+ A8  A   3  DFF  * *     A-C--F-H  Low Slow      SM_AMIGA_1_   
+ F12  F   4  DFF  * *     A-C--F--  Low Slow      SM_AMIGA_2_   
+ F5  F   5  TFF  * *     --C--F--  Low Slow      SM_AMIGA_3_   
+ F9  F   3  DFF  * *     --C--F--  Low Slow      SM_AMIGA_4_   
+ F4  F   3  DFF  * *     -BC--F-H  Low Slow      SM_AMIGA_5_   
+ C4  C   3  DFF  * *     A-C--F--  Low Slow      SM_AMIGA_6_   
+ F8  F  14  DFF  * *     --CD---H  Low Slow      SM_AMIGA_i_7_   
+ D10  D   2  DFF  * *     ---D-F--  Low Slow      cpu_est_0_   
+ D6  D   3  DFF  * *     ---D-FG-  Low Slow      cpu_est_1_   
+ D13  D   4  DFF  * *     ---D-FG-  Low Slow      cpu_est_2_   
+ D2  D   3  DFF  * *     ---D-FG-  Low Slow      cpu_est_3_   
+ B5  B   2  DFF  * *     -B-D----  Low Slow      inst_AMIGA_BUS_ENABLE_DMA_HIGH   
+ B9  B   2  DFF  * *     -BC-----  Low Slow      inst_AMIGA_BUS_ENABLE_DMA_LOW   
+ A12  A   7  DFF  * *     A------H  Low Slow      inst_AS_000_DMA   
+ B13  B   2  DFF  * *     -B--E---  Low Slow      inst_AS_000_INT   
+ C5  C   7  DFF  * *     --C-----  Low Slow      inst_AS_030_000_SYNC   
+ H13  H   1  DFF  * *     -BCDE--H  Low Slow      inst_AS_030_D0   
+ E8  E   1  DFF  * *     -BC---G-  Low Slow      inst_BGACK_030_INT_D   
+ D9  D   1  DFF  * *     -BCD--G-  Low Slow      inst_CLK_000_D0   
+ C8  C   1  DFF  * *     -BC---G-  Low Slow      inst_CLK_000_D1   
+ G9  G   1  DFF  * *     A--D-FG-  Low Slow      inst_CLK_000_NE   
+ D14  D   1  DFF  * *     ---D-F--  Low Slow      inst_CLK_000_NE_D0   
+ F0  F   1  DFF  * *     A-CD-F-H  Low Slow      inst_CLK_000_PE   
+ A13  A   8  DFF  * *     A-------  Low Slow      inst_CLK_030_H   
+ E2  E   1  DFF  * *     -B------  Low Slow      inst_CLK_OUT_EXP_INT   
+ G6  G   2  DFF  * *     ---D--G-  Low Slow      inst_CLK_OUT_PRE_25   
+ E5  E   1  DFF  * *     ----E-G-  Low Slow      inst_CLK_OUT_PRE_50   
+ D3  D   1  DFF  * *     ------GH  Low Slow      inst_CLK_OUT_PRE_D   
+ A9  A   9  DFF  * *     A-------  Low Slow      inst_DS_000_DMA   
+ C12  C   5  DFF  * *     --CD----  Low Slow      inst_DS_000_ENABLE   
+ A3  A   1  DFF  * *     -----F--  Low Slow      inst_DTACK_D0   
+ A1  A   3  DFF  * *     A--D----  Low Slow      inst_LDS_000_INT   
+ G5  G   2  DFF  * *     AB-DE-GH  Low Slow      inst_RESET_OUT   
+ A5  A   2  DFF  * *     A--D----  Low Slow      inst_UDS_000_INT   
+ C1  C   1  DFF  * *     ---D-F--  Low Slow      inst_VPA_D   
+ H5  H   1  DFF  * *     A-CDE-GH  Low Slow      inst_nEXP_SPACE_D0reg   
+----------------------------------------------------------------------
+
+<Note> Power : Hi = High
+               MH = Medium High
+               ML = Medium Low
+               Lo = Low
+
+
+
+
+Signals_Fanout_List
+~~~~~~~~~~~~~~~~~~~
+Signal Source  :    Fanout List
+-----------------------------------------------------------------------------
+    SIZE_1_{ I}:inst_LDS_000_INT{ A}
+      A_31_{ C}:           CIIN{ E}         CIIN_0{ E}
+     IPL_2_{ H}:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
+               :      IPL_D0_2_{ B}
+      FC_1_{ G}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ C}
+     IPL_1_{ G}:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
+               :      IPL_D0_1_{ B}
+     AS_030{ I}:         AS_000{ E}           BERR{ E}         FPU_CS{ H}
+               : inst_AS_030_D0{ H}
+     IPL_0_{ H}:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
+               :      IPL_D0_0_{ B}
+     AS_000{ F}:         AS_030{ H}         DS_030{ A}AMIGA_BUS_DATA_DIR{ E}
+               :      BGACK_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
+               :   CYCLE_DMA_0_{ A}   CYCLE_DMA_1_{ A} inst_CLK_030_H{ A}
+      FC_0_{ G}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ C}
+    UDS_000{ E}:             A0{ G}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
+               :    SIZE_DMA_0_{ G}    SIZE_DMA_1_{ G} inst_CLK_030_H{ A}
+    LDS_000{ E}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}    SIZE_DMA_0_{ G}
+               :    SIZE_DMA_1_{ G} inst_CLK_030_H{ A}
+         A1{ G}:inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}
+ nEXP_SPACE{. }:inst_nEXP_SPACE_D0reg{ H}
+       BERR{ F}:         DSACK1{ H}inst_AS_000_INT{ B}    SM_AMIGA_5_{ F}
+               :inst_AS_030_000_SYNC{ C}    SM_AMIGA_0_{ F}    SM_AMIGA_4_{ F}
+               :inst_DS_000_ENABLE{ C}    SM_AMIGA_6_{ C}    SM_AMIGA_1_{ A}
+               :    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}  SM_AMIGA_i_7_{ F}
+     BG_030{ D}:         BG_000{ D}
+  BGACK_000{ E}:           BERR{ E}         FPU_CS{ H}      BGACK_030{ H}
+    CLK_030{. }:         DSACK1{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
+               : inst_CLK_030_H{ A}
+    CLK_000{. }:inst_CLK_000_D0{ D}
+  FPU_SENSE{ B}:           BERR{ E}         FPU_CS{ H}
+      DTACK{ E}:  inst_DTACK_D0{ A}
+        VPA{. }:     inst_VPA_D{ C}
+        RST{. }:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
+               :         RW_000{ H}             A0{ G}         BG_000{ D}
+               :      BGACK_030{ H}         DSACK1{ H}            VMA{ D}
+               :             RW{ G}inst_AS_000_INT{ B}    SM_AMIGA_5_{ F}
+               :inst_AMIGA_BUS_ENABLE_DMA_LOW{ B} inst_AS_030_D0{ H}inst_nEXP_SPACE_D0reg{ H}
+               :inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ E}inst_AS_000_DMA{ A}
+               :inst_DS_000_DMA{ A}   CYCLE_DMA_0_{ A}   CYCLE_DMA_1_{ A}
+               :    SIZE_DMA_0_{ G}    SIZE_DMA_1_{ G}     inst_VPA_D{ C}
+               :inst_UDS_000_INT{ A}inst_LDS_000_INT{ A}  inst_DTACK_D0{ A}
+               : inst_RESET_OUT{ G}      IPL_D0_0_{ B}      IPL_D0_1_{ B}
+               :      IPL_D0_2_{ B}    SM_AMIGA_0_{ F}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}
+               :    SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C}     RST_DLY_0_{ G}
+               :     RST_DLY_1_{ G}     RST_DLY_2_{ G}    SM_AMIGA_6_{ C}
+               : inst_CLK_030_H{ A}    SM_AMIGA_1_{ A}    SM_AMIGA_3_{ F}
+               :    SM_AMIGA_2_{ F}  SM_AMIGA_i_7_{ F}
+    SIZE_0_{ H}:inst_LDS_000_INT{ A}
+      A_30_{ C}:           CIIN{ E}         CIIN_0{ E}
+      A_29_{ C}:           CIIN{ E}         CIIN_0{ E}
+      A_28_{ D}:           CIIN{ E}         CIIN_0{ E}
+      A_27_{ D}:           CIIN{ E}         CIIN_0{ E}
+      A_26_{ D}:           CIIN{ E}         CIIN_0{ E}
+      A_25_{ D}:           CIIN{ E}         CIIN_0{ E}
+      A_24_{ D}:           CIIN{ E}         CIIN_0{ E}
+      A_23_{ I}:           CIIN{ E}         CIIN_0{ E}
+      A_22_{ I}:           CIIN{ E}         CIIN_0{ E}
+      A_21_{ B}:           CIIN{ E}         CIIN_0{ E}
+      A_20_{ B}:           CIIN{ E}         CIIN_0{ E}
+      A_19_{ B}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ C}
+      A_18_{ B}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ C}
+      A_17_{ G}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ C}
+      A_16_{ B}:           BERR{ E}         FPU_CS{ H}inst_AS_030_000_SYNC{ C}
+RN_IPL_030_2_{ C}:     IPL_030_2_{ B}
+RN_IPL_030_1_{ C}:     IPL_030_1_{ B}
+RN_IPL_030_0_{ C}:     IPL_030_0_{ B}
+     RW_000{ I}:AMIGA_BUS_DATA_DIR{ E}             RW{ G}inst_DS_000_DMA{ A}
+  RN_RW_000{ I}:         RW_000{ H}
+         A0{ H}:inst_UDS_000_INT{ A}inst_LDS_000_INT{ A}
+      RN_A0{ H}:             A0{ G}
+  RN_BG_000{ E}:         BG_000{ D}
+RN_BGACK_030{ I}:        SIZE_1_{ H}         AS_030{ H}         AS_000{ E}
+               :         DS_030{ A}        UDS_000{ D}        LDS_000{ D}
+               :AMIGA_BUS_DATA_DIR{ E}        SIZE_0_{ G}AMIGA_BUS_ENABLE_LOW{ C}
+               :AMIGA_BUS_ENABLE_HIGH{ D}         RW_000{ H}             A0{ G}
+               :      BGACK_030{ H}             RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}
+               :inst_AS_030_000_SYNC{ C}inst_BGACK_030_INT_D{ E}inst_AS_000_DMA{ A}
+               :inst_DS_000_DMA{ A}   CYCLE_DMA_0_{ A}   CYCLE_DMA_1_{ A}
+               :    SIZE_DMA_0_{ G}    SIZE_DMA_1_{ G}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}
+               : inst_CLK_030_H{ A}
+  RN_DSACK1{ I}:         DSACK1{ H}
+     RN_VMA{ E}:            VMA{ D}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
+               :  SM_AMIGA_i_7_{ F}
+         RW{ H}:         RW_000{ H}inst_DS_000_ENABLE{ C}
+      RN_RW{ H}:             RW{ G}
+ cpu_est_0_{ E}:            VMA{ D}     cpu_est_0_{ D}     cpu_est_1_{ D}
+               :     cpu_est_2_{ D}     cpu_est_3_{ D}    SM_AMIGA_3_{ F}
+               :    SM_AMIGA_2_{ F}  SM_AMIGA_i_7_{ F}
+ cpu_est_1_{ E}:              E{ G}            VMA{ D}     cpu_est_1_{ D}
+               :     cpu_est_2_{ D}     cpu_est_3_{ D}    SM_AMIGA_3_{ F}
+               :    SM_AMIGA_2_{ F}  SM_AMIGA_i_7_{ F}
+ cpu_est_2_{ E}:              E{ G}            VMA{ D}     cpu_est_2_{ D}
+               :     cpu_est_3_{ D}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
+               :  SM_AMIGA_i_7_{ F}
+ cpu_est_3_{ E}:              E{ G}            VMA{ D}     cpu_est_1_{ D}
+               :     cpu_est_3_{ D}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
+               :  SM_AMIGA_i_7_{ F}
+inst_AS_000_INT{ C}:         AS_000{ E}inst_AS_000_INT{ B}
+SM_AMIGA_5_{ G}:         RW_000{ H}inst_AS_000_INT{ B}    SM_AMIGA_5_{ F}
+               :        N_210_i{ C}    SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C}
+               :  SM_AMIGA_i_7_{ F}
+inst_AMIGA_BUS_ENABLE_DMA_LOW{ C}:AMIGA_BUS_ENABLE_LOW{ C}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}
+inst_AS_030_D0{ I}:           CIIN{ E}         BG_000{ D}         DSACK1{ H}
+               :inst_AS_000_INT{ B}inst_AS_030_000_SYNC{ C}inst_DS_000_ENABLE{ C}
+               :         CIIN_0{ E}
+inst_nEXP_SPACE_D0reg{ I}:        SIZE_1_{ H}         AS_030{ H}         DS_030{ A}
+               :AMIGA_BUS_DATA_DIR{ E}        SIZE_0_{ G}             A0{ G}
+               :         BG_000{ D}         DSACK1{ H}inst_AS_030_000_SYNC{ C}
+               :        N_210_i{ C}    SM_AMIGA_6_{ C}         CIIN_0{ E}
+inst_AS_030_000_SYNC{ D}:inst_AS_030_000_SYNC{ C}        N_210_i{ C}    SM_AMIGA_6_{ C}
+inst_BGACK_030_INT_D{ F}:             A0{ G}             RW{ G}inst_AMIGA_BUS_ENABLE_DMA_LOW{ B}
+               :inst_AS_030_000_SYNC{ C}    SIZE_DMA_0_{ G}    SIZE_DMA_1_{ G}
+               :inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}
+inst_AS_000_DMA{ B}:         AS_030{ H}inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}
+               : inst_CLK_030_H{ A}
+inst_DS_000_DMA{ B}:         DS_030{ A}inst_DS_000_DMA{ A}
+CYCLE_DMA_0_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}   CYCLE_DMA_0_{ A}
+               :   CYCLE_DMA_1_{ A} inst_CLK_030_H{ A}
+CYCLE_DMA_1_{ B}:inst_AS_000_DMA{ A}inst_DS_000_DMA{ A}   CYCLE_DMA_1_{ A}
+               : inst_CLK_030_H{ A}
+SIZE_DMA_0_{ H}:        SIZE_1_{ H}        SIZE_0_{ G}    SIZE_DMA_0_{ G}
+SIZE_DMA_1_{ H}:        SIZE_1_{ H}        SIZE_0_{ G}    SIZE_DMA_1_{ G}
+ inst_VPA_D{ D}:            VMA{ D}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
+               :  SM_AMIGA_i_7_{ F}
+inst_UDS_000_INT{ B}:        UDS_000{ D}inst_UDS_000_INT{ A}
+inst_LDS_000_INT{ B}:        LDS_000{ D}inst_LDS_000_INT{ A}
+inst_CLK_OUT_PRE_D{ E}:    CLK_DIV_OUT{ G}         DSACK1{ H}
+inst_DTACK_D0{ B}:    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}  SM_AMIGA_i_7_{ F}
+inst_RESET_OUT{ H}:         AS_030{ H}         AS_000{ E}         DS_030{ A}
+               :        UDS_000{ D}        LDS_000{ D}          RESET{ B}
+               :         RW_000{ H}             A0{ G}             RW{ G}
+               : inst_RESET_OUT{ G}
+inst_CLK_OUT_PRE_50{ F}:inst_CLK_OUT_PRE_50{ E}inst_CLK_OUT_PRE_25{ G}inst_CLK_OUT_EXP_INT{ E}
+    N_210_i{ D}:  SM_AMIGA_i_7_{ F}
+inst_CLK_OUT_PRE_25{ H}:inst_CLK_OUT_PRE_D{ D}inst_CLK_OUT_PRE_25{ G}
+inst_CLK_000_D1{ D}:        N_210_i{ C}CLK_000_P_SYNC_0_{ B}CLK_000_N_SYNC_0_{ G}
+               :    SM_AMIGA_6_{ C}
+inst_CLK_000_D0{ E}:         BG_000{ D}        N_210_i{ C}inst_CLK_000_D1{ C}
+               :CLK_000_P_SYNC_0_{ B}CLK_000_N_SYNC_0_{ G}    SM_AMIGA_6_{ C}
+inst_CLK_000_PE{ G}:         RW_000{ H}      BGACK_030{ H}            VMA{ D}
+               :    SM_AMIGA_5_{ F}   CYCLE_DMA_0_{ A}   CYCLE_DMA_1_{ A}
+               :    SM_AMIGA_0_{ F}    SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C}
+               :    SM_AMIGA_6_{ C}    SM_AMIGA_1_{ A}    SM_AMIGA_3_{ F}
+               :    SM_AMIGA_2_{ F}  SM_AMIGA_i_7_{ F}
+inst_CLK_OUT_EXP_INT{ F}:        CLK_EXP{ B}
+CLK_000_P_SYNC_9_{ G}:inst_CLK_000_PE{ F}
+inst_CLK_000_NE{ H}:            VMA{ D}    SM_AMIGA_5_{ F} inst_RESET_OUT{ G}
+               :inst_CLK_000_NE_D0{ D}    SM_AMIGA_0_{ F}    SM_AMIGA_4_{ F}
+               :     RST_DLY_0_{ G}     RST_DLY_1_{ G}     RST_DLY_2_{ G}
+               :    SM_AMIGA_1_{ A}  SM_AMIGA_i_7_{ F}
+CLK_000_N_SYNC_11_{ I}:inst_CLK_000_NE{ G}
+  IPL_D0_0_{ C}:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
+  IPL_D0_1_{ C}:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
+  IPL_D0_2_{ C}:     IPL_030_2_{ B}     IPL_030_1_{ B}     IPL_030_0_{ B}
+inst_CLK_000_NE_D0{ E}:     cpu_est_0_{ D}     cpu_est_1_{ D}     cpu_est_2_{ D}
+               :     cpu_est_3_{ D}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
+               :  SM_AMIGA_i_7_{ F}
+SM_AMIGA_0_{ G}:         RW_000{ H}        N_210_i{ C}    SM_AMIGA_0_{ F}
+               :inst_DS_000_ENABLE{ C}  SM_AMIGA_i_7_{ F}
+inst_AMIGA_BUS_ENABLE_DMA_HIGH{ C}:AMIGA_BUS_ENABLE_HIGH{ D}inst_AMIGA_BUS_ENABLE_DMA_HIGH{ B}
+SM_AMIGA_4_{ G}:        N_210_i{ C}    SM_AMIGA_4_{ F}inst_DS_000_ENABLE{ C}
+               :    SM_AMIGA_3_{ F}  SM_AMIGA_i_7_{ F}
+inst_DS_000_ENABLE{ D}:        UDS_000{ D}        LDS_000{ D}inst_DS_000_ENABLE{ C}
+ RST_DLY_0_{ H}: inst_RESET_OUT{ G}     RST_DLY_0_{ G}     RST_DLY_1_{ G}
+               :     RST_DLY_2_{ G}
+ RST_DLY_1_{ H}: inst_RESET_OUT{ G}     RST_DLY_0_{ G}     RST_DLY_1_{ G}
+               :     RST_DLY_2_{ G}
+ RST_DLY_2_{ H}: inst_RESET_OUT{ G}     RST_DLY_0_{ G}     RST_DLY_1_{ G}
+               :     RST_DLY_2_{ G}
+CLK_000_P_SYNC_0_{ C}:CLK_000_P_SYNC_1_{ B}
+CLK_000_P_SYNC_1_{ C}:CLK_000_P_SYNC_2_{ F}
+CLK_000_P_SYNC_2_{ G}:CLK_000_P_SYNC_3_{ F}
+CLK_000_P_SYNC_3_{ G}:CLK_000_P_SYNC_4_{ E}
+CLK_000_P_SYNC_4_{ F}:CLK_000_P_SYNC_5_{ B}
+CLK_000_P_SYNC_5_{ C}:CLK_000_P_SYNC_6_{ F}
+CLK_000_P_SYNC_6_{ G}:CLK_000_P_SYNC_7_{ B}
+CLK_000_P_SYNC_7_{ C}:CLK_000_P_SYNC_8_{ G}
+CLK_000_P_SYNC_8_{ H}:CLK_000_P_SYNC_9_{ F}
+CLK_000_N_SYNC_0_{ H}:CLK_000_N_SYNC_1_{ F}
+CLK_000_N_SYNC_1_{ G}:CLK_000_N_SYNC_2_{ F}
+CLK_000_N_SYNC_2_{ G}:CLK_000_N_SYNC_3_{ D}
+CLK_000_N_SYNC_3_{ E}:CLK_000_N_SYNC_4_{ D}
+CLK_000_N_SYNC_4_{ E}:CLK_000_N_SYNC_5_{ A}
+CLK_000_N_SYNC_5_{ B}:CLK_000_N_SYNC_6_{ A}
+CLK_000_N_SYNC_6_{ B}:CLK_000_N_SYNC_7_{ G}
+CLK_000_N_SYNC_7_{ H}:CLK_000_N_SYNC_8_{ B}
+CLK_000_N_SYNC_8_{ C}:CLK_000_N_SYNC_9_{ D}
+CLK_000_N_SYNC_9_{ E}:         DSACK1{ H}CLK_000_N_SYNC_10_{ H}
+CLK_000_N_SYNC_10_{ I}:         DSACK1{ H}CLK_000_N_SYNC_11_{ H}
+SM_AMIGA_6_{ D}:    SM_AMIGA_5_{ F}inst_UDS_000_INT{ A}inst_LDS_000_INT{ A}
+               :        N_210_i{ C}inst_DS_000_ENABLE{ C}    SM_AMIGA_6_{ C}
+               :  SM_AMIGA_i_7_{ F}
+inst_CLK_030_H{ B}:inst_DS_000_DMA{ A} inst_CLK_030_H{ A}
+SM_AMIGA_1_{ B}:         DSACK1{ H}        N_210_i{ C}    SM_AMIGA_0_{ F}
+               :    SM_AMIGA_1_{ A}  SM_AMIGA_i_7_{ F}
+SM_AMIGA_3_{ G}:        N_210_i{ C}    SM_AMIGA_3_{ F}    SM_AMIGA_2_{ F}
+               :  SM_AMIGA_i_7_{ F}
+SM_AMIGA_2_{ G}:        N_210_i{ C}    SM_AMIGA_1_{ A}    SM_AMIGA_2_{ F}
+               :  SM_AMIGA_i_7_{ F}
+SM_AMIGA_i_7_{ G}:AMIGA_BUS_ENABLE_HIGH{ D}         RW_000{ H}inst_AS_030_000_SYNC{ C}
+               :inst_DS_000_ENABLE{ C}    SM_AMIGA_6_{ C}
+     CIIN_0{ F}:           CIIN{ E}
+-----------------------------------------------------------------------------
+
+<Note> {.} : Indicates block location of signal
+
+
+Set_Reset_Summary
+~~~~~~~~~~~~~~~~~
+
+Block  A
+block level set pt   : GND
+block level reset pt : GND
+Equations :
+|     |     |Block|Block| Signal
+| Reg |Mode |Set  |Reset| Name
++-----+-----+-----+-----+------------------------
+|     |     |     |     | DS_030
+|     |     |     |     | AVEC
+|  *  |  S  | BS  | BR  | SM_AMIGA_1_
+|  *  |  S  | BS  | BR  | inst_AS_000_DMA
+|  *  |  S  | BS  | BR  | inst_LDS_000_INT
+|  *  |  S  | BS  | BR  | inst_UDS_000_INT
+|  *  |  S  | BS  | BR  | inst_DS_000_DMA
+|  *  |  S  | BS  | BR  | inst_CLK_030_H
+|  *  |  S  | BS  | BR  | CYCLE_DMA_1_
+|  *  |  S  | BS  | BR  | CYCLE_DMA_0_
+|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_6_
+|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_5_
+|  *  |  S  | BS  | BR  | inst_DTACK_D0
+|     |     |     |     | A_19_
+|     |     |     |     | A_16_
+|     |     |     |     | A_18_
+|     |     |     |     | FPU_SENSE
+|     |     |     |     | A_21_
+|     |     |     |     | A_20_
+
+
+Block  B
+block level set pt   : GND
+block level reset pt : GND
+Equations :
+|     |     |Block|Block| Signal
+| Reg |Mode |Set  |Reset| Name
++-----+-----+-----+-----+------------------------
+|  *  |  S  | BS  | BR  | IPL_030_2_
+|  *  |  S  | BS  | BR  | IPL_030_0_
+|  *  |  S  | BS  | BR  | IPL_030_1_
+|     |     |     |     | CLK_EXP
+|     |     |     |     | RESET
+|  *  |  S  | BS  | BR  | inst_AMIGA_BUS_ENABLE_DMA_HIGH
+|  *  |  S  | BS  | BR  | inst_AMIGA_BUS_ENABLE_DMA_LOW
+|  *  |  S  | BS  | BR  | inst_AS_000_INT
+|  *  |  S  | BS  | BR  | RN_IPL_030_0_
+|  *  |  S  | BS  | BR  | RN_IPL_030_1_
+|  *  |  S  | BS  | BR  | RN_IPL_030_2_
+|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_8_
+|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_7_
+|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_5_
+|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_1_
+|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_0_
+|  *  |  S  | BS  | BR  | IPL_D0_2_
+|  *  |  S  | BS  | BR  | IPL_D0_1_
+|  *  |  S  | BS  | BR  | IPL_D0_0_
+|     |     |     |     | A_29_
+|     |     |     |     | A_30_
+|     |     |     |     | A_31_
+
+
+Block  C
+block level set pt   : GND
+block level reset pt : GND
+Equations :
+|     |     |Block|Block| Signal
+| Reg |Mode |Set  |Reset| Name
++-----+-----+-----+-----+------------------------
+|     |     |     |     | AMIGA_BUS_ENABLE_LOW
+|  *  |  S  | BS  | BR  | SM_AMIGA_6_
+|  *  |  S  | BS  | BR  | inst_CLK_000_D1
+|  *  |  S  | BS  | BR  | inst_DS_000_ENABLE
+|  *  |  S  | BS  | BR  | inst_VPA_D
+|  *  |  S  | BS  | BR  | inst_AS_030_000_SYNC
+|     |     |     |     | N_210_i
+|     |     |     |     | BG_030
+|     |     |     |     | A_24_
+|     |     |     |     | A_25_
+|     |     |     |     | A_26_
+|     |     |     |     | A_27_
+|     |     |     |     | A_28_
+
+
+Block  D
+block level set pt   : GND
+block level reset pt : GND
+Equations :
+|     |     |Block|Block| Signal
+| Reg |Mode |Set  |Reset| Name
++-----+-----+-----+-----+------------------------
+|     |     |     |     | UDS_000
+|     |     |     |     | LDS_000
+|  *  |  S  | BS  | BR  | VMA
+|     |     |     |     | AMIGA_BUS_ENABLE_HIGH
+|  *  |  S  | BS  | BR  | BG_000
+|     |     |     |     | AMIGA_ADDR_ENABLE
+|  *  |  S  | BS  | BR  | inst_CLK_000_D0
+|  *  |  S  | BS  | BR  | cpu_est_2_
+|  *  |  S  | BS  | BR  | cpu_est_3_
+|  *  |  S  | BS  | BR  | cpu_est_1_
+|  *  |  S  | BS  | BR  | RN_VMA
+|  *  |  S  | BS  | BR  | cpu_est_0_
+|  *  |  S  | BS  | BR  | inst_CLK_000_NE_D0
+|  *  |  S  | BS  | BR  | inst_CLK_OUT_PRE_D
+|  *  |  S  | BS  | BR  | RN_BG_000
+|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_9_
+|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_4_
+|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_3_
+|     |     |     |     | BGACK_000
+|     |     |     |     | DTACK
+
+
+Block  E
+block level set pt   : GND
+block level reset pt : GND
+Equations :
+|     |     |Block|Block| Signal
+| Reg |Mode |Set  |Reset| Name
++-----+-----+-----+-----+------------------------
+|     |     |     |     | BERR
+|     |     |     |     | AS_000
+|     |     |     |     | AMIGA_BUS_DATA_DIR
+|     |     |     |     | CIIN
+|  *  |  S  | BS  | BR  | inst_BGACK_030_INT_D
+|  *  |  S  | BS  | BR  | inst_CLK_OUT_PRE_50
+|     |     |     |     | CIIN_0
+|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_4_
+|  *  |  S  | BS  | BR  | inst_CLK_OUT_EXP_INT
+
+
+Block  F
+block level set pt   : GND
+block level reset pt : GND
+Equations :
+|     |     |Block|Block| Signal
+| Reg |Mode |Set  |Reset| Name
++-----+-----+-----+-----+------------------------
+|  *  |  S  | BS  | BR  | inst_CLK_000_PE
+|  *  |  S  | BS  | BR  | SM_AMIGA_5_
+|  *  |  S  | BS  | BR  | SM_AMIGA_i_7_
+|  *  |  S  | BS  | BR  | SM_AMIGA_2_
+|  *  |  S  | BS  | BR  | SM_AMIGA_0_
+|  *  |  S  | BS  | BR  | SM_AMIGA_3_
+|  *  |  S  | BS  | BR  | SM_AMIGA_4_
+|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_2_
+|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_1_
+|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_6_
+|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_3_
+|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_2_
+|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_9_
+|     |     |     |     | A_17_
+|     |     |     |     | FC_1_
+|     |     |     |     | FC_0_
+|     |     |     |     | A1
+|     |     |     |     | IPL_1_
+
+
+Block  G
+block level set pt   : GND
+block level reset pt : GND
+Equations :
+|     |     |Block|Block| Signal
+| Reg |Mode |Set  |Reset| Name
++-----+-----+-----+-----+------------------------
+|  *  |  S  | BS  | BR  | RW
+|  *  |  S  | BS  | BR  | A0
+|     |     |     |     | SIZE_0_
+|     |     |     |     | E
+|  *  |  S  | BS  | BR  | CLK_DIV_OUT
+|  *  |  S  | BS  | BR  | inst_RESET_OUT
+|  *  |  S  | BS  | BR  | inst_CLK_000_NE
+|  *  |  S  | BS  | BR  | SIZE_DMA_1_
+|  *  |  S  | BS  | BR  | SIZE_DMA_0_
+|  *  |  S  | BS  | BR  | inst_CLK_OUT_PRE_25
+|  *  |  S  | BS  | BR  | RST_DLY_1_
+|  *  |  S  | BS  | BR  | RN_A0
+|  *  |  S  | BS  | BR  | RST_DLY_0_
+|  *  |  S  | BS  | BR  | RN_RW
+|  *  |  S  | BS  | BR  | RST_DLY_2_
+|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_7_
+|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_0_
+|  *  |  S  | BS  | BR  | CLK_000_P_SYNC_8_
+|     |     |     |     | IPL_2_
+|     |     |     |     | IPL_0_
+
+
+Block  H
+block level set pt   : GND
+block level reset pt : GND
+Equations :
+|     |     |Block|Block| Signal
+| Reg |Mode |Set  |Reset| Name
++-----+-----+-----+-----+------------------------
+|  *  |  S  | BS  | BR  | RW_000
+|     |     |     |     | AS_030
+|     |     |     |     | SIZE_1_
+|  *  |  S  | BS  | BR  | DSACK1
+|  *  |  S  | BS  | BR  | BGACK_030
+|     |     |     |     | FPU_CS
+|  *  |  S  | BS  | BR  | RN_BGACK_030
+|  *  |  S  | BS  | BR  | inst_nEXP_SPACE_D0reg
+|  *  |  S  | BS  | BR  | inst_AS_030_D0
+|  *  |  S  | BS  | BR  | RN_DSACK1
+|  *  |  S  | BS  | BR  | RN_RW_000
+|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_10_
+|  *  |  S  | BS  | BR  | CLK_000_N_SYNC_11_
+|     |     |     |     | A_23_
+|     |     |     |     | A_22_
+
+
+<Note> (S) means the macrocell is configured in synchronous mode
+       i.e. it uses the block-level set and reset pt.
+       (A) means the macrocell is configured in asynchronous mode
+       i.e. it can have its independant set or reset pt.
+       (BS) means the block-level set pt is selected.
+       (BR) means the block-level reset pt is selected.
+
+
+
+
+BLOCK_A_LOGIC_ARRAY_FANIN
+~~~~~~~~~~~~~~~~~~~~~~~~~
+CSM             Signal    Source        CSM             Signal    Source
+------------------------------------    ------------------------------------
+mx A0              A0        pin 69     mx A17            BERR        pin 41
+mx A1     SM_AMIGA_2_    mcell  F12     mx A18inst_UDS_000_INT     mcell  A5
+mx A2 inst_DS_000_DMA     mcell  A9     mx A19CLK_000_N_SYNC_4_    mcell  D11
+mx A3CLK_000_N_SYNC_5_    mcell  A14     mx A20         SIZE_1_        pin 79
+mx A4         CLK_030        pin 64     mx A21             RST        pin 86
+mx A5 inst_CLK_000_PE     mcell  F0     mx A22    CYCLE_DMA_1_     mcell  A2
+mx A6     SM_AMIGA_6_     mcell  C4     mx A23    RN_BGACK_030     mcell  H4
+mx A7             ...           ...     mx A24         LDS_000        pin 31
+mx A8         UDS_000        pin 32     mx A25  inst_CLK_030_H    mcell  A13
+mx A9           DTACK        pin 30     mx A26             ...           ...
+mx A10    CYCLE_DMA_0_     mcell  A6     mx A27 inst_CLK_000_NE     mcell  G9
+mx A11             ...           ...     mx A28          RW_000        pin 80
+mx A12inst_LDS_000_INT     mcell  A1     mx A29             ...           ...
+mx A13inst_nEXP_SPACE_D0reg     mcell  H5     mx A30     SM_AMIGA_1_     mcell  A8
+mx A14         SIZE_0_        pin 70     mx A31             ...           ...
+mx A15 inst_AS_000_DMA    mcell  A12     mx A32  inst_RESET_OUT     mcell  G5
+mx A16          AS_000        pin 42
+----------------------------------------------------------------------------
+
+
+BLOCK_B_LOGIC_ARRAY_FANIN
+~~~~~~~~~~~~~~~~~~~~~~~~~
+CSM             Signal    Source        CSM             Signal    Source
+------------------------------------    ------------------------------------
+mx B0             RST        pin 86     mx B17   RN_IPL_030_0_     mcell  B8
+mx B1            BERR        pin 41     mx B18             ...           ...
+mx B2CLK_000_P_SYNC_4_    mcell  E13     mx B19  inst_AS_030_D0    mcell  H13
+mx B3              A1        pin 60     mx B20    RN_BGACK_030     mcell  H4
+mx B4          IPL_2_        pin 68     mx B21          IPL_1_        pin 56
+mx B5CLK_000_P_SYNC_0_     mcell  B3     mx B22  inst_RESET_OUT     mcell  G5
+mx B6inst_AMIGA_BUS_ENABLE_DMA_LOW     mcell  B9     mx B23             ...           ...
+mx B7       IPL_D0_1_    mcell  B11     mx B24       IPL_D0_2_     mcell  B7
+mx B8inst_BGACK_030_INT_D     mcell  E8     mx B25 inst_CLK_000_D0     mcell  D9
+mx B9             ...           ...     mx B26   RN_IPL_030_1_    mcell  B12
+mx B10 inst_AS_000_INT    mcell  B13     mx B27       IPL_D0_0_    mcell  B15
+mx B11CLK_000_P_SYNC_6_     mcell  F6     mx B28inst_AMIGA_BUS_ENABLE_DMA_HIGH     mcell  B5
+mx B12CLK_000_N_SYNC_7_     mcell  G7     mx B29 inst_CLK_000_D1     mcell  C8
+mx B13             ...           ...     mx B30   RN_IPL_030_2_     mcell  B4
+mx B14     SM_AMIGA_5_     mcell  F4     mx B31             ...           ...
+mx B15inst_CLK_OUT_EXP_INT     mcell  E2     mx B32             ...           ...
+mx B16          IPL_0_        pin 67
+----------------------------------------------------------------------------
+
+
+BLOCK_C_LOGIC_ARRAY_FANIN
+~~~~~~~~~~~~~~~~~~~~~~~~~
+CSM             Signal    Source        CSM             Signal    Source
+------------------------------------    ------------------------------------
+mx C0    RN_BGACK_030     mcell  H4     mx C17     SM_AMIGA_2_    mcell  F12
+mx C1            BERR        pin 41     mx C18     SM_AMIGA_4_     mcell  F9
+mx C2   SM_AMIGA_i_7_     mcell  F8     mx C19  inst_AS_030_D0    mcell  H13
+mx C3     SM_AMIGA_1_     mcell  A8     mx C20             VPA        pin 36
+mx C4inst_DS_000_ENABLE    mcell  C12     mx C21             RST        pin 86
+mx C5 inst_CLK_000_PE     mcell  F0     mx C22             ...           ...
+mx C6           A_19_        pin 97     mx C23             ...           ...
+mx C7inst_AS_030_000_SYNC     mcell  C5     mx C24           FC_0_        pin 57
+mx C8           A_17_        pin 59     mx C25 inst_CLK_000_D0     mcell  D9
+mx C9     SM_AMIGA_3_     mcell  F5     mx C26           A_16_        pin 96
+mx C10     SM_AMIGA_5_     mcell  F4     mx C27             ...           ...
+mx C11              RW        pin 71     mx C28             ...           ...
+mx C12           FC_1_        pin 58     mx C29 inst_CLK_000_D1     mcell  C8
+mx C13inst_nEXP_SPACE_D0reg     mcell  H5     mx C30inst_BGACK_030_INT_D     mcell  E8
+mx C14     SM_AMIGA_6_     mcell  C4     mx C31           A_18_        pin 95
+mx C15     SM_AMIGA_0_     mcell  F1     mx C32             ...           ...
+mx C16inst_AMIGA_BUS_ENABLE_DMA_LOW     mcell  B9
+----------------------------------------------------------------------------
+
+
+BLOCK_D_LOGIC_ARRAY_FANIN
+~~~~~~~~~~~~~~~~~~~~~~~~~
+CSM             Signal    Source        CSM             Signal    Source
+------------------------------------    ------------------------------------
+mx D0             RST        pin 86     mx D17       RN_BG_000     mcell  D1
+mx D1      inst_VPA_D     mcell  C1     mx D18inst_UDS_000_INT     mcell  A5
+mx D2CLK_000_N_SYNC_3_    mcell  D15     mx D19  inst_AS_030_D0    mcell  H13
+mx D3      cpu_est_3_     mcell  D2     mx D20      cpu_est_0_    mcell  D10
+mx D4          BG_030        pin 21     mx D21      cpu_est_2_    mcell  D13
+mx D5inst_CLK_OUT_PRE_25     mcell  G6     mx D22  inst_RESET_OUT     mcell  G5
+mx D6CLK_000_N_SYNC_2_    mcell  F13     mx D23    RN_BGACK_030     mcell  H4
+mx D7 inst_CLK_000_D0     mcell  D9     mx D24inst_CLK_000_NE_D0    mcell  D14
+mx D8             ...           ...     mx D25 inst_CLK_000_PE     mcell  F0
+mx D9inst_LDS_000_INT     mcell  A1     mx D26          RN_VMA     mcell  D0
+mx D10CLK_000_N_SYNC_8_     mcell  B2     mx D27             ...           ...
+mx D11             ...           ...     mx D28inst_AMIGA_BUS_ENABLE_DMA_HIGH     mcell  B5
+mx D12 inst_CLK_000_NE     mcell  G9     mx D29             ...           ...
+mx D13inst_nEXP_SPACE_D0reg     mcell  H5     mx D30             ...           ...
+mx D14         CLK_000        pin 11     mx D31             ...           ...
+mx D15inst_DS_000_ENABLE    mcell  C12     mx D32   SM_AMIGA_i_7_     mcell  F8
+mx D16      cpu_est_1_     mcell  D6
+----------------------------------------------------------------------------
+
+
+BLOCK_E_LOGIC_ARRAY_FANIN
+~~~~~~~~~~~~~~~~~~~~~~~~~
+CSM             Signal    Source        CSM             Signal    Source
+------------------------------------    ------------------------------------
+mx E0             RST        pin 86     mx E17           A_26_        pin 17
+mx E1           FC_1_        pin 58     mx E18       BGACK_000        pin 28
+mx E2          CIIN_0     mcell  E9     mx E19CLK_000_P_SYNC_3_    mcell  F10
+mx E3           A_27_        pin 16     mx E20           A_22_        pin 84
+mx E4inst_nEXP_SPACE_D0reg     mcell  H5     mx E21          RW_000        pin 80
+mx E5           A_24_        pin 19     mx E22  inst_RESET_OUT     mcell  G5
+mx E6           A_19_        pin 97     mx E23    RN_BGACK_030     mcell  H4
+mx E7           A_28_        pin 15     mx E24           FC_0_        pin 57
+mx E8           A_23_        pin 85     mx E25           A_31_         pin 4
+mx E9           A_30_         pin 5     mx E26           A_16_        pin 96
+mx E10 inst_AS_000_INT    mcell  B13     mx E27           A_17_        pin 59
+mx E11       FPU_SENSE        pin 91     mx E28  inst_AS_030_D0    mcell  H13
+mx E12           A_25_        pin 18     mx E29           A_20_        pin 93
+mx E13           A_29_         pin 6     mx E30             ...           ...
+mx E14inst_CLK_OUT_PRE_50     mcell  E5     mx E31           A_18_        pin 95
+mx E15           A_21_        pin 94     mx E32          AS_030        pin 82
+mx E16          AS_000        pin 42
+----------------------------------------------------------------------------
+
+
+BLOCK_F_LOGIC_ARRAY_FANIN
+~~~~~~~~~~~~~~~~~~~~~~~~~
+CSM             Signal    Source        CSM             Signal    Source
+------------------------------------    ------------------------------------
+mx F0             RST        pin 86     mx F17inst_CLK_000_NE_D0    mcell  D14
+mx F1     SM_AMIGA_2_    mcell  F12     mx F18CLK_000_P_SYNC_8_    mcell  G15
+mx F2      cpu_est_0_    mcell  D10     mx F19             ...           ...
+mx F3     SM_AMIGA_1_     mcell  A8     mx F20CLK_000_P_SYNC_1_    mcell  B14
+mx F4      cpu_est_1_     mcell  D6     mx F21      cpu_est_2_    mcell  D13
+mx F5 inst_CLK_000_PE     mcell  F0     mx F22      inst_VPA_D     mcell  C1
+mx F6   inst_DTACK_D0     mcell  A3     mx F23             ...           ...
+mx F7CLK_000_P_SYNC_9_     mcell  F3     mx F24             ...           ...
+mx F8CLK_000_P_SYNC_2_    mcell  F14     mx F25            BERR        pin 41
+mx F9CLK_000_N_SYNC_0_    mcell  G11     mx F26          RN_VMA     mcell  D0
+mx F10 inst_CLK_000_NE     mcell  G9     mx F27     SM_AMIGA_3_     mcell  F5
+mx F11             ...           ...     mx F28             ...           ...
+mx F12CLK_000_P_SYNC_5_    mcell  B10     mx F29     SM_AMIGA_6_     mcell  C4
+mx F13         N_210_i     mcell  C9     mx F30     SM_AMIGA_0_     mcell  F1
+mx F14     SM_AMIGA_5_     mcell  F4     mx F31             ...           ...
+mx F15CLK_000_N_SYNC_1_     mcell  F2     mx F32     SM_AMIGA_4_     mcell  F9
+mx F16      cpu_est_3_     mcell  D2
+----------------------------------------------------------------------------
+
+
+BLOCK_G_LOGIC_ARRAY_FANIN
+~~~~~~~~~~~~~~~~~~~~~~~~~
+CSM             Signal    Source        CSM             Signal    Source
+------------------------------------    ------------------------------------
+mx G0         LDS_000        pin 31     mx G17           RN_RW     mcell  G0
+mx G1      cpu_est_2_    mcell  D13     mx G18             ...           ...
+mx G2CLK_000_P_SYNC_7_     mcell  B6     mx G19             ...           ...
+mx G3inst_CLK_OUT_PRE_50     mcell  E5     mx G20    RN_BGACK_030     mcell  H4
+mx G4inst_nEXP_SPACE_D0reg     mcell  H5     mx G21             RST        pin 86
+mx G5inst_CLK_OUT_PRE_25     mcell  G6     mx G22      RST_DLY_1_    mcell  G10
+mx G6          RW_000        pin 80     mx G23     SIZE_DMA_0_     mcell  G2
+mx G7CLK_000_N_SYNC_11_     mcell  H6     mx G24      RST_DLY_2_     mcell  G3
+mx G8         UDS_000        pin 32     mx G25 inst_CLK_000_D0     mcell  D9
+mx G9inst_CLK_OUT_PRE_D     mcell  D3     mx G26             ...           ...
+mx G10      RST_DLY_0_    mcell  G14     mx G27 inst_CLK_000_NE     mcell  G9
+mx G11             ...           ...     mx G28      cpu_est_3_     mcell  D2
+mx G12     SIZE_DMA_1_    mcell  G13     mx G29 inst_CLK_000_D1     mcell  C8
+mx G13           RN_A0     mcell  G8     mx G30      cpu_est_1_     mcell  D6
+mx G14CLK_000_N_SYNC_6_    mcell  A10     mx G31             ...           ...
+mx G15             ...           ...     mx G32  inst_RESET_OUT     mcell  G5
+mx G16inst_BGACK_030_INT_D     mcell  E8
+----------------------------------------------------------------------------
+
+
+BLOCK_H_LOGIC_ARRAY_FANIN
+~~~~~~~~~~~~~~~~~~~~~~~~~
+CSM             Signal    Source        CSM             Signal    Source
+------------------------------------    ------------------------------------
+mx H0             RST        pin 86     mx H17           FC_0_        pin 57
+mx H1            BERR        pin 41     mx H18     SM_AMIGA_1_     mcell  A8
+mx H2   SM_AMIGA_i_7_     mcell  F8     mx H19       FPU_SENSE        pin 91
+mx H3  inst_RESET_OUT     mcell  G5     mx H20    RN_BGACK_030     mcell  H4
+mx H4           A_18_        pin 95     mx H21      nEXP_SPACE        pin 14
+mx H5       RN_DSACK1     mcell  H9     mx H22inst_CLK_OUT_PRE_D     mcell  D3
+mx H6           A_19_        pin 97     mx H23     SIZE_DMA_0_     mcell  G2
+mx H7  inst_AS_030_D0    mcell  H13     mx H24             ...           ...
+mx H8CLK_000_N_SYNC_9_     mcell  D7     mx H25     SIZE_DMA_1_    mcell  G13
+mx H9          AS_030        pin 82     mx H26           A_16_        pin 96
+mx H10     SM_AMIGA_0_     mcell  F1     mx H27           A_17_        pin 59
+mx H11              RW        pin 71     mx H28         CLK_030        pin 64
+mx H12           FC_1_        pin 58     mx H29     SM_AMIGA_5_     mcell  F4
+mx H13inst_nEXP_SPACE_D0reg     mcell  H5     mx H30       RN_RW_000     mcell  H0
+mx H14CLK_000_N_SYNC_10_     mcell  H2     mx H31 inst_CLK_000_PE     mcell  F0
+mx H15 inst_AS_000_DMA    mcell  A12     mx H32       BGACK_000        pin 28
+mx H16          AS_000        pin 42
+----------------------------------------------------------------------------
+
+<Note> CSM indicates the mux inputs from the Central Switch Matrix.
+<Note> Source indicates where the signal comes from (pin or macrocell). 
+
+
+
+
+PostFit_Equations
+~~~~~~~~~~~~~~~~~
+
+
+ P-Terms   Fan-in  Fan-out  Type  Name (attributes)
+---------  ------  -------  ----  -----------------
+   1          2        1    Pin   SIZE_1_ 
+   1          2        1    Pin   SIZE_1_.OE 
+   1          2        1    Pin   AS_030- 
+   1          3        1    Pin   AS_030.OE 
+   1          2        1    Pin   AS_000- 
+   1          2        1    Pin   AS_000.OE 
+   1          2        1    Pin   DS_030- 
+   1          3        1    Pin   DS_030.OE 
+   1          2        1    Pin   UDS_000- 
+   1          2        1    Pin   UDS_000.OE 
+   1          2        1    Pin   LDS_000- 
+   1          2        1    Pin   LDS_000.OE 
+   0          0        1    Pin   BERR 
+   1          9        1    Pin   BERR.OE 
+   1          1        1    Pin   CLK_EXP 
+   1          9        1    Pin   FPU_CS- 
+   1          0        1    Pin   AVEC 
+   2          3        1    Pin   E 
+   0          0        1    Pin   RESET 
+   1          1        1    Pin   RESET.OE 
+   0          0        1    Pin   AMIGA_ADDR_ENABLE 
+   2          4        1    Pin   AMIGA_BUS_DATA_DIR 
+   1          2        1    Pin   SIZE_0_ 
+   1          2        1    Pin   SIZE_0_.OE 
+   1          2        1    Pin   AMIGA_BUS_ENABLE_LOW- 
+   2          3        1    Pin   AMIGA_BUS_ENABLE_HIGH 
+   1         13        1    Pin   CIIN 
+   1          1        1    Pin   CIIN.OE 
+  10          8        1    Pin   IPL_030_2_.D- 
+   1          1        1    Pin   IPL_030_2_.C 
+  10          8        1    Pin   IPL_030_1_.D- 
+   1          1        1    Pin   IPL_030_1_.C 
+  10          8        1    Pin   IPL_030_0_.D- 
+   1          1        1    Pin   IPL_030_0_.C 
+   1          2        1    Pin   RW_000.OE 
+   3          7        1    Pin   RW_000.D- 
+   1          1        1    Pin   RW_000.C 
+   1          3        1    Pin   A0.OE 
+   3          5        1    Pin   A0.D 
+   1          1        1    Pin   A0.C 
+   2          6        1    Pin   BG_000.D- 
+   1          1        1    Pin   BG_000.C 
+   3          5        1    Pin   BGACK_030.D 
+   1          1        1    Pin   BGACK_030.C 
+   1          1        1    Pin   CLK_DIV_OUT.D 
+   1          1        1    Pin   CLK_DIV_OUT.C 
+   1          1        1    Pin   DSACK1.OE 
+   4          9        1    Pin   DSACK1.D- 
+   1          1        1    Pin   DSACK1.C 
+   3          9        1    Pin   VMA.T 
+   1          1        1    Pin   VMA.C 
+   1          2        1    Pin   RW.OE 
+   2          5        1    Pin   RW.D- 
+   1          1        1    Pin   RW.C 
+   2          2        1    Node  cpu_est_0_.D 
+   1          1        1    Node  cpu_est_0_.C 
+   3          4        1    Node  cpu_est_1_.D 
+   1          1        1    Node  cpu_est_1_.C 
+   4          4        1    Node  cpu_est_2_.D 
+   1          1        1    Node  cpu_est_2_.C 
+   3          5        1    Node  cpu_est_3_.D 
+   1          1        1    Node  cpu_est_3_.C 
+   2          5        1    Node  inst_AS_000_INT.D- 
+   1          1        1    Node  inst_AS_000_INT.C 
+   3          6        1    Node  SM_AMIGA_5_.D 
+   1          1        1    Node  SM_AMIGA_5_.C 
+   2          5        1    Node  inst_AMIGA_BUS_ENABLE_DMA_LOW.D- 
+   1          1        1    Node  inst_AMIGA_BUS_ENABLE_DMA_LOW.C 
+   1          2        1    Node  inst_AS_030_D0.D- 
+   1          1        1    Node  inst_AS_030_D0.C 
+   1          2        1    Node  inst_nEXP_SPACE_D0reg.D- 
+   1          1        1    Node  inst_nEXP_SPACE_D0reg.C 
+   7         14        1    Node  inst_AS_030_000_SYNC.D- 
+   1          1        1    Node  inst_AS_030_000_SYNC.C 
+   1          2        1    Node  inst_BGACK_030_INT_D.D- 
+   1          1        1    Node  inst_BGACK_030_INT_D.C 
+   7          9        1    Node  inst_AS_000_DMA.D 
+   1          1        1    Node  inst_AS_000_DMA.C 
+   9         12        1    Node  inst_DS_000_DMA.D 
+   1          1        1    Node  inst_DS_000_DMA.C 
+   2          5        1    Node  CYCLE_DMA_0_.D 
+   1          1        1    Node  CYCLE_DMA_0_.C 
+   3          6        1    Node  CYCLE_DMA_1_.D 
+   1          1        1    Node  CYCLE_DMA_1_.C 
+   3          6        1    Node  SIZE_DMA_0_.D- 
+   1          1        1    Node  SIZE_DMA_0_.C 
+   3          6        1    Node  SIZE_DMA_1_.D 
+   1          1        1    Node  SIZE_DMA_1_.C 
+   1          2        1    Node  inst_VPA_D.D- 
+   1          1        1    Node  inst_VPA_D.C 
+   2          4        1    Node  inst_UDS_000_INT.D- 
+   1          1        1    Node  inst_UDS_000_INT.C 
+   3          6        1    Node  inst_LDS_000_INT.D 
+   1          1        1    Node  inst_LDS_000_INT.C 
+   1          1        1    Node  inst_CLK_OUT_PRE_D.D 
+   1          1        1    Node  inst_CLK_OUT_PRE_D.C 
+   1          2        1    Node  inst_DTACK_D0.D- 
+   1          1        1    Node  inst_DTACK_D0.C 
+   2          6        1    Node  inst_RESET_OUT.D 
+   1          1        1    Node  inst_RESET_OUT.C 
+   1          1        1    Node  inst_CLK_OUT_PRE_50.D 
+   1          1        1    Node  inst_CLK_OUT_PRE_50.C 
+   4         11        1    Node  N_210_i- 
+   2          2        1    Node  inst_CLK_OUT_PRE_25.D 
+   1          1        1    Node  inst_CLK_OUT_PRE_25.C 
+   1          1        1    Node  inst_CLK_000_D1.D 
+   1          1        1    Node  inst_CLK_000_D1.C 
+   1          1        1    Node  inst_CLK_000_D0.D 
+   1          1        1    Node  inst_CLK_000_D0.C 
+   1          1        1    Node  inst_CLK_000_PE.D 
+   1          1        1    Node  inst_CLK_000_PE.C 
+   1          1        1    Node  inst_CLK_OUT_EXP_INT.D 
+   1          1        1    Node  inst_CLK_OUT_EXP_INT.C 
+   1          1        1    Node  CLK_000_P_SYNC_9_.D 
+   1          1        1    Node  CLK_000_P_SYNC_9_.C 
+   1          1        1    Node  inst_CLK_000_NE.D 
+   1          1        1    Node  inst_CLK_000_NE.C 
+   1          1        1    Node  CLK_000_N_SYNC_11_.D 
+   1          1        1    Node  CLK_000_N_SYNC_11_.C 
+   1          2        1    Node  IPL_D0_0_.D- 
+   1          1        1    Node  IPL_D0_0_.C 
+   1          2        1    Node  IPL_D0_1_.D- 
+   1          1        1    Node  IPL_D0_1_.C 
+   1          2        1    Node  IPL_D0_2_.D- 
+   1          1        1    Node  IPL_D0_2_.C 
+   1          1        1    Node  inst_CLK_000_NE_D0.D 
+   1          1        1    Node  inst_CLK_000_NE_D0.C 
+   2          6        1    Node  SM_AMIGA_0_.D 
+   1          1        1    Node  SM_AMIGA_0_.C 
+   2          5        1    Node  inst_AMIGA_BUS_ENABLE_DMA_HIGH.D- 
+   1          1        1    Node  inst_AMIGA_BUS_ENABLE_DMA_HIGH.C 
+   3          6        1    Node  SM_AMIGA_4_.D 
+   1          1        1    Node  SM_AMIGA_4_.C 
+   5         11        1    Node  inst_DS_000_ENABLE.D 
+   1          1        1    Node  inst_DS_000_ENABLE.C 
+   3          5        1    Node  RST_DLY_0_.D 
+   1          1        1    Node  RST_DLY_0_.C 
+   4          5        1    Node  RST_DLY_1_.D 
+   1          1        1    Node  RST_DLY_1_.C 
+   2          5        1    Node  RST_DLY_2_.D 
+   1          1        1    Node  RST_DLY_2_.C 
+   1          2        1    Node  CLK_000_P_SYNC_0_.D 
+   1          1        1    Node  CLK_000_P_SYNC_0_.C 
+   1          1        1    Node  CLK_000_P_SYNC_1_.D 
+   1          1        1    Node  CLK_000_P_SYNC_1_.C 
+   1          1        1    Node  CLK_000_P_SYNC_2_.D 
+   1          1        1    Node  CLK_000_P_SYNC_2_.C 
+   1          1        1    Node  CLK_000_P_SYNC_3_.D 
+   1          1        1    Node  CLK_000_P_SYNC_3_.C 
+   1          1        1    Node  CLK_000_P_SYNC_4_.D 
+   1          1        1    Node  CLK_000_P_SYNC_4_.C 
+   1          1        1    Node  CLK_000_P_SYNC_5_.D 
+   1          1        1    Node  CLK_000_P_SYNC_5_.C 
+   1          1        1    Node  CLK_000_P_SYNC_6_.D 
+   1          1        1    Node  CLK_000_P_SYNC_6_.C 
+   1          1        1    Node  CLK_000_P_SYNC_7_.D 
+   1          1        1    Node  CLK_000_P_SYNC_7_.C 
+   1          1        1    Node  CLK_000_P_SYNC_8_.D 
+   1          1        1    Node  CLK_000_P_SYNC_8_.C 
+   1          2        1    Node  CLK_000_N_SYNC_0_.D 
+   1          1        1    Node  CLK_000_N_SYNC_0_.C 
+   1          1        1    Node  CLK_000_N_SYNC_1_.D 
+   1          1        1    Node  CLK_000_N_SYNC_1_.C 
+   1          1        1    Node  CLK_000_N_SYNC_2_.D 
+   1          1        1    Node  CLK_000_N_SYNC_2_.C 
+   1          1        1    Node  CLK_000_N_SYNC_3_.D 
+   1          1        1    Node  CLK_000_N_SYNC_3_.C 
+   1          1        1    Node  CLK_000_N_SYNC_4_.D 
+   1          1        1    Node  CLK_000_N_SYNC_4_.C 
+   1          1        1    Node  CLK_000_N_SYNC_5_.D 
+   1          1        1    Node  CLK_000_N_SYNC_5_.C 
+   1          1        1    Node  CLK_000_N_SYNC_6_.D 
+   1          1        1    Node  CLK_000_N_SYNC_6_.C 
+   1          1        1    Node  CLK_000_N_SYNC_7_.D 
+   1          1        1    Node  CLK_000_N_SYNC_7_.C 
+   1          1        1    Node  CLK_000_N_SYNC_8_.D 
+   1          1        1    Node  CLK_000_N_SYNC_8_.C 
+   1          1        1    Node  CLK_000_N_SYNC_9_.D 
+   1          1        1    Node  CLK_000_N_SYNC_9_.C 
+   1          1        1    Node  CLK_000_N_SYNC_10_.D 
+   1          1        1    Node  CLK_000_N_SYNC_10_.C 
+   3          9        1    Node  SM_AMIGA_6_.D 
+   1          1        1    Node  SM_AMIGA_6_.C 
+   8         10        1    Node  inst_CLK_030_H.D 
+   1          1        1    Node  inst_CLK_030_H.C 
+   3          6        1    Node  SM_AMIGA_1_.D 
+   1          1        1    Node  SM_AMIGA_1_.C 
+   5         13        1    Node  SM_AMIGA_3_.T 
+   1          1        1    Node  SM_AMIGA_3_.C 
+   4         13        1    Node  SM_AMIGA_2_.D 
+   1          1        1    Node  SM_AMIGA_2_.C 
+  14         20        1    Node  SM_AMIGA_i_7_.D 
+   1          1        1    Node  SM_AMIGA_i_7_.C 
+   2         14        1    Node  CIIN_0 
+=========
+ 327                 P-Term Total: 327
+                       Total Pins: 61
+                      Total Nodes: 71
+            Average P-Term/Output: 2
+
+
+Equations:
+
+SIZE_1_ = (!SIZE_DMA_0_.Q & SIZE_DMA_1_.Q);
+
+SIZE_1_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
+
+!AS_030 = (!inst_AS_000_DMA.Q & !AS_000.PIN);
+
+AS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q);
+
+!AS_000 = (!inst_AS_000_INT.Q & !AS_030.PIN);
+
+AS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
+
+!DS_030 = (!inst_DS_000_DMA.Q & !AS_000.PIN);
+
+DS_030.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q);
+
+!UDS_000 = (!inst_UDS_000_INT.Q & inst_DS_000_ENABLE.Q);
+
+UDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
+
+!LDS_000 = (!inst_LDS_000_INT.Q & inst_DS_000_ENABLE.Q);
+
+LDS_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
+
+BERR = (0);
+
+BERR.OE = (FC_1_ & BGACK_000 & FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
+
+CLK_EXP = (!inst_CLK_OUT_EXP_INT.Q);
+
+!FPU_CS = (FC_1_ & BGACK_000 & !FPU_SENSE & !A_19_ & !A_18_ & A_17_ & !A_16_ & FC_0_ & !AS_030.PIN);
+
+AVEC = (1);
+
+E = (!cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q
+     # cpu_est_1_.Q & cpu_est_2_.Q & !cpu_est_3_.Q);
+
+RESET = (0);
+
+RESET.OE = (!inst_RESET_OUT.Q);
+
+AMIGA_ADDR_ENABLE = (0);
+
+AMIGA_BUS_DATA_DIR = (BGACK_030.Q & !RW_000.PIN
+     # !BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & !AS_000.PIN & RW_000.PIN);
+
+SIZE_0_ = (SIZE_DMA_0_.Q & !SIZE_DMA_1_.Q);
+
+SIZE_0_.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q);
+
+!AMIGA_BUS_ENABLE_LOW = (!BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q);
+
+AMIGA_BUS_ENABLE_HIGH = (!BGACK_030.Q & inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q
+     # BGACK_030.Q & !SM_AMIGA_i_7_.Q);
+
+CIIN = (!A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
+
+CIIN.OE = (CIIN_0);
+
+!IPL_030_2_.D = (!IPL_2_ & RST & !IPL_030_2_.Q
+     # RST & !IPL_D0_2_.Q & !IPL_030_2_.Q
+     # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_2_.Q
+     # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_2_.Q
+     # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_2_.Q
+     # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_2_.Q
+     # !IPL_2_ & RST & IPL_1_ & IPL_0_ & IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
+     # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
+     # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
+     # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
+
+IPL_030_2_.C = (CLK_OSZI);
+
+!IPL_030_1_.D = (RST & !IPL_1_ & !IPL_030_1_.Q
+     # RST & !IPL_D0_1_.Q & !IPL_030_1_.Q
+     # RST & !IPL_0_ & IPL_D0_0_.Q & !IPL_030_1_.Q
+     # RST & IPL_0_ & !IPL_D0_0_.Q & !IPL_030_1_.Q
+     # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_1_.Q
+     # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_1_.Q
+     # IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
+     # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
+     # !IPL_2_ & RST & !IPL_1_ & IPL_0_ & IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q
+     # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
+
+IPL_030_1_.C = (CLK_OSZI);
+
+!IPL_030_0_.D = (RST & !IPL_0_ & !IPL_030_0_.Q
+     # RST & !IPL_D0_0_.Q & !IPL_030_0_.Q
+     # RST & !IPL_1_ & IPL_D0_1_.Q & !IPL_030_0_.Q
+     # RST & IPL_1_ & !IPL_D0_1_.Q & !IPL_030_0_.Q
+     # !IPL_2_ & RST & IPL_D0_2_.Q & !IPL_030_0_.Q
+     # IPL_2_ & RST & !IPL_D0_2_.Q & !IPL_030_0_.Q
+     # IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & IPL_D0_2_.Q
+     # IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & IPL_D0_2_.Q
+     # !IPL_2_ & RST & IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & IPL_D0_1_.Q & !IPL_D0_2_.Q
+     # !IPL_2_ & RST & !IPL_1_ & !IPL_0_ & !IPL_D0_0_.Q & !IPL_D0_1_.Q & !IPL_D0_2_.Q);
+
+IPL_030_0_.C = (CLK_OSZI);
+
+RW_000.OE = (BGACK_030.Q & inst_RESET_OUT.Q);
+
+!RW_000.D = (RST & SM_AMIGA_5_.Q & !RW.PIN
+     # RST & !SM_AMIGA_5_.Q & !inst_CLK_000_PE.Q & !RW_000.Q & SM_AMIGA_i_7_.Q
+     # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !RW_000.Q & SM_AMIGA_i_7_.Q);
+
+RW_000.C = (CLK_OSZI);
+
+A0.OE = (!BGACK_030.Q & !inst_nEXP_SPACE_D0reg.Q & inst_RESET_OUT.Q);
+
+A0.D = (!RST
+     # !BGACK_030.Q & UDS_000.PIN
+     # BGACK_030.Q & inst_BGACK_030_INT_D.Q & A0.Q);
+
+A0.C = (CLK_OSZI);
+
+!BG_000.D = (!BG_030 & RST & !BG_000.Q
+     # !BG_030 & RST & inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_CLK_000_D0.Q);
+
+BG_000.C = (CLK_OSZI);
+
+BGACK_030.D = (!RST
+     # BGACK_000 & BGACK_030.Q
+     # BGACK_000 & inst_CLK_000_PE.Q & AS_000.PIN);
+
+BGACK_030.C = (CLK_OSZI);
+
+CLK_DIV_OUT.D = (inst_CLK_OUT_PRE_D.Q);
+
+CLK_DIV_OUT.C = (CLK_OSZI);
+
+DSACK1.OE = (inst_nEXP_SPACE_D0reg.Q);
+
+!DSACK1.D = (RST & CLK_000_N_SYNC_10_.Q & SM_AMIGA_1_.Q
+     # !CLK_030 & RST & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
+     # RST & inst_CLK_OUT_PRE_D.Q & CLK_000_N_SYNC_9_.Q & SM_AMIGA_1_.Q
+     # RST & !inst_AS_030_D0.Q & !DSACK1.Q & BERR.PIN);
+
+DSACK1.C = (CLK_OSZI);
+
+VMA.T = (!RST & !VMA.Q
+     # !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & inst_CLK_000_PE.Q
+     # RST & VMA.Q & cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & !cpu_est_3_.Q & !inst_VPA_D.Q & inst_CLK_000_NE.Q);
+
+VMA.C = (CLK_OSZI);
+
+RW.OE = (!BGACK_030.Q & inst_RESET_OUT.Q);
+
+!RW.D = (RST & !BGACK_030.Q & !RW_000.PIN
+     # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !RW.Q);
+
+RW.C = (CLK_OSZI);
+
+cpu_est_0_.D = (!cpu_est_0_.Q & inst_CLK_000_NE_D0.Q
+     # cpu_est_0_.Q & !inst_CLK_000_NE_D0.Q);
+
+cpu_est_0_.C = (CLK_OSZI);
+
+cpu_est_1_.D = (!cpu_est_0_.Q & cpu_est_1_.Q
+     # cpu_est_1_.Q & !inst_CLK_000_NE_D0.Q
+     # cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_3_.Q & inst_CLK_000_NE_D0.Q);
+
+cpu_est_1_.C = (CLK_OSZI);
+
+cpu_est_2_.D = (!cpu_est_0_.Q & cpu_est_2_.Q
+     # !cpu_est_1_.Q & cpu_est_2_.Q
+     # cpu_est_2_.Q & !inst_CLK_000_NE_D0.Q
+     # cpu_est_0_.Q & cpu_est_1_.Q & !cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
+
+cpu_est_2_.C = (CLK_OSZI);
+
+cpu_est_3_.D = (!cpu_est_0_.Q & cpu_est_3_.Q
+     # cpu_est_3_.Q & !inst_CLK_000_NE_D0.Q
+     # cpu_est_0_.Q & cpu_est_1_.Q & cpu_est_2_.Q & inst_CLK_000_NE_D0.Q);
+
+cpu_est_3_.C = (CLK_OSZI);
+
+!inst_AS_000_INT.D = (RST & SM_AMIGA_5_.Q
+     # RST & !inst_AS_000_INT.Q & !inst_AS_030_D0.Q & BERR.PIN);
+
+inst_AS_000_INT.C = (CLK_OSZI);
+
+SM_AMIGA_5_.D = (RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & SM_AMIGA_6_.Q
+     # RST & SM_AMIGA_5_.Q & !inst_CLK_000_NE.Q & BERR.PIN
+     # RST & SM_AMIGA_5_.Q & SM_AMIGA_6_.Q & BERR.PIN);
+
+SM_AMIGA_5_.C = (CLK_OSZI);
+
+!inst_AMIGA_BUS_ENABLE_DMA_LOW.D = (A1 & RST & !BGACK_030.Q
+     # RST & BGACK_030.Q & !inst_AMIGA_BUS_ENABLE_DMA_LOW.Q & inst_BGACK_030_INT_D.Q);
+
+inst_AMIGA_BUS_ENABLE_DMA_LOW.C = (CLK_OSZI);
+
+!inst_AS_030_D0.D = (RST & !AS_030.PIN);
+
+inst_AS_030_D0.C = (CLK_OSZI);
+
+!inst_nEXP_SPACE_D0reg.D = (!nEXP_SPACE & RST);
+
+inst_nEXP_SPACE_D0reg.C = (CLK_OSZI);
+
+!inst_AS_030_000_SYNC.D = (RST & !inst_AS_030_D0.Q & !inst_AS_030_000_SYNC.Q & BERR.PIN
+     # !FC_1_ & RST & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
+     # RST & A_19_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
+     # RST & A_18_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
+     # RST & !A_17_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
+     # RST & A_16_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN
+     # RST & !FC_0_ & BGACK_030.Q & !inst_AS_030_D0.Q & inst_nEXP_SPACE_D0reg.Q & inst_BGACK_030_INT_D.Q & !SM_AMIGA_i_7_.Q & BERR.PIN);
+
+inst_AS_030_000_SYNC.C = (CLK_OSZI);
+
+!inst_BGACK_030_INT_D.D = (RST & !BGACK_030.Q);
+
+inst_BGACK_030_INT_D.C = (CLK_OSZI);
+
+inst_AS_000_DMA.D = (!RST
+     # BGACK_030.Q
+     # AS_000.PIN
+     # !CLK_030 & inst_AS_000_DMA.Q
+     # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
+     # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
+     # UDS_000.PIN & LDS_000.PIN);
+
+inst_AS_000_DMA.C = (CLK_OSZI);
+
+inst_DS_000_DMA.D = (!RST
+     # BGACK_030.Q
+     # AS_000.PIN
+     # CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q
+     # !CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q
+     # UDS_000.PIN & LDS_000.PIN
+     # !CLK_030 & inst_DS_000_DMA.Q & !RW_000.PIN
+     # inst_DS_000_DMA.Q & !inst_CLK_030_H.Q & !RW_000.PIN
+     # CLK_030 & inst_AS_000_DMA.Q & inst_CLK_030_H.Q & !RW_000.PIN);
+
+inst_DS_000_DMA.C = (CLK_OSZI);
+
+CYCLE_DMA_0_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & inst_CLK_000_PE.Q & !AS_000.PIN
+     # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN);
+
+CYCLE_DMA_0_.C = (CLK_OSZI);
+
+CYCLE_DMA_1_.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN
+     # RST & !BGACK_030.Q & CYCLE_DMA_1_.Q & !inst_CLK_000_PE.Q & !AS_000.PIN
+     # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_000_PE.Q & !AS_000.PIN);
+
+CYCLE_DMA_1_.C = (CLK_OSZI);
+
+!SIZE_DMA_0_.D = (RST & BGACK_030.Q & !inst_BGACK_030_INT_D.Q
+     # RST & BGACK_030.Q & !SIZE_DMA_0_.Q
+     # RST & !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
+
+SIZE_DMA_0_.C = (CLK_OSZI);
+
+SIZE_DMA_1_.D = (!RST
+     # BGACK_030.Q & inst_BGACK_030_INT_D.Q & SIZE_DMA_1_.Q
+     # !BGACK_030.Q & !UDS_000.PIN & !LDS_000.PIN);
+
+SIZE_DMA_1_.C = (CLK_OSZI);
+
+!inst_VPA_D.D = (!VPA & RST);
+
+inst_VPA_D.C = (CLK_OSZI);
+
+!inst_UDS_000_INT.D = (RST & !inst_UDS_000_INT.Q & !SM_AMIGA_6_.Q
+     # RST & SM_AMIGA_6_.Q & !A0.PIN);
+
+inst_UDS_000_INT.C = (CLK_OSZI);
+
+inst_LDS_000_INT.D = (!RST
+     # inst_LDS_000_INT.Q & !SM_AMIGA_6_.Q
+     # SM_AMIGA_6_.Q & SIZE_0_.PIN & !SIZE_1_.PIN & !A0.PIN);
+
+inst_LDS_000_INT.C = (CLK_OSZI);
+
+inst_CLK_OUT_PRE_D.D = (inst_CLK_OUT_PRE_25.Q);
+
+inst_CLK_OUT_PRE_D.C = (CLK_OSZI);
+
+!inst_DTACK_D0.D = (!DTACK & RST);
+
+inst_DTACK_D0.C = (CLK_OSZI);
+
+inst_RESET_OUT.D = (RST & inst_RESET_OUT.Q
+     # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q);
+
+inst_RESET_OUT.C = (CLK_OSZI);
+
+inst_CLK_OUT_PRE_50.D = (!inst_CLK_OUT_PRE_50.Q);
+
+inst_CLK_OUT_PRE_50.C = (CLK_OSZI);
+
+!N_210_i = (!SM_AMIGA_5_.Q & !inst_nEXP_SPACE_D0reg.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
+     # !SM_AMIGA_5_.Q & inst_AS_030_000_SYNC.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
+     # !SM_AMIGA_5_.Q & !inst_CLK_000_D1.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
+     # !SM_AMIGA_5_.Q & inst_CLK_000_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q);
+
+inst_CLK_OUT_PRE_25.D = (!inst_CLK_OUT_PRE_50.Q & inst_CLK_OUT_PRE_25.Q
+     # inst_CLK_OUT_PRE_50.Q & !inst_CLK_OUT_PRE_25.Q);
+
+inst_CLK_OUT_PRE_25.C = (CLK_OSZI);
+
+inst_CLK_000_D1.D = (inst_CLK_000_D0.Q);
+
+inst_CLK_000_D1.C = (CLK_OSZI);
+
+inst_CLK_000_D0.D = (CLK_000);
+
+inst_CLK_000_D0.C = (CLK_OSZI);
+
+inst_CLK_000_PE.D = (CLK_000_P_SYNC_9_.Q);
+
+inst_CLK_000_PE.C = (CLK_OSZI);
+
+inst_CLK_OUT_EXP_INT.D = (inst_CLK_OUT_PRE_50.Q);
+
+inst_CLK_OUT_EXP_INT.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_9_.D = (CLK_000_P_SYNC_8_.Q);
+
+CLK_000_P_SYNC_9_.C = (CLK_OSZI);
+
+inst_CLK_000_NE.D = (CLK_000_N_SYNC_11_.Q);
+
+inst_CLK_000_NE.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_11_.D = (CLK_000_N_SYNC_10_.Q);
+
+CLK_000_N_SYNC_11_.C = (CLK_OSZI);
+
+!IPL_D0_0_.D = (RST & !IPL_0_);
+
+IPL_D0_0_.C = (CLK_OSZI);
+
+!IPL_D0_1_.D = (RST & !IPL_1_);
+
+IPL_D0_1_.C = (CLK_OSZI);
+
+!IPL_D0_2_.D = (!IPL_2_ & RST);
+
+IPL_D0_2_.C = (CLK_OSZI);
+
+inst_CLK_000_NE_D0.D = (inst_CLK_000_NE.Q);
+
+inst_CLK_000_NE_D0.C = (CLK_OSZI);
+
+SM_AMIGA_0_.D = (RST & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & SM_AMIGA_1_.Q
+     # RST & !inst_CLK_000_PE.Q & SM_AMIGA_0_.Q & BERR.PIN);
+
+SM_AMIGA_0_.C = (CLK_OSZI);
+
+!inst_AMIGA_BUS_ENABLE_DMA_HIGH.D = (!A1 & RST & !BGACK_030.Q
+     # RST & BGACK_030.Q & inst_BGACK_030_INT_D.Q & !inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q);
+
+inst_AMIGA_BUS_ENABLE_DMA_HIGH.C = (CLK_OSZI);
+
+SM_AMIGA_4_.D = (RST & SM_AMIGA_5_.Q & inst_CLK_000_NE.Q
+     # RST & SM_AMIGA_5_.Q & SM_AMIGA_4_.Q
+     # RST & !inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & BERR.PIN);
+
+SM_AMIGA_4_.C = (CLK_OSZI);
+
+inst_DS_000_ENABLE.D = (RST & !inst_AS_030_D0.Q & inst_DS_000_ENABLE.Q & BERR.PIN
+     # RST & !SM_AMIGA_5_.Q & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q
+     # RST & !SM_AMIGA_5_.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q
+     # RST & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN
+     # RST & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & SM_AMIGA_i_7_.Q & RW.PIN);
+
+inst_DS_000_ENABLE.C = (CLK_OSZI);
+
+RST_DLY_0_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_0_.Q
+     # RST & inst_CLK_000_NE.Q & !RST_DLY_0_.Q
+     # RST & RST_DLY_0_.Q & RST_DLY_1_.Q & RST_DLY_2_.Q);
+
+RST_DLY_0_.C = (CLK_OSZI);
+
+RST_DLY_1_.D = (RST & !inst_CLK_000_NE.Q & RST_DLY_1_.Q
+     # RST & !RST_DLY_0_.Q & RST_DLY_1_.Q
+     # RST & RST_DLY_1_.Q & RST_DLY_2_.Q
+     # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & !RST_DLY_1_.Q);
+
+RST_DLY_1_.C = (CLK_OSZI);
+
+RST_DLY_2_.D = (RST & RST_DLY_2_.Q
+     # RST & inst_CLK_000_NE.Q & RST_DLY_0_.Q & RST_DLY_1_.Q);
+
+RST_DLY_2_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_0_.D = (!inst_CLK_000_D1.Q & inst_CLK_000_D0.Q);
+
+CLK_000_P_SYNC_0_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_1_.D = (CLK_000_P_SYNC_0_.Q);
+
+CLK_000_P_SYNC_1_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_2_.D = (CLK_000_P_SYNC_1_.Q);
+
+CLK_000_P_SYNC_2_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_3_.D = (CLK_000_P_SYNC_2_.Q);
+
+CLK_000_P_SYNC_3_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_4_.D = (CLK_000_P_SYNC_3_.Q);
+
+CLK_000_P_SYNC_4_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_5_.D = (CLK_000_P_SYNC_4_.Q);
+
+CLK_000_P_SYNC_5_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_6_.D = (CLK_000_P_SYNC_5_.Q);
+
+CLK_000_P_SYNC_6_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_7_.D = (CLK_000_P_SYNC_6_.Q);
+
+CLK_000_P_SYNC_7_.C = (CLK_OSZI);
+
+CLK_000_P_SYNC_8_.D = (CLK_000_P_SYNC_7_.Q);
+
+CLK_000_P_SYNC_8_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_0_.D = (inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q);
+
+CLK_000_N_SYNC_0_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_1_.D = (CLK_000_N_SYNC_0_.Q);
+
+CLK_000_N_SYNC_1_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_2_.D = (CLK_000_N_SYNC_1_.Q);
+
+CLK_000_N_SYNC_2_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_3_.D = (CLK_000_N_SYNC_2_.Q);
+
+CLK_000_N_SYNC_3_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_4_.D = (CLK_000_N_SYNC_3_.Q);
+
+CLK_000_N_SYNC_4_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_5_.D = (CLK_000_N_SYNC_4_.Q);
+
+CLK_000_N_SYNC_5_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_6_.D = (CLK_000_N_SYNC_5_.Q);
+
+CLK_000_N_SYNC_6_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_7_.D = (CLK_000_N_SYNC_6_.Q);
+
+CLK_000_N_SYNC_7_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_8_.D = (CLK_000_N_SYNC_7_.Q);
+
+CLK_000_N_SYNC_8_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_9_.D = (CLK_000_N_SYNC_8_.Q);
+
+CLK_000_N_SYNC_9_.C = (CLK_OSZI);
+
+CLK_000_N_SYNC_10_.D = (CLK_000_N_SYNC_9_.Q);
+
+CLK_000_N_SYNC_10_.C = (CLK_OSZI);
+
+SM_AMIGA_6_.D = (RST & SM_AMIGA_6_.Q & !SM_AMIGA_i_7_.Q
+     # RST & !inst_CLK_000_PE.Q & SM_AMIGA_6_.Q & BERR.PIN
+     # RST & inst_nEXP_SPACE_D0reg.Q & !inst_AS_030_000_SYNC.Q & inst_CLK_000_D1.Q & !inst_CLK_000_D0.Q & !SM_AMIGA_i_7_.Q);
+
+SM_AMIGA_6_.C = (CLK_OSZI);
+
+inst_CLK_030_H.D = (RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
+     # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !UDS_000.PIN
+     # RST & !BGACK_030.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
+     # RST & !BGACK_030.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & inst_CLK_030_H.Q & !AS_000.PIN & !LDS_000.PIN
+     # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
+     # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !UDS_000.PIN
+     # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & !CYCLE_DMA_0_.Q & CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN
+     # !CLK_030 & RST & !BGACK_030.Q & !inst_AS_000_DMA.Q & CYCLE_DMA_0_.Q & !CYCLE_DMA_1_.Q & !AS_000.PIN & !LDS_000.PIN);
+
+inst_CLK_030_H.C = (CLK_OSZI);
+
+SM_AMIGA_1_.D = (RST & inst_CLK_000_PE.Q & !SM_AMIGA_1_.Q & SM_AMIGA_2_.Q
+     # RST & !inst_CLK_000_NE.Q & SM_AMIGA_1_.Q & BERR.PIN
+     # RST & SM_AMIGA_1_.Q & SM_AMIGA_2_.Q & BERR.PIN);
+
+SM_AMIGA_1_.C = (CLK_OSZI);
+
+SM_AMIGA_3_.T = (!RST & SM_AMIGA_3_.Q
+     # SM_AMIGA_3_.Q & !BERR.PIN
+     # RST & inst_CLK_000_PE.Q & SM_AMIGA_4_.Q & !SM_AMIGA_3_.Q
+     # inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q
+     # !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_4_.Q & SM_AMIGA_3_.Q);
+
+SM_AMIGA_3_.C = (CLK_OSZI);
+
+SM_AMIGA_2_.D = (RST & SM_AMIGA_3_.Q & SM_AMIGA_2_.Q
+     # RST & !inst_CLK_000_PE.Q & SM_AMIGA_2_.Q & BERR.PIN
+     # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q
+     # RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & inst_CLK_000_NE_D0.Q & SM_AMIGA_3_.Q);
+
+SM_AMIGA_2_.C = (CLK_OSZI);
+
+SM_AMIGA_i_7_.D = (RST & N_210_i & !inst_CLK_000_PE.Q & BERR.PIN
+     # RST & N_210_i & !SM_AMIGA_0_.Q & BERR.PIN
+     # RST & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_3_.Q
+     # RST & !SM_AMIGA_5_.Q & N_210_i & inst_CLK_000_PE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q
+     # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
+     # RST & N_210_i & inst_CLK_000_NE.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
+     # RST & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
+     # RST & !SM_AMIGA_5_.Q & N_210_i & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_3_.Q & !SM_AMIGA_2_.Q
+     # RST & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_210_i & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q
+     # RST & !SM_AMIGA_5_.Q & inst_VPA_D.Q & !inst_DTACK_D0.Q & N_210_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q
+     # RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q
+     # RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & N_210_i & inst_CLK_000_PE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_1_.Q
+     # RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !inst_VPA_D.Q & N_210_i & inst_CLK_000_NE.Q & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_2_.Q
+     # RST & !VMA.Q & !cpu_est_0_.Q & !cpu_est_1_.Q & !cpu_est_2_.Q & cpu_est_3_.Q & !SM_AMIGA_5_.Q & !inst_VPA_D.Q & N_210_i & inst_CLK_000_NE_D0.Q & !SM_AMIGA_0_.Q & !SM_AMIGA_4_.Q & !SM_AMIGA_6_.Q & !SM_AMIGA_1_.Q & !SM_AMIGA_2_.Q);
+
+SM_AMIGA_i_7_.C = (CLK_OSZI);
+
+CIIN_0 = (inst_nEXP_SPACE_D0reg.Q
+     # !A_31_ & !A_30_ & !A_29_ & !A_28_ & !A_27_ & !A_26_ & !A_25_ & !A_24_ & A_23_ & A_22_ & A_21_ & A_20_ & !inst_AS_030_D0.Q);
+
+
+Reverse-Polarity Equations:
+
diff --git a/Logic/68030_tk.svl b/Logic/68030_tk.svl
new file mode 100644
index 0000000..579ba2b
--- /dev/null
+++ b/Logic/68030_tk.svl
@@ -0,0 +1,2 @@
+Part Number: M4A5-128/64-10VC
+Need not generate svf file according to the constraints, exit
diff --git a/Logic/68030_tk.tal b/Logic/68030_tk.tal
new file mode 100644
index 0000000..9ce6739
--- /dev/null
+++ b/Logic/68030_tk.tal
@@ -0,0 +1,130 @@
+
+
+Design Name = 68030_tk.tt4
+~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+
+*******************
+* TIMING ANALYSIS *
+*******************
+
+Timing Analysis KEY:
+One unit of delay time is equivalent to one pass 
+     through the Central Switch Matrix.
+..   Delay ( in this column ) not applicable to the indicated signal.
+TSU, Set-Up Time ( 0 for input-paired signals ),
+     represents the number of switch matrix passes between
+     an input pin and a register setup before clock.
+     TSU is reported on the register.
+TCO, Clocked Output-to-Pin Time ( 0 for output-paired signals ),
+     represents the number of switch matrix passes between
+     a clocked register and an output pin.
+     TCO is reported on the register.
+TPD, Propagation Delay Time ( calculated only for combinatorial eqns.),
+     represents the number of switch matrix passes between
+     an input pin and an output pin.
+     TPD is reported on the output pin.
+TCR, Clocked Output-to-Register Time,
+     represents the number of switch matrix passes between
+     a clocked register and the register it drives ( before clock ).
+     TCR is reported on the driving register.
+
+                    TSU       TCO       TPD       TCR
+                  #passes   #passes   #passes   #passes
+SIGNAL NAME       min  max  min  max  min  max  min  max
+ inst_AS_000_INT   1    1    1    3   ..   ..    2    3   
+ inst_AS_000_DMA   1    2    1    3   ..   ..    1    3   
+          DS_030  ..   ..   ..   ..    1    2   ..   ..   
+          FPU_CS  ..   ..   ..   ..    1    2   ..   ..   
+AMIGA_BUS_DATA_DIR  ..   ..   ..   ..    1    2   ..   ..   
+       BGACK_030   1    2    0    1   ..   ..    1    1   
+    RN_BGACK_030   1    2    0    1   ..   ..    1    1   
+     SM_AMIGA_5_   1    1   ..   ..   ..   ..    1    2   
+  inst_AS_030_D0   1    2    1    1   ..   ..    1    1   
+inst_nEXP_SPACE_D0reg   1    1    1    1   ..   ..    1    2   
+inst_AS_030_000_SYNC   1    1   ..   ..   ..   ..    1    2   
+ inst_DS_000_DMA   1    2    1    1   ..   ..   ..   ..   
+    CYCLE_DMA_0_   1    2   ..   ..   ..   ..    1    1   
+    CYCLE_DMA_1_   1    2   ..   ..   ..   ..    1    1   
+     SIZE_DMA_0_   1    1    1    1   ..   ..    2    2   
+     SIZE_DMA_1_   1    1    1    1   ..   ..    2    2   
+inst_UDS_000_INT   1    1    1    1   ..   ..    2    2   
+inst_LDS_000_INT   1    1    1    1   ..   ..    2    2   
+ inst_CLK_000_D1  ..   ..   ..   ..   ..   ..    1    2   
+ inst_CLK_000_D0   1    1   ..   ..   ..   ..    1    2   
+     SM_AMIGA_0_   1    1   ..   ..   ..   ..    1    2   
+     SM_AMIGA_4_   1    1   ..   ..   ..   ..    1    2   
+inst_DS_000_ENABLE   1    1    1    1   ..   ..    2    2   
+     SM_AMIGA_6_   1    1   ..   ..   ..   ..    1    2   
+  inst_CLK_030_H   1    2   ..   ..   ..   ..    1    1   
+     SM_AMIGA_1_   1    1   ..   ..   ..   ..    1    2   
+     SM_AMIGA_3_   1    1   ..   ..   ..   ..    1    2   
+     SM_AMIGA_2_   1    1   ..   ..   ..   ..    1    2   
+          AS_030  ..   ..   ..   ..    1    1   ..   ..   
+          AS_000  ..   ..   ..   ..    1    1   ..   ..   
+            CIIN  ..   ..   ..   ..    1    1   ..   ..   
+      IPL_030_2_   1    1    0    0   ..   ..    1    1   
+   RN_IPL_030_2_   1    1    0    0   ..   ..    1    1   
+      IPL_030_1_   1    1    0    0   ..   ..    1    1   
+   RN_IPL_030_1_   1    1    0    0   ..   ..    1    1   
+      IPL_030_0_   1    1    0    0   ..   ..    1    1   
+   RN_IPL_030_0_   1    1    0    0   ..   ..    1    1   
+          RW_000   1    1    0    0   ..   ..    1    1   
+       RN_RW_000   1    1    0    0   ..   ..    1    1   
+              A0   1    1    0    0   ..   ..    1    1   
+           RN_A0   1    1    0    0   ..   ..    1    1   
+          BG_000   1    1    0    0   ..   ..    1    1   
+       RN_BG_000   1    1    0    0   ..   ..    1    1   
+          DSACK1   1    1    0    0   ..   ..    1    1   
+       RN_DSACK1   1    1    0    0   ..   ..    1    1   
+             VMA   1    1    0    0   ..   ..    1    1   
+          RN_VMA   1    1    0    0   ..   ..    1    1   
+              RW   1    1    0    0   ..   ..    1    1   
+           RN_RW   1    1    0    0   ..   ..    1    1   
+      cpu_est_0_  ..   ..   ..   ..   ..   ..    1    1   
+      cpu_est_1_  ..   ..    1    1   ..   ..    1    1   
+      cpu_est_2_  ..   ..    1    1   ..   ..    1    1   
+      cpu_est_3_  ..   ..    1    1   ..   ..    1    1   
+inst_AMIGA_BUS_ENABLE_DMA_LOW   1    1    1    1   ..   ..   ..   ..   
+inst_BGACK_030_INT_D   1    1   ..   ..   ..   ..    1    1   
+      inst_VPA_D   1    1   ..   ..   ..   ..    1    1   
+inst_CLK_OUT_PRE_D  ..   ..   ..   ..   ..   ..    1    1   
+   inst_DTACK_D0   1    1   ..   ..   ..   ..    1    1   
+  inst_RESET_OUT   1    1   ..   ..   ..   ..   ..   ..   
+inst_CLK_OUT_PRE_50  ..   ..   ..   ..   ..   ..    1    1   
+inst_CLK_OUT_PRE_25  ..   ..   ..   ..   ..   ..    1    1   
+ inst_CLK_000_PE  ..   ..   ..   ..   ..   ..    1    1   
+inst_CLK_OUT_EXP_INT  ..   ..    1    1   ..   ..   ..   ..   
+CLK_000_P_SYNC_9_  ..   ..   ..   ..   ..   ..    1    1   
+ inst_CLK_000_NE  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_N_SYNC_11_  ..   ..   ..   ..   ..   ..    1    1   
+       IPL_D0_0_   1    1   ..   ..   ..   ..    1    1   
+       IPL_D0_1_   1    1   ..   ..   ..   ..    1    1   
+       IPL_D0_2_   1    1   ..   ..   ..   ..    1    1   
+inst_CLK_000_NE_D0  ..   ..   ..   ..   ..   ..    1    1   
+inst_AMIGA_BUS_ENABLE_DMA_HIGH   1    1    1    1   ..   ..   ..   ..   
+      RST_DLY_0_   1    1   ..   ..   ..   ..    1    1   
+      RST_DLY_1_   1    1   ..   ..   ..   ..    1    1   
+      RST_DLY_2_   1    1   ..   ..   ..   ..    1    1   
+CLK_000_P_SYNC_0_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_P_SYNC_1_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_P_SYNC_2_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_P_SYNC_3_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_P_SYNC_4_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_P_SYNC_5_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_P_SYNC_6_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_P_SYNC_7_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_P_SYNC_8_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_N_SYNC_0_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_N_SYNC_1_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_N_SYNC_2_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_N_SYNC_3_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_N_SYNC_4_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_N_SYNC_5_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_N_SYNC_6_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_N_SYNC_7_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_N_SYNC_8_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_N_SYNC_9_  ..   ..   ..   ..   ..   ..    1    1   
+CLK_000_N_SYNC_10_  ..   ..   ..   ..   ..   ..    1    1   
+   SM_AMIGA_i_7_   1    1    1    1   ..   ..    1    1   
+          CIIN_0  ..   ..   ..   ..    1    1   ..   ..   
\ No newline at end of file
diff --git a/Logic/68030_tk.tt2 b/Logic/68030_tk.tt2
new file mode 100644
index 0000000..eccd2bc
--- /dev/null
+++ b/Logic/68030_tk.tt2
@@ -0,0 +1,573 @@
+#$ TOOL ispLEVER Classic 1.8.00.04.29.14
+#$ DATE Sun Jan 24 16:20:54 2016
+#$ MODULE 68030_tk
+#$ PINS 61 SIZE_1_ A_31_ IPL_2_ FC_1_ IPL_1_ AS_030 IPL_0_ AS_000 FC_0_ DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_EXP FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR SIZE_0_ AMIGA_BUS_ENABLE_LOW A_30_ AMIGA_BUS_ENABLE_HIGH A_29_ CIIN A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 BGACK_030 CLK_DIV_OUT DSACK1 VMA RW
+#$ NODES 70 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 N_210_i inst_CLK_OUT_PRE_25 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE inst_CLK_OUT_EXP_INT CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_
+.type fr
+.i 122
+.o 193
+.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q N_210_i inst_CLK_OUT_PRE_25.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q inst_CLK_OUT_EXP_INT.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN
+.ob DS_030 CLK_EXP FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_2_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_P_SYNC_0_.C inst_DS_000_ENABLE.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_CLK_OUT_PRE_25.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C A0.C inst_BGACK_030_INT_D.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C CLK_DIV_OUT.C inst_CLK_000_D1.C inst_CLK_000_NE_D0.C inst_CLK_OUT_EXP_INT.C inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.C inst_CLK_000_PE.C SIZE_1_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ N_210_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE BGACK_030.D CLK_DIV_OUT.D VMA.T cpu_est_0_.D cpu_est_1_.D cpu_est_2_.D cpu_est_3_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D inst_CLK_000_D1.D inst_CLK_000_D0.D inst_CLK_000_PE.D inst_CLK_OUT_EXP_INT.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D
+.p 561
+-------------------------------------------------------------------------------------------------------------------------- ~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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+---------------------------------------0-1-------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+0-------------00000001111----------------0-------------------------------------------------------------------------------- ~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+------------------------------------------1------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--------------------------------0---------0------------------------------------------------------------------------------- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~11~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+--1----------------------0010--1-----------1------------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~1~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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+.end
diff --git a/Logic/68030_tk.tt3 b/Logic/68030_tk.tt3
new file mode 100644
index 0000000..f2e0233
--- /dev/null
+++ b/Logic/68030_tk.tt3
@@ -0,0 +1,573 @@
+#$ TOOL ispLEVER Classic 1.8.00.04.29.14
+#$ DATE Sun Jan 24 16:20:54 2016
+#$ MODULE 68030_tk
+#$ PINS 61 SIZE_1_ A_31_ IPL_2_ FC_1_ IPL_1_ AS_030 IPL_0_ AS_000 FC_0_ DS_030 UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_EXP FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR SIZE_0_ AMIGA_BUS_ENABLE_LOW A_30_ AMIGA_BUS_ENABLE_HIGH A_29_ CIIN A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 BGACK_030 CLK_DIV_OUT DSACK1 VMA RW 
+#$ NODES 70 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AS_000_INT SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT inst_CLK_OUT_PRE_50 N_210_i inst_CLK_OUT_PRE_25 inst_CLK_000_D1 inst_CLK_000_D0 inst_CLK_000_PE inst_CLK_OUT_EXP_INT CLK_000_P_SYNC_9_ inst_CLK_000_NE CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_ SM_AMIGA_2_ SM_AMIGA_i_7_ 
+.type fr
+.i 122
+.o 193
+.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q inst_AS_000_INT.Q SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q N_210_i inst_CLK_OUT_PRE_25.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q inst_CLK_000_PE.Q inst_CLK_OUT_EXP_INT.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN
+.ob DS_030 CLK_EXP FPU_CS AVEC E RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN SM_AMIGA_i_7_.C SM_AMIGA_6_.C SM_AMIGA_5_.C SM_AMIGA_4_.C SM_AMIGA_3_.C SM_AMIGA_2_.C SM_AMIGA_1_.C SM_AMIGA_0_.C cpu_est_2_.C cpu_est_3_.C IPL_030_0_.C IPL_030_1_.C IPL_030_2_.C IPL_D0_0_.C IPL_D0_1_.C IPL_D0_2_.C CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.C CYCLE_DMA_1_.C SIZE_DMA_0_.C SIZE_DMA_1_.C cpu_est_0_.C cpu_est_1_.C CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.C RST_DLY_0_.C RST_DLY_1_.C RST_DLY_2_.C CLK_000_P_SYNC_0_.C inst_DS_000_ENABLE.C RW.C RW_000.C inst_LDS_000_INT.C BGACK_030.C inst_AS_000_DMA.C inst_AS_030_000_SYNC.C inst_AS_000_INT.C DSACK1.C inst_DS_000_DMA.C inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.C inst_VPA_D.C inst_DTACK_D0.C inst_CLK_030_H.C inst_RESET_OUT.C inst_CLK_OUT_PRE_25.C BG_000.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.C VMA.C inst_UDS_000_INT.C A0.C inst_BGACK_030_INT_D.C inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.C CLK_DIV_OUT.C inst_CLK_000_D1.C inst_CLK_000_NE_D0.C inst_CLK_OUT_EXP_INT.C inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.C inst_CLK_000_PE.C SIZE_1_ AS_030 AS_000 UDS_000 LDS_000 BERR SIZE_0_ N_210_i AS_030.OE AS_000.OE RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE RESET.OE CIIN.OE BGACK_030.D CLK_DIV_OUT.D VMA.T cpu_est_0_.D cpu_est_1_.D cpu_est_2_.D cpu_est_3_.D inst_AS_000_INT.D SM_AMIGA_5_.D inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AS_030_D0.D inst_nEXP_SPACE_D0reg.D inst_AS_030_000_SYNC.D inst_BGACK_030_INT_D.D inst_AS_000_DMA.D inst_DS_000_DMA.D CYCLE_DMA_0_.D CYCLE_DMA_1_.D SIZE_DMA_0_.D SIZE_DMA_1_.D inst_VPA_D.D inst_UDS_000_INT.D inst_LDS_000_INT.D inst_CLK_OUT_PRE_D.D inst_DTACK_D0.D inst_RESET_OUT.D inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_25.D inst_CLK_000_D1.D inst_CLK_000_D0.D inst_CLK_000_PE.D inst_CLK_OUT_EXP_INT.D CLK_000_P_SYNC_9_.D inst_CLK_000_NE.D CLK_000_N_SYNC_11_.D IPL_D0_0_.D IPL_D0_1_.D IPL_D0_2_.D inst_CLK_000_NE_D0.D SM_AMIGA_0_.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.D DSACK1.D SM_AMIGA_4_.D inst_DS_000_ENABLE.D RST_DLY_0_.D RST_DLY_1_.D RST_DLY_2_.D CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_8_.D CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_10_.D RW_000.D RW.D A0.D SM_AMIGA_6_.D inst_CLK_030_H.D SM_AMIGA_1_.D SM_AMIGA_3_.T SM_AMIGA_2_.D SM_AMIGA_i_7_.D BG_000.D IPL_030_0_.D IPL_030_1_.D IPL_030_2_.D
+.p 561
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+.end
diff --git a/Logic/68030_tk.tt4 b/Logic/68030_tk.tt4
new file mode 100644
index 0000000..65f9fb7
--- /dev/null
+++ b/Logic/68030_tk.tt4
@@ -0,0 +1,321 @@
+#$ TOOL  ispLEVER Classic 1.8.00.04.29.14
+#$ DATE  Sun Jan 24 16:20:54 2016
+#$ MODULE  BUS68030
+#$ PINS 61 SIZE_1_ A_31_ IPL_2_ FC_1_ IPL_1_ AS_030 IPL_0_ AS_000 FC_0_ DS_030
+ UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
+ CLK_EXP FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE
+ AMIGA_BUS_DATA_DIR SIZE_0_ AMIGA_BUS_ENABLE_LOW A_30_ AMIGA_BUS_ENABLE_HIGH
+ A_29_ CIIN A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_
+ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 BGACK_030
+ CLK_DIV_OUT DSACK1 VMA RW
+#$ NODES 71 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AS_000_INT
+ SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg
+ inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA
+ CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT
+ inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT
+ inst_CLK_OUT_PRE_50 N_210_i inst_CLK_OUT_PRE_25 inst_CLK_000_D1 inst_CLK_000_D0
+ inst_CLK_000_PE inst_CLK_OUT_EXP_INT CLK_000_P_SYNC_9_ inst_CLK_000_NE
+ CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_
+ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_
+ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_
+ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_
+ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_
+ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_
+ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_
+ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_
+ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
+.type f
+.i 123
+.o 194
+.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
+ FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
+ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q
+ cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q inst_AS_000_INT.Q
+ SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
+ inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q
+ inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q
+ SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q
+ inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q
+ N_210_i inst_CLK_OUT_PRE_25.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q
+ inst_CLK_000_PE.Q inst_CLK_OUT_EXP_INT.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q
+ CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q
+ SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q
+ inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q
+ CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q
+ CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q
+ CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q
+ CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q
+ CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q
+ SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q
+ SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN
+ AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN
+ BERR.PIN RW.PIN CIIN_0
+.ob SIZE_1_ SIZE_1_.OE AS_030% AS_030.OE AS_000% AS_000.OE DS_030% DS_030.OE
+ UDS_000% UDS_000.OE LDS_000% LDS_000.OE BERR BERR.OE CLK_EXP FPU_CS% AVEC E
+ RESET RESET.OE AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR SIZE_0_ SIZE_0_.OE
+ AMIGA_BUS_ENABLE_LOW% AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE IPL_030_2_.D%
+ IPL_030_2_.C IPL_030_1_.D% IPL_030_1_.C IPL_030_0_.D% IPL_030_0_.C RW_000.D%
+ RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D% BG_000.C BGACK_030.D BGACK_030.C
+ CLK_DIV_OUT.D CLK_DIV_OUT.C DSACK1.D% DSACK1.C DSACK1.OE VMA.T VMA.C RW.D% RW.C
+ RW.OE cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D
+ cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C inst_AS_000_INT.D% inst_AS_000_INT.C
+ SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D%
+ inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D% inst_AS_030_D0.C
+ inst_nEXP_SPACE_D0reg.D% inst_nEXP_SPACE_D0reg.C inst_AS_030_000_SYNC.D%
+ inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D% inst_BGACK_030_INT_D.C
+ inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C
+ CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D%
+ SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D% inst_VPA_D.C
+ inst_UDS_000_INT.D% inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C
+ inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D% inst_DTACK_D0.C
+ inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C
+ N_210_i% inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C inst_CLK_000_D1.D
+ inst_CLK_000_D1.C inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D
+ inst_CLK_000_PE.C inst_CLK_OUT_EXP_INT.D inst_CLK_OUT_EXP_INT.C
+ CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D inst_CLK_000_NE.C
+ CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C IPL_D0_0_.D% IPL_D0_0_.C IPL_D0_1_.D%
+ IPL_D0_1_.C IPL_D0_2_.D% IPL_D0_2_.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C
+ SM_AMIGA_0_.D SM_AMIGA_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D%
+ inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_4_.D SM_AMIGA_4_.C
+ inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D
+ RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C
+ CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C
+ CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C
+ CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C
+ CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C
+ CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C
+ CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C
+ CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C
+ CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C
+ CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C
+ CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C SM_AMIGA_6_.D SM_AMIGA_6_.C
+ inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_3_.T
+ SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C CIIN_0
+.phase 11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
+.p 225
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diff --git a/Logic/68030_tk.tte b/Logic/68030_tk.tte
new file mode 100644
index 0000000..6af9f40
--- /dev/null
+++ b/Logic/68030_tk.tte
@@ -0,0 +1,321 @@
+#$ TOOL  ispLEVER Classic 1.8.00.04.29.14
+#$ DATE  Sun Jan 24 16:20:54 2016
+#$ MODULE  BUS68030
+#$ PINS 61 SIZE_1_ A_31_ IPL_2_ FC_1_ IPL_1_ AS_030 IPL_0_ AS_000 FC_0_ DS_030
+ UDS_000 LDS_000 A1 nEXP_SPACE BERR BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
+ CLK_EXP FPU_CS FPU_SENSE DTACK AVEC E VPA RST RESET AMIGA_ADDR_ENABLE
+ AMIGA_BUS_DATA_DIR SIZE_0_ AMIGA_BUS_ENABLE_LOW A_30_ AMIGA_BUS_ENABLE_HIGH
+ A_29_ CIIN A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_
+ A_17_ A_16_ IPL_030_2_ IPL_030_1_ IPL_030_0_ RW_000 A0 BG_000 BGACK_030
+ CLK_DIV_OUT DSACK1 VMA RW
+#$ NODES 71 cpu_est_0_ cpu_est_1_ cpu_est_2_ cpu_est_3_ inst_AS_000_INT
+ SM_AMIGA_5_ inst_AMIGA_BUS_ENABLE_DMA_LOW inst_AS_030_D0 inst_nEXP_SPACE_D0reg
+ inst_AS_030_000_SYNC inst_BGACK_030_INT_D inst_AS_000_DMA inst_DS_000_DMA
+ CYCLE_DMA_0_ CYCLE_DMA_1_ SIZE_DMA_0_ SIZE_DMA_1_ inst_VPA_D inst_UDS_000_INT
+ inst_LDS_000_INT inst_CLK_OUT_PRE_D inst_DTACK_D0 inst_RESET_OUT
+ inst_CLK_OUT_PRE_50 N_210_i inst_CLK_OUT_PRE_25 inst_CLK_000_D1 inst_CLK_000_D0
+ inst_CLK_000_PE inst_CLK_OUT_EXP_INT CLK_000_P_SYNC_9_ inst_CLK_000_NE
+ CLK_000_N_SYNC_11_ IPL_D0_0_ IPL_D0_1_ IPL_D0_2_ inst_CLK_000_NE_D0 SM_AMIGA_0_
+ inst_AMIGA_BUS_ENABLE_DMA_HIGH SM_AMIGA_4_ inst_DS_000_ENABLE RST_DLY_0_
+ RST_DLY_1_ RST_DLY_2_ CLK_000_P_SYNC_0_ CLK_000_P_SYNC_1_ CLK_000_P_SYNC_2_
+ CLK_000_P_SYNC_3_ CLK_000_P_SYNC_4_ CLK_000_P_SYNC_5_ CLK_000_P_SYNC_6_
+ CLK_000_P_SYNC_7_ CLK_000_P_SYNC_8_ CLK_000_N_SYNC_0_ CLK_000_N_SYNC_1_
+ CLK_000_N_SYNC_2_ CLK_000_N_SYNC_3_ CLK_000_N_SYNC_4_ CLK_000_N_SYNC_5_
+ CLK_000_N_SYNC_6_ CLK_000_N_SYNC_7_ CLK_000_N_SYNC_8_ CLK_000_N_SYNC_9_
+ CLK_000_N_SYNC_10_ SM_AMIGA_6_ inst_CLK_030_H SM_AMIGA_1_ SM_AMIGA_3_
+ SM_AMIGA_2_ SM_AMIGA_i_7_ CIIN_0
+.type f
+.i 123
+.o 194
+.ilb A_31_ IPL_2_ FC_1_ A1 nEXP_SPACE BG_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI
+ FPU_SENSE DTACK VPA RST A_30_ A_29_ A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_
+ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ IPL_1_ IPL_0_ FC_0_ BGACK_030.Q VMA.Q
+ cpu_est_0_.Q cpu_est_1_.Q cpu_est_2_.Q cpu_est_3_.Q inst_AS_000_INT.Q
+ SM_AMIGA_5_.Q inst_AMIGA_BUS_ENABLE_DMA_LOW.Q inst_AS_030_D0.Q
+ inst_nEXP_SPACE_D0reg.Q inst_AS_030_000_SYNC.Q inst_BGACK_030_INT_D.Q
+ inst_AS_000_DMA.Q inst_DS_000_DMA.Q CYCLE_DMA_0_.Q CYCLE_DMA_1_.Q SIZE_DMA_0_.Q
+ SIZE_DMA_1_.Q inst_VPA_D.Q inst_UDS_000_INT.Q inst_LDS_000_INT.Q
+ inst_CLK_OUT_PRE_D.Q inst_DTACK_D0.Q inst_RESET_OUT.Q inst_CLK_OUT_PRE_50.Q
+ N_210_i inst_CLK_OUT_PRE_25.Q inst_CLK_000_D1.Q inst_CLK_000_D0.Q
+ inst_CLK_000_PE.Q inst_CLK_OUT_EXP_INT.Q CLK_000_P_SYNC_9_.Q inst_CLK_000_NE.Q
+ CLK_000_N_SYNC_11_.Q IPL_D0_0_.Q IPL_D0_1_.Q IPL_D0_2_.Q inst_CLK_000_NE_D0.Q
+ SM_AMIGA_0_.Q inst_AMIGA_BUS_ENABLE_DMA_HIGH.Q DSACK1.Q SM_AMIGA_4_.Q
+ inst_DS_000_ENABLE.Q RST_DLY_0_.Q RST_DLY_1_.Q RST_DLY_2_.Q CLK_000_P_SYNC_0_.Q
+ CLK_000_P_SYNC_1_.Q CLK_000_P_SYNC_2_.Q CLK_000_P_SYNC_3_.Q CLK_000_P_SYNC_4_.Q
+ CLK_000_P_SYNC_5_.Q CLK_000_P_SYNC_6_.Q CLK_000_P_SYNC_7_.Q CLK_000_P_SYNC_8_.Q
+ CLK_000_N_SYNC_0_.Q CLK_000_N_SYNC_1_.Q CLK_000_N_SYNC_2_.Q CLK_000_N_SYNC_3_.Q
+ CLK_000_N_SYNC_4_.Q CLK_000_N_SYNC_5_.Q CLK_000_N_SYNC_6_.Q CLK_000_N_SYNC_7_.Q
+ CLK_000_N_SYNC_8_.Q CLK_000_N_SYNC_9_.Q CLK_000_N_SYNC_10_.Q RW_000.Q RW.Q A0.Q
+ SM_AMIGA_6_.Q inst_CLK_030_H.Q SM_AMIGA_1_.Q SM_AMIGA_3_.Q SM_AMIGA_2_.Q
+ SM_AMIGA_i_7_.Q BG_000.Q IPL_030_0_.Q IPL_030_1_.Q IPL_030_2_.Q AS_030.PIN
+ AS_000.PIN RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN
+ BERR.PIN RW.PIN CIIN_0
+.ob SIZE_1_ SIZE_1_.OE AS_030- AS_030.OE AS_000- AS_000.OE DS_030- DS_030.OE
+ UDS_000- UDS_000.OE LDS_000- LDS_000.OE BERR BERR.OE CLK_EXP FPU_CS- AVEC E
+ RESET RESET.OE AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR SIZE_0_ SIZE_0_.OE
+ AMIGA_BUS_ENABLE_LOW- AMIGA_BUS_ENABLE_HIGH CIIN CIIN.OE IPL_030_2_.D-
+ IPL_030_2_.C IPL_030_1_.D- IPL_030_1_.C IPL_030_0_.D- IPL_030_0_.C RW_000.D-
+ RW_000.C RW_000.OE A0.D A0.C A0.OE BG_000.D- BG_000.C BGACK_030.D BGACK_030.C
+ CLK_DIV_OUT.D CLK_DIV_OUT.C DSACK1.D- DSACK1.C DSACK1.OE VMA.T VMA.C RW.D- RW.C
+ RW.OE cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C cpu_est_2_.D
+ cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C inst_AS_000_INT.D- inst_AS_000_INT.C
+ SM_AMIGA_5_.D SM_AMIGA_5_.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D-
+ inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_AS_030_D0.D- inst_AS_030_D0.C
+ inst_nEXP_SPACE_D0reg.D- inst_nEXP_SPACE_D0reg.C inst_AS_030_000_SYNC.D-
+ inst_AS_030_000_SYNC.C inst_BGACK_030_INT_D.D- inst_BGACK_030_INT_D.C
+ inst_AS_000_DMA.D inst_AS_000_DMA.C inst_DS_000_DMA.D inst_DS_000_DMA.C
+ CYCLE_DMA_0_.D CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D-
+ SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C inst_VPA_D.D- inst_VPA_D.C
+ inst_UDS_000_INT.D- inst_UDS_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C
+ inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_DTACK_D0.D- inst_DTACK_D0.C
+ inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C
+ N_210_i- inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C inst_CLK_000_D1.D
+ inst_CLK_000_D1.C inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D
+ inst_CLK_000_PE.C inst_CLK_OUT_EXP_INT.D inst_CLK_OUT_EXP_INT.C
+ CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C inst_CLK_000_NE.D inst_CLK_000_NE.C
+ CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C IPL_D0_0_.D- IPL_D0_0_.C IPL_D0_1_.D-
+ IPL_D0_1_.C IPL_D0_2_.D- IPL_D0_2_.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C
+ SM_AMIGA_0_.D SM_AMIGA_0_.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D-
+ inst_AMIGA_BUS_ENABLE_DMA_HIGH.C SM_AMIGA_4_.D SM_AMIGA_4_.C
+ inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D
+ RST_DLY_1_.C RST_DLY_2_.D RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C
+ CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C
+ CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C
+ CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C
+ CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C
+ CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C
+ CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C
+ CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C
+ CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C
+ CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C
+ CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C SM_AMIGA_6_.D SM_AMIGA_6_.C
+ inst_CLK_030_H.D inst_CLK_030_H.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_3_.T
+ SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C CIIN_0
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+.end
diff --git a/Logic/68030_tk.v2l b/Logic/68030_tk.v2l
new file mode 100644
index 0000000..e69de29
diff --git a/Logic/68030_tk.vcl b/Logic/68030_tk.vcl
new file mode 100644
index 0000000..6d42c92
--- /dev/null
+++ b/Logic/68030_tk.vcl
@@ -0,0 +1,249 @@
+[DEVICE]
+
+Family = M4A5;
+PartType = M4A5-128/64;
+Package = 100TQFP;
+PartNumber = M4A5-128/64-10VC;
+Speed = -10;
+Operating_condition = COM;
+EN_Segment = NO;
+Pin_MC_1to1 = NO;
+Voltage = 5.0;
+
+[REVISION]
+
+RCS = "$Revision: 1.2 $";
+Parent = m4a5.lci;
+SDS_file = m4a5.sds;
+Design = 68030_tk.tt4;
+Rev = 0.01;
+DATE = 1/24/16;
+TIME = 16:20:59;
+Type = TT2;
+Pre_Fit_Time = 1;
+Source_Format = Pure_VHDL;
+
+[IGNORE ASSIGNMENTS]
+
+Pin_Assignments = NO;
+Pin_Keep_Block = NO;
+Pin_Keep_Segment = NO;
+Group_Assignments = NO;
+Macrocell_Assignments = NO;
+Macrocell_Keep_Block = NO;
+Macrocell_Keep_Segment = NO;
+Pin_Reservation = NO;
+Timing_Constraints = NO;
+Block_Reservation = NO;
+Segment_Reservation = NO;
+Ignore_Source_Location = NO;
+Ignore_Source_Optimization = NO;
+Ignore_Source_Timing = NO;
+
+[CLEAR ASSIGNMENTS]
+
+Pin_Assignments = NO;
+Pin_Keep_Block = NO;
+Pin_Keep_Segment = NO;
+Group_Assignments = NO;
+Macrocell_Assignments = NO;
+Macrocell_Keep_Block = NO;
+Macrocell_Keep_Segment = NO;
+Pin_Reservation = NO;
+Timing_Constraints = NO;
+Block_Reservation = NO;
+Segment_Reservation = NO;
+Ignore_Source_Location = NO;
+Ignore_Source_Optimization = NO;
+Ignore_Source_Timing = NO;
+
+[BACKANNOTATE NETLIST]
+
+Netlist = VHDL;
+Delay_File = SDF;
+Generic_VCC = ;
+Generic_GND = ;
+
+[BACKANNOTATE ASSIGNMENTS]
+
+Pin_Assignment = NO;
+Pin_Block = NO;
+Pin_Macrocell_Block = NO;
+Routing = NO;
+
+[GLOBAL PROJECT OPTIMIZATION]
+
+Balanced_Partitioning = YES;
+Spread_Placement = YES;
+Max_Pin_Percent = 100;
+Max_Macrocell_Percent = 100;
+Max_Inter_Seg_Percent = 100;
+Max_Seg_In_Percent = 100;
+Max_Blk_In_Percent = 100;
+
+[FITTER REPORT FORMAT]
+
+Fitter_Options = YES;
+Pinout_Diagram = NO;
+Pinout_Listing = YES;
+Detailed_Block_Segment_Summary = YES;
+Input_Signal_List = YES;
+Output_Signal_List = YES;
+Bidir_Signal_List = YES;
+Node_Signal_List = YES;
+Signal_Fanout_List = YES;
+Block_Segment_Fanin_List = YES;
+Prefit_Eqn = YES;
+Postfit_Eqn = YES;
+Page_Break = YES;
+
+[OPTIMIZATION OPTIONS]
+
+Logic_Reduction = YES;
+Max_PTerm_Split = 16;
+Max_PTerm_Collapse = 16;
+XOR_Synthesis = YES;
+Node_Collapse = Yes;
+DT_Synthesis = Yes;
+
+[FITTER GLOBAL OPTIONS]
+
+Run_Time = 0;
+Set_Reset_Dont_Care = NO;
+In_Reg_Optimize = YES;
+Clock_Optimize = NO;
+Conf_Unused_IOs = OUT_LOW;
+
+[POWER]
+Powerlevel = Low, High;
+Default = High;
+Low = 8, H, G, F, E, D, C, B, A;
+Type = GLB;
+
+[HARDWARE DEVICE OPTIONS]
+Zero_Hold_Time = Yes;
+Signature_Word = 0;
+Pull_up = Yes;
+Out_Slew_Rate = SLOW, FAST, 7, CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, 
+	AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH;
+Device_max_fanin = 33;
+Device_max_pterms = 20;
+Usercode_Format = Hex;
+
+[PIN RESERVATIONS]
+layer = OFF;
+
+[LOCATION ASSIGNMENT]
+
+Layer = OFF
+BERR = OUTPUT,41,4,-;
+RW_000 = BIDIR,80,7,-;
+AS_000 = OUTPUT,42,4,-;
+RW = BIDIR,71,6,-;
+AS_030 = OUTPUT,82,7,-;
+UDS_000 = OUTPUT,32,3,-;
+LDS_000 = OUTPUT,31,3,-;
+A0 = BIDIR,69,6,-;
+SIZE_1_ = OUTPUT,79,7,-;
+SIZE_0_ = OUTPUT,70,6,-;
+IPL_030_2_ = OUTPUT,9,1,-;
+IPL_030_0_ = OUTPUT,8,1,-;
+IPL_030_1_ = OUTPUT,7,1,-;
+DSACK1 = OUTPUT,81,7,-;
+BGACK_030 = OUTPUT,83,7,-;
+VMA = OUTPUT,35,3,-;
+E = OUTPUT,66,6,-;
+AMIGA_BUS_DATA_DIR = OUTPUT,48,4,-;
+AMIGA_BUS_ENABLE_HIGH = OUTPUT,34,3,-;
+BG_000 = OUTPUT,29,3,-;
+DS_030 = OUTPUT,98,0,-;
+AVEC = OUTPUT,92,0,-;
+FPU_CS = OUTPUT,78,7,-;
+CLK_DIV_OUT = OUTPUT,65,6,-;
+CIIN = OUTPUT,47,4,-;
+AMIGA_ADDR_ENABLE = OUTPUT,33,3,-;
+AMIGA_BUS_ENABLE_LOW = OUTPUT,20,2,-;
+CLK_EXP = OUTPUT,10,1,-;
+RESET = OUTPUT,3,1,-;
+RN_BGACK_030 = NODE,-1,7,-;
+inst_RESET_OUT = NODE,*,6,-;
+inst_nEXP_SPACE_D0reg = NODE,*,7,-;
+inst_CLK_000_PE = NODE,*,5,-;
+inst_AS_030_D0 = NODE,*,7,-;
+SM_AMIGA_1_ = NODE,*,0,-;
+SM_AMIGA_5_ = NODE,*,5,-;
+inst_CLK_000_NE = NODE,*,6,-;
+inst_CLK_000_D0 = NODE,*,3,-;
+SM_AMIGA_i_7_ = NODE,*,5,-;
+SM_AMIGA_2_ = NODE,*,5,-;
+cpu_est_2_ = NODE,*,3,-;
+SM_AMIGA_6_ = NODE,*,2,-;
+cpu_est_3_ = NODE,*,3,-;
+cpu_est_1_ = NODE,*,3,-;
+SM_AMIGA_0_ = NODE,*,5,-;
+inst_CLK_000_D1 = NODE,*,2,-;
+inst_BGACK_030_INT_D = NODE,*,4,-;
+inst_AS_000_DMA = NODE,*,0,-;
+SM_AMIGA_3_ = NODE,*,5,-;
+inst_DS_000_ENABLE = NODE,*,2,-;
+RN_VMA = NODE,-1,3,-;
+SM_AMIGA_4_ = NODE,*,5,-;
+inst_LDS_000_INT = NODE,*,0,-;
+SIZE_DMA_1_ = NODE,*,6,-;
+SIZE_DMA_0_ = NODE,*,6,-;
+inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,*,1,-;
+inst_CLK_OUT_PRE_25 = NODE,*,6,-;
+inst_UDS_000_INT = NODE,*,0,-;
+inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,*,1,-;
+inst_AS_000_INT = NODE,*,1,-;
+cpu_est_0_ = NODE,*,3,-;
+inst_CLK_000_NE_D0 = NODE,*,3,-;
+inst_CLK_OUT_PRE_50 = NODE,*,4,-;
+inst_CLK_OUT_PRE_D = NODE,*,3,-;
+inst_VPA_D = NODE,*,2,-;
+RN_IPL_030_0_ = NODE,-1,1,-;
+RN_IPL_030_1_ = NODE,-1,1,-;
+RN_IPL_030_2_ = NODE,-1,1,-;
+inst_DS_000_DMA = NODE,*,0,-;
+inst_CLK_030_H = NODE,*,0,-;
+inst_AS_030_000_SYNC = NODE,*,2,-;
+RN_DSACK1 = NODE,-1,7,-;
+RST_DLY_1_ = NODE,*,6,-;
+N_210_i = NODE,*,2,-;
+RN_A0 = NODE,-1,6,-;
+RN_RW_000 = NODE,-1,7,-;
+RST_DLY_0_ = NODE,*,6,-;
+CYCLE_DMA_1_ = NODE,*,0,-;
+RN_RW = NODE,-1,6,-;
+RN_BG_000 = NODE,-1,3,-;
+CIIN_0 = NODE,*,4,-;
+RST_DLY_2_ = NODE,*,6,-;
+CYCLE_DMA_0_ = NODE,*,0,-;
+CLK_000_N_SYNC_10_ = NODE,*,7,-;
+CLK_000_N_SYNC_9_ = NODE,*,3,-;
+CLK_000_N_SYNC_8_ = NODE,*,1,-;
+CLK_000_N_SYNC_7_ = NODE,*,6,-;
+CLK_000_N_SYNC_6_ = NODE,*,0,-;
+CLK_000_N_SYNC_5_ = NODE,*,0,-;
+CLK_000_N_SYNC_4_ = NODE,*,3,-;
+CLK_000_N_SYNC_3_ = NODE,*,3,-;
+CLK_000_N_SYNC_2_ = NODE,*,5,-;
+CLK_000_N_SYNC_1_ = NODE,*,5,-;
+CLK_000_N_SYNC_0_ = NODE,*,6,-;
+CLK_000_P_SYNC_8_ = NODE,*,6,-;
+CLK_000_P_SYNC_7_ = NODE,*,1,-;
+CLK_000_P_SYNC_6_ = NODE,*,5,-;
+CLK_000_P_SYNC_5_ = NODE,*,1,-;
+CLK_000_P_SYNC_4_ = NODE,*,4,-;
+CLK_000_P_SYNC_3_ = NODE,*,5,-;
+CLK_000_P_SYNC_2_ = NODE,*,5,-;
+CLK_000_P_SYNC_1_ = NODE,*,1,-;
+CLK_000_P_SYNC_0_ = NODE,*,1,-;
+IPL_D0_2_ = NODE,*,1,-;
+IPL_D0_1_ = NODE,*,1,-;
+IPL_D0_0_ = NODE,*,1,-;
+CLK_000_N_SYNC_11_ = NODE,*,7,-;
+CLK_000_P_SYNC_9_ = NODE,*,5,-;
+inst_CLK_OUT_EXP_INT = NODE,*,4,-;
+inst_DTACK_D0 = NODE,*,0,-;
+CLK_OSZI = INPUT,61,-,-;
diff --git a/Logic/68030_tk.vco b/Logic/68030_tk.vco
new file mode 100644
index 0000000..c5fcf75
--- /dev/null
+++ b/Logic/68030_tk.vco
@@ -0,0 +1,270 @@
+[DEVICE]
+
+Family = M4A5;
+PartType = M4A5-128/64;
+Package = 100TQFP;
+PartNumber = M4A5-128/64-10VC;
+Speed = -10;
+Operating_condition = COM;
+EN_Segment = NO;
+Pin_MC_1to1 = NO;
+Voltage = 5.0;
+
+[REVISION]
+
+RCS = "$Revision: 1.2 $";
+Parent = m4a5.lci;
+SDS_file = m4a5.sds;
+Design = 68030_tk.tt4;
+Rev = 0.01;
+DATE = 1/24/16;
+TIME = 16:20:59;
+Type = TT2;
+Pre_Fit_Time = 1;
+Source_Format = Pure_VHDL;
+
+[IGNORE ASSIGNMENTS]
+
+Pin_Assignments = NO;
+Pin_Keep_Block = NO;
+Pin_Keep_Segment = NO;
+Group_Assignments = NO;
+Macrocell_Assignments = NO;
+Macrocell_Keep_Block = NO;
+Macrocell_Keep_Segment = NO;
+Pin_Reservation = NO;
+Timing_Constraints = NO;
+Block_Reservation = NO;
+Segment_Reservation = NO;
+Ignore_Source_Location = NO;
+Ignore_Source_Optimization = NO;
+Ignore_Source_Timing = NO;
+
+[CLEAR ASSIGNMENTS]
+
+Pin_Assignments = NO;
+Pin_Keep_Block = NO;
+Pin_Keep_Segment = NO;
+Group_Assignments = NO;
+Macrocell_Assignments = NO;
+Macrocell_Keep_Block = NO;
+Macrocell_Keep_Segment = NO;
+Pin_Reservation = NO;
+Timing_Constraints = NO;
+Block_Reservation = NO;
+Segment_Reservation = NO;
+Ignore_Source_Location = NO;
+Ignore_Source_Optimization = NO;
+Ignore_Source_Timing = NO;
+
+[BACKANNOTATE NETLIST]
+
+Netlist = VHDL;
+Delay_File = SDF;
+Generic_VCC = ;
+Generic_GND = ;
+
+[BACKANNOTATE ASSIGNMENTS]
+
+Pin_Assignment = NO;
+Pin_Block = NO;
+Pin_Macrocell_Block = NO;
+Routing = NO;
+
+[GLOBAL PROJECT OPTIMIZATION]
+
+Balanced_Partitioning = YES;
+Spread_Placement = YES;
+Max_Pin_Percent = 100;
+Max_Macrocell_Percent = 100;
+Max_Inter_Seg_Percent = 100;
+Max_Seg_In_Percent = 100;
+Max_Blk_In_Percent = 100;
+
+[FITTER REPORT FORMAT]
+
+Fitter_Options = YES;
+Pinout_Diagram = NO;
+Pinout_Listing = YES;
+Detailed_Block_Segment_Summary = YES;
+Input_Signal_List = YES;
+Output_Signal_List = YES;
+Bidir_Signal_List = YES;
+Node_Signal_List = YES;
+Signal_Fanout_List = YES;
+Block_Segment_Fanin_List = YES;
+Prefit_Eqn = YES;
+Postfit_Eqn = YES;
+Page_Break = YES;
+
+[OPTIMIZATION OPTIONS]
+
+Logic_Reduction = YES;
+Max_PTerm_Split = 16;
+Max_PTerm_Collapse = 16;
+XOR_Synthesis = YES;
+Node_Collapse = Yes;
+DT_Synthesis = Yes;
+
+[FITTER GLOBAL OPTIONS]
+
+Run_Time = 0;
+Set_Reset_Dont_Care = NO;
+In_Reg_Optimize = YES;
+Clock_Optimize = NO;
+Conf_Unused_IOs = OUT_LOW;
+
+[POWER]
+Powerlevel = Low, High;
+Default = High;
+Low = 8, H, G, F, E, D, C, B, A;
+Type = GLB;
+
+[HARDWARE DEVICE OPTIONS]
+Zero_Hold_Time = Yes;
+Signature_Word = 0;
+Pull_up = Yes;
+Out_Slew_Rate = SLOW, FAST, 7, CLK_DIV_OUT, CLK_EXP, FPU_CS, AMIGA_BUS_DATA_DIR, AMIGA_BUS_ENABLE_LOW, 
+	AMIGA_ADDR_ENABLE, AMIGA_BUS_ENABLE_HIGH;
+Device_max_fanin = 33;
+Device_max_pterms = 20;
+Usercode_Format = Hex;
+
+[PIN RESERVATIONS]
+layer = OFF;
+
+[LOCATION ASSIGNMENT]
+
+Layer = OFF;
+SIZE_1_ = BIDIR,79, H,-;
+A_31_ = INPUT,4, B,-;
+IPL_2_ = INPUT,68, G,-;
+FC_1_ = INPUT,58, F,-;
+IPL_1_ = INPUT,56, F,-;
+AS_030 = BIDIR,82, H,-;
+IPL_0_ = INPUT,67, G,-;
+AS_000 = BIDIR,42, E,-;
+FC_0_ = INPUT,57, F,-;
+DS_030 = OUTPUT,98, A,-;
+UDS_000 = BIDIR,32, D,-;
+LDS_000 = BIDIR,31, D,-;
+A1 = INPUT,60, F,-;
+nEXP_SPACE = INPUT,14,-,-;
+BERR = BIDIR,41, E,-;
+BG_030 = INPUT,21, C,-;
+BGACK_000 = INPUT,28, D,-;
+CLK_030 = INPUT,64,-,-;
+CLK_000 = INPUT,11,-,-;
+CLK_OSZI = INPUT,61,-,-;
+CLK_EXP = OUTPUT,10, B,-;
+FPU_CS = OUTPUT,78, H,-;
+FPU_SENSE = INPUT,91, A,-;
+DTACK = INPUT,30, D,-;
+AVEC = OUTPUT,92, A,-;
+E = OUTPUT,66, G,-;
+VPA = INPUT,36,-,-;
+RST = INPUT,86,-,-;
+RESET = OUTPUT,3, B,-;
+AMIGA_ADDR_ENABLE = OUTPUT,33, D,-;
+AMIGA_BUS_DATA_DIR = OUTPUT,48, E,-;
+SIZE_0_ = BIDIR,70, G,-;
+AMIGA_BUS_ENABLE_LOW = OUTPUT,20, C,-;
+A_30_ = INPUT,5, B,-;
+AMIGA_BUS_ENABLE_HIGH = OUTPUT,34, D,-;
+A_29_ = INPUT,6, B,-;
+CIIN = OUTPUT,47, E,-;
+A_28_ = INPUT,15, C,-;
+A_27_ = INPUT,16, C,-;
+A_26_ = INPUT,17, C,-;
+A_25_ = INPUT,18, C,-;
+A_24_ = INPUT,19, C,-;
+A_23_ = INPUT,85, H,-;
+A_22_ = INPUT,84, H,-;
+A_21_ = INPUT,94, A,-;
+A_20_ = INPUT,93, A,-;
+A_19_ = INPUT,97, A,-;
+A_18_ = INPUT,95, A,-;
+A_17_ = INPUT,59, F,-;
+A_16_ = INPUT,96, A,-;
+IPL_030_2_ = OUTPUT,9, B,-;
+IPL_030_1_ = OUTPUT,7, B,-;
+IPL_030_0_ = OUTPUT,8, B,-;
+RW_000 = BIDIR,80, H,-;
+A0 = BIDIR,69, G,-;
+BG_000 = OUTPUT,29, D,-;
+BGACK_030 = OUTPUT,83, H,-;
+CLK_DIV_OUT = OUTPUT,65, G,-;
+DSACK1 = OUTPUT,81, H,-;
+VMA = OUTPUT,35, D,-;
+RW = BIDIR,71, G,-;
+cpu_est_0_ = NODE,10, D,-;
+cpu_est_1_ = NODE,6, D,-;
+cpu_est_2_ = NODE,13, D,-;
+cpu_est_3_ = NODE,2, D,-;
+inst_AS_000_INT = NODE,13, B,-;
+SM_AMIGA_5_ = NODE,4, F,-;
+inst_AMIGA_BUS_ENABLE_DMA_LOW = NODE,9, B,-;
+inst_AS_030_D0 = NODE,13, H,-;
+inst_nEXP_SPACE_D0reg = NODE,5, H,-;
+inst_AS_030_000_SYNC = NODE,5, C,-;
+inst_BGACK_030_INT_D = NODE,8, E,-;
+inst_AS_000_DMA = NODE,12, A,-;
+inst_DS_000_DMA = NODE,9, A,-;
+CYCLE_DMA_0_ = NODE,6, A,-;
+CYCLE_DMA_1_ = NODE,2, A,-;
+SIZE_DMA_0_ = NODE,2, G,-;
+SIZE_DMA_1_ = NODE,13, G,-;
+inst_VPA_D = NODE,1, C,-;
+inst_UDS_000_INT = NODE,5, A,-;
+inst_LDS_000_INT = NODE,1, A,-;
+inst_CLK_OUT_PRE_D = NODE,3, D,-;
+inst_DTACK_D0 = NODE,3, A,-;
+inst_RESET_OUT = NODE,5, G,-;
+inst_CLK_OUT_PRE_50 = NODE,5, E,-;
+N_210_i = NODE,9, C,-;
+inst_CLK_OUT_PRE_25 = NODE,6, G,-;
+inst_CLK_000_D1 = NODE,8, C,-;
+inst_CLK_000_D0 = NODE,9, D,-;
+inst_CLK_000_PE = NODE,0, F,-;
+inst_CLK_OUT_EXP_INT = NODE,2, E,-;
+CLK_000_P_SYNC_9_ = NODE,3, F,-;
+inst_CLK_000_NE = NODE,9, G,-;
+CLK_000_N_SYNC_11_ = NODE,6, H,-;
+IPL_D0_0_ = NODE,15, B,-;
+IPL_D0_1_ = NODE,11, B,-;
+IPL_D0_2_ = NODE,7, B,-;
+inst_CLK_000_NE_D0 = NODE,14, D,-;
+SM_AMIGA_0_ = NODE,1, F,-;
+inst_AMIGA_BUS_ENABLE_DMA_HIGH = NODE,5, B,-;
+SM_AMIGA_4_ = NODE,9, F,-;
+inst_DS_000_ENABLE = NODE,12, C,-;
+RST_DLY_0_ = NODE,14, G,-;
+RST_DLY_1_ = NODE,10, G,-;
+RST_DLY_2_ = NODE,3, G,-;
+CLK_000_P_SYNC_0_ = NODE,3, B,-;
+CLK_000_P_SYNC_1_ = NODE,14, B,-;
+CLK_000_P_SYNC_2_ = NODE,14, F,-;
+CLK_000_P_SYNC_3_ = NODE,10, F,-;
+CLK_000_P_SYNC_4_ = NODE,13, E,-;
+CLK_000_P_SYNC_5_ = NODE,10, B,-;
+CLK_000_P_SYNC_6_ = NODE,6, F,-;
+CLK_000_P_SYNC_7_ = NODE,6, B,-;
+CLK_000_P_SYNC_8_ = NODE,15, G,-;
+CLK_000_N_SYNC_0_ = NODE,11, G,-;
+CLK_000_N_SYNC_1_ = NODE,2, F,-;
+CLK_000_N_SYNC_2_ = NODE,13, F,-;
+CLK_000_N_SYNC_3_ = NODE,15, D,-;
+CLK_000_N_SYNC_4_ = NODE,11, D,-;
+CLK_000_N_SYNC_5_ = NODE,14, A,-;
+CLK_000_N_SYNC_6_ = NODE,10, A,-;
+CLK_000_N_SYNC_7_ = NODE,7, G,-;
+CLK_000_N_SYNC_8_ = NODE,2, B,-;
+CLK_000_N_SYNC_9_ = NODE,7, D,-;
+CLK_000_N_SYNC_10_ = NODE,2, H,-;
+SM_AMIGA_6_ = NODE,4, C,-;
+inst_CLK_030_H = NODE,13, A,-;
+SM_AMIGA_1_ = NODE,8, A,-;
+SM_AMIGA_3_ = NODE,5, F,-;
+SM_AMIGA_2_ = NODE,12, F,-;
+SM_AMIGA_i_7_ = NODE,8, F,-;
+CIIN_0 = NODE,9, E,-;
diff --git a/Logic/68030_tk.vct b/Logic/68030_tk.vct
new file mode 100644
index 0000000..c26f14d
--- /dev/null
+++ b/Logic/68030_tk.vct
@@ -0,0 +1,221 @@
+[DEVICE]
+Family = M4A5;
+PartType = M4A5-128/64;
+Package = 100TQFP;
+PartNumber = M4A5-128/64-10VC;
+Speed = -10;
+Operating_condition = COM;
+EN_Segment = No;
+Pin_MC_1to1 = No;
+EN_PinReserve_IO = Yes;
+EN_PinReserve_BIDIR = Yes;
+Voltage = 5.0;
+
+[REVISION]
+RCS = "$Revision: 1.2 $";
+Parent = m4a5.lci;
+SDS_File = m4a5.sds;
+DATE = 03/16/2015;
+TIME = 21:53:52;
+Source_Format = Pure_VHDL;
+Type = TT2;
+Pre_Fit_Time = 1;
+
+[IGNORE ASSIGNMENTS]
+Pin_Assignments = No;
+Pin_Keep_Block = No;
+Pin_Keep_Segment = No;
+Group_Assignments = No;
+Macrocell_Assignments = No;
+Macrocell_Keep_Block = No;
+Macrocell_Keep_Segment = No;
+Pin_Reservation = No;
+Block_Reservation = No;
+Segment_Reservation = No;
+Timing_Constraints = No;
+
+[CLEAR ASSIGNMENTS]
+Pin_Assignments = No;
+Pin_Keep_Block = No;
+Pin_Keep_Segment = No;
+Group_Assignments = No;
+Macrocell_Assignments = No;
+Macrocell_Keep_Block = No;
+Macrocell_Keep_Segment = No;
+Pin_Reservation = No;
+Block_Reservation = No;
+Segment_Reservation = No;
+Timing_Constraints = No;
+
+[BACKANNOTATE ASSIGNMENTS]
+Pin_Block = No;
+Pin_Macrocell_Block = No;
+Routing = No;
+
+[GLOBAL PROJECT OPTIMIZATION]
+Balanced_Partitioning = Yes;
+Spread_Placement = Yes;
+Max_Pin_Percent = 100;
+Max_Macrocell_Percent = 100;
+Max_Blk_In_Percent = 100;
+
+[OPTIMIZATION OPTIONS]
+Logic_Reduction = Yes;
+Max_PTerm_Split = 16;
+Max_PTerm_Collapse = 16;
+XOR_Synthesis = Yes;
+EN_XOR_Synthesis = Yes;
+XOR_Gate = Yes;
+Node_Collapse = Yes;
+Keep_XOR = Yes;
+DT_Synthesis = Yes;
+Clock_PTerm = Min;
+Reset_PTerm = On;
+Preset_PTerm = On;
+Clock_Enable_PTerm = On;
+Output_Enable_PTerm = On;
+EN_DT_Synthesis = Yes;
+Cluster_PTerm = 5;
+FF_inv = No;
+EN_Use_CE = No;
+Use_CE = No;
+Use_Internal_COM_FB = Yes;
+EN_use_Internal_COM_FB = Yes;
+Set_Reset_Swap = No;
+EN_Set_Reset_Swap = No;
+Density = No;
+DeMorgan = Yes;
+T_FF = Yes;
+Max_Symbols = 32;
+
+[FITTER GLOBAL OPTIONS]
+Run_Time = 0;
+Set_Reset_Dont_Care = No;
+EN_Set_Reset_Dont_Care = Yes;
+In_Reg_Optimize = Yes;
+EN_In_Reg_Optimize = No;
+Clock_Optimize = No;
+Global_Clock_As_Pterm = No;
+Show_Iterations = No;
+Routing_Attempts = 2;
+Conf_Unused_IOs = Out_Low;
+
+[HARDWARE DEVICE OPTIONS]
+Zero_Hold_Time = Yes;
+Signature_Word = 0;
+Pull_up = Yes;
+Out_Slew_Rate = SLOW,FAST,7,CLK_DIV_OUT,CLK_EXP,FPU_CS,AMIGA_BUS_DATA_DIR,AMIGA_BUS_ENABLE_LOW,AMIGA_ADDR_ENABLE,AMIGA_BUS_ENABLE_HIGH;
+Device_max_fanin = 33;
+Device_max_pterms = 20;
+Usercode_Format = Hex;
+
+[PIN RESERVATIONS]
+Layer = OFF;
+
+[LOCATION ASSIGNMENT]
+Layer = OFF;
+AS_030 = input,82,H,-;
+A_16_ = input,96,A,-;
+A_17_ = input,59,F,-;
+A_18_ = input,95,A,-;
+A_19_ = input,97,A,-;
+BGACK_000 = input,28,D,-;
+BG_030 = input,21,C,-;
+CLK_000 = input,11,-,-;
+CLK_030 = input,64,-,-;
+CLK_OSZI = input,61,-,-;
+FC_0_ = input,57,F,-;
+FC_1_ = input,58,F,-;
+IPL_0_ = input,67,G,-;
+IPL_1_ = input,56,F,-;
+IPL_2_ = input,68,G,-;
+RST = input,86,-,-;
+RW = input,71,G,-;
+SIZE_1_ = input,79,H,-;
+SIZE_0_ = input,70,G,-;
+VPA = input,36,-,-;
+AVEC = input,92,A,-;
+BGACK_030 = input,83,H,-;
+BG_000 = input,29,D,-;
+CLK_DIV_OUT = input,65,G,-;
+CLK_EXP = input,10,B,-;
+E = input,66,G,-;
+FPU_CS = input,78,H,-;
+IPL_030_0_ = input,8,B,-;
+IPL_030_1_ = input,7,B,-;
+IPL_030_2_ = input,9,B,-;
+LDS_000 = input,31,D,-;
+UDS_000 = input,32,D,-;
+VMA = input,35,D,-;
+DTACK = input,30,D,-;
+RESET = input,3,B,-;
+AMIGA_BUS_DATA_DIR = input,48,E,-;
+AMIGA_BUS_ENABLE_LOW = input,20,C,-;
+CIIN = input,47,E,-;
+A_20_ = input,93,A,-;
+A_21_ = input,94,A,-;
+A_22_ = input,84,H,-;
+A_24_ = input,19,C,-;
+A_25_ = input,18,C,-;
+A_26_ = input,17,C,-;
+A_27_ = input,16,C,-;
+A_28_ = input,15,C,-;
+A_29_ = input,6,B,-;
+A_30_ = input,5,B,-;
+A_31_ = input,4,B,-;
+DS_030 = input,98,A,-;
+BERR = input,41,E,-;
+nEXP_SPACE = input,14,-,-;
+A0 = input,69,G,-;
+DSACK1 = input,81,H,-;
+RW_000 = input,80,H,-;
+AS_000 = input,42,E,-;
+AMIGA_ADDR_ENABLE = input,33,D,-;
+AMIGA_BUS_ENABLE_HIGH = input,34,D,-;
+A_23_ = input,85,H,-;
+FPU_SENSE = input,91,A,-;
+A1 = input,60,F,-;
+A_3_ = input,44,E,-;
+A_2_ = input,43,E,-;
+
+[GROUP ASSIGNMENT]
+Layer = OFF;
+
+[SPACE RESERVATIONS]
+Layer = OFF;
+
+[BACKANNOTATE NETLIST]
+Delay_File = SDF;
+Netlist = VHDL;
+VCC_GND = Cell;
+
+[FITTER REPORT FORMAT]
+Fitter_Options = Yes;
+Pinout_Diagram = No;
+Pinout_Listing = Yes;
+Detailed_Block_Segment_Summary = Yes;
+Input_Signal_List = Yes;
+Output_Signal_List = Yes;
+Bidir_Signal_List = Yes;
+Node_Signal_List = Yes;
+Signal_Fanout_List = Yes;
+Block_Segment_Fanin_List = Yes;
+Postfit_Eqn = Yes;
+Page_Break = Yes;
+
+[POWER]
+Powerlevel =  Low,High;
+Default = High;
+Low = 8,H,G,F,E,D,C,B,A;
+Type = GLB;
+
+[SOURCE CONSTRAINT OPTION]
+Import_source_constraint = Yes;
+Disable_warning_message = No;
+
+[TIMING ANALYZER]
+Last_source=;
+Last_source_type=Fmax;
+
+[INPUT REGISTERS]
+
diff --git a/Logic/68030_tk.xrf b/Logic/68030_tk.xrf
new file mode 100644
index 0000000..de2340b
--- /dev/null
+++ b/Logic/68030_tk.xrf
@@ -0,0 +1,16 @@
+Signal Name Cross Reference File
+
+ispLEVER Classic 1.8.00.04.29.14
+
+Design '68030_tk' created Sun Jan 24 16:20:54 2016
+
+
+ LEGEND:  '>'  Functional Block Port Separator
+          '/'  Hierarchy Path Separator
+          '@'  Automatically Generated Node
+
+
+Short Name                              Hierarchical Name
+----------                              -----------------
+
+ *** Shortened names not required for this design. ***
diff --git a/Logic/BUS68030.bl0 b/Logic/BUS68030.bl0
new file mode 100644
index 0000000..5ce81bf
--- /dev/null
+++ b/Logic/BUS68030.bl0
@@ -0,0 +1,1881 @@
+#$ DATE Sun Jan 24 16:20:54 2016
+#$ TOOL EDIF2BLIF version IspLever 1.0 
+#$ MODULE bus68030
+#$ PINS 75 A_9_ A_8_ SIZE_1_ A_7_ A_6_ A_31_ A_5_ A_4_ IPL_030_2_ A_3_ A_2_ IPL_2_ IPL_030_1_ IPL_030_0_ FC_1_ IPL_1_ AS_030 IPL_0_ AS_000 FC_0_ RW_000 DS_030 UDS_000 LDS_000 A0 A1 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR SIZE_0_ AMIGA_BUS_ENABLE_LOW A_30_ AMIGA_BUS_ENABLE_HIGH A_29_ CIIN A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ A_19_ A_18_ A_17_ A_16_ A_15_ A_14_ A_13_ A_12_ A_11_ A_10_
+#$ NODES 681 N_184 N_184_0 rw_000_dma_0_un1_n N_180 N_185_0 rw_000_dma_0_un0_n N_179 UDS_000_c_i a0_dma_0_un3_n pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2 \
+#  LDS_000_c_i a0_dma_0_un1_n N_312 N_173_i a0_dma_0_un0_n N_270 N_358_0 amiga_bus_enable_dma_low_0_un3_n inst_BGACK_030_INTreg N_357 \
+#  N_239_i amiga_bus_enable_dma_low_0_un1_n inst_CLK_OUT_INTreg N_354 pos_clk_size_dma_6_0_1__n amiga_bus_enable_dma_low_0_un0_n vcc_n_n N_227 N_238_i amiga_bus_enable_dma_high_0_un3_n \
+#  un5_e N_378 pos_clk_size_dma_6_0_0__n amiga_bus_enable_dma_high_0_un1_n inst_VMA_INTreg N_29 N_237_i amiga_bus_enable_dma_high_0_un0_n gnd_n_n N_28 \
+#  N_236_i cpu_est_0_2__un3_n un1_amiga_bus_enable_low N_3 AMIGA_BUS_DATA_DIR_c_0 cpu_est_0_2__un1_n un3_size N_5 N_331_i cpu_est_0_2__un0_n \
+#  un4_size N_7 pos_clk_un6_bgack_000_0_n cpu_est_0_3__un3_n un4_uds_000 N_190_i N_356_0 cpu_est_0_3__un1_n un4_lds_000 un1_amiga_bus_enable_low_i \
+#  N_352_0 cpu_est_0_3__un0_n un5_ciin un21_fpu_cs_i N_8_i ipl_030_0_0__un3_n un4_as_000 CLK_OUT_EXP_INT_i N_46_0 ipl_030_0_0__un1_n \
+#  un1_SM_AMIGA_5 AS_000_i N_10_i ipl_030_0_0__un0_n un21_fpu_cs DS_000_DMA_i N_44_0 rw_000_int_0_un3_n un22_berr sm_amiga_i_5__n \
+#  N_19_i rw_000_int_0_un1_n un6_ds_030 sm_amiga_i_6__n N_41_0 rw_000_int_0_un0_n cpu_est_0_ sm_amiga_i_0__n N_20_i uds_000_int_0_un3_n \
+#  cpu_est_1_ CLK_000_NE_i N_40_0 uds_000_int_0_un1_n cpu_est_2_ sm_amiga_i_4__n N_24_i uds_000_int_0_un0_n cpu_est_3_ RW_000_i \
+#  N_36_0 vma_int_0_un3_n inst_AS_000_INT sm_amiga_i_2__n N_25_i vma_int_0_un1_n SM_AMIGA_5_ CLK_000_D0_i N_35_0 vma_int_0_un0_n \
+#  inst_AMIGA_BUS_ENABLE_DMA_LOW BERR_i bg_000_0_un3_n inst_AS_030_D0 sm_amiga_i_1__n N_198_i bg_000_0_un1_n inst_nEXP_SPACE_D0reg CLK_000_PE_i N_243_2_i \
+#  bg_000_0_un0_n inst_AS_030_000_SYNC N_410_i_0 N_196_i cpu_est_0_1__un3_n inst_BGACK_030_INT_D sm_amiga_i_i_7__n N_195_i cpu_est_0_1__un1_n inst_AS_000_DMA \
+#  AS_030_i cpu_est_0_1__un0_n inst_DS_000_DMA FPU_SENSE_i N_201_i dsack1_int_0_un3_n CYCLE_DMA_0_ nEXP_SPACE_D0_i N_200_i dsack1_int_0_un1_n \
+#  CYCLE_DMA_1_ BGACK_030_INT_i N_199_i dsack1_int_0_un0_n SIZE_DMA_0_ AMIGA_BUS_ENABLE_DMA_HIGH_i N_182_0 ds_000_enable_0_un3_n SIZE_DMA_1_ A1_i \
+#  N_158_i ds_000_enable_0_un1_n inst_VPA_D CLK_030_H_i N_148_i ds_000_enable_0_un0_n inst_UDS_000_INT a_i_16__n N_307_i lds_000_int_0_un3_n \
+#  inst_LDS_000_INT a_i_18__n N_143_0 lds_000_int_0_un1_n inst_CLK_OUT_PRE_D a_i_19__n N_217_i lds_000_int_0_un0_n inst_DTACK_D0 N_114_i \
+#  N_235_i a_15__n inst_RESET_OUT N_113_i inst_CLK_OUT_PRE_50 AS_000_INT_i N_210_i a_14__n inst_CLK_OUT_PRE_25 AMIGA_BUS_ENABLE_DMA_LOW_i \
+#  inst_CLK_000_D1 rst_dly_i_2__n N_207_i a_13__n inst_CLK_000_D0 rst_dly_i_0__n N_208_i inst_CLK_000_PE rst_dly_i_1__n N_206_i \
+#  a_12__n inst_CLK_OUT_EXP_INT RESET_OUT_i CLK_000_P_SYNC_9_ size_dma_i_1__n N_313_i a_11__n inst_CLK_000_NE size_dma_i_0__n N_211_i \
+#  CLK_000_N_SYNC_11_ AS_030_D0_i N_212_i a_10__n IPL_D0_0_ a_i_24__n N_183_0 IPL_D0_1_ sm_amiga_i_3__n N_181_0 \
+#  a_9__n IPL_D0_2_ cpu_est_i_3__n N_178_0 inst_CLK_000_NE_D0 cpu_est_i_0__n N_69_0 a_8__n SM_AMIGA_0_ VPA_D_i \
+#  N_329_i inst_AMIGA_BUS_ENABLE_DMA_HIGH cpu_est_i_1__n N_176_i a_7__n inst_DSACK1_INTreg CLK_030_i N_175_0 pos_clk_ipl_n CLK_000_D1_i \
+#  N_174_0 a_6__n SM_AMIGA_4_ cpu_est_i_2__n N_171_0 inst_DS_000_ENABLE DTACK_D0_i un1_SM_AMIGA_5_i a_5__n RST_DLY_0_ \
+#  RW_i N_324_i RST_DLY_1_ a_i_31__n N_326_i a_4__n RST_DLY_2_ a_i_29__n N_168_i pos_clk_un8_bg_030_n \
+#  a_i_30__n VMA_INT_i a_3__n CLK_000_P_SYNC_0_ a_i_27__n N_165_i CLK_000_P_SYNC_1_ a_i_28__n N_164_i a_2__n \
+#  CLK_000_P_SYNC_2_ a_i_25__n N_162_i CLK_000_P_SYNC_3_ a_i_26__n clk_000_n_sync_i_10__n CLK_000_P_SYNC_4_ N_213_i N_321_i CLK_000_P_SYNC_5_ \
+#  N_214_i N_159_0 CLK_000_P_SYNC_6_ N_215_i N_318_i CLK_000_P_SYNC_7_ N_156_i CLK_000_P_SYNC_8_ DS_000_ENABLE_1_sqmuxa_i N_155_i \
+#  CLK_000_N_SYNC_0_ N_98_i N_154_i CLK_000_N_SYNC_1_ un6_ds_030_i CLK_OUT_PRE_D_i CLK_000_N_SYNC_2_ un4_as_000_i N_152_0 CLK_000_N_SYNC_3_ \
+#  un4_lds_000_i N_150_i CLK_000_N_SYNC_4_ un4_uds_000_i AS_030_000_SYNC_i CLK_000_N_SYNC_5_ LDS_000_INT_i N_147_i CLK_000_N_SYNC_6_ UDS_000_INT_i \
+#  N_145_i CLK_000_N_SYNC_7_ AS_030_c N_281_i CLK_000_N_SYNC_8_ N_302_i CLK_000_N_SYNC_9_ AS_000_c CLK_000_N_SYNC_10_ N_279_i \
+#  inst_RW_000_INT RW_000_c N_280_i inst_RW_000_DMA un5_e_0 pos_clk_un7_clk_000_pe_n N_278_i inst_A0_DMA UDS_000_c cpu_est_2_0_3__n \
+#  SM_AMIGA_6_ N_277_i DS_000_ENABLE_1_sqmuxa LDS_000_c N_348_i inst_CLK_030_H cpu_est_2_0_2__n SM_AMIGA_1_ size_c_0__n N_128_i \
+#  SM_AMIGA_3_ N_193_i SM_AMIGA_2_ size_c_1__n N_241_i pos_clk_un3_as_030_d0_n DS_000_ENABLE_1_sqmuxa_1 N_240_i N_4 N_124_0 \
+#  N_6 N_269_0 un5_ciin_i N_61_0 un1_as_030_i N_17 N_228_i N_18 N_355_0 N_21 \
+#  N_226_i N_22 N_26 N_224_i N_27 N_225_i CLK_OUT_PRE_25_0 N_282_0 N_221_i N_222_i \
+#  N_219_i N_220_i N_283_0 N_216_i N_218_i cpu_est_2_0_1__n N_373_i N_375_i pos_clk_un7_clk_000_pe_0_n N_188_i \
+#  a_c_16__n N_205_i a_c_17__n pos_clk_un8_sm_amiga_i_n A0_c_i a_c_18__n size_c_i_1__n N_27_i a_c_19__n N_31_0 \
+#  ipl_c_i_0__n a_c_20__n N_52_0 N_4_i a_c_21__n N_49_0 N_17_i SM_AMIGA_i_7_ a_c_22__n N_43_0 \
+#  N_124 N_18_i cpu_est_2_1__n a_c_23__n N_42_0 cpu_est_2_2__n N_21_i cpu_est_2_3__n a_c_24__n N_39_0 \
+#  G_134 N_22_i G_135 a_c_25__n N_38_0 G_136 N_26_i N_269 a_c_26__n N_34_0 \
+#  N_61 BG_030_c_i a_c_27__n pos_clk_un8_bg_030_0_n N_98 N_161_i_1 a_c_28__n N_161_i_2 pos_clk_un8_sm_amiga_i_1_n N_355 \
+#  a_c_29__n N_324_1 N_324_2 N_128 a_c_30__n N_150_i_1 N_137 un1_SM_AMIGA_5_i_1 N_145 a_c_31__n \
+#  un1_SM_AMIGA_5_i_2 N_148 N_138_i_1 N_150 A0_c N_138_i_2 N_152 N_146_i_1 N_154 A1_c \
+#  N_146_i_2 N_156 N_146_i_3 N_159 nEXP_SPACE_c N_220_1 N_161 N_220_2 N_165 BERR_c \
+#  N_375_1 N_168 N_375_2 N_171 BG_030_c N_373_1 N_174 N_373_2 N_175 BG_000DFFreg \
+#  N_210_1 N_178 N_210_2 N_181 N_210_3 N_183 BGACK_000_c un5_ciin_1 N_188 un5_ciin_2 \
+#  N_190 CLK_030_c un5_ciin_3 N_193 un5_ciin_4 N_195 un5_ciin_5 N_200 un5_ciin_6 N_205 \
+#  CLK_OSZI_c un5_ciin_7 N_206 un5_ciin_8 N_207 un5_ciin_9 N_208 un5_ciin_10 N_210 un5_ciin_11 \
+#  N_211 FPU_SENSE_c N_302_1 N_212 N_244_i_1 N_373 IPL_030DFF_0_reg N_244_i_2 N_375 N_243_i_1 \
+#  N_216 IPL_030DFF_1_reg N_410_1 N_218 N_410_2 N_219 IPL_030DFF_2_reg N_410_3 N_220 N_410_4 \
+#  N_221 ipl_c_0__n N_237_1 N_222 N_237_2 N_224 ipl_c_1__n un21_fpu_cs_1 N_225 un22_berr_1_0 \
+#  N_226 ipl_c_2__n N_233_1 N_228 N_233_2 N_230 N_245_i_1 N_231 DTACK_c N_128_i_1 \
+#  N_240 N_134_i_1 N_241 N_124_0_1 N_277 N_267_i_1 N_278 VPA_c N_268_i_1 N_279 \
+#  N_355_0_1 N_280 N_353_i_1 N_281 RST_c N_140_i_1 N_302 N_142_i_1 N_313 N_280_1 \
+#  N_318 RW_c N_225_1 N_321 N_224_1 N_324 fc_c_0__n N_219_1 N_326 N_218_1 \
+#  N_329 fc_c_1__n N_212_1 N_332 N_208_1 N_348 N_207_1 cpu_est_0_0_x2_0_x2_0_ AMIGA_BUS_DATA_DIR_c N_200_1 \
+#  pos_clk_CYCLE_DMA_5_0_i_0_x2 N_195_1 pos_clk_CYCLE_DMA_5_1_i_0_x2 pos_clk_ipl_1_n N_235 ipl_030_0_1__un3_n N_196 ipl_030_0_1__un1_n N_143 N_7_i \
+#  ipl_030_0_1__un0_n N_158 N_47_0 as_030_000_sync_0_un3_n N_198 N_5_i as_030_000_sync_0_un1_n N_199 N_48_0 as_030_000_sync_0_un0_n \
+#  N_307 N_3_i as_000_int_0_un3_n N_201 N_50_0 as_000_int_0_un1_n N_182 nEXP_SPACE_c_i as_000_int_0_un0_n N_243_2 \
+#  N_55_0 ds_000_dma_0_un3_n N_8 VPA_c_i ds_000_dma_0_un1_n N_356 N_56_0 ds_000_dma_0_un0_n N_10 DTACK_c_i \
+#  ipl_030_0_2__un3_n pos_clk_un6_bgack_000_n N_57_0 ipl_030_0_2__un1_n N_19 ipl_c_i_1__n ipl_030_0_2__un0_n N_352 N_53_0 un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n \
+#  N_327 ipl_c_i_2__n un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n N_20 N_54_0 un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n pos_clk_a0_dma_3_n N_28_i sm_amiga_srsts_i_0_0_m3_1__un3_n N_24 \
+#  N_32_0 sm_amiga_srsts_i_0_0_m3_1__un1_n N_113 N_29_i sm_amiga_srsts_i_0_0_m3_1__un0_n N_25 N_33_0 sm_amiga_srsts_i_0_0_m3_5__un3_n N_114 N_378_i \
+#  sm_amiga_srsts_i_0_0_m3_5__un1_n pos_clk_size_dma_6_0__n sm_amiga_srsts_i_0_0_m3_5__un0_n N_232 size_dma_0_0__un3_n pos_clk_size_dma_6_1__n N_227_i size_dma_0_0__un1_n N_410 N_354_0 \
+#  size_dma_0_0__un0_n N_185 N_233_i size_dma_0_1__un3_n N_236 N_357_0 size_dma_0_1__un1_n N_238 N_270_0 size_dma_0_1__un0_n \
+#  N_173 AS_000_DMA_i as_000_dma_0_un3_n N_239 N_137_0 as_000_dma_0_un1_n N_331 N_312_i as_000_dma_0_un0_n N_237 \
+#  pos_clk_un3_as_030_d0_i_n bgack_030_int_0_un3_n un22_berr_1 N_161_i bgack_030_int_0_un1_n N_233 N_179_0 bgack_030_int_0_un0_n N_209 N_180_0 \
+#  rw_000_dma_0_un3_n 
+.model bus68030
+.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF \
+  CLK_OSZI.BLIF FPU_SENSE.BLIF DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \
+  A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF A_19_.BLIF A_18_.BLIF \
+  A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF \
+  A_8_.BLIF A_7_.BLIF A_6_.BLIF A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF \
+  FC_0_.BLIF SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_184.BLIF N_184_0.BLIF rw_000_dma_0_un1_n.BLIF N_180.BLIF N_185_0.BLIF rw_000_dma_0_un0_n.BLIF N_179.BLIF UDS_000_c_i.BLIF \
+  a0_dma_0_un3_n.BLIF pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2.BLIF LDS_000_c_i.BLIF a0_dma_0_un1_n.BLIF N_312.BLIF N_173_i.BLIF a0_dma_0_un0_n.BLIF N_270.BLIF N_358_0.BLIF \
+  amiga_bus_enable_dma_low_0_un3_n.BLIF inst_BGACK_030_INTreg.BLIF N_357.BLIF N_239_i.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF inst_CLK_OUT_INTreg.BLIF N_354.BLIF pos_clk_size_dma_6_0_1__n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF \
+  vcc_n_n.BLIF N_227.BLIF N_238_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF un5_e.BLIF N_378.BLIF pos_clk_size_dma_6_0_0__n.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF inst_VMA_INTreg.BLIF \
+  N_29.BLIF N_237_i.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF gnd_n_n.BLIF N_28.BLIF N_236_i.BLIF cpu_est_0_2__un3_n.BLIF un1_amiga_bus_enable_low.BLIF N_3.BLIF \
+  AMIGA_BUS_DATA_DIR_c_0.BLIF cpu_est_0_2__un1_n.BLIF un3_size.BLIF N_5.BLIF N_331_i.BLIF cpu_est_0_2__un0_n.BLIF un4_size.BLIF N_7.BLIF pos_clk_un6_bgack_000_0_n.BLIF \
+  cpu_est_0_3__un3_n.BLIF un4_uds_000.BLIF N_190_i.BLIF N_356_0.BLIF cpu_est_0_3__un1_n.BLIF un4_lds_000.BLIF un1_amiga_bus_enable_low_i.BLIF N_352_0.BLIF cpu_est_0_3__un0_n.BLIF \
+  un5_ciin.BLIF un21_fpu_cs_i.BLIF N_8_i.BLIF ipl_030_0_0__un3_n.BLIF un4_as_000.BLIF CLK_OUT_EXP_INT_i.BLIF N_46_0.BLIF ipl_030_0_0__un1_n.BLIF un1_SM_AMIGA_5.BLIF \
+  AS_000_i.BLIF N_10_i.BLIF ipl_030_0_0__un0_n.BLIF un21_fpu_cs.BLIF DS_000_DMA_i.BLIF N_44_0.BLIF rw_000_int_0_un3_n.BLIF un22_berr.BLIF sm_amiga_i_5__n.BLIF \
+  N_19_i.BLIF rw_000_int_0_un1_n.BLIF un6_ds_030.BLIF sm_amiga_i_6__n.BLIF N_41_0.BLIF rw_000_int_0_un0_n.BLIF cpu_est_0_.BLIF sm_amiga_i_0__n.BLIF N_20_i.BLIF \
+  uds_000_int_0_un3_n.BLIF cpu_est_1_.BLIF CLK_000_NE_i.BLIF N_40_0.BLIF uds_000_int_0_un1_n.BLIF cpu_est_2_.BLIF sm_amiga_i_4__n.BLIF N_24_i.BLIF uds_000_int_0_un0_n.BLIF \
+  cpu_est_3_.BLIF RW_000_i.BLIF N_36_0.BLIF vma_int_0_un3_n.BLIF inst_AS_000_INT.BLIF sm_amiga_i_2__n.BLIF N_25_i.BLIF vma_int_0_un1_n.BLIF SM_AMIGA_5_.BLIF \
+  CLK_000_D0_i.BLIF N_35_0.BLIF vma_int_0_un0_n.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF BERR_i.BLIF bg_000_0_un3_n.BLIF inst_AS_030_D0.BLIF sm_amiga_i_1__n.BLIF N_198_i.BLIF \
+  bg_000_0_un1_n.BLIF inst_nEXP_SPACE_D0reg.BLIF CLK_000_PE_i.BLIF N_243_2_i.BLIF bg_000_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF N_410_i_0.BLIF N_196_i.BLIF cpu_est_0_1__un3_n.BLIF \
+  inst_BGACK_030_INT_D.BLIF sm_amiga_i_i_7__n.BLIF N_195_i.BLIF cpu_est_0_1__un1_n.BLIF inst_AS_000_DMA.BLIF AS_030_i.BLIF cpu_est_0_1__un0_n.BLIF inst_DS_000_DMA.BLIF FPU_SENSE_i.BLIF \
+  N_201_i.BLIF dsack1_int_0_un3_n.BLIF CYCLE_DMA_0_.BLIF nEXP_SPACE_D0_i.BLIF N_200_i.BLIF dsack1_int_0_un1_n.BLIF CYCLE_DMA_1_.BLIF BGACK_030_INT_i.BLIF N_199_i.BLIF \
+  dsack1_int_0_un0_n.BLIF SIZE_DMA_0_.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF N_182_0.BLIF ds_000_enable_0_un3_n.BLIF SIZE_DMA_1_.BLIF A1_i.BLIF N_158_i.BLIF ds_000_enable_0_un1_n.BLIF \
+  inst_VPA_D.BLIF CLK_030_H_i.BLIF N_148_i.BLIF ds_000_enable_0_un0_n.BLIF inst_UDS_000_INT.BLIF a_i_16__n.BLIF N_307_i.BLIF lds_000_int_0_un3_n.BLIF inst_LDS_000_INT.BLIF \
+  a_i_18__n.BLIF N_143_0.BLIF lds_000_int_0_un1_n.BLIF inst_CLK_OUT_PRE_D.BLIF a_i_19__n.BLIF N_217_i.BLIF lds_000_int_0_un0_n.BLIF inst_DTACK_D0.BLIF N_114_i.BLIF \
+  N_235_i.BLIF a_15__n.BLIF inst_RESET_OUT.BLIF N_113_i.BLIF inst_CLK_OUT_PRE_50.BLIF AS_000_INT_i.BLIF N_210_i.BLIF a_14__n.BLIF inst_CLK_OUT_PRE_25.BLIF \
+  AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF inst_CLK_000_D1.BLIF rst_dly_i_2__n.BLIF N_207_i.BLIF a_13__n.BLIF inst_CLK_000_D0.BLIF rst_dly_i_0__n.BLIF N_208_i.BLIF inst_CLK_000_PE.BLIF \
+  rst_dly_i_1__n.BLIF N_206_i.BLIF a_12__n.BLIF inst_CLK_OUT_EXP_INT.BLIF RESET_OUT_i.BLIF CLK_000_P_SYNC_9_.BLIF size_dma_i_1__n.BLIF N_313_i.BLIF a_11__n.BLIF \
+  inst_CLK_000_NE.BLIF size_dma_i_0__n.BLIF N_211_i.BLIF CLK_000_N_SYNC_11_.BLIF AS_030_D0_i.BLIF N_212_i.BLIF a_10__n.BLIF IPL_D0_0_.BLIF a_i_24__n.BLIF \
+  N_183_0.BLIF IPL_D0_1_.BLIF sm_amiga_i_3__n.BLIF N_181_0.BLIF a_9__n.BLIF IPL_D0_2_.BLIF cpu_est_i_3__n.BLIF N_178_0.BLIF inst_CLK_000_NE_D0.BLIF \
+  cpu_est_i_0__n.BLIF N_69_0.BLIF a_8__n.BLIF SM_AMIGA_0_.BLIF VPA_D_i.BLIF N_329_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF cpu_est_i_1__n.BLIF N_176_i.BLIF \
+  a_7__n.BLIF inst_DSACK1_INTreg.BLIF CLK_030_i.BLIF N_175_0.BLIF pos_clk_ipl_n.BLIF CLK_000_D1_i.BLIF N_174_0.BLIF a_6__n.BLIF SM_AMIGA_4_.BLIF \
+  cpu_est_i_2__n.BLIF N_171_0.BLIF inst_DS_000_ENABLE.BLIF DTACK_D0_i.BLIF un1_SM_AMIGA_5_i.BLIF a_5__n.BLIF RST_DLY_0_.BLIF RW_i.BLIF N_324_i.BLIF \
+  RST_DLY_1_.BLIF a_i_31__n.BLIF N_326_i.BLIF a_4__n.BLIF RST_DLY_2_.BLIF a_i_29__n.BLIF N_168_i.BLIF pos_clk_un8_bg_030_n.BLIF a_i_30__n.BLIF \
+  VMA_INT_i.BLIF a_3__n.BLIF CLK_000_P_SYNC_0_.BLIF a_i_27__n.BLIF N_165_i.BLIF CLK_000_P_SYNC_1_.BLIF a_i_28__n.BLIF N_164_i.BLIF a_2__n.BLIF \
+  CLK_000_P_SYNC_2_.BLIF a_i_25__n.BLIF N_162_i.BLIF CLK_000_P_SYNC_3_.BLIF a_i_26__n.BLIF clk_000_n_sync_i_10__n.BLIF CLK_000_P_SYNC_4_.BLIF N_213_i.BLIF N_321_i.BLIF \
+  CLK_000_P_SYNC_5_.BLIF N_214_i.BLIF N_159_0.BLIF CLK_000_P_SYNC_6_.BLIF N_215_i.BLIF N_318_i.BLIF CLK_000_P_SYNC_7_.BLIF N_156_i.BLIF CLK_000_P_SYNC_8_.BLIF \
+  DS_000_ENABLE_1_sqmuxa_i.BLIF N_155_i.BLIF CLK_000_N_SYNC_0_.BLIF N_98_i.BLIF N_154_i.BLIF CLK_000_N_SYNC_1_.BLIF un6_ds_030_i.BLIF CLK_OUT_PRE_D_i.BLIF CLK_000_N_SYNC_2_.BLIF \
+  un4_as_000_i.BLIF N_152_0.BLIF CLK_000_N_SYNC_3_.BLIF un4_lds_000_i.BLIF N_150_i.BLIF CLK_000_N_SYNC_4_.BLIF un4_uds_000_i.BLIF AS_030_000_SYNC_i.BLIF CLK_000_N_SYNC_5_.BLIF \
+  LDS_000_INT_i.BLIF N_147_i.BLIF CLK_000_N_SYNC_6_.BLIF UDS_000_INT_i.BLIF N_145_i.BLIF CLK_000_N_SYNC_7_.BLIF AS_030_c.BLIF N_281_i.BLIF CLK_000_N_SYNC_8_.BLIF \
+  N_302_i.BLIF CLK_000_N_SYNC_9_.BLIF AS_000_c.BLIF CLK_000_N_SYNC_10_.BLIF N_279_i.BLIF inst_RW_000_INT.BLIF RW_000_c.BLIF N_280_i.BLIF inst_RW_000_DMA.BLIF \
+  un5_e_0.BLIF pos_clk_un7_clk_000_pe_n.BLIF N_278_i.BLIF inst_A0_DMA.BLIF UDS_000_c.BLIF cpu_est_2_0_3__n.BLIF SM_AMIGA_6_.BLIF N_277_i.BLIF DS_000_ENABLE_1_sqmuxa.BLIF \
+  LDS_000_c.BLIF N_348_i.BLIF inst_CLK_030_H.BLIF cpu_est_2_0_2__n.BLIF SM_AMIGA_1_.BLIF size_c_0__n.BLIF N_128_i.BLIF SM_AMIGA_3_.BLIF N_193_i.BLIF \
+  SM_AMIGA_2_.BLIF size_c_1__n.BLIF N_241_i.BLIF pos_clk_un3_as_030_d0_n.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF N_240_i.BLIF N_4.BLIF N_124_0.BLIF N_6.BLIF \
+  N_269_0.BLIF un5_ciin_i.BLIF N_61_0.BLIF un1_as_030_i.BLIF N_17.BLIF N_228_i.BLIF N_18.BLIF N_355_0.BLIF N_21.BLIF \
+  N_226_i.BLIF N_22.BLIF N_26.BLIF N_224_i.BLIF N_27.BLIF N_225_i.BLIF CLK_OUT_PRE_25_0.BLIF N_282_0.BLIF N_221_i.BLIF \
+  N_222_i.BLIF N_219_i.BLIF N_220_i.BLIF N_283_0.BLIF N_216_i.BLIF N_218_i.BLIF cpu_est_2_0_1__n.BLIF N_373_i.BLIF N_375_i.BLIF \
+  pos_clk_un7_clk_000_pe_0_n.BLIF N_188_i.BLIF a_c_16__n.BLIF N_205_i.BLIF a_c_17__n.BLIF pos_clk_un8_sm_amiga_i_n.BLIF A0_c_i.BLIF a_c_18__n.BLIF size_c_i_1__n.BLIF \
+  N_27_i.BLIF a_c_19__n.BLIF N_31_0.BLIF ipl_c_i_0__n.BLIF a_c_20__n.BLIF N_52_0.BLIF N_4_i.BLIF a_c_21__n.BLIF N_49_0.BLIF \
+  N_17_i.BLIF SM_AMIGA_i_7_.BLIF a_c_22__n.BLIF N_43_0.BLIF N_124.BLIF N_18_i.BLIF cpu_est_2_1__n.BLIF a_c_23__n.BLIF N_42_0.BLIF \
+  cpu_est_2_2__n.BLIF N_21_i.BLIF cpu_est_2_3__n.BLIF a_c_24__n.BLIF N_39_0.BLIF G_134.BLIF N_22_i.BLIF G_135.BLIF a_c_25__n.BLIF \
+  N_38_0.BLIF G_136.BLIF N_26_i.BLIF N_269.BLIF a_c_26__n.BLIF N_34_0.BLIF N_61.BLIF BG_030_c_i.BLIF a_c_27__n.BLIF \
+  pos_clk_un8_bg_030_0_n.BLIF N_98.BLIF N_161_i_1.BLIF a_c_28__n.BLIF N_161_i_2.BLIF pos_clk_un8_sm_amiga_i_1_n.BLIF N_355.BLIF a_c_29__n.BLIF N_324_1.BLIF \
+  N_324_2.BLIF N_128.BLIF a_c_30__n.BLIF N_150_i_1.BLIF N_137.BLIF un1_SM_AMIGA_5_i_1.BLIF N_145.BLIF a_c_31__n.BLIF un1_SM_AMIGA_5_i_2.BLIF \
+  N_148.BLIF N_138_i_1.BLIF N_150.BLIF A0_c.BLIF N_138_i_2.BLIF N_152.BLIF N_146_i_1.BLIF N_154.BLIF A1_c.BLIF \
+  N_146_i_2.BLIF N_156.BLIF N_146_i_3.BLIF N_159.BLIF nEXP_SPACE_c.BLIF N_220_1.BLIF N_161.BLIF N_220_2.BLIF N_165.BLIF \
+  BERR_c.BLIF N_375_1.BLIF N_168.BLIF N_375_2.BLIF N_171.BLIF BG_030_c.BLIF N_373_1.BLIF N_174.BLIF N_373_2.BLIF \
+  N_175.BLIF BG_000DFFreg.BLIF N_210_1.BLIF N_178.BLIF N_210_2.BLIF N_181.BLIF N_210_3.BLIF N_183.BLIF BGACK_000_c.BLIF \
+  un5_ciin_1.BLIF N_188.BLIF un5_ciin_2.BLIF N_190.BLIF CLK_030_c.BLIF un5_ciin_3.BLIF N_193.BLIF un5_ciin_4.BLIF N_195.BLIF \
+  un5_ciin_5.BLIF N_200.BLIF un5_ciin_6.BLIF N_205.BLIF CLK_OSZI_c.BLIF un5_ciin_7.BLIF N_206.BLIF un5_ciin_8.BLIF N_207.BLIF \
+  un5_ciin_9.BLIF N_208.BLIF un5_ciin_10.BLIF N_210.BLIF un5_ciin_11.BLIF N_211.BLIF FPU_SENSE_c.BLIF N_302_1.BLIF N_212.BLIF \
+  N_244_i_1.BLIF N_373.BLIF IPL_030DFF_0_reg.BLIF N_244_i_2.BLIF N_375.BLIF N_243_i_1.BLIF N_216.BLIF IPL_030DFF_1_reg.BLIF N_410_1.BLIF \
+  N_218.BLIF N_410_2.BLIF N_219.BLIF IPL_030DFF_2_reg.BLIF N_410_3.BLIF N_220.BLIF N_410_4.BLIF N_221.BLIF ipl_c_0__n.BLIF \
+  N_237_1.BLIF N_222.BLIF N_237_2.BLIF N_224.BLIF ipl_c_1__n.BLIF un21_fpu_cs_1.BLIF N_225.BLIF un22_berr_1_0.BLIF N_226.BLIF \
+  ipl_c_2__n.BLIF N_233_1.BLIF N_228.BLIF N_233_2.BLIF N_230.BLIF N_245_i_1.BLIF N_231.BLIF DTACK_c.BLIF N_128_i_1.BLIF \
+  N_240.BLIF N_134_i_1.BLIF N_241.BLIF N_124_0_1.BLIF N_277.BLIF N_267_i_1.BLIF N_278.BLIF VPA_c.BLIF N_268_i_1.BLIF \
+  N_279.BLIF N_355_0_1.BLIF N_280.BLIF N_353_i_1.BLIF N_281.BLIF RST_c.BLIF N_140_i_1.BLIF N_302.BLIF N_142_i_1.BLIF \
+  N_313.BLIF N_280_1.BLIF N_318.BLIF RW_c.BLIF N_225_1.BLIF N_321.BLIF N_224_1.BLIF N_324.BLIF fc_c_0__n.BLIF \
+  N_219_1.BLIF N_326.BLIF N_218_1.BLIF N_329.BLIF fc_c_1__n.BLIF N_212_1.BLIF N_332.BLIF N_208_1.BLIF N_348.BLIF \
+  N_207_1.BLIF cpu_est_0_0_x2_0_x2_0_.BLIF AMIGA_BUS_DATA_DIR_c.BLIF N_200_1.BLIF pos_clk_CYCLE_DMA_5_0_i_0_x2.BLIF N_195_1.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF pos_clk_ipl_1_n.BLIF N_235.BLIF \
+  ipl_030_0_1__un3_n.BLIF N_196.BLIF ipl_030_0_1__un1_n.BLIF N_143.BLIF N_7_i.BLIF ipl_030_0_1__un0_n.BLIF N_158.BLIF N_47_0.BLIF as_030_000_sync_0_un3_n.BLIF \
+  N_198.BLIF N_5_i.BLIF as_030_000_sync_0_un1_n.BLIF N_199.BLIF N_48_0.BLIF as_030_000_sync_0_un0_n.BLIF N_307.BLIF N_3_i.BLIF as_000_int_0_un3_n.BLIF \
+  N_201.BLIF N_50_0.BLIF as_000_int_0_un1_n.BLIF N_182.BLIF nEXP_SPACE_c_i.BLIF as_000_int_0_un0_n.BLIF N_243_2.BLIF N_55_0.BLIF ds_000_dma_0_un3_n.BLIF \
+  N_8.BLIF VPA_c_i.BLIF ds_000_dma_0_un1_n.BLIF N_356.BLIF N_56_0.BLIF ds_000_dma_0_un0_n.BLIF N_10.BLIF DTACK_c_i.BLIF ipl_030_0_2__un3_n.BLIF \
+  pos_clk_un6_bgack_000_n.BLIF N_57_0.BLIF ipl_030_0_2__un1_n.BLIF N_19.BLIF ipl_c_i_1__n.BLIF ipl_030_0_2__un0_n.BLIF N_352.BLIF N_53_0.BLIF un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n.BLIF \
+  N_327.BLIF ipl_c_i_2__n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n.BLIF N_20.BLIF N_54_0.BLIF un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n.BLIF pos_clk_a0_dma_3_n.BLIF N_28_i.BLIF sm_amiga_srsts_i_0_0_m3_1__un3_n.BLIF \
+  N_24.BLIF N_32_0.BLIF sm_amiga_srsts_i_0_0_m3_1__un1_n.BLIF N_113.BLIF N_29_i.BLIF sm_amiga_srsts_i_0_0_m3_1__un0_n.BLIF N_25.BLIF N_33_0.BLIF sm_amiga_srsts_i_0_0_m3_5__un3_n.BLIF \
+  N_114.BLIF N_378_i.BLIF sm_amiga_srsts_i_0_0_m3_5__un1_n.BLIF pos_clk_size_dma_6_0__n.BLIF sm_amiga_srsts_i_0_0_m3_5__un0_n.BLIF N_232.BLIF size_dma_0_0__un3_n.BLIF pos_clk_size_dma_6_1__n.BLIF N_227_i.BLIF \
+  size_dma_0_0__un1_n.BLIF N_410.BLIF N_354_0.BLIF size_dma_0_0__un0_n.BLIF N_185.BLIF N_233_i.BLIF size_dma_0_1__un3_n.BLIF N_236.BLIF N_357_0.BLIF \
+  size_dma_0_1__un1_n.BLIF N_238.BLIF N_270_0.BLIF size_dma_0_1__un0_n.BLIF N_173.BLIF AS_000_DMA_i.BLIF as_000_dma_0_un3_n.BLIF N_239.BLIF N_137_0.BLIF \
+  as_000_dma_0_un1_n.BLIF N_331.BLIF N_312_i.BLIF as_000_dma_0_un0_n.BLIF N_237.BLIF pos_clk_un3_as_030_d0_i_n.BLIF bgack_030_int_0_un3_n.BLIF un22_berr_1.BLIF N_161_i.BLIF \
+  bgack_030_int_0_un1_n.BLIF N_233.BLIF N_179_0.BLIF bgack_030_int_0_un0_n.BLIF N_209.BLIF N_180_0.BLIF rw_000_dma_0_un3_n.BLIF AS_030.PIN AS_000.PIN \
+  RW_000.PIN UDS_000.PIN LDS_000.PIN SIZE_0_.PIN SIZE_1_.PIN A0.PIN BERR.PIN RW.PIN  
+.outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 AVEC E VMA \
+  RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D SM_AMIGA_i_7_.C SM_AMIGA_6_.D \
+  SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C \
+  SM_AMIGA_0_.D SM_AMIGA_0_.C cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \
+  IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D IPL_D0_2_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D CLK_000_N_SYNC_6_.C \
+  CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D \
+  CYCLE_DMA_0_.C CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \
+  CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.D CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D \
+  CLK_000_P_SYNC_6_.C CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D CLK_000_N_SYNC_1_.C \
+  CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D CLK_000_N_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C RST_DLY_2_.D \
+  RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_RW_000_DMA.D inst_RW_000_DMA.C inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \
+  inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C inst_DS_000_DMA.D \
+  inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C \
+  inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D \
+  inst_VMA_INTreg.C inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_NE.D inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \
+  inst_CLK_OUT_INTreg.D inst_CLK_OUT_INTreg.C inst_CLK_000_D1.D inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C inst_CLK_OUT_EXP_INT.D inst_CLK_OUT_EXP_INT.C inst_CLK_OUT_PRE_D.D inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.D \
+  inst_CLK_000_D0.C inst_CLK_000_PE.D inst_CLK_000_PE.C G_136.X1 G_136.X2 G_135.X1 G_135.X2 pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2.X1 pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2.X2 pos_clk_CYCLE_DMA_5_1_i_0_x2.X1 pos_clk_CYCLE_DMA_5_1_i_0_x2.X2 \
+  pos_clk_CYCLE_DMA_5_0_i_0_x2.X1 pos_clk_CYCLE_DMA_5_0_i_0_x2.X2 cpu_est_0_0_x2_0_x2_0_.X1 cpu_est_0_0_x2_0_x2_0_.X2 CLK_OUT_PRE_25_0.X1 CLK_OUT_PRE_25_0.X2 G_134.X1 G_134.X2 SIZE_1_ AS_030 AS_000 RW_000 UDS_000 LDS_000 A0 BERR RW SIZE_0_ N_184 N_184_0 rw_000_dma_0_un1_n \
+  N_180 N_185_0 rw_000_dma_0_un0_n N_179 UDS_000_c_i a0_dma_0_un3_n LDS_000_c_i a0_dma_0_un1_n N_312 N_173_i a0_dma_0_un0_n \
+  N_270 N_358_0 amiga_bus_enable_dma_low_0_un3_n N_357 N_239_i amiga_bus_enable_dma_low_0_un1_n N_354 pos_clk_size_dma_6_0_1__n amiga_bus_enable_dma_low_0_un0_n vcc_n_n N_227 \
+  N_238_i amiga_bus_enable_dma_high_0_un3_n un5_e N_378 pos_clk_size_dma_6_0_0__n amiga_bus_enable_dma_high_0_un1_n N_29 N_237_i amiga_bus_enable_dma_high_0_un0_n gnd_n_n N_28 \
+  N_236_i cpu_est_0_2__un3_n un1_amiga_bus_enable_low N_3 AMIGA_BUS_DATA_DIR_c_0 cpu_est_0_2__un1_n un3_size N_5 N_331_i cpu_est_0_2__un0_n un4_size \
+  N_7 pos_clk_un6_bgack_000_0_n cpu_est_0_3__un3_n un4_uds_000 N_190_i N_356_0 cpu_est_0_3__un1_n un4_lds_000 un1_amiga_bus_enable_low_i N_352_0 cpu_est_0_3__un0_n \
+  un5_ciin un21_fpu_cs_i N_8_i ipl_030_0_0__un3_n un4_as_000 CLK_OUT_EXP_INT_i N_46_0 ipl_030_0_0__un1_n un1_SM_AMIGA_5 AS_000_i N_10_i \
+  ipl_030_0_0__un0_n un21_fpu_cs DS_000_DMA_i N_44_0 rw_000_int_0_un3_n un22_berr sm_amiga_i_5__n N_19_i rw_000_int_0_un1_n un6_ds_030 sm_amiga_i_6__n \
+  N_41_0 rw_000_int_0_un0_n sm_amiga_i_0__n N_20_i uds_000_int_0_un3_n CLK_000_NE_i N_40_0 uds_000_int_0_un1_n sm_amiga_i_4__n N_24_i uds_000_int_0_un0_n \
+  RW_000_i N_36_0 vma_int_0_un3_n sm_amiga_i_2__n N_25_i vma_int_0_un1_n CLK_000_D0_i N_35_0 vma_int_0_un0_n BERR_i bg_000_0_un3_n \
+  sm_amiga_i_1__n N_198_i bg_000_0_un1_n CLK_000_PE_i N_243_2_i bg_000_0_un0_n N_410_i_0 N_196_i cpu_est_0_1__un3_n sm_amiga_i_i_7__n N_195_i \
+  cpu_est_0_1__un1_n AS_030_i cpu_est_0_1__un0_n FPU_SENSE_i N_201_i dsack1_int_0_un3_n nEXP_SPACE_D0_i N_200_i dsack1_int_0_un1_n BGACK_030_INT_i N_199_i \
+  dsack1_int_0_un0_n AMIGA_BUS_ENABLE_DMA_HIGH_i N_182_0 ds_000_enable_0_un3_n A1_i N_158_i ds_000_enable_0_un1_n CLK_030_H_i N_148_i ds_000_enable_0_un0_n a_i_16__n \
+  N_307_i lds_000_int_0_un3_n a_i_18__n N_143_0 lds_000_int_0_un1_n a_i_19__n N_217_i lds_000_int_0_un0_n N_114_i N_235_i a_15__n \
+  N_113_i AS_000_INT_i N_210_i a_14__n AMIGA_BUS_ENABLE_DMA_LOW_i rst_dly_i_2__n N_207_i a_13__n rst_dly_i_0__n N_208_i rst_dly_i_1__n \
+  N_206_i a_12__n RESET_OUT_i size_dma_i_1__n N_313_i a_11__n size_dma_i_0__n N_211_i AS_030_D0_i N_212_i a_10__n \
+  a_i_24__n N_183_0 sm_amiga_i_3__n N_181_0 a_9__n cpu_est_i_3__n N_178_0 cpu_est_i_0__n N_69_0 a_8__n VPA_D_i \
+  N_329_i cpu_est_i_1__n N_176_i a_7__n CLK_030_i N_175_0 pos_clk_ipl_n CLK_000_D1_i N_174_0 a_6__n cpu_est_i_2__n \
+  N_171_0 DTACK_D0_i un1_SM_AMIGA_5_i a_5__n RW_i N_324_i a_i_31__n N_326_i a_4__n a_i_29__n N_168_i \
+  pos_clk_un8_bg_030_n a_i_30__n VMA_INT_i a_3__n a_i_27__n N_165_i a_i_28__n N_164_i a_2__n a_i_25__n N_162_i \
+  a_i_26__n clk_000_n_sync_i_10__n N_213_i N_321_i N_214_i N_159_0 N_215_i N_318_i N_156_i DS_000_ENABLE_1_sqmuxa_i N_155_i \
+  N_98_i N_154_i un6_ds_030_i CLK_OUT_PRE_D_i un4_as_000_i N_152_0 un4_lds_000_i N_150_i un4_uds_000_i AS_030_000_SYNC_i LDS_000_INT_i \
+  N_147_i UDS_000_INT_i N_145_i AS_030_c N_281_i N_302_i AS_000_c N_279_i RW_000_c N_280_i un5_e_0 \
+  pos_clk_un7_clk_000_pe_n N_278_i UDS_000_c cpu_est_2_0_3__n N_277_i DS_000_ENABLE_1_sqmuxa LDS_000_c N_348_i cpu_est_2_0_2__n size_c_0__n N_128_i \
+  N_193_i size_c_1__n N_241_i pos_clk_un3_as_030_d0_n DS_000_ENABLE_1_sqmuxa_1 N_240_i N_4 N_124_0 N_6 N_269_0 un5_ciin_i \
+  N_61_0 un1_as_030_i N_17 N_228_i N_18 N_355_0 N_21 N_226_i N_22 N_26 N_224_i \
+  N_27 N_225_i N_282_0 N_221_i N_222_i N_219_i N_220_i N_283_0 N_216_i N_218_i cpu_est_2_0_1__n \
+  N_373_i N_375_i pos_clk_un7_clk_000_pe_0_n N_188_i a_c_16__n N_205_i a_c_17__n pos_clk_un8_sm_amiga_i_n A0_c_i a_c_18__n size_c_i_1__n \
+  N_27_i a_c_19__n N_31_0 ipl_c_i_0__n a_c_20__n N_52_0 N_4_i a_c_21__n N_49_0 N_17_i a_c_22__n \
+  N_43_0 N_124 N_18_i cpu_est_2_1__n a_c_23__n N_42_0 cpu_est_2_2__n N_21_i cpu_est_2_3__n a_c_24__n N_39_0 \
+  N_22_i a_c_25__n N_38_0 N_26_i N_269 a_c_26__n N_34_0 N_61 BG_030_c_i a_c_27__n pos_clk_un8_bg_030_0_n \
+  N_98 N_161_i_1 a_c_28__n N_161_i_2 pos_clk_un8_sm_amiga_i_1_n N_355 a_c_29__n N_324_1 N_324_2 N_128 a_c_30__n \
+  N_150_i_1 N_137 un1_SM_AMIGA_5_i_1 N_145 a_c_31__n un1_SM_AMIGA_5_i_2 N_148 N_138_i_1 N_150 A0_c N_138_i_2 \
+  N_152 N_146_i_1 N_154 A1_c N_146_i_2 N_156 N_146_i_3 N_159 nEXP_SPACE_c N_220_1 N_161 \
+  N_220_2 N_165 BERR_c N_375_1 N_168 N_375_2 N_171 BG_030_c N_373_1 N_174 N_373_2 \
+  N_175 N_210_1 N_178 N_210_2 N_181 N_210_3 N_183 BGACK_000_c un5_ciin_1 N_188 un5_ciin_2 \
+  N_190 CLK_030_c un5_ciin_3 N_193 un5_ciin_4 N_195 un5_ciin_5 N_200 un5_ciin_6 N_205 CLK_OSZI_c \
+  un5_ciin_7 N_206 un5_ciin_8 N_207 un5_ciin_9 N_208 un5_ciin_10 N_210 un5_ciin_11 N_211 FPU_SENSE_c \
+  N_302_1 N_212 N_244_i_1 N_373 N_244_i_2 N_375 N_243_i_1 N_216 N_410_1 N_218 N_410_2 \
+  N_219 N_410_3 N_220 N_410_4 N_221 ipl_c_0__n N_237_1 N_222 N_237_2 N_224 ipl_c_1__n \
+  un21_fpu_cs_1 N_225 un22_berr_1_0 N_226 ipl_c_2__n N_233_1 N_228 N_233_2 N_230 N_245_i_1 N_231 \
+  DTACK_c N_128_i_1 N_240 N_134_i_1 N_241 N_124_0_1 N_277 N_267_i_1 N_278 VPA_c N_268_i_1 \
+  N_279 N_355_0_1 N_280 N_353_i_1 N_281 RST_c N_140_i_1 N_302 N_142_i_1 N_313 N_280_1 \
+  N_318 RW_c N_225_1 N_321 N_224_1 N_324 fc_c_0__n N_219_1 N_326 N_218_1 N_329 \
+  fc_c_1__n N_212_1 N_332 N_208_1 N_348 N_207_1 AMIGA_BUS_DATA_DIR_c N_200_1 N_195_1 pos_clk_ipl_1_n N_235 \
+  ipl_030_0_1__un3_n N_196 ipl_030_0_1__un1_n N_143 N_7_i ipl_030_0_1__un0_n N_158 N_47_0 as_030_000_sync_0_un3_n N_198 N_5_i \
+  as_030_000_sync_0_un1_n N_199 N_48_0 as_030_000_sync_0_un0_n N_307 N_3_i as_000_int_0_un3_n N_201 N_50_0 as_000_int_0_un1_n N_182 \
+  nEXP_SPACE_c_i as_000_int_0_un0_n N_243_2 N_55_0 ds_000_dma_0_un3_n N_8 VPA_c_i ds_000_dma_0_un1_n N_356 N_56_0 ds_000_dma_0_un0_n \
+  N_10 DTACK_c_i ipl_030_0_2__un3_n pos_clk_un6_bgack_000_n N_57_0 ipl_030_0_2__un1_n N_19 ipl_c_i_1__n ipl_030_0_2__un0_n N_352 N_53_0 \
+  un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n N_327 ipl_c_i_2__n un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n N_20 N_54_0 un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n pos_clk_a0_dma_3_n N_28_i sm_amiga_srsts_i_0_0_m3_1__un3_n N_24 \
+  N_32_0 sm_amiga_srsts_i_0_0_m3_1__un1_n N_113 N_29_i sm_amiga_srsts_i_0_0_m3_1__un0_n N_25 N_33_0 sm_amiga_srsts_i_0_0_m3_5__un3_n N_114 N_378_i sm_amiga_srsts_i_0_0_m3_5__un1_n \
+  pos_clk_size_dma_6_0__n sm_amiga_srsts_i_0_0_m3_5__un0_n N_232 size_dma_0_0__un3_n pos_clk_size_dma_6_1__n N_227_i size_dma_0_0__un1_n N_410 N_354_0 size_dma_0_0__un0_n N_185 \
+  N_233_i size_dma_0_1__un3_n N_236 N_357_0 size_dma_0_1__un1_n N_238 N_270_0 size_dma_0_1__un0_n N_173 AS_000_DMA_i as_000_dma_0_un3_n \
+  N_239 N_137_0 as_000_dma_0_un1_n N_331 N_312_i as_000_dma_0_un0_n N_237 pos_clk_un3_as_030_d0_i_n bgack_030_int_0_un3_n un22_berr_1 N_161_i \
+  bgack_030_int_0_un1_n N_233 N_179_0 bgack_030_int_0_un0_n N_209 N_180_0 rw_000_dma_0_un3_n AS_030.OE AS_000.OE \
+  RW_000.OE UDS_000.OE LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE \
+  DSACK1.OE RESET.OE CIIN.OE
+.names N_137.BLIF AS_030
+1 1
+.names AS_030.PIN AS_030_c
+1 1
+.names N_231.BLIF AS_030.OE
+1 1
+.names un4_as_000_i.BLIF AS_000
+1 1
+.names AS_000.PIN AS_000_c
+1 1
+.names N_230.BLIF AS_000.OE
+1 1
+.names inst_RW_000_INT.BLIF RW_000
+1 1
+.names RW_000.PIN RW_000_c
+1 1
+.names N_230.BLIF RW_000.OE
+1 1
+.names un4_uds_000_i.BLIF UDS_000
+1 1
+.names UDS_000.PIN UDS_000_c
+1 1
+.names N_230.BLIF UDS_000.OE
+1 1
+.names un4_lds_000_i.BLIF LDS_000
+1 1
+.names LDS_000.PIN LDS_000_c
+1 1
+.names N_230.BLIF LDS_000.OE
+1 1
+.names un4_size.BLIF SIZE_0_
+1 1
+.names SIZE_0_.PIN size_c_0__n
+1 1
+.names un1_as_030_i.BLIF SIZE_0_.OE
+1 1
+.names un3_size.BLIF SIZE_1_
+1 1
+.names SIZE_1_.PIN size_c_1__n
+1 1
+.names un1_as_030_i.BLIF SIZE_1_.OE
+1 1
+.names inst_A0_DMA.BLIF A0
+1 1
+.names A0.PIN A0_c
+1 1
+.names N_231.BLIF A0.OE
+1 1
+.names gnd_n_n.BLIF BERR
+1 1
+.names BERR.PIN BERR_c
+1 1
+.names un22_berr.BLIF BERR.OE
+1 1
+.names inst_RW_000_DMA.BLIF RW
+1 1
+.names RW.PIN RW_c
+1 1
+.names N_332.BLIF RW.OE
+1 1
+.names un6_ds_030_i.BLIF DS_030
+1 1
+.names N_231.BLIF DS_030.OE
+1 1
+.names inst_DSACK1_INTreg.BLIF DSACK1
+1 1
+.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE
+1 1
+.names gnd_n_n.BLIF RESET
+1 1
+.names RESET_OUT_i.BLIF RESET.OE
+1 1
+.names un5_ciin.BLIF CIIN
+1 1
+.names N_61.BLIF CIIN.OE
+1 1
+.names  un5_ciin_1.BLIF un5_ciin_2.BLIF un5_ciin_7
+11 1
+.names  inst_CLK_000_NE.BLIF CLK_000_NE_i
+0 1
+.names  inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n
+0 1
+.names  un5_ciin_3.BLIF un5_ciin_4.BLIF un5_ciin_8
+11 1
+.names  SM_AMIGA_4_.BLIF sm_amiga_i_4__n
+0 1
+.names  cpu_est_2_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n
+11 1
+.names  CLK_OSZI_c.BLIF RST_DLY_1_.C
+1 1
+.names  un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9
+11 1
+.names  CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_222
+11 1
+.names  cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n
+11 1
+.names  un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10
+11 1
+.names  SM_AMIGA_0_.BLIF sm_amiga_i_0__n
+0 1
+.names  cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D
+1- 1
+-1 1
+.names  un5_ciin_9.BLIF a_i_30__n.BLIF un5_ciin_11
+11 1
+.names  N_184.BLIF sm_amiga_i_0__n.BLIF N_378
+11 1
+.names  inst_UDS_000_INT.BLIF UDS_000_INT_i
+0 1
+.names  un5_ciin_10.BLIF un5_ciin_11.BLIF un5_ciin
+11 1
+.names  SM_AMIGA_6_.BLIF sm_amiga_i_6__n
+0 1
+.names  inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un4_uds_000
+11 1
+.names  CLK_OSZI_c.BLIF RST_DLY_2_.C
+1 1
+.names  CLK_000_NE_i.BLIF rst_dly_i_0__n.BLIF N_302_1
+11 1
+.names  N_180.BLIF sm_amiga_i_6__n.BLIF N_205
+11 1
+.names  inst_LDS_000_INT.BLIF LDS_000_INT_i
+0 1
+.names  N_302_1.BLIF RST_c.BLIF N_302
+11 1
+.names  inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un4_lds_000
+11 1
+.names  N_199_i.BLIF N_200_i.BLIF N_244_i_1
+11 1
+.names  BG_030_c_i.BLIF N_128.BLIF pos_clk_un8_bg_030_0_n
+11 1
+.names  N_201_i.BLIF RST_c.BLIF N_244_i_2
+11 1
+.names  inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_209
+11 1
+.names  un4_uds_000.BLIF un4_uds_000_i
+0 1
+.names  CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C
+1 1
+.names  N_244_i_1.BLIF N_244_i_2.BLIF RST_DLY_1_.D
+11 1
+.names  pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n
+0 1
+.names  un4_lds_000.BLIF un4_lds_000_i
+0 1
+.names  N_243_2_i.BLIF N_195_i.BLIF N_243_i_1
+11 1
+.names  ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n
+11 1
+.names  un4_as_000.BLIF un4_as_000_i
+0 1
+.names  N_243_i_1.BLIF N_196_i.BLIF RST_DLY_2_.D
+11 1
+.names  IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
+11 1
+.names  un6_ds_030.BLIF un6_ds_030_i
+0 1
+.names  fc_c_0__n.BLIF fc_c_1__n.BLIF N_410_1
+11 1
+.names  ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29
+1- 1
+-1 1
+.names  N_98.BLIF N_98_i
+0 1
+.names  CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C
+1 1
+.names  a_c_17__n.BLIF a_i_16__n.BLIF N_410_2
+11 1
+.names  SM_AMIGA_1_.BLIF sm_amiga_i_1__n
+0 1
+.names  N_269.BLIF dsack1_int_0_un3_n
+0 1
+.names  VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_375_2
+11 1
+.names  CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_179_0
+11 1
+.names  N_98_i.BLIF N_269.BLIF dsack1_int_0_un1_n
+11 1
+.names  N_375_1.BLIF N_375_2.BLIF N_375
+11 1
+.names  BERR_c.BLIF BERR_i
+0 1
+.names  inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n
+11 1
+.names  inst_CLK_000_PE.BLIF N_155_i.BLIF N_373_1
+11 1
+.names  AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n
+11 1
+.names  dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_4
+1- 1
+-1 1
+.names  CLK_OSZI_c.BLIF inst_RW_000_DMA.C
+1 1
+.names  cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_373_2
+11 1
+.names  DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n
+0 1
+.names  N_373_1.BLIF N_373_2.BLIF N_373
+11 1
+.names  AS_000_DMA_i.BLIF AS_000_i.BLIF N_137_0
+11 1
+.names  inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un1_n
+11 1
+.names  N_150.BLIF N_162_i.BLIF N_210_1
+11 1
+.names  sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_270_0
+11 1
+.names  un1_SM_AMIGA_5_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n
+11 1
+.names  N_164_i.BLIF N_165_i.BLIF N_210_2
+11 1
+.names  N_233_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_357_0
+11 1
+.names  ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6
+1- 1
+-1 1
+.names  CLK_OSZI_c.BLIF inst_RW_000_INT.C
+1 1
+.names  N_210_1.BLIF N_210_2.BLIF N_210_3
+11 1
+.names  N_161_i.BLIF N_227_i.BLIF N_354_0
+11 1
+.names  SM_AMIGA_6_.BLIF lds_000_int_0_un3_n
+0 1
+.names  N_210_3.BLIF sm_amiga_i_3__n.BLIF N_210
+11 1
+.names  inst_CLK_000_D0.BLIF CLK_000_D0_i
+0 1
+.names  pos_clk_un8_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n
+11 1
+.names  AS_030_D0_i.BLIF a_c_20__n.BLIF un5_ciin_1
+11 1
+.names  inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D
+11 1
+.names  inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n
+11 1
+.names  a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2
+11 1
+.names  N_176_i.BLIF N_378_i.BLIF SM_AMIGA_0_.D
+11 1
+.names  lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_17
+1- 1
+-1 1
+.names  CLK_OSZI_c.BLIF inst_LDS_000_INT.C
+1 1
+.names  a_c_23__n.BLIF a_i_24__n.BLIF un5_ciin_3
+11 1
+.names  LDS_000_c.BLIF UDS_000_c.BLIF N_312
+11 1
+.names  vcc_n_n
+1
+.names  a_i_25__n.BLIF a_i_26__n.BLIF un5_ciin_4
+11 1
+.names  SM_AMIGA_2_.BLIF sm_amiga_i_2__n
+0 1
+.names  gnd_n_n
+.names  a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5
+11 1
+.names  N_179.BLIF sm_amiga_i_2__n.BLIF N_241
+11 1
+.names  A_15_.BLIF a_15__n
+1 1
+.names  a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6
+11 1
+.names  inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n
+0 1
+.names  A_14_.BLIF a_14__n
+1 1
+.names  CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C
+1 1
+.names  N_150_i_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_150_i
+11 1
+.names  SM_AMIGA_i_7_.BLIF inst_BGACK_030_INTreg.BLIF un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n
+11 1
+.names  A_13_.BLIF a_13__n
+1 1
+.names  DS_000_ENABLE_1_sqmuxa_i.BLIF N_162_i.BLIF un1_SM_AMIGA_5_i_1
+11 1
+.names  AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n
+11 1
+.names  A_12_.BLIF a_12__n
+1 1
+.names  N_318_i.BLIF SM_AMIGA_i_7_.BLIF un1_SM_AMIGA_5_i_2
+11 1
+.names  un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n.BLIF N_190
+1- 1
+-1 1
+.names  A_11_.BLIF a_11__n
+1 1
+.names  un1_SM_AMIGA_5_i_1.BLIF un1_SM_AMIGA_5_i_2.BLIF un1_SM_AMIGA_5_i
+11 1
+.names  inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
+0 1
+.names  A_10_.BLIF a_10__n
+1 1
+.names  CLK_OSZI_c.BLIF inst_AS_000_DMA.C
+1 1
+.names  N_211_i.BLIF N_212_i.BLIF N_138_i_1
+11 1
+.names  inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i
+0 1
+.names  A_9_.BLIF a_9__n
+1 1
+.names  N_313_i.BLIF RST_c.BLIF N_138_i_2
+11 1
+.names  FPU_SENSE_c.BLIF FPU_SENSE_i
+0 1
+.names  A_8_.BLIF a_8__n
+1 1
+.names  N_138_i_1.BLIF N_138_i_2.BLIF SM_AMIGA_3_.D
+11 1
+.names  BGACK_000_c.BLIF N_410.BLIF un22_berr_1
+11 1
+.names  A_7_.BLIF a_7__n
+1 1
+.names  N_176_i.BLIF N_206_i.BLIF N_146_i_1
+11 1
+.names  AS_030_c.BLIF AS_030_i
+0 1
+.names  A_6_.BLIF a_6__n
+1 1
+.names  CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
+1 1
+.names  N_207_i.BLIF N_208_i.BLIF N_146_i_2
+11 1
+.names  SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n
+0 1
+.names  A_5_.BLIF a_5__n
+1 1
+.names  N_146_i_1.BLIF N_146_i_2.BLIF N_146_i_3
+11 1
+.names  N_410.BLIF N_410_i_0
+0 1
+.names  A_4_.BLIF a_4__n
+1 1
+.names  N_146_i_3.BLIF N_210_i.BLIF SM_AMIGA_i_7_.D
+11 1
+.names  SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_0_m3_1__un3_n
+0 1
+.names  A_3_.BLIF a_3__n
+1 1
+.names  inst_CLK_000_NE_D0.BLIF N_168.BLIF N_220_1
+11 1
+.names  BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_0_m3_1__un1_n
+11 1
+.names  A_2_.BLIF a_2__n
+1 1
+.names  CLK_OSZI_c.BLIF inst_AS_000_INT.C
+1 1
+.names  RST_c.BLIF SM_AMIGA_3_.BLIF N_220_2
+11 1
+.names  CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_0_m3_1__un3_n.BLIF sm_amiga_srsts_i_0_0_m3_1__un0_n
+11 1
+.names  N_220_1.BLIF N_220_2.BLIF N_220
+11 1
+.names  sm_amiga_srsts_i_0_0_m3_1__un1_n.BLIF sm_amiga_srsts_i_0_0_m3_1__un0_n.BLIF N_193
+1- 1
+-1 1
+.names  inst_CLK_000_NE.BLIF N_348.BLIF N_375_1
+11 1
+.names  N_22.BLIF N_22_i
+0 1
+.names  CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C
+1 1
+.names  N_38_0.BLIF inst_VMA_INTreg.D
+0 1
+.names  inst_CLK_000_PE.BLIF CLK_000_PE_i
+0 1
+.names  N_26.BLIF N_26_i
+0 1
+.names  SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m3_5__un3_n
+0 1
+.names  N_34_0.BLIF BG_000DFFreg.D
+0 1
+.names  BERR_i.BLIF SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m3_5__un1_n
+11 1
+.names  BG_030_c.BLIF BG_030_c_i
+0 1
+.names  CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_0_m3_5__un3_n.BLIF sm_amiga_srsts_i_0_0_m3_5__un0_n
+11 1
+.names  CLK_OSZI_c.BLIF inst_DS_000_DMA.C
+1 1
+.names  pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n
+0 1
+.names  sm_amiga_srsts_i_0_0_m3_5__un1_n.BLIF sm_amiga_srsts_i_0_0_m3_5__un0_n.BLIF N_188
+1- 1
+-1 1
+.names  AS_000_i.BLIF pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2.BLIF N_161_i_1
+11 1
+.names  inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_184_0
+11 1
+.names  BGACK_030_INT_i.BLIF N_312_i.BLIF N_161_i_2
+11 1
+.names  CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_180_0
+11 1
+.names  N_161_i_1.BLIF N_161_i_2.BLIF N_161_i
+11 1
+.names  A1_c.BLIF A1_i
+0 1
+.names  CLK_OSZI_c.BLIF inst_AS_030_D0.C
+1 1
+.names  size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un8_sm_amiga_i_1_n
+11 1
+.names  A1_i.BLIF BGACK_030_INT_i.BLIF N_114
+11 1
+.names  pos_clk_un8_sm_amiga_i_1_n.BLIF size_c_0__n.BLIF pos_clk_un8_sm_amiga_i_n
+11 1
+.names  A1_c.BLIF BGACK_030_INT_i.BLIF N_113
+11 1
+.names  N_154_i.BLIF N_155_i.BLIF N_324_1
+11 1
+.names  inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_327
+11 1
+.names  VMA_INT_i.BLIF VPA_D_i.BLIF N_324_2
+11 1
+.names  AS_000_c.BLIF inst_CLK_000_PE.BLIF N_331
+11 1
+.names  CLK_OSZI_c.BLIF inst_nEXP_SPACE_D0reg.C
+1 1
+.names  N_324_1.BLIF N_324_2.BLIF N_324
+11 1
+.names  BGACK_030_INT_i.BLIF RW_000_i.BLIF N_352_0
+11 1
+.names  AS_030_000_SYNC_i.BLIF N_147_i.BLIF N_150_i_1
+11 1
+.names  CLK_030_i.BLIF N_161_i.BLIF N_356_0
+11 1
+.names  N_205.BLIF N_205_i
+0 1
+.names  BGACK_000_c.BLIF N_331_i.BLIF pos_clk_un6_bgack_000_0_n
+11 1
+.names  A0_c.BLIF A0_c_i
+0 1
+.names  N_236_i.BLIF N_237_i.BLIF AMIGA_BUS_DATA_DIR_c_0
+11 1
+.names  CLK_OSZI_c.BLIF inst_VPA_D.C
+1 1
+.names  size_c_1__n.BLIF size_c_i_1__n
+0 1
+.names  N_238_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n
+11 1
+.names  N_27.BLIF N_27_i
+0 1
+.names  N_239_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n
+11 1
+.names  N_31_0.BLIF IPL_030DFF_0_reg.D
+0 1
+.names  AS_030_i.BLIF RST_c.BLIF N_358_0
+11 1
+.names  ipl_c_0__n.BLIF ipl_c_i_0__n
+0 1
+.names  LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_173_i
+11 1
+.names  CLK_OSZI_c.BLIF inst_DTACK_D0.C
+1 1
+.names  N_52_0.BLIF IPL_D0_0_.D
+0 1
+.names  AS_000_DMA_i.BLIF CLK_030_i.BLIF N_185_0
+11 1
+.names  N_4.BLIF N_4_i
+0 1
+.names  inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i
+0 1
+.names  N_49_0.BLIF inst_DSACK1_INTreg.D
+0 1
+.names  N_19_i.BLIF RST_c.BLIF N_41_0
+11 1
+.names  N_17.BLIF N_17_i
+0 1
+.names  N_10_i.BLIF RST_c.BLIF N_44_0
+11 1
+.names  CLK_OSZI_c.BLIF inst_CLK_030_H.C
+1 1
+.names  N_43_0.BLIF inst_LDS_000_INT.D
+0 1
+.names  N_8_i.BLIF RST_c.BLIF N_46_0
+11 1
+.names  N_18.BLIF N_18_i
+0 1
+.names  N_232.BLIF size_dma_0_0__un3_n
+0 1
+.names  N_42_0.BLIF inst_RW_000_INT.D
+0 1
+.names  SIZE_DMA_0_.BLIF N_232.BLIF size_dma_0_0__un1_n
+11 1
+.names  N_21.BLIF N_21_i
+0 1
+.names  pos_clk_size_dma_6_0__n.BLIF size_dma_0_0__un3_n.BLIF size_dma_0_0__un0_n
+11 1
+.names  CLK_OSZI_c.BLIF inst_RESET_OUT.C
+1 1
+.names  N_39_0.BLIF inst_UDS_000_INT.D
+0 1
+.names  size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D
+1- 1
+-1 1
+.names  N_224.BLIF N_224_i
+0 1
+.names  N_232.BLIF size_dma_0_1__un3_n
+0 1
+.names  N_225.BLIF N_225_i
+0 1
+.names  SIZE_DMA_1_.BLIF N_232.BLIF size_dma_0_1__un1_n
+11 1
+.names  N_282_0.BLIF SM_AMIGA_6_.D
+0 1
+.names  pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF size_dma_0_1__un0_n
+11 1
+.names  CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C
+1 1
+.names  N_221.BLIF N_221_i
+0 1
+.names  size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D
+1- 1
+-1 1
+.names  CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C
+1 1
+.names  N_222.BLIF N_222_i
+0 1
+.names  a_c_18__n.BLIF a_i_18__n
+0 1
+.names  N_219.BLIF N_219_i
+0 1
+.names  a_c_19__n.BLIF a_i_19__n
+0 1
+.names  N_220.BLIF N_220_i
+0 1
+.names  a_c_16__n.BLIF a_i_16__n
+0 1
+.names  CLK_OSZI_c.BLIF BG_000DFFreg.C
+1 1
+.names  N_283_0.BLIF SM_AMIGA_2_.D
+0 1
+.names  inst_CLK_030_H.BLIF CLK_030_H_i
+0 1
+.names  CLK_OSZI_c.BLIF SM_AMIGA_6_.C
+1 1
+.names  N_216.BLIF N_216_i
+0 1
+.names  CLK_030_H_i.BLIF N_185.BLIF N_226
+11 1
+.names  N_218.BLIF N_218_i
+0 1
+.names  N_327.BLIF RST_c.BLIF N_232
+11 1
+.names  cpu_est_2_0_1__n.BLIF cpu_est_2_1__n
+0 1
+.names  inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_236
+11 1
+.names  CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
+1 1
+.names  N_373.BLIF N_373_i
+0 1
+.names  BGACK_030_INT_i.BLIF N_173.BLIF N_238
+11 1
+.names  CLK_OSZI_c.BLIF SM_AMIGA_5_.C
+1 1
+.names  N_375.BLIF N_375_i
+0 1
+.names  BGACK_030_INT_i.BLIF N_173_i.BLIF N_239
+11 1
+.names  pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n
+0 1
+.names  BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n
+11 1
+.names  N_188.BLIF N_188_i
+0 1
+.names  inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i
+0 1
+.names  CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C
+1 1
+.names  cpu_est_2_0_3__n.BLIF cpu_est_2_3__n
+0 1
+.names  AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF un1_amiga_bus_enable_low
+11 1
+.names  CLK_OSZI_c.BLIF SM_AMIGA_4_.C
+1 1
+.names  N_277.BLIF N_277_i
+0 1
+.names  inst_AS_000_INT.BLIF AS_000_INT_i
+0 1
+.names  N_348.BLIF N_348_i
+0 1
+.names  AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000
+11 1
+.names  cpu_est_2_0_2__n.BLIF cpu_est_2_2__n
+0 1
+.names  N_356.BLIF as_000_dma_0_un3_n
+0 1
+.names  CLK_OSZI_c.BLIF inst_VMA_INTreg.C
+1 1
+.names  N_128_i.BLIF N_128
+0 1
+.names  N_161.BLIF N_356.BLIF as_000_dma_0_un1_n
+11 1
+.names  CLK_OSZI_c.BLIF SM_AMIGA_3_.C
+1 1
+.names  N_193.BLIF N_193_i
+0 1
+.names  inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n
+11 1
+.names  N_241.BLIF N_241_i
+0 1
+.names  as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_8
+1- 1
+-1 1
+.names  N_240.BLIF N_240_i
+0 1
+.names  pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n
+0 1
+.names  CLK_OSZI_c.BLIF inst_UDS_000_INT.C
+1 1
+.names  N_124_0.BLIF N_124
+0 1
+.names  BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n
+11 1
+.names  CLK_OSZI_c.BLIF SM_AMIGA_2_.C
+1 1
+.names  N_269_0.BLIF N_269
+0 1
+.names  inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF bgack_030_int_0_un0_n
+11 1
+.names  un5_ciin.BLIF un5_ciin_i
+0 1
+.names  bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_10
+1- 1
+-1 1
+.names  N_61_0.BLIF N_61
+0 1
+.names  N_327.BLIF rw_000_dma_0_un3_n
+0 1
+.names  CLK_OSZI_c.BLIF inst_A0_DMA.C
+1 1
+.names  N_228.BLIF N_228_i
+0 1
+.names  inst_RW_000_DMA.BLIF N_327.BLIF rw_000_dma_0_un1_n
+11 1
+.names  CLK_OSZI_c.BLIF SM_AMIGA_1_.C
+1 1
+.names  N_355_0.BLIF N_355
+0 1
+.names  N_352.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n
+11 1
+.names  N_226.BLIF N_226_i
+0 1
+.names  rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19
+1- 1
+-1 1
+.names  N_159_0.BLIF N_159
+0 1
+.names  N_327.BLIF a0_dma_0_un3_n
+0 1
+.names  CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C
+1 1
+.names  N_318.BLIF N_318_i
+0 1
+.names  inst_A0_DMA.BLIF N_327.BLIF a0_dma_0_un1_n
+11 1
+.names  CLK_OSZI_c.BLIF SM_AMIGA_0_.C
+1 1
+.names  N_156_i.BLIF N_156
+0 1
+.names  pos_clk_a0_dma_3_n.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n
+11 1
+.names  N_154_i.BLIF N_154
+0 1
+.names  a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20
+1- 1
+-1 1
+.names  inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i
+0 1
+.names  N_113.BLIF N_113_i
+0 1
+.names  CLK_OSZI_c.BLIF inst_CLK_000_NE.C
+1 1
+.names  N_152_0.BLIF N_152
+0 1
+.names  N_327.BLIF amiga_bus_enable_dma_low_0_un3_n
+0 1
+.names  CLK_OSZI_c.BLIF cpu_est_2_.C
+1 1
+.names  N_150_i.BLIF N_150
+0 1
+.names  inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_327.BLIF amiga_bus_enable_dma_low_0_un1_n
+11 1
+.names  inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
+0 1
+.names  N_113_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF amiga_bus_enable_dma_low_0_un0_n
+11 1
+.names  N_145_i.BLIF N_145
+0 1
+.names  amiga_bus_enable_dma_low_0_un1_n.BLIF amiga_bus_enable_dma_low_0_un0_n.BLIF N_24
+1- 1
+-1 1
+.names  CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C
+1 1
+.names  N_281.BLIF N_281_i
+0 1
+.names  N_114.BLIF N_114_i
+0 1
+.names  CLK_OSZI_c.BLIF cpu_est_3_.C
+1 1
+.names  N_302.BLIF N_302_i
+0 1
+.names  N_327.BLIF amiga_bus_enable_dma_high_0_un3_n
+0 1
+.names  N_279.BLIF N_279_i
+0 1
+.names  inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_327.BLIF amiga_bus_enable_dma_high_0_un1_n
+11 1
+.names  inst_CLK_OUT_PRE_D.BLIF inst_CLK_OUT_INTreg.D
+1 1
+.names  N_280.BLIF N_280_i
+0 1
+.names  N_114_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF amiga_bus_enable_dma_high_0_un0_n
+11 1
+.names  un5_e_0.BLIF un5_e
+0 1
+.names  amiga_bus_enable_dma_high_0_un1_n.BLIF amiga_bus_enable_dma_high_0_un0_n.BLIF N_25
+1- 1
+-1 1
+.names  CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C
+1 1
+.names  CLK_OSZI_c.BLIF inst_CLK_OUT_INTreg.C
+1 1
+.names  N_278.BLIF N_278_i
+0 1
+.names  N_25_i.BLIF RST_c.BLIF N_35_0
+11 1
+.names  N_181_0.BLIF N_181
+0 1
+.names  N_24_i.BLIF RST_c.BLIF N_36_0
+11 1
+.names  N_178_0.BLIF N_178
+0 1
+.names  N_20_i.BLIF RST_c.BLIF N_40_0
+11 1
+.names  inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
+1 1
+.names  N_69_0.BLIF inst_BGACK_030_INT_D.D
+0 1
+.names  N_148_i.BLIF N_307.BLIF N_199
+11 1
+.names  CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C
+1 1
+.names  N_329.BLIF N_329_i
+0 1
+.names  CLK_000_NE_i.BLIF rst_dly_i_1__n.BLIF N_201
+11 1
+.names  CLK_OSZI_c.BLIF inst_CLK_000_D1.C
+1 1
+.names  N_175_0.BLIF N_175
+0 1
+.names  inst_RESET_OUT.BLIF RESET_OUT_i
+0 1
+.names  N_174_0.BLIF N_174
+0 1
+.names  N_182.BLIF RESET_OUT_i.BLIF N_235
+11 1
+.names  N_171_0.BLIF N_171
+0 1
+.names  N_143.BLIF RST_DLY_0_.BLIF N_281
+11 1
+.names  CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C
+1 1
+.names  inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D
+1 1
+.names  un1_SM_AMIGA_5_i.BLIF un1_SM_AMIGA_5
+0 1
+.names  inst_CLK_000_NE.BLIF N_158.BLIF N_307
+11 1
+.names  N_324.BLIF N_324_i
+0 1
+.names  N_158.BLIF RST_c.BLIF N_217_i
+11 1
+.names  CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C
+1 1
+.names  N_326.BLIF N_326_i
+0 1
+.names  N_307_i.BLIF RST_c.BLIF N_143_0
+11 1
+.names  N_168_i.BLIF N_168
+0 1
+.names  RST_DLY_0_.BLIF rst_dly_i_0__n
+0 1
+.names  CLK_OSZI_c.BLIF IPL_D0_0_.C
+1 1
+.names  inst_VMA_INTreg.BLIF VMA_INT_i
+0 1
+.names  RST_DLY_1_.BLIF rst_dly_i_1__n
+0 1
+.names  inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_EXP_INT.D
+1 1
+.names  N_165_i.BLIF N_165
+0 1
+.names  RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_148_i
+11 1
+.names  CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n
+0 1
+.names  RST_DLY_2_.BLIF rst_dly_i_2__n
+0 1
+.names  CLK_OSZI_c.BLIF inst_CLK_OUT_EXP_INT.C
+1 1
+.names  N_321.BLIF N_321_i
+0 1
+.names  N_148_i.BLIF RST_DLY_2_.BLIF N_158_i
+11 1
+.names  CLK_OSZI_c.BLIF IPL_D0_1_.C
+1 1
+.names  N_199.BLIF N_199_i
+0 1
+.names  inst_CLK_000_NE.BLIF N_158_i.BLIF N_182_0
+11 1
+.names  N_182_0.BLIF N_182
+0 1
+.names  N_198_i.BLIF RST_c.BLIF N_243_2_i
+11 1
+.names  inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_D.D
+1 1
+.names  N_158_i.BLIF N_158
+0 1
+.names  cpu_est_3_.BLIF cpu_est_i_3__n
+0 1
+.names  N_148_i.BLIF N_148
+0 1
+.names  cpu_est_0_.BLIF cpu_est_i_0__n
+0 1
+.names  CLK_OSZI_c.BLIF IPL_D0_2_.C
+1 1
+.names  CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C
+1 1
+.names  N_307.BLIF N_307_i
+0 1
+.names  SM_AMIGA_3_.BLIF sm_amiga_i_3__n
+0 1
+.names  N_143_0.BLIF N_143
+0 1
+.names  inst_AS_030_D0.BLIF AS_030_D0_i
+0 1
+.names  N_235.BLIF N_235_i
+0 1
+.names  a_c_24__n.BLIF a_i_24__n
+0 1
+.names  N_210.BLIF N_210_i
+0 1
+.names  SIZE_DMA_0_.BLIF size_dma_i_0__n
+0 1
+.names  CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C
+1 1
+.names  CLK_OSZI_c.BLIF inst_CLK_000_D0.C
+1 1
+.names  N_207.BLIF N_207_i
+0 1
+.names  SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size
+11 1
+.names  N_208.BLIF N_208_i
+0 1
+.names  SIZE_DMA_1_.BLIF size_dma_i_1__n
+0 1
+.names  N_206.BLIF N_206_i
+0 1
+.names  SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size
+11 1
+.names  N_313.BLIF N_313_i
+0 1
+.names  N_235_i.BLIF RST_c.BLIF inst_RESET_OUT.D
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C
+1 1
+.names  CLK_OSZI_c.BLIF inst_CLK_000_PE.C
+1 1
+.names  N_211.BLIF N_211_i
+0 1
+.names  BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_332
+11 1
+.names  A_16_.BLIF a_c_16__n
+1 1
+.names  N_212.BLIF N_212_i
+0 1
+.names  N_332.BLIF nEXP_SPACE_D0_i.BLIF N_231
+11 1
+.names  A_17_.BLIF a_c_17__n
+1 1
+.names  N_183_0.BLIF N_183
+0 1
+.names  inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF N_230
+11 1
+.names  IPL_D0_2_.BLIF G_136.X1
+1 1
+.names  A_18_.BLIF a_c_18__n
+1 1
+.names  N_44_0.BLIF inst_BGACK_030_INTreg.D
+0 1
+.names  N_158_i.BLIF N_243_2.BLIF N_196
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C
+1 1
+.names  A_19_.BLIF a_c_19__n
+1 1
+.names  N_19.BLIF N_19_i
+0 1
+.names  CLK_000_NE_i.BLIF rst_dly_i_2__n.BLIF N_198
+11 1
+.names  ipl_c_2__n.BLIF G_136.X2
+1 1
+.names  A_20_.BLIF a_c_20__n
+1 1
+.names  N_41_0.BLIF inst_RW_000_DMA.D
+0 1
+.names  clk_000_n_sync_i_10__n.BLIF N_321_i.BLIF N_159_0
+11 1
+.names  A_21_.BLIF a_c_21__n
+1 1
+.names  N_20.BLIF N_20_i
+0 1
+.names  sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_162_i
+11 1
+.names  A_22_.BLIF a_c_22__n
+1 1
+.names  N_40_0.BLIF inst_A0_DMA.D
+0 1
+.names  sm_amiga_i_2__n.BLIF sm_amiga_i_4__n.BLIF N_164_i
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C
+1 1
+.names  IPL_D0_1_.BLIF G_135.X1
+1 1
+.names  A_23_.BLIF a_c_23__n
+1 1
+.names  N_24.BLIF N_24_i
+0 1
+.names  sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_165_i
+11 1
+.names  A_24_.BLIF a_c_24__n
+1 1
+.names  N_36_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D
+0 1
+.names  N_324_i.BLIF N_326_i.BLIF N_168_i
+11 1
+.names  ipl_c_1__n.BLIF G_135.X2
+1 1
+.names  A_25_.BLIF a_c_25__n
+1 1
+.names  N_25.BLIF N_25_i
+0 1
+.names  N_164_i.BLIF sm_amiga_i_6__n.BLIF N_171_0
+11 1
+.names  A_26_.BLIF a_c_26__n
+1 1
+.names  N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D
+0 1
+.names  N_145.BLIF SM_AMIGA_i_7_.BLIF N_174_0
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C
+1 1
+.names  A_27_.BLIF a_c_27__n
+1 1
+.names  N_198.BLIF N_198_i
+0 1
+.names  N_145.BLIF sm_amiga_i_3__n.BLIF N_175_0
+11 1
+.names  CYCLE_DMA_0_.BLIF pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2.X1
+1 1
+.names  A_28_.BLIF a_c_28__n
+1 1
+.names  N_243_2_i.BLIF N_243_2
+0 1
+.names  N_329_i.BLIF RST_c.BLIF N_176_i
+11 1
+.names  A_29_.BLIF a_c_29__n
+1 1
+.names  N_196.BLIF N_196_i
+0 1
+.names  BGACK_030_INT_i.BLIF RST_c.BLIF N_69_0
+11 1
+.names  CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
+1 1
+.names  CYCLE_DMA_1_.BLIF pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2.X2
+1 1
+.names  A_30_.BLIF a_c_30__n
+1 1
+.names  N_195.BLIF N_195_i
+0 1
+.names  N_145_i.BLIF SM_AMIGA_4_.BLIF N_178_0
+11 1
+.names  A_31_.BLIF a_c_31__n
+1 1
+.names  N_201.BLIF N_201_i
+0 1
+.names  inst_CLK_000_NE_D0.BLIF N_168.BLIF N_181_0
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C
+1 1
+.names  N_200.BLIF N_200_i
+0 1
+.names  inst_CLK_000_PE.BLIF SM_AMIGA_4_.BLIF N_183_0
+11 1
+.names  CYCLE_DMA_1_.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.X1
+1 1
+.names  A1.BLIF A1_c
+1 1
+.names  N_358_0.BLIF inst_AS_030_D0.D
+0 1
+.names  nEXP_SPACE.BLIF nEXP_SPACE_c
+1 1
+.names  N_239.BLIF N_239_i
+0 1
+.names  inst_VPA_D.BLIF VPA_D_i
+0 1
+.names  CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D
+1 1
+.names  N_209.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.X2
+1 1
+.names  pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n
+0 1
+.names  BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF un1_as_030_i
+11 1
+.names  BG_030.BLIF BG_030_c
+1 1
+.names  N_238.BLIF N_238_i
+0 1
+.names  nEXP_SPACE_D0_i.BLIF un5_ciin_i.BLIF N_61_0
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C
+1 1
+.names  BG_000DFFreg.BLIF BG_000
+1 1
+.names  pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n
+0 1
+.names  N_98_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_269_0
+11 1
+.names  inst_CLK_000_PE.BLIF pos_clk_CYCLE_DMA_5_0_i_0_x2.X1
+1 1
+.names  inst_BGACK_030_INTreg.BLIF BGACK_030
+1 1
+.names  N_237.BLIF N_237_i
+0 1
+.names  N_277_i.BLIF N_348_i.BLIF cpu_est_2_0_2__n
+11 1
+.names  BGACK_000.BLIF BGACK_000_c
+1 1
+.names  N_236.BLIF N_236_i
+0 1
+.names  N_154.BLIF N_278_i.BLIF cpu_est_2_0_3__n
+11 1
+.names  CYCLE_DMA_0_.BLIF pos_clk_CYCLE_DMA_5_0_i_0_x2.X2
+1 1
+.names  CLK_030.BLIF CLK_030_c
+1 1
+.names  AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c
+0 1
+.names  N_279_i.BLIF N_280_i.BLIF un5_e_0
+11 1
+.names  CLK_OSZI_c.BLIF CYCLE_DMA_0_.C
+1 1
+.names  CLK_000.BLIF inst_CLK_000_D0.D
+1 1
+.names  N_331.BLIF N_331_i
+0 1
+.names  BERR_c.BLIF CLK_000_PE_i.BLIF N_145_i
+11 1
+.names  CLK_OSZI.BLIF CLK_OSZI_c
+1 1
+.names  pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n
+0 1
+.names  inst_CLK_000_D1.BLIF CLK_000_D1_i
+0 1
+.names  inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_x2_0_.X1
+1 1
+.names  inst_CLK_OUT_INTreg.BLIF CLK_DIV_OUT
+1 1
+.names  N_356_0.BLIF N_356
+0 1
+.names  CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_147_i
+11 1
+.names  CLK_OUT_EXP_INT_i.BLIF CLK_EXP
+1 1
+.names  N_352_0.BLIF N_352
+0 1
+.names  CLK_030_c.BLIF CLK_030_i
+0 1
+.names  CLK_OSZI_c.BLIF CYCLE_DMA_1_.C
+1 1
+.names  cpu_est_0_.BLIF cpu_est_0_0_x2_0_x2_0_.X2
+1 1
+.names  un21_fpu_cs_i.BLIF FPU_CS
+1 1
+.names  N_8.BLIF N_8_i
+0 1
+.names  CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_152_0
+11 1
+.names  FPU_SENSE.BLIF FPU_SENSE_c
+1 1
+.names  N_46_0.BLIF inst_AS_000_DMA.D
+0 1
+.names  cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_154_i
+11 1
+.names  IPL_030DFF_0_reg.BLIF IPL_030_0_
+1 1
+.names  N_10.BLIF N_10_i
+0 1
+.names  cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_155_i
+11 1
+.names  inst_CLK_OUT_PRE_25.BLIF CLK_OUT_PRE_25_0.X1
+1 1
+.names  IPL_030DFF_1_reg.BLIF IPL_030_1_
+1 1
+.names  N_233.BLIF N_233_i
+0 1
+.names  cpu_est_1_.BLIF cpu_est_i_1__n
+0 1
+.names  CLK_OSZI_c.BLIF SIZE_DMA_0_.C
+1 1
+.names  IPL_030DFF_2_reg.BLIF IPL_030_2_
+1 1
+.names  N_357_0.BLIF N_357
+0 1
+.names  cpu_est_0_.BLIF cpu_est_1_.BLIF N_156_i
+11 1
+.names  inst_CLK_OUT_PRE_50.BLIF CLK_OUT_PRE_25_0.X2
+1 1
+.names  IPL_0_.BLIF ipl_c_0__n
+1 1
+.names  N_270_0.BLIF N_270
+0 1
+.names  N_156.BLIF cpu_est_2_.BLIF N_277
+11 1
+.names  IPL_1_.BLIF ipl_c_1__n
+1 1
+.names  inst_AS_000_DMA.BLIF AS_000_DMA_i
+0 1
+.names  N_156_i.BLIF cpu_est_2_.BLIF N_278
+11 1
+.names  IPL_2_.BLIF ipl_c_2__n
+1 1
+.names  N_137_0.BLIF N_137
+0 1
+.names  N_155_i.BLIF cpu_est_3_.BLIF N_279
+11 1
+.names  CLK_OSZI_c.BLIF SIZE_DMA_1_.C
+1 1
+.names  IPL_D0_0_.BLIF G_134.X1
+1 1
+.names  N_312.BLIF N_312_i
+0 1
+.names  BERR_i.BLIF SM_AMIGA_3_.BLIF N_313
+11 1
+.names  DTACK.BLIF DTACK_c
+1 1
+.names  pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n
+0 1
+.names  CLK_000_PE_i.BLIF SM_AMIGA_4_.BLIF N_318
+11 1
+.names  ipl_c_0__n.BLIF G_134.X2
+1 1
+.names  vcc_n_n.BLIF AVEC
+1 1
+.names  N_161_i.BLIF N_161
+0 1
+.names  CLK_000_N_SYNC_9_.BLIF N_152.BLIF N_321
+11 1
+.names  un5_e.BLIF E
+1 1
+.names  N_179_0.BLIF N_179
+0 1
+.names  inst_DTACK_D0.BLIF DTACK_D0_i
+0 1
+.names  CLK_OSZI_c.BLIF cpu_est_0_.C
+1 1
+.names  VPA.BLIF VPA_c
+1 1
+.names  N_180_0.BLIF N_180
+0 1
+.names  DTACK_D0_i.BLIF inst_VPA_D.BLIF N_326
+11 1
+.names  CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D
+1 1
+.names  inst_VMA_INTreg.BLIF VMA
+1 1
+.names  N_184_0.BLIF N_184
+0 1
+.names  N_145.BLIF SM_AMIGA_0_.BLIF N_329
+11 1
+.names  CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D
+1 1
+.names  RST.BLIF RST_c
+1 1
+.names  N_185_0.BLIF N_185
+0 1
+.names  cpu_est_2_.BLIF cpu_est_i_2__n
+0 1
+.names  CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D
+1 1
+.names  UDS_000_c.BLIF UDS_000_c_i
+0 1
+.names  N_156_i.BLIF cpu_est_i_2__n.BLIF N_348
+11 1
+.names  CLK_OSZI_c.BLIF cpu_est_1_.C
+1 1
+.names  CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D
+1 1
+.names  LDS_000_c.BLIF LDS_000_c_i
+0 1
+.names  N_373_i.BLIF N_375_i.BLIF pos_clk_un7_clk_000_pe_0_n
+11 1
+.names  CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
+1 1
+.names  FC_0_.BLIF fc_c_0__n
+1 1
+.names  N_173_i.BLIF N_173
+0 1
+.names  N_216_i.BLIF N_218_i.BLIF cpu_est_2_0_1__n
+11 1
+.names  cpu_est_0_0_x2_0_x2_0_.BLIF cpu_est_0_.D
+1 1
+.names  FC_1_.BLIF fc_c_1__n
+1 1
+.names  VPA_c.BLIF VPA_c_i
+0 1
+.names  N_219_i.BLIF N_220_i.BLIF N_283_0
+11 1
+.names  CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D
+1 1
+.names  gnd_n_n.BLIF AMIGA_ADDR_ENABLE
+1 1
+.names  N_56_0.BLIF inst_VPA_D.D
+0 1
+.names  N_224_i.BLIF N_225_i.BLIF N_282_0
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C
+1 1
+.names  CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D
+1 1
+.names  AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR
+1 1
+.names  DTACK_c.BLIF DTACK_c_i
+0 1
+.names  a_c_27__n.BLIF a_i_27__n
+0 1
+.names  CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D
+1 1
+.names  un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW
+1 1
+.names  N_57_0.BLIF inst_DTACK_D0.D
+0 1
+.names  a_c_28__n.BLIF a_i_28__n
+0 1
+.names  CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D
+1 1
+.names  N_190_i.BLIF AMIGA_BUS_ENABLE_HIGH
+1 1
+.names  ipl_c_1__n.BLIF ipl_c_i_1__n
+0 1
+.names  a_c_29__n.BLIF a_i_29__n
+0 1
+.names  CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
+1 1
+.names  N_53_0.BLIF IPL_D0_1_.D
+0 1
+.names  a_c_30__n.BLIF a_i_30__n
+0 1
+.names  CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C
+1 1
+.names  CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D
+1 1
+.names  N_165.BLIF BERR_i.BLIF N_208_1
+11 1
+.names  ipl_c_2__n.BLIF ipl_c_i_2__n
+0 1
+.names  a_c_31__n.BLIF a_i_31__n
+0 1
+.names  CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D
+1 1
+.names  N_208_1.BLIF CLK_000_NE_i.BLIF N_208
+11 1
+.names  N_54_0.BLIF IPL_D0_2_.D
+0 1
+.names  CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D
+1 1
+.names  N_171.BLIF BERR_i.BLIF N_207_1
+11 1
+.names  N_28.BLIF N_28_i
+0 1
+.names  CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D
+1 1
+.names  N_207_1.BLIF CLK_000_PE_i.BLIF N_207
+11 1
+.names  N_32_0.BLIF IPL_030DFF_1_reg.D
+0 1
+.names  N_181.BLIF N_313.BLIF N_206
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C
+1 1
+.names  CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D
+1 1
+.names  N_217_i.BLIF rst_dly_i_0__n.BLIF N_200_1
+11 1
+.names  N_29.BLIF N_29_i
+0 1
+.names  N_183.BLIF sm_amiga_i_3__n.BLIF N_211
+11 1
+.names  CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D
+1 1
+.names  N_200_1.BLIF rst_dly_i_1__n.BLIF N_200
+11 1
+.names  N_33_0.BLIF IPL_030DFF_2_reg.D
+0 1
+.names  cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_216
+11 1
+.names  CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D
+1 1
+.names  N_148.BLIF N_217_i.BLIF N_195_1
+11 1
+.names  N_378.BLIF N_378_i
+0 1
+.names  N_178.BLIF sm_amiga_i_5__n.BLIF N_221
+11 1
+.names  CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D
+1 1
+.names  N_195_1.BLIF rst_dly_i_2__n.BLIF N_195
+11 1
+.names  N_227.BLIF N_227_i
+0 1
+.names  RW_c.BLIF RW_i
+0 1
+.names  CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C
+1 1
+.names  CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D
+1 1
+.names  N_215_i.BLIF N_213_i.BLIF pos_clk_ipl_1_n
+11 1
+.names  N_354_0.BLIF N_354
+0 1
+.names  RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa
+11 1
+.names  CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D
+1 1
+.names  pos_clk_ipl_1_n.BLIF N_214_i.BLIF pos_clk_ipl_n
+11 1
+.names  N_7.BLIF N_7_i
+0 1
+.names  N_159.BLIF SM_AMIGA_1_.BLIF N_98
+11 1
+.names  CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D
+1 1
+.names  N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D
+11 1
+.names  N_47_0.BLIF inst_AS_030_000_SYNC.D
+0 1
+.names  pos_clk_un3_as_030_d0_i_n.BLIF un1_SM_AMIGA_5.BLIF DS_000_ENABLE_1_sqmuxa_1
+11 1
+.names  N_188_i.BLIF N_205_i.BLIF N_142_i_1
+11 1
+.names  N_5.BLIF N_5_i
+0 1
+.names  inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
+0 1
+.names  CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C
+1 1
+.names  N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D
+11 1
+.names  N_48_0.BLIF inst_AS_000_INT.D
+0 1
+.names  G_134.BLIF N_213_i
+0 1
+.names  cpu_est_1_.BLIF cpu_est_2_.BLIF N_280_1
+11 1
+.names  N_3.BLIF N_3_i
+0 1
+.names  G_135.BLIF N_214_i
+0 1
+.names  N_280_1.BLIF cpu_est_i_3__n.BLIF N_280
+11 1
+.names  N_50_0.BLIF inst_DS_000_DMA.D
+0 1
+.names  G_136.BLIF N_215_i
+0 1
+.names  N_150_i.BLIF RST_c.BLIF N_225_1
+11 1
+.names  nEXP_SPACE_c.BLIF nEXP_SPACE_c_i
+0 1
+.names  a_c_25__n.BLIF a_i_25__n
+0 1
+.names  CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C
+1 1
+.names  N_225_1.BLIF sm_amiga_i_i_7__n.BLIF N_225
+11 1
+.names  N_55_0.BLIF inst_nEXP_SPACE_D0reg.D
+0 1
+.names  a_c_26__n.BLIF a_i_26__n
+0 1
+.names  N_174.BLIF RST_c.BLIF N_224_1
+11 1
+.names  AS_000_c.BLIF AS_000_i
+0 1
+.names  inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n
+0 1
+.names  N_224_1.BLIF SM_AMIGA_6_.BLIF N_224
+11 1
+.names  inst_DS_000_DMA.BLIF DS_000_DMA_i
+0 1
+.names  cpu_est_2_2__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n
+11 1
+.names  N_175.BLIF RST_c.BLIF N_219_1
+11 1
+.names  AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030
+11 1
+.names  cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C
+1 1
+.names  N_219_1.BLIF SM_AMIGA_2_.BLIF N_219
+11 1
+.names  N_190.BLIF N_190_i
+0 1
+.names  cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D
+1- 1
+-1 1
+.names  cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_218_1
+11 1
+.names  un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i
+0 1
+.names  inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n
+0 1
+.names  N_218_1.BLIF cpu_est_i_3__n.BLIF N_218
+11 1
+.names  un21_fpu_cs.BLIF un21_fpu_cs_i
+0 1
+.names  cpu_est_2_3__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n
+11 1
+.names  inst_CLK_000_NE_D0.BLIF N_168.BLIF N_212_1
+11 1
+.names  inst_CLK_OUT_EXP_INT.BLIF CLK_OUT_EXP_INT_i
+0 1
+.names  cpu_est_3_.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C
+1 1
+.names  N_212_1.BLIF sm_amiga_i_4__n.BLIF N_212
+11 1
+.names  pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n
+0 1
+.names  cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D
+1- 1
+-1 1
+.names  inst_AS_030_D0.BLIF inst_CLK_000_D0.BLIF N_128_i_1
+11 1
+.names  ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n
+11 1
+.names  pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n
+0 1
+.names  N_128_i_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_128_i
+11 1
+.names  IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
+11 1
+.names  ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n
+11 1
+.names  N_193_i.BLIF N_241_i.BLIF N_134_i_1
+11 1
+.names  ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28
+1- 1
+-1 1
+.names  IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C
+1 1
+.names  N_134_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D
+11 1
+.names  N_29_i.BLIF RST_c.BLIF N_33_0
+11 1
+.names  ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27
+1- 1
+-1 1
+.names  N_240_i.BLIF sm_amiga_i_5__n.BLIF N_124_0_1
+11 1
+.names  N_28_i.BLIF RST_c.BLIF N_32_0
+11 1
+.names  DS_000_ENABLE_1_sqmuxa.BLIF DS_000_ENABLE_1_sqmuxa_i
+0 1
+.names  N_124_0_1.BLIF SM_AMIGA_i_7_.BLIF N_124_0
+11 1
+.names  ipl_c_i_2__n.BLIF RST_c.BLIF N_54_0
+11 1
+.names  N_124.BLIF rw_000_int_0_un3_n
+0 1
+.names  N_147_i.BLIF CLK_000_N_SYNC_0_.D
+1 1
+.names  pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF AS_000_i.BLIF N_267_i_1
+11 1
+.names  ipl_c_i_1__n.BLIF RST_c.BLIF N_53_0
+11 1
+.names  DS_000_ENABLE_1_sqmuxa_i.BLIF N_124.BLIF rw_000_int_0_un1_n
+11 1
+.names  N_267_i_1.BLIF N_69_0.BLIF CYCLE_DMA_1_.D
+11 1
+.names  DTACK_c_i.BLIF RST_c.BLIF N_57_0
+11 1
+.names  inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C
+1 1
+.names  pos_clk_CYCLE_DMA_5_0_i_0_x2.BLIF AS_000_i.BLIF N_268_i_1
+11 1
+.names  RST_c.BLIF VPA_c_i.BLIF N_56_0
+11 1
+.names  rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_18
+1- 1
+-1 1
+.names  N_268_i_1.BLIF N_69_0.BLIF CYCLE_DMA_0_.D
+11 1
+.names  RST_c.BLIF nEXP_SPACE_c_i.BLIF N_55_0
+11 1
+.names  SM_AMIGA_6_.BLIF uds_000_int_0_un3_n
+0 1
+.names  N_161_i.BLIF N_228_i.BLIF N_355_0_1
+11 1
+.names  N_3_i.BLIF RST_c.BLIF N_50_0
+11 1
+.names  A0_c.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n
+11 1
+.names  N_355_0_1.BLIF RW_000_i.BLIF N_355_0
+11 1
+.names  N_5_i.BLIF RST_c.BLIF N_48_0
+11 1
+.names  inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C
+1 1
+.names  N_161_i.BLIF N_226_i.BLIF N_353_i_1
+11 1
+.names  N_7_i.BLIF RST_c.BLIF N_47_0
+11 1
+.names  uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21
+1- 1
+-1 1
+.names  N_353_i_1.BLIF RST_c.BLIF inst_CLK_030_H.D
+11 1
+.names  N_357.BLIF as_030_000_sync_0_un3_n
+0 1
+.names  pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n
+0 1
+.names  N_221_i.BLIF N_222_i.BLIF N_140_i_1
+11 1
+.names  pos_clk_un3_as_030_d0_n.BLIF N_357.BLIF as_030_000_sync_0_un1_n
+11 1
+.names  cpu_est_i_1__n.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n
+11 1
+.names  a_i_18__n.BLIF a_i_19__n.BLIF N_410_3
+11 1
+.names  inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF as_030_000_sync_0_un0_n
+11 1
+.names  inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C
+1 1
+.names  N_410_1.BLIF N_410_2.BLIF N_410_4
+11 1
+.names  as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_7
+1- 1
+-1 1
+.names  vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_22
+1- 1
+-1 1
+.names  N_410_4.BLIF N_410_3.BLIF N_410
+11 1
+.names  SM_AMIGA_5_.BLIF sm_amiga_i_5__n
+0 1
+.names  pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n
+0 1
+.names  AS_000_i.BLIF BGACK_030_INT_i.BLIF N_237_1
+11 1
+.names  N_270.BLIF as_000_int_0_un3_n
+0 1
+.names  BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n
+11 1
+.names  RW_000_c.BLIF nEXP_SPACE_D0_i.BLIF N_237_2
+11 1
+.names  sm_amiga_i_5__n.BLIF N_270.BLIF as_000_int_0_un1_n
+11 1
+.names  BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C
+1 1
+.names  N_237_1.BLIF N_237_2.BLIF N_237
+11 1
+.names  inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
+11 1
+.names  bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26
+1- 1
+-1 1
+.names  AS_030_i.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1
+11 1
+.names  as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_5
+1- 1
+-1 1
+.names  N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D
+11 1
+.names  un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs
+11 1
+.names  N_355.BLIF ds_000_dma_0_un3_n
+0 1
+.names  N_26_i.BLIF RST_c.BLIF N_34_0
+11 1
+.names  un22_berr_1.BLIF AS_030_i.BLIF un22_berr_1_0
+11 1
+.names  N_354.BLIF N_355.BLIF ds_000_dma_0_un1_n
+11 1
+.names  N_22_i.BLIF RST_c.BLIF N_38_0
+11 1
+.names  CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C
+1 1
+.names  un22_berr_1_0.BLIF FPU_SENSE_c.BLIF un22_berr
+11 1
+.names  inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n
+11 1
+.names  N_21_i.BLIF RST_c.BLIF N_39_0
+11 1
+.names  N_327.BLIF N_410_i_0.BLIF N_233_1
+11 1
+.names  ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3
+1- 1
+-1 1
+.names  N_18_i.BLIF RST_c.BLIF N_42_0
+11 1
+.names  sm_amiga_i_i_7__n.BLIF inst_nEXP_SPACE_D0reg.BLIF N_233_2
+11 1
+.names  inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_240
+11 1
+.names  N_17_i.BLIF RST_c.BLIF N_43_0
+11 1
+.names  N_233_1.BLIF N_233_2.BLIF N_233
+11 1
+.names  inst_CLK_030_H.BLIF CLK_030_c.BLIF N_228
+11 1
+.names  N_4_i.BLIF RST_c.BLIF N_49_0
+11 1
+.names  CLK_OSZI_c.BLIF RST_DLY_0_.C
+1 1
+.names  N_281_i.BLIF N_302_i.BLIF N_245_i_1
+11 1
+.names  RW_000_c.BLIF RW_000_i
+0 1
+.names  ipl_c_i_0__n.BLIF RST_c.BLIF N_52_0
+11 1
+.names  N_245_i_1.BLIF RST_c.BLIF RST_DLY_0_.D
+11 1
+.names  inst_AS_000_DMA.BLIF RW_000_i.BLIF N_227
+11 1
+.names  N_27_i.BLIF RST_c.BLIF N_31_0
+11 1
+.end
diff --git a/Logic/BUS68030.bl1 b/Logic/BUS68030.bl1
new file mode 100644
index 0000000..b63d398
--- /dev/null
+++ b/Logic/BUS68030.bl1
@@ -0,0 +1,2325 @@
+#$ TOOL ispLEVER Classic 1.8.00.04.29.14
+#$ DATE Sun Jan 24 16:20:54 2016
+#$ MODULE bus68030
+#$ PINS 75 A_9_ A_8_ SIZE_1_ A_7_ A_6_ A_31_ A_5_ A_4_ IPL_030_2_ A_3_ A_2_ IPL_2_ \
+#  IPL_030_1_ IPL_030_0_ FC_1_ IPL_1_ AS_030 IPL_0_ AS_000 FC_0_ RW_000 DS_030 UDS_000 \
+#  LDS_000 A0 A1 nEXP_SPACE BERR BG_030 BG_000 BGACK_030 BGACK_000 CLK_030 CLK_000 CLK_OSZI \
+#  CLK_DIV_OUT CLK_EXP FPU_CS FPU_SENSE DSACK1 DTACK AVEC E VPA VMA RST RESET RW \
+#  AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR SIZE_0_ AMIGA_BUS_ENABLE_LOW A_30_ \
+#  AMIGA_BUS_ENABLE_HIGH A_29_ CIIN A_28_ A_27_ A_26_ A_25_ A_24_ A_23_ A_22_ A_21_ A_20_ \
+#  A_19_ A_18_ A_17_ A_16_ A_15_ A_14_ A_13_ A_12_ A_11_ A_10_
+#$ NODES 681 N_184 N_184_0 rw_000_dma_0_un1_n N_180 N_185_0 rw_000_dma_0_un0_n N_179 \
+#  UDS_000_c_i a0_dma_0_un3_n pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2 LDS_000_c_i \
+#  a0_dma_0_un1_n N_312 N_173_i a0_dma_0_un0_n N_270 N_358_0 \
+#  amiga_bus_enable_dma_low_0_un3_n inst_BGACK_030_INTreg N_357 N_239_i \
+#  amiga_bus_enable_dma_low_0_un1_n inst_CLK_OUT_INTreg N_354 \
+#  pos_clk_size_dma_6_0_1__n amiga_bus_enable_dma_low_0_un0_n vcc_n_n N_227 N_238_i \
+#  amiga_bus_enable_dma_high_0_un3_n un5_e N_378 pos_clk_size_dma_6_0_0__n \
+#  amiga_bus_enable_dma_high_0_un1_n inst_VMA_INTreg N_29 N_237_i \
+#  amiga_bus_enable_dma_high_0_un0_n gnd_n_n N_28 N_236_i cpu_est_0_2__un3_n \
+#  un1_amiga_bus_enable_low N_3 AMIGA_BUS_DATA_DIR_c_0 cpu_est_0_2__un1_n un3_size N_5 \
+#  N_331_i cpu_est_0_2__un0_n un4_size N_7 pos_clk_un6_bgack_000_0_n \
+#  cpu_est_0_3__un3_n un4_uds_000 N_190_i N_356_0 cpu_est_0_3__un1_n un4_lds_000 \
+#  un1_amiga_bus_enable_low_i N_352_0 cpu_est_0_3__un0_n un5_ciin un21_fpu_cs_i N_8_i \
+#  ipl_030_0_0__un3_n un4_as_000 CLK_OUT_EXP_INT_i N_46_0 ipl_030_0_0__un1_n \
+#  un1_SM_AMIGA_5 AS_000_i N_10_i ipl_030_0_0__un0_n un21_fpu_cs DS_000_DMA_i N_44_0 \
+#  rw_000_int_0_un3_n un22_berr sm_amiga_i_5__n N_19_i rw_000_int_0_un1_n un6_ds_030 \
+#  sm_amiga_i_6__n N_41_0 rw_000_int_0_un0_n cpu_est_0_ sm_amiga_i_0__n N_20_i \
+#  uds_000_int_0_un3_n cpu_est_1_ CLK_000_NE_i N_40_0 uds_000_int_0_un1_n cpu_est_2_ \
+#  sm_amiga_i_4__n N_24_i uds_000_int_0_un0_n cpu_est_3_ RW_000_i N_36_0 \
+#  vma_int_0_un3_n inst_AS_000_INT sm_amiga_i_2__n N_25_i vma_int_0_un1_n SM_AMIGA_5_ \
+#  CLK_000_D0_i N_35_0 vma_int_0_un0_n inst_AMIGA_BUS_ENABLE_DMA_LOW BERR_i \
+#  bg_000_0_un3_n inst_AS_030_D0 sm_amiga_i_1__n N_198_i bg_000_0_un1_n \
+#  inst_nEXP_SPACE_D0reg CLK_000_PE_i N_243_2_i bg_000_0_un0_n inst_AS_030_000_SYNC \
+#  N_410_i_0 N_196_i cpu_est_0_1__un3_n inst_BGACK_030_INT_D sm_amiga_i_i_7__n N_195_i \
+#  cpu_est_0_1__un1_n inst_AS_000_DMA AS_030_i cpu_est_0_1__un0_n inst_DS_000_DMA \
+#  FPU_SENSE_i N_201_i dsack1_int_0_un3_n CYCLE_DMA_0_ nEXP_SPACE_D0_i N_200_i \
+#  dsack1_int_0_un1_n CYCLE_DMA_1_ BGACK_030_INT_i N_199_i dsack1_int_0_un0_n \
+#  SIZE_DMA_0_ AMIGA_BUS_ENABLE_DMA_HIGH_i N_182_0 ds_000_enable_0_un3_n SIZE_DMA_1_ \
+#  A1_i N_158_i ds_000_enable_0_un1_n inst_VPA_D CLK_030_H_i N_148_i \
+#  ds_000_enable_0_un0_n inst_UDS_000_INT a_i_16__n N_307_i lds_000_int_0_un3_n \
+#  inst_LDS_000_INT a_i_18__n N_143_0 lds_000_int_0_un1_n inst_CLK_OUT_PRE_D a_i_19__n \
+#  N_217_i lds_000_int_0_un0_n inst_DTACK_D0 N_114_i N_235_i a_15__n inst_RESET_OUT \
+#  N_113_i inst_CLK_OUT_PRE_50 AS_000_INT_i N_210_i a_14__n inst_CLK_OUT_PRE_25 \
+#  AMIGA_BUS_ENABLE_DMA_LOW_i inst_CLK_000_D1 rst_dly_i_2__n N_207_i a_13__n \
+#  inst_CLK_000_D0 rst_dly_i_0__n N_208_i inst_CLK_000_PE rst_dly_i_1__n N_206_i \
+#  a_12__n inst_CLK_OUT_EXP_INT RESET_OUT_i CLK_000_P_SYNC_9_ size_dma_i_1__n N_313_i \
+#  a_11__n inst_CLK_000_NE size_dma_i_0__n N_211_i CLK_000_N_SYNC_11_ AS_030_D0_i \
+#  N_212_i a_10__n IPL_D0_0_ a_i_24__n N_183_0 IPL_D0_1_ sm_amiga_i_3__n N_181_0 a_9__n \
+#  IPL_D0_2_ cpu_est_i_3__n N_178_0 inst_CLK_000_NE_D0 cpu_est_i_0__n N_69_0 a_8__n \
+#  SM_AMIGA_0_ VPA_D_i N_329_i inst_AMIGA_BUS_ENABLE_DMA_HIGH cpu_est_i_1__n N_176_i \
+#  a_7__n inst_DSACK1_INTreg CLK_030_i N_175_0 pos_clk_ipl_n CLK_000_D1_i N_174_0 a_6__n \
+#  SM_AMIGA_4_ cpu_est_i_2__n N_171_0 inst_DS_000_ENABLE DTACK_D0_i un1_SM_AMIGA_5_i \
+#  a_5__n RST_DLY_0_ RW_i N_324_i RST_DLY_1_ a_i_31__n N_326_i a_4__n RST_DLY_2_ a_i_29__n \
+#  N_168_i pos_clk_un8_bg_030_n a_i_30__n VMA_INT_i a_3__n CLK_000_P_SYNC_0_ a_i_27__n \
+#  N_165_i CLK_000_P_SYNC_1_ a_i_28__n N_164_i a_2__n CLK_000_P_SYNC_2_ a_i_25__n \
+#  N_162_i CLK_000_P_SYNC_3_ a_i_26__n clk_000_n_sync_i_10__n CLK_000_P_SYNC_4_ \
+#  N_213_i N_321_i CLK_000_P_SYNC_5_ N_214_i N_159_0 CLK_000_P_SYNC_6_ N_215_i N_318_i \
+#  CLK_000_P_SYNC_7_ N_156_i CLK_000_P_SYNC_8_ DS_000_ENABLE_1_sqmuxa_i N_155_i \
+#  CLK_000_N_SYNC_0_ N_98_i N_154_i CLK_000_N_SYNC_1_ un6_ds_030_i CLK_OUT_PRE_D_i \
+#  CLK_000_N_SYNC_2_ un4_as_000_i N_152_0 CLK_000_N_SYNC_3_ un4_lds_000_i N_150_i \
+#  CLK_000_N_SYNC_4_ un4_uds_000_i AS_030_000_SYNC_i CLK_000_N_SYNC_5_ LDS_000_INT_i \
+#  N_147_i CLK_000_N_SYNC_6_ UDS_000_INT_i N_145_i CLK_000_N_SYNC_7_ AS_030_c N_281_i \
+#  CLK_000_N_SYNC_8_ N_302_i CLK_000_N_SYNC_9_ AS_000_c CLK_000_N_SYNC_10_ N_279_i \
+#  inst_RW_000_INT RW_000_c N_280_i inst_RW_000_DMA un5_e_0 pos_clk_un7_clk_000_pe_n \
+#  N_278_i inst_A0_DMA UDS_000_c cpu_est_2_0_3__n SM_AMIGA_6_ N_277_i \
+#  DS_000_ENABLE_1_sqmuxa LDS_000_c N_348_i inst_CLK_030_H cpu_est_2_0_2__n \
+#  SM_AMIGA_1_ size_c_0__n N_128_i SM_AMIGA_3_ N_193_i SM_AMIGA_2_ size_c_1__n N_241_i \
+#  pos_clk_un3_as_030_d0_n DS_000_ENABLE_1_sqmuxa_1 N_240_i N_4 N_124_0 N_6 N_269_0 \
+#  un5_ciin_i N_61_0 un1_as_030_i N_17 N_228_i N_18 N_355_0 N_21 N_226_i N_22 N_26 N_224_i \
+#  N_27 N_225_i CLK_OUT_PRE_25_0 N_282_0 N_221_i N_222_i N_219_i N_220_i N_283_0 N_216_i \
+#  N_218_i cpu_est_2_0_1__n N_373_i N_375_i pos_clk_un7_clk_000_pe_0_n N_188_i \
+#  a_c_16__n N_205_i a_c_17__n pos_clk_un8_sm_amiga_i_n A0_c_i a_c_18__n size_c_i_1__n \
+#  N_27_i a_c_19__n N_31_0 ipl_c_i_0__n a_c_20__n N_52_0 N_4_i a_c_21__n N_49_0 N_17_i \
+#  SM_AMIGA_i_7_ a_c_22__n N_43_0 N_124 N_18_i cpu_est_2_1__n a_c_23__n N_42_0 \
+#  cpu_est_2_2__n N_21_i cpu_est_2_3__n a_c_24__n N_39_0 G_134 N_22_i G_135 a_c_25__n \
+#  N_38_0 G_136 N_26_i N_269 a_c_26__n N_34_0 N_61 BG_030_c_i a_c_27__n \
+#  pos_clk_un8_bg_030_0_n N_98 N_161_i_1 a_c_28__n N_161_i_2 \
+#  pos_clk_un8_sm_amiga_i_1_n N_355 a_c_29__n N_324_1 N_324_2 N_128 a_c_30__n N_150_i_1 \
+#  N_137 un1_SM_AMIGA_5_i_1 N_145 a_c_31__n un1_SM_AMIGA_5_i_2 N_148 N_138_i_1 N_150 A0_c \
+#  N_138_i_2 N_152 N_146_i_1 N_154 A1_c N_146_i_2 N_156 N_146_i_3 N_159 nEXP_SPACE_c \
+#  N_220_1 N_161 N_220_2 N_165 BERR_c N_375_1 N_168 N_375_2 N_171 BG_030_c N_373_1 N_174 \
+#  N_373_2 N_175 BG_000DFFreg N_210_1 N_178 N_210_2 N_181 N_210_3 N_183 BGACK_000_c \
+#  un5_ciin_1 N_188 un5_ciin_2 N_190 CLK_030_c un5_ciin_3 N_193 un5_ciin_4 N_195 \
+#  un5_ciin_5 N_200 un5_ciin_6 N_205 CLK_OSZI_c un5_ciin_7 N_206 un5_ciin_8 N_207 \
+#  un5_ciin_9 N_208 un5_ciin_10 N_210 un5_ciin_11 N_211 FPU_SENSE_c N_302_1 N_212 \
+#  N_244_i_1 N_373 IPL_030DFF_0_reg N_244_i_2 N_375 N_243_i_1 N_216 IPL_030DFF_1_reg \
+#  N_410_1 N_218 N_410_2 N_219 IPL_030DFF_2_reg N_410_3 N_220 N_410_4 N_221 ipl_c_0__n \
+#  N_237_1 N_222 N_237_2 N_224 ipl_c_1__n un21_fpu_cs_1 N_225 un22_berr_1_0 N_226 \
+#  ipl_c_2__n N_233_1 N_228 N_233_2 N_230 N_245_i_1 N_231 DTACK_c N_128_i_1 N_240 N_134_i_1 \
+#  N_241 N_124_0_1 N_277 N_267_i_1 N_278 VPA_c N_268_i_1 N_279 N_355_0_1 N_280 N_353_i_1 \
+#  N_281 RST_c N_140_i_1 N_302 N_142_i_1 N_313 N_280_1 N_318 RW_c N_225_1 N_321 N_224_1 N_324 \
+#  fc_c_0__n N_219_1 N_326 N_218_1 N_329 fc_c_1__n N_212_1 N_332 N_208_1 N_348 N_207_1 \
+#  cpu_est_0_0_x2_0_x2_0_ AMIGA_BUS_DATA_DIR_c N_200_1 pos_clk_CYCLE_DMA_5_0_i_0_x2 \
+#  N_195_1 pos_clk_CYCLE_DMA_5_1_i_0_x2 pos_clk_ipl_1_n N_235 ipl_030_0_1__un3_n N_196 \
+#  ipl_030_0_1__un1_n N_143 N_7_i ipl_030_0_1__un0_n N_158 N_47_0 \
+#  as_030_000_sync_0_un3_n N_198 N_5_i as_030_000_sync_0_un1_n N_199 N_48_0 \
+#  as_030_000_sync_0_un0_n N_307 N_3_i as_000_int_0_un3_n N_201 N_50_0 \
+#  as_000_int_0_un1_n N_182 nEXP_SPACE_c_i as_000_int_0_un0_n N_243_2 N_55_0 \
+#  ds_000_dma_0_un3_n N_8 VPA_c_i ds_000_dma_0_un1_n N_356 N_56_0 ds_000_dma_0_un0_n \
+#  N_10 DTACK_c_i ipl_030_0_2__un3_n pos_clk_un6_bgack_000_n N_57_0 ipl_030_0_2__un1_n \
+#  N_19 ipl_c_i_1__n ipl_030_0_2__un0_n N_352 N_53_0 \
+#  un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n N_327 ipl_c_i_2__n \
+#  un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n N_20 N_54_0 \
+#  un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n pos_clk_a0_dma_3_n N_28_i \
+#  sm_amiga_srsts_i_0_0_m3_1__un3_n N_24 N_32_0 sm_amiga_srsts_i_0_0_m3_1__un1_n \
+#  N_113 N_29_i sm_amiga_srsts_i_0_0_m3_1__un0_n N_25 N_33_0 \
+#  sm_amiga_srsts_i_0_0_m3_5__un3_n N_114 N_378_i sm_amiga_srsts_i_0_0_m3_5__un1_n \
+#  pos_clk_size_dma_6_0__n sm_amiga_srsts_i_0_0_m3_5__un0_n N_232 \
+#  size_dma_0_0__un3_n pos_clk_size_dma_6_1__n N_227_i size_dma_0_0__un1_n N_410 \
+#  N_354_0 size_dma_0_0__un0_n N_185 N_233_i size_dma_0_1__un3_n N_236 N_357_0 \
+#  size_dma_0_1__un1_n N_238 N_270_0 size_dma_0_1__un0_n N_173 AS_000_DMA_i \
+#  as_000_dma_0_un3_n N_239 N_137_0 as_000_dma_0_un1_n N_331 N_312_i as_000_dma_0_un0_n \
+#  N_237 pos_clk_un3_as_030_d0_i_n bgack_030_int_0_un3_n un22_berr_1 N_161_i \
+#  bgack_030_int_0_un1_n N_233 N_179_0 bgack_030_int_0_un0_n N_209 N_180_0 \
+#  rw_000_dma_0_un3_n
+.model bus68030
+.inputs A_31_.BLIF IPL_2_.BLIF FC_1_.BLIF A1.BLIF nEXP_SPACE.BLIF BG_030.BLIF \
+BGACK_000.BLIF CLK_030.BLIF CLK_000.BLIF CLK_OSZI.BLIF FPU_SENSE.BLIF \
+DTACK.BLIF VPA.BLIF RST.BLIF A_30_.BLIF A_29_.BLIF A_28_.BLIF A_27_.BLIF \
+A_26_.BLIF A_25_.BLIF A_24_.BLIF A_23_.BLIF A_22_.BLIF A_21_.BLIF A_20_.BLIF \
+A_19_.BLIF A_18_.BLIF A_17_.BLIF A_16_.BLIF A_15_.BLIF A_14_.BLIF A_13_.BLIF \
+A_12_.BLIF A_11_.BLIF A_10_.BLIF A_9_.BLIF A_8_.BLIF A_7_.BLIF A_6_.BLIF \
+A_5_.BLIF A_4_.BLIF A_3_.BLIF A_2_.BLIF IPL_1_.BLIF IPL_0_.BLIF FC_0_.BLIF \
+SIZE_1_.BLIF AS_030.BLIF AS_000.BLIF RW_000.BLIF UDS_000.BLIF LDS_000.BLIF \
+A0.BLIF BERR.BLIF RW.BLIF SIZE_0_.BLIF N_184.BLIF N_184_0.BLIF \
+rw_000_dma_0_un1_n.BLIF N_180.BLIF N_185_0.BLIF rw_000_dma_0_un0_n.BLIF \
+N_179.BLIF UDS_000_c_i.BLIF a0_dma_0_un3_n.BLIF \
+pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2.BLIF LDS_000_c_i.BLIF \
+a0_dma_0_un1_n.BLIF N_312.BLIF N_173_i.BLIF a0_dma_0_un0_n.BLIF N_270.BLIF \
+N_358_0.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF inst_BGACK_030_INTreg.BLIF \
+N_357.BLIF N_239_i.BLIF amiga_bus_enable_dma_low_0_un1_n.BLIF \
+inst_CLK_OUT_INTreg.BLIF N_354.BLIF pos_clk_size_dma_6_0_1__n.BLIF \
+amiga_bus_enable_dma_low_0_un0_n.BLIF vcc_n_n.BLIF N_227.BLIF N_238_i.BLIF \
+amiga_bus_enable_dma_high_0_un3_n.BLIF un5_e.BLIF N_378.BLIF \
+pos_clk_size_dma_6_0_0__n.BLIF amiga_bus_enable_dma_high_0_un1_n.BLIF \
+inst_VMA_INTreg.BLIF N_29.BLIF N_237_i.BLIF \
+amiga_bus_enable_dma_high_0_un0_n.BLIF gnd_n_n.BLIF N_28.BLIF N_236_i.BLIF \
+cpu_est_0_2__un3_n.BLIF un1_amiga_bus_enable_low.BLIF N_3.BLIF \
+AMIGA_BUS_DATA_DIR_c_0.BLIF cpu_est_0_2__un1_n.BLIF un3_size.BLIF N_5.BLIF \
+N_331_i.BLIF cpu_est_0_2__un0_n.BLIF un4_size.BLIF N_7.BLIF \
+pos_clk_un6_bgack_000_0_n.BLIF cpu_est_0_3__un3_n.BLIF un4_uds_000.BLIF \
+N_190_i.BLIF N_356_0.BLIF cpu_est_0_3__un1_n.BLIF un4_lds_000.BLIF \
+un1_amiga_bus_enable_low_i.BLIF N_352_0.BLIF cpu_est_0_3__un0_n.BLIF \
+un5_ciin.BLIF un21_fpu_cs_i.BLIF N_8_i.BLIF ipl_030_0_0__un3_n.BLIF \
+un4_as_000.BLIF CLK_OUT_EXP_INT_i.BLIF N_46_0.BLIF ipl_030_0_0__un1_n.BLIF \
+un1_SM_AMIGA_5.BLIF AS_000_i.BLIF N_10_i.BLIF ipl_030_0_0__un0_n.BLIF \
+un21_fpu_cs.BLIF DS_000_DMA_i.BLIF N_44_0.BLIF rw_000_int_0_un3_n.BLIF \
+un22_berr.BLIF sm_amiga_i_5__n.BLIF N_19_i.BLIF rw_000_int_0_un1_n.BLIF \
+un6_ds_030.BLIF sm_amiga_i_6__n.BLIF N_41_0.BLIF rw_000_int_0_un0_n.BLIF \
+cpu_est_0_.BLIF sm_amiga_i_0__n.BLIF N_20_i.BLIF uds_000_int_0_un3_n.BLIF \
+cpu_est_1_.BLIF CLK_000_NE_i.BLIF N_40_0.BLIF uds_000_int_0_un1_n.BLIF \
+cpu_est_2_.BLIF sm_amiga_i_4__n.BLIF N_24_i.BLIF uds_000_int_0_un0_n.BLIF \
+cpu_est_3_.BLIF RW_000_i.BLIF N_36_0.BLIF vma_int_0_un3_n.BLIF \
+inst_AS_000_INT.BLIF sm_amiga_i_2__n.BLIF N_25_i.BLIF vma_int_0_un1_n.BLIF \
+SM_AMIGA_5_.BLIF CLK_000_D0_i.BLIF N_35_0.BLIF vma_int_0_un0_n.BLIF \
+inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF BERR_i.BLIF bg_000_0_un3_n.BLIF \
+inst_AS_030_D0.BLIF sm_amiga_i_1__n.BLIF N_198_i.BLIF bg_000_0_un1_n.BLIF \
+inst_nEXP_SPACE_D0reg.BLIF CLK_000_PE_i.BLIF N_243_2_i.BLIF \
+bg_000_0_un0_n.BLIF inst_AS_030_000_SYNC.BLIF N_410_i_0.BLIF N_196_i.BLIF \
+cpu_est_0_1__un3_n.BLIF inst_BGACK_030_INT_D.BLIF sm_amiga_i_i_7__n.BLIF \
+N_195_i.BLIF cpu_est_0_1__un1_n.BLIF inst_AS_000_DMA.BLIF AS_030_i.BLIF \
+cpu_est_0_1__un0_n.BLIF inst_DS_000_DMA.BLIF FPU_SENSE_i.BLIF N_201_i.BLIF \
+dsack1_int_0_un3_n.BLIF CYCLE_DMA_0_.BLIF nEXP_SPACE_D0_i.BLIF N_200_i.BLIF \
+dsack1_int_0_un1_n.BLIF CYCLE_DMA_1_.BLIF BGACK_030_INT_i.BLIF N_199_i.BLIF \
+dsack1_int_0_un0_n.BLIF SIZE_DMA_0_.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \
+N_182_0.BLIF ds_000_enable_0_un3_n.BLIF SIZE_DMA_1_.BLIF A1_i.BLIF \
+N_158_i.BLIF ds_000_enable_0_un1_n.BLIF inst_VPA_D.BLIF CLK_030_H_i.BLIF \
+N_148_i.BLIF ds_000_enable_0_un0_n.BLIF inst_UDS_000_INT.BLIF a_i_16__n.BLIF \
+N_307_i.BLIF lds_000_int_0_un3_n.BLIF inst_LDS_000_INT.BLIF a_i_18__n.BLIF \
+N_143_0.BLIF lds_000_int_0_un1_n.BLIF inst_CLK_OUT_PRE_D.BLIF a_i_19__n.BLIF \
+N_217_i.BLIF lds_000_int_0_un0_n.BLIF inst_DTACK_D0.BLIF N_114_i.BLIF \
+N_235_i.BLIF a_15__n.BLIF inst_RESET_OUT.BLIF N_113_i.BLIF \
+inst_CLK_OUT_PRE_50.BLIF AS_000_INT_i.BLIF N_210_i.BLIF a_14__n.BLIF \
+inst_CLK_OUT_PRE_25.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF inst_CLK_000_D1.BLIF \
+rst_dly_i_2__n.BLIF N_207_i.BLIF a_13__n.BLIF inst_CLK_000_D0.BLIF \
+rst_dly_i_0__n.BLIF N_208_i.BLIF inst_CLK_000_PE.BLIF rst_dly_i_1__n.BLIF \
+N_206_i.BLIF a_12__n.BLIF inst_CLK_OUT_EXP_INT.BLIF RESET_OUT_i.BLIF \
+CLK_000_P_SYNC_9_.BLIF size_dma_i_1__n.BLIF N_313_i.BLIF a_11__n.BLIF \
+inst_CLK_000_NE.BLIF size_dma_i_0__n.BLIF N_211_i.BLIF CLK_000_N_SYNC_11_.BLIF \
+AS_030_D0_i.BLIF N_212_i.BLIF a_10__n.BLIF IPL_D0_0_.BLIF a_i_24__n.BLIF \
+N_183_0.BLIF IPL_D0_1_.BLIF sm_amiga_i_3__n.BLIF N_181_0.BLIF a_9__n.BLIF \
+IPL_D0_2_.BLIF cpu_est_i_3__n.BLIF N_178_0.BLIF inst_CLK_000_NE_D0.BLIF \
+cpu_est_i_0__n.BLIF N_69_0.BLIF a_8__n.BLIF SM_AMIGA_0_.BLIF VPA_D_i.BLIF \
+N_329_i.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF cpu_est_i_1__n.BLIF \
+N_176_i.BLIF a_7__n.BLIF inst_DSACK1_INTreg.BLIF CLK_030_i.BLIF N_175_0.BLIF \
+pos_clk_ipl_n.BLIF CLK_000_D1_i.BLIF N_174_0.BLIF a_6__n.BLIF SM_AMIGA_4_.BLIF \
+cpu_est_i_2__n.BLIF N_171_0.BLIF inst_DS_000_ENABLE.BLIF DTACK_D0_i.BLIF \
+un1_SM_AMIGA_5_i.BLIF a_5__n.BLIF RST_DLY_0_.BLIF RW_i.BLIF N_324_i.BLIF \
+RST_DLY_1_.BLIF a_i_31__n.BLIF N_326_i.BLIF a_4__n.BLIF RST_DLY_2_.BLIF \
+a_i_29__n.BLIF N_168_i.BLIF pos_clk_un8_bg_030_n.BLIF a_i_30__n.BLIF \
+VMA_INT_i.BLIF a_3__n.BLIF CLK_000_P_SYNC_0_.BLIF a_i_27__n.BLIF N_165_i.BLIF \
+CLK_000_P_SYNC_1_.BLIF a_i_28__n.BLIF N_164_i.BLIF a_2__n.BLIF \
+CLK_000_P_SYNC_2_.BLIF a_i_25__n.BLIF N_162_i.BLIF CLK_000_P_SYNC_3_.BLIF \
+a_i_26__n.BLIF clk_000_n_sync_i_10__n.BLIF CLK_000_P_SYNC_4_.BLIF N_213_i.BLIF \
+N_321_i.BLIF CLK_000_P_SYNC_5_.BLIF N_214_i.BLIF N_159_0.BLIF \
+CLK_000_P_SYNC_6_.BLIF N_215_i.BLIF N_318_i.BLIF CLK_000_P_SYNC_7_.BLIF \
+N_156_i.BLIF CLK_000_P_SYNC_8_.BLIF DS_000_ENABLE_1_sqmuxa_i.BLIF N_155_i.BLIF \
+CLK_000_N_SYNC_0_.BLIF N_98_i.BLIF N_154_i.BLIF CLK_000_N_SYNC_1_.BLIF \
+un6_ds_030_i.BLIF CLK_OUT_PRE_D_i.BLIF CLK_000_N_SYNC_2_.BLIF \
+un4_as_000_i.BLIF N_152_0.BLIF CLK_000_N_SYNC_3_.BLIF un4_lds_000_i.BLIF \
+N_150_i.BLIF CLK_000_N_SYNC_4_.BLIF un4_uds_000_i.BLIF AS_030_000_SYNC_i.BLIF \
+CLK_000_N_SYNC_5_.BLIF LDS_000_INT_i.BLIF N_147_i.BLIF CLK_000_N_SYNC_6_.BLIF \
+UDS_000_INT_i.BLIF N_145_i.BLIF CLK_000_N_SYNC_7_.BLIF AS_030_c.BLIF \
+N_281_i.BLIF CLK_000_N_SYNC_8_.BLIF N_302_i.BLIF CLK_000_N_SYNC_9_.BLIF \
+AS_000_c.BLIF CLK_000_N_SYNC_10_.BLIF N_279_i.BLIF inst_RW_000_INT.BLIF \
+RW_000_c.BLIF N_280_i.BLIF inst_RW_000_DMA.BLIF un5_e_0.BLIF \
+pos_clk_un7_clk_000_pe_n.BLIF N_278_i.BLIF inst_A0_DMA.BLIF UDS_000_c.BLIF \
+cpu_est_2_0_3__n.BLIF SM_AMIGA_6_.BLIF N_277_i.BLIF \
+DS_000_ENABLE_1_sqmuxa.BLIF LDS_000_c.BLIF N_348_i.BLIF inst_CLK_030_H.BLIF \
+cpu_est_2_0_2__n.BLIF SM_AMIGA_1_.BLIF size_c_0__n.BLIF N_128_i.BLIF \
+SM_AMIGA_3_.BLIF N_193_i.BLIF SM_AMIGA_2_.BLIF size_c_1__n.BLIF N_241_i.BLIF \
+pos_clk_un3_as_030_d0_n.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF N_240_i.BLIF \
+N_4.BLIF N_124_0.BLIF N_6.BLIF N_269_0.BLIF un5_ciin_i.BLIF N_61_0.BLIF \
+un1_as_030_i.BLIF N_17.BLIF N_228_i.BLIF N_18.BLIF N_355_0.BLIF N_21.BLIF \
+N_226_i.BLIF N_22.BLIF N_26.BLIF N_224_i.BLIF N_27.BLIF N_225_i.BLIF \
+CLK_OUT_PRE_25_0.BLIF N_282_0.BLIF N_221_i.BLIF N_222_i.BLIF N_219_i.BLIF \
+N_220_i.BLIF N_283_0.BLIF N_216_i.BLIF N_218_i.BLIF cpu_est_2_0_1__n.BLIF \
+N_373_i.BLIF N_375_i.BLIF pos_clk_un7_clk_000_pe_0_n.BLIF N_188_i.BLIF \
+a_c_16__n.BLIF N_205_i.BLIF a_c_17__n.BLIF pos_clk_un8_sm_amiga_i_n.BLIF \
+A0_c_i.BLIF a_c_18__n.BLIF size_c_i_1__n.BLIF N_27_i.BLIF a_c_19__n.BLIF \
+N_31_0.BLIF ipl_c_i_0__n.BLIF a_c_20__n.BLIF N_52_0.BLIF N_4_i.BLIF \
+a_c_21__n.BLIF N_49_0.BLIF N_17_i.BLIF SM_AMIGA_i_7_.BLIF a_c_22__n.BLIF \
+N_43_0.BLIF N_124.BLIF N_18_i.BLIF cpu_est_2_1__n.BLIF a_c_23__n.BLIF \
+N_42_0.BLIF cpu_est_2_2__n.BLIF N_21_i.BLIF cpu_est_2_3__n.BLIF a_c_24__n.BLIF \
+N_39_0.BLIF G_134.BLIF N_22_i.BLIF G_135.BLIF a_c_25__n.BLIF N_38_0.BLIF \
+G_136.BLIF N_26_i.BLIF N_269.BLIF a_c_26__n.BLIF N_34_0.BLIF N_61.BLIF \
+BG_030_c_i.BLIF a_c_27__n.BLIF pos_clk_un8_bg_030_0_n.BLIF N_98.BLIF \
+N_161_i_1.BLIF a_c_28__n.BLIF N_161_i_2.BLIF pos_clk_un8_sm_amiga_i_1_n.BLIF \
+N_355.BLIF a_c_29__n.BLIF N_324_1.BLIF N_324_2.BLIF N_128.BLIF a_c_30__n.BLIF \
+N_150_i_1.BLIF N_137.BLIF un1_SM_AMIGA_5_i_1.BLIF N_145.BLIF a_c_31__n.BLIF \
+un1_SM_AMIGA_5_i_2.BLIF N_148.BLIF N_138_i_1.BLIF N_150.BLIF A0_c.BLIF \
+N_138_i_2.BLIF N_152.BLIF N_146_i_1.BLIF N_154.BLIF A1_c.BLIF N_146_i_2.BLIF \
+N_156.BLIF N_146_i_3.BLIF N_159.BLIF nEXP_SPACE_c.BLIF N_220_1.BLIF N_161.BLIF \
+N_220_2.BLIF N_165.BLIF BERR_c.BLIF N_375_1.BLIF N_168.BLIF N_375_2.BLIF \
+N_171.BLIF BG_030_c.BLIF N_373_1.BLIF N_174.BLIF N_373_2.BLIF N_175.BLIF \
+BG_000DFFreg.BLIF N_210_1.BLIF N_178.BLIF N_210_2.BLIF N_181.BLIF N_210_3.BLIF \
+N_183.BLIF BGACK_000_c.BLIF un5_ciin_1.BLIF N_188.BLIF un5_ciin_2.BLIF \
+N_190.BLIF CLK_030_c.BLIF un5_ciin_3.BLIF N_193.BLIF un5_ciin_4.BLIF \
+N_195.BLIF un5_ciin_5.BLIF N_200.BLIF un5_ciin_6.BLIF N_205.BLIF \
+CLK_OSZI_c.BLIF un5_ciin_7.BLIF N_206.BLIF un5_ciin_8.BLIF N_207.BLIF \
+un5_ciin_9.BLIF N_208.BLIF un5_ciin_10.BLIF N_210.BLIF un5_ciin_11.BLIF \
+N_211.BLIF FPU_SENSE_c.BLIF N_302_1.BLIF N_212.BLIF N_244_i_1.BLIF N_373.BLIF \
+IPL_030DFF_0_reg.BLIF N_244_i_2.BLIF N_375.BLIF N_243_i_1.BLIF N_216.BLIF \
+IPL_030DFF_1_reg.BLIF N_410_1.BLIF N_218.BLIF N_410_2.BLIF N_219.BLIF \
+IPL_030DFF_2_reg.BLIF N_410_3.BLIF N_220.BLIF N_410_4.BLIF N_221.BLIF \
+ipl_c_0__n.BLIF N_237_1.BLIF N_222.BLIF N_237_2.BLIF N_224.BLIF \
+ipl_c_1__n.BLIF un21_fpu_cs_1.BLIF N_225.BLIF un22_berr_1_0.BLIF N_226.BLIF \
+ipl_c_2__n.BLIF N_233_1.BLIF N_228.BLIF N_233_2.BLIF N_230.BLIF N_245_i_1.BLIF \
+N_231.BLIF DTACK_c.BLIF N_128_i_1.BLIF N_240.BLIF N_134_i_1.BLIF N_241.BLIF \
+N_124_0_1.BLIF N_277.BLIF N_267_i_1.BLIF N_278.BLIF VPA_c.BLIF N_268_i_1.BLIF \
+N_279.BLIF N_355_0_1.BLIF N_280.BLIF N_353_i_1.BLIF N_281.BLIF RST_c.BLIF \
+N_140_i_1.BLIF N_302.BLIF N_142_i_1.BLIF N_313.BLIF N_280_1.BLIF N_318.BLIF \
+RW_c.BLIF N_225_1.BLIF N_321.BLIF N_224_1.BLIF N_324.BLIF fc_c_0__n.BLIF \
+N_219_1.BLIF N_326.BLIF N_218_1.BLIF N_329.BLIF fc_c_1__n.BLIF N_212_1.BLIF \
+N_332.BLIF N_208_1.BLIF N_348.BLIF N_207_1.BLIF cpu_est_0_0_x2_0_x2_0_.BLIF \
+AMIGA_BUS_DATA_DIR_c.BLIF N_200_1.BLIF pos_clk_CYCLE_DMA_5_0_i_0_x2.BLIF \
+N_195_1.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF pos_clk_ipl_1_n.BLIF N_235.BLIF \
+ipl_030_0_1__un3_n.BLIF N_196.BLIF ipl_030_0_1__un1_n.BLIF N_143.BLIF \
+N_7_i.BLIF ipl_030_0_1__un0_n.BLIF N_158.BLIF N_47_0.BLIF \
+as_030_000_sync_0_un3_n.BLIF N_198.BLIF N_5_i.BLIF \
+as_030_000_sync_0_un1_n.BLIF N_199.BLIF N_48_0.BLIF \
+as_030_000_sync_0_un0_n.BLIF N_307.BLIF N_3_i.BLIF as_000_int_0_un3_n.BLIF \
+N_201.BLIF N_50_0.BLIF as_000_int_0_un1_n.BLIF N_182.BLIF nEXP_SPACE_c_i.BLIF \
+as_000_int_0_un0_n.BLIF N_243_2.BLIF N_55_0.BLIF ds_000_dma_0_un3_n.BLIF \
+N_8.BLIF VPA_c_i.BLIF ds_000_dma_0_un1_n.BLIF N_356.BLIF N_56_0.BLIF \
+ds_000_dma_0_un0_n.BLIF N_10.BLIF DTACK_c_i.BLIF ipl_030_0_2__un3_n.BLIF \
+pos_clk_un6_bgack_000_n.BLIF N_57_0.BLIF ipl_030_0_2__un1_n.BLIF N_19.BLIF \
+ipl_c_i_1__n.BLIF ipl_030_0_2__un0_n.BLIF N_352.BLIF N_53_0.BLIF \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n.BLIF N_327.BLIF \
+ipl_c_i_2__n.BLIF un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n.BLIF \
+N_20.BLIF N_54_0.BLIF un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n.BLIF \
+pos_clk_a0_dma_3_n.BLIF N_28_i.BLIF sm_amiga_srsts_i_0_0_m3_1__un3_n.BLIF \
+N_24.BLIF N_32_0.BLIF sm_amiga_srsts_i_0_0_m3_1__un1_n.BLIF N_113.BLIF \
+N_29_i.BLIF sm_amiga_srsts_i_0_0_m3_1__un0_n.BLIF N_25.BLIF N_33_0.BLIF \
+sm_amiga_srsts_i_0_0_m3_5__un3_n.BLIF N_114.BLIF N_378_i.BLIF \
+sm_amiga_srsts_i_0_0_m3_5__un1_n.BLIF pos_clk_size_dma_6_0__n.BLIF \
+sm_amiga_srsts_i_0_0_m3_5__un0_n.BLIF N_232.BLIF size_dma_0_0__un3_n.BLIF \
+pos_clk_size_dma_6_1__n.BLIF N_227_i.BLIF size_dma_0_0__un1_n.BLIF N_410.BLIF \
+N_354_0.BLIF size_dma_0_0__un0_n.BLIF N_185.BLIF N_233_i.BLIF \
+size_dma_0_1__un3_n.BLIF N_236.BLIF N_357_0.BLIF size_dma_0_1__un1_n.BLIF \
+N_238.BLIF N_270_0.BLIF size_dma_0_1__un0_n.BLIF N_173.BLIF AS_000_DMA_i.BLIF \
+as_000_dma_0_un3_n.BLIF N_239.BLIF N_137_0.BLIF as_000_dma_0_un1_n.BLIF \
+N_331.BLIF N_312_i.BLIF as_000_dma_0_un0_n.BLIF N_237.BLIF \
+pos_clk_un3_as_030_d0_i_n.BLIF bgack_030_int_0_un3_n.BLIF un22_berr_1.BLIF \
+N_161_i.BLIF bgack_030_int_0_un1_n.BLIF N_233.BLIF N_179_0.BLIF \
+bgack_030_int_0_un0_n.BLIF N_209.BLIF N_180_0.BLIF rw_000_dma_0_un3_n.BLIF \
+AS_030.PIN.BLIF AS_000.PIN.BLIF RW_000.PIN.BLIF UDS_000.PIN.BLIF \
+LDS_000.PIN.BLIF SIZE_0_.PIN.BLIF SIZE_1_.PIN.BLIF A0.PIN.BLIF BERR.PIN.BLIF \
+RW.PIN.BLIF
+.outputs IPL_030_2_ DS_030 BG_000 BGACK_030 CLK_DIV_OUT CLK_EXP FPU_CS DSACK1 \
+AVEC E VMA RESET AMIGA_ADDR_ENABLE AMIGA_BUS_DATA_DIR AMIGA_BUS_ENABLE_LOW \
+AMIGA_BUS_ENABLE_HIGH CIIN IPL_030_1_ IPL_030_0_ SM_AMIGA_i_7_.D \
+SM_AMIGA_i_7_.C SM_AMIGA_6_.D SM_AMIGA_6_.C SM_AMIGA_5_.D SM_AMIGA_5_.C \
+SM_AMIGA_4_.D SM_AMIGA_4_.C SM_AMIGA_3_.D SM_AMIGA_3_.C SM_AMIGA_2_.D \
+SM_AMIGA_2_.C SM_AMIGA_1_.D SM_AMIGA_1_.C SM_AMIGA_0_.D SM_AMIGA_0_.C \
+cpu_est_2_.D cpu_est_2_.C cpu_est_3_.D cpu_est_3_.C IPL_030DFF_0_reg.D \
+IPL_030DFF_0_reg.C IPL_030DFF_1_reg.D IPL_030DFF_1_reg.C IPL_030DFF_2_reg.D \
+IPL_030DFF_2_reg.C IPL_D0_0_.D IPL_D0_0_.C IPL_D0_1_.D IPL_D0_1_.C IPL_D0_2_.D \
+IPL_D0_2_.C CLK_000_N_SYNC_5_.D CLK_000_N_SYNC_5_.C CLK_000_N_SYNC_6_.D \
+CLK_000_N_SYNC_6_.C CLK_000_N_SYNC_7_.D CLK_000_N_SYNC_7_.C \
+CLK_000_N_SYNC_8_.D CLK_000_N_SYNC_8_.C CLK_000_N_SYNC_9_.D \
+CLK_000_N_SYNC_9_.C CLK_000_N_SYNC_10_.D CLK_000_N_SYNC_10_.C \
+CLK_000_N_SYNC_11_.D CLK_000_N_SYNC_11_.C CYCLE_DMA_0_.D CYCLE_DMA_0_.C \
+CYCLE_DMA_1_.D CYCLE_DMA_1_.C SIZE_DMA_0_.D SIZE_DMA_0_.C SIZE_DMA_1_.D \
+SIZE_DMA_1_.C cpu_est_0_.D cpu_est_0_.C cpu_est_1_.D cpu_est_1_.C \
+CLK_000_P_SYNC_1_.D CLK_000_P_SYNC_1_.C CLK_000_P_SYNC_2_.D \
+CLK_000_P_SYNC_2_.C CLK_000_P_SYNC_3_.D CLK_000_P_SYNC_3_.C \
+CLK_000_P_SYNC_4_.D CLK_000_P_SYNC_4_.C CLK_000_P_SYNC_5_.D \
+CLK_000_P_SYNC_5_.C CLK_000_P_SYNC_6_.D CLK_000_P_SYNC_6_.C \
+CLK_000_P_SYNC_7_.D CLK_000_P_SYNC_7_.C CLK_000_P_SYNC_8_.D \
+CLK_000_P_SYNC_8_.C CLK_000_P_SYNC_9_.D CLK_000_P_SYNC_9_.C \
+CLK_000_N_SYNC_0_.D CLK_000_N_SYNC_0_.C CLK_000_N_SYNC_1_.D \
+CLK_000_N_SYNC_1_.C CLK_000_N_SYNC_2_.D CLK_000_N_SYNC_2_.C \
+CLK_000_N_SYNC_3_.D CLK_000_N_SYNC_3_.C CLK_000_N_SYNC_4_.D \
+CLK_000_N_SYNC_4_.C RST_DLY_0_.D RST_DLY_0_.C RST_DLY_1_.D RST_DLY_1_.C \
+RST_DLY_2_.D RST_DLY_2_.C CLK_000_P_SYNC_0_.D CLK_000_P_SYNC_0_.C \
+inst_DS_000_ENABLE.D inst_DS_000_ENABLE.C inst_RW_000_DMA.D inst_RW_000_DMA.C \
+inst_RW_000_INT.D inst_RW_000_INT.C inst_LDS_000_INT.D inst_LDS_000_INT.C \
+inst_BGACK_030_INTreg.D inst_BGACK_030_INTreg.C inst_AS_000_DMA.D \
+inst_AS_000_DMA.C inst_AS_030_000_SYNC.D inst_AS_030_000_SYNC.C \
+inst_AS_000_INT.D inst_AS_000_INT.C inst_DSACK1_INTreg.D inst_DSACK1_INTreg.C \
+inst_DS_000_DMA.D inst_DS_000_DMA.C inst_AS_030_D0.D inst_AS_030_D0.C \
+inst_nEXP_SPACE_D0reg.D inst_nEXP_SPACE_D0reg.C inst_VPA_D.D inst_VPA_D.C \
+inst_DTACK_D0.D inst_DTACK_D0.C inst_CLK_030_H.D inst_CLK_030_H.C \
+inst_RESET_OUT.D inst_RESET_OUT.C inst_CLK_OUT_PRE_25.D inst_CLK_OUT_PRE_25.C \
+BG_000DFFreg.D BG_000DFFreg.C inst_AMIGA_BUS_ENABLE_DMA_HIGH.D \
+inst_AMIGA_BUS_ENABLE_DMA_HIGH.C inst_AMIGA_BUS_ENABLE_DMA_LOW.D \
+inst_AMIGA_BUS_ENABLE_DMA_LOW.C inst_VMA_INTreg.D inst_VMA_INTreg.C \
+inst_UDS_000_INT.D inst_UDS_000_INT.C inst_A0_DMA.D inst_A0_DMA.C \
+inst_BGACK_030_INT_D.D inst_BGACK_030_INT_D.C inst_CLK_000_NE.D \
+inst_CLK_000_NE.C inst_CLK_OUT_PRE_50.D inst_CLK_OUT_PRE_50.C \
+inst_CLK_OUT_INTreg.D inst_CLK_OUT_INTreg.C inst_CLK_000_D1.D \
+inst_CLK_000_D1.C inst_CLK_000_NE_D0.D inst_CLK_000_NE_D0.C \
+inst_CLK_OUT_EXP_INT.D inst_CLK_OUT_EXP_INT.C inst_CLK_OUT_PRE_D.D \
+inst_CLK_OUT_PRE_D.C inst_CLK_000_D0.D inst_CLK_000_D0.C inst_CLK_000_PE.D \
+inst_CLK_000_PE.C SIZE_1_ AS_030 AS_000 RW_000 UDS_000 LDS_000 A0 BERR RW \
+SIZE_0_ N_184 N_184_0 rw_000_dma_0_un1_n N_180 N_185_0 rw_000_dma_0_un0_n \
+N_179 UDS_000_c_i a0_dma_0_un3_n LDS_000_c_i a0_dma_0_un1_n N_312 N_173_i \
+a0_dma_0_un0_n N_270 N_358_0 amiga_bus_enable_dma_low_0_un3_n N_357 N_239_i \
+amiga_bus_enable_dma_low_0_un1_n N_354 pos_clk_size_dma_6_0_1__n \
+amiga_bus_enable_dma_low_0_un0_n vcc_n_n N_227 N_238_i \
+amiga_bus_enable_dma_high_0_un3_n un5_e N_378 pos_clk_size_dma_6_0_0__n \
+amiga_bus_enable_dma_high_0_un1_n N_29 N_237_i \
+amiga_bus_enable_dma_high_0_un0_n gnd_n_n N_28 N_236_i cpu_est_0_2__un3_n \
+un1_amiga_bus_enable_low N_3 AMIGA_BUS_DATA_DIR_c_0 cpu_est_0_2__un1_n \
+un3_size N_5 N_331_i cpu_est_0_2__un0_n un4_size N_7 pos_clk_un6_bgack_000_0_n \
+cpu_est_0_3__un3_n un4_uds_000 N_190_i N_356_0 cpu_est_0_3__un1_n un4_lds_000 \
+un1_amiga_bus_enable_low_i N_352_0 cpu_est_0_3__un0_n un5_ciin un21_fpu_cs_i \
+N_8_i ipl_030_0_0__un3_n un4_as_000 CLK_OUT_EXP_INT_i N_46_0 \
+ipl_030_0_0__un1_n un1_SM_AMIGA_5 AS_000_i N_10_i ipl_030_0_0__un0_n \
+un21_fpu_cs DS_000_DMA_i N_44_0 rw_000_int_0_un3_n un22_berr sm_amiga_i_5__n \
+N_19_i rw_000_int_0_un1_n un6_ds_030 sm_amiga_i_6__n N_41_0 rw_000_int_0_un0_n \
+sm_amiga_i_0__n N_20_i uds_000_int_0_un3_n CLK_000_NE_i N_40_0 \
+uds_000_int_0_un1_n sm_amiga_i_4__n N_24_i uds_000_int_0_un0_n RW_000_i N_36_0 \
+vma_int_0_un3_n sm_amiga_i_2__n N_25_i vma_int_0_un1_n CLK_000_D0_i N_35_0 \
+vma_int_0_un0_n BERR_i bg_000_0_un3_n sm_amiga_i_1__n N_198_i bg_000_0_un1_n \
+CLK_000_PE_i N_243_2_i bg_000_0_un0_n N_410_i_0 N_196_i cpu_est_0_1__un3_n \
+sm_amiga_i_i_7__n N_195_i cpu_est_0_1__un1_n AS_030_i cpu_est_0_1__un0_n \
+FPU_SENSE_i N_201_i dsack1_int_0_un3_n nEXP_SPACE_D0_i N_200_i \
+dsack1_int_0_un1_n BGACK_030_INT_i N_199_i dsack1_int_0_un0_n \
+AMIGA_BUS_ENABLE_DMA_HIGH_i N_182_0 ds_000_enable_0_un3_n A1_i N_158_i \
+ds_000_enable_0_un1_n CLK_030_H_i N_148_i ds_000_enable_0_un0_n a_i_16__n \
+N_307_i lds_000_int_0_un3_n a_i_18__n N_143_0 lds_000_int_0_un1_n a_i_19__n \
+N_217_i lds_000_int_0_un0_n N_114_i N_235_i a_15__n N_113_i AS_000_INT_i \
+N_210_i a_14__n AMIGA_BUS_ENABLE_DMA_LOW_i rst_dly_i_2__n N_207_i a_13__n \
+rst_dly_i_0__n N_208_i rst_dly_i_1__n N_206_i a_12__n RESET_OUT_i \
+size_dma_i_1__n N_313_i a_11__n size_dma_i_0__n N_211_i AS_030_D0_i N_212_i \
+a_10__n a_i_24__n N_183_0 sm_amiga_i_3__n N_181_0 a_9__n cpu_est_i_3__n \
+N_178_0 cpu_est_i_0__n N_69_0 a_8__n VPA_D_i N_329_i cpu_est_i_1__n N_176_i \
+a_7__n CLK_030_i N_175_0 pos_clk_ipl_n CLK_000_D1_i N_174_0 a_6__n \
+cpu_est_i_2__n N_171_0 DTACK_D0_i un1_SM_AMIGA_5_i a_5__n RW_i N_324_i \
+a_i_31__n N_326_i a_4__n a_i_29__n N_168_i pos_clk_un8_bg_030_n a_i_30__n \
+VMA_INT_i a_3__n a_i_27__n N_165_i a_i_28__n N_164_i a_2__n a_i_25__n N_162_i \
+a_i_26__n clk_000_n_sync_i_10__n N_213_i N_321_i N_214_i N_159_0 N_215_i \
+N_318_i N_156_i DS_000_ENABLE_1_sqmuxa_i N_155_i N_98_i N_154_i un6_ds_030_i \
+CLK_OUT_PRE_D_i un4_as_000_i N_152_0 un4_lds_000_i N_150_i un4_uds_000_i \
+AS_030_000_SYNC_i LDS_000_INT_i N_147_i UDS_000_INT_i N_145_i AS_030_c N_281_i \
+N_302_i AS_000_c N_279_i RW_000_c N_280_i un5_e_0 pos_clk_un7_clk_000_pe_n \
+N_278_i UDS_000_c cpu_est_2_0_3__n N_277_i DS_000_ENABLE_1_sqmuxa LDS_000_c \
+N_348_i cpu_est_2_0_2__n size_c_0__n N_128_i N_193_i size_c_1__n N_241_i \
+pos_clk_un3_as_030_d0_n DS_000_ENABLE_1_sqmuxa_1 N_240_i N_4 N_124_0 N_6 \
+N_269_0 un5_ciin_i N_61_0 un1_as_030_i N_17 N_228_i N_18 N_355_0 N_21 N_226_i \
+N_22 N_26 N_224_i N_27 N_225_i N_282_0 N_221_i N_222_i N_219_i N_220_i N_283_0 \
+N_216_i N_218_i cpu_est_2_0_1__n N_373_i N_375_i pos_clk_un7_clk_000_pe_0_n \
+N_188_i a_c_16__n N_205_i a_c_17__n pos_clk_un8_sm_amiga_i_n A0_c_i a_c_18__n \
+size_c_i_1__n N_27_i a_c_19__n N_31_0 ipl_c_i_0__n a_c_20__n N_52_0 N_4_i \
+a_c_21__n N_49_0 N_17_i a_c_22__n N_43_0 N_124 N_18_i cpu_est_2_1__n a_c_23__n \
+N_42_0 cpu_est_2_2__n N_21_i cpu_est_2_3__n a_c_24__n N_39_0 N_22_i a_c_25__n \
+N_38_0 N_26_i N_269 a_c_26__n N_34_0 N_61 BG_030_c_i a_c_27__n \
+pos_clk_un8_bg_030_0_n N_98 N_161_i_1 a_c_28__n N_161_i_2 \
+pos_clk_un8_sm_amiga_i_1_n N_355 a_c_29__n N_324_1 N_324_2 N_128 a_c_30__n \
+N_150_i_1 N_137 un1_SM_AMIGA_5_i_1 N_145 a_c_31__n un1_SM_AMIGA_5_i_2 N_148 \
+N_138_i_1 N_150 A0_c N_138_i_2 N_152 N_146_i_1 N_154 A1_c N_146_i_2 N_156 \
+N_146_i_3 N_159 nEXP_SPACE_c N_220_1 N_161 N_220_2 N_165 BERR_c N_375_1 N_168 \
+N_375_2 N_171 BG_030_c N_373_1 N_174 N_373_2 N_175 N_210_1 N_178 N_210_2 N_181 \
+N_210_3 N_183 BGACK_000_c un5_ciin_1 N_188 un5_ciin_2 N_190 CLK_030_c \
+un5_ciin_3 N_193 un5_ciin_4 N_195 un5_ciin_5 N_200 un5_ciin_6 N_205 CLK_OSZI_c \
+un5_ciin_7 N_206 un5_ciin_8 N_207 un5_ciin_9 N_208 un5_ciin_10 N_210 \
+un5_ciin_11 N_211 FPU_SENSE_c N_302_1 N_212 N_244_i_1 N_373 N_244_i_2 N_375 \
+N_243_i_1 N_216 N_410_1 N_218 N_410_2 N_219 N_410_3 N_220 N_410_4 N_221 \
+ipl_c_0__n N_237_1 N_222 N_237_2 N_224 ipl_c_1__n un21_fpu_cs_1 N_225 \
+un22_berr_1_0 N_226 ipl_c_2__n N_233_1 N_228 N_233_2 N_230 N_245_i_1 N_231 \
+DTACK_c N_128_i_1 N_240 N_134_i_1 N_241 N_124_0_1 N_277 N_267_i_1 N_278 VPA_c \
+N_268_i_1 N_279 N_355_0_1 N_280 N_353_i_1 N_281 RST_c N_140_i_1 N_302 \
+N_142_i_1 N_313 N_280_1 N_318 RW_c N_225_1 N_321 N_224_1 N_324 fc_c_0__n \
+N_219_1 N_326 N_218_1 N_329 fc_c_1__n N_212_1 N_332 N_208_1 N_348 N_207_1 \
+AMIGA_BUS_DATA_DIR_c N_200_1 N_195_1 pos_clk_ipl_1_n N_235 ipl_030_0_1__un3_n \
+N_196 ipl_030_0_1__un1_n N_143 N_7_i ipl_030_0_1__un0_n N_158 N_47_0 \
+as_030_000_sync_0_un3_n N_198 N_5_i as_030_000_sync_0_un1_n N_199 N_48_0 \
+as_030_000_sync_0_un0_n N_307 N_3_i as_000_int_0_un3_n N_201 N_50_0 \
+as_000_int_0_un1_n N_182 nEXP_SPACE_c_i as_000_int_0_un0_n N_243_2 N_55_0 \
+ds_000_dma_0_un3_n N_8 VPA_c_i ds_000_dma_0_un1_n N_356 N_56_0 \
+ds_000_dma_0_un0_n N_10 DTACK_c_i ipl_030_0_2__un3_n pos_clk_un6_bgack_000_n \
+N_57_0 ipl_030_0_2__un1_n N_19 ipl_c_i_1__n ipl_030_0_2__un0_n N_352 N_53_0 \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n N_327 ipl_c_i_2__n \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n N_20 N_54_0 \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n pos_clk_a0_dma_3_n N_28_i \
+sm_amiga_srsts_i_0_0_m3_1__un3_n N_24 N_32_0 sm_amiga_srsts_i_0_0_m3_1__un1_n \
+N_113 N_29_i sm_amiga_srsts_i_0_0_m3_1__un0_n N_25 N_33_0 \
+sm_amiga_srsts_i_0_0_m3_5__un3_n N_114 N_378_i \
+sm_amiga_srsts_i_0_0_m3_5__un1_n pos_clk_size_dma_6_0__n \
+sm_amiga_srsts_i_0_0_m3_5__un0_n N_232 size_dma_0_0__un3_n \
+pos_clk_size_dma_6_1__n N_227_i size_dma_0_0__un1_n N_410 N_354_0 \
+size_dma_0_0__un0_n N_185 N_233_i size_dma_0_1__un3_n N_236 N_357_0 \
+size_dma_0_1__un1_n N_238 N_270_0 size_dma_0_1__un0_n N_173 AS_000_DMA_i \
+as_000_dma_0_un3_n N_239 N_137_0 as_000_dma_0_un1_n N_331 N_312_i \
+as_000_dma_0_un0_n N_237 pos_clk_un3_as_030_d0_i_n bgack_030_int_0_un3_n \
+un22_berr_1 N_161_i bgack_030_int_0_un1_n N_233 N_179_0 bgack_030_int_0_un0_n \
+N_209 N_180_0 rw_000_dma_0_un3_n AS_030.OE AS_000.OE RW_000.OE UDS_000.OE \
+LDS_000.OE SIZE_0_.OE SIZE_1_.OE A0.OE BERR.OE RW.OE DS_030.OE DSACK1.OE \
+RESET.OE CIIN.OE pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2 CLK_OUT_PRE_25_0 \
+G_134 G_135 G_136 cpu_est_0_0_x2_0_x2_0_ pos_clk_CYCLE_DMA_5_0_i_0_x2 \
+pos_clk_CYCLE_DMA_5_1_i_0_x2
+.names N_146_i_3.BLIF N_210_i.BLIF SM_AMIGA_i_7_.D
+11 1
+.names N_282_0.BLIF SM_AMIGA_6_.D
+0 1
+.names N_142_i_1.BLIF RST_c.BLIF SM_AMIGA_5_.D
+11 1
+.names N_140_i_1.BLIF RST_c.BLIF SM_AMIGA_4_.D
+11 1
+.names N_138_i_1.BLIF N_138_i_2.BLIF SM_AMIGA_3_.D
+11 1
+.names N_283_0.BLIF SM_AMIGA_2_.D
+0 1
+.names N_134_i_1.BLIF RST_c.BLIF SM_AMIGA_1_.D
+11 1
+.names N_176_i.BLIF N_378_i.BLIF SM_AMIGA_0_.D
+11 1
+.names cpu_est_0_2__un1_n.BLIF cpu_est_0_2__un0_n.BLIF cpu_est_2_.D
+1- 1
+-1 1
+.names cpu_est_0_3__un1_n.BLIF cpu_est_0_3__un0_n.BLIF cpu_est_3_.D
+1- 1
+-1 1
+.names N_31_0.BLIF IPL_030DFF_0_reg.D
+0 1
+.names N_32_0.BLIF IPL_030DFF_1_reg.D
+0 1
+.names N_33_0.BLIF IPL_030DFF_2_reg.D
+0 1
+.names N_52_0.BLIF IPL_D0_0_.D
+0 1
+.names N_53_0.BLIF IPL_D0_1_.D
+0 1
+.names N_54_0.BLIF IPL_D0_2_.D
+0 1
+.names N_268_i_1.BLIF N_69_0.BLIF CYCLE_DMA_0_.D
+11 1
+.names N_267_i_1.BLIF N_69_0.BLIF CYCLE_DMA_1_.D
+11 1
+.names size_dma_0_0__un1_n.BLIF size_dma_0_0__un0_n.BLIF SIZE_DMA_0_.D
+1- 1
+-1 1
+.names size_dma_0_1__un1_n.BLIF size_dma_0_1__un0_n.BLIF SIZE_DMA_1_.D
+1- 1
+-1 1
+.names cpu_est_0_1__un1_n.BLIF cpu_est_0_1__un0_n.BLIF cpu_est_1_.D
+1- 1
+-1 1
+.names N_245_i_1.BLIF RST_c.BLIF RST_DLY_0_.D
+11 1
+.names N_244_i_1.BLIF N_244_i_2.BLIF RST_DLY_1_.D
+11 1
+.names N_243_i_1.BLIF N_196_i.BLIF RST_DLY_2_.D
+11 1
+.names inst_CLK_000_D0.BLIF CLK_000_D1_i.BLIF CLK_000_P_SYNC_0_.D
+11 1
+.names N_6.BLIF RST_c.BLIF inst_DS_000_ENABLE.D
+11 1
+.names N_41_0.BLIF inst_RW_000_DMA.D
+0 1
+.names N_42_0.BLIF inst_RW_000_INT.D
+0 1
+.names N_43_0.BLIF inst_LDS_000_INT.D
+0 1
+.names N_44_0.BLIF inst_BGACK_030_INTreg.D
+0 1
+.names N_46_0.BLIF inst_AS_000_DMA.D
+0 1
+.names N_47_0.BLIF inst_AS_030_000_SYNC.D
+0 1
+.names N_48_0.BLIF inst_AS_000_INT.D
+0 1
+.names N_49_0.BLIF inst_DSACK1_INTreg.D
+0 1
+.names N_50_0.BLIF inst_DS_000_DMA.D
+0 1
+.names N_358_0.BLIF inst_AS_030_D0.D
+0 1
+.names N_55_0.BLIF inst_nEXP_SPACE_D0reg.D
+0 1
+.names N_56_0.BLIF inst_VPA_D.D
+0 1
+.names N_57_0.BLIF inst_DTACK_D0.D
+0 1
+.names N_353_i_1.BLIF RST_c.BLIF inst_CLK_030_H.D
+11 1
+.names N_235_i.BLIF RST_c.BLIF inst_RESET_OUT.D
+11 1
+.names N_34_0.BLIF BG_000DFFreg.D
+0 1
+.names N_35_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.D
+0 1
+.names N_36_0.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.D
+0 1
+.names N_38_0.BLIF inst_VMA_INTreg.D
+0 1
+.names N_39_0.BLIF inst_UDS_000_INT.D
+0 1
+.names N_40_0.BLIF inst_A0_DMA.D
+0 1
+.names N_69_0.BLIF inst_BGACK_030_INT_D.D
+0 1
+.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_50.D
+0 1
+.names N_184_0.BLIF N_184
+0 1
+.names inst_CLK_000_NE.BLIF SM_AMIGA_1_.BLIF N_184_0
+11 1
+.names inst_RW_000_DMA.BLIF N_327.BLIF rw_000_dma_0_un1_n
+11 1
+.names N_180_0.BLIF N_180
+0 1
+.names AS_000_DMA_i.BLIF CLK_030_i.BLIF N_185_0
+11 1
+.names N_352.BLIF rw_000_dma_0_un3_n.BLIF rw_000_dma_0_un0_n
+11 1
+.names N_179_0.BLIF N_179
+0 1
+.names UDS_000_c.BLIF UDS_000_c_i
+0 1
+.names N_327.BLIF a0_dma_0_un3_n
+0 1
+.names LDS_000_c.BLIF LDS_000_c_i
+0 1
+.names inst_A0_DMA.BLIF N_327.BLIF a0_dma_0_un1_n
+11 1
+.names LDS_000_c.BLIF UDS_000_c.BLIF N_312
+11 1
+.names LDS_000_c_i.BLIF UDS_000_c_i.BLIF N_173_i
+11 1
+.names pos_clk_a0_dma_3_n.BLIF a0_dma_0_un3_n.BLIF a0_dma_0_un0_n
+11 1
+.names N_270_0.BLIF N_270
+0 1
+.names AS_030_i.BLIF RST_c.BLIF N_358_0
+11 1
+.names N_327.BLIF amiga_bus_enable_dma_low_0_un3_n
+0 1
+.names N_357_0.BLIF N_357
+0 1
+.names N_239.BLIF N_239_i
+0 1
+.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF N_327.BLIF \
+amiga_bus_enable_dma_low_0_un1_n
+11 1
+.names N_354_0.BLIF N_354
+0 1
+.names N_239_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_1__n
+11 1
+.names N_113_i.BLIF amiga_bus_enable_dma_low_0_un3_n.BLIF \
+amiga_bus_enable_dma_low_0_un0_n
+11 1
+.names vcc_n_n
+ 1
+.names inst_AS_000_DMA.BLIF RW_000_i.BLIF N_227
+11 1
+.names N_238.BLIF N_238_i
+0 1
+.names N_327.BLIF amiga_bus_enable_dma_high_0_un3_n
+0 1
+.names un5_e_0.BLIF un5_e
+0 1
+.names N_184.BLIF sm_amiga_i_0__n.BLIF N_378
+11 1
+.names N_238_i.BLIF RST_c.BLIF pos_clk_size_dma_6_0_0__n
+11 1
+.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF N_327.BLIF \
+amiga_bus_enable_dma_high_0_un1_n
+11 1
+.names ipl_030_0_2__un1_n.BLIF ipl_030_0_2__un0_n.BLIF N_29
+1- 1
+-1 1
+.names N_237.BLIF N_237_i
+0 1
+.names N_114_i.BLIF amiga_bus_enable_dma_high_0_un3_n.BLIF \
+amiga_bus_enable_dma_high_0_un0_n
+11 1
+.names gnd_n_n
+.names ipl_030_0_1__un1_n.BLIF ipl_030_0_1__un0_n.BLIF N_28
+1- 1
+-1 1
+.names N_236.BLIF N_236_i
+0 1
+.names inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un3_n
+0 1
+.names AMIGA_BUS_ENABLE_DMA_LOW_i.BLIF BGACK_030_INT_i.BLIF \
+un1_amiga_bus_enable_low
+11 1
+.names ds_000_dma_0_un1_n.BLIF ds_000_dma_0_un0_n.BLIF N_3
+1- 1
+-1 1
+.names N_236_i.BLIF N_237_i.BLIF AMIGA_BUS_DATA_DIR_c_0
+11 1
+.names cpu_est_2_2__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_2__un1_n
+11 1
+.names SIZE_DMA_1_.BLIF size_dma_i_0__n.BLIF un3_size
+11 1
+.names as_000_int_0_un1_n.BLIF as_000_int_0_un0_n.BLIF N_5
+1- 1
+-1 1
+.names N_331.BLIF N_331_i
+0 1
+.names cpu_est_2_.BLIF cpu_est_0_2__un3_n.BLIF cpu_est_0_2__un0_n
+11 1
+.names SIZE_DMA_0_.BLIF size_dma_i_1__n.BLIF un4_size
+11 1
+.names as_030_000_sync_0_un1_n.BLIF as_030_000_sync_0_un0_n.BLIF N_7
+1- 1
+-1 1
+.names BGACK_000_c.BLIF N_331_i.BLIF pos_clk_un6_bgack_000_0_n
+11 1
+.names inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un3_n
+0 1
+.names inst_DS_000_ENABLE.BLIF UDS_000_INT_i.BLIF un4_uds_000
+11 1
+.names N_190.BLIF N_190_i
+0 1
+.names CLK_030_i.BLIF N_161_i.BLIF N_356_0
+11 1
+.names cpu_est_2_3__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_3__un1_n
+11 1
+.names inst_DS_000_ENABLE.BLIF LDS_000_INT_i.BLIF un4_lds_000
+11 1
+.names un1_amiga_bus_enable_low.BLIF un1_amiga_bus_enable_low_i
+0 1
+.names BGACK_030_INT_i.BLIF RW_000_i.BLIF N_352_0
+11 1
+.names cpu_est_3_.BLIF cpu_est_0_3__un3_n.BLIF cpu_est_0_3__un0_n
+11 1
+.names un5_ciin_10.BLIF un5_ciin_11.BLIF un5_ciin
+11 1
+.names un21_fpu_cs.BLIF un21_fpu_cs_i
+0 1
+.names N_8.BLIF N_8_i
+0 1
+.names pos_clk_ipl_n.BLIF ipl_030_0_0__un3_n
+0 1
+.names AS_000_INT_i.BLIF AS_030_i.BLIF un4_as_000
+11 1
+.names inst_CLK_OUT_EXP_INT.BLIF CLK_OUT_EXP_INT_i
+0 1
+.names N_8_i.BLIF RST_c.BLIF N_46_0
+11 1
+.names ipl_c_0__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_0__un1_n
+11 1
+.names un1_SM_AMIGA_5_i.BLIF un1_SM_AMIGA_5
+0 1
+.names AS_000_c.BLIF AS_000_i
+0 1
+.names N_10.BLIF N_10_i
+0 1
+.names IPL_030DFF_0_reg.BLIF ipl_030_0_0__un3_n.BLIF ipl_030_0_0__un0_n
+11 1
+.names un21_fpu_cs_1.BLIF un22_berr_1.BLIF un21_fpu_cs
+11 1
+.names inst_DS_000_DMA.BLIF DS_000_DMA_i
+0 1
+.names N_10_i.BLIF RST_c.BLIF N_44_0
+11 1
+.names N_124.BLIF rw_000_int_0_un3_n
+0 1
+.names un22_berr_1_0.BLIF FPU_SENSE_c.BLIF un22_berr
+11 1
+.names SM_AMIGA_5_.BLIF sm_amiga_i_5__n
+0 1
+.names N_19.BLIF N_19_i
+0 1
+.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_124.BLIF rw_000_int_0_un1_n
+11 1
+.names AS_000_i.BLIF DS_000_DMA_i.BLIF un6_ds_030
+11 1
+.names SM_AMIGA_6_.BLIF sm_amiga_i_6__n
+0 1
+.names N_19_i.BLIF RST_c.BLIF N_41_0
+11 1
+.names inst_RW_000_INT.BLIF rw_000_int_0_un3_n.BLIF rw_000_int_0_un0_n
+11 1
+.names SM_AMIGA_0_.BLIF sm_amiga_i_0__n
+0 1
+.names N_20.BLIF N_20_i
+0 1
+.names SM_AMIGA_6_.BLIF uds_000_int_0_un3_n
+0 1
+.names inst_CLK_000_NE.BLIF CLK_000_NE_i
+0 1
+.names N_20_i.BLIF RST_c.BLIF N_40_0
+11 1
+.names A0_c.BLIF SM_AMIGA_6_.BLIF uds_000_int_0_un1_n
+11 1
+.names SM_AMIGA_4_.BLIF sm_amiga_i_4__n
+0 1
+.names N_24.BLIF N_24_i
+0 1
+.names inst_UDS_000_INT.BLIF uds_000_int_0_un3_n.BLIF uds_000_int_0_un0_n
+11 1
+.names RW_000_c.BLIF RW_000_i
+0 1
+.names N_24_i.BLIF RST_c.BLIF N_36_0
+11 1
+.names pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un3_n
+0 1
+.names SM_AMIGA_2_.BLIF sm_amiga_i_2__n
+0 1
+.names N_25.BLIF N_25_i
+0 1
+.names cpu_est_i_1__n.BLIF pos_clk_un7_clk_000_pe_n.BLIF vma_int_0_un1_n
+11 1
+.names inst_CLK_000_D0.BLIF CLK_000_D0_i
+0 1
+.names N_25_i.BLIF RST_c.BLIF N_35_0
+11 1
+.names inst_VMA_INTreg.BLIF vma_int_0_un3_n.BLIF vma_int_0_un0_n
+11 1
+.names BERR_c.BLIF BERR_i
+0 1
+.names pos_clk_un8_bg_030_n.BLIF bg_000_0_un3_n
+0 1
+.names SM_AMIGA_1_.BLIF sm_amiga_i_1__n
+0 1
+.names N_198.BLIF N_198_i
+0 1
+.names BG_030_c.BLIF pos_clk_un8_bg_030_n.BLIF bg_000_0_un1_n
+11 1
+.names inst_CLK_000_PE.BLIF CLK_000_PE_i
+0 1
+.names N_198_i.BLIF RST_c.BLIF N_243_2_i
+11 1
+.names BG_000DFFreg.BLIF bg_000_0_un3_n.BLIF bg_000_0_un0_n
+11 1
+.names N_410.BLIF N_410_i_0
+0 1
+.names N_196.BLIF N_196_i
+0 1
+.names inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un3_n
+0 1
+.names SM_AMIGA_i_7_.BLIF sm_amiga_i_i_7__n
+0 1
+.names N_195.BLIF N_195_i
+0 1
+.names cpu_est_2_1__n.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_1__un1_n
+11 1
+.names AS_030_c.BLIF AS_030_i
+0 1
+.names cpu_est_1_.BLIF cpu_est_0_1__un3_n.BLIF cpu_est_0_1__un0_n
+11 1
+.names FPU_SENSE_c.BLIF FPU_SENSE_i
+0 1
+.names N_201.BLIF N_201_i
+0 1
+.names N_269.BLIF dsack1_int_0_un3_n
+0 1
+.names inst_nEXP_SPACE_D0reg.BLIF nEXP_SPACE_D0_i
+0 1
+.names N_200.BLIF N_200_i
+0 1
+.names N_98_i.BLIF N_269.BLIF dsack1_int_0_un1_n
+11 1
+.names inst_BGACK_030_INTreg.BLIF BGACK_030_INT_i
+0 1
+.names N_199.BLIF N_199_i
+0 1
+.names inst_DSACK1_INTreg.BLIF dsack1_int_0_un3_n.BLIF dsack1_int_0_un0_n
+11 1
+.names inst_AMIGA_BUS_ENABLE_DMA_HIGH.BLIF AMIGA_BUS_ENABLE_DMA_HIGH_i
+0 1
+.names inst_CLK_000_NE.BLIF N_158_i.BLIF N_182_0
+11 1
+.names DS_000_ENABLE_1_sqmuxa_1.BLIF ds_000_enable_0_un3_n
+0 1
+.names A1_c.BLIF A1_i
+0 1
+.names N_148_i.BLIF RST_DLY_2_.BLIF N_158_i
+11 1
+.names inst_DS_000_ENABLE.BLIF DS_000_ENABLE_1_sqmuxa_1.BLIF \
+ds_000_enable_0_un1_n
+11 1
+.names inst_CLK_030_H.BLIF CLK_030_H_i
+0 1
+.names RST_DLY_0_.BLIF RST_DLY_1_.BLIF N_148_i
+11 1
+.names un1_SM_AMIGA_5_i.BLIF ds_000_enable_0_un3_n.BLIF ds_000_enable_0_un0_n
+11 1
+.names a_c_16__n.BLIF a_i_16__n
+0 1
+.names N_307.BLIF N_307_i
+0 1
+.names SM_AMIGA_6_.BLIF lds_000_int_0_un3_n
+0 1
+.names a_c_18__n.BLIF a_i_18__n
+0 1
+.names N_307_i.BLIF RST_c.BLIF N_143_0
+11 1
+.names pos_clk_un8_sm_amiga_i_n.BLIF SM_AMIGA_6_.BLIF lds_000_int_0_un1_n
+11 1
+.names a_c_19__n.BLIF a_i_19__n
+0 1
+.names N_158.BLIF RST_c.BLIF N_217_i
+11 1
+.names inst_LDS_000_INT.BLIF lds_000_int_0_un3_n.BLIF lds_000_int_0_un0_n
+11 1
+.names N_114.BLIF N_114_i
+0 1
+.names N_235.BLIF N_235_i
+0 1
+.names N_113.BLIF N_113_i
+0 1
+.names inst_AS_000_INT.BLIF AS_000_INT_i
+0 1
+.names N_210.BLIF N_210_i
+0 1
+.names inst_AMIGA_BUS_ENABLE_DMA_LOW.BLIF AMIGA_BUS_ENABLE_DMA_LOW_i
+0 1
+.names RST_DLY_2_.BLIF rst_dly_i_2__n
+0 1
+.names N_207.BLIF N_207_i
+0 1
+.names RST_DLY_0_.BLIF rst_dly_i_0__n
+0 1
+.names N_208.BLIF N_208_i
+0 1
+.names RST_DLY_1_.BLIF rst_dly_i_1__n
+0 1
+.names N_206.BLIF N_206_i
+0 1
+.names inst_RESET_OUT.BLIF RESET_OUT_i
+0 1
+.names SIZE_DMA_1_.BLIF size_dma_i_1__n
+0 1
+.names N_313.BLIF N_313_i
+0 1
+.names SIZE_DMA_0_.BLIF size_dma_i_0__n
+0 1
+.names N_211.BLIF N_211_i
+0 1
+.names inst_AS_030_D0.BLIF AS_030_D0_i
+0 1
+.names N_212.BLIF N_212_i
+0 1
+.names a_c_24__n.BLIF a_i_24__n
+0 1
+.names inst_CLK_000_PE.BLIF SM_AMIGA_4_.BLIF N_183_0
+11 1
+.names SM_AMIGA_3_.BLIF sm_amiga_i_3__n
+0 1
+.names inst_CLK_000_NE_D0.BLIF N_168.BLIF N_181_0
+11 1
+.names cpu_est_3_.BLIF cpu_est_i_3__n
+0 1
+.names N_145_i.BLIF SM_AMIGA_4_.BLIF N_178_0
+11 1
+.names cpu_est_0_.BLIF cpu_est_i_0__n
+0 1
+.names BGACK_030_INT_i.BLIF RST_c.BLIF N_69_0
+11 1
+.names inst_VPA_D.BLIF VPA_D_i
+0 1
+.names N_329.BLIF N_329_i
+0 1
+.names cpu_est_1_.BLIF cpu_est_i_1__n
+0 1
+.names N_329_i.BLIF RST_c.BLIF N_176_i
+11 1
+.names CLK_030_c.BLIF CLK_030_i
+0 1
+.names N_145.BLIF sm_amiga_i_3__n.BLIF N_175_0
+11 1
+.names pos_clk_ipl_1_n.BLIF N_214_i.BLIF pos_clk_ipl_n
+11 1
+.names inst_CLK_000_D1.BLIF CLK_000_D1_i
+0 1
+.names N_145.BLIF SM_AMIGA_i_7_.BLIF N_174_0
+11 1
+.names cpu_est_2_.BLIF cpu_est_i_2__n
+0 1
+.names N_164_i.BLIF sm_amiga_i_6__n.BLIF N_171_0
+11 1
+.names inst_DTACK_D0.BLIF DTACK_D0_i
+0 1
+.names un1_SM_AMIGA_5_i_1.BLIF un1_SM_AMIGA_5_i_2.BLIF un1_SM_AMIGA_5_i
+11 1
+.names RW_c.BLIF RW_i
+0 1
+.names N_324.BLIF N_324_i
+0 1
+.names a_c_31__n.BLIF a_i_31__n
+0 1
+.names N_326.BLIF N_326_i
+0 1
+.names a_c_29__n.BLIF a_i_29__n
+0 1
+.names N_324_i.BLIF N_326_i.BLIF N_168_i
+11 1
+.names pos_clk_un8_bg_030_0_n.BLIF pos_clk_un8_bg_030_n
+0 1
+.names a_c_30__n.BLIF a_i_30__n
+0 1
+.names inst_VMA_INTreg.BLIF VMA_INT_i
+0 1
+.names a_c_27__n.BLIF a_i_27__n
+0 1
+.names sm_amiga_i_1__n.BLIF sm_amiga_i_5__n.BLIF N_165_i
+11 1
+.names a_c_28__n.BLIF a_i_28__n
+0 1
+.names sm_amiga_i_2__n.BLIF sm_amiga_i_4__n.BLIF N_164_i
+11 1
+.names a_c_25__n.BLIF a_i_25__n
+0 1
+.names sm_amiga_i_0__n.BLIF sm_amiga_i_6__n.BLIF N_162_i
+11 1
+.names a_c_26__n.BLIF a_i_26__n
+0 1
+.names CLK_000_N_SYNC_10_.BLIF clk_000_n_sync_i_10__n
+0 1
+.names G_134.BLIF N_213_i
+0 1
+.names N_321.BLIF N_321_i
+0 1
+.names G_135.BLIF N_214_i
+0 1
+.names clk_000_n_sync_i_10__n.BLIF N_321_i.BLIF N_159_0
+11 1
+.names G_136.BLIF N_215_i
+0 1
+.names N_318.BLIF N_318_i
+0 1
+.names cpu_est_0_.BLIF cpu_est_1_.BLIF N_156_i
+11 1
+.names DS_000_ENABLE_1_sqmuxa.BLIF DS_000_ENABLE_1_sqmuxa_i
+0 1
+.names cpu_est_i_1__n.BLIF cpu_est_i_2__n.BLIF N_155_i
+11 1
+.names N_98.BLIF N_98_i
+0 1
+.names cpu_est_3_.BLIF cpu_est_i_0__n.BLIF N_154_i
+11 1
+.names un6_ds_030.BLIF un6_ds_030_i
+0 1
+.names inst_CLK_OUT_PRE_D.BLIF CLK_OUT_PRE_D_i
+0 1
+.names un4_as_000.BLIF un4_as_000_i
+0 1
+.names CLK_030_c.BLIF CLK_OUT_PRE_D_i.BLIF N_152_0
+11 1
+.names un4_lds_000.BLIF un4_lds_000_i
+0 1
+.names N_150_i_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_150_i
+11 1
+.names un4_uds_000.BLIF un4_uds_000_i
+0 1
+.names inst_AS_030_000_SYNC.BLIF AS_030_000_SYNC_i
+0 1
+.names inst_LDS_000_INT.BLIF LDS_000_INT_i
+0 1
+.names CLK_000_D0_i.BLIF inst_CLK_000_D1.BLIF N_147_i
+11 1
+.names inst_UDS_000_INT.BLIF UDS_000_INT_i
+0 1
+.names BERR_c.BLIF CLK_000_PE_i.BLIF N_145_i
+11 1
+.names N_281.BLIF N_281_i
+0 1
+.names N_302.BLIF N_302_i
+0 1
+.names N_279.BLIF N_279_i
+0 1
+.names N_280.BLIF N_280_i
+0 1
+.names N_279_i.BLIF N_280_i.BLIF un5_e_0
+11 1
+.names pos_clk_un7_clk_000_pe_0_n.BLIF pos_clk_un7_clk_000_pe_n
+0 1
+.names N_278.BLIF N_278_i
+0 1
+.names N_154.BLIF N_278_i.BLIF cpu_est_2_0_3__n
+11 1
+.names N_277.BLIF N_277_i
+0 1
+.names RW_i.BLIF SM_AMIGA_5_.BLIF DS_000_ENABLE_1_sqmuxa
+11 1
+.names N_348.BLIF N_348_i
+0 1
+.names N_277_i.BLIF N_348_i.BLIF cpu_est_2_0_2__n
+11 1
+.names N_128_i_1.BLIF inst_nEXP_SPACE_D0reg.BLIF N_128_i
+11 1
+.names N_193.BLIF N_193_i
+0 1
+.names N_241.BLIF N_241_i
+0 1
+.names pos_clk_un3_as_030_d0_i_n.BLIF pos_clk_un3_as_030_d0_n
+0 1
+.names pos_clk_un3_as_030_d0_i_n.BLIF un1_SM_AMIGA_5.BLIF \
+DS_000_ENABLE_1_sqmuxa_1
+11 1
+.names N_240.BLIF N_240_i
+0 1
+.names dsack1_int_0_un1_n.BLIF dsack1_int_0_un0_n.BLIF N_4
+1- 1
+-1 1
+.names N_124_0_1.BLIF SM_AMIGA_i_7_.BLIF N_124_0
+11 1
+.names ds_000_enable_0_un1_n.BLIF ds_000_enable_0_un0_n.BLIF N_6
+1- 1
+-1 1
+.names N_98_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_269_0
+11 1
+.names un5_ciin.BLIF un5_ciin_i
+0 1
+.names nEXP_SPACE_D0_i.BLIF un5_ciin_i.BLIF N_61_0
+11 1
+.names BGACK_030_INT_i.BLIF nEXP_SPACE_D0_i.BLIF un1_as_030_i
+11 1
+.names lds_000_int_0_un1_n.BLIF lds_000_int_0_un0_n.BLIF N_17
+1- 1
+-1 1
+.names N_228.BLIF N_228_i
+0 1
+.names rw_000_int_0_un1_n.BLIF rw_000_int_0_un0_n.BLIF N_18
+1- 1
+-1 1
+.names N_355_0_1.BLIF RW_000_i.BLIF N_355_0
+11 1
+.names uds_000_int_0_un1_n.BLIF uds_000_int_0_un0_n.BLIF N_21
+1- 1
+-1 1
+.names N_226.BLIF N_226_i
+0 1
+.names vma_int_0_un1_n.BLIF vma_int_0_un0_n.BLIF N_22
+1- 1
+-1 1
+.names bg_000_0_un1_n.BLIF bg_000_0_un0_n.BLIF N_26
+1- 1
+-1 1
+.names N_224.BLIF N_224_i
+0 1
+.names ipl_030_0_0__un1_n.BLIF ipl_030_0_0__un0_n.BLIF N_27
+1- 1
+-1 1
+.names N_225.BLIF N_225_i
+0 1
+.names N_224_i.BLIF N_225_i.BLIF N_282_0
+11 1
+.names N_221.BLIF N_221_i
+0 1
+.names N_222.BLIF N_222_i
+0 1
+.names N_219.BLIF N_219_i
+0 1
+.names N_220.BLIF N_220_i
+0 1
+.names N_219_i.BLIF N_220_i.BLIF N_283_0
+11 1
+.names N_216.BLIF N_216_i
+0 1
+.names N_218.BLIF N_218_i
+0 1
+.names N_216_i.BLIF N_218_i.BLIF cpu_est_2_0_1__n
+11 1
+.names N_373.BLIF N_373_i
+0 1
+.names N_375.BLIF N_375_i
+0 1
+.names N_373_i.BLIF N_375_i.BLIF pos_clk_un7_clk_000_pe_0_n
+11 1
+.names N_188.BLIF N_188_i
+0 1
+.names N_205.BLIF N_205_i
+0 1
+.names pos_clk_un8_sm_amiga_i_1_n.BLIF size_c_0__n.BLIF \
+pos_clk_un8_sm_amiga_i_n
+11 1
+.names A0_c.BLIF A0_c_i
+0 1
+.names size_c_1__n.BLIF size_c_i_1__n
+0 1
+.names N_27.BLIF N_27_i
+0 1
+.names N_27_i.BLIF RST_c.BLIF N_31_0
+11 1
+.names ipl_c_0__n.BLIF ipl_c_i_0__n
+0 1
+.names ipl_c_i_0__n.BLIF RST_c.BLIF N_52_0
+11 1
+.names N_4.BLIF N_4_i
+0 1
+.names N_4_i.BLIF RST_c.BLIF N_49_0
+11 1
+.names N_17.BLIF N_17_i
+0 1
+.names N_17_i.BLIF RST_c.BLIF N_43_0
+11 1
+.names N_124_0.BLIF N_124
+0 1
+.names N_18.BLIF N_18_i
+0 1
+.names cpu_est_2_0_1__n.BLIF cpu_est_2_1__n
+0 1
+.names N_18_i.BLIF RST_c.BLIF N_42_0
+11 1
+.names cpu_est_2_0_2__n.BLIF cpu_est_2_2__n
+0 1
+.names N_21.BLIF N_21_i
+0 1
+.names cpu_est_2_0_3__n.BLIF cpu_est_2_3__n
+0 1
+.names N_21_i.BLIF RST_c.BLIF N_39_0
+11 1
+.names N_22.BLIF N_22_i
+0 1
+.names N_22_i.BLIF RST_c.BLIF N_38_0
+11 1
+.names N_26.BLIF N_26_i
+0 1
+.names N_269_0.BLIF N_269
+0 1
+.names N_26_i.BLIF RST_c.BLIF N_34_0
+11 1
+.names N_61_0.BLIF N_61
+0 1
+.names BG_030_c.BLIF BG_030_c_i
+0 1
+.names BG_030_c_i.BLIF N_128.BLIF pos_clk_un8_bg_030_0_n
+11 1
+.names N_159.BLIF SM_AMIGA_1_.BLIF N_98
+11 1
+.names AS_000_i.BLIF pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2.BLIF N_161_i_1
+11 1
+.names BGACK_030_INT_i.BLIF N_312_i.BLIF N_161_i_2
+11 1
+.names size_c_i_1__n.BLIF A0_c_i.BLIF pos_clk_un8_sm_amiga_i_1_n
+11 1
+.names N_355_0.BLIF N_355
+0 1
+.names N_154_i.BLIF N_155_i.BLIF N_324_1
+11 1
+.names VMA_INT_i.BLIF VPA_D_i.BLIF N_324_2
+11 1
+.names N_128_i.BLIF N_128
+0 1
+.names AS_030_000_SYNC_i.BLIF N_147_i.BLIF N_150_i_1
+11 1
+.names N_137_0.BLIF N_137
+0 1
+.names DS_000_ENABLE_1_sqmuxa_i.BLIF N_162_i.BLIF un1_SM_AMIGA_5_i_1
+11 1
+.names N_145_i.BLIF N_145
+0 1
+.names N_318_i.BLIF SM_AMIGA_i_7_.BLIF un1_SM_AMIGA_5_i_2
+11 1
+.names N_148_i.BLIF N_148
+0 1
+.names N_211_i.BLIF N_212_i.BLIF N_138_i_1
+11 1
+.names N_150_i.BLIF N_150
+0 1
+.names N_313_i.BLIF RST_c.BLIF N_138_i_2
+11 1
+.names N_152_0.BLIF N_152
+0 1
+.names N_176_i.BLIF N_206_i.BLIF N_146_i_1
+11 1
+.names N_154_i.BLIF N_154
+0 1
+.names N_207_i.BLIF N_208_i.BLIF N_146_i_2
+11 1
+.names N_156_i.BLIF N_156
+0 1
+.names N_146_i_1.BLIF N_146_i_2.BLIF N_146_i_3
+11 1
+.names N_159_0.BLIF N_159
+0 1
+.names inst_CLK_000_NE_D0.BLIF N_168.BLIF N_220_1
+11 1
+.names N_161_i.BLIF N_161
+0 1
+.names RST_c.BLIF SM_AMIGA_3_.BLIF N_220_2
+11 1
+.names N_165_i.BLIF N_165
+0 1
+.names inst_CLK_000_NE.BLIF N_348.BLIF N_375_1
+11 1
+.names N_168_i.BLIF N_168
+0 1
+.names VPA_D_i.BLIF cpu_est_i_3__n.BLIF N_375_2
+11 1
+.names N_171_0.BLIF N_171
+0 1
+.names inst_CLK_000_PE.BLIF N_155_i.BLIF N_373_1
+11 1
+.names N_174_0.BLIF N_174
+0 1
+.names cpu_est_i_0__n.BLIF cpu_est_i_3__n.BLIF N_373_2
+11 1
+.names N_175_0.BLIF N_175
+0 1
+.names N_150.BLIF N_162_i.BLIF N_210_1
+11 1
+.names N_178_0.BLIF N_178
+0 1
+.names N_164_i.BLIF N_165_i.BLIF N_210_2
+11 1
+.names N_181_0.BLIF N_181
+0 1
+.names N_210_1.BLIF N_210_2.BLIF N_210_3
+11 1
+.names N_183_0.BLIF N_183
+0 1
+.names AS_030_D0_i.BLIF a_c_20__n.BLIF un5_ciin_1
+11 1
+.names sm_amiga_srsts_i_0_0_m3_5__un1_n.BLIF \
+sm_amiga_srsts_i_0_0_m3_5__un0_n.BLIF N_188
+1- 1
+-1 1
+.names a_c_21__n.BLIF a_c_22__n.BLIF un5_ciin_2
+11 1
+.names un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n.BLIF \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n.BLIF N_190
+1- 1
+-1 1
+.names a_c_23__n.BLIF a_i_24__n.BLIF un5_ciin_3
+11 1
+.names sm_amiga_srsts_i_0_0_m3_1__un1_n.BLIF \
+sm_amiga_srsts_i_0_0_m3_1__un0_n.BLIF N_193
+1- 1
+-1 1
+.names a_i_25__n.BLIF a_i_26__n.BLIF un5_ciin_4
+11 1
+.names N_195_1.BLIF rst_dly_i_2__n.BLIF N_195
+11 1
+.names a_i_31__n.BLIF a_i_27__n.BLIF un5_ciin_5
+11 1
+.names N_200_1.BLIF rst_dly_i_1__n.BLIF N_200
+11 1
+.names a_i_28__n.BLIF a_i_29__n.BLIF un5_ciin_6
+11 1
+.names N_180.BLIF sm_amiga_i_6__n.BLIF N_205
+11 1
+.names un5_ciin_1.BLIF un5_ciin_2.BLIF un5_ciin_7
+11 1
+.names N_181.BLIF N_313.BLIF N_206
+11 1
+.names un5_ciin_3.BLIF un5_ciin_4.BLIF un5_ciin_8
+11 1
+.names N_207_1.BLIF CLK_000_PE_i.BLIF N_207
+11 1
+.names un5_ciin_5.BLIF un5_ciin_6.BLIF un5_ciin_9
+11 1
+.names N_208_1.BLIF CLK_000_NE_i.BLIF N_208
+11 1
+.names un5_ciin_7.BLIF un5_ciin_8.BLIF un5_ciin_10
+11 1
+.names N_210_3.BLIF sm_amiga_i_3__n.BLIF N_210
+11 1
+.names un5_ciin_9.BLIF a_i_30__n.BLIF un5_ciin_11
+11 1
+.names N_183.BLIF sm_amiga_i_3__n.BLIF N_211
+11 1
+.names CLK_000_NE_i.BLIF rst_dly_i_0__n.BLIF N_302_1
+11 1
+.names N_212_1.BLIF sm_amiga_i_4__n.BLIF N_212
+11 1
+.names N_199_i.BLIF N_200_i.BLIF N_244_i_1
+11 1
+.names N_373_1.BLIF N_373_2.BLIF N_373
+11 1
+.names N_201_i.BLIF RST_c.BLIF N_244_i_2
+11 1
+.names N_375_1.BLIF N_375_2.BLIF N_375
+11 1
+.names N_243_2_i.BLIF N_195_i.BLIF N_243_i_1
+11 1
+.names cpu_est_1_.BLIF cpu_est_i_0__n.BLIF N_216
+11 1
+.names fc_c_0__n.BLIF fc_c_1__n.BLIF N_410_1
+11 1
+.names N_218_1.BLIF cpu_est_i_3__n.BLIF N_218
+11 1
+.names a_c_17__n.BLIF a_i_16__n.BLIF N_410_2
+11 1
+.names N_219_1.BLIF SM_AMIGA_2_.BLIF N_219
+11 1
+.names a_i_18__n.BLIF a_i_19__n.BLIF N_410_3
+11 1
+.names N_220_1.BLIF N_220_2.BLIF N_220
+11 1
+.names N_410_1.BLIF N_410_2.BLIF N_410_4
+11 1
+.names N_178.BLIF sm_amiga_i_5__n.BLIF N_221
+11 1
+.names AS_000_i.BLIF BGACK_030_INT_i.BLIF N_237_1
+11 1
+.names CLK_000_NE_i.BLIF sm_amiga_i_4__n.BLIF N_222
+11 1
+.names RW_000_c.BLIF nEXP_SPACE_D0_i.BLIF N_237_2
+11 1
+.names N_224_1.BLIF SM_AMIGA_6_.BLIF N_224
+11 1
+.names AS_030_i.BLIF FPU_SENSE_i.BLIF un21_fpu_cs_1
+11 1
+.names N_225_1.BLIF sm_amiga_i_i_7__n.BLIF N_225
+11 1
+.names un22_berr_1.BLIF AS_030_i.BLIF un22_berr_1_0
+11 1
+.names CLK_030_H_i.BLIF N_185.BLIF N_226
+11 1
+.names N_327.BLIF N_410_i_0.BLIF N_233_1
+11 1
+.names inst_CLK_030_H.BLIF CLK_030_c.BLIF N_228
+11 1
+.names sm_amiga_i_i_7__n.BLIF inst_nEXP_SPACE_D0reg.BLIF N_233_2
+11 1
+.names inst_BGACK_030_INTreg.BLIF inst_RESET_OUT.BLIF N_230
+11 1
+.names N_281_i.BLIF N_302_i.BLIF N_245_i_1
+11 1
+.names N_332.BLIF nEXP_SPACE_D0_i.BLIF N_231
+11 1
+.names inst_AS_030_D0.BLIF inst_CLK_000_D0.BLIF N_128_i_1
+11 1
+.names inst_CLK_000_PE.BLIF SM_AMIGA_0_.BLIF N_240
+11 1
+.names N_193_i.BLIF N_241_i.BLIF N_134_i_1
+11 1
+.names N_179.BLIF sm_amiga_i_2__n.BLIF N_241
+11 1
+.names N_240_i.BLIF sm_amiga_i_5__n.BLIF N_124_0_1
+11 1
+.names N_156.BLIF cpu_est_2_.BLIF N_277
+11 1
+.names pos_clk_CYCLE_DMA_5_1_i_0_x2.BLIF AS_000_i.BLIF N_267_i_1
+11 1
+.names N_156_i.BLIF cpu_est_2_.BLIF N_278
+11 1
+.names pos_clk_CYCLE_DMA_5_0_i_0_x2.BLIF AS_000_i.BLIF N_268_i_1
+11 1
+.names N_155_i.BLIF cpu_est_3_.BLIF N_279
+11 1
+.names N_161_i.BLIF N_228_i.BLIF N_355_0_1
+11 1
+.names N_280_1.BLIF cpu_est_i_3__n.BLIF N_280
+11 1
+.names N_161_i.BLIF N_226_i.BLIF N_353_i_1
+11 1
+.names N_143.BLIF RST_DLY_0_.BLIF N_281
+11 1
+.names N_221_i.BLIF N_222_i.BLIF N_140_i_1
+11 1
+.names N_302_1.BLIF RST_c.BLIF N_302
+11 1
+.names N_188_i.BLIF N_205_i.BLIF N_142_i_1
+11 1
+.names BERR_i.BLIF SM_AMIGA_3_.BLIF N_313
+11 1
+.names cpu_est_1_.BLIF cpu_est_2_.BLIF N_280_1
+11 1
+.names CLK_000_PE_i.BLIF SM_AMIGA_4_.BLIF N_318
+11 1
+.names N_150_i.BLIF RST_c.BLIF N_225_1
+11 1
+.names CLK_000_N_SYNC_9_.BLIF N_152.BLIF N_321
+11 1
+.names N_174.BLIF RST_c.BLIF N_224_1
+11 1
+.names N_324_1.BLIF N_324_2.BLIF N_324
+11 1
+.names N_175.BLIF RST_c.BLIF N_219_1
+11 1
+.names DTACK_D0_i.BLIF inst_VPA_D.BLIF N_326
+11 1
+.names cpu_est_0_.BLIF cpu_est_i_1__n.BLIF N_218_1
+11 1
+.names N_145.BLIF SM_AMIGA_0_.BLIF N_329
+11 1
+.names inst_CLK_000_NE_D0.BLIF N_168.BLIF N_212_1
+11 1
+.names BGACK_030_INT_i.BLIF inst_RESET_OUT.BLIF N_332
+11 1
+.names N_165.BLIF BERR_i.BLIF N_208_1
+11 1
+.names N_156_i.BLIF cpu_est_i_2__n.BLIF N_348
+11 1
+.names N_171.BLIF BERR_i.BLIF N_207_1
+11 1
+.names AMIGA_BUS_DATA_DIR_c_0.BLIF AMIGA_BUS_DATA_DIR_c
+0 1
+.names N_217_i.BLIF rst_dly_i_0__n.BLIF N_200_1
+11 1
+.names N_148.BLIF N_217_i.BLIF N_195_1
+11 1
+.names N_215_i.BLIF N_213_i.BLIF pos_clk_ipl_1_n
+11 1
+.names N_182.BLIF RESET_OUT_i.BLIF N_235
+11 1
+.names pos_clk_ipl_n.BLIF ipl_030_0_1__un3_n
+0 1
+.names N_158_i.BLIF N_243_2.BLIF N_196
+11 1
+.names ipl_c_1__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_1__un1_n
+11 1
+.names N_143_0.BLIF N_143
+0 1
+.names N_7.BLIF N_7_i
+0 1
+.names IPL_030DFF_1_reg.BLIF ipl_030_0_1__un3_n.BLIF ipl_030_0_1__un0_n
+11 1
+.names N_158_i.BLIF N_158
+0 1
+.names N_7_i.BLIF RST_c.BLIF N_47_0
+11 1
+.names N_357.BLIF as_030_000_sync_0_un3_n
+0 1
+.names CLK_000_NE_i.BLIF rst_dly_i_2__n.BLIF N_198
+11 1
+.names N_5.BLIF N_5_i
+0 1
+.names pos_clk_un3_as_030_d0_n.BLIF N_357.BLIF as_030_000_sync_0_un1_n
+11 1
+.names N_148_i.BLIF N_307.BLIF N_199
+11 1
+.names N_5_i.BLIF RST_c.BLIF N_48_0
+11 1
+.names inst_AS_030_000_SYNC.BLIF as_030_000_sync_0_un3_n.BLIF \
+as_030_000_sync_0_un0_n
+11 1
+.names inst_CLK_000_NE.BLIF N_158.BLIF N_307
+11 1
+.names N_3.BLIF N_3_i
+0 1
+.names N_270.BLIF as_000_int_0_un3_n
+0 1
+.names CLK_000_NE_i.BLIF rst_dly_i_1__n.BLIF N_201
+11 1
+.names N_3_i.BLIF RST_c.BLIF N_50_0
+11 1
+.names sm_amiga_i_5__n.BLIF N_270.BLIF as_000_int_0_un1_n
+11 1
+.names N_182_0.BLIF N_182
+0 1
+.names nEXP_SPACE_c.BLIF nEXP_SPACE_c_i
+0 1
+.names inst_AS_000_INT.BLIF as_000_int_0_un3_n.BLIF as_000_int_0_un0_n
+11 1
+.names N_243_2_i.BLIF N_243_2
+0 1
+.names RST_c.BLIF nEXP_SPACE_c_i.BLIF N_55_0
+11 1
+.names N_355.BLIF ds_000_dma_0_un3_n
+0 1
+.names as_000_dma_0_un1_n.BLIF as_000_dma_0_un0_n.BLIF N_8
+1- 1
+-1 1
+.names VPA_c.BLIF VPA_c_i
+0 1
+.names N_354.BLIF N_355.BLIF ds_000_dma_0_un1_n
+11 1
+.names N_356_0.BLIF N_356
+0 1
+.names RST_c.BLIF VPA_c_i.BLIF N_56_0
+11 1
+.names inst_DS_000_DMA.BLIF ds_000_dma_0_un3_n.BLIF ds_000_dma_0_un0_n
+11 1
+.names bgack_030_int_0_un1_n.BLIF bgack_030_int_0_un0_n.BLIF N_10
+1- 1
+-1 1
+.names DTACK_c.BLIF DTACK_c_i
+0 1
+.names pos_clk_ipl_n.BLIF ipl_030_0_2__un3_n
+0 1
+.names pos_clk_un6_bgack_000_0_n.BLIF pos_clk_un6_bgack_000_n
+0 1
+.names DTACK_c_i.BLIF RST_c.BLIF N_57_0
+11 1
+.names ipl_c_2__n.BLIF pos_clk_ipl_n.BLIF ipl_030_0_2__un1_n
+11 1
+.names rw_000_dma_0_un1_n.BLIF rw_000_dma_0_un0_n.BLIF N_19
+1- 1
+-1 1
+.names ipl_c_1__n.BLIF ipl_c_i_1__n
+0 1
+.names IPL_030DFF_2_reg.BLIF ipl_030_0_2__un3_n.BLIF ipl_030_0_2__un0_n
+11 1
+.names N_352_0.BLIF N_352
+0 1
+.names ipl_c_i_1__n.BLIF RST_c.BLIF N_53_0
+11 1
+.names inst_BGACK_030_INTreg.BLIF \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n
+0 1
+.names inst_BGACK_030_INTreg.BLIF inst_BGACK_030_INT_D.BLIF N_327
+11 1
+.names ipl_c_2__n.BLIF ipl_c_i_2__n
+0 1
+.names SM_AMIGA_i_7_.BLIF inst_BGACK_030_INTreg.BLIF \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n
+11 1
+.names a0_dma_0_un1_n.BLIF a0_dma_0_un0_n.BLIF N_20
+1- 1
+-1 1
+.names ipl_c_i_2__n.BLIF RST_c.BLIF N_54_0
+11 1
+.names AMIGA_BUS_ENABLE_DMA_HIGH_i.BLIF \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n.BLIF \
+un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n
+11 1
+.names BGACK_030_INT_i.BLIF UDS_000_c.BLIF pos_clk_a0_dma_3_n
+11 1
+.names N_28.BLIF N_28_i
+0 1
+.names SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_0_m3_1__un3_n
+0 1
+.names amiga_bus_enable_dma_low_0_un1_n.BLIF \
+amiga_bus_enable_dma_low_0_un0_n.BLIF N_24
+1- 1
+-1 1
+.names N_28_i.BLIF RST_c.BLIF N_32_0
+11 1
+.names BERR_i.BLIF SM_AMIGA_1_.BLIF sm_amiga_srsts_i_0_0_m3_1__un1_n
+11 1
+.names A1_c.BLIF BGACK_030_INT_i.BLIF N_113
+11 1
+.names N_29.BLIF N_29_i
+0 1
+.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_0_m3_1__un3_n.BLIF \
+sm_amiga_srsts_i_0_0_m3_1__un0_n
+11 1
+.names amiga_bus_enable_dma_high_0_un1_n.BLIF \
+amiga_bus_enable_dma_high_0_un0_n.BLIF N_25
+1- 1
+-1 1
+.names N_29_i.BLIF RST_c.BLIF N_33_0
+11 1
+.names SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m3_5__un3_n
+0 1
+.names A1_i.BLIF BGACK_030_INT_i.BLIF N_114
+11 1
+.names N_378.BLIF N_378_i
+0 1
+.names BERR_i.BLIF SM_AMIGA_5_.BLIF sm_amiga_srsts_i_0_0_m3_5__un1_n
+11 1
+.names pos_clk_size_dma_6_0_0__n.BLIF pos_clk_size_dma_6_0__n
+0 1
+.names CLK_000_PE_i.BLIF sm_amiga_srsts_i_0_0_m3_5__un3_n.BLIF \
+sm_amiga_srsts_i_0_0_m3_5__un0_n
+11 1
+.names N_327.BLIF RST_c.BLIF N_232
+11 1
+.names N_232.BLIF size_dma_0_0__un3_n
+0 1
+.names pos_clk_size_dma_6_0_1__n.BLIF pos_clk_size_dma_6_1__n
+0 1
+.names N_227.BLIF N_227_i
+0 1
+.names SIZE_DMA_0_.BLIF N_232.BLIF size_dma_0_0__un1_n
+11 1
+.names N_410_4.BLIF N_410_3.BLIF N_410
+11 1
+.names N_161_i.BLIF N_227_i.BLIF N_354_0
+11 1
+.names pos_clk_size_dma_6_0__n.BLIF size_dma_0_0__un3_n.BLIF \
+size_dma_0_0__un0_n
+11 1
+.names N_185_0.BLIF N_185
+0 1
+.names N_233.BLIF N_233_i
+0 1
+.names N_232.BLIF size_dma_0_1__un3_n
+0 1
+.names inst_BGACK_030_INTreg.BLIF RW_000_i.BLIF N_236
+11 1
+.names N_233_i.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_357_0
+11 1
+.names SIZE_DMA_1_.BLIF N_232.BLIF size_dma_0_1__un1_n
+11 1
+.names BGACK_030_INT_i.BLIF N_173.BLIF N_238
+11 1
+.names sm_amiga_i_5__n.BLIF pos_clk_un3_as_030_d0_i_n.BLIF N_270_0
+11 1
+.names pos_clk_size_dma_6_1__n.BLIF size_dma_0_1__un3_n.BLIF \
+size_dma_0_1__un0_n
+11 1
+.names N_173_i.BLIF N_173
+0 1
+.names inst_AS_000_DMA.BLIF AS_000_DMA_i
+0 1
+.names N_356.BLIF as_000_dma_0_un3_n
+0 1
+.names BGACK_030_INT_i.BLIF N_173_i.BLIF N_239
+11 1
+.names AS_000_DMA_i.BLIF AS_000_i.BLIF N_137_0
+11 1
+.names N_161.BLIF N_356.BLIF as_000_dma_0_un1_n
+11 1
+.names AS_000_c.BLIF inst_CLK_000_PE.BLIF N_331
+11 1
+.names N_312.BLIF N_312_i
+0 1
+.names inst_AS_000_DMA.BLIF as_000_dma_0_un3_n.BLIF as_000_dma_0_un0_n
+11 1
+.names N_237_1.BLIF N_237_2.BLIF N_237
+11 1
+.names AS_030_D0_i.BLIF BERR_c.BLIF pos_clk_un3_as_030_d0_i_n
+11 1
+.names pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un3_n
+0 1
+.names BGACK_000_c.BLIF N_410.BLIF un22_berr_1
+11 1
+.names N_161_i_1.BLIF N_161_i_2.BLIF N_161_i
+11 1
+.names BGACK_000_c.BLIF pos_clk_un6_bgack_000_n.BLIF bgack_030_int_0_un1_n
+11 1
+.names N_233_1.BLIF N_233_2.BLIF N_233
+11 1
+.names CLK_000_NE_i.BLIF SM_AMIGA_1_.BLIF N_179_0
+11 1
+.names inst_BGACK_030_INTreg.BLIF bgack_030_int_0_un3_n.BLIF \
+bgack_030_int_0_un0_n
+11 1
+.names inst_CLK_000_PE.BLIF CYCLE_DMA_0_.BLIF N_209
+11 1
+.names CLK_000_NE_i.BLIF SM_AMIGA_5_.BLIF N_180_0
+11 1
+.names N_327.BLIF rw_000_dma_0_un3_n
+0 1
+.names IPL_030DFF_2_reg.BLIF IPL_030_2_
+1 1
+0 0
+.names un6_ds_030_i.BLIF DS_030
+1 1
+0 0
+.names BG_000DFFreg.BLIF BG_000
+1 1
+0 0
+.names inst_BGACK_030_INTreg.BLIF BGACK_030
+1 1
+0 0
+.names inst_CLK_OUT_INTreg.BLIF CLK_DIV_OUT
+1 1
+0 0
+.names CLK_OUT_EXP_INT_i.BLIF CLK_EXP
+1 1
+0 0
+.names un21_fpu_cs_i.BLIF FPU_CS
+1 1
+0 0
+.names inst_DSACK1_INTreg.BLIF DSACK1
+1 1
+0 0
+.names vcc_n_n.BLIF AVEC
+1 1
+0 0
+.names un5_e.BLIF E
+1 1
+0 0
+.names inst_VMA_INTreg.BLIF VMA
+1 1
+0 0
+.names gnd_n_n.BLIF RESET
+1 1
+0 0
+.names gnd_n_n.BLIF AMIGA_ADDR_ENABLE
+1 1
+0 0
+.names AMIGA_BUS_DATA_DIR_c.BLIF AMIGA_BUS_DATA_DIR
+1 1
+0 0
+.names un1_amiga_bus_enable_low_i.BLIF AMIGA_BUS_ENABLE_LOW
+1 1
+0 0
+.names N_190_i.BLIF AMIGA_BUS_ENABLE_HIGH
+1 1
+0 0
+.names un5_ciin.BLIF CIIN
+1 1
+0 0
+.names IPL_030DFF_1_reg.BLIF IPL_030_1_
+1 1
+0 0
+.names IPL_030DFF_0_reg.BLIF IPL_030_0_
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_i_7_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_6_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_5_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_4_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_3_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_2_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_1_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SM_AMIGA_0_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF cpu_est_2_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF cpu_est_3_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF IPL_030DFF_0_reg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF IPL_030DFF_1_reg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF IPL_030DFF_2_reg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF IPL_D0_0_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF IPL_D0_1_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF IPL_D0_2_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_4_.BLIF CLK_000_N_SYNC_5_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_5_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_5_.BLIF CLK_000_N_SYNC_6_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_6_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_6_.BLIF CLK_000_N_SYNC_7_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_7_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_7_.BLIF CLK_000_N_SYNC_8_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_8_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_8_.BLIF CLK_000_N_SYNC_9_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_9_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_9_.BLIF CLK_000_N_SYNC_10_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_10_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_10_.BLIF CLK_000_N_SYNC_11_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_11_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CYCLE_DMA_0_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CYCLE_DMA_1_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SIZE_DMA_0_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF SIZE_DMA_1_.C
+1 1
+0 0
+.names cpu_est_0_0_x2_0_x2_0_.BLIF cpu_est_0_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF cpu_est_0_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF cpu_est_1_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_0_.BLIF CLK_000_P_SYNC_1_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_1_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_1_.BLIF CLK_000_P_SYNC_2_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_2_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_2_.BLIF CLK_000_P_SYNC_3_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_3_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_3_.BLIF CLK_000_P_SYNC_4_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_4_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_4_.BLIF CLK_000_P_SYNC_5_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_5_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_5_.BLIF CLK_000_P_SYNC_6_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_6_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_6_.BLIF CLK_000_P_SYNC_7_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_7_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_7_.BLIF CLK_000_P_SYNC_8_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_8_.C
+1 1
+0 0
+.names CLK_000_P_SYNC_8_.BLIF CLK_000_P_SYNC_9_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_9_.C
+1 1
+0 0
+.names N_147_i.BLIF CLK_000_N_SYNC_0_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_0_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_0_.BLIF CLK_000_N_SYNC_1_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_1_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_1_.BLIF CLK_000_N_SYNC_2_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_2_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_2_.BLIF CLK_000_N_SYNC_3_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_3_.C
+1 1
+0 0
+.names CLK_000_N_SYNC_3_.BLIF CLK_000_N_SYNC_4_.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_N_SYNC_4_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF RST_DLY_0_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF RST_DLY_1_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF RST_DLY_2_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF CLK_000_P_SYNC_0_.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_DS_000_ENABLE.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_RW_000_DMA.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_RW_000_INT.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_LDS_000_INT.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_BGACK_030_INTreg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_AS_000_DMA.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_AS_030_000_SYNC.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_AS_000_INT.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_DSACK1_INTreg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_DS_000_DMA.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_AS_030_D0.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_nEXP_SPACE_D0reg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_VPA_D.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_DTACK_D0.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_030_H.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_RESET_OUT.C
+1 1
+0 0
+.names CLK_OUT_PRE_25_0.BLIF inst_CLK_OUT_PRE_25.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_25.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF BG_000DFFreg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_HIGH.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_AMIGA_BUS_ENABLE_DMA_LOW.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_VMA_INTreg.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_UDS_000_INT.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_A0_DMA.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_BGACK_030_INT_D.C
+1 1
+0 0
+.names CLK_000_N_SYNC_11_.BLIF inst_CLK_000_NE.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_000_NE.C
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_50.C
+1 1
+0 0
+.names inst_CLK_OUT_PRE_D.BLIF inst_CLK_OUT_INTreg.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_OUT_INTreg.C
+1 1
+0 0
+.names inst_CLK_000_D0.BLIF inst_CLK_000_D1.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_000_D1.C
+1 1
+0 0
+.names inst_CLK_000_NE.BLIF inst_CLK_000_NE_D0.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_000_NE_D0.C
+1 1
+0 0
+.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_EXP_INT.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_OUT_EXP_INT.C
+1 1
+0 0
+.names inst_CLK_OUT_PRE_25.BLIF inst_CLK_OUT_PRE_D.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_OUT_PRE_D.C
+1 1
+0 0
+.names CLK_000.BLIF inst_CLK_000_D0.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_000_D0.C
+1 1
+0 0
+.names CLK_000_P_SYNC_9_.BLIF inst_CLK_000_PE.D
+1 1
+0 0
+.names CLK_OSZI_c.BLIF inst_CLK_000_PE.C
+1 1
+0 0
+.names un3_size.BLIF SIZE_1_
+1 1
+0 0
+.names N_137.BLIF AS_030
+1 1
+0 0
+.names un4_as_000_i.BLIF AS_000
+1 1
+0 0
+.names inst_RW_000_INT.BLIF RW_000
+1 1
+0 0
+.names un4_uds_000_i.BLIF UDS_000
+1 1
+0 0
+.names un4_lds_000_i.BLIF LDS_000
+1 1
+0 0
+.names inst_A0_DMA.BLIF A0
+1 1
+0 0
+.names gnd_n_n.BLIF BERR
+1 1
+0 0
+.names inst_RW_000_DMA.BLIF RW
+1 1
+0 0
+.names un4_size.BLIF SIZE_0_
+1 1
+0 0
+.names A_15_.BLIF a_15__n
+1 1
+0 0
+.names A_14_.BLIF a_14__n
+1 1
+0 0
+.names A_13_.BLIF a_13__n
+1 1
+0 0
+.names A_12_.BLIF a_12__n
+1 1
+0 0
+.names A_11_.BLIF a_11__n
+1 1
+0 0
+.names A_10_.BLIF a_10__n
+1 1
+0 0
+.names A_9_.BLIF a_9__n
+1 1
+0 0
+.names A_8_.BLIF a_8__n
+1 1
+0 0
+.names A_7_.BLIF a_7__n
+1 1
+0 0
+.names A_6_.BLIF a_6__n
+1 1
+0 0
+.names A_5_.BLIF a_5__n
+1 1
+0 0
+.names A_4_.BLIF a_4__n
+1 1
+0 0
+.names A_3_.BLIF a_3__n
+1 1
+0 0
+.names A_2_.BLIF a_2__n
+1 1
+0 0
+.names AS_030.PIN.BLIF AS_030_c
+1 1
+0 0
+.names AS_000.PIN.BLIF AS_000_c
+1 1
+0 0
+.names RW_000.PIN.BLIF RW_000_c
+1 1
+0 0
+.names UDS_000.PIN.BLIF UDS_000_c
+1 1
+0 0
+.names LDS_000.PIN.BLIF LDS_000_c
+1 1
+0 0
+.names SIZE_0_.PIN.BLIF size_c_0__n
+1 1
+0 0
+.names SIZE_1_.PIN.BLIF size_c_1__n
+1 1
+0 0
+.names A_16_.BLIF a_c_16__n
+1 1
+0 0
+.names A_17_.BLIF a_c_17__n
+1 1
+0 0
+.names A_18_.BLIF a_c_18__n
+1 1
+0 0
+.names A_19_.BLIF a_c_19__n
+1 1
+0 0
+.names A_20_.BLIF a_c_20__n
+1 1
+0 0
+.names A_21_.BLIF a_c_21__n
+1 1
+0 0
+.names A_22_.BLIF a_c_22__n
+1 1
+0 0
+.names A_23_.BLIF a_c_23__n
+1 1
+0 0
+.names A_24_.BLIF a_c_24__n
+1 1
+0 0
+.names A_25_.BLIF a_c_25__n
+1 1
+0 0
+.names A_26_.BLIF a_c_26__n
+1 1
+0 0
+.names A_27_.BLIF a_c_27__n
+1 1
+0 0
+.names A_28_.BLIF a_c_28__n
+1 1
+0 0
+.names A_29_.BLIF a_c_29__n
+1 1
+0 0
+.names A_30_.BLIF a_c_30__n
+1 1
+0 0
+.names A_31_.BLIF a_c_31__n
+1 1
+0 0
+.names A0.PIN.BLIF A0_c
+1 1
+0 0
+.names A1.BLIF A1_c
+1 1
+0 0
+.names nEXP_SPACE.BLIF nEXP_SPACE_c
+1 1
+0 0
+.names BERR.PIN.BLIF BERR_c
+1 1
+0 0
+.names BG_030.BLIF BG_030_c
+1 1
+0 0
+.names BGACK_000.BLIF BGACK_000_c
+1 1
+0 0
+.names CLK_030.BLIF CLK_030_c
+1 1
+0 0
+.names CLK_OSZI.BLIF CLK_OSZI_c
+1 1
+0 0
+.names FPU_SENSE.BLIF FPU_SENSE_c
+1 1
+0 0
+.names IPL_0_.BLIF ipl_c_0__n
+1 1
+0 0
+.names IPL_1_.BLIF ipl_c_1__n
+1 1
+0 0
+.names IPL_2_.BLIF ipl_c_2__n
+1 1
+0 0
+.names DTACK.BLIF DTACK_c
+1 1
+0 0
+.names VPA.BLIF VPA_c
+1 1
+0 0
+.names RST.BLIF RST_c
+1 1
+0 0
+.names RW.PIN.BLIF RW_c
+1 1
+0 0
+.names FC_0_.BLIF fc_c_0__n
+1 1
+0 0
+.names FC_1_.BLIF fc_c_1__n
+1 1
+0 0
+.names N_231.BLIF AS_030.OE
+1 1
+0 0
+.names N_230.BLIF AS_000.OE
+1 1
+0 0
+.names N_230.BLIF RW_000.OE
+1 1
+0 0
+.names N_230.BLIF UDS_000.OE
+1 1
+0 0
+.names N_230.BLIF LDS_000.OE
+1 1
+0 0
+.names un1_as_030_i.BLIF SIZE_0_.OE
+1 1
+0 0
+.names un1_as_030_i.BLIF SIZE_1_.OE
+1 1
+0 0
+.names N_231.BLIF A0.OE
+1 1
+0 0
+.names un22_berr.BLIF BERR.OE
+1 1
+0 0
+.names N_332.BLIF RW.OE
+1 1
+0 0
+.names N_231.BLIF DS_030.OE
+1 1
+0 0
+.names inst_nEXP_SPACE_D0reg.BLIF DSACK1.OE
+1 1
+0 0
+.names RESET_OUT_i.BLIF RESET.OE
+1 1
+0 0
+.names N_61.BLIF CIIN.OE
+1 1
+0 0
+.names CYCLE_DMA_0_.BLIF CYCLE_DMA_1_.BLIF \
+pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2
+01 1
+10 1
+11 0
+00 0
+.names inst_CLK_OUT_PRE_50.BLIF inst_CLK_OUT_PRE_25.BLIF CLK_OUT_PRE_25_0
+01 1
+10 1
+11 0
+00 0
+.names IPL_D0_0_.BLIF ipl_c_0__n.BLIF G_134
+01 1
+10 1
+11 0
+00 0
+.names IPL_D0_1_.BLIF ipl_c_1__n.BLIF G_135
+01 1
+10 1
+11 0
+00 0
+.names IPL_D0_2_.BLIF ipl_c_2__n.BLIF G_136
+01 1
+10 1
+11 0
+00 0
+.names cpu_est_0_.BLIF inst_CLK_000_NE_D0.BLIF cpu_est_0_0_x2_0_x2_0_
+01 1
+10 1
+11 0
+00 0
+.names CYCLE_DMA_0_.BLIF inst_CLK_000_PE.BLIF pos_clk_CYCLE_DMA_5_0_i_0_x2
+01 1
+10 1
+11 0
+00 0
+.names CYCLE_DMA_1_.BLIF N_209.BLIF pos_clk_CYCLE_DMA_5_1_i_0_x2
+01 1
+10 1
+11 0
+00 0
+.end
diff --git a/Logic/BUS68030.edi b/Logic/BUS68030.edi
new file mode 100644
index 0000000..b919969
--- /dev/null
+++ b/Logic/BUS68030.edi
@@ -0,0 +1,4596 @@
+(edif BUS68030
+  (edifVersion 2 0 0)
+  (edifLevel 0)
+  (keywordMap (keywordLevel 0))
+  (status
+    (written
+      (timeStamp 2016 1 24 16 20 49)
+      (author "Synopsys, Inc.")
+      (program "Synplify Pro" (version "I-2014.03LC , mapper maplat, Build 923R"))
+     )
+   )
+  (external mach
+    (edifLevel 0)
+    (technology (numberDefinition ))
+    (cell AND2 (cellType GENERIC)
+       (view prim (viewType NETLIST)
+         (interface
+           (port O (direction OUTPUT))
+           (port I0 (direction INPUT))
+           (port I1 (direction INPUT))
+         )
+       )
+    )
+    (cell BI_DIR (cellType GENERIC)
+       (view prim (viewType NETLIST)
+         (interface
+           (port O (direction OUTPUT))
+           (port I0 (direction INPUT))
+           (port IO (direction INOUT))
+           (port OE (direction INPUT))
+         )
+       )
+    )
+    (cell BUFTH (cellType GENERIC)
+       (view prim (viewType NETLIST)
+         (interface
+           (port O (direction OUTPUT))
+           (port I0 (direction INPUT))
+           (port OE (direction INPUT))
+         )
+       )
+    )
+    (cell DFF (cellType GENERIC)
+       (view prim (viewType NETLIST)
+         (interface
+           (port Q (direction OUTPUT))
+           (port D (direction INPUT))
+           (port CLK (direction INPUT))
+         )
+       )
+    )
+    (cell IBUF (cellType GENERIC)
+       (view prim (viewType NETLIST)
+         (interface
+           (port O (direction OUTPUT))
+           (port I0 (direction INPUT))
+         )
+       )
+    )
+    (cell INV (cellType GENERIC)
+       (view prim (viewType NETLIST)
+         (interface
+           (port O (direction OUTPUT))
+           (port I0 (direction INPUT))
+         )
+       )
+    )
+    (cell OBUF (cellType GENERIC)
+       (view prim (viewType NETLIST)
+         (interface
+           (port O (direction OUTPUT))
+           (port I0 (direction INPUT))
+         )
+       )
+    )
+    (cell OR2 (cellType GENERIC)
+       (view prim (viewType NETLIST)
+         (interface
+           (port O (direction OUTPUT))
+           (port I0 (direction INPUT))
+           (port I1 (direction INPUT))
+         )
+       )
+    )
+    (cell XOR2 (cellType GENERIC)
+       (view prim (viewType NETLIST)
+         (interface
+           (port O (direction OUTPUT))
+           (port I0 (direction INPUT))
+           (port I1 (direction INPUT))
+         )
+       )
+    )
+  )
+  (library work
+    (edifLevel 0)
+    (technology (numberDefinition ))
+    (cell BUS68030 (cellType GENERIC)
+       (view behavioral (viewType NETLIST)
+         (interface
+           (port (array (rename size "SIZE(1:0)") 2) (direction INOUT))
+           (port (array (rename a "A(31:2)") 30) (direction INPUT))
+           (port (array (rename ipl_030 "IPL_030(2:0)") 3) (direction OUTPUT))
+           (port (array (rename ipl "IPL(2:0)") 3) (direction INPUT))
+           (port (array (rename fc "FC(1:0)") 2) (direction INPUT))
+           (port AS_030 (direction INOUT))
+           (port AS_000 (direction INOUT))
+           (port RW_000 (direction INOUT))
+           (port DS_030 (direction OUTPUT))
+           (port UDS_000 (direction INOUT))
+           (port LDS_000 (direction INOUT))
+           (port A0 (direction INOUT))
+           (port A1 (direction INPUT))
+           (port nEXP_SPACE (direction INPUT))
+           (port BERR (direction INOUT))
+           (port BG_030 (direction INPUT))
+           (port BG_000 (direction OUTPUT))
+           (port BGACK_030 (direction OUTPUT))
+           (port BGACK_000 (direction INPUT))
+           (port CLK_030 (direction INPUT))
+           (port CLK_000 (direction INPUT))
+           (port CLK_OSZI (direction INPUT))
+           (port CLK_DIV_OUT (direction OUTPUT))
+           (port CLK_EXP (direction OUTPUT))
+           (port FPU_CS (direction OUTPUT))
+           (port FPU_SENSE (direction INPUT))
+           (port DSACK1 (direction OUTPUT))
+           (port DTACK (direction INPUT))
+           (port AVEC (direction OUTPUT))
+           (port E (direction OUTPUT))
+           (port VPA (direction INPUT))
+           (port VMA (direction OUTPUT))
+           (port RST (direction INPUT))
+           (port RESET (direction OUTPUT))
+           (port RW (direction INOUT))
+           (port AMIGA_ADDR_ENABLE (direction OUTPUT))
+           (port AMIGA_BUS_DATA_DIR (direction OUTPUT))
+           (port AMIGA_BUS_ENABLE_LOW (direction OUTPUT))
+           (port AMIGA_BUS_ENABLE_HIGH (direction OUTPUT))
+           (port CIIN (direction OUTPUT))
+         )
+         (contents
+          (instance (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename SM_AMIGA_6 "SM_AMIGA[6]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename SM_AMIGA_5 "SM_AMIGA[5]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename SM_AMIGA_4 "SM_AMIGA[4]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename SM_AMIGA_3 "SM_AMIGA[3]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename SM_AMIGA_2 "SM_AMIGA[2]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename SM_AMIGA_1 "SM_AMIGA[1]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename SM_AMIGA_0 "SM_AMIGA[0]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename cpu_est_2 "cpu_est[2]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename cpu_est_3 "cpu_est[3]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename IPL_030DFF_0 "IPL_030DFF[0]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename IPL_030DFF_1 "IPL_030DFF[1]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename IPL_030DFF_2 "IPL_030DFF[2]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename IPL_D0_0 "IPL_D0[0]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename IPL_D0_1 "IPL_D0[1]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename IPL_D0_2 "IPL_D0[2]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_N_SYNC_5 "CLK_000_N_SYNC[5]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_N_SYNC_6 "CLK_000_N_SYNC[6]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_N_SYNC_7 "CLK_000_N_SYNC[7]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename SIZE_DMA_0 "SIZE_DMA[0]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename SIZE_DMA_1 "SIZE_DMA[1]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename cpu_est_0 "cpu_est[0]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename cpu_est_1 "cpu_est[1]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_P_SYNC_1 "CLK_000_P_SYNC[1]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_P_SYNC_2 "CLK_000_P_SYNC[2]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_P_SYNC_3 "CLK_000_P_SYNC[3]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_P_SYNC_4 "CLK_000_P_SYNC[4]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_P_SYNC_5 "CLK_000_P_SYNC[5]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_P_SYNC_6 "CLK_000_P_SYNC[6]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_P_SYNC_7 "CLK_000_P_SYNC[7]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_P_SYNC_8 "CLK_000_P_SYNC[8]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_N_SYNC_0 "CLK_000_N_SYNC[0]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_N_SYNC_1 "CLK_000_N_SYNC[1]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_N_SYNC_2 "CLK_000_N_SYNC[2]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_N_SYNC_3 "CLK_000_N_SYNC[3]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_N_SYNC_4 "CLK_000_N_SYNC[4]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename RST_DLY_0 "RST_DLY[0]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename RST_DLY_1 "RST_DLY[1]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename RST_DLY_2 "RST_DLY[2]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance DS_000_ENABLE (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance RW_000_DMA (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance RW_000_INT (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance LDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance BGACK_030_INT (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance AS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance AS_030_000_SYNC (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance AS_000_INT (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance DSACK1_INT (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance DS_000_DMA (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance AS_030_D0 (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance nEXP_SPACE_D0 (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance VPA_D (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance DTACK_D0 (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance CLK_030_H (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance RESET_OUT (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance CLK_OUT_PRE_25 (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance BG_000DFF (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance AMIGA_BUS_ENABLE_DMA_HIGH (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance AMIGA_BUS_ENABLE_DMA_LOW (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance VMA_INT (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance UDS_000_INT (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance A0_DMA (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance BGACK_030_INT_D (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance CLK_000_NE (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance CLK_OUT_PRE_50 (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance CLK_OUT_INT (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance CLK_000_D1 (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance CLK_000_NE_D0 (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance CLK_OUT_EXP_INT (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance CLK_OUT_PRE_D (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance CLK_000_D0 (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance CLK_000_PE (viewRef prim (cellRef DFF (libraryRef mach)))
+          )
+          (instance AS_030 (viewRef prim (cellRef BI_DIR (libraryRef mach)))          )
+          (instance AS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach)))          )
+          (instance RW_000 (viewRef prim (cellRef BI_DIR (libraryRef mach)))          )
+          (instance DS_030 (viewRef prim (cellRef BUFTH (libraryRef mach)))          )
+          (instance UDS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach)))          )
+          (instance LDS_000 (viewRef prim (cellRef BI_DIR (libraryRef mach)))          )
+          (instance (rename SIZE_0 "SIZE[0]") (viewRef prim (cellRef BI_DIR (libraryRef mach)))          )
+          (instance (rename SIZE_1 "SIZE[1]") (viewRef prim (cellRef BI_DIR (libraryRef mach)))          )
+          (instance (rename A_2 "A[2]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_3 "A[3]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_4 "A[4]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_5 "A[5]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_6 "A[6]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_7 "A[7]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_8 "A[8]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_9 "A[9]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_10 "A[10]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_11 "A[11]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_12 "A[12]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_13 "A[13]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_14 "A[14]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_15 "A[15]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_16 "A[16]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_17 "A[17]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_18 "A[18]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_19 "A[19]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_20 "A[20]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_21 "A[21]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_22 "A[22]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_23 "A[23]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_24 "A[24]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_25 "A[25]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_26 "A[26]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_27 "A[27]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_28 "A[28]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_29 "A[29]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_30 "A[30]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename A_31 "A[31]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance A0 (viewRef prim (cellRef BI_DIR (libraryRef mach)))          )
+          (instance A1 (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance nEXP_SPACE (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance BERR (viewRef prim (cellRef BI_DIR (libraryRef mach)))          )
+          (instance BG_030 (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance BG_000 (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance BGACK_030 (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance BGACK_000 (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance CLK_030 (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance CLK_000 (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance CLK_OSZI (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance CLK_DIV_OUT (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance CLK_EXP (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance FPU_CS (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance FPU_SENSE (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename IPL_030_0 "IPL_030[0]") (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance (rename IPL_030_1 "IPL_030[1]") (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance (rename IPL_030_2 "IPL_030[2]") (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance (rename IPL_0 "IPL[0]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename IPL_1 "IPL[1]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename IPL_2 "IPL[2]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance DSACK1 (viewRef prim (cellRef BUFTH (libraryRef mach)))          )
+          (instance DTACK (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance AVEC (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance E (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance VPA (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance VMA (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance RST (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance RESET (viewRef prim (cellRef BUFTH (libraryRef mach)))          )
+          (instance RW (viewRef prim (cellRef BI_DIR (libraryRef mach)))          )
+          (instance (rename FC_0 "FC[0]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance (rename FC_1 "FC[1]") (viewRef prim (cellRef IBUF (libraryRef mach)))          )
+          (instance AMIGA_ADDR_ENABLE (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance AMIGA_BUS_DATA_DIR (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance AMIGA_BUS_ENABLE_LOW (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance AMIGA_BUS_ENABLE_HIGH (viewRef prim (cellRef OBUF (libraryRef mach)))          )
+          (instance CIIN (viewRef prim (cellRef BUFTH (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_a3_1_1_0 "SM_AMIGA_nss_i_i_0_0_a3_1_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_a3_1_0 "SM_AMIGA_nss_i_i_0_0_a3_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_a3_0_1_0 "SM_AMIGA_nss_i_i_0_0_a3_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_a3_0_0 "SM_AMIGA_nss_i_i_0_0_a3_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e1_i_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e1_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e2_i_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e2_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance G_137_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance G_137 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_4 "SM_AMIGA_srsts_i_0_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_1_5 "SM_AMIGA_srsts_i_0_0_1[5]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_5 "SM_AMIGA_srsts_i_0_0[5]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_e_0_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_e_0_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_a3_0_1_6 "SM_AMIGA_srsts_i_i_0_a3_0_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_a3_0_6 "SM_AMIGA_srsts_i_i_0_a3_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_a3_1_6 "SM_AMIGA_srsts_i_i_0_a3_1[6]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_a3_6 "SM_AMIGA_srsts_i_i_0_a3[6]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_a3_1_2 "SM_AMIGA_srsts_i_i_0_a3_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_a3_2 "SM_AMIGA_srsts_i_i_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_a3_0_1_1 "cpu_est_2_0_0_a3_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_a3_0_1 "cpu_est_2_0_0_a3_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_a3_0_1_3 "SM_AMIGA_srsts_i_0_0_a3_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_a3_0_3 "SM_AMIGA_srsts_i_0_0_a3_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un6_bg_030_0_a2_i_1 "pos_clk.un6_bg_030_0_a2_i_1") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un6_bg_030_0_a2_i "pos_clk.un6_bg_030_0_a2_i") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_1_1 "SM_AMIGA_srsts_i_0_0_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_1 "SM_AMIGA_srsts_i_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un1_SM_AMIGA_3_i_0_0_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un1_SM_AMIGA_3_i_0_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_CYCLE_DMA_5_1_i_0_1 "pos_clk.CYCLE_DMA_5_1_i_0_1") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_CYCLE_DMA_5_1_i_0 "pos_clk.CYCLE_DMA_5_1_i_0") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_1 "pos_clk.CYCLE_DMA_5_0_i_0_1") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_CYCLE_DMA_5_0_i_0 "pos_clk.CYCLE_DMA_5_0_i_0") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance DS_000_DMA_2_sqmuxa_0_a2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance DS_000_DMA_2_sqmuxa_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance CLK_030_H_2_0_a2_i_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance CLK_030_H_2_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_1_4 "SM_AMIGA_srsts_i_0_0_1[4]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un37_as_030_d0_i_a2_1_3 "pos_clk.un37_as_030_d0_i_a2_1_3") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un37_as_030_d0_i_a2_1_4 "pos_clk.un37_as_030_d0_i_a2_1_4") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un37_as_030_d0_i_a2_1 "pos_clk.un37_as_030_d0_i_a2_1") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AMIGA_BUS_DATA_DIR_0_0_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AMIGA_BUS_DATA_DIR_0_0_0_a3_0_2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AMIGA_BUS_DATA_DIR_0_0_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un21_fpu_cs_0_a2_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un21_fpu_cs_0_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un22_berr_0_a2_0_a3_1_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un22_berr_0_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un37_as_030_d0_i_i_a3_1 "pos_clk.un37_as_030_d0_i_i_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un37_as_030_d0_i_i_a3_2 "pos_clk.un37_as_030_d0_i_i_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un37_as_030_d0_i_i_a3 "pos_clk.un37_as_030_d0_i_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e0_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e0_i_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_ciin_0_a2_0_a3_7 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_ciin_0_a2_0_a3_8 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_ciin_0_a2_0_a3_9 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_ciin_0_a2_0_a3_10 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_ciin_0_a2_0_a3_11 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_ciin_0_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e0_i_0_a3_0_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e0_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e1_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e1_i_0_2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e1_i_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e2_i_0_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e2_i_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un37_as_030_d0_i_a2_1_1 "pos_clk.un37_as_030_d0_i_a2_1_1") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un37_as_030_d0_i_a2_1_2 "pos_clk.un37_as_030_d0_i_a2_1_2") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un7_clk_000_pe_0_0_a3_0_2 "pos_clk.un7_clk_000_pe_0_0_a3_0_2") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un7_clk_000_pe_0_0_a3_0 "pos_clk.un7_clk_000_pe_0_0_a3_0") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un7_clk_000_pe_0_0_a3_1 "pos_clk.un7_clk_000_pe_0_0_a3_1") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un7_clk_000_pe_0_0_a3_2 "pos_clk.un7_clk_000_pe_0_0_a3_2") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un7_clk_000_pe_0_0_a3 "pos_clk.un7_clk_000_pe_0_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_a3_2_1_0 "SM_AMIGA_nss_i_i_0_0_a3_2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_a3_2_2_0 "SM_AMIGA_nss_i_i_0_0_a3_2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_a3_2_3_0 "SM_AMIGA_nss_i_i_0_0_a3_2_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_a3_2_0 "SM_AMIGA_nss_i_i_0_0_a3_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_ciin_0_a2_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_ciin_0_a2_0_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_ciin_0_a2_0_a3_3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_ciin_0_a2_0_a3_4 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_ciin_0_a2_0_a3_5 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_ciin_0_a2_0_a3_6 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0 "SM_AMIGA_nss_i_i_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un1_SM_AMIGA_5_0_o2_3_o3_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un1_SM_AMIGA_5_0_o2_3_o3_2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un1_SM_AMIGA_5_0_o2_3_o3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_1_3 "SM_AMIGA_srsts_i_0_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_2_3 "SM_AMIGA_srsts_i_0_0_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_3 "SM_AMIGA_srsts_i_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_1_0 "SM_AMIGA_nss_i_i_0_0_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_2_0 "SM_AMIGA_nss_i_i_0_0_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_3_0 "SM_AMIGA_nss_i_i_0_0_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_0 "SM_AMIGA_nss_i_i_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_a3_0_1_2 "SM_AMIGA_srsts_i_i_0_a3_0_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_a3_0_2_2 "SM_AMIGA_srsts_i_i_0_a3_0_2[2]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_a3_0_2 "SM_AMIGA_srsts_i_i_0_a3_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un7_clk_000_pe_0_0_a3_0_1 "pos_clk.un7_clk_000_pe_0_0_a3_0_1") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance N_22_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance VMA_INT_1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_26_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance BG_000_1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance BG_030_c_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_un8_bg_030_i "pos_clk.un8_bg_030_i") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3_1 "pos_clk.un24_bgack_030_int_i_0_i_a3_i_o3_1") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3_2 "pos_clk.un24_bgack_030_int_i_0_i_a3_i_o3_2") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3 "pos_clk.un24_bgack_030_int_i_0_i_a3_i_o3") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un8_sm_amiga_1 "pos_clk.un8_sm_amiga_1") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un8_sm_amiga "pos_clk.un8_sm_amiga") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_1_3 "SM_AMIGA_srsts_i_0_0_a2_0_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_2_3 "SM_AMIGA_srsts_i_0_0_a2_0_2[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_a2_0_3 "SM_AMIGA_srsts_i_0_0_a2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_o2_1_0_0 "SM_AMIGA_nss_i_i_0_0_o2_1_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance N_205_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance A0_c_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SIZE_c_i_1 "SIZE_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_27_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename IPL_030_1_i_0 "IPL_030_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename IPL_c_i_0 "IPL_c_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename IPL_D0_0_i_0 "IPL_D0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_4_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance DSACK1_INT_1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_17_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance LDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_18_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance RW_000_INT_2_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_21_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance UDS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_224_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_225_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_i_6 "SM_AMIGA_srsts_i_i_0_i[6]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_221_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_222_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_219_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_220_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_i_2 "SM_AMIGA_srsts_i_i_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_216_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_218_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_0_i_1 "cpu_est_2_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_373_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_375_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_un7_clk_000_pe_0_0_i "pos_clk.un7_clk_000_pe_0_0_i") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_188_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_0_i_3 "cpu_est_2_0_0_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_277_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_348_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_0_i_2 "cpu_est_2_0_0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_un6_bg_030_0_a2_i_i "pos_clk.un6_bg_030_0_a2_i_i") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_193_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_241_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_240_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un1_SM_AMIGA_3_i_0_0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance DSACK1_INT_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un5_ciin_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un8_ciin_i_0_0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_228_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance DS_000_DMA_2_sqmuxa_0_a2_i_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_226_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance DSACK1_INT_1_sqmuxa_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_318_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_0_o2_i_2 "cpu_est_2_0_0_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_0_o2_i_3 "cpu_est_2_0_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance CLK_OUT_PRE_D_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance DSACK1_INT_1_sqmuxa_i_0_o2_0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_o2_i_0 "SM_AMIGA_nss_i_i_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance AS_030_000_SYNC_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_o2_3_i_0 "SM_AMIGA_nss_i_i_0_0_o2_3_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_281_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_302_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_279_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_280_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un5_e_0_0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_278_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_o2_2_i_0 "SM_AMIGA_nss_i_i_0_0_o2_2_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_4 "SM_AMIGA_srsts_i_0_0_o2_i[4]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_0_0_o3_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_329_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_o2_i_2 "SM_AMIGA_srsts_i_i_0_o2_i[2]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_o2_i_6 "SM_AMIGA_srsts_i_i_0_o2_i[6]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_o2_1_i_0 "SM_AMIGA_nss_i_i_0_0_o2_1_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un1_SM_AMIGA_5_0_o2_3_o3_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_324_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_326_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_i_3 "SM_AMIGA_srsts_i_0_0_o2_0_i[3]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance VMA_INT_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0_i_0 "SM_AMIGA_nss_i_i_0_0_o2_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename CLK_000_N_SYNC_i_10 "CLK_000_N_SYNC_i[10]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_321_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_199_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance RESET_OUT_2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance RESET_OUT_1_sqmuxa_i_0_143_0_o2_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance RST_DLY_e2_i_0_o2_0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_307_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance RST_DLY_e2_i_0_o2_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_235_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_210_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_207_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_208_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_206_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_313_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_211_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_212_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_3 "SM_AMIGA_srsts_i_0_0_o2_i[3]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance BGACK_030_INT_1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_19_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance RW_000_DMA_2_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_20_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance A0_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_24_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance AMIGA_BUS_ENABLE_DMA_LOW_1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_25_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance AMIGA_BUS_ENABLE_DMA_HIGH_1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_198_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance RST_DLY_e2_i_0_2_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_196_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_195_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_201_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_200_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance AS_030_D0_0_i_a2_i_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_239_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_SIZE_DMA_6_0_0_0_i_1 "pos_clk.SIZE_DMA_6_0_0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_238_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_SIZE_DMA_6_0_0_0_i_0 "pos_clk.SIZE_DMA_6_0_0_0_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_237_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_236_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance AMIGA_BUS_DATA_DIR_0_0_0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_331_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_un6_bgack_000_0_0_i "pos_clk.un6_bgack_000_0_0_i") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance AS_000_DMA_1_sqmuxa_0_a2_i_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un14_amiga_bus_data_dir_0_a2_i_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_8_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance AS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_10_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_233_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_un37_as_030_d0_i_i_i "pos_clk.un37_as_030_d0_i_i_i") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance AS_000_INT_1_sqmuxa_i_0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance AS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un6_as_030_i_0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_312_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_un3_as_030_d0_0_o2_0_o3_i "pos_clk.un3_as_030_d0_0_o2_0_o3_i") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3_i "pos_clk.un24_bgack_030_int_i_0_i_a3_i_o3_i") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_1 "SM_AMIGA_srsts_i_0_0_o2_i[1]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_5 "SM_AMIGA_srsts_i_0_0_o2_i[5]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_o2_i_0 "SM_AMIGA_srsts_i_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance CLK_030_H_2_0_a2_i_o2_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance UDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance LDS_000_c_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_SIZE_DMA_6_0_0_0_o2_i_0 "pos_clk.SIZE_DMA_6_0_0_0_o2_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance VPA_c_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance VPA_D_0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance DTACK_c_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance DTACK_D0_0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename IPL_c_i_1 "IPL_c_i[1]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename IPL_D0_0_i_1 "IPL_D0_0_i[1]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename IPL_c_i_2 "IPL_c_i[2]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename IPL_D0_0_i_2 "IPL_D0_0_i[2]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_28_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename IPL_030_1_i_1 "IPL_030_1_i[1]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_29_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename IPL_030_1_i_2 "IPL_030_1_i[2]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_378_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_227_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_DS_000_DMA_4_f0_i_a2_i_i "pos_clk.DS_000_DMA_4_f0_i_a2_i_i") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_7_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance AS_030_000_SYNC_1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_5_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance AS_000_INT_1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_3_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance DS_000_DMA_1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance nEXP_SPACE_c_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance nEXP_SPACE_D0_0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance I_193 (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance DS_000_DMA_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un6_ds_030 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance N_190_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un1_amiga_bus_enable_low_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un21_fpu_cs_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance CLK_OUT_EXP_INT_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename IPL_030_0_1__r "IPL_030_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename IPL_030_0_1__m "IPL_030_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename IPL_030_0_1__n "IPL_030_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename IPL_030_0_1__p "IPL_030_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename IPL_030_1_2 "IPL_030_1[2]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename IPL_030_1_1 "IPL_030_1[1]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename IPL_D0_0_2 "IPL_D0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename IPL_D0_0_1 "IPL_D0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance DTACK_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance VPA_D_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance nEXP_SPACE_D0_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance DS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AS_030_000_SYNC_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename AS_030_000_SYNC_0_r "AS_030_000_SYNC_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename AS_030_000_SYNC_0_m "AS_030_000_SYNC_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename AS_030_000_SYNC_0_n "AS_030_000_SYNC_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename AS_030_000_SYNC_0_p "AS_030_000_SYNC_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename AS_000_INT_0_r "AS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename AS_000_INT_0_m "AS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename AS_000_INT_0_n "AS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename AS_000_INT_0_p "AS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename DS_000_DMA_0_r "DS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename DS_000_DMA_0_m "DS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename DS_000_DMA_0_n "DS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename DS_000_DMA_0_p "DS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance un1_SM_AMIGA_3_i_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance DS_000_DMA_2_sqmuxa_0_a2_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance I_194 (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_DS_000_DMA_4_f0_i_a2_i_a3 "pos_clk.DS_000_DMA_4_f0_i_a2_i_a3") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance CLK_000_NE_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_a3_0_4 "SM_AMIGA_srsts_i_0_0_a3_0[4]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_a3_0 "SM_AMIGA_srsts_i_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_a3_5 "SM_AMIGA_srsts_i_0_0_a3[5]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance G_136 (viewRef prim (cellRef XOR2 (libraryRef mach)))          )
+          (instance G_135 (viewRef prim (cellRef XOR2 (libraryRef mach)))          )
+          (instance G_129 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename IPL_030_0_2__r "IPL_030_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename IPL_030_0_2__m "IPL_030_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename IPL_030_0_2__n "IPL_030_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename IPL_030_0_2__p "IPL_030_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_o2_1 "SM_AMIGA_srsts_i_0_0_o2[1]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance I_195 (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_un3_as_030_d0_0_o2_0_o3 "pos_clk.un3_as_030_d0_0_o2_0_o3") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2 "pos_clk.un24_bgack_030_int_i_0_i_a3_i_x2") (viewRef prim (cellRef XOR2 (libraryRef mach)))          )
+          (instance un6_as_030_i_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AS_000_INT_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un37_as_030_d0_i_i "pos_clk.un37_as_030_d0_i_i") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_DS_000_DMA_4_f0_i_a2_i "pos_clk.DS_000_DMA_4_f0_i_a2_i") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance CLK_000_D0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_CLK_000_P_SYNC_2_0_a2_i_0 "pos_clk.CLK_000_P_SYNC_2_0_a2_i[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_0 "SM_AMIGA_srsts_i_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un24_bgack_030_int_i_0_i_a3_i_a2 "pos_clk.un24_bgack_030_int_i_0_i_a3_i_a2") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_a3_1 "SM_AMIGA_srsts_i_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__r "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0_.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__m "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__n "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__p "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance BGACK_030_INT_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance nEXP_SPACE_D0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance FPU_SENSE_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un22_berr_0_a2_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance I_196 (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_410_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_m3_1__r "SM_AMIGA_srsts_i_0_0_m3_1_.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_m3_1__m "SM_AMIGA_srsts_i_0_0_m3_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_m3_1__n "SM_AMIGA_srsts_i_0_0_m3_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_m3_1__p "SM_AMIGA_srsts_i_0_0_m3_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename pos_clk_CYCLE_DMA_5_1_i_0_x2 "pos_clk.CYCLE_DMA_5_1_i_0_x2") (viewRef prim (cellRef XOR2 (libraryRef mach)))          )
+          (instance (rename pos_clk_CYCLE_DMA_5_0_i_0_x2 "pos_clk.CYCLE_DMA_5_0_i_0_x2") (viewRef prim (cellRef XOR2 (libraryRef mach)))          )
+          (instance CLK_000_PE_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_m3_5__r "SM_AMIGA_srsts_i_0_0_m3_5_.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_m3_5__m "SM_AMIGA_srsts_i_0_0_m3_5_.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_m3_5__n "SM_AMIGA_srsts_i_0_0_m3_5_.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_m3_5__p "SM_AMIGA_srsts_i_0_0_m3_5_.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_o2_0 "SM_AMIGA_srsts_i_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_o2_5 "SM_AMIGA_srsts_i_0_0_o2[5]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance A1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3 "pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3 "pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance SIZE_DMA_3_sqmuxa_i_o2_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un6_bgack_000_0_0_a2 "pos_clk.un6_bgack_000_0_0_a2") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un14_amiga_bus_data_dir_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AS_000_DMA_1_sqmuxa_0_a2_i (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un6_bgack_000_0_0 "pos_clk.un6_bgack_000_0_0") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AMIGA_BUS_DATA_DIR_0_0_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_SIZE_DMA_6_0_0_0_0 "pos_clk.SIZE_DMA_6_0_0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_SIZE_DMA_6_0_0_0_1 "pos_clk.SIZE_DMA_6_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AS_030_D0_0_i_a2_i (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_SIZE_DMA_6_0_0_0_o2_0 "pos_clk.SIZE_DMA_6_0_0_0_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance CLK_030_H_2_0_a2_i_o2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AMIGA_BUS_ENABLE_DMA_HIGH_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance RW_000_DMA_2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance BGACK_030_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AS_000_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SIZE_DMA_0_0__r "SIZE_DMA_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SIZE_DMA_0_0__m "SIZE_DMA_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SIZE_DMA_0_0__n "SIZE_DMA_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SIZE_DMA_0_0__p "SIZE_DMA_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename SIZE_DMA_0_1__r "SIZE_DMA_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SIZE_DMA_0_1__m "SIZE_DMA_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SIZE_DMA_0_1__n "SIZE_DMA_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SIZE_DMA_0_1__p "SIZE_DMA_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename A_i_18 "A_i[18]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename A_i_19 "A_i[19]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename A_i_16 "A_i[16]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance CLK_030_H_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance CLK_030_H_2_0_a2_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance SIZE_DMA_3_sqmuxa_i_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AMIGA_BUS_DATA_DIR_0_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_SIZE_DMA_6_0_0_0_a3_0 "pos_clk.SIZE_DMA_6_0_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_SIZE_DMA_6_0_0_0_a3_1 "pos_clk.SIZE_DMA_6_0_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_A0_DMA_3_0_a2_0_a3 "pos_clk.A0_DMA_3_0_a2_0_a3") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AMIGA_BUS_ENABLE_DMA_LOW_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un1_amiga_bus_enable_low (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un4_as_000 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename AS_000_DMA_0_r "AS_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename AS_000_DMA_0_m "AS_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename AS_000_DMA_0_n "AS_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename AS_000_DMA_0_p "AS_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename BGACK_030_INT_0_r "BGACK_030_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename BGACK_030_INT_0_m "BGACK_030_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename BGACK_030_INT_0_n "BGACK_030_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename BGACK_030_INT_0_p "BGACK_030_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename RW_000_DMA_0_r "RW_000_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename RW_000_DMA_0_m "RW_000_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename RW_000_DMA_0_n "RW_000_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename RW_000_DMA_0_p "RW_000_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename A0_DMA_0_r "A0_DMA_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename A0_DMA_0_m "A0_DMA_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename A0_DMA_0_n "A0_DMA_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename A0_DMA_0_p "A0_DMA_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance N_113_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_r "AMIGA_BUS_ENABLE_DMA_LOW_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_m "AMIGA_BUS_ENABLE_DMA_LOW_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_n "AMIGA_BUS_ENABLE_DMA_LOW_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename AMIGA_BUS_ENABLE_DMA_LOW_0_p "AMIGA_BUS_ENABLE_DMA_LOW_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance N_114_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_r "AMIGA_BUS_ENABLE_DMA_HIGH_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_m "AMIGA_BUS_ENABLE_DMA_HIGH_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_n "AMIGA_BUS_ENABLE_DMA_HIGH_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_p "AMIGA_BUS_ENABLE_DMA_HIGH_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance AMIGA_BUS_ENABLE_DMA_HIGH_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AMIGA_BUS_ENABLE_DMA_LOW_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance A0_DMA_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e1_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e1_i_0_a3_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RESET_OUT_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance RESET_OUT_2_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e0_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e2_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RESET_OUT_1_sqmuxa_i_0_143_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e2_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename RST_DLY_i_0 "RST_DLY_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename RST_DLY_i_1 "RST_DLY_i[1]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance RST_DLY_e2_i_0_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename RST_DLY_i_2 "RST_DLY_i[2]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance RESET_OUT_1_sqmuxa_i_0_143_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RESET_OUT_2_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e2_i_0_2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_i_3 "cpu_est_i[3]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename cpu_est_i_0 "cpu_est_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance AS_030_D0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename A_i_24 "A_i[24]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un3_size (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un4_size (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RESET_OUT_2_i_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un2_rw_0_i_a2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un3_as_030_0_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un1_as_000_0_i_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e2_i_0_a3_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RST_DLY_e2_i_0_a3_2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance DSACK1_INT_1_sqmuxa_i_0_o2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_o2_5_0 "SM_AMIGA_nss_i_i_0_0_o2_5[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_o2_6_0 "SM_AMIGA_nss_i_i_0_0_o2_6[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_o2_0_0 "SM_AMIGA_nss_i_i_0_0_o2_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_o2_0_3 "SM_AMIGA_srsts_i_0_0_o2_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_o2_1_0 "SM_AMIGA_nss_i_i_0_0_o2_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_o2_6 "SM_AMIGA_srsts_i_i_0_o2[6]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_o2_2 "SM_AMIGA_srsts_i_i_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_o3_0 "SM_AMIGA_nss_i_i_0_0_o3[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_0_0_o3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_o2_4 "SM_AMIGA_srsts_i_0_0_o2[4]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_o2_2_0 "SM_AMIGA_nss_i_i_0_0_o2_2[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_o2_3 "SM_AMIGA_srsts_i_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_0_0_x2_0_x2_0 "cpu_est_0_0_x2_0_x2[0]") (viewRef prim (cellRef XOR2 (libraryRef mach)))          )
+          (instance VPA_D_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un1_as_030_0_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un8_ciin_i_0_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance DSACK1_INT_1_sqmuxa_i_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_0_2 "cpu_est_2_0_0_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_0_3 "cpu_est_2_0_0_0[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_e_0_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_o2_3_0 "SM_AMIGA_nss_i_i_0_0_o2_3[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance CLK_000_D1_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename pos_clk_CLK_000_N_SYNC_2_0_o3_i_o2_0 "pos_clk.CLK_000_N_SYNC_2_0_o3_i_o2[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance CLK_030_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance DSACK1_INT_1_sqmuxa_i_0_o2_0 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_0_o2_3 "cpu_est_2_0_0_0_o2[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un7_clk_000_pe_0_0_o2 "pos_clk.un7_clk_000_pe_0_0_o2") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_i_1 "cpu_est_i[1]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_0_o2_2 "cpu_est_2_0_0_0_o2[2]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_0_a3_2 "cpu_est_2_0_0_0_a3[2]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_0_a3_3 "cpu_est_2_0_0_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un5_e_0_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_a2_3 "SM_AMIGA_srsts_i_0_0_a2[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un1_SM_AMIGA_5_0_o2_3_a2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance DSACK1_INT_1_sqmuxa_i_0_a2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance DTACK_D0_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_a2_1_3 "SM_AMIGA_srsts_i_0_0_a2_1[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_a2_0 "SM_AMIGA_nss_i_i_0_0_a2[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_i_2 "cpu_est_i[2]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_0_a2_2 "cpu_est_2_0_0_0_a2[2]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un7_clk_000_pe_0_0 "pos_clk.un7_clk_000_pe_0_0") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_0_1 "cpu_est_2_0_0_0[1]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_2 "SM_AMIGA_srsts_i_i_0[2]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_i_0_6 "SM_AMIGA_srsts_i_i_0[6]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename A_i_27 "A_i[27]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename A_i_28 "A_i[28]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename A_i_29 "A_i[29]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename A_i_30 "A_i[30]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename A_i_31 "A_i[31]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance CLK_OUT_PRE_25_0 (viewRef prim (cellRef XOR2 (libraryRef mach)))          )
+          (instance G_134 (viewRef prim (cellRef XOR2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_nss_i_i_0_0_a3_0 "SM_AMIGA_nss_i_i_0_0_a3[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_a3_3 "SM_AMIGA_srsts_i_0_0_a3[3]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_2_0_0_0_a3_1 "cpu_est_2_0_0_0_a3[1]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename SM_AMIGA_srsts_i_0_0_a3_4 "SM_AMIGA_srsts_i_0_0_a3[4]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance I_197 (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance DS_000_ENABLE_1_sqmuxa_0_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance DSACK1_INT_1_sqmuxa_i_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance DS_000_ENABLE_1_sqmuxa_1_a2_0_a3 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance CLK_OUT_PRE_50_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_213_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_214_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_215_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename A_i_25 "A_i[25]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename A_i_26 "A_i[26]") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename cpu_est_0_2__r "cpu_est_0_2_.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename cpu_est_0_2__m "cpu_est_0_2_.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_0_2__n "cpu_est_0_2_.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_0_2__p "cpu_est_0_2_.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename cpu_est_0_3__r "cpu_est_0_3_.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename cpu_est_0_3__m "cpu_est_0_3_.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_0_3__n "cpu_est_0_3_.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_0_3__p "cpu_est_0_3_.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename IPL_030_0_0__r "IPL_030_0_0_.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename IPL_030_0_0__m "IPL_030_0_0_.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename IPL_030_0_0__n "IPL_030_0_0_.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename IPL_030_0_0__p "IPL_030_0_0_.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance DS_000_ENABLE_1_sqmuxa_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename RW_000_INT_0_r "RW_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename RW_000_INT_0_m "RW_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename RW_000_INT_0_n "RW_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename RW_000_INT_0_p "RW_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename UDS_000_INT_0_r "UDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename UDS_000_INT_0_m "UDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename UDS_000_INT_0_n "UDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename UDS_000_INT_0_p "UDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename VMA_INT_0_r "VMA_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename VMA_INT_0_m "VMA_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename VMA_INT_0_n "VMA_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename VMA_INT_0_p "VMA_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename BG_000_0_r "BG_000_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename BG_000_0_m "BG_000_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename BG_000_0_n "BG_000_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename BG_000_0_p "BG_000_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance DS_000_ENABLE_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance BG_000_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance VMA_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance UDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance RW_000_INT_2 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance LDS_000_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance DSACK1_INT_1 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename IPL_D0_0_0 "IPL_D0_0[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename IPL_030_1_0 "IPL_030_1[0]") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_0_1__r "cpu_est_0_1_.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename cpu_est_0_1__m "cpu_est_0_1_.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_0_1__n "cpu_est_0_1_.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename cpu_est_0_1__p "cpu_est_0_1_.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance UDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un4_uds_000 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance LDS_000_INT_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un4_lds_000 (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename pos_clk_un8_bg_030 "pos_clk.un8_bg_030") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance un4_uds_000_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un4_lds_000_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un4_as_000_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance un6_ds_030_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance N_98_i (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename DSACK1_INT_0_r "DSACK1_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename DSACK1_INT_0_m "DSACK1_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename DSACK1_INT_0_n "DSACK1_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename DSACK1_INT_0_p "DSACK1_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename DS_000_ENABLE_0_r "DS_000_ENABLE_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename DS_000_ENABLE_0_m "DS_000_ENABLE_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename DS_000_ENABLE_0_n "DS_000_ENABLE_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename DS_000_ENABLE_0_p "DS_000_ENABLE_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (instance (rename LDS_000_INT_0_r "LDS_000_INT_0.r") (viewRef prim (cellRef INV (libraryRef mach)))          )
+          (instance (rename LDS_000_INT_0_m "LDS_000_INT_0.m") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename LDS_000_INT_0_n "LDS_000_INT_0.n") (viewRef prim (cellRef AND2 (libraryRef mach)))          )
+          (instance (rename LDS_000_INT_0_p "LDS_000_INT_0.p") (viewRef prim (cellRef OR2 (libraryRef mach)))          )
+          (net BGACK_030_INT (joined
+           (portRef Q (instanceRef BGACK_030_INT))
+           (portRef I0 (instanceRef un1_as_000_0_i_a3))
+           (portRef I0 (instanceRef BGACK_030_INT_0_n))
+           (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3))
+           (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i_a2))
+           (portRef I0 (instanceRef BGACK_030_INT_i))
+           (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__m))
+           (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__r))
+           (portRef I0 (instanceRef BGACK_030))
+          ))
+          (net CLK_OUT_INT (joined
+           (portRef Q (instanceRef CLK_OUT_INT))
+           (portRef I0 (instanceRef CLK_DIV_OUT))
+          ))
+          (net VCC (joined
+           (portRef I0 (instanceRef AVEC))
+          ))
+          (net un5_e (joined
+           (portRef O (instanceRef un5_e_0_0_i))
+           (portRef I0 (instanceRef E))
+          ))
+          (net VMA_INT (joined
+           (portRef Q (instanceRef VMA_INT))
+           (portRef I0 (instanceRef VMA_INT_0_n))
+           (portRef I0 (instanceRef VMA_INT_i))
+           (portRef I0 (instanceRef VMA))
+          ))
+          (net GND (joined
+           (portRef I0 (instanceRef AMIGA_ADDR_ENABLE))
+           (portRef I0 (instanceRef BERR))
+           (portRef I0 (instanceRef RESET))
+          ))
+          (net un1_amiga_bus_enable_low (joined
+           (portRef O (instanceRef un1_amiga_bus_enable_low))
+           (portRef I0 (instanceRef un1_amiga_bus_enable_low_i))
+          ))
+          (net un3_size (joined
+           (portRef O (instanceRef un3_size))
+           (portRef I0 (instanceRef SIZE_1))
+          ))
+          (net un4_size (joined
+           (portRef O (instanceRef un4_size))
+           (portRef I0 (instanceRef SIZE_0))
+          ))
+          (net un4_uds_000 (joined
+           (portRef O (instanceRef un4_uds_000))
+           (portRef I0 (instanceRef un4_uds_000_i))
+          ))
+          (net un4_lds_000 (joined
+           (portRef O (instanceRef un4_lds_000))
+           (portRef I0 (instanceRef un4_lds_000_i))
+          ))
+          (net un5_ciin (joined
+           (portRef O (instanceRef un5_ciin_0_a2_0_a3))
+           (portRef I0 (instanceRef un5_ciin_i))
+           (portRef I0 (instanceRef CIIN))
+          ))
+          (net un4_as_000 (joined
+           (portRef O (instanceRef un4_as_000))
+           (portRef I0 (instanceRef un4_as_000_i))
+          ))
+          (net un1_SM_AMIGA_5 (joined
+           (portRef O (instanceRef un1_SM_AMIGA_5_0_o2_3_o3_i))
+           (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_1_a2_0_a3))
+          ))
+          (net un21_fpu_cs (joined
+           (portRef O (instanceRef un21_fpu_cs_0_a2_0_a3))
+           (portRef I0 (instanceRef un21_fpu_cs_i))
+          ))
+          (net un22_berr (joined
+           (portRef O (instanceRef un22_berr_0_a2_0_a3))
+           (portRef OE (instanceRef BERR))
+          ))
+          (net un6_ds_030 (joined
+           (portRef O (instanceRef un6_ds_030))
+           (portRef I0 (instanceRef un6_ds_030_i))
+          ))
+          (net (rename cpu_est_0 "cpu_est[0]") (joined
+           (portRef Q (instanceRef cpu_est_0))
+           (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_2))
+           (portRef I1 (instanceRef cpu_est_0_0_x2_0_x2_0))
+           (portRef I0 (instanceRef cpu_est_i_0))
+           (portRef I0 (instanceRef cpu_est_2_0_0_a3_0_1_1))
+          ))
+          (net (rename cpu_est_1 "cpu_est[1]") (joined
+           (portRef Q (instanceRef cpu_est_1))
+           (portRef I0 (instanceRef cpu_est_0_1__n))
+           (portRef I0 (instanceRef cpu_est_2_0_0_0_a3_1))
+           (portRef I1 (instanceRef cpu_est_2_0_0_0_o2_2))
+           (portRef I0 (instanceRef cpu_est_i_1))
+           (portRef I0 (instanceRef un5_e_0_0_a3_0_1))
+          ))
+          (net (rename cpu_est_2 "cpu_est[2]") (joined
+           (portRef Q (instanceRef cpu_est_2))
+           (portRef I0 (instanceRef cpu_est_0_2__n))
+           (portRef I0 (instanceRef cpu_est_i_2))
+           (portRef I1 (instanceRef cpu_est_2_0_0_0_a3_3))
+           (portRef I1 (instanceRef cpu_est_2_0_0_0_a3_2))
+           (portRef I1 (instanceRef un5_e_0_0_a3_0_1))
+          ))
+          (net (rename cpu_est_3 "cpu_est[3]") (joined
+           (portRef Q (instanceRef cpu_est_3))
+           (portRef I0 (instanceRef cpu_est_0_3__n))
+           (portRef I1 (instanceRef un5_e_0_0_a3))
+           (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_3))
+           (portRef I0 (instanceRef cpu_est_i_3))
+          ))
+          (net AS_000_INT (joined
+           (portRef Q (instanceRef AS_000_INT))
+           (portRef I0 (instanceRef AS_000_INT_i))
+           (portRef I0 (instanceRef AS_000_INT_0_n))
+          ))
+          (net (rename SM_AMIGA_5 "SM_AMIGA[5]") (joined
+           (portRef Q (instanceRef SM_AMIGA_5))
+           (portRef I1 (instanceRef DS_000_ENABLE_1_sqmuxa_0_a2_0_a3))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_5))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_m3_5__m))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m3_5__r))
+           (portRef I0 (instanceRef SM_AMIGA_i_5))
+          ))
+          (net AMIGA_BUS_ENABLE_DMA_LOW (joined
+           (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_LOW))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i))
+          ))
+          (net AS_030_D0 (joined
+           (portRef Q (instanceRef AS_030_D0))
+           (portRef I0 (instanceRef AS_030_D0_i))
+           (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2_i_1))
+          ))
+          (net nEXP_SPACE_D0 (joined
+           (portRef Q (instanceRef nEXP_SPACE_D0))
+           (portRef I0 (instanceRef nEXP_SPACE_D0_i))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0))
+           (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_i_a3_2))
+           (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_i))
+           (portRef OE (instanceRef DSACK1))
+          ))
+          (net AS_030_000_SYNC (joined
+           (portRef Q (instanceRef AS_030_000_SYNC))
+           (portRef I0 (instanceRef AS_030_000_SYNC_0_n))
+           (portRef I0 (instanceRef AS_030_000_SYNC_i))
+          ))
+          (net BGACK_030_INT_D (joined
+           (portRef Q (instanceRef BGACK_030_INT_D))
+           (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i_a2))
+          ))
+          (net AS_000_DMA (joined
+           (portRef Q (instanceRef AS_000_DMA))
+           (portRef I0 (instanceRef AS_000_DMA_0_n))
+           (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i_a3))
+           (portRef I0 (instanceRef AS_000_DMA_i))
+          ))
+          (net DS_000_DMA (joined
+           (portRef Q (instanceRef DS_000_DMA))
+           (portRef I0 (instanceRef DS_000_DMA_0_n))
+           (portRef I0 (instanceRef DS_000_DMA_i))
+          ))
+          (net (rename CYCLE_DMA_0 "CYCLE_DMA[0]") (joined
+           (portRef Q (instanceRef CYCLE_DMA_0))
+           (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_x2))
+           (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2))
+           (portRef I1 (instanceRef G_129))
+          ))
+          (net (rename CYCLE_DMA_1 "CYCLE_DMA[1]") (joined
+           (portRef Q (instanceRef CYCLE_DMA_1))
+           (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_x2))
+           (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2))
+          ))
+          (net (rename SIZE_DMA_0 "SIZE_DMA[0]") (joined
+           (portRef Q (instanceRef SIZE_DMA_0))
+           (portRef I0 (instanceRef un4_size))
+           (portRef I0 (instanceRef SIZE_DMA_i_0))
+           (portRef I0 (instanceRef SIZE_DMA_0_0__m))
+          ))
+          (net (rename SIZE_DMA_1 "SIZE_DMA[1]") (joined
+           (portRef Q (instanceRef SIZE_DMA_1))
+           (portRef I0 (instanceRef SIZE_DMA_i_1))
+           (portRef I0 (instanceRef un3_size))
+           (portRef I0 (instanceRef SIZE_DMA_0_1__m))
+          ))
+          (net VPA_D (joined
+           (portRef Q (instanceRef VPA_D))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3))
+           (portRef I0 (instanceRef VPA_D_i))
+          ))
+          (net UDS_000_INT (joined
+           (portRef Q (instanceRef UDS_000_INT))
+           (portRef I0 (instanceRef UDS_000_INT_i))
+           (portRef I0 (instanceRef UDS_000_INT_0_n))
+          ))
+          (net LDS_000_INT (joined
+           (portRef Q (instanceRef LDS_000_INT))
+           (portRef I0 (instanceRef LDS_000_INT_0_n))
+           (portRef I0 (instanceRef LDS_000_INT_i))
+          ))
+          (net CLK_OUT_PRE_D (joined
+           (portRef Q (instanceRef CLK_OUT_PRE_D))
+           (portRef I0 (instanceRef CLK_OUT_PRE_D_i))
+           (portRef D (instanceRef CLK_OUT_INT))
+          ))
+          (net DTACK_D0 (joined
+           (portRef Q (instanceRef DTACK_D0))
+           (portRef I0 (instanceRef DTACK_D0_i))
+          ))
+          (net RESET_OUT (joined
+           (portRef Q (instanceRef RESET_OUT))
+           (portRef I1 (instanceRef un1_as_000_0_i_a3))
+           (portRef I1 (instanceRef un2_rw_0_i_a2))
+           (portRef I0 (instanceRef RESET_OUT_i))
+          ))
+          (net CLK_OUT_PRE_50 (joined
+           (portRef Q (instanceRef CLK_OUT_PRE_50))
+           (portRef I0 (instanceRef CLK_OUT_PRE_50_i))
+           (portRef I1 (instanceRef CLK_OUT_PRE_25_0))
+           (portRef D (instanceRef CLK_OUT_EXP_INT))
+          ))
+          (net CLK_OUT_PRE_25 (joined
+           (portRef Q (instanceRef CLK_OUT_PRE_25))
+           (portRef I0 (instanceRef CLK_OUT_PRE_25_0))
+           (portRef D (instanceRef CLK_OUT_PRE_D))
+          ))
+          (net CLK_000_D1 (joined
+           (portRef Q (instanceRef CLK_000_D1))
+           (portRef I1 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_o3_i_o2_0))
+           (portRef I0 (instanceRef CLK_000_D1_i))
+          ))
+          (net CLK_000_D0 (joined
+           (portRef Q (instanceRef CLK_000_D0))
+           (portRef I0 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_i_0))
+           (portRef I0 (instanceRef CLK_000_D0_i))
+           (portRef I1 (instanceRef pos_clk_un6_bg_030_0_a2_i_1))
+           (portRef D (instanceRef CLK_000_D1))
+          ))
+          (net CLK_000_PE (joined
+           (portRef Q (instanceRef CLK_000_PE))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_3))
+           (portRef I1 (instanceRef pos_clk_un6_bgack_000_0_0_a2))
+           (portRef I0 (instanceRef CLK_000_PE_i))
+           (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_x2))
+           (portRef I0 (instanceRef G_129))
+           (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0_0_a3))
+           (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_1))
+          ))
+          (net CLK_OUT_EXP_INT (joined
+           (portRef Q (instanceRef CLK_OUT_EXP_INT))
+           (portRef I0 (instanceRef CLK_OUT_EXP_INT_i))
+          ))
+          (net (rename CLK_000_P_SYNC_9 "CLK_000_P_SYNC[9]") (joined
+           (portRef Q (instanceRef CLK_000_P_SYNC_9))
+           (portRef D (instanceRef CLK_000_PE))
+          ))
+          (net CLK_000_NE (joined
+           (portRef Q (instanceRef CLK_000_NE))
+           (portRef I0 (instanceRef RESET_OUT_2_i_0_o2))
+           (portRef I0 (instanceRef RST_DLY_e2_i_0_a2))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0))
+           (portRef I0 (instanceRef CLK_000_NE_i))
+           (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0_1))
+           (portRef D (instanceRef CLK_000_NE_D0))
+          ))
+          (net (rename CLK_000_N_SYNC_11 "CLK_000_N_SYNC[11]") (joined
+           (portRef Q (instanceRef CLK_000_N_SYNC_11))
+           (portRef D (instanceRef CLK_000_NE))
+          ))
+          (net (rename IPL_D0_0 "IPL_D0[0]") (joined
+           (portRef Q (instanceRef IPL_D0_0))
+           (portRef I0 (instanceRef G_134))
+          ))
+          (net (rename IPL_D0_1 "IPL_D0[1]") (joined
+           (portRef Q (instanceRef IPL_D0_1))
+           (portRef I0 (instanceRef G_135))
+          ))
+          (net (rename IPL_D0_2 "IPL_D0[2]") (joined
+           (portRef Q (instanceRef IPL_D0_2))
+           (portRef I0 (instanceRef G_136))
+          ))
+          (net CLK_000_NE_D0 (joined
+           (portRef Q (instanceRef CLK_000_NE_D0))
+           (portRef I1 (instanceRef cpu_est_0_1__m))
+           (portRef I0 (instanceRef cpu_est_0_1__r))
+           (portRef I1 (instanceRef cpu_est_0_3__m))
+           (portRef I0 (instanceRef cpu_est_0_3__r))
+           (portRef I1 (instanceRef cpu_est_0_2__m))
+           (portRef I0 (instanceRef cpu_est_0_2__r))
+           (portRef I0 (instanceRef cpu_est_0_0_x2_0_x2_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_1_2))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_1_3))
+          ))
+          (net (rename SM_AMIGA_0 "SM_AMIGA[0]") (joined
+           (portRef Q (instanceRef SM_AMIGA_0))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0))
+           (portRef I0 (instanceRef SM_AMIGA_i_0))
+           (portRef I1 (instanceRef un1_SM_AMIGA_3_i_0_0_a3))
+          ))
+          (net AMIGA_BUS_ENABLE_DMA_HIGH (joined
+           (portRef Q (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_i))
+          ))
+          (net DSACK1_INT (joined
+           (portRef Q (instanceRef DSACK1_INT))
+           (portRef I0 (instanceRef DSACK1_INT_0_n))
+           (portRef I0 (instanceRef DSACK1))
+          ))
+          (net (rename pos_clk_ipl "pos_clk.ipl") (joined
+           (portRef O (instanceRef G_137))
+           (portRef I1 (instanceRef IPL_030_0_0__m))
+           (portRef I0 (instanceRef IPL_030_0_0__r))
+           (portRef I1 (instanceRef IPL_030_0_2__m))
+           (portRef I0 (instanceRef IPL_030_0_2__r))
+           (portRef I1 (instanceRef IPL_030_0_1__m))
+           (portRef I0 (instanceRef IPL_030_0_1__r))
+          ))
+          (net (rename SM_AMIGA_4 "SM_AMIGA[4]") (joined
+           (portRef Q (instanceRef SM_AMIGA_4))
+           (portRef I1 (instanceRef un1_SM_AMIGA_5_0_o2_3_a2))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_3))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_4))
+           (portRef I0 (instanceRef SM_AMIGA_i_4))
+          ))
+          (net DS_000_ENABLE (joined
+           (portRef Q (instanceRef DS_000_ENABLE))
+           (portRef I0 (instanceRef DS_000_ENABLE_0_m))
+           (portRef I0 (instanceRef un4_lds_000))
+           (portRef I0 (instanceRef un4_uds_000))
+          ))
+          (net (rename RST_DLY_0 "RST_DLY[0]") (joined
+           (portRef Q (instanceRef RST_DLY_0))
+           (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_0))
+           (portRef I0 (instanceRef RST_DLY_i_0))
+           (portRef I1 (instanceRef RST_DLY_e0_i_0_a3))
+          ))
+          (net (rename RST_DLY_1 "RST_DLY[1]") (joined
+           (portRef Q (instanceRef RST_DLY_1))
+           (portRef I1 (instanceRef RST_DLY_e2_i_0_o2_0))
+           (portRef I0 (instanceRef RST_DLY_i_1))
+          ))
+          (net (rename RST_DLY_2 "RST_DLY[2]") (joined
+           (portRef Q (instanceRef RST_DLY_2))
+           (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_0_o2))
+           (portRef I0 (instanceRef RST_DLY_i_2))
+          ))
+          (net (rename pos_clk_un8_bg_030 "pos_clk.un8_bg_030") (joined
+           (portRef O (instanceRef pos_clk_un8_bg_030_i))
+           (portRef I1 (instanceRef BG_000_0_m))
+           (portRef I0 (instanceRef BG_000_0_r))
+          ))
+          (net (rename CLK_000_P_SYNC_0 "CLK_000_P_SYNC[0]") (joined
+           (portRef Q (instanceRef CLK_000_P_SYNC_0))
+           (portRef D (instanceRef CLK_000_P_SYNC_1))
+          ))
+          (net (rename CLK_000_P_SYNC_1 "CLK_000_P_SYNC[1]") (joined
+           (portRef Q (instanceRef CLK_000_P_SYNC_1))
+           (portRef D (instanceRef CLK_000_P_SYNC_2))
+          ))
+          (net (rename CLK_000_P_SYNC_2 "CLK_000_P_SYNC[2]") (joined
+           (portRef Q (instanceRef CLK_000_P_SYNC_2))
+           (portRef D (instanceRef CLK_000_P_SYNC_3))
+          ))
+          (net (rename CLK_000_P_SYNC_3 "CLK_000_P_SYNC[3]") (joined
+           (portRef Q (instanceRef CLK_000_P_SYNC_3))
+           (portRef D (instanceRef CLK_000_P_SYNC_4))
+          ))
+          (net (rename CLK_000_P_SYNC_4 "CLK_000_P_SYNC[4]") (joined
+           (portRef Q (instanceRef CLK_000_P_SYNC_4))
+           (portRef D (instanceRef CLK_000_P_SYNC_5))
+          ))
+          (net (rename CLK_000_P_SYNC_5 "CLK_000_P_SYNC[5]") (joined
+           (portRef Q (instanceRef CLK_000_P_SYNC_5))
+           (portRef D (instanceRef CLK_000_P_SYNC_6))
+          ))
+          (net (rename CLK_000_P_SYNC_6 "CLK_000_P_SYNC[6]") (joined
+           (portRef Q (instanceRef CLK_000_P_SYNC_6))
+           (portRef D (instanceRef CLK_000_P_SYNC_7))
+          ))
+          (net (rename CLK_000_P_SYNC_7 "CLK_000_P_SYNC[7]") (joined
+           (portRef Q (instanceRef CLK_000_P_SYNC_7))
+           (portRef D (instanceRef CLK_000_P_SYNC_8))
+          ))
+          (net (rename CLK_000_P_SYNC_8 "CLK_000_P_SYNC[8]") (joined
+           (portRef Q (instanceRef CLK_000_P_SYNC_8))
+           (portRef D (instanceRef CLK_000_P_SYNC_9))
+          ))
+          (net (rename CLK_000_N_SYNC_0 "CLK_000_N_SYNC[0]") (joined
+           (portRef Q (instanceRef CLK_000_N_SYNC_0))
+           (portRef D (instanceRef CLK_000_N_SYNC_1))
+          ))
+          (net (rename CLK_000_N_SYNC_1 "CLK_000_N_SYNC[1]") (joined
+           (portRef Q (instanceRef CLK_000_N_SYNC_1))
+           (portRef D (instanceRef CLK_000_N_SYNC_2))
+          ))
+          (net (rename CLK_000_N_SYNC_2 "CLK_000_N_SYNC[2]") (joined
+           (portRef Q (instanceRef CLK_000_N_SYNC_2))
+           (portRef D (instanceRef CLK_000_N_SYNC_3))
+          ))
+          (net (rename CLK_000_N_SYNC_3 "CLK_000_N_SYNC[3]") (joined
+           (portRef Q (instanceRef CLK_000_N_SYNC_3))
+           (portRef D (instanceRef CLK_000_N_SYNC_4))
+          ))
+          (net (rename CLK_000_N_SYNC_4 "CLK_000_N_SYNC[4]") (joined
+           (portRef Q (instanceRef CLK_000_N_SYNC_4))
+           (portRef D (instanceRef CLK_000_N_SYNC_5))
+          ))
+          (net (rename CLK_000_N_SYNC_5 "CLK_000_N_SYNC[5]") (joined
+           (portRef Q (instanceRef CLK_000_N_SYNC_5))
+           (portRef D (instanceRef CLK_000_N_SYNC_6))
+          ))
+          (net (rename CLK_000_N_SYNC_6 "CLK_000_N_SYNC[6]") (joined
+           (portRef Q (instanceRef CLK_000_N_SYNC_6))
+           (portRef D (instanceRef CLK_000_N_SYNC_7))
+          ))
+          (net (rename CLK_000_N_SYNC_7 "CLK_000_N_SYNC[7]") (joined
+           (portRef Q (instanceRef CLK_000_N_SYNC_7))
+           (portRef D (instanceRef CLK_000_N_SYNC_8))
+          ))
+          (net (rename CLK_000_N_SYNC_8 "CLK_000_N_SYNC[8]") (joined
+           (portRef Q (instanceRef CLK_000_N_SYNC_8))
+           (portRef D (instanceRef CLK_000_N_SYNC_9))
+          ))
+          (net (rename CLK_000_N_SYNC_9 "CLK_000_N_SYNC[9]") (joined
+           (portRef Q (instanceRef CLK_000_N_SYNC_9))
+           (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2))
+           (portRef D (instanceRef CLK_000_N_SYNC_10))
+          ))
+          (net (rename CLK_000_N_SYNC_10 "CLK_000_N_SYNC[10]") (joined
+           (portRef Q (instanceRef CLK_000_N_SYNC_10))
+           (portRef I0 (instanceRef CLK_000_N_SYNC_i_10))
+           (portRef D (instanceRef CLK_000_N_SYNC_11))
+          ))
+          (net RW_000_INT (joined
+           (portRef Q (instanceRef RW_000_INT))
+           (portRef I0 (instanceRef RW_000_INT_0_n))
+           (portRef I0 (instanceRef RW_000))
+          ))
+          (net RW_000_DMA (joined
+           (portRef Q (instanceRef RW_000_DMA))
+           (portRef I0 (instanceRef RW_000_DMA_0_m))
+           (portRef I0 (instanceRef RW))
+          ))
+          (net (rename pos_clk_un7_clk_000_pe "pos_clk.un7_clk_000_pe") (joined
+           (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0_i))
+           (portRef I1 (instanceRef VMA_INT_0_m))
+           (portRef I0 (instanceRef VMA_INT_0_r))
+          ))
+          (net A0_DMA (joined
+           (portRef Q (instanceRef A0_DMA))
+           (portRef I0 (instanceRef A0_DMA_0_m))
+           (portRef I0 (instanceRef A0))
+          ))
+          (net (rename SM_AMIGA_6 "SM_AMIGA[6]") (joined
+           (portRef Q (instanceRef SM_AMIGA_6))
+           (portRef I1 (instanceRef LDS_000_INT_0_m))
+           (portRef I0 (instanceRef LDS_000_INT_0_r))
+           (portRef I1 (instanceRef UDS_000_INT_0_m))
+           (portRef I0 (instanceRef UDS_000_INT_0_r))
+           (portRef I0 (instanceRef SM_AMIGA_i_6))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a3_6))
+          ))
+          (net DS_000_ENABLE_1_sqmuxa (joined
+           (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_0_a2_0_a3))
+           (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_i))
+          ))
+          (net CLK_030_H (joined
+           (portRef Q (instanceRef CLK_030_H))
+           (portRef I0 (instanceRef CLK_030_H_i))
+           (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_a3))
+          ))
+          (net (rename SM_AMIGA_1 "SM_AMIGA[1]") (joined
+           (portRef Q (instanceRef SM_AMIGA_1))
+           (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a3))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_m3_1__m))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m3_1__r))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_1))
+           (portRef I0 (instanceRef SM_AMIGA_i_1))
+          ))
+          (net (rename SM_AMIGA_3 "SM_AMIGA[3]") (joined
+           (portRef Q (instanceRef SM_AMIGA_3))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3))
+           (portRef I0 (instanceRef SM_AMIGA_i_3))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_2_2))
+          ))
+          (net (rename SM_AMIGA_2 "SM_AMIGA[2]") (joined
+           (portRef Q (instanceRef SM_AMIGA_2))
+           (portRef I0 (instanceRef SM_AMIGA_i_2))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a3_2))
+          ))
+          (net (rename pos_clk_un3_as_030_d0 "pos_clk.un3_as_030_d0") (joined
+           (portRef O (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o3_i))
+           (portRef I0 (instanceRef AS_030_000_SYNC_0_m))
+          ))
+          (net DS_000_ENABLE_1_sqmuxa_1 (joined
+           (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_1_a2_0_a3))
+           (portRef I1 (instanceRef DS_000_ENABLE_0_m))
+           (portRef I0 (instanceRef DS_000_ENABLE_0_r))
+          ))
+          (net N_4 (joined
+           (portRef O (instanceRef DSACK1_INT_0_p))
+           (portRef I0 (instanceRef N_4_i))
+          ))
+          (net N_6 (joined
+           (portRef O (instanceRef DS_000_ENABLE_0_p))
+           (portRef I0 (instanceRef DS_000_ENABLE_1))
+          ))
+          (net N_11 (joined
+           (portRef O (instanceRef SIZE_DMA_0_0__p))
+           (portRef D (instanceRef SIZE_DMA_0))
+          ))
+          (net N_12 (joined
+           (portRef O (instanceRef SIZE_DMA_0_1__p))
+           (portRef D (instanceRef SIZE_DMA_1))
+          ))
+          (net N_14 (joined
+           (portRef O (instanceRef cpu_est_0_1__p))
+           (portRef D (instanceRef cpu_est_1))
+          ))
+          (net N_15 (joined
+           (portRef O (instanceRef cpu_est_0_2__p))
+           (portRef D (instanceRef cpu_est_2))
+          ))
+          (net N_16 (joined
+           (portRef O (instanceRef cpu_est_0_3__p))
+           (portRef D (instanceRef cpu_est_3))
+          ))
+          (net N_17 (joined
+           (portRef O (instanceRef LDS_000_INT_0_p))
+           (portRef I0 (instanceRef N_17_i))
+          ))
+          (net N_18 (joined
+           (portRef O (instanceRef RW_000_INT_0_p))
+           (portRef I0 (instanceRef N_18_i))
+          ))
+          (net N_21 (joined
+           (portRef O (instanceRef UDS_000_INT_0_p))
+           (portRef I0 (instanceRef N_21_i))
+          ))
+          (net N_22 (joined
+           (portRef O (instanceRef VMA_INT_0_p))
+           (portRef I0 (instanceRef N_22_i))
+          ))
+          (net N_26 (joined
+           (portRef O (instanceRef BG_000_0_p))
+           (portRef I0 (instanceRef N_26_i))
+          ))
+          (net N_27 (joined
+           (portRef O (instanceRef IPL_030_0_0__p))
+           (portRef I0 (instanceRef N_27_i))
+          ))
+          (net N_30 (joined
+           (portRef O (instanceRef CLK_OUT_PRE_25_0))
+           (portRef D (instanceRef CLK_OUT_PRE_25))
+          ))
+          (net N_31 (joined
+           (portRef O (instanceRef IPL_030_1_i_0))
+           (portRef D (instanceRef IPL_030DFF_0))
+          ))
+          (net N_32 (joined
+           (portRef O (instanceRef IPL_030_1_i_1))
+           (portRef D (instanceRef IPL_030DFF_1))
+          ))
+          (net N_33 (joined
+           (portRef O (instanceRef IPL_030_1_i_2))
+           (portRef D (instanceRef IPL_030DFF_2))
+          ))
+          (net N_34 (joined
+           (portRef O (instanceRef BG_000_1_i))
+           (portRef D (instanceRef BG_000DFF))
+          ))
+          (net N_35 (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i))
+           (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH))
+          ))
+          (net N_36 (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i))
+           (portRef D (instanceRef AMIGA_BUS_ENABLE_DMA_LOW))
+          ))
+          (net N_38 (joined
+           (portRef O (instanceRef VMA_INT_1_i))
+           (portRef D (instanceRef VMA_INT))
+          ))
+          (net N_39 (joined
+           (portRef O (instanceRef UDS_000_INT_1_i))
+           (portRef D (instanceRef UDS_000_INT))
+          ))
+          (net N_40 (joined
+           (portRef O (instanceRef A0_DMA_1_i))
+           (portRef D (instanceRef A0_DMA))
+          ))
+          (net N_41 (joined
+           (portRef O (instanceRef RW_000_DMA_2_i))
+           (portRef D (instanceRef RW_000_DMA))
+          ))
+          (net N_42 (joined
+           (portRef O (instanceRef RW_000_INT_2_i))
+           (portRef D (instanceRef RW_000_INT))
+          ))
+          (net N_43 (joined
+           (portRef O (instanceRef LDS_000_INT_1_i))
+           (portRef D (instanceRef LDS_000_INT))
+          ))
+          (net N_44 (joined
+           (portRef O (instanceRef BGACK_030_INT_1_i))
+           (portRef D (instanceRef BGACK_030_INT))
+          ))
+          (net N_46 (joined
+           (portRef O (instanceRef AS_000_DMA_1_i))
+           (portRef D (instanceRef AS_000_DMA))
+          ))
+          (net N_47 (joined
+           (portRef O (instanceRef AS_030_000_SYNC_1_i))
+           (portRef D (instanceRef AS_030_000_SYNC))
+          ))
+          (net N_48 (joined
+           (portRef O (instanceRef AS_000_INT_1_i))
+           (portRef D (instanceRef AS_000_INT))
+          ))
+          (net N_49 (joined
+           (portRef O (instanceRef DSACK1_INT_1_i))
+           (portRef D (instanceRef DSACK1_INT))
+          ))
+          (net N_50 (joined
+           (portRef O (instanceRef DS_000_DMA_1_i))
+           (portRef D (instanceRef DS_000_DMA))
+          ))
+          (net N_52 (joined
+           (portRef O (instanceRef IPL_D0_0_i_0))
+           (portRef D (instanceRef IPL_D0_0))
+          ))
+          (net N_53 (joined
+           (portRef O (instanceRef IPL_D0_0_i_1))
+           (portRef D (instanceRef IPL_D0_1))
+          ))
+          (net N_54 (joined
+           (portRef O (instanceRef IPL_D0_0_i_2))
+           (portRef D (instanceRef IPL_D0_2))
+          ))
+          (net N_55 (joined
+           (portRef O (instanceRef nEXP_SPACE_D0_0_i))
+           (portRef D (instanceRef nEXP_SPACE_D0))
+          ))
+          (net N_56 (joined
+           (portRef O (instanceRef VPA_D_0_i))
+           (portRef D (instanceRef VPA_D))
+          ))
+          (net N_57 (joined
+           (portRef O (instanceRef DTACK_D0_0_i))
+           (portRef D (instanceRef DTACK_D0))
+          ))
+          (net N_60 (joined
+           (portRef O (instanceRef DS_000_ENABLE_1))
+           (portRef D (instanceRef DS_000_ENABLE))
+          ))
+          (net (rename SM_AMIGA_i_7 "SM_AMIGA_i[7]") (joined
+           (portRef Q (instanceRef SM_AMIGA_i_7))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_o2_6))
+           (portRef I0 (instanceRef SM_AMIGA_i_i_7))
+           (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__m))
+           (portRef I1 (instanceRef un1_SM_AMIGA_5_0_o2_3_o3_2))
+           (portRef I1 (instanceRef un1_SM_AMIGA_3_i_0_0))
+          ))
+          (net N_124 (joined
+           (portRef O (instanceRef un1_SM_AMIGA_3_i_0_0_i))
+           (portRef I1 (instanceRef RW_000_INT_0_m))
+           (portRef I0 (instanceRef RW_000_INT_0_r))
+          ))
+          (net (rename cpu_est_2_1 "cpu_est_2[1]") (joined
+           (portRef O (instanceRef cpu_est_2_0_0_0_i_1))
+           (portRef I0 (instanceRef cpu_est_0_1__m))
+          ))
+          (net (rename cpu_est_2_2 "cpu_est_2[2]") (joined
+           (portRef O (instanceRef cpu_est_2_0_0_0_i_2))
+           (portRef I0 (instanceRef cpu_est_0_2__m))
+          ))
+          (net (rename cpu_est_2_3 "cpu_est_2[3]") (joined
+           (portRef O (instanceRef cpu_est_2_0_0_0_i_3))
+           (portRef I0 (instanceRef cpu_est_0_3__m))
+          ))
+          (net N_213 (joined
+           (portRef O (instanceRef G_134))
+           (portRef I0 (instanceRef N_213_i))
+          ))
+          (net N_214 (joined
+           (portRef O (instanceRef G_135))
+           (portRef I0 (instanceRef N_214_i))
+          ))
+          (net N_215 (joined
+           (portRef O (instanceRef G_136))
+           (portRef I0 (instanceRef N_215_i))
+          ))
+          (net N_269 (joined
+           (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_i))
+           (portRef I1 (instanceRef DSACK1_INT_0_m))
+           (portRef I0 (instanceRef DSACK1_INT_0_r))
+          ))
+          (net N_61 (joined
+           (portRef O (instanceRef un8_ciin_i_0_0_i))
+           (portRef OE (instanceRef CIIN))
+          ))
+          (net N_69 (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_0_0_o3_i))
+           (portRef D (instanceRef BGACK_030_INT_D))
+          ))
+          (net N_98 (joined
+           (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_a3))
+           (portRef I0 (instanceRef N_98_i))
+          ))
+          (net N_282 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_i_6))
+           (portRef D (instanceRef SM_AMIGA_6))
+          ))
+          (net N_283 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_i_2))
+           (portRef D (instanceRef SM_AMIGA_2))
+          ))
+          (net N_355 (joined
+           (portRef O (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_i))
+           (portRef I1 (instanceRef DS_000_DMA_0_m))
+           (portRef I0 (instanceRef DS_000_DMA_0_r))
+          ))
+          (net N_358 (joined
+           (portRef O (instanceRef AS_030_D0_0_i_a2_i_i))
+           (portRef D (instanceRef AS_030_D0))
+          ))
+          (net N_128 (joined
+           (portRef O (instanceRef pos_clk_un6_bg_030_0_a2_i_i))
+           (portRef I1 (instanceRef pos_clk_un8_bg_030))
+          ))
+          (net N_137 (joined
+           (portRef O (instanceRef un6_as_030_i_0_i))
+           (portRef I0 (instanceRef AS_030))
+          ))
+          (net N_145 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_3_i_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_o2_2))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_o2_6))
+          ))
+          (net N_148 (joined
+           (portRef O (instanceRef RST_DLY_e2_i_0_o2_0_i))
+           (portRef I0 (instanceRef RST_DLY_e2_i_0_a3_1))
+          ))
+          (net N_150 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_i_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_2_1_0))
+          ))
+          (net N_152 (joined
+           (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_0_i))
+           (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2))
+          ))
+          (net N_154 (joined
+           (portRef O (instanceRef cpu_est_2_0_0_0_o2_i_3))
+           (portRef I0 (instanceRef cpu_est_2_0_0_0_3))
+          ))
+          (net N_156 (joined
+           (portRef O (instanceRef cpu_est_2_0_0_0_o2_i_2))
+           (portRef I0 (instanceRef cpu_est_2_0_0_0_a3_2))
+          ))
+          (net N_159 (joined
+           (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_i))
+           (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_a3))
+          ))
+          (net N_161 (joined
+           (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3_i))
+           (portRef I0 (instanceRef AS_000_DMA_0_m))
+          ))
+          (net N_165 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_i_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_1_1_0))
+          ))
+          (net N_168 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_i_3))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_1_2))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_1_3))
+          ))
+          (net N_171 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_i_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0_1_0))
+          ))
+          (net N_174 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_o2_i_6))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a3_1_6))
+          ))
+          (net N_175 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_o2_i_2))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a3_1_2))
+          ))
+          (net N_178 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_4))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_4))
+          ))
+          (net N_181 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_i_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0))
+          ))
+          (net N_183 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_3))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_3))
+          ))
+          (net N_188 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_m3_5__p))
+           (portRef I0 (instanceRef N_188_i))
+          ))
+          (net N_190 (joined
+           (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__p))
+           (portRef I0 (instanceRef N_190_i))
+          ))
+          (net N_193 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_m3_1__p))
+           (portRef I0 (instanceRef N_193_i))
+          ))
+          (net N_195 (joined
+           (portRef O (instanceRef RST_DLY_e2_i_0_a3))
+           (portRef I0 (instanceRef N_195_i))
+          ))
+          (net N_200 (joined
+           (portRef O (instanceRef RST_DLY_e1_i_0_a3_0))
+           (portRef I0 (instanceRef N_200_i))
+          ))
+          (net N_205 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a3_5))
+           (portRef I0 (instanceRef N_205_i))
+          ))
+          (net N_206 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0))
+           (portRef I0 (instanceRef N_206_i))
+          ))
+          (net N_207 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0_0))
+           (portRef I0 (instanceRef N_207_i))
+          ))
+          (net N_208 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a3_1_0))
+           (portRef I0 (instanceRef N_208_i))
+          ))
+          (net N_210 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a3_2_0))
+           (portRef I0 (instanceRef N_210_i))
+          ))
+          (net N_211 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a3_3))
+           (portRef I0 (instanceRef N_211_i))
+          ))
+          (net N_212 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_3))
+           (portRef I0 (instanceRef N_212_i))
+          ))
+          (net N_373 (joined
+           (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0_a3))
+           (portRef I0 (instanceRef N_373_i))
+          ))
+          (net N_375 (joined
+           (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0))
+           (portRef I0 (instanceRef N_375_i))
+          ))
+          (net N_216 (joined
+           (portRef O (instanceRef cpu_est_2_0_0_0_a3_1))
+           (portRef I0 (instanceRef N_216_i))
+          ))
+          (net N_218 (joined
+           (portRef O (instanceRef cpu_est_2_0_0_a3_0_1))
+           (portRef I0 (instanceRef N_218_i))
+          ))
+          (net N_219 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a3_2))
+           (portRef I0 (instanceRef N_219_i))
+          ))
+          (net N_220 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_2))
+           (portRef I0 (instanceRef N_220_i))
+          ))
+          (net N_221 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a3_4))
+           (portRef I0 (instanceRef N_221_i))
+          ))
+          (net N_222 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_4))
+           (portRef I0 (instanceRef N_222_i))
+          ))
+          (net N_224 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a3_6))
+           (portRef I0 (instanceRef N_224_i))
+          ))
+          (net N_225 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_6))
+           (portRef I0 (instanceRef N_225_i))
+          ))
+          (net N_226 (joined
+           (portRef O (instanceRef CLK_030_H_2_0_a2_i_a3))
+           (portRef I0 (instanceRef N_226_i))
+          ))
+          (net N_228 (joined
+           (portRef O (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_a3))
+           (portRef I0 (instanceRef N_228_i))
+          ))
+          (net N_230 (joined
+           (portRef O (instanceRef un1_as_000_0_i_a3))
+           (portRef OE (instanceRef AS_000))
+           (portRef OE (instanceRef LDS_000))
+           (portRef OE (instanceRef RW_000))
+           (portRef OE (instanceRef UDS_000))
+          ))
+          (net N_231 (joined
+           (portRef O (instanceRef un3_as_030_0_i_a3))
+           (portRef OE (instanceRef A0))
+           (portRef OE (instanceRef AS_030))
+           (portRef OE (instanceRef DS_030))
+          ))
+          (net N_240 (joined
+           (portRef O (instanceRef un1_SM_AMIGA_3_i_0_0_a3))
+           (portRef I0 (instanceRef N_240_i))
+          ))
+          (net N_241 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a3_1))
+           (portRef I0 (instanceRef N_241_i))
+          ))
+          (net N_277 (joined
+           (portRef O (instanceRef cpu_est_2_0_0_0_a3_2))
+           (portRef I0 (instanceRef N_277_i))
+          ))
+          (net N_278 (joined
+           (portRef O (instanceRef cpu_est_2_0_0_0_a3_3))
+           (portRef I0 (instanceRef N_278_i))
+          ))
+          (net N_279 (joined
+           (portRef O (instanceRef un5_e_0_0_a3))
+           (portRef I0 (instanceRef N_279_i))
+          ))
+          (net N_280 (joined
+           (portRef O (instanceRef un5_e_0_0_a3_0))
+           (portRef I0 (instanceRef N_280_i))
+          ))
+          (net N_281 (joined
+           (portRef O (instanceRef RST_DLY_e0_i_0_a3))
+           (portRef I0 (instanceRef N_281_i))
+          ))
+          (net N_302 (joined
+           (portRef O (instanceRef RST_DLY_e0_i_0_a3_0))
+           (portRef I0 (instanceRef N_302_i))
+          ))
+          (net N_313 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_3))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0))
+           (portRef I0 (instanceRef N_313_i))
+          ))
+          (net N_318 (joined
+           (portRef O (instanceRef un1_SM_AMIGA_5_0_o2_3_a2))
+           (portRef I0 (instanceRef N_318_i))
+          ))
+          (net N_321 (joined
+           (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_a2))
+           (portRef I0 (instanceRef N_321_i))
+          ))
+          (net N_324 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3))
+           (portRef I0 (instanceRef N_324_i))
+          ))
+          (net N_326 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3))
+           (portRef I0 (instanceRef N_326_i))
+          ))
+          (net N_329 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a2_0))
+           (portRef I0 (instanceRef N_329_i))
+          ))
+          (net N_332 (joined
+           (portRef O (instanceRef un2_rw_0_i_a2))
+           (portRef I0 (instanceRef un3_as_030_0_i_a3))
+           (portRef OE (instanceRef RW))
+          ))
+          (net N_348 (joined
+           (portRef O (instanceRef cpu_est_2_0_0_0_a2_2))
+           (portRef I0 (instanceRef N_348_i))
+           (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0_1))
+          ))
+          (net N_189_i (joined
+           (portRef O (instanceRef cpu_est_0_0_x2_0_x2_0))
+           (portRef D (instanceRef cpu_est_0))
+          ))
+          (net N_191_i (joined
+           (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_x2))
+           (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_1))
+          ))
+          (net N_192_i (joined
+           (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_x2))
+           (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_1))
+          ))
+          (net N_235 (joined
+           (portRef O (instanceRef RESET_OUT_2_i_0_a3))
+           (portRef I0 (instanceRef N_235_i))
+          ))
+          (net N_196 (joined
+           (portRef O (instanceRef RST_DLY_e2_i_0_a3_0))
+           (portRef I0 (instanceRef N_196_i))
+          ))
+          (net N_143 (joined
+           (portRef O (instanceRef RST_DLY_e2_i_0_o2_i))
+           (portRef I0 (instanceRef RST_DLY_e0_i_0_a3))
+          ))
+          (net N_158 (joined
+           (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_143_0_o2_i))
+           (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_0))
+           (portRef I1 (instanceRef RST_DLY_e2_i_0_a2))
+          ))
+          (net N_198 (joined
+           (portRef O (instanceRef RST_DLY_e2_i_0_a3_2))
+           (portRef I0 (instanceRef N_198_i))
+          ))
+          (net N_199 (joined
+           (portRef O (instanceRef RST_DLY_e1_i_0_a3))
+           (portRef I0 (instanceRef N_199_i))
+          ))
+          (net N_307 (joined
+           (portRef O (instanceRef RST_DLY_e2_i_0_a2))
+           (portRef I1 (instanceRef RST_DLY_e1_i_0_a3))
+           (portRef I0 (instanceRef N_307_i))
+          ))
+          (net N_201 (joined
+           (portRef O (instanceRef RST_DLY_e1_i_0_a3_1))
+           (portRef I0 (instanceRef N_201_i))
+          ))
+          (net N_182 (joined
+           (portRef O (instanceRef RESET_OUT_2_i_0_o2_i))
+           (portRef I0 (instanceRef RESET_OUT_2_i_0_a3))
+          ))
+          (net N_243_2 (joined
+           (portRef O (instanceRef RST_DLY_e2_i_0_2_i))
+           (portRef I1 (instanceRef RST_DLY_e2_i_0_a3_0))
+          ))
+          (net N_8 (joined
+           (portRef O (instanceRef AS_000_DMA_0_p))
+           (portRef I0 (instanceRef N_8_i))
+          ))
+          (net N_356 (joined
+           (portRef O (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i_i))
+           (portRef I1 (instanceRef AS_000_DMA_0_m))
+           (portRef I0 (instanceRef AS_000_DMA_0_r))
+          ))
+          (net N_10 (joined
+           (portRef O (instanceRef BGACK_030_INT_0_p))
+           (portRef I0 (instanceRef N_10_i))
+          ))
+          (net (rename pos_clk_un6_bgack_000 "pos_clk.un6_bgack_000") (joined
+           (portRef O (instanceRef pos_clk_un6_bgack_000_0_0_i))
+           (portRef I1 (instanceRef BGACK_030_INT_0_m))
+           (portRef I0 (instanceRef BGACK_030_INT_0_r))
+          ))
+          (net N_19 (joined
+           (portRef O (instanceRef RW_000_DMA_0_p))
+           (portRef I0 (instanceRef N_19_i))
+          ))
+          (net N_352 (joined
+           (portRef O (instanceRef un14_amiga_bus_data_dir_0_a2_i_i))
+           (portRef I0 (instanceRef RW_000_DMA_0_n))
+          ))
+          (net N_327 (joined
+           (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_o2_i_a2))
+           (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r))
+           (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r))
+           (portRef I1 (instanceRef A0_DMA_0_m))
+           (portRef I0 (instanceRef A0_DMA_0_r))
+           (portRef I1 (instanceRef RW_000_DMA_0_m))
+           (portRef I0 (instanceRef RW_000_DMA_0_r))
+           (portRef I0 (instanceRef SIZE_DMA_3_sqmuxa_i_i_a3))
+           (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_i_a3_1))
+          ))
+          (net N_20 (joined
+           (portRef O (instanceRef A0_DMA_0_p))
+           (portRef I0 (instanceRef N_20_i))
+          ))
+          (net (rename pos_clk_A0_DMA_3 "pos_clk.A0_DMA_3") (joined
+           (portRef O (instanceRef pos_clk_A0_DMA_3_0_a2_0_a3))
+           (portRef I0 (instanceRef A0_DMA_0_n))
+          ))
+          (net N_24 (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p))
+           (portRef I0 (instanceRef N_24_i))
+          ))
+          (net N_113 (joined
+           (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3))
+           (portRef I0 (instanceRef N_113_i))
+          ))
+          (net N_25 (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p))
+           (portRef I0 (instanceRef N_25_i))
+          ))
+          (net N_114 (joined
+           (portRef O (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3))
+           (portRef I0 (instanceRef N_114_i))
+          ))
+          (net (rename pos_clk_SIZE_DMA_6_0 "pos_clk.SIZE_DMA_6[0]") (joined
+           (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_0))
+           (portRef I0 (instanceRef SIZE_DMA_0_0__n))
+          ))
+          (net N_232 (joined
+           (portRef O (instanceRef SIZE_DMA_3_sqmuxa_i_i_a3))
+           (portRef I1 (instanceRef SIZE_DMA_0_1__m))
+           (portRef I0 (instanceRef SIZE_DMA_0_1__r))
+           (portRef I1 (instanceRef SIZE_DMA_0_0__m))
+           (portRef I0 (instanceRef SIZE_DMA_0_0__r))
+          ))
+          (net (rename pos_clk_SIZE_DMA_6_1 "pos_clk.SIZE_DMA_6[1]") (joined
+           (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_1))
+           (portRef I0 (instanceRef SIZE_DMA_0_1__n))
+          ))
+          (net N_410 (joined
+           (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1))
+           (portRef I0 (instanceRef N_410_i))
+           (portRef I1 (instanceRef un22_berr_0_a2_0_a3_1))
+          ))
+          (net N_185 (joined
+           (portRef O (instanceRef CLK_030_H_2_0_a2_i_o2_i))
+           (portRef I1 (instanceRef CLK_030_H_2_0_a2_i_a3))
+          ))
+          (net N_236 (joined
+           (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3))
+           (portRef I0 (instanceRef N_236_i))
+          ))
+          (net N_238 (joined
+           (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_0))
+           (portRef I0 (instanceRef N_238_i))
+          ))
+          (net N_173 (joined
+           (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_i_0))
+           (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_0))
+          ))
+          (net N_239 (joined
+           (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_1))
+           (portRef I0 (instanceRef N_239_i))
+          ))
+          (net N_331 (joined
+           (portRef O (instanceRef pos_clk_un6_bgack_000_0_0_a2))
+           (portRef I0 (instanceRef N_331_i))
+          ))
+          (net N_237 (joined
+           (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0))
+           (portRef I0 (instanceRef N_237_i))
+          ))
+          (net un22_berr_1 (joined
+           (portRef O (instanceRef un22_berr_0_a2_0_a3_1))
+           (portRef I0 (instanceRef un22_berr_0_a2_0_a3_1_0))
+           (portRef I1 (instanceRef un21_fpu_cs_0_a2_0_a3))
+          ))
+          (net N_233 (joined
+           (portRef O (instanceRef pos_clk_un37_as_030_d0_i_i_a3))
+           (portRef I0 (instanceRef N_233_i))
+          ))
+          (net N_209 (joined
+           (portRef O (instanceRef G_129))
+           (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_x2))
+          ))
+          (net N_184 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_0))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0))
+          ))
+          (net N_180 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_5))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_5))
+          ))
+          (net N_179 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_1))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_1))
+          ))
+          (net N_139_i (joined
+           (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2))
+           (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3_1))
+          ))
+          (net N_312 (joined
+           (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_a2))
+           (portRef I0 (instanceRef N_312_i))
+          ))
+          (net N_270 (joined
+           (portRef O (instanceRef AS_000_INT_1_sqmuxa_i_0_i))
+           (portRef I1 (instanceRef AS_000_INT_0_m))
+           (portRef I0 (instanceRef AS_000_INT_0_r))
+          ))
+          (net N_357 (joined
+           (portRef O (instanceRef pos_clk_un37_as_030_d0_i_i_i))
+           (portRef I1 (instanceRef AS_030_000_SYNC_0_m))
+           (portRef I0 (instanceRef AS_030_000_SYNC_0_r))
+          ))
+          (net N_354 (joined
+           (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i_i))
+           (portRef I0 (instanceRef DS_000_DMA_0_m))
+          ))
+          (net N_227 (joined
+           (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i_a3))
+           (portRef I0 (instanceRef N_227_i))
+          ))
+          (net N_378 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a3_0))
+           (portRef I0 (instanceRef N_378_i))
+          ))
+          (net N_29 (joined
+           (portRef O (instanceRef IPL_030_0_2__p))
+           (portRef I0 (instanceRef N_29_i))
+          ))
+          (net N_28 (joined
+           (portRef O (instanceRef IPL_030_0_1__p))
+           (portRef I0 (instanceRef N_28_i))
+          ))
+          (net N_3 (joined
+           (portRef O (instanceRef DS_000_DMA_0_p))
+           (portRef I0 (instanceRef N_3_i))
+          ))
+          (net N_5 (joined
+           (portRef O (instanceRef AS_000_INT_0_p))
+           (portRef I0 (instanceRef N_5_i))
+          ))
+          (net N_7 (joined
+           (portRef O (instanceRef AS_030_000_SYNC_0_p))
+           (portRef I0 (instanceRef N_7_i))
+          ))
+          (net N_190_i (joined
+           (portRef O (instanceRef N_190_i))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_HIGH))
+          ))
+          (net un1_amiga_bus_enable_low_i (joined
+           (portRef O (instanceRef un1_amiga_bus_enable_low_i))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_LOW))
+          ))
+          (net un21_fpu_cs_i (joined
+           (portRef O (instanceRef un21_fpu_cs_i))
+           (portRef I0 (instanceRef FPU_CS))
+          ))
+          (net CLK_OUT_EXP_INT_i (joined
+           (portRef O (instanceRef CLK_OUT_EXP_INT_i))
+           (portRef I0 (instanceRef CLK_EXP))
+          ))
+          (net AS_000_i (joined
+           (portRef O (instanceRef I_193))
+           (portRef I1 (instanceRef un6_as_030_i_0))
+           (portRef I0 (instanceRef un6_ds_030))
+           (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3_1))
+           (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_1))
+           (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_1))
+           (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_1))
+          ))
+          (net DS_000_DMA_i (joined
+           (portRef O (instanceRef DS_000_DMA_i))
+           (portRef I1 (instanceRef un6_ds_030))
+          ))
+          (net (rename SM_AMIGA_i_5 "SM_AMIGA_i[5]") (joined
+           (portRef O (instanceRef SM_AMIGA_i_5))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_4))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_0))
+           (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i_0))
+           (portRef I0 (instanceRef AS_000_INT_0_m))
+           (portRef I1 (instanceRef un1_SM_AMIGA_3_i_0_0_1))
+          ))
+          (net (rename SM_AMIGA_i_6 "SM_AMIGA_i[6]") (joined
+           (portRef O (instanceRef SM_AMIGA_i_6))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_5_0))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_5))
+          ))
+          (net (rename SM_AMIGA_i_0 "SM_AMIGA_i[0]") (joined
+           (portRef O (instanceRef SM_AMIGA_i_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_5_0))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0))
+          ))
+          (net CLK_000_NE_i (joined
+           (portRef O (instanceRef CLK_000_NE_i))
+           (portRef I0 (instanceRef RST_DLY_e2_i_0_a3_2))
+           (portRef I0 (instanceRef RST_DLY_e1_i_0_a3_1))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_5))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_1))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_4))
+           (portRef I0 (instanceRef RST_DLY_e0_i_0_a3_0_1))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_1_0))
+          ))
+          (net (rename SM_AMIGA_i_4 "SM_AMIGA_i[4]") (joined
+           (portRef O (instanceRef SM_AMIGA_i_4))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_6_0))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_4))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_3))
+          ))
+          (net RW_000_i (joined
+           (portRef O (instanceRef I_194))
+           (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3))
+           (portRef I1 (instanceRef un14_amiga_bus_data_dir_0_a2_i))
+           (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i_a3))
+           (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i))
+          ))
+          (net (rename SM_AMIGA_i_2 "SM_AMIGA_i[2]") (joined
+           (portRef O (instanceRef SM_AMIGA_i_2))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_6_0))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_1))
+          ))
+          (net CLK_000_D0_i (joined
+           (portRef O (instanceRef CLK_000_D0_i))
+           (portRef I0 (instanceRef pos_clk_CLK_000_N_SYNC_2_0_o3_i_o2_0))
+          ))
+          (net BERR_i (joined
+           (portRef O (instanceRef I_195))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_3))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m3_5__m))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m3_1__m))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0_1_0))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_1_1_0))
+          ))
+          (net (rename SM_AMIGA_i_1 "SM_AMIGA_i[1]") (joined
+           (portRef O (instanceRef SM_AMIGA_i_1))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_0))
+          ))
+          (net CLK_000_PE_i (joined
+           (portRef O (instanceRef CLK_000_PE_i))
+           (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o2_3_a2))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_3_0))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m3_5__n))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m3_1__n))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0_0))
+          ))
+          (net N_410_i_0 (joined
+           (portRef O (instanceRef N_410_i))
+           (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_i_a3_1))
+          ))
+          (net (rename SM_AMIGA_i_i_7 "SM_AMIGA_i_i[7]") (joined
+           (portRef O (instanceRef SM_AMIGA_i_i_7))
+           (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_i_a3_2))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_6))
+          ))
+          (net AS_030_i (joined
+           (portRef O (instanceRef I_196))
+           (portRef I1 (instanceRef un4_as_000))
+           (portRef I0 (instanceRef AS_030_D0_0_i_a2_i))
+           (portRef I1 (instanceRef un22_berr_0_a2_0_a3_1_0))
+           (portRef I0 (instanceRef un21_fpu_cs_0_a2_0_a3_1))
+          ))
+          (net FPU_SENSE_i (joined
+           (portRef O (instanceRef FPU_SENSE_i))
+           (portRef I1 (instanceRef un21_fpu_cs_0_a2_0_a3_1))
+          ))
+          (net nEXP_SPACE_D0_i (joined
+           (portRef O (instanceRef nEXP_SPACE_D0_i))
+           (portRef I0 (instanceRef un8_ciin_i_0_0))
+           (portRef I1 (instanceRef un1_as_030_0_0))
+           (portRef I1 (instanceRef un3_as_030_0_i_a3))
+           (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_2))
+          ))
+          (net BGACK_030_INT_i (joined
+           (portRef O (instanceRef BGACK_030_INT_i))
+           (portRef I0 (instanceRef un1_as_030_0_0))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_0_0_o3))
+           (portRef I0 (instanceRef un2_rw_0_i_a2))
+           (portRef I1 (instanceRef un1_amiga_bus_enable_low))
+           (portRef I0 (instanceRef pos_clk_A0_DMA_3_0_a2_0_a3))
+           (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_1))
+           (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_0))
+           (portRef I0 (instanceRef un14_amiga_bus_data_dir_0_a2_i))
+           (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3))
+           (portRef I1 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3))
+           (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3_2))
+           (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_1))
+          ))
+          (net AMIGA_BUS_ENABLE_DMA_HIGH_i (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_i))
+           (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__n))
+          ))
+          (net A1_i (joined
+           (portRef O (instanceRef A1_i))
+           (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3))
+          ))
+          (net CLK_030_H_i (joined
+           (portRef O (instanceRef CLK_030_H_i))
+           (portRef I0 (instanceRef CLK_030_H_2_0_a2_i_a3))
+          ))
+          (net (rename A_i_16 "A_i[16]") (joined
+           (portRef O (instanceRef A_i_16))
+           (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_2))
+          ))
+          (net (rename A_i_18 "A_i[18]") (joined
+           (portRef O (instanceRef A_i_18))
+           (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3))
+          ))
+          (net (rename A_i_19 "A_i[19]") (joined
+           (portRef O (instanceRef A_i_19))
+           (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3))
+          ))
+          (net N_114_i (joined
+           (portRef O (instanceRef N_114_i))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n))
+          ))
+          (net N_113_i (joined
+           (portRef O (instanceRef N_113_i))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n))
+          ))
+          (net AS_000_INT_i (joined
+           (portRef O (instanceRef AS_000_INT_i))
+           (portRef I0 (instanceRef un4_as_000))
+          ))
+          (net AMIGA_BUS_ENABLE_DMA_LOW_i (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_i))
+           (portRef I0 (instanceRef un1_amiga_bus_enable_low))
+          ))
+          (net (rename RST_DLY_i_2 "RST_DLY_i[2]") (joined
+           (portRef O (instanceRef RST_DLY_i_2))
+           (portRef I1 (instanceRef RST_DLY_e2_i_0_a3_2))
+           (portRef I1 (instanceRef RST_DLY_e2_i_0_a3))
+          ))
+          (net (rename RST_DLY_i_0 "RST_DLY_i[0]") (joined
+           (portRef O (instanceRef RST_DLY_i_0))
+           (portRef I1 (instanceRef RST_DLY_e0_i_0_a3_0_1))
+           (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_0_1))
+          ))
+          (net (rename RST_DLY_i_1 "RST_DLY_i[1]") (joined
+           (portRef O (instanceRef RST_DLY_i_1))
+           (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_1))
+           (portRef I1 (instanceRef RST_DLY_e1_i_0_a3_0))
+          ))
+          (net RESET_OUT_i (joined
+           (portRef O (instanceRef RESET_OUT_i))
+           (portRef I1 (instanceRef RESET_OUT_2_i_0_a3))
+           (portRef OE (instanceRef RESET))
+          ))
+          (net (rename SIZE_DMA_i_1 "SIZE_DMA_i[1]") (joined
+           (portRef O (instanceRef SIZE_DMA_i_1))
+           (portRef I1 (instanceRef un4_size))
+          ))
+          (net (rename SIZE_DMA_i_0 "SIZE_DMA_i[0]") (joined
+           (portRef O (instanceRef SIZE_DMA_i_0))
+           (portRef I1 (instanceRef un3_size))
+          ))
+          (net AS_030_D0_i (joined
+           (portRef O (instanceRef AS_030_D0_i))
+           (portRef I0 (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o3))
+           (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_1))
+          ))
+          (net (rename A_i_24 "A_i[24]") (joined
+           (portRef O (instanceRef A_i_24))
+           (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_3))
+          ))
+          (net (rename SM_AMIGA_i_3 "SM_AMIGA_i[3]") (joined
+           (portRef O (instanceRef SM_AMIGA_i_3))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a3_3))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_o2_2))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_2_0))
+          ))
+          (net (rename cpu_est_i_3 "cpu_est_i[3]") (joined
+           (portRef O (instanceRef cpu_est_i_3))
+           (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_2))
+           (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0_2))
+           (portRef I1 (instanceRef cpu_est_2_0_0_a3_0_1))
+           (portRef I1 (instanceRef un5_e_0_0_a3_0))
+          ))
+          (net (rename cpu_est_i_0 "cpu_est_i[0]") (joined
+           (portRef O (instanceRef cpu_est_i_0))
+           (portRef I1 (instanceRef cpu_est_2_0_0_0_a3_1))
+           (portRef I1 (instanceRef cpu_est_2_0_0_0_o2_3))
+           (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_2))
+          ))
+          (net VPA_D_i (joined
+           (portRef O (instanceRef VPA_D_i))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_2_3))
+           (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0_2))
+          ))
+          (net (rename cpu_est_i_1 "cpu_est_i[1]") (joined
+           (portRef O (instanceRef cpu_est_i_1))
+           (portRef I0 (instanceRef VMA_INT_0_m))
+           (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_o2))
+           (portRef I1 (instanceRef cpu_est_2_0_0_a3_0_1_1))
+          ))
+          (net CLK_030_i (joined
+           (portRef O (instanceRef CLK_030_i))
+           (portRef I1 (instanceRef CLK_030_H_2_0_a2_i_o2))
+           (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i))
+          ))
+          (net CLK_000_D1_i (joined
+           (portRef O (instanceRef CLK_000_D1_i))
+           (portRef I1 (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_i_0))
+          ))
+          (net (rename cpu_est_i_2 "cpu_est_i[2]") (joined
+           (portRef O (instanceRef cpu_est_i_2))
+           (portRef I1 (instanceRef cpu_est_2_0_0_0_a2_2))
+           (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_o2))
+          ))
+          (net DTACK_D0_i (joined
+           (portRef O (instanceRef DTACK_D0_i))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_1_3))
+          ))
+          (net RW_i (joined
+           (portRef O (instanceRef I_197))
+           (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_0_a2_0_a3))
+          ))
+          (net (rename A_i_31 "A_i[31]") (joined
+           (portRef O (instanceRef A_i_31))
+           (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_5))
+          ))
+          (net (rename A_i_29 "A_i[29]") (joined
+           (portRef O (instanceRef A_i_29))
+           (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_6))
+          ))
+          (net (rename A_i_30 "A_i[30]") (joined
+           (portRef O (instanceRef A_i_30))
+           (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_11))
+          ))
+          (net (rename A_i_27 "A_i[27]") (joined
+           (portRef O (instanceRef A_i_27))
+           (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_5))
+          ))
+          (net (rename A_i_28 "A_i[28]") (joined
+           (portRef O (instanceRef A_i_28))
+           (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_6))
+          ))
+          (net (rename A_i_25 "A_i[25]") (joined
+           (portRef O (instanceRef A_i_25))
+           (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_4))
+          ))
+          (net (rename A_i_26 "A_i[26]") (joined
+           (portRef O (instanceRef A_i_26))
+           (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_4))
+          ))
+          (net N_213_i (joined
+           (portRef O (instanceRef N_213_i))
+           (portRef I1 (instanceRef G_137_1))
+          ))
+          (net N_214_i (joined
+           (portRef O (instanceRef N_214_i))
+           (portRef I1 (instanceRef G_137))
+          ))
+          (net N_215_i (joined
+           (portRef O (instanceRef N_215_i))
+           (portRef I0 (instanceRef G_137_1))
+          ))
+          (net CLK_OUT_PRE_50_i (joined
+           (portRef O (instanceRef CLK_OUT_PRE_50_i))
+           (portRef D (instanceRef CLK_OUT_PRE_50))
+          ))
+          (net DS_000_ENABLE_1_sqmuxa_i (joined
+           (portRef O (instanceRef DS_000_ENABLE_1_sqmuxa_i))
+           (portRef I0 (instanceRef RW_000_INT_0_m))
+           (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o2_3_o3_1))
+          ))
+          (net N_98_i (joined
+           (portRef O (instanceRef N_98_i))
+           (portRef I0 (instanceRef DSACK1_INT_0_m))
+           (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0))
+          ))
+          (net un6_ds_030_i (joined
+           (portRef O (instanceRef un6_ds_030_i))
+           (portRef I0 (instanceRef DS_030))
+          ))
+          (net un4_as_000_i (joined
+           (portRef O (instanceRef un4_as_000_i))
+           (portRef I0 (instanceRef AS_000))
+          ))
+          (net un4_lds_000_i (joined
+           (portRef O (instanceRef un4_lds_000_i))
+           (portRef I0 (instanceRef LDS_000))
+          ))
+          (net un4_uds_000_i (joined
+           (portRef O (instanceRef un4_uds_000_i))
+           (portRef I0 (instanceRef UDS_000))
+          ))
+          (net LDS_000_INT_i (joined
+           (portRef O (instanceRef LDS_000_INT_i))
+           (portRef I1 (instanceRef un4_lds_000))
+          ))
+          (net UDS_000_INT_i (joined
+           (portRef O (instanceRef UDS_000_INT_i))
+           (portRef I1 (instanceRef un4_uds_000))
+          ))
+          (net AS_030_c (joined
+           (portRef O (instanceRef AS_030))
+           (portRef I0 (instanceRef I_196))
+          ))
+          (net AS_030 (joined
+           (portRef AS_030)
+           (portRef IO (instanceRef AS_030))
+          ))
+          (net AS_000_c (joined
+           (portRef O (instanceRef AS_000))
+           (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0_a2))
+           (portRef I0 (instanceRef I_193))
+          ))
+          (net AS_000 (joined
+           (portRef AS_000)
+           (portRef IO (instanceRef AS_000))
+          ))
+          (net RW_000_c (joined
+           (portRef O (instanceRef RW_000))
+           (portRef I0 (instanceRef I_194))
+           (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_2))
+          ))
+          (net RW_000 (joined
+           (portRef IO (instanceRef RW_000))
+           (portRef RW_000)
+          ))
+          (net DS_030 (joined
+           (portRef O (instanceRef DS_030))
+           (portRef DS_030)
+          ))
+          (net UDS_000_c (joined
+           (portRef O (instanceRef UDS_000))
+           (portRef I1 (instanceRef pos_clk_A0_DMA_3_0_a2_0_a3))
+           (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_a2))
+           (portRef I0 (instanceRef UDS_000_c_i))
+          ))
+          (net UDS_000 (joined
+           (portRef IO (instanceRef UDS_000))
+           (portRef UDS_000)
+          ))
+          (net LDS_000_c (joined
+           (portRef O (instanceRef LDS_000))
+           (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_a2))
+           (portRef I0 (instanceRef LDS_000_c_i))
+          ))
+          (net LDS_000 (joined
+           (portRef IO (instanceRef LDS_000))
+           (portRef LDS_000)
+          ))
+          (net (rename SIZE_c_0 "SIZE_c[0]") (joined
+           (portRef O (instanceRef SIZE_0))
+           (portRef I1 (instanceRef pos_clk_un8_sm_amiga))
+          ))
+          (net (rename SIZE_0 "SIZE[0]") (joined
+           (portRef IO (instanceRef SIZE_0))
+           (portRef (member size 1))
+          ))
+          (net (rename SIZE_c_1 "SIZE_c[1]") (joined
+           (portRef O (instanceRef SIZE_1))
+           (portRef I0 (instanceRef SIZE_c_i_1))
+          ))
+          (net (rename SIZE_1 "SIZE[1]") (joined
+           (portRef (member size 0))
+           (portRef IO (instanceRef SIZE_1))
+          ))
+          (net (rename A_c_2 "A_c[2]") (joined
+           (portRef O (instanceRef A_2))
+          ))
+          (net (rename A_2 "A[2]") (joined
+           (portRef (member a 29))
+           (portRef I0 (instanceRef A_2))
+          ))
+          (net (rename A_c_3 "A_c[3]") (joined
+           (portRef O (instanceRef A_3))
+          ))
+          (net (rename A_3 "A[3]") (joined
+           (portRef (member a 28))
+           (portRef I0 (instanceRef A_3))
+          ))
+          (net (rename A_c_4 "A_c[4]") (joined
+           (portRef O (instanceRef A_4))
+          ))
+          (net (rename A_4 "A[4]") (joined
+           (portRef (member a 27))
+           (portRef I0 (instanceRef A_4))
+          ))
+          (net (rename A_c_5 "A_c[5]") (joined
+           (portRef O (instanceRef A_5))
+          ))
+          (net (rename A_5 "A[5]") (joined
+           (portRef (member a 26))
+           (portRef I0 (instanceRef A_5))
+          ))
+          (net (rename A_c_6 "A_c[6]") (joined
+           (portRef O (instanceRef A_6))
+          ))
+          (net (rename A_6 "A[6]") (joined
+           (portRef (member a 25))
+           (portRef I0 (instanceRef A_6))
+          ))
+          (net (rename A_c_7 "A_c[7]") (joined
+           (portRef O (instanceRef A_7))
+          ))
+          (net (rename A_7 "A[7]") (joined
+           (portRef (member a 24))
+           (portRef I0 (instanceRef A_7))
+          ))
+          (net (rename A_c_8 "A_c[8]") (joined
+           (portRef O (instanceRef A_8))
+          ))
+          (net (rename A_8 "A[8]") (joined
+           (portRef (member a 23))
+           (portRef I0 (instanceRef A_8))
+          ))
+          (net (rename A_c_9 "A_c[9]") (joined
+           (portRef O (instanceRef A_9))
+          ))
+          (net (rename A_9 "A[9]") (joined
+           (portRef (member a 22))
+           (portRef I0 (instanceRef A_9))
+          ))
+          (net (rename A_c_10 "A_c[10]") (joined
+           (portRef O (instanceRef A_10))
+          ))
+          (net (rename A_10 "A[10]") (joined
+           (portRef (member a 21))
+           (portRef I0 (instanceRef A_10))
+          ))
+          (net (rename A_c_11 "A_c[11]") (joined
+           (portRef O (instanceRef A_11))
+          ))
+          (net (rename A_11 "A[11]") (joined
+           (portRef (member a 20))
+           (portRef I0 (instanceRef A_11))
+          ))
+          (net (rename A_c_12 "A_c[12]") (joined
+           (portRef O (instanceRef A_12))
+          ))
+          (net (rename A_12 "A[12]") (joined
+           (portRef (member a 19))
+           (portRef I0 (instanceRef A_12))
+          ))
+          (net (rename A_c_13 "A_c[13]") (joined
+           (portRef O (instanceRef A_13))
+          ))
+          (net (rename A_13 "A[13]") (joined
+           (portRef (member a 18))
+           (portRef I0 (instanceRef A_13))
+          ))
+          (net (rename A_c_14 "A_c[14]") (joined
+           (portRef O (instanceRef A_14))
+          ))
+          (net (rename A_14 "A[14]") (joined
+           (portRef (member a 17))
+           (portRef I0 (instanceRef A_14))
+          ))
+          (net (rename A_c_15 "A_c[15]") (joined
+           (portRef O (instanceRef A_15))
+          ))
+          (net (rename A_15 "A[15]") (joined
+           (portRef (member a 16))
+           (portRef I0 (instanceRef A_15))
+          ))
+          (net (rename A_c_16 "A_c[16]") (joined
+           (portRef O (instanceRef A_16))
+           (portRef I0 (instanceRef A_i_16))
+          ))
+          (net (rename A_16 "A[16]") (joined
+           (portRef (member a 15))
+           (portRef I0 (instanceRef A_16))
+          ))
+          (net (rename A_c_17 "A_c[17]") (joined
+           (portRef O (instanceRef A_17))
+           (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_2))
+          ))
+          (net (rename A_17 "A[17]") (joined
+           (portRef (member a 14))
+           (portRef I0 (instanceRef A_17))
+          ))
+          (net (rename A_c_18 "A_c[18]") (joined
+           (portRef O (instanceRef A_18))
+           (portRef I0 (instanceRef A_i_18))
+          ))
+          (net (rename A_18 "A[18]") (joined
+           (portRef (member a 13))
+           (portRef I0 (instanceRef A_18))
+          ))
+          (net (rename A_c_19 "A_c[19]") (joined
+           (portRef O (instanceRef A_19))
+           (portRef I0 (instanceRef A_i_19))
+          ))
+          (net (rename A_19 "A[19]") (joined
+           (portRef (member a 12))
+           (portRef I0 (instanceRef A_19))
+          ))
+          (net (rename A_c_20 "A_c[20]") (joined
+           (portRef O (instanceRef A_20))
+           (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_1))
+          ))
+          (net (rename A_20 "A[20]") (joined
+           (portRef (member a 11))
+           (portRef I0 (instanceRef A_20))
+          ))
+          (net (rename A_c_21 "A_c[21]") (joined
+           (portRef O (instanceRef A_21))
+           (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_2))
+          ))
+          (net (rename A_21 "A[21]") (joined
+           (portRef (member a 10))
+           (portRef I0 (instanceRef A_21))
+          ))
+          (net (rename A_c_22 "A_c[22]") (joined
+           (portRef O (instanceRef A_22))
+           (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_2))
+          ))
+          (net (rename A_22 "A[22]") (joined
+           (portRef (member a 9))
+           (portRef I0 (instanceRef A_22))
+          ))
+          (net (rename A_c_23 "A_c[23]") (joined
+           (portRef O (instanceRef A_23))
+           (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_3))
+          ))
+          (net (rename A_23 "A[23]") (joined
+           (portRef (member a 8))
+           (portRef I0 (instanceRef A_23))
+          ))
+          (net (rename A_c_24 "A_c[24]") (joined
+           (portRef O (instanceRef A_24))
+           (portRef I0 (instanceRef A_i_24))
+          ))
+          (net (rename A_24 "A[24]") (joined
+           (portRef (member a 7))
+           (portRef I0 (instanceRef A_24))
+          ))
+          (net (rename A_c_25 "A_c[25]") (joined
+           (portRef O (instanceRef A_25))
+           (portRef I0 (instanceRef A_i_25))
+          ))
+          (net (rename A_25 "A[25]") (joined
+           (portRef (member a 6))
+           (portRef I0 (instanceRef A_25))
+          ))
+          (net (rename A_c_26 "A_c[26]") (joined
+           (portRef O (instanceRef A_26))
+           (portRef I0 (instanceRef A_i_26))
+          ))
+          (net (rename A_26 "A[26]") (joined
+           (portRef (member a 5))
+           (portRef I0 (instanceRef A_26))
+          ))
+          (net (rename A_c_27 "A_c[27]") (joined
+           (portRef O (instanceRef A_27))
+           (portRef I0 (instanceRef A_i_27))
+          ))
+          (net (rename A_27 "A[27]") (joined
+           (portRef (member a 4))
+           (portRef I0 (instanceRef A_27))
+          ))
+          (net (rename A_c_28 "A_c[28]") (joined
+           (portRef O (instanceRef A_28))
+           (portRef I0 (instanceRef A_i_28))
+          ))
+          (net (rename A_28 "A[28]") (joined
+           (portRef (member a 3))
+           (portRef I0 (instanceRef A_28))
+          ))
+          (net (rename A_c_29 "A_c[29]") (joined
+           (portRef O (instanceRef A_29))
+           (portRef I0 (instanceRef A_i_29))
+          ))
+          (net (rename A_29 "A[29]") (joined
+           (portRef (member a 2))
+           (portRef I0 (instanceRef A_29))
+          ))
+          (net (rename A_c_30 "A_c[30]") (joined
+           (portRef O (instanceRef A_30))
+           (portRef I0 (instanceRef A_i_30))
+          ))
+          (net (rename A_30 "A[30]") (joined
+           (portRef (member a 1))
+           (portRef I0 (instanceRef A_30))
+          ))
+          (net (rename A_c_31 "A_c[31]") (joined
+           (portRef O (instanceRef A_31))
+           (portRef I0 (instanceRef A_i_31))
+          ))
+          (net (rename A_31 "A[31]") (joined
+           (portRef (member a 0))
+           (portRef I0 (instanceRef A_31))
+          ))
+          (net A0_c (joined
+           (portRef O (instanceRef A0))
+           (portRef I0 (instanceRef UDS_000_INT_0_m))
+           (portRef I0 (instanceRef A0_c_i))
+          ))
+          (net A0 (joined
+           (portRef A0)
+           (portRef IO (instanceRef A0))
+          ))
+          (net A1_c (joined
+           (portRef O (instanceRef A1))
+           (portRef I0 (instanceRef pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3))
+           (portRef I0 (instanceRef A1_i))
+          ))
+          (net A1 (joined
+           (portRef A1)
+           (portRef I0 (instanceRef A1))
+          ))
+          (net nEXP_SPACE_c (joined
+           (portRef O (instanceRef nEXP_SPACE))
+           (portRef I0 (instanceRef nEXP_SPACE_c_i))
+          ))
+          (net nEXP_SPACE (joined
+           (portRef nEXP_SPACE)
+           (portRef I0 (instanceRef nEXP_SPACE))
+          ))
+          (net BERR_c (joined
+           (portRef O (instanceRef BERR))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_3_0))
+           (portRef I1 (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o3))
+           (portRef I0 (instanceRef I_195))
+          ))
+          (net BERR (joined
+           (portRef BERR)
+           (portRef IO (instanceRef BERR))
+          ))
+          (net BG_030_c (joined
+           (portRef O (instanceRef BG_030))
+           (portRef I0 (instanceRef BG_000_0_m))
+           (portRef I0 (instanceRef BG_030_c_i))
+          ))
+          (net BG_030 (joined
+           (portRef BG_030)
+           (portRef I0 (instanceRef BG_030))
+          ))
+          (net BG_000_c (joined
+           (portRef Q (instanceRef BG_000DFF))
+           (portRef I0 (instanceRef BG_000_0_n))
+           (portRef I0 (instanceRef BG_000))
+          ))
+          (net BG_000 (joined
+           (portRef O (instanceRef BG_000))
+           (portRef BG_000)
+          ))
+          (net BGACK_030 (joined
+           (portRef O (instanceRef BGACK_030))
+           (portRef BGACK_030)
+          ))
+          (net BGACK_000_c (joined
+           (portRef O (instanceRef BGACK_000))
+           (portRef I0 (instanceRef BGACK_030_INT_0_m))
+           (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0))
+           (portRef I0 (instanceRef un22_berr_0_a2_0_a3_1))
+          ))
+          (net BGACK_000 (joined
+           (portRef BGACK_000)
+           (portRef I0 (instanceRef BGACK_000))
+          ))
+          (net CLK_030_c (joined
+           (portRef O (instanceRef CLK_030))
+           (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_0))
+           (portRef I0 (instanceRef CLK_030_i))
+           (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_a3))
+          ))
+          (net CLK_030 (joined
+           (portRef CLK_030)
+           (portRef I0 (instanceRef CLK_030))
+          ))
+          (net CLK_000_c (joined
+           (portRef O (instanceRef CLK_000))
+           (portRef D (instanceRef CLK_000_D0))
+          ))
+          (net CLK_000 (joined
+           (portRef CLK_000)
+           (portRef I0 (instanceRef CLK_000))
+          ))
+          (net CLK_OSZI_c (joined
+           (portRef O (instanceRef CLK_OSZI))
+           (portRef CLK (instanceRef A0_DMA))
+           (portRef CLK (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH))
+           (portRef CLK (instanceRef AMIGA_BUS_ENABLE_DMA_LOW))
+           (portRef CLK (instanceRef AS_000_DMA))
+           (portRef CLK (instanceRef AS_000_INT))
+           (portRef CLK (instanceRef AS_030_000_SYNC))
+           (portRef CLK (instanceRef AS_030_D0))
+           (portRef CLK (instanceRef BGACK_030_INT))
+           (portRef CLK (instanceRef BGACK_030_INT_D))
+           (portRef CLK (instanceRef BG_000DFF))
+           (portRef CLK (instanceRef CLK_000_D0))
+           (portRef CLK (instanceRef CLK_000_D1))
+           (portRef CLK (instanceRef CLK_000_NE))
+           (portRef CLK (instanceRef CLK_000_NE_D0))
+           (portRef CLK (instanceRef CLK_000_N_SYNC_0))
+           (portRef CLK (instanceRef CLK_000_N_SYNC_1))
+           (portRef CLK (instanceRef CLK_000_N_SYNC_2))
+           (portRef CLK (instanceRef CLK_000_N_SYNC_3))
+           (portRef CLK (instanceRef CLK_000_N_SYNC_4))
+           (portRef CLK (instanceRef CLK_000_N_SYNC_5))
+           (portRef CLK (instanceRef CLK_000_N_SYNC_6))
+           (portRef CLK (instanceRef CLK_000_N_SYNC_7))
+           (portRef CLK (instanceRef CLK_000_N_SYNC_8))
+           (portRef CLK (instanceRef CLK_000_N_SYNC_9))
+           (portRef CLK (instanceRef CLK_000_N_SYNC_10))
+           (portRef CLK (instanceRef CLK_000_N_SYNC_11))
+           (portRef CLK (instanceRef CLK_000_PE))
+           (portRef CLK (instanceRef CLK_000_P_SYNC_0))
+           (portRef CLK (instanceRef CLK_000_P_SYNC_1))
+           (portRef CLK (instanceRef CLK_000_P_SYNC_2))
+           (portRef CLK (instanceRef CLK_000_P_SYNC_3))
+           (portRef CLK (instanceRef CLK_000_P_SYNC_4))
+           (portRef CLK (instanceRef CLK_000_P_SYNC_5))
+           (portRef CLK (instanceRef CLK_000_P_SYNC_6))
+           (portRef CLK (instanceRef CLK_000_P_SYNC_7))
+           (portRef CLK (instanceRef CLK_000_P_SYNC_8))
+           (portRef CLK (instanceRef CLK_000_P_SYNC_9))
+           (portRef CLK (instanceRef CLK_030_H))
+           (portRef CLK (instanceRef CLK_OUT_EXP_INT))
+           (portRef CLK (instanceRef CLK_OUT_INT))
+           (portRef CLK (instanceRef CLK_OUT_PRE_25))
+           (portRef CLK (instanceRef CLK_OUT_PRE_50))
+           (portRef CLK (instanceRef CLK_OUT_PRE_D))
+           (portRef CLK (instanceRef CYCLE_DMA_0))
+           (portRef CLK (instanceRef CYCLE_DMA_1))
+           (portRef CLK (instanceRef DSACK1_INT))
+           (portRef CLK (instanceRef DS_000_DMA))
+           (portRef CLK (instanceRef DS_000_ENABLE))
+           (portRef CLK (instanceRef DTACK_D0))
+           (portRef CLK (instanceRef IPL_030DFF_0))
+           (portRef CLK (instanceRef IPL_030DFF_1))
+           (portRef CLK (instanceRef IPL_030DFF_2))
+           (portRef CLK (instanceRef IPL_D0_0))
+           (portRef CLK (instanceRef IPL_D0_1))
+           (portRef CLK (instanceRef IPL_D0_2))
+           (portRef CLK (instanceRef LDS_000_INT))
+           (portRef CLK (instanceRef RESET_OUT))
+           (portRef CLK (instanceRef RST_DLY_0))
+           (portRef CLK (instanceRef RST_DLY_1))
+           (portRef CLK (instanceRef RST_DLY_2))
+           (portRef CLK (instanceRef RW_000_DMA))
+           (portRef CLK (instanceRef RW_000_INT))
+           (portRef CLK (instanceRef SIZE_DMA_0))
+           (portRef CLK (instanceRef SIZE_DMA_1))
+           (portRef CLK (instanceRef SM_AMIGA_0))
+           (portRef CLK (instanceRef SM_AMIGA_1))
+           (portRef CLK (instanceRef SM_AMIGA_2))
+           (portRef CLK (instanceRef SM_AMIGA_3))
+           (portRef CLK (instanceRef SM_AMIGA_4))
+           (portRef CLK (instanceRef SM_AMIGA_5))
+           (portRef CLK (instanceRef SM_AMIGA_6))
+           (portRef CLK (instanceRef SM_AMIGA_i_7))
+           (portRef CLK (instanceRef UDS_000_INT))
+           (portRef CLK (instanceRef VMA_INT))
+           (portRef CLK (instanceRef VPA_D))
+           (portRef CLK (instanceRef cpu_est_0))
+           (portRef CLK (instanceRef cpu_est_1))
+           (portRef CLK (instanceRef cpu_est_2))
+           (portRef CLK (instanceRef cpu_est_3))
+           (portRef CLK (instanceRef nEXP_SPACE_D0))
+          ))
+          (net CLK_OSZI (joined
+           (portRef CLK_OSZI)
+           (portRef I0 (instanceRef CLK_OSZI))
+          ))
+          (net CLK_DIV_OUT (joined
+           (portRef O (instanceRef CLK_DIV_OUT))
+           (portRef CLK_DIV_OUT)
+          ))
+          (net CLK_EXP (joined
+           (portRef O (instanceRef CLK_EXP))
+           (portRef CLK_EXP)
+          ))
+          (net FPU_CS (joined
+           (portRef O (instanceRef FPU_CS))
+           (portRef FPU_CS)
+          ))
+          (net FPU_SENSE_c (joined
+           (portRef O (instanceRef FPU_SENSE))
+           (portRef I0 (instanceRef FPU_SENSE_i))
+           (portRef I1 (instanceRef un22_berr_0_a2_0_a3))
+          ))
+          (net FPU_SENSE (joined
+           (portRef FPU_SENSE)
+           (portRef I0 (instanceRef FPU_SENSE))
+          ))
+          (net (rename IPL_030_c_0 "IPL_030_c[0]") (joined
+           (portRef Q (instanceRef IPL_030DFF_0))
+           (portRef I0 (instanceRef IPL_030_0_0__n))
+           (portRef I0 (instanceRef IPL_030_0))
+          ))
+          (net (rename IPL_030_0 "IPL_030[0]") (joined
+           (portRef O (instanceRef IPL_030_0))
+           (portRef (member ipl_030 2))
+          ))
+          (net (rename IPL_030_c_1 "IPL_030_c[1]") (joined
+           (portRef Q (instanceRef IPL_030DFF_1))
+           (portRef I0 (instanceRef IPL_030_0_1__n))
+           (portRef I0 (instanceRef IPL_030_1))
+          ))
+          (net (rename IPL_030_1 "IPL_030[1]") (joined
+           (portRef O (instanceRef IPL_030_1))
+           (portRef (member ipl_030 1))
+          ))
+          (net (rename IPL_030_c_2 "IPL_030_c[2]") (joined
+           (portRef Q (instanceRef IPL_030DFF_2))
+           (portRef I0 (instanceRef IPL_030_0_2__n))
+           (portRef I0 (instanceRef IPL_030_2))
+          ))
+          (net (rename IPL_030_2 "IPL_030[2]") (joined
+           (portRef O (instanceRef IPL_030_2))
+           (portRef (member ipl_030 0))
+          ))
+          (net (rename IPL_c_0 "IPL_c[0]") (joined
+           (portRef O (instanceRef IPL_0))
+           (portRef I0 (instanceRef IPL_030_0_0__m))
+           (portRef I1 (instanceRef G_134))
+           (portRef I0 (instanceRef IPL_c_i_0))
+          ))
+          (net (rename IPL_0 "IPL[0]") (joined
+           (portRef (member ipl 2))
+           (portRef I0 (instanceRef IPL_0))
+          ))
+          (net (rename IPL_c_1 "IPL_c[1]") (joined
+           (portRef O (instanceRef IPL_1))
+           (portRef I1 (instanceRef G_135))
+           (portRef I0 (instanceRef IPL_030_0_1__m))
+           (portRef I0 (instanceRef IPL_c_i_1))
+          ))
+          (net (rename IPL_1 "IPL[1]") (joined
+           (portRef (member ipl 1))
+           (portRef I0 (instanceRef IPL_1))
+          ))
+          (net (rename IPL_c_2 "IPL_c[2]") (joined
+           (portRef O (instanceRef IPL_2))
+           (portRef I0 (instanceRef IPL_030_0_2__m))
+           (portRef I1 (instanceRef G_136))
+           (portRef I0 (instanceRef IPL_c_i_2))
+          ))
+          (net (rename IPL_2 "IPL[2]") (joined
+           (portRef (member ipl 0))
+           (portRef I0 (instanceRef IPL_2))
+          ))
+          (net DSACK1 (joined
+           (portRef O (instanceRef DSACK1))
+           (portRef DSACK1)
+          ))
+          (net DTACK_c (joined
+           (portRef O (instanceRef DTACK))
+           (portRef I0 (instanceRef DTACK_c_i))
+          ))
+          (net DTACK (joined
+           (portRef DTACK)
+           (portRef I0 (instanceRef DTACK))
+          ))
+          (net AVEC (joined
+           (portRef O (instanceRef AVEC))
+           (portRef AVEC)
+          ))
+          (net E (joined
+           (portRef O (instanceRef E))
+           (portRef E)
+          ))
+          (net VPA_c (joined
+           (portRef O (instanceRef VPA))
+           (portRef I0 (instanceRef VPA_c_i))
+          ))
+          (net VPA (joined
+           (portRef VPA)
+           (portRef I0 (instanceRef VPA))
+          ))
+          (net VMA (joined
+           (portRef O (instanceRef VMA))
+           (portRef VMA)
+          ))
+          (net RST_c (joined
+           (portRef O (instanceRef RST))
+           (portRef I1 (instanceRef IPL_030_1_0))
+           (portRef I1 (instanceRef IPL_D0_0_0))
+           (portRef I1 (instanceRef DSACK1_INT_1))
+           (portRef I1 (instanceRef LDS_000_INT_1))
+           (portRef I1 (instanceRef RW_000_INT_2))
+           (portRef I1 (instanceRef UDS_000_INT_1))
+           (portRef I1 (instanceRef VMA_INT_1))
+           (portRef I1 (instanceRef BG_000_1))
+           (portRef I1 (instanceRef DS_000_ENABLE_1))
+           (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_0_0_o3))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o3_0))
+           (portRef I1 (instanceRef RESET_OUT_2_i_0))
+           (portRef I1 (instanceRef RST_DLY_e2_i_0_2))
+           (portRef I1 (instanceRef RST_DLY_e2_i_0_o2))
+           (portRef I1 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_0))
+           (portRef I1 (instanceRef A0_DMA_1))
+           (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1))
+           (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1))
+           (portRef I1 (instanceRef SIZE_DMA_3_sqmuxa_i_i_a3))
+           (portRef I1 (instanceRef AS_000_DMA_1))
+           (portRef I1 (instanceRef BGACK_030_INT_1))
+           (portRef I1 (instanceRef RW_000_DMA_2))
+           (portRef I1 (instanceRef AS_030_D0_0_i_a2_i))
+           (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1))
+           (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0))
+           (portRef I1 (instanceRef AS_030_000_SYNC_1))
+           (portRef I1 (instanceRef AS_000_INT_1))
+           (portRef I1 (instanceRef DS_000_DMA_1))
+           (portRef I0 (instanceRef nEXP_SPACE_D0_0))
+           (portRef I0 (instanceRef VPA_D_0))
+           (portRef I1 (instanceRef DTACK_D0_0))
+           (portRef I1 (instanceRef IPL_D0_0_1))
+           (portRef I1 (instanceRef IPL_D0_0_2))
+           (portRef I1 (instanceRef IPL_030_1_1))
+           (portRef I1 (instanceRef IPL_030_1_2))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_2_2))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_2_3))
+           (portRef I1 (instanceRef RST_DLY_e1_i_0_2))
+           (portRef I1 (instanceRef RST_DLY_e0_i_0_a3_0))
+           (portRef I1 (instanceRef RST_DLY_e0_i_0))
+           (portRef I1 (instanceRef CLK_030_H_2_0_a2_i))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a3_1_2))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a3_1_6))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_1_6))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_5))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_4))
+          ))
+          (net RST (joined
+           (portRef RST)
+           (portRef I0 (instanceRef RST))
+          ))
+          (net RESET (joined
+           (portRef O (instanceRef RESET))
+           (portRef RESET)
+          ))
+          (net RW_c (joined
+           (portRef O (instanceRef RW))
+           (portRef I0 (instanceRef I_197))
+          ))
+          (net RW (joined
+           (portRef IO (instanceRef RW))
+           (portRef RW)
+          ))
+          (net (rename FC_c_0 "FC_c[0]") (joined
+           (portRef O (instanceRef FC_0))
+           (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_1))
+          ))
+          (net (rename FC_0 "FC[0]") (joined
+           (portRef (member fc 1))
+           (portRef I0 (instanceRef FC_0))
+          ))
+          (net (rename FC_c_1 "FC_c[1]") (joined
+           (portRef O (instanceRef FC_1))
+           (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_1))
+          ))
+          (net (rename FC_1 "FC[1]") (joined
+           (portRef (member fc 0))
+           (portRef I0 (instanceRef FC_1))
+          ))
+          (net AMIGA_ADDR_ENABLE (joined
+           (portRef O (instanceRef AMIGA_ADDR_ENABLE))
+           (portRef AMIGA_ADDR_ENABLE)
+          ))
+          (net AMIGA_BUS_DATA_DIR_c (joined
+           (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_i))
+           (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR))
+          ))
+          (net AMIGA_BUS_DATA_DIR (joined
+           (portRef O (instanceRef AMIGA_BUS_DATA_DIR))
+           (portRef AMIGA_BUS_DATA_DIR)
+          ))
+          (net AMIGA_BUS_ENABLE_LOW (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_LOW))
+           (portRef AMIGA_BUS_ENABLE_LOW)
+          ))
+          (net AMIGA_BUS_ENABLE_HIGH (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_HIGH))
+           (portRef AMIGA_BUS_ENABLE_HIGH)
+          ))
+          (net CIIN (joined
+           (portRef O (instanceRef CIIN))
+           (portRef CIIN)
+          ))
+          (net N_7_i (joined
+           (portRef O (instanceRef N_7_i))
+           (portRef I0 (instanceRef AS_030_000_SYNC_1))
+          ))
+          (net N_47_0 (joined
+           (portRef O (instanceRef AS_030_000_SYNC_1))
+           (portRef I0 (instanceRef AS_030_000_SYNC_1_i))
+          ))
+          (net N_5_i (joined
+           (portRef O (instanceRef N_5_i))
+           (portRef I0 (instanceRef AS_000_INT_1))
+          ))
+          (net N_48_0 (joined
+           (portRef O (instanceRef AS_000_INT_1))
+           (portRef I0 (instanceRef AS_000_INT_1_i))
+          ))
+          (net N_3_i (joined
+           (portRef O (instanceRef N_3_i))
+           (portRef I0 (instanceRef DS_000_DMA_1))
+          ))
+          (net N_50_0 (joined
+           (portRef O (instanceRef DS_000_DMA_1))
+           (portRef I0 (instanceRef DS_000_DMA_1_i))
+          ))
+          (net nEXP_SPACE_c_i (joined
+           (portRef O (instanceRef nEXP_SPACE_c_i))
+           (portRef I1 (instanceRef nEXP_SPACE_D0_0))
+          ))
+          (net N_55_0 (joined
+           (portRef O (instanceRef nEXP_SPACE_D0_0))
+           (portRef I0 (instanceRef nEXP_SPACE_D0_0_i))
+          ))
+          (net VPA_c_i (joined
+           (portRef O (instanceRef VPA_c_i))
+           (portRef I1 (instanceRef VPA_D_0))
+          ))
+          (net N_56_0 (joined
+           (portRef O (instanceRef VPA_D_0))
+           (portRef I0 (instanceRef VPA_D_0_i))
+          ))
+          (net DTACK_c_i (joined
+           (portRef O (instanceRef DTACK_c_i))
+           (portRef I0 (instanceRef DTACK_D0_0))
+          ))
+          (net N_57_0 (joined
+           (portRef O (instanceRef DTACK_D0_0))
+           (portRef I0 (instanceRef DTACK_D0_0_i))
+          ))
+          (net (rename IPL_c_i_1 "IPL_c_i[1]") (joined
+           (portRef O (instanceRef IPL_c_i_1))
+           (portRef I0 (instanceRef IPL_D0_0_1))
+          ))
+          (net N_53_0 (joined
+           (portRef O (instanceRef IPL_D0_0_1))
+           (portRef I0 (instanceRef IPL_D0_0_i_1))
+          ))
+          (net (rename IPL_c_i_2 "IPL_c_i[2]") (joined
+           (portRef O (instanceRef IPL_c_i_2))
+           (portRef I0 (instanceRef IPL_D0_0_2))
+          ))
+          (net N_54_0 (joined
+           (portRef O (instanceRef IPL_D0_0_2))
+           (portRef I0 (instanceRef IPL_D0_0_i_2))
+          ))
+          (net N_28_i (joined
+           (portRef O (instanceRef N_28_i))
+           (portRef I0 (instanceRef IPL_030_1_1))
+          ))
+          (net N_32_0 (joined
+           (portRef O (instanceRef IPL_030_1_1))
+           (portRef I0 (instanceRef IPL_030_1_i_1))
+          ))
+          (net N_29_i (joined
+           (portRef O (instanceRef N_29_i))
+           (portRef I0 (instanceRef IPL_030_1_2))
+          ))
+          (net N_33_0 (joined
+           (portRef O (instanceRef IPL_030_1_2))
+           (portRef I0 (instanceRef IPL_030_1_i_2))
+          ))
+          (net N_378_i (joined
+           (portRef O (instanceRef N_378_i))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_0))
+          ))
+          (net N_132_i (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_0))
+           (portRef D (instanceRef SM_AMIGA_0))
+          ))
+          (net N_351_i (joined
+           (portRef O (instanceRef pos_clk_CLK_000_P_SYNC_2_0_a2_i_0))
+           (portRef D (instanceRef CLK_000_P_SYNC_0))
+          ))
+          (net N_227_i (joined
+           (portRef O (instanceRef N_227_i))
+           (portRef I1 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i))
+          ))
+          (net N_354_0 (joined
+           (portRef O (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i))
+           (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i_i))
+          ))
+          (net N_233_i (joined
+           (portRef O (instanceRef N_233_i))
+           (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_i))
+          ))
+          (net N_357_0 (joined
+           (portRef O (instanceRef pos_clk_un37_as_030_d0_i_i))
+           (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_i_i))
+          ))
+          (net N_270_0 (joined
+           (portRef O (instanceRef AS_000_INT_1_sqmuxa_i_0))
+           (portRef I0 (instanceRef AS_000_INT_1_sqmuxa_i_0_i))
+          ))
+          (net AS_000_DMA_i (joined
+           (portRef O (instanceRef AS_000_DMA_i))
+           (portRef I0 (instanceRef CLK_030_H_2_0_a2_i_o2))
+           (portRef I0 (instanceRef un6_as_030_i_0))
+          ))
+          (net N_137_0 (joined
+           (portRef O (instanceRef un6_as_030_i_0))
+           (portRef I0 (instanceRef un6_as_030_i_0_i))
+          ))
+          (net N_312_i (joined
+           (portRef O (instanceRef N_312_i))
+           (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3_2))
+          ))
+          (net (rename pos_clk_un3_as_030_d0_i "pos_clk.un3_as_030_d0_i") (joined
+           (portRef O (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o3))
+           (portRef I0 (instanceRef DS_000_ENABLE_1_sqmuxa_1_a2_0_a3))
+           (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0))
+           (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_i))
+           (portRef I1 (instanceRef AS_000_INT_1_sqmuxa_i_0))
+           (portRef I0 (instanceRef pos_clk_un3_as_030_d0_0_o2_0_o3_i))
+          ))
+          (net N_161_i (joined
+           (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3))
+           (portRef I1 (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i))
+           (portRef I0 (instanceRef pos_clk_DS_000_DMA_4_f0_i_a2_i))
+           (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3_i))
+           (portRef I0 (instanceRef CLK_030_H_2_0_a2_i_1))
+           (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_1))
+          ))
+          (net N_179_0 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_1))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_1))
+          ))
+          (net N_180_0 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_5))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_5))
+          ))
+          (net N_184_0 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_0))
+          ))
+          (net N_185_0 (joined
+           (portRef O (instanceRef CLK_030_H_2_0_a2_i_o2))
+           (portRef I0 (instanceRef CLK_030_H_2_0_a2_i_o2_i))
+          ))
+          (net UDS_000_c_i (joined
+           (portRef O (instanceRef UDS_000_c_i))
+           (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_0))
+          ))
+          (net LDS_000_c_i (joined
+           (portRef O (instanceRef LDS_000_c_i))
+           (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_0))
+          ))
+          (net N_173_i (joined
+           (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_0))
+           (portRef I1 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_a3_1))
+           (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_o2_i_0))
+          ))
+          (net N_358_0 (joined
+           (portRef O (instanceRef AS_030_D0_0_i_a2_i))
+           (portRef I0 (instanceRef AS_030_D0_0_i_a2_i_i))
+          ))
+          (net N_239_i (joined
+           (portRef O (instanceRef N_239_i))
+           (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1))
+          ))
+          (net (rename pos_clk_SIZE_DMA_6_0_1 "pos_clk.SIZE_DMA_6_0[1]") (joined
+           (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_1))
+           (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_1))
+          ))
+          (net N_238_i (joined
+           (portRef O (instanceRef N_238_i))
+           (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0))
+          ))
+          (net (rename pos_clk_SIZE_DMA_6_0_0 "pos_clk.SIZE_DMA_6_0[0]") (joined
+           (portRef O (instanceRef pos_clk_SIZE_DMA_6_0_0_0_0))
+           (portRef I0 (instanceRef pos_clk_SIZE_DMA_6_0_0_0_i_0))
+          ))
+          (net N_237_i (joined
+           (portRef O (instanceRef N_237_i))
+           (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0))
+          ))
+          (net N_236_i (joined
+           (portRef O (instanceRef N_236_i))
+           (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0))
+          ))
+          (net AMIGA_BUS_DATA_DIR_c_0 (joined
+           (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0))
+           (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_i))
+          ))
+          (net N_331_i (joined
+           (portRef O (instanceRef N_331_i))
+           (portRef I1 (instanceRef pos_clk_un6_bgack_000_0_0))
+          ))
+          (net (rename pos_clk_un6_bgack_000_0 "pos_clk.un6_bgack_000_0") (joined
+           (portRef O (instanceRef pos_clk_un6_bgack_000_0_0))
+           (portRef I0 (instanceRef pos_clk_un6_bgack_000_0_0_i))
+          ))
+          (net N_356_0 (joined
+           (portRef O (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i))
+           (portRef I0 (instanceRef AS_000_DMA_1_sqmuxa_0_a2_i_i))
+          ))
+          (net N_352_0 (joined
+           (portRef O (instanceRef un14_amiga_bus_data_dir_0_a2_i))
+           (portRef I0 (instanceRef un14_amiga_bus_data_dir_0_a2_i_i))
+          ))
+          (net N_8_i (joined
+           (portRef O (instanceRef N_8_i))
+           (portRef I0 (instanceRef AS_000_DMA_1))
+          ))
+          (net N_46_0 (joined
+           (portRef O (instanceRef AS_000_DMA_1))
+           (portRef I0 (instanceRef AS_000_DMA_1_i))
+          ))
+          (net N_10_i (joined
+           (portRef O (instanceRef N_10_i))
+           (portRef I0 (instanceRef BGACK_030_INT_1))
+          ))
+          (net N_44_0 (joined
+           (portRef O (instanceRef BGACK_030_INT_1))
+           (portRef I0 (instanceRef BGACK_030_INT_1_i))
+          ))
+          (net N_19_i (joined
+           (portRef O (instanceRef N_19_i))
+           (portRef I0 (instanceRef RW_000_DMA_2))
+          ))
+          (net N_41_0 (joined
+           (portRef O (instanceRef RW_000_DMA_2))
+           (portRef I0 (instanceRef RW_000_DMA_2_i))
+          ))
+          (net N_20_i (joined
+           (portRef O (instanceRef N_20_i))
+           (portRef I0 (instanceRef A0_DMA_1))
+          ))
+          (net N_40_0 (joined
+           (portRef O (instanceRef A0_DMA_1))
+           (portRef I0 (instanceRef A0_DMA_1_i))
+          ))
+          (net N_24_i (joined
+           (portRef O (instanceRef N_24_i))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1))
+          ))
+          (net N_36_0 (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_1_i))
+          ))
+          (net N_25_i (joined
+           (portRef O (instanceRef N_25_i))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1))
+          ))
+          (net N_35_0 (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_1_i))
+          ))
+          (net N_243_i (joined
+           (portRef O (instanceRef RST_DLY_e2_i_0))
+           (portRef D (instanceRef RST_DLY_2))
+          ))
+          (net N_198_i (joined
+           (portRef O (instanceRef N_198_i))
+           (portRef I0 (instanceRef RST_DLY_e2_i_0_2))
+          ))
+          (net N_243_2_i (joined
+           (portRef O (instanceRef RST_DLY_e2_i_0_2))
+           (portRef I0 (instanceRef RST_DLY_e2_i_0_2_i))
+           (portRef I0 (instanceRef RST_DLY_e2_i_0_1))
+          ))
+          (net N_196_i (joined
+           (portRef O (instanceRef N_196_i))
+           (portRef I1 (instanceRef RST_DLY_e2_i_0))
+          ))
+          (net N_195_i (joined
+           (portRef O (instanceRef N_195_i))
+           (portRef I1 (instanceRef RST_DLY_e2_i_0_1))
+          ))
+          (net N_244_i (joined
+           (portRef O (instanceRef RST_DLY_e1_i_0))
+           (portRef D (instanceRef RST_DLY_1))
+          ))
+          (net N_201_i (joined
+           (portRef O (instanceRef N_201_i))
+           (portRef I0 (instanceRef RST_DLY_e1_i_0_2))
+          ))
+          (net N_200_i (joined
+           (portRef O (instanceRef N_200_i))
+           (portRef I1 (instanceRef RST_DLY_e1_i_0_1))
+          ))
+          (net N_199_i (joined
+           (portRef O (instanceRef N_199_i))
+           (portRef I0 (instanceRef RST_DLY_e1_i_0_1))
+          ))
+          (net N_182_0 (joined
+           (portRef O (instanceRef RESET_OUT_2_i_0_o2))
+           (portRef I0 (instanceRef RESET_OUT_2_i_0_o2_i))
+          ))
+          (net N_158_i (joined
+           (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_143_0_o2))
+           (portRef I0 (instanceRef RST_DLY_e2_i_0_a3_0))
+           (portRef I1 (instanceRef RESET_OUT_2_i_0_o2))
+           (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_0_o2_i))
+          ))
+          (net N_148_i (joined
+           (portRef O (instanceRef RST_DLY_e2_i_0_o2_0))
+           (portRef I0 (instanceRef RESET_OUT_1_sqmuxa_i_0_143_0_o2))
+           (portRef I0 (instanceRef RST_DLY_e1_i_0_a3))
+           (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_0_i))
+          ))
+          (net N_307_i (joined
+           (portRef O (instanceRef N_307_i))
+           (portRef I0 (instanceRef RST_DLY_e2_i_0_o2))
+          ))
+          (net N_143_0 (joined
+           (portRef O (instanceRef RST_DLY_e2_i_0_o2))
+           (portRef I0 (instanceRef RST_DLY_e2_i_0_o2_i))
+          ))
+          (net N_217_i (joined
+           (portRef O (instanceRef RESET_OUT_1_sqmuxa_i_0_143_0))
+           (portRef I1 (instanceRef RST_DLY_e2_i_0_a3_1))
+           (portRef I0 (instanceRef RST_DLY_e1_i_0_a3_0_1))
+          ))
+          (net N_235_i (joined
+           (portRef O (instanceRef N_235_i))
+           (portRef I0 (instanceRef RESET_OUT_2_i_0))
+          ))
+          (net N_266_i (joined
+           (portRef O (instanceRef RESET_OUT_2_i_0))
+           (portRef D (instanceRef RESET_OUT))
+          ))
+          (net N_210_i (joined
+           (portRef O (instanceRef N_210_i))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_0))
+          ))
+          (net N_146_i (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_0))
+           (portRef D (instanceRef SM_AMIGA_i_7))
+          ))
+          (net N_207_i (joined
+           (portRef O (instanceRef N_207_i))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_2_0))
+          ))
+          (net N_208_i (joined
+           (portRef O (instanceRef N_208_i))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_2_0))
+          ))
+          (net N_206_i (joined
+           (portRef O (instanceRef N_206_i))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_1_0))
+          ))
+          (net N_138_i (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_3))
+           (portRef D (instanceRef SM_AMIGA_3))
+          ))
+          (net N_313_i (joined
+           (portRef O (instanceRef N_313_i))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_2_3))
+          ))
+          (net N_211_i (joined
+           (portRef O (instanceRef N_211_i))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_3))
+          ))
+          (net N_212_i (joined
+           (portRef O (instanceRef N_212_i))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_3))
+          ))
+          (net N_183_0 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_3))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_3))
+          ))
+          (net N_181_0 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_2_i_0))
+          ))
+          (net N_178_0 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_4))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_i_4))
+          ))
+          (net N_69_0 (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_0_0_o3))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_sqmuxa_i_0_0_o3_i))
+           (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0))
+           (portRef I1 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0))
+          ))
+          (net N_329_i (joined
+           (portRef O (instanceRef N_329_i))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o3_0))
+          ))
+          (net N_176_i (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o3_0))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_1_0))
+          ))
+          (net N_175_0 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_o2_2))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_o2_i_2))
+          ))
+          (net N_174_0 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_o2_6))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_o2_i_6))
+          ))
+          (net N_171_0 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_i_0))
+          ))
+          (net un1_SM_AMIGA_5_i (joined
+           (portRef O (instanceRef un1_SM_AMIGA_5_0_o2_3_o3))
+           (portRef I0 (instanceRef DS_000_ENABLE_0_n))
+           (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o2_3_o3_i))
+          ))
+          (net N_324_i (joined
+           (portRef O (instanceRef N_324_i))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3))
+          ))
+          (net N_326_i (joined
+           (portRef O (instanceRef N_326_i))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3))
+          ))
+          (net N_168_i (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_3))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_0_i_3))
+          ))
+          (net VMA_INT_i (joined
+           (portRef O (instanceRef VMA_INT_i))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_2_3))
+          ))
+          (net N_165_i (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0_i_0))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_2_2_0))
+          ))
+          (net N_164_i (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_6_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_2_2_0))
+          ))
+          (net N_162_i (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_5_0))
+           (portRef I1 (instanceRef un1_SM_AMIGA_5_0_o2_3_o3_1))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_2_1_0))
+          ))
+          (net (rename CLK_000_N_SYNC_i_10 "CLK_000_N_SYNC_i[10]") (joined
+           (portRef O (instanceRef CLK_000_N_SYNC_i_10))
+           (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2))
+          ))
+          (net N_321_i (joined
+           (portRef O (instanceRef N_321_i))
+           (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2))
+          ))
+          (net N_159_0 (joined
+           (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2))
+           (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_i))
+          ))
+          (net N_318_i (joined
+           (portRef O (instanceRef N_318_i))
+           (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o2_3_o3_2))
+          ))
+          (net N_156_i (joined
+           (portRef O (instanceRef cpu_est_2_0_0_0_o2_2))
+           (portRef I0 (instanceRef cpu_est_2_0_0_0_a2_2))
+           (portRef I0 (instanceRef cpu_est_2_0_0_0_a3_3))
+           (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_i_2))
+          ))
+          (net N_155_i (joined
+           (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0_o2))
+           (portRef I0 (instanceRef un5_e_0_0_a3))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1_3))
+           (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_1))
+          ))
+          (net N_154_i (joined
+           (portRef O (instanceRef cpu_est_2_0_0_0_o2_3))
+           (portRef I0 (instanceRef cpu_est_2_0_0_0_o2_i_3))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1_3))
+          ))
+          (net CLK_OUT_PRE_D_i (joined
+           (portRef O (instanceRef CLK_OUT_PRE_D_i))
+           (portRef I1 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_0))
+          ))
+          (net N_152_0 (joined
+           (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_0))
+           (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_o2_0_i))
+          ))
+          (net N_150_i (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_i_0))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_1_6))
+          ))
+          (net AS_030_000_SYNC_i (joined
+           (portRef O (instanceRef AS_030_000_SYNC_i))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0_0))
+          ))
+          (net N_147_i (joined
+           (portRef O (instanceRef pos_clk_CLK_000_N_SYNC_2_0_o3_i_o2_0))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0_0))
+           (portRef D (instanceRef CLK_000_N_SYNC_0))
+          ))
+          (net N_145_i (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_3_0))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_o2_4))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_3_i_0))
+          ))
+          (net N_281_i (joined
+           (portRef O (instanceRef N_281_i))
+           (portRef I0 (instanceRef RST_DLY_e0_i_0_1))
+          ))
+          (net N_302_i (joined
+           (portRef O (instanceRef N_302_i))
+           (portRef I1 (instanceRef RST_DLY_e0_i_0_1))
+          ))
+          (net N_245_i (joined
+           (portRef O (instanceRef RST_DLY_e0_i_0))
+           (portRef D (instanceRef RST_DLY_0))
+          ))
+          (net N_279_i (joined
+           (portRef O (instanceRef N_279_i))
+           (portRef I0 (instanceRef un5_e_0_0))
+          ))
+          (net N_280_i (joined
+           (portRef O (instanceRef N_280_i))
+           (portRef I1 (instanceRef un5_e_0_0))
+          ))
+          (net un5_e_0 (joined
+           (portRef O (instanceRef un5_e_0_0))
+           (portRef I0 (instanceRef un5_e_0_0_i))
+          ))
+          (net N_278_i (joined
+           (portRef O (instanceRef N_278_i))
+           (portRef I1 (instanceRef cpu_est_2_0_0_0_3))
+          ))
+          (net (rename cpu_est_2_0_3 "cpu_est_2_0[3]") (joined
+           (portRef O (instanceRef cpu_est_2_0_0_0_3))
+           (portRef I0 (instanceRef cpu_est_2_0_0_0_i_3))
+          ))
+          (net N_277_i (joined
+           (portRef O (instanceRef N_277_i))
+           (portRef I0 (instanceRef cpu_est_2_0_0_0_2))
+          ))
+          (net N_348_i (joined
+           (portRef O (instanceRef N_348_i))
+           (portRef I1 (instanceRef cpu_est_2_0_0_0_2))
+          ))
+          (net (rename cpu_est_2_0_2 "cpu_est_2_0[2]") (joined
+           (portRef O (instanceRef cpu_est_2_0_0_0_2))
+           (portRef I0 (instanceRef cpu_est_2_0_0_0_i_2))
+          ))
+          (net N_128_i (joined
+           (portRef O (instanceRef pos_clk_un6_bg_030_0_a2_i))
+           (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2_i_i))
+          ))
+          (net N_193_i (joined
+           (portRef O (instanceRef N_193_i))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_1))
+          ))
+          (net N_241_i (joined
+           (portRef O (instanceRef N_241_i))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_1))
+          ))
+          (net N_134_i (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1))
+           (portRef D (instanceRef SM_AMIGA_1))
+          ))
+          (net N_240_i (joined
+           (portRef O (instanceRef N_240_i))
+           (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0_0_1))
+          ))
+          (net N_124_0 (joined
+           (portRef O (instanceRef un1_SM_AMIGA_3_i_0_0))
+           (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0_0_i))
+          ))
+          (net N_267_i (joined
+           (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_0))
+           (portRef D (instanceRef CYCLE_DMA_1))
+          ))
+          (net N_268_i (joined
+           (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0))
+           (portRef D (instanceRef CYCLE_DMA_0))
+          ))
+          (net N_269_0 (joined
+           (portRef O (instanceRef DSACK1_INT_1_sqmuxa_i_0))
+           (portRef I0 (instanceRef DSACK1_INT_1_sqmuxa_i_0_i))
+          ))
+          (net un5_ciin_i (joined
+           (portRef O (instanceRef un5_ciin_i))
+           (portRef I1 (instanceRef un8_ciin_i_0_0))
+          ))
+          (net N_61_0 (joined
+           (portRef O (instanceRef un8_ciin_i_0_0))
+           (portRef I0 (instanceRef un8_ciin_i_0_0_i))
+          ))
+          (net un1_as_030_i (joined
+           (portRef O (instanceRef un1_as_030_0_0))
+           (portRef OE (instanceRef SIZE_0))
+           (portRef OE (instanceRef SIZE_1))
+          ))
+          (net N_228_i (joined
+           (portRef O (instanceRef N_228_i))
+           (portRef I1 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_1))
+          ))
+          (net N_355_0 (joined
+           (portRef O (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i))
+           (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_i))
+          ))
+          (net N_226_i (joined
+           (portRef O (instanceRef N_226_i))
+           (portRef I1 (instanceRef CLK_030_H_2_0_a2_i_1))
+          ))
+          (net N_353_i (joined
+           (portRef O (instanceRef CLK_030_H_2_0_a2_i))
+           (portRef D (instanceRef CLK_030_H))
+          ))
+          (net N_224_i (joined
+           (portRef O (instanceRef N_224_i))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_6))
+          ))
+          (net N_225_i (joined
+           (portRef O (instanceRef N_225_i))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_6))
+          ))
+          (net N_282_0 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_6))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_i_6))
+          ))
+          (net N_221_i (joined
+           (portRef O (instanceRef N_221_i))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_4))
+          ))
+          (net N_222_i (joined
+           (portRef O (instanceRef N_222_i))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_4))
+          ))
+          (net N_140_i (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_4))
+           (portRef D (instanceRef SM_AMIGA_4))
+          ))
+          (net N_219_i (joined
+           (portRef O (instanceRef N_219_i))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_2))
+          ))
+          (net N_220_i (joined
+           (portRef O (instanceRef N_220_i))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_2))
+          ))
+          (net N_283_0 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_2))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_i_2))
+          ))
+          (net N_216_i (joined
+           (portRef O (instanceRef N_216_i))
+           (portRef I0 (instanceRef cpu_est_2_0_0_0_1))
+          ))
+          (net N_218_i (joined
+           (portRef O (instanceRef N_218_i))
+           (portRef I1 (instanceRef cpu_est_2_0_0_0_1))
+          ))
+          (net (rename cpu_est_2_0_1 "cpu_est_2_0[1]") (joined
+           (portRef O (instanceRef cpu_est_2_0_0_0_1))
+           (portRef I0 (instanceRef cpu_est_2_0_0_0_i_1))
+          ))
+          (net N_373_i (joined
+           (portRef O (instanceRef N_373_i))
+           (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0))
+          ))
+          (net N_375_i (joined
+           (portRef O (instanceRef N_375_i))
+           (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0))
+          ))
+          (net (rename pos_clk_un7_clk_000_pe_0 "pos_clk.un7_clk_000_pe_0") (joined
+           (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0))
+           (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_i))
+          ))
+          (net N_188_i (joined
+           (portRef O (instanceRef N_188_i))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1_5))
+          ))
+          (net N_205_i (joined
+           (portRef O (instanceRef N_205_i))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_1_5))
+          ))
+          (net N_142_i (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_5))
+           (portRef D (instanceRef SM_AMIGA_5))
+          ))
+          (net (rename pos_clk_un8_sm_amiga_i "pos_clk.un8_sm_amiga_i") (joined
+           (portRef O (instanceRef pos_clk_un8_sm_amiga))
+           (portRef I0 (instanceRef LDS_000_INT_0_m))
+          ))
+          (net A0_c_i (joined
+           (portRef O (instanceRef A0_c_i))
+           (portRef I1 (instanceRef pos_clk_un8_sm_amiga_1))
+          ))
+          (net (rename SIZE_c_i_1 "SIZE_c_i[1]") (joined
+           (portRef O (instanceRef SIZE_c_i_1))
+           (portRef I0 (instanceRef pos_clk_un8_sm_amiga_1))
+          ))
+          (net N_27_i (joined
+           (portRef O (instanceRef N_27_i))
+           (portRef I0 (instanceRef IPL_030_1_0))
+          ))
+          (net N_31_0 (joined
+           (portRef O (instanceRef IPL_030_1_0))
+           (portRef I0 (instanceRef IPL_030_1_i_0))
+          ))
+          (net (rename IPL_c_i_0 "IPL_c_i[0]") (joined
+           (portRef O (instanceRef IPL_c_i_0))
+           (portRef I0 (instanceRef IPL_D0_0_0))
+          ))
+          (net N_52_0 (joined
+           (portRef O (instanceRef IPL_D0_0_0))
+           (portRef I0 (instanceRef IPL_D0_0_i_0))
+          ))
+          (net N_4_i (joined
+           (portRef O (instanceRef N_4_i))
+           (portRef I0 (instanceRef DSACK1_INT_1))
+          ))
+          (net N_49_0 (joined
+           (portRef O (instanceRef DSACK1_INT_1))
+           (portRef I0 (instanceRef DSACK1_INT_1_i))
+          ))
+          (net N_17_i (joined
+           (portRef O (instanceRef N_17_i))
+           (portRef I0 (instanceRef LDS_000_INT_1))
+          ))
+          (net N_43_0 (joined
+           (portRef O (instanceRef LDS_000_INT_1))
+           (portRef I0 (instanceRef LDS_000_INT_1_i))
+          ))
+          (net N_18_i (joined
+           (portRef O (instanceRef N_18_i))
+           (portRef I0 (instanceRef RW_000_INT_2))
+          ))
+          (net N_42_0 (joined
+           (portRef O (instanceRef RW_000_INT_2))
+           (portRef I0 (instanceRef RW_000_INT_2_i))
+          ))
+          (net N_21_i (joined
+           (portRef O (instanceRef N_21_i))
+           (portRef I0 (instanceRef UDS_000_INT_1))
+          ))
+          (net N_39_0 (joined
+           (portRef O (instanceRef UDS_000_INT_1))
+           (portRef I0 (instanceRef UDS_000_INT_1_i))
+          ))
+          (net N_22_i (joined
+           (portRef O (instanceRef N_22_i))
+           (portRef I0 (instanceRef VMA_INT_1))
+          ))
+          (net N_38_0 (joined
+           (portRef O (instanceRef VMA_INT_1))
+           (portRef I0 (instanceRef VMA_INT_1_i))
+          ))
+          (net N_26_i (joined
+           (portRef O (instanceRef N_26_i))
+           (portRef I0 (instanceRef BG_000_1))
+          ))
+          (net N_34_0 (joined
+           (portRef O (instanceRef BG_000_1))
+           (portRef I0 (instanceRef BG_000_1_i))
+          ))
+          (net BG_030_c_i (joined
+           (portRef O (instanceRef BG_030_c_i))
+           (portRef I0 (instanceRef pos_clk_un8_bg_030))
+          ))
+          (net (rename pos_clk_un8_bg_030_0 "pos_clk.un8_bg_030_0") (joined
+           (portRef O (instanceRef pos_clk_un8_bg_030))
+           (portRef I0 (instanceRef pos_clk_un8_bg_030_i))
+          ))
+          (net N_161_i_1 (joined
+           (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3_1))
+           (portRef I0 (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3))
+          ))
+          (net N_161_i_2 (joined
+           (portRef O (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3_2))
+           (portRef I1 (instanceRef pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3))
+          ))
+          (net (rename pos_clk_un8_sm_amiga_i_1 "pos_clk.un8_sm_amiga_i_1") (joined
+           (portRef O (instanceRef pos_clk_un8_sm_amiga_1))
+           (portRef I0 (instanceRef pos_clk_un8_sm_amiga))
+          ))
+          (net N_324_1 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_1_3))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3))
+          ))
+          (net N_324_2 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_2_3))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_a2_0_3))
+          ))
+          (net N_150_i_1 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_o2_1_0_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_o2_0))
+          ))
+          (net un1_SM_AMIGA_5_i_1 (joined
+           (portRef O (instanceRef un1_SM_AMIGA_5_0_o2_3_o3_1))
+           (portRef I0 (instanceRef un1_SM_AMIGA_5_0_o2_3_o3))
+          ))
+          (net un1_SM_AMIGA_5_i_2 (joined
+           (portRef O (instanceRef un1_SM_AMIGA_5_0_o2_3_o3_2))
+           (portRef I1 (instanceRef un1_SM_AMIGA_5_0_o2_3_o3))
+          ))
+          (net N_138_i_1 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_3))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_3))
+          ))
+          (net N_138_i_2 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_2_3))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_3))
+          ))
+          (net N_146_i_1 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_1_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_3_0))
+          ))
+          (net N_146_i_2 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_2_0))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_3_0))
+          ))
+          (net N_146_i_3 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_3_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_0))
+          ))
+          (net N_220_1 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_1_2))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_2))
+          ))
+          (net N_220_2 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_2_2))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_2))
+          ))
+          (net N_375_1 (joined
+           (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0_1))
+           (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0))
+          ))
+          (net N_375_2 (joined
+           (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0_2))
+           (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_0))
+          ))
+          (net N_373_1 (joined
+           (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_1))
+           (portRef I0 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3))
+          ))
+          (net N_373_2 (joined
+           (portRef O (instanceRef pos_clk_un7_clk_000_pe_0_0_a3_2))
+           (portRef I1 (instanceRef pos_clk_un7_clk_000_pe_0_0_a3))
+          ))
+          (net N_210_1 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a3_2_1_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_2_3_0))
+          ))
+          (net N_210_2 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a3_2_2_0))
+           (portRef I1 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_2_3_0))
+          ))
+          (net N_210_3 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a3_2_3_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_2_0))
+          ))
+          (net un5_ciin_1 (joined
+           (portRef O (instanceRef un5_ciin_0_a2_0_a3_1))
+           (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_7))
+          ))
+          (net un5_ciin_2 (joined
+           (portRef O (instanceRef un5_ciin_0_a2_0_a3_2))
+           (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_7))
+          ))
+          (net un5_ciin_3 (joined
+           (portRef O (instanceRef un5_ciin_0_a2_0_a3_3))
+           (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_8))
+          ))
+          (net un5_ciin_4 (joined
+           (portRef O (instanceRef un5_ciin_0_a2_0_a3_4))
+           (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_8))
+          ))
+          (net un5_ciin_5 (joined
+           (portRef O (instanceRef un5_ciin_0_a2_0_a3_5))
+           (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_9))
+          ))
+          (net un5_ciin_6 (joined
+           (portRef O (instanceRef un5_ciin_0_a2_0_a3_6))
+           (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_9))
+          ))
+          (net un5_ciin_7 (joined
+           (portRef O (instanceRef un5_ciin_0_a2_0_a3_7))
+           (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_10))
+          ))
+          (net un5_ciin_8 (joined
+           (portRef O (instanceRef un5_ciin_0_a2_0_a3_8))
+           (portRef I1 (instanceRef un5_ciin_0_a2_0_a3_10))
+          ))
+          (net un5_ciin_9 (joined
+           (portRef O (instanceRef un5_ciin_0_a2_0_a3_9))
+           (portRef I0 (instanceRef un5_ciin_0_a2_0_a3_11))
+          ))
+          (net un5_ciin_10 (joined
+           (portRef O (instanceRef un5_ciin_0_a2_0_a3_10))
+           (portRef I0 (instanceRef un5_ciin_0_a2_0_a3))
+          ))
+          (net un5_ciin_11 (joined
+           (portRef O (instanceRef un5_ciin_0_a2_0_a3_11))
+           (portRef I1 (instanceRef un5_ciin_0_a2_0_a3))
+          ))
+          (net N_302_1 (joined
+           (portRef O (instanceRef RST_DLY_e0_i_0_a3_0_1))
+           (portRef I0 (instanceRef RST_DLY_e0_i_0_a3_0))
+          ))
+          (net N_244_i_1 (joined
+           (portRef O (instanceRef RST_DLY_e1_i_0_1))
+           (portRef I0 (instanceRef RST_DLY_e1_i_0))
+          ))
+          (net N_244_i_2 (joined
+           (portRef O (instanceRef RST_DLY_e1_i_0_2))
+           (portRef I1 (instanceRef RST_DLY_e1_i_0))
+          ))
+          (net N_243_i_1 (joined
+           (portRef O (instanceRef RST_DLY_e2_i_0_1))
+           (portRef I0 (instanceRef RST_DLY_e2_i_0))
+          ))
+          (net N_410_1 (joined
+           (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_1))
+           (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4))
+          ))
+          (net N_410_2 (joined
+           (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_2))
+           (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4))
+          ))
+          (net N_410_3 (joined
+           (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_3))
+           (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_a2_1))
+          ))
+          (net N_410_4 (joined
+           (portRef O (instanceRef pos_clk_un37_as_030_d0_i_a2_1_4))
+           (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_a2_1))
+          ))
+          (net N_237_1 (joined
+           (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_1))
+           (portRef I0 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0))
+          ))
+          (net N_237_2 (joined
+           (portRef O (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0_2))
+           (portRef I1 (instanceRef AMIGA_BUS_DATA_DIR_0_0_0_a3_0))
+          ))
+          (net un21_fpu_cs_1 (joined
+           (portRef O (instanceRef un21_fpu_cs_0_a2_0_a3_1))
+           (portRef I0 (instanceRef un21_fpu_cs_0_a2_0_a3))
+          ))
+          (net un22_berr_1_0 (joined
+           (portRef O (instanceRef un22_berr_0_a2_0_a3_1_0))
+           (portRef I0 (instanceRef un22_berr_0_a2_0_a3))
+          ))
+          (net N_233_1 (joined
+           (portRef O (instanceRef pos_clk_un37_as_030_d0_i_i_a3_1))
+           (portRef I0 (instanceRef pos_clk_un37_as_030_d0_i_i_a3))
+          ))
+          (net N_233_2 (joined
+           (portRef O (instanceRef pos_clk_un37_as_030_d0_i_i_a3_2))
+           (portRef I1 (instanceRef pos_clk_un37_as_030_d0_i_i_a3))
+          ))
+          (net N_245_i_1 (joined
+           (portRef O (instanceRef RST_DLY_e0_i_0_1))
+           (portRef I0 (instanceRef RST_DLY_e0_i_0))
+          ))
+          (net N_128_i_1 (joined
+           (portRef O (instanceRef pos_clk_un6_bg_030_0_a2_i_1))
+           (portRef I0 (instanceRef pos_clk_un6_bg_030_0_a2_i))
+          ))
+          (net N_134_i_1 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_1))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_1))
+          ))
+          (net N_124_0_1 (joined
+           (portRef O (instanceRef un1_SM_AMIGA_3_i_0_0_1))
+           (portRef I0 (instanceRef un1_SM_AMIGA_3_i_0_0))
+          ))
+          (net N_267_i_1 (joined
+           (portRef O (instanceRef pos_clk_CYCLE_DMA_5_1_i_0_1))
+           (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_1_i_0))
+          ))
+          (net N_268_i_1 (joined
+           (portRef O (instanceRef pos_clk_CYCLE_DMA_5_0_i_0_1))
+           (portRef I0 (instanceRef pos_clk_CYCLE_DMA_5_0_i_0))
+          ))
+          (net N_355_0_1 (joined
+           (portRef O (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i_1))
+           (portRef I0 (instanceRef DS_000_DMA_2_sqmuxa_0_a2_i))
+          ))
+          (net N_353_i_1 (joined
+           (portRef O (instanceRef CLK_030_H_2_0_a2_i_1))
+           (portRef I0 (instanceRef CLK_030_H_2_0_a2_i))
+          ))
+          (net N_140_i_1 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_4))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_4))
+          ))
+          (net N_142_i_1 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_1_5))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_5))
+          ))
+          (net N_280_1 (joined
+           (portRef O (instanceRef un5_e_0_0_a3_0_1))
+           (portRef I0 (instanceRef un5_e_0_0_a3_0))
+          ))
+          (net N_225_1 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_1_6))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a3_0_6))
+          ))
+          (net N_224_1 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a3_1_6))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a3_6))
+          ))
+          (net N_219_1 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_i_0_a3_1_2))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_i_0_a3_2))
+          ))
+          (net N_218_1 (joined
+           (portRef O (instanceRef cpu_est_2_0_0_a3_0_1_1))
+           (portRef I0 (instanceRef cpu_est_2_0_0_a3_0_1))
+          ))
+          (net N_212_1 (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_1_3))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_a3_0_3))
+          ))
+          (net N_208_1 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a3_1_1_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_1_0))
+          ))
+          (net N_207_1 (joined
+           (portRef O (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0_1_0))
+           (portRef I0 (instanceRef SM_AMIGA_nss_i_i_0_0_a3_0_0))
+          ))
+          (net N_200_1 (joined
+           (portRef O (instanceRef RST_DLY_e1_i_0_a3_0_1))
+           (portRef I0 (instanceRef RST_DLY_e1_i_0_a3_0))
+          ))
+          (net N_195_1 (joined
+           (portRef O (instanceRef RST_DLY_e2_i_0_a3_1))
+           (portRef I0 (instanceRef RST_DLY_e2_i_0_a3))
+          ))
+          (net (rename pos_clk_ipl_1 "pos_clk.ipl_1") (joined
+           (portRef O (instanceRef G_137_1))
+           (portRef I0 (instanceRef G_137))
+          ))
+          (net (rename IPL_030_0_1__un3 "IPL_030_0_1_.un3") (joined
+           (portRef O (instanceRef IPL_030_0_1__r))
+           (portRef I1 (instanceRef IPL_030_0_1__n))
+          ))
+          (net (rename IPL_030_0_1__un1 "IPL_030_0_1_.un1") (joined
+           (portRef O (instanceRef IPL_030_0_1__m))
+           (portRef I0 (instanceRef IPL_030_0_1__p))
+          ))
+          (net (rename IPL_030_0_1__un0 "IPL_030_0_1_.un0") (joined
+           (portRef O (instanceRef IPL_030_0_1__n))
+           (portRef I1 (instanceRef IPL_030_0_1__p))
+          ))
+          (net (rename AS_030_000_SYNC_0_un3 "AS_030_000_SYNC_0.un3") (joined
+           (portRef O (instanceRef AS_030_000_SYNC_0_r))
+           (portRef I1 (instanceRef AS_030_000_SYNC_0_n))
+          ))
+          (net (rename AS_030_000_SYNC_0_un1 "AS_030_000_SYNC_0.un1") (joined
+           (portRef O (instanceRef AS_030_000_SYNC_0_m))
+           (portRef I0 (instanceRef AS_030_000_SYNC_0_p))
+          ))
+          (net (rename AS_030_000_SYNC_0_un0 "AS_030_000_SYNC_0.un0") (joined
+           (portRef O (instanceRef AS_030_000_SYNC_0_n))
+           (portRef I1 (instanceRef AS_030_000_SYNC_0_p))
+          ))
+          (net (rename AS_000_INT_0_un3 "AS_000_INT_0.un3") (joined
+           (portRef O (instanceRef AS_000_INT_0_r))
+           (portRef I1 (instanceRef AS_000_INT_0_n))
+          ))
+          (net (rename AS_000_INT_0_un1 "AS_000_INT_0.un1") (joined
+           (portRef O (instanceRef AS_000_INT_0_m))
+           (portRef I0 (instanceRef AS_000_INT_0_p))
+          ))
+          (net (rename AS_000_INT_0_un0 "AS_000_INT_0.un0") (joined
+           (portRef O (instanceRef AS_000_INT_0_n))
+           (portRef I1 (instanceRef AS_000_INT_0_p))
+          ))
+          (net (rename DS_000_DMA_0_un3 "DS_000_DMA_0.un3") (joined
+           (portRef O (instanceRef DS_000_DMA_0_r))
+           (portRef I1 (instanceRef DS_000_DMA_0_n))
+          ))
+          (net (rename DS_000_DMA_0_un1 "DS_000_DMA_0.un1") (joined
+           (portRef O (instanceRef DS_000_DMA_0_m))
+           (portRef I0 (instanceRef DS_000_DMA_0_p))
+          ))
+          (net (rename DS_000_DMA_0_un0 "DS_000_DMA_0.un0") (joined
+           (portRef O (instanceRef DS_000_DMA_0_n))
+           (portRef I1 (instanceRef DS_000_DMA_0_p))
+          ))
+          (net (rename IPL_030_0_2__un3 "IPL_030_0_2_.un3") (joined
+           (portRef O (instanceRef IPL_030_0_2__r))
+           (portRef I1 (instanceRef IPL_030_0_2__n))
+          ))
+          (net (rename IPL_030_0_2__un1 "IPL_030_0_2_.un1") (joined
+           (portRef O (instanceRef IPL_030_0_2__m))
+           (portRef I0 (instanceRef IPL_030_0_2__p))
+          ))
+          (net (rename IPL_030_0_2__un0 "IPL_030_0_2_.un0") (joined
+           (portRef O (instanceRef IPL_030_0_2__n))
+           (portRef I1 (instanceRef IPL_030_0_2__p))
+          ))
+          (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__un3 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0_.un3") (joined
+           (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__r))
+           (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__n))
+          ))
+          (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__un1 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0_.un1") (joined
+           (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__m))
+           (portRef I0 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__p))
+          ))
+          (net (rename un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__un0 "un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0_.un0") (joined
+           (portRef O (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__n))
+           (portRef I1 (instanceRef un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__p))
+          ))
+          (net (rename SM_AMIGA_srsts_i_0_0_m3_1__un3 "SM_AMIGA_srsts_i_0_0_m3_1_.un3") (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_m3_1__r))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_m3_1__n))
+          ))
+          (net (rename SM_AMIGA_srsts_i_0_0_m3_1__un1 "SM_AMIGA_srsts_i_0_0_m3_1_.un1") (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_m3_1__m))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m3_1__p))
+          ))
+          (net (rename SM_AMIGA_srsts_i_0_0_m3_1__un0 "SM_AMIGA_srsts_i_0_0_m3_1_.un0") (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_m3_1__n))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_m3_1__p))
+          ))
+          (net (rename SM_AMIGA_srsts_i_0_0_m3_5__un3 "SM_AMIGA_srsts_i_0_0_m3_5_.un3") (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_m3_5__r))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_m3_5__n))
+          ))
+          (net (rename SM_AMIGA_srsts_i_0_0_m3_5__un1 "SM_AMIGA_srsts_i_0_0_m3_5_.un1") (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_m3_5__m))
+           (portRef I0 (instanceRef SM_AMIGA_srsts_i_0_0_m3_5__p))
+          ))
+          (net (rename SM_AMIGA_srsts_i_0_0_m3_5__un0 "SM_AMIGA_srsts_i_0_0_m3_5_.un0") (joined
+           (portRef O (instanceRef SM_AMIGA_srsts_i_0_0_m3_5__n))
+           (portRef I1 (instanceRef SM_AMIGA_srsts_i_0_0_m3_5__p))
+          ))
+          (net (rename SIZE_DMA_0_0__un3 "SIZE_DMA_0_0_.un3") (joined
+           (portRef O (instanceRef SIZE_DMA_0_0__r))
+           (portRef I1 (instanceRef SIZE_DMA_0_0__n))
+          ))
+          (net (rename SIZE_DMA_0_0__un1 "SIZE_DMA_0_0_.un1") (joined
+           (portRef O (instanceRef SIZE_DMA_0_0__m))
+           (portRef I0 (instanceRef SIZE_DMA_0_0__p))
+          ))
+          (net (rename SIZE_DMA_0_0__un0 "SIZE_DMA_0_0_.un0") (joined
+           (portRef O (instanceRef SIZE_DMA_0_0__n))
+           (portRef I1 (instanceRef SIZE_DMA_0_0__p))
+          ))
+          (net (rename SIZE_DMA_0_1__un3 "SIZE_DMA_0_1_.un3") (joined
+           (portRef O (instanceRef SIZE_DMA_0_1__r))
+           (portRef I1 (instanceRef SIZE_DMA_0_1__n))
+          ))
+          (net (rename SIZE_DMA_0_1__un1 "SIZE_DMA_0_1_.un1") (joined
+           (portRef O (instanceRef SIZE_DMA_0_1__m))
+           (portRef I0 (instanceRef SIZE_DMA_0_1__p))
+          ))
+          (net (rename SIZE_DMA_0_1__un0 "SIZE_DMA_0_1_.un0") (joined
+           (portRef O (instanceRef SIZE_DMA_0_1__n))
+           (portRef I1 (instanceRef SIZE_DMA_0_1__p))
+          ))
+          (net (rename AS_000_DMA_0_un3 "AS_000_DMA_0.un3") (joined
+           (portRef O (instanceRef AS_000_DMA_0_r))
+           (portRef I1 (instanceRef AS_000_DMA_0_n))
+          ))
+          (net (rename AS_000_DMA_0_un1 "AS_000_DMA_0.un1") (joined
+           (portRef O (instanceRef AS_000_DMA_0_m))
+           (portRef I0 (instanceRef AS_000_DMA_0_p))
+          ))
+          (net (rename AS_000_DMA_0_un0 "AS_000_DMA_0.un0") (joined
+           (portRef O (instanceRef AS_000_DMA_0_n))
+           (portRef I1 (instanceRef AS_000_DMA_0_p))
+          ))
+          (net (rename BGACK_030_INT_0_un3 "BGACK_030_INT_0.un3") (joined
+           (portRef O (instanceRef BGACK_030_INT_0_r))
+           (portRef I1 (instanceRef BGACK_030_INT_0_n))
+          ))
+          (net (rename BGACK_030_INT_0_un1 "BGACK_030_INT_0.un1") (joined
+           (portRef O (instanceRef BGACK_030_INT_0_m))
+           (portRef I0 (instanceRef BGACK_030_INT_0_p))
+          ))
+          (net (rename BGACK_030_INT_0_un0 "BGACK_030_INT_0.un0") (joined
+           (portRef O (instanceRef BGACK_030_INT_0_n))
+           (portRef I1 (instanceRef BGACK_030_INT_0_p))
+          ))
+          (net (rename RW_000_DMA_0_un3 "RW_000_DMA_0.un3") (joined
+           (portRef O (instanceRef RW_000_DMA_0_r))
+           (portRef I1 (instanceRef RW_000_DMA_0_n))
+          ))
+          (net (rename RW_000_DMA_0_un1 "RW_000_DMA_0.un1") (joined
+           (portRef O (instanceRef RW_000_DMA_0_m))
+           (portRef I0 (instanceRef RW_000_DMA_0_p))
+          ))
+          (net (rename RW_000_DMA_0_un0 "RW_000_DMA_0.un0") (joined
+           (portRef O (instanceRef RW_000_DMA_0_n))
+           (portRef I1 (instanceRef RW_000_DMA_0_p))
+          ))
+          (net (rename A0_DMA_0_un3 "A0_DMA_0.un3") (joined
+           (portRef O (instanceRef A0_DMA_0_r))
+           (portRef I1 (instanceRef A0_DMA_0_n))
+          ))
+          (net (rename A0_DMA_0_un1 "A0_DMA_0.un1") (joined
+           (portRef O (instanceRef A0_DMA_0_m))
+           (portRef I0 (instanceRef A0_DMA_0_p))
+          ))
+          (net (rename A0_DMA_0_un0 "A0_DMA_0.un0") (joined
+           (portRef O (instanceRef A0_DMA_0_n))
+           (portRef I1 (instanceRef A0_DMA_0_p))
+          ))
+          (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un3 "AMIGA_BUS_ENABLE_DMA_LOW_0.un3") (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_r))
+           (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n))
+          ))
+          (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un1 "AMIGA_BUS_ENABLE_DMA_LOW_0.un1") (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_m))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p))
+          ))
+          (net (rename AMIGA_BUS_ENABLE_DMA_LOW_0_un0 "AMIGA_BUS_ENABLE_DMA_LOW_0.un0") (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_n))
+           (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_LOW_0_p))
+          ))
+          (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un3 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un3") (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_r))
+           (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n))
+          ))
+          (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un1 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un1") (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_m))
+           (portRef I0 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p))
+          ))
+          (net (rename AMIGA_BUS_ENABLE_DMA_HIGH_0_un0 "AMIGA_BUS_ENABLE_DMA_HIGH_0.un0") (joined
+           (portRef O (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_n))
+           (portRef I1 (instanceRef AMIGA_BUS_ENABLE_DMA_HIGH_0_p))
+          ))
+          (net (rename cpu_est_0_2__un3 "cpu_est_0_2_.un3") (joined
+           (portRef O (instanceRef cpu_est_0_2__r))
+           (portRef I1 (instanceRef cpu_est_0_2__n))
+          ))
+          (net (rename cpu_est_0_2__un1 "cpu_est_0_2_.un1") (joined
+           (portRef O (instanceRef cpu_est_0_2__m))
+           (portRef I0 (instanceRef cpu_est_0_2__p))
+          ))
+          (net (rename cpu_est_0_2__un0 "cpu_est_0_2_.un0") (joined
+           (portRef O (instanceRef cpu_est_0_2__n))
+           (portRef I1 (instanceRef cpu_est_0_2__p))
+          ))
+          (net (rename cpu_est_0_3__un3 "cpu_est_0_3_.un3") (joined
+           (portRef O (instanceRef cpu_est_0_3__r))
+           (portRef I1 (instanceRef cpu_est_0_3__n))
+          ))
+          (net (rename cpu_est_0_3__un1 "cpu_est_0_3_.un1") (joined
+           (portRef O (instanceRef cpu_est_0_3__m))
+           (portRef I0 (instanceRef cpu_est_0_3__p))
+          ))
+          (net (rename cpu_est_0_3__un0 "cpu_est_0_3_.un0") (joined
+           (portRef O (instanceRef cpu_est_0_3__n))
+           (portRef I1 (instanceRef cpu_est_0_3__p))
+          ))
+          (net (rename IPL_030_0_0__un3 "IPL_030_0_0_.un3") (joined
+           (portRef O (instanceRef IPL_030_0_0__r))
+           (portRef I1 (instanceRef IPL_030_0_0__n))
+          ))
+          (net (rename IPL_030_0_0__un1 "IPL_030_0_0_.un1") (joined
+           (portRef O (instanceRef IPL_030_0_0__m))
+           (portRef I0 (instanceRef IPL_030_0_0__p))
+          ))
+          (net (rename IPL_030_0_0__un0 "IPL_030_0_0_.un0") (joined
+           (portRef O (instanceRef IPL_030_0_0__n))
+           (portRef I1 (instanceRef IPL_030_0_0__p))
+          ))
+          (net (rename RW_000_INT_0_un3 "RW_000_INT_0.un3") (joined
+           (portRef O (instanceRef RW_000_INT_0_r))
+           (portRef I1 (instanceRef RW_000_INT_0_n))
+          ))
+          (net (rename RW_000_INT_0_un1 "RW_000_INT_0.un1") (joined
+           (portRef O (instanceRef RW_000_INT_0_m))
+           (portRef I0 (instanceRef RW_000_INT_0_p))
+          ))
+          (net (rename RW_000_INT_0_un0 "RW_000_INT_0.un0") (joined
+           (portRef O (instanceRef RW_000_INT_0_n))
+           (portRef I1 (instanceRef RW_000_INT_0_p))
+          ))
+          (net (rename UDS_000_INT_0_un3 "UDS_000_INT_0.un3") (joined
+           (portRef O (instanceRef UDS_000_INT_0_r))
+           (portRef I1 (instanceRef UDS_000_INT_0_n))
+          ))
+          (net (rename UDS_000_INT_0_un1 "UDS_000_INT_0.un1") (joined
+           (portRef O (instanceRef UDS_000_INT_0_m))
+           (portRef I0 (instanceRef UDS_000_INT_0_p))
+          ))
+          (net (rename UDS_000_INT_0_un0 "UDS_000_INT_0.un0") (joined
+           (portRef O (instanceRef UDS_000_INT_0_n))
+           (portRef I1 (instanceRef UDS_000_INT_0_p))
+          ))
+          (net (rename VMA_INT_0_un3 "VMA_INT_0.un3") (joined
+           (portRef O (instanceRef VMA_INT_0_r))
+           (portRef I1 (instanceRef VMA_INT_0_n))
+          ))
+          (net (rename VMA_INT_0_un1 "VMA_INT_0.un1") (joined
+           (portRef O (instanceRef VMA_INT_0_m))
+           (portRef I0 (instanceRef VMA_INT_0_p))
+          ))
+          (net (rename VMA_INT_0_un0 "VMA_INT_0.un0") (joined
+           (portRef O (instanceRef VMA_INT_0_n))
+           (portRef I1 (instanceRef VMA_INT_0_p))
+          ))
+          (net (rename BG_000_0_un3 "BG_000_0.un3") (joined
+           (portRef O (instanceRef BG_000_0_r))
+           (portRef I1 (instanceRef BG_000_0_n))
+          ))
+          (net (rename BG_000_0_un1 "BG_000_0.un1") (joined
+           (portRef O (instanceRef BG_000_0_m))
+           (portRef I0 (instanceRef BG_000_0_p))
+          ))
+          (net (rename BG_000_0_un0 "BG_000_0.un0") (joined
+           (portRef O (instanceRef BG_000_0_n))
+           (portRef I1 (instanceRef BG_000_0_p))
+          ))
+          (net (rename cpu_est_0_1__un3 "cpu_est_0_1_.un3") (joined
+           (portRef O (instanceRef cpu_est_0_1__r))
+           (portRef I1 (instanceRef cpu_est_0_1__n))
+          ))
+          (net (rename cpu_est_0_1__un1 "cpu_est_0_1_.un1") (joined
+           (portRef O (instanceRef cpu_est_0_1__m))
+           (portRef I0 (instanceRef cpu_est_0_1__p))
+          ))
+          (net (rename cpu_est_0_1__un0 "cpu_est_0_1_.un0") (joined
+           (portRef O (instanceRef cpu_est_0_1__n))
+           (portRef I1 (instanceRef cpu_est_0_1__p))
+          ))
+          (net (rename DSACK1_INT_0_un3 "DSACK1_INT_0.un3") (joined
+           (portRef O (instanceRef DSACK1_INT_0_r))
+           (portRef I1 (instanceRef DSACK1_INT_0_n))
+          ))
+          (net (rename DSACK1_INT_0_un1 "DSACK1_INT_0.un1") (joined
+           (portRef O (instanceRef DSACK1_INT_0_m))
+           (portRef I0 (instanceRef DSACK1_INT_0_p))
+          ))
+          (net (rename DSACK1_INT_0_un0 "DSACK1_INT_0.un0") (joined
+           (portRef O (instanceRef DSACK1_INT_0_n))
+           (portRef I1 (instanceRef DSACK1_INT_0_p))
+          ))
+          (net (rename DS_000_ENABLE_0_un3 "DS_000_ENABLE_0.un3") (joined
+           (portRef O (instanceRef DS_000_ENABLE_0_r))
+           (portRef I1 (instanceRef DS_000_ENABLE_0_n))
+          ))
+          (net (rename DS_000_ENABLE_0_un1 "DS_000_ENABLE_0.un1") (joined
+           (portRef O (instanceRef DS_000_ENABLE_0_m))
+           (portRef I0 (instanceRef DS_000_ENABLE_0_p))
+          ))
+          (net (rename DS_000_ENABLE_0_un0 "DS_000_ENABLE_0.un0") (joined
+           (portRef O (instanceRef DS_000_ENABLE_0_n))
+           (portRef I1 (instanceRef DS_000_ENABLE_0_p))
+          ))
+          (net (rename LDS_000_INT_0_un3 "LDS_000_INT_0.un3") (joined
+           (portRef O (instanceRef LDS_000_INT_0_r))
+           (portRef I1 (instanceRef LDS_000_INT_0_n))
+          ))
+          (net (rename LDS_000_INT_0_un1 "LDS_000_INT_0.un1") (joined
+           (portRef O (instanceRef LDS_000_INT_0_m))
+           (portRef I0 (instanceRef LDS_000_INT_0_p))
+          ))
+          (net (rename LDS_000_INT_0_un0 "LDS_000_INT_0.un0") (joined
+           (portRef O (instanceRef LDS_000_INT_0_n))
+           (portRef I1 (instanceRef LDS_000_INT_0_p))
+          ))
+         )
+        (property orig_inst_of (string "BUS68030"))
+       )
+    )
+  )
+  (design BUS68030 (cellRef BUS68030 (libraryRef work)))
+)
diff --git a/Logic/BUS68030.fse b/Logic/BUS68030.fse
index b871b07..f43bb72 100644
--- a/Logic/BUS68030.fse
+++ b/Logic/BUS68030.fse
@@ -1,20 +1,20 @@
 
-fsm_encoding {7139371391} onehot
+fsm_encoding {7138371381} onehot
 
-fsm_state_encoding {7139371391} idle_p {00000000}
+fsm_state_encoding {7138371381} idle_p {00000000}
 
-fsm_state_encoding {7139371391} idle_n {00000011}
+fsm_state_encoding {7138371381} idle_n {00000011}
 
-fsm_state_encoding {7139371391} as_set_p {00000101}
+fsm_state_encoding {7138371381} as_set_p {00000101}
 
-fsm_state_encoding {7139371391} as_set_n {00001001}
+fsm_state_encoding {7138371381} as_set_n {00001001}
 
-fsm_state_encoding {7139371391} sample_dtack_p {00010001}
+fsm_state_encoding {7138371381} sample_dtack_p {00010001}
 
-fsm_state_encoding {7139371391} data_fetch_n {00100001}
+fsm_state_encoding {7138371381} data_fetch_n {00100001}
 
-fsm_state_encoding {7139371391} data_fetch_p {01000001}
+fsm_state_encoding {7138371381} data_fetch_p {01000001}
 
-fsm_state_encoding {7139371391} end_cycle_n {10000001}
+fsm_state_encoding {7138371381} end_cycle_n {10000001}
 
-fsm_registers {7139371391} {SM_AMIGA[0]}  {SM_AMIGA[1]}  {SM_AMIGA[2]}  {SM_AMIGA[3]}  {SM_AMIGA[4]}  {SM_AMIGA[5]}  {SM_AMIGA[6]}  {SM_AMIGA_i[7]} 
+fsm_registers {7138371381} {SM_AMIGA[0]}  {SM_AMIGA[1]}  {SM_AMIGA[2]}  {SM_AMIGA[3]}  {SM_AMIGA[4]}  {SM_AMIGA[5]}  {SM_AMIGA[6]}  {SM_AMIGA_i[7]} 
diff --git a/Logic/BUS68030.naf b/Logic/BUS68030.naf
new file mode 100644
index 0000000..24daa01
--- /dev/null
+++ b/Logic/BUS68030.naf
@@ -0,0 +1,75 @@
+AS_030  b
+AS_000  b
+RW_000  b
+DS_030  b
+UDS_000  b
+LDS_000  b
+SIZE[1]  b
+SIZE[0]  b
+A[31]  i
+A[30]  i
+A[29]  i
+A[28]  i
+A[27]  i
+A[26]  i
+A[25]  i
+A[24]  i
+A[23]  i
+A[22]  i
+A[21]  i
+A[20]  i
+A[19]  i
+A[18]  i
+A[17]  i
+A[16]  i
+A[15]  i
+A[14]  i
+A[13]  i
+A[12]  i
+A[11]  i
+A[10]  i
+A[9]  i
+A[8]  i
+A[7]  i
+A[6]  i
+A[5]  i
+A[4]  i
+A[3]  i
+A[2]  i
+A0  b
+A1  i
+nEXP_SPACE  i
+BERR  b
+BG_030  i
+BG_000  o
+BGACK_030  o
+BGACK_000  i
+CLK_030  i
+CLK_000  i
+CLK_OSZI  i
+CLK_DIV_OUT  o
+CLK_EXP  o
+FPU_CS  o
+FPU_SENSE  i
+IPL_030[2]  o
+IPL_030[1]  o
+IPL_030[0]  o
+IPL[2]  i
+IPL[1]  i
+IPL[0]  i
+DSACK1  b
+DTACK  b
+AVEC  o
+E  o
+VPA  i
+VMA  o
+RST  i
+RESET  b
+RW  b
+FC[1]  i
+FC[0]  i
+AMIGA_ADDR_ENABLE  o
+AMIGA_BUS_DATA_DIR  o
+AMIGA_BUS_ENABLE_LOW  o
+AMIGA_BUS_ENABLE_HIGH  o
+CIIN  o
diff --git a/Logic/BUS68030.prj b/Logic/BUS68030.prj
index 40811d7..6a87d09 100644
--- a/Logic/BUS68030.prj
+++ b/Logic/BUS68030.prj
@@ -1,6 +1,6 @@
 #-- Lattice Semiconductor Corporation Ltd.
 #-- Synplify OEM project file c:/users/matze/documents/github/68030tk/logic\BUS68030.prj
-#-- Written on Sat Oct 10 21:59:34 2015
+#-- Written on Sun Jan 24 16:20:40 2016
 
 
 #device options
diff --git a/Logic/BUS68030.srm b/Logic/BUS68030.srm
new file mode 100644
index 0000000..0fb8f8e
--- /dev/null
+++ b/Logic/BUS68030.srm
@@ -0,0 +1,3649 @@
+%%% protect protected_file
+f "c:\isplever\synpbase\lib\vhd\std.vhd"; #file 0
+af  .is_vhdl 1;
+af  .child_list "-1";
+af  .parent_list "-1";
+f "c:\isplever\synpbase\lib\vhd\snps_haps_pkg.vhd"; #file 1
+af  .is_vhdl 1;
+af  .child_list "-1";
+af  .parent_list "-1";
+f "c:\isplever\synpbase\lib\vhd\std1164.vhd"; #file 2
+af  .is_vhdl 1;
+af  .child_list "-1";
+af  .parent_list "-1";
+f "c:\isplever\synpbase\lib\vhd\numeric.vhd"; #file 3
+af  .is_vhdl 1;
+af  .child_list "-1";
+af  .parent_list "-1";
+f "c:\isplever\synpbase\lib\vhd\umr_capim.vhd"; #file 4
+af  .is_vhdl 1;
+af  .child_list "-1";
+af  .parent_list "-1";
+f "c:\isplever\synpbase\lib\vhd\arith.vhd"; #file 5
+af  .is_vhdl 1;
+af  .child_list "-1";
+af  .parent_list "-1";
+f "c:\isplever\synpbase\lib\vhd\unsigned.vhd"; #file 6
+af  .is_vhdl 1;
+af  .child_list "-1";
+af  .parent_list "-1";
+f "c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd"; #file 7
+af  .is_vhdl 1;
+af  .child_list "-1";
+af  .parent_list "-1";
+VNAME 'mach.MACH_DFF.prim'; # view id 0
+VNAME 'mach.DFF.prim'; # view id 1
+VNAME 'mach.BI_DIR.prim'; # view id 2
+VNAME 'mach.BUFTH.prim'; # view id 3
+VNAME 'mach.IBUF.prim'; # view id 4
+VNAME 'mach.OBUF.prim'; # view id 5
+VNAME 'mach.AND2.prim'; # view id 6
+VNAME 'mach.INV.prim'; # view id 7
+VNAME 'mach.OR2.prim'; # view id 8
+VNAME 'mach.XOR2.prim'; # view id 9
+VNAME 'work.BUS68030.behavioral'; # view id 10
+@ERMRlENORBvq]w_7wsRbH
+l;N3ORCV8HMCF8V;R4
+RNP3#8H#PFDCRlC4N;
+PHR3#Hbsl;R4
+RNP3M#$_MDH	HCs8lR"N3OEv]qB_w7w3Hbsl
+";F;RT
+7HR;R
+HB;pi
+RNH#_$MHD#OFRO	4o;
+bpRBiN;
+b$R#MF_bsD0VNRo#cH;
+R
+);H;R1
+hHRmwaQQ; )
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+oR4kM;M
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+FmH;
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+Hm
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+B;bjRf:VjRNCD#RDVN#tCRh
+7;bjRf:GjRFRsPmRRmQQjR4@;
+ 
+
+
+
+ftell;
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+POR38#L_NRPC{P
+NRM#$_VsCCMsCOOC_D	FORN{
+P$R1#l0CRN{
+P#R3$sM_CDVOF_O	0C$bR
+g;}};
+;;
+}
+RNP3#FLF8b0FRMC4L;
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+b$R#MF_bsD0VNRo#UL;
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+NR03sDs_FHNoMl"CRqj1_j;j"
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+RNH#_$M0#sH0CN0R
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+b$R#MF_bsD0VNRo#UF;
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+NR83CHsVNsMN$NRlC'x#HC
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+R(@@::.n4n:.::4jMu X_q1uBM R _Xu1Buq N;
+HsR30FD_sMHoNRlC"XM uu_1q"B ;R
+L@:@(.4(:::.(c :A)A)R ;))
+RNH3Ds0_HFsolMNCAR" "));H
+NRM#$_H0s#00NC;R4
+RobA) );b
+NRM#$_sbF0NVDoU#R;R
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+RNH3Ds0_HFsolMNCAR"td_jj
+";F@R@(g:.:.4:g::nAjt_jAjRtj_jjN;
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+@HR@d(:4::4dg4::qAtBji_jAjRtiqB_jjj;H
+NR03sDs_FHNoMl"CRABtqij_jj
+";H@R@(.:d:d4:.::(B_pijRdjB_pij;dj
+RNH3Ds0_HFsolMNCBR"pji_d;j"
+@HR@d(:d::4d(d::iBp_jjjRiBp_jjj;H
+NR03sDs_FHNoMl"CRB_pij"jj;R
+H@:@(d4c:::dcUp:Bi1_mZBQRpmi_1;ZQ
+RNH3Ds0_HFsolMNCBR"pmi_1"ZQ;R
+F@:@(d46:::d64B4:p7i_Qme_zBaRp7i_Qme_z
+a;N3HRs_0DFosHMCNlRp"BiQ_7ez_ma
+";F@R@(n:d:d4:n::(B_pi RXuB_pi ;Xu
+RNH3Ds0_HFsolMNCBR"p i_X;u"
+@FR@d(:(::4dn(::zwu_RB1w_uzB
+1;N3HRs_0DFosHMCNlRu"wz1_B"H;
+R(@@::dU4U:d:wg:u1z_  h1Rzwu_h1 1
+ ;N3HRs_0DFosHMCNlRu"wz _1h"1 ;R
+F@:@(d4g:::dg(u:Qpd_jj:r.jQ9Rujp_d.jr:Rj9Q_upjrdj.9:j;H
+NR03sDs_FHNoMl"CRQ_upj"dj;H
+NR83CHsVNsMN$NRlC'DHb_jjd'H;
+R(@@::cj4j:c:Qd:u.pr:Rj9Qrup.9:jRpQurj.:9N;
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+HCR38NHVs$sNMCNlRb'HD
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+NRD3#bHFsos8HRM"HF"k0;H
+NRF3bsD0N8RHs"0Fk"H;
+R(@@::c.4.:c:76:aiqBRq7aB
+i;N3HRs_0DFosHMCNlRa"7q"Bi;H
+NRs3FHHo8sHR'M0Fk'F;
+R(@@::cd4d:c:qc:eR BqBe ;H
+NR03sDs_FHNoMl"CRqBe "F;
+R(@@::cc4c:c: 4:R
+ ;N3HRs_0DFosHMCNlR"" ;R
+H@:@(c46:::c6du:equReqN;
+HsR30FD_sMHoNRlC"qeu"F;
+R(@@::cn4n:c:ed:veqRv
+q;N3HRs_0DFosHMCNlRv"eq
+";H@R@((:c:c4:(::d)R1a);1a
+RNH3Ds0_HFsolMNC)R"1;a"
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+NR03sDs_FHNoMl"CR)  1a
+";N3HR#FDbs8HoH"sRHkMF0
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+RNH3HC8VsNsNN$Ml'CRV;O'
+@FR@6(:.::464.:(v:qQ_tqq)77_q hARp qtvQq7_q7 )_hpqA N;
+HsR30FD_sMHoNRlC"Qqvtqq_7_7) Ahqp; "
+@FR@6(:d::464d:Uv:qQ_tqA_z17qqa_)7QRQqvtAq_z71_q_aq7;Q)
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+";F@R@(c:6:64:cj:.:QqvtAq_z 1_hpqA m_pWvRqQ_tqA_z1 Ahqpp _m
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+@FR@6(:6::46.6:4v:qQ_tqA_z1 Ahqp] _QRt]qtvQqz_A1h_ q Ap_t]Q]N;
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+@FR@6(:n::46cn::QBQhQRBQ
+h;N3HRs_0DFosHMCNlRQ"BQ;h"
+RoMk_M6CN;
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+n;okMRMN4_lNHo_#Lk_NCML_DCD;FI
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRdkM_x#HCN;
+M#R3N_PCM_C0VoDN#.4R6
+n;okMRM#c_H;xC
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRckM_#k8_jjj;M
+NRN3#PMC_CV0_D#No46R.no;
+MMRkc8_D#j_jjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;okMRMO6_H;HM
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRckM__N#j;jj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR4kM__1vqtvQq;_6
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR.kM4b_Vk#_O;M
+NRN3#PMC_CV0_D#No46R.no;
+MMRk.L._C;ss
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRnkM__8#j;dj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRch_;M
+NRN3#PMC_CV0_D#No46R.no;
+M_RhnN;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;44
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR4h_.N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;4c
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR4h_6N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;4n
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR4h_(N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;4U
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR.h_4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;..
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR.h_nN;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;.(
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRdh_jN;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;d4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRdh_.N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;dd
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRdh_cN;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;d6
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRdh_nN;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;dU
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRdh_gN;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;cj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRch_4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;c.
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRch_dN;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;cc
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRch_nN;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;c(
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRch_UN;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;cg
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+oR6h_jN;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;6.
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR6h_dN;
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+n;ohMR_;6c
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR6h_6N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;6n
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR6h_(N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;nj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR(h_.N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;(d
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+oR(h_cN;
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+n;ohMR_;(6
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR(h_nN;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;((
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR(h_UN;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_;(g
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR4h_.
+c;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMh4_.dN;
+M#R3N_PCM_C0VoDN#.4R6
+n;ohMR_c.4;M
+NRN3#PMC_CV0_D#No46R.no;
+M_Rh.;46
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR.h_n
+g;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMhU_..N;
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+n;ohMR_d.U;M
+NRN3#PMC_CV0_D#No46R.no;
+M_Rhd;66
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRdh_6
+U;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMh(_ddN;
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+n;ohMR_6d(;M
+NRN3#PMC_CV0_D#No46R.no;
+MuRQpd_jj__j4k_3M
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+RoMQ_upj_djj__434kM;M
+NRN3#PMC_CV0_D#No46R.no;
+MuRQpd_jj__j4k_3M
+j;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMqj1_djj_j1j_Y_hBjM3kdN;
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+n;oqMR1d_jjj_jjY_1hjB_34kM;M
+NRN3#PMC_CV0_D#No46R.no;
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+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR_q1j_jjQ_hajM3kdN;
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+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR_71j_jj7_vqjM3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;o7MR1j_jjv_7q3_jk;Mj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRpQu_jjd_.j__M3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oQMRujp_djj__3._k;M4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRpQu_jjd_.j__M3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;okMRMq4_vqQt_1Az_q hA_p 7_vq]]Qt_lH_.__jlj.__M3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;okMRMq4_vqQt_1Az_q hA_p 7_vq]]Qt_lH_.__jlj.__M3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;okMRMq4_vqQt_1Az_q hA_p 7_vq]]Qt_lH_.__jlj.__M3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;o1MRvv_qQ_tq#0s##__Hj__jl4d__M3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;o1MRvv_qQ_tq#0s##__Hj__jl4d__M3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;o1MRvv_qQ_tq#0s##__Hj__jl4d__M3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;o1MRvv_qQ_tq#0s##__Hj__jl6d__M3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;o1MRvv_qQ_tq#0s##__Hj__jl6d__M3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;o1MRvv_qQ_tq#0s##__Hj__jl6d__M3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;o1MRQ_Z 7_vqj__j3dkM;M
+NRN3#PMC_CV0_D#No46R.no;
+MQR1Z7 _vjq__3j_k;M4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRZ1Q v_7q__jjk_3M
+j;N3MR#CNP_0MC_NVDoR#4.;6n
+RoM1 QZ_q7v_4j__M3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;o1MRQ_Z 7_vqj__434kM;M
+NRN3#PMC_CV0_D#No46R.no;
+MQR1Z7 _vjq__34_k;Mj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR_q1j_jj7_vqjM3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oqMR1j_jjv_7q3_jk;M4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR_q1j_jj7_vqjM3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oAMRtiqB_jjd_aQh_kj3M
+d;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMABtqid_jjh_Qa3_jk;M4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRqAtBji_dQj_hja_3jkM;M
+NRN3#PMC_CV0_D#No46R.no;
+MWR)_jjj_q7v_kj3M
+d;N3MR#CNP_0MC_NVDoR#4.;6n
+RoM)jW_j7j_vjq_34kM;M
+NRN3#PMC_CV0_D#No46R.no;
+MWR)_jjj_q7v_kj3M
+j;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMq7j_vjq_3dkM;M
+NRN3#PMC_CV0_D#No46R.no;
+MjRq_q7v_kj3M
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMq7j_vjq_3jkM;M
+NRN3#PMC_CV0_D#No46R.no;
+MvRqQ_tqA_z1 Ahqp7 _vpq_mjW_3dkM;M
+NRN3#PMC_CV0_D#No46R.no;
+MvRqQ_tqA_z1 Ahqp7 _vpq_mjW_34kM;M
+NRN3#PMC_CV0_D#No46R.no;
+MvRqQ_tqA_z1 Ahqp7 _vpq_mjW_3jkM;M
+NRN3#PMC_CV0_D#No46R.no;
+MvRqQ_tqA_z1 Ahqp7 _v]q_Q_t]jM3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oqMRvqQt_1Az_q hA_p 7_vq]]Qt_kj3M
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMqtvQqz_A1h_ q Ap_q7v_t]Q]3_jk;Mj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRkOb_0C#_.j__M3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oOMRbCk_#j0__3._k;M4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRkOb_0C#_.j__M3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oOMRbCk_#j0__3d_k;Md
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRkOb_0C#_dj__M3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;oOMRbCk_#j0__3d_k;Mj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRpQu_jjd_jj__M3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oQMRujp_djj__3j_k;M4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRpQu_jjd_jj__M3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;o)MRWj_jjh_Qa3_jk;Md
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR_)Wj_jjQ_hajM3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;o)MRWj_jjh_Qa3_jk;Mj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR1z7_jjj_aQh_kj3M
+d;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMz_71j_jjQ_hajM3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;ozMR7j1_jQj_hja_3jkM;M
+NRN3#PMC_CV0_D#No46R.no;
+MvReqh_Qa3_jk;Md
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRqev_aQh_kj3M
+4;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMe_vqQ_hajM3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oAMRtj_jj3_jk;Md
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR_Atj_jjjM3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;oAMRtj_jj3_jk;Mj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRkOb_0C#_4j__M3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;oOMRbCk_#j0__34_k;M4
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRkOb_0C#_4j__M3kjN;
+M#R3N_PCM_C0VoDN#.4R6
+n;o7MR1iqB4h_Qa3_jk;Md
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oRq71B_i4Q_hajM3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;o7MR1iqB4h_Qa3_jk;Mj
+RNM3P#NCC_M0D_VN4o#Rn.6;M
+oR_71j_jj Ahqpj _3dkM;M
+NRN3#PMC_CV0_D#No46R.no;
+M1R7_jjj_q hA_p jM3k4N;
+M#R3N_PCM_C0VoDN#.4R6
+n;o7MR1j_jjh_ q Ap_kj3M
+j;N3MR#CNP_0MC_NVDoR#4.;6n
+RoMp_71j_jjQ_hajM3kdN;
+M#R3N_PCM_C0VoDN#.4R6
+n;opMR7j1_jQj_hja_34kM;M
+NRN3#PMC_CV0_D#No46R.no;
+M7Rp1j_jjh_Qa3_jk;Mj
+RNM3P#NCC_M0D_VN4o#Rn.6;R
+b@:@j4::44+:.40j:sRkCfjj:Rk0sCsR0keCRB
+B;b@R@j::44::4.j+4:DVN#fCRjR:jV#NDCNRVDR#Ct;h7
+@bR@4(:ddU:(d:4Ug:d+:4j1qv_vqQtr(j:9jRf:ojRE0F#R_1vqtvQq:rj(h9R_,(.hd_(,(h_c_,h(h6,_,(nh(_(,(h_U_,h(
+g;ombRr;j9
+RNb#_$Mb0FsVoDN#cRn;b
+oR4mr9N;
+b$R#MF_bsD0VNRo#n
+c;ombRr;.9
+RNb#_$Mb0FsVoDN#cRn;b
+oRdmr9N;
+b$R#MF_bsD0VNRo#n
+c;ombRr;c9
+RNb#_$Mb0FsVoDN#cRn;b
+oR6mr9N;
+b$R#MF_bsD0VNRo#n
+c;ombRr;n9
+RNb#_$Mb0FsVoDN#cRn;b
+oR(mr9N;
+b$R#MF_bsD0VNRo#n
+c;N3HRsC0D_R0F4N;
+H$R#M#_Vl8_HR4"(d(Ud44dU"N;
+HsR30FD_sMHoNRlC"_1vqtvQq
+";N3HRV_#lVlsF#"0R1qv_vqQtR;d"
+RNH3lV#_#0F01R"vv_qQRtqU
+";N3HRV_#l0DNLCR#0"jjjRj4jjjjjjjsj44Rjjjjjjjjs4jjRjj4jjsjjjR44j4jjjjjjsj4jRjjjjj4jjjs44jRjj4jjj4js4jjRjjjjjs4j4R44jjjjj4jjs
+";N3HRV_#lFosHMCNlRv"1_Qqvt;q"
+RNH3lV#_N#00CCso;R4
+RNH3N#00lC_NHbbM"oRRjRRjjjjjRj4-j>Rjjjjj\jjMRRRjjjjjjj4RR->jjjjj4j4\RMRRjjjjjj4j>R-Rjjjjjj44R\MRjRjjjj4j-jR>jRjjjj4jM4\RjRRjjj4jRjj-j>Rjjj4j\j4MRRRjjj4jjjjRR->jjj4j4jj\RMRRjj4jjjjj>R-Rjj4jjjj4R\MRjR4jjjjj-jR>jR4jjjjjM4\"s;
+R(@@:U4d::d(4:dUd4g+jv:1_Qqvtjqr:R(9fjj:ROlNEwR7wsRbH1lRvv_qQ_tqH9r(
+=ST1qv_vqQt_(Hr97
+S=4h_cHn_
+pSBip=Bi1_mZOQ_;H
+NR03sD0C_F;R4
+RNH#_$MV_#lH"8R(U4ddd(4U;4"
+RNH3Ds0_HFsolMNC1R"vv_qQ"tq;H
+NR#3Vls_VF0l#Rv"1_QqvtdqR"N;
+HVR3#0l_FR#0"_1vqtvQq"RU;H
+NR#3VlN_0L#DC0jR"j4jRjjjjjsjjjRj4jj4jjjjjsjj4R4jjjjjjj4sj4jRjjj4jj4jsjjjRj4jjjsjj4Rj4jjjjjj4jsj44Rjjjj4jjj4s44jRjjjjjj"4s;H
+NR#3Vls_FHNoMl"CR1qv_vqQt"N;
+HVR3##l_0CN0sRCo4N;
+HFR3sHHoMM#0NRlC'_1vqtvQq:rj(;9'
+RNH3PHM_k#FsROC'_1vqtvQq9r('N;
+H#R3$HM_MPH0N"DRj
+";s@R@(d:4U(:d:U4d:+dg41j:vv_qQrtqj9:(R:fjjNRlO7ERwbwRsRHl1qv_vqQtr
+n9S1T=vv_qQrtqnS9
+7_=h.
+U.SiBp=iBp_Zm1Q;_O
+RNH3Ds0CF_0R
+4;N#HR$VM_#Hl_8(R"4ddU(U4d4
+";N3HRs_0DFosHMCNlRv"1_Qqvt;q"
+RNH3lV#_FVslR#0"_1vqtvQq"Rd;H
+NR#3VlF_0#"0R1qv_vqQtR;U"
+RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j4jsjj4Rjjjj4sjj4R4jjjjjjjj4s444Rjjjjjjj4;s"
+RNH3lV#_HFsolMNC1R"vv_qQ"tq;H
+NR#3Vl0_#Ns0CC4oR;H
+NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9
+';s@R@(d:4U(:d:U4d:+dg41j:vv_qQrtqj9:(R:fjjNRlO7ERwbwRsRHl1qv_vqQtr
+69S1T=vv_qQrtq6S9
+7_=h4_c.HB
+SpBi=pmi_1_ZQON;
+HsR30_DC04FR;H
+NRM#$_lV#_RH8"d(4U4d(d"U4;H
+NR03sDs_FHNoMl"CR1qv_vqQt"N;
+HVR3#Vl_s#Fl01R"vv_qQRtqd
+";N3HRV_#l00F#Rv"1_QqvtUqR"N;
+HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N;
+HVR3#Fl_sMHoNRlC"_1vqtvQq
+";N3HRV_#l#00NCosCR
+4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R
+s@:@(4:dUd4(:ddU:gj+4:_1vqtvQq:rj(f9RjR:jlENORw7wRHbslvR1_Qqvtcqr9T
+S=_1vqtvQq9rc
+=S7hc_4j
+_HSiBp=iBp_Zm1Q;_O
+RNH3Ds0CF_0R
+4;N#HR$VM_#Hl_8(R"4ddU(U4d4
+";N3HRs_0DFosHMCNlRv"1_Qqvt;q"
+RNH3lV#_FVslR#0"_1vqtvQq"Rd;H
+NR#3VlF_0#"0R1qv_vqQtR;U"
+RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j4jsjj4Rjjjj4sjj4R4jjjjjjjj4s444Rjjjjjjj4;s"
+RNH3lV#_HFsolMNC1R"vv_qQ"tq;H
+NR#3Vl0_#Ns0CC4oR;H
+NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9
+';s@R@(d:4U(:d:U4d:+dg41j:vv_qQrtqj9:(R:fjjNRlO7ERwbwRsRHl1qv_vqQtr
+d9S1T=vv_qQrtqdS9
+7_=h4_dUHB
+SpBi=pmi_1_ZQON;
+HsR30_DC04FR;H
+NRM#$_lV#_RH8"d(4U4d(d"U4;H
+NR03sDs_FHNoMl"CR1qv_vqQt"N;
+HVR3#Vl_s#Fl01R"vv_qQRtqd
+";N3HRV_#l00F#Rv"1_QqvtUqR"N;
+HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N;
+HVR3#Fl_sMHoNRlC"_1vqtvQq
+";N3HRV_#l#00NCosCR
+4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R
+s@:@(4:dUd4(:ddU:gj+4:_1vqtvQq:rj(f9RjR:jlENORw7wRHbslvR1_Qqvt.qr9T
+S=_1vqtvQq9r.
+=S7hU_.dB
+SpBi=pmi_1_ZQON;
+HsR30_DC04FR;H
+NRM#$_lV#_RH8"d(4U4d(d"U4;H
+NR03sDs_FHNoMl"CR1qv_vqQt"N;
+HVR3#Vl_s#Fl01R"vv_qQRtqd
+";N3HRV_#l00F#Rv"1_QqvtUqR"N;
+HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N;
+HVR3#Fl_sMHoNRlC"_1vqtvQq
+";N3HRV_#l#00NCosCR
+4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R
+s@:@(4:dUd4(:ddU:gj+4:_1vqtvQq:rj(f9RjR:jlENORw7wRHbslvR1_Qqvt4qr9T
+S=_1vqtvQq9r4
+=S7hd_4c
+_HSiBp=iBp_Zm1Q;_O
+RNH3Ds0CF_0R
+4;N#HR$VM_#Hl_8(R"4ddU(U4d4
+";N3HRs_0DFosHMCNlRv"1_Qqvt;q"
+RNH3lV#_FVslR#0"_1vqtvQq"Rd;H
+NR#3VlF_0#"0R1qv_vqQtR;U"
+RNH3lV#_L0ND0C#Rj"jjjR4jjjjjjjsjj4R4jjjjsjjjR4jjjj4jjjjs4j4Rjjj4jjjjjs4jjRjjjj4j4jsjj4Rjjjj4sjj4R4jjjjjjjj4s444Rjjjjjjj4;s"
+RNH3lV#_HFsolMNC1R"vv_qQ"tq;H
+NR#3Vl0_#Ns0CC4oR;H
+NRs3FHMoH#N0Ml'CR1qv_vqQtr(j:9
+';s@R@(d:4U(:d:U4d:+dg41j:vv_qQrtqj9:(R:fjjNRlO7ERwbwRsRHl1qv_vqQtr
+j9S1T=vv_qQrtqjS9
+7_=h4_d.HB
+SpBi=pmi_1_ZQON;
+HsR30_DC04FR;H
+NRM#$_lV#_RH8"d(4U4d(d"U4;H
+NR03sDs_FHNoMl"CR1qv_vqQt"N;
+HVR3#Vl_s#Fl01R"vv_qQRtqd
+";N3HRV_#l00F#Rv"1_QqvtUqR"N;
+HVR3#0l_NCLD#"0RjRjj4jjjjjjjs4jjRjj4jjjjj4sjjjRj4jjjjjjs4j4Rjjj4jsjj4Rjjjjjj4jjjs44jRjjjjjj4j4s4jjRjjjjj44js4j4Rjjjjjsj4"N;
+HVR3#Fl_sMHoNRlC"_1vqtvQq
+";N3HRV_#l#00NCosCR
+4;N3HRFosHH0M#MCNlRv'1_Qqvtjqr:'(9;R
+s@:@(4:dUd4(:ddU:gj+4:kOb_0C#rjd:9jRf:ljRNROE7RwwblsHRkOb_0C#r
+.9SOT=bCk_#.0r97
+S=4h_6B
+SpBi=pmi_1_ZQON;
+HsR30FD_sMHoNRlC"kOb_0C#"N;
+HkR3MNVsOM_H8RCG.s;
+R(@@:U4d::d(4:dUd4g+jb:Ok#_C0:rdjf9RjR:jlENORw7wRHbslbROk#_C09rd
+=STO_bkCr#0dS9
+7_=h4Sn
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRb"Ok#_C0
+";N3HRksMVNHO_MG8CR
+d;s@R@(d:4U(:d:U4d:+dg4Qj:ujp_d.jr:Rj9fjj:ROlNEwR7wsRbHQlRujp_dwj7w9rj
+=STQ_upj_djO9rj
+=S7h4_d
+pSBip=Bi1_mZOQ_;H
+NR03sDs_FHNoMl"CRQ_upj"dj;H
+NRM3kVOsN_8HMCjGR;R
+s@:@(4:dUd4(:ddU:gj+4:pQu_jjdrj.:9jRf:ljRNROE7RwwblsHRpQu_jjd7rww4S9
+Tu=Qpd_jjr_O4S9
+7_=hdS.
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRu"Qpd_jj
+";N3HRksMVNHO_MG8CR
+4;s@R@(d:4U(:d:U4d:+dg4Qj:ujp_d.jr:Rj9fjj:ROlNEwR7wsRbHQlRujp_dwj7w9r.
+=STQ_upj_djO9r.
+=S7hd_d
+pSBip=Bi1_mZOQ_;H
+NR03sDs_FHNoMl"CRQ_upj"dj;H
+NRM3kVOsN_8HMC.GR;R
+s@:@(4:dUd4(:ddU:gj+4:pQu_r7j.9:jR:fjjNRlO7ERwbwRsRHlQ_up7jjr9T
+S=pQu_r7jjS9
+7_=h6S.
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRu"Qpj_7"N;
+HkR3MNVsOM_H8RCGjN;
+H#R3$HM_MPH0N"DR4
+";s@R@(d:4U(:d:U4d:+dg4Qj:u7p_j:r.jf9RjR:jlENORw7wRHbsluRQpj_7r
+49SQT=u7p_j9r4
+=S7hd_6
+pSBip=Bi1_mZOQ_;H
+NR03sDs_FHNoMl"CRQ_up7;j"
+RNH3VkMs_NOHCM8G;R4
+RNH3M#$_HHM0DPNR""4;R
+s@:@(4:dUd4(:ddU:gj+4:pQu_r7j.9:jR:fjjNRlO7ERwbwRsRHlQ_up7.jr9T
+S=pQu_r7j.S9
+7_=h6Sc
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRu"Qpj_7"N;
+HkR3MNVsOM_H8RCG.N;
+H#R3$HM_MPH0N"DR4
+";s@R@(d:4c4:n:c4d:+(64Bj:pji_jhj__h1YB4r4:Rj9fjj:ROlNEwR7wsRbHBlRpji_jhj__h1YB9r6
+=STB_pij_jjhY_1h6Br97
+S=iBp_jjj_1h_YrhBcS9
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRp"Bij_jj__h1BYh"N;
+HIR3NCsM8kbsMoHMR
+4;N3HRksMVNHO_MG8CR
+6;N3HR#_$MH0MHPRND";j"
+@sR@4(:dnc:4d:4c6:(+:4jB_pij_jjhY_1h4Br49:jR:fjjNRlO7ERwbwRsRHlB_pij_jjhY_1hnBr9T
+S=iBp_jjj_1h_YrhBnS9
+7p=Bij_jj__h1BYhr
+69SiBp=iBp_Zm1Q;_O
+RNH3Ds0_HFsolMNCBR"pji_jhj__h1YB
+";N3HRIMNsCs8bkMMHo;R4
+RNH3VkMs_NOHCM8G;Rn
+RNH3M#$_HHM0DPNR""j;R
+s@:@(4:dcn44:d(c:6j+4:iBp_jjj_1h_YrhB4j4:9jRf:ljRNROE7RwwblsHRiBp_jjj_1h_YrhB(S9
+Tp=Bij_jj__h1BYhr
+(9SB7=pji_jhj__h1YB9rn
+pSBip=Bi1_mZOQ_;H
+NR03sDs_FHNoMl"CRB_pij_jjhY_1h;B"
+RNH3sINMbC8sHkMM4oR;H
+NRM3kVOsN_8HMC(GR;H
+NR$3#MM_HHN0PDjR""s;
+R(@@:c4d::n44:dc(46+jp:Bij_jj__h1BYhr:44jf9RjR:jlENORw7wRHbslpRBij_jj__h1BYhr
+U9SBT=pji_jhj__h1YB9rU
+=S7B_pij_jjhY_1h(Br9B
+SpBi=pmi_1_ZQON;
+HsR30FD_sMHoNRlC"iBp_jjj_1h_Y"hB;H
+NRN3Is8MCbMskHRMo4N;
+HkR3MNVsOM_H8RCGUN;
+H#R3$HM_MPH0N"DRj
+";s@R@(d:4c4:n:c4d:+(64Bj:pji_jhj__h1YB4r4:Rj9fjj:ROlNEwR7wsRbHBlRpji_jhj__h1YB9rg
+=STB_pij_jjhY_1hgBr97
+S=iBp_jjj_1h_YrhBUS9
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRp"Bij_jj__h1BYh"N;
+HIR3NCsM8kbsMoHMR
+4;N3HRksMVNHO_MG8CR
+g;N3HR#_$MH0MHPRND";j"
+@sR@4(:dnc:4d:4c6:(+:4jB_pij_jjhY_1h4Br49:jR:fjjNRlO7ERwbwRsRHlB_pij_jjhY_1h4BrjS9
+Tp=Bij_jj__h1BYhr94j
+=S7B_pij_jjhY_1hgBr9B
+SpBi=pmi_1_ZQON;
+HsR30FD_sMHoNRlC"iBp_jjj_1h_Y"hB;H
+NRN3Is8MCbMskHRMo4N;
+HkR3MNVsOM_H8RCG4
+j;N3HR#_$MH0MHPRND";j"
+@sR@4(:dnc:4d:4c6:(+:4jB_pij_jjhY_1h4Br49:jR:fjjNRlO7ERwbwRsRHlB_pij_jjhY_1h4Br4S9
+Tp=Bij_jj__h1BYhr944
+=S7B_pij_jjhY_1h4BrjS9
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRp"Bij_jj__h1BYh"N;
+HIR3NCsM8kbsMoHMR
+4;N3HRksMVNHO_MG8CR;44
+RNH3M#$_HHM0DPNR""j;R
+s@:@(4:dUd4(:ddU:gj+4:BBYp7 _v4qr:Rj9fjj:ROlNEwR7wsRbHBlRY Bp_q7vr
+j9SBT=Y Bp_q7vr
+j9Sh7=_U.n_SH
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRY"BB_p 7"vq;H
+NRM3kVOsN_8HMCjGR;H
+NR$3#MM_HHN0PDjR""s;
+R(@@:U4d::d(4:dUd4g+jY:BB_p 7rvq49:jR:fjjNRlO7ERwbwRsRHlBpYB v_7q9r4
+=STBpYB v_7q9r4
+=S7hn_.(
+_HSiBp=iBp_Zm1Q;_O
+RNH3Ds0_HFsolMNCBR"Y Bp_q7v"N;
+HkR3MNVsOM_H8RCG4N;
+H#R3$HM_MPH0N"DRj
+";s@R@(d:4U(:d:U4d:+dg41j:Q_Z 7rvq49:jR:fjjNRlO7ERwbwRsRHl1 QZ_q7vr
+j9S1T=Q_Z 7rvqjS9
+7_=h4S4
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRQ"1Z7 _v;q"
+RNH3VkMs_NOHCM8G;Rj
+RNH3M#$_HHM0DPNR""4;R
+s@:@(4:dUd4(:ddU:gj+4:Z1Q v_7q:r4jf9RjR:jlENORw7wRHbslQR1Z7 _v4qr9T
+S=Z1Q v_7q9r4
+=S7h._4
+pSBip=Bi1_mZOQ_;H
+NR03sDs_FHNoMl"CR1 QZ_q7v"N;
+HkR3MNVsOM_H8RCG4N;
+H#R3$HM_MPH0N"DR4
+";s@R@(d:4U(:d:U4d:+dg4Oj:bCk_#d0r:Rj9fjj:ROlNEwR7wsRbHOlRbCk_#j0r9T
+S=kOb_0C#r
+j9Sh7=_g4U_SH
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRb"Ok#_C0
+";N3HRksMVNHO_MG8CR
+j;s@R@(d:4U(:d:U4d:+dg4Oj:bCk_#d0r:Rj9fjj:ROlNEwR7wsRbHOlRbCk_#40r9T
+S=kOb_0C#r
+49Sh7=_
+4cSiBp=iBp_Zm1Q;_O
+RNH3Ds0_HFsolMNCOR"bCk_#;0"
+RNH3VkMs_NOHCM8G;R4
+@sR@4(:ddd:cd:4dn:d+:4jB_pij_jjuY_1h4Brj9:jR:fjjNRlO7ERwbwRsRHlB_pij_jjuY_1h4Br9T
+S=iBp_jjj_1u_YrhB4S9
+7p=Bij_jj__u1BYhr
+j9SiBp=iBp_Zm1Q;_O
+RNH3Ds0_HFsolMNCBR"pji_juj__h1YB
+";N3HRIMNsCs8bkMMHo;R4
+RNH3VkMs_NOHCM8G;R4
+RNH3M#$_HHM0DPNR""j;R
+s@:@(4:ddd4c:ddd:nj+4:iBp_jjj_1u_YrhB4jj:9jRf:ljRNROE7RwwblsHRiBp_jjj_1u_YrhB.S9
+Tp=Bij_jj__u1BYhr
+.9SB7=pji_juj__h1YB9r4
+pSBip=Bi1_mZOQ_;H
+NR03sDs_FHNoMl"CRB_pij_jjuY_1h;B"
+RNH3sINMbC8sHkMM4oR;H
+NRM3kVOsN_8HMC.GR;H
+NR$3#MM_HHN0PDjR""s;
+R(@@:d4d::dc4:ddd4n+jp:Bij_jj__u1BYhr:4jjf9RjR:jlENORw7wRHbslpRBij_jj__u1BYhr
+d9SBT=pji_juj__h1YB9rd
+=S7B_pij_jjuY_1h.Br9B
+SpBi=pmi_1_ZQON;
+HsR30FD_sMHoNRlC"iBp_jjj_1u_Y"hB;H
+NRN3Is8MCbMskHRMo4N;
+HkR3MNVsOM_H8RCGdN;
+H#R3$HM_MPH0N"DRj
+";s@R@(d:4dc:d:d4d:+dn4Bj:pji_juj__h1YBjr4:Rj9fjj:ROlNEwR7wsRbHBlRpji_juj__h1YB9rc
+=STB_pij_jjuY_1hcBr97
+S=iBp_jjj_1u_YrhBdS9
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRp"Bij_jj__u1BYh"N;
+HIR3NCsM8kbsMoHMR
+4;N3HRksMVNHO_MG8CR
+c;N3HR#_$MH0MHPRND";j"
+@sR@4(:ddd:cd:4dn:d+:4jB_pij_jjuY_1h4Brj9:jR:fjjNRlO7ERwbwRsRHlB_pij_jjuY_1h6Br9T
+S=iBp_jjj_1u_YrhB6S9
+7p=Bij_jj__u1BYhr
+c9SiBp=iBp_Zm1Q;_O
+RNH3Ds0_HFsolMNCBR"pji_juj__h1YB
+";N3HRIMNsCs8bkMMHo;R4
+RNH3VkMs_NOHCM8G;R6
+RNH3M#$_HHM0DPNR""j;R
+s@:@(4:ddd4c:ddd:nj+4:iBp_jjj_1u_YrhB4jj:9jRf:ljRNROE7RwwblsHRiBp_jjj_1u_YrhBnS9
+Tp=Bij_jj__u1BYhr
+n9SB7=pji_juj__h1YB9r6
+pSBip=Bi1_mZOQ_;H
+NR03sDs_FHNoMl"CRB_pij_jjuY_1h;B"
+RNH3sINMbC8sHkMM4oR;H
+NRM3kVOsN_8HMCnGR;H
+NR$3#MM_HHN0PDjR""s;
+R(@@:d4d::dc4:ddd4n+jp:Bij_jj__u1BYhr:4jjf9RjR:jlENORw7wRHbslpRBij_jj__u1BYhr
+(9SBT=pji_juj__h1YB9r(
+=S7B_pij_jjuY_1hnBr9B
+SpBi=pmi_1_ZQON;
+HsR30FD_sMHoNRlC"iBp_jjj_1u_Y"hB;H
+NRN3Is8MCbMskHRMo4N;
+HkR3MNVsOM_H8RCG(N;
+H#R3$HM_MPH0N"DRj
+";s@R@(d:4dc:d:d4d:+dn4Bj:pji_juj__h1YBjr4:Rj9fjj:ROlNEwR7wsRbHBlRpji_juj__h1YB9rU
+=STB_pij_jjuY_1hUBr97
+S=iBp_jjj_1u_YrhB(S9
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRp"Bij_jj__u1BYh"N;
+HIR3NCsM8kbsMoHMR
+4;N3HRksMVNHO_MG8CR
+U;N3HR#_$MH0MHPRND";j"
+@sR@4(:ddd:cd:4dn:d+:4jB_pij_jjuY_1h4Brj9:jR:fjjNRlO7ERwbwRsRHlB_pij_jjuY_1hgBr9T
+S=iBp_jjj_1u_YrhBgS9
+7p=Bij_jj__u1BYhr
+U9SiBp=iBp_Zm1Q;_O
+RNH3Ds0_HFsolMNCBR"pji_juj__h1YB
+";N3HRIMNsCs8bkMMHo;R4
+RNH3VkMs_NOHCM8G;Rg
+RNH3M#$_HHM0DPNR""j;R
+s@:@(4:dcn44:d(c:6j+4:iBp_jjj_1h_YrhB4j4:9jRf:ljRNROE7RwwblsHRiBp_jjj_1h_YrhBjS9
+Tp=Bij_jj__h1BYhr
+j9Sh7=_(4c_SH
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRp"Bij_jj__h1BYh"N;
+HIR3NCsM8kbsMoHMR
+4;N3HRksMVNHO_MG8CR
+j;N3HR#_$MH0MHPRND";j"
+@sR@4(:dnc:4d:4c6:(+:4jB_pij_jjhY_1h4Br49:jR:fjjNRlO7ERwbwRsRHlB_pij_jjhY_1h4Br9T
+S=iBp_jjj_1h_YrhB4S9
+7p=Bij_jj__h1BYhr
+j9SiBp=iBp_Zm1Q;_O
+RNH3Ds0_HFsolMNCBR"pji_jhj__h1YB
+";N3HRIMNsCs8bkMMHo;R4
+RNH3VkMs_NOHCM8G;R4
+RNH3M#$_HHM0DPNR""j;R
+s@:@(4:dcn44:d(c:6j+4:iBp_jjj_1h_YrhB4j4:9jRf:ljRNROE7RwwblsHRiBp_jjj_1h_YrhB.S9
+Tp=Bij_jj__h1BYhr
+.9SB7=pji_jhj__h1YB9r4
+pSBip=Bi1_mZOQ_;H
+NR03sDs_FHNoMl"CRB_pij_jjhY_1h;B"
+RNH3sINMbC8sHkMM4oR;H
+NRM3kVOsN_8HMC.GR;H
+NR$3#MM_HHN0PDjR""s;
+R(@@:c4d::n44:dc(46+jp:Bij_jj__h1BYhr:44jf9RjR:jlENORw7wRHbslpRBij_jj__h1BYhr
+d9SBT=pji_jhj__h1YB9rd
+=S7B_pij_jjhY_1h.Br9B
+SpBi=pmi_1_ZQON;
+HsR30FD_sMHoNRlC"iBp_jjj_1h_Y"hB;H
+NRN3Is8MCbMskHRMo4N;
+HkR3MNVsOM_H8RCGdN;
+H#R3$HM_MPH0N"DRj
+";s@R@(d:4c4:n:c4d:+(64Bj:pji_jhj__h1YB4r4:Rj9fjj:ROlNEwR7wsRbHBlRpji_jhj__h1YB9rc
+=STB_pij_jjhY_1hcBr97
+S=iBp_jjj_1h_YrhBdS9
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRp"Bij_jj__h1BYh"N;
+HIR3NCsM8kbsMoHMR
+4;N3HRksMVNHO_MG8CR
+c;N3HR#_$MH0MHPRND";j"
+@sR@4(:ddU:(d:4Ug:d+:4j)_1a7rpY.9:jR:fjjNRlO7ERwbwRsRHl)_1a7rpYjS9
+T1=)ap_7Y9rj
+=S7hc_.6
+_HSiBp=iBp_Zm1Q;_O
+RNH3Ds0_HFsolMNC)R"17a_p;Y"
+RNH3M#$_HHM0DPNR""j;R
+s@:@(4:dUd4(:ddU:gj+4:a)1_Y7prj.:9jRf:ljRNROE7RwwblsHRa)1_Y7pr
+49S)T=17a_p4Yr97
+S=.h_cHc_
+pSBip=Bi1_mZOQ_;H
+NR03sDs_FHNoMl"CR)_1a7"pY;H
+NR$3#MM_HHN0PDjR""s;
+R(@@:U4d::d(4:dUd4g+j1:)ap_7Y:r.jf9RjR:jlENORw7wRHbsl1R)ap_7Y9r.
+=ST)_1a7rpY.S9
+7_=h._cdHB
+SpBi=pmi_1_ZQON;
+HsR30FD_sMHoNRlC"a)1_Y7p"N;
+H#R3$HM_MPH0N"DRj
+";s@R@(d:4dc:d:d4d:+dn4Bj:pji_juj__h1YBjr4:Rj9fjj:ROlNEwR7wsRbHBlRpji_juj__h1YB9rj
+=STB_pij_jjuY_1hjBr97
+S=dh_6H4_
+pSBip=Bi1_mZOQ_;H
+NR03sDs_FHNoMl"CRB_pij_jjuY_1h;B"
+RNH3sINMbC8sHkMM4oR;H
+NRM3kVOsN_8HMCjGR;H
+NR$3#MM_HHN0PDjR""s;
+R(@@:U4d::d(4:dUd4g+j1:7_jjj_q hARp fjj:ROlNEwR7wsRbH7lR1j_jjh_ q Ap
+=ST7j1_j j_hpqA 7
+S=nh_jB
+SpBi=pmi_1_ZQON;
+HsR30FD_sMHoNRlC"_71j_jj Ahqp; "
+RNH3M#$_HHM0DPNR""j;R
+s@:@(4:dUd4(:ddU:gj+4:_)Wj_jj7Rvqfjj:ROlNEwR7wsRbH)lRWj_jjv_7qT
+S=_)Wj_jj7
+vqSh7=_
+c4SiBp=iBp_Zm1Q;_O
+RNH3Ds0_HFsolMNC)R"Wj_jjv_7q
+";N3HR#_$MH0MHPRND";4"
+@sR@4(:ddU:(d:4Ug:d+:4j)jW_jQj_hfaRjR:jlENORw7wRHbslWR)_jjj_aQh
+=ST)jW_jQj_hSa
+7_=hcS.
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRW")_jjj_aQh"N;
+H#R3$HM_MPH0N"DR4
+";s@R@(d:4U(:d:U4d:+dg4pj:7j1_jQj_hfaRjR:jlENORw7wRHbsl7Rp1j_jjh_QaT
+S=1p7_jjj_aQh
+=S7hd_c
+pSBip=Bi1_mZOQ_;H
+NR03sDs_FHNoMl"CRp_71j_jjQ"ha;H
+NR$3#MM_HHN0PD4R""s;
+R(@@:U4d::d(4:dUd4g+jt:Aq_Bij_djQRhafjj:ROlNEwR7wsRbHAlRtiqB_jjd_aQh
+=STABtqid_jjh_Qa7
+S=ch_cB
+SpBi=pmi_1_ZQON;
+HsR30FD_sMHoNRlC"qAtBji_dQj_h;a"
+RNH3_HMDbFFR
+4;N3HR#_$MH0MHPRND";4"
+@sR@4(:ddU:(d:4Ug:d+:4jqj1_j7j_vfqRjR:jlENORw7wRHbsl1Rq_jjj_q7v
+=STqj1_j7j_vSq
+7_=hcSn
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlR1"q_jjj_q7v"N;
+H#R3$HM_MPH0N"DR4
+";s@R@(d:4U(:d:U4d:+dg4qj:1d_jjj_jjY_1hfBRjR:jlENORw7wRHbsl1Rq_jjd_jjj_h1YBT
+S=_q1j_djj_jj1BYh
+=S7h(_c
+pSBip=Bi1_mZOQ_;H
+NR03sDs_FHNoMl"CRqj1_djj_j1j_Y"hB;H
+NR$3#MM_HHN0PD4R""s;
+R(@@:U4d::d(4:dUd4g+j1:q_jjj_aQhR:fjjNRlO7ERwbwRsRHlqj1_jQj_hSa
+T1=q_jjj_aQh
+=S7hU_c
+pSBip=Bi1_mZOQ_;H
+NR03sDs_FHNoMl"CRqj1_jQj_h;a"
+RNH3M#$_HHM0DPNR""4;R
+s@:@(4:dUd4(:ddU:gj+4:q71B_i4QRhafjj:ROlNEwR7wsRbH7lR1iqB4h_QaT
+S=q71B_i4Q
+haSh7=_
+cgSiBp=iBp_Zm1Q;_O
+RNH3Ds0_HFsolMNC7R"1iqB4h_Qa
+";N3HR#_$MH0MHPRND";4"
+@sR@4(:ddU:(d:4Ug:d+:4j7j1_j7j_vfqRjR:jlENORw7wRHbsl1R7_jjj_q7v
+=ST7j1_j7j_vSq
+7_=h6Sj
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlR1"7_jjj_q7v"N;
+H#R3$HM_MPH0N"DR4
+";s@R@(d:4U(:d:U4d:+dg4qj:1d_jjj_7R:fjjNRlO7ERwbwRsRHlqj1_d7j_jT
+S=_q1j_dj7Sj
+7_=hd
+6USiBp=iBp_Zm1Q;_O
+RNH3Ds0_HFsolMNCqR"1d_jjj_7"N;
+H#R3$HM_MPH0N"DR4
+";s@R@(d:4U(:d:U4d:+dg4Mj: _Xu1Buq j_7R:fjjNRlO7ERwbwRsRHlMu X_q1uB7 _jT
+S=XM uu_1q_B 7Sj
+7_=h6S6
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlR "MX1u_u qB_"7j;H
+NR$3#MM_HHN0PDjR""s;
+R(@@:U4d::d(4:dUd4g+ju:eqR_7fjj:ROlNEwR7wsRbHelRu7q_
+=STe_uq77
+S=6h_nB
+SpBi=pmi_1_ZQON;
+HsR30FD_sMHoNRlC"qeu_;7"
+RNH3M#$_HHM0DPNR""4;R
+s@:@(4:dUd4(:ddU:gj+4:q7aB7i_jjRf:ljRNROE7RwwblsHRq7aB7i_jT
+S=q7aB7i_j7
+S=6h_(B
+SpBi=pmi_1_ZQON;
+HsR30FD_sMHoNRlC"q7aB7i_j
+";N3HR#_$MH0MHPRND";4"
+@sR@4(:ddU:(d:4Ug:d+:4jB_pij_dj]jRf:ljRNROE7RwwblsHRiBp_jjd_S]
+Tp=Bid_jj
+_]Sh7=_dd6_SH
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRp"Bid_jj"_];H
+NR$3#MM_HHN0PD4R""s;
+R(@@:U4d::d(4:dUd4g+j :)1_ amRzafjj:ROlNEwR7wsRbH)lR a1 _amz
+=ST)  1az_ma7
+S=.h_nHn_
+pSBip=Bi1_mZOQ_;H
+NR03sDs_FHNoMl"CR)  1az_ma
+";N3HR#_$MH0MHPRND";j"
+@sR@4(:.d.:n.:4.U:d+:4jB_pim_zau_) .f6RjR:jlENORw7wRHbslpRBiz_ma)_u 6_.
+=STB_pim_zau_) .S6
+7_=hdSj
+B=piB_pimQ1Z_
+O;N3HRs_0DFosHMCNlRp"Biz_ma)_u 6_."N;
+HHR3MF_DFdbR;H
+NR$3#MM_HHN0PD4R""s;
+R(@@:U4d::d(4:dUd4g+jt:A_jjjR:fjjNRlO7ERwbwRsRHlAjt_jwj7wT
+S=_Atj_jjO7
+S=dh_cB
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+NRM3H_FDFb;Rj
+@sR@4(:ddU:(d:4Ug:d+:4jqtvQqz_A1h_ q Ap_q7v_t]Q]jRf:ljRNROE7RwwblsHRQqvtAq_z 1_hpqA v_7qQ_]tS]
+Tv=qQ_tqA_z1 Ahqp7 _v]q_Q
+t]Sh7=_
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+RNH3Ds0_HFsolMNCqR"vqQt_1Az_q hA_p 7_vq]]Qt"N;
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+";s@R@(d:4U(:d:U4d:+dg4qj:vqQt_1Az_q hA_p 7_vqpRmWfjj:ROlNEwR7wsRbHqlRvqQt_1Az_q hA_p 7_vqp
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+NR$3#MM_HHN0PD4R""s;
+R(@@:U4d::d(4:dUd4g+jv:eqh_QajRf:ljRNROE7RwwblsHRqev_aQh
+=STe_vqQ
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+RNH3Ds0_HFsolMNCeR"vQq_h;a"
+RNH3_HMDbFFR
+c;N3HR#_$MH0MHPRND";4"
+@sR@4(:ddU:(d:4Ug:d+:4jz_71j_jjQRhafjj:ROlNEwR7wsRbHzlR7j1_jQj_hSa
+T7=z1j_jjh_Qa7
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+";s@R@(d:4U(:d:U4d:+dg4qj:jv_7qjRf:ljRNROE7RwwblsHR_qj7
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+R(@@:U4d::d(4:dUd4g+jt:Aq_Bij_djQ_ha7jRf:ljRNROE7RwwblsHRqAtBji_dQj_h7a_
+=STABtqid_jjh_Qa
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+S=iBp_jjj_
+h SB7=pji_jhj__h1YB4r49B
+SpBi=pmi_1_ZQON;
+HsR30FD_sMHoNRlC"iBp_jjj_"h ;H
+NR$3#MM_HHN0PDjR""s;
+R(@@:44c::dc4:c4d4n+jp:Biz_ma)_u j_6R:fjjNRlO7ERwbwRsRHlB_pim_zau_) 6Sj
+Tp=Biz_ma)_u j_6
+=S7B_pim_zau_) 6Hj_
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+RNH3M#$_HHM0DPNR""4;R
+s@:@(4:.6d46:.d6:(j+4:iBp_amz_aQhR:fjjNRlO7ERwbwRsRHlB_pim_zaQ
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+_7SiBp=iBp_Zm1Q;_O
+RNH3Ds0_HFsolMNCBR"pmi_zQa_h;a"
+RNH3M#$_HHM0DPNR""4;R
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+=STB_pij_jjh7 _j7
+S=iBp_jjj_
+h SiBp=iBp_Zm1Q;_O
+RNH3Ds0_HFsolMNCBR"pji_jhj_ j_7"N;
+H#R3$HM_MPH0N"DRj
+";s@R@(.:4nc:d:n4.:+dn4Bj:pmi_z a_XQu_hfaRjR:jlENORw7wRHbslpRBiz_maX_ uh_QaT
+S=iBp_amz_u X_aQh
+=S7B_pim_zau_) 6Sj
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+";N3HR#_$MH0MHPRND";4"
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+=Smqj1_jOj_
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+ Sm=.h_d
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+=Smp_71j_jjOQ
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+=Sm1 QZ_4Or9Q
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+=Smqr_OcS9
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+=Smqr_OUS9
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+ Sm=.h_d
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+=SmMu X_q1uBO _
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+fsRjR:jlENOR_AQ7RQ)blsHR)A )m
+S=)A )
+_OS=Qjt
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+ Sm=.kM.C_Ls
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+=SmAjt_jSj
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+=SmABtqid_jjQ
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+=SmABtqij_jj
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+=SmB_pij_djOQ
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+=SmB_pij_jjOQ
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+S=iBp_u X
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+=Smw_uzBS1
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+S=zwu_h1 1O _
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+=SmQ_upjrdjjS9
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+=SmQ_upO9r4
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+=SmqtvQqz_A1q_7a7q_QS)
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+=Smb_F#O\D	3DHb
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+=Smh4_.g
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+S=.h_4Sg
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+=Sm1 QZ_HO_r
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+=Smhg_d
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+c;sjRf:ljRNROEQRheblsHR.h_.H6_
+=Smh._.6
+_HS=Qjh._.6s;
+R:fjjNRlOQERhbeRsRHl1qv_vqQt_##s0H#__jH__nHr9m
+S=.h_US.
+Qhj=_..U_
+j;sjRf:ljRNROEQRheblsHR.h_.H4_
+=Smh._.4
+_HS=Qjh._.4s;
+R:fjjNRlOQERhbeRsRHlh._..
+_HShm=_..._SH
+Qhj=_...;R
+sfjj:ROlNEhRQesRbHhlR_g.4_SH
+m_=h._4gHQ
+Sj_=h.;4g
+fsRjR:jlENOReQhRHbsl_Rh._.jHm
+S=.h_.Hj_
+jSQ=.h_.
+j;sjRf:ljRNROEQRheblsHR_1vqtvQqs_##_0#H__Hjr_H.S9
+m_=h.
+UdS=QjhU_.d;_j
+fsRjR:jlENOReQhRHbsl_Rh._4nHm
+S=.h_4Hn_
+jSQ=.h_4
+n;sjRf:ljRNROEQRheblsHR.h_4HU_
+=Smh4_.U
+_HS=Qjh4_.Us;
+R:fjjNRlOQERhbeRsRHlO_bkC_#0.__jj__jH9r4
+=SmO_bkC_#0.9r4
+jSQ=kOb_0C#_j._r;49
+fsRjR:jlENOReQhRHbsl_Rhd_(dHm
+S=dh_(Hd_
+jSQ=dh_(
+d;sjRf:ljRNROEQRheblsHRdh_(H6_
+=Smh(_d6
+_HS=Qjh(_d6s;
+R:fjjNRlOQERhbeRsRHlb_F#O\D	3(kM_	OD_jjj__bCj__jHm
+S=#bF_	OD\M3k(D_O	j_jjC_b
+jSQ=#bF_	OD\M3k(D_O	j_jjC_b_
+j;sjRf:ljRNROEQRheblsHR4h_UHU_
+=SmhU_4U
+_HS=QjhU_4Us;
+R:fjjNRlOQERhbeRsRHlO_bkC_#0.__jj__jH9rd
+=SmO_bkC_#0.9rd
+jSQ=kOb_0C#_j._r;d9
+fsRjR:jlENOReQhRHbsl_Rh._((Hm
+S=.h_(H(_
+jSQ=.h_(
+(;sjRf:ljRNROEQRheblsHRdh_cHU_
+=Smhc_dU
+_HS=Qjhc_dUs;
+R:fjjNRlOQERhbeRsRHlO_bkC_#0.__jj__jH9r.
+=SmO_bkC_#0.9r.
+jSQ=kOb_0C#_j._r;.9
+fsRjR:jlENOReQhRHbslFRb#D_O	k\3MLn_od_jj__jNH.__SH
+m_=h4
+.US=Qjh._4U;_H
+fsRjR:jlENOReQhRHbsl_Rh4_gdHm
+S=4h_gHd_
+jSQ=4h_g
+d;sjRf:ljRNROEQRheblsHR.h_cH4_
+=Smhc_.4
+_HS=Qjhc_.4s;
+R:fjjNRlOQERhbeRsRHlhc_.j
+_HShm=_j.c_SH
+Qhj=_j.c;R
+sfjj:ROlNEhRQesRbHklRM14_vv_qQ_tqd__Hj__jHm
+S=4h_.Sc
+Qhj=_c4._
+j;sjRf:ljRNROEQRheblsHRq71B_i4Q_ha4J_#lNkG_jH__SH
+m_=h.
+ngS=Qjhn_.g;_j
+fsRjR:jlENOReQhRHbslMRk6H_OHHM_
+=Smk_M6OMHH_SH
+Qkj=MO6_H;HM
+fsRjR:jlENOReQhRHbslMRkUH_OHHM__jj__SH
+m_=hnS4
+Qhj=__n4js;
+R:fjjNRlOQERhbeRsRHlh._.U
+_HShm=_U.._SH
+Qhj=_U..;R
+sfjj:ROlNEhRQesRbH7lR1j_jjv_7q__.#kJlGjN___N.H
+_HShm=_6d6
+jSQ=dh_6j6_;R
+sfjj:ROlNEhRQesRbHhlR_n.._SH
+m_=h._.nHQ
+Sj_=h.;.n
+fsRjR:jlENOReQhRHbsl1R7q4Bi_aQh_#4_JGlkN__Hj._F_SH
+m_=h4
+6gS=Qjh6_4g;_j
+fsRjR:jlENOReQhRHbsl_Rhd_4UHm
+S=dh_4HU_
+jSQ=dh_4
+U;sjRf:ljRNROEQRheblsHRkOb_0C#_j.__jj___F.H9r.
+=Smh6_4nQ
+Sj_=h4_6nHs;
+R:fjjNRlOQERhbeRsRHlO_bkC_#0.__jj__jFH._r
+d9Shm=_c46
+jSQ=4h_6Hc_;R
+sfjj:ROlNEhRQesRbHBlRpmi_zua_)7 __SH
+mp=Biz_ma)_u __7HQ
+Sjp=Biz_ma)_u ;_7
+fsRjR:jlENOReQhRHbsl1R7q4Bi_aQh_#4_JGlkN__Hj._F_Hj_
+=Smh6_4.Q
+Sj_=h4_6.js;
+R:fjjNRlOQERhbeRsRHl1qv_vqQt_#M#_HH__jj___F.H9rj
+=Smh6_4jQ
+Sj_=h4_6jHs;
+R:fjjNRlOQERhbeRsRHlqj1_djj_j1j_Y_hBHm
+S=_q1j_djj_jj1BYh_SH
+Qqj=1d_jjj_jjY_1h
+B;sjRf:ljRNROEQRheblsHR_1vqtvQq#_M#__HH__jj._F_Hd_r
+j9Shm=_64c
+jSQ=4h_cH6_;R
+sfjj:ROlNEhRQesRbHhlR_4.U_SH
+m_=h._U4HQ
+Sj_=h.;U4
+fsRjR:jlENOReQhRHbsl_Rhd_j.Hm
+S=dh_jH._
+jSQ=dh_j
+.;sjRf:ljRNROEQRheblsHR.h_(Hg_
+=Smh(_.g
+_HS=Qjh(_.gs;
+R:fjjNRlOQERhbeRsRHlhU_.j
+_HShm=_j.U_SH
+Qhj=_j.U;R
+sfjj:ROlNEhRQesRbHklRMC6__jj__SH
+mM=k6
+_CS=Qjk_M6C;_j
+fsRjR:jlENOReQhRHbsl_Rh._(UHm
+S=.h_(HU_
+jSQ=.h_(
+U;sjRf:ljRNROEQRheblsHR_1vqtvQq#_M#__HH__jj._F_H._r
+j9Shm=_44U
+jSQ=4h_Uj4_;R
+sfjj:ROlNEhRQesRbH1lRvv_qQ_tq#0s##__Hj__jFH._r
+c9Shm=_U4(
+jSQ=4h_(jU_;R
+sfjj:ROlNEhRQesRbHqlRvqQt_1Az_q hA_p 7_vq]]Qt_#j_JGlkN__Hj__jFHd_
+=Smhg_n
+jSQ=nh_g;_j
+fsRjR:jlENOReQhRHbsl_Rhd_.gHm
+S=dh_.Hg_
+jSQ=dh_.
+g;sjRf:ljRNROEQRheblsHR_1vqtvQqs_##_0#H__Hj._F_.Hr9m
+S=4h_(S6
+Qhj=_64(_
+j;sjRf:ljRNROEQRheblsHR_1vqtvQqs_##_0#H__Hj._F_nHr9m
+S=4h_(Sc
+Qhj=_c4(_
+j;sjRf:ljRNROEQRheblsHR_1vqtvQq#_M#__HH__jj._F_H4_r
+j9Shm=_44(
+jSQ=4h_(j4_;R
+sfjj:ROlNEhRQesRbHklRM14_vv_qQ_tq6__jFd.___FdHm
+S=4kM__1vqtvQq
+_6S=Qjk_M41qv_vqQt_H6_;R
+sfjj:ROlNEhRQesRbHhlR_cd._SH
+m_=hd_.cHQ
+Sj_=hd;.c
+fsRjR:jlENOReQhRHbsl_Rhd_.nHm
+S=dh_.Hn_
+jSQ=dh_.
+n;sjRf:ljRNROEQRheblsHR_1vqtvQqs_##_0#H__jj._F_Hj_r
+d9Shm=_U4n
+jSQ=4h_nHU_;R
+sfjj:ROlNEhRQesRbHelRvQq_hHa_
+=Sme_vqQ_haHQ
+Sjv=eqh_Qas;
+R:fjjNRlOQERhbeRsRHl1qv_vqQt_#M#_HH__jj___F.jr_HjS9
+m_=h4
+n6S=Qjhn_46;_H
+fsRjR:jlENOReQhRHbslpRBij_jj__h1BYh_4HrjS9
+mp=Bij_jj__h1BYh_4HrjS9
+QBj=pji_jhj__h1YBjr49s;
+R:fjjNRlOQERhbeRsRHlh._d4
+_HShm=_4d._SH
+Qhj=_4d.;R
+sfjj:ROlNEhRQesRbHhlR_g4g_SH
+m_=h4_ggHQ
+Sj_=h4;gg
+fsRjR:jlENOReQhRHbsl R)1_ am_za.__Hj._F_SH
+m_=h4
+U.S=QjhU_4.;_j
+fsRjR:jlENOReQhRHbsl R)1_ am_za4J_#lNkG_jH__d4c_Fj_.
+_HShm=_U46
+jSQ=4h_6HU_;R
+sfjj:ROlNEhRQesRbH)lR17a_pCY_.__Hj._F_Hj_
+=Smhc_4UQ
+Sj_=h4_cUHs;
+R:fjjNRlOQERhbeRsRHlhj_d(
+_HShm=_(dj_SH
+Qhj=_(dj;R
+sfjj:ROlNEhRQesRbH)lR17a_pCY_.__Hj._F_SH
+m_=h4
+cdS=Qjhc_4d;_j
+fsRjR:jlENOReQhRHbsl_Rh._d6Hm
+S=.h_dH6_
+jSQ=.h_d
+6;sjRf:ljRNROEQRheblsHR.h_4Hj_
+=Smh4_.j
+_HS=Qjh4_.js;
+R:fjjNRlOQERhbeRsRHlhj_.(
+_HShm=_(.j_SH
+Qhj=_(.j;R
+sfjj:ROlNEhRQesRbHhlR_U.j_SH
+m_=h._jUHQ
+Sj_=h.;jU
+fsRjR:jlENOReQhRHbsl_Rh._jnHm
+S=.h_jHn_
+jSQ=.h_j
+n;sjRf:ljRNROEQRheblsHRdh_4Hd_
+=Smh4_dd
+_HS=Qjh4_dds;
+R:fjjNRlOQERhbeRsRHlh4_.4
+_HShm=_4.4_SH
+Qhj=_4.4;R
+sfjj:ROlNEhRQesRbHhlR_..4_SH
+m_=h._4.HQ
+Sj_=h.;4.
+fsRjR:jlENOReQhRHbslvR1_Qqvt#q_s##0_jH__Fj_.r_HdS9
+m_=h4
+UdS=QjhU_4d;_j
+fsRjR:jlENOReQhRHbsltRAq_Bij_djQ_ha4
+_HShm=_
+ccS=Qjhc_c_
+j;sjRf:ljRNROEQRheblsHR4h_g
+_HShm=__4gHQ
+Sj_=h4
+g;sjRf:ljRNROEQRheblsHR_)Wj_jj7_vq.
+_HShm=_
+c4S=Qjh4_c_
+j;sjRf:ljRNROEQRheblsHR.h_j
+_HShm=__.jHQ
+Sj_=h.
+j;sjRf:ljRNROEQRheblsHR_qj7_vq4
+_HShm=_
+cjS=Qjhj_c_
+j;sjRf:ljRNROEQRheblsHR.h_c
+_HShm=__.cHQ
+Sj_=h.
+c;sjRf:ljRNROEQRheblsHRQqvtAq_z 1_hpqA v_7qm_pW__4Hm
+S=dh_nQ
+Sj_=hdjn_;R
+sfjj:ROlNEhRQesRbHhlR__.6Hm
+S=.h_6
+_HS=Qjh6_.;R
+sfjj:ROlNEhRQesRbHqlRvqQt_1Az_q hA_p 7_vq]]Qt_H4_
+=Smh6_d
+jSQ=dh_6;_j
+fsRjR:jlENOReQhRHbsl_Rh4_gUHm
+S=4h_gHU_
+jSQ=4h_g
+U;sjRf:ljRNROEQRheblsHRa)1_Y7p__C.H__j.
+_HShm=_d.c_S.
+Qhj=_d.c_H._;R
+sfjj:ROlNEhRQesRbHhlR_n4g_SH
+m_=h4_gnHQ
+Sj_=h4;gn
+fsRjR:jlENOReQhRHbsl_Rh4_g6Hm
+S=4h_gH6_
+jSQ=4h_g
+6;sjRf:ljRNROEQRheblsHR.h_jH4_
+=Smhj_.4
+_HS=Qjhj_.4s;
+R:fjjNRlOQERhbeRsRHlhj_.j
+_HShm=_j.j_SH
+Qhj=_j.j;R
+sfjj:ROlNEhRQesRbHqlR1d_jjj_7_Hj___N.H
+_HShm=_Ud6
+jSQ=dh_6jU_;R
+sfjj:ROlNEhRQesRbHhlR_g.d_SH
+m_=h._dgHQ
+Sj_=h.;dg
+fsRjR:jlENOReQhRHbslFRb#D_O	1\3Q_Z 7_vqn__jj__jH9r4
+=Smb_F#O\D	3Z1Q v_7qr_n4S9
+Qbj=FO#_D3	\1 QZ_q7v_jn_r;49
+fsRjR:jlENOReQhRHbsl_Rh._dUHm
+S=.h_dHU_
+jSQ=.h_d
+U;sjRf:ljRNROEQRheblsHR#bF_	OD\Q31Z7 _vnq__jj__Hj_r
+j9Sbm=FO#_D3	\1 QZ_q7v_jnr9Q
+SjF=b#D_O	1\3Q_Z 7_vqnr_jj
+9;sjRf:ljRNROEQRheblsHR.h_dH(_
+=Smhd_.(
+_HS=Qjhd_.(s;
+R:fjjNRlOQERhbeRsRHlhd_.n
+_HShm=_n.d_SH
+Qhj=_n.d;R
+sfjj:ROlNEhRQesRbHqlRvqQt_1Az_a7qqQ_7)__jj__jHm
+S=QqvtAq_z71_q_aq7_Q)OQ
+Sjv=qQ_tqA_z17qqa_)7Q_jO_;R
+sfjj:ROlNEhRQesRbHhlR_4dd_SH
+m_=hd_d4HQ
+Sj_=hd;d4
+fsRjR:jlENOReQhRHbslFRb#D_O	k\3MLn_o	NO_jjj_jj__SH
+mF=b#D_O	k\3MLn_o	NO_jjj
+jSQ=#bF_	OD\M3kno_LN_O	j_jjjs;
+R:fjjNRlOQERhbeRsRHlqj1_j7j_v4q__l#Jk_GNj._N_HH_
+=Smh6_dnQ
+Sj_=hd_6njs;
+R:fjjNRlOQERhbeRsRHlkcM4_HNloLN_k8#_N_0N8_Hsj._N_HH_
+=Smh6_d.Q
+Sj_=hd_6.js;
+R:fjjNRlOQERhbeRsRHlh__UHm
+S=Uh__SH
+Qhj=_
+U;sjRf:ljRNROEQRheblsHR_q1j_jj7_vq4
+_HShm=_
+cnS=Qjhn_c_
+j;sjRf:ljRNROEQRheblsHR4h_j
+_HShm=__4jHQ
+Sj_=h4
+j;sjRf:ljRNROEQRheblsHR.h_dHd_
+=Smhd_.d
+_HS=Qjhd_.ds;
+R:fjjNRlOQERhbeRsRHlb_F#O\D	3dkM(#_N_jjd__8jH__HHm
+S=dh_6S(
+Qhj=_(d6_
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+m_=h.
+(jS=Qjh(_.j;_j
+fsRjR:jlENOReQhRHbsl1Rq_jjj_q7v_SH
+m1=q_jjj_q7v_SH
+Qqj=1j_jjv_7qs;
+R:fjjNRlOQERhbeRsRHlk_MnNj#_dHj__Hj_
+=Smhd_4(Q
+Sj_=h4_d(js;
+R:fjjNRlOQERhbeRsRHlh4_d.
+_HShm=_.d4_SH
+Qhj=_.d4;R
+sfjj:ROlNEhRQesRbHblRFO#_D3	\k_MdNj#_d8j_j__jFj.___FdHm
+S=#bF_	OD\M3kd#_N_jjd_
+8jS=Qjb_F#O\D	3dkM__N#j_dj8Hj_;R
+sfjj:ROlNEhRQesRbHblRFO#_D3	\kcM._NLoOj	_dHj_MH0__Hj___NdHd_F_SH
+m_=h4
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+fsRjR:jlENOReQhRHbslvR1_Qqvt#q_s##0_jH__Fj_.r_H4S9
+m_=h4
+(gS=Qjh(_4g;_j
+fsRjR:jlENOReQhRHbslvR1_Qqvt#q_s##0_jH__Fj_.r_H6S9
+m_=h4
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+fsRjR:jlENOReQhRHbslvR1_Qqvt#q_s##0_jH__Fj_.r_HjS9
+m_=h4
+UcS=QjhU_4c;_j
+fsRjR:jlENOReQhRHbslpRBid_jj__].__jNH.___F.Hm
+S=4h_US6
+Qhj=_64U_
+j;sjRf:ljRNROEQRheblsHR1z7_jjj_HO_
+=Smz_71j_jjO
+_HS=Qjz_71j_jjOs;
+R:fjjNRlOQERhbeRsRHlp_71j_jjO
+_HSpm=7j1_jOj__SH
+Qpj=7j1_jOj_;R
+sfjj:ROlNEhRQesRbHblRFO#_D3	\1 QZ_q7v_jn__jj___F.H9rj
+=Smh(_4dQ
+Sj_=h4_(dHs;
+R:fjjNRlOQERhbeRsRHle_uqO
+_HSem=uOq__SH
+Qej=uOq_;R
+sfjj:ROlNEhRQesRbHelRu7q__Hj_
+=Smhn_6
+jSQ=6h_n;_j
+fsRjR:jlENOReQhRHbslaR7q_BiO
+_HS7m=aiqB_HO_
+jSQ=q7aBOi_;R
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+_HShm=_
+6(S=Qjh(_6_
+j;sjRf:ljRNROEQRheblsHRpQu_HO_r
+49SQm=uOp__4Hr9Q
+Sju=Qpr_O4
+9;sjRf:ljRNROEQRheblsHRpQu__7jjr_H4S9
+m_=h6Sd
+Qhj=__6djs;
+R:fjjNRlOQERhbeRsRHlQ_upOr_H.S9
+mu=Qp__OH9r.
+jSQ=pQu_.Or9s;
+R:fjjNRlOQERhbeRsRHlQ_up7jj__.Hr9m
+S=6h_cQ
+Sj_=h6jc_;R
+sfjj:ROlNEhRQesRbHhlR__.UHm
+S=.h_U
+_HS=QjhU_.;R
+sfjj:ROlNEhRQesRbHQlRujp_d4j__4Hr9m
+S=dh_.Q
+Sj_=hdj._;R
+sfjj:ROlNEhRQesRbHhlR__.gHm
+S=.h_g
+_HS=Qjhg_.;R
+sfjj:ROlNEhRQesRbHQlRujp_d4j__.Hr9m
+S=dh_dQ
+Sj_=hdjd_;R
+sfjj:ROlNEhRQesRbHhlR_Ud(_SH
+m_=hd_(UHQ
+Sj_=hd;(U
+fsRjR:jlENOReQhRHbsl_Rh._.(Hm
+S=.h_.H(_
+jSQ=.h_.
+(;sjRf:ljRNROEQRheblsHR#bF_	OD\137_jjj_q7v_Vc_j__HNH.__SH
+m_=hd
+6cS=Qjh6_dc;_j
+fsRjR:jlENOReQhRHbsl_Rh(
+_HShm=_H(_
+jSQ=(h_;R
+sfjj:ROlNEhRQesRbHqlR1d_jjj_jjY_1h4B__SH
+m_=hcS(
+Qhj=__c(js;
+R:fjjNRlOQERhbeRsRHlh__6Hm
+S=6h__SH
+Qhj=_
+6;sjRf:ljRNROEQRheblsHR_q1j_jjQ_ha4
+_HShm=_
+cUS=QjhU_c_
+j;sjRf:ljRNROEQRheblsHRdh__SH
+m_=hd
+_HS=Qjh;_d
+fsRjR:jlENOReQhRHbsl1R7_jjj_q7v_H4_
+=Smhj_6
+jSQ=6h_j;_j
+fsRjR:jlENOReQhRHbsl RMX1u_u qB_HO_
+=SmMu X_q1uBO __SH
+QMj= _Xu1Buq ;_O
+fsRjR:jlENOReQhRHbsl RMX1u_u qB__7jj
+_HShm=_
+66S=Qjh6_6_
+j;sjRf:ljRNROEQRheblsHR4Q_gSd
+m1=q_jjj_SH
+Qqj=1j_jj;_O
+fsRjR:jlENOReQhRHbsl1R7_jjj_q7v_SH
+m1=7_jjj_q7v_SH
+Q7j=1j_jjv_7qs;
+R:fjjNRlOqERhR7.blsHRnkM__8#j
+djSkm=M8n_#d_jjQ
+Sj1=q_jjj_SH
+Q74=1j_jjv_7q;_H
+fsRjR:jlENOReQhRHbsl_Rh4_gjHm
+S=4h_gHj_
+jSQ=4h_g
+j;sjRf:ljRNROEQRheblsHR4kM_HNloLN_kC#_MDNLCF_DI
+_HSkm=MN4_lNHo_#Lk_NCML_DCD_FIHQ
+SjM=k4l_NH_oNL_k#CLMNDDC_F
+I;sjRf:ljRNROEQRheblsHR.kM4b_Vk#_O_SH
+mM=k.V4_bOk_#
+_HS=Qjk4M._kVb_;O#
+fsRjR:jlENOReQhRHbslpRBiz_maX_ uh_Qa
+_HSBm=pmi_z a_XQu_hHa_
+jSQ=iBp_amz_u X_aQh;R
+sfjj:ROlNEhRQesRbHQlRujp_djj__34_sm
+S=pQu_jjd_4j__M3kdQ
+SjF=b#D_O	H\3b
+D;sjRf:ljRNROEq.h7RHbsluRQpd_jj__j4l_3
+=SmQ_upj_djj__434kM
+jSQ=pQu_4Or9Q
+S4F=b#D_O	H\3b
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+=Sm7j1_j j_hpqA __4#kJlG4N_
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+=Smh4_.d
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+=Smh6_4
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+=SmO_bkC_#0j__d3jkM
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+=SmQ_upj_djj__j3dkM
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+=Sm)jW_jQj_hja_3jkM
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+=SmAjt_jjj_3dkM
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+=Smhn_.
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+=Smp_71j_jjQ_haHQ
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+=Smk_McD_8#j
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+sfjj:ROlNEhRQesRbH7lR1j_jjh_ q Ap_sj3
+=Sm7j1_j j_hpqA 3_jk
+MdS=Qj7j1_j j_hpqA __4#kJlG4N_;R
+sfjj:ROlNEhRq7b.RsRHl7j1_j j_hpqA 3_jlm
+S=_71j_jj Ahqpj _34kM
+jSQ=_71j_jj AhqpS 
+Q74=1j_jjh_ q Ap_#4_JGlkN;_4
+fsRjR:jlENOR7qh.sRbH7lR1j_jjh_ q Ap_Mj3
+=Sm7j1_j j_hpqA 3_jk
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+4SQ=_71j_jj Ahqpj _3dkM;R
+sfjj:ROlNE)Rm.sRbH7lR1j_jjh_ q Ap_bj3
+=Smh
+_nS=Qj7j1_j j_hpqA 3_jk
+M4S=Q47j1_j j_hpqA 3_jk;Mj
+fsRjR:jlENOReQhRHbsl7Rp1j_jjh_Qa3_jsm
+S=1p7_jjj_aQh_kj3MSd
+Q1j=vv_qQrtqn
+9;sjRf:ljRNROEq.h7RHbsl7Rp1j_jjh_Qa3_jlm
+S=1p7_jjj_aQh_kj3MS4
+Qbj=FO#_D3	\k_MU#Nl_lNHo_SH
+Q14=vv_qQrtqn
+9;sjRf:ljRNROEq.h7RHbsl7Rp1j_jjh_Qa3_jMm
+S=1p7_jjj_aQh_kj3MSj
+Qpj=7j1_jQj_hSa
+Qp4=7j1_jQj_hja_3dkM;R
+sfjj:ROlNE)Rm.sRbHplR7j1_jQj_hja_3Sb
+m_=h4S(
+Qpj=7j1_jQj_hja_34kM
+4SQ=1p7_jjj_aQh_kj3M
+j;
+
+@ 
diff --git a/Logic/BUS68030.srr b/Logic/BUS68030.srr
new file mode 100644
index 0000000..d0b1a72
--- /dev/null
+++ b/Logic/BUS68030.srr
@@ -0,0 +1,107 @@
+#Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
+#install: C:\ispLever\synpbase
+#OS: Windows 7 6.2
+#Hostname: DEEPTHOUGHT
+
+#Implementation: logic
+
+$ Start of Compile
+#Sun Jan 24 16:20:47 2016
+
+Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
+@N|Running in 64-bit mode
+Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
+
+@N: CD720 :"C:\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
+@N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
+File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
+VHDL syntax check successful!
+File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
+@N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral 
+@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":65:10:65:11|Using sequential encoding for type sm_e
+@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000
+@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven 
+Post processing for work.bus68030.behavioral
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register DS_030_D0_3  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register AMIGA_BUS_ENABLE_INT_4  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D4_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D3_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D2_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2  
+@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
+@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
+@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register SM_AMIGA
+Extracted state machine for register SM_AMIGA
+State machine has 8 reachable states with original encodings of:
+   000
+   001
+   010
+   011
+   100
+   101
+   110
+   111
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register cpu_est
+@W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused 
+@END
+
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Jan 24 16:20:47 2016
+
+###########################################################]
+Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
+@N|Running in 64-bit mode
+File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
+
+At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Jan 24 16:20:48 2016
+
+###########################################################]
+Map & Optimize Report
+
+Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014
+Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
+Product Version I-2014.03LC 
+@N: MF248 |Running in 64-bit mode.
+@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
+Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
+original code -> new code
+   000 -> 00000000
+   001 -> 00000011
+   010 -> 00000101
+   011 -> 00001001
+   100 -> 00010001
+   101 -> 00100001
+   110 -> 01000001
+   111 -> 10000001
+@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE
+---------------------------------------
+Resource Usage Report
+
+Simple gate primitives:
+DFF             80 uses
+BI_DIR          10 uses
+BUFTH           4 uses
+IBUF            46 uses
+OBUF            15 uses
+AND2            297 uses
+INV             261 uses
+OR2             27 uses
+XOR2            8 uses
+
+
+@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
+I-2014.03LC 
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Jan 24 16:20:49 2016
+
+###########################################################]
diff --git a/Logic/BUS68030.srs b/Logic/BUS68030.srs
new file mode 100644
index 0000000..f26060f
Binary files /dev/null and b/Logic/BUS68030.srs differ
diff --git a/Logic/Programming.xcf b/Logic/Programming.xcf
index 0fa282d..d379cff 100644
--- a/Logic/Programming.xcf
+++ b/Logic/Programming.xcf
@@ -18,9 +18,9 @@
 				<BScanLen>1</BScanLen>
 				<BScanVal>0</BScanVal>
 			</Bypass>
-			<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk.jed</File>
-			<FileTime>07/09/15 18:49:07</FileTime>
-			<JedecChecksum>0x42BE</JedecChecksum>
+			<File>C:\Users\Matze\Documents\GitHub\68030tk\Logic\68030_tk-50MHz.jed</File>
+			<FileTime>10/10/15 21:57:01</FileTime>
+			<JedecChecksum>0x5646</JedecChecksum>
 			<Operation>Erase,Program,Verify</Operation>
 			<Option>
 				<SVFVendor>JTAG STANDARD</SVFVendor>
diff --git a/Logic/automake.err b/Logic/automake.err
new file mode 100644
index 0000000..f964a6e
--- /dev/null
+++ b/Logic/automake.err
@@ -0,0 +1 @@
+Need not generate svf file according to the constraints, exit
diff --git a/Logic/bus68030.exf b/Logic/bus68030.exf
new file mode 100644
index 0000000..05fea8f
--- /dev/null
+++ b/Logic/bus68030.exf
@@ -0,0 +1,772 @@
+Section Type   Array Num   Name                     Real Name          Base     Number     Increment
+// -------------------------------------------------------------------------------------------------
+      Port          1      A(31:2)                        A                 31         30            -1
+      Port          2      IPL(2:0)                      IPL                  2          3            -1
+      Port          3      FC(1:0)                       FC                  1          2            -1
+      Port          4      IPL_030(2:0)                  IPL_030                  2          3            -1
+      Port          5      SIZE(1:0)                     SIZE                  1          2            -1
+End
+Section Member   Rename                   Array-Notation          Array Number     Index
+// -------------------------------------------------------------------------------------
+        Port      SIZE_1_                     SIZE[1]                       5            0            
+        Port      SIZE_0_                     SIZE[0]                       5            1            
+        Port      A_31_                        A[31]                       1            0            
+        Port      A_30_                        A[30]                       1            1            
+        Port      A_29_                        A[29]                       1            2            
+        Port      A_28_                        A[28]                       1            3            
+        Port      A_27_                        A[27]                       1            4            
+        Port      A_26_                        A[26]                       1            5            
+        Port      A_25_                        A[25]                       1            6            
+        Port      A_24_                        A[24]                       1            7            
+        Port      A_23_                        A[23]                       1            8            
+        Port      A_22_                        A[22]                       1            9            
+        Port      A_21_                        A[21]                       1            10            
+        Port      A_20_                        A[20]                       1            11            
+        Port      A_19_                        A[19]                       1            12            
+        Port      A_18_                        A[18]                       1            13            
+        Port      A_17_                        A[17]                       1            14            
+        Port      A_16_                        A[16]                       1            15            
+        Port      A_15_                        A[15]                       1            16            
+        Port      A_14_                        A[14]                       1            17            
+        Port      A_13_                        A[13]                       1            18            
+        Port      A_12_                        A[12]                       1            19            
+        Port      A_11_                        A[11]                       1            20            
+        Port      A_10_                        A[10]                       1            21            
+        Port      A_9_                        A[9]                       1            22            
+        Port      A_8_                        A[8]                       1            23            
+        Port      A_7_                        A[7]                       1            24            
+        Port      A_6_                        A[6]                       1            25            
+        Port      A_5_                        A[5]                       1            26            
+        Port      A_4_                        A[4]                       1            27            
+        Port      A_3_                        A[3]                       1            28            
+        Port      A_2_                        A[2]                       1            29            
+        Port      IPL_030_2_                  IPL_030[2]                       4            0            
+        Port      IPL_030_1_                  IPL_030[1]                       4            1            
+        Port      IPL_030_0_                  IPL_030[0]                       4            2            
+        Port      IPL_2_                      IPL[2]                       2            0            
+        Port      IPL_1_                      IPL[1]                       2            1            
+        Port      IPL_0_                      IPL[0]                       2            2            
+        Port      FC_1_                       FC[1]                       3            0            
+        Port      FC_0_                       FC[0]                       3            1            
+End
+Section Cross Reference File
+Design 'BUS68030' created Sun Jan 24 16:20:54 2016
+   Type              New Name                               Original Name
+// ----------------------------------------------------------------------
+   Inst                i_z3U3U                                  AS_030
+   Inst                i_z3V3V                                  AS_000
+   Inst                i_z4040                                  RW_000
+   Inst                i_z4141                                  DS_030
+   Inst                i_z4242                                 UDS_000
+   Inst                i_z4343                                 LDS_000
+   Inst                i_z5454                                      A0
+   Inst                i_z5757                                    BERR
+   Inst                i_z5P5P                                  DSACK1
+   Inst                i_z6060                                   RESET
+   Inst                i_z6161                                      RW
+   Inst                i_z6868                                    CIIN
+   Inst         cpu_est_0_1__r                            cpu_est_0_1_.r
+   Inst          SM_AMIGA_i_4_                             SM_AMIGA_i[4]
+   Inst         cpu_est_0_1__m                            cpu_est_0_1_.m
+   Inst   SM_AMIGA_srsts_i_0_0_a3_0_4_              SM_AMIGA_srsts_i_0_0_a3_0[4]
+   Inst         cpu_est_0_1__n                            cpu_est_0_1_.n
+   Inst          SM_AMIGA_i_0_                             SM_AMIGA_i[0]
+   Inst         cpu_est_0_1__p                            cpu_est_0_1_.p
+   Inst   SM_AMIGA_srsts_i_0_0_a3_0_                SM_AMIGA_srsts_i_0_0_a3[0]
+   Inst          SM_AMIGA_i_6_                             SM_AMIGA_i[6]
+   Inst   SM_AMIGA_srsts_i_0_0_a3_5_                SM_AMIGA_srsts_i_0_0_a3[5]
+   Inst     pos_clk_un8_bg_030                        pos_clk.un8_bg_030
+   Inst         IPL_030_0_2__r                            IPL_030_0_2_.r
+   Inst         IPL_030_0_2__m                            IPL_030_0_2_.m
+   Inst         IPL_030_0_2__n                            IPL_030_0_2_.n
+   Inst   pos_clk_un37_as_030_d0_i_a2_1_1           pos_clk.un37_as_030_d0_i_a2_1_1
+   Inst         IPL_030_0_2__p                            IPL_030_0_2_.p
+   Inst   pos_clk_un37_as_030_d0_i_a2_1_2           pos_clk.un37_as_030_d0_i_a2_1_2
+   Inst          SM_AMIGA_i_1_                             SM_AMIGA_i[1]
+   Inst         DSACK1_INT_0_r                            DSACK1_INT_0.r
+   Inst   pos_clk_un7_clk_000_pe_0_0_a3_0_2         pos_clk.un7_clk_000_pe_0_0_a3_0_2
+   Inst   SM_AMIGA_srsts_i_0_0_o2_1_                SM_AMIGA_srsts_i_0_0_o2[1]
+   Inst         DSACK1_INT_0_m                            DSACK1_INT_0.m
+   Inst   pos_clk_un7_clk_000_pe_0_0_a3_0           pos_clk.un7_clk_000_pe_0_0_a3_0
+   Inst         DSACK1_INT_0_n                            DSACK1_INT_0.n
+   Inst   pos_clk_un7_clk_000_pe_0_0_a3_1           pos_clk.un7_clk_000_pe_0_0_a3_1
+   Inst   pos_clk_un3_as_030_d0_0_o2_0_o3           pos_clk.un3_as_030_d0_0_o2_0_o3
+   Inst         DSACK1_INT_0_p                            DSACK1_INT_0.p
+   Inst   pos_clk_un7_clk_000_pe_0_0_a3_2           pos_clk.un7_clk_000_pe_0_0_a3_2
+   Inst   pos_clk_un24_bgack_030_int_i_0_i_a3_i_x2  pos_clk.un24_bgack_030_int_i_0_i_a3_i_x2
+   Inst      DS_000_ENABLE_0_r                         DS_000_ENABLE_0.r
+   Inst   pos_clk_un7_clk_000_pe_0_0_a3             pos_clk.un7_clk_000_pe_0_0_a3
+   Inst      DS_000_ENABLE_0_m                         DS_000_ENABLE_0.m
+   Inst   SM_AMIGA_nss_i_i_0_0_a3_2_1_0_            SM_AMIGA_nss_i_i_0_0_a3_2_1[0]
+   Inst      DS_000_ENABLE_0_n                         DS_000_ENABLE_0.n
+   Inst   SM_AMIGA_nss_i_i_0_0_a3_2_2_0_            SM_AMIGA_nss_i_i_0_0_a3_2_2[0]
+   Inst   pos_clk_un37_as_030_d0_i_i                pos_clk.un37_as_030_d0_i_i
+   Inst      DS_000_ENABLE_0_p                         DS_000_ENABLE_0.p
+   Inst   SM_AMIGA_nss_i_i_0_0_a3_2_3_0_            SM_AMIGA_nss_i_i_0_0_a3_2_3[0]
+   Inst   pos_clk_DS_000_DMA_4_f0_i_a2_i            pos_clk.DS_000_DMA_4_f0_i_a2_i
+   Inst        LDS_000_INT_0_r                           LDS_000_INT_0.r
+   Inst   SM_AMIGA_nss_i_i_0_0_a3_2_0_              SM_AMIGA_nss_i_i_0_0_a3_2[0]
+   Inst        LDS_000_INT_0_m                           LDS_000_INT_0.m
+   Inst   pos_clk_CLK_000_P_SYNC_2_0_a2_i_0_        pos_clk.CLK_000_P_SYNC_2_0_a2_i[0]
+   Inst        LDS_000_INT_0_n                           LDS_000_INT_0.n
+   Inst   SM_AMIGA_srsts_i_0_0_0_                   SM_AMIGA_srsts_i_0_0[0]
+   Inst        LDS_000_INT_0_p                           LDS_000_INT_0.p
+   Inst   pos_clk_un24_bgack_030_int_i_0_i_a3_i_a2  pos_clk.un24_bgack_030_int_i_0_i_a3_i_a2
+   Inst          SM_AMIGA_i_2_                             SM_AMIGA_i[2]
+   Inst   SM_AMIGA_srsts_i_0_0_a3_1_                SM_AMIGA_srsts_i_0_0_a3[1]
+   Inst   un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__r  un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0_.r
+   Inst   SM_AMIGA_nss_i_i_0_0_o2_0_                SM_AMIGA_nss_i_i_0_0_o2[0]
+   Inst   un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__m  un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0_.m
+   Inst   un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__n  un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0_.n
+   Inst   un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0__p  un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0_.p
+   Inst   SM_AMIGA_srsts_i_0_0_1_3_                 SM_AMIGA_srsts_i_0_0_1[3]
+   Inst   SM_AMIGA_srsts_i_0_0_2_3_                 SM_AMIGA_srsts_i_0_0_2[3]
+   Inst   SM_AMIGA_srsts_i_0_0_3_                   SM_AMIGA_srsts_i_0_0[3]
+   Inst   SM_AMIGA_nss_i_i_0_0_1_0_                 SM_AMIGA_nss_i_i_0_0_1[0]
+   Inst   SM_AMIGA_nss_i_i_0_0_2_0_                 SM_AMIGA_nss_i_i_0_0_2[0]
+   Inst        SM_AMIGA_i_i_7_                           SM_AMIGA_i_i[7]
+   Inst   SM_AMIGA_nss_i_i_0_0_3_0_                 SM_AMIGA_nss_i_i_0_0_3[0]
+   Inst   SM_AMIGA_nss_i_i_0_0_0_                   SM_AMIGA_nss_i_i_0_0[0]
+   Inst   SM_AMIGA_srsts_i_0_0_m3_1__r              SM_AMIGA_srsts_i_0_0_m3_1_.r
+   Inst   SM_AMIGA_srsts_i_i_0_a3_0_1_2_            SM_AMIGA_srsts_i_i_0_a3_0_1[2]
+   Inst   SM_AMIGA_srsts_i_0_0_m3_1__m              SM_AMIGA_srsts_i_0_0_m3_1_.m
+   Inst   SM_AMIGA_srsts_i_i_0_a3_0_2_2_            SM_AMIGA_srsts_i_i_0_a3_0_2[2]
+   Inst   SM_AMIGA_srsts_i_0_0_m3_1__n              SM_AMIGA_srsts_i_0_0_m3_1_.n
+   Inst   SM_AMIGA_srsts_i_i_0_a3_0_2_              SM_AMIGA_srsts_i_i_0_a3_0[2]
+   Inst   SM_AMIGA_srsts_i_0_0_m3_1__p              SM_AMIGA_srsts_i_0_0_m3_1_.p
+   Inst   pos_clk_un7_clk_000_pe_0_0_a3_0_1         pos_clk.un7_clk_000_pe_0_0_a3_0_1
+   Inst   pos_clk_CYCLE_DMA_5_1_i_0_x2              pos_clk.CYCLE_DMA_5_1_i_0_x2
+   Inst   pos_clk_CYCLE_DMA_5_0_i_0_x2              pos_clk.CYCLE_DMA_5_0_i_0_x2
+   Inst          SM_AMIGA_i_7_                             SM_AMIGA_i[7]
+   Inst            SM_AMIGA_6_                               SM_AMIGA[6]
+   Inst   SM_AMIGA_srsts_i_0_0_m3_5__r              SM_AMIGA_srsts_i_0_0_m3_5_.r
+   Inst            SM_AMIGA_5_                               SM_AMIGA[5]
+   Inst   SM_AMIGA_srsts_i_0_0_m3_5__m              SM_AMIGA_srsts_i_0_0_m3_5_.m
+   Inst            SM_AMIGA_4_                               SM_AMIGA[4]
+   Inst   SM_AMIGA_srsts_i_0_0_m3_5__n              SM_AMIGA_srsts_i_0_0_m3_5_.n
+   Inst            SM_AMIGA_3_                               SM_AMIGA[3]
+   Inst   pos_clk_un8_bg_030_i                      pos_clk.un8_bg_030_i
+   Inst   SM_AMIGA_srsts_i_0_0_m3_5__p              SM_AMIGA_srsts_i_0_0_m3_5_.p
+   Inst            SM_AMIGA_2_                               SM_AMIGA[2]
+   Inst   pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3_1  pos_clk.un24_bgack_030_int_i_0_i_a3_i_o3_1
+   Inst   SM_AMIGA_srsts_i_0_0_o2_0_                SM_AMIGA_srsts_i_0_0_o2[0]
+   Inst            SM_AMIGA_1_                               SM_AMIGA[1]
+   Inst   pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3_2  pos_clk.un24_bgack_030_int_i_0_i_a3_i_o3_2
+   Inst   SM_AMIGA_srsts_i_0_0_o2_5_                SM_AMIGA_srsts_i_0_0_o2[5]
+   Inst            SM_AMIGA_0_                               SM_AMIGA[0]
+   Inst   pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3  pos_clk.un24_bgack_030_int_i_0_i_a3_i_o3
+   Inst             cpu_est_2_                                cpu_est[2]
+   Inst   pos_clk_un8_sm_amiga_1                    pos_clk.un8_sm_amiga_1
+   Inst   pos_clk_AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3  pos_clk.AMIGA_BUS_ENABLE_DMA_HIGH_3_i_a2_0_a3
+   Inst             cpu_est_3_                                cpu_est[3]
+   Inst   pos_clk_un8_sm_amiga                      pos_clk.un8_sm_amiga
+   Inst   pos_clk_AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3  pos_clk.AMIGA_BUS_ENABLE_DMA_LOW_3_i_a2_0_a3
+   Inst          IPL_030DFF_0_                             IPL_030DFF[0]
+   Inst   SM_AMIGA_srsts_i_0_0_a2_0_1_3_            SM_AMIGA_srsts_i_0_0_a2_0_1[3]
+   Inst          IPL_030DFF_1_                             IPL_030DFF[1]
+   Inst   SM_AMIGA_srsts_i_0_0_a2_0_2_3_            SM_AMIGA_srsts_i_0_0_a2_0_2[3]
+   Inst   pos_clk_un6_bgack_000_0_0_a2              pos_clk.un6_bgack_000_0_0_a2
+   Inst          IPL_030DFF_2_                             IPL_030DFF[2]
+   Inst   SM_AMIGA_srsts_i_0_0_a2_0_3_              SM_AMIGA_srsts_i_0_0_a2_0[3]
+   Inst              IPL_D0_0_                                 IPL_D0[0]
+   Inst   SM_AMIGA_nss_i_i_0_0_o2_1_0_0_            SM_AMIGA_nss_i_i_0_0_o2_1_0[0]
+   Inst              IPL_D0_1_                                 IPL_D0[1]
+   Inst   pos_clk_un6_bgack_000_0_0                 pos_clk.un6_bgack_000_0_0
+   Inst              IPL_D0_2_                                 IPL_D0[2]
+   Inst      CLK_000_N_SYNC_5_                         CLK_000_N_SYNC[5]
+   Inst            SIZE_c_i_1_                               SIZE_c_i[1]
+   Inst   pos_clk_SIZE_DMA_6_0_0_0_0_               pos_clk.SIZE_DMA_6_0_0_0[0]
+   Inst      CLK_000_N_SYNC_6_                         CLK_000_N_SYNC[6]
+   Inst   pos_clk_SIZE_DMA_6_0_0_0_1_               pos_clk.SIZE_DMA_6_0_0_0[1]
+   Inst      CLK_000_N_SYNC_7_                         CLK_000_N_SYNC[7]
+   Inst         IPL_030_1_i_0_                            IPL_030_1_i[0]
+   Inst      CLK_000_N_SYNC_8_                         CLK_000_N_SYNC[8]
+   Inst             IPL_c_i_0_                                IPL_c_i[0]
+   Inst   pos_clk_SIZE_DMA_6_0_0_0_o2_0_            pos_clk.SIZE_DMA_6_0_0_0_o2[0]
+   Inst      CLK_000_N_SYNC_9_                         CLK_000_N_SYNC[9]
+   Inst          IPL_D0_0_i_0_                             IPL_D0_0_i[0]
+   Inst     CLK_000_N_SYNC_10_                        CLK_000_N_SYNC[10]
+   Inst     CLK_000_N_SYNC_11_                        CLK_000_N_SYNC[11]
+   Inst           CYCLE_DMA_0_                              CYCLE_DMA[0]
+   Inst           CYCLE_DMA_1_                              CYCLE_DMA[1]
+   Inst            SIZE_DMA_0_                               SIZE_DMA[0]
+   Inst        SIZE_DMA_0_0__r                           SIZE_DMA_0_0_.r
+   Inst            SIZE_DMA_1_                               SIZE_DMA[1]
+   Inst        SIZE_DMA_0_0__m                           SIZE_DMA_0_0_.m
+   Inst             cpu_est_0_                                cpu_est[0]
+   Inst        SIZE_DMA_0_0__n                           SIZE_DMA_0_0_.n
+   Inst             cpu_est_1_                                cpu_est[1]
+   Inst        SIZE_DMA_0_0__p                           SIZE_DMA_0_0_.p
+   Inst      CLK_000_P_SYNC_1_                         CLK_000_P_SYNC[1]
+   Inst        SIZE_DMA_0_1__r                           SIZE_DMA_0_1_.r
+   Inst      CLK_000_P_SYNC_2_                         CLK_000_P_SYNC[2]
+   Inst        SIZE_DMA_0_1__m                           SIZE_DMA_0_1_.m
+   Inst      CLK_000_P_SYNC_3_                         CLK_000_P_SYNC[3]
+   Inst   SM_AMIGA_srsts_i_i_0_i_6_                 SM_AMIGA_srsts_i_i_0_i[6]
+   Inst        SIZE_DMA_0_1__n                           SIZE_DMA_0_1_.n
+   Inst      CLK_000_P_SYNC_4_                         CLK_000_P_SYNC[4]
+   Inst        SIZE_DMA_0_1__p                           SIZE_DMA_0_1_.p
+   Inst      CLK_000_P_SYNC_5_                         CLK_000_P_SYNC[5]
+   Inst                A_i_18_                                   A_i[18]
+   Inst      CLK_000_P_SYNC_6_                         CLK_000_P_SYNC[6]
+   Inst                A_i_19_                                   A_i[19]
+   Inst      CLK_000_P_SYNC_7_                         CLK_000_P_SYNC[7]
+   Inst                A_i_16_                                   A_i[16]
+   Inst      CLK_000_P_SYNC_8_                         CLK_000_P_SYNC[8]
+   Inst   SM_AMIGA_srsts_i_i_0_i_2_                 SM_AMIGA_srsts_i_i_0_i[2]
+   Inst      CLK_000_P_SYNC_9_                         CLK_000_P_SYNC[9]
+   Inst      CLK_000_N_SYNC_0_                         CLK_000_N_SYNC[0]
+   Inst      CLK_000_N_SYNC_1_                         CLK_000_N_SYNC[1]
+   Inst   cpu_est_2_0_0_0_i_1_                      cpu_est_2_0_0_0_i[1]
+   Inst      CLK_000_N_SYNC_2_                         CLK_000_N_SYNC[2]
+   Inst   pos_clk_SIZE_DMA_6_0_0_0_a3_0_            pos_clk.SIZE_DMA_6_0_0_0_a3[0]
+   Inst      CLK_000_N_SYNC_3_                         CLK_000_N_SYNC[3]
+   Inst   pos_clk_SIZE_DMA_6_0_0_0_a3_1_            pos_clk.SIZE_DMA_6_0_0_0_a3[1]
+   Inst      CLK_000_N_SYNC_4_                         CLK_000_N_SYNC[4]
+   Inst   pos_clk_un7_clk_000_pe_0_0_i              pos_clk.un7_clk_000_pe_0_0_i
+   Inst   pos_clk_A0_DMA_3_0_a2_0_a3                pos_clk.A0_DMA_3_0_a2_0_a3
+   Inst             RST_DLY_0_                                RST_DLY[0]
+   Inst             RST_DLY_1_                                RST_DLY[1]
+   Inst   cpu_est_2_0_0_0_i_3_                      cpu_est_2_0_0_0_i[3]
+   Inst             RST_DLY_2_                                RST_DLY[2]
+   Inst      CLK_000_P_SYNC_0_                         CLK_000_P_SYNC[0]
+   Inst   cpu_est_2_0_0_0_i_2_                      cpu_est_2_0_0_0_i[2]
+   Inst         AS_000_DMA_0_r                            AS_000_DMA_0.r
+   Inst   pos_clk_un6_bg_030_0_a2_i_i               pos_clk.un6_bg_030_0_a2_i_i
+   Inst         AS_000_DMA_0_m                            AS_000_DMA_0.m
+   Inst         AS_000_DMA_0_n                            AS_000_DMA_0.n
+   Inst         AS_000_DMA_0_p                            AS_000_DMA_0.p
+   Inst      BGACK_030_INT_0_r                         BGACK_030_INT_0.r
+   Inst      BGACK_030_INT_0_m                         BGACK_030_INT_0.m
+   Inst      BGACK_030_INT_0_n                         BGACK_030_INT_0.n
+   Inst      BGACK_030_INT_0_p                         BGACK_030_INT_0.p
+   Inst         RW_000_DMA_0_r                            RW_000_DMA_0.r
+   Inst         RW_000_DMA_0_m                            RW_000_DMA_0.m
+   Inst         RW_000_DMA_0_n                            RW_000_DMA_0.n
+   Inst         RW_000_DMA_0_p                            RW_000_DMA_0.p
+   Inst             A0_DMA_0_r                                A0_DMA_0.r
+   Inst             A0_DMA_0_m                                A0_DMA_0.m
+   Inst   cpu_est_2_0_0_0_o2_i_2_                   cpu_est_2_0_0_0_o2_i[2]
+   Inst             A0_DMA_0_n                                A0_DMA_0.n
+   Inst   cpu_est_2_0_0_0_o2_i_3_                   cpu_est_2_0_0_0_o2_i[3]
+   Inst             A0_DMA_0_p                                A0_DMA_0.p
+   Inst   AMIGA_BUS_ENABLE_DMA_LOW_0_r              AMIGA_BUS_ENABLE_DMA_LOW_0.r
+   Inst   SM_AMIGA_nss_i_i_0_0_o2_i_0_              SM_AMIGA_nss_i_i_0_0_o2_i[0]
+   Inst   AMIGA_BUS_ENABLE_DMA_LOW_0_m              AMIGA_BUS_ENABLE_DMA_LOW_0.m
+   Inst   AMIGA_BUS_ENABLE_DMA_LOW_0_n              AMIGA_BUS_ENABLE_DMA_LOW_0.n
+   Inst   SM_AMIGA_nss_i_i_0_0_o2_3_i_0_            SM_AMIGA_nss_i_i_0_0_o2_3_i[0]
+   Inst   AMIGA_BUS_ENABLE_DMA_LOW_0_p              AMIGA_BUS_ENABLE_DMA_LOW_0.p
+   Inst   AMIGA_BUS_ENABLE_DMA_HIGH_0_r             AMIGA_BUS_ENABLE_DMA_HIGH_0.r
+   Inst   AMIGA_BUS_ENABLE_DMA_HIGH_0_m             AMIGA_BUS_ENABLE_DMA_HIGH_0.m
+   Inst   AMIGA_BUS_ENABLE_DMA_HIGH_0_n             AMIGA_BUS_ENABLE_DMA_HIGH_0.n
+   Inst   AMIGA_BUS_ENABLE_DMA_HIGH_0_p             AMIGA_BUS_ENABLE_DMA_HIGH_0.p
+   Inst   SM_AMIGA_nss_i_i_0_0_o2_2_i_0_            SM_AMIGA_nss_i_i_0_0_o2_2_i[0]
+   Inst   SM_AMIGA_srsts_i_0_0_o2_i_4_              SM_AMIGA_srsts_i_0_0_o2_i[4]
+   Inst   SM_AMIGA_srsts_i_i_0_o2_i_2_              SM_AMIGA_srsts_i_i_0_o2_i[2]
+   Inst   SM_AMIGA_srsts_i_i_0_o2_i_6_              SM_AMIGA_srsts_i_i_0_o2_i[6]
+   Inst   SM_AMIGA_nss_i_i_0_0_o2_1_i_0_            SM_AMIGA_nss_i_i_0_0_o2_1_i[0]
+   Inst   SM_AMIGA_srsts_i_0_0_o2_0_i_3_            SM_AMIGA_srsts_i_0_0_o2_0_i[3]
+   Inst           RST_DLY_i_0_                              RST_DLY_i[0]
+   Inst           RST_DLY_i_1_                              RST_DLY_i[1]
+   Inst                SIZE_0_                                   SIZE[0]
+   Inst   SM_AMIGA_nss_i_i_0_0_o2_0_i_0_            SM_AMIGA_nss_i_i_0_0_o2_0_i[0]
+   Inst                SIZE_1_                                   SIZE[1]
+   Inst   CLK_000_N_SYNC_i_10_                      CLK_000_N_SYNC_i[10]
+   Inst           RST_DLY_i_2_                              RST_DLY_i[2]
+   Inst           cpu_est_i_3_                              cpu_est_i[3]
+   Inst           cpu_est_i_0_                              cpu_est_i[0]
+   Inst          SM_AMIGA_i_3_                             SM_AMIGA_i[3]
+   Inst                A_i_24_                                   A_i[24]
+   Inst          SIZE_DMA_i_0_                             SIZE_DMA_i[0]
+   Inst          SIZE_DMA_i_1_                             SIZE_DMA_i[1]
+   Inst                  A_16_                                     A[16]
+   Inst                  A_17_                                     A[17]
+   Inst   SM_AMIGA_srsts_i_0_0_o2_i_3_              SM_AMIGA_srsts_i_0_0_o2_i[3]
+   Inst                  A_18_                                     A[18]
+   Inst                  A_19_                                     A[19]
+   Inst                  A_20_                                     A[20]
+   Inst                  A_21_                                     A[21]
+   Inst   SM_AMIGA_nss_i_i_0_0_o2_5_0_              SM_AMIGA_nss_i_i_0_0_o2_5[0]
+   Inst                  A_22_                                     A[22]
+   Inst   SM_AMIGA_nss_i_i_0_0_o2_6_0_              SM_AMIGA_nss_i_i_0_0_o2_6[0]
+   Inst                  A_23_                                     A[23]
+   Inst   SM_AMIGA_nss_i_i_0_0_o2_0_0_              SM_AMIGA_nss_i_i_0_0_o2_0[0]
+   Inst                  A_24_                                     A[24]
+   Inst   SM_AMIGA_srsts_i_0_0_o2_0_3_              SM_AMIGA_srsts_i_0_0_o2_0[3]
+   Inst                  A_25_                                     A[25]
+   Inst   SM_AMIGA_nss_i_i_0_0_o2_1_0_              SM_AMIGA_nss_i_i_0_0_o2_1[0]
+   Inst                  A_26_                                     A[26]
+   Inst   SM_AMIGA_srsts_i_i_0_o2_6_                SM_AMIGA_srsts_i_i_0_o2[6]
+   Inst                  A_27_                                     A[27]
+   Inst   SM_AMIGA_srsts_i_i_0_o2_2_                SM_AMIGA_srsts_i_i_0_o2[2]
+   Inst                  A_28_                                     A[28]
+   Inst   SM_AMIGA_nss_i_i_0_0_o3_0_                SM_AMIGA_nss_i_i_0_0_o3[0]
+   Inst                  A_29_                                     A[29]
+   Inst                  A_30_                                     A[30]
+   Inst   SM_AMIGA_srsts_i_0_0_o2_4_                SM_AMIGA_srsts_i_0_0_o2[4]
+   Inst                  A_31_                                     A[31]
+   Inst   SM_AMIGA_nss_i_i_0_0_o2_2_0_              SM_AMIGA_nss_i_i_0_0_o2_2[0]
+   Inst   SM_AMIGA_srsts_i_0_0_o2_3_                SM_AMIGA_srsts_i_0_0_o2[3]
+   Inst   cpu_est_0_0_x2_0_x2_0_                    cpu_est_0_0_x2_0_x2[0]
+   Inst   pos_clk_SIZE_DMA_6_0_0_0_i_1_             pos_clk.SIZE_DMA_6_0_0_0_i[1]
+   Inst   pos_clk_SIZE_DMA_6_0_0_0_i_0_             pos_clk.SIZE_DMA_6_0_0_0_i[0]
+   Inst     cpu_est_2_0_0_0_2_                        cpu_est_2_0_0_0[2]
+   Inst     cpu_est_2_0_0_0_3_                        cpu_est_2_0_0_0[3]
+   Inst   SM_AMIGA_nss_i_i_0_0_o2_3_0_              SM_AMIGA_nss_i_i_0_0_o2_3[0]
+   Inst   pos_clk_un6_bgack_000_0_0_i               pos_clk.un6_bgack_000_0_0_i
+   Inst   pos_clk_CLK_000_N_SYNC_2_0_o3_i_o2_0_     pos_clk.CLK_000_N_SYNC_2_0_o3_i_o2[0]
+   Inst   cpu_est_2_0_0_0_o2_3_                     cpu_est_2_0_0_0_o2[3]
+   Inst             IPL_030_0_                                IPL_030[0]
+   Inst   pos_clk_un7_clk_000_pe_0_0_o2             pos_clk.un7_clk_000_pe_0_0_o2
+   Inst             IPL_030_1_                                IPL_030[1]
+   Inst           cpu_est_i_1_                              cpu_est_i[1]
+   Inst             IPL_030_2_                                IPL_030[2]
+   Inst   pos_clk_un37_as_030_d0_i_i_i              pos_clk.un37_as_030_d0_i_i_i
+   Inst   cpu_est_2_0_0_0_o2_2_                     cpu_est_2_0_0_0_o2[2]
+   Inst                 IPL_0_                                    IPL[0]
+   Inst   cpu_est_2_0_0_0_a3_2_                     cpu_est_2_0_0_0_a3[2]
+   Inst                 IPL_1_                                    IPL[1]
+   Inst   cpu_est_2_0_0_0_a3_3_                     cpu_est_2_0_0_0_a3[3]
+   Inst                 IPL_2_                                    IPL[2]
+   Inst   SM_AMIGA_srsts_i_0_0_a2_3_                SM_AMIGA_srsts_i_0_0_a2[3]
+   Inst   pos_clk_un3_as_030_d0_0_o2_0_o3_i         pos_clk.un3_as_030_d0_0_o2_0_o3_i
+   Inst   pos_clk_un24_bgack_030_int_i_0_i_a3_i_o3_i  pos_clk.un24_bgack_030_int_i_0_i_a3_i_o3_i
+   Inst   SM_AMIGA_srsts_i_0_0_o2_i_1_              SM_AMIGA_srsts_i_0_0_o2_i[1]
+   Inst   SM_AMIGA_srsts_i_0_0_o2_i_5_              SM_AMIGA_srsts_i_0_0_o2_i[5]
+   Inst   SM_AMIGA_srsts_i_0_0_a2_1_3_              SM_AMIGA_srsts_i_0_0_a2_1[3]
+   Inst   SM_AMIGA_srsts_i_0_0_o2_i_0_              SM_AMIGA_srsts_i_0_0_o2_i[0]
+   Inst   SM_AMIGA_nss_i_i_0_0_a2_0_                SM_AMIGA_nss_i_i_0_0_a2[0]
+   Inst           cpu_est_i_2_                              cpu_est_i[2]
+   Inst   cpu_est_2_0_0_0_a2_2_                     cpu_est_2_0_0_0_a2[2]
+   Inst   pos_clk_un7_clk_000_pe_0_0                pos_clk.un7_clk_000_pe_0_0
+   Inst                  FC_0_                                     FC[0]
+   Inst   pos_clk_SIZE_DMA_6_0_0_0_o2_i_0_          pos_clk.SIZE_DMA_6_0_0_0_o2_i[0]
+   Inst     cpu_est_2_0_0_0_1_                        cpu_est_2_0_0_0[1]
+   Inst                  FC_1_                                     FC[1]
+   Inst   SM_AMIGA_srsts_i_i_0_2_                   SM_AMIGA_srsts_i_i_0[2]
+   Inst   SM_AMIGA_srsts_i_i_0_6_                   SM_AMIGA_srsts_i_i_0[6]
+   Inst                A_i_27_                                   A_i[27]
+   Inst                A_i_28_                                   A_i[28]
+   Inst             IPL_c_i_1_                                IPL_c_i[1]
+   Inst                A_i_29_                                   A_i[29]
+   Inst          IPL_D0_0_i_1_                             IPL_D0_0_i[1]
+   Inst                A_i_30_                                   A_i[30]
+   Inst   SM_AMIGA_nss_i_i_0_0_a3_1_1_0_            SM_AMIGA_nss_i_i_0_0_a3_1_1[0]
+   Inst             IPL_c_i_2_                                IPL_c_i[2]
+   Inst                A_i_31_                                   A_i[31]
+   Inst   SM_AMIGA_nss_i_i_0_0_a3_1_0_              SM_AMIGA_nss_i_i_0_0_a3_1[0]
+   Inst          IPL_D0_0_i_2_                             IPL_D0_0_i[2]
+   Inst   SM_AMIGA_nss_i_i_0_0_a3_0_1_0_            SM_AMIGA_nss_i_i_0_0_a3_0_1[0]
+   Inst   SM_AMIGA_nss_i_i_0_0_a3_0_0_              SM_AMIGA_nss_i_i_0_0_a3_0[0]
+   Inst         IPL_030_1_i_1_                            IPL_030_1_i[1]
+   Inst   SM_AMIGA_nss_i_i_0_0_a3_0_                SM_AMIGA_nss_i_i_0_0_a3[0]
+   Inst   SM_AMIGA_srsts_i_0_0_a3_3_                SM_AMIGA_srsts_i_0_0_a3[3]
+   Inst         IPL_030_1_i_2_                            IPL_030_1_i[2]
+   Inst   cpu_est_2_0_0_0_a3_1_                     cpu_est_2_0_0_0_a3[1]
+   Inst   SM_AMIGA_srsts_i_0_0_a3_4_                SM_AMIGA_srsts_i_0_0_a3[4]
+   Inst   pos_clk_DS_000_DMA_4_f0_i_a2_i_i          pos_clk.DS_000_DMA_4_f0_i_a2_i_i
+   Inst   SM_AMIGA_srsts_i_0_0_4_                   SM_AMIGA_srsts_i_0_0[4]
+   Inst   SM_AMIGA_srsts_i_0_0_1_5_                 SM_AMIGA_srsts_i_0_0_1[5]
+   Inst   SM_AMIGA_srsts_i_0_0_5_                   SM_AMIGA_srsts_i_0_0[5]
+   Inst   SM_AMIGA_srsts_i_i_0_a3_0_1_6_            SM_AMIGA_srsts_i_i_0_a3_0_1[6]
+   Inst                A_i_25_                                   A_i[25]
+   Inst   SM_AMIGA_srsts_i_i_0_a3_0_6_              SM_AMIGA_srsts_i_i_0_a3_0[6]
+   Inst                A_i_26_                                   A_i[26]
+   Inst   SM_AMIGA_srsts_i_i_0_a3_1_6_              SM_AMIGA_srsts_i_i_0_a3_1[6]
+   Inst         cpu_est_0_2__r                            cpu_est_0_2_.r
+   Inst   SM_AMIGA_srsts_i_i_0_a3_6_                SM_AMIGA_srsts_i_i_0_a3[6]
+   Inst         cpu_est_0_2__m                            cpu_est_0_2_.m
+   Inst   SM_AMIGA_srsts_i_i_0_a3_1_2_              SM_AMIGA_srsts_i_i_0_a3_1[2]
+   Inst         cpu_est_0_2__n                            cpu_est_0_2_.n
+   Inst   SM_AMIGA_srsts_i_i_0_a3_2_                SM_AMIGA_srsts_i_i_0_a3[2]
+   Inst         cpu_est_0_2__p                            cpu_est_0_2_.p
+   Inst   cpu_est_2_0_0_a3_0_1_1_                   cpu_est_2_0_0_a3_0_1[1]
+   Inst         cpu_est_0_3__r                            cpu_est_0_3_.r
+   Inst   cpu_est_2_0_0_a3_0_1_                     cpu_est_2_0_0_a3_0[1]
+   Inst         cpu_est_0_3__m                            cpu_est_0_3_.m
+   Inst   SM_AMIGA_srsts_i_0_0_a3_0_1_3_            SM_AMIGA_srsts_i_0_0_a3_0_1[3]
+   Inst         cpu_est_0_3__n                            cpu_est_0_3_.n
+   Inst   SM_AMIGA_srsts_i_0_0_a3_0_3_              SM_AMIGA_srsts_i_0_0_a3_0[3]
+   Inst         IPL_030_0_1__r                            IPL_030_0_1_.r
+   Inst         cpu_est_0_3__p                            cpu_est_0_3_.p
+   Inst   pos_clk_un6_bg_030_0_a2_i_1               pos_clk.un6_bg_030_0_a2_i_1
+   Inst         IPL_030_0_1__m                            IPL_030_0_1_.m
+   Inst         IPL_030_0_0__r                            IPL_030_0_0_.r
+   Inst   pos_clk_un6_bg_030_0_a2_i                 pos_clk.un6_bg_030_0_a2_i
+   Inst         IPL_030_0_1__n                            IPL_030_0_1_.n
+   Inst         IPL_030_0_0__m                            IPL_030_0_0_.m
+   Inst   SM_AMIGA_srsts_i_0_0_1_1_                 SM_AMIGA_srsts_i_0_0_1[1]
+   Inst         IPL_030_0_1__p                            IPL_030_0_1_.p
+   Inst         IPL_030_0_0__n                            IPL_030_0_0_.n
+   Inst   SM_AMIGA_srsts_i_0_0_1_                   SM_AMIGA_srsts_i_0_0[1]
+   Inst           IPL_030_1_2_                              IPL_030_1[2]
+   Inst         IPL_030_0_0__p                            IPL_030_0_0_.p
+   Inst           IPL_030_1_1_                              IPL_030_1[1]
+   Inst            IPL_D0_0_2_                               IPL_D0_0[2]
+   Inst         RW_000_INT_0_r                            RW_000_INT_0.r
+   Inst   pos_clk_CYCLE_DMA_5_1_i_0_1               pos_clk.CYCLE_DMA_5_1_i_0_1
+   Inst            IPL_D0_0_1_                               IPL_D0_0[1]
+   Inst         RW_000_INT_0_m                            RW_000_INT_0.m
+   Inst   pos_clk_CYCLE_DMA_5_1_i_0                 pos_clk.CYCLE_DMA_5_1_i_0
+   Inst         RW_000_INT_0_n                            RW_000_INT_0.n
+   Inst   pos_clk_CYCLE_DMA_5_0_i_0_1               pos_clk.CYCLE_DMA_5_0_i_0_1
+   Inst         RW_000_INT_0_p                            RW_000_INT_0.p
+   Inst   pos_clk_CYCLE_DMA_5_0_i_0                 pos_clk.CYCLE_DMA_5_0_i_0
+   Inst        UDS_000_INT_0_r                           UDS_000_INT_0.r
+   Inst        UDS_000_INT_0_m                           UDS_000_INT_0.m
+   Inst        UDS_000_INT_0_n                           UDS_000_INT_0.n
+   Inst        UDS_000_INT_0_p                           UDS_000_INT_0.p
+   Inst    AS_030_000_SYNC_0_r                       AS_030_000_SYNC_0.r
+   Inst            VMA_INT_0_r                               VMA_INT_0.r
+   Inst   SM_AMIGA_srsts_i_0_0_1_4_                 SM_AMIGA_srsts_i_0_0_1[4]
+   Inst    AS_030_000_SYNC_0_m                       AS_030_000_SYNC_0.m
+   Inst            VMA_INT_0_m                               VMA_INT_0.m
+   Inst   pos_clk_un37_as_030_d0_i_a2_1_3           pos_clk.un37_as_030_d0_i_a2_1_3
+   Inst    AS_030_000_SYNC_0_n                       AS_030_000_SYNC_0.n
+   Inst            VMA_INT_0_n                               VMA_INT_0.n
+   Inst   pos_clk_un37_as_030_d0_i_a2_1_4           pos_clk.un37_as_030_d0_i_a2_1_4
+   Inst    AS_030_000_SYNC_0_p                       AS_030_000_SYNC_0.p
+   Inst            VMA_INT_0_p                               VMA_INT_0.p
+   Inst   pos_clk_un37_as_030_d0_i_a2_1             pos_clk.un37_as_030_d0_i_a2_1
+   Inst          SM_AMIGA_i_5_                             SM_AMIGA_i[5]
+   Inst             BG_000_0_r                                BG_000_0.r
+   Inst         AS_000_INT_0_r                            AS_000_INT_0.r
+   Inst             BG_000_0_m                                BG_000_0.m
+   Inst         AS_000_INT_0_m                            AS_000_INT_0.m
+   Inst             BG_000_0_n                                BG_000_0.n
+   Inst         AS_000_INT_0_n                            AS_000_INT_0.n
+   Inst             BG_000_0_p                                BG_000_0.p
+   Inst         AS_000_INT_0_p                            AS_000_INT_0.p
+   Inst         DS_000_DMA_0_r                            DS_000_DMA_0.r
+   Inst         DS_000_DMA_0_m                            DS_000_DMA_0.m
+   Inst         DS_000_DMA_0_n                            DS_000_DMA_0.n
+   Inst   pos_clk_un37_as_030_d0_i_i_a3_1           pos_clk.un37_as_030_d0_i_i_a3_1
+   Inst         DS_000_DMA_0_p                            DS_000_DMA_0.p
+   Inst   pos_clk_un37_as_030_d0_i_i_a3_2           pos_clk.un37_as_030_d0_i_i_a3_2
+   Inst   pos_clk_un37_as_030_d0_i_i_a3             pos_clk.un37_as_030_d0_i_i_a3
+   Inst            IPL_D0_0_0_                               IPL_D0_0[0]
+   Inst   pos_clk_DS_000_DMA_4_f0_i_a2_i_a3         pos_clk.DS_000_DMA_4_f0_i_a2_i_a3
+   Inst           IPL_030_1_0_                              IPL_030_1[0]
+   Net      rw_000_dma_0_un1_n                          RW_000_DMA_0.un1
+   Net      rw_000_dma_0_un0_n                          RW_000_DMA_0.un0
+   Net          a0_dma_0_un3_n                              A0_DMA_0.un3
+   Net          a0_dma_0_un1_n                              A0_DMA_0.un1
+   Net          a0_dma_0_un0_n                              A0_DMA_0.un0
+   Net    amiga_bus_enable_dma_low_0_un3_n            AMIGA_BUS_ENABLE_DMA_LOW_0.un3
+   Net    amiga_bus_enable_dma_low_0_un1_n            AMIGA_BUS_ENABLE_DMA_LOW_0.un1
+   Net    pos_clk_size_dma_6_0_1__n                   pos_clk.SIZE_DMA_6_0[1]
+   Net    amiga_bus_enable_dma_low_0_un0_n            AMIGA_BUS_ENABLE_DMA_LOW_0.un0
+   Net                 vcc_n_n                                       VCC
+   Net    amiga_bus_enable_dma_high_0_un3_n           AMIGA_BUS_ENABLE_DMA_HIGH_0.un3
+   Net    pos_clk_size_dma_6_0_0__n                   pos_clk.SIZE_DMA_6_0[0]
+   Net    amiga_bus_enable_dma_high_0_un1_n           AMIGA_BUS_ENABLE_DMA_HIGH_0.un1
+   Net    amiga_bus_enable_dma_high_0_un0_n           AMIGA_BUS_ENABLE_DMA_HIGH_0.un0
+   Net                 gnd_n_n                                       GND
+   Net      cpu_est_0_2__un3_n                          cpu_est_0_2_.un3
+   Net      cpu_est_0_2__un1_n                          cpu_est_0_2_.un1
+   Net      cpu_est_0_2__un0_n                          cpu_est_0_2_.un0
+   Net    pos_clk_un6_bgack_000_0_n                   pos_clk.un6_bgack_000_0
+   Net      cpu_est_0_3__un3_n                          cpu_est_0_3_.un3
+   Net      cpu_est_0_3__un1_n                          cpu_est_0_3_.un1
+   Net      cpu_est_0_3__un0_n                          cpu_est_0_3_.un0
+   Net      ipl_030_0_0__un3_n                          IPL_030_0_0_.un3
+   Net      ipl_030_0_0__un1_n                          IPL_030_0_0_.un1
+   Net      ipl_030_0_0__un0_n                          IPL_030_0_0_.un0
+   Net      rw_000_int_0_un3_n                          RW_000_INT_0.un3
+   Net         sm_amiga_i_5__n                             SM_AMIGA_i[5]
+   Net      rw_000_int_0_un1_n                          RW_000_INT_0.un1
+   Net         sm_amiga_i_6__n                             SM_AMIGA_i[6]
+   Net      rw_000_int_0_un0_n                          RW_000_INT_0.un0
+   Net            cpu_est_0__n                                cpu_est[0]
+   Net         sm_amiga_i_0__n                             SM_AMIGA_i[0]
+   Net     uds_000_int_0_un3_n                         UDS_000_INT_0.un3
+   Net            cpu_est_1__n                                cpu_est[1]
+   Net     uds_000_int_0_un1_n                         UDS_000_INT_0.un1
+   Net            cpu_est_2__n                                cpu_est[2]
+   Net         sm_amiga_i_4__n                             SM_AMIGA_i[4]
+   Net     uds_000_int_0_un0_n                         UDS_000_INT_0.un0
+   Net            cpu_est_3__n                                cpu_est[3]
+   Net         vma_int_0_un3_n                             VMA_INT_0.un3
+   Net         sm_amiga_i_2__n                             SM_AMIGA_i[2]
+   Net         vma_int_0_un1_n                             VMA_INT_0.un1
+   Net           sm_amiga_5__n                               SM_AMIGA[5]
+   Net         vma_int_0_un0_n                             VMA_INT_0.un0
+   Net          bg_000_0_un3_n                              BG_000_0.un3
+   Net         sm_amiga_i_1__n                             SM_AMIGA_i[1]
+   Net          bg_000_0_un1_n                              BG_000_0.un1
+   Net          bg_000_0_un0_n                              BG_000_0.un0
+   Net      cpu_est_0_1__un3_n                          cpu_est_0_1_.un3
+   Net       sm_amiga_i_i_7__n                           SM_AMIGA_i_i[7]
+   Net      cpu_est_0_1__un1_n                          cpu_est_0_1_.un1
+   Net      cpu_est_0_1__un0_n                          cpu_est_0_1_.un0
+   Net      dsack1_int_0_un3_n                          DSACK1_INT_0.un3
+   Net          cycle_dma_0__n                              CYCLE_DMA[0]
+   Net      dsack1_int_0_un1_n                          DSACK1_INT_0.un1
+   Net          cycle_dma_1__n                              CYCLE_DMA[1]
+   Net      dsack1_int_0_un0_n                          DSACK1_INT_0.un0
+   Net           size_dma_0__n                               SIZE_DMA[0]
+   Net    ds_000_enable_0_un3_n                       DS_000_ENABLE_0.un3
+   Net           size_dma_1__n                               SIZE_DMA[1]
+   Net    ds_000_enable_0_un1_n                       DS_000_ENABLE_0.un1
+   Net    ds_000_enable_0_un0_n                       DS_000_ENABLE_0.un0
+   Net               a_i_16__n                                   A_i[16]
+   Net     lds_000_int_0_un3_n                         LDS_000_INT_0.un3
+   Net               a_i_18__n                                   A_i[18]
+   Net     lds_000_int_0_un1_n                         LDS_000_INT_0.un1
+   Net               a_i_19__n                                   A_i[19]
+   Net     lds_000_int_0_un0_n                         LDS_000_INT_0.un0
+   Net                 a_15__n                                     A[15]
+   Net                 a_14__n                                     A[14]
+   Net          rst_dly_i_2__n                              RST_DLY_i[2]
+   Net                 a_13__n                                     A[13]
+   Net          rst_dly_i_0__n                              RST_DLY_i[0]
+   Net          rst_dly_i_1__n                              RST_DLY_i[1]
+   Net                 a_12__n                                     A[12]
+   Net     clk_000_p_sync_9__n                         CLK_000_P_SYNC[9]
+   Net         size_dma_i_1__n                             SIZE_DMA_i[1]
+   Net                 a_11__n                                     A[11]
+   Net         size_dma_i_0__n                             SIZE_DMA_i[0]
+   Net    clk_000_n_sync_11__n                        CLK_000_N_SYNC[11]
+   Net                 a_10__n                                     A[10]
+   Net             ipl_d0_0__n                                 IPL_D0[0]
+   Net               a_i_24__n                                   A_i[24]
+   Net             ipl_d0_1__n                                 IPL_D0[1]
+   Net         sm_amiga_i_3__n                             SM_AMIGA_i[3]
+   Net                  a_9__n                                      A[9]
+   Net             ipl_d0_2__n                                 IPL_D0[2]
+   Net          cpu_est_i_3__n                              cpu_est_i[3]
+   Net          cpu_est_i_0__n                              cpu_est_i[0]
+   Net                  a_8__n                                      A[8]
+   Net           sm_amiga_0__n                               SM_AMIGA[0]
+   Net          cpu_est_i_1__n                              cpu_est_i[1]
+   Net                  a_7__n                                      A[7]
+   Net           pos_clk_ipl_n                               pos_clk.ipl
+   Net                  a_6__n                                      A[6]
+   Net           sm_amiga_4__n                               SM_AMIGA[4]
+   Net          cpu_est_i_2__n                              cpu_est_i[2]
+   Net                  a_5__n                                      A[5]
+   Net            rst_dly_0__n                                RST_DLY[0]
+   Net            rst_dly_1__n                                RST_DLY[1]
+   Net               a_i_31__n                                   A_i[31]
+   Net                  a_4__n                                      A[4]
+   Net            rst_dly_2__n                                RST_DLY[2]
+   Net               a_i_29__n                                   A_i[29]
+   Net    pos_clk_un8_bg_030_n                        pos_clk.un8_bg_030
+   Net               a_i_30__n                                   A_i[30]
+   Net                  a_3__n                                      A[3]
+   Net     clk_000_p_sync_0__n                         CLK_000_P_SYNC[0]
+   Net               a_i_27__n                                   A_i[27]
+   Net     clk_000_p_sync_1__n                         CLK_000_P_SYNC[1]
+   Net               a_i_28__n                                   A_i[28]
+   Net                  a_2__n                                      A[2]
+   Net     clk_000_p_sync_2__n                         CLK_000_P_SYNC[2]
+   Net               a_i_25__n                                   A_i[25]
+   Net     clk_000_p_sync_3__n                         CLK_000_P_SYNC[3]
+   Net               a_i_26__n                                   A_i[26]
+   Net    clk_000_n_sync_i_10__n                      CLK_000_N_SYNC_i[10]
+   Net     clk_000_p_sync_4__n                         CLK_000_P_SYNC[4]
+   Net     clk_000_p_sync_5__n                         CLK_000_P_SYNC[5]
+   Net     clk_000_p_sync_6__n                         CLK_000_P_SYNC[6]
+   Net     clk_000_p_sync_7__n                         CLK_000_P_SYNC[7]
+   Net     clk_000_p_sync_8__n                         CLK_000_P_SYNC[8]
+   Net     clk_000_n_sync_0__n                         CLK_000_N_SYNC[0]
+   Net     clk_000_n_sync_1__n                         CLK_000_N_SYNC[1]
+   Net     clk_000_n_sync_2__n                         CLK_000_N_SYNC[2]
+   Net     clk_000_n_sync_3__n                         CLK_000_N_SYNC[3]
+   Net     clk_000_n_sync_4__n                         CLK_000_N_SYNC[4]
+   Net     clk_000_n_sync_5__n                         CLK_000_N_SYNC[5]
+   Net     clk_000_n_sync_6__n                         CLK_000_N_SYNC[6]
+   Net     clk_000_n_sync_7__n                         CLK_000_N_SYNC[7]
+   Net     clk_000_n_sync_8__n                         CLK_000_N_SYNC[8]
+   Net     clk_000_n_sync_9__n                         CLK_000_N_SYNC[9]
+   Net    clk_000_n_sync_10__n                        CLK_000_N_SYNC[10]
+   Net    pos_clk_un7_clk_000_pe_n                    pos_clk.un7_clk_000_pe
+   Net        cpu_est_2_0_3__n                            cpu_est_2_0[3]
+   Net           sm_amiga_6__n                               SM_AMIGA[6]
+   Net        cpu_est_2_0_2__n                            cpu_est_2_0[2]
+   Net           sm_amiga_1__n                               SM_AMIGA[1]
+   Net             size_c_0__n                                 SIZE_c[0]
+   Net           sm_amiga_3__n                               SM_AMIGA[3]
+   Net               size_0__n                                   SIZE[0]
+   Net           sm_amiga_2__n                               SM_AMIGA[2]
+   Net             size_c_1__n                                 SIZE_c[1]
+   Net    pos_clk_un3_as_030_d0_n                     pos_clk.un3_as_030_d0
+   Net        cpu_est_2_0_1__n                            cpu_est_2_0[1]
+   Net    pos_clk_un7_clk_000_pe_0_n                  pos_clk.un7_clk_000_pe_0
+   Net               a_c_16__n                                   A_c[16]
+   Net                 a_16__n                                     A[16]
+   Net               a_c_17__n                                   A_c[17]
+   Net    pos_clk_un8_sm_amiga_i_n                    pos_clk.un8_sm_amiga_i
+   Net                 a_17__n                                     A[17]
+   Net               a_c_18__n                                   A_c[18]
+   Net           size_c_i_1__n                               SIZE_c_i[1]
+   Net                 a_18__n                                     A[18]
+   Net               a_c_19__n                                   A_c[19]
+   Net                 a_19__n                                     A[19]
+   Net            ipl_c_i_0__n                                IPL_c_i[0]
+   Net               a_c_20__n                                   A_c[20]
+   Net                 a_20__n                                     A[20]
+   Net               a_c_21__n                                   A_c[21]
+   Net                 a_21__n                                     A[21]
+   Net         sm_amiga_i_7__n                             SM_AMIGA_i[7]
+   Net               a_c_22__n                                   A_c[22]
+   Net                 a_22__n                                     A[22]
+   Net          cpu_est_2_1__n                              cpu_est_2[1]
+   Net               a_c_23__n                                   A_c[23]
+   Net          cpu_est_2_2__n                              cpu_est_2[2]
+   Net                 a_23__n                                     A[23]
+   Net          cpu_est_2_3__n                              cpu_est_2[3]
+   Net               a_c_24__n                                   A_c[24]
+   Net                 a_24__n                                     A[24]
+   Net               a_c_25__n                                   A_c[25]
+   Net                 a_25__n                                     A[25]
+   Net               a_c_26__n                                   A_c[26]
+   Net                 a_26__n                                     A[26]
+   Net               a_c_27__n                                   A_c[27]
+   Net    pos_clk_un8_bg_030_0_n                      pos_clk.un8_bg_030_0
+   Net                 a_27__n                                     A[27]
+   Net               a_c_28__n                                   A_c[28]
+   Net                 a_28__n                                     A[28]
+   Net    pos_clk_un8_sm_amiga_i_1_n                  pos_clk.un8_sm_amiga_i_1
+   Net               a_c_29__n                                   A_c[29]
+   Net                 a_29__n                                     A[29]
+   Net               a_c_30__n                                   A_c[30]
+   Net                 a_30__n                                     A[30]
+   Net               a_c_31__n                                   A_c[31]
+   Net          ipl_030_c_0__n                              IPL_030_c[0]
+   Net            ipl_030_0__n                                IPL_030[0]
+   Net          ipl_030_c_1__n                              IPL_030_c[1]
+   Net            ipl_030_1__n                                IPL_030[1]
+   Net          ipl_030_c_2__n                              IPL_030_c[2]
+   Net              ipl_c_0__n                                  IPL_c[0]
+   Net                ipl_0__n                                    IPL[0]
+   Net              ipl_c_1__n                                  IPL_c[1]
+   Net                ipl_1__n                                    IPL[1]
+   Net              ipl_c_2__n                                  IPL_c[2]
+   Net               fc_c_0__n                                   FC_c[0]
+   Net                 fc_0__n                                     FC[0]
+   Net               fc_c_1__n                                   FC_c[1]
+   Net         pos_clk_ipl_1_n                             pos_clk.ipl_1
+   Net      ipl_030_0_1__un3_n                          IPL_030_0_1_.un3
+   Net      ipl_030_0_1__un1_n                          IPL_030_0_1_.un1
+   Net      ipl_030_0_1__un0_n                          IPL_030_0_1_.un0
+   Net    as_030_000_sync_0_un3_n                     AS_030_000_SYNC_0.un3
+   Net    as_030_000_sync_0_un1_n                     AS_030_000_SYNC_0.un1
+   Net    as_030_000_sync_0_un0_n                     AS_030_000_SYNC_0.un0
+   Net      as_000_int_0_un3_n                          AS_000_INT_0.un3
+   Net      as_000_int_0_un1_n                          AS_000_INT_0.un1
+   Net      as_000_int_0_un0_n                          AS_000_INT_0.un0
+   Net      ds_000_dma_0_un3_n                          DS_000_DMA_0.un3
+   Net      ds_000_dma_0_un1_n                          DS_000_DMA_0.un1
+   Net      ds_000_dma_0_un0_n                          DS_000_DMA_0.un0
+   Net      ipl_030_0_2__un3_n                          IPL_030_0_2_.un3
+   Net    pos_clk_un6_bgack_000_n                     pos_clk.un6_bgack_000
+   Net      ipl_030_0_2__un1_n                          IPL_030_0_2_.un1
+   Net            ipl_c_i_1__n                                IPL_c_i[1]
+   Net      ipl_030_0_2__un0_n                          IPL_030_0_2_.un0
+   Net    un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un3_n  un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0_.un3
+   Net            ipl_c_i_2__n                                IPL_c_i[2]
+   Net    un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un1_n  un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0_.un1
+   Net    un1_amiga_bus_enable_dma_high_i_m2_0_m2_0__un0_n  un1_AMIGA_BUS_ENABLE_DMA_HIGH_i_m2_0_m2_0_.un0
+   Net      pos_clk_a0_dma_3_n                          pos_clk.A0_DMA_3
+   Net    sm_amiga_srsts_i_0_0_m3_1__un3_n            SM_AMIGA_srsts_i_0_0_m3_1_.un3
+   Net    sm_amiga_srsts_i_0_0_m3_1__un1_n            SM_AMIGA_srsts_i_0_0_m3_1_.un1
+   Net    sm_amiga_srsts_i_0_0_m3_1__un0_n            SM_AMIGA_srsts_i_0_0_m3_1_.un0
+   Net    sm_amiga_srsts_i_0_0_m3_5__un3_n            SM_AMIGA_srsts_i_0_0_m3_5_.un3
+   Net    sm_amiga_srsts_i_0_0_m3_5__un1_n            SM_AMIGA_srsts_i_0_0_m3_5_.un1
+   Net    pos_clk_size_dma_6_0__n                     pos_clk.SIZE_DMA_6[0]
+   Net    sm_amiga_srsts_i_0_0_m3_5__un0_n            SM_AMIGA_srsts_i_0_0_m3_5_.un0
+   Net     size_dma_0_0__un3_n                         SIZE_DMA_0_0_.un3
+   Net    pos_clk_size_dma_6_1__n                     pos_clk.SIZE_DMA_6[1]
+   Net     size_dma_0_0__un1_n                         SIZE_DMA_0_0_.un1
+   Net     size_dma_0_0__un0_n                         SIZE_DMA_0_0_.un0
+   Net     size_dma_0_1__un3_n                         SIZE_DMA_0_1_.un3
+   Net     size_dma_0_1__un1_n                         SIZE_DMA_0_1_.un1
+   Net     size_dma_0_1__un0_n                         SIZE_DMA_0_1_.un0
+   Net      as_000_dma_0_un3_n                          AS_000_DMA_0.un3
+   Net      as_000_dma_0_un1_n                          AS_000_DMA_0.un1
+   Net      as_000_dma_0_un0_n                          AS_000_DMA_0.un0
+   Net    pos_clk_un3_as_030_d0_i_n                   pos_clk.un3_as_030_d0_i
+   Net    bgack_030_int_0_un3_n                       BGACK_030_INT_0.un3
+   Net    bgack_030_int_0_un1_n                       BGACK_030_INT_0.un1
+   Net    bgack_030_int_0_un0_n                       BGACK_030_INT_0.un0
+   Net      rw_000_dma_0_un3_n                          RW_000_DMA_0.un3
+End
+Section Type      Name
+// ----------------------------------------------------------------------
+        Input     A_31_
+        Input     IPL_2_
+        Input     FC_1_
+        Input     A1
+        Input     nEXP_SPACE
+        Input     BG_030
+        Input     BGACK_000
+        Input     CLK_030
+        Input     CLK_000
+        Input     CLK_OSZI
+        Input     FPU_SENSE
+        Input     DTACK
+        Input     VPA
+        Input     RST
+        Input     A_30_
+        Input     A_29_
+        Input     A_28_
+        Input     A_27_
+        Input     A_26_
+        Input     A_25_
+        Input     A_24_
+        Input     A_23_
+        Input     A_22_
+        Input     A_21_
+        Input     A_20_
+        Input     A_19_
+        Input     A_18_
+        Input     A_17_
+        Input     A_16_
+        Input     A_15_
+        Input     A_14_
+        Input     A_13_
+        Input     A_12_
+        Input     A_11_
+        Input     A_10_
+        Input     A_9_
+        Input     A_8_
+        Input     A_7_
+        Input     A_6_
+        Input     A_5_
+        Input     A_4_
+        Input     A_3_
+        Input     A_2_
+        Input     IPL_1_
+        Input     IPL_0_
+        Input     FC_0_
+        Output     IPL_030_2_
+        Output     DS_030
+        Output     BG_000
+        Output     BGACK_030
+        Output     CLK_DIV_OUT
+        Output     CLK_EXP
+        Output     FPU_CS
+        Output     DSACK1
+        Output     AVEC
+        Output     E
+        Output     VMA
+        Output     RESET
+        Output     AMIGA_ADDR_ENABLE
+        Output     AMIGA_BUS_DATA_DIR
+        Output     AMIGA_BUS_ENABLE_LOW
+        Output     AMIGA_BUS_ENABLE_HIGH
+        Output     CIIN
+        Output     IPL_030_1_
+        Output     IPL_030_0_
+        Bidi     SIZE_1_
+        Bidi     AS_030
+        Bidi     AS_000
+        Bidi     RW_000
+        Bidi     UDS_000
+        Bidi     LDS_000
+        Bidi     A0
+        Bidi     BERR
+        Bidi     RW
+        Bidi     SIZE_0_
+End
diff --git a/Logic/bus68030.srf b/Logic/bus68030.srf
index a8e4836..d0b1a72 100644
--- a/Logic/bus68030.srf
+++ b/Logic/bus68030.srf
@@ -6,7 +6,7 @@
 #Implementation: logic
 
 $ Start of Compile
-#Sat Oct 10 21:59:41 2015
+#Sun Jan 24 16:20:47 2016
 
 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
 @N|Running in 64-bit mode
@@ -18,19 +18,20 @@ File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed -
 VHDL syntax check successful!
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
 @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral 
-@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:17|Signal clk_out_pre is undriven 
+@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":65:10:65:11|Using sequential encoding for type sm_e
+@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000
+@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven 
 Post processing for work.bus68030.behavioral
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register AMIGA_BUS_ENABLE_INT_4  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:36:124:38|Pruning register CLK_OUT_PRE_50_D_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":156:2:156:3|Pruning register CLK_030_D0_2  
-@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
-@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
-@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register DS_030_D0_3  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register AMIGA_BUS_ENABLE_INT_4  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D4_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D3_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D2_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2  
+@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
+@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
+@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register SM_AMIGA
 Extracted state machine for register SM_AMIGA
 State machine has 8 reachable states with original encodings of:
    000
@@ -41,14 +42,14 @@ State machine has 8 reachable states with original encodings of:
    101
    110
    111
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register cpu_est
 @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused 
 @END
 
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Sat Oct 10 21:59:42 2015
+# Sun Jan 24 16:20:47 2016
 
 ###########################################################]
 Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
@@ -58,6 +59,49 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
 At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Sat Oct 10 21:59:43 2015
+# Sun Jan 24 16:20:48 2016
+
+###########################################################]
+Map & Optimize Report
+
+Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014
+Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
+Product Version I-2014.03LC 
+@N: MF248 |Running in 64-bit mode.
+@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
+Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
+original code -> new code
+   000 -> 00000000
+   001 -> 00000011
+   010 -> 00000101
+   011 -> 00001001
+   100 -> 00010001
+   101 -> 00100001
+   110 -> 01000001
+   111 -> 10000001
+@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE
+---------------------------------------
+Resource Usage Report
+
+Simple gate primitives:
+DFF             80 uses
+BI_DIR          10 uses
+BUFTH           4 uses
+IBUF            46 uses
+OBUF            15 uses
+AND2            297 uses
+INV             261 uses
+OR2             27 uses
+XOR2            8 uses
+
+
+@N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
+I-2014.03LC 
+Mapper successful!
+
+At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
+
+Process took 0h:00m:01s realtime, 0h:00m:01s cputime
+# Sun Jan 24 16:20:49 2016
 
 ###########################################################]
diff --git a/Logic/dm/BUS68030_comp.xdm b/Logic/dm/BUS68030_comp.xdm
index ebe85f0..e0b1a0c 100644
--- a/Logic/dm/BUS68030_comp.xdm
+++ b/Logic/dm/BUS68030_comp.xdm
@@ -26,10 +26,10 @@ S7RCVMI="F3s	Anz1Ujjd3ELCNFPHs"NDR"D=PDE8"S>
 SR<WN(=""DRL=d"4"ORL=""(R=CD""4dR=CO""4cR
 />SqS<R"M=3ONsEDVHCP"R=""(/S>
 SR<qM3="lkF8DHCVDRC"P(=""
-/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jd3j4j.6"
+/>SqS<R"M=3CODNbMk_C#0b0._H"lCR"P=jc3jn6U("
 />SqS<R"M=3CODNbMk_C#0b04_H"lCR"P=jj3jjjjj"
 />SqS<R"M=3MOF#M0N0C_soP"R=J"&k;F0ABtqid_jjh_Qa)_u &R4J0kF;>"/
-<SSq=RM"03#lH0D#H00lRC"Pj="3jjjj"jj/S>
+<SSq=RM"03#lH0D#H00lRC"Pj="36j4n".6/S>
 SR<qMF="s_HoH0M#_"FVR"P=&FJk0z;A1jnUdJj&k;F0"
 />SqS<R"M=3HFsolhNCP"R=J"&k;F0Anz1Ujjd&FJk0/;">
 
diff --git a/Logic/lattice_cmd.rs2 b/Logic/lattice_cmd.rs2
index 184d2b5..16f63ef 100644
--- a/Logic/lattice_cmd.rs2
+++ b/Logic/lattice_cmd.rs2
@@ -1 +1 @@
--src 68030_tk.tt4 -type PLA -devfile "C:/ispLever/ispcpld/dat/mach4a/mach447ace.dev" -lci "68030_tk.lct" -touch "68030_tk.tt4"
+-src 68030_tk.tt4 -type PLA -devfile "C:/ispLever/ispcpld/dat/mach4a/mach447ace.dev" -postfit -lci 68030_tk.lco
diff --git a/Logic/run_options.txt b/Logic/run_options.txt
index 37c934d..7cf6168 100644
--- a/Logic/run_options.txt
+++ b/Logic/run_options.txt
@@ -1,7 +1,7 @@
 #--  Synopsys, Inc.
 #--  Version I-2014.03LC 
 #--  Project file C:\users\matze\documents\github\68030tk\logic\run_options.txt
-#--  Written on Sat Oct 10 21:59:41 2015
+#--  Written on Sun Jan 24 16:20:47 2016
 
 
 #project files
diff --git a/Logic/syndos.env b/Logic/syndos.env
new file mode 100644
index 0000000..dab14eb
--- /dev/null
+++ b/Logic/syndos.env
@@ -0,0 +1,39 @@
+ABEL5DEV=C:\ispLever\ispcpld\lib5
+DIOEDA_ABEL5DEV=C:\ispLever\ispcpld\lib5
+DIOEDA_ActiveHDL=C:\ispLever\active-hdl\BIN
+DIOEDA_ActiveHDLPath=C:\ispLever\active-hdl\BIN
+DIOEDA_AppNotes=C:\ispLever\ispcpld\bin
+DIOEDA_Bin=C:\ispLever\ispcpld\bin
+DIOEDA_Config=C:\ispLever\ispcpld\config
+DIOEDA_CONTEXT=ispLEVER CLASSIC
+DIOEDA_DSPPATH=C:\ispLever\ispLeverDSP
+DIOEDA_EPICPATH=C:\ispLever\ispfpga\bin\nt
+DIOEDA_Examples=C:\ispLever\examples
+DIOEDA_FPGABinPath=C:\ispLever\ispfpga\bin\nt
+DIOEDA_FPGAPath=C:\ispLever\ispfpga
+DIOEDA_HDLExplorer=C:\ispLever\hdle\win32
+DIOEDA_INI=C:\lsc_env
+DIOEDA_ispVM=C:\ispLever\ispvmsystem
+DIOEDA_ispVMSystem=C:\ispLever\ispvmsystem
+DIOEDA_License=C:\ispLever\license
+DIOEDA_MachPath=C:\ispLever\ispcpld\bin
+DIOEDA_Manuals=C:\ispLever\ispcpld\manuals
+DIOEDA_ModelSim=C:\ispLever\modelsim\win32loem
+DIOEDA_ModelsimPath=C:\ispLever\modelsim\win32loem
+DIOEDA_PDSPath=C:\ispLever\ispcomp
+DIOEDA_Precision=C:\isptools\precision
+DIOEDA_PrecisionPath=C:\isptools\precision
+DIOEDA_ProductName=ispLEVER
+DIOEDA_ProductPrefix=SYN
+DIOEDA_ProductTitle=ispLEVER
+DIOEDA_ProductType=1.8.00.04.29.14_LS_HDL_BASE_PC_N
+DIOEDA_ProductVersion=1.8.00.04
+DIOEDA_ProgramFolder=Lattice Semiconductor ispLEVER Classic 1.8
+DIOEDA_Root=C:\ispLever\ispcpld
+DIOEDA_Spectrum=C:\isptools\spectrum
+DIOEDA_SpectrumPath=C:\isptools\spectrum
+DIOEDA_Synplify=C:\ispLever\synpbase
+DIOEDA_SynplifyPath=C:\ispLever\synpbase
+DIOEDA_Tutorial=C:\ispLever\ispcpld\tutorial
+DIOPRODUCT=ispLEVER
+PATH=C:\ispLever\ispcpld\bin
diff --git a/Logic/synlog/BUS68030_multi_srs_gen.srr b/Logic/synlog/BUS68030_multi_srs_gen.srr
index 24423c4..bc3d023 100644
--- a/Logic/synlog/BUS68030_multi_srs_gen.srr
+++ b/Logic/synlog/BUS68030_multi_srs_gen.srr
@@ -5,6 +5,6 @@ File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs cha
 At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Sat Oct 10 21:59:43 2015
+# Sun Jan 24 16:20:48 2016
 
 ###########################################################]
diff --git a/Logic/synlog/bus68030_fpga_mapper.srr b/Logic/synlog/bus68030_fpga_mapper.srr
index bac8a2d..2c8da42 100644
--- a/Logic/synlog/bus68030_fpga_mapper.srr
+++ b/Logic/synlog/bus68030_fpga_mapper.srr
@@ -2,8 +2,7 @@ Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014
 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
 Product Version I-2014.03LC 
 @N: MF248 |Running in 64-bit mode.
-@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":513:16:513:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) 
-@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
+@N:"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
 Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
 original code -> new code
    000 -> 00000000
@@ -14,21 +13,20 @@ original code -> new code
    101 -> 00100001
    110 -> 01000001
    111 -> 10000001
-@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":191:4:191:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits 
-@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE
+@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE
 ---------------------------------------
 Resource Usage Report
 
 Simple gate primitives:
-DFF             78 uses
-BI_DIR          11 uses
-IBUF            46 uses
-OBUF            14 uses
+DFF             80 uses
+BI_DIR          10 uses
 BUFTH           4 uses
-AND2            307 uses
-INV             265 uses
-OR2             25 uses
-XOR2            7 uses
+IBUF            46 uses
+OBUF            15 uses
+AND2            297 uses
+INV             261 uses
+OR2             27 uses
+XOR2            8 uses
 
 
 @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
@@ -38,6 +36,6 @@ Mapper successful!
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Sat Oct 10 21:59:43 2015
+# Sun Jan 24 16:20:49 2016
 
 ###########################################################]
diff --git a/Logic/synlog/report/BUS68030_compiler_errors.txt b/Logic/synlog/report/BUS68030_compiler_errors.txt
index b745913..5036d2f 100644
--- a/Logic/synlog/report/BUS68030_compiler_errors.txt
+++ b/Logic/synlog/report/BUS68030_compiler_errors.txt
@@ -1,3 +1,3 @@
-@E: CG119 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":215:39:215:40|Expecting closing )
+@E: CG234 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":86:6:86:6|Duplicate definition of e1
 @E|Parse errors encountered - exiting
 
diff --git a/Logic/synlog/report/BUS68030_compiler_notes.txt b/Logic/synlog/report/BUS68030_compiler_notes.txt
index 9e1730f..9cf0853 100644
--- a/Logic/synlog/report/BUS68030_compiler_notes.txt
+++ b/Logic/synlog/report/BUS68030_compiler_notes.txt
@@ -2,6 +2,8 @@
 @N: CD720 :"C:\ispLever\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
 @N:"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Top entity is set to BUS68030.
 @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral 
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
+@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":65:10:65:11|Using sequential encoding for type sm_e
+@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register SM_AMIGA
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register cpu_est
 
diff --git a/Logic/synlog/report/BUS68030_compiler_runstatus.xml b/Logic/synlog/report/BUS68030_compiler_runstatus.xml
index 4d17f63..9d9d415 100644
--- a/Logic/synlog/report/BUS68030_compiler_runstatus.xml
+++ b/Logic/synlog/report/BUS68030_compiler_runstatus.xml
@@ -14,11 +14,11 @@ The file contains the job information from compiler to be displayed as part of t
   </job_status>
 <job_info> 
 			<info name="Notes">
-  <data>6</data>
+  <data>8</data>
   <report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_notes.txt</data></report_link>
   </info>
 			<info name="Warnings">
-  <data>12</data>
+  <data>11</data>
   <report_link name="more"><data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_compiler_warnings.txt</data></report_link>
   </info>
 			<info name="Errors">
@@ -29,13 +29,13 @@ The file contains the job information from compiler to be displayed as part of t
   <data>-</data>
   </info>
 			<info name="Real Time">
-  <data>0h:00m:01s</data>
+  <data>0h:00m:00s</data>
   </info>
 			<info name="Peak Memory">
   <data>-</data>
   </info>
 			<info name="Date &amp;Time">
-  <data type="timestamp">1444507182</data>
+  <data type="timestamp">1453648847</data>
   </info>
 			</job_info>
 </job_run_status>
\ No newline at end of file
diff --git a/Logic/synlog/report/BUS68030_compiler_warnings.txt b/Logic/synlog/report/BUS68030_compiler_warnings.txt
index 22dc430..ba2c16f 100644
--- a/Logic/synlog/report/BUS68030_compiler_warnings.txt
+++ b/Logic/synlog/report/BUS68030_compiler_warnings.txt
@@ -1,13 +1,12 @@
-@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:17|Signal clk_out_pre is undriven 
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register AMIGA_BUS_ENABLE_INT_4  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:36:124:38|Pruning register CLK_OUT_PRE_50_D_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":156:2:156:3|Pruning register CLK_030_D0_2  
-@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
-@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
-@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
+@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven 
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register DS_030_D0_3  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register AMIGA_BUS_ENABLE_INT_4  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D4_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D3_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D2_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2  
+@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
+@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
+@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
 @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused 
 
diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt b/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt
index 1dd4c4d..9330d5e 100644
--- a/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt
+++ b/Logic/synlog/report/BUS68030_fpga_mapper_notes.txt
@@ -1,3 +1,2 @@
 @N: MF248 |Running in 64-bit mode.
-@N: MO106 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":191:4:191:7|Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits 
 @N: FC100 |Timing Report not generated for this device, please use place and route tools for timing analysis.
diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
index 89c07c6..546b1ed 100644
--- a/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
+++ b/Logic/synlog/report/BUS68030_fpga_mapper_runstatus.xml
@@ -13,13 +13,13 @@ The file contains the job information from mapper to be displayed as part of the
 </job_status>
 <job_info>
 <info name="Notes">
-<data>3</data>
+<data>2</data>
 <report_link name="more">
 <data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_notes.txt</data>
 </report_link>
 </info>
 <info name="Warnings">
-<data>2</data>
+<data>1</data>
 <report_link name="more">
 <data>C:\users\matze\documents\github\68030tk\logic\synlog\report\BUS68030_fpga_mapper_warnings.txt</data>
 </report_link>
@@ -40,7 +40,7 @@ The file contains the job information from mapper to be displayed as part of the
 <data>105MB</data>
 </info>
 <info name="Date &amp; Time">
-<data type="timestamp">1444507183</data>
+<data type="timestamp">1453648849</data>
 </info>
 </job_info>
 </job_run_status>
diff --git a/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt b/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt
index 97571e3..613af04 100644
--- a/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt
+++ b/Logic/synlog/report/BUS68030_fpga_mapper_warnings.txt
@@ -1,2 +1 @@
-@W: MO111 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":513:16:513:18|Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) 
-@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE
+@W: BN132 :"c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE
diff --git a/Logic/syntmp/BUS68030_srr.htm b/Logic/syntmp/BUS68030_srr.htm
index e8b26d2..a515dea 100644
--- a/Logic/syntmp/BUS68030_srr.htm
+++ b/Logic/syntmp/BUS68030_srr.htm
@@ -1,5 +1,5 @@
 <html><body><samp><pre>
-<!@TC:1444507181>
+<!@TC:1453648847>
 #Build: Synplify Pro I-2014.03LC , Build 063R, May 27 2014
 #install: C:\ispLever\synpbase
 #OS: Windows 7 6.2
@@ -8,31 +8,32 @@
 #Implementation: logic
 
 <a name=compilerReport1>$ Start of Compile</a>
-#Sat Oct 10 21:59:41 2015
+#Sun Jan 24 16:20:47 2016
 
 Synopsys VHDL Compiler, version comp201403rcp1, Build 060R, built May 27 2014
-@N: : <!@TM:1444507182> | Running in 64-bit mode 
+@N: : <!@TM:1453648847> | Running in 64-bit mode 
 Copyright (C) 1994-2014 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
 
-@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1444507182> | Setting time resolution to ns
-@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1444507182> | Top entity is set to BUS68030.
+@N:<a href="@N:CD720:@XP_HELP">CD720</a> : <a href="C:\ispLever\synpbase\lib\vhd\std.vhd:123:18:123:22:@N:CD720:@XP_MSG">std.vhd(123)</a><!@TM:1453648847> | Setting time resolution to ns
+@N: : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N::@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1453648847> | Top entity is set to BUS68030.
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
 VHDL syntax check successful!
 File C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd changed - recompiling
-@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1444507182> | Synthesizing work.bus68030.behavioral 
-<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:126:7:126:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(126)</a><!@TM:1444507182> | Signal clk_out_pre is undriven </font>
+@N:<a href="@N:CD630:@XP_HELP">CD630</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:13:7:13:15:@N:CD630:@XP_MSG">68030-68000-bus.vhd(13)</a><!@TM:1453648847> | Synthesizing work.bus68030.behavioral 
+@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:65:10:65:12:@N:CD233:@XP_MSG">68030-68000-bus.vhd(65)</a><!@TM:1453648847> | Using sequential encoding for type sm_e
+@N:<a href="@N:CD233:@XP_HELP">CD233</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:82:14:82:16:@N:CD233:@XP_MSG">68030-68000-bus.vhd(82)</a><!@TM:1453648847> | Using sequential encoding for type sm_68000
+<font color=#A52A2A>@W:<a href="@W:CD638:@XP_HELP">CD638</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:7:124:18:@W:CD638:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1453648847> | Signal clk_out_pre is undriven </font>
 Post processing for work.bus68030.behavioral
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1444507182> | Pruning register AMIGA_BUS_ENABLE_INT_4  </font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1444507182> | Pruning register CLK_000_D4_2  </font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1444507182> | Pruning register CLK_000_D3_2  </font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1444507182> | Pruning register CLK_000_D2_2  </font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:127:35:127:38:@W:CL169:@XP_MSG">68030-68000-bus.vhd(127)</a><!@TM:1444507182> | Pruning register CLK_OUT_INT_2  </font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:124:36:124:39:@W:CL169:@XP_MSG">68030-68000-bus.vhd(124)</a><!@TM:1444507182> | Pruning register CLK_OUT_PRE_50_D_2  </font>
-<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:156:2:156:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(156)</a><!@TM:1444507182> | Pruning register CLK_030_D0_2  </font>
-<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:135:61:135:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(135)</a><!@TM:1444507182> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
-<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:34:134:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1444507182> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
-<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1444507182> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
-@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1444507182> | Trying to extract state machine for register SM_AMIGA
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453648847> | Pruning register DS_030_D0_3  </font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL169:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453648847> | Pruning register AMIGA_BUS_ENABLE_INT_4  </font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:132:34:132:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(132)</a><!@TM:1453648847> | Pruning register CLK_000_D4_2  </font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:131:34:131:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(131)</a><!@TM:1453648847> | Pruning register CLK_000_D3_2  </font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:130:34:130:37:@W:CL169:@XP_MSG">68030-68000-bus.vhd(130)</a><!@TM:1453648847> | Pruning register CLK_000_D2_2  </font>
+<font color=#A52A2A>@W:<a href="@W:CL169:@XP_HELP">CL169</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:155:2:155:4:@W:CL169:@XP_MSG">68030-68000-bus.vhd(155)</a><!@TM:1453648847> | Pruning register CLK_030_D0_2  </font>
+<font color=#A52A2A>@W:<a href="@W:CL265:@XP_HELP">CL265</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:61:134:76:@W:CL265:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1453648847> | Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... </font>
+<font color=#A52A2A>@W:<a href="@W:CL271:@XP_HELP">CL271</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:CL271:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1453648847> | Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... </font>
+<font color=#A52A2A>@W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@W:CL189:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453648847> | Register bit BGACK_030_INT_PRE is always 1, optimizing ...</font>
+@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453648847> | Trying to extract state machine for register SM_AMIGA
 Extracted state machine for register SM_AMIGA
 State machine has 8 reachable states with original encodings of:
    000
@@ -43,24 +44,24 @@ State machine has 8 reachable states with original encodings of:
    101
    110
    111
-@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1444507182> | Trying to extract state machine for register cpu_est
-<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1444507182> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
+@N:<a href="@N:CL201:@XP_HELP">CL201</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N:CL201:@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453648847> | Trying to extract state machine for register cpu_est
+<font color=#A52A2A>@W:<a href="@W:CL246:@XP_HELP">CL246</a> : <a href="C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:23:1:23:2:@W:CL246:@XP_MSG">68030-68000-bus.vhd(23)</a><!@TM:1453648847> | Input port bits 15 to 2 of a(31 downto 2) are unused </font>
 @END
 
-At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
+At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Sat Oct 10 21:59:42 2015
+# Sun Jan 24 16:20:47 2016
 
 ###########################################################]
 Synopsys Netlist Linker, version comp201403rcp1, Build 060R, built May 27 2014
-@N: : <!@TM:1444507183> | Running in 64-bit mode 
+@N: : <!@TM:1453648848> | Running in 64-bit mode 
 File C:\users\matze\documents\github\68030tk\logic\synwork\BUS68030_comp.srs changed - recompiling
 
 At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Sat Oct 10 21:59:43 2015
+# Sun Jan 24 16:20:48 2016
 
 ###########################################################]
 Map & Optimize Report
@@ -68,9 +69,8 @@ Map & Optimize Report
 <a name=mapperReport2>Synopsys CPLD Technology Mapper, Version maplat, Build 923R, Built May  6 2014</a>
 Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use or distribution of the software is strictly prohibited.
 Product Version I-2014.03LC 
-@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1444507183> | Running in 64-bit mode. 
-<font color=#A52A2A>@W:<a href="@W:MO111:@XP_HELP">MO111</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:513:16:513:19:@W:MO111:@XP_MSG">68030-68000-bus.vhd(513)</a><!@TM:1444507183> | Tristate driver CLK_DIV_OUT_1 on net CLK_DIV_OUT_1 has its enable tied to GND (module BUS68030) </font>
-@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:139:37:139:40:@N::@XP_MSG">68030-68000-bus.vhd(139)</a><!@TM:1444507183> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
+@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1453648849> | Running in 64-bit mode. 
+@N: : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:138:37:138:40:@N::@XP_MSG">68030-68000-bus.vhd(138)</a><!@TM:1453648849> | Found counter in view:work.BUS68030(behavioral) inst RST_DLY[2:0]
 Encoding state machine SM_AMIGA[0:7] (view:work.BUS68030(behavioral))
 original code -> new code
    000 -> 00000000
@@ -81,31 +81,30 @@ original code -> new code
    101 -> 00100001
    110 -> 01000001
    111 -> 10000001
-@N:<a href="@N:MO106:@XP_HELP">MO106</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:191:4:191:8:@N:MO106:@XP_MSG">68030-68000-bus.vhd(191)</a><!@TM:1444507183> | Found ROM, 'pos_clk\.cpu_est_11[3:0]', 16 words by 4 bits 
-<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:134:34:134:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(134)</a><!@TM:1444507183> | Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE</font>
+<font color=#A52A2A>@W:<a href="@W:BN132:@XP_HELP">BN132</a> : <a href="c:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd:133:34:133:37:@W:BN132:@XP_MSG">68030-68000-bus.vhd(133)</a><!@TM:1453648849> | Removing instance CLK_000_P_SYNC[10],  because it is equivalent to instance CLK_000_PE</font>
 ---------------------------------------
 <a name=resourceUsage3>Resource Usage Report</a>
 
 Simple gate primitives:
-DFF             78 uses
-BI_DIR          11 uses
-IBUF            46 uses
-OBUF            14 uses
+DFF             80 uses
+BI_DIR          10 uses
 BUFTH           4 uses
-AND2            307 uses
-INV             265 uses
-OR2             25 uses
-XOR2            7 uses
+IBUF            46 uses
+OBUF            15 uses
+AND2            297 uses
+INV             261 uses
+OR2             27 uses
+XOR2            8 uses
 
 
-@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1444507183> | Timing Report not generated for this device, please use place and route tools for timing analysis. 
+@N:<a href="@N:FC100:@XP_HELP">FC100</a> : <!@TM:1453648849> | Timing Report not generated for this device, please use place and route tools for timing analysis. 
 I-2014.03LC 
 Mapper successful!
 
 At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 39MB peak: 105MB)
 
 Process took 0h:00m:01s realtime, 0h:00m:01s cputime
-# Sat Oct 10 21:59:43 2015
+# Sun Jan 24 16:20:49 2016
 
 ###########################################################]
 
diff --git a/Logic/syntmp/BUS68030_toc.htm b/Logic/syntmp/BUS68030_toc.htm
index 9f694e6..e6a821f 100644
--- a/Logic/syntmp/BUS68030_toc.htm
+++ b/Logic/syntmp/BUS68030_toc.htm
@@ -16,7 +16,7 @@
 <li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#mapperReport2" target="srrFrame" title="">Mapper Report</a>  
 <ul rel="open" >
 <li><a href="file:///C:\users\matze\documents\github\68030tk\logic\syntmp\BUS68030_srr.htm#resourceUsage3" target="srrFrame" title="">Resource Utilization</a>  </li></ul></li></ul></li>
-<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (21:59 10-Oct)</a>  
+<li><a href="file:///C:\users\matze\documents\github\68030tk\logic\stdout.log" target="srrFrame" title="">Session Log (16:20 24-Jan)</a>  
 <ul  ></ul></li>         </ul>
         </li>
    </ul>
diff --git a/Logic/syntmp/run_option.xml b/Logic/syntmp/run_option.xml
index baad302..bfdac24 100644
--- a/Logic/syntmp/run_option.xml
+++ b/Logic/syntmp/run_option.xml
@@ -3,7 +3,7 @@
   Synopsys, Inc.
   Version I-2014.03LC 
   Project file C:\users\matze\documents\github\68030tk\logic\syntmp\run_option.xml
-  Written on Sat Oct 10 21:59:41 2015
+  Written on Sun Jan 24 16:20:47 2016
 
 
 --> 
diff --git a/Logic/syntmp/statusReport.html b/Logic/syntmp/statusReport.html
index 0c74ffb..fe8835b 100644
--- a/Logic/syntmp/statusReport.html
+++ b/Logic/syntmp/statusReport.html
@@ -32,29 +32,29 @@
          </tr>
   <tr>
   <td class="optionTitle">Compile Input</td><td>Complete</td>
- <td>6</td>
- <td>12</td>
+ <td>8</td>
+ <td>11</td>
 <td>0</td>
 <td>-</td>
-<td>0m:01s</td>
+<td>0m:00s</td>
 <td>-</td>
-<td><font size="-1">10.10.2015</font><br/><font size="-2">21:59:42</font></td>
+<td><font size="-1">24.01.2016</font><br/><font size="-2">16:20:47</font></td>
 </tr> 
 
  <tr>
   <td class="optionTitle">Map & Optimize</td><td>Complete</td>
- <td>3</td>
  <td>2</td>
+ <td>1</td>
 <td>0</td>
 <td>0m:00s</td>
 <td>0m:00s</td>
 <td>105MB</td>
-<td><font size="-1">10.10.2015</font><br/><font size="-2">21:59:43</font></td>
+<td><font size="-1">24.01.2016</font><br/><font size="-2">16:20:49</font></td>
 </tr> 
 
 <tr>
   <td class="optionTitle">Multi-srs Generator</td>
-  <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">10.10.2015</font><br/><font size="-2">21:59:43</font></td> 		</tbody>
+  <td>Complete</td><td class="empty"></td><td class="empty"></td><td class="empty"></td><td>0m:00s</td><td class="empty"></td><td class="empty"></td><td><font size="-1">24.01.2016</font><br/><font size="-2">16:20:48</font></td> 		</tbody>
      </table>
  </td></tr></table></body> 
  </html>
\ No newline at end of file
diff --git a/Logic/synwork/BUS68030_comp.fdep b/Logic/synwork/BUS68030_comp.fdep
index babd22e..e80c793 100644
--- a/Logic/synwork/BUS68030_comp.fdep
+++ b/Logic/synwork/BUS68030_comp.fdep
@@ -1,15 +1,15 @@
 #defaultlanguage:vhdl
 #OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
-#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401227704
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310460974
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401227322
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401227322
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401227322
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401227322
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401227568
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401227322
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401227322
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1444507148
+#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401224104
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310457374
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401223722
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401223722
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401223722
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1453648836
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_comp.fdeporig b/Logic/synwork/BUS68030_comp.fdeporig
index 4b00b4a..ac054ff 100644
--- a/Logic/synwork/BUS68030_comp.fdeporig
+++ b/Logic/synwork/BUS68030_comp.fdeporig
@@ -1,15 +1,15 @@
 #defaultlanguage:vhdl
 #OPTIONS:"|-top|BUS68030|-prodtype|synplify_pro|-nostructver|-dfltencoding|sequential|-encrypt|-pro|-lite|-ui|-fid2|-ram|-sharing|on|-ll|2000|-autosm|-ignore_undefined_lib|-lib|work"
-#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401227704
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310460974
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401227322
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401227322
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401227322
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401227322
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401227568
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401227322
-#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401227322
-#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1444507148
+#CUR:"C:\\ispLever\\synpbase\\bin64\\c_vhdl.exe":1401224104
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\location.map":1310457374
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std.vhd":1401223722
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\snps_haps_pkg.vhd":1401223722
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\std1164.vhd":1401223722
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\numeric.vhd":1401223722
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\umr_capim.vhd":1401223968
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\arith.vhd":1401223722
+#CUR:"C:\\ispLever\\synpbase\\lib\\vhd\\unsigned.vhd":1401223722
+#CUR:"C:\\users\\matze\\documents\\github\\68030tk\\logic\\68030-68000-bus.vhd":1453648836
 0 "C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd" vhdl
 
 # Dependency Lists (Uses list)
diff --git a/Logic/synwork/BUS68030_comp.srs b/Logic/synwork/BUS68030_comp.srs
index 2ab3e9d..b883ba4 100644
Binary files a/Logic/synwork/BUS68030_comp.srs and b/Logic/synwork/BUS68030_comp.srs differ
diff --git a/Logic/synwork/BUS68030_comp.tlg b/Logic/synwork/BUS68030_comp.tlg
index 56d1cd4..480482a 100644
--- a/Logic/synwork/BUS68030_comp.tlg
+++ b/Logic/synwork/BUS68030_comp.tlg
@@ -1,17 +1,18 @@
 @N: CD630 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":13:7:13:14|Synthesizing work.bus68030.behavioral 
-@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":126:7:126:17|Signal clk_out_pre is undriven 
+@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":65:10:65:11|Using sequential encoding for type sm_e
+@N: CD233 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":82:14:82:15|Using sequential encoding for type sm_68000
+@W: CD638 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:7:124:17|Signal clk_out_pre is undriven 
 Post processing for work.bus68030.behavioral
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Pruning register AMIGA_BUS_ENABLE_INT_4  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning register CLK_000_D4_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D3_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D2_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":127:35:127:37|Pruning register CLK_OUT_INT_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":124:36:124:38|Pruning register CLK_OUT_PRE_50_D_2  
-@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":156:2:156:3|Pruning register CLK_030_D0_2  
-@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":135:61:135:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
-@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:34:134:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
-@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register SM_AMIGA
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register DS_030_D0_3  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Pruning register AMIGA_BUS_ENABLE_INT_4  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":132:34:132:36|Pruning register CLK_000_D4_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":131:34:131:36|Pruning register CLK_000_D3_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":130:34:130:36|Pruning register CLK_000_D2_2  
+@W: CL169 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":155:2:155:3|Pruning register CLK_030_D0_2  
+@W: CL265 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":134:61:134:75|Pruning bit 12 of CLK_000_N_SYNC_3(12 downto 0) -- not in use ... 
+@W: CL271 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":133:34:133:36|Pruning bits 12 to 11 of CLK_000_P_SYNC_3(12 downto 0) -- not in use ... 
+@W: CL189 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Register bit BGACK_030_INT_PRE is always 1, optimizing ...
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register SM_AMIGA
 Extracted state machine for register SM_AMIGA
 State machine has 8 reachable states with original encodings of:
    000
@@ -22,5 +23,5 @@ State machine has 8 reachable states with original encodings of:
    101
    110
    111
-@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":139:37:139:39|Trying to extract state machine for register cpu_est
+@N: CL201 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":138:37:138:39|Trying to extract state machine for register cpu_est
 @W: CL246 :"C:\users\matze\documents\github\68030tk\logic\68030-68000-bus.vhd":23:1:23:1|Input port bits 15 to 2 of a(31 downto 2) are unused 
diff --git a/Logic/synwork/BUS68030_mult.srs b/Logic/synwork/BUS68030_mult.srs
index 22755f3..f26060f 100644
Binary files a/Logic/synwork/BUS68030_mult.srs and b/Logic/synwork/BUS68030_mult.srs differ
diff --git a/Logic/synwork/BUS68030_mult_srs/skeleton.srs b/Logic/synwork/BUS68030_mult_srs/skeleton.srs
index 64f82fa..a04b722 100644
Binary files a/Logic/synwork/BUS68030_mult_srs/skeleton.srs and b/Logic/synwork/BUS68030_mult_srs/skeleton.srs differ
diff --git a/Logic/synwork/BUS68030_s.srs b/Logic/synwork/BUS68030_s.srs
index 2ab3e9d..b883ba4 100644
Binary files a/Logic/synwork/BUS68030_s.srs and b/Logic/synwork/BUS68030_s.srs differ